1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2018 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma, disassemble_info *);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma get64 (void);
58 static bfd_signed_vma get32 (void);
59 static bfd_signed_vma get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VZERO_Fixup (int, int);
99 static void VCMP_Fixup (int, int);
100 static void VPCMP_Fixup (int, int);
101 static void VPCOM_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void OP_Mwaitx (int, int);
106 static void NOP_Fixup1 (int, int);
107 static void NOP_Fixup2 (int, int);
108 static void OP_3DNowSuffix (int, int);
109 static void CMP_Fixup (int, int);
110 static void BadOp (void);
111 static void REP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void NOTRACK_Fixup (int, int);
114 static void HLE_Fixup1 (int, int);
115 static void HLE_Fixup2 (int, int);
116 static void HLE_Fixup3 (int, int);
117 static void CMPXCHG8B_Fixup (int, int);
118 static void XMM_Fixup (int, int);
119 static void CRC32_Fixup (int, int);
120 static void FXSAVE_Fixup (int, int);
121 static void PCMPESTR_Fixup (int, int);
122 static void OP_LWPCB_E (int, int);
123 static void OP_LWP_E (int, int);
124 static void OP_Vex_2src_1 (int, int);
125 static void OP_Vex_2src_2 (int, int);
127 static void MOVBE_Fixup (int, int);
129 static void OP_Mask (int, int);
132 /* Points to first byte not fetched. */
133 bfd_byte *max_fetched;
134 bfd_byte the_buffer[MAX_MNEM_SIZE];
137 OPCODES_SIGJMP_BUF bailout;
147 enum address_mode address_mode;
149 /* Flags for the prefixes for the current instruction. See below. */
152 /* REX prefix the current instruction. See below. */
154 /* Bits of REX we've already used. */
156 /* REX bits in original REX prefix ignored. */
157 static int rex_ignored;
158 /* Mark parts used in the REX prefix. When we are testing for
159 empty prefix (for 8bit register REX extension), just mask it
160 out. Otherwise test for REX bit is excuse for existence of REX
161 only in case value is nonzero. */
162 #define USED_REX(value) \
167 rex_used |= (value) | REX_OPCODE; \
170 rex_used |= REX_OPCODE; \
173 /* Flags for prefixes which we somehow handled when printing the
174 current instruction. */
175 static int used_prefixes;
177 /* Flags stored in PREFIXES. */
178 #define PREFIX_REPZ 1
179 #define PREFIX_REPNZ 2
180 #define PREFIX_LOCK 4
182 #define PREFIX_SS 0x10
183 #define PREFIX_DS 0x20
184 #define PREFIX_ES 0x40
185 #define PREFIX_FS 0x80
186 #define PREFIX_GS 0x100
187 #define PREFIX_DATA 0x200
188 #define PREFIX_ADDR 0x400
189 #define PREFIX_FWAIT 0x800
191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
192 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
194 #define FETCH_DATA(info, addr) \
195 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
196 ? 1 : fetch_data ((info), (addr)))
199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
202 struct dis_private *priv = (struct dis_private *) info->private_data;
203 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
205 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
206 status = (*info->read_memory_func) (start,
208 addr - priv->max_fetched,
214 /* If we did manage to read at least one byte, then
215 print_insn_i386 will do something sensible. Otherwise, print
216 an error. We do that here because this is where we know
218 if (priv->max_fetched == priv->the_buffer)
219 (*info->memory_error_func) (status, start, info);
220 OPCODES_SIGLONGJMP (priv->bailout, 1);
223 priv->max_fetched = addr;
227 /* Possible values for prefix requirement. */
228 #define PREFIX_IGNORED_SHIFT 16
229 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
233 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
235 /* Opcode prefixes. */
236 #define PREFIX_OPCODE (PREFIX_REPZ \
240 /* Prefixes ignored. */
241 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
242 | PREFIX_IGNORED_REPNZ \
243 | PREFIX_IGNORED_DATA)
245 #define XX { NULL, 0 }
246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
248 #define Eb { OP_E, b_mode }
249 #define Ebnd { OP_E, bnd_mode }
250 #define EbS { OP_E, b_swap_mode }
251 #define EbndS { OP_E, bnd_swap_mode }
252 #define Ev { OP_E, v_mode }
253 #define Ev_bnd { OP_E, v_bnd_mode }
254 #define EvS { OP_E, v_swap_mode }
255 #define Ed { OP_E, d_mode }
256 #define Edq { OP_E, dq_mode }
257 #define Edqw { OP_E, dqw_mode }
258 #define Edqb { OP_E, dqb_mode }
259 #define Edb { OP_E, db_mode }
260 #define Edw { OP_E, dw_mode }
261 #define Edqd { OP_E, dqd_mode }
262 #define Eq { OP_E, q_mode }
263 #define indirEv { OP_indirE, indir_v_mode }
264 #define indirEp { OP_indirE, f_mode }
265 #define stackEv { OP_E, stack_v_mode }
266 #define Em { OP_E, m_mode }
267 #define Ew { OP_E, w_mode }
268 #define M { OP_M, 0 } /* lea, lgdt, etc. */
269 #define Ma { OP_M, a_mode }
270 #define Mb { OP_M, b_mode }
271 #define Md { OP_M, d_mode }
272 #define Mo { OP_M, o_mode }
273 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
274 #define Mq { OP_M, q_mode }
275 #define Mx { OP_M, x_mode }
276 #define Mxmm { OP_M, xmm_mode }
277 #define Gb { OP_G, b_mode }
278 #define Gbnd { OP_G, bnd_mode }
279 #define Gv { OP_G, v_mode }
280 #define Gd { OP_G, d_mode }
281 #define Gdq { OP_G, dq_mode }
282 #define Gm { OP_G, m_mode }
283 #define Gw { OP_G, w_mode }
284 #define Rd { OP_R, d_mode }
285 #define Rdq { OP_R, dq_mode }
286 #define Rm { OP_R, m_mode }
287 #define Ib { OP_I, b_mode }
288 #define sIb { OP_sI, b_mode } /* sign extened byte */
289 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
290 #define Iv { OP_I, v_mode }
291 #define sIv { OP_sI, v_mode }
292 #define Iq { OP_I, q_mode }
293 #define Iv64 { OP_I64, v_mode }
294 #define Iw { OP_I, w_mode }
295 #define I1 { OP_I, const_1_mode }
296 #define Jb { OP_J, b_mode }
297 #define Jv { OP_J, v_mode }
298 #define Cm { OP_C, m_mode }
299 #define Dm { OP_D, m_mode }
300 #define Td { OP_T, d_mode }
301 #define Skip_MODRM { OP_Skip_MODRM, 0 }
303 #define RMeAX { OP_REG, eAX_reg }
304 #define RMeBX { OP_REG, eBX_reg }
305 #define RMeCX { OP_REG, eCX_reg }
306 #define RMeDX { OP_REG, eDX_reg }
307 #define RMeSP { OP_REG, eSP_reg }
308 #define RMeBP { OP_REG, eBP_reg }
309 #define RMeSI { OP_REG, eSI_reg }
310 #define RMeDI { OP_REG, eDI_reg }
311 #define RMrAX { OP_REG, rAX_reg }
312 #define RMrBX { OP_REG, rBX_reg }
313 #define RMrCX { OP_REG, rCX_reg }
314 #define RMrDX { OP_REG, rDX_reg }
315 #define RMrSP { OP_REG, rSP_reg }
316 #define RMrBP { OP_REG, rBP_reg }
317 #define RMrSI { OP_REG, rSI_reg }
318 #define RMrDI { OP_REG, rDI_reg }
319 #define RMAL { OP_REG, al_reg }
320 #define RMCL { OP_REG, cl_reg }
321 #define RMDL { OP_REG, dl_reg }
322 #define RMBL { OP_REG, bl_reg }
323 #define RMAH { OP_REG, ah_reg }
324 #define RMCH { OP_REG, ch_reg }
325 #define RMDH { OP_REG, dh_reg }
326 #define RMBH { OP_REG, bh_reg }
327 #define RMAX { OP_REG, ax_reg }
328 #define RMDX { OP_REG, dx_reg }
330 #define eAX { OP_IMREG, eAX_reg }
331 #define eBX { OP_IMREG, eBX_reg }
332 #define eCX { OP_IMREG, eCX_reg }
333 #define eDX { OP_IMREG, eDX_reg }
334 #define eSP { OP_IMREG, eSP_reg }
335 #define eBP { OP_IMREG, eBP_reg }
336 #define eSI { OP_IMREG, eSI_reg }
337 #define eDI { OP_IMREG, eDI_reg }
338 #define AL { OP_IMREG, al_reg }
339 #define CL { OP_IMREG, cl_reg }
340 #define DL { OP_IMREG, dl_reg }
341 #define BL { OP_IMREG, bl_reg }
342 #define AH { OP_IMREG, ah_reg }
343 #define CH { OP_IMREG, ch_reg }
344 #define DH { OP_IMREG, dh_reg }
345 #define BH { OP_IMREG, bh_reg }
346 #define AX { OP_IMREG, ax_reg }
347 #define DX { OP_IMREG, dx_reg }
348 #define zAX { OP_IMREG, z_mode_ax_reg }
349 #define indirDX { OP_IMREG, indir_dx_reg }
351 #define Sw { OP_SEG, w_mode }
352 #define Sv { OP_SEG, v_mode }
353 #define Ap { OP_DIR, 0 }
354 #define Ob { OP_OFF64, b_mode }
355 #define Ov { OP_OFF64, v_mode }
356 #define Xb { OP_DSreg, eSI_reg }
357 #define Xv { OP_DSreg, eSI_reg }
358 #define Xz { OP_DSreg, eSI_reg }
359 #define Yb { OP_ESreg, eDI_reg }
360 #define Yv { OP_ESreg, eDI_reg }
361 #define DSBX { OP_DSreg, eBX_reg }
363 #define es { OP_REG, es_reg }
364 #define ss { OP_REG, ss_reg }
365 #define cs { OP_REG, cs_reg }
366 #define ds { OP_REG, ds_reg }
367 #define fs { OP_REG, fs_reg }
368 #define gs { OP_REG, gs_reg }
370 #define MX { OP_MMX, 0 }
371 #define XM { OP_XMM, 0 }
372 #define XMScalar { OP_XMM, scalar_mode }
373 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
374 #define XMM { OP_XMM, xmm_mode }
375 #define XMxmmq { OP_XMM, xmmq_mode }
376 #define EM { OP_EM, v_mode }
377 #define EMS { OP_EM, v_swap_mode }
378 #define EMd { OP_EM, d_mode }
379 #define EMx { OP_EM, x_mode }
380 #define EXbScalar { OP_EX, b_scalar_mode }
381 #define EXw { OP_EX, w_mode }
382 #define EXwScalar { OP_EX, w_scalar_mode }
383 #define EXd { OP_EX, d_mode }
384 #define EXdScalar { OP_EX, d_scalar_mode }
385 #define EXdS { OP_EX, d_swap_mode }
386 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
387 #define EXq { OP_EX, q_mode }
388 #define EXqScalar { OP_EX, q_scalar_mode }
389 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
390 #define EXqS { OP_EX, q_swap_mode }
391 #define EXx { OP_EX, x_mode }
392 #define EXxS { OP_EX, x_swap_mode }
393 #define EXxmm { OP_EX, xmm_mode }
394 #define EXymm { OP_EX, ymm_mode }
395 #define EXxmmq { OP_EX, xmmq_mode }
396 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
397 #define EXxmm_mb { OP_EX, xmm_mb_mode }
398 #define EXxmm_mw { OP_EX, xmm_mw_mode }
399 #define EXxmm_md { OP_EX, xmm_md_mode }
400 #define EXxmm_mq { OP_EX, xmm_mq_mode }
401 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
402 #define EXxmmdw { OP_EX, xmmdw_mode }
403 #define EXxmmqd { OP_EX, xmmqd_mode }
404 #define EXymmq { OP_EX, ymmq_mode }
405 #define EXVexWdq { OP_EX, vex_w_dq_mode }
406 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
407 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
408 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
409 #define MS { OP_MS, v_mode }
410 #define XS { OP_XS, v_mode }
411 #define EMCq { OP_EMC, q_mode }
412 #define MXC { OP_MXC, 0 }
413 #define OPSUF { OP_3DNowSuffix, 0 }
414 #define CMP { CMP_Fixup, 0 }
415 #define XMM0 { XMM_Fixup, 0 }
416 #define FXSAVE { FXSAVE_Fixup, 0 }
417 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
418 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
420 #define Vex { OP_VEX, vex_mode }
421 #define VexScalar { OP_VEX, vex_scalar_mode }
422 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
423 #define Vex128 { OP_VEX, vex128_mode }
424 #define Vex256 { OP_VEX, vex256_mode }
425 #define VexGdq { OP_VEX, dq_mode }
426 #define EXdVex { OP_EX_Vex, d_mode }
427 #define EXdVexS { OP_EX_Vex, d_swap_mode }
428 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
429 #define EXqVex { OP_EX_Vex, q_mode }
430 #define EXqVexS { OP_EX_Vex, q_swap_mode }
431 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
432 #define EXVexW { OP_EX_VexW, x_mode }
433 #define EXdVexW { OP_EX_VexW, d_mode }
434 #define EXqVexW { OP_EX_VexW, q_mode }
435 #define EXVexImmW { OP_EX_VexImmW, x_mode }
436 #define XMVex { OP_XMM_Vex, 0 }
437 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
438 #define XMVexW { OP_XMM_VexW, 0 }
439 #define XMVexI4 { OP_REG_VexI4, x_mode }
440 #define PCLMUL { PCLMUL_Fixup, 0 }
441 #define VZERO { VZERO_Fixup, 0 }
442 #define VCMP { VCMP_Fixup, 0 }
443 #define VPCMP { VPCMP_Fixup, 0 }
444 #define VPCOM { VPCOM_Fixup, 0 }
446 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
447 #define EXxEVexS { OP_Rounding, evex_sae_mode }
449 #define XMask { OP_Mask, mask_mode }
450 #define MaskG { OP_G, mask_mode }
451 #define MaskE { OP_E, mask_mode }
452 #define MaskBDE { OP_E, mask_bd_mode }
453 #define MaskR { OP_R, mask_mode }
454 #define MaskVex { OP_VEX, mask_mode }
456 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
457 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
458 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
459 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
461 /* Used handle "rep" prefix for string instructions. */
462 #define Xbr { REP_Fixup, eSI_reg }
463 #define Xvr { REP_Fixup, eSI_reg }
464 #define Ybr { REP_Fixup, eDI_reg }
465 #define Yvr { REP_Fixup, eDI_reg }
466 #define Yzr { REP_Fixup, eDI_reg }
467 #define indirDXr { REP_Fixup, indir_dx_reg }
468 #define ALr { REP_Fixup, al_reg }
469 #define eAXr { REP_Fixup, eAX_reg }
471 /* Used handle HLE prefix for lockable instructions. */
472 #define Ebh1 { HLE_Fixup1, b_mode }
473 #define Evh1 { HLE_Fixup1, v_mode }
474 #define Ebh2 { HLE_Fixup2, b_mode }
475 #define Evh2 { HLE_Fixup2, v_mode }
476 #define Ebh3 { HLE_Fixup3, b_mode }
477 #define Evh3 { HLE_Fixup3, v_mode }
479 #define BND { BND_Fixup, 0 }
480 #define NOTRACK { NOTRACK_Fixup, 0 }
482 #define cond_jump_flag { NULL, cond_jump_mode }
483 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
485 /* bits in sizeflag */
486 #define SUFFIX_ALWAYS 4
494 /* byte operand with operand swapped */
496 /* byte operand, sign extend like 'T' suffix */
498 /* operand size depends on prefixes */
500 /* operand size depends on prefixes with operand swapped */
504 /* double word operand */
506 /* double word operand with operand swapped */
508 /* quad word operand */
510 /* quad word operand with operand swapped */
512 /* ten-byte operand */
514 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
515 broadcast enabled. */
517 /* Similar to x_mode, but with different EVEX mem shifts. */
519 /* Similar to x_mode, but with disabled broadcast. */
521 /* Similar to x_mode, but with operands swapped and disabled broadcast
524 /* 16-byte XMM operand */
526 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
527 memory operand (depending on vector length). Broadcast isn't
530 /* Same as xmmq_mode, but broadcast is allowed. */
531 evex_half_bcst_xmmq_mode,
532 /* XMM register or byte memory operand */
534 /* XMM register or word memory operand */
536 /* XMM register or double word memory operand */
538 /* XMM register or quad word memory operand */
540 /* XMM register or double/quad word memory operand, depending on
543 /* 16-byte XMM, word, double word or quad word operand. */
545 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
547 /* 32-byte YMM operand */
549 /* quad word, ymmword or zmmword memory operand. */
551 /* 32-byte YMM or 16-byte word operand */
553 /* d_mode in 32bit, q_mode in 64bit mode. */
555 /* pair of v_mode operands */
560 /* operand size depends on REX prefixes. */
562 /* registers like dq_mode, memory like w_mode. */
566 /* bounds operand with operand swapped */
568 /* 4- or 6-byte pointer operand */
571 /* v_mode for indirect branch opcodes. */
573 /* v_mode for stack-related opcodes. */
575 /* non-quad operand size depends on prefixes */
577 /* 16-byte operand */
579 /* registers like dq_mode, memory like b_mode. */
581 /* registers like d_mode, memory like b_mode. */
583 /* registers like d_mode, memory like w_mode. */
585 /* registers like dq_mode, memory like d_mode. */
587 /* normal vex mode */
589 /* 128bit vex mode */
591 /* 256bit vex mode */
593 /* operand size depends on the VEX.W bit. */
596 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
597 vex_vsib_d_w_dq_mode,
598 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
600 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
601 vex_vsib_q_w_dq_mode,
602 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
605 /* scalar, ignore vector length. */
607 /* like b_mode, ignore vector length. */
609 /* like w_mode, ignore vector length. */
611 /* like d_mode, ignore vector length. */
613 /* like d_swap_mode, ignore vector length. */
615 /* like q_mode, ignore vector length. */
617 /* like q_swap_mode, ignore vector length. */
619 /* like vex_mode, ignore vector length. */
621 /* like vex_w_dq_mode, ignore vector length. */
622 vex_scalar_w_dq_mode,
624 /* Static rounding. */
626 /* Supress all exceptions. */
629 /* Mask register operand. */
631 /* Mask register operand. */
698 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
700 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
701 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
702 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
703 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
704 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
705 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
706 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
707 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
708 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
709 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
710 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
711 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
712 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
713 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
714 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
836 MOD_VEX_0F12_PREFIX_0,
838 MOD_VEX_0F16_PREFIX_0,
841 MOD_VEX_W_0_0F41_P_0_LEN_1,
842 MOD_VEX_W_1_0F41_P_0_LEN_1,
843 MOD_VEX_W_0_0F41_P_2_LEN_1,
844 MOD_VEX_W_1_0F41_P_2_LEN_1,
845 MOD_VEX_W_0_0F42_P_0_LEN_1,
846 MOD_VEX_W_1_0F42_P_0_LEN_1,
847 MOD_VEX_W_0_0F42_P_2_LEN_1,
848 MOD_VEX_W_1_0F42_P_2_LEN_1,
849 MOD_VEX_W_0_0F44_P_0_LEN_1,
850 MOD_VEX_W_1_0F44_P_0_LEN_1,
851 MOD_VEX_W_0_0F44_P_2_LEN_1,
852 MOD_VEX_W_1_0F44_P_2_LEN_1,
853 MOD_VEX_W_0_0F45_P_0_LEN_1,
854 MOD_VEX_W_1_0F45_P_0_LEN_1,
855 MOD_VEX_W_0_0F45_P_2_LEN_1,
856 MOD_VEX_W_1_0F45_P_2_LEN_1,
857 MOD_VEX_W_0_0F46_P_0_LEN_1,
858 MOD_VEX_W_1_0F46_P_0_LEN_1,
859 MOD_VEX_W_0_0F46_P_2_LEN_1,
860 MOD_VEX_W_1_0F46_P_2_LEN_1,
861 MOD_VEX_W_0_0F47_P_0_LEN_1,
862 MOD_VEX_W_1_0F47_P_0_LEN_1,
863 MOD_VEX_W_0_0F47_P_2_LEN_1,
864 MOD_VEX_W_1_0F47_P_2_LEN_1,
865 MOD_VEX_W_0_0F4A_P_0_LEN_1,
866 MOD_VEX_W_1_0F4A_P_0_LEN_1,
867 MOD_VEX_W_0_0F4A_P_2_LEN_1,
868 MOD_VEX_W_1_0F4A_P_2_LEN_1,
869 MOD_VEX_W_0_0F4B_P_0_LEN_1,
870 MOD_VEX_W_1_0F4B_P_0_LEN_1,
871 MOD_VEX_W_0_0F4B_P_2_LEN_1,
883 MOD_VEX_W_0_0F91_P_0_LEN_0,
884 MOD_VEX_W_1_0F91_P_0_LEN_0,
885 MOD_VEX_W_0_0F91_P_2_LEN_0,
886 MOD_VEX_W_1_0F91_P_2_LEN_0,
887 MOD_VEX_W_0_0F92_P_0_LEN_0,
888 MOD_VEX_W_0_0F92_P_2_LEN_0,
889 MOD_VEX_W_0_0F92_P_3_LEN_0,
890 MOD_VEX_W_1_0F92_P_3_LEN_0,
891 MOD_VEX_W_0_0F93_P_0_LEN_0,
892 MOD_VEX_W_0_0F93_P_2_LEN_0,
893 MOD_VEX_W_0_0F93_P_3_LEN_0,
894 MOD_VEX_W_1_0F93_P_3_LEN_0,
895 MOD_VEX_W_0_0F98_P_0_LEN_0,
896 MOD_VEX_W_1_0F98_P_0_LEN_0,
897 MOD_VEX_W_0_0F98_P_2_LEN_0,
898 MOD_VEX_W_1_0F98_P_2_LEN_0,
899 MOD_VEX_W_0_0F99_P_0_LEN_0,
900 MOD_VEX_W_1_0F99_P_0_LEN_0,
901 MOD_VEX_W_0_0F99_P_2_LEN_0,
902 MOD_VEX_W_1_0F99_P_2_LEN_0,
905 MOD_VEX_0FD7_PREFIX_2,
906 MOD_VEX_0FE7_PREFIX_2,
907 MOD_VEX_0FF0_PREFIX_3,
908 MOD_VEX_0F381A_PREFIX_2,
909 MOD_VEX_0F382A_PREFIX_2,
910 MOD_VEX_0F382C_PREFIX_2,
911 MOD_VEX_0F382D_PREFIX_2,
912 MOD_VEX_0F382E_PREFIX_2,
913 MOD_VEX_0F382F_PREFIX_2,
914 MOD_VEX_0F385A_PREFIX_2,
915 MOD_VEX_0F388C_PREFIX_2,
916 MOD_VEX_0F388E_PREFIX_2,
917 MOD_VEX_W_0_0F3A30_P_2_LEN_0,
918 MOD_VEX_W_1_0F3A30_P_2_LEN_0,
919 MOD_VEX_W_0_0F3A31_P_2_LEN_0,
920 MOD_VEX_W_1_0F3A31_P_2_LEN_0,
921 MOD_VEX_W_0_0F3A32_P_2_LEN_0,
922 MOD_VEX_W_1_0F3A32_P_2_LEN_0,
923 MOD_VEX_W_0_0F3A33_P_2_LEN_0,
924 MOD_VEX_W_1_0F3A33_P_2_LEN_0,
926 MOD_EVEX_0F10_PREFIX_1,
927 MOD_EVEX_0F10_PREFIX_3,
928 MOD_EVEX_0F11_PREFIX_1,
929 MOD_EVEX_0F11_PREFIX_3,
930 MOD_EVEX_0F12_PREFIX_0,
931 MOD_EVEX_0F16_PREFIX_0,
932 MOD_EVEX_0F38C6_REG_1,
933 MOD_EVEX_0F38C6_REG_2,
934 MOD_EVEX_0F38C6_REG_5,
935 MOD_EVEX_0F38C6_REG_6,
936 MOD_EVEX_0F38C7_REG_1,
937 MOD_EVEX_0F38C7_REG_2,
938 MOD_EVEX_0F38C7_REG_5,
939 MOD_EVEX_0F38C7_REG_6
960 PREFIX_MOD_0_0F01_REG_5,
961 PREFIX_MOD_3_0F01_REG_5_RM_0,
962 PREFIX_MOD_3_0F01_REG_5_RM_2,
1007 PREFIX_MOD_0_0FAE_REG_4,
1008 PREFIX_MOD_3_0FAE_REG_4,
1009 PREFIX_MOD_0_0FAE_REG_5,
1010 PREFIX_MOD_3_0FAE_REG_5,
1018 PREFIX_MOD_0_0FC7_REG_6,
1019 PREFIX_MOD_3_0FC7_REG_6,
1020 PREFIX_MOD_3_0FC7_REG_7,
1148 PREFIX_VEX_0F71_REG_2,
1149 PREFIX_VEX_0F71_REG_4,
1150 PREFIX_VEX_0F71_REG_6,
1151 PREFIX_VEX_0F72_REG_2,
1152 PREFIX_VEX_0F72_REG_4,
1153 PREFIX_VEX_0F72_REG_6,
1154 PREFIX_VEX_0F73_REG_2,
1155 PREFIX_VEX_0F73_REG_3,
1156 PREFIX_VEX_0F73_REG_6,
1157 PREFIX_VEX_0F73_REG_7,
1330 PREFIX_VEX_0F38F3_REG_1,
1331 PREFIX_VEX_0F38F3_REG_2,
1332 PREFIX_VEX_0F38F3_REG_3,
1451 PREFIX_EVEX_0F71_REG_2,
1452 PREFIX_EVEX_0F71_REG_4,
1453 PREFIX_EVEX_0F71_REG_6,
1454 PREFIX_EVEX_0F72_REG_0,
1455 PREFIX_EVEX_0F72_REG_1,
1456 PREFIX_EVEX_0F72_REG_2,
1457 PREFIX_EVEX_0F72_REG_4,
1458 PREFIX_EVEX_0F72_REG_6,
1459 PREFIX_EVEX_0F73_REG_2,
1460 PREFIX_EVEX_0F73_REG_3,
1461 PREFIX_EVEX_0F73_REG_6,
1462 PREFIX_EVEX_0F73_REG_7,
1658 PREFIX_EVEX_0F38C6_REG_1,
1659 PREFIX_EVEX_0F38C6_REG_2,
1660 PREFIX_EVEX_0F38C6_REG_5,
1661 PREFIX_EVEX_0F38C6_REG_6,
1662 PREFIX_EVEX_0F38C7_REG_1,
1663 PREFIX_EVEX_0F38C7_REG_2,
1664 PREFIX_EVEX_0F38C7_REG_5,
1665 PREFIX_EVEX_0F38C7_REG_6,
1767 THREE_BYTE_0F38 = 0,
1794 VEX_LEN_0F10_P_1 = 0,
1798 VEX_LEN_0F12_P_0_M_0,
1799 VEX_LEN_0F12_P_0_M_1,
1802 VEX_LEN_0F16_P_0_M_0,
1803 VEX_LEN_0F16_P_0_M_1,
1867 VEX_LEN_0FAE_R_2_M_0,
1868 VEX_LEN_0FAE_R_3_M_0,
1877 VEX_LEN_0F381A_P_2_M_0,
1880 VEX_LEN_0F385A_P_2_M_0,
1883 VEX_LEN_0F38F3_R_1_P_0,
1884 VEX_LEN_0F38F3_R_2_P_0,
1885 VEX_LEN_0F38F3_R_3_P_0,
1930 VEX_LEN_0FXOP_08_CC,
1931 VEX_LEN_0FXOP_08_CD,
1932 VEX_LEN_0FXOP_08_CE,
1933 VEX_LEN_0FXOP_08_CF,
1934 VEX_LEN_0FXOP_08_EC,
1935 VEX_LEN_0FXOP_08_ED,
1936 VEX_LEN_0FXOP_08_EE,
1937 VEX_LEN_0FXOP_08_EF,
1938 VEX_LEN_0FXOP_09_80,
1972 VEX_W_0F41_P_0_LEN_1,
1973 VEX_W_0F41_P_2_LEN_1,
1974 VEX_W_0F42_P_0_LEN_1,
1975 VEX_W_0F42_P_2_LEN_1,
1976 VEX_W_0F44_P_0_LEN_0,
1977 VEX_W_0F44_P_2_LEN_0,
1978 VEX_W_0F45_P_0_LEN_1,
1979 VEX_W_0F45_P_2_LEN_1,
1980 VEX_W_0F46_P_0_LEN_1,
1981 VEX_W_0F46_P_2_LEN_1,
1982 VEX_W_0F47_P_0_LEN_1,
1983 VEX_W_0F47_P_2_LEN_1,
1984 VEX_W_0F4A_P_0_LEN_1,
1985 VEX_W_0F4A_P_2_LEN_1,
1986 VEX_W_0F4B_P_0_LEN_1,
1987 VEX_W_0F4B_P_2_LEN_1,
2067 VEX_W_0F90_P_0_LEN_0,
2068 VEX_W_0F90_P_2_LEN_0,
2069 VEX_W_0F91_P_0_LEN_0,
2070 VEX_W_0F91_P_2_LEN_0,
2071 VEX_W_0F92_P_0_LEN_0,
2072 VEX_W_0F92_P_2_LEN_0,
2073 VEX_W_0F92_P_3_LEN_0,
2074 VEX_W_0F93_P_0_LEN_0,
2075 VEX_W_0F93_P_2_LEN_0,
2076 VEX_W_0F93_P_3_LEN_0,
2077 VEX_W_0F98_P_0_LEN_0,
2078 VEX_W_0F98_P_2_LEN_0,
2079 VEX_W_0F99_P_0_LEN_0,
2080 VEX_W_0F99_P_2_LEN_0,
2159 VEX_W_0F381A_P_2_M_0,
2171 VEX_W_0F382A_P_2_M_0,
2173 VEX_W_0F382C_P_2_M_0,
2174 VEX_W_0F382D_P_2_M_0,
2175 VEX_W_0F382E_P_2_M_0,
2176 VEX_W_0F382F_P_2_M_0,
2198 VEX_W_0F385A_P_2_M_0,
2223 VEX_W_0F3A30_P_2_LEN_0,
2224 VEX_W_0F3A31_P_2_LEN_0,
2225 VEX_W_0F3A32_P_2_LEN_0,
2226 VEX_W_0F3A33_P_2_LEN_0,
2245 EVEX_W_0F10_P_1_M_0,
2246 EVEX_W_0F10_P_1_M_1,
2248 EVEX_W_0F10_P_3_M_0,
2249 EVEX_W_0F10_P_3_M_1,
2251 EVEX_W_0F11_P_1_M_0,
2252 EVEX_W_0F11_P_1_M_1,
2254 EVEX_W_0F11_P_3_M_0,
2255 EVEX_W_0F11_P_3_M_1,
2256 EVEX_W_0F12_P_0_M_0,
2257 EVEX_W_0F12_P_0_M_1,
2267 EVEX_W_0F16_P_0_M_0,
2268 EVEX_W_0F16_P_0_M_1,
2339 EVEX_W_0F72_R_2_P_2,
2340 EVEX_W_0F72_R_6_P_2,
2341 EVEX_W_0F73_R_2_P_2,
2342 EVEX_W_0F73_R_6_P_2,
2450 EVEX_W_0F38C7_R_1_P_2,
2451 EVEX_W_0F38C7_R_2_P_2,
2452 EVEX_W_0F38C7_R_5_P_2,
2453 EVEX_W_0F38C7_R_6_P_2,
2494 typedef void (*op_rtn) (int bytemode, int sizeflag);
2503 unsigned int prefix_requirement;
2506 /* Upper case letters in the instruction names here are macros.
2507 'A' => print 'b' if no register operands or suffix_always is true
2508 'B' => print 'b' if suffix_always is true
2509 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2511 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2512 suffix_always is true
2513 'E' => print 'e' if 32-bit form of jcxz
2514 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2515 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2516 'H' => print ",pt" or ",pn" branch hint
2517 'I' => honor following macro letter even in Intel mode (implemented only
2518 for some of the macro letters)
2520 'K' => print 'd' or 'q' if rex prefix is present.
2521 'L' => print 'l' if suffix_always is true
2522 'M' => print 'r' if intel_mnemonic is false.
2523 'N' => print 'n' if instruction has no wait "prefix"
2524 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2525 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2526 or suffix_always is true. print 'q' if rex prefix is present.
2527 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2529 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2530 'S' => print 'w', 'l' or 'q' if suffix_always is true
2531 'T' => print 'q' in 64bit mode if instruction has no operand size
2532 prefix and behave as 'P' otherwise
2533 'U' => print 'q' in 64bit mode if instruction has no operand size
2534 prefix and behave as 'Q' otherwise
2535 'V' => print 'q' in 64bit mode if instruction has no operand size
2536 prefix and behave as 'S' otherwise
2537 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2538 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2540 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2541 '!' => change condition from true to false or from false to true.
2542 '%' => add 1 upper case letter to the macro.
2543 '^' => print 'w' or 'l' depending on operand size prefix or
2544 suffix_always is true (lcall/ljmp).
2545 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2546 on operand size prefix.
2547 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2548 has no operand size prefix for AMD64 ISA, behave as 'P'
2551 2 upper case letter macros:
2552 "XY" => print 'x' or 'y' if suffix_always is true or no register
2553 operands and no broadcast.
2554 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2555 register operands and no broadcast.
2556 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2557 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2558 or suffix_always is true
2559 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2560 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2561 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2562 "LW" => print 'd', 'q' depending on the VEX.W bit
2563 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2564 an operand size prefix, or suffix_always is true. print
2565 'q' if rex prefix is present.
2567 Many of the above letters print nothing in Intel mode. See "putop"
2570 Braces '{' and '}', and vertical bars '|', indicate alternative
2571 mnemonic strings for AT&T and Intel. */
2573 static const struct dis386 dis386[] = {
2575 { "addB", { Ebh1, Gb }, 0 },
2576 { "addS", { Evh1, Gv }, 0 },
2577 { "addB", { Gb, EbS }, 0 },
2578 { "addS", { Gv, EvS }, 0 },
2579 { "addB", { AL, Ib }, 0 },
2580 { "addS", { eAX, Iv }, 0 },
2581 { X86_64_TABLE (X86_64_06) },
2582 { X86_64_TABLE (X86_64_07) },
2584 { "orB", { Ebh1, Gb }, 0 },
2585 { "orS", { Evh1, Gv }, 0 },
2586 { "orB", { Gb, EbS }, 0 },
2587 { "orS", { Gv, EvS }, 0 },
2588 { "orB", { AL, Ib }, 0 },
2589 { "orS", { eAX, Iv }, 0 },
2590 { X86_64_TABLE (X86_64_0D) },
2591 { Bad_Opcode }, /* 0x0f extended opcode escape */
2593 { "adcB", { Ebh1, Gb }, 0 },
2594 { "adcS", { Evh1, Gv }, 0 },
2595 { "adcB", { Gb, EbS }, 0 },
2596 { "adcS", { Gv, EvS }, 0 },
2597 { "adcB", { AL, Ib }, 0 },
2598 { "adcS", { eAX, Iv }, 0 },
2599 { X86_64_TABLE (X86_64_16) },
2600 { X86_64_TABLE (X86_64_17) },
2602 { "sbbB", { Ebh1, Gb }, 0 },
2603 { "sbbS", { Evh1, Gv }, 0 },
2604 { "sbbB", { Gb, EbS }, 0 },
2605 { "sbbS", { Gv, EvS }, 0 },
2606 { "sbbB", { AL, Ib }, 0 },
2607 { "sbbS", { eAX, Iv }, 0 },
2608 { X86_64_TABLE (X86_64_1E) },
2609 { X86_64_TABLE (X86_64_1F) },
2611 { "andB", { Ebh1, Gb }, 0 },
2612 { "andS", { Evh1, Gv }, 0 },
2613 { "andB", { Gb, EbS }, 0 },
2614 { "andS", { Gv, EvS }, 0 },
2615 { "andB", { AL, Ib }, 0 },
2616 { "andS", { eAX, Iv }, 0 },
2617 { Bad_Opcode }, /* SEG ES prefix */
2618 { X86_64_TABLE (X86_64_27) },
2620 { "subB", { Ebh1, Gb }, 0 },
2621 { "subS", { Evh1, Gv }, 0 },
2622 { "subB", { Gb, EbS }, 0 },
2623 { "subS", { Gv, EvS }, 0 },
2624 { "subB", { AL, Ib }, 0 },
2625 { "subS", { eAX, Iv }, 0 },
2626 { Bad_Opcode }, /* SEG CS prefix */
2627 { X86_64_TABLE (X86_64_2F) },
2629 { "xorB", { Ebh1, Gb }, 0 },
2630 { "xorS", { Evh1, Gv }, 0 },
2631 { "xorB", { Gb, EbS }, 0 },
2632 { "xorS", { Gv, EvS }, 0 },
2633 { "xorB", { AL, Ib }, 0 },
2634 { "xorS", { eAX, Iv }, 0 },
2635 { Bad_Opcode }, /* SEG SS prefix */
2636 { X86_64_TABLE (X86_64_37) },
2638 { "cmpB", { Eb, Gb }, 0 },
2639 { "cmpS", { Ev, Gv }, 0 },
2640 { "cmpB", { Gb, EbS }, 0 },
2641 { "cmpS", { Gv, EvS }, 0 },
2642 { "cmpB", { AL, Ib }, 0 },
2643 { "cmpS", { eAX, Iv }, 0 },
2644 { Bad_Opcode }, /* SEG DS prefix */
2645 { X86_64_TABLE (X86_64_3F) },
2647 { "inc{S|}", { RMeAX }, 0 },
2648 { "inc{S|}", { RMeCX }, 0 },
2649 { "inc{S|}", { RMeDX }, 0 },
2650 { "inc{S|}", { RMeBX }, 0 },
2651 { "inc{S|}", { RMeSP }, 0 },
2652 { "inc{S|}", { RMeBP }, 0 },
2653 { "inc{S|}", { RMeSI }, 0 },
2654 { "inc{S|}", { RMeDI }, 0 },
2656 { "dec{S|}", { RMeAX }, 0 },
2657 { "dec{S|}", { RMeCX }, 0 },
2658 { "dec{S|}", { RMeDX }, 0 },
2659 { "dec{S|}", { RMeBX }, 0 },
2660 { "dec{S|}", { RMeSP }, 0 },
2661 { "dec{S|}", { RMeBP }, 0 },
2662 { "dec{S|}", { RMeSI }, 0 },
2663 { "dec{S|}", { RMeDI }, 0 },
2665 { "pushV", { RMrAX }, 0 },
2666 { "pushV", { RMrCX }, 0 },
2667 { "pushV", { RMrDX }, 0 },
2668 { "pushV", { RMrBX }, 0 },
2669 { "pushV", { RMrSP }, 0 },
2670 { "pushV", { RMrBP }, 0 },
2671 { "pushV", { RMrSI }, 0 },
2672 { "pushV", { RMrDI }, 0 },
2674 { "popV", { RMrAX }, 0 },
2675 { "popV", { RMrCX }, 0 },
2676 { "popV", { RMrDX }, 0 },
2677 { "popV", { RMrBX }, 0 },
2678 { "popV", { RMrSP }, 0 },
2679 { "popV", { RMrBP }, 0 },
2680 { "popV", { RMrSI }, 0 },
2681 { "popV", { RMrDI }, 0 },
2683 { X86_64_TABLE (X86_64_60) },
2684 { X86_64_TABLE (X86_64_61) },
2685 { X86_64_TABLE (X86_64_62) },
2686 { X86_64_TABLE (X86_64_63) },
2687 { Bad_Opcode }, /* seg fs */
2688 { Bad_Opcode }, /* seg gs */
2689 { Bad_Opcode }, /* op size prefix */
2690 { Bad_Opcode }, /* adr size prefix */
2692 { "pushT", { sIv }, 0 },
2693 { "imulS", { Gv, Ev, Iv }, 0 },
2694 { "pushT", { sIbT }, 0 },
2695 { "imulS", { Gv, Ev, sIb }, 0 },
2696 { "ins{b|}", { Ybr, indirDX }, 0 },
2697 { X86_64_TABLE (X86_64_6D) },
2698 { "outs{b|}", { indirDXr, Xb }, 0 },
2699 { X86_64_TABLE (X86_64_6F) },
2701 { "joH", { Jb, BND, cond_jump_flag }, 0 },
2702 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
2703 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
2704 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
2705 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
2706 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
2707 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
2708 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
2710 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
2711 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
2712 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
2713 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
2714 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
2715 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
2716 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
2717 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
2719 { REG_TABLE (REG_80) },
2720 { REG_TABLE (REG_81) },
2721 { X86_64_TABLE (X86_64_82) },
2722 { REG_TABLE (REG_83) },
2723 { "testB", { Eb, Gb }, 0 },
2724 { "testS", { Ev, Gv }, 0 },
2725 { "xchgB", { Ebh2, Gb }, 0 },
2726 { "xchgS", { Evh2, Gv }, 0 },
2728 { "movB", { Ebh3, Gb }, 0 },
2729 { "movS", { Evh3, Gv }, 0 },
2730 { "movB", { Gb, EbS }, 0 },
2731 { "movS", { Gv, EvS }, 0 },
2732 { "movD", { Sv, Sw }, 0 },
2733 { MOD_TABLE (MOD_8D) },
2734 { "movD", { Sw, Sv }, 0 },
2735 { REG_TABLE (REG_8F) },
2737 { PREFIX_TABLE (PREFIX_90) },
2738 { "xchgS", { RMeCX, eAX }, 0 },
2739 { "xchgS", { RMeDX, eAX }, 0 },
2740 { "xchgS", { RMeBX, eAX }, 0 },
2741 { "xchgS", { RMeSP, eAX }, 0 },
2742 { "xchgS", { RMeBP, eAX }, 0 },
2743 { "xchgS", { RMeSI, eAX }, 0 },
2744 { "xchgS", { RMeDI, eAX }, 0 },
2746 { "cW{t|}R", { XX }, 0 },
2747 { "cR{t|}O", { XX }, 0 },
2748 { X86_64_TABLE (X86_64_9A) },
2749 { Bad_Opcode }, /* fwait */
2750 { "pushfT", { XX }, 0 },
2751 { "popfT", { XX }, 0 },
2752 { "sahf", { XX }, 0 },
2753 { "lahf", { XX }, 0 },
2755 { "mov%LB", { AL, Ob }, 0 },
2756 { "mov%LS", { eAX, Ov }, 0 },
2757 { "mov%LB", { Ob, AL }, 0 },
2758 { "mov%LS", { Ov, eAX }, 0 },
2759 { "movs{b|}", { Ybr, Xb }, 0 },
2760 { "movs{R|}", { Yvr, Xv }, 0 },
2761 { "cmps{b|}", { Xb, Yb }, 0 },
2762 { "cmps{R|}", { Xv, Yv }, 0 },
2764 { "testB", { AL, Ib }, 0 },
2765 { "testS", { eAX, Iv }, 0 },
2766 { "stosB", { Ybr, AL }, 0 },
2767 { "stosS", { Yvr, eAX }, 0 },
2768 { "lodsB", { ALr, Xb }, 0 },
2769 { "lodsS", { eAXr, Xv }, 0 },
2770 { "scasB", { AL, Yb }, 0 },
2771 { "scasS", { eAX, Yv }, 0 },
2773 { "movB", { RMAL, Ib }, 0 },
2774 { "movB", { RMCL, Ib }, 0 },
2775 { "movB", { RMDL, Ib }, 0 },
2776 { "movB", { RMBL, Ib }, 0 },
2777 { "movB", { RMAH, Ib }, 0 },
2778 { "movB", { RMCH, Ib }, 0 },
2779 { "movB", { RMDH, Ib }, 0 },
2780 { "movB", { RMBH, Ib }, 0 },
2782 { "mov%LV", { RMeAX, Iv64 }, 0 },
2783 { "mov%LV", { RMeCX, Iv64 }, 0 },
2784 { "mov%LV", { RMeDX, Iv64 }, 0 },
2785 { "mov%LV", { RMeBX, Iv64 }, 0 },
2786 { "mov%LV", { RMeSP, Iv64 }, 0 },
2787 { "mov%LV", { RMeBP, Iv64 }, 0 },
2788 { "mov%LV", { RMeSI, Iv64 }, 0 },
2789 { "mov%LV", { RMeDI, Iv64 }, 0 },
2791 { REG_TABLE (REG_C0) },
2792 { REG_TABLE (REG_C1) },
2793 { "retT", { Iw, BND }, 0 },
2794 { "retT", { BND }, 0 },
2795 { X86_64_TABLE (X86_64_C4) },
2796 { X86_64_TABLE (X86_64_C5) },
2797 { REG_TABLE (REG_C6) },
2798 { REG_TABLE (REG_C7) },
2800 { "enterT", { Iw, Ib }, 0 },
2801 { "leaveT", { XX }, 0 },
2802 { "Jret{|f}P", { Iw }, 0 },
2803 { "Jret{|f}P", { XX }, 0 },
2804 { "int3", { XX }, 0 },
2805 { "int", { Ib }, 0 },
2806 { X86_64_TABLE (X86_64_CE) },
2807 { "iret%LP", { XX }, 0 },
2809 { REG_TABLE (REG_D0) },
2810 { REG_TABLE (REG_D1) },
2811 { REG_TABLE (REG_D2) },
2812 { REG_TABLE (REG_D3) },
2813 { X86_64_TABLE (X86_64_D4) },
2814 { X86_64_TABLE (X86_64_D5) },
2816 { "xlat", { DSBX }, 0 },
2827 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2828 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2829 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2830 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2831 { "inB", { AL, Ib }, 0 },
2832 { "inG", { zAX, Ib }, 0 },
2833 { "outB", { Ib, AL }, 0 },
2834 { "outG", { Ib, zAX }, 0 },
2836 { X86_64_TABLE (X86_64_E8) },
2837 { X86_64_TABLE (X86_64_E9) },
2838 { X86_64_TABLE (X86_64_EA) },
2839 { "jmp", { Jb, BND }, 0 },
2840 { "inB", { AL, indirDX }, 0 },
2841 { "inG", { zAX, indirDX }, 0 },
2842 { "outB", { indirDX, AL }, 0 },
2843 { "outG", { indirDX, zAX }, 0 },
2845 { Bad_Opcode }, /* lock prefix */
2846 { "icebp", { XX }, 0 },
2847 { Bad_Opcode }, /* repne */
2848 { Bad_Opcode }, /* repz */
2849 { "hlt", { XX }, 0 },
2850 { "cmc", { XX }, 0 },
2851 { REG_TABLE (REG_F6) },
2852 { REG_TABLE (REG_F7) },
2854 { "clc", { XX }, 0 },
2855 { "stc", { XX }, 0 },
2856 { "cli", { XX }, 0 },
2857 { "sti", { XX }, 0 },
2858 { "cld", { XX }, 0 },
2859 { "std", { XX }, 0 },
2860 { REG_TABLE (REG_FE) },
2861 { REG_TABLE (REG_FF) },
2864 static const struct dis386 dis386_twobyte[] = {
2866 { REG_TABLE (REG_0F00 ) },
2867 { REG_TABLE (REG_0F01 ) },
2868 { "larS", { Gv, Ew }, 0 },
2869 { "lslS", { Gv, Ew }, 0 },
2871 { "syscall", { XX }, 0 },
2872 { "clts", { XX }, 0 },
2873 { "sysret%LP", { XX }, 0 },
2875 { "invd", { XX }, 0 },
2876 { PREFIX_TABLE (PREFIX_0F09) },
2878 { "ud2", { XX }, 0 },
2880 { REG_TABLE (REG_0F0D) },
2881 { "femms", { XX }, 0 },
2882 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2884 { PREFIX_TABLE (PREFIX_0F10) },
2885 { PREFIX_TABLE (PREFIX_0F11) },
2886 { PREFIX_TABLE (PREFIX_0F12) },
2887 { MOD_TABLE (MOD_0F13) },
2888 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2889 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2890 { PREFIX_TABLE (PREFIX_0F16) },
2891 { MOD_TABLE (MOD_0F17) },
2893 { REG_TABLE (REG_0F18) },
2894 { "nopQ", { Ev }, 0 },
2895 { PREFIX_TABLE (PREFIX_0F1A) },
2896 { PREFIX_TABLE (PREFIX_0F1B) },
2897 { "nopQ", { Ev }, 0 },
2898 { "nopQ", { Ev }, 0 },
2899 { PREFIX_TABLE (PREFIX_0F1E) },
2900 { "nopQ", { Ev }, 0 },
2902 { "movZ", { Rm, Cm }, 0 },
2903 { "movZ", { Rm, Dm }, 0 },
2904 { "movZ", { Cm, Rm }, 0 },
2905 { "movZ", { Dm, Rm }, 0 },
2906 { MOD_TABLE (MOD_0F24) },
2908 { MOD_TABLE (MOD_0F26) },
2911 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2912 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2913 { PREFIX_TABLE (PREFIX_0F2A) },
2914 { PREFIX_TABLE (PREFIX_0F2B) },
2915 { PREFIX_TABLE (PREFIX_0F2C) },
2916 { PREFIX_TABLE (PREFIX_0F2D) },
2917 { PREFIX_TABLE (PREFIX_0F2E) },
2918 { PREFIX_TABLE (PREFIX_0F2F) },
2920 { "wrmsr", { XX }, 0 },
2921 { "rdtsc", { XX }, 0 },
2922 { "rdmsr", { XX }, 0 },
2923 { "rdpmc", { XX }, 0 },
2924 { "sysenter", { XX }, 0 },
2925 { "sysexit", { XX }, 0 },
2927 { "getsec", { XX }, 0 },
2929 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2931 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2938 { "cmovoS", { Gv, Ev }, 0 },
2939 { "cmovnoS", { Gv, Ev }, 0 },
2940 { "cmovbS", { Gv, Ev }, 0 },
2941 { "cmovaeS", { Gv, Ev }, 0 },
2942 { "cmoveS", { Gv, Ev }, 0 },
2943 { "cmovneS", { Gv, Ev }, 0 },
2944 { "cmovbeS", { Gv, Ev }, 0 },
2945 { "cmovaS", { Gv, Ev }, 0 },
2947 { "cmovsS", { Gv, Ev }, 0 },
2948 { "cmovnsS", { Gv, Ev }, 0 },
2949 { "cmovpS", { Gv, Ev }, 0 },
2950 { "cmovnpS", { Gv, Ev }, 0 },
2951 { "cmovlS", { Gv, Ev }, 0 },
2952 { "cmovgeS", { Gv, Ev }, 0 },
2953 { "cmovleS", { Gv, Ev }, 0 },
2954 { "cmovgS", { Gv, Ev }, 0 },
2956 { MOD_TABLE (MOD_0F51) },
2957 { PREFIX_TABLE (PREFIX_0F51) },
2958 { PREFIX_TABLE (PREFIX_0F52) },
2959 { PREFIX_TABLE (PREFIX_0F53) },
2960 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2961 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2962 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2963 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2965 { PREFIX_TABLE (PREFIX_0F58) },
2966 { PREFIX_TABLE (PREFIX_0F59) },
2967 { PREFIX_TABLE (PREFIX_0F5A) },
2968 { PREFIX_TABLE (PREFIX_0F5B) },
2969 { PREFIX_TABLE (PREFIX_0F5C) },
2970 { PREFIX_TABLE (PREFIX_0F5D) },
2971 { PREFIX_TABLE (PREFIX_0F5E) },
2972 { PREFIX_TABLE (PREFIX_0F5F) },
2974 { PREFIX_TABLE (PREFIX_0F60) },
2975 { PREFIX_TABLE (PREFIX_0F61) },
2976 { PREFIX_TABLE (PREFIX_0F62) },
2977 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2978 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2979 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2980 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2981 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2983 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2984 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2985 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2986 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2987 { PREFIX_TABLE (PREFIX_0F6C) },
2988 { PREFIX_TABLE (PREFIX_0F6D) },
2989 { "movK", { MX, Edq }, PREFIX_OPCODE },
2990 { PREFIX_TABLE (PREFIX_0F6F) },
2992 { PREFIX_TABLE (PREFIX_0F70) },
2993 { REG_TABLE (REG_0F71) },
2994 { REG_TABLE (REG_0F72) },
2995 { REG_TABLE (REG_0F73) },
2996 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2997 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2998 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2999 { "emms", { XX }, PREFIX_OPCODE },
3001 { PREFIX_TABLE (PREFIX_0F78) },
3002 { PREFIX_TABLE (PREFIX_0F79) },
3005 { PREFIX_TABLE (PREFIX_0F7C) },
3006 { PREFIX_TABLE (PREFIX_0F7D) },
3007 { PREFIX_TABLE (PREFIX_0F7E) },
3008 { PREFIX_TABLE (PREFIX_0F7F) },
3010 { "joH", { Jv, BND, cond_jump_flag }, 0 },
3011 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
3012 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
3013 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
3014 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
3015 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
3016 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
3017 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
3019 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
3020 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
3021 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
3022 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
3023 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
3024 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
3025 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
3026 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
3028 { "seto", { Eb }, 0 },
3029 { "setno", { Eb }, 0 },
3030 { "setb", { Eb }, 0 },
3031 { "setae", { Eb }, 0 },
3032 { "sete", { Eb }, 0 },
3033 { "setne", { Eb }, 0 },
3034 { "setbe", { Eb }, 0 },
3035 { "seta", { Eb }, 0 },
3037 { "sets", { Eb }, 0 },
3038 { "setns", { Eb }, 0 },
3039 { "setp", { Eb }, 0 },
3040 { "setnp", { Eb }, 0 },
3041 { "setl", { Eb }, 0 },
3042 { "setge", { Eb }, 0 },
3043 { "setle", { Eb }, 0 },
3044 { "setg", { Eb }, 0 },
3046 { "pushT", { fs }, 0 },
3047 { "popT", { fs }, 0 },
3048 { "cpuid", { XX }, 0 },
3049 { "btS", { Ev, Gv }, 0 },
3050 { "shldS", { Ev, Gv, Ib }, 0 },
3051 { "shldS", { Ev, Gv, CL }, 0 },
3052 { REG_TABLE (REG_0FA6) },
3053 { REG_TABLE (REG_0FA7) },
3055 { "pushT", { gs }, 0 },
3056 { "popT", { gs }, 0 },
3057 { "rsm", { XX }, 0 },
3058 { "btsS", { Evh1, Gv }, 0 },
3059 { "shrdS", { Ev, Gv, Ib }, 0 },
3060 { "shrdS", { Ev, Gv, CL }, 0 },
3061 { REG_TABLE (REG_0FAE) },
3062 { "imulS", { Gv, Ev }, 0 },
3064 { "cmpxchgB", { Ebh1, Gb }, 0 },
3065 { "cmpxchgS", { Evh1, Gv }, 0 },
3066 { MOD_TABLE (MOD_0FB2) },
3067 { "btrS", { Evh1, Gv }, 0 },
3068 { MOD_TABLE (MOD_0FB4) },
3069 { MOD_TABLE (MOD_0FB5) },
3070 { "movz{bR|x}", { Gv, Eb }, 0 },
3071 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3073 { PREFIX_TABLE (PREFIX_0FB8) },
3074 { "ud1S", { Gv, Ev }, 0 },
3075 { REG_TABLE (REG_0FBA) },
3076 { "btcS", { Evh1, Gv }, 0 },
3077 { PREFIX_TABLE (PREFIX_0FBC) },
3078 { PREFIX_TABLE (PREFIX_0FBD) },
3079 { "movs{bR|x}", { Gv, Eb }, 0 },
3080 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3082 { "xaddB", { Ebh1, Gb }, 0 },
3083 { "xaddS", { Evh1, Gv }, 0 },
3084 { PREFIX_TABLE (PREFIX_0FC2) },
3085 { MOD_TABLE (MOD_0FC3) },
3086 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
3087 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
3088 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
3089 { REG_TABLE (REG_0FC7) },
3091 { "bswap", { RMeAX }, 0 },
3092 { "bswap", { RMeCX }, 0 },
3093 { "bswap", { RMeDX }, 0 },
3094 { "bswap", { RMeBX }, 0 },
3095 { "bswap", { RMeSP }, 0 },
3096 { "bswap", { RMeBP }, 0 },
3097 { "bswap", { RMeSI }, 0 },
3098 { "bswap", { RMeDI }, 0 },
3100 { PREFIX_TABLE (PREFIX_0FD0) },
3101 { "psrlw", { MX, EM }, PREFIX_OPCODE },
3102 { "psrld", { MX, EM }, PREFIX_OPCODE },
3103 { "psrlq", { MX, EM }, PREFIX_OPCODE },
3104 { "paddq", { MX, EM }, PREFIX_OPCODE },
3105 { "pmullw", { MX, EM }, PREFIX_OPCODE },
3106 { PREFIX_TABLE (PREFIX_0FD6) },
3107 { MOD_TABLE (MOD_0FD7) },
3109 { "psubusb", { MX, EM }, PREFIX_OPCODE },
3110 { "psubusw", { MX, EM }, PREFIX_OPCODE },
3111 { "pminub", { MX, EM }, PREFIX_OPCODE },
3112 { "pand", { MX, EM }, PREFIX_OPCODE },
3113 { "paddusb", { MX, EM }, PREFIX_OPCODE },
3114 { "paddusw", { MX, EM }, PREFIX_OPCODE },
3115 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
3116 { "pandn", { MX, EM }, PREFIX_OPCODE },
3118 { "pavgb", { MX, EM }, PREFIX_OPCODE },
3119 { "psraw", { MX, EM }, PREFIX_OPCODE },
3120 { "psrad", { MX, EM }, PREFIX_OPCODE },
3121 { "pavgw", { MX, EM }, PREFIX_OPCODE },
3122 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
3123 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
3124 { PREFIX_TABLE (PREFIX_0FE6) },
3125 { PREFIX_TABLE (PREFIX_0FE7) },
3127 { "psubsb", { MX, EM }, PREFIX_OPCODE },
3128 { "psubsw", { MX, EM }, PREFIX_OPCODE },
3129 { "pminsw", { MX, EM }, PREFIX_OPCODE },
3130 { "por", { MX, EM }, PREFIX_OPCODE },
3131 { "paddsb", { MX, EM }, PREFIX_OPCODE },
3132 { "paddsw", { MX, EM }, PREFIX_OPCODE },
3133 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
3134 { "pxor", { MX, EM }, PREFIX_OPCODE },
3136 { PREFIX_TABLE (PREFIX_0FF0) },
3137 { "psllw", { MX, EM }, PREFIX_OPCODE },
3138 { "pslld", { MX, EM }, PREFIX_OPCODE },
3139 { "psllq", { MX, EM }, PREFIX_OPCODE },
3140 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
3141 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
3142 { "psadbw", { MX, EM }, PREFIX_OPCODE },
3143 { PREFIX_TABLE (PREFIX_0FF7) },
3145 { "psubb", { MX, EM }, PREFIX_OPCODE },
3146 { "psubw", { MX, EM }, PREFIX_OPCODE },
3147 { "psubd", { MX, EM }, PREFIX_OPCODE },
3148 { "psubq", { MX, EM }, PREFIX_OPCODE },
3149 { "paddb", { MX, EM }, PREFIX_OPCODE },
3150 { "paddw", { MX, EM }, PREFIX_OPCODE },
3151 { "paddd", { MX, EM }, PREFIX_OPCODE },
3152 { "ud0S", { Gv, Ev }, 0 },
3155 static const unsigned char onebyte_has_modrm[256] = {
3156 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3157 /* ------------------------------- */
3158 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3159 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3160 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3161 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3162 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3163 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3164 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3165 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3166 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3167 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3168 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3169 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3170 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3171 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3172 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3173 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3174 /* ------------------------------- */
3175 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3178 static const unsigned char twobyte_has_modrm[256] = {
3179 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3180 /* ------------------------------- */
3181 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3182 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3183 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3184 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3185 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3186 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3187 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3188 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3189 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3190 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3191 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3192 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
3193 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3194 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3195 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3196 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
3197 /* ------------------------------- */
3198 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3201 static char obuf[100];
3203 static char *mnemonicendp;
3204 static char scratchbuf[100];
3205 static unsigned char *start_codep;
3206 static unsigned char *insn_codep;
3207 static unsigned char *codep;
3208 static unsigned char *end_codep;
3209 static int last_lock_prefix;
3210 static int last_repz_prefix;
3211 static int last_repnz_prefix;
3212 static int last_data_prefix;
3213 static int last_addr_prefix;
3214 static int last_rex_prefix;
3215 static int last_seg_prefix;
3216 static int fwait_prefix;
3217 /* The active segment register prefix. */
3218 static int active_seg_prefix;
3219 #define MAX_CODE_LENGTH 15
3220 /* We can up to 14 prefixes since the maximum instruction length is
3222 static int all_prefixes[MAX_CODE_LENGTH - 1];
3223 static disassemble_info *the_info;
3231 static unsigned char need_modrm;
3241 int register_specifier;
3248 int mask_register_specifier;
3254 static unsigned char need_vex;
3255 static unsigned char need_vex_reg;
3256 static unsigned char vex_w_done;
3264 /* If we are accessing mod/rm/reg without need_modrm set, then the
3265 values are stale. Hitting this abort likely indicates that you
3266 need to update onebyte_has_modrm or twobyte_has_modrm. */
3267 #define MODRM_CHECK if (!need_modrm) abort ()
3269 static const char **names64;
3270 static const char **names32;
3271 static const char **names16;
3272 static const char **names8;
3273 static const char **names8rex;
3274 static const char **names_seg;
3275 static const char *index64;
3276 static const char *index32;
3277 static const char **index16;
3278 static const char **names_bnd;
3280 static const char *intel_names64[] = {
3281 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3282 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3284 static const char *intel_names32[] = {
3285 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3286 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3288 static const char *intel_names16[] = {
3289 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3290 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3292 static const char *intel_names8[] = {
3293 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3295 static const char *intel_names8rex[] = {
3296 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3297 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3299 static const char *intel_names_seg[] = {
3300 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3302 static const char *intel_index64 = "riz";
3303 static const char *intel_index32 = "eiz";
3304 static const char *intel_index16[] = {
3305 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3308 static const char *att_names64[] = {
3309 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3310 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3312 static const char *att_names32[] = {
3313 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3314 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3316 static const char *att_names16[] = {
3317 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3318 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3320 static const char *att_names8[] = {
3321 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3323 static const char *att_names8rex[] = {
3324 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3325 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3327 static const char *att_names_seg[] = {
3328 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3330 static const char *att_index64 = "%riz";
3331 static const char *att_index32 = "%eiz";
3332 static const char *att_index16[] = {
3333 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3336 static const char **names_mm;
3337 static const char *intel_names_mm[] = {
3338 "mm0", "mm1", "mm2", "mm3",
3339 "mm4", "mm5", "mm6", "mm7"
3341 static const char *att_names_mm[] = {
3342 "%mm0", "%mm1", "%mm2", "%mm3",
3343 "%mm4", "%mm5", "%mm6", "%mm7"
3346 static const char *intel_names_bnd[] = {
3347 "bnd0", "bnd1", "bnd2", "bnd3"
3350 static const char *att_names_bnd[] = {
3351 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3354 static const char **names_xmm;
3355 static const char *intel_names_xmm[] = {
3356 "xmm0", "xmm1", "xmm2", "xmm3",
3357 "xmm4", "xmm5", "xmm6", "xmm7",
3358 "xmm8", "xmm9", "xmm10", "xmm11",
3359 "xmm12", "xmm13", "xmm14", "xmm15",
3360 "xmm16", "xmm17", "xmm18", "xmm19",
3361 "xmm20", "xmm21", "xmm22", "xmm23",
3362 "xmm24", "xmm25", "xmm26", "xmm27",
3363 "xmm28", "xmm29", "xmm30", "xmm31"
3365 static const char *att_names_xmm[] = {
3366 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3367 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3368 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3369 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3370 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3371 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3372 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3373 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3376 static const char **names_ymm;
3377 static const char *intel_names_ymm[] = {
3378 "ymm0", "ymm1", "ymm2", "ymm3",
3379 "ymm4", "ymm5", "ymm6", "ymm7",
3380 "ymm8", "ymm9", "ymm10", "ymm11",
3381 "ymm12", "ymm13", "ymm14", "ymm15",
3382 "ymm16", "ymm17", "ymm18", "ymm19",
3383 "ymm20", "ymm21", "ymm22", "ymm23",
3384 "ymm24", "ymm25", "ymm26", "ymm27",
3385 "ymm28", "ymm29", "ymm30", "ymm31"
3387 static const char *att_names_ymm[] = {
3388 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3389 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3390 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3391 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3392 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3393 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3394 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3395 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3398 static const char **names_zmm;
3399 static const char *intel_names_zmm[] = {
3400 "zmm0", "zmm1", "zmm2", "zmm3",
3401 "zmm4", "zmm5", "zmm6", "zmm7",
3402 "zmm8", "zmm9", "zmm10", "zmm11",
3403 "zmm12", "zmm13", "zmm14", "zmm15",
3404 "zmm16", "zmm17", "zmm18", "zmm19",
3405 "zmm20", "zmm21", "zmm22", "zmm23",
3406 "zmm24", "zmm25", "zmm26", "zmm27",
3407 "zmm28", "zmm29", "zmm30", "zmm31"
3409 static const char *att_names_zmm[] = {
3410 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3411 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3412 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3413 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3414 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3415 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3416 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3417 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3420 static const char **names_mask;
3421 static const char *intel_names_mask[] = {
3422 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3424 static const char *att_names_mask[] = {
3425 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3428 static const char *names_rounding[] =
3436 static const struct dis386 reg_table[][8] = {
3439 { "addA", { Ebh1, Ib }, 0 },
3440 { "orA", { Ebh1, Ib }, 0 },
3441 { "adcA", { Ebh1, Ib }, 0 },
3442 { "sbbA", { Ebh1, Ib }, 0 },
3443 { "andA", { Ebh1, Ib }, 0 },
3444 { "subA", { Ebh1, Ib }, 0 },
3445 { "xorA", { Ebh1, Ib }, 0 },
3446 { "cmpA", { Eb, Ib }, 0 },
3450 { "addQ", { Evh1, Iv }, 0 },
3451 { "orQ", { Evh1, Iv }, 0 },
3452 { "adcQ", { Evh1, Iv }, 0 },
3453 { "sbbQ", { Evh1, Iv }, 0 },
3454 { "andQ", { Evh1, Iv }, 0 },
3455 { "subQ", { Evh1, Iv }, 0 },
3456 { "xorQ", { Evh1, Iv }, 0 },
3457 { "cmpQ", { Ev, Iv }, 0 },
3461 { "addQ", { Evh1, sIb }, 0 },
3462 { "orQ", { Evh1, sIb }, 0 },
3463 { "adcQ", { Evh1, sIb }, 0 },
3464 { "sbbQ", { Evh1, sIb }, 0 },
3465 { "andQ", { Evh1, sIb }, 0 },
3466 { "subQ", { Evh1, sIb }, 0 },
3467 { "xorQ", { Evh1, sIb }, 0 },
3468 { "cmpQ", { Ev, sIb }, 0 },
3472 { "popU", { stackEv }, 0 },
3473 { XOP_8F_TABLE (XOP_09) },
3477 { XOP_8F_TABLE (XOP_09) },
3481 { "rolA", { Eb, Ib }, 0 },
3482 { "rorA", { Eb, Ib }, 0 },
3483 { "rclA", { Eb, Ib }, 0 },
3484 { "rcrA", { Eb, Ib }, 0 },
3485 { "shlA", { Eb, Ib }, 0 },
3486 { "shrA", { Eb, Ib }, 0 },
3487 { "shlA", { Eb, Ib }, 0 },
3488 { "sarA", { Eb, Ib }, 0 },
3492 { "rolQ", { Ev, Ib }, 0 },
3493 { "rorQ", { Ev, Ib }, 0 },
3494 { "rclQ", { Ev, Ib }, 0 },
3495 { "rcrQ", { Ev, Ib }, 0 },
3496 { "shlQ", { Ev, Ib }, 0 },
3497 { "shrQ", { Ev, Ib }, 0 },
3498 { "shlQ", { Ev, Ib }, 0 },
3499 { "sarQ", { Ev, Ib }, 0 },
3503 { "movA", { Ebh3, Ib }, 0 },
3510 { MOD_TABLE (MOD_C6_REG_7) },
3514 { "movQ", { Evh3, Iv }, 0 },
3521 { MOD_TABLE (MOD_C7_REG_7) },
3525 { "rolA", { Eb, I1 }, 0 },
3526 { "rorA", { Eb, I1 }, 0 },
3527 { "rclA", { Eb, I1 }, 0 },
3528 { "rcrA", { Eb, I1 }, 0 },
3529 { "shlA", { Eb, I1 }, 0 },
3530 { "shrA", { Eb, I1 }, 0 },
3531 { "shlA", { Eb, I1 }, 0 },
3532 { "sarA", { Eb, I1 }, 0 },
3536 { "rolQ", { Ev, I1 }, 0 },
3537 { "rorQ", { Ev, I1 }, 0 },
3538 { "rclQ", { Ev, I1 }, 0 },
3539 { "rcrQ", { Ev, I1 }, 0 },
3540 { "shlQ", { Ev, I1 }, 0 },
3541 { "shrQ", { Ev, I1 }, 0 },
3542 { "shlQ", { Ev, I1 }, 0 },
3543 { "sarQ", { Ev, I1 }, 0 },
3547 { "rolA", { Eb, CL }, 0 },
3548 { "rorA", { Eb, CL }, 0 },
3549 { "rclA", { Eb, CL }, 0 },
3550 { "rcrA", { Eb, CL }, 0 },
3551 { "shlA", { Eb, CL }, 0 },
3552 { "shrA", { Eb, CL }, 0 },
3553 { "shlA", { Eb, CL }, 0 },
3554 { "sarA", { Eb, CL }, 0 },
3558 { "rolQ", { Ev, CL }, 0 },
3559 { "rorQ", { Ev, CL }, 0 },
3560 { "rclQ", { Ev, CL }, 0 },
3561 { "rcrQ", { Ev, CL }, 0 },
3562 { "shlQ", { Ev, CL }, 0 },
3563 { "shrQ", { Ev, CL }, 0 },
3564 { "shlQ", { Ev, CL }, 0 },
3565 { "sarQ", { Ev, CL }, 0 },
3569 { "testA", { Eb, Ib }, 0 },
3570 { "testA", { Eb, Ib }, 0 },
3571 { "notA", { Ebh1 }, 0 },
3572 { "negA", { Ebh1 }, 0 },
3573 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
3574 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
3575 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
3576 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
3580 { "testQ", { Ev, Iv }, 0 },
3581 { "testQ", { Ev, Iv }, 0 },
3582 { "notQ", { Evh1 }, 0 },
3583 { "negQ", { Evh1 }, 0 },
3584 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
3585 { "imulQ", { Ev }, 0 },
3586 { "divQ", { Ev }, 0 },
3587 { "idivQ", { Ev }, 0 },
3591 { "incA", { Ebh1 }, 0 },
3592 { "decA", { Ebh1 }, 0 },
3596 { "incQ", { Evh1 }, 0 },
3597 { "decQ", { Evh1 }, 0 },
3598 { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3599 { MOD_TABLE (MOD_FF_REG_3) },
3600 { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3601 { MOD_TABLE (MOD_FF_REG_5) },
3602 { "pushU", { stackEv }, 0 },
3607 { "sldtD", { Sv }, 0 },
3608 { "strD", { Sv }, 0 },
3609 { "lldt", { Ew }, 0 },
3610 { "ltr", { Ew }, 0 },
3611 { "verr", { Ew }, 0 },
3612 { "verw", { Ew }, 0 },
3618 { MOD_TABLE (MOD_0F01_REG_0) },
3619 { MOD_TABLE (MOD_0F01_REG_1) },
3620 { MOD_TABLE (MOD_0F01_REG_2) },
3621 { MOD_TABLE (MOD_0F01_REG_3) },
3622 { "smswD", { Sv }, 0 },
3623 { MOD_TABLE (MOD_0F01_REG_5) },
3624 { "lmsw", { Ew }, 0 },
3625 { MOD_TABLE (MOD_0F01_REG_7) },
3629 { "prefetch", { Mb }, 0 },
3630 { "prefetchw", { Mb }, 0 },
3631 { "prefetchwt1", { Mb }, 0 },
3632 { "prefetch", { Mb }, 0 },
3633 { "prefetch", { Mb }, 0 },
3634 { "prefetch", { Mb }, 0 },
3635 { "prefetch", { Mb }, 0 },
3636 { "prefetch", { Mb }, 0 },
3640 { MOD_TABLE (MOD_0F18_REG_0) },
3641 { MOD_TABLE (MOD_0F18_REG_1) },
3642 { MOD_TABLE (MOD_0F18_REG_2) },
3643 { MOD_TABLE (MOD_0F18_REG_3) },
3644 { MOD_TABLE (MOD_0F18_REG_4) },
3645 { MOD_TABLE (MOD_0F18_REG_5) },
3646 { MOD_TABLE (MOD_0F18_REG_6) },
3647 { MOD_TABLE (MOD_0F18_REG_7) },
3649 /* REG_0F1E_MOD_3 */
3651 { "nopQ", { Ev }, 0 },
3652 { "rdsspK", { Rdq }, PREFIX_OPCODE },
3653 { "nopQ", { Ev }, 0 },
3654 { "nopQ", { Ev }, 0 },
3655 { "nopQ", { Ev }, 0 },
3656 { "nopQ", { Ev }, 0 },
3657 { "nopQ", { Ev }, 0 },
3658 { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3664 { MOD_TABLE (MOD_0F71_REG_2) },
3666 { MOD_TABLE (MOD_0F71_REG_4) },
3668 { MOD_TABLE (MOD_0F71_REG_6) },
3674 { MOD_TABLE (MOD_0F72_REG_2) },
3676 { MOD_TABLE (MOD_0F72_REG_4) },
3678 { MOD_TABLE (MOD_0F72_REG_6) },
3684 { MOD_TABLE (MOD_0F73_REG_2) },
3685 { MOD_TABLE (MOD_0F73_REG_3) },
3688 { MOD_TABLE (MOD_0F73_REG_6) },
3689 { MOD_TABLE (MOD_0F73_REG_7) },
3693 { "montmul", { { OP_0f07, 0 } }, 0 },
3694 { "xsha1", { { OP_0f07, 0 } }, 0 },
3695 { "xsha256", { { OP_0f07, 0 } }, 0 },
3699 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
3700 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
3701 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
3702 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
3703 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
3704 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
3708 { MOD_TABLE (MOD_0FAE_REG_0) },
3709 { MOD_TABLE (MOD_0FAE_REG_1) },
3710 { MOD_TABLE (MOD_0FAE_REG_2) },
3711 { MOD_TABLE (MOD_0FAE_REG_3) },
3712 { MOD_TABLE (MOD_0FAE_REG_4) },
3713 { MOD_TABLE (MOD_0FAE_REG_5) },
3714 { MOD_TABLE (MOD_0FAE_REG_6) },
3715 { MOD_TABLE (MOD_0FAE_REG_7) },
3723 { "btQ", { Ev, Ib }, 0 },
3724 { "btsQ", { Evh1, Ib }, 0 },
3725 { "btrQ", { Evh1, Ib }, 0 },
3726 { "btcQ", { Evh1, Ib }, 0 },
3731 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3733 { MOD_TABLE (MOD_0FC7_REG_3) },
3734 { MOD_TABLE (MOD_0FC7_REG_4) },
3735 { MOD_TABLE (MOD_0FC7_REG_5) },
3736 { MOD_TABLE (MOD_0FC7_REG_6) },
3737 { MOD_TABLE (MOD_0FC7_REG_7) },
3743 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3745 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3747 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3753 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3755 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3757 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3763 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3764 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3767 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3768 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3774 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3775 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3777 /* REG_VEX_0F38F3 */
3780 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3781 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3782 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3786 { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3787 { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3791 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3792 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3794 /* REG_XOP_TBM_01 */
3797 { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3798 { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3799 { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 },
3800 { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3801 { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 },
3802 { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 },
3803 { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3805 /* REG_XOP_TBM_02 */
3808 { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3813 { "blci", { { OP_LWP_E, 0 }, Ev }, 0 },
3815 #define NEED_REG_TABLE
3816 #include "i386-dis-evex.h"
3817 #undef NEED_REG_TABLE
3820 static const struct dis386 prefix_table[][4] = {
3823 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3824 { "pause", { XX }, 0 },
3825 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3826 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3829 /* PREFIX_MOD_0_0F01_REG_5 */
3832 { "rstorssp", { Mq }, PREFIX_OPCODE },
3835 /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3838 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3841 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3844 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3849 { "wbinvd", { XX }, 0 },
3850 { "wbnoinvd", { XX }, 0 },
3855 { "movups", { XM, EXx }, PREFIX_OPCODE },
3856 { "movss", { XM, EXd }, PREFIX_OPCODE },
3857 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3858 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3863 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3864 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3865 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3866 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3871 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3872 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3873 { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3874 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3879 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3880 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3881 { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3886 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3887 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3888 { "bndmov", { Gbnd, Ebnd }, 0 },
3889 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3894 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3895 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3896 { "bndmov", { EbndS, Gbnd }, 0 },
3897 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3902 { "nopQ", { Ev }, PREFIX_OPCODE },
3903 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3904 { "nopQ", { Ev }, PREFIX_OPCODE },
3905 { "nopQ", { Ev }, PREFIX_OPCODE },
3910 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3911 { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3912 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3913 { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3918 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3919 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3920 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3921 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3926 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3927 { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE },
3928 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3929 { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE },
3934 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3935 { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE },
3936 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3937 { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE },
3942 { "ucomiss",{ XM, EXd }, 0 },
3944 { "ucomisd",{ XM, EXq }, 0 },
3949 { "comiss", { XM, EXd }, 0 },
3951 { "comisd", { XM, EXq }, 0 },
3956 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3957 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3958 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3959 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3964 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3965 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3970 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3971 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3976 { "addps", { XM, EXx }, PREFIX_OPCODE },
3977 { "addss", { XM, EXd }, PREFIX_OPCODE },
3978 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3979 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3984 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3985 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3986 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3987 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3992 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3993 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3994 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3995 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
4000 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
4001 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
4002 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
4007 { "subps", { XM, EXx }, PREFIX_OPCODE },
4008 { "subss", { XM, EXd }, PREFIX_OPCODE },
4009 { "subpd", { XM, EXx }, PREFIX_OPCODE },
4010 { "subsd", { XM, EXq }, PREFIX_OPCODE },
4015 { "minps", { XM, EXx }, PREFIX_OPCODE },
4016 { "minss", { XM, EXd }, PREFIX_OPCODE },
4017 { "minpd", { XM, EXx }, PREFIX_OPCODE },
4018 { "minsd", { XM, EXq }, PREFIX_OPCODE },
4023 { "divps", { XM, EXx }, PREFIX_OPCODE },
4024 { "divss", { XM, EXd }, PREFIX_OPCODE },
4025 { "divpd", { XM, EXx }, PREFIX_OPCODE },
4026 { "divsd", { XM, EXq }, PREFIX_OPCODE },
4031 { "maxps", { XM, EXx }, PREFIX_OPCODE },
4032 { "maxss", { XM, EXd }, PREFIX_OPCODE },
4033 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
4034 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
4039 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
4041 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
4046 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
4048 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
4053 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
4055 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
4062 { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
4069 { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
4074 { "movq", { MX, EM }, PREFIX_OPCODE },
4075 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
4076 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4081 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4082 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4083 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4084 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4087 /* PREFIX_0F73_REG_3 */
4091 { "psrldq", { XS, Ib }, 0 },
4094 /* PREFIX_0F73_REG_7 */
4098 { "pslldq", { XS, Ib }, 0 },
4103 {"vmread", { Em, Gm }, 0 },
4105 {"extrq", { XS, Ib, Ib }, 0 },
4106 {"insertq", { XM, XS, Ib, Ib }, 0 },
4111 {"vmwrite", { Gm, Em }, 0 },
4113 {"extrq", { XM, XS }, 0 },
4114 {"insertq", { XM, XS }, 0 },
4121 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4122 { "haddps", { XM, EXx }, PREFIX_OPCODE },
4129 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4130 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4135 { "movK", { Edq, MX }, PREFIX_OPCODE },
4136 { "movq", { XM, EXq }, PREFIX_OPCODE },
4137 { "movK", { Edq, XM }, PREFIX_OPCODE },
4142 { "movq", { EMS, MX }, PREFIX_OPCODE },
4143 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4144 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4147 /* PREFIX_0FAE_REG_0 */
4150 { "rdfsbase", { Ev }, 0 },
4153 /* PREFIX_0FAE_REG_1 */
4156 { "rdgsbase", { Ev }, 0 },
4159 /* PREFIX_0FAE_REG_2 */
4162 { "wrfsbase", { Ev }, 0 },
4165 /* PREFIX_0FAE_REG_3 */
4168 { "wrgsbase", { Ev }, 0 },
4171 /* PREFIX_MOD_0_0FAE_REG_4 */
4173 { "xsave", { FXSAVE }, 0 },
4174 { "ptwrite%LQ", { Edq }, 0 },
4177 /* PREFIX_MOD_3_0FAE_REG_4 */
4180 { "ptwrite%LQ", { Edq }, 0 },
4183 /* PREFIX_MOD_0_0FAE_REG_5 */
4185 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
4188 /* PREFIX_MOD_3_0FAE_REG_5 */
4190 { "lfence", { Skip_MODRM }, 0 },
4191 { "incsspK", { Rdq }, PREFIX_OPCODE },
4194 /* PREFIX_0FAE_REG_6 */
4196 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
4197 { "clrssbsy", { Mq }, PREFIX_OPCODE },
4198 { "clwb", { Mb }, PREFIX_OPCODE },
4201 /* PREFIX_0FAE_REG_7 */
4203 { "clflush", { Mb }, 0 },
4205 { "clflushopt", { Mb }, 0 },
4211 { "popcntS", { Gv, Ev }, 0 },
4216 { "bsfS", { Gv, Ev }, 0 },
4217 { "tzcntS", { Gv, Ev }, 0 },
4218 { "bsfS", { Gv, Ev }, 0 },
4223 { "bsrS", { Gv, Ev }, 0 },
4224 { "lzcntS", { Gv, Ev }, 0 },
4225 { "bsrS", { Gv, Ev }, 0 },
4230 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
4231 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
4232 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
4233 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
4236 /* PREFIX_MOD_0_0FC3 */
4238 { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4241 /* PREFIX_MOD_0_0FC7_REG_6 */
4243 { "vmptrld",{ Mq }, 0 },
4244 { "vmxon", { Mq }, 0 },
4245 { "vmclear",{ Mq }, 0 },
4248 /* PREFIX_MOD_3_0FC7_REG_6 */
4250 { "rdrand", { Ev }, 0 },
4252 { "rdrand", { Ev }, 0 }
4255 /* PREFIX_MOD_3_0FC7_REG_7 */
4257 { "rdseed", { Ev }, 0 },
4258 { "rdpid", { Em }, 0 },
4259 { "rdseed", { Ev }, 0 },
4266 { "addsubpd", { XM, EXx }, 0 },
4267 { "addsubps", { XM, EXx }, 0 },
4273 { "movq2dq",{ XM, MS }, 0 },
4274 { "movq", { EXqS, XM }, 0 },
4275 { "movdq2q",{ MX, XS }, 0 },
4281 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4282 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4283 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4288 { "movntq", { Mq, MX }, PREFIX_OPCODE },
4290 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4298 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4303 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4305 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4312 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4319 { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4326 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4333 { "ptest", { XM, EXx }, PREFIX_OPCODE },
4340 { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4347 { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4354 { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4361 { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4368 { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4375 { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4382 { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4389 { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4396 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4403 { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4410 { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4417 { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4424 { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4431 { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4438 { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4445 { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4452 { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4459 { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4466 { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4473 { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4480 { "pminud", { XM, EXx }, PREFIX_OPCODE },
4487 { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4494 { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4501 { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4508 { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4515 { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4522 { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4529 { "invept", { Gm, Mo }, PREFIX_OPCODE },
4536 { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4543 { "invpcid", { Gm, M }, PREFIX_OPCODE },
4548 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4553 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4558 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4563 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4568 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4573 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4580 { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4587 { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4594 { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4601 { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4608 { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4615 { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4620 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4622 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4623 { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4628 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4630 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4631 { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4638 { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4643 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4644 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
4645 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
4653 { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4660 { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4667 { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4674 { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4681 { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4688 { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4695 { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4702 { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4709 { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4716 { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4723 { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4730 { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4737 { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4744 { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4751 { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE },
4758 { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE },
4765 { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4772 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4779 { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4786 { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4793 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4800 { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4805 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4812 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4819 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4826 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4829 /* PREFIX_VEX_0F10 */
4831 { VEX_W_TABLE (VEX_W_0F10_P_0) },
4832 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4833 { VEX_W_TABLE (VEX_W_0F10_P_2) },
4834 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4837 /* PREFIX_VEX_0F11 */
4839 { VEX_W_TABLE (VEX_W_0F11_P_0) },
4840 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4841 { VEX_W_TABLE (VEX_W_0F11_P_2) },
4842 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4845 /* PREFIX_VEX_0F12 */
4847 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4848 { VEX_W_TABLE (VEX_W_0F12_P_1) },
4849 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4850 { VEX_W_TABLE (VEX_W_0F12_P_3) },
4853 /* PREFIX_VEX_0F16 */
4855 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4856 { VEX_W_TABLE (VEX_W_0F16_P_1) },
4857 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4860 /* PREFIX_VEX_0F2A */
4863 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4865 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4868 /* PREFIX_VEX_0F2C */
4871 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4873 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4876 /* PREFIX_VEX_0F2D */
4879 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4881 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4884 /* PREFIX_VEX_0F2E */
4886 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4888 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4891 /* PREFIX_VEX_0F2F */
4893 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4895 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4898 /* PREFIX_VEX_0F41 */
4900 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4902 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4905 /* PREFIX_VEX_0F42 */
4907 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4909 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4912 /* PREFIX_VEX_0F44 */
4914 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4916 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4919 /* PREFIX_VEX_0F45 */
4921 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4923 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4926 /* PREFIX_VEX_0F46 */
4928 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4930 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4933 /* PREFIX_VEX_0F47 */
4935 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4937 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4940 /* PREFIX_VEX_0F4A */
4942 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4944 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4947 /* PREFIX_VEX_0F4B */
4949 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4951 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4954 /* PREFIX_VEX_0F51 */
4956 { VEX_W_TABLE (VEX_W_0F51_P_0) },
4957 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4958 { VEX_W_TABLE (VEX_W_0F51_P_2) },
4959 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4962 /* PREFIX_VEX_0F52 */
4964 { VEX_W_TABLE (VEX_W_0F52_P_0) },
4965 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4968 /* PREFIX_VEX_0F53 */
4970 { VEX_W_TABLE (VEX_W_0F53_P_0) },
4971 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4974 /* PREFIX_VEX_0F58 */
4976 { VEX_W_TABLE (VEX_W_0F58_P_0) },
4977 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4978 { VEX_W_TABLE (VEX_W_0F58_P_2) },
4979 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4982 /* PREFIX_VEX_0F59 */
4984 { VEX_W_TABLE (VEX_W_0F59_P_0) },
4985 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4986 { VEX_W_TABLE (VEX_W_0F59_P_2) },
4987 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4990 /* PREFIX_VEX_0F5A */
4992 { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4993 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4994 { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4995 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4998 /* PREFIX_VEX_0F5B */
5000 { VEX_W_TABLE (VEX_W_0F5B_P_0) },
5001 { VEX_W_TABLE (VEX_W_0F5B_P_1) },
5002 { VEX_W_TABLE (VEX_W_0F5B_P_2) },
5005 /* PREFIX_VEX_0F5C */
5007 { VEX_W_TABLE (VEX_W_0F5C_P_0) },
5008 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
5009 { VEX_W_TABLE (VEX_W_0F5C_P_2) },
5010 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
5013 /* PREFIX_VEX_0F5D */
5015 { VEX_W_TABLE (VEX_W_0F5D_P_0) },
5016 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
5017 { VEX_W_TABLE (VEX_W_0F5D_P_2) },
5018 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
5021 /* PREFIX_VEX_0F5E */
5023 { VEX_W_TABLE (VEX_W_0F5E_P_0) },
5024 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
5025 { VEX_W_TABLE (VEX_W_0F5E_P_2) },
5026 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
5029 /* PREFIX_VEX_0F5F */
5031 { VEX_W_TABLE (VEX_W_0F5F_P_0) },
5032 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
5033 { VEX_W_TABLE (VEX_W_0F5F_P_2) },
5034 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
5037 /* PREFIX_VEX_0F60 */
5041 { VEX_W_TABLE (VEX_W_0F60_P_2) },
5044 /* PREFIX_VEX_0F61 */
5048 { VEX_W_TABLE (VEX_W_0F61_P_2) },
5051 /* PREFIX_VEX_0F62 */
5055 { VEX_W_TABLE (VEX_W_0F62_P_2) },
5058 /* PREFIX_VEX_0F63 */
5062 { VEX_W_TABLE (VEX_W_0F63_P_2) },
5065 /* PREFIX_VEX_0F64 */
5069 { VEX_W_TABLE (VEX_W_0F64_P_2) },
5072 /* PREFIX_VEX_0F65 */
5076 { VEX_W_TABLE (VEX_W_0F65_P_2) },
5079 /* PREFIX_VEX_0F66 */
5083 { VEX_W_TABLE (VEX_W_0F66_P_2) },
5086 /* PREFIX_VEX_0F67 */
5090 { VEX_W_TABLE (VEX_W_0F67_P_2) },
5093 /* PREFIX_VEX_0F68 */
5097 { VEX_W_TABLE (VEX_W_0F68_P_2) },
5100 /* PREFIX_VEX_0F69 */
5104 { VEX_W_TABLE (VEX_W_0F69_P_2) },
5107 /* PREFIX_VEX_0F6A */
5111 { VEX_W_TABLE (VEX_W_0F6A_P_2) },
5114 /* PREFIX_VEX_0F6B */
5118 { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5121 /* PREFIX_VEX_0F6C */
5125 { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5128 /* PREFIX_VEX_0F6D */
5132 { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5135 /* PREFIX_VEX_0F6E */
5139 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5142 /* PREFIX_VEX_0F6F */
5145 { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5146 { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5149 /* PREFIX_VEX_0F70 */
5152 { VEX_W_TABLE (VEX_W_0F70_P_1) },
5153 { VEX_W_TABLE (VEX_W_0F70_P_2) },
5154 { VEX_W_TABLE (VEX_W_0F70_P_3) },
5157 /* PREFIX_VEX_0F71_REG_2 */
5161 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5164 /* PREFIX_VEX_0F71_REG_4 */
5168 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5171 /* PREFIX_VEX_0F71_REG_6 */
5175 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5178 /* PREFIX_VEX_0F72_REG_2 */
5182 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5185 /* PREFIX_VEX_0F72_REG_4 */
5189 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5192 /* PREFIX_VEX_0F72_REG_6 */
5196 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5199 /* PREFIX_VEX_0F73_REG_2 */
5203 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5206 /* PREFIX_VEX_0F73_REG_3 */
5210 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5213 /* PREFIX_VEX_0F73_REG_6 */
5217 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5220 /* PREFIX_VEX_0F73_REG_7 */
5224 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5227 /* PREFIX_VEX_0F74 */
5231 { VEX_W_TABLE (VEX_W_0F74_P_2) },
5234 /* PREFIX_VEX_0F75 */
5238 { VEX_W_TABLE (VEX_W_0F75_P_2) },
5241 /* PREFIX_VEX_0F76 */
5245 { VEX_W_TABLE (VEX_W_0F76_P_2) },
5248 /* PREFIX_VEX_0F77 */
5250 { VEX_W_TABLE (VEX_W_0F77_P_0) },
5253 /* PREFIX_VEX_0F7C */
5257 { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5258 { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5261 /* PREFIX_VEX_0F7D */
5265 { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5266 { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5269 /* PREFIX_VEX_0F7E */
5272 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5273 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5276 /* PREFIX_VEX_0F7F */
5279 { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5280 { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5283 /* PREFIX_VEX_0F90 */
5285 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5287 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5290 /* PREFIX_VEX_0F91 */
5292 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5294 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5297 /* PREFIX_VEX_0F92 */
5299 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5301 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5302 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5305 /* PREFIX_VEX_0F93 */
5307 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5309 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5310 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5313 /* PREFIX_VEX_0F98 */
5315 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5317 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5320 /* PREFIX_VEX_0F99 */
5322 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5324 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5327 /* PREFIX_VEX_0FC2 */
5329 { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5330 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5331 { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5332 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5335 /* PREFIX_VEX_0FC4 */
5339 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5342 /* PREFIX_VEX_0FC5 */
5346 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5349 /* PREFIX_VEX_0FD0 */
5353 { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5354 { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5357 /* PREFIX_VEX_0FD1 */
5361 { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5364 /* PREFIX_VEX_0FD2 */
5368 { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5371 /* PREFIX_VEX_0FD3 */
5375 { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5378 /* PREFIX_VEX_0FD4 */
5382 { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5385 /* PREFIX_VEX_0FD5 */
5389 { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5392 /* PREFIX_VEX_0FD6 */
5396 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5399 /* PREFIX_VEX_0FD7 */
5403 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5406 /* PREFIX_VEX_0FD8 */
5410 { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5413 /* PREFIX_VEX_0FD9 */
5417 { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5420 /* PREFIX_VEX_0FDA */
5424 { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5427 /* PREFIX_VEX_0FDB */
5431 { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5434 /* PREFIX_VEX_0FDC */
5438 { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5441 /* PREFIX_VEX_0FDD */
5445 { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5448 /* PREFIX_VEX_0FDE */
5452 { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5455 /* PREFIX_VEX_0FDF */
5459 { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5462 /* PREFIX_VEX_0FE0 */
5466 { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5469 /* PREFIX_VEX_0FE1 */
5473 { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5476 /* PREFIX_VEX_0FE2 */
5480 { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5483 /* PREFIX_VEX_0FE3 */
5487 { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5490 /* PREFIX_VEX_0FE4 */
5494 { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5497 /* PREFIX_VEX_0FE5 */
5501 { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5504 /* PREFIX_VEX_0FE6 */
5507 { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5508 { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5509 { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5512 /* PREFIX_VEX_0FE7 */
5516 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5519 /* PREFIX_VEX_0FE8 */
5523 { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5526 /* PREFIX_VEX_0FE9 */
5530 { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5533 /* PREFIX_VEX_0FEA */
5537 { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5540 /* PREFIX_VEX_0FEB */
5544 { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5547 /* PREFIX_VEX_0FEC */
5551 { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5554 /* PREFIX_VEX_0FED */
5558 { VEX_W_TABLE (VEX_W_0FED_P_2) },
5561 /* PREFIX_VEX_0FEE */
5565 { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5568 /* PREFIX_VEX_0FEF */
5572 { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5575 /* PREFIX_VEX_0FF0 */
5580 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5583 /* PREFIX_VEX_0FF1 */
5587 { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5590 /* PREFIX_VEX_0FF2 */
5594 { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5597 /* PREFIX_VEX_0FF3 */
5601 { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5604 /* PREFIX_VEX_0FF4 */
5608 { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5611 /* PREFIX_VEX_0FF5 */
5615 { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5618 /* PREFIX_VEX_0FF6 */
5622 { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5625 /* PREFIX_VEX_0FF7 */
5629 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5632 /* PREFIX_VEX_0FF8 */
5636 { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5639 /* PREFIX_VEX_0FF9 */
5643 { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5646 /* PREFIX_VEX_0FFA */
5650 { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5653 /* PREFIX_VEX_0FFB */
5657 { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5660 /* PREFIX_VEX_0FFC */
5664 { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5667 /* PREFIX_VEX_0FFD */
5671 { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5674 /* PREFIX_VEX_0FFE */
5678 { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5681 /* PREFIX_VEX_0F3800 */
5685 { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5688 /* PREFIX_VEX_0F3801 */
5692 { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5695 /* PREFIX_VEX_0F3802 */
5699 { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5702 /* PREFIX_VEX_0F3803 */
5706 { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5709 /* PREFIX_VEX_0F3804 */
5713 { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5716 /* PREFIX_VEX_0F3805 */
5720 { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5723 /* PREFIX_VEX_0F3806 */
5727 { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5730 /* PREFIX_VEX_0F3807 */
5734 { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5737 /* PREFIX_VEX_0F3808 */
5741 { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5744 /* PREFIX_VEX_0F3809 */
5748 { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5751 /* PREFIX_VEX_0F380A */
5755 { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5758 /* PREFIX_VEX_0F380B */
5762 { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5765 /* PREFIX_VEX_0F380C */
5769 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5772 /* PREFIX_VEX_0F380D */
5776 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5779 /* PREFIX_VEX_0F380E */
5783 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5786 /* PREFIX_VEX_0F380F */
5790 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5793 /* PREFIX_VEX_0F3813 */
5797 { "vcvtph2ps", { XM, EXxmmq }, 0 },
5800 /* PREFIX_VEX_0F3816 */
5804 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5807 /* PREFIX_VEX_0F3817 */
5811 { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5814 /* PREFIX_VEX_0F3818 */
5818 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5821 /* PREFIX_VEX_0F3819 */
5825 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5828 /* PREFIX_VEX_0F381A */
5832 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5835 /* PREFIX_VEX_0F381C */
5839 { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5842 /* PREFIX_VEX_0F381D */
5846 { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5849 /* PREFIX_VEX_0F381E */
5853 { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5856 /* PREFIX_VEX_0F3820 */
5860 { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5863 /* PREFIX_VEX_0F3821 */
5867 { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5870 /* PREFIX_VEX_0F3822 */
5874 { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5877 /* PREFIX_VEX_0F3823 */
5881 { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5884 /* PREFIX_VEX_0F3824 */
5888 { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5891 /* PREFIX_VEX_0F3825 */
5895 { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5898 /* PREFIX_VEX_0F3828 */
5902 { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5905 /* PREFIX_VEX_0F3829 */
5909 { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5912 /* PREFIX_VEX_0F382A */
5916 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5919 /* PREFIX_VEX_0F382B */
5923 { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5926 /* PREFIX_VEX_0F382C */
5930 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5933 /* PREFIX_VEX_0F382D */
5937 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5940 /* PREFIX_VEX_0F382E */
5944 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5947 /* PREFIX_VEX_0F382F */
5951 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5954 /* PREFIX_VEX_0F3830 */
5958 { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5961 /* PREFIX_VEX_0F3831 */
5965 { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5968 /* PREFIX_VEX_0F3832 */
5972 { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5975 /* PREFIX_VEX_0F3833 */
5979 { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5982 /* PREFIX_VEX_0F3834 */
5986 { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5989 /* PREFIX_VEX_0F3835 */
5993 { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5996 /* PREFIX_VEX_0F3836 */
6000 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
6003 /* PREFIX_VEX_0F3837 */
6007 { VEX_W_TABLE (VEX_W_0F3837_P_2) },
6010 /* PREFIX_VEX_0F3838 */
6014 { VEX_W_TABLE (VEX_W_0F3838_P_2) },
6017 /* PREFIX_VEX_0F3839 */
6021 { VEX_W_TABLE (VEX_W_0F3839_P_2) },
6024 /* PREFIX_VEX_0F383A */
6028 { VEX_W_TABLE (VEX_W_0F383A_P_2) },
6031 /* PREFIX_VEX_0F383B */
6035 { VEX_W_TABLE (VEX_W_0F383B_P_2) },
6038 /* PREFIX_VEX_0F383C */
6042 { VEX_W_TABLE (VEX_W_0F383C_P_2) },
6045 /* PREFIX_VEX_0F383D */
6049 { VEX_W_TABLE (VEX_W_0F383D_P_2) },
6052 /* PREFIX_VEX_0F383E */
6056 { VEX_W_TABLE (VEX_W_0F383E_P_2) },
6059 /* PREFIX_VEX_0F383F */
6063 { VEX_W_TABLE (VEX_W_0F383F_P_2) },
6066 /* PREFIX_VEX_0F3840 */
6070 { VEX_W_TABLE (VEX_W_0F3840_P_2) },
6073 /* PREFIX_VEX_0F3841 */
6077 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
6080 /* PREFIX_VEX_0F3845 */
6084 { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
6087 /* PREFIX_VEX_0F3846 */
6091 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
6094 /* PREFIX_VEX_0F3847 */
6098 { "vpsllv%LW", { XM, Vex, EXx }, 0 },
6101 /* PREFIX_VEX_0F3858 */
6105 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
6108 /* PREFIX_VEX_0F3859 */
6112 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
6115 /* PREFIX_VEX_0F385A */
6119 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6122 /* PREFIX_VEX_0F3878 */
6126 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6129 /* PREFIX_VEX_0F3879 */
6133 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6136 /* PREFIX_VEX_0F388C */
6140 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6143 /* PREFIX_VEX_0F388E */
6147 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6150 /* PREFIX_VEX_0F3890 */
6154 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6157 /* PREFIX_VEX_0F3891 */
6161 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6164 /* PREFIX_VEX_0F3892 */
6168 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6171 /* PREFIX_VEX_0F3893 */
6175 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6178 /* PREFIX_VEX_0F3896 */
6182 { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6185 /* PREFIX_VEX_0F3897 */
6189 { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6192 /* PREFIX_VEX_0F3898 */
6196 { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6199 /* PREFIX_VEX_0F3899 */
6203 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6206 /* PREFIX_VEX_0F389A */
6210 { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6213 /* PREFIX_VEX_0F389B */
6217 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6220 /* PREFIX_VEX_0F389C */
6224 { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6227 /* PREFIX_VEX_0F389D */
6231 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6234 /* PREFIX_VEX_0F389E */
6238 { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6241 /* PREFIX_VEX_0F389F */
6245 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6248 /* PREFIX_VEX_0F38A6 */
6252 { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6256 /* PREFIX_VEX_0F38A7 */
6260 { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6263 /* PREFIX_VEX_0F38A8 */
6267 { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6270 /* PREFIX_VEX_0F38A9 */
6274 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6277 /* PREFIX_VEX_0F38AA */
6281 { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6284 /* PREFIX_VEX_0F38AB */
6288 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6291 /* PREFIX_VEX_0F38AC */
6295 { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6298 /* PREFIX_VEX_0F38AD */
6302 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6305 /* PREFIX_VEX_0F38AE */
6309 { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6312 /* PREFIX_VEX_0F38AF */
6316 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6319 /* PREFIX_VEX_0F38B6 */
6323 { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6326 /* PREFIX_VEX_0F38B7 */
6330 { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6333 /* PREFIX_VEX_0F38B8 */
6337 { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6340 /* PREFIX_VEX_0F38B9 */
6344 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6347 /* PREFIX_VEX_0F38BA */
6351 { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6354 /* PREFIX_VEX_0F38BB */
6358 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6361 /* PREFIX_VEX_0F38BC */
6365 { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6368 /* PREFIX_VEX_0F38BD */
6372 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6375 /* PREFIX_VEX_0F38BE */
6379 { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6382 /* PREFIX_VEX_0F38BF */
6386 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6389 /* PREFIX_VEX_0F38CF */
6393 { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6396 /* PREFIX_VEX_0F38DB */
6400 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6403 /* PREFIX_VEX_0F38DC */
6407 { "vaesenc", { XM, Vex, EXx }, 0 },
6410 /* PREFIX_VEX_0F38DD */
6414 { "vaesenclast", { XM, Vex, EXx }, 0 },
6417 /* PREFIX_VEX_0F38DE */
6421 { "vaesdec", { XM, Vex, EXx }, 0 },
6424 /* PREFIX_VEX_0F38DF */
6428 { "vaesdeclast", { XM, Vex, EXx }, 0 },
6431 /* PREFIX_VEX_0F38F2 */
6433 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6436 /* PREFIX_VEX_0F38F3_REG_1 */
6438 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6441 /* PREFIX_VEX_0F38F3_REG_2 */
6443 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6446 /* PREFIX_VEX_0F38F3_REG_3 */
6448 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6451 /* PREFIX_VEX_0F38F5 */
6453 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6454 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6456 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6459 /* PREFIX_VEX_0F38F6 */
6464 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6467 /* PREFIX_VEX_0F38F7 */
6469 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6470 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6471 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6472 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6475 /* PREFIX_VEX_0F3A00 */
6479 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6482 /* PREFIX_VEX_0F3A01 */
6486 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6489 /* PREFIX_VEX_0F3A02 */
6493 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6496 /* PREFIX_VEX_0F3A04 */
6500 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6503 /* PREFIX_VEX_0F3A05 */
6507 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6510 /* PREFIX_VEX_0F3A06 */
6514 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6517 /* PREFIX_VEX_0F3A08 */
6521 { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6524 /* PREFIX_VEX_0F3A09 */
6528 { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6531 /* PREFIX_VEX_0F3A0A */
6535 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6538 /* PREFIX_VEX_0F3A0B */
6542 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6545 /* PREFIX_VEX_0F3A0C */
6549 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6552 /* PREFIX_VEX_0F3A0D */
6556 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6559 /* PREFIX_VEX_0F3A0E */
6563 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6566 /* PREFIX_VEX_0F3A0F */
6570 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6573 /* PREFIX_VEX_0F3A14 */
6577 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6580 /* PREFIX_VEX_0F3A15 */
6584 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6587 /* PREFIX_VEX_0F3A16 */
6591 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6594 /* PREFIX_VEX_0F3A17 */
6598 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6601 /* PREFIX_VEX_0F3A18 */
6605 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6608 /* PREFIX_VEX_0F3A19 */
6612 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6615 /* PREFIX_VEX_0F3A1D */
6619 { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6622 /* PREFIX_VEX_0F3A20 */
6626 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6629 /* PREFIX_VEX_0F3A21 */
6633 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6636 /* PREFIX_VEX_0F3A22 */
6640 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6643 /* PREFIX_VEX_0F3A30 */
6647 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6650 /* PREFIX_VEX_0F3A31 */
6654 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6657 /* PREFIX_VEX_0F3A32 */
6661 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6664 /* PREFIX_VEX_0F3A33 */
6668 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6671 /* PREFIX_VEX_0F3A38 */
6675 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6678 /* PREFIX_VEX_0F3A39 */
6682 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6685 /* PREFIX_VEX_0F3A40 */
6689 { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6692 /* PREFIX_VEX_0F3A41 */
6696 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6699 /* PREFIX_VEX_0F3A42 */
6703 { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6706 /* PREFIX_VEX_0F3A44 */
6710 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 },
6713 /* PREFIX_VEX_0F3A46 */
6717 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6720 /* PREFIX_VEX_0F3A48 */
6724 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6727 /* PREFIX_VEX_0F3A49 */
6731 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6734 /* PREFIX_VEX_0F3A4A */
6738 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6741 /* PREFIX_VEX_0F3A4B */
6745 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6748 /* PREFIX_VEX_0F3A4C */
6752 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6755 /* PREFIX_VEX_0F3A5C */
6759 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6762 /* PREFIX_VEX_0F3A5D */
6766 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6769 /* PREFIX_VEX_0F3A5E */
6773 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6776 /* PREFIX_VEX_0F3A5F */
6780 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6783 /* PREFIX_VEX_0F3A60 */
6787 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6791 /* PREFIX_VEX_0F3A61 */
6795 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6798 /* PREFIX_VEX_0F3A62 */
6802 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6805 /* PREFIX_VEX_0F3A63 */
6809 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6812 /* PREFIX_VEX_0F3A68 */
6816 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6819 /* PREFIX_VEX_0F3A69 */
6823 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6826 /* PREFIX_VEX_0F3A6A */
6830 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6833 /* PREFIX_VEX_0F3A6B */
6837 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6840 /* PREFIX_VEX_0F3A6C */
6844 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6847 /* PREFIX_VEX_0F3A6D */
6851 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6854 /* PREFIX_VEX_0F3A6E */
6858 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6861 /* PREFIX_VEX_0F3A6F */
6865 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6868 /* PREFIX_VEX_0F3A78 */
6872 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6875 /* PREFIX_VEX_0F3A79 */
6879 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6882 /* PREFIX_VEX_0F3A7A */
6886 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6889 /* PREFIX_VEX_0F3A7B */
6893 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6896 /* PREFIX_VEX_0F3A7C */
6900 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6904 /* PREFIX_VEX_0F3A7D */
6908 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6911 /* PREFIX_VEX_0F3A7E */
6915 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6918 /* PREFIX_VEX_0F3A7F */
6922 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6925 /* PREFIX_VEX_0F3ACE */
6929 { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6932 /* PREFIX_VEX_0F3ACF */
6936 { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6939 /* PREFIX_VEX_0F3ADF */
6943 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6946 /* PREFIX_VEX_0F3AF0 */
6951 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6954 #define NEED_PREFIX_TABLE
6955 #include "i386-dis-evex.h"
6956 #undef NEED_PREFIX_TABLE
6959 static const struct dis386 x86_64_table[][2] = {
6962 { "pushP", { es }, 0 },
6967 { "popP", { es }, 0 },
6972 { "pushP", { cs }, 0 },
6977 { "pushP", { ss }, 0 },
6982 { "popP", { ss }, 0 },
6987 { "pushP", { ds }, 0 },
6992 { "popP", { ds }, 0 },
6997 { "daa", { XX }, 0 },
7002 { "das", { XX }, 0 },
7007 { "aaa", { XX }, 0 },
7012 { "aas", { XX }, 0 },
7017 { "pushaP", { XX }, 0 },
7022 { "popaP", { XX }, 0 },
7027 { MOD_TABLE (MOD_62_32BIT) },
7028 { EVEX_TABLE (EVEX_0F) },
7033 { "arpl", { Ew, Gw }, 0 },
7034 { "movs{lq|xd}", { Gv, Ed }, 0 },
7039 { "ins{R|}", { Yzr, indirDX }, 0 },
7040 { "ins{G|}", { Yzr, indirDX }, 0 },
7045 { "outs{R|}", { indirDXr, Xz }, 0 },
7046 { "outs{G|}", { indirDXr, Xz }, 0 },
7051 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
7052 { REG_TABLE (REG_80) },
7057 { "Jcall{T|}", { Ap }, 0 },
7062 { MOD_TABLE (MOD_C4_32BIT) },
7063 { VEX_C4_TABLE (VEX_0F) },
7068 { MOD_TABLE (MOD_C5_32BIT) },
7069 { VEX_C5_TABLE (VEX_0F) },
7074 { "into", { XX }, 0 },
7079 { "aam", { Ib }, 0 },
7084 { "aad", { Ib }, 0 },
7089 { "callP", { Jv, BND }, 0 },
7090 { "call@", { Jv, BND }, 0 }
7095 { "jmpP", { Jv, BND }, 0 },
7096 { "jmp@", { Jv, BND }, 0 }
7101 { "Jjmp{T|}", { Ap }, 0 },
7104 /* X86_64_0F01_REG_0 */
7106 { "sgdt{Q|IQ}", { M }, 0 },
7107 { "sgdt", { M }, 0 },
7110 /* X86_64_0F01_REG_1 */
7112 { "sidt{Q|IQ}", { M }, 0 },
7113 { "sidt", { M }, 0 },
7116 /* X86_64_0F01_REG_2 */
7118 { "lgdt{Q|Q}", { M }, 0 },
7119 { "lgdt", { M }, 0 },
7122 /* X86_64_0F01_REG_3 */
7124 { "lidt{Q|Q}", { M }, 0 },
7125 { "lidt", { M }, 0 },
7129 static const struct dis386 three_byte_table[][256] = {
7131 /* THREE_BYTE_0F38 */
7134 { "pshufb", { MX, EM }, PREFIX_OPCODE },
7135 { "phaddw", { MX, EM }, PREFIX_OPCODE },
7136 { "phaddd", { MX, EM }, PREFIX_OPCODE },
7137 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
7138 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
7139 { "phsubw", { MX, EM }, PREFIX_OPCODE },
7140 { "phsubd", { MX, EM }, PREFIX_OPCODE },
7141 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
7143 { "psignb", { MX, EM }, PREFIX_OPCODE },
7144 { "psignw", { MX, EM }, PREFIX_OPCODE },
7145 { "psignd", { MX, EM }, PREFIX_OPCODE },
7146 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
7152 { PREFIX_TABLE (PREFIX_0F3810) },
7156 { PREFIX_TABLE (PREFIX_0F3814) },
7157 { PREFIX_TABLE (PREFIX_0F3815) },
7159 { PREFIX_TABLE (PREFIX_0F3817) },
7165 { "pabsb", { MX, EM }, PREFIX_OPCODE },
7166 { "pabsw", { MX, EM }, PREFIX_OPCODE },
7167 { "pabsd", { MX, EM }, PREFIX_OPCODE },
7170 { PREFIX_TABLE (PREFIX_0F3820) },
7171 { PREFIX_TABLE (PREFIX_0F3821) },
7172 { PREFIX_TABLE (PREFIX_0F3822) },
7173 { PREFIX_TABLE (PREFIX_0F3823) },
7174 { PREFIX_TABLE (PREFIX_0F3824) },
7175 { PREFIX_TABLE (PREFIX_0F3825) },
7179 { PREFIX_TABLE (PREFIX_0F3828) },
7180 { PREFIX_TABLE (PREFIX_0F3829) },
7181 { PREFIX_TABLE (PREFIX_0F382A) },
7182 { PREFIX_TABLE (PREFIX_0F382B) },
7188 { PREFIX_TABLE (PREFIX_0F3830) },
7189 { PREFIX_TABLE (PREFIX_0F3831) },
7190 { PREFIX_TABLE (PREFIX_0F3832) },
7191 { PREFIX_TABLE (PREFIX_0F3833) },
7192 { PREFIX_TABLE (PREFIX_0F3834) },
7193 { PREFIX_TABLE (PREFIX_0F3835) },
7195 { PREFIX_TABLE (PREFIX_0F3837) },
7197 { PREFIX_TABLE (PREFIX_0F3838) },
7198 { PREFIX_TABLE (PREFIX_0F3839) },
7199 { PREFIX_TABLE (PREFIX_0F383A) },
7200 { PREFIX_TABLE (PREFIX_0F383B) },
7201 { PREFIX_TABLE (PREFIX_0F383C) },
7202 { PREFIX_TABLE (PREFIX_0F383D) },
7203 { PREFIX_TABLE (PREFIX_0F383E) },
7204 { PREFIX_TABLE (PREFIX_0F383F) },
7206 { PREFIX_TABLE (PREFIX_0F3840) },
7207 { PREFIX_TABLE (PREFIX_0F3841) },
7278 { PREFIX_TABLE (PREFIX_0F3880) },
7279 { PREFIX_TABLE (PREFIX_0F3881) },
7280 { PREFIX_TABLE (PREFIX_0F3882) },
7359 { PREFIX_TABLE (PREFIX_0F38C8) },
7360 { PREFIX_TABLE (PREFIX_0F38C9) },
7361 { PREFIX_TABLE (PREFIX_0F38CA) },
7362 { PREFIX_TABLE (PREFIX_0F38CB) },
7363 { PREFIX_TABLE (PREFIX_0F38CC) },
7364 { PREFIX_TABLE (PREFIX_0F38CD) },
7366 { PREFIX_TABLE (PREFIX_0F38CF) },
7380 { PREFIX_TABLE (PREFIX_0F38DB) },
7381 { PREFIX_TABLE (PREFIX_0F38DC) },
7382 { PREFIX_TABLE (PREFIX_0F38DD) },
7383 { PREFIX_TABLE (PREFIX_0F38DE) },
7384 { PREFIX_TABLE (PREFIX_0F38DF) },
7404 { PREFIX_TABLE (PREFIX_0F38F0) },
7405 { PREFIX_TABLE (PREFIX_0F38F1) },
7409 { PREFIX_TABLE (PREFIX_0F38F5) },
7410 { PREFIX_TABLE (PREFIX_0F38F6) },
7422 /* THREE_BYTE_0F3A */
7434 { PREFIX_TABLE (PREFIX_0F3A08) },
7435 { PREFIX_TABLE (PREFIX_0F3A09) },
7436 { PREFIX_TABLE (PREFIX_0F3A0A) },
7437 { PREFIX_TABLE (PREFIX_0F3A0B) },
7438 { PREFIX_TABLE (PREFIX_0F3A0C) },
7439 { PREFIX_TABLE (PREFIX_0F3A0D) },
7440 { PREFIX_TABLE (PREFIX_0F3A0E) },
7441 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
7447 { PREFIX_TABLE (PREFIX_0F3A14) },
7448 { PREFIX_TABLE (PREFIX_0F3A15) },
7449 { PREFIX_TABLE (PREFIX_0F3A16) },
7450 { PREFIX_TABLE (PREFIX_0F3A17) },
7461 { PREFIX_TABLE (PREFIX_0F3A20) },
7462 { PREFIX_TABLE (PREFIX_0F3A21) },
7463 { PREFIX_TABLE (PREFIX_0F3A22) },
7497 { PREFIX_TABLE (PREFIX_0F3A40) },
7498 { PREFIX_TABLE (PREFIX_0F3A41) },
7499 { PREFIX_TABLE (PREFIX_0F3A42) },
7501 { PREFIX_TABLE (PREFIX_0F3A44) },
7533 { PREFIX_TABLE (PREFIX_0F3A60) },
7534 { PREFIX_TABLE (PREFIX_0F3A61) },
7535 { PREFIX_TABLE (PREFIX_0F3A62) },
7536 { PREFIX_TABLE (PREFIX_0F3A63) },
7654 { PREFIX_TABLE (PREFIX_0F3ACC) },
7656 { PREFIX_TABLE (PREFIX_0F3ACE) },
7657 { PREFIX_TABLE (PREFIX_0F3ACF) },
7675 { PREFIX_TABLE (PREFIX_0F3ADF) },
7715 static const struct dis386 xop_table[][256] = {
7868 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7869 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7870 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7878 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7879 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7886 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7887 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7888 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7896 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7897 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7901 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7902 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7905 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7923 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7935 { "vprotb", { XM, Vex_2src_1, Ib }, 0 },
7936 { "vprotw", { XM, Vex_2src_1, Ib }, 0 },
7937 { "vprotd", { XM, Vex_2src_1, Ib }, 0 },
7938 { "vprotq", { XM, Vex_2src_1, Ib }, 0 },
7948 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7949 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7950 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7951 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7984 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7985 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7986 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7987 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8011 { REG_TABLE (REG_XOP_TBM_01) },
8012 { REG_TABLE (REG_XOP_TBM_02) },
8030 { REG_TABLE (REG_XOP_LWPCB) },
8154 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8155 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8156 { "vfrczss", { XM, EXd }, 0 },
8157 { "vfrczsd", { XM, EXq }, 0 },
8172 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8173 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8174 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8175 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8176 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8177 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8178 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8179 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8181 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8182 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8183 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8184 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8227 { "vphaddbw", { XM, EXxmm }, 0 },
8228 { "vphaddbd", { XM, EXxmm }, 0 },
8229 { "vphaddbq", { XM, EXxmm }, 0 },
8232 { "vphaddwd", { XM, EXxmm }, 0 },
8233 { "vphaddwq", { XM, EXxmm }, 0 },
8238 { "vphadddq", { XM, EXxmm }, 0 },
8245 { "vphaddubw", { XM, EXxmm }, 0 },
8246 { "vphaddubd", { XM, EXxmm }, 0 },
8247 { "vphaddubq", { XM, EXxmm }, 0 },
8250 { "vphadduwd", { XM, EXxmm }, 0 },
8251 { "vphadduwq", { XM, EXxmm }, 0 },
8256 { "vphaddudq", { XM, EXxmm }, 0 },
8263 { "vphsubbw", { XM, EXxmm }, 0 },
8264 { "vphsubwd", { XM, EXxmm }, 0 },
8265 { "vphsubdq", { XM, EXxmm }, 0 },
8319 { "bextr", { Gv, Ev, Iq }, 0 },
8321 { REG_TABLE (REG_XOP_LWP) },
8591 static const struct dis386 vex_table[][256] = {
8613 { PREFIX_TABLE (PREFIX_VEX_0F10) },
8614 { PREFIX_TABLE (PREFIX_VEX_0F11) },
8615 { PREFIX_TABLE (PREFIX_VEX_0F12) },
8616 { MOD_TABLE (MOD_VEX_0F13) },
8617 { VEX_W_TABLE (VEX_W_0F14) },
8618 { VEX_W_TABLE (VEX_W_0F15) },
8619 { PREFIX_TABLE (PREFIX_VEX_0F16) },
8620 { MOD_TABLE (MOD_VEX_0F17) },
8640 { VEX_W_TABLE (VEX_W_0F28) },
8641 { VEX_W_TABLE (VEX_W_0F29) },
8642 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8643 { MOD_TABLE (MOD_VEX_0F2B) },
8644 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8645 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8646 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8647 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8668 { PREFIX_TABLE (PREFIX_VEX_0F41) },
8669 { PREFIX_TABLE (PREFIX_VEX_0F42) },
8671 { PREFIX_TABLE (PREFIX_VEX_0F44) },
8672 { PREFIX_TABLE (PREFIX_VEX_0F45) },
8673 { PREFIX_TABLE (PREFIX_VEX_0F46) },
8674 { PREFIX_TABLE (PREFIX_VEX_0F47) },
8678 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8679 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8685 { MOD_TABLE (MOD_VEX_0F50) },
8686 { PREFIX_TABLE (PREFIX_VEX_0F51) },
8687 { PREFIX_TABLE (PREFIX_VEX_0F52) },
8688 { PREFIX_TABLE (PREFIX_VEX_0F53) },
8689 { "vandpX", { XM, Vex, EXx }, 0 },
8690 { "vandnpX", { XM, Vex, EXx }, 0 },
8691 { "vorpX", { XM, Vex, EXx }, 0 },
8692 { "vxorpX", { XM, Vex, EXx }, 0 },
8694 { PREFIX_TABLE (PREFIX_VEX_0F58) },
8695 { PREFIX_TABLE (PREFIX_VEX_0F59) },
8696 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8697 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8698 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8699 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8700 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8701 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8703 { PREFIX_TABLE (PREFIX_VEX_0F60) },
8704 { PREFIX_TABLE (PREFIX_VEX_0F61) },
8705 { PREFIX_TABLE (PREFIX_VEX_0F62) },
8706 { PREFIX_TABLE (PREFIX_VEX_0F63) },
8707 { PREFIX_TABLE (PREFIX_VEX_0F64) },
8708 { PREFIX_TABLE (PREFIX_VEX_0F65) },
8709 { PREFIX_TABLE (PREFIX_VEX_0F66) },
8710 { PREFIX_TABLE (PREFIX_VEX_0F67) },
8712 { PREFIX_TABLE (PREFIX_VEX_0F68) },
8713 { PREFIX_TABLE (PREFIX_VEX_0F69) },
8714 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8715 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8716 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8717 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8718 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8719 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8721 { PREFIX_TABLE (PREFIX_VEX_0F70) },
8722 { REG_TABLE (REG_VEX_0F71) },
8723 { REG_TABLE (REG_VEX_0F72) },
8724 { REG_TABLE (REG_VEX_0F73) },
8725 { PREFIX_TABLE (PREFIX_VEX_0F74) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F75) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F76) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F77) },
8734 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8735 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8736 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F90) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F91) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F92) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F93) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F98) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F99) },
8790 { REG_TABLE (REG_VEX_0FAE) },
8813 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8815 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8816 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8817 { "vshufpX", { XM, Vex, EXx, Ib }, 0 },
8829 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8830 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8831 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8832 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8833 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8834 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8835 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8836 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8838 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8839 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8840 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8841 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8842 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8843 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8844 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8845 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8847 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8848 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8849 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8850 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8851 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8852 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8853 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8854 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8856 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8857 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8858 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8859 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8860 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8861 { PREFIX_TABLE (PREFIX_VEX_0FED) },
8862 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8863 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8865 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8866 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8867 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8868 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8869 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8870 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8871 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8872 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8874 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8875 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8876 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8877 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8878 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8879 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8880 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8886 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8895 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8896 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8907 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8923 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8924 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8925 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8926 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8927 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8954 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8956 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8959 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8963 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8964 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8965 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8985 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8986 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8987 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9022 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9048 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9049 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9050 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9051 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9054 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9055 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9057 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9058 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9059 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9061 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9062 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9063 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9064 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9077 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9078 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9079 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9080 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9081 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9082 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9094 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9096 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9098 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9099 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9118 { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
9132 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9134 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9135 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9136 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9158 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9159 { REG_TABLE (REG_VEX_0F38F3) },
9161 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9162 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9163 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9177 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9178 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9179 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9181 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9182 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9183 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9186 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9187 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9188 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9189 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9190 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9191 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9192 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9193 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9199 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9200 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9201 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9202 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9204 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9205 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9209 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9213 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9214 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9215 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9231 { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9232 { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9233 { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9234 { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9240 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9241 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9249 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9250 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9251 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9253 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9255 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9258 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9259 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9260 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9261 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9262 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9280 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9281 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9282 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9283 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9285 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9286 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9287 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9288 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9294 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9295 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9296 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9297 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9298 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9299 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9300 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9301 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9312 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9313 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9314 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9315 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9316 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9317 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9318 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9319 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9408 { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9409 { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9427 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9447 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9467 #define NEED_OPCODE_TABLE
9468 #include "i386-dis-evex.h"
9469 #undef NEED_OPCODE_TABLE
9470 static const struct dis386 vex_len_table[][2] = {
9471 /* VEX_LEN_0F10_P_1 */
9473 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9474 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9477 /* VEX_LEN_0F10_P_3 */
9479 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9480 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9483 /* VEX_LEN_0F11_P_1 */
9485 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9486 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9489 /* VEX_LEN_0F11_P_3 */
9491 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9492 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9495 /* VEX_LEN_0F12_P_0_M_0 */
9497 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9500 /* VEX_LEN_0F12_P_0_M_1 */
9502 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9505 /* VEX_LEN_0F12_P_2 */
9507 { VEX_W_TABLE (VEX_W_0F12_P_2) },
9510 /* VEX_LEN_0F13_M_0 */
9512 { VEX_W_TABLE (VEX_W_0F13_M_0) },
9515 /* VEX_LEN_0F16_P_0_M_0 */
9517 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9520 /* VEX_LEN_0F16_P_0_M_1 */
9522 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9525 /* VEX_LEN_0F16_P_2 */
9527 { VEX_W_TABLE (VEX_W_0F16_P_2) },
9530 /* VEX_LEN_0F17_M_0 */
9532 { VEX_W_TABLE (VEX_W_0F17_M_0) },
9535 /* VEX_LEN_0F2A_P_1 */
9537 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9538 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9541 /* VEX_LEN_0F2A_P_3 */
9543 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9544 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9547 /* VEX_LEN_0F2C_P_1 */
9549 { "vcvttss2si", { Gv, EXdScalar }, 0 },
9550 { "vcvttss2si", { Gv, EXdScalar }, 0 },
9553 /* VEX_LEN_0F2C_P_3 */
9555 { "vcvttsd2si", { Gv, EXqScalar }, 0 },
9556 { "vcvttsd2si", { Gv, EXqScalar }, 0 },
9559 /* VEX_LEN_0F2D_P_1 */
9561 { "vcvtss2si", { Gv, EXdScalar }, 0 },
9562 { "vcvtss2si", { Gv, EXdScalar }, 0 },
9565 /* VEX_LEN_0F2D_P_3 */
9567 { "vcvtsd2si", { Gv, EXqScalar }, 0 },
9568 { "vcvtsd2si", { Gv, EXqScalar }, 0 },
9571 /* VEX_LEN_0F2E_P_0 */
9573 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9574 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9577 /* VEX_LEN_0F2E_P_2 */
9579 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9580 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9583 /* VEX_LEN_0F2F_P_0 */
9585 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9586 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9589 /* VEX_LEN_0F2F_P_2 */
9591 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9592 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9595 /* VEX_LEN_0F41_P_0 */
9598 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9600 /* VEX_LEN_0F41_P_2 */
9603 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9605 /* VEX_LEN_0F42_P_0 */
9608 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9610 /* VEX_LEN_0F42_P_2 */
9613 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9615 /* VEX_LEN_0F44_P_0 */
9617 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9619 /* VEX_LEN_0F44_P_2 */
9621 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9623 /* VEX_LEN_0F45_P_0 */
9626 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9628 /* VEX_LEN_0F45_P_2 */
9631 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9633 /* VEX_LEN_0F46_P_0 */
9636 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9638 /* VEX_LEN_0F46_P_2 */
9641 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9643 /* VEX_LEN_0F47_P_0 */
9646 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9648 /* VEX_LEN_0F47_P_2 */
9651 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9653 /* VEX_LEN_0F4A_P_0 */
9656 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9658 /* VEX_LEN_0F4A_P_2 */
9661 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9663 /* VEX_LEN_0F4B_P_0 */
9666 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9668 /* VEX_LEN_0F4B_P_2 */
9671 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9674 /* VEX_LEN_0F51_P_1 */
9676 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9677 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9680 /* VEX_LEN_0F51_P_3 */
9682 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9683 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9686 /* VEX_LEN_0F52_P_1 */
9688 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9689 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9692 /* VEX_LEN_0F53_P_1 */
9694 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9695 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9698 /* VEX_LEN_0F58_P_1 */
9700 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9701 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9704 /* VEX_LEN_0F58_P_3 */
9706 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9707 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9710 /* VEX_LEN_0F59_P_1 */
9712 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9713 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9716 /* VEX_LEN_0F59_P_3 */
9718 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9719 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9722 /* VEX_LEN_0F5A_P_1 */
9724 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9725 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9728 /* VEX_LEN_0F5A_P_3 */
9730 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9731 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9734 /* VEX_LEN_0F5C_P_1 */
9736 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9737 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9740 /* VEX_LEN_0F5C_P_3 */
9742 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9743 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9746 /* VEX_LEN_0F5D_P_1 */
9748 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9749 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9752 /* VEX_LEN_0F5D_P_3 */
9754 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9755 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9758 /* VEX_LEN_0F5E_P_1 */
9760 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9761 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9764 /* VEX_LEN_0F5E_P_3 */
9766 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9767 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9770 /* VEX_LEN_0F5F_P_1 */
9772 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9773 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9776 /* VEX_LEN_0F5F_P_3 */
9778 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9779 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9782 /* VEX_LEN_0F6E_P_2 */
9784 { "vmovK", { XMScalar, Edq }, 0 },
9785 { "vmovK", { XMScalar, Edq }, 0 },
9788 /* VEX_LEN_0F7E_P_1 */
9790 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9791 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9794 /* VEX_LEN_0F7E_P_2 */
9796 { "vmovK", { Edq, XMScalar }, 0 },
9797 { "vmovK", { Edq, XMScalar }, 0 },
9800 /* VEX_LEN_0F90_P_0 */
9802 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9805 /* VEX_LEN_0F90_P_2 */
9807 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9810 /* VEX_LEN_0F91_P_0 */
9812 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9815 /* VEX_LEN_0F91_P_2 */
9817 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9820 /* VEX_LEN_0F92_P_0 */
9822 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9825 /* VEX_LEN_0F92_P_2 */
9827 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9830 /* VEX_LEN_0F92_P_3 */
9832 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9835 /* VEX_LEN_0F93_P_0 */
9837 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9840 /* VEX_LEN_0F93_P_2 */
9842 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9845 /* VEX_LEN_0F93_P_3 */
9847 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9850 /* VEX_LEN_0F98_P_0 */
9852 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9855 /* VEX_LEN_0F98_P_2 */
9857 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9860 /* VEX_LEN_0F99_P_0 */
9862 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9865 /* VEX_LEN_0F99_P_2 */
9867 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9870 /* VEX_LEN_0FAE_R_2_M_0 */
9872 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9875 /* VEX_LEN_0FAE_R_3_M_0 */
9877 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9880 /* VEX_LEN_0FC2_P_1 */
9882 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9883 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9886 /* VEX_LEN_0FC2_P_3 */
9888 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9889 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9892 /* VEX_LEN_0FC4_P_2 */
9894 { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9897 /* VEX_LEN_0FC5_P_2 */
9899 { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9902 /* VEX_LEN_0FD6_P_2 */
9904 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9905 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9908 /* VEX_LEN_0FF7_P_2 */
9910 { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9913 /* VEX_LEN_0F3816_P_2 */
9916 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9919 /* VEX_LEN_0F3819_P_2 */
9922 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9925 /* VEX_LEN_0F381A_P_2_M_0 */
9928 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9931 /* VEX_LEN_0F3836_P_2 */
9934 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9937 /* VEX_LEN_0F3841_P_2 */
9939 { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9942 /* VEX_LEN_0F385A_P_2_M_0 */
9945 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9948 /* VEX_LEN_0F38DB_P_2 */
9950 { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9953 /* VEX_LEN_0F38F2_P_0 */
9955 { "andnS", { Gdq, VexGdq, Edq }, 0 },
9958 /* VEX_LEN_0F38F3_R_1_P_0 */
9960 { "blsrS", { VexGdq, Edq }, 0 },
9963 /* VEX_LEN_0F38F3_R_2_P_0 */
9965 { "blsmskS", { VexGdq, Edq }, 0 },
9968 /* VEX_LEN_0F38F3_R_3_P_0 */
9970 { "blsiS", { VexGdq, Edq }, 0 },
9973 /* VEX_LEN_0F38F5_P_0 */
9975 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
9978 /* VEX_LEN_0F38F5_P_1 */
9980 { "pextS", { Gdq, VexGdq, Edq }, 0 },
9983 /* VEX_LEN_0F38F5_P_3 */
9985 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
9988 /* VEX_LEN_0F38F6_P_3 */
9990 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
9993 /* VEX_LEN_0F38F7_P_0 */
9995 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
9998 /* VEX_LEN_0F38F7_P_1 */
10000 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
10003 /* VEX_LEN_0F38F7_P_2 */
10005 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
10008 /* VEX_LEN_0F38F7_P_3 */
10010 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
10013 /* VEX_LEN_0F3A00_P_2 */
10016 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10019 /* VEX_LEN_0F3A01_P_2 */
10022 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10025 /* VEX_LEN_0F3A06_P_2 */
10028 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10031 /* VEX_LEN_0F3A0A_P_2 */
10033 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10034 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10037 /* VEX_LEN_0F3A0B_P_2 */
10039 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10040 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10043 /* VEX_LEN_0F3A14_P_2 */
10045 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10048 /* VEX_LEN_0F3A15_P_2 */
10050 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10053 /* VEX_LEN_0F3A16_P_2 */
10055 { "vpextrK", { Edq, XM, Ib }, 0 },
10058 /* VEX_LEN_0F3A17_P_2 */
10060 { "vextractps", { Edqd, XM, Ib }, 0 },
10063 /* VEX_LEN_0F3A18_P_2 */
10066 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10069 /* VEX_LEN_0F3A19_P_2 */
10072 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10075 /* VEX_LEN_0F3A20_P_2 */
10077 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10080 /* VEX_LEN_0F3A21_P_2 */
10082 { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10085 /* VEX_LEN_0F3A22_P_2 */
10087 { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 },
10090 /* VEX_LEN_0F3A30_P_2 */
10092 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10095 /* VEX_LEN_0F3A31_P_2 */
10097 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10100 /* VEX_LEN_0F3A32_P_2 */
10102 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10105 /* VEX_LEN_0F3A33_P_2 */
10107 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10110 /* VEX_LEN_0F3A38_P_2 */
10113 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10116 /* VEX_LEN_0F3A39_P_2 */
10119 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10122 /* VEX_LEN_0F3A41_P_2 */
10124 { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10127 /* VEX_LEN_0F3A46_P_2 */
10130 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10133 /* VEX_LEN_0F3A60_P_2 */
10135 { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10138 /* VEX_LEN_0F3A61_P_2 */
10140 { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10143 /* VEX_LEN_0F3A62_P_2 */
10145 { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10148 /* VEX_LEN_0F3A63_P_2 */
10150 { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10153 /* VEX_LEN_0F3A6A_P_2 */
10155 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10158 /* VEX_LEN_0F3A6B_P_2 */
10160 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10163 /* VEX_LEN_0F3A6E_P_2 */
10165 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10168 /* VEX_LEN_0F3A6F_P_2 */
10170 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10173 /* VEX_LEN_0F3A7A_P_2 */
10175 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10178 /* VEX_LEN_0F3A7B_P_2 */
10180 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10183 /* VEX_LEN_0F3A7E_P_2 */
10185 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10188 /* VEX_LEN_0F3A7F_P_2 */
10190 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10193 /* VEX_LEN_0F3ADF_P_2 */
10195 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10198 /* VEX_LEN_0F3AF0_P_3 */
10200 { "rorxS", { Gdq, Edq, Ib }, 0 },
10203 /* VEX_LEN_0FXOP_08_CC */
10205 { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 },
10208 /* VEX_LEN_0FXOP_08_CD */
10210 { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 },
10213 /* VEX_LEN_0FXOP_08_CE */
10215 { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 },
10218 /* VEX_LEN_0FXOP_08_CF */
10220 { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 },
10223 /* VEX_LEN_0FXOP_08_EC */
10225 { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 },
10228 /* VEX_LEN_0FXOP_08_ED */
10230 { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 },
10233 /* VEX_LEN_0FXOP_08_EE */
10235 { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 },
10238 /* VEX_LEN_0FXOP_08_EF */
10240 { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 },
10243 /* VEX_LEN_0FXOP_09_80 */
10245 { "vfrczps", { XM, EXxmm }, 0 },
10246 { "vfrczps", { XM, EXymmq }, 0 },
10249 /* VEX_LEN_0FXOP_09_81 */
10251 { "vfrczpd", { XM, EXxmm }, 0 },
10252 { "vfrczpd", { XM, EXymmq }, 0 },
10256 static const struct dis386 vex_w_table[][2] = {
10258 /* VEX_W_0F10_P_0 */
10259 { "vmovups", { XM, EXx }, 0 },
10262 /* VEX_W_0F10_P_1 */
10263 { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
10266 /* VEX_W_0F10_P_2 */
10267 { "vmovupd", { XM, EXx }, 0 },
10270 /* VEX_W_0F10_P_3 */
10271 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
10274 /* VEX_W_0F11_P_0 */
10275 { "vmovups", { EXxS, XM }, 0 },
10278 /* VEX_W_0F11_P_1 */
10279 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10282 /* VEX_W_0F11_P_2 */
10283 { "vmovupd", { EXxS, XM }, 0 },
10286 /* VEX_W_0F11_P_3 */
10287 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10290 /* VEX_W_0F12_P_0_M_0 */
10291 { "vmovlps", { XM, Vex128, EXq }, 0 },
10294 /* VEX_W_0F12_P_0_M_1 */
10295 { "vmovhlps", { XM, Vex128, EXq }, 0 },
10298 /* VEX_W_0F12_P_1 */
10299 { "vmovsldup", { XM, EXx }, 0 },
10302 /* VEX_W_0F12_P_2 */
10303 { "vmovlpd", { XM, Vex128, EXq }, 0 },
10306 /* VEX_W_0F12_P_3 */
10307 { "vmovddup", { XM, EXymmq }, 0 },
10310 /* VEX_W_0F13_M_0 */
10311 { "vmovlpX", { EXq, XM }, 0 },
10315 { "vunpcklpX", { XM, Vex, EXx }, 0 },
10319 { "vunpckhpX", { XM, Vex, EXx }, 0 },
10322 /* VEX_W_0F16_P_0_M_0 */
10323 { "vmovhps", { XM, Vex128, EXq }, 0 },
10326 /* VEX_W_0F16_P_0_M_1 */
10327 { "vmovlhps", { XM, Vex128, EXq }, 0 },
10330 /* VEX_W_0F16_P_1 */
10331 { "vmovshdup", { XM, EXx }, 0 },
10334 /* VEX_W_0F16_P_2 */
10335 { "vmovhpd", { XM, Vex128, EXq }, 0 },
10338 /* VEX_W_0F17_M_0 */
10339 { "vmovhpX", { EXq, XM }, 0 },
10343 { "vmovapX", { XM, EXx }, 0 },
10347 { "vmovapX", { EXxS, XM }, 0 },
10350 /* VEX_W_0F2B_M_0 */
10351 { "vmovntpX", { Mx, XM }, 0 },
10354 /* VEX_W_0F2E_P_0 */
10355 { "vucomiss", { XMScalar, EXdScalar }, 0 },
10358 /* VEX_W_0F2E_P_2 */
10359 { "vucomisd", { XMScalar, EXqScalar }, 0 },
10362 /* VEX_W_0F2F_P_0 */
10363 { "vcomiss", { XMScalar, EXdScalar }, 0 },
10366 /* VEX_W_0F2F_P_2 */
10367 { "vcomisd", { XMScalar, EXqScalar }, 0 },
10370 /* VEX_W_0F41_P_0_LEN_1 */
10371 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10372 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10375 /* VEX_W_0F41_P_2_LEN_1 */
10376 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10377 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10380 /* VEX_W_0F42_P_0_LEN_1 */
10381 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10382 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10385 /* VEX_W_0F42_P_2_LEN_1 */
10386 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10387 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10390 /* VEX_W_0F44_P_0_LEN_0 */
10391 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10392 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10395 /* VEX_W_0F44_P_2_LEN_0 */
10396 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10397 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10400 /* VEX_W_0F45_P_0_LEN_1 */
10401 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10402 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10405 /* VEX_W_0F45_P_2_LEN_1 */
10406 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10407 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10410 /* VEX_W_0F46_P_0_LEN_1 */
10411 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10412 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10415 /* VEX_W_0F46_P_2_LEN_1 */
10416 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10417 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10420 /* VEX_W_0F47_P_0_LEN_1 */
10421 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10422 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10425 /* VEX_W_0F47_P_2_LEN_1 */
10426 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10427 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10430 /* VEX_W_0F4A_P_0_LEN_1 */
10431 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10432 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10435 /* VEX_W_0F4A_P_2_LEN_1 */
10436 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10437 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10440 /* VEX_W_0F4B_P_0_LEN_1 */
10441 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10442 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10445 /* VEX_W_0F4B_P_2_LEN_1 */
10446 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10449 /* VEX_W_0F50_M_0 */
10450 { "vmovmskpX", { Gdq, XS }, 0 },
10453 /* VEX_W_0F51_P_0 */
10454 { "vsqrtps", { XM, EXx }, 0 },
10457 /* VEX_W_0F51_P_1 */
10458 { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10461 /* VEX_W_0F51_P_2 */
10462 { "vsqrtpd", { XM, EXx }, 0 },
10465 /* VEX_W_0F51_P_3 */
10466 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10469 /* VEX_W_0F52_P_0 */
10470 { "vrsqrtps", { XM, EXx }, 0 },
10473 /* VEX_W_0F52_P_1 */
10474 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10477 /* VEX_W_0F53_P_0 */
10478 { "vrcpps", { XM, EXx }, 0 },
10481 /* VEX_W_0F53_P_1 */
10482 { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
10485 /* VEX_W_0F58_P_0 */
10486 { "vaddps", { XM, Vex, EXx }, 0 },
10489 /* VEX_W_0F58_P_1 */
10490 { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
10493 /* VEX_W_0F58_P_2 */
10494 { "vaddpd", { XM, Vex, EXx }, 0 },
10497 /* VEX_W_0F58_P_3 */
10498 { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10501 /* VEX_W_0F59_P_0 */
10502 { "vmulps", { XM, Vex, EXx }, 0 },
10505 /* VEX_W_0F59_P_1 */
10506 { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
10509 /* VEX_W_0F59_P_2 */
10510 { "vmulpd", { XM, Vex, EXx }, 0 },
10513 /* VEX_W_0F59_P_3 */
10514 { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10517 /* VEX_W_0F5A_P_0 */
10518 { "vcvtps2pd", { XM, EXxmmq }, 0 },
10521 /* VEX_W_0F5A_P_1 */
10522 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
10525 /* VEX_W_0F5A_P_3 */
10526 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
10529 /* VEX_W_0F5B_P_0 */
10530 { "vcvtdq2ps", { XM, EXx }, 0 },
10533 /* VEX_W_0F5B_P_1 */
10534 { "vcvttps2dq", { XM, EXx }, 0 },
10537 /* VEX_W_0F5B_P_2 */
10538 { "vcvtps2dq", { XM, EXx }, 0 },
10541 /* VEX_W_0F5C_P_0 */
10542 { "vsubps", { XM, Vex, EXx }, 0 },
10545 /* VEX_W_0F5C_P_1 */
10546 { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
10549 /* VEX_W_0F5C_P_2 */
10550 { "vsubpd", { XM, Vex, EXx }, 0 },
10553 /* VEX_W_0F5C_P_3 */
10554 { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10557 /* VEX_W_0F5D_P_0 */
10558 { "vminps", { XM, Vex, EXx }, 0 },
10561 /* VEX_W_0F5D_P_1 */
10562 { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
10565 /* VEX_W_0F5D_P_2 */
10566 { "vminpd", { XM, Vex, EXx }, 0 },
10569 /* VEX_W_0F5D_P_3 */
10570 { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10573 /* VEX_W_0F5E_P_0 */
10574 { "vdivps", { XM, Vex, EXx }, 0 },
10577 /* VEX_W_0F5E_P_1 */
10578 { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
10581 /* VEX_W_0F5E_P_2 */
10582 { "vdivpd", { XM, Vex, EXx }, 0 },
10585 /* VEX_W_0F5E_P_3 */
10586 { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10589 /* VEX_W_0F5F_P_0 */
10590 { "vmaxps", { XM, Vex, EXx }, 0 },
10593 /* VEX_W_0F5F_P_1 */
10594 { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
10597 /* VEX_W_0F5F_P_2 */
10598 { "vmaxpd", { XM, Vex, EXx }, 0 },
10601 /* VEX_W_0F5F_P_3 */
10602 { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10605 /* VEX_W_0F60_P_2 */
10606 { "vpunpcklbw", { XM, Vex, EXx }, 0 },
10609 /* VEX_W_0F61_P_2 */
10610 { "vpunpcklwd", { XM, Vex, EXx }, 0 },
10613 /* VEX_W_0F62_P_2 */
10614 { "vpunpckldq", { XM, Vex, EXx }, 0 },
10617 /* VEX_W_0F63_P_2 */
10618 { "vpacksswb", { XM, Vex, EXx }, 0 },
10621 /* VEX_W_0F64_P_2 */
10622 { "vpcmpgtb", { XM, Vex, EXx }, 0 },
10625 /* VEX_W_0F65_P_2 */
10626 { "vpcmpgtw", { XM, Vex, EXx }, 0 },
10629 /* VEX_W_0F66_P_2 */
10630 { "vpcmpgtd", { XM, Vex, EXx }, 0 },
10633 /* VEX_W_0F67_P_2 */
10634 { "vpackuswb", { XM, Vex, EXx }, 0 },
10637 /* VEX_W_0F68_P_2 */
10638 { "vpunpckhbw", { XM, Vex, EXx }, 0 },
10641 /* VEX_W_0F69_P_2 */
10642 { "vpunpckhwd", { XM, Vex, EXx }, 0 },
10645 /* VEX_W_0F6A_P_2 */
10646 { "vpunpckhdq", { XM, Vex, EXx }, 0 },
10649 /* VEX_W_0F6B_P_2 */
10650 { "vpackssdw", { XM, Vex, EXx }, 0 },
10653 /* VEX_W_0F6C_P_2 */
10654 { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
10657 /* VEX_W_0F6D_P_2 */
10658 { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
10661 /* VEX_W_0F6F_P_1 */
10662 { "vmovdqu", { XM, EXx }, 0 },
10665 /* VEX_W_0F6F_P_2 */
10666 { "vmovdqa", { XM, EXx }, 0 },
10669 /* VEX_W_0F70_P_1 */
10670 { "vpshufhw", { XM, EXx, Ib }, 0 },
10673 /* VEX_W_0F70_P_2 */
10674 { "vpshufd", { XM, EXx, Ib }, 0 },
10677 /* VEX_W_0F70_P_3 */
10678 { "vpshuflw", { XM, EXx, Ib }, 0 },
10681 /* VEX_W_0F71_R_2_P_2 */
10682 { "vpsrlw", { Vex, XS, Ib }, 0 },
10685 /* VEX_W_0F71_R_4_P_2 */
10686 { "vpsraw", { Vex, XS, Ib }, 0 },
10689 /* VEX_W_0F71_R_6_P_2 */
10690 { "vpsllw", { Vex, XS, Ib }, 0 },
10693 /* VEX_W_0F72_R_2_P_2 */
10694 { "vpsrld", { Vex, XS, Ib }, 0 },
10697 /* VEX_W_0F72_R_4_P_2 */
10698 { "vpsrad", { Vex, XS, Ib }, 0 },
10701 /* VEX_W_0F72_R_6_P_2 */
10702 { "vpslld", { Vex, XS, Ib }, 0 },
10705 /* VEX_W_0F73_R_2_P_2 */
10706 { "vpsrlq", { Vex, XS, Ib }, 0 },
10709 /* VEX_W_0F73_R_3_P_2 */
10710 { "vpsrldq", { Vex, XS, Ib }, 0 },
10713 /* VEX_W_0F73_R_6_P_2 */
10714 { "vpsllq", { Vex, XS, Ib }, 0 },
10717 /* VEX_W_0F73_R_7_P_2 */
10718 { "vpslldq", { Vex, XS, Ib }, 0 },
10721 /* VEX_W_0F74_P_2 */
10722 { "vpcmpeqb", { XM, Vex, EXx }, 0 },
10725 /* VEX_W_0F75_P_2 */
10726 { "vpcmpeqw", { XM, Vex, EXx }, 0 },
10729 /* VEX_W_0F76_P_2 */
10730 { "vpcmpeqd", { XM, Vex, EXx }, 0 },
10733 /* VEX_W_0F77_P_0 */
10734 { "", { VZERO }, 0 },
10737 /* VEX_W_0F7C_P_2 */
10738 { "vhaddpd", { XM, Vex, EXx }, 0 },
10741 /* VEX_W_0F7C_P_3 */
10742 { "vhaddps", { XM, Vex, EXx }, 0 },
10745 /* VEX_W_0F7D_P_2 */
10746 { "vhsubpd", { XM, Vex, EXx }, 0 },
10749 /* VEX_W_0F7D_P_3 */
10750 { "vhsubps", { XM, Vex, EXx }, 0 },
10753 /* VEX_W_0F7E_P_1 */
10754 { "vmovq", { XMScalar, EXqScalar }, 0 },
10757 /* VEX_W_0F7F_P_1 */
10758 { "vmovdqu", { EXxS, XM }, 0 },
10761 /* VEX_W_0F7F_P_2 */
10762 { "vmovdqa", { EXxS, XM }, 0 },
10765 /* VEX_W_0F90_P_0_LEN_0 */
10766 { "kmovw", { MaskG, MaskE }, 0 },
10767 { "kmovq", { MaskG, MaskE }, 0 },
10770 /* VEX_W_0F90_P_2_LEN_0 */
10771 { "kmovb", { MaskG, MaskBDE }, 0 },
10772 { "kmovd", { MaskG, MaskBDE }, 0 },
10775 /* VEX_W_0F91_P_0_LEN_0 */
10776 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10777 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10780 /* VEX_W_0F91_P_2_LEN_0 */
10781 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10782 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10785 /* VEX_W_0F92_P_0_LEN_0 */
10786 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10789 /* VEX_W_0F92_P_2_LEN_0 */
10790 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10793 /* VEX_W_0F92_P_3_LEN_0 */
10794 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10795 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10798 /* VEX_W_0F93_P_0_LEN_0 */
10799 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10802 /* VEX_W_0F93_P_2_LEN_0 */
10803 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10806 /* VEX_W_0F93_P_3_LEN_0 */
10807 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10808 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10811 /* VEX_W_0F98_P_0_LEN_0 */
10812 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10813 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10816 /* VEX_W_0F98_P_2_LEN_0 */
10817 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10818 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10821 /* VEX_W_0F99_P_0_LEN_0 */
10822 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10823 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10826 /* VEX_W_0F99_P_2_LEN_0 */
10827 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10828 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10831 /* VEX_W_0FAE_R_2_M_0 */
10832 { "vldmxcsr", { Md }, 0 },
10835 /* VEX_W_0FAE_R_3_M_0 */
10836 { "vstmxcsr", { Md }, 0 },
10839 /* VEX_W_0FC2_P_0 */
10840 { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
10843 /* VEX_W_0FC2_P_1 */
10844 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10847 /* VEX_W_0FC2_P_2 */
10848 { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
10851 /* VEX_W_0FC2_P_3 */
10852 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10855 /* VEX_W_0FC4_P_2 */
10856 { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
10859 /* VEX_W_0FC5_P_2 */
10860 { "vpextrw", { Gdq, XS, Ib }, 0 },
10863 /* VEX_W_0FD0_P_2 */
10864 { "vaddsubpd", { XM, Vex, EXx }, 0 },
10867 /* VEX_W_0FD0_P_3 */
10868 { "vaddsubps", { XM, Vex, EXx }, 0 },
10871 /* VEX_W_0FD1_P_2 */
10872 { "vpsrlw", { XM, Vex, EXxmm }, 0 },
10875 /* VEX_W_0FD2_P_2 */
10876 { "vpsrld", { XM, Vex, EXxmm }, 0 },
10879 /* VEX_W_0FD3_P_2 */
10880 { "vpsrlq", { XM, Vex, EXxmm }, 0 },
10883 /* VEX_W_0FD4_P_2 */
10884 { "vpaddq", { XM, Vex, EXx }, 0 },
10887 /* VEX_W_0FD5_P_2 */
10888 { "vpmullw", { XM, Vex, EXx }, 0 },
10891 /* VEX_W_0FD6_P_2 */
10892 { "vmovq", { EXqScalarS, XMScalar }, 0 },
10895 /* VEX_W_0FD7_P_2_M_1 */
10896 { "vpmovmskb", { Gdq, XS }, 0 },
10899 /* VEX_W_0FD8_P_2 */
10900 { "vpsubusb", { XM, Vex, EXx }, 0 },
10903 /* VEX_W_0FD9_P_2 */
10904 { "vpsubusw", { XM, Vex, EXx }, 0 },
10907 /* VEX_W_0FDA_P_2 */
10908 { "vpminub", { XM, Vex, EXx }, 0 },
10911 /* VEX_W_0FDB_P_2 */
10912 { "vpand", { XM, Vex, EXx }, 0 },
10915 /* VEX_W_0FDC_P_2 */
10916 { "vpaddusb", { XM, Vex, EXx }, 0 },
10919 /* VEX_W_0FDD_P_2 */
10920 { "vpaddusw", { XM, Vex, EXx }, 0 },
10923 /* VEX_W_0FDE_P_2 */
10924 { "vpmaxub", { XM, Vex, EXx }, 0 },
10927 /* VEX_W_0FDF_P_2 */
10928 { "vpandn", { XM, Vex, EXx }, 0 },
10931 /* VEX_W_0FE0_P_2 */
10932 { "vpavgb", { XM, Vex, EXx }, 0 },
10935 /* VEX_W_0FE1_P_2 */
10936 { "vpsraw", { XM, Vex, EXxmm }, 0 },
10939 /* VEX_W_0FE2_P_2 */
10940 { "vpsrad", { XM, Vex, EXxmm }, 0 },
10943 /* VEX_W_0FE3_P_2 */
10944 { "vpavgw", { XM, Vex, EXx }, 0 },
10947 /* VEX_W_0FE4_P_2 */
10948 { "vpmulhuw", { XM, Vex, EXx }, 0 },
10951 /* VEX_W_0FE5_P_2 */
10952 { "vpmulhw", { XM, Vex, EXx }, 0 },
10955 /* VEX_W_0FE6_P_1 */
10956 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
10959 /* VEX_W_0FE6_P_2 */
10960 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
10963 /* VEX_W_0FE6_P_3 */
10964 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
10967 /* VEX_W_0FE7_P_2_M_0 */
10968 { "vmovntdq", { Mx, XM }, 0 },
10971 /* VEX_W_0FE8_P_2 */
10972 { "vpsubsb", { XM, Vex, EXx }, 0 },
10975 /* VEX_W_0FE9_P_2 */
10976 { "vpsubsw", { XM, Vex, EXx }, 0 },
10979 /* VEX_W_0FEA_P_2 */
10980 { "vpminsw", { XM, Vex, EXx }, 0 },
10983 /* VEX_W_0FEB_P_2 */
10984 { "vpor", { XM, Vex, EXx }, 0 },
10987 /* VEX_W_0FEC_P_2 */
10988 { "vpaddsb", { XM, Vex, EXx }, 0 },
10991 /* VEX_W_0FED_P_2 */
10992 { "vpaddsw", { XM, Vex, EXx }, 0 },
10995 /* VEX_W_0FEE_P_2 */
10996 { "vpmaxsw", { XM, Vex, EXx }, 0 },
10999 /* VEX_W_0FEF_P_2 */
11000 { "vpxor", { XM, Vex, EXx }, 0 },
11003 /* VEX_W_0FF0_P_3_M_0 */
11004 { "vlddqu", { XM, M }, 0 },
11007 /* VEX_W_0FF1_P_2 */
11008 { "vpsllw", { XM, Vex, EXxmm }, 0 },
11011 /* VEX_W_0FF2_P_2 */
11012 { "vpslld", { XM, Vex, EXxmm }, 0 },
11015 /* VEX_W_0FF3_P_2 */
11016 { "vpsllq", { XM, Vex, EXxmm }, 0 },
11019 /* VEX_W_0FF4_P_2 */
11020 { "vpmuludq", { XM, Vex, EXx }, 0 },
11023 /* VEX_W_0FF5_P_2 */
11024 { "vpmaddwd", { XM, Vex, EXx }, 0 },
11027 /* VEX_W_0FF6_P_2 */
11028 { "vpsadbw", { XM, Vex, EXx }, 0 },
11031 /* VEX_W_0FF7_P_2 */
11032 { "vmaskmovdqu", { XM, XS }, 0 },
11035 /* VEX_W_0FF8_P_2 */
11036 { "vpsubb", { XM, Vex, EXx }, 0 },
11039 /* VEX_W_0FF9_P_2 */
11040 { "vpsubw", { XM, Vex, EXx }, 0 },
11043 /* VEX_W_0FFA_P_2 */
11044 { "vpsubd", { XM, Vex, EXx }, 0 },
11047 /* VEX_W_0FFB_P_2 */
11048 { "vpsubq", { XM, Vex, EXx }, 0 },
11051 /* VEX_W_0FFC_P_2 */
11052 { "vpaddb", { XM, Vex, EXx }, 0 },
11055 /* VEX_W_0FFD_P_2 */
11056 { "vpaddw", { XM, Vex, EXx }, 0 },
11059 /* VEX_W_0FFE_P_2 */
11060 { "vpaddd", { XM, Vex, EXx }, 0 },
11063 /* VEX_W_0F3800_P_2 */
11064 { "vpshufb", { XM, Vex, EXx }, 0 },
11067 /* VEX_W_0F3801_P_2 */
11068 { "vphaddw", { XM, Vex, EXx }, 0 },
11071 /* VEX_W_0F3802_P_2 */
11072 { "vphaddd", { XM, Vex, EXx }, 0 },
11075 /* VEX_W_0F3803_P_2 */
11076 { "vphaddsw", { XM, Vex, EXx }, 0 },
11079 /* VEX_W_0F3804_P_2 */
11080 { "vpmaddubsw", { XM, Vex, EXx }, 0 },
11083 /* VEX_W_0F3805_P_2 */
11084 { "vphsubw", { XM, Vex, EXx }, 0 },
11087 /* VEX_W_0F3806_P_2 */
11088 { "vphsubd", { XM, Vex, EXx }, 0 },
11091 /* VEX_W_0F3807_P_2 */
11092 { "vphsubsw", { XM, Vex, EXx }, 0 },
11095 /* VEX_W_0F3808_P_2 */
11096 { "vpsignb", { XM, Vex, EXx }, 0 },
11099 /* VEX_W_0F3809_P_2 */
11100 { "vpsignw", { XM, Vex, EXx }, 0 },
11103 /* VEX_W_0F380A_P_2 */
11104 { "vpsignd", { XM, Vex, EXx }, 0 },
11107 /* VEX_W_0F380B_P_2 */
11108 { "vpmulhrsw", { XM, Vex, EXx }, 0 },
11111 /* VEX_W_0F380C_P_2 */
11112 { "vpermilps", { XM, Vex, EXx }, 0 },
11115 /* VEX_W_0F380D_P_2 */
11116 { "vpermilpd", { XM, Vex, EXx }, 0 },
11119 /* VEX_W_0F380E_P_2 */
11120 { "vtestps", { XM, EXx }, 0 },
11123 /* VEX_W_0F380F_P_2 */
11124 { "vtestpd", { XM, EXx }, 0 },
11127 /* VEX_W_0F3816_P_2 */
11128 { "vpermps", { XM, Vex, EXx }, 0 },
11131 /* VEX_W_0F3817_P_2 */
11132 { "vptest", { XM, EXx }, 0 },
11135 /* VEX_W_0F3818_P_2 */
11136 { "vbroadcastss", { XM, EXxmm_md }, 0 },
11139 /* VEX_W_0F3819_P_2 */
11140 { "vbroadcastsd", { XM, EXxmm_mq }, 0 },
11143 /* VEX_W_0F381A_P_2_M_0 */
11144 { "vbroadcastf128", { XM, Mxmm }, 0 },
11147 /* VEX_W_0F381C_P_2 */
11148 { "vpabsb", { XM, EXx }, 0 },
11151 /* VEX_W_0F381D_P_2 */
11152 { "vpabsw", { XM, EXx }, 0 },
11155 /* VEX_W_0F381E_P_2 */
11156 { "vpabsd", { XM, EXx }, 0 },
11159 /* VEX_W_0F3820_P_2 */
11160 { "vpmovsxbw", { XM, EXxmmq }, 0 },
11163 /* VEX_W_0F3821_P_2 */
11164 { "vpmovsxbd", { XM, EXxmmqd }, 0 },
11167 /* VEX_W_0F3822_P_2 */
11168 { "vpmovsxbq", { XM, EXxmmdw }, 0 },
11171 /* VEX_W_0F3823_P_2 */
11172 { "vpmovsxwd", { XM, EXxmmq }, 0 },
11175 /* VEX_W_0F3824_P_2 */
11176 { "vpmovsxwq", { XM, EXxmmqd }, 0 },
11179 /* VEX_W_0F3825_P_2 */
11180 { "vpmovsxdq", { XM, EXxmmq }, 0 },
11183 /* VEX_W_0F3828_P_2 */
11184 { "vpmuldq", { XM, Vex, EXx }, 0 },
11187 /* VEX_W_0F3829_P_2 */
11188 { "vpcmpeqq", { XM, Vex, EXx }, 0 },
11191 /* VEX_W_0F382A_P_2_M_0 */
11192 { "vmovntdqa", { XM, Mx }, 0 },
11195 /* VEX_W_0F382B_P_2 */
11196 { "vpackusdw", { XM, Vex, EXx }, 0 },
11199 /* VEX_W_0F382C_P_2_M_0 */
11200 { "vmaskmovps", { XM, Vex, Mx }, 0 },
11203 /* VEX_W_0F382D_P_2_M_0 */
11204 { "vmaskmovpd", { XM, Vex, Mx }, 0 },
11207 /* VEX_W_0F382E_P_2_M_0 */
11208 { "vmaskmovps", { Mx, Vex, XM }, 0 },
11211 /* VEX_W_0F382F_P_2_M_0 */
11212 { "vmaskmovpd", { Mx, Vex, XM }, 0 },
11215 /* VEX_W_0F3830_P_2 */
11216 { "vpmovzxbw", { XM, EXxmmq }, 0 },
11219 /* VEX_W_0F3831_P_2 */
11220 { "vpmovzxbd", { XM, EXxmmqd }, 0 },
11223 /* VEX_W_0F3832_P_2 */
11224 { "vpmovzxbq", { XM, EXxmmdw }, 0 },
11227 /* VEX_W_0F3833_P_2 */
11228 { "vpmovzxwd", { XM, EXxmmq }, 0 },
11231 /* VEX_W_0F3834_P_2 */
11232 { "vpmovzxwq", { XM, EXxmmqd }, 0 },
11235 /* VEX_W_0F3835_P_2 */
11236 { "vpmovzxdq", { XM, EXxmmq }, 0 },
11239 /* VEX_W_0F3836_P_2 */
11240 { "vpermd", { XM, Vex, EXx }, 0 },
11243 /* VEX_W_0F3837_P_2 */
11244 { "vpcmpgtq", { XM, Vex, EXx }, 0 },
11247 /* VEX_W_0F3838_P_2 */
11248 { "vpminsb", { XM, Vex, EXx }, 0 },
11251 /* VEX_W_0F3839_P_2 */
11252 { "vpminsd", { XM, Vex, EXx }, 0 },
11255 /* VEX_W_0F383A_P_2 */
11256 { "vpminuw", { XM, Vex, EXx }, 0 },
11259 /* VEX_W_0F383B_P_2 */
11260 { "vpminud", { XM, Vex, EXx }, 0 },
11263 /* VEX_W_0F383C_P_2 */
11264 { "vpmaxsb", { XM, Vex, EXx }, 0 },
11267 /* VEX_W_0F383D_P_2 */
11268 { "vpmaxsd", { XM, Vex, EXx }, 0 },
11271 /* VEX_W_0F383E_P_2 */
11272 { "vpmaxuw", { XM, Vex, EXx }, 0 },
11275 /* VEX_W_0F383F_P_2 */
11276 { "vpmaxud", { XM, Vex, EXx }, 0 },
11279 /* VEX_W_0F3840_P_2 */
11280 { "vpmulld", { XM, Vex, EXx }, 0 },
11283 /* VEX_W_0F3841_P_2 */
11284 { "vphminposuw", { XM, EXx }, 0 },
11287 /* VEX_W_0F3846_P_2 */
11288 { "vpsravd", { XM, Vex, EXx }, 0 },
11291 /* VEX_W_0F3858_P_2 */
11292 { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11295 /* VEX_W_0F3859_P_2 */
11296 { "vpbroadcastq", { XM, EXxmm_mq }, 0 },
11299 /* VEX_W_0F385A_P_2_M_0 */
11300 { "vbroadcasti128", { XM, Mxmm }, 0 },
11303 /* VEX_W_0F3878_P_2 */
11304 { "vpbroadcastb", { XM, EXxmm_mb }, 0 },
11307 /* VEX_W_0F3879_P_2 */
11308 { "vpbroadcastw", { XM, EXxmm_mw }, 0 },
11311 /* VEX_W_0F38CF_P_2 */
11312 { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
11315 /* VEX_W_0F38DB_P_2 */
11316 { "vaesimc", { XM, EXx }, 0 },
11319 /* VEX_W_0F3A00_P_2 */
11321 { "vpermq", { XM, EXx, Ib }, 0 },
11324 /* VEX_W_0F3A01_P_2 */
11326 { "vpermpd", { XM, EXx, Ib }, 0 },
11329 /* VEX_W_0F3A02_P_2 */
11330 { "vpblendd", { XM, Vex, EXx, Ib }, 0 },
11333 /* VEX_W_0F3A04_P_2 */
11334 { "vpermilps", { XM, EXx, Ib }, 0 },
11337 /* VEX_W_0F3A05_P_2 */
11338 { "vpermilpd", { XM, EXx, Ib }, 0 },
11341 /* VEX_W_0F3A06_P_2 */
11342 { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 },
11345 /* VEX_W_0F3A08_P_2 */
11346 { "vroundps", { XM, EXx, Ib }, 0 },
11349 /* VEX_W_0F3A09_P_2 */
11350 { "vroundpd", { XM, EXx, Ib }, 0 },
11353 /* VEX_W_0F3A0A_P_2 */
11354 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11357 /* VEX_W_0F3A0B_P_2 */
11358 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11361 /* VEX_W_0F3A0C_P_2 */
11362 { "vblendps", { XM, Vex, EXx, Ib }, 0 },
11365 /* VEX_W_0F3A0D_P_2 */
11366 { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
11369 /* VEX_W_0F3A0E_P_2 */
11370 { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
11373 /* VEX_W_0F3A0F_P_2 */
11374 { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
11377 /* VEX_W_0F3A14_P_2 */
11378 { "vpextrb", { Edqb, XM, Ib }, 0 },
11381 /* VEX_W_0F3A15_P_2 */
11382 { "vpextrw", { Edqw, XM, Ib }, 0 },
11385 /* VEX_W_0F3A18_P_2 */
11386 { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 },
11389 /* VEX_W_0F3A19_P_2 */
11390 { "vextractf128", { EXxmm, XM, Ib }, 0 },
11393 /* VEX_W_0F3A20_P_2 */
11394 { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
11397 /* VEX_W_0F3A21_P_2 */
11398 { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
11401 /* VEX_W_0F3A30_P_2_LEN_0 */
11402 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11403 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11406 /* VEX_W_0F3A31_P_2_LEN_0 */
11407 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11408 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11411 /* VEX_W_0F3A32_P_2_LEN_0 */
11412 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11413 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11416 /* VEX_W_0F3A33_P_2_LEN_0 */
11417 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11418 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11421 /* VEX_W_0F3A38_P_2 */
11422 { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 },
11425 /* VEX_W_0F3A39_P_2 */
11426 { "vextracti128", { EXxmm, XM, Ib }, 0 },
11429 /* VEX_W_0F3A40_P_2 */
11430 { "vdpps", { XM, Vex, EXx, Ib }, 0 },
11433 /* VEX_W_0F3A41_P_2 */
11434 { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
11437 /* VEX_W_0F3A42_P_2 */
11438 { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
11441 /* VEX_W_0F3A46_P_2 */
11442 { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
11445 /* VEX_W_0F3A48_P_2 */
11446 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11447 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11450 /* VEX_W_0F3A49_P_2 */
11451 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11452 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11455 /* VEX_W_0F3A4A_P_2 */
11456 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 },
11459 /* VEX_W_0F3A4B_P_2 */
11460 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 },
11463 /* VEX_W_0F3A4C_P_2 */
11464 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
11467 /* VEX_W_0F3A62_P_2 */
11468 { "vpcmpistrm", { XM, EXx, Ib }, 0 },
11471 /* VEX_W_0F3A63_P_2 */
11472 { "vpcmpistri", { XM, EXx, Ib }, 0 },
11475 /* VEX_W_0F3ACE_P_2 */
11477 { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
11480 /* VEX_W_0F3ACF_P_2 */
11482 { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 },
11485 /* VEX_W_0F3ADF_P_2 */
11486 { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11488 #define NEED_VEX_W_TABLE
11489 #include "i386-dis-evex.h"
11490 #undef NEED_VEX_W_TABLE
11493 static const struct dis386 mod_table[][2] = {
11496 { "leaS", { Gv, M }, 0 },
11501 { RM_TABLE (RM_C6_REG_7) },
11506 { RM_TABLE (RM_C7_REG_7) },
11510 { "Jcall^", { indirEp }, 0 },
11514 { "Jjmp^", { indirEp }, 0 },
11517 /* MOD_0F01_REG_0 */
11518 { X86_64_TABLE (X86_64_0F01_REG_0) },
11519 { RM_TABLE (RM_0F01_REG_0) },
11522 /* MOD_0F01_REG_1 */
11523 { X86_64_TABLE (X86_64_0F01_REG_1) },
11524 { RM_TABLE (RM_0F01_REG_1) },
11527 /* MOD_0F01_REG_2 */
11528 { X86_64_TABLE (X86_64_0F01_REG_2) },
11529 { RM_TABLE (RM_0F01_REG_2) },
11532 /* MOD_0F01_REG_3 */
11533 { X86_64_TABLE (X86_64_0F01_REG_3) },
11534 { RM_TABLE (RM_0F01_REG_3) },
11537 /* MOD_0F01_REG_5 */
11538 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
11539 { RM_TABLE (RM_0F01_REG_5) },
11542 /* MOD_0F01_REG_7 */
11543 { "invlpg", { Mb }, 0 },
11544 { RM_TABLE (RM_0F01_REG_7) },
11547 /* MOD_0F12_PREFIX_0 */
11548 { "movlps", { XM, EXq }, PREFIX_OPCODE },
11549 { "movhlps", { XM, EXq }, PREFIX_OPCODE },
11553 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
11556 /* MOD_0F16_PREFIX_0 */
11557 { "movhps", { XM, EXq }, 0 },
11558 { "movlhps", { XM, EXq }, 0 },
11562 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
11565 /* MOD_0F18_REG_0 */
11566 { "prefetchnta", { Mb }, 0 },
11569 /* MOD_0F18_REG_1 */
11570 { "prefetcht0", { Mb }, 0 },
11573 /* MOD_0F18_REG_2 */
11574 { "prefetcht1", { Mb }, 0 },
11577 /* MOD_0F18_REG_3 */
11578 { "prefetcht2", { Mb }, 0 },
11581 /* MOD_0F18_REG_4 */
11582 { "nop/reserved", { Mb }, 0 },
11585 /* MOD_0F18_REG_5 */
11586 { "nop/reserved", { Mb }, 0 },
11589 /* MOD_0F18_REG_6 */
11590 { "nop/reserved", { Mb }, 0 },
11593 /* MOD_0F18_REG_7 */
11594 { "nop/reserved", { Mb }, 0 },
11597 /* MOD_0F1A_PREFIX_0 */
11598 { "bndldx", { Gbnd, Ev_bnd }, 0 },
11599 { "nopQ", { Ev }, 0 },
11602 /* MOD_0F1B_PREFIX_0 */
11603 { "bndstx", { Ev_bnd, Gbnd }, 0 },
11604 { "nopQ", { Ev }, 0 },
11607 /* MOD_0F1B_PREFIX_1 */
11608 { "bndmk", { Gbnd, Ev_bnd }, 0 },
11609 { "nopQ", { Ev }, 0 },
11612 /* MOD_0F1E_PREFIX_1 */
11613 { "nopQ", { Ev }, 0 },
11614 { REG_TABLE (REG_0F1E_MOD_3) },
11619 { "movL", { Rd, Td }, 0 },
11624 { "movL", { Td, Rd }, 0 },
11627 /* MOD_0F2B_PREFIX_0 */
11628 {"movntps", { Mx, XM }, PREFIX_OPCODE },
11631 /* MOD_0F2B_PREFIX_1 */
11632 {"movntss", { Md, XM }, PREFIX_OPCODE },
11635 /* MOD_0F2B_PREFIX_2 */
11636 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
11639 /* MOD_0F2B_PREFIX_3 */
11640 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
11645 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
11648 /* MOD_0F71_REG_2 */
11650 { "psrlw", { MS, Ib }, 0 },
11653 /* MOD_0F71_REG_4 */
11655 { "psraw", { MS, Ib }, 0 },
11658 /* MOD_0F71_REG_6 */
11660 { "psllw", { MS, Ib }, 0 },
11663 /* MOD_0F72_REG_2 */
11665 { "psrld", { MS, Ib }, 0 },
11668 /* MOD_0F72_REG_4 */
11670 { "psrad", { MS, Ib }, 0 },
11673 /* MOD_0F72_REG_6 */
11675 { "pslld", { MS, Ib }, 0 },
11678 /* MOD_0F73_REG_2 */
11680 { "psrlq", { MS, Ib }, 0 },
11683 /* MOD_0F73_REG_3 */
11685 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11688 /* MOD_0F73_REG_6 */
11690 { "psllq", { MS, Ib }, 0 },
11693 /* MOD_0F73_REG_7 */
11695 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11698 /* MOD_0FAE_REG_0 */
11699 { "fxsave", { FXSAVE }, 0 },
11700 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11703 /* MOD_0FAE_REG_1 */
11704 { "fxrstor", { FXSAVE }, 0 },
11705 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11708 /* MOD_0FAE_REG_2 */
11709 { "ldmxcsr", { Md }, 0 },
11710 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11713 /* MOD_0FAE_REG_3 */
11714 { "stmxcsr", { Md }, 0 },
11715 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11718 /* MOD_0FAE_REG_4 */
11719 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11720 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11723 /* MOD_0FAE_REG_5 */
11724 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
11725 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
11728 /* MOD_0FAE_REG_6 */
11729 { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11730 { RM_TABLE (RM_0FAE_REG_6) },
11733 /* MOD_0FAE_REG_7 */
11734 { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11735 { RM_TABLE (RM_0FAE_REG_7) },
11739 { "lssS", { Gv, Mp }, 0 },
11743 { "lfsS", { Gv, Mp }, 0 },
11747 { "lgsS", { Gv, Mp }, 0 },
11751 { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11754 /* MOD_0FC7_REG_3 */
11755 { "xrstors", { FXSAVE }, 0 },
11758 /* MOD_0FC7_REG_4 */
11759 { "xsavec", { FXSAVE }, 0 },
11762 /* MOD_0FC7_REG_5 */
11763 { "xsaves", { FXSAVE }, 0 },
11766 /* MOD_0FC7_REG_6 */
11767 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11768 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11771 /* MOD_0FC7_REG_7 */
11772 { "vmptrst", { Mq }, 0 },
11773 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11778 { "pmovmskb", { Gdq, MS }, 0 },
11781 /* MOD_0FE7_PREFIX_2 */
11782 { "movntdq", { Mx, XM }, 0 },
11785 /* MOD_0FF0_PREFIX_3 */
11786 { "lddqu", { XM, M }, 0 },
11789 /* MOD_0F382A_PREFIX_2 */
11790 { "movntdqa", { XM, Mx }, 0 },
11793 /* MOD_0F38F5_PREFIX_2 */
11794 { "wrussK", { M, Gdq }, PREFIX_OPCODE },
11797 /* MOD_0F38F6_PREFIX_0 */
11798 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
11802 { "bound{S|}", { Gv, Ma }, 0 },
11803 { EVEX_TABLE (EVEX_0F) },
11807 { "lesS", { Gv, Mp }, 0 },
11808 { VEX_C4_TABLE (VEX_0F) },
11812 { "ldsS", { Gv, Mp }, 0 },
11813 { VEX_C5_TABLE (VEX_0F) },
11816 /* MOD_VEX_0F12_PREFIX_0 */
11817 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11818 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11822 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11825 /* MOD_VEX_0F16_PREFIX_0 */
11826 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11827 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11831 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11835 { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11838 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11840 { "kandw", { MaskG, MaskVex, MaskR }, 0 },
11843 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11845 { "kandq", { MaskG, MaskVex, MaskR }, 0 },
11848 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11850 { "kandb", { MaskG, MaskVex, MaskR }, 0 },
11853 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11855 { "kandd", { MaskG, MaskVex, MaskR }, 0 },
11858 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11860 { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
11863 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11865 { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
11868 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11870 { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
11873 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11875 { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
11878 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11880 { "knotw", { MaskG, MaskR }, 0 },
11883 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11885 { "knotq", { MaskG, MaskR }, 0 },
11888 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11890 { "knotb", { MaskG, MaskR }, 0 },
11893 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11895 { "knotd", { MaskG, MaskR }, 0 },
11898 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11900 { "korw", { MaskG, MaskVex, MaskR }, 0 },
11903 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11905 { "korq", { MaskG, MaskVex, MaskR }, 0 },
11908 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11910 { "korb", { MaskG, MaskVex, MaskR }, 0 },
11913 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11915 { "kord", { MaskG, MaskVex, MaskR }, 0 },
11918 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11920 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
11923 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11925 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
11928 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11930 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
11933 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11935 { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
11938 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11940 { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
11943 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11945 { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
11948 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11950 { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
11953 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11955 { "kxord", { MaskG, MaskVex, MaskR }, 0 },
11958 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11960 { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
11963 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11965 { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
11968 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11970 { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
11973 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11975 { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
11978 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11980 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
11983 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11985 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
11988 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11990 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
11995 { VEX_W_TABLE (VEX_W_0F50_M_0) },
11998 /* MOD_VEX_0F71_REG_2 */
12000 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
12003 /* MOD_VEX_0F71_REG_4 */
12005 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
12008 /* MOD_VEX_0F71_REG_6 */
12010 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
12013 /* MOD_VEX_0F72_REG_2 */
12015 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12018 /* MOD_VEX_0F72_REG_4 */
12020 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12023 /* MOD_VEX_0F72_REG_6 */
12025 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12028 /* MOD_VEX_0F73_REG_2 */
12030 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12033 /* MOD_VEX_0F73_REG_3 */
12035 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12038 /* MOD_VEX_0F73_REG_6 */
12040 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12043 /* MOD_VEX_0F73_REG_7 */
12045 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12048 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12049 { "kmovw", { Ew, MaskG }, 0 },
12053 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12054 { "kmovq", { Eq, MaskG }, 0 },
12058 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12059 { "kmovb", { Eb, MaskG }, 0 },
12063 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12064 { "kmovd", { Ed, MaskG }, 0 },
12068 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12070 { "kmovw", { MaskG, Rdq }, 0 },
12073 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12075 { "kmovb", { MaskG, Rdq }, 0 },
12078 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12080 { "kmovd", { MaskG, Rdq }, 0 },
12083 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12085 { "kmovq", { MaskG, Rdq }, 0 },
12088 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12090 { "kmovw", { Gdq, MaskR }, 0 },
12093 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12095 { "kmovb", { Gdq, MaskR }, 0 },
12098 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12100 { "kmovd", { Gdq, MaskR }, 0 },
12103 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12105 { "kmovq", { Gdq, MaskR }, 0 },
12108 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12110 { "kortestw", { MaskG, MaskR }, 0 },
12113 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12115 { "kortestq", { MaskG, MaskR }, 0 },
12118 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12120 { "kortestb", { MaskG, MaskR }, 0 },
12123 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12125 { "kortestd", { MaskG, MaskR }, 0 },
12128 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12130 { "ktestw", { MaskG, MaskR }, 0 },
12133 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12135 { "ktestq", { MaskG, MaskR }, 0 },
12138 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12140 { "ktestb", { MaskG, MaskR }, 0 },
12143 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12145 { "ktestd", { MaskG, MaskR }, 0 },
12148 /* MOD_VEX_0FAE_REG_2 */
12149 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12152 /* MOD_VEX_0FAE_REG_3 */
12153 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12156 /* MOD_VEX_0FD7_PREFIX_2 */
12158 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12161 /* MOD_VEX_0FE7_PREFIX_2 */
12162 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12165 /* MOD_VEX_0FF0_PREFIX_3 */
12166 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12169 /* MOD_VEX_0F381A_PREFIX_2 */
12170 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12173 /* MOD_VEX_0F382A_PREFIX_2 */
12174 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12177 /* MOD_VEX_0F382C_PREFIX_2 */
12178 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12181 /* MOD_VEX_0F382D_PREFIX_2 */
12182 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12185 /* MOD_VEX_0F382E_PREFIX_2 */
12186 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12189 /* MOD_VEX_0F382F_PREFIX_2 */
12190 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12193 /* MOD_VEX_0F385A_PREFIX_2 */
12194 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12197 /* MOD_VEX_0F388C_PREFIX_2 */
12198 { "vpmaskmov%LW", { XM, Vex, Mx }, 0 },
12201 /* MOD_VEX_0F388E_PREFIX_2 */
12202 { "vpmaskmov%LW", { Mx, Vex, XM }, 0 },
12205 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12207 { "kshiftrb", { MaskG, MaskR, Ib }, 0 },
12210 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12212 { "kshiftrw", { MaskG, MaskR, Ib }, 0 },
12215 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12217 { "kshiftrd", { MaskG, MaskR, Ib }, 0 },
12220 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12222 { "kshiftrq", { MaskG, MaskR, Ib }, 0 },
12225 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12227 { "kshiftlb", { MaskG, MaskR, Ib }, 0 },
12230 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12232 { "kshiftlw", { MaskG, MaskR, Ib }, 0 },
12235 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12237 { "kshiftld", { MaskG, MaskR, Ib }, 0 },
12240 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12242 { "kshiftlq", { MaskG, MaskR, Ib }, 0 },
12244 #define NEED_MOD_TABLE
12245 #include "i386-dis-evex.h"
12246 #undef NEED_MOD_TABLE
12249 static const struct dis386 rm_table[][8] = {
12252 { "xabort", { Skip_MODRM, Ib }, 0 },
12256 { "xbeginT", { Skip_MODRM, Jv }, 0 },
12259 /* RM_0F01_REG_0 */
12261 { "vmcall", { Skip_MODRM }, 0 },
12262 { "vmlaunch", { Skip_MODRM }, 0 },
12263 { "vmresume", { Skip_MODRM }, 0 },
12264 { "vmxoff", { Skip_MODRM }, 0 },
12265 { "pconfig", { Skip_MODRM }, 0 },
12268 /* RM_0F01_REG_1 */
12269 { "monitor", { { OP_Monitor, 0 } }, 0 },
12270 { "mwait", { { OP_Mwait, 0 } }, 0 },
12271 { "clac", { Skip_MODRM }, 0 },
12272 { "stac", { Skip_MODRM }, 0 },
12276 { "encls", { Skip_MODRM }, 0 },
12279 /* RM_0F01_REG_2 */
12280 { "xgetbv", { Skip_MODRM }, 0 },
12281 { "xsetbv", { Skip_MODRM }, 0 },
12284 { "vmfunc", { Skip_MODRM }, 0 },
12285 { "xend", { Skip_MODRM }, 0 },
12286 { "xtest", { Skip_MODRM }, 0 },
12287 { "enclu", { Skip_MODRM }, 0 },
12290 /* RM_0F01_REG_3 */
12291 { "vmrun", { Skip_MODRM }, 0 },
12292 { "vmmcall", { Skip_MODRM }, 0 },
12293 { "vmload", { Skip_MODRM }, 0 },
12294 { "vmsave", { Skip_MODRM }, 0 },
12295 { "stgi", { Skip_MODRM }, 0 },
12296 { "clgi", { Skip_MODRM }, 0 },
12297 { "skinit", { Skip_MODRM }, 0 },
12298 { "invlpga", { Skip_MODRM }, 0 },
12301 /* RM_0F01_REG_5 */
12302 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
12304 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
12308 { "rdpkru", { Skip_MODRM }, 0 },
12309 { "wrpkru", { Skip_MODRM }, 0 },
12312 /* RM_0F01_REG_7 */
12313 { "swapgs", { Skip_MODRM }, 0 },
12314 { "rdtscp", { Skip_MODRM }, 0 },
12315 { "monitorx", { { OP_Monitor, 0 } }, 0 },
12316 { "mwaitx", { { OP_Mwaitx, 0 } }, 0 },
12317 { "clzero", { Skip_MODRM }, 0 },
12320 /* RM_0F1E_MOD_3_REG_7 */
12321 { "nopQ", { Ev }, 0 },
12322 { "nopQ", { Ev }, 0 },
12323 { "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
12324 { "endbr32", { Skip_MODRM }, PREFIX_OPCODE },
12325 { "nopQ", { Ev }, 0 },
12326 { "nopQ", { Ev }, 0 },
12327 { "nopQ", { Ev }, 0 },
12328 { "nopQ", { Ev }, 0 },
12331 /* RM_0FAE_REG_6 */
12332 { "mfence", { Skip_MODRM }, 0 },
12335 /* RM_0FAE_REG_7 */
12336 { "sfence", { Skip_MODRM }, 0 },
12341 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12343 /* We use the high bit to indicate different name for the same
12345 #define REP_PREFIX (0xf3 | 0x100)
12346 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12347 #define XRELEASE_PREFIX (0xf3 | 0x400)
12348 #define BND_PREFIX (0xf2 | 0x400)
12349 #define NOTRACK_PREFIX (0x3e | 0x100)
12354 int newrex, i, length;
12360 last_lock_prefix = -1;
12361 last_repz_prefix = -1;
12362 last_repnz_prefix = -1;
12363 last_data_prefix = -1;
12364 last_addr_prefix = -1;
12365 last_rex_prefix = -1;
12366 last_seg_prefix = -1;
12368 active_seg_prefix = 0;
12369 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12370 all_prefixes[i] = 0;
12373 /* The maximum instruction length is 15bytes. */
12374 while (length < MAX_CODE_LENGTH - 1)
12376 FETCH_DATA (the_info, codep + 1);
12380 /* REX prefixes family. */
12397 if (address_mode == mode_64bit)
12401 last_rex_prefix = i;
12404 prefixes |= PREFIX_REPZ;
12405 last_repz_prefix = i;
12408 prefixes |= PREFIX_REPNZ;
12409 last_repnz_prefix = i;
12412 prefixes |= PREFIX_LOCK;
12413 last_lock_prefix = i;
12416 prefixes |= PREFIX_CS;
12417 last_seg_prefix = i;
12418 active_seg_prefix = PREFIX_CS;
12421 prefixes |= PREFIX_SS;
12422 last_seg_prefix = i;
12423 active_seg_prefix = PREFIX_SS;
12426 prefixes |= PREFIX_DS;
12427 last_seg_prefix = i;
12428 active_seg_prefix = PREFIX_DS;
12431 prefixes |= PREFIX_ES;
12432 last_seg_prefix = i;
12433 active_seg_prefix = PREFIX_ES;
12436 prefixes |= PREFIX_FS;
12437 last_seg_prefix = i;
12438 active_seg_prefix = PREFIX_FS;
12441 prefixes |= PREFIX_GS;
12442 last_seg_prefix = i;
12443 active_seg_prefix = PREFIX_GS;
12446 prefixes |= PREFIX_DATA;
12447 last_data_prefix = i;
12450 prefixes |= PREFIX_ADDR;
12451 last_addr_prefix = i;
12454 /* fwait is really an instruction. If there are prefixes
12455 before the fwait, they belong to the fwait, *not* to the
12456 following instruction. */
12458 if (prefixes || rex)
12460 prefixes |= PREFIX_FWAIT;
12462 /* This ensures that the previous REX prefixes are noticed
12463 as unused prefixes, as in the return case below. */
12467 prefixes = PREFIX_FWAIT;
12472 /* Rex is ignored when followed by another prefix. */
12478 if (*codep != FWAIT_OPCODE)
12479 all_prefixes[i++] = *codep;
12487 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12490 static const char *
12491 prefix_name (int pref, int sizeflag)
12493 static const char *rexes [16] =
12496 "rex.B", /* 0x41 */
12497 "rex.X", /* 0x42 */
12498 "rex.XB", /* 0x43 */
12499 "rex.R", /* 0x44 */
12500 "rex.RB", /* 0x45 */
12501 "rex.RX", /* 0x46 */
12502 "rex.RXB", /* 0x47 */
12503 "rex.W", /* 0x48 */
12504 "rex.WB", /* 0x49 */
12505 "rex.WX", /* 0x4a */
12506 "rex.WXB", /* 0x4b */
12507 "rex.WR", /* 0x4c */
12508 "rex.WRB", /* 0x4d */
12509 "rex.WRX", /* 0x4e */
12510 "rex.WRXB", /* 0x4f */
12515 /* REX prefixes family. */
12532 return rexes [pref - 0x40];
12552 return (sizeflag & DFLAG) ? "data16" : "data32";
12554 if (address_mode == mode_64bit)
12555 return (sizeflag & AFLAG) ? "addr32" : "addr64";
12557 return (sizeflag & AFLAG) ? "addr16" : "addr32";
12562 case XACQUIRE_PREFIX:
12564 case XRELEASE_PREFIX:
12568 case NOTRACK_PREFIX:
12575 static char op_out[MAX_OPERANDS][100];
12576 static int op_ad, op_index[MAX_OPERANDS];
12577 static int two_source_ops;
12578 static bfd_vma op_address[MAX_OPERANDS];
12579 static bfd_vma op_riprel[MAX_OPERANDS];
12580 static bfd_vma start_pc;
12583 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12584 * (see topic "Redundant prefixes" in the "Differences from 8086"
12585 * section of the "Virtual 8086 Mode" chapter.)
12586 * 'pc' should be the address of this instruction, it will
12587 * be used to print the target address if this is a relative jump or call
12588 * The function returns the length of this instruction in bytes.
12591 static char intel_syntax;
12592 static char intel_mnemonic = !SYSV386_COMPAT;
12593 static char open_char;
12594 static char close_char;
12595 static char separator_char;
12596 static char scale_char;
12604 static enum x86_64_isa isa64;
12606 /* Here for backwards compatibility. When gdb stops using
12607 print_insn_i386_att and print_insn_i386_intel these functions can
12608 disappear, and print_insn_i386 be merged into print_insn. */
12610 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12614 return print_insn (pc, info);
12618 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12622 return print_insn (pc, info);
12626 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12630 return print_insn (pc, info);
12634 print_i386_disassembler_options (FILE *stream)
12636 fprintf (stream, _("\n\
12637 The following i386/x86-64 specific disassembler options are supported for use\n\
12638 with the -M switch (multiple options should be separated by commas):\n"));
12640 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
12641 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
12642 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
12643 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
12644 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
12645 fprintf (stream, _(" att-mnemonic\n"
12646 " Display instruction in AT&T mnemonic\n"));
12647 fprintf (stream, _(" intel-mnemonic\n"
12648 " Display instruction in Intel mnemonic\n"));
12649 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
12650 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
12651 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
12652 fprintf (stream, _(" data32 Assume 32bit data size\n"));
12653 fprintf (stream, _(" data16 Assume 16bit data size\n"));
12654 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12655 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
12656 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
12660 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12662 /* Get a pointer to struct dis386 with a valid name. */
12664 static const struct dis386 *
12665 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12667 int vindex, vex_table_index;
12669 if (dp->name != NULL)
12672 switch (dp->op[0].bytemode)
12674 case USE_REG_TABLE:
12675 dp = ®_table[dp->op[1].bytemode][modrm.reg];
12678 case USE_MOD_TABLE:
12679 vindex = modrm.mod == 0x3 ? 1 : 0;
12680 dp = &mod_table[dp->op[1].bytemode][vindex];
12684 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12687 case USE_PREFIX_TABLE:
12690 /* The prefix in VEX is implicit. */
12691 switch (vex.prefix)
12696 case REPE_PREFIX_OPCODE:
12699 case DATA_PREFIX_OPCODE:
12702 case REPNE_PREFIX_OPCODE:
12712 int last_prefix = -1;
12715 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12716 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12718 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12720 if (last_repz_prefix > last_repnz_prefix)
12723 prefix = PREFIX_REPZ;
12724 last_prefix = last_repz_prefix;
12729 prefix = PREFIX_REPNZ;
12730 last_prefix = last_repnz_prefix;
12733 /* Check if prefix should be ignored. */
12734 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12735 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12740 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12743 prefix = PREFIX_DATA;
12744 last_prefix = last_data_prefix;
12749 used_prefixes |= prefix;
12750 all_prefixes[last_prefix] = 0;
12753 dp = &prefix_table[dp->op[1].bytemode][vindex];
12756 case USE_X86_64_TABLE:
12757 vindex = address_mode == mode_64bit ? 1 : 0;
12758 dp = &x86_64_table[dp->op[1].bytemode][vindex];
12761 case USE_3BYTE_TABLE:
12762 FETCH_DATA (info, codep + 2);
12764 dp = &three_byte_table[dp->op[1].bytemode][vindex];
12766 modrm.mod = (*codep >> 6) & 3;
12767 modrm.reg = (*codep >> 3) & 7;
12768 modrm.rm = *codep & 7;
12771 case USE_VEX_LEN_TABLE:
12775 switch (vex.length)
12788 dp = &vex_len_table[dp->op[1].bytemode][vindex];
12791 case USE_XOP_8F_TABLE:
12792 FETCH_DATA (info, codep + 3);
12793 /* All bits in the REX prefix are ignored. */
12795 rex = ~(*codep >> 5) & 0x7;
12797 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12798 switch ((*codep & 0x1f))
12804 vex_table_index = XOP_08;
12807 vex_table_index = XOP_09;
12810 vex_table_index = XOP_0A;
12814 vex.w = *codep & 0x80;
12815 if (vex.w && address_mode == mode_64bit)
12818 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12819 if (address_mode != mode_64bit)
12821 /* In 16/32-bit mode REX_B is silently ignored. */
12825 vex.length = (*codep & 0x4) ? 256 : 128;
12826 switch ((*codep & 0x3))
12831 vex.prefix = DATA_PREFIX_OPCODE;
12834 vex.prefix = REPE_PREFIX_OPCODE;
12837 vex.prefix = REPNE_PREFIX_OPCODE;
12844 dp = &xop_table[vex_table_index][vindex];
12847 FETCH_DATA (info, codep + 1);
12848 modrm.mod = (*codep >> 6) & 3;
12849 modrm.reg = (*codep >> 3) & 7;
12850 modrm.rm = *codep & 7;
12853 case USE_VEX_C4_TABLE:
12855 FETCH_DATA (info, codep + 3);
12856 /* All bits in the REX prefix are ignored. */
12858 rex = ~(*codep >> 5) & 0x7;
12859 switch ((*codep & 0x1f))
12865 vex_table_index = VEX_0F;
12868 vex_table_index = VEX_0F38;
12871 vex_table_index = VEX_0F3A;
12875 vex.w = *codep & 0x80;
12876 if (address_mode == mode_64bit)
12883 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12884 is ignored, other REX bits are 0 and the highest bit in
12885 VEX.vvvv is also ignored (but we mustn't clear it here). */
12888 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12889 vex.length = (*codep & 0x4) ? 256 : 128;
12890 switch ((*codep & 0x3))
12895 vex.prefix = DATA_PREFIX_OPCODE;
12898 vex.prefix = REPE_PREFIX_OPCODE;
12901 vex.prefix = REPNE_PREFIX_OPCODE;
12908 dp = &vex_table[vex_table_index][vindex];
12910 /* There is no MODRM byte for VEX0F 77. */
12911 if (vex_table_index != VEX_0F || vindex != 0x77)
12913 FETCH_DATA (info, codep + 1);
12914 modrm.mod = (*codep >> 6) & 3;
12915 modrm.reg = (*codep >> 3) & 7;
12916 modrm.rm = *codep & 7;
12920 case USE_VEX_C5_TABLE:
12922 FETCH_DATA (info, codep + 2);
12923 /* All bits in the REX prefix are ignored. */
12925 rex = (*codep & 0x80) ? 0 : REX_R;
12927 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12929 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12930 vex.length = (*codep & 0x4) ? 256 : 128;
12931 switch ((*codep & 0x3))
12936 vex.prefix = DATA_PREFIX_OPCODE;
12939 vex.prefix = REPE_PREFIX_OPCODE;
12942 vex.prefix = REPNE_PREFIX_OPCODE;
12949 dp = &vex_table[dp->op[1].bytemode][vindex];
12951 /* There is no MODRM byte for VEX 77. */
12952 if (vindex != 0x77)
12954 FETCH_DATA (info, codep + 1);
12955 modrm.mod = (*codep >> 6) & 3;
12956 modrm.reg = (*codep >> 3) & 7;
12957 modrm.rm = *codep & 7;
12961 case USE_VEX_W_TABLE:
12965 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12968 case USE_EVEX_TABLE:
12969 two_source_ops = 0;
12972 FETCH_DATA (info, codep + 4);
12973 /* All bits in the REX prefix are ignored. */
12975 /* The first byte after 0x62. */
12976 rex = ~(*codep >> 5) & 0x7;
12977 vex.r = *codep & 0x10;
12978 switch ((*codep & 0xf))
12981 return &bad_opcode;
12983 vex_table_index = EVEX_0F;
12986 vex_table_index = EVEX_0F38;
12989 vex_table_index = EVEX_0F3A;
12993 /* The second byte after 0x62. */
12995 vex.w = *codep & 0x80;
12996 if (vex.w && address_mode == mode_64bit)
12999 vex.register_specifier = (~(*codep >> 3)) & 0xf;
13002 if (!(*codep & 0x4))
13003 return &bad_opcode;
13005 switch ((*codep & 0x3))
13010 vex.prefix = DATA_PREFIX_OPCODE;
13013 vex.prefix = REPE_PREFIX_OPCODE;
13016 vex.prefix = REPNE_PREFIX_OPCODE;
13020 /* The third byte after 0x62. */
13023 /* Remember the static rounding bits. */
13024 vex.ll = (*codep >> 5) & 3;
13025 vex.b = (*codep & 0x10) != 0;
13027 vex.v = *codep & 0x8;
13028 vex.mask_register_specifier = *codep & 0x7;
13029 vex.zeroing = *codep & 0x80;
13031 if (address_mode != mode_64bit)
13033 /* In 16/32-bit mode silently ignore following bits. */
13043 dp = &evex_table[vex_table_index][vindex];
13045 FETCH_DATA (info, codep + 1);
13046 modrm.mod = (*codep >> 6) & 3;
13047 modrm.reg = (*codep >> 3) & 7;
13048 modrm.rm = *codep & 7;
13050 /* Set vector length. */
13051 if (modrm.mod == 3 && vex.b)
13067 return &bad_opcode;
13080 if (dp->name != NULL)
13083 return get_valid_dis386 (dp, info);
13087 get_sib (disassemble_info *info, int sizeflag)
13089 /* If modrm.mod == 3, operand must be register. */
13091 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13095 FETCH_DATA (info, codep + 2);
13096 sib.index = (codep [1] >> 3) & 7;
13097 sib.scale = (codep [1] >> 6) & 3;
13098 sib.base = codep [1] & 7;
13103 print_insn (bfd_vma pc, disassemble_info *info)
13105 const struct dis386 *dp;
13107 char *op_txt[MAX_OPERANDS];
13109 int sizeflag, orig_sizeflag;
13111 struct dis_private priv;
13114 priv.orig_sizeflag = AFLAG | DFLAG;
13115 if ((info->mach & bfd_mach_i386_i386) != 0)
13116 address_mode = mode_32bit;
13117 else if (info->mach == bfd_mach_i386_i8086)
13119 address_mode = mode_16bit;
13120 priv.orig_sizeflag = 0;
13123 address_mode = mode_64bit;
13125 if (intel_syntax == (char) -1)
13126 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13128 for (p = info->disassembler_options; p != NULL; )
13130 if (CONST_STRNEQ (p, "amd64"))
13132 else if (CONST_STRNEQ (p, "intel64"))
13134 else if (CONST_STRNEQ (p, "x86-64"))
13136 address_mode = mode_64bit;
13137 priv.orig_sizeflag = AFLAG | DFLAG;
13139 else if (CONST_STRNEQ (p, "i386"))
13141 address_mode = mode_32bit;
13142 priv.orig_sizeflag = AFLAG | DFLAG;
13144 else if (CONST_STRNEQ (p, "i8086"))
13146 address_mode = mode_16bit;
13147 priv.orig_sizeflag = 0;
13149 else if (CONST_STRNEQ (p, "intel"))
13152 if (CONST_STRNEQ (p + 5, "-mnemonic"))
13153 intel_mnemonic = 1;
13155 else if (CONST_STRNEQ (p, "att"))
13158 if (CONST_STRNEQ (p + 3, "-mnemonic"))
13159 intel_mnemonic = 0;
13161 else if (CONST_STRNEQ (p, "addr"))
13163 if (address_mode == mode_64bit)
13165 if (p[4] == '3' && p[5] == '2')
13166 priv.orig_sizeflag &= ~AFLAG;
13167 else if (p[4] == '6' && p[5] == '4')
13168 priv.orig_sizeflag |= AFLAG;
13172 if (p[4] == '1' && p[5] == '6')
13173 priv.orig_sizeflag &= ~AFLAG;
13174 else if (p[4] == '3' && p[5] == '2')
13175 priv.orig_sizeflag |= AFLAG;
13178 else if (CONST_STRNEQ (p, "data"))
13180 if (p[4] == '1' && p[5] == '6')
13181 priv.orig_sizeflag &= ~DFLAG;
13182 else if (p[4] == '3' && p[5] == '2')
13183 priv.orig_sizeflag |= DFLAG;
13185 else if (CONST_STRNEQ (p, "suffix"))
13186 priv.orig_sizeflag |= SUFFIX_ALWAYS;
13188 p = strchr (p, ',');
13193 if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13195 (*info->fprintf_func) (info->stream,
13196 _("64-bit address is disabled"));
13202 names64 = intel_names64;
13203 names32 = intel_names32;
13204 names16 = intel_names16;
13205 names8 = intel_names8;
13206 names8rex = intel_names8rex;
13207 names_seg = intel_names_seg;
13208 names_mm = intel_names_mm;
13209 names_bnd = intel_names_bnd;
13210 names_xmm = intel_names_xmm;
13211 names_ymm = intel_names_ymm;
13212 names_zmm = intel_names_zmm;
13213 index64 = intel_index64;
13214 index32 = intel_index32;
13215 names_mask = intel_names_mask;
13216 index16 = intel_index16;
13219 separator_char = '+';
13224 names64 = att_names64;
13225 names32 = att_names32;
13226 names16 = att_names16;
13227 names8 = att_names8;
13228 names8rex = att_names8rex;
13229 names_seg = att_names_seg;
13230 names_mm = att_names_mm;
13231 names_bnd = att_names_bnd;
13232 names_xmm = att_names_xmm;
13233 names_ymm = att_names_ymm;
13234 names_zmm = att_names_zmm;
13235 index64 = att_index64;
13236 index32 = att_index32;
13237 names_mask = att_names_mask;
13238 index16 = att_index16;
13241 separator_char = ',';
13245 /* The output looks better if we put 7 bytes on a line, since that
13246 puts most long word instructions on a single line. Use 8 bytes
13248 if ((info->mach & bfd_mach_l1om) != 0)
13249 info->bytes_per_line = 8;
13251 info->bytes_per_line = 7;
13253 info->private_data = &priv;
13254 priv.max_fetched = priv.the_buffer;
13255 priv.insn_start = pc;
13258 for (i = 0; i < MAX_OPERANDS; ++i)
13266 start_codep = priv.the_buffer;
13267 codep = priv.the_buffer;
13269 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13273 /* Getting here means we tried for data but didn't get it. That
13274 means we have an incomplete instruction of some sort. Just
13275 print the first byte as a prefix or a .byte pseudo-op. */
13276 if (codep > priv.the_buffer)
13278 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13280 (*info->fprintf_func) (info->stream, "%s", name);
13283 /* Just print the first byte as a .byte instruction. */
13284 (*info->fprintf_func) (info->stream, ".byte 0x%x",
13285 (unsigned int) priv.the_buffer[0]);
13295 sizeflag = priv.orig_sizeflag;
13297 if (!ckprefix () || rex_used)
13299 /* Too many prefixes or unused REX prefixes. */
13301 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13303 (*info->fprintf_func) (info->stream, "%s%s",
13305 prefix_name (all_prefixes[i], sizeflag));
13309 insn_codep = codep;
13311 FETCH_DATA (info, codep + 1);
13312 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13314 if (((prefixes & PREFIX_FWAIT)
13315 && ((*codep < 0xd8) || (*codep > 0xdf))))
13317 /* Handle prefixes before fwait. */
13318 for (i = 0; i < fwait_prefix && all_prefixes[i];
13320 (*info->fprintf_func) (info->stream, "%s ",
13321 prefix_name (all_prefixes[i], sizeflag));
13322 (*info->fprintf_func) (info->stream, "fwait");
13326 if (*codep == 0x0f)
13328 unsigned char threebyte;
13331 FETCH_DATA (info, codep + 1);
13332 threebyte = *codep;
13333 dp = &dis386_twobyte[threebyte];
13334 need_modrm = twobyte_has_modrm[*codep];
13339 dp = &dis386[*codep];
13340 need_modrm = onebyte_has_modrm[*codep];
13344 /* Save sizeflag for printing the extra prefixes later before updating
13345 it for mnemonic and operand processing. The prefix names depend
13346 only on the address mode. */
13347 orig_sizeflag = sizeflag;
13348 if (prefixes & PREFIX_ADDR)
13350 if ((prefixes & PREFIX_DATA))
13356 FETCH_DATA (info, codep + 1);
13357 modrm.mod = (*codep >> 6) & 3;
13358 modrm.reg = (*codep >> 3) & 7;
13359 modrm.rm = *codep & 7;
13365 memset (&vex, 0, sizeof (vex));
13367 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13369 get_sib (info, sizeflag);
13370 dofloat (sizeflag);
13374 dp = get_valid_dis386 (dp, info);
13375 if (dp != NULL && putop (dp->name, sizeflag) == 0)
13377 get_sib (info, sizeflag);
13378 for (i = 0; i < MAX_OPERANDS; ++i)
13381 op_ad = MAX_OPERANDS - 1 - i;
13383 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13384 /* For EVEX instruction after the last operand masking
13385 should be printed. */
13386 if (i == 0 && vex.evex)
13388 /* Don't print {%k0}. */
13389 if (vex.mask_register_specifier)
13392 oappend (names_mask[vex.mask_register_specifier]);
13402 /* Check if the REX prefix is used. */
13403 if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13404 all_prefixes[last_rex_prefix] = 0;
13406 /* Check if the SEG prefix is used. */
13407 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13408 | PREFIX_FS | PREFIX_GS)) != 0
13409 && (used_prefixes & active_seg_prefix) != 0)
13410 all_prefixes[last_seg_prefix] = 0;
13412 /* Check if the ADDR prefix is used. */
13413 if ((prefixes & PREFIX_ADDR) != 0
13414 && (used_prefixes & PREFIX_ADDR) != 0)
13415 all_prefixes[last_addr_prefix] = 0;
13417 /* Check if the DATA prefix is used. */
13418 if ((prefixes & PREFIX_DATA) != 0
13419 && (used_prefixes & PREFIX_DATA) != 0)
13420 all_prefixes[last_data_prefix] = 0;
13422 /* Print the extra prefixes. */
13424 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13425 if (all_prefixes[i])
13428 name = prefix_name (all_prefixes[i], orig_sizeflag);
13431 prefix_length += strlen (name) + 1;
13432 (*info->fprintf_func) (info->stream, "%s ", name);
13435 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13436 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13437 used by putop and MMX/SSE operand and may be overriden by the
13438 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13440 if (dp->prefix_requirement == PREFIX_OPCODE
13441 && dp != &bad_opcode
13443 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13445 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13447 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13449 && (used_prefixes & PREFIX_DATA) == 0))))
13451 (*info->fprintf_func) (info->stream, "(bad)");
13452 return end_codep - priv.the_buffer;
13455 /* Check maximum code length. */
13456 if ((codep - start_codep) > MAX_CODE_LENGTH)
13458 (*info->fprintf_func) (info->stream, "(bad)");
13459 return MAX_CODE_LENGTH;
13462 obufp = mnemonicendp;
13463 for (i = strlen (obuf) + prefix_length; i < 6; i++)
13466 (*info->fprintf_func) (info->stream, "%s", obuf);
13468 /* The enter and bound instructions are printed with operands in the same
13469 order as the intel book; everything else is printed in reverse order. */
13470 if (intel_syntax || two_source_ops)
13474 for (i = 0; i < MAX_OPERANDS; ++i)
13475 op_txt[i] = op_out[i];
13477 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13478 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13480 op_txt[2] = op_out[3];
13481 op_txt[3] = op_out[2];
13484 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13486 op_ad = op_index[i];
13487 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13488 op_index[MAX_OPERANDS - 1 - i] = op_ad;
13489 riprel = op_riprel[i];
13490 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13491 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13496 for (i = 0; i < MAX_OPERANDS; ++i)
13497 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13501 for (i = 0; i < MAX_OPERANDS; ++i)
13505 (*info->fprintf_func) (info->stream, ",");
13506 if (op_index[i] != -1 && !op_riprel[i])
13507 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13509 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13513 for (i = 0; i < MAX_OPERANDS; i++)
13514 if (op_index[i] != -1 && op_riprel[i])
13516 (*info->fprintf_func) (info->stream, " # ");
13517 (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13518 + op_address[op_index[i]]), info);
13521 return codep - priv.the_buffer;
13524 static const char *float_mem[] = {
13599 static const unsigned char float_mem_mode[] = {
13674 #define ST { OP_ST, 0 }
13675 #define STi { OP_STi, 0 }
13677 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13678 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13679 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13680 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13681 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13682 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13683 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13684 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13685 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13687 static const struct dis386 float_reg[][8] = {
13690 { "fadd", { ST, STi }, 0 },
13691 { "fmul", { ST, STi }, 0 },
13692 { "fcom", { STi }, 0 },
13693 { "fcomp", { STi }, 0 },
13694 { "fsub", { ST, STi }, 0 },
13695 { "fsubr", { ST, STi }, 0 },
13696 { "fdiv", { ST, STi }, 0 },
13697 { "fdivr", { ST, STi }, 0 },
13701 { "fld", { STi }, 0 },
13702 { "fxch", { STi }, 0 },
13712 { "fcmovb", { ST, STi }, 0 },
13713 { "fcmove", { ST, STi }, 0 },
13714 { "fcmovbe",{ ST, STi }, 0 },
13715 { "fcmovu", { ST, STi }, 0 },
13723 { "fcmovnb",{ ST, STi }, 0 },
13724 { "fcmovne",{ ST, STi }, 0 },
13725 { "fcmovnbe",{ ST, STi }, 0 },
13726 { "fcmovnu",{ ST, STi }, 0 },
13728 { "fucomi", { ST, STi }, 0 },
13729 { "fcomi", { ST, STi }, 0 },
13734 { "fadd", { STi, ST }, 0 },
13735 { "fmul", { STi, ST }, 0 },
13738 { "fsub{!M|r}", { STi, ST }, 0 },
13739 { "fsub{M|}", { STi, ST }, 0 },
13740 { "fdiv{!M|r}", { STi, ST }, 0 },
13741 { "fdiv{M|}", { STi, ST }, 0 },
13745 { "ffree", { STi }, 0 },
13747 { "fst", { STi }, 0 },
13748 { "fstp", { STi }, 0 },
13749 { "fucom", { STi }, 0 },
13750 { "fucomp", { STi }, 0 },
13756 { "faddp", { STi, ST }, 0 },
13757 { "fmulp", { STi, ST }, 0 },
13760 { "fsub{!M|r}p", { STi, ST }, 0 },
13761 { "fsub{M|}p", { STi, ST }, 0 },
13762 { "fdiv{!M|r}p", { STi, ST }, 0 },
13763 { "fdiv{M|}p", { STi, ST }, 0 },
13767 { "ffreep", { STi }, 0 },
13772 { "fucomip", { ST, STi }, 0 },
13773 { "fcomip", { ST, STi }, 0 },
13778 static char *fgrps[][8] = {
13781 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13786 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13791 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13796 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13801 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13806 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13811 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13816 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13817 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13822 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13827 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13832 swap_operand (void)
13834 mnemonicendp[0] = '.';
13835 mnemonicendp[1] = 's';
13840 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13841 int sizeflag ATTRIBUTE_UNUSED)
13843 /* Skip mod/rm byte. */
13849 dofloat (int sizeflag)
13851 const struct dis386 *dp;
13852 unsigned char floatop;
13854 floatop = codep[-1];
13856 if (modrm.mod != 3)
13858 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13860 putop (float_mem[fp_indx], sizeflag);
13863 OP_E (float_mem_mode[fp_indx], sizeflag);
13866 /* Skip mod/rm byte. */
13870 dp = &float_reg[floatop - 0xd8][modrm.reg];
13871 if (dp->name == NULL)
13873 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13875 /* Instruction fnstsw is only one with strange arg. */
13876 if (floatop == 0xdf && codep[-1] == 0xe0)
13877 strcpy (op_out[0], names16[0]);
13881 putop (dp->name, sizeflag);
13886 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13891 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13895 /* Like oappend (below), but S is a string starting with '%'.
13896 In Intel syntax, the '%' is elided. */
13898 oappend_maybe_intel (const char *s)
13900 oappend (s + intel_syntax);
13904 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13906 oappend_maybe_intel ("%st");
13910 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13912 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13913 oappend_maybe_intel (scratchbuf);
13916 /* Capital letters in template are macros. */
13918 putop (const char *in_template, int sizeflag)
13923 unsigned int l = 0, len = 1;
13926 #define SAVE_LAST(c) \
13927 if (l < len && l < sizeof (last)) \
13932 for (p = in_template; *p; p++)
13948 while (*++p != '|')
13949 if (*p == '}' || *p == '\0')
13952 /* Fall through. */
13957 while (*++p != '}')
13968 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13972 if (l == 0 && len == 1)
13977 if (sizeflag & SUFFIX_ALWAYS)
13990 if (address_mode == mode_64bit
13991 && !(prefixes & PREFIX_ADDR))
14002 if (intel_syntax && !alt)
14004 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14006 if (sizeflag & DFLAG)
14007 *obufp++ = intel_syntax ? 'd' : 'l';
14009 *obufp++ = intel_syntax ? 'w' : 's';
14010 used_prefixes |= (prefixes & PREFIX_DATA);
14014 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14017 if (modrm.mod == 3)
14023 if (sizeflag & DFLAG)
14024 *obufp++ = intel_syntax ? 'd' : 'l';
14027 used_prefixes |= (prefixes & PREFIX_DATA);
14033 case 'E': /* For jcxz/jecxz */
14034 if (address_mode == mode_64bit)
14036 if (sizeflag & AFLAG)
14042 if (sizeflag & AFLAG)
14044 used_prefixes |= (prefixes & PREFIX_ADDR);
14049 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14051 if (sizeflag & AFLAG)
14052 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14054 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14055 used_prefixes |= (prefixes & PREFIX_ADDR);
14059 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14061 if ((rex & REX_W) || (sizeflag & DFLAG))
14065 if (!(rex & REX_W))
14066 used_prefixes |= (prefixes & PREFIX_DATA);
14071 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14072 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14074 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14077 if (prefixes & PREFIX_DS)
14096 if (l != 0 || len != 1)
14098 if (l != 1 || len != 2 || last[0] != 'X')
14103 if (!need_vex || !vex.evex)
14106 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14108 switch (vex.length)
14126 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14131 /* Fall through. */
14134 if (l != 0 || len != 1)
14142 if (sizeflag & SUFFIX_ALWAYS)
14146 if (intel_mnemonic != cond)
14150 if ((prefixes & PREFIX_FWAIT) == 0)
14153 used_prefixes |= PREFIX_FWAIT;
14159 else if (intel_syntax && (sizeflag & DFLAG))
14163 if (!(rex & REX_W))
14164 used_prefixes |= (prefixes & PREFIX_DATA);
14168 && address_mode == mode_64bit
14169 && isa64 == intel64)
14174 /* Fall through. */
14177 && address_mode == mode_64bit
14178 && ((sizeflag & DFLAG) || (rex & REX_W)))
14183 /* Fall through. */
14186 if (l == 0 && len == 1)
14191 if ((rex & REX_W) == 0
14192 && (prefixes & PREFIX_DATA))
14194 if ((sizeflag & DFLAG) == 0)
14196 used_prefixes |= (prefixes & PREFIX_DATA);
14200 if ((prefixes & PREFIX_DATA)
14202 || (sizeflag & SUFFIX_ALWAYS))
14209 if (sizeflag & DFLAG)
14213 used_prefixes |= (prefixes & PREFIX_DATA);
14219 if (l != 1 || len != 2 || last[0] != 'L')
14225 if ((prefixes & PREFIX_DATA)
14227 || (sizeflag & SUFFIX_ALWAYS))
14234 if (sizeflag & DFLAG)
14235 *obufp++ = intel_syntax ? 'd' : 'l';
14238 used_prefixes |= (prefixes & PREFIX_DATA);
14246 if (address_mode == mode_64bit
14247 && ((sizeflag & DFLAG) || (rex & REX_W)))
14249 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14253 /* Fall through. */
14256 if (l == 0 && len == 1)
14259 if (intel_syntax && !alt)
14262 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14268 if (sizeflag & DFLAG)
14269 *obufp++ = intel_syntax ? 'd' : 'l';
14272 used_prefixes |= (prefixes & PREFIX_DATA);
14278 if (l != 1 || len != 2 || last[0] != 'L')
14284 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14299 else if (sizeflag & DFLAG)
14308 if (intel_syntax && !p[1]
14309 && ((rex & REX_W) || (sizeflag & DFLAG)))
14311 if (!(rex & REX_W))
14312 used_prefixes |= (prefixes & PREFIX_DATA);
14315 if (l == 0 && len == 1)
14319 if (address_mode == mode_64bit
14320 && ((sizeflag & DFLAG) || (rex & REX_W)))
14322 if (sizeflag & SUFFIX_ALWAYS)
14344 /* Fall through. */
14347 if (l == 0 && len == 1)
14352 if (sizeflag & SUFFIX_ALWAYS)
14358 if (sizeflag & DFLAG)
14362 used_prefixes |= (prefixes & PREFIX_DATA);
14376 if (address_mode == mode_64bit
14377 && !(prefixes & PREFIX_ADDR))
14388 if (l != 0 || len != 1)
14393 if (need_vex && vex.prefix)
14395 if (vex.prefix == DATA_PREFIX_OPCODE)
14402 if (prefixes & PREFIX_DATA)
14406 used_prefixes |= (prefixes & PREFIX_DATA);
14410 if (l == 0 && len == 1)
14414 if (l != 1 || len != 2 || last[0] != 'X')
14422 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14424 switch (vex.length)
14440 if (l == 0 && len == 1)
14442 /* operand size flag for cwtl, cbtw */
14451 else if (sizeflag & DFLAG)
14455 if (!(rex & REX_W))
14456 used_prefixes |= (prefixes & PREFIX_DATA);
14463 && last[0] != 'L'))
14470 if (last[0] == 'X')
14471 *obufp++ = vex.w ? 'd': 's';
14473 *obufp++ = vex.w ? 'q': 'd';
14479 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14481 if (sizeflag & DFLAG)
14485 used_prefixes |= (prefixes & PREFIX_DATA);
14491 if (address_mode == mode_64bit
14492 && (isa64 == intel64
14493 || ((sizeflag & DFLAG) || (rex & REX_W))))
14495 else if ((prefixes & PREFIX_DATA))
14497 if (!(sizeflag & DFLAG))
14499 used_prefixes |= (prefixes & PREFIX_DATA);
14506 mnemonicendp = obufp;
14511 oappend (const char *s)
14513 obufp = stpcpy (obufp, s);
14519 /* Only print the active segment register. */
14520 if (!active_seg_prefix)
14523 used_prefixes |= active_seg_prefix;
14524 switch (active_seg_prefix)
14527 oappend_maybe_intel ("%cs:");
14530 oappend_maybe_intel ("%ds:");
14533 oappend_maybe_intel ("%ss:");
14536 oappend_maybe_intel ("%es:");
14539 oappend_maybe_intel ("%fs:");
14542 oappend_maybe_intel ("%gs:");
14550 OP_indirE (int bytemode, int sizeflag)
14554 OP_E (bytemode, sizeflag);
14558 print_operand_value (char *buf, int hex, bfd_vma disp)
14560 if (address_mode == mode_64bit)
14568 sprintf_vma (tmp, disp);
14569 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14570 strcpy (buf + 2, tmp + i);
14574 bfd_signed_vma v = disp;
14581 /* Check for possible overflow on 0x8000000000000000. */
14584 strcpy (buf, "9223372036854775808");
14598 tmp[28 - i] = (v % 10) + '0';
14602 strcpy (buf, tmp + 29 - i);
14608 sprintf (buf, "0x%x", (unsigned int) disp);
14610 sprintf (buf, "%d", (int) disp);
14614 /* Put DISP in BUF as signed hex number. */
14617 print_displacement (char *buf, bfd_vma disp)
14619 bfd_signed_vma val = disp;
14628 /* Check for possible overflow. */
14631 switch (address_mode)
14634 strcpy (buf + j, "0x8000000000000000");
14637 strcpy (buf + j, "0x80000000");
14640 strcpy (buf + j, "0x8000");
14650 sprintf_vma (tmp, (bfd_vma) val);
14651 for (i = 0; tmp[i] == '0'; i++)
14653 if (tmp[i] == '\0')
14655 strcpy (buf + j, tmp + i);
14659 intel_operand_size (int bytemode, int sizeflag)
14663 && (bytemode == x_mode
14664 || bytemode == evex_half_bcst_xmmq_mode))
14667 oappend ("QWORD PTR ");
14669 oappend ("DWORD PTR ");
14678 oappend ("BYTE PTR ");
14683 oappend ("WORD PTR ");
14686 if (address_mode == mode_64bit && isa64 == intel64)
14688 oappend ("QWORD PTR ");
14691 /* Fall through. */
14693 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14695 oappend ("QWORD PTR ");
14698 /* Fall through. */
14704 oappend ("QWORD PTR ");
14707 if ((sizeflag & DFLAG) || bytemode == dq_mode)
14708 oappend ("DWORD PTR ");
14710 oappend ("WORD PTR ");
14711 used_prefixes |= (prefixes & PREFIX_DATA);
14715 if ((rex & REX_W) || (sizeflag & DFLAG))
14717 oappend ("WORD PTR ");
14718 if (!(rex & REX_W))
14719 used_prefixes |= (prefixes & PREFIX_DATA);
14722 if (sizeflag & DFLAG)
14723 oappend ("QWORD PTR ");
14725 oappend ("DWORD PTR ");
14726 used_prefixes |= (prefixes & PREFIX_DATA);
14729 case d_scalar_mode:
14730 case d_scalar_swap_mode:
14733 oappend ("DWORD PTR ");
14736 case q_scalar_mode:
14737 case q_scalar_swap_mode:
14739 oappend ("QWORD PTR ");
14742 if (address_mode == mode_64bit)
14743 oappend ("QWORD PTR ");
14745 oappend ("DWORD PTR ");
14748 if (sizeflag & DFLAG)
14749 oappend ("FWORD PTR ");
14751 oappend ("DWORD PTR ");
14752 used_prefixes |= (prefixes & PREFIX_DATA);
14755 oappend ("TBYTE PTR ");
14759 case evex_x_gscat_mode:
14760 case evex_x_nobcst_mode:
14761 case b_scalar_mode:
14762 case w_scalar_mode:
14765 switch (vex.length)
14768 oappend ("XMMWORD PTR ");
14771 oappend ("YMMWORD PTR ");
14774 oappend ("ZMMWORD PTR ");
14781 oappend ("XMMWORD PTR ");
14784 oappend ("XMMWORD PTR ");
14787 oappend ("YMMWORD PTR ");
14790 case evex_half_bcst_xmmq_mode:
14794 switch (vex.length)
14797 oappend ("QWORD PTR ");
14800 oappend ("XMMWORD PTR ");
14803 oappend ("YMMWORD PTR ");
14813 switch (vex.length)
14818 oappend ("BYTE PTR ");
14828 switch (vex.length)
14833 oappend ("WORD PTR ");
14843 switch (vex.length)
14848 oappend ("DWORD PTR ");
14858 switch (vex.length)
14863 oappend ("QWORD PTR ");
14873 switch (vex.length)
14876 oappend ("WORD PTR ");
14879 oappend ("DWORD PTR ");
14882 oappend ("QWORD PTR ");
14892 switch (vex.length)
14895 oappend ("DWORD PTR ");
14898 oappend ("QWORD PTR ");
14901 oappend ("XMMWORD PTR ");
14911 switch (vex.length)
14914 oappend ("QWORD PTR ");
14917 oappend ("YMMWORD PTR ");
14920 oappend ("ZMMWORD PTR ");
14930 switch (vex.length)
14934 oappend ("XMMWORD PTR ");
14941 oappend ("OWORD PTR ");
14944 case vex_w_dq_mode:
14945 case vex_scalar_w_dq_mode:
14950 oappend ("QWORD PTR ");
14952 oappend ("DWORD PTR ");
14954 case vex_vsib_d_w_dq_mode:
14955 case vex_vsib_q_w_dq_mode:
14962 oappend ("QWORD PTR ");
14964 oappend ("DWORD PTR ");
14968 switch (vex.length)
14971 oappend ("XMMWORD PTR ");
14974 oappend ("YMMWORD PTR ");
14977 oappend ("ZMMWORD PTR ");
14984 case vex_vsib_q_w_d_mode:
14985 case vex_vsib_d_w_d_mode:
14986 if (!need_vex || !vex.evex)
14989 switch (vex.length)
14992 oappend ("QWORD PTR ");
14995 oappend ("XMMWORD PTR ");
14998 oappend ("YMMWORD PTR ");
15006 if (!need_vex || vex.length != 128)
15009 oappend ("DWORD PTR ");
15011 oappend ("BYTE PTR ");
15017 oappend ("QWORD PTR ");
15019 oappend ("WORD PTR ");
15028 OP_E_register (int bytemode, int sizeflag)
15030 int reg = modrm.rm;
15031 const char **names;
15037 if ((sizeflag & SUFFIX_ALWAYS)
15038 && (bytemode == b_swap_mode
15039 || bytemode == bnd_swap_mode
15040 || bytemode == v_swap_mode))
15066 names = address_mode == mode_64bit ? names64 : names32;
15069 case bnd_swap_mode:
15078 if (address_mode == mode_64bit && isa64 == intel64)
15083 /* Fall through. */
15085 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15091 /* Fall through. */
15103 if ((sizeflag & DFLAG)
15104 || (bytemode != v_mode
15105 && bytemode != v_swap_mode))
15109 used_prefixes |= (prefixes & PREFIX_DATA);
15119 names = names_mask;
15124 oappend (INTERNAL_DISASSEMBLER_ERROR);
15127 oappend (names[reg]);
15131 OP_E_memory (int bytemode, int sizeflag)
15134 int add = (rex & REX_B) ? 8 : 0;
15140 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
15142 && bytemode != x_mode
15143 && bytemode != xmmq_mode
15144 && bytemode != evex_half_bcst_xmmq_mode)
15159 case vex_vsib_d_w_dq_mode:
15160 case vex_vsib_d_w_d_mode:
15161 case vex_vsib_q_w_dq_mode:
15162 case vex_vsib_q_w_d_mode:
15163 case evex_x_gscat_mode:
15165 shift = vex.w ? 3 : 2;
15168 case evex_half_bcst_xmmq_mode:
15172 shift = vex.w ? 3 : 2;
15175 /* Fall through. */
15179 case evex_x_nobcst_mode:
15181 switch (vex.length)
15204 case q_scalar_mode:
15206 case q_scalar_swap_mode:
15212 case d_scalar_mode:
15214 case d_scalar_swap_mode:
15217 case w_scalar_mode:
15221 case b_scalar_mode:
15228 /* Make necessary corrections to shift for modes that need it.
15229 For these modes we currently have shift 4, 5 or 6 depending on
15230 vex.length (it corresponds to xmmword, ymmword or zmmword
15231 operand). We might want to make it 3, 4 or 5 (e.g. for
15232 xmmq_mode). In case of broadcast enabled the corrections
15233 aren't needed, as element size is always 32 or 64 bits. */
15235 && (bytemode == xmmq_mode
15236 || bytemode == evex_half_bcst_xmmq_mode))
15238 else if (bytemode == xmmqd_mode)
15240 else if (bytemode == xmmdw_mode)
15242 else if (bytemode == ymmq_mode && vex.length == 128)
15250 intel_operand_size (bytemode, sizeflag);
15253 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15255 /* 32/64 bit address mode */
15264 int addr32flag = !((sizeflag & AFLAG)
15265 || bytemode == v_bnd_mode
15266 || bytemode == bnd_mode
15267 || bytemode == bnd_swap_mode);
15268 const char **indexes64 = names64;
15269 const char **indexes32 = names32;
15279 vindex = sib.index;
15285 case vex_vsib_d_w_dq_mode:
15286 case vex_vsib_d_w_d_mode:
15287 case vex_vsib_q_w_dq_mode:
15288 case vex_vsib_q_w_d_mode:
15298 switch (vex.length)
15301 indexes64 = indexes32 = names_xmm;
15305 || bytemode == vex_vsib_q_w_dq_mode
15306 || bytemode == vex_vsib_q_w_d_mode)
15307 indexes64 = indexes32 = names_ymm;
15309 indexes64 = indexes32 = names_xmm;
15313 || bytemode == vex_vsib_q_w_dq_mode
15314 || bytemode == vex_vsib_q_w_d_mode)
15315 indexes64 = indexes32 = names_zmm;
15317 indexes64 = indexes32 = names_ymm;
15324 haveindex = vindex != 4;
15331 rbase = base + add;
15339 if (address_mode == mode_64bit && !havesib)
15345 FETCH_DATA (the_info, codep + 1);
15347 if ((disp & 0x80) != 0)
15349 if (vex.evex && shift > 0)
15357 /* In 32bit mode, we need index register to tell [offset] from
15358 [eiz*1 + offset]. */
15359 needindex = (havesib
15362 && address_mode == mode_32bit);
15363 havedisp = (havebase
15365 || (havesib && (haveindex || scale != 0)));
15368 if (modrm.mod != 0 || base == 5)
15370 if (havedisp || riprel)
15371 print_displacement (scratchbuf, disp);
15373 print_operand_value (scratchbuf, 1, disp);
15374 oappend (scratchbuf);
15378 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15382 if ((havebase || haveindex || riprel)
15383 && (bytemode != v_bnd_mode)
15384 && (bytemode != bnd_mode)
15385 && (bytemode != bnd_swap_mode))
15386 used_prefixes |= PREFIX_ADDR;
15388 if (havedisp || (intel_syntax && riprel))
15390 *obufp++ = open_char;
15391 if (intel_syntax && riprel)
15394 oappend (!addr32flag ? "rip" : "eip");
15398 oappend (address_mode == mode_64bit && !addr32flag
15399 ? names64[rbase] : names32[rbase]);
15402 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15403 print index to tell base + index from base. */
15407 || (havebase && base != ESP_REG_NUM))
15409 if (!intel_syntax || havebase)
15411 *obufp++ = separator_char;
15415 oappend (address_mode == mode_64bit && !addr32flag
15416 ? indexes64[vindex] : indexes32[vindex]);
15418 oappend (address_mode == mode_64bit && !addr32flag
15419 ? index64 : index32);
15421 *obufp++ = scale_char;
15423 sprintf (scratchbuf, "%d", 1 << scale);
15424 oappend (scratchbuf);
15428 && (disp || modrm.mod != 0 || base == 5))
15430 if (!havedisp || (bfd_signed_vma) disp >= 0)
15435 else if (modrm.mod != 1 && disp != -disp)
15439 disp = - (bfd_signed_vma) disp;
15443 print_displacement (scratchbuf, disp);
15445 print_operand_value (scratchbuf, 1, disp);
15446 oappend (scratchbuf);
15449 *obufp++ = close_char;
15452 else if (intel_syntax)
15454 if (modrm.mod != 0 || base == 5)
15456 if (!active_seg_prefix)
15458 oappend (names_seg[ds_reg - es_reg]);
15461 print_operand_value (scratchbuf, 1, disp);
15462 oappend (scratchbuf);
15468 /* 16 bit address mode */
15469 used_prefixes |= prefixes & PREFIX_ADDR;
15476 if ((disp & 0x8000) != 0)
15481 FETCH_DATA (the_info, codep + 1);
15483 if ((disp & 0x80) != 0)
15485 if (vex.evex && shift > 0)
15490 if ((disp & 0x8000) != 0)
15496 if (modrm.mod != 0 || modrm.rm == 6)
15498 print_displacement (scratchbuf, disp);
15499 oappend (scratchbuf);
15502 if (modrm.mod != 0 || modrm.rm != 6)
15504 *obufp++ = open_char;
15506 oappend (index16[modrm.rm]);
15508 && (disp || modrm.mod != 0 || modrm.rm == 6))
15510 if ((bfd_signed_vma) disp >= 0)
15515 else if (modrm.mod != 1)
15519 disp = - (bfd_signed_vma) disp;
15522 print_displacement (scratchbuf, disp);
15523 oappend (scratchbuf);
15526 *obufp++ = close_char;
15529 else if (intel_syntax)
15531 if (!active_seg_prefix)
15533 oappend (names_seg[ds_reg - es_reg]);
15536 print_operand_value (scratchbuf, 1, disp & 0xffff);
15537 oappend (scratchbuf);
15540 if (vex.evex && vex.b
15541 && (bytemode == x_mode
15542 || bytemode == xmmq_mode
15543 || bytemode == evex_half_bcst_xmmq_mode))
15546 || bytemode == xmmq_mode
15547 || bytemode == evex_half_bcst_xmmq_mode)
15549 switch (vex.length)
15552 oappend ("{1to2}");
15555 oappend ("{1to4}");
15558 oappend ("{1to8}");
15566 switch (vex.length)
15569 oappend ("{1to4}");
15572 oappend ("{1to8}");
15575 oappend ("{1to16}");
15585 OP_E (int bytemode, int sizeflag)
15587 /* Skip mod/rm byte. */
15591 if (modrm.mod == 3)
15592 OP_E_register (bytemode, sizeflag);
15594 OP_E_memory (bytemode, sizeflag);
15598 OP_G (int bytemode, int sizeflag)
15609 oappend (names8rex[modrm.reg + add]);
15611 oappend (names8[modrm.reg + add]);
15614 oappend (names16[modrm.reg + add]);
15619 oappend (names32[modrm.reg + add]);
15622 oappend (names64[modrm.reg + add]);
15625 if (modrm.reg > 0x3)
15630 oappend (names_bnd[modrm.reg]);
15639 oappend (names64[modrm.reg + add]);
15642 if ((sizeflag & DFLAG) || bytemode != v_mode)
15643 oappend (names32[modrm.reg + add]);
15645 oappend (names16[modrm.reg + add]);
15646 used_prefixes |= (prefixes & PREFIX_DATA);
15650 if (address_mode == mode_64bit)
15651 oappend (names64[modrm.reg + add]);
15653 oappend (names32[modrm.reg + add]);
15657 if ((modrm.reg + add) > 0x7)
15662 oappend (names_mask[modrm.reg + add]);
15665 oappend (INTERNAL_DISASSEMBLER_ERROR);
15678 FETCH_DATA (the_info, codep + 8);
15679 a = *codep++ & 0xff;
15680 a |= (*codep++ & 0xff) << 8;
15681 a |= (*codep++ & 0xff) << 16;
15682 a |= (*codep++ & 0xffu) << 24;
15683 b = *codep++ & 0xff;
15684 b |= (*codep++ & 0xff) << 8;
15685 b |= (*codep++ & 0xff) << 16;
15686 b |= (*codep++ & 0xffu) << 24;
15687 x = a + ((bfd_vma) b << 32);
15695 static bfd_signed_vma
15698 bfd_signed_vma x = 0;
15700 FETCH_DATA (the_info, codep + 4);
15701 x = *codep++ & (bfd_signed_vma) 0xff;
15702 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15703 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15704 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15708 static bfd_signed_vma
15711 bfd_signed_vma x = 0;
15713 FETCH_DATA (the_info, codep + 4);
15714 x = *codep++ & (bfd_signed_vma) 0xff;
15715 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15716 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15717 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15719 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15729 FETCH_DATA (the_info, codep + 2);
15730 x = *codep++ & 0xff;
15731 x |= (*codep++ & 0xff) << 8;
15736 set_op (bfd_vma op, int riprel)
15738 op_index[op_ad] = op_ad;
15739 if (address_mode == mode_64bit)
15741 op_address[op_ad] = op;
15742 op_riprel[op_ad] = riprel;
15746 /* Mask to get a 32-bit address. */
15747 op_address[op_ad] = op & 0xffffffff;
15748 op_riprel[op_ad] = riprel & 0xffffffff;
15753 OP_REG (int code, int sizeflag)
15760 case es_reg: case ss_reg: case cs_reg:
15761 case ds_reg: case fs_reg: case gs_reg:
15762 oappend (names_seg[code - es_reg]);
15774 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15775 case sp_reg: case bp_reg: case si_reg: case di_reg:
15776 s = names16[code - ax_reg + add];
15778 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15779 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15782 s = names8rex[code - al_reg + add];
15784 s = names8[code - al_reg];
15786 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15787 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15788 if (address_mode == mode_64bit
15789 && ((sizeflag & DFLAG) || (rex & REX_W)))
15791 s = names64[code - rAX_reg + add];
15794 code += eAX_reg - rAX_reg;
15795 /* Fall through. */
15796 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15797 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15800 s = names64[code - eAX_reg + add];
15803 if (sizeflag & DFLAG)
15804 s = names32[code - eAX_reg + add];
15806 s = names16[code - eAX_reg + add];
15807 used_prefixes |= (prefixes & PREFIX_DATA);
15811 s = INTERNAL_DISASSEMBLER_ERROR;
15818 OP_IMREG (int code, int sizeflag)
15830 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15831 case sp_reg: case bp_reg: case si_reg: case di_reg:
15832 s = names16[code - ax_reg];
15834 case es_reg: case ss_reg: case cs_reg:
15835 case ds_reg: case fs_reg: case gs_reg:
15836 s = names_seg[code - es_reg];
15838 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15839 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15842 s = names8rex[code - al_reg];
15844 s = names8[code - al_reg];
15846 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15847 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15850 s = names64[code - eAX_reg];
15853 if (sizeflag & DFLAG)
15854 s = names32[code - eAX_reg];
15856 s = names16[code - eAX_reg];
15857 used_prefixes |= (prefixes & PREFIX_DATA);
15860 case z_mode_ax_reg:
15861 if ((rex & REX_W) || (sizeflag & DFLAG))
15865 if (!(rex & REX_W))
15866 used_prefixes |= (prefixes & PREFIX_DATA);
15869 s = INTERNAL_DISASSEMBLER_ERROR;
15876 OP_I (int bytemode, int sizeflag)
15879 bfd_signed_vma mask = -1;
15884 FETCH_DATA (the_info, codep + 1);
15889 if (address_mode == mode_64bit)
15894 /* Fall through. */
15901 if (sizeflag & DFLAG)
15911 used_prefixes |= (prefixes & PREFIX_DATA);
15923 oappend (INTERNAL_DISASSEMBLER_ERROR);
15928 scratchbuf[0] = '$';
15929 print_operand_value (scratchbuf + 1, 1, op);
15930 oappend_maybe_intel (scratchbuf);
15931 scratchbuf[0] = '\0';
15935 OP_I64 (int bytemode, int sizeflag)
15938 bfd_signed_vma mask = -1;
15940 if (address_mode != mode_64bit)
15942 OP_I (bytemode, sizeflag);
15949 FETCH_DATA (the_info, codep + 1);
15959 if (sizeflag & DFLAG)
15969 used_prefixes |= (prefixes & PREFIX_DATA);
15977 oappend (INTERNAL_DISASSEMBLER_ERROR);
15982 scratchbuf[0] = '$';
15983 print_operand_value (scratchbuf + 1, 1, op);
15984 oappend_maybe_intel (scratchbuf);
15985 scratchbuf[0] = '\0';
15989 OP_sI (int bytemode, int sizeflag)
15997 FETCH_DATA (the_info, codep + 1);
15999 if ((op & 0x80) != 0)
16001 if (bytemode == b_T_mode)
16003 if (address_mode != mode_64bit
16004 || !((sizeflag & DFLAG) || (rex & REX_W)))
16006 /* The operand-size prefix is overridden by a REX prefix. */
16007 if ((sizeflag & DFLAG) || (rex & REX_W))
16015 if (!(rex & REX_W))
16017 if (sizeflag & DFLAG)
16025 /* The operand-size prefix is overridden by a REX prefix. */
16026 if ((sizeflag & DFLAG) || (rex & REX_W))
16032 oappend (INTERNAL_DISASSEMBLER_ERROR);
16036 scratchbuf[0] = '$';
16037 print_operand_value (scratchbuf + 1, 1, op);
16038 oappend_maybe_intel (scratchbuf);
16042 OP_J (int bytemode, int sizeflag)
16046 bfd_vma segment = 0;
16051 FETCH_DATA (the_info, codep + 1);
16053 if ((disp & 0x80) != 0)
16057 if (isa64 == amd64)
16059 if ((sizeflag & DFLAG)
16060 || (address_mode == mode_64bit
16061 && (isa64 != amd64 || (rex & REX_W))))
16066 if ((disp & 0x8000) != 0)
16068 /* In 16bit mode, address is wrapped around at 64k within
16069 the same segment. Otherwise, a data16 prefix on a jump
16070 instruction means that the pc is masked to 16 bits after
16071 the displacement is added! */
16073 if ((prefixes & PREFIX_DATA) == 0)
16074 segment = ((start_pc + (codep - start_codep))
16075 & ~((bfd_vma) 0xffff));
16077 if (address_mode != mode_64bit
16078 || (isa64 == amd64 && !(rex & REX_W)))
16079 used_prefixes |= (prefixes & PREFIX_DATA);
16082 oappend (INTERNAL_DISASSEMBLER_ERROR);
16085 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16087 print_operand_value (scratchbuf, 1, disp);
16088 oappend (scratchbuf);
16092 OP_SEG (int bytemode, int sizeflag)
16094 if (bytemode == w_mode)
16095 oappend (names_seg[modrm.reg]);
16097 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16101 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16105 if (sizeflag & DFLAG)
16115 used_prefixes |= (prefixes & PREFIX_DATA);
16117 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16119 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16120 oappend (scratchbuf);
16124 OP_OFF (int bytemode, int sizeflag)
16128 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16129 intel_operand_size (bytemode, sizeflag);
16132 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16139 if (!active_seg_prefix)
16141 oappend (names_seg[ds_reg - es_reg]);
16145 print_operand_value (scratchbuf, 1, off);
16146 oappend (scratchbuf);
16150 OP_OFF64 (int bytemode, int sizeflag)
16154 if (address_mode != mode_64bit
16155 || (prefixes & PREFIX_ADDR))
16157 OP_OFF (bytemode, sizeflag);
16161 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16162 intel_operand_size (bytemode, sizeflag);
16169 if (!active_seg_prefix)
16171 oappend (names_seg[ds_reg - es_reg]);
16175 print_operand_value (scratchbuf, 1, off);
16176 oappend (scratchbuf);
16180 ptr_reg (int code, int sizeflag)
16184 *obufp++ = open_char;
16185 used_prefixes |= (prefixes & PREFIX_ADDR);
16186 if (address_mode == mode_64bit)
16188 if (!(sizeflag & AFLAG))
16189 s = names32[code - eAX_reg];
16191 s = names64[code - eAX_reg];
16193 else if (sizeflag & AFLAG)
16194 s = names32[code - eAX_reg];
16196 s = names16[code - eAX_reg];
16198 *obufp++ = close_char;
16203 OP_ESreg (int code, int sizeflag)
16209 case 0x6d: /* insw/insl */
16210 intel_operand_size (z_mode, sizeflag);
16212 case 0xa5: /* movsw/movsl/movsq */
16213 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16214 case 0xab: /* stosw/stosl */
16215 case 0xaf: /* scasw/scasl */
16216 intel_operand_size (v_mode, sizeflag);
16219 intel_operand_size (b_mode, sizeflag);
16222 oappend_maybe_intel ("%es:");
16223 ptr_reg (code, sizeflag);
16227 OP_DSreg (int code, int sizeflag)
16233 case 0x6f: /* outsw/outsl */
16234 intel_operand_size (z_mode, sizeflag);
16236 case 0xa5: /* movsw/movsl/movsq */
16237 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16238 case 0xad: /* lodsw/lodsl/lodsq */
16239 intel_operand_size (v_mode, sizeflag);
16242 intel_operand_size (b_mode, sizeflag);
16245 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16246 default segment register DS is printed. */
16247 if (!active_seg_prefix)
16248 active_seg_prefix = PREFIX_DS;
16250 ptr_reg (code, sizeflag);
16254 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16262 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16264 all_prefixes[last_lock_prefix] = 0;
16265 used_prefixes |= PREFIX_LOCK;
16270 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16271 oappend_maybe_intel (scratchbuf);
16275 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16284 sprintf (scratchbuf, "db%d", modrm.reg + add);
16286 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16287 oappend (scratchbuf);
16291 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16293 sprintf (scratchbuf, "%%tr%d", modrm.reg);
16294 oappend_maybe_intel (scratchbuf);
16298 OP_R (int bytemode, int sizeflag)
16300 /* Skip mod/rm byte. */
16303 OP_E_register (bytemode, sizeflag);
16307 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16309 int reg = modrm.reg;
16310 const char **names;
16312 used_prefixes |= (prefixes & PREFIX_DATA);
16313 if (prefixes & PREFIX_DATA)
16322 oappend (names[reg]);
16326 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16328 int reg = modrm.reg;
16329 const char **names;
16341 && bytemode != xmm_mode
16342 && bytemode != xmmq_mode
16343 && bytemode != evex_half_bcst_xmmq_mode
16344 && bytemode != ymm_mode
16345 && bytemode != scalar_mode)
16347 switch (vex.length)
16354 || (bytemode != vex_vsib_q_w_dq_mode
16355 && bytemode != vex_vsib_q_w_d_mode))
16367 else if (bytemode == xmmq_mode
16368 || bytemode == evex_half_bcst_xmmq_mode)
16370 switch (vex.length)
16383 else if (bytemode == ymm_mode)
16387 oappend (names[reg]);
16391 OP_EM (int bytemode, int sizeflag)
16394 const char **names;
16396 if (modrm.mod != 3)
16399 && (bytemode == v_mode || bytemode == v_swap_mode))
16401 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16402 used_prefixes |= (prefixes & PREFIX_DATA);
16404 OP_E (bytemode, sizeflag);
16408 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16411 /* Skip mod/rm byte. */
16414 used_prefixes |= (prefixes & PREFIX_DATA);
16416 if (prefixes & PREFIX_DATA)
16425 oappend (names[reg]);
16428 /* cvt* are the only instructions in sse2 which have
16429 both SSE and MMX operands and also have 0x66 prefix
16430 in their opcode. 0x66 was originally used to differentiate
16431 between SSE and MMX instruction(operands). So we have to handle the
16432 cvt* separately using OP_EMC and OP_MXC */
16434 OP_EMC (int bytemode, int sizeflag)
16436 if (modrm.mod != 3)
16438 if (intel_syntax && bytemode == v_mode)
16440 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16441 used_prefixes |= (prefixes & PREFIX_DATA);
16443 OP_E (bytemode, sizeflag);
16447 /* Skip mod/rm byte. */
16450 used_prefixes |= (prefixes & PREFIX_DATA);
16451 oappend (names_mm[modrm.rm]);
16455 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16457 used_prefixes |= (prefixes & PREFIX_DATA);
16458 oappend (names_mm[modrm.reg]);
16462 OP_EX (int bytemode, int sizeflag)
16465 const char **names;
16467 /* Skip mod/rm byte. */
16471 if (modrm.mod != 3)
16473 OP_E_memory (bytemode, sizeflag);
16488 if ((sizeflag & SUFFIX_ALWAYS)
16489 && (bytemode == x_swap_mode
16490 || bytemode == d_swap_mode
16491 || bytemode == d_scalar_swap_mode
16492 || bytemode == q_swap_mode
16493 || bytemode == q_scalar_swap_mode))
16497 && bytemode != xmm_mode
16498 && bytemode != xmmdw_mode
16499 && bytemode != xmmqd_mode
16500 && bytemode != xmm_mb_mode
16501 && bytemode != xmm_mw_mode
16502 && bytemode != xmm_md_mode
16503 && bytemode != xmm_mq_mode
16504 && bytemode != xmm_mdq_mode
16505 && bytemode != xmmq_mode
16506 && bytemode != evex_half_bcst_xmmq_mode
16507 && bytemode != ymm_mode
16508 && bytemode != d_scalar_mode
16509 && bytemode != d_scalar_swap_mode
16510 && bytemode != q_scalar_mode
16511 && bytemode != q_scalar_swap_mode
16512 && bytemode != vex_scalar_w_dq_mode)
16514 switch (vex.length)
16529 else if (bytemode == xmmq_mode
16530 || bytemode == evex_half_bcst_xmmq_mode)
16532 switch (vex.length)
16545 else if (bytemode == ymm_mode)
16549 oappend (names[reg]);
16553 OP_MS (int bytemode, int sizeflag)
16555 if (modrm.mod == 3)
16556 OP_EM (bytemode, sizeflag);
16562 OP_XS (int bytemode, int sizeflag)
16564 if (modrm.mod == 3)
16565 OP_EX (bytemode, sizeflag);
16571 OP_M (int bytemode, int sizeflag)
16573 if (modrm.mod == 3)
16574 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16577 OP_E (bytemode, sizeflag);
16581 OP_0f07 (int bytemode, int sizeflag)
16583 if (modrm.mod != 3 || modrm.rm != 0)
16586 OP_E (bytemode, sizeflag);
16589 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16590 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16593 NOP_Fixup1 (int bytemode, int sizeflag)
16595 if ((prefixes & PREFIX_DATA) != 0
16598 && address_mode == mode_64bit))
16599 OP_REG (bytemode, sizeflag);
16601 strcpy (obuf, "nop");
16605 NOP_Fixup2 (int bytemode, int sizeflag)
16607 if ((prefixes & PREFIX_DATA) != 0
16610 && address_mode == mode_64bit))
16611 OP_IMREG (bytemode, sizeflag);
16614 static const char *const Suffix3DNow[] = {
16615 /* 00 */ NULL, NULL, NULL, NULL,
16616 /* 04 */ NULL, NULL, NULL, NULL,
16617 /* 08 */ NULL, NULL, NULL, NULL,
16618 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
16619 /* 10 */ NULL, NULL, NULL, NULL,
16620 /* 14 */ NULL, NULL, NULL, NULL,
16621 /* 18 */ NULL, NULL, NULL, NULL,
16622 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
16623 /* 20 */ NULL, NULL, NULL, NULL,
16624 /* 24 */ NULL, NULL, NULL, NULL,
16625 /* 28 */ NULL, NULL, NULL, NULL,
16626 /* 2C */ NULL, NULL, NULL, NULL,
16627 /* 30 */ NULL, NULL, NULL, NULL,
16628 /* 34 */ NULL, NULL, NULL, NULL,
16629 /* 38 */ NULL, NULL, NULL, NULL,
16630 /* 3C */ NULL, NULL, NULL, NULL,
16631 /* 40 */ NULL, NULL, NULL, NULL,
16632 /* 44 */ NULL, NULL, NULL, NULL,
16633 /* 48 */ NULL, NULL, NULL, NULL,
16634 /* 4C */ NULL, NULL, NULL, NULL,
16635 /* 50 */ NULL, NULL, NULL, NULL,
16636 /* 54 */ NULL, NULL, NULL, NULL,
16637 /* 58 */ NULL, NULL, NULL, NULL,
16638 /* 5C */ NULL, NULL, NULL, NULL,
16639 /* 60 */ NULL, NULL, NULL, NULL,
16640 /* 64 */ NULL, NULL, NULL, NULL,
16641 /* 68 */ NULL, NULL, NULL, NULL,
16642 /* 6C */ NULL, NULL, NULL, NULL,
16643 /* 70 */ NULL, NULL, NULL, NULL,
16644 /* 74 */ NULL, NULL, NULL, NULL,
16645 /* 78 */ NULL, NULL, NULL, NULL,
16646 /* 7C */ NULL, NULL, NULL, NULL,
16647 /* 80 */ NULL, NULL, NULL, NULL,
16648 /* 84 */ NULL, NULL, NULL, NULL,
16649 /* 88 */ NULL, NULL, "pfnacc", NULL,
16650 /* 8C */ NULL, NULL, "pfpnacc", NULL,
16651 /* 90 */ "pfcmpge", NULL, NULL, NULL,
16652 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
16653 /* 98 */ NULL, NULL, "pfsub", NULL,
16654 /* 9C */ NULL, NULL, "pfadd", NULL,
16655 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
16656 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
16657 /* A8 */ NULL, NULL, "pfsubr", NULL,
16658 /* AC */ NULL, NULL, "pfacc", NULL,
16659 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
16660 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
16661 /* B8 */ NULL, NULL, NULL, "pswapd",
16662 /* BC */ NULL, NULL, NULL, "pavgusb",
16663 /* C0 */ NULL, NULL, NULL, NULL,
16664 /* C4 */ NULL, NULL, NULL, NULL,
16665 /* C8 */ NULL, NULL, NULL, NULL,
16666 /* CC */ NULL, NULL, NULL, NULL,
16667 /* D0 */ NULL, NULL, NULL, NULL,
16668 /* D4 */ NULL, NULL, NULL, NULL,
16669 /* D8 */ NULL, NULL, NULL, NULL,
16670 /* DC */ NULL, NULL, NULL, NULL,
16671 /* E0 */ NULL, NULL, NULL, NULL,
16672 /* E4 */ NULL, NULL, NULL, NULL,
16673 /* E8 */ NULL, NULL, NULL, NULL,
16674 /* EC */ NULL, NULL, NULL, NULL,
16675 /* F0 */ NULL, NULL, NULL, NULL,
16676 /* F4 */ NULL, NULL, NULL, NULL,
16677 /* F8 */ NULL, NULL, NULL, NULL,
16678 /* FC */ NULL, NULL, NULL, NULL,
16682 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16684 const char *mnemonic;
16686 FETCH_DATA (the_info, codep + 1);
16687 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16688 place where an 8-bit immediate would normally go. ie. the last
16689 byte of the instruction. */
16690 obufp = mnemonicendp;
16691 mnemonic = Suffix3DNow[*codep++ & 0xff];
16693 oappend (mnemonic);
16696 /* Since a variable sized modrm/sib chunk is between the start
16697 of the opcode (0x0f0f) and the opcode suffix, we need to do
16698 all the modrm processing first, and don't know until now that
16699 we have a bad opcode. This necessitates some cleaning up. */
16700 op_out[0][0] = '\0';
16701 op_out[1][0] = '\0';
16704 mnemonicendp = obufp;
16707 static struct op simd_cmp_op[] =
16709 { STRING_COMMA_LEN ("eq") },
16710 { STRING_COMMA_LEN ("lt") },
16711 { STRING_COMMA_LEN ("le") },
16712 { STRING_COMMA_LEN ("unord") },
16713 { STRING_COMMA_LEN ("neq") },
16714 { STRING_COMMA_LEN ("nlt") },
16715 { STRING_COMMA_LEN ("nle") },
16716 { STRING_COMMA_LEN ("ord") }
16720 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16722 unsigned int cmp_type;
16724 FETCH_DATA (the_info, codep + 1);
16725 cmp_type = *codep++ & 0xff;
16726 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16729 char *p = mnemonicendp - 2;
16733 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16734 mnemonicendp += simd_cmp_op[cmp_type].len;
16738 /* We have a reserved extension byte. Output it directly. */
16739 scratchbuf[0] = '$';
16740 print_operand_value (scratchbuf + 1, 1, cmp_type);
16741 oappend_maybe_intel (scratchbuf);
16742 scratchbuf[0] = '\0';
16747 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16748 int sizeflag ATTRIBUTE_UNUSED)
16750 /* mwaitx %eax,%ecx,%ebx */
16753 const char **names = (address_mode == mode_64bit
16754 ? names64 : names32);
16755 strcpy (op_out[0], names[0]);
16756 strcpy (op_out[1], names[1]);
16757 strcpy (op_out[2], names[3]);
16758 two_source_ops = 1;
16760 /* Skip mod/rm byte. */
16766 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16767 int sizeflag ATTRIBUTE_UNUSED)
16769 /* mwait %eax,%ecx */
16772 const char **names = (address_mode == mode_64bit
16773 ? names64 : names32);
16774 strcpy (op_out[0], names[0]);
16775 strcpy (op_out[1], names[1]);
16776 two_source_ops = 1;
16778 /* Skip mod/rm byte. */
16784 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16785 int sizeflag ATTRIBUTE_UNUSED)
16787 /* monitor %eax,%ecx,%edx" */
16790 const char **op1_names;
16791 const char **names = (address_mode == mode_64bit
16792 ? names64 : names32);
16794 if (!(prefixes & PREFIX_ADDR))
16795 op1_names = (address_mode == mode_16bit
16796 ? names16 : names);
16799 /* Remove "addr16/addr32". */
16800 all_prefixes[last_addr_prefix] = 0;
16801 op1_names = (address_mode != mode_32bit
16802 ? names32 : names16);
16803 used_prefixes |= PREFIX_ADDR;
16805 strcpy (op_out[0], op1_names[0]);
16806 strcpy (op_out[1], names[1]);
16807 strcpy (op_out[2], names[2]);
16808 two_source_ops = 1;
16810 /* Skip mod/rm byte. */
16818 /* Throw away prefixes and 1st. opcode byte. */
16819 codep = insn_codep + 1;
16824 REP_Fixup (int bytemode, int sizeflag)
16826 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16828 if (prefixes & PREFIX_REPZ)
16829 all_prefixes[last_repz_prefix] = REP_PREFIX;
16836 OP_IMREG (bytemode, sizeflag);
16839 OP_ESreg (bytemode, sizeflag);
16842 OP_DSreg (bytemode, sizeflag);
16850 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16854 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16856 if (prefixes & PREFIX_REPNZ)
16857 all_prefixes[last_repnz_prefix] = BND_PREFIX;
16860 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16864 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16865 int sizeflag ATTRIBUTE_UNUSED)
16867 if (active_seg_prefix == PREFIX_DS
16868 && (address_mode != mode_64bit || last_data_prefix < 0))
16870 /* NOTRACK prefix is only valid on indirect branch instructions.
16871 NB: DATA prefix is unsupported for Intel64. */
16872 active_seg_prefix = 0;
16873 all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
16877 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16878 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16882 HLE_Fixup1 (int bytemode, int sizeflag)
16885 && (prefixes & PREFIX_LOCK) != 0)
16887 if (prefixes & PREFIX_REPZ)
16888 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16889 if (prefixes & PREFIX_REPNZ)
16890 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16893 OP_E (bytemode, sizeflag);
16896 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16897 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16901 HLE_Fixup2 (int bytemode, int sizeflag)
16903 if (modrm.mod != 3)
16905 if (prefixes & PREFIX_REPZ)
16906 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16907 if (prefixes & PREFIX_REPNZ)
16908 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16911 OP_E (bytemode, sizeflag);
16914 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16915 "xrelease" for memory operand. No check for LOCK prefix. */
16918 HLE_Fixup3 (int bytemode, int sizeflag)
16921 && last_repz_prefix > last_repnz_prefix
16922 && (prefixes & PREFIX_REPZ) != 0)
16923 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16925 OP_E (bytemode, sizeflag);
16929 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16934 /* Change cmpxchg8b to cmpxchg16b. */
16935 char *p = mnemonicendp - 2;
16936 mnemonicendp = stpcpy (p, "16b");
16939 else if ((prefixes & PREFIX_LOCK) != 0)
16941 if (prefixes & PREFIX_REPZ)
16942 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16943 if (prefixes & PREFIX_REPNZ)
16944 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16947 OP_M (bytemode, sizeflag);
16951 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16953 const char **names;
16957 switch (vex.length)
16971 oappend (names[reg]);
16975 CRC32_Fixup (int bytemode, int sizeflag)
16977 /* Add proper suffix to "crc32". */
16978 char *p = mnemonicendp;
16997 if (sizeflag & DFLAG)
17001 used_prefixes |= (prefixes & PREFIX_DATA);
17005 oappend (INTERNAL_DISASSEMBLER_ERROR);
17012 if (modrm.mod == 3)
17016 /* Skip mod/rm byte. */
17021 add = (rex & REX_B) ? 8 : 0;
17022 if (bytemode == b_mode)
17026 oappend (names8rex[modrm.rm + add]);
17028 oappend (names8[modrm.rm + add]);
17034 oappend (names64[modrm.rm + add]);
17035 else if ((prefixes & PREFIX_DATA))
17036 oappend (names16[modrm.rm + add]);
17038 oappend (names32[modrm.rm + add]);
17042 OP_E (bytemode, sizeflag);
17046 FXSAVE_Fixup (int bytemode, int sizeflag)
17048 /* Add proper suffix to "fxsave" and "fxrstor". */
17052 char *p = mnemonicendp;
17058 OP_M (bytemode, sizeflag);
17062 PCMPESTR_Fixup (int bytemode, int sizeflag)
17064 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
17067 char *p = mnemonicendp;
17072 else if (sizeflag & SUFFIX_ALWAYS)
17079 OP_EX (bytemode, sizeflag);
17082 /* Display the destination register operand for instructions with
17086 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17089 const char **names;
17097 reg = vex.register_specifier;
17098 if (address_mode != mode_64bit)
17100 else if (vex.evex && !vex.v)
17103 if (bytemode == vex_scalar_mode)
17105 oappend (names_xmm[reg]);
17109 switch (vex.length)
17116 case vex_vsib_q_w_dq_mode:
17117 case vex_vsib_q_w_d_mode:
17133 names = names_mask;
17147 case vex_vsib_q_w_dq_mode:
17148 case vex_vsib_q_w_d_mode:
17149 names = vex.w ? names_ymm : names_xmm;
17158 names = names_mask;
17161 /* See PR binutils/20893 for a reproducer. */
17173 oappend (names[reg]);
17176 /* Get the VEX immediate byte without moving codep. */
17178 static unsigned char
17179 get_vex_imm8 (int sizeflag, int opnum)
17181 int bytes_before_imm = 0;
17183 if (modrm.mod != 3)
17185 /* There are SIB/displacement bytes. */
17186 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17188 /* 32/64 bit address mode */
17189 int base = modrm.rm;
17191 /* Check SIB byte. */
17194 FETCH_DATA (the_info, codep + 1);
17196 /* When decoding the third source, don't increase
17197 bytes_before_imm as this has already been incremented
17198 by one in OP_E_memory while decoding the second
17201 bytes_before_imm++;
17204 /* Don't increase bytes_before_imm when decoding the third source,
17205 it has already been incremented by OP_E_memory while decoding
17206 the second source operand. */
17212 /* When modrm.rm == 5 or modrm.rm == 4 and base in
17213 SIB == 5, there is a 4 byte displacement. */
17215 /* No displacement. */
17217 /* Fall through. */
17219 /* 4 byte displacement. */
17220 bytes_before_imm += 4;
17223 /* 1 byte displacement. */
17224 bytes_before_imm++;
17231 /* 16 bit address mode */
17232 /* Don't increase bytes_before_imm when decoding the third source,
17233 it has already been incremented by OP_E_memory while decoding
17234 the second source operand. */
17240 /* When modrm.rm == 6, there is a 2 byte displacement. */
17242 /* No displacement. */
17244 /* Fall through. */
17246 /* 2 byte displacement. */
17247 bytes_before_imm += 2;
17250 /* 1 byte displacement: when decoding the third source,
17251 don't increase bytes_before_imm as this has already
17252 been incremented by one in OP_E_memory while decoding
17253 the second source operand. */
17255 bytes_before_imm++;
17263 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17264 return codep [bytes_before_imm];
17268 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17270 const char **names;
17272 if (reg == -1 && modrm.mod != 3)
17274 OP_E_memory (bytemode, sizeflag);
17286 if (address_mode != mode_64bit)
17290 switch (vex.length)
17301 oappend (names[reg]);
17305 OP_EX_VexImmW (int bytemode, int sizeflag)
17308 static unsigned char vex_imm8;
17310 if (vex_w_done == 0)
17314 /* Skip mod/rm byte. */
17318 vex_imm8 = get_vex_imm8 (sizeflag, 0);
17321 reg = vex_imm8 >> 4;
17323 OP_EX_VexReg (bytemode, sizeflag, reg);
17325 else if (vex_w_done == 1)
17330 reg = vex_imm8 >> 4;
17332 OP_EX_VexReg (bytemode, sizeflag, reg);
17336 /* Output the imm8 directly. */
17337 scratchbuf[0] = '$';
17338 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17339 oappend_maybe_intel (scratchbuf);
17340 scratchbuf[0] = '\0';
17346 OP_Vex_2src (int bytemode, int sizeflag)
17348 if (modrm.mod == 3)
17350 int reg = modrm.rm;
17354 oappend (names_xmm[reg]);
17359 && (bytemode == v_mode || bytemode == v_swap_mode))
17361 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17362 used_prefixes |= (prefixes & PREFIX_DATA);
17364 OP_E (bytemode, sizeflag);
17369 OP_Vex_2src_1 (int bytemode, int sizeflag)
17371 if (modrm.mod == 3)
17373 /* Skip mod/rm byte. */
17380 unsigned int reg = vex.register_specifier;
17382 if (address_mode != mode_64bit)
17384 oappend (names_xmm[reg]);
17387 OP_Vex_2src (bytemode, sizeflag);
17391 OP_Vex_2src_2 (int bytemode, int sizeflag)
17394 OP_Vex_2src (bytemode, sizeflag);
17397 unsigned int reg = vex.register_specifier;
17399 if (address_mode != mode_64bit)
17401 oappend (names_xmm[reg]);
17406 OP_EX_VexW (int bytemode, int sizeflag)
17412 /* Skip mod/rm byte. */
17417 reg = get_vex_imm8 (sizeflag, 0) >> 4;
17422 reg = get_vex_imm8 (sizeflag, 1) >> 4;
17425 OP_EX_VexReg (bytemode, sizeflag, reg);
17433 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17436 const char **names;
17438 FETCH_DATA (the_info, codep + 1);
17441 if (bytemode != x_mode)
17445 if (address_mode != mode_64bit)
17448 switch (vex.length)
17459 oappend (names[reg]);
17463 OP_XMM_VexW (int bytemode, int sizeflag)
17465 /* Turn off the REX.W bit since it is used for swapping operands
17468 OP_XMM (bytemode, sizeflag);
17472 OP_EX_Vex (int bytemode, int sizeflag)
17474 if (modrm.mod != 3)
17476 if (vex.register_specifier != 0)
17480 OP_EX (bytemode, sizeflag);
17484 OP_XMM_Vex (int bytemode, int sizeflag)
17486 if (modrm.mod != 3)
17488 if (vex.register_specifier != 0)
17492 OP_XMM (bytemode, sizeflag);
17496 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17498 switch (vex.length)
17501 mnemonicendp = stpcpy (obuf, "vzeroupper");
17504 mnemonicendp = stpcpy (obuf, "vzeroall");
17511 static struct op vex_cmp_op[] =
17513 { STRING_COMMA_LEN ("eq") },
17514 { STRING_COMMA_LEN ("lt") },
17515 { STRING_COMMA_LEN ("le") },
17516 { STRING_COMMA_LEN ("unord") },
17517 { STRING_COMMA_LEN ("neq") },
17518 { STRING_COMMA_LEN ("nlt") },
17519 { STRING_COMMA_LEN ("nle") },
17520 { STRING_COMMA_LEN ("ord") },
17521 { STRING_COMMA_LEN ("eq_uq") },
17522 { STRING_COMMA_LEN ("nge") },
17523 { STRING_COMMA_LEN ("ngt") },
17524 { STRING_COMMA_LEN ("false") },
17525 { STRING_COMMA_LEN ("neq_oq") },
17526 { STRING_COMMA_LEN ("ge") },
17527 { STRING_COMMA_LEN ("gt") },
17528 { STRING_COMMA_LEN ("true") },
17529 { STRING_COMMA_LEN ("eq_os") },
17530 { STRING_COMMA_LEN ("lt_oq") },
17531 { STRING_COMMA_LEN ("le_oq") },
17532 { STRING_COMMA_LEN ("unord_s") },
17533 { STRING_COMMA_LEN ("neq_us") },
17534 { STRING_COMMA_LEN ("nlt_uq") },
17535 { STRING_COMMA_LEN ("nle_uq") },
17536 { STRING_COMMA_LEN ("ord_s") },
17537 { STRING_COMMA_LEN ("eq_us") },
17538 { STRING_COMMA_LEN ("nge_uq") },
17539 { STRING_COMMA_LEN ("ngt_uq") },
17540 { STRING_COMMA_LEN ("false_os") },
17541 { STRING_COMMA_LEN ("neq_os") },
17542 { STRING_COMMA_LEN ("ge_oq") },
17543 { STRING_COMMA_LEN ("gt_oq") },
17544 { STRING_COMMA_LEN ("true_us") },
17548 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17550 unsigned int cmp_type;
17552 FETCH_DATA (the_info, codep + 1);
17553 cmp_type = *codep++ & 0xff;
17554 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17557 char *p = mnemonicendp - 2;
17561 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17562 mnemonicendp += vex_cmp_op[cmp_type].len;
17566 /* We have a reserved extension byte. Output it directly. */
17567 scratchbuf[0] = '$';
17568 print_operand_value (scratchbuf + 1, 1, cmp_type);
17569 oappend_maybe_intel (scratchbuf);
17570 scratchbuf[0] = '\0';
17575 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17576 int sizeflag ATTRIBUTE_UNUSED)
17578 unsigned int cmp_type;
17583 FETCH_DATA (the_info, codep + 1);
17584 cmp_type = *codep++ & 0xff;
17585 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17586 If it's the case, print suffix, otherwise - print the immediate. */
17587 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17592 char *p = mnemonicendp - 2;
17594 /* vpcmp* can have both one- and two-lettered suffix. */
17608 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17609 mnemonicendp += simd_cmp_op[cmp_type].len;
17613 /* We have a reserved extension byte. Output it directly. */
17614 scratchbuf[0] = '$';
17615 print_operand_value (scratchbuf + 1, 1, cmp_type);
17616 oappend_maybe_intel (scratchbuf);
17617 scratchbuf[0] = '\0';
17621 static const struct op xop_cmp_op[] =
17623 { STRING_COMMA_LEN ("lt") },
17624 { STRING_COMMA_LEN ("le") },
17625 { STRING_COMMA_LEN ("gt") },
17626 { STRING_COMMA_LEN ("ge") },
17627 { STRING_COMMA_LEN ("eq") },
17628 { STRING_COMMA_LEN ("neq") },
17629 { STRING_COMMA_LEN ("false") },
17630 { STRING_COMMA_LEN ("true") }
17634 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
17635 int sizeflag ATTRIBUTE_UNUSED)
17637 unsigned int cmp_type;
17639 FETCH_DATA (the_info, codep + 1);
17640 cmp_type = *codep++ & 0xff;
17641 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
17644 char *p = mnemonicendp - 2;
17646 /* vpcom* can have both one- and two-lettered suffix. */
17660 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
17661 mnemonicendp += xop_cmp_op[cmp_type].len;
17665 /* We have a reserved extension byte. Output it directly. */
17666 scratchbuf[0] = '$';
17667 print_operand_value (scratchbuf + 1, 1, cmp_type);
17668 oappend_maybe_intel (scratchbuf);
17669 scratchbuf[0] = '\0';
17673 static const struct op pclmul_op[] =
17675 { STRING_COMMA_LEN ("lql") },
17676 { STRING_COMMA_LEN ("hql") },
17677 { STRING_COMMA_LEN ("lqh") },
17678 { STRING_COMMA_LEN ("hqh") }
17682 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17683 int sizeflag ATTRIBUTE_UNUSED)
17685 unsigned int pclmul_type;
17687 FETCH_DATA (the_info, codep + 1);
17688 pclmul_type = *codep++ & 0xff;
17689 switch (pclmul_type)
17700 if (pclmul_type < ARRAY_SIZE (pclmul_op))
17703 char *p = mnemonicendp - 3;
17708 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17709 mnemonicendp += pclmul_op[pclmul_type].len;
17713 /* We have a reserved extension byte. Output it directly. */
17714 scratchbuf[0] = '$';
17715 print_operand_value (scratchbuf + 1, 1, pclmul_type);
17716 oappend_maybe_intel (scratchbuf);
17717 scratchbuf[0] = '\0';
17722 MOVBE_Fixup (int bytemode, int sizeflag)
17724 /* Add proper suffix to "movbe". */
17725 char *p = mnemonicendp;
17734 if (sizeflag & SUFFIX_ALWAYS)
17740 if (sizeflag & DFLAG)
17744 used_prefixes |= (prefixes & PREFIX_DATA);
17749 oappend (INTERNAL_DISASSEMBLER_ERROR);
17756 OP_M (bytemode, sizeflag);
17760 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17763 const char **names;
17765 /* Skip mod/rm byte. */
17779 oappend (names[reg]);
17783 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17785 const char **names;
17786 unsigned int reg = vex.register_specifier;
17793 if (address_mode != mode_64bit)
17795 oappend (names[reg]);
17799 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17802 || (bytemode != mask_mode && bytemode != mask_bd_mode))
17806 if ((rex & REX_R) != 0 || !vex.r)
17812 oappend (names_mask [modrm.reg]);
17816 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17819 || (bytemode != evex_rounding_mode
17820 && bytemode != evex_sae_mode))
17822 if (modrm.mod == 3 && vex.b)
17825 case evex_rounding_mode:
17826 oappend (names_rounding[vex.ll]);
17828 case evex_sae_mode: