1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
30 /* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
40 #include "opcode/i386.h"
41 #include "libiberty.h"
45 static int fetch_data (struct disassemble_info *, bfd_byte *);
46 static void ckprefix (void);
47 static const char *prefix_name (int, int);
48 static int print_insn (bfd_vma, disassemble_info *);
49 static void dofloat (int);
50 static void OP_ST (int, int);
51 static void OP_STi (int, int);
52 static int putop (const char *, int);
53 static void oappend (const char *);
54 static void append_seg (void);
55 static void OP_indirE (int, int);
56 static void print_operand_value (char *, int, bfd_vma);
57 static void OP_E_register (int, int);
58 static void OP_E_memory (int, int);
59 static void OP_E_extended (int, int);
60 static void print_displacement (char *, bfd_vma);
61 static void OP_E (int, int);
62 static void OP_G (int, int);
63 static bfd_vma get64 (void);
64 static bfd_signed_vma get32 (void);
65 static bfd_signed_vma get32s (void);
66 static int get16 (void);
67 static void set_op (bfd_vma, int);
68 static void OP_Skip_MODRM (int, int);
69 static void OP_REG (int, int);
70 static void OP_IMREG (int, int);
71 static void OP_I (int, int);
72 static void OP_I64 (int, int);
73 static void OP_sI (int, int);
74 static void OP_J (int, int);
75 static void OP_SEG (int, int);
76 static void OP_DIR (int, int);
77 static void OP_OFF (int, int);
78 static void OP_OFF64 (int, int);
79 static void ptr_reg (int, int);
80 static void OP_ESreg (int, int);
81 static void OP_DSreg (int, int);
82 static void OP_C (int, int);
83 static void OP_D (int, int);
84 static void OP_T (int, int);
85 static void OP_R (int, int);
86 static void OP_MMX (int, int);
87 static void OP_XMM (int, int);
88 static void OP_EM (int, int);
89 static void OP_EX (int, int);
90 static void OP_EMC (int,int);
91 static void OP_MXC (int,int);
92 static void OP_MS (int, int);
93 static void OP_XS (int, int);
94 static void OP_M (int, int);
95 static void OP_VEX (int, int);
96 static void OP_VEX_FMA (int, int);
97 static void OP_EX_Vex (int, int);
98 static void OP_EX_VexW (int, int);
99 static void OP_XMM_Vex (int, int);
100 static void OP_XMM_VexW (int, int);
101 static void OP_REG_VexI4 (int, int);
102 static void PCLMUL_Fixup (int, int);
103 static void VEXI4_Fixup (int, int);
104 static void VZERO_Fixup (int, int);
105 static void VCMP_Fixup (int, int);
106 static void OP_0f07 (int, int);
107 static void OP_Monitor (int, int);
108 static void OP_Mwait (int, int);
109 static void NOP_Fixup1 (int, int);
110 static void NOP_Fixup2 (int, int);
111 static void OP_3DNowSuffix (int, int);
112 static void CMP_Fixup (int, int);
113 static void BadOp (void);
114 static void REP_Fixup (int, int);
115 static void CMPXCHG8B_Fixup (int, int);
116 static void XMM_Fixup (int, int);
117 static void CRC32_Fixup (int, int);
119 static void MOVBE_Fixup (int, int);
122 /* Points to first byte not fetched. */
123 bfd_byte *max_fetched;
124 bfd_byte the_buffer[MAX_MNEM_SIZE];
137 enum address_mode address_mode;
139 /* Flags for the prefixes for the current instruction. See below. */
142 /* REX prefix the current instruction. See below. */
144 /* Bits of REX we've already used. */
146 /* Original REX prefix. */
147 static int rex_original;
148 /* REX bits in original REX prefix ignored. It may not be the same
149 as rex_original since some bits may not be ignored. */
150 static int rex_ignored;
151 /* Mark parts used in the REX prefix. When we are testing for
152 empty prefix (for 8bit register REX extension), just mask it
153 out. Otherwise test for REX bit is excuse for existence of REX
154 only in case value is nonzero. */
155 #define USED_REX(value) \
160 rex_used |= (value) | REX_OPCODE; \
163 rex_used |= REX_OPCODE; \
166 /* Flags for prefixes which we somehow handled when printing the
167 current instruction. */
168 static int used_prefixes;
170 /* Flags stored in PREFIXES. */
171 #define PREFIX_REPZ 1
172 #define PREFIX_REPNZ 2
173 #define PREFIX_LOCK 4
175 #define PREFIX_SS 0x10
176 #define PREFIX_DS 0x20
177 #define PREFIX_ES 0x40
178 #define PREFIX_FS 0x80
179 #define PREFIX_GS 0x100
180 #define PREFIX_DATA 0x200
181 #define PREFIX_ADDR 0x400
182 #define PREFIX_FWAIT 0x800
184 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
185 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
187 #define FETCH_DATA(info, addr) \
188 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
189 ? 1 : fetch_data ((info), (addr)))
192 fetch_data (struct disassemble_info *info, bfd_byte *addr)
195 struct dis_private *priv = (struct dis_private *) info->private_data;
196 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
198 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
199 status = (*info->read_memory_func) (start,
201 addr - priv->max_fetched,
207 /* If we did manage to read at least one byte, then
208 print_insn_i386 will do something sensible. Otherwise, print
209 an error. We do that here because this is where we know
211 if (priv->max_fetched == priv->the_buffer)
212 (*info->memory_error_func) (status, start, info);
213 longjmp (priv->bailout, 1);
216 priv->max_fetched = addr;
220 #define XX { NULL, 0 }
222 #define Eb { OP_E, b_mode }
223 #define EbS { OP_E, b_swap_mode }
224 #define Ev { OP_E, v_mode }
225 #define EvS { OP_E, v_swap_mode }
226 #define Ed { OP_E, d_mode }
227 #define Edq { OP_E, dq_mode }
228 #define Edqw { OP_E, dqw_mode }
229 #define Edqb { OP_E, dqb_mode }
230 #define Edqd { OP_E, dqd_mode }
231 #define Eq { OP_E, q_mode }
232 #define indirEv { OP_indirE, stack_v_mode }
233 #define indirEp { OP_indirE, f_mode }
234 #define stackEv { OP_E, stack_v_mode }
235 #define Em { OP_E, m_mode }
236 #define Ew { OP_E, w_mode }
237 #define M { OP_M, 0 } /* lea, lgdt, etc. */
238 #define Ma { OP_M, a_mode }
239 #define Mb { OP_M, b_mode }
240 #define Md { OP_M, d_mode }
241 #define Mo { OP_M, o_mode }
242 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
243 #define Mq { OP_M, q_mode }
244 #define Mx { OP_M, x_mode }
245 #define Mxmm { OP_M, xmm_mode }
246 #define Gb { OP_G, b_mode }
247 #define Gv { OP_G, v_mode }
248 #define Gd { OP_G, d_mode }
249 #define Gdq { OP_G, dq_mode }
250 #define Gm { OP_G, m_mode }
251 #define Gw { OP_G, w_mode }
252 #define Rd { OP_R, d_mode }
253 #define Rm { OP_R, m_mode }
254 #define Ib { OP_I, b_mode }
255 #define sIb { OP_sI, b_mode } /* sign extened byte */
256 #define Iv { OP_I, v_mode }
257 #define Iq { OP_I, q_mode }
258 #define Iv64 { OP_I64, v_mode }
259 #define Iw { OP_I, w_mode }
260 #define I1 { OP_I, const_1_mode }
261 #define Jb { OP_J, b_mode }
262 #define Jv { OP_J, v_mode }
263 #define Cm { OP_C, m_mode }
264 #define Dm { OP_D, m_mode }
265 #define Td { OP_T, d_mode }
266 #define Skip_MODRM { OP_Skip_MODRM, 0 }
268 #define RMeAX { OP_REG, eAX_reg }
269 #define RMeBX { OP_REG, eBX_reg }
270 #define RMeCX { OP_REG, eCX_reg }
271 #define RMeDX { OP_REG, eDX_reg }
272 #define RMeSP { OP_REG, eSP_reg }
273 #define RMeBP { OP_REG, eBP_reg }
274 #define RMeSI { OP_REG, eSI_reg }
275 #define RMeDI { OP_REG, eDI_reg }
276 #define RMrAX { OP_REG, rAX_reg }
277 #define RMrBX { OP_REG, rBX_reg }
278 #define RMrCX { OP_REG, rCX_reg }
279 #define RMrDX { OP_REG, rDX_reg }
280 #define RMrSP { OP_REG, rSP_reg }
281 #define RMrBP { OP_REG, rBP_reg }
282 #define RMrSI { OP_REG, rSI_reg }
283 #define RMrDI { OP_REG, rDI_reg }
284 #define RMAL { OP_REG, al_reg }
285 #define RMAL { OP_REG, al_reg }
286 #define RMCL { OP_REG, cl_reg }
287 #define RMDL { OP_REG, dl_reg }
288 #define RMBL { OP_REG, bl_reg }
289 #define RMAH { OP_REG, ah_reg }
290 #define RMCH { OP_REG, ch_reg }
291 #define RMDH { OP_REG, dh_reg }
292 #define RMBH { OP_REG, bh_reg }
293 #define RMAX { OP_REG, ax_reg }
294 #define RMDX { OP_REG, dx_reg }
296 #define eAX { OP_IMREG, eAX_reg }
297 #define eBX { OP_IMREG, eBX_reg }
298 #define eCX { OP_IMREG, eCX_reg }
299 #define eDX { OP_IMREG, eDX_reg }
300 #define eSP { OP_IMREG, eSP_reg }
301 #define eBP { OP_IMREG, eBP_reg }
302 #define eSI { OP_IMREG, eSI_reg }
303 #define eDI { OP_IMREG, eDI_reg }
304 #define AL { OP_IMREG, al_reg }
305 #define CL { OP_IMREG, cl_reg }
306 #define DL { OP_IMREG, dl_reg }
307 #define BL { OP_IMREG, bl_reg }
308 #define AH { OP_IMREG, ah_reg }
309 #define CH { OP_IMREG, ch_reg }
310 #define DH { OP_IMREG, dh_reg }
311 #define BH { OP_IMREG, bh_reg }
312 #define AX { OP_IMREG, ax_reg }
313 #define DX { OP_IMREG, dx_reg }
314 #define zAX { OP_IMREG, z_mode_ax_reg }
315 #define indirDX { OP_IMREG, indir_dx_reg }
317 #define Sw { OP_SEG, w_mode }
318 #define Sv { OP_SEG, v_mode }
319 #define Ap { OP_DIR, 0 }
320 #define Ob { OP_OFF64, b_mode }
321 #define Ov { OP_OFF64, v_mode }
322 #define Xb { OP_DSreg, eSI_reg }
323 #define Xv { OP_DSreg, eSI_reg }
324 #define Xz { OP_DSreg, eSI_reg }
325 #define Yb { OP_ESreg, eDI_reg }
326 #define Yv { OP_ESreg, eDI_reg }
327 #define DSBX { OP_DSreg, eBX_reg }
329 #define es { OP_REG, es_reg }
330 #define ss { OP_REG, ss_reg }
331 #define cs { OP_REG, cs_reg }
332 #define ds { OP_REG, ds_reg }
333 #define fs { OP_REG, fs_reg }
334 #define gs { OP_REG, gs_reg }
336 #define MX { OP_MMX, 0 }
337 #define XM { OP_XMM, 0 }
338 #define XMM { OP_XMM, xmm_mode }
339 #define EM { OP_EM, v_mode }
340 #define EMS { OP_EM, v_swap_mode }
341 #define EMd { OP_EM, d_mode }
342 #define EMx { OP_EM, x_mode }
343 #define EXw { OP_EX, w_mode }
344 #define EXd { OP_EX, d_mode }
345 #define EXdS { OP_EX, d_swap_mode }
346 #define EXq { OP_EX, q_mode }
347 #define EXqS { OP_EX, q_swap_mode }
348 #define EXx { OP_EX, x_mode }
349 #define EXxS { OP_EX, x_swap_mode }
350 #define EXxmm { OP_EX, xmm_mode }
351 #define EXxmmq { OP_EX, xmmq_mode }
352 #define EXymmq { OP_EX, ymmq_mode }
353 #define EXVexWdq { OP_EX, vex_w_dq_mode }
354 #define MS { OP_MS, v_mode }
355 #define XS { OP_XS, v_mode }
356 #define EMCq { OP_EMC, q_mode }
357 #define MXC { OP_MXC, 0 }
358 #define OPSUF { OP_3DNowSuffix, 0 }
359 #define CMP { CMP_Fixup, 0 }
360 #define XMM0 { XMM_Fixup, 0 }
362 #define Vex { OP_VEX, vex_mode }
363 #define Vex128 { OP_VEX, vex128_mode }
364 #define Vex256 { OP_VEX, vex256_mode }
365 #define VexI4 { VEXI4_Fixup, 0}
366 #define VexFMA { OP_VEX_FMA, vex_mode }
367 #define Vex128FMA { OP_VEX_FMA, vex128_mode }
368 #define EXdVex { OP_EX_Vex, d_mode }
369 #define EXdVexS { OP_EX_Vex, d_swap_mode }
370 #define EXqVex { OP_EX_Vex, q_mode }
371 #define EXqVexS { OP_EX_Vex, q_swap_mode }
372 #define EXVexW { OP_EX_VexW, x_mode }
373 #define EXdVexW { OP_EX_VexW, d_mode }
374 #define EXqVexW { OP_EX_VexW, q_mode }
375 #define XMVex { OP_XMM_Vex, 0 }
376 #define XMVexW { OP_XMM_VexW, 0 }
377 #define XMVexI4 { OP_REG_VexI4, x_mode }
378 #define PCLMUL { PCLMUL_Fixup, 0 }
379 #define VZERO { VZERO_Fixup, 0 }
380 #define VCMP { VCMP_Fixup, 0 }
382 /* Used handle "rep" prefix for string instructions. */
383 #define Xbr { REP_Fixup, eSI_reg }
384 #define Xvr { REP_Fixup, eSI_reg }
385 #define Ybr { REP_Fixup, eDI_reg }
386 #define Yvr { REP_Fixup, eDI_reg }
387 #define Yzr { REP_Fixup, eDI_reg }
388 #define indirDXr { REP_Fixup, indir_dx_reg }
389 #define ALr { REP_Fixup, al_reg }
390 #define eAXr { REP_Fixup, eAX_reg }
392 #define cond_jump_flag { NULL, cond_jump_mode }
393 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
395 /* bits in sizeflag */
396 #define SUFFIX_ALWAYS 4
402 /* byte operand with operand swapped */
403 #define b_swap_mode (b_mode + 1)
404 /* operand size depends on prefixes */
405 #define v_mode (b_swap_mode + 1)
406 /* operand size depends on prefixes with operand swapped */
407 #define v_swap_mode (v_mode + 1)
409 #define w_mode (v_swap_mode + 1)
410 /* double word operand */
411 #define d_mode (w_mode + 1)
412 /* double word operand with operand swapped */
413 #define d_swap_mode (d_mode + 1)
414 /* quad word operand */
415 #define q_mode (d_swap_mode + 1)
416 /* quad word operand with operand swapped */
417 #define q_swap_mode (q_mode + 1)
418 /* ten-byte operand */
419 #define t_mode (q_swap_mode + 1)
420 /* 16-byte XMM or 32-byte YMM operand */
421 #define x_mode (t_mode + 1)
422 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
423 #define x_swap_mode (x_mode + 1)
424 /* 16-byte XMM operand */
425 #define xmm_mode (x_swap_mode + 1)
426 /* 16-byte XMM or quad word operand */
427 #define xmmq_mode (xmm_mode + 1)
428 /* 32-byte YMM or quad word operand */
429 #define ymmq_mode (xmmq_mode + 1)
430 /* d_mode in 32bit, q_mode in 64bit mode. */
431 #define m_mode (ymmq_mode + 1)
432 /* pair of v_mode operands */
433 #define a_mode (m_mode + 1)
434 #define cond_jump_mode (a_mode + 1)
435 #define loop_jcxz_mode (cond_jump_mode + 1)
436 /* operand size depends on REX prefixes. */
437 #define dq_mode (loop_jcxz_mode + 1)
438 /* registers like dq_mode, memory like w_mode. */
439 #define dqw_mode (dq_mode + 1)
440 /* 4- or 6-byte pointer operand */
441 #define f_mode (dqw_mode + 1)
442 #define const_1_mode (f_mode + 1)
443 /* v_mode for stack-related opcodes. */
444 #define stack_v_mode (const_1_mode + 1)
445 /* non-quad operand size depends on prefixes */
446 #define z_mode (stack_v_mode + 1)
447 /* 16-byte operand */
448 #define o_mode (z_mode + 1)
449 /* registers like dq_mode, memory like b_mode. */
450 #define dqb_mode (o_mode + 1)
451 /* registers like dq_mode, memory like d_mode. */
452 #define dqd_mode (dqb_mode + 1)
453 /* normal vex mode */
454 #define vex_mode (dqd_mode + 1)
455 /* 128bit vex mode */
456 #define vex128_mode (vex_mode + 1)
457 /* 256bit vex mode */
458 #define vex256_mode (vex128_mode + 1)
459 /* operand size depends on the VEX.W bit. */
460 #define vex_w_dq_mode (vex256_mode + 1)
462 #define es_reg (vex_w_dq_mode + 1)
463 #define cs_reg (es_reg + 1)
464 #define ss_reg (cs_reg + 1)
465 #define ds_reg (ss_reg + 1)
466 #define fs_reg (ds_reg + 1)
467 #define gs_reg (fs_reg + 1)
469 #define eAX_reg (gs_reg + 1)
470 #define eCX_reg (eAX_reg + 1)
471 #define eDX_reg (eCX_reg + 1)
472 #define eBX_reg (eDX_reg + 1)
473 #define eSP_reg (eBX_reg + 1)
474 #define eBP_reg (eSP_reg + 1)
475 #define eSI_reg (eBP_reg + 1)
476 #define eDI_reg (eSI_reg + 1)
478 #define al_reg (eDI_reg + 1)
479 #define cl_reg (al_reg + 1)
480 #define dl_reg (cl_reg + 1)
481 #define bl_reg (dl_reg + 1)
482 #define ah_reg (bl_reg + 1)
483 #define ch_reg (ah_reg + 1)
484 #define dh_reg (ch_reg + 1)
485 #define bh_reg (dh_reg + 1)
487 #define ax_reg (bh_reg + 1)
488 #define cx_reg (ax_reg + 1)
489 #define dx_reg (cx_reg + 1)
490 #define bx_reg (dx_reg + 1)
491 #define sp_reg (bx_reg + 1)
492 #define bp_reg (sp_reg + 1)
493 #define si_reg (bp_reg + 1)
494 #define di_reg (si_reg + 1)
496 #define rAX_reg (di_reg + 1)
497 #define rCX_reg (rAX_reg + 1)
498 #define rDX_reg (rCX_reg + 1)
499 #define rBX_reg (rDX_reg + 1)
500 #define rSP_reg (rBX_reg + 1)
501 #define rBP_reg (rSP_reg + 1)
502 #define rSI_reg (rBP_reg + 1)
503 #define rDI_reg (rSI_reg + 1)
505 #define z_mode_ax_reg (rDI_reg + 1)
506 #define indir_dx_reg (z_mode_ax_reg + 1)
510 #define USE_REG_TABLE (FLOATCODE + 1)
511 #define USE_MOD_TABLE (USE_REG_TABLE + 1)
512 #define USE_RM_TABLE (USE_MOD_TABLE + 1)
513 #define USE_PREFIX_TABLE (USE_RM_TABLE + 1)
514 #define USE_X86_64_TABLE (USE_PREFIX_TABLE + 1)
515 #define USE_3BYTE_TABLE (USE_X86_64_TABLE + 1)
516 #define USE_VEX_C4_TABLE (USE_3BYTE_TABLE + 1)
517 #define USE_VEX_C5_TABLE (USE_VEX_C4_TABLE + 1)
518 #define USE_VEX_LEN_TABLE (USE_VEX_C5_TABLE + 1)
520 #define FLOAT NULL, { { NULL, FLOATCODE } }
522 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
523 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
524 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
525 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
526 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
527 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
528 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
529 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
530 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
531 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
534 #define REG_81 (REG_80 + 1)
535 #define REG_82 (REG_81 + 1)
536 #define REG_8F (REG_82 + 1)
537 #define REG_C0 (REG_8F + 1)
538 #define REG_C1 (REG_C0 + 1)
539 #define REG_C6 (REG_C1 + 1)
540 #define REG_C7 (REG_C6 + 1)
541 #define REG_D0 (REG_C7 + 1)
542 #define REG_D1 (REG_D0 + 1)
543 #define REG_D2 (REG_D1 + 1)
544 #define REG_D3 (REG_D2 + 1)
545 #define REG_F6 (REG_D3 + 1)
546 #define REG_F7 (REG_F6 + 1)
547 #define REG_FE (REG_F7 + 1)
548 #define REG_FF (REG_FE + 1)
549 #define REG_0F00 (REG_FF + 1)
550 #define REG_0F01 (REG_0F00 + 1)
551 #define REG_0F0D (REG_0F01 + 1)
552 #define REG_0F18 (REG_0F0D + 1)
553 #define REG_0F71 (REG_0F18 + 1)
554 #define REG_0F72 (REG_0F71 + 1)
555 #define REG_0F73 (REG_0F72 + 1)
556 #define REG_0FA6 (REG_0F73 + 1)
557 #define REG_0FA7 (REG_0FA6 + 1)
558 #define REG_0FAE (REG_0FA7 + 1)
559 #define REG_0FBA (REG_0FAE + 1)
560 #define REG_0FC7 (REG_0FBA + 1)
561 #define REG_VEX_71 (REG_0FC7 + 1)
562 #define REG_VEX_72 (REG_VEX_71 + 1)
563 #define REG_VEX_73 (REG_VEX_72 + 1)
564 #define REG_VEX_AE (REG_VEX_73 + 1)
567 #define MOD_0F01_REG_0 (MOD_8D + 1)
568 #define MOD_0F01_REG_1 (MOD_0F01_REG_0 + 1)
569 #define MOD_0F01_REG_2 (MOD_0F01_REG_1 + 1)
570 #define MOD_0F01_REG_3 (MOD_0F01_REG_2 + 1)
571 #define MOD_0F01_REG_7 (MOD_0F01_REG_3 + 1)
572 #define MOD_0F12_PREFIX_0 (MOD_0F01_REG_7 + 1)
573 #define MOD_0F13 (MOD_0F12_PREFIX_0 + 1)
574 #define MOD_0F16_PREFIX_0 (MOD_0F13 + 1)
575 #define MOD_0F17 (MOD_0F16_PREFIX_0 + 1)
576 #define MOD_0F18_REG_0 (MOD_0F17 + 1)
577 #define MOD_0F18_REG_1 (MOD_0F18_REG_0 + 1)
578 #define MOD_0F18_REG_2 (MOD_0F18_REG_1 + 1)
579 #define MOD_0F18_REG_3 (MOD_0F18_REG_2 + 1)
580 #define MOD_0F20 (MOD_0F18_REG_3 + 1)
581 #define MOD_0F21 (MOD_0F20 + 1)
582 #define MOD_0F22 (MOD_0F21 + 1)
583 #define MOD_0F23 (MOD_0F22 + 1)
584 #define MOD_0F24 (MOD_0F23 + 1)
585 #define MOD_0F26 (MOD_0F24 + 1)
586 #define MOD_0F2B_PREFIX_0 (MOD_0F26 + 1)
587 #define MOD_0F2B_PREFIX_1 (MOD_0F2B_PREFIX_0 + 1)
588 #define MOD_0F2B_PREFIX_2 (MOD_0F2B_PREFIX_1 + 1)
589 #define MOD_0F2B_PREFIX_3 (MOD_0F2B_PREFIX_2 + 1)
590 #define MOD_0F51 (MOD_0F2B_PREFIX_3 + 1)
591 #define MOD_0F71_REG_2 (MOD_0F51 + 1)
592 #define MOD_0F71_REG_4 (MOD_0F71_REG_2 + 1)
593 #define MOD_0F71_REG_6 (MOD_0F71_REG_4 + 1)
594 #define MOD_0F72_REG_2 (MOD_0F71_REG_6 + 1)
595 #define MOD_0F72_REG_4 (MOD_0F72_REG_2 + 1)
596 #define MOD_0F72_REG_6 (MOD_0F72_REG_4 + 1)
597 #define MOD_0F73_REG_2 (MOD_0F72_REG_6 + 1)
598 #define MOD_0F73_REG_3 (MOD_0F73_REG_2 + 1)
599 #define MOD_0F73_REG_6 (MOD_0F73_REG_3 + 1)
600 #define MOD_0F73_REG_7 (MOD_0F73_REG_6 + 1)
601 #define MOD_0FAE_REG_0 (MOD_0F73_REG_7 + 1)
602 #define MOD_0FAE_REG_1 (MOD_0FAE_REG_0 + 1)
603 #define MOD_0FAE_REG_2 (MOD_0FAE_REG_1 + 1)
604 #define MOD_0FAE_REG_3 (MOD_0FAE_REG_2 + 1)
605 #define MOD_0FAE_REG_4 (MOD_0FAE_REG_3 + 1)
606 #define MOD_0FAE_REG_5 (MOD_0FAE_REG_4 + 1)
607 #define MOD_0FAE_REG_6 (MOD_0FAE_REG_5 + 1)
608 #define MOD_0FAE_REG_7 (MOD_0FAE_REG_6 + 1)
609 #define MOD_0FB2 (MOD_0FAE_REG_7 + 1)
610 #define MOD_0FB4 (MOD_0FB2 + 1)
611 #define MOD_0FB5 (MOD_0FB4 + 1)
612 #define MOD_0FC7_REG_6 (MOD_0FB5 + 1)
613 #define MOD_0FC7_REG_7 (MOD_0FC7_REG_6 + 1)
614 #define MOD_0FD7 (MOD_0FC7_REG_7 + 1)
615 #define MOD_0FE7_PREFIX_2 (MOD_0FD7 + 1)
616 #define MOD_0FF0_PREFIX_3 (MOD_0FE7_PREFIX_2 + 1)
617 #define MOD_0F382A_PREFIX_2 (MOD_0FF0_PREFIX_3 + 1)
618 #define MOD_62_32BIT (MOD_0F382A_PREFIX_2 + 1)
619 #define MOD_C4_32BIT (MOD_62_32BIT + 1)
620 #define MOD_C5_32BIT (MOD_C4_32BIT + 1)
621 #define MOD_VEX_12_PREFIX_0 (MOD_C5_32BIT + 1)
622 #define MOD_VEX_13 (MOD_VEX_12_PREFIX_0 + 1)
623 #define MOD_VEX_16_PREFIX_0 (MOD_VEX_13 + 1)
624 #define MOD_VEX_17 (MOD_VEX_16_PREFIX_0 + 1)
625 #define MOD_VEX_2B (MOD_VEX_17 + 1)
626 #define MOD_VEX_51 (MOD_VEX_2B + 1)
627 #define MOD_VEX_71_REG_2 (MOD_VEX_51 + 1)
628 #define MOD_VEX_71_REG_4 (MOD_VEX_71_REG_2 + 1)
629 #define MOD_VEX_71_REG_6 (MOD_VEX_71_REG_4 + 1)
630 #define MOD_VEX_72_REG_2 (MOD_VEX_71_REG_6 + 1)
631 #define MOD_VEX_72_REG_4 (MOD_VEX_72_REG_2 + 1)
632 #define MOD_VEX_72_REG_6 (MOD_VEX_72_REG_4 + 1)
633 #define MOD_VEX_73_REG_2 (MOD_VEX_72_REG_6 + 1)
634 #define MOD_VEX_73_REG_3 (MOD_VEX_73_REG_2 + 1)
635 #define MOD_VEX_73_REG_6 (MOD_VEX_73_REG_3 + 1)
636 #define MOD_VEX_73_REG_7 (MOD_VEX_73_REG_6 + 1)
637 #define MOD_VEX_AE_REG_2 (MOD_VEX_73_REG_7 + 1)
638 #define MOD_VEX_AE_REG_3 (MOD_VEX_AE_REG_2 + 1)
639 #define MOD_VEX_D7_PREFIX_2 (MOD_VEX_AE_REG_3 + 1)
640 #define MOD_VEX_E7_PREFIX_2 (MOD_VEX_D7_PREFIX_2 + 1)
641 #define MOD_VEX_F0_PREFIX_3 (MOD_VEX_E7_PREFIX_2 + 1)
642 #define MOD_VEX_3818_PREFIX_2 (MOD_VEX_F0_PREFIX_3 + 1)
643 #define MOD_VEX_3819_PREFIX_2 (MOD_VEX_3818_PREFIX_2 + 1)
644 #define MOD_VEX_381A_PREFIX_2 (MOD_VEX_3819_PREFIX_2 + 1)
645 #define MOD_VEX_382A_PREFIX_2 (MOD_VEX_381A_PREFIX_2 + 1)
646 #define MOD_VEX_382C_PREFIX_2 (MOD_VEX_382A_PREFIX_2 + 1)
647 #define MOD_VEX_382D_PREFIX_2 (MOD_VEX_382C_PREFIX_2 + 1)
648 #define MOD_VEX_382E_PREFIX_2 (MOD_VEX_382D_PREFIX_2 + 1)
649 #define MOD_VEX_382F_PREFIX_2 (MOD_VEX_382E_PREFIX_2 + 1)
651 #define RM_0F01_REG_0 0
652 #define RM_0F01_REG_1 (RM_0F01_REG_0 + 1)
653 #define RM_0F01_REG_2 (RM_0F01_REG_1 + 1)
654 #define RM_0F01_REG_3 (RM_0F01_REG_2 + 1)
655 #define RM_0F01_REG_7 (RM_0F01_REG_3 + 1)
656 #define RM_0FAE_REG_5 (RM_0F01_REG_7 + 1)
657 #define RM_0FAE_REG_6 (RM_0FAE_REG_5 + 1)
658 #define RM_0FAE_REG_7 (RM_0FAE_REG_6 + 1)
661 #define PREFIX_0F10 (PREFIX_90 + 1)
662 #define PREFIX_0F11 (PREFIX_0F10 + 1)
663 #define PREFIX_0F12 (PREFIX_0F11 + 1)
664 #define PREFIX_0F16 (PREFIX_0F12 + 1)
665 #define PREFIX_0F2A (PREFIX_0F16 + 1)
666 #define PREFIX_0F2B (PREFIX_0F2A + 1)
667 #define PREFIX_0F2C (PREFIX_0F2B + 1)
668 #define PREFIX_0F2D (PREFIX_0F2C + 1)
669 #define PREFIX_0F2E (PREFIX_0F2D + 1)
670 #define PREFIX_0F2F (PREFIX_0F2E + 1)
671 #define PREFIX_0F51 (PREFIX_0F2F + 1)
672 #define PREFIX_0F52 (PREFIX_0F51 + 1)
673 #define PREFIX_0F53 (PREFIX_0F52 + 1)
674 #define PREFIX_0F58 (PREFIX_0F53 + 1)
675 #define PREFIX_0F59 (PREFIX_0F58 + 1)
676 #define PREFIX_0F5A (PREFIX_0F59 + 1)
677 #define PREFIX_0F5B (PREFIX_0F5A + 1)
678 #define PREFIX_0F5C (PREFIX_0F5B + 1)
679 #define PREFIX_0F5D (PREFIX_0F5C + 1)
680 #define PREFIX_0F5E (PREFIX_0F5D + 1)
681 #define PREFIX_0F5F (PREFIX_0F5E + 1)
682 #define PREFIX_0F60 (PREFIX_0F5F + 1)
683 #define PREFIX_0F61 (PREFIX_0F60 + 1)
684 #define PREFIX_0F62 (PREFIX_0F61 + 1)
685 #define PREFIX_0F6C (PREFIX_0F62 + 1)
686 #define PREFIX_0F6D (PREFIX_0F6C + 1)
687 #define PREFIX_0F6F (PREFIX_0F6D + 1)
688 #define PREFIX_0F70 (PREFIX_0F6F + 1)
689 #define PREFIX_0F73_REG_3 (PREFIX_0F70 + 1)
690 #define PREFIX_0F73_REG_7 (PREFIX_0F73_REG_3 + 1)
691 #define PREFIX_0F78 (PREFIX_0F73_REG_7 + 1)
692 #define PREFIX_0F79 (PREFIX_0F78 + 1)
693 #define PREFIX_0F7C (PREFIX_0F79 + 1)
694 #define PREFIX_0F7D (PREFIX_0F7C + 1)
695 #define PREFIX_0F7E (PREFIX_0F7D + 1)
696 #define PREFIX_0F7F (PREFIX_0F7E + 1)
697 #define PREFIX_0FB8 (PREFIX_0F7F + 1)
698 #define PREFIX_0FBD (PREFIX_0FB8 + 1)
699 #define PREFIX_0FC2 (PREFIX_0FBD + 1)
700 #define PREFIX_0FC3 (PREFIX_0FC2 + 1)
701 #define PREFIX_0FC7_REG_6 (PREFIX_0FC3 + 1)
702 #define PREFIX_0FD0 (PREFIX_0FC7_REG_6 + 1)
703 #define PREFIX_0FD6 (PREFIX_0FD0 + 1)
704 #define PREFIX_0FE6 (PREFIX_0FD6 + 1)
705 #define PREFIX_0FE7 (PREFIX_0FE6 + 1)
706 #define PREFIX_0FF0 (PREFIX_0FE7 + 1)
707 #define PREFIX_0FF7 (PREFIX_0FF0 + 1)
708 #define PREFIX_0F3810 (PREFIX_0FF7 + 1)
709 #define PREFIX_0F3814 (PREFIX_0F3810 + 1)
710 #define PREFIX_0F3815 (PREFIX_0F3814 + 1)
711 #define PREFIX_0F3817 (PREFIX_0F3815 + 1)
712 #define PREFIX_0F3820 (PREFIX_0F3817 + 1)
713 #define PREFIX_0F3821 (PREFIX_0F3820 + 1)
714 #define PREFIX_0F3822 (PREFIX_0F3821 + 1)
715 #define PREFIX_0F3823 (PREFIX_0F3822 + 1)
716 #define PREFIX_0F3824 (PREFIX_0F3823 + 1)
717 #define PREFIX_0F3825 (PREFIX_0F3824 + 1)
718 #define PREFIX_0F3828 (PREFIX_0F3825 + 1)
719 #define PREFIX_0F3829 (PREFIX_0F3828 + 1)
720 #define PREFIX_0F382A (PREFIX_0F3829 + 1)
721 #define PREFIX_0F382B (PREFIX_0F382A + 1)
722 #define PREFIX_0F3830 (PREFIX_0F382B + 1)
723 #define PREFIX_0F3831 (PREFIX_0F3830 + 1)
724 #define PREFIX_0F3832 (PREFIX_0F3831 + 1)
725 #define PREFIX_0F3833 (PREFIX_0F3832 + 1)
726 #define PREFIX_0F3834 (PREFIX_0F3833 + 1)
727 #define PREFIX_0F3835 (PREFIX_0F3834 + 1)
728 #define PREFIX_0F3837 (PREFIX_0F3835 + 1)
729 #define PREFIX_0F3838 (PREFIX_0F3837 + 1)
730 #define PREFIX_0F3839 (PREFIX_0F3838 + 1)
731 #define PREFIX_0F383A (PREFIX_0F3839 + 1)
732 #define PREFIX_0F383B (PREFIX_0F383A + 1)
733 #define PREFIX_0F383C (PREFIX_0F383B + 1)
734 #define PREFIX_0F383D (PREFIX_0F383C + 1)
735 #define PREFIX_0F383E (PREFIX_0F383D + 1)
736 #define PREFIX_0F383F (PREFIX_0F383E + 1)
737 #define PREFIX_0F3840 (PREFIX_0F383F + 1)
738 #define PREFIX_0F3841 (PREFIX_0F3840 + 1)
739 #define PREFIX_0F3880 (PREFIX_0F3841 + 1)
740 #define PREFIX_0F3881 (PREFIX_0F3880 + 1)
741 #define PREFIX_0F38DB (PREFIX_0F3881 + 1)
742 #define PREFIX_0F38DC (PREFIX_0F38DB + 1)
743 #define PREFIX_0F38DD (PREFIX_0F38DC + 1)
744 #define PREFIX_0F38DE (PREFIX_0F38DD + 1)
745 #define PREFIX_0F38DF (PREFIX_0F38DE + 1)
746 #define PREFIX_0F38F0 (PREFIX_0F38DF + 1)
747 #define PREFIX_0F38F1 (PREFIX_0F38F0 + 1)
748 #define PREFIX_0F3A08 (PREFIX_0F38F1 + 1)
749 #define PREFIX_0F3A09 (PREFIX_0F3A08 + 1)
750 #define PREFIX_0F3A0A (PREFIX_0F3A09 + 1)
751 #define PREFIX_0F3A0B (PREFIX_0F3A0A + 1)
752 #define PREFIX_0F3A0C (PREFIX_0F3A0B + 1)
753 #define PREFIX_0F3A0D (PREFIX_0F3A0C + 1)
754 #define PREFIX_0F3A0E (PREFIX_0F3A0D + 1)
755 #define PREFIX_0F3A14 (PREFIX_0F3A0E + 1)
756 #define PREFIX_0F3A15 (PREFIX_0F3A14 + 1)
757 #define PREFIX_0F3A16 (PREFIX_0F3A15 + 1)
758 #define PREFIX_0F3A17 (PREFIX_0F3A16 + 1)
759 #define PREFIX_0F3A20 (PREFIX_0F3A17 + 1)
760 #define PREFIX_0F3A21 (PREFIX_0F3A20 + 1)
761 #define PREFIX_0F3A22 (PREFIX_0F3A21 + 1)
762 #define PREFIX_0F3A40 (PREFIX_0F3A22 + 1)
763 #define PREFIX_0F3A41 (PREFIX_0F3A40 + 1)
764 #define PREFIX_0F3A42 (PREFIX_0F3A41 + 1)
765 #define PREFIX_0F3A44 (PREFIX_0F3A42 + 1)
766 #define PREFIX_0F3A60 (PREFIX_0F3A44 + 1)
767 #define PREFIX_0F3A61 (PREFIX_0F3A60 + 1)
768 #define PREFIX_0F3A62 (PREFIX_0F3A61 + 1)
769 #define PREFIX_0F3A63 (PREFIX_0F3A62 + 1)
770 #define PREFIX_0F3ADF (PREFIX_0F3A63 + 1)
771 #define PREFIX_VEX_10 (PREFIX_0F3ADF + 1)
772 #define PREFIX_VEX_11 (PREFIX_VEX_10 + 1)
773 #define PREFIX_VEX_12 (PREFIX_VEX_11 + 1)
774 #define PREFIX_VEX_16 (PREFIX_VEX_12 + 1)
775 #define PREFIX_VEX_2A (PREFIX_VEX_16 + 1)
776 #define PREFIX_VEX_2C (PREFIX_VEX_2A + 1)
777 #define PREFIX_VEX_2D (PREFIX_VEX_2C + 1)
778 #define PREFIX_VEX_2E (PREFIX_VEX_2D + 1)
779 #define PREFIX_VEX_2F (PREFIX_VEX_2E + 1)
780 #define PREFIX_VEX_51 (PREFIX_VEX_2F + 1)
781 #define PREFIX_VEX_52 (PREFIX_VEX_51 + 1)
782 #define PREFIX_VEX_53 (PREFIX_VEX_52 + 1)
783 #define PREFIX_VEX_58 (PREFIX_VEX_53 + 1)
784 #define PREFIX_VEX_59 (PREFIX_VEX_58 + 1)
785 #define PREFIX_VEX_5A (PREFIX_VEX_59 + 1)
786 #define PREFIX_VEX_5B (PREFIX_VEX_5A + 1)
787 #define PREFIX_VEX_5C (PREFIX_VEX_5B + 1)
788 #define PREFIX_VEX_5D (PREFIX_VEX_5C + 1)
789 #define PREFIX_VEX_5E (PREFIX_VEX_5D + 1)
790 #define PREFIX_VEX_5F (PREFIX_VEX_5E + 1)
791 #define PREFIX_VEX_60 (PREFIX_VEX_5F + 1)
792 #define PREFIX_VEX_61 (PREFIX_VEX_60 + 1)
793 #define PREFIX_VEX_62 (PREFIX_VEX_61 + 1)
794 #define PREFIX_VEX_63 (PREFIX_VEX_62 + 1)
795 #define PREFIX_VEX_64 (PREFIX_VEX_63 + 1)
796 #define PREFIX_VEX_65 (PREFIX_VEX_64 + 1)
797 #define PREFIX_VEX_66 (PREFIX_VEX_65 + 1)
798 #define PREFIX_VEX_67 (PREFIX_VEX_66 + 1)
799 #define PREFIX_VEX_68 (PREFIX_VEX_67 + 1)
800 #define PREFIX_VEX_69 (PREFIX_VEX_68 + 1)
801 #define PREFIX_VEX_6A (PREFIX_VEX_69 + 1)
802 #define PREFIX_VEX_6B (PREFIX_VEX_6A + 1)
803 #define PREFIX_VEX_6C (PREFIX_VEX_6B + 1)
804 #define PREFIX_VEX_6D (PREFIX_VEX_6C + 1)
805 #define PREFIX_VEX_6E (PREFIX_VEX_6D + 1)
806 #define PREFIX_VEX_6F (PREFIX_VEX_6E + 1)
807 #define PREFIX_VEX_70 (PREFIX_VEX_6F + 1)
808 #define PREFIX_VEX_71_REG_2 (PREFIX_VEX_70 + 1)
809 #define PREFIX_VEX_71_REG_4 (PREFIX_VEX_71_REG_2 + 1)
810 #define PREFIX_VEX_71_REG_6 (PREFIX_VEX_71_REG_4 + 1)
811 #define PREFIX_VEX_72_REG_2 (PREFIX_VEX_71_REG_6 + 1)
812 #define PREFIX_VEX_72_REG_4 (PREFIX_VEX_72_REG_2 + 1)
813 #define PREFIX_VEX_72_REG_6 (PREFIX_VEX_72_REG_4 + 1)
814 #define PREFIX_VEX_73_REG_2 (PREFIX_VEX_72_REG_6 + 1)
815 #define PREFIX_VEX_73_REG_3 (PREFIX_VEX_73_REG_2 + 1)
816 #define PREFIX_VEX_73_REG_6 (PREFIX_VEX_73_REG_3 + 1)
817 #define PREFIX_VEX_73_REG_7 (PREFIX_VEX_73_REG_6 + 1)
818 #define PREFIX_VEX_74 (PREFIX_VEX_73_REG_7 + 1)
819 #define PREFIX_VEX_75 (PREFIX_VEX_74 + 1)
820 #define PREFIX_VEX_76 (PREFIX_VEX_75 + 1)
821 #define PREFIX_VEX_77 (PREFIX_VEX_76 + 1)
822 #define PREFIX_VEX_7C (PREFIX_VEX_77 + 1)
823 #define PREFIX_VEX_7D (PREFIX_VEX_7C + 1)
824 #define PREFIX_VEX_7E (PREFIX_VEX_7D + 1)
825 #define PREFIX_VEX_7F (PREFIX_VEX_7E + 1)
826 #define PREFIX_VEX_C2 (PREFIX_VEX_7F + 1)
827 #define PREFIX_VEX_C4 (PREFIX_VEX_C2 + 1)
828 #define PREFIX_VEX_C5 (PREFIX_VEX_C4 + 1)
829 #define PREFIX_VEX_D0 (PREFIX_VEX_C5 + 1)
830 #define PREFIX_VEX_D1 (PREFIX_VEX_D0 + 1)
831 #define PREFIX_VEX_D2 (PREFIX_VEX_D1 + 1)
832 #define PREFIX_VEX_D3 (PREFIX_VEX_D2 + 1)
833 #define PREFIX_VEX_D4 (PREFIX_VEX_D3 + 1)
834 #define PREFIX_VEX_D5 (PREFIX_VEX_D4 + 1)
835 #define PREFIX_VEX_D6 (PREFIX_VEX_D5 + 1)
836 #define PREFIX_VEX_D7 (PREFIX_VEX_D6 + 1)
837 #define PREFIX_VEX_D8 (PREFIX_VEX_D7 + 1)
838 #define PREFIX_VEX_D9 (PREFIX_VEX_D8 + 1)
839 #define PREFIX_VEX_DA (PREFIX_VEX_D9 + 1)
840 #define PREFIX_VEX_DB (PREFIX_VEX_DA + 1)
841 #define PREFIX_VEX_DC (PREFIX_VEX_DB + 1)
842 #define PREFIX_VEX_DD (PREFIX_VEX_DC + 1)
843 #define PREFIX_VEX_DE (PREFIX_VEX_DD + 1)
844 #define PREFIX_VEX_DF (PREFIX_VEX_DE + 1)
845 #define PREFIX_VEX_E0 (PREFIX_VEX_DF + 1)
846 #define PREFIX_VEX_E1 (PREFIX_VEX_E0 + 1)
847 #define PREFIX_VEX_E2 (PREFIX_VEX_E1 + 1)
848 #define PREFIX_VEX_E3 (PREFIX_VEX_E2 + 1)
849 #define PREFIX_VEX_E4 (PREFIX_VEX_E3 + 1)
850 #define PREFIX_VEX_E5 (PREFIX_VEX_E4 + 1)
851 #define PREFIX_VEX_E6 (PREFIX_VEX_E5 + 1)
852 #define PREFIX_VEX_E7 (PREFIX_VEX_E6 + 1)
853 #define PREFIX_VEX_E8 (PREFIX_VEX_E7 + 1)
854 #define PREFIX_VEX_E9 (PREFIX_VEX_E8 + 1)
855 #define PREFIX_VEX_EA (PREFIX_VEX_E9 + 1)
856 #define PREFIX_VEX_EB (PREFIX_VEX_EA + 1)
857 #define PREFIX_VEX_EC (PREFIX_VEX_EB + 1)
858 #define PREFIX_VEX_ED (PREFIX_VEX_EC + 1)
859 #define PREFIX_VEX_EE (PREFIX_VEX_ED + 1)
860 #define PREFIX_VEX_EF (PREFIX_VEX_EE + 1)
861 #define PREFIX_VEX_F0 (PREFIX_VEX_EF + 1)
862 #define PREFIX_VEX_F1 (PREFIX_VEX_F0 + 1)
863 #define PREFIX_VEX_F2 (PREFIX_VEX_F1 + 1)
864 #define PREFIX_VEX_F3 (PREFIX_VEX_F2 + 1)
865 #define PREFIX_VEX_F4 (PREFIX_VEX_F3 + 1)
866 #define PREFIX_VEX_F5 (PREFIX_VEX_F4 + 1)
867 #define PREFIX_VEX_F6 (PREFIX_VEX_F5 + 1)
868 #define PREFIX_VEX_F7 (PREFIX_VEX_F6 + 1)
869 #define PREFIX_VEX_F8 (PREFIX_VEX_F7 + 1)
870 #define PREFIX_VEX_F9 (PREFIX_VEX_F8 + 1)
871 #define PREFIX_VEX_FA (PREFIX_VEX_F9 + 1)
872 #define PREFIX_VEX_FB (PREFIX_VEX_FA + 1)
873 #define PREFIX_VEX_FC (PREFIX_VEX_FB + 1)
874 #define PREFIX_VEX_FD (PREFIX_VEX_FC + 1)
875 #define PREFIX_VEX_FE (PREFIX_VEX_FD + 1)
876 #define PREFIX_VEX_3800 (PREFIX_VEX_FE + 1)
877 #define PREFIX_VEX_3801 (PREFIX_VEX_3800 + 1)
878 #define PREFIX_VEX_3802 (PREFIX_VEX_3801 + 1)
879 #define PREFIX_VEX_3803 (PREFIX_VEX_3802 + 1)
880 #define PREFIX_VEX_3804 (PREFIX_VEX_3803 + 1)
881 #define PREFIX_VEX_3805 (PREFIX_VEX_3804 + 1)
882 #define PREFIX_VEX_3806 (PREFIX_VEX_3805 + 1)
883 #define PREFIX_VEX_3807 (PREFIX_VEX_3806 + 1)
884 #define PREFIX_VEX_3808 (PREFIX_VEX_3807 + 1)
885 #define PREFIX_VEX_3809 (PREFIX_VEX_3808 + 1)
886 #define PREFIX_VEX_380A (PREFIX_VEX_3809 + 1)
887 #define PREFIX_VEX_380B (PREFIX_VEX_380A + 1)
888 #define PREFIX_VEX_380C (PREFIX_VEX_380B + 1)
889 #define PREFIX_VEX_380D (PREFIX_VEX_380C + 1)
890 #define PREFIX_VEX_380E (PREFIX_VEX_380D + 1)
891 #define PREFIX_VEX_380F (PREFIX_VEX_380E + 1)
892 #define PREFIX_VEX_3817 (PREFIX_VEX_380F + 1)
893 #define PREFIX_VEX_3818 (PREFIX_VEX_3817 + 1)
894 #define PREFIX_VEX_3819 (PREFIX_VEX_3818 + 1)
895 #define PREFIX_VEX_381A (PREFIX_VEX_3819 + 1)
896 #define PREFIX_VEX_381C (PREFIX_VEX_381A + 1)
897 #define PREFIX_VEX_381D (PREFIX_VEX_381C + 1)
898 #define PREFIX_VEX_381E (PREFIX_VEX_381D + 1)
899 #define PREFIX_VEX_3820 (PREFIX_VEX_381E + 1)
900 #define PREFIX_VEX_3821 (PREFIX_VEX_3820 + 1)
901 #define PREFIX_VEX_3822 (PREFIX_VEX_3821 + 1)
902 #define PREFIX_VEX_3823 (PREFIX_VEX_3822 + 1)
903 #define PREFIX_VEX_3824 (PREFIX_VEX_3823 + 1)
904 #define PREFIX_VEX_3825 (PREFIX_VEX_3824 + 1)
905 #define PREFIX_VEX_3828 (PREFIX_VEX_3825 + 1)
906 #define PREFIX_VEX_3829 (PREFIX_VEX_3828 + 1)
907 #define PREFIX_VEX_382A (PREFIX_VEX_3829 + 1)
908 #define PREFIX_VEX_382B (PREFIX_VEX_382A + 1)
909 #define PREFIX_VEX_382C (PREFIX_VEX_382B + 1)
910 #define PREFIX_VEX_382D (PREFIX_VEX_382C + 1)
911 #define PREFIX_VEX_382E (PREFIX_VEX_382D + 1)
912 #define PREFIX_VEX_382F (PREFIX_VEX_382E + 1)
913 #define PREFIX_VEX_3830 (PREFIX_VEX_382F + 1)
914 #define PREFIX_VEX_3831 (PREFIX_VEX_3830 + 1)
915 #define PREFIX_VEX_3832 (PREFIX_VEX_3831 + 1)
916 #define PREFIX_VEX_3833 (PREFIX_VEX_3832 + 1)
917 #define PREFIX_VEX_3834 (PREFIX_VEX_3833 + 1)
918 #define PREFIX_VEX_3835 (PREFIX_VEX_3834 + 1)
919 #define PREFIX_VEX_3837 (PREFIX_VEX_3835 + 1)
920 #define PREFIX_VEX_3838 (PREFIX_VEX_3837 + 1)
921 #define PREFIX_VEX_3839 (PREFIX_VEX_3838 + 1)
922 #define PREFIX_VEX_383A (PREFIX_VEX_3839 + 1)
923 #define PREFIX_VEX_383B (PREFIX_VEX_383A + 1)
924 #define PREFIX_VEX_383C (PREFIX_VEX_383B + 1)
925 #define PREFIX_VEX_383D (PREFIX_VEX_383C + 1)
926 #define PREFIX_VEX_383E (PREFIX_VEX_383D + 1)
927 #define PREFIX_VEX_383F (PREFIX_VEX_383E + 1)
928 #define PREFIX_VEX_3840 (PREFIX_VEX_383F + 1)
929 #define PREFIX_VEX_3841 (PREFIX_VEX_3840 + 1)
930 #define PREFIX_VEX_3896 (PREFIX_VEX_3841 + 1)
931 #define PREFIX_VEX_3897 (PREFIX_VEX_3896 + 1)
932 #define PREFIX_VEX_3898 (PREFIX_VEX_3897 + 1)
933 #define PREFIX_VEX_3899 (PREFIX_VEX_3898 + 1)
934 #define PREFIX_VEX_389A (PREFIX_VEX_3899 + 1)
935 #define PREFIX_VEX_389B (PREFIX_VEX_389A + 1)
936 #define PREFIX_VEX_389C (PREFIX_VEX_389B + 1)
937 #define PREFIX_VEX_389D (PREFIX_VEX_389C + 1)
938 #define PREFIX_VEX_389E (PREFIX_VEX_389D + 1)
939 #define PREFIX_VEX_389F (PREFIX_VEX_389E + 1)
940 #define PREFIX_VEX_38A6 (PREFIX_VEX_389F + 1)
941 #define PREFIX_VEX_38A7 (PREFIX_VEX_38A6 + 1)
942 #define PREFIX_VEX_38A8 (PREFIX_VEX_38A7 + 1)
943 #define PREFIX_VEX_38A9 (PREFIX_VEX_38A8 + 1)
944 #define PREFIX_VEX_38AA (PREFIX_VEX_38A9 + 1)
945 #define PREFIX_VEX_38AB (PREFIX_VEX_38AA + 1)
946 #define PREFIX_VEX_38AC (PREFIX_VEX_38AB + 1)
947 #define PREFIX_VEX_38AD (PREFIX_VEX_38AC + 1)
948 #define PREFIX_VEX_38AE (PREFIX_VEX_38AD + 1)
949 #define PREFIX_VEX_38AF (PREFIX_VEX_38AE + 1)
950 #define PREFIX_VEX_38B6 (PREFIX_VEX_38AF + 1)
951 #define PREFIX_VEX_38B7 (PREFIX_VEX_38B6 + 1)
952 #define PREFIX_VEX_38B8 (PREFIX_VEX_38B7 + 1)
953 #define PREFIX_VEX_38B9 (PREFIX_VEX_38B8 + 1)
954 #define PREFIX_VEX_38BA (PREFIX_VEX_38B9 + 1)
955 #define PREFIX_VEX_38BB (PREFIX_VEX_38BA + 1)
956 #define PREFIX_VEX_38BC (PREFIX_VEX_38BB + 1)
957 #define PREFIX_VEX_38BD (PREFIX_VEX_38BC + 1)
958 #define PREFIX_VEX_38BE (PREFIX_VEX_38BD + 1)
959 #define PREFIX_VEX_38BF (PREFIX_VEX_38BE + 1)
960 #define PREFIX_VEX_38DB (PREFIX_VEX_38BF + 1)
961 #define PREFIX_VEX_38DC (PREFIX_VEX_38DB + 1)
962 #define PREFIX_VEX_38DD (PREFIX_VEX_38DC + 1)
963 #define PREFIX_VEX_38DE (PREFIX_VEX_38DD + 1)
964 #define PREFIX_VEX_38DF (PREFIX_VEX_38DE + 1)
965 #define PREFIX_VEX_3A04 (PREFIX_VEX_38DF + 1)
966 #define PREFIX_VEX_3A05 (PREFIX_VEX_3A04 + 1)
967 #define PREFIX_VEX_3A06 (PREFIX_VEX_3A05 + 1)
968 #define PREFIX_VEX_3A08 (PREFIX_VEX_3A06 + 1)
969 #define PREFIX_VEX_3A09 (PREFIX_VEX_3A08 + 1)
970 #define PREFIX_VEX_3A0A (PREFIX_VEX_3A09 + 1)
971 #define PREFIX_VEX_3A0B (PREFIX_VEX_3A0A + 1)
972 #define PREFIX_VEX_3A0C (PREFIX_VEX_3A0B + 1)
973 #define PREFIX_VEX_3A0D (PREFIX_VEX_3A0C + 1)
974 #define PREFIX_VEX_3A0E (PREFIX_VEX_3A0D + 1)
975 #define PREFIX_VEX_3A0F (PREFIX_VEX_3A0E + 1)
976 #define PREFIX_VEX_3A14 (PREFIX_VEX_3A0F + 1)
977 #define PREFIX_VEX_3A15 (PREFIX_VEX_3A14 + 1)
978 #define PREFIX_VEX_3A16 (PREFIX_VEX_3A15 + 1)
979 #define PREFIX_VEX_3A17 (PREFIX_VEX_3A16 + 1)
980 #define PREFIX_VEX_3A18 (PREFIX_VEX_3A17 + 1)
981 #define PREFIX_VEX_3A19 (PREFIX_VEX_3A18 + 1)
982 #define PREFIX_VEX_3A20 (PREFIX_VEX_3A19 + 1)
983 #define PREFIX_VEX_3A21 (PREFIX_VEX_3A20 + 1)
984 #define PREFIX_VEX_3A22 (PREFIX_VEX_3A21 + 1)
985 #define PREFIX_VEX_3A40 (PREFIX_VEX_3A22 + 1)
986 #define PREFIX_VEX_3A41 (PREFIX_VEX_3A40 + 1)
987 #define PREFIX_VEX_3A42 (PREFIX_VEX_3A41 + 1)
988 #define PREFIX_VEX_3A44 (PREFIX_VEX_3A42 + 1)
989 #define PREFIX_VEX_3A4A (PREFIX_VEX_3A44 + 1)
990 #define PREFIX_VEX_3A4B (PREFIX_VEX_3A4A + 1)
991 #define PREFIX_VEX_3A4C (PREFIX_VEX_3A4B + 1)
992 #define PREFIX_VEX_3A5C (PREFIX_VEX_3A4C + 1)
993 #define PREFIX_VEX_3A5D (PREFIX_VEX_3A5C + 1)
994 #define PREFIX_VEX_3A5E (PREFIX_VEX_3A5D + 1)
995 #define PREFIX_VEX_3A5F (PREFIX_VEX_3A5E + 1)
996 #define PREFIX_VEX_3A60 (PREFIX_VEX_3A5F + 1)
997 #define PREFIX_VEX_3A61 (PREFIX_VEX_3A60 + 1)
998 #define PREFIX_VEX_3A62 (PREFIX_VEX_3A61 + 1)
999 #define PREFIX_VEX_3A63 (PREFIX_VEX_3A62 + 1)
1000 #define PREFIX_VEX_3A68 (PREFIX_VEX_3A63 + 1)
1001 #define PREFIX_VEX_3A69 (PREFIX_VEX_3A68 + 1)
1002 #define PREFIX_VEX_3A6A (PREFIX_VEX_3A69 + 1)
1003 #define PREFIX_VEX_3A6B (PREFIX_VEX_3A6A + 1)
1004 #define PREFIX_VEX_3A6C (PREFIX_VEX_3A6B + 1)
1005 #define PREFIX_VEX_3A6D (PREFIX_VEX_3A6C + 1)
1006 #define PREFIX_VEX_3A6E (PREFIX_VEX_3A6D + 1)
1007 #define PREFIX_VEX_3A6F (PREFIX_VEX_3A6E + 1)
1008 #define PREFIX_VEX_3A78 (PREFIX_VEX_3A6F + 1)
1009 #define PREFIX_VEX_3A79 (PREFIX_VEX_3A78 + 1)
1010 #define PREFIX_VEX_3A7A (PREFIX_VEX_3A79 + 1)
1011 #define PREFIX_VEX_3A7B (PREFIX_VEX_3A7A + 1)
1012 #define PREFIX_VEX_3A7C (PREFIX_VEX_3A7B + 1)
1013 #define PREFIX_VEX_3A7D (PREFIX_VEX_3A7C + 1)
1014 #define PREFIX_VEX_3A7E (PREFIX_VEX_3A7D + 1)
1015 #define PREFIX_VEX_3A7F (PREFIX_VEX_3A7E + 1)
1016 #define PREFIX_VEX_3ADF (PREFIX_VEX_3A7F + 1)
1019 #define X86_64_07 (X86_64_06 + 1)
1020 #define X86_64_0D (X86_64_07 + 1)
1021 #define X86_64_16 (X86_64_0D + 1)
1022 #define X86_64_17 (X86_64_16 + 1)
1023 #define X86_64_1E (X86_64_17 + 1)
1024 #define X86_64_1F (X86_64_1E + 1)
1025 #define X86_64_27 (X86_64_1F + 1)
1026 #define X86_64_2F (X86_64_27 + 1)
1027 #define X86_64_37 (X86_64_2F + 1)
1028 #define X86_64_3F (X86_64_37 + 1)
1029 #define X86_64_60 (X86_64_3F + 1)
1030 #define X86_64_61 (X86_64_60 + 1)
1031 #define X86_64_62 (X86_64_61 + 1)
1032 #define X86_64_63 (X86_64_62 + 1)
1033 #define X86_64_6D (X86_64_63 + 1)
1034 #define X86_64_6F (X86_64_6D + 1)
1035 #define X86_64_9A (X86_64_6F + 1)
1036 #define X86_64_C4 (X86_64_9A + 1)
1037 #define X86_64_C5 (X86_64_C4 + 1)
1038 #define X86_64_CE (X86_64_C5 + 1)
1039 #define X86_64_D4 (X86_64_CE + 1)
1040 #define X86_64_D5 (X86_64_D4 + 1)
1041 #define X86_64_EA (X86_64_D5 + 1)
1042 #define X86_64_0F01_REG_0 (X86_64_EA + 1)
1043 #define X86_64_0F01_REG_1 (X86_64_0F01_REG_0 + 1)
1044 #define X86_64_0F01_REG_2 (X86_64_0F01_REG_1 + 1)
1045 #define X86_64_0F01_REG_3 (X86_64_0F01_REG_2 + 1)
1047 #define THREE_BYTE_0F38 0
1048 #define THREE_BYTE_0F3A (THREE_BYTE_0F38 + 1)
1049 #define THREE_BYTE_0F7A (THREE_BYTE_0F3A + 1)
1052 #define VEX_0F38 (VEX_0F + 1)
1053 #define VEX_0F3A (VEX_0F38 + 1)
1055 #define VEX_LEN_10_P_1 0
1056 #define VEX_LEN_10_P_3 (VEX_LEN_10_P_1 + 1)
1057 #define VEX_LEN_11_P_1 (VEX_LEN_10_P_3 + 1)
1058 #define VEX_LEN_11_P_3 (VEX_LEN_11_P_1 + 1)
1059 #define VEX_LEN_12_P_0_M_0 (VEX_LEN_11_P_3 + 1)
1060 #define VEX_LEN_12_P_0_M_1 (VEX_LEN_12_P_0_M_0 + 1)
1061 #define VEX_LEN_12_P_2 (VEX_LEN_12_P_0_M_1 + 1)
1062 #define VEX_LEN_13_M_0 (VEX_LEN_12_P_2 + 1)
1063 #define VEX_LEN_16_P_0_M_0 (VEX_LEN_13_M_0 + 1)
1064 #define VEX_LEN_16_P_0_M_1 (VEX_LEN_16_P_0_M_0 + 1)
1065 #define VEX_LEN_16_P_2 (VEX_LEN_16_P_0_M_1 + 1)
1066 #define VEX_LEN_17_M_0 (VEX_LEN_16_P_2 + 1)
1067 #define VEX_LEN_2A_P_1 (VEX_LEN_17_M_0 + 1)
1068 #define VEX_LEN_2A_P_3 (VEX_LEN_2A_P_1 + 1)
1069 #define VEX_LEN_2C_P_1 (VEX_LEN_2A_P_3 + 1)
1070 #define VEX_LEN_2C_P_3 (VEX_LEN_2C_P_1 + 1)
1071 #define VEX_LEN_2D_P_1 (VEX_LEN_2C_P_3 + 1)
1072 #define VEX_LEN_2D_P_3 (VEX_LEN_2D_P_1 + 1)
1073 #define VEX_LEN_2E_P_0 (VEX_LEN_2D_P_3 + 1)
1074 #define VEX_LEN_2E_P_2 (VEX_LEN_2E_P_0 + 1)
1075 #define VEX_LEN_2F_P_0 (VEX_LEN_2E_P_2 + 1)
1076 #define VEX_LEN_2F_P_2 (VEX_LEN_2F_P_0 + 1)
1077 #define VEX_LEN_51_P_1 (VEX_LEN_2F_P_2 + 1)
1078 #define VEX_LEN_51_P_3 (VEX_LEN_51_P_1 + 1)
1079 #define VEX_LEN_52_P_1 (VEX_LEN_51_P_3 + 1)
1080 #define VEX_LEN_53_P_1 (VEX_LEN_52_P_1 + 1)
1081 #define VEX_LEN_58_P_1 (VEX_LEN_53_P_1 + 1)
1082 #define VEX_LEN_58_P_3 (VEX_LEN_58_P_1 + 1)
1083 #define VEX_LEN_59_P_1 (VEX_LEN_58_P_3 + 1)
1084 #define VEX_LEN_59_P_3 (VEX_LEN_59_P_1 + 1)
1085 #define VEX_LEN_5A_P_1 (VEX_LEN_59_P_3 + 1)
1086 #define VEX_LEN_5A_P_3 (VEX_LEN_5A_P_1 + 1)
1087 #define VEX_LEN_5C_P_1 (VEX_LEN_5A_P_3 + 1)
1088 #define VEX_LEN_5C_P_3 (VEX_LEN_5C_P_1 + 1)
1089 #define VEX_LEN_5D_P_1 (VEX_LEN_5C_P_3 + 1)
1090 #define VEX_LEN_5D_P_3 (VEX_LEN_5D_P_1 + 1)
1091 #define VEX_LEN_5E_P_1 (VEX_LEN_5D_P_3 + 1)
1092 #define VEX_LEN_5E_P_3 (VEX_LEN_5E_P_1 + 1)
1093 #define VEX_LEN_5F_P_1 (VEX_LEN_5E_P_3 + 1)
1094 #define VEX_LEN_5F_P_3 (VEX_LEN_5F_P_1 + 1)
1095 #define VEX_LEN_60_P_2 (VEX_LEN_5F_P_3 + 1)
1096 #define VEX_LEN_61_P_2 (VEX_LEN_60_P_2 + 1)
1097 #define VEX_LEN_62_P_2 (VEX_LEN_61_P_2 + 1)
1098 #define VEX_LEN_63_P_2 (VEX_LEN_62_P_2 + 1)
1099 #define VEX_LEN_64_P_2 (VEX_LEN_63_P_2 + 1)
1100 #define VEX_LEN_65_P_2 (VEX_LEN_64_P_2 + 1)
1101 #define VEX_LEN_66_P_2 (VEX_LEN_65_P_2 + 1)
1102 #define VEX_LEN_67_P_2 (VEX_LEN_66_P_2 + 1)
1103 #define VEX_LEN_68_P_2 (VEX_LEN_67_P_2 + 1)
1104 #define VEX_LEN_69_P_2 (VEX_LEN_68_P_2 + 1)
1105 #define VEX_LEN_6A_P_2 (VEX_LEN_69_P_2 + 1)
1106 #define VEX_LEN_6B_P_2 (VEX_LEN_6A_P_2 + 1)
1107 #define VEX_LEN_6C_P_2 (VEX_LEN_6B_P_2 + 1)
1108 #define VEX_LEN_6D_P_2 (VEX_LEN_6C_P_2 + 1)
1109 #define VEX_LEN_6E_P_2 (VEX_LEN_6D_P_2 + 1)
1110 #define VEX_LEN_70_P_1 (VEX_LEN_6E_P_2 + 1)
1111 #define VEX_LEN_70_P_2 (VEX_LEN_70_P_1 + 1)
1112 #define VEX_LEN_70_P_3 (VEX_LEN_70_P_2 + 1)
1113 #define VEX_LEN_71_R_2_P_2 (VEX_LEN_70_P_3 + 1)
1114 #define VEX_LEN_71_R_4_P_2 (VEX_LEN_71_R_2_P_2 + 1)
1115 #define VEX_LEN_71_R_6_P_2 (VEX_LEN_71_R_4_P_2 + 1)
1116 #define VEX_LEN_72_R_2_P_2 (VEX_LEN_71_R_6_P_2 + 1)
1117 #define VEX_LEN_72_R_4_P_2 (VEX_LEN_72_R_2_P_2 + 1)
1118 #define VEX_LEN_72_R_6_P_2 (VEX_LEN_72_R_4_P_2 + 1)
1119 #define VEX_LEN_73_R_2_P_2 (VEX_LEN_72_R_6_P_2 + 1)
1120 #define VEX_LEN_73_R_3_P_2 (VEX_LEN_73_R_2_P_2 + 1)
1121 #define VEX_LEN_73_R_6_P_2 (VEX_LEN_73_R_3_P_2 + 1)
1122 #define VEX_LEN_73_R_7_P_2 (VEX_LEN_73_R_6_P_2 + 1)
1123 #define VEX_LEN_74_P_2 (VEX_LEN_73_R_7_P_2 + 1)
1124 #define VEX_LEN_75_P_2 (VEX_LEN_74_P_2 + 1)
1125 #define VEX_LEN_76_P_2 (VEX_LEN_75_P_2 + 1)
1126 #define VEX_LEN_7E_P_1 (VEX_LEN_76_P_2 + 1)
1127 #define VEX_LEN_7E_P_2 (VEX_LEN_7E_P_1 + 1)
1128 #define VEX_LEN_AE_R_2_M_0 (VEX_LEN_7E_P_2 + 1)
1129 #define VEX_LEN_AE_R_3_M_0 (VEX_LEN_AE_R_2_M_0 + 1)
1130 #define VEX_LEN_C2_P_1 (VEX_LEN_AE_R_3_M_0 + 1)
1131 #define VEX_LEN_C2_P_3 (VEX_LEN_C2_P_1 + 1)
1132 #define VEX_LEN_C4_P_2 (VEX_LEN_C2_P_3 + 1)
1133 #define VEX_LEN_C5_P_2 (VEX_LEN_C4_P_2 + 1)
1134 #define VEX_LEN_D1_P_2 (VEX_LEN_C5_P_2 + 1)
1135 #define VEX_LEN_D2_P_2 (VEX_LEN_D1_P_2 + 1)
1136 #define VEX_LEN_D3_P_2 (VEX_LEN_D2_P_2 + 1)
1137 #define VEX_LEN_D4_P_2 (VEX_LEN_D3_P_2 + 1)
1138 #define VEX_LEN_D5_P_2 (VEX_LEN_D4_P_2 + 1)
1139 #define VEX_LEN_D6_P_2 (VEX_LEN_D5_P_2 + 1)
1140 #define VEX_LEN_D7_P_2_M_1 (VEX_LEN_D6_P_2 + 1)
1141 #define VEX_LEN_D8_P_2 (VEX_LEN_D7_P_2_M_1 + 1)
1142 #define VEX_LEN_D9_P_2 (VEX_LEN_D8_P_2 + 1)
1143 #define VEX_LEN_DA_P_2 (VEX_LEN_D9_P_2 + 1)
1144 #define VEX_LEN_DB_P_2 (VEX_LEN_DA_P_2 + 1)
1145 #define VEX_LEN_DC_P_2 (VEX_LEN_DB_P_2 + 1)
1146 #define VEX_LEN_DD_P_2 (VEX_LEN_DC_P_2 + 1)
1147 #define VEX_LEN_DE_P_2 (VEX_LEN_DD_P_2 + 1)
1148 #define VEX_LEN_DF_P_2 (VEX_LEN_DE_P_2 + 1)
1149 #define VEX_LEN_E0_P_2 (VEX_LEN_DF_P_2 + 1)
1150 #define VEX_LEN_E1_P_2 (VEX_LEN_E0_P_2 + 1)
1151 #define VEX_LEN_E2_P_2 (VEX_LEN_E1_P_2 + 1)
1152 #define VEX_LEN_E3_P_2 (VEX_LEN_E2_P_2 + 1)
1153 #define VEX_LEN_E4_P_2 (VEX_LEN_E3_P_2 + 1)
1154 #define VEX_LEN_E5_P_2 (VEX_LEN_E4_P_2 + 1)
1155 #define VEX_LEN_E8_P_2 (VEX_LEN_E5_P_2 + 1)
1156 #define VEX_LEN_E9_P_2 (VEX_LEN_E8_P_2 + 1)
1157 #define VEX_LEN_EA_P_2 (VEX_LEN_E9_P_2 + 1)
1158 #define VEX_LEN_EB_P_2 (VEX_LEN_EA_P_2 + 1)
1159 #define VEX_LEN_EC_P_2 (VEX_LEN_EB_P_2 + 1)
1160 #define VEX_LEN_ED_P_2 (VEX_LEN_EC_P_2 + 1)
1161 #define VEX_LEN_EE_P_2 (VEX_LEN_ED_P_2 + 1)
1162 #define VEX_LEN_EF_P_2 (VEX_LEN_EE_P_2 + 1)
1163 #define VEX_LEN_F1_P_2 (VEX_LEN_EF_P_2 + 1)
1164 #define VEX_LEN_F2_P_2 (VEX_LEN_F1_P_2 + 1)
1165 #define VEX_LEN_F3_P_2 (VEX_LEN_F2_P_2 + 1)
1166 #define VEX_LEN_F4_P_2 (VEX_LEN_F3_P_2 + 1)
1167 #define VEX_LEN_F5_P_2 (VEX_LEN_F4_P_2 + 1)
1168 #define VEX_LEN_F6_P_2 (VEX_LEN_F5_P_2 + 1)
1169 #define VEX_LEN_F7_P_2 (VEX_LEN_F6_P_2 + 1)
1170 #define VEX_LEN_F8_P_2 (VEX_LEN_F7_P_2 + 1)
1171 #define VEX_LEN_F9_P_2 (VEX_LEN_F8_P_2 + 1)
1172 #define VEX_LEN_FA_P_2 (VEX_LEN_F9_P_2 + 1)
1173 #define VEX_LEN_FB_P_2 (VEX_LEN_FA_P_2 + 1)
1174 #define VEX_LEN_FC_P_2 (VEX_LEN_FB_P_2 + 1)
1175 #define VEX_LEN_FD_P_2 (VEX_LEN_FC_P_2 + 1)
1176 #define VEX_LEN_FE_P_2 (VEX_LEN_FD_P_2 + 1)
1177 #define VEX_LEN_3800_P_2 (VEX_LEN_FE_P_2 + 1)
1178 #define VEX_LEN_3801_P_2 (VEX_LEN_3800_P_2 + 1)
1179 #define VEX_LEN_3802_P_2 (VEX_LEN_3801_P_2 + 1)
1180 #define VEX_LEN_3803_P_2 (VEX_LEN_3802_P_2 + 1)
1181 #define VEX_LEN_3804_P_2 (VEX_LEN_3803_P_2 + 1)
1182 #define VEX_LEN_3805_P_2 (VEX_LEN_3804_P_2 + 1)
1183 #define VEX_LEN_3806_P_2 (VEX_LEN_3805_P_2 + 1)
1184 #define VEX_LEN_3807_P_2 (VEX_LEN_3806_P_2 + 1)
1185 #define VEX_LEN_3808_P_2 (VEX_LEN_3807_P_2 + 1)
1186 #define VEX_LEN_3809_P_2 (VEX_LEN_3808_P_2 + 1)
1187 #define VEX_LEN_380A_P_2 (VEX_LEN_3809_P_2 + 1)
1188 #define VEX_LEN_380B_P_2 (VEX_LEN_380A_P_2 + 1)
1189 #define VEX_LEN_3819_P_2_M_0 (VEX_LEN_380B_P_2 + 1)
1190 #define VEX_LEN_381A_P_2_M_0 (VEX_LEN_3819_P_2_M_0 + 1)
1191 #define VEX_LEN_381C_P_2 (VEX_LEN_381A_P_2_M_0 + 1)
1192 #define VEX_LEN_381D_P_2 (VEX_LEN_381C_P_2 + 1)
1193 #define VEX_LEN_381E_P_2 (VEX_LEN_381D_P_2 + 1)
1194 #define VEX_LEN_3820_P_2 (VEX_LEN_381E_P_2 + 1)
1195 #define VEX_LEN_3821_P_2 (VEX_LEN_3820_P_2 + 1)
1196 #define VEX_LEN_3822_P_2 (VEX_LEN_3821_P_2 + 1)
1197 #define VEX_LEN_3823_P_2 (VEX_LEN_3822_P_2 + 1)
1198 #define VEX_LEN_3824_P_2 (VEX_LEN_3823_P_2 + 1)
1199 #define VEX_LEN_3825_P_2 (VEX_LEN_3824_P_2 + 1)
1200 #define VEX_LEN_3828_P_2 (VEX_LEN_3825_P_2 + 1)
1201 #define VEX_LEN_3829_P_2 (VEX_LEN_3828_P_2 + 1)
1202 #define VEX_LEN_382A_P_2_M_0 (VEX_LEN_3829_P_2 + 1)
1203 #define VEX_LEN_382B_P_2 (VEX_LEN_382A_P_2_M_0 + 1)
1204 #define VEX_LEN_3830_P_2 (VEX_LEN_382B_P_2 + 1)
1205 #define VEX_LEN_3831_P_2 (VEX_LEN_3830_P_2 + 1)
1206 #define VEX_LEN_3832_P_2 (VEX_LEN_3831_P_2 + 1)
1207 #define VEX_LEN_3833_P_2 (VEX_LEN_3832_P_2 + 1)
1208 #define VEX_LEN_3834_P_2 (VEX_LEN_3833_P_2 + 1)
1209 #define VEX_LEN_3835_P_2 (VEX_LEN_3834_P_2 + 1)
1210 #define VEX_LEN_3837_P_2 (VEX_LEN_3835_P_2 + 1)
1211 #define VEX_LEN_3838_P_2 (VEX_LEN_3837_P_2 + 1)
1212 #define VEX_LEN_3839_P_2 (VEX_LEN_3838_P_2 + 1)
1213 #define VEX_LEN_383A_P_2 (VEX_LEN_3839_P_2 + 1)
1214 #define VEX_LEN_383B_P_2 (VEX_LEN_383A_P_2 + 1)
1215 #define VEX_LEN_383C_P_2 (VEX_LEN_383B_P_2 + 1)
1216 #define VEX_LEN_383D_P_2 (VEX_LEN_383C_P_2 + 1)
1217 #define VEX_LEN_383E_P_2 (VEX_LEN_383D_P_2 + 1)
1218 #define VEX_LEN_383F_P_2 (VEX_LEN_383E_P_2 + 1)
1219 #define VEX_LEN_3840_P_2 (VEX_LEN_383F_P_2 + 1)
1220 #define VEX_LEN_3841_P_2 (VEX_LEN_3840_P_2 + 1)
1221 #define VEX_LEN_38DB_P_2 (VEX_LEN_3841_P_2 + 1)
1222 #define VEX_LEN_38DC_P_2 (VEX_LEN_38DB_P_2 + 1)
1223 #define VEX_LEN_38DD_P_2 (VEX_LEN_38DC_P_2 + 1)
1224 #define VEX_LEN_38DE_P_2 (VEX_LEN_38DD_P_2 + 1)
1225 #define VEX_LEN_38DF_P_2 (VEX_LEN_38DE_P_2 + 1)
1226 #define VEX_LEN_3A06_P_2 (VEX_LEN_38DF_P_2 + 1)
1227 #define VEX_LEN_3A0A_P_2 (VEX_LEN_3A06_P_2 + 1)
1228 #define VEX_LEN_3A0B_P_2 (VEX_LEN_3A0A_P_2 + 1)
1229 #define VEX_LEN_3A0E_P_2 (VEX_LEN_3A0B_P_2 + 1)
1230 #define VEX_LEN_3A0F_P_2 (VEX_LEN_3A0E_P_2 + 1)
1231 #define VEX_LEN_3A14_P_2 (VEX_LEN_3A0F_P_2 + 1)
1232 #define VEX_LEN_3A15_P_2 (VEX_LEN_3A14_P_2 + 1)
1233 #define VEX_LEN_3A16_P_2 (VEX_LEN_3A15_P_2 + 1)
1234 #define VEX_LEN_3A17_P_2 (VEX_LEN_3A16_P_2 + 1)
1235 #define VEX_LEN_3A18_P_2 (VEX_LEN_3A17_P_2 + 1)
1236 #define VEX_LEN_3A19_P_2 (VEX_LEN_3A18_P_2 + 1)
1237 #define VEX_LEN_3A20_P_2 (VEX_LEN_3A19_P_2 + 1)
1238 #define VEX_LEN_3A21_P_2 (VEX_LEN_3A20_P_2 + 1)
1239 #define VEX_LEN_3A22_P_2 (VEX_LEN_3A21_P_2 + 1)
1240 #define VEX_LEN_3A41_P_2 (VEX_LEN_3A22_P_2 + 1)
1241 #define VEX_LEN_3A42_P_2 (VEX_LEN_3A41_P_2 + 1)
1242 #define VEX_LEN_3A44_P_2 (VEX_LEN_3A42_P_2 + 1)
1243 #define VEX_LEN_3A4C_P_2 (VEX_LEN_3A44_P_2 + 1)
1244 #define VEX_LEN_3A60_P_2 (VEX_LEN_3A4C_P_2 + 1)
1245 #define VEX_LEN_3A61_P_2 (VEX_LEN_3A60_P_2 + 1)
1246 #define VEX_LEN_3A62_P_2 (VEX_LEN_3A61_P_2 + 1)
1247 #define VEX_LEN_3A63_P_2 (VEX_LEN_3A62_P_2 + 1)
1248 #define VEX_LEN_3A6A_P_2 (VEX_LEN_3A63_P_2 + 1)
1249 #define VEX_LEN_3A6B_P_2 (VEX_LEN_3A6A_P_2 + 1)
1250 #define VEX_LEN_3A6E_P_2 (VEX_LEN_3A6B_P_2 + 1)
1251 #define VEX_LEN_3A6F_P_2 (VEX_LEN_3A6E_P_2 + 1)
1252 #define VEX_LEN_3A7A_P_2 (VEX_LEN_3A6F_P_2 + 1)
1253 #define VEX_LEN_3A7B_P_2 (VEX_LEN_3A7A_P_2 + 1)
1254 #define VEX_LEN_3A7E_P_2 (VEX_LEN_3A7B_P_2 + 1)
1255 #define VEX_LEN_3A7F_P_2 (VEX_LEN_3A7E_P_2 + 1)
1256 #define VEX_LEN_3ADF_P_2 (VEX_LEN_3A7F_P_2 + 1)
1258 typedef void (*op_rtn) (int bytemode, int sizeflag);
1269 /* Upper case letters in the instruction names here are macros.
1270 'A' => print 'b' if no register operands or suffix_always is true
1271 'B' => print 'b' if suffix_always is true
1272 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1274 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1275 suffix_always is true
1276 'E' => print 'e' if 32-bit form of jcxz
1277 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1278 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1279 'H' => print ",pt" or ",pn" branch hint
1280 'I' => honor following macro letter even in Intel mode (implemented only
1281 for some of the macro letters)
1283 'K' => print 'd' or 'q' if rex prefix is present.
1284 'L' => print 'l' if suffix_always is true
1285 'M' => print 'r' if intel_mnemonic is false.
1286 'N' => print 'n' if instruction has no wait "prefix"
1287 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1288 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1289 or suffix_always is true. print 'q' if rex prefix is present.
1290 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1292 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1293 'S' => print 'w', 'l' or 'q' if suffix_always is true
1294 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1295 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1296 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1297 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1298 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1299 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1300 suffix_always is true.
1301 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1302 '!' => change condition from true to false or from false to true.
1303 '%' => add 1 upper case letter to the macro.
1305 2 upper case letter macros:
1306 "XY" => print 'x' or 'y' if no register operands or suffix_always
1308 'XW' => print 's', 'd' depending on the VEX.W bit (for FMA)
1309 'LQ' => print 'l' ('d' in Intel mode) or 'q' for memory operand
1310 or suffix_always is true
1312 Many of the above letters print nothing in Intel mode. See "putop"
1315 Braces '{' and '}', and vertical bars '|', indicate alternative
1316 mnemonic strings for AT&T and Intel. */
1318 static const struct dis386 dis386[] = {
1320 { "addB", { Eb, Gb } },
1321 { "addS", { Ev, Gv } },
1322 { "addB", { Gb, EbS } },
1323 { "addS", { Gv, EvS } },
1324 { "addB", { AL, Ib } },
1325 { "addS", { eAX, Iv } },
1326 { X86_64_TABLE (X86_64_06) },
1327 { X86_64_TABLE (X86_64_07) },
1329 { "orB", { Eb, Gb } },
1330 { "orS", { Ev, Gv } },
1331 { "orB", { Gb, EbS } },
1332 { "orS", { Gv, EvS } },
1333 { "orB", { AL, Ib } },
1334 { "orS", { eAX, Iv } },
1335 { X86_64_TABLE (X86_64_0D) },
1336 { "(bad)", { XX } }, /* 0x0f extended opcode escape */
1338 { "adcB", { Eb, Gb } },
1339 { "adcS", { Ev, Gv } },
1340 { "adcB", { Gb, EbS } },
1341 { "adcS", { Gv, EvS } },
1342 { "adcB", { AL, Ib } },
1343 { "adcS", { eAX, Iv } },
1344 { X86_64_TABLE (X86_64_16) },
1345 { X86_64_TABLE (X86_64_17) },
1347 { "sbbB", { Eb, Gb } },
1348 { "sbbS", { Ev, Gv } },
1349 { "sbbB", { Gb, EbS } },
1350 { "sbbS", { Gv, EvS } },
1351 { "sbbB", { AL, Ib } },
1352 { "sbbS", { eAX, Iv } },
1353 { X86_64_TABLE (X86_64_1E) },
1354 { X86_64_TABLE (X86_64_1F) },
1356 { "andB", { Eb, Gb } },
1357 { "andS", { Ev, Gv } },
1358 { "andB", { Gb, EbS } },
1359 { "andS", { Gv, EvS } },
1360 { "andB", { AL, Ib } },
1361 { "andS", { eAX, Iv } },
1362 { "(bad)", { XX } }, /* SEG ES prefix */
1363 { X86_64_TABLE (X86_64_27) },
1365 { "subB", { Eb, Gb } },
1366 { "subS", { Ev, Gv } },
1367 { "subB", { Gb, EbS } },
1368 { "subS", { Gv, EvS } },
1369 { "subB", { AL, Ib } },
1370 { "subS", { eAX, Iv } },
1371 { "(bad)", { XX } }, /* SEG CS prefix */
1372 { X86_64_TABLE (X86_64_2F) },
1374 { "xorB", { Eb, Gb } },
1375 { "xorS", { Ev, Gv } },
1376 { "xorB", { Gb, EbS } },
1377 { "xorS", { Gv, EvS } },
1378 { "xorB", { AL, Ib } },
1379 { "xorS", { eAX, Iv } },
1380 { "(bad)", { XX } }, /* SEG SS prefix */
1381 { X86_64_TABLE (X86_64_37) },
1383 { "cmpB", { Eb, Gb } },
1384 { "cmpS", { Ev, Gv } },
1385 { "cmpB", { Gb, EbS } },
1386 { "cmpS", { Gv, EvS } },
1387 { "cmpB", { AL, Ib } },
1388 { "cmpS", { eAX, Iv } },
1389 { "(bad)", { XX } }, /* SEG DS prefix */
1390 { X86_64_TABLE (X86_64_3F) },
1392 { "inc{S|}", { RMeAX } },
1393 { "inc{S|}", { RMeCX } },
1394 { "inc{S|}", { RMeDX } },
1395 { "inc{S|}", { RMeBX } },
1396 { "inc{S|}", { RMeSP } },
1397 { "inc{S|}", { RMeBP } },
1398 { "inc{S|}", { RMeSI } },
1399 { "inc{S|}", { RMeDI } },
1401 { "dec{S|}", { RMeAX } },
1402 { "dec{S|}", { RMeCX } },
1403 { "dec{S|}", { RMeDX } },
1404 { "dec{S|}", { RMeBX } },
1405 { "dec{S|}", { RMeSP } },
1406 { "dec{S|}", { RMeBP } },
1407 { "dec{S|}", { RMeSI } },
1408 { "dec{S|}", { RMeDI } },
1410 { "pushV", { RMrAX } },
1411 { "pushV", { RMrCX } },
1412 { "pushV", { RMrDX } },
1413 { "pushV", { RMrBX } },
1414 { "pushV", { RMrSP } },
1415 { "pushV", { RMrBP } },
1416 { "pushV", { RMrSI } },
1417 { "pushV", { RMrDI } },
1419 { "popV", { RMrAX } },
1420 { "popV", { RMrCX } },
1421 { "popV", { RMrDX } },
1422 { "popV", { RMrBX } },
1423 { "popV", { RMrSP } },
1424 { "popV", { RMrBP } },
1425 { "popV", { RMrSI } },
1426 { "popV", { RMrDI } },
1428 { X86_64_TABLE (X86_64_60) },
1429 { X86_64_TABLE (X86_64_61) },
1430 { X86_64_TABLE (X86_64_62) },
1431 { X86_64_TABLE (X86_64_63) },
1432 { "(bad)", { XX } }, /* seg fs */
1433 { "(bad)", { XX } }, /* seg gs */
1434 { "(bad)", { XX } }, /* op size prefix */
1435 { "(bad)", { XX } }, /* adr size prefix */
1437 { "pushT", { Iq } },
1438 { "imulS", { Gv, Ev, Iv } },
1439 { "pushT", { sIb } },
1440 { "imulS", { Gv, Ev, sIb } },
1441 { "ins{b|}", { Ybr, indirDX } },
1442 { X86_64_TABLE (X86_64_6D) },
1443 { "outs{b|}", { indirDXr, Xb } },
1444 { X86_64_TABLE (X86_64_6F) },
1446 { "joH", { Jb, XX, cond_jump_flag } },
1447 { "jnoH", { Jb, XX, cond_jump_flag } },
1448 { "jbH", { Jb, XX, cond_jump_flag } },
1449 { "jaeH", { Jb, XX, cond_jump_flag } },
1450 { "jeH", { Jb, XX, cond_jump_flag } },
1451 { "jneH", { Jb, XX, cond_jump_flag } },
1452 { "jbeH", { Jb, XX, cond_jump_flag } },
1453 { "jaH", { Jb, XX, cond_jump_flag } },
1455 { "jsH", { Jb, XX, cond_jump_flag } },
1456 { "jnsH", { Jb, XX, cond_jump_flag } },
1457 { "jpH", { Jb, XX, cond_jump_flag } },
1458 { "jnpH", { Jb, XX, cond_jump_flag } },
1459 { "jlH", { Jb, XX, cond_jump_flag } },
1460 { "jgeH", { Jb, XX, cond_jump_flag } },
1461 { "jleH", { Jb, XX, cond_jump_flag } },
1462 { "jgH", { Jb, XX, cond_jump_flag } },
1464 { REG_TABLE (REG_80) },
1465 { REG_TABLE (REG_81) },
1466 { "(bad)", { XX } },
1467 { REG_TABLE (REG_82) },
1468 { "testB", { Eb, Gb } },
1469 { "testS", { Ev, Gv } },
1470 { "xchgB", { Eb, Gb } },
1471 { "xchgS", { Ev, Gv } },
1473 { "movB", { Eb, Gb } },
1474 { "movS", { Ev, Gv } },
1475 { "movB", { Gb, EbS } },
1476 { "movS", { Gv, EvS } },
1477 { "movD", { Sv, Sw } },
1478 { MOD_TABLE (MOD_8D) },
1479 { "movD", { Sw, Sv } },
1480 { REG_TABLE (REG_8F) },
1482 { PREFIX_TABLE (PREFIX_90) },
1483 { "xchgS", { RMeCX, eAX } },
1484 { "xchgS", { RMeDX, eAX } },
1485 { "xchgS", { RMeBX, eAX } },
1486 { "xchgS", { RMeSP, eAX } },
1487 { "xchgS", { RMeBP, eAX } },
1488 { "xchgS", { RMeSI, eAX } },
1489 { "xchgS", { RMeDI, eAX } },
1491 { "cW{t|}R", { XX } },
1492 { "cR{t|}O", { XX } },
1493 { X86_64_TABLE (X86_64_9A) },
1494 { "(bad)", { XX } }, /* fwait */
1495 { "pushfT", { XX } },
1496 { "popfT", { XX } },
1500 { "movB", { AL, Ob } },
1501 { "movS", { eAX, Ov } },
1502 { "movB", { Ob, AL } },
1503 { "movS", { Ov, eAX } },
1504 { "movs{b|}", { Ybr, Xb } },
1505 { "movs{R|}", { Yvr, Xv } },
1506 { "cmps{b|}", { Xb, Yb } },
1507 { "cmps{R|}", { Xv, Yv } },
1509 { "testB", { AL, Ib } },
1510 { "testS", { eAX, Iv } },
1511 { "stosB", { Ybr, AL } },
1512 { "stosS", { Yvr, eAX } },
1513 { "lodsB", { ALr, Xb } },
1514 { "lodsS", { eAXr, Xv } },
1515 { "scasB", { AL, Yb } },
1516 { "scasS", { eAX, Yv } },
1518 { "movB", { RMAL, Ib } },
1519 { "movB", { RMCL, Ib } },
1520 { "movB", { RMDL, Ib } },
1521 { "movB", { RMBL, Ib } },
1522 { "movB", { RMAH, Ib } },
1523 { "movB", { RMCH, Ib } },
1524 { "movB", { RMDH, Ib } },
1525 { "movB", { RMBH, Ib } },
1527 { "movS", { RMeAX, Iv64 } },
1528 { "movS", { RMeCX, Iv64 } },
1529 { "movS", { RMeDX, Iv64 } },
1530 { "movS", { RMeBX, Iv64 } },
1531 { "movS", { RMeSP, Iv64 } },
1532 { "movS", { RMeBP, Iv64 } },
1533 { "movS", { RMeSI, Iv64 } },
1534 { "movS", { RMeDI, Iv64 } },
1536 { REG_TABLE (REG_C0) },
1537 { REG_TABLE (REG_C1) },
1540 { X86_64_TABLE (X86_64_C4) },
1541 { X86_64_TABLE (X86_64_C5) },
1542 { REG_TABLE (REG_C6) },
1543 { REG_TABLE (REG_C7) },
1545 { "enterT", { Iw, Ib } },
1546 { "leaveT", { XX } },
1547 { "Jret{|f}P", { Iw } },
1548 { "Jret{|f}P", { XX } },
1551 { X86_64_TABLE (X86_64_CE) },
1552 { "iretP", { XX } },
1554 { REG_TABLE (REG_D0) },
1555 { REG_TABLE (REG_D1) },
1556 { REG_TABLE (REG_D2) },
1557 { REG_TABLE (REG_D3) },
1558 { X86_64_TABLE (X86_64_D4) },
1559 { X86_64_TABLE (X86_64_D5) },
1560 { "(bad)", { XX } },
1561 { "xlat", { DSBX } },
1572 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
1573 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
1574 { "loopFH", { Jb, XX, loop_jcxz_flag } },
1575 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
1576 { "inB", { AL, Ib } },
1577 { "inG", { zAX, Ib } },
1578 { "outB", { Ib, AL } },
1579 { "outG", { Ib, zAX } },
1581 { "callT", { Jv } },
1583 { X86_64_TABLE (X86_64_EA) },
1585 { "inB", { AL, indirDX } },
1586 { "inG", { zAX, indirDX } },
1587 { "outB", { indirDX, AL } },
1588 { "outG", { indirDX, zAX } },
1590 { "(bad)", { XX } }, /* lock prefix */
1591 { "icebp", { XX } },
1592 { "(bad)", { XX } }, /* repne */
1593 { "(bad)", { XX } }, /* repz */
1596 { REG_TABLE (REG_F6) },
1597 { REG_TABLE (REG_F7) },
1605 { REG_TABLE (REG_FE) },
1606 { REG_TABLE (REG_FF) },
1609 static const struct dis386 dis386_twobyte[] = {
1611 { REG_TABLE (REG_0F00 ) },
1612 { REG_TABLE (REG_0F01 ) },
1613 { "larS", { Gv, Ew } },
1614 { "lslS", { Gv, Ew } },
1615 { "(bad)", { XX } },
1616 { "syscall", { XX } },
1618 { "sysretP", { XX } },
1621 { "wbinvd", { XX } },
1622 { "(bad)", { XX } },
1624 { "(bad)", { XX } },
1625 { REG_TABLE (REG_0F0D) },
1626 { "femms", { XX } },
1627 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
1629 { PREFIX_TABLE (PREFIX_0F10) },
1630 { PREFIX_TABLE (PREFIX_0F11) },
1631 { PREFIX_TABLE (PREFIX_0F12) },
1632 { MOD_TABLE (MOD_0F13) },
1633 { "unpcklpX", { XM, EXx } },
1634 { "unpckhpX", { XM, EXx } },
1635 { PREFIX_TABLE (PREFIX_0F16) },
1636 { MOD_TABLE (MOD_0F17) },
1638 { REG_TABLE (REG_0F18) },
1647 { MOD_TABLE (MOD_0F20) },
1648 { MOD_TABLE (MOD_0F21) },
1649 { MOD_TABLE (MOD_0F22) },
1650 { MOD_TABLE (MOD_0F23) },
1651 { MOD_TABLE (MOD_0F24) },
1652 { "(bad)", { XX } },
1653 { MOD_TABLE (MOD_0F26) },
1654 { "(bad)", { XX } },
1656 { "movapX", { XM, EXx } },
1657 { "movapX", { EXxS, XM } },
1658 { PREFIX_TABLE (PREFIX_0F2A) },
1659 { PREFIX_TABLE (PREFIX_0F2B) },
1660 { PREFIX_TABLE (PREFIX_0F2C) },
1661 { PREFIX_TABLE (PREFIX_0F2D) },
1662 { PREFIX_TABLE (PREFIX_0F2E) },
1663 { PREFIX_TABLE (PREFIX_0F2F) },
1665 { "wrmsr", { XX } },
1666 { "rdtsc", { XX } },
1667 { "rdmsr", { XX } },
1668 { "rdpmc", { XX } },
1669 { "sysenter", { XX } },
1670 { "sysexit", { XX } },
1671 { "(bad)", { XX } },
1672 { "getsec", { XX } },
1674 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
1675 { "(bad)", { XX } },
1676 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
1677 { "(bad)", { XX } },
1678 { "(bad)", { XX } },
1679 { "(bad)", { XX } },
1680 { "(bad)", { XX } },
1681 { "(bad)", { XX } },
1683 { "cmovoS", { Gv, Ev } },
1684 { "cmovnoS", { Gv, Ev } },
1685 { "cmovbS", { Gv, Ev } },
1686 { "cmovaeS", { Gv, Ev } },
1687 { "cmoveS", { Gv, Ev } },
1688 { "cmovneS", { Gv, Ev } },
1689 { "cmovbeS", { Gv, Ev } },
1690 { "cmovaS", { Gv, Ev } },
1692 { "cmovsS", { Gv, Ev } },
1693 { "cmovnsS", { Gv, Ev } },
1694 { "cmovpS", { Gv, Ev } },
1695 { "cmovnpS", { Gv, Ev } },
1696 { "cmovlS", { Gv, Ev } },
1697 { "cmovgeS", { Gv, Ev } },
1698 { "cmovleS", { Gv, Ev } },
1699 { "cmovgS", { Gv, Ev } },
1701 { MOD_TABLE (MOD_0F51) },
1702 { PREFIX_TABLE (PREFIX_0F51) },
1703 { PREFIX_TABLE (PREFIX_0F52) },
1704 { PREFIX_TABLE (PREFIX_0F53) },
1705 { "andpX", { XM, EXx } },
1706 { "andnpX", { XM, EXx } },
1707 { "orpX", { XM, EXx } },
1708 { "xorpX", { XM, EXx } },
1710 { PREFIX_TABLE (PREFIX_0F58) },
1711 { PREFIX_TABLE (PREFIX_0F59) },
1712 { PREFIX_TABLE (PREFIX_0F5A) },
1713 { PREFIX_TABLE (PREFIX_0F5B) },
1714 { PREFIX_TABLE (PREFIX_0F5C) },
1715 { PREFIX_TABLE (PREFIX_0F5D) },
1716 { PREFIX_TABLE (PREFIX_0F5E) },
1717 { PREFIX_TABLE (PREFIX_0F5F) },
1719 { PREFIX_TABLE (PREFIX_0F60) },
1720 { PREFIX_TABLE (PREFIX_0F61) },
1721 { PREFIX_TABLE (PREFIX_0F62) },
1722 { "packsswb", { MX, EM } },
1723 { "pcmpgtb", { MX, EM } },
1724 { "pcmpgtw", { MX, EM } },
1725 { "pcmpgtd", { MX, EM } },
1726 { "packuswb", { MX, EM } },
1728 { "punpckhbw", { MX, EM } },
1729 { "punpckhwd", { MX, EM } },
1730 { "punpckhdq", { MX, EM } },
1731 { "packssdw", { MX, EM } },
1732 { PREFIX_TABLE (PREFIX_0F6C) },
1733 { PREFIX_TABLE (PREFIX_0F6D) },
1734 { "movK", { MX, Edq } },
1735 { PREFIX_TABLE (PREFIX_0F6F) },
1737 { PREFIX_TABLE (PREFIX_0F70) },
1738 { REG_TABLE (REG_0F71) },
1739 { REG_TABLE (REG_0F72) },
1740 { REG_TABLE (REG_0F73) },
1741 { "pcmpeqb", { MX, EM } },
1742 { "pcmpeqw", { MX, EM } },
1743 { "pcmpeqd", { MX, EM } },
1746 { PREFIX_TABLE (PREFIX_0F78) },
1747 { PREFIX_TABLE (PREFIX_0F79) },
1748 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
1749 { "(bad)", { XX } },
1750 { PREFIX_TABLE (PREFIX_0F7C) },
1751 { PREFIX_TABLE (PREFIX_0F7D) },
1752 { PREFIX_TABLE (PREFIX_0F7E) },
1753 { PREFIX_TABLE (PREFIX_0F7F) },
1755 { "joH", { Jv, XX, cond_jump_flag } },
1756 { "jnoH", { Jv, XX, cond_jump_flag } },
1757 { "jbH", { Jv, XX, cond_jump_flag } },
1758 { "jaeH", { Jv, XX, cond_jump_flag } },
1759 { "jeH", { Jv, XX, cond_jump_flag } },
1760 { "jneH", { Jv, XX, cond_jump_flag } },
1761 { "jbeH", { Jv, XX, cond_jump_flag } },
1762 { "jaH", { Jv, XX, cond_jump_flag } },
1764 { "jsH", { Jv, XX, cond_jump_flag } },
1765 { "jnsH", { Jv, XX, cond_jump_flag } },
1766 { "jpH", { Jv, XX, cond_jump_flag } },
1767 { "jnpH", { Jv, XX, cond_jump_flag } },
1768 { "jlH", { Jv, XX, cond_jump_flag } },
1769 { "jgeH", { Jv, XX, cond_jump_flag } },
1770 { "jleH", { Jv, XX, cond_jump_flag } },
1771 { "jgH", { Jv, XX, cond_jump_flag } },
1774 { "setno", { Eb } },
1776 { "setae", { Eb } },
1778 { "setne", { Eb } },
1779 { "setbe", { Eb } },
1783 { "setns", { Eb } },
1785 { "setnp", { Eb } },
1787 { "setge", { Eb } },
1788 { "setle", { Eb } },
1791 { "pushT", { fs } },
1793 { "cpuid", { XX } },
1794 { "btS", { Ev, Gv } },
1795 { "shldS", { Ev, Gv, Ib } },
1796 { "shldS", { Ev, Gv, CL } },
1797 { REG_TABLE (REG_0FA6) },
1798 { REG_TABLE (REG_0FA7) },
1800 { "pushT", { gs } },
1803 { "btsS", { Ev, Gv } },
1804 { "shrdS", { Ev, Gv, Ib } },
1805 { "shrdS", { Ev, Gv, CL } },
1806 { REG_TABLE (REG_0FAE) },
1807 { "imulS", { Gv, Ev } },
1809 { "cmpxchgB", { Eb, Gb } },
1810 { "cmpxchgS", { Ev, Gv } },
1811 { MOD_TABLE (MOD_0FB2) },
1812 { "btrS", { Ev, Gv } },
1813 { MOD_TABLE (MOD_0FB4) },
1814 { MOD_TABLE (MOD_0FB5) },
1815 { "movz{bR|x}", { Gv, Eb } },
1816 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
1818 { PREFIX_TABLE (PREFIX_0FB8) },
1820 { REG_TABLE (REG_0FBA) },
1821 { "btcS", { Ev, Gv } },
1822 { "bsfS", { Gv, Ev } },
1823 { PREFIX_TABLE (PREFIX_0FBD) },
1824 { "movs{bR|x}", { Gv, Eb } },
1825 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
1827 { "xaddB", { Eb, Gb } },
1828 { "xaddS", { Ev, Gv } },
1829 { PREFIX_TABLE (PREFIX_0FC2) },
1830 { PREFIX_TABLE (PREFIX_0FC3) },
1831 { "pinsrw", { MX, Edqw, Ib } },
1832 { "pextrw", { Gdq, MS, Ib } },
1833 { "shufpX", { XM, EXx, Ib } },
1834 { REG_TABLE (REG_0FC7) },
1836 { "bswap", { RMeAX } },
1837 { "bswap", { RMeCX } },
1838 { "bswap", { RMeDX } },
1839 { "bswap", { RMeBX } },
1840 { "bswap", { RMeSP } },
1841 { "bswap", { RMeBP } },
1842 { "bswap", { RMeSI } },
1843 { "bswap", { RMeDI } },
1845 { PREFIX_TABLE (PREFIX_0FD0) },
1846 { "psrlw", { MX, EM } },
1847 { "psrld", { MX, EM } },
1848 { "psrlq", { MX, EM } },
1849 { "paddq", { MX, EM } },
1850 { "pmullw", { MX, EM } },
1851 { PREFIX_TABLE (PREFIX_0FD6) },
1852 { MOD_TABLE (MOD_0FD7) },
1854 { "psubusb", { MX, EM } },
1855 { "psubusw", { MX, EM } },
1856 { "pminub", { MX, EM } },
1857 { "pand", { MX, EM } },
1858 { "paddusb", { MX, EM } },
1859 { "paddusw", { MX, EM } },
1860 { "pmaxub", { MX, EM } },
1861 { "pandn", { MX, EM } },
1863 { "pavgb", { MX, EM } },
1864 { "psraw", { MX, EM } },
1865 { "psrad", { MX, EM } },
1866 { "pavgw", { MX, EM } },
1867 { "pmulhuw", { MX, EM } },
1868 { "pmulhw", { MX, EM } },
1869 { PREFIX_TABLE (PREFIX_0FE6) },
1870 { PREFIX_TABLE (PREFIX_0FE7) },
1872 { "psubsb", { MX, EM } },
1873 { "psubsw", { MX, EM } },
1874 { "pminsw", { MX, EM } },
1875 { "por", { MX, EM } },
1876 { "paddsb", { MX, EM } },
1877 { "paddsw", { MX, EM } },
1878 { "pmaxsw", { MX, EM } },
1879 { "pxor", { MX, EM } },
1881 { PREFIX_TABLE (PREFIX_0FF0) },
1882 { "psllw", { MX, EM } },
1883 { "pslld", { MX, EM } },
1884 { "psllq", { MX, EM } },
1885 { "pmuludq", { MX, EM } },
1886 { "pmaddwd", { MX, EM } },
1887 { "psadbw", { MX, EM } },
1888 { PREFIX_TABLE (PREFIX_0FF7) },
1890 { "psubb", { MX, EM } },
1891 { "psubw", { MX, EM } },
1892 { "psubd", { MX, EM } },
1893 { "psubq", { MX, EM } },
1894 { "paddb", { MX, EM } },
1895 { "paddw", { MX, EM } },
1896 { "paddd", { MX, EM } },
1897 { "(bad)", { XX } },
1900 static const unsigned char onebyte_has_modrm[256] = {
1901 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1902 /* ------------------------------- */
1903 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1904 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1905 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1906 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1907 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1908 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1909 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1910 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1911 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1912 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1913 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1914 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1915 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1916 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1917 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1918 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1919 /* ------------------------------- */
1920 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1923 static const unsigned char twobyte_has_modrm[256] = {
1924 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1925 /* ------------------------------- */
1926 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1927 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1928 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1929 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1930 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1931 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1932 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1933 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1934 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1935 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1936 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1937 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1938 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1939 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1940 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1941 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1942 /* ------------------------------- */
1943 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1946 static char obuf[100];
1948 static char *mnemonicendp;
1949 static char scratchbuf[100];
1950 static unsigned char *start_codep;
1951 static unsigned char *insn_codep;
1952 static unsigned char *codep;
1953 static const char *lock_prefix;
1954 static const char *data_prefix;
1955 static const char *addr_prefix;
1956 static const char *repz_prefix;
1957 static const char *repnz_prefix;
1958 static disassemble_info *the_info;
1966 static unsigned char need_modrm;
1969 int register_specifier;
1975 static unsigned char need_vex;
1976 static unsigned char need_vex_reg;
1977 static unsigned char vex_w_done;
1985 /* If we are accessing mod/rm/reg without need_modrm set, then the
1986 values are stale. Hitting this abort likely indicates that you
1987 need to update onebyte_has_modrm or twobyte_has_modrm. */
1988 #define MODRM_CHECK if (!need_modrm) abort ()
1990 static const char **names64;
1991 static const char **names32;
1992 static const char **names16;
1993 static const char **names8;
1994 static const char **names8rex;
1995 static const char **names_seg;
1996 static const char *index64;
1997 static const char *index32;
1998 static const char **index16;
2000 static const char *intel_names64[] = {
2001 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2002 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2004 static const char *intel_names32[] = {
2005 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2006 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2008 static const char *intel_names16[] = {
2009 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2010 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2012 static const char *intel_names8[] = {
2013 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2015 static const char *intel_names8rex[] = {
2016 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2017 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2019 static const char *intel_names_seg[] = {
2020 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2022 static const char *intel_index64 = "riz";
2023 static const char *intel_index32 = "eiz";
2024 static const char *intel_index16[] = {
2025 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2028 static const char *att_names64[] = {
2029 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2030 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2032 static const char *att_names32[] = {
2033 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2034 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2036 static const char *att_names16[] = {
2037 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2038 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2040 static const char *att_names8[] = {
2041 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2043 static const char *att_names8rex[] = {
2044 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2045 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2047 static const char *att_names_seg[] = {
2048 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2050 static const char *att_index64 = "%riz";
2051 static const char *att_index32 = "%eiz";
2052 static const char *att_index16[] = {
2053 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2056 static const struct dis386 reg_table[][8] = {
2059 { "addA", { Eb, Ib } },
2060 { "orA", { Eb, Ib } },
2061 { "adcA", { Eb, Ib } },
2062 { "sbbA", { Eb, Ib } },
2063 { "andA", { Eb, Ib } },
2064 { "subA", { Eb, Ib } },
2065 { "xorA", { Eb, Ib } },
2066 { "cmpA", { Eb, Ib } },
2070 { "addQ", { Ev, Iv } },
2071 { "orQ", { Ev, Iv } },
2072 { "adcQ", { Ev, Iv } },
2073 { "sbbQ", { Ev, Iv } },
2074 { "andQ", { Ev, Iv } },
2075 { "subQ", { Ev, Iv } },
2076 { "xorQ", { Ev, Iv } },
2077 { "cmpQ", { Ev, Iv } },
2081 { "addQ", { Ev, sIb } },
2082 { "orQ", { Ev, sIb } },
2083 { "adcQ", { Ev, sIb } },
2084 { "sbbQ", { Ev, sIb } },
2085 { "andQ", { Ev, sIb } },
2086 { "subQ", { Ev, sIb } },
2087 { "xorQ", { Ev, sIb } },
2088 { "cmpQ", { Ev, sIb } },
2092 { "popU", { stackEv } },
2093 { "(bad)", { XX } },
2094 { "(bad)", { XX } },
2095 { "(bad)", { XX } },
2096 { "(bad)", { XX } },
2097 { "(bad)", { XX } },
2098 { "(bad)", { XX } },
2099 { "(bad)", { XX } },
2103 { "rolA", { Eb, Ib } },
2104 { "rorA", { Eb, Ib } },
2105 { "rclA", { Eb, Ib } },
2106 { "rcrA", { Eb, Ib } },
2107 { "shlA", { Eb, Ib } },
2108 { "shrA", { Eb, Ib } },
2109 { "(bad)", { XX } },
2110 { "sarA", { Eb, Ib } },
2114 { "rolQ", { Ev, Ib } },
2115 { "rorQ", { Ev, Ib } },
2116 { "rclQ", { Ev, Ib } },
2117 { "rcrQ", { Ev, Ib } },
2118 { "shlQ", { Ev, Ib } },
2119 { "shrQ", { Ev, Ib } },
2120 { "(bad)", { XX } },
2121 { "sarQ", { Ev, Ib } },
2125 { "movA", { Eb, Ib } },
2126 { "(bad)", { XX } },
2127 { "(bad)", { XX } },
2128 { "(bad)", { XX } },
2129 { "(bad)", { XX } },
2130 { "(bad)", { XX } },
2131 { "(bad)", { XX } },
2132 { "(bad)", { XX } },
2136 { "movQ", { Ev, Iv } },
2137 { "(bad)", { XX } },
2138 { "(bad)", { XX } },
2139 { "(bad)", { XX } },
2140 { "(bad)", { XX } },
2141 { "(bad)", { XX } },
2142 { "(bad)", { XX } },
2143 { "(bad)", { XX } },
2147 { "rolA", { Eb, I1 } },
2148 { "rorA", { Eb, I1 } },
2149 { "rclA", { Eb, I1 } },
2150 { "rcrA", { Eb, I1 } },
2151 { "shlA", { Eb, I1 } },
2152 { "shrA", { Eb, I1 } },
2153 { "(bad)", { XX } },
2154 { "sarA", { Eb, I1 } },
2158 { "rolQ", { Ev, I1 } },
2159 { "rorQ", { Ev, I1 } },
2160 { "rclQ", { Ev, I1 } },
2161 { "rcrQ", { Ev, I1 } },
2162 { "shlQ", { Ev, I1 } },
2163 { "shrQ", { Ev, I1 } },
2164 { "(bad)", { XX } },
2165 { "sarQ", { Ev, I1 } },
2169 { "rolA", { Eb, CL } },
2170 { "rorA", { Eb, CL } },
2171 { "rclA", { Eb, CL } },
2172 { "rcrA", { Eb, CL } },
2173 { "shlA", { Eb, CL } },
2174 { "shrA", { Eb, CL } },
2175 { "(bad)", { XX } },
2176 { "sarA", { Eb, CL } },
2180 { "rolQ", { Ev, CL } },
2181 { "rorQ", { Ev, CL } },
2182 { "rclQ", { Ev, CL } },
2183 { "rcrQ", { Ev, CL } },
2184 { "shlQ", { Ev, CL } },
2185 { "shrQ", { Ev, CL } },
2186 { "(bad)", { XX } },
2187 { "sarQ", { Ev, CL } },
2191 { "testA", { Eb, Ib } },
2192 { "(bad)", { XX } },
2195 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
2196 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
2197 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
2198 { "idivA", { Eb } }, /* and idiv for consistency. */
2202 { "testQ", { Ev, Iv } },
2203 { "(bad)", { XX } },
2206 { "mulQ", { Ev } }, /* Don't print the implicit register. */
2207 { "imulQ", { Ev } },
2209 { "idivQ", { Ev } },
2215 { "(bad)", { XX } },
2216 { "(bad)", { XX } },
2217 { "(bad)", { XX } },
2218 { "(bad)", { XX } },
2219 { "(bad)", { XX } },
2220 { "(bad)", { XX } },
2226 { "callT", { indirEv } },
2227 { "JcallT", { indirEp } },
2228 { "jmpT", { indirEv } },
2229 { "JjmpT", { indirEp } },
2230 { "pushU", { stackEv } },
2231 { "(bad)", { XX } },
2235 { "sldtD", { Sv } },
2241 { "(bad)", { XX } },
2242 { "(bad)", { XX } },
2246 { MOD_TABLE (MOD_0F01_REG_0) },
2247 { MOD_TABLE (MOD_0F01_REG_1) },
2248 { MOD_TABLE (MOD_0F01_REG_2) },
2249 { MOD_TABLE (MOD_0F01_REG_3) },
2250 { "smswD", { Sv } },
2251 { "(bad)", { XX } },
2253 { MOD_TABLE (MOD_0F01_REG_7) },
2257 { "prefetch", { Eb } },
2258 { "prefetchw", { Eb } },
2259 { "(bad)", { XX } },
2260 { "(bad)", { XX } },
2261 { "(bad)", { XX } },
2262 { "(bad)", { XX } },
2263 { "(bad)", { XX } },
2264 { "(bad)", { XX } },
2268 { MOD_TABLE (MOD_0F18_REG_0) },
2269 { MOD_TABLE (MOD_0F18_REG_1) },
2270 { MOD_TABLE (MOD_0F18_REG_2) },
2271 { MOD_TABLE (MOD_0F18_REG_3) },
2272 { "(bad)", { XX } },
2273 { "(bad)", { XX } },
2274 { "(bad)", { XX } },
2275 { "(bad)", { XX } },
2279 { "(bad)", { XX } },
2280 { "(bad)", { XX } },
2281 { MOD_TABLE (MOD_0F71_REG_2) },
2282 { "(bad)", { XX } },
2283 { MOD_TABLE (MOD_0F71_REG_4) },
2284 { "(bad)", { XX } },
2285 { MOD_TABLE (MOD_0F71_REG_6) },
2286 { "(bad)", { XX } },
2290 { "(bad)", { XX } },
2291 { "(bad)", { XX } },
2292 { MOD_TABLE (MOD_0F72_REG_2) },
2293 { "(bad)", { XX } },
2294 { MOD_TABLE (MOD_0F72_REG_4) },
2295 { "(bad)", { XX } },
2296 { MOD_TABLE (MOD_0F72_REG_6) },
2297 { "(bad)", { XX } },
2301 { "(bad)", { XX } },
2302 { "(bad)", { XX } },
2303 { MOD_TABLE (MOD_0F73_REG_2) },
2304 { MOD_TABLE (MOD_0F73_REG_3) },
2305 { "(bad)", { XX } },
2306 { "(bad)", { XX } },
2307 { MOD_TABLE (MOD_0F73_REG_6) },
2308 { MOD_TABLE (MOD_0F73_REG_7) },
2312 { "montmul", { { OP_0f07, 0 } } },
2313 { "xsha1", { { OP_0f07, 0 } } },
2314 { "xsha256", { { OP_0f07, 0 } } },
2315 { "(bad)", { { OP_0f07, 0 } } },
2316 { "(bad)", { { OP_0f07, 0 } } },
2317 { "(bad)", { { OP_0f07, 0 } } },
2318 { "(bad)", { { OP_0f07, 0 } } },
2319 { "(bad)", { { OP_0f07, 0 } } },
2323 { "xstore-rng", { { OP_0f07, 0 } } },
2324 { "xcrypt-ecb", { { OP_0f07, 0 } } },
2325 { "xcrypt-cbc", { { OP_0f07, 0 } } },
2326 { "xcrypt-ctr", { { OP_0f07, 0 } } },
2327 { "xcrypt-cfb", { { OP_0f07, 0 } } },
2328 { "xcrypt-ofb", { { OP_0f07, 0 } } },
2329 { "(bad)", { { OP_0f07, 0 } } },
2330 { "(bad)", { { OP_0f07, 0 } } },
2334 { MOD_TABLE (MOD_0FAE_REG_0) },
2335 { MOD_TABLE (MOD_0FAE_REG_1) },
2336 { MOD_TABLE (MOD_0FAE_REG_2) },
2337 { MOD_TABLE (MOD_0FAE_REG_3) },
2338 { MOD_TABLE (MOD_0FAE_REG_4) },
2339 { MOD_TABLE (MOD_0FAE_REG_5) },
2340 { MOD_TABLE (MOD_0FAE_REG_6) },
2341 { MOD_TABLE (MOD_0FAE_REG_7) },
2345 { "(bad)", { XX } },
2346 { "(bad)", { XX } },
2347 { "(bad)", { XX } },
2348 { "(bad)", { XX } },
2349 { "btQ", { Ev, Ib } },
2350 { "btsQ", { Ev, Ib } },
2351 { "btrQ", { Ev, Ib } },
2352 { "btcQ", { Ev, Ib } },
2356 { "(bad)", { XX } },
2357 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2358 { "(bad)", { XX } },
2359 { "(bad)", { XX } },
2360 { "(bad)", { XX } },
2361 { "(bad)", { XX } },
2362 { MOD_TABLE (MOD_0FC7_REG_6) },
2363 { MOD_TABLE (MOD_0FC7_REG_7) },
2367 { "(bad)", { XX } },
2368 { "(bad)", { XX } },
2369 { MOD_TABLE (MOD_VEX_71_REG_2) },
2370 { "(bad)", { XX } },
2371 { MOD_TABLE (MOD_VEX_71_REG_4) },
2372 { "(bad)", { XX } },
2373 { MOD_TABLE (MOD_VEX_71_REG_6) },
2374 { "(bad)", { XX } },
2378 { "(bad)", { XX } },
2379 { "(bad)", { XX } },
2380 { MOD_TABLE (MOD_VEX_72_REG_2) },
2381 { "(bad)", { XX } },
2382 { MOD_TABLE (MOD_VEX_72_REG_4) },
2383 { "(bad)", { XX } },
2384 { MOD_TABLE (MOD_VEX_72_REG_6) },
2385 { "(bad)", { XX } },
2389 { "(bad)", { XX } },
2390 { "(bad)", { XX } },
2391 { MOD_TABLE (MOD_VEX_73_REG_2) },
2392 { MOD_TABLE (MOD_VEX_73_REG_3) },
2393 { "(bad)", { XX } },
2394 { "(bad)", { XX } },
2395 { MOD_TABLE (MOD_VEX_73_REG_6) },
2396 { MOD_TABLE (MOD_VEX_73_REG_7) },
2400 { "(bad)", { XX } },
2401 { "(bad)", { XX } },
2402 { MOD_TABLE (MOD_VEX_AE_REG_2) },
2403 { MOD_TABLE (MOD_VEX_AE_REG_3) },
2404 { "(bad)", { XX } },
2405 { "(bad)", { XX } },
2406 { "(bad)", { XX } },
2407 { "(bad)", { XX } },
2411 static const struct dis386 prefix_table[][4] = {
2414 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2415 { "pause", { XX } },
2416 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2417 { "(bad)", { XX } },
2422 { "movups", { XM, EXx } },
2423 { "movss", { XM, EXd } },
2424 { "movupd", { XM, EXx } },
2425 { "movsd", { XM, EXq } },
2430 { "movups", { EXxS, XM } },
2431 { "movss", { EXdS, XM } },
2432 { "movupd", { EXxS, XM } },
2433 { "movsd", { EXqS, XM } },
2438 { MOD_TABLE (MOD_0F12_PREFIX_0) },
2439 { "movsldup", { XM, EXx } },
2440 { "movlpd", { XM, EXq } },
2441 { "movddup", { XM, EXq } },
2446 { MOD_TABLE (MOD_0F16_PREFIX_0) },
2447 { "movshdup", { XM, EXx } },
2448 { "movhpd", { XM, EXq } },
2449 { "(bad)", { XX } },
2454 { "cvtpi2ps", { XM, EMCq } },
2455 { "cvtsi2ss%LQ", { XM, Ev } },
2456 { "cvtpi2pd", { XM, EMCq } },
2457 { "cvtsi2sd%LQ", { XM, Ev } },
2462 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2463 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2464 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2465 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2470 { "cvttps2pi", { MXC, EXq } },
2471 { "cvttss2siY", { Gv, EXd } },
2472 { "cvttpd2pi", { MXC, EXx } },
2473 { "cvttsd2siY", { Gv, EXq } },
2478 { "cvtps2pi", { MXC, EXq } },
2479 { "cvtss2siY", { Gv, EXd } },
2480 { "cvtpd2pi", { MXC, EXx } },
2481 { "cvtsd2siY", { Gv, EXq } },
2486 { "ucomiss",{ XM, EXd } },
2487 { "(bad)", { XX } },
2488 { "ucomisd",{ XM, EXq } },
2489 { "(bad)", { XX } },
2494 { "comiss", { XM, EXd } },
2495 { "(bad)", { XX } },
2496 { "comisd", { XM, EXq } },
2497 { "(bad)", { XX } },
2502 { "sqrtps", { XM, EXx } },
2503 { "sqrtss", { XM, EXd } },
2504 { "sqrtpd", { XM, EXx } },
2505 { "sqrtsd", { XM, EXq } },
2510 { "rsqrtps",{ XM, EXx } },
2511 { "rsqrtss",{ XM, EXd } },
2512 { "(bad)", { XX } },
2513 { "(bad)", { XX } },
2518 { "rcpps", { XM, EXx } },
2519 { "rcpss", { XM, EXd } },
2520 { "(bad)", { XX } },
2521 { "(bad)", { XX } },
2526 { "addps", { XM, EXx } },
2527 { "addss", { XM, EXd } },
2528 { "addpd", { XM, EXx } },
2529 { "addsd", { XM, EXq } },
2534 { "mulps", { XM, EXx } },
2535 { "mulss", { XM, EXd } },
2536 { "mulpd", { XM, EXx } },
2537 { "mulsd", { XM, EXq } },
2542 { "cvtps2pd", { XM, EXq } },
2543 { "cvtss2sd", { XM, EXd } },
2544 { "cvtpd2ps", { XM, EXx } },
2545 { "cvtsd2ss", { XM, EXq } },
2550 { "cvtdq2ps", { XM, EXx } },
2551 { "cvttps2dq", { XM, EXx } },
2552 { "cvtps2dq", { XM, EXx } },
2553 { "(bad)", { XX } },
2558 { "subps", { XM, EXx } },
2559 { "subss", { XM, EXd } },
2560 { "subpd", { XM, EXx } },
2561 { "subsd", { XM, EXq } },
2566 { "minps", { XM, EXx } },
2567 { "minss", { XM, EXd } },
2568 { "minpd", { XM, EXx } },
2569 { "minsd", { XM, EXq } },
2574 { "divps", { XM, EXx } },
2575 { "divss", { XM, EXd } },
2576 { "divpd", { XM, EXx } },
2577 { "divsd", { XM, EXq } },
2582 { "maxps", { XM, EXx } },
2583 { "maxss", { XM, EXd } },
2584 { "maxpd", { XM, EXx } },
2585 { "maxsd", { XM, EXq } },
2590 { "punpcklbw",{ MX, EMd } },
2591 { "(bad)", { XX } },
2592 { "punpcklbw",{ MX, EMx } },
2593 { "(bad)", { XX } },
2598 { "punpcklwd",{ MX, EMd } },
2599 { "(bad)", { XX } },
2600 { "punpcklwd",{ MX, EMx } },
2601 { "(bad)", { XX } },
2606 { "punpckldq",{ MX, EMd } },
2607 { "(bad)", { XX } },
2608 { "punpckldq",{ MX, EMx } },
2609 { "(bad)", { XX } },
2614 { "(bad)", { XX } },
2615 { "(bad)", { XX } },
2616 { "punpcklqdq", { XM, EXx } },
2617 { "(bad)", { XX } },
2622 { "(bad)", { XX } },
2623 { "(bad)", { XX } },
2624 { "punpckhqdq", { XM, EXx } },
2625 { "(bad)", { XX } },
2630 { "movq", { MX, EM } },
2631 { "movdqu", { XM, EXx } },
2632 { "movdqa", { XM, EXx } },
2633 { "(bad)", { XX } },
2638 { "pshufw", { MX, EM, Ib } },
2639 { "pshufhw",{ XM, EXx, Ib } },
2640 { "pshufd", { XM, EXx, Ib } },
2641 { "pshuflw",{ XM, EXx, Ib } },
2644 /* PREFIX_0F73_REG_3 */
2646 { "(bad)", { XX } },
2647 { "(bad)", { XX } },
2648 { "psrldq", { XS, Ib } },
2649 { "(bad)", { XX } },
2652 /* PREFIX_0F73_REG_7 */
2654 { "(bad)", { XX } },
2655 { "(bad)", { XX } },
2656 { "pslldq", { XS, Ib } },
2657 { "(bad)", { XX } },
2662 {"vmread", { Em, Gm } },
2664 {"extrq", { XS, Ib, Ib } },
2665 {"insertq", { XM, XS, Ib, Ib } },
2670 {"vmwrite", { Gm, Em } },
2672 {"extrq", { XM, XS } },
2673 {"insertq", { XM, XS } },
2678 { "(bad)", { XX } },
2679 { "(bad)", { XX } },
2680 { "haddpd", { XM, EXx } },
2681 { "haddps", { XM, EXx } },
2686 { "(bad)", { XX } },
2687 { "(bad)", { XX } },
2688 { "hsubpd", { XM, EXx } },
2689 { "hsubps", { XM, EXx } },
2694 { "movK", { Edq, MX } },
2695 { "movq", { XM, EXq } },
2696 { "movK", { Edq, XM } },
2697 { "(bad)", { XX } },
2702 { "movq", { EMS, MX } },
2703 { "movdqu", { EXxS, XM } },
2704 { "movdqa", { EXxS, XM } },
2705 { "(bad)", { XX } },
2710 { "(bad)", { XX } },
2711 { "popcntS", { Gv, Ev } },
2712 { "(bad)", { XX } },
2713 { "(bad)", { XX } },
2718 { "bsrS", { Gv, Ev } },
2719 { "lzcntS", { Gv, Ev } },
2720 { "bsrS", { Gv, Ev } },
2721 { "(bad)", { XX } },
2726 { "cmpps", { XM, EXx, CMP } },
2727 { "cmpss", { XM, EXd, CMP } },
2728 { "cmppd", { XM, EXx, CMP } },
2729 { "cmpsd", { XM, EXq, CMP } },
2734 { "movntiS", { Ma, Gv } },
2735 { "(bad)", { XX } },
2736 { "(bad)", { XX } },
2737 { "(bad)", { XX } },
2740 /* PREFIX_0FC7_REG_6 */
2742 { "vmptrld",{ Mq } },
2743 { "vmxon", { Mq } },
2744 { "vmclear",{ Mq } },
2745 { "(bad)", { XX } },
2750 { "(bad)", { XX } },
2751 { "(bad)", { XX } },
2752 { "addsubpd", { XM, EXx } },
2753 { "addsubps", { XM, EXx } },
2758 { "(bad)", { XX } },
2759 { "movq2dq",{ XM, MS } },
2760 { "movq", { EXqS, XM } },
2761 { "movdq2q",{ MX, XS } },
2766 { "(bad)", { XX } },
2767 { "cvtdq2pd", { XM, EXq } },
2768 { "cvttpd2dq", { XM, EXx } },
2769 { "cvtpd2dq", { XM, EXx } },
2774 { "movntq", { Mq, MX } },
2775 { "(bad)", { XX } },
2776 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
2777 { "(bad)", { XX } },
2782 { "(bad)", { XX } },
2783 { "(bad)", { XX } },
2784 { "(bad)", { XX } },
2785 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
2790 { "maskmovq", { MX, MS } },
2791 { "(bad)", { XX } },
2792 { "maskmovdqu", { XM, XS } },
2793 { "(bad)", { XX } },
2798 { "(bad)", { XX } },
2799 { "(bad)", { XX } },
2800 { "pblendvb", { XM, EXx, XMM0 } },
2801 { "(bad)", { XX } },
2806 { "(bad)", { XX } },
2807 { "(bad)", { XX } },
2808 { "blendvps", { XM, EXx, XMM0 } },
2809 { "(bad)", { XX } },
2814 { "(bad)", { XX } },
2815 { "(bad)", { XX } },
2816 { "blendvpd", { XM, EXx, XMM0 } },
2817 { "(bad)", { XX } },
2822 { "(bad)", { XX } },
2823 { "(bad)", { XX } },
2824 { "ptest", { XM, EXx } },
2825 { "(bad)", { XX } },
2830 { "(bad)", { XX } },
2831 { "(bad)", { XX } },
2832 { "pmovsxbw", { XM, EXq } },
2833 { "(bad)", { XX } },
2838 { "(bad)", { XX } },
2839 { "(bad)", { XX } },
2840 { "pmovsxbd", { XM, EXd } },
2841 { "(bad)", { XX } },
2846 { "(bad)", { XX } },
2847 { "(bad)", { XX } },
2848 { "pmovsxbq", { XM, EXw } },
2849 { "(bad)", { XX } },
2854 { "(bad)", { XX } },
2855 { "(bad)", { XX } },
2856 { "pmovsxwd", { XM, EXq } },
2857 { "(bad)", { XX } },
2862 { "(bad)", { XX } },
2863 { "(bad)", { XX } },
2864 { "pmovsxwq", { XM, EXd } },
2865 { "(bad)", { XX } },
2870 { "(bad)", { XX } },
2871 { "(bad)", { XX } },
2872 { "pmovsxdq", { XM, EXq } },
2873 { "(bad)", { XX } },
2878 { "(bad)", { XX } },
2879 { "(bad)", { XX } },
2880 { "pmuldq", { XM, EXx } },
2881 { "(bad)", { XX } },
2886 { "(bad)", { XX } },
2887 { "(bad)", { XX } },
2888 { "pcmpeqq", { XM, EXx } },
2889 { "(bad)", { XX } },
2894 { "(bad)", { XX } },
2895 { "(bad)", { XX } },
2896 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
2897 { "(bad)", { XX } },
2902 { "(bad)", { XX } },
2903 { "(bad)", { XX } },
2904 { "packusdw", { XM, EXx } },
2905 { "(bad)", { XX } },
2910 { "(bad)", { XX } },
2911 { "(bad)", { XX } },
2912 { "pmovzxbw", { XM, EXq } },
2913 { "(bad)", { XX } },
2918 { "(bad)", { XX } },
2919 { "(bad)", { XX } },
2920 { "pmovzxbd", { XM, EXd } },
2921 { "(bad)", { XX } },
2926 { "(bad)", { XX } },
2927 { "(bad)", { XX } },
2928 { "pmovzxbq", { XM, EXw } },
2929 { "(bad)", { XX } },
2934 { "(bad)", { XX } },
2935 { "(bad)", { XX } },
2936 { "pmovzxwd", { XM, EXq } },
2937 { "(bad)", { XX } },
2942 { "(bad)", { XX } },
2943 { "(bad)", { XX } },
2944 { "pmovzxwq", { XM, EXd } },
2945 { "(bad)", { XX } },
2950 { "(bad)", { XX } },
2951 { "(bad)", { XX } },
2952 { "pmovzxdq", { XM, EXq } },
2953 { "(bad)", { XX } },
2958 { "(bad)", { XX } },
2959 { "(bad)", { XX } },
2960 { "pcmpgtq", { XM, EXx } },
2961 { "(bad)", { XX } },
2966 { "(bad)", { XX } },
2967 { "(bad)", { XX } },
2968 { "pminsb", { XM, EXx } },
2969 { "(bad)", { XX } },
2974 { "(bad)", { XX } },
2975 { "(bad)", { XX } },
2976 { "pminsd", { XM, EXx } },
2977 { "(bad)", { XX } },
2982 { "(bad)", { XX } },
2983 { "(bad)", { XX } },
2984 { "pminuw", { XM, EXx } },
2985 { "(bad)", { XX } },
2990 { "(bad)", { XX } },
2991 { "(bad)", { XX } },
2992 { "pminud", { XM, EXx } },
2993 { "(bad)", { XX } },
2998 { "(bad)", { XX } },
2999 { "(bad)", { XX } },
3000 { "pmaxsb", { XM, EXx } },
3001 { "(bad)", { XX } },
3006 { "(bad)", { XX } },
3007 { "(bad)", { XX } },
3008 { "pmaxsd", { XM, EXx } },
3009 { "(bad)", { XX } },
3014 { "(bad)", { XX } },
3015 { "(bad)", { XX } },
3016 { "pmaxuw", { XM, EXx } },
3017 { "(bad)", { XX } },
3022 { "(bad)", { XX } },
3023 { "(bad)", { XX } },
3024 { "pmaxud", { XM, EXx } },
3025 { "(bad)", { XX } },
3030 { "(bad)", { XX } },
3031 { "(bad)", { XX } },
3032 { "pmulld", { XM, EXx } },
3033 { "(bad)", { XX } },
3038 { "(bad)", { XX } },
3039 { "(bad)", { XX } },
3040 { "phminposuw", { XM, EXx } },
3041 { "(bad)", { XX } },
3046 { "(bad)", { XX } },
3047 { "(bad)", { XX } },
3048 { "invept", { Gm, Mo } },
3049 { "(bad)", { XX } },
3054 { "(bad)", { XX } },
3055 { "(bad)", { XX } },
3056 { "invvpid", { Gm, Mo } },
3057 { "(bad)", { XX } },
3062 { "(bad)", { XX } },
3063 { "(bad)", { XX } },
3064 { "aesimc", { XM, EXx } },
3065 { "(bad)", { XX } },
3070 { "(bad)", { XX } },
3071 { "(bad)", { XX } },
3072 { "aesenc", { XM, EXx } },
3073 { "(bad)", { XX } },
3078 { "(bad)", { XX } },
3079 { "(bad)", { XX } },
3080 { "aesenclast", { XM, EXx } },
3081 { "(bad)", { XX } },
3086 { "(bad)", { XX } },
3087 { "(bad)", { XX } },
3088 { "aesdec", { XM, EXx } },
3089 { "(bad)", { XX } },
3094 { "(bad)", { XX } },
3095 { "(bad)", { XX } },
3096 { "aesdeclast", { XM, EXx } },
3097 { "(bad)", { XX } },
3102 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3103 { "(bad)", { XX } },
3104 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3105 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
3110 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3111 { "(bad)", { XX } },
3112 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3113 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
3118 { "(bad)", { XX } },
3119 { "(bad)", { XX } },
3120 { "roundps", { XM, EXx, Ib } },
3121 { "(bad)", { XX } },
3126 { "(bad)", { XX } },
3127 { "(bad)", { XX } },
3128 { "roundpd", { XM, EXx, Ib } },
3129 { "(bad)", { XX } },
3134 { "(bad)", { XX } },
3135 { "(bad)", { XX } },
3136 { "roundss", { XM, EXd, Ib } },
3137 { "(bad)", { XX } },
3142 { "(bad)", { XX } },
3143 { "(bad)", { XX } },
3144 { "roundsd", { XM, EXq, Ib } },
3145 { "(bad)", { XX } },
3150 { "(bad)", { XX } },
3151 { "(bad)", { XX } },
3152 { "blendps", { XM, EXx, Ib } },
3153 { "(bad)", { XX } },
3158 { "(bad)", { XX } },
3159 { "(bad)", { XX } },
3160 { "blendpd", { XM, EXx, Ib } },
3161 { "(bad)", { XX } },
3166 { "(bad)", { XX } },
3167 { "(bad)", { XX } },
3168 { "pblendw", { XM, EXx, Ib } },
3169 { "(bad)", { XX } },
3174 { "(bad)", { XX } },
3175 { "(bad)", { XX } },
3176 { "pextrb", { Edqb, XM, Ib } },
3177 { "(bad)", { XX } },
3182 { "(bad)", { XX } },
3183 { "(bad)", { XX } },
3184 { "pextrw", { Edqw, XM, Ib } },
3185 { "(bad)", { XX } },
3190 { "(bad)", { XX } },
3191 { "(bad)", { XX } },
3192 { "pextrK", { Edq, XM, Ib } },
3193 { "(bad)", { XX } },
3198 { "(bad)", { XX } },
3199 { "(bad)", { XX } },
3200 { "extractps", { Edqd, XM, Ib } },
3201 { "(bad)", { XX } },
3206 { "(bad)", { XX } },
3207 { "(bad)", { XX } },
3208 { "pinsrb", { XM, Edqb, Ib } },
3209 { "(bad)", { XX } },
3214 { "(bad)", { XX } },
3215 { "(bad)", { XX } },
3216 { "insertps", { XM, EXd, Ib } },
3217 { "(bad)", { XX } },
3222 { "(bad)", { XX } },
3223 { "(bad)", { XX } },
3224 { "pinsrK", { XM, Edq, Ib } },
3225 { "(bad)", { XX } },
3230 { "(bad)", { XX } },
3231 { "(bad)", { XX } },
3232 { "dpps", { XM, EXx, Ib } },
3233 { "(bad)", { XX } },
3238 { "(bad)", { XX } },
3239 { "(bad)", { XX } },
3240 { "dppd", { XM, EXx, Ib } },
3241 { "(bad)", { XX } },
3246 { "(bad)", { XX } },
3247 { "(bad)", { XX } },
3248 { "mpsadbw", { XM, EXx, Ib } },
3249 { "(bad)", { XX } },
3254 { "(bad)", { XX } },
3255 { "(bad)", { XX } },
3256 { "pclmulqdq", { XM, EXx, PCLMUL } },
3257 { "(bad)", { XX } },
3262 { "(bad)", { XX } },
3263 { "(bad)", { XX } },
3264 { "pcmpestrm", { XM, EXx, Ib } },
3265 { "(bad)", { XX } },
3270 { "(bad)", { XX } },
3271 { "(bad)", { XX } },
3272 { "pcmpestri", { XM, EXx, Ib } },
3273 { "(bad)", { XX } },
3278 { "(bad)", { XX } },
3279 { "(bad)", { XX } },
3280 { "pcmpistrm", { XM, EXx, Ib } },
3281 { "(bad)", { XX } },
3286 { "(bad)", { XX } },
3287 { "(bad)", { XX } },
3288 { "pcmpistri", { XM, EXx, Ib } },
3289 { "(bad)", { XX } },
3294 { "(bad)", { XX } },
3295 { "(bad)", { XX } },
3296 { "aeskeygenassist", { XM, EXx, Ib } },
3297 { "(bad)", { XX } },
3302 { "vmovups", { XM, EXx } },
3303 { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3304 { "vmovupd", { XM, EXx } },
3305 { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3310 { "vmovups", { EXxS, XM } },
3311 { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3312 { "vmovupd", { EXxS, XM } },
3313 { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3318 { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3319 { "vmovsldup", { XM, EXx } },
3320 { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3321 { "vmovddup", { XM, EXymmq } },
3326 { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3327 { "vmovshdup", { XM, EXx } },
3328 { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3329 { "(bad)", { XX } },
3334 { "(bad)", { XX } },
3335 { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3336 { "(bad)", { XX } },
3337 { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3342 { "(bad)", { XX } },
3343 { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3344 { "(bad)", { XX } },
3345 { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3350 { "(bad)", { XX } },
3351 { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3352 { "(bad)", { XX } },
3353 { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3358 { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3359 { "(bad)", { XX } },
3360 { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3361 { "(bad)", { XX } },
3366 { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3367 { "(bad)", { XX } },
3368 { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3369 { "(bad)", { XX } },
3374 { "vsqrtps", { XM, EXx } },
3375 { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3376 { "vsqrtpd", { XM, EXx } },
3377 { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3382 { "vrsqrtps", { XM, EXx } },
3383 { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3384 { "(bad)", { XX } },
3385 { "(bad)", { XX } },
3390 { "vrcpps", { XM, EXx } },
3391 { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3392 { "(bad)", { XX } },
3393 { "(bad)", { XX } },
3398 { "vaddps", { XM, Vex, EXx } },
3399 { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3400 { "vaddpd", { XM, Vex, EXx } },
3401 { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3406 { "vmulps", { XM, Vex, EXx } },
3407 { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3408 { "vmulpd", { XM, Vex, EXx } },
3409 { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3414 { "vcvtps2pd", { XM, EXxmmq } },
3415 { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3416 { "vcvtpd2ps%XY", { XMM, EXx } },
3417 { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3422 { "vcvtdq2ps", { XM, EXx } },
3423 { "vcvttps2dq", { XM, EXx } },
3424 { "vcvtps2dq", { XM, EXx } },
3425 { "(bad)", { XX } },
3430 { "vsubps", { XM, Vex, EXx } },
3431 { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3432 { "vsubpd", { XM, Vex, EXx } },
3433 { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3438 { "vminps", { XM, Vex, EXx } },
3439 { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3440 { "vminpd", { XM, Vex, EXx } },
3441 { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3446 { "vdivps", { XM, Vex, EXx } },
3447 { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3448 { "vdivpd", { XM, Vex, EXx } },
3449 { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3454 { "vmaxps", { XM, Vex, EXx } },
3455 { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3456 { "vmaxpd", { XM, Vex, EXx } },
3457 { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3462 { "(bad)", { XX } },
3463 { "(bad)", { XX } },
3464 { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3465 { "(bad)", { XX } },
3470 { "(bad)", { XX } },
3471 { "(bad)", { XX } },
3472 { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3473 { "(bad)", { XX } },
3478 { "(bad)", { XX } },
3479 { "(bad)", { XX } },
3480 { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3481 { "(bad)", { XX } },
3486 { "(bad)", { XX } },
3487 { "(bad)", { XX } },
3488 { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3489 { "(bad)", { XX } },
3494 { "(bad)", { XX } },
3495 { "(bad)", { XX } },
3496 { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3497 { "(bad)", { XX } },
3502 { "(bad)", { XX } },
3503 { "(bad)", { XX } },
3504 { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3505 { "(bad)", { XX } },
3510 { "(bad)", { XX } },
3511 { "(bad)", { XX } },
3512 { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3513 { "(bad)", { XX } },
3518 { "(bad)", { XX } },
3519 { "(bad)", { XX } },
3520 { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3521 { "(bad)", { XX } },
3526 { "(bad)", { XX } },
3527 { "(bad)", { XX } },
3528 { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3529 { "(bad)", { XX } },
3534 { "(bad)", { XX } },
3535 { "(bad)", { XX } },
3536 { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3537 { "(bad)", { XX } },
3542 { "(bad)", { XX } },
3543 { "(bad)", { XX } },
3544 { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3545 { "(bad)", { XX } },
3550 { "(bad)", { XX } },
3551 { "(bad)", { XX } },
3552 { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3553 { "(bad)", { XX } },
3558 { "(bad)", { XX } },
3559 { "(bad)", { XX } },
3560 { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3561 { "(bad)", { XX } },
3566 { "(bad)", { XX } },
3567 { "(bad)", { XX } },
3568 { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3569 { "(bad)", { XX } },
3574 { "(bad)", { XX } },
3575 { "(bad)", { XX } },
3576 { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3577 { "(bad)", { XX } },
3582 { "(bad)", { XX } },
3583 { "vmovdqu", { XM, EXx } },
3584 { "vmovdqa", { XM, EXx } },
3585 { "(bad)", { XX } },
3590 { "(bad)", { XX } },
3591 { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3592 { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3593 { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3596 /* PREFIX_VEX_71_REG_2 */
3598 { "(bad)", { XX } },
3599 { "(bad)", { XX } },
3600 { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3601 { "(bad)", { XX } },
3604 /* PREFIX_VEX_71_REG_4 */
3606 { "(bad)", { XX } },
3607 { "(bad)", { XX } },
3608 { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3609 { "(bad)", { XX } },
3612 /* PREFIX_VEX_71_REG_6 */
3614 { "(bad)", { XX } },
3615 { "(bad)", { XX } },
3616 { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3617 { "(bad)", { XX } },
3620 /* PREFIX_VEX_72_REG_2 */
3622 { "(bad)", { XX } },
3623 { "(bad)", { XX } },
3624 { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3625 { "(bad)", { XX } },
3628 /* PREFIX_VEX_72_REG_4 */
3630 { "(bad)", { XX } },
3631 { "(bad)", { XX } },
3632 { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3633 { "(bad)", { XX } },
3636 /* PREFIX_VEX_72_REG_6 */
3638 { "(bad)", { XX } },
3639 { "(bad)", { XX } },
3640 { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3641 { "(bad)", { XX } },
3644 /* PREFIX_VEX_73_REG_2 */
3646 { "(bad)", { XX } },
3647 { "(bad)", { XX } },
3648 { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3649 { "(bad)", { XX } },
3652 /* PREFIX_VEX_73_REG_3 */
3654 { "(bad)", { XX } },
3655 { "(bad)", { XX } },
3656 { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3657 { "(bad)", { XX } },
3660 /* PREFIX_VEX_73_REG_6 */
3662 { "(bad)", { XX } },
3663 { "(bad)", { XX } },
3664 { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3665 { "(bad)", { XX } },
3668 /* PREFIX_VEX_73_REG_7 */
3670 { "(bad)", { XX } },
3671 { "(bad)", { XX } },
3672 { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3673 { "(bad)", { XX } },
3678 { "(bad)", { XX } },
3679 { "(bad)", { XX } },
3680 { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3681 { "(bad)", { XX } },
3686 { "(bad)", { XX } },
3687 { "(bad)", { XX } },
3688 { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3689 { "(bad)", { XX } },
3694 { "(bad)", { XX } },
3695 { "(bad)", { XX } },
3696 { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3697 { "(bad)", { XX } },
3703 { "(bad)", { XX } },
3704 { "(bad)", { XX } },
3705 { "(bad)", { XX } },
3710 { "(bad)", { XX } },
3711 { "(bad)", { XX } },
3712 { "vhaddpd", { XM, Vex, EXx } },
3713 { "vhaddps", { XM, Vex, EXx } },
3718 { "(bad)", { XX } },
3719 { "(bad)", { XX } },
3720 { "vhsubpd", { XM, Vex, EXx } },
3721 { "vhsubps", { XM, Vex, EXx } },
3726 { "(bad)", { XX } },
3727 { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3728 { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3729 { "(bad)", { XX } },
3734 { "(bad)", { XX } },
3735 { "vmovdqu", { EXxS, XM } },
3736 { "vmovdqa", { EXxS, XM } },
3737 { "(bad)", { XX } },
3742 { "vcmpps", { XM, Vex, EXx, VCMP } },
3743 { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3744 { "vcmppd", { XM, Vex, EXx, VCMP } },
3745 { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3750 { "(bad)", { XX } },
3751 { "(bad)", { XX } },
3752 { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3753 { "(bad)", { XX } },
3758 { "(bad)", { XX } },
3759 { "(bad)", { XX } },
3760 { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3761 { "(bad)", { XX } },
3766 { "(bad)", { XX } },
3767 { "(bad)", { XX } },
3768 { "vaddsubpd", { XM, Vex, EXx } },
3769 { "vaddsubps", { XM, Vex, EXx } },
3774 { "(bad)", { XX } },
3775 { "(bad)", { XX } },
3776 { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3777 { "(bad)", { XX } },
3782 { "(bad)", { XX } },
3783 { "(bad)", { XX } },
3784 { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3785 { "(bad)", { XX } },
3790 { "(bad)", { XX } },
3791 { "(bad)", { XX } },
3792 { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3793 { "(bad)", { XX } },
3798 { "(bad)", { XX } },
3799 { "(bad)", { XX } },
3800 { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3801 { "(bad)", { XX } },
3806 { "(bad)", { XX } },
3807 { "(bad)", { XX } },
3808 { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
3809 { "(bad)", { XX } },
3814 { "(bad)", { XX } },
3815 { "(bad)", { XX } },
3816 { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
3817 { "(bad)", { XX } },
3822 { "(bad)", { XX } },
3823 { "(bad)", { XX } },
3824 { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
3825 { "(bad)", { XX } },
3830 { "(bad)", { XX } },
3831 { "(bad)", { XX } },
3832 { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
3833 { "(bad)", { XX } },
3838 { "(bad)", { XX } },
3839 { "(bad)", { XX } },
3840 { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
3841 { "(bad)", { XX } },
3846 { "(bad)", { XX } },
3847 { "(bad)", { XX } },
3848 { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
3849 { "(bad)", { XX } },
3854 { "(bad)", { XX } },
3855 { "(bad)", { XX } },
3856 { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
3857 { "(bad)", { XX } },
3862 { "(bad)", { XX } },
3863 { "(bad)", { XX } },
3864 { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
3865 { "(bad)", { XX } },
3870 { "(bad)", { XX } },
3871 { "(bad)", { XX } },
3872 { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
3873 { "(bad)", { XX } },
3878 { "(bad)", { XX } },
3879 { "(bad)", { XX } },
3880 { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
3881 { "(bad)", { XX } },
3886 { "(bad)", { XX } },
3887 { "(bad)", { XX } },
3888 { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
3889 { "(bad)", { XX } },
3894 { "(bad)", { XX } },
3895 { "(bad)", { XX } },
3896 { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
3897 { "(bad)", { XX } },
3902 { "(bad)", { XX } },
3903 { "(bad)", { XX } },
3904 { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
3905 { "(bad)", { XX } },
3910 { "(bad)", { XX } },
3911 { "(bad)", { XX } },
3912 { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
3913 { "(bad)", { XX } },
3918 { "(bad)", { XX } },
3919 { "(bad)", { XX } },
3920 { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
3921 { "(bad)", { XX } },
3926 { "(bad)", { XX } },
3927 { "(bad)", { XX } },
3928 { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
3929 { "(bad)", { XX } },
3934 { "(bad)", { XX } },
3935 { "(bad)", { XX } },
3936 { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
3937 { "(bad)", { XX } },
3942 { "(bad)", { XX } },
3943 { "vcvtdq2pd", { XM, EXxmmq } },
3944 { "vcvttpd2dq%XY", { XMM, EXx } },
3945 { "vcvtpd2dq%XY", { XMM, EXx } },
3950 { "(bad)", { XX } },
3951 { "(bad)", { XX } },
3952 { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
3953 { "(bad)", { XX } },
3958 { "(bad)", { XX } },
3959 { "(bad)", { XX } },
3960 { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
3961 { "(bad)", { XX } },
3966 { "(bad)", { XX } },
3967 { "(bad)", { XX } },
3968 { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
3969 { "(bad)", { XX } },
3974 { "(bad)", { XX } },
3975 { "(bad)", { XX } },
3976 { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
3977 { "(bad)", { XX } },
3982 { "(bad)", { XX } },
3983 { "(bad)", { XX } },
3984 { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
3985 { "(bad)", { XX } },
3990 { "(bad)", { XX } },
3991 { "(bad)", { XX } },
3992 { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
3993 { "(bad)", { XX } },
3998 { "(bad)", { XX } },
3999 { "(bad)", { XX } },
4000 { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
4001 { "(bad)", { XX } },
4006 { "(bad)", { XX } },
4007 { "(bad)", { XX } },
4008 { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4009 { "(bad)", { XX } },
4014 { "(bad)", { XX } },
4015 { "(bad)", { XX } },
4016 { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4017 { "(bad)", { XX } },
4022 { "(bad)", { XX } },
4023 { "(bad)", { XX } },
4024 { "(bad)", { XX } },
4025 { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4030 { "(bad)", { XX } },
4031 { "(bad)", { XX } },
4032 { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4033 { "(bad)", { XX } },
4038 { "(bad)", { XX } },
4039 { "(bad)", { XX } },
4040 { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4041 { "(bad)", { XX } },
4046 { "(bad)", { XX } },
4047 { "(bad)", { XX } },
4048 { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4049 { "(bad)", { XX } },
4054 { "(bad)", { XX } },
4055 { "(bad)", { XX } },
4056 { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4057 { "(bad)", { XX } },
4062 { "(bad)", { XX } },
4063 { "(bad)", { XX } },
4064 { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4065 { "(bad)", { XX } },
4070 { "(bad)", { XX } },
4071 { "(bad)", { XX } },
4072 { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4073 { "(bad)", { XX } },
4078 { "(bad)", { XX } },
4079 { "(bad)", { XX } },
4080 { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4081 { "(bad)", { XX } },
4086 { "(bad)", { XX } },
4087 { "(bad)", { XX } },
4088 { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4089 { "(bad)", { XX } },
4094 { "(bad)", { XX } },
4095 { "(bad)", { XX } },
4096 { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4097 { "(bad)", { XX } },
4102 { "(bad)", { XX } },
4103 { "(bad)", { XX } },
4104 { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4105 { "(bad)", { XX } },
4110 { "(bad)", { XX } },
4111 { "(bad)", { XX } },
4112 { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4113 { "(bad)", { XX } },
4118 { "(bad)", { XX } },
4119 { "(bad)", { XX } },
4120 { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4121 { "(bad)", { XX } },
4126 { "(bad)", { XX } },
4127 { "(bad)", { XX } },
4128 { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4129 { "(bad)", { XX } },
4134 { "(bad)", { XX } },
4135 { "(bad)", { XX } },
4136 { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4137 { "(bad)", { XX } },
4140 /* PREFIX_VEX_3800 */
4142 { "(bad)", { XX } },
4143 { "(bad)", { XX } },
4144 { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4145 { "(bad)", { XX } },
4148 /* PREFIX_VEX_3801 */
4150 { "(bad)", { XX } },
4151 { "(bad)", { XX } },
4152 { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4153 { "(bad)", { XX } },
4156 /* PREFIX_VEX_3802 */
4158 { "(bad)", { XX } },
4159 { "(bad)", { XX } },
4160 { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4161 { "(bad)", { XX } },
4164 /* PREFIX_VEX_3803 */
4166 { "(bad)", { XX } },
4167 { "(bad)", { XX } },
4168 { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4169 { "(bad)", { XX } },
4172 /* PREFIX_VEX_3804 */
4174 { "(bad)", { XX } },
4175 { "(bad)", { XX } },
4176 { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4177 { "(bad)", { XX } },
4180 /* PREFIX_VEX_3805 */
4182 { "(bad)", { XX } },
4183 { "(bad)", { XX } },
4184 { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4185 { "(bad)", { XX } },
4188 /* PREFIX_VEX_3806 */
4190 { "(bad)", { XX } },
4191 { "(bad)", { XX } },
4192 { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4193 { "(bad)", { XX } },
4196 /* PREFIX_VEX_3807 */
4198 { "(bad)", { XX } },
4199 { "(bad)", { XX } },
4200 { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4201 { "(bad)", { XX } },
4204 /* PREFIX_VEX_3808 */
4206 { "(bad)", { XX } },
4207 { "(bad)", { XX } },
4208 { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4209 { "(bad)", { XX } },
4212 /* PREFIX_VEX_3809 */
4214 { "(bad)", { XX } },
4215 { "(bad)", { XX } },
4216 { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4217 { "(bad)", { XX } },
4220 /* PREFIX_VEX_380A */
4222 { "(bad)", { XX } },
4223 { "(bad)", { XX } },
4224 { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4225 { "(bad)", { XX } },
4228 /* PREFIX_VEX_380B */
4230 { "(bad)", { XX } },
4231 { "(bad)", { XX } },
4232 { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4233 { "(bad)", { XX } },
4236 /* PREFIX_VEX_380C */
4238 { "(bad)", { XX } },
4239 { "(bad)", { XX } },
4240 { "vpermilps", { XM, Vex, EXx } },
4241 { "(bad)", { XX } },
4244 /* PREFIX_VEX_380D */
4246 { "(bad)", { XX } },
4247 { "(bad)", { XX } },
4248 { "vpermilpd", { XM, Vex, EXx } },
4249 { "(bad)", { XX } },
4252 /* PREFIX_VEX_380E */
4254 { "(bad)", { XX } },
4255 { "(bad)", { XX } },
4256 { "vtestps", { XM, EXx } },
4257 { "(bad)", { XX } },
4260 /* PREFIX_VEX_380F */
4262 { "(bad)", { XX } },
4263 { "(bad)", { XX } },
4264 { "vtestpd", { XM, EXx } },
4265 { "(bad)", { XX } },
4268 /* PREFIX_VEX_3817 */
4270 { "(bad)", { XX } },
4271 { "(bad)", { XX } },
4272 { "vptest", { XM, EXx } },
4273 { "(bad)", { XX } },
4276 /* PREFIX_VEX_3818 */
4278 { "(bad)", { XX } },
4279 { "(bad)", { XX } },
4280 { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4281 { "(bad)", { XX } },
4284 /* PREFIX_VEX_3819 */
4286 { "(bad)", { XX } },
4287 { "(bad)", { XX } },
4288 { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4289 { "(bad)", { XX } },
4292 /* PREFIX_VEX_381A */
4294 { "(bad)", { XX } },
4295 { "(bad)", { XX } },
4296 { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4297 { "(bad)", { XX } },
4300 /* PREFIX_VEX_381C */
4302 { "(bad)", { XX } },
4303 { "(bad)", { XX } },
4304 { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4305 { "(bad)", { XX } },
4308 /* PREFIX_VEX_381D */
4310 { "(bad)", { XX } },
4311 { "(bad)", { XX } },
4312 { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4313 { "(bad)", { XX } },
4316 /* PREFIX_VEX_381E */
4318 { "(bad)", { XX } },
4319 { "(bad)", { XX } },
4320 { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4321 { "(bad)", { XX } },
4324 /* PREFIX_VEX_3820 */
4326 { "(bad)", { XX } },
4327 { "(bad)", { XX } },
4328 { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4329 { "(bad)", { XX } },
4332 /* PREFIX_VEX_3821 */
4334 { "(bad)", { XX } },
4335 { "(bad)", { XX } },
4336 { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4337 { "(bad)", { XX } },
4340 /* PREFIX_VEX_3822 */
4342 { "(bad)", { XX } },
4343 { "(bad)", { XX } },
4344 { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4345 { "(bad)", { XX } },
4348 /* PREFIX_VEX_3823 */
4350 { "(bad)", { XX } },
4351 { "(bad)", { XX } },
4352 { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4353 { "(bad)", { XX } },
4356 /* PREFIX_VEX_3824 */
4358 { "(bad)", { XX } },
4359 { "(bad)", { XX } },
4360 { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4361 { "(bad)", { XX } },
4364 /* PREFIX_VEX_3825 */
4366 { "(bad)", { XX } },
4367 { "(bad)", { XX } },
4368 { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4369 { "(bad)", { XX } },
4372 /* PREFIX_VEX_3828 */
4374 { "(bad)", { XX } },
4375 { "(bad)", { XX } },
4376 { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4377 { "(bad)", { XX } },
4380 /* PREFIX_VEX_3829 */
4382 { "(bad)", { XX } },
4383 { "(bad)", { XX } },
4384 { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4385 { "(bad)", { XX } },
4388 /* PREFIX_VEX_382A */
4390 { "(bad)", { XX } },
4391 { "(bad)", { XX } },
4392 { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4393 { "(bad)", { XX } },
4396 /* PREFIX_VEX_382B */
4398 { "(bad)", { XX } },
4399 { "(bad)", { XX } },
4400 { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4401 { "(bad)", { XX } },
4404 /* PREFIX_VEX_382C */
4406 { "(bad)", { XX } },
4407 { "(bad)", { XX } },
4408 { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4409 { "(bad)", { XX } },
4412 /* PREFIX_VEX_382D */
4414 { "(bad)", { XX } },
4415 { "(bad)", { XX } },
4416 { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4417 { "(bad)", { XX } },
4420 /* PREFIX_VEX_382E */
4422 { "(bad)", { XX } },
4423 { "(bad)", { XX } },
4424 { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4425 { "(bad)", { XX } },
4428 /* PREFIX_VEX_382F */
4430 { "(bad)", { XX } },
4431 { "(bad)", { XX } },
4432 { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4433 { "(bad)", { XX } },
4436 /* PREFIX_VEX_3830 */
4438 { "(bad)", { XX } },
4439 { "(bad)", { XX } },
4440 { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4441 { "(bad)", { XX } },
4444 /* PREFIX_VEX_3831 */
4446 { "(bad)", { XX } },
4447 { "(bad)", { XX } },
4448 { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4449 { "(bad)", { XX } },
4452 /* PREFIX_VEX_3832 */
4454 { "(bad)", { XX } },
4455 { "(bad)", { XX } },
4456 { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4457 { "(bad)", { XX } },
4460 /* PREFIX_VEX_3833 */
4462 { "(bad)", { XX } },
4463 { "(bad)", { XX } },
4464 { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4465 { "(bad)", { XX } },
4468 /* PREFIX_VEX_3834 */
4470 { "(bad)", { XX } },
4471 { "(bad)", { XX } },
4472 { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4473 { "(bad)", { XX } },
4476 /* PREFIX_VEX_3835 */
4478 { "(bad)", { XX } },
4479 { "(bad)", { XX } },
4480 { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4481 { "(bad)", { XX } },
4484 /* PREFIX_VEX_3837 */
4486 { "(bad)", { XX } },
4487 { "(bad)", { XX } },
4488 { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4489 { "(bad)", { XX } },
4492 /* PREFIX_VEX_3838 */
4494 { "(bad)", { XX } },
4495 { "(bad)", { XX } },
4496 { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4497 { "(bad)", { XX } },
4500 /* PREFIX_VEX_3839 */
4502 { "(bad)", { XX } },
4503 { "(bad)", { XX } },
4504 { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4505 { "(bad)", { XX } },
4508 /* PREFIX_VEX_383A */
4510 { "(bad)", { XX } },
4511 { "(bad)", { XX } },
4512 { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4513 { "(bad)", { XX } },
4516 /* PREFIX_VEX_383B */
4518 { "(bad)", { XX } },
4519 { "(bad)", { XX } },
4520 { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4521 { "(bad)", { XX } },
4524 /* PREFIX_VEX_383C */
4526 { "(bad)", { XX } },
4527 { "(bad)", { XX } },
4528 { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4529 { "(bad)", { XX } },
4532 /* PREFIX_VEX_383D */
4534 { "(bad)", { XX } },
4535 { "(bad)", { XX } },
4536 { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4537 { "(bad)", { XX } },
4540 /* PREFIX_VEX_383E */
4542 { "(bad)", { XX } },
4543 { "(bad)", { XX } },
4544 { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4545 { "(bad)", { XX } },
4548 /* PREFIX_VEX_383F */
4550 { "(bad)", { XX } },
4551 { "(bad)", { XX } },
4552 { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4553 { "(bad)", { XX } },
4556 /* PREFIX_VEX_3840 */
4558 { "(bad)", { XX } },
4559 { "(bad)", { XX } },
4560 { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4561 { "(bad)", { XX } },
4564 /* PREFIX_VEX_3841 */
4566 { "(bad)", { XX } },
4567 { "(bad)", { XX } },
4568 { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4569 { "(bad)", { XX } },
4572 /* PREFIX_VEX_3896 */
4574 { "(bad)", { XX } },
4575 { "(bad)", { XX } },
4576 { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4577 { "(bad)", { XX } },
4580 /* PREFIX_VEX_3897 */
4582 { "(bad)", { XX } },
4583 { "(bad)", { XX } },
4584 { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4585 { "(bad)", { XX } },
4588 /* PREFIX_VEX_3898 */
4590 { "(bad)", { XX } },
4591 { "(bad)", { XX } },
4592 { "vfmadd132p%XW", { XM, Vex, EXx } },
4593 { "(bad)", { XX } },
4596 /* PREFIX_VEX_3899 */
4598 { "(bad)", { XX } },
4599 { "(bad)", { XX } },
4600 { "vfmadd132s%XW", { XM, Vex, EXVexWdq } },
4601 { "(bad)", { XX } },
4604 /* PREFIX_VEX_389A */
4606 { "(bad)", { XX } },
4607 { "(bad)", { XX } },
4608 { "vfmsub132p%XW", { XM, Vex, EXx } },
4609 { "(bad)", { XX } },
4612 /* PREFIX_VEX_389B */
4614 { "(bad)", { XX } },
4615 { "(bad)", { XX } },
4616 { "vfmsub132s%XW", { XM, Vex, EXVexWdq } },
4617 { "(bad)", { XX } },
4620 /* PREFIX_VEX_389C */
4622 { "(bad)", { XX } },
4623 { "(bad)", { XX } },
4624 { "vfnmadd132p%XW", { XM, Vex, EXx } },
4625 { "(bad)", { XX } },
4628 /* PREFIX_VEX_389D */
4630 { "(bad)", { XX } },
4631 { "(bad)", { XX } },
4632 { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } },
4633 { "(bad)", { XX } },
4636 /* PREFIX_VEX_389E */
4638 { "(bad)", { XX } },
4639 { "(bad)", { XX } },
4640 { "vfnmsub132p%XW", { XM, Vex, EXx } },
4641 { "(bad)", { XX } },
4644 /* PREFIX_VEX_389F */
4646 { "(bad)", { XX } },
4647 { "(bad)", { XX } },
4648 { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } },
4649 { "(bad)", { XX } },
4652 /* PREFIX_VEX_38A6 */
4654 { "(bad)", { XX } },
4655 { "(bad)", { XX } },
4656 { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4657 { "(bad)", { XX } },
4660 /* PREFIX_VEX_38A7 */
4662 { "(bad)", { XX } },
4663 { "(bad)", { XX } },
4664 { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4665 { "(bad)", { XX } },
4668 /* PREFIX_VEX_38A8 */
4670 { "(bad)", { XX } },
4671 { "(bad)", { XX } },
4672 { "vfmadd213p%XW", { XM, Vex, EXx } },
4673 { "(bad)", { XX } },
4676 /* PREFIX_VEX_38A9 */
4678 { "(bad)", { XX } },
4679 { "(bad)", { XX } },
4680 { "vfmadd213s%XW", { XM, Vex, EXVexWdq } },
4681 { "(bad)", { XX } },
4684 /* PREFIX_VEX_38AA */
4686 { "(bad)", { XX } },
4687 { "(bad)", { XX } },
4688 { "vfmsub213p%XW", { XM, Vex, EXx } },
4689 { "(bad)", { XX } },
4692 /* PREFIX_VEX_38AB */
4694 { "(bad)", { XX } },
4695 { "(bad)", { XX } },
4696 { "vfmsub213s%XW", { XM, Vex, EXVexWdq } },
4697 { "(bad)", { XX } },
4700 /* PREFIX_VEX_38AC */
4702 { "(bad)", { XX } },
4703 { "(bad)", { XX } },
4704 { "vfnmadd213p%XW", { XM, Vex, EXx } },
4705 { "(bad)", { XX } },
4708 /* PREFIX_VEX_38AD */
4710 { "(bad)", { XX } },
4711 { "(bad)", { XX } },
4712 { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } },
4713 { "(bad)", { XX } },
4716 /* PREFIX_VEX_38AE */
4718 { "(bad)", { XX } },
4719 { "(bad)", { XX } },
4720 { "vfnmsub213p%XW", { XM, Vex, EXx } },
4721 { "(bad)", { XX } },
4724 /* PREFIX_VEX_38AF */
4726 { "(bad)", { XX } },
4727 { "(bad)", { XX } },
4728 { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } },
4729 { "(bad)", { XX } },
4732 /* PREFIX_VEX_38B6 */
4734 { "(bad)", { XX } },
4735 { "(bad)", { XX } },
4736 { "vfmaddsub231p%XW", { XM, Vex, EXx } },
4737 { "(bad)", { XX } },
4740 /* PREFIX_VEX_38B7 */
4742 { "(bad)", { XX } },
4743 { "(bad)", { XX } },
4744 { "vfmsubadd231p%XW", { XM, Vex, EXx } },
4745 { "(bad)", { XX } },
4748 /* PREFIX_VEX_38B8 */
4750 { "(bad)", { XX } },
4751 { "(bad)", { XX } },
4752 { "vfmadd231p%XW", { XM, Vex, EXx } },
4753 { "(bad)", { XX } },
4756 /* PREFIX_VEX_38B9 */
4758 { "(bad)", { XX } },
4759 { "(bad)", { XX } },
4760 { "vfmadd231s%XW", { XM, Vex, EXVexWdq } },
4761 { "(bad)", { XX } },
4764 /* PREFIX_VEX_38BA */
4766 { "(bad)", { XX } },
4767 { "(bad)", { XX } },
4768 { "vfmsub231p%XW", { XM, Vex, EXx } },
4769 { "(bad)", { XX } },
4772 /* PREFIX_VEX_38BB */
4774 { "(bad)", { XX } },
4775 { "(bad)", { XX } },
4776 { "vfmsub231s%XW", { XM, Vex, EXVexWdq } },
4777 { "(bad)", { XX } },
4780 /* PREFIX_VEX_38BC */
4782 { "(bad)", { XX } },
4783 { "(bad)", { XX } },
4784 { "vfnmadd231p%XW", { XM, Vex, EXx } },
4785 { "(bad)", { XX } },
4788 /* PREFIX_VEX_38BD */
4790 { "(bad)", { XX } },
4791 { "(bad)", { XX } },
4792 { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } },
4793 { "(bad)", { XX } },
4796 /* PREFIX_VEX_38BE */
4798 { "(bad)", { XX } },
4799 { "(bad)", { XX } },
4800 { "vfnmsub231p%XW", { XM, Vex, EXx } },
4801 { "(bad)", { XX } },
4804 /* PREFIX_VEX_38BF */
4806 { "(bad)", { XX } },
4807 { "(bad)", { XX } },
4808 { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } },
4809 { "(bad)", { XX } },
4812 /* PREFIX_VEX_38DB */
4814 { "(bad)", { XX } },
4815 { "(bad)", { XX } },
4816 { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
4817 { "(bad)", { XX } },
4820 /* PREFIX_VEX_38DC */
4822 { "(bad)", { XX } },
4823 { "(bad)", { XX } },
4824 { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
4825 { "(bad)", { XX } },
4828 /* PREFIX_VEX_38DD */
4830 { "(bad)", { XX } },
4831 { "(bad)", { XX } },
4832 { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
4833 { "(bad)", { XX } },
4836 /* PREFIX_VEX_38DE */
4838 { "(bad)", { XX } },
4839 { "(bad)", { XX } },
4840 { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
4841 { "(bad)", { XX } },
4844 /* PREFIX_VEX_38DF */
4846 { "(bad)", { XX } },
4847 { "(bad)", { XX } },
4848 { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
4849 { "(bad)", { XX } },
4852 /* PREFIX_VEX_3A04 */
4854 { "(bad)", { XX } },
4855 { "(bad)", { XX } },
4856 { "vpermilps", { XM, EXx, Ib } },
4857 { "(bad)", { XX } },
4860 /* PREFIX_VEX_3A05 */
4862 { "(bad)", { XX } },
4863 { "(bad)", { XX } },
4864 { "vpermilpd", { XM, EXx, Ib } },
4865 { "(bad)", { XX } },
4868 /* PREFIX_VEX_3A06 */
4870 { "(bad)", { XX } },
4871 { "(bad)", { XX } },
4872 { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4873 { "(bad)", { XX } },
4876 /* PREFIX_VEX_3A08 */
4878 { "(bad)", { XX } },
4879 { "(bad)", { XX } },
4880 { "vroundps", { XM, EXx, Ib } },
4881 { "(bad)", { XX } },
4884 /* PREFIX_VEX_3A09 */
4886 { "(bad)", { XX } },
4887 { "(bad)", { XX } },
4888 { "vroundpd", { XM, EXx, Ib } },
4889 { "(bad)", { XX } },
4892 /* PREFIX_VEX_3A0A */
4894 { "(bad)", { XX } },
4895 { "(bad)", { XX } },
4896 { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4897 { "(bad)", { XX } },
4900 /* PREFIX_VEX_3A0B */
4902 { "(bad)", { XX } },
4903 { "(bad)", { XX } },
4904 { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4905 { "(bad)", { XX } },
4908 /* PREFIX_VEX_3A0C */
4910 { "(bad)", { XX } },
4911 { "(bad)", { XX } },
4912 { "vblendps", { XM, Vex, EXx, Ib } },
4913 { "(bad)", { XX } },
4916 /* PREFIX_VEX_3A0D */
4918 { "(bad)", { XX } },
4919 { "(bad)", { XX } },
4920 { "vblendpd", { XM, Vex, EXx, Ib } },
4921 { "(bad)", { XX } },
4924 /* PREFIX_VEX_3A0E */
4926 { "(bad)", { XX } },
4927 { "(bad)", { XX } },
4928 { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4929 { "(bad)", { XX } },
4932 /* PREFIX_VEX_3A0F */
4934 { "(bad)", { XX } },
4935 { "(bad)", { XX } },
4936 { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
4937 { "(bad)", { XX } },
4940 /* PREFIX_VEX_3A14 */
4942 { "(bad)", { XX } },
4943 { "(bad)", { XX } },
4944 { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
4945 { "(bad)", { XX } },
4948 /* PREFIX_VEX_3A15 */
4950 { "(bad)", { XX } },
4951 { "(bad)", { XX } },
4952 { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
4953 { "(bad)", { XX } },
4956 /* PREFIX_VEX_3A16 */
4958 { "(bad)", { XX } },
4959 { "(bad)", { XX } },
4960 { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
4961 { "(bad)", { XX } },
4964 /* PREFIX_VEX_3A17 */
4966 { "(bad)", { XX } },
4967 { "(bad)", { XX } },
4968 { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
4969 { "(bad)", { XX } },
4972 /* PREFIX_VEX_3A18 */
4974 { "(bad)", { XX } },
4975 { "(bad)", { XX } },
4976 { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
4977 { "(bad)", { XX } },
4980 /* PREFIX_VEX_3A19 */
4982 { "(bad)", { XX } },
4983 { "(bad)", { XX } },
4984 { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
4985 { "(bad)", { XX } },
4988 /* PREFIX_VEX_3A20 */
4990 { "(bad)", { XX } },
4991 { "(bad)", { XX } },
4992 { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
4993 { "(bad)", { XX } },
4996 /* PREFIX_VEX_3A21 */
4998 { "(bad)", { XX } },
4999 { "(bad)", { XX } },
5000 { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
5001 { "(bad)", { XX } },
5004 /* PREFIX_VEX_3A22 */
5006 { "(bad)", { XX } },
5007 { "(bad)", { XX } },
5008 { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5009 { "(bad)", { XX } },
5012 /* PREFIX_VEX_3A40 */
5014 { "(bad)", { XX } },
5015 { "(bad)", { XX } },
5016 { "vdpps", { XM, Vex, EXx, Ib } },
5017 { "(bad)", { XX } },
5020 /* PREFIX_VEX_3A41 */
5022 { "(bad)", { XX } },
5023 { "(bad)", { XX } },
5024 { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
5025 { "(bad)", { XX } },
5028 /* PREFIX_VEX_3A42 */
5030 { "(bad)", { XX } },
5031 { "(bad)", { XX } },
5032 { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
5033 { "(bad)", { XX } },
5036 /* PREFIX_VEX_3A44 */
5038 { "(bad)", { XX } },
5039 { "(bad)", { XX } },
5040 { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },
5041 { "(bad)", { XX } },
5044 /* PREFIX_VEX_3A4A */
5046 { "(bad)", { XX } },
5047 { "(bad)", { XX } },
5048 { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
5049 { "(bad)", { XX } },
5052 /* PREFIX_VEX_3A4B */
5054 { "(bad)", { XX } },
5055 { "(bad)", { XX } },
5056 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
5057 { "(bad)", { XX } },
5060 /* PREFIX_VEX_3A4C */
5062 { "(bad)", { XX } },
5063 { "(bad)", { XX } },
5064 { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
5065 { "(bad)", { XX } },
5068 /* PREFIX_VEX_3A5C */
5070 { "(bad)", { XX } },
5071 { "(bad)", { XX } },
5072 { "vfmaddsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5073 { "(bad)", { XX } },
5076 /* PREFIX_VEX_3A5D */
5078 { "(bad)", { XX } },
5079 { "(bad)", { XX } },
5080 { "vfmaddsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5081 { "(bad)", { XX } },
5084 /* PREFIX_VEX_3A5E */
5086 { "(bad)", { XX } },
5087 { "(bad)", { XX } },
5088 { "vfmsubaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5089 { "(bad)", { XX } },
5092 /* PREFIX_VEX_3A5F */
5094 { "(bad)", { XX } },
5095 { "(bad)", { XX } },
5096 { "vfmsubaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5097 { "(bad)", { XX } },
5100 /* PREFIX_VEX_3A60 */
5102 { "(bad)", { XX } },
5103 { "(bad)", { XX } },
5104 { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
5105 { "(bad)", { XX } },
5108 /* PREFIX_VEX_3A61 */
5110 { "(bad)", { XX } },
5111 { "(bad)", { XX } },
5112 { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
5113 { "(bad)", { XX } },
5116 /* PREFIX_VEX_3A62 */
5118 { "(bad)", { XX } },
5119 { "(bad)", { XX } },
5120 { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
5121 { "(bad)", { XX } },
5124 /* PREFIX_VEX_3A63 */
5126 { "(bad)", { XX } },
5127 { "(bad)", { XX } },
5128 { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
5129 { "(bad)", { XX } },
5132 /* PREFIX_VEX_3A68 */
5134 { "(bad)", { XX } },
5135 { "(bad)", { XX } },
5136 { "vfmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5137 { "(bad)", { XX } },
5140 /* PREFIX_VEX_3A69 */
5142 { "(bad)", { XX } },
5143 { "(bad)", { XX } },
5144 { "vfmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5145 { "(bad)", { XX } },
5148 /* PREFIX_VEX_3A6A */
5150 { "(bad)", { XX } },
5151 { "(bad)", { XX } },
5152 { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
5153 { "(bad)", { XX } },
5156 /* PREFIX_VEX_3A6B */
5158 { "(bad)", { XX } },
5159 { "(bad)", { XX } },
5160 { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
5161 { "(bad)", { XX } },
5164 /* PREFIX_VEX_3A6C */
5166 { "(bad)", { XX } },
5167 { "(bad)", { XX } },
5168 { "vfmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5169 { "(bad)", { XX } },
5172 /* PREFIX_VEX_3A6D */
5174 { "(bad)", { XX } },
5175 { "(bad)", { XX } },
5176 { "vfmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5177 { "(bad)", { XX } },
5180 /* PREFIX_VEX_3A6E */
5182 { "(bad)", { XX } },
5183 { "(bad)", { XX } },
5184 { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
5185 { "(bad)", { XX } },
5188 /* PREFIX_VEX_3A6F */
5190 { "(bad)", { XX } },
5191 { "(bad)", { XX } },
5192 { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
5193 { "(bad)", { XX } },
5196 /* PREFIX_VEX_3A78 */
5198 { "(bad)", { XX } },
5199 { "(bad)", { XX } },
5200 { "vfnmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5201 { "(bad)", { XX } },
5204 /* PREFIX_VEX_3A79 */
5206 { "(bad)", { XX } },
5207 { "(bad)", { XX } },
5208 { "vfnmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5209 { "(bad)", { XX } },
5212 /* PREFIX_VEX_3A7A */
5214 { "(bad)", { XX } },
5215 { "(bad)", { XX } },
5216 { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
5217 { "(bad)", { XX } },
5220 /* PREFIX_VEX_3A7B */
5222 { "(bad)", { XX } },
5223 { "(bad)", { XX } },
5224 { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
5225 { "(bad)", { XX } },
5228 /* PREFIX_VEX_3A7C */
5230 { "(bad)", { XX } },
5231 { "(bad)", { XX } },
5232 { "vfnmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5233 { "(bad)", { XX } },
5236 /* PREFIX_VEX_3A7D */
5238 { "(bad)", { XX } },
5239 { "(bad)", { XX } },
5240 { "vfnmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5241 { "(bad)", { XX } },
5244 /* PREFIX_VEX_3A7E */
5246 { "(bad)", { XX } },
5247 { "(bad)", { XX } },
5248 { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5249 { "(bad)", { XX } },
5252 /* PREFIX_VEX_3A7F */
5254 { "(bad)", { XX } },
5255 { "(bad)", { XX } },
5256 { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5257 { "(bad)", { XX } },
5260 /* PREFIX_VEX_3ADF */
5262 { "(bad)", { XX } },
5263 { "(bad)", { XX } },
5264 { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5265 { "(bad)", { XX } },
5269 static const struct dis386 x86_64_table[][2] = {
5272 { "push{T|}", { es } },
5273 { "(bad)", { XX } },
5278 { "pop{T|}", { es } },
5279 { "(bad)", { XX } },
5284 { "push{T|}", { cs } },
5285 { "(bad)", { XX } },
5290 { "push{T|}", { ss } },
5291 { "(bad)", { XX } },
5296 { "pop{T|}", { ss } },
5297 { "(bad)", { XX } },
5302 { "push{T|}", { ds } },
5303 { "(bad)", { XX } },
5308 { "pop{T|}", { ds } },
5309 { "(bad)", { XX } },
5315 { "(bad)", { XX } },
5321 { "(bad)", { XX } },
5327 { "(bad)", { XX } },
5333 { "(bad)", { XX } },
5338 { "pusha{P|}", { XX } },
5339 { "(bad)", { XX } },
5344 { "popa{P|}", { XX } },
5345 { "(bad)", { XX } },
5350 { MOD_TABLE (MOD_62_32BIT) },
5351 { "(bad)", { XX } },
5356 { "arpl", { Ew, Gw } },
5357 { "movs{lq|xd}", { Gv, Ed } },
5362 { "ins{R|}", { Yzr, indirDX } },
5363 { "ins{G|}", { Yzr, indirDX } },
5368 { "outs{R|}", { indirDXr, Xz } },
5369 { "outs{G|}", { indirDXr, Xz } },
5374 { "Jcall{T|}", { Ap } },
5375 { "(bad)", { XX } },
5380 { MOD_TABLE (MOD_C4_32BIT) },
5381 { VEX_C4_TABLE (VEX_0F) },
5386 { MOD_TABLE (MOD_C5_32BIT) },
5387 { VEX_C5_TABLE (VEX_0F) },
5393 { "(bad)", { XX } },
5399 { "(bad)", { XX } },
5405 { "(bad)", { XX } },
5410 { "Jjmp{T|}", { Ap } },
5411 { "(bad)", { XX } },
5414 /* X86_64_0F01_REG_0 */
5416 { "sgdt{Q|IQ}", { M } },
5420 /* X86_64_0F01_REG_1 */
5422 { "sidt{Q|IQ}", { M } },
5426 /* X86_64_0F01_REG_2 */
5428 { "lgdt{Q|Q}", { M } },
5432 /* X86_64_0F01_REG_3 */
5434 { "lidt{Q|Q}", { M } },
5439 static const struct dis386 three_byte_table[][256] = {
5441 /* THREE_BYTE_0F38 */
5444 { "pshufb", { MX, EM } },
5445 { "phaddw", { MX, EM } },
5446 { "phaddd", { MX, EM } },
5447 { "phaddsw", { MX, EM } },
5448 { "pmaddubsw", { MX, EM } },
5449 { "phsubw", { MX, EM } },
5450 { "phsubd", { MX, EM } },
5451 { "phsubsw", { MX, EM } },
5453 { "psignb", { MX, EM } },
5454 { "psignw", { MX, EM } },
5455 { "psignd", { MX, EM } },
5456 { "pmulhrsw", { MX, EM } },
5457 { "(bad)", { XX } },
5458 { "(bad)", { XX } },
5459 { "(bad)", { XX } },
5460 { "(bad)", { XX } },
5462 { PREFIX_TABLE (PREFIX_0F3810) },
5463 { "(bad)", { XX } },
5464 { "(bad)", { XX } },
5465 { "(bad)", { XX } },
5466 { PREFIX_TABLE (PREFIX_0F3814) },
5467 { PREFIX_TABLE (PREFIX_0F3815) },
5468 { "(bad)", { XX } },
5469 { PREFIX_TABLE (PREFIX_0F3817) },
5471 { "(bad)", { XX } },
5472 { "(bad)", { XX } },
5473 { "(bad)", { XX } },
5474 { "(bad)", { XX } },
5475 { "pabsb", { MX, EM } },
5476 { "pabsw", { MX, EM } },
5477 { "pabsd", { MX, EM } },
5478 { "(bad)", { XX } },
5480 { PREFIX_TABLE (PREFIX_0F3820) },
5481 { PREFIX_TABLE (PREFIX_0F3821) },
5482 { PREFIX_TABLE (PREFIX_0F3822) },
5483 { PREFIX_TABLE (PREFIX_0F3823) },
5484 { PREFIX_TABLE (PREFIX_0F3824) },
5485 { PREFIX_TABLE (PREFIX_0F3825) },
5486 { "(bad)", { XX } },
5487 { "(bad)", { XX } },
5489 { PREFIX_TABLE (PREFIX_0F3828) },
5490 { PREFIX_TABLE (PREFIX_0F3829) },
5491 { PREFIX_TABLE (PREFIX_0F382A) },
5492 { PREFIX_TABLE (PREFIX_0F382B) },
5493 { "(bad)", { XX } },
5494 { "(bad)", { XX } },
5495 { "(bad)", { XX } },
5496 { "(bad)", { XX } },
5498 { PREFIX_TABLE (PREFIX_0F3830) },
5499 { PREFIX_TABLE (PREFIX_0F3831) },
5500 { PREFIX_TABLE (PREFIX_0F3832) },
5501 { PREFIX_TABLE (PREFIX_0F3833) },
5502 { PREFIX_TABLE (PREFIX_0F3834) },
5503 { PREFIX_TABLE (PREFIX_0F3835) },
5504 { "(bad)", { XX } },
5505 { PREFIX_TABLE (PREFIX_0F3837) },
5507 { PREFIX_TABLE (PREFIX_0F3838) },
5508 { PREFIX_TABLE (PREFIX_0F3839) },
5509 { PREFIX_TABLE (PREFIX_0F383A) },
5510 { PREFIX_TABLE (PREFIX_0F383B) },
5511 { PREFIX_TABLE (PREFIX_0F383C) },
5512 { PREFIX_TABLE (PREFIX_0F383D) },
5513 { PREFIX_TABLE (PREFIX_0F383E) },
5514 { PREFIX_TABLE (PREFIX_0F383F) },
5516 { PREFIX_TABLE (PREFIX_0F3840) },
5517 { PREFIX_TABLE (PREFIX_0F3841) },
5518 { "(bad)", { XX } },
5519 { "(bad)", { XX } },
5520 { "(bad)", { XX } },
5521 { "(bad)", { XX } },
5522 { "(bad)", { XX } },
5523 { "(bad)", { XX } },
5525 { "(bad)", { XX } },
5526 { "(bad)", { XX } },
5527 { "(bad)", { XX } },
5528 { "(bad)", { XX } },
5529 { "(bad)", { XX } },
5530 { "(bad)", { XX } },
5531 { "(bad)", { XX } },
5532 { "(bad)", { XX } },
5534 { "(bad)", { XX } },
5535 { "(bad)", { XX } },
5536 { "(bad)", { XX } },
5537 { "(bad)", { XX } },
5538 { "(bad)", { XX } },
5539 { "(bad)", { XX } },
5540 { "(bad)", { XX } },
5541 { "(bad)", { XX } },
5543 { "(bad)", { XX } },
5544 { "(bad)", { XX } },
5545 { "(bad)", { XX } },
5546 { "(bad)", { XX } },
5547 { "(bad)", { XX } },
5548 { "(bad)", { XX } },
5549 { "(bad)", { XX } },
5550 { "(bad)", { XX } },
5552 { "(bad)", { XX } },
5553 { "(bad)", { XX } },
5554 { "(bad)", { XX } },
5555 { "(bad)", { XX } },
5556 { "(bad)", { XX } },
5557 { "(bad)", { XX } },
5558 { "(bad)", { XX } },
5559 { "(bad)", { XX } },
5561 { "(bad)", { XX } },
5562 { "(bad)", { XX } },
5563 { "(bad)", { XX } },
5564 { "(bad)", { XX } },
5565 { "(bad)", { XX } },
5566 { "(bad)", { XX } },
5567 { "(bad)", { XX } },
5568 { "(bad)", { XX } },
5570 { "(bad)", { XX } },
5571 { "(bad)", { XX } },
5572 { "(bad)", { XX } },
5573 { "(bad)", { XX } },
5574 { "(bad)", { XX } },
5575 { "(bad)", { XX } },
5576 { "(bad)", { XX } },
5577 { "(bad)", { XX } },
5579 { "(bad)", { XX } },
5580 { "(bad)", { XX } },
5581 { "(bad)", { XX } },
5582 { "(bad)", { XX } },
5583 { "(bad)", { XX } },
5584 { "(bad)", { XX } },
5585 { "(bad)", { XX } },
5586 { "(bad)", { XX } },
5588 { PREFIX_TABLE (PREFIX_0F3880) },
5589 { PREFIX_TABLE (PREFIX_0F3881) },
5590 { "(bad)", { XX } },
5591 { "(bad)", { XX } },
5592 { "(bad)", { XX } },
5593 { "(bad)", { XX } },
5594 { "(bad)", { XX } },
5595 { "(bad)", { XX } },
5597 { "(bad)", { XX } },
5598 { "(bad)", { XX } },
5599 { "(bad)", { XX } },
5600 { "(bad)", { XX } },
5601 { "(bad)", { XX } },
5602 { "(bad)", { XX } },
5603 { "(bad)", { XX } },
5604 { "(bad)", { XX } },
5606 { "(bad)", { XX } },
5607 { "(bad)", { XX } },
5608 { "(bad)", { XX } },
5609 { "(bad)", { XX } },
5610 { "(bad)", { XX } },
5611 { "(bad)", { XX } },
5612 { "(bad)", { XX } },
5613 { "(bad)", { XX } },
5615 { "(bad)", { XX } },
5616 { "(bad)", { XX } },
5617 { "(bad)", { XX } },
5618 { "(bad)", { XX } },
5619 { "(bad)", { XX } },
5620 { "(bad)", { XX } },
5621 { "(bad)", { XX } },
5622 { "(bad)", { XX } },
5624 { "(bad)", { XX } },
5625 { "(bad)", { XX } },
5626 { "(bad)", { XX } },
5627 { "(bad)", { XX } },
5628 { "(bad)", { XX } },
5629 { "(bad)", { XX } },
5630 { "(bad)", { XX } },
5631 { "(bad)", { XX } },
5633 { "(bad)", { XX } },
5634 { "(bad)", { XX } },
5635 { "(bad)", { XX } },
5636 { "(bad)", { XX } },
5637 { "(bad)", { XX } },
5638 { "(bad)", { XX } },
5639 { "(bad)", { XX } },
5640 { "(bad)", { XX } },
5642 { "(bad)", { XX } },
5643 { "(bad)", { XX } },
5644 { "(bad)", { XX } },
5645 { "(bad)", { XX } },
5646 { "(bad)", { XX } },
5647 { "(bad)", { XX } },
5648 { "(bad)", { XX } },
5649 { "(bad)", { XX } },
5651 { "(bad)", { XX } },
5652 { "(bad)", { XX } },
5653 { "(bad)", { XX } },
5654 { "(bad)", { XX } },
5655 { "(bad)", { XX } },
5656 { "(bad)", { XX } },
5657 { "(bad)", { XX } },
5658 { "(bad)", { XX } },
5660 { "(bad)", { XX } },
5661 { "(bad)", { XX } },
5662 { "(bad)", { XX } },
5663 { "(bad)", { XX } },
5664 { "(bad)", { XX } },
5665 { "(bad)", { XX } },
5666 { "(bad)", { XX } },
5667 { "(bad)", { XX } },
5669 { "(bad)", { XX } },
5670 { "(bad)", { XX } },
5671 { "(bad)", { XX } },
5672 { "(bad)", { XX } },
5673 { "(bad)", { XX } },
5674 { "(bad)", { XX } },
5675 { "(bad)", { XX } },
5676 { "(bad)", { XX } },
5678 { "(bad)", { XX } },
5679 { "(bad)", { XX } },
5680 { "(bad)", { XX } },
5681 { "(bad)", { XX } },
5682 { "(bad)", { XX } },
5683 { "(bad)", { XX } },
5684 { "(bad)", { XX } },
5685 { "(bad)", { XX } },
5687 { "(bad)", { XX } },
5688 { "(bad)", { XX } },
5689 { "(bad)", { XX } },
5690 { PREFIX_TABLE (PREFIX_0F38DB) },
5691 { PREFIX_TABLE (PREFIX_0F38DC) },
5692 { PREFIX_TABLE (PREFIX_0F38DD) },
5693 { PREFIX_TABLE (PREFIX_0F38DE) },
5694 { PREFIX_TABLE (PREFIX_0F38DF) },
5696 { "(bad)", { XX } },
5697 { "(bad)", { XX } },
5698 { "(bad)", { XX } },
5699 { "(bad)", { XX } },
5700 { "(bad)", { XX } },
5701 { "(bad)", { XX } },
5702 { "(bad)", { XX } },
5703 { "(bad)", { XX } },
5705 { "(bad)", { XX } },
5706 { "(bad)", { XX } },
5707 { "(bad)", { XX } },
5708 { "(bad)", { XX } },
5709 { "(bad)", { XX } },
5710 { "(bad)", { XX } },
5711 { "(bad)", { XX } },
5712 { "(bad)", { XX } },
5714 { PREFIX_TABLE (PREFIX_0F38F0) },
5715 { PREFIX_TABLE (PREFIX_0F38F1) },
5716 { "(bad)", { XX } },
5717 { "(bad)", { XX } },
5718 { "(bad)", { XX } },
5719 { "(bad)", { XX } },
5720 { "(bad)", { XX } },
5721 { "(bad)", { XX } },
5723 { "(bad)", { XX } },
5724 { "(bad)", { XX } },
5725 { "(bad)", { XX } },
5726 { "(bad)", { XX } },
5727 { "(bad)", { XX } },
5728 { "(bad)", { XX } },
5729 { "(bad)", { XX } },
5730 { "(bad)", { XX } },
5732 /* THREE_BYTE_0F3A */
5735 { "(bad)", { XX } },
5736 { "(bad)", { XX } },
5737 { "(bad)", { XX } },
5738 { "(bad)", { XX } },
5739 { "(bad)", { XX } },
5740 { "(bad)", { XX } },
5741 { "(bad)", { XX } },
5742 { "(bad)", { XX } },
5744 { PREFIX_TABLE (PREFIX_0F3A08) },
5745 { PREFIX_TABLE (PREFIX_0F3A09) },
5746 { PREFIX_TABLE (PREFIX_0F3A0A) },
5747 { PREFIX_TABLE (PREFIX_0F3A0B) },
5748 { PREFIX_TABLE (PREFIX_0F3A0C) },
5749 { PREFIX_TABLE (PREFIX_0F3A0D) },
5750 { PREFIX_TABLE (PREFIX_0F3A0E) },
5751 { "palignr", { MX, EM, Ib } },
5753 { "(bad)", { XX } },
5754 { "(bad)", { XX } },
5755 { "(bad)", { XX } },
5756 { "(bad)", { XX } },
5757 { PREFIX_TABLE (PREFIX_0F3A14) },
5758 { PREFIX_TABLE (PREFIX_0F3A15) },
5759 { PREFIX_TABLE (PREFIX_0F3A16) },
5760 { PREFIX_TABLE (PREFIX_0F3A17) },
5762 { "(bad)", { XX } },
5763 { "(bad)", { XX } },
5764 { "(bad)", { XX } },
5765 { "(bad)", { XX } },
5766 { "(bad)", { XX } },
5767 { "(bad)", { XX } },
5768 { "(bad)", { XX } },
5769 { "(bad)", { XX } },
5771 { PREFIX_TABLE (PREFIX_0F3A20) },
5772 { PREFIX_TABLE (PREFIX_0F3A21) },
5773 { PREFIX_TABLE (PREFIX_0F3A22) },
5774 { "(bad)", { XX } },
5775 { "(bad)", { XX } },
5776 { "(bad)", { XX } },
5777 { "(bad)", { XX } },
5778 { "(bad)", { XX } },
5780 { "(bad)", { XX } },
5781 { "(bad)", { XX } },
5782 { "(bad)", { XX } },
5783 { "(bad)", { XX } },
5784 { "(bad)", { XX } },
5785 { "(bad)", { XX } },
5786 { "(bad)", { XX } },
5787 { "(bad)", { XX } },
5789 { "(bad)", { XX } },
5790 { "(bad)", { XX } },
5791 { "(bad)", { XX } },
5792 { "(bad)", { XX } },
5793 { "(bad)", { XX } },
5794 { "(bad)", { XX } },
5795 { "(bad)", { XX } },
5796 { "(bad)", { XX } },
5798 { "(bad)", { XX } },
5799 { "(bad)", { XX } },
5800 { "(bad)", { XX } },
5801 { "(bad)", { XX } },
5802 { "(bad)", { XX } },
5803 { "(bad)", { XX } },
5804 { "(bad)", { XX } },
5805 { "(bad)", { XX } },
5807 { PREFIX_TABLE (PREFIX_0F3A40) },
5808 { PREFIX_TABLE (PREFIX_0F3A41) },
5809 { PREFIX_TABLE (PREFIX_0F3A42) },
5810 { "(bad)", { XX } },
5811 { PREFIX_TABLE (PREFIX_0F3A44) },
5812 { "(bad)", { XX } },
5813 { "(bad)", { XX } },
5814 { "(bad)", { XX } },
5816 { "(bad)", { XX } },
5817 { "(bad)", { XX } },
5818 { "(bad)", { XX } },
5819 { "(bad)", { XX } },
5820 { "(bad)", { XX } },
5821 { "(bad)", { XX } },
5822 { "(bad)", { XX } },
5823 { "(bad)", { XX } },
5825 { "(bad)", { XX } },
5826 { "(bad)", { XX } },
5827 { "(bad)", { XX } },
5828 { "(bad)", { XX } },
5829 { "(bad)", { XX } },
5830 { "(bad)", { XX } },
5831 { "(bad)", { XX } },
5832 { "(bad)", { XX } },
5834 { "(bad)", { XX } },
5835 { "(bad)", { XX } },
5836 { "(bad)", { XX } },
5837 { "(bad)", { XX } },
5838 { "(bad)", { XX } },
5839 { "(bad)", { XX } },
5840 { "(bad)", { XX } },
5841 { "(bad)", { XX } },
5843 { PREFIX_TABLE (PREFIX_0F3A60) },
5844 { PREFIX_TABLE (PREFIX_0F3A61) },
5845 { PREFIX_TABLE (PREFIX_0F3A62) },
5846 { PREFIX_TABLE (PREFIX_0F3A63) },
5847 { "(bad)", { XX } },
5848 { "(bad)", { XX } },
5849 { "(bad)", { XX } },
5850 { "(bad)", { XX } },
5852 { "(bad)", { XX } },
5853 { "(bad)", { XX } },
5854 { "(bad)", { XX } },
5855 { "(bad)", { XX } },
5856 { "(bad)", { XX } },
5857 { "(bad)", { XX } },
5858 { "(bad)", { XX } },
5859 { "(bad)", { XX } },
5861 { "(bad)", { XX } },
5862 { "(bad)", { XX } },
5863 { "(bad)", { XX } },
5864 { "(bad)", { XX } },
5865 { "(bad)", { XX } },
5866 { "(bad)", { XX } },
5867 { "(bad)", { XX } },
5868 { "(bad)", { XX } },
5870 { "(bad)", { XX } },
5871 { "(bad)", { XX } },
5872 { "(bad)", { XX } },
5873 { "(bad)", { XX } },
5874 { "(bad)", { XX } },
5875 { "(bad)", { XX } },
5876 { "(bad)", { XX } },
5877 { "(bad)", { XX } },
5879 { "(bad)", { XX } },
5880 { "(bad)", { XX } },
5881 { "(bad)", { XX } },
5882 { "(bad)", { XX } },
5883 { "(bad)", { XX } },
5884 { "(bad)", { XX } },
5885 { "(bad)", { XX } },
5886 { "(bad)", { XX } },
5888 { "(bad)", { XX } },
5889 { "(bad)", { XX } },
5890 { "(bad)", { XX } },
5891 { "(bad)", { XX } },
5892 { "(bad)", { XX } },
5893 { "(bad)", { XX } },
5894 { "(bad)", { XX } },
5895 { "(bad)", { XX } },
5897 { "(bad)", { XX } },
5898 { "(bad)", { XX } },
5899 { "(bad)", { XX } },
5900 { "(bad)", { XX } },
5901 { "(bad)", { XX } },
5902 { "(bad)", { XX } },
5903 { "(bad)", { XX } },
5904 { "(bad)", { XX } },
5906 { "(bad)", { XX } },
5907 { "(bad)", { XX } },
5908 { "(bad)", { XX } },
5909 { "(bad)", { XX } },
5910 { "(bad)", { XX } },
5911 { "(bad)", { XX } },
5912 { "(bad)", { XX } },
5913 { "(bad)", { XX } },
5915 { "(bad)", { XX } },
5916 { "(bad)", { XX } },
5917 { "(bad)", { XX } },
5918 { "(bad)", { XX } },
5919 { "(bad)", { XX } },
5920 { "(bad)", { XX } },
5921 { "(bad)", { XX } },
5922 { "(bad)", { XX } },
5924 { "(bad)", { XX } },
5925 { "(bad)", { XX } },
5926 { "(bad)", { XX } },
5927 { "(bad)", { XX } },
5928 { "(bad)", { XX } },
5929 { "(bad)", { XX } },
5930 { "(bad)", { XX } },
5931 { "(bad)", { XX } },
5933 { "(bad)", { XX } },
5934 { "(bad)", { XX } },
5935 { "(bad)", { XX } },
5936 { "(bad)", { XX } },
5937 { "(bad)", { XX } },
5938 { "(bad)", { XX } },
5939 { "(bad)", { XX } },
5940 { "(bad)", { XX } },
5942 { "(bad)", { XX } },
5943 { "(bad)", { XX } },
5944 { "(bad)", { XX } },
5945 { "(bad)", { XX } },
5946 { "(bad)", { XX } },
5947 { "(bad)", { XX } },
5948 { "(bad)", { XX } },
5949 { "(bad)", { XX } },
5951 { "(bad)", { XX } },
5952 { "(bad)", { XX } },
5953 { "(bad)", { XX } },
5954 { "(bad)", { XX } },
5955 { "(bad)", { XX } },
5956 { "(bad)", { XX } },
5957 { "(bad)", { XX } },
5958 { "(bad)", { XX } },
5960 { "(bad)", { XX } },
5961 { "(bad)", { XX } },
5962 { "(bad)", { XX } },
5963 { "(bad)", { XX } },
5964 { "(bad)", { XX } },
5965 { "(bad)", { XX } },
5966 { "(bad)", { XX } },
5967 { "(bad)", { XX } },
5969 { "(bad)", { XX } },
5970 { "(bad)", { XX } },
5971 { "(bad)", { XX } },
5972 { "(bad)", { XX } },
5973 { "(bad)", { XX } },
5974 { "(bad)", { XX } },
5975 { "(bad)", { XX } },
5976 { "(bad)", { XX } },
5978 { "(bad)", { XX } },
5979 { "(bad)", { XX } },
5980 { "(bad)", { XX } },
5981 { "(bad)", { XX } },
5982 { "(bad)", { XX } },
5983 { "(bad)", { XX } },
5984 { "(bad)", { XX } },
5985 { PREFIX_TABLE (PREFIX_0F3ADF) },
5987 { "(bad)", { XX } },
5988 { "(bad)", { XX } },
5989 { "(bad)", { XX } },
5990 { "(bad)", { XX } },
5991 { "(bad)", { XX } },
5992 { "(bad)", { XX } },
5993 { "(bad)", { XX } },
5994 { "(bad)", { XX } },
5996 { "(bad)", { XX } },
5997 { "(bad)", { XX } },
5998 { "(bad)", { XX } },
5999 { "(bad)", { XX } },
6000 { "(bad)", { XX } },
6001 { "(bad)", { XX } },
6002 { "(bad)", { XX } },
6003 { "(bad)", { XX } },
6005 { "(bad)", { XX } },
6006 { "(bad)", { XX } },
6007 { "(bad)", { XX } },
6008 { "(bad)", { XX } },
6009 { "(bad)", { XX } },
6010 { "(bad)", { XX } },
6011 { "(bad)", { XX } },
6012 { "(bad)", { XX } },
6014 { "(bad)", { XX } },
6015 { "(bad)", { XX } },
6016 { "(bad)", { XX } },
6017 { "(bad)", { XX } },
6018 { "(bad)", { XX } },
6019 { "(bad)", { XX } },
6020 { "(bad)", { XX } },
6021 { "(bad)", { XX } },
6024 /* THREE_BYTE_0F7A */
6027 { "(bad)", { XX } },
6028 { "(bad)", { XX } },
6029 { "(bad)", { XX } },
6030 { "(bad)", { XX } },
6031 { "(bad)", { XX } },
6032 { "(bad)", { XX } },
6033 { "(bad)", { XX } },
6034 { "(bad)", { XX } },
6036 { "(bad)", { XX } },
6037 { "(bad)", { XX } },
6038 { "(bad)", { XX } },
6039 { "(bad)", { XX } },
6040 { "(bad)", { XX } },
6041 { "(bad)", { XX } },
6042 { "(bad)", { XX } },
6043 { "(bad)", { XX } },
6045 { "(bad)", { XX } },
6046 { "(bad)", { XX } },
6047 { "(bad)", { XX } },
6048 { "(bad)", { XX } },
6049 { "(bad)", { XX } },
6050 { "(bad)", { XX } },
6051 { "(bad)", { XX } },
6052 { "(bad)", { XX } },
6054 { "(bad)", { XX } },
6055 { "(bad)", { XX } },
6056 { "(bad)", { XX } },
6057 { "(bad)", { XX } },
6058 { "(bad)", { XX } },
6059 { "(bad)", { XX } },
6060 { "(bad)", { XX } },
6061 { "(bad)", { XX } },
6063 { "ptest", { XX } },
6064 { "(bad)", { XX } },
6065 { "(bad)", { XX } },
6066 { "(bad)", { XX } },
6067 { "(bad)", { XX } },
6068 { "(bad)", { XX } },
6069 { "(bad)", { XX } },
6070 { "(bad)", { XX } },
6072 { "(bad)", { XX } },
6073 { "(bad)", { XX } },
6074 { "(bad)", { XX } },
6075 { "(bad)", { XX } },
6076 { "(bad)", { XX } },
6077 { "(bad)", { XX } },
6078 { "(bad)", { XX } },
6079 { "(bad)", { XX } },
6081 { "(bad)", { XX } },
6082 { "(bad)", { XX } },
6083 { "(bad)", { XX } },
6084 { "(bad)", { XX } },
6085 { "(bad)", { XX } },
6086 { "(bad)", { XX } },
6087 { "(bad)", { XX } },
6088 { "(bad)", { XX } },
6090 { "(bad)", { XX } },
6091 { "(bad)", { XX } },
6092 { "(bad)", { XX } },
6093 { "(bad)", { XX } },
6094 { "(bad)", { XX } },
6095 { "(bad)", { XX } },
6096 { "(bad)", { XX } },
6097 { "(bad)", { XX } },
6099 { "(bad)", { XX } },
6100 { "phaddbw", { XM, EXq } },
6101 { "phaddbd", { XM, EXq } },
6102 { "phaddbq", { XM, EXq } },
6103 { "(bad)", { XX } },
6104 { "(bad)", { XX } },
6105 { "phaddwd", { XM, EXq } },
6106 { "phaddwq", { XM, EXq } },
6108 { "(bad)", { XX } },
6109 { "(bad)", { XX } },
6110 { "(bad)", { XX } },
6111 { "phadddq", { XM, EXq } },
6112 { "(bad)", { XX } },
6113 { "(bad)", { XX } },
6114 { "(bad)", { XX } },
6115 { "(bad)", { XX } },
6117 { "(bad)", { XX } },
6118 { "phaddubw", { XM, EXq } },
6119 { "phaddubd", { XM, EXq } },
6120 { "phaddubq", { XM, EXq } },
6121 { "(bad)", { XX } },
6122 { "(bad)", { XX } },
6123 { "phadduwd", { XM, EXq } },
6124 { "phadduwq", { XM, EXq } },
6126 { "(bad)", { XX } },
6127 { "(bad)", { XX } },
6128 { "(bad)", { XX } },
6129 { "phaddudq", { XM, EXq } },
6130 { "(bad)", { XX } },
6131 { "(bad)", { XX } },
6132 { "(bad)", { XX } },
6133 { "(bad)", { XX } },
6135 { "(bad)", { XX } },
6136 { "phsubbw", { XM, EXq } },
6137 { "phsubbd", { XM, EXq } },
6138 { "phsubbq", { XM, EXq } },
6139 { "(bad)", { XX } },
6140 { "(bad)", { XX } },
6141 { "(bad)", { XX } },
6142 { "(bad)", { XX } },
6144 { "(bad)", { XX } },
6145 { "(bad)", { XX } },
6146 { "(bad)", { XX } },
6147 { "(bad)", { XX } },
6148 { "(bad)", { XX } },
6149 { "(bad)", { XX } },
6150 { "(bad)", { XX } },
6151 { "(bad)", { XX } },
6153 { "(bad)", { XX } },
6154 { "(bad)", { XX } },
6155 { "(bad)", { XX } },
6156 { "(bad)", { XX } },
6157 { "(bad)", { XX } },
6158 { "(bad)", { XX } },
6159 { "(bad)", { XX } },
6160 { "(bad)", { XX } },
6162 { "(bad)", { XX } },
6163 { "(bad)", { XX } },
6164 { "(bad)", { XX } },
6165 { "(bad)", { XX } },
6166 { "(bad)", { XX } },
6167 { "(bad)", { XX } },
6168 { "(bad)", { XX } },
6169 { "(bad)", { XX } },
6171 { "(bad)", { XX } },
6172 { "(bad)", { XX } },
6173 { "(bad)", { XX } },
6174 { "(bad)", { XX } },
6175 { "(bad)", { XX } },
6176 { "(bad)", { XX } },
6177 { "(bad)", { XX } },
6178 { "(bad)", { XX } },
6180 { "(bad)", { XX } },
6181 { "(bad)", { XX } },
6182 { "(bad)", { XX } },
6183 { "(bad)", { XX } },
6184 { "(bad)", { XX } },
6185 { "(bad)", { XX } },
6186 { "(bad)", { XX } },
6187 { "(bad)", { XX } },
6189 { "(bad)", { XX } },
6190 { "(bad)", { XX } },
6191 { "(bad)", { XX } },
6192 { "(bad)", { XX } },
6193 { "(bad)", { XX } },
6194 { "(bad)", { XX } },
6195 { "(bad)", { XX } },
6196 { "(bad)", { XX } },
6198 { "(bad)", { XX } },
6199 { "(bad)", { XX } },
6200 { "(bad)", { XX } },
6201 { "(bad)", { XX } },
6202 { "(bad)", { XX } },
6203 { "(bad)", { XX } },
6204 { "(bad)", { XX } },
6205 { "(bad)", { XX } },
6207 { "(bad)", { XX } },
6208 { "(bad)", { XX } },
6209 { "(bad)", { XX } },
6210 { "(bad)", { XX } },
6211 { "(bad)", { XX } },
6212 { "(bad)", { XX } },
6213 { "(bad)", { XX } },
6214 { "(bad)", { XX } },
6216 { "(bad)", { XX } },
6217 { "(bad)", { XX } },
6218 { "(bad)", { XX } },
6219 { "(bad)", { XX } },
6220 { "(bad)", { XX } },
6221 { "(bad)", { XX } },
6222 { "(bad)", { XX } },
6223 { "(bad)", { XX } },
6225 { "(bad)", { XX } },
6226 { "(bad)", { XX } },
6227 { "(bad)", { XX } },
6228 { "(bad)", { XX } },
6229 { "(bad)", { XX } },
6230 { "(bad)", { XX } },
6231 { "(bad)", { XX } },
6232 { "(bad)", { XX } },
6234 { "(bad)", { XX } },
6235 { "(bad)", { XX } },
6236 { "(bad)", { XX } },
6237 { "(bad)", { XX } },
6238 { "(bad)", { XX } },
6239 { "(bad)", { XX } },
6240 { "(bad)", { XX } },
6241 { "(bad)", { XX } },
6243 { "(bad)", { XX } },
6244 { "(bad)", { XX } },
6245 { "(bad)", { XX } },
6246 { "(bad)", { XX } },
6247 { "(bad)", { XX } },
6248 { "(bad)", { XX } },
6249 { "(bad)", { XX } },
6250 { "(bad)", { XX } },
6252 { "(bad)", { XX } },
6253 { "(bad)", { XX } },
6254 { "(bad)", { XX } },
6255 { "(bad)", { XX } },
6256 { "(bad)", { XX } },
6257 { "(bad)", { XX } },
6258 { "(bad)", { XX } },
6259 { "(bad)", { XX } },
6261 { "(bad)", { XX } },
6262 { "(bad)", { XX } },
6263 { "(bad)", { XX } },
6264 { "(bad)", { XX } },
6265 { "(bad)", { XX } },
6266 { "(bad)", { XX } },
6267 { "(bad)", { XX } },
6268 { "(bad)", { XX } },
6270 { "(bad)", { XX } },
6271 { "(bad)", { XX } },
6272 { "(bad)", { XX } },
6273 { "(bad)", { XX } },
6274 { "(bad)", { XX } },
6275 { "(bad)", { XX } },
6276 { "(bad)", { XX } },
6277 { "(bad)", { XX } },
6279 { "(bad)", { XX } },
6280 { "(bad)", { XX } },
6281 { "(bad)", { XX } },
6282 { "(bad)", { XX } },
6283 { "(bad)", { XX } },
6284 { "(bad)", { XX } },
6285 { "(bad)", { XX } },
6286 { "(bad)", { XX } },
6288 { "(bad)", { XX } },
6289 { "(bad)", { XX } },
6290 { "(bad)", { XX } },
6291 { "(bad)", { XX } },
6292 { "(bad)", { XX } },
6293 { "(bad)", { XX } },
6294 { "(bad)", { XX } },
6295 { "(bad)", { XX } },
6297 { "(bad)", { XX } },
6298 { "(bad)", { XX } },
6299 { "(bad)", { XX } },
6300 { "(bad)", { XX } },
6301 { "(bad)", { XX } },
6302 { "(bad)", { XX } },
6303 { "(bad)", { XX } },
6304 { "(bad)", { XX } },
6306 { "(bad)", { XX } },
6307 { "(bad)", { XX } },
6308 { "(bad)", { XX } },
6309 { "(bad)", { XX } },
6310 { "(bad)", { XX } },
6311 { "(bad)", { XX } },
6312 { "(bad)", { XX } },
6313 { "(bad)", { XX } },
6318 static const struct dis386 vex_table[][256] = {
6322 { "(bad)", { XX } },
6323 { "(bad)", { XX } },
6324 { "(bad)", { XX } },
6325 { "(bad)", { XX } },
6326 { "(bad)", { XX } },
6327 { "(bad)", { XX } },
6328 { "(bad)", { XX } },
6329 { "(bad)", { XX } },
6331 { "(bad)", { XX } },
6332 { "(bad)", { XX } },
6333 { "(bad)", { XX } },
6334 { "(bad)", { XX } },
6335 { "(bad)", { XX } },
6336 { "(bad)", { XX } },
6337 { "(bad)", { XX } },
6338 { "(bad)", { XX } },
6340 { PREFIX_TABLE (PREFIX_VEX_10) },
6341 { PREFIX_TABLE (PREFIX_VEX_11) },
6342 { PREFIX_TABLE (PREFIX_VEX_12) },
6343 { MOD_TABLE (MOD_VEX_13) },
6344 { "vunpcklpX", { XM, Vex, EXx } },
6345 { "vunpckhpX", { XM, Vex, EXx } },
6346 { PREFIX_TABLE (PREFIX_VEX_16) },
6347 { MOD_TABLE (MOD_VEX_17) },
6349 { "(bad)", { XX } },
6350 { "(bad)", { XX } },
6351 { "(bad)", { XX } },
6352 { "(bad)", { XX } },
6353 { "(bad)", { XX } },
6354 { "(bad)", { XX } },
6355 { "(bad)", { XX } },
6356 { "(bad)", { XX } },
6358 { "(bad)", { XX } },
6359 { "(bad)", { XX } },
6360 { "(bad)", { XX } },
6361 { "(bad)", { XX } },
6362 { "(bad)", { XX } },
6363 { "(bad)", { XX } },
6364 { "(bad)", { XX } },
6365 { "(bad)", { XX } },
6367 { "vmovapX", { XM, EXx } },
6368 { "vmovapX", { EXxS, XM } },
6369 { PREFIX_TABLE (PREFIX_VEX_2A) },
6370 { MOD_TABLE (MOD_VEX_2B) },
6371 { PREFIX_TABLE (PREFIX_VEX_2C) },
6372 { PREFIX_TABLE (PREFIX_VEX_2D) },
6373 { PREFIX_TABLE (PREFIX_VEX_2E) },
6374 { PREFIX_TABLE (PREFIX_VEX_2F) },
6376 { "(bad)", { XX } },
6377 { "(bad)", { XX } },
6378 { "(bad)", { XX } },
6379 { "(bad)", { XX } },
6380 { "(bad)", { XX } },
6381 { "(bad)", { XX } },
6382 { "(bad)", { XX } },
6383 { "(bad)", { XX } },
6385 { "(bad)", { XX } },
6386 { "(bad)", { XX } },
6387 { "(bad)", { XX } },
6388 { "(bad)", { XX } },
6389 { "(bad)", { XX } },
6390 { "(bad)", { XX } },
6391 { "(bad)", { XX } },
6392 { "(bad)", { XX } },
6394 { "(bad)", { XX } },
6395 { "(bad)", { XX } },
6396 { "(bad)", { XX } },
6397 { "(bad)", { XX } },
6398 { "(bad)", { XX } },
6399 { "(bad)", { XX } },
6400 { "(bad)", { XX } },
6401 { "(bad)", { XX } },
6403 { "(bad)", { XX } },
6404 { "(bad)", { XX } },
6405 { "(bad)", { XX } },
6406 { "(bad)", { XX } },
6407 { "(bad)", { XX } },
6408 { "(bad)", { XX } },
6409 { "(bad)", { XX } },
6410 { "(bad)", { XX } },
6412 { MOD_TABLE (MOD_VEX_51) },
6413 { PREFIX_TABLE (PREFIX_VEX_51) },
6414 { PREFIX_TABLE (PREFIX_VEX_52) },
6415 { PREFIX_TABLE (PREFIX_VEX_53) },
6416 { "vandpX", { XM, Vex, EXx } },
6417 { "vandnpX", { XM, Vex, EXx } },
6418 { "vorpX", { XM, Vex, EXx } },
6419 { "vxorpX", { XM, Vex, EXx } },
6421 { PREFIX_TABLE (PREFIX_VEX_58) },
6422 { PREFIX_TABLE (PREFIX_VEX_59) },
6423 { PREFIX_TABLE (PREFIX_VEX_5A) },
6424 { PREFIX_TABLE (PREFIX_VEX_5B) },
6425 { PREFIX_TABLE (PREFIX_VEX_5C) },
6426 { PREFIX_TABLE (PREFIX_VEX_5D) },
6427 { PREFIX_TABLE (PREFIX_VEX_5E) },
6428 { PREFIX_TABLE (PREFIX_VEX_5F) },
6430 { PREFIX_TABLE (PREFIX_VEX_60) },
6431 { PREFIX_TABLE (PREFIX_VEX_61) },
6432 { PREFIX_TABLE (PREFIX_VEX_62) },
6433 { PREFIX_TABLE (PREFIX_VEX_63) },
6434 { PREFIX_TABLE (PREFIX_VEX_64) },
6435 { PREFIX_TABLE (PREFIX_VEX_65) },
6436 { PREFIX_TABLE (PREFIX_VEX_66) },
6437 { PREFIX_TABLE (PREFIX_VEX_67) },
6439 { PREFIX_TABLE (PREFIX_VEX_68) },
6440 { PREFIX_TABLE (PREFIX_VEX_69) },
6441 { PREFIX_TABLE (PREFIX_VEX_6A) },
6442 { PREFIX_TABLE (PREFIX_VEX_6B) },
6443 { PREFIX_TABLE (PREFIX_VEX_6C) },
6444 { PREFIX_TABLE (PREFIX_VEX_6D) },
6445 { PREFIX_TABLE (PREFIX_VEX_6E) },
6446 { PREFIX_TABLE (PREFIX_VEX_6F) },
6448 { PREFIX_TABLE (PREFIX_VEX_70) },
6449 { REG_TABLE (REG_VEX_71) },
6450 { REG_TABLE (REG_VEX_72) },
6451 { REG_TABLE (REG_VEX_73) },
6452 { PREFIX_TABLE (PREFIX_VEX_74) },
6453 { PREFIX_TABLE (PREFIX_VEX_75) },
6454 { PREFIX_TABLE (PREFIX_VEX_76) },
6455 { PREFIX_TABLE (PREFIX_VEX_77) },
6457 { "(bad)", { XX } },
6458 { "(bad)", { XX } },
6459 { "(bad)", { XX } },
6460 { "(bad)", { XX } },
6461 { PREFIX_TABLE (PREFIX_VEX_7C) },
6462 { PREFIX_TABLE (PREFIX_VEX_7D) },
6463 { PREFIX_TABLE (PREFIX_VEX_7E) },
6464 { PREFIX_TABLE (PREFIX_VEX_7F) },
6466 { "(bad)", { XX } },
6467 { "(bad)", { XX } },
6468 { "(bad)", { XX } },
6469 { "(bad)", { XX } },
6470 { "(bad)", { XX } },
6471 { "(bad)", { XX } },
6472 { "(bad)", { XX } },
6473 { "(bad)", { XX } },
6475 { "(bad)", { XX } },
6476 { "(bad)", { XX } },
6477 { "(bad)", { XX } },
6478 { "(bad)", { XX } },
6479 { "(bad)", { XX } },
6480 { "(bad)", { XX } },
6481 { "(bad)", { XX } },
6482 { "(bad)", { XX } },
6484 { "(bad)", { XX } },
6485 { "(bad)", { XX } },
6486 { "(bad)", { XX } },
6487 { "(bad)", { XX } },
6488 { "(bad)", { XX } },
6489 { "(bad)", { XX } },
6490 { "(bad)", { XX } },
6491 { "(bad)", { XX } },
6493 { "(bad)", { XX } },
6494 { "(bad)", { XX } },
6495 { "(bad)", { XX } },
6496 { "(bad)", { XX } },
6497 { "(bad)", { XX } },
6498 { "(bad)", { XX } },
6499 { "(bad)", { XX } },
6500 { "(bad)", { XX } },
6502 { "(bad)", { XX } },
6503 { "(bad)", { XX } },
6504 { "(bad)", { XX } },
6505 { "(bad)", { XX } },
6506 { "(bad)", { XX } },
6507 { "(bad)", { XX } },
6508 { "(bad)", { XX } },
6509 { "(bad)", { XX } },
6511 { "(bad)", { XX } },
6512 { "(bad)", { XX } },
6513 { "(bad)", { XX } },
6514 { "(bad)", { XX } },
6515 { "(bad)", { XX } },
6516 { "(bad)", { XX } },
6517 { REG_TABLE (REG_VEX_AE) },
6518 { "(bad)", { XX } },
6520 { "(bad)", { XX } },
6521 { "(bad)", { XX } },
6522 { "(bad)", { XX } },
6523 { "(bad)", { XX } },
6524 { "(bad)", { XX } },
6525 { "(bad)", { XX } },
6526 { "(bad)", { XX } },
6527 { "(bad)", { XX } },
6529 { "(bad)", { XX } },
6530 { "(bad)", { XX } },
6531 { "(bad)", { XX } },
6532 { "(bad)", { XX } },
6533 { "(bad)", { XX } },
6534 { "(bad)", { XX } },
6535 { "(bad)", { XX } },
6536 { "(bad)", { XX } },
6538 { "(bad)", { XX } },
6539 { "(bad)", { XX } },
6540 { PREFIX_TABLE (PREFIX_VEX_C2) },
6541 { "(bad)", { XX } },
6542 { PREFIX_TABLE (PREFIX_VEX_C4) },
6543 { PREFIX_TABLE (PREFIX_VEX_C5) },
6544 { "vshufpX", { XM, Vex, EXx, Ib } },
6545 { "(bad)", { XX } },
6547 { "(bad)", { XX } },
6548 { "(bad)", { XX } },
6549 { "(bad)", { XX } },
6550 { "(bad)", { XX } },
6551 { "(bad)", { XX } },
6552 { "(bad)", { XX } },
6553 { "(bad)", { XX } },
6554 { "(bad)", { XX } },
6556 { PREFIX_TABLE (PREFIX_VEX_D0) },
6557 { PREFIX_TABLE (PREFIX_VEX_D1) },
6558 { PREFIX_TABLE (PREFIX_VEX_D2) },
6559 { PREFIX_TABLE (PREFIX_VEX_D3) },
6560 { PREFIX_TABLE (PREFIX_VEX_D4) },
6561 { PREFIX_TABLE (PREFIX_VEX_D5) },
6562 { PREFIX_TABLE (PREFIX_VEX_D6) },
6563 { PREFIX_TABLE (PREFIX_VEX_D7) },
6565 { PREFIX_TABLE (PREFIX_VEX_D8) },
6566 { PREFIX_TABLE (PREFIX_VEX_D9) },
6567 { PREFIX_TABLE (PREFIX_VEX_DA) },
6568 { PREFIX_TABLE (PREFIX_VEX_DB) },
6569 { PREFIX_TABLE (PREFIX_VEX_DC) },
6570 { PREFIX_TABLE (PREFIX_VEX_DD) },
6571 { PREFIX_TABLE (PREFIX_VEX_DE) },
6572 { PREFIX_TABLE (PREFIX_VEX_DF) },
6574 { PREFIX_TABLE (PREFIX_VEX_E0) },
6575 { PREFIX_TABLE (PREFIX_VEX_E1) },
6576 { PREFIX_TABLE (PREFIX_VEX_E2) },
6577 { PREFIX_TABLE (PREFIX_VEX_E3) },
6578 { PREFIX_TABLE (PREFIX_VEX_E4) },
6579 { PREFIX_TABLE (PREFIX_VEX_E5) },
6580 { PREFIX_TABLE (PREFIX_VEX_E6) },
6581 { PREFIX_TABLE (PREFIX_VEX_E7) },
6583 { PREFIX_TABLE (PREFIX_VEX_E8) },
6584 { PREFIX_TABLE (PREFIX_VEX_E9) },
6585 { PREFIX_TABLE (PREFIX_VEX_EA) },
6586 { PREFIX_TABLE (PREFIX_VEX_EB) },
6587 { PREFIX_TABLE (PREFIX_VEX_EC) },
6588 { PREFIX_TABLE (PREFIX_VEX_ED) },
6589 { PREFIX_TABLE (PREFIX_VEX_EE) },
6590 { PREFIX_TABLE (PREFIX_VEX_EF) },
6592 { PREFIX_TABLE (PREFIX_VEX_F0) },
6593 { PREFIX_TABLE (PREFIX_VEX_F1) },
6594 { PREFIX_TABLE (PREFIX_VEX_F2) },
6595 { PREFIX_TABLE (PREFIX_VEX_F3) },
6596 { PREFIX_TABLE (PREFIX_VEX_F4) },
6597 { PREFIX_TABLE (PREFIX_VEX_F5) },
6598 { PREFIX_TABLE (PREFIX_VEX_F6) },
6599 { PREFIX_TABLE (PREFIX_VEX_F7) },
6601 { PREFIX_TABLE (PREFIX_VEX_F8) },
6602 { PREFIX_TABLE (PREFIX_VEX_F9) },
6603 { PREFIX_TABLE (PREFIX_VEX_FA) },
6604 { PREFIX_TABLE (PREFIX_VEX_FB) },
6605 { PREFIX_TABLE (PREFIX_VEX_FC) },
6606 { PREFIX_TABLE (PREFIX_VEX_FD) },
6607 { PREFIX_TABLE (PREFIX_VEX_FE) },
6608 { "(bad)", { XX } },
6613 { PREFIX_TABLE (PREFIX_VEX_3800) },
6614 { PREFIX_TABLE (PREFIX_VEX_3801) },
6615 { PREFIX_TABLE (PREFIX_VEX_3802) },
6616 { PREFIX_TABLE (PREFIX_VEX_3803) },
6617 { PREFIX_TABLE (PREFIX_VEX_3804) },
6618 { PREFIX_TABLE (PREFIX_VEX_3805) },
6619 { PREFIX_TABLE (PREFIX_VEX_3806) },
6620 { PREFIX_TABLE (PREFIX_VEX_3807) },
6622 { PREFIX_TABLE (PREFIX_VEX_3808) },
6623 { PREFIX_TABLE (PREFIX_VEX_3809) },
6624 { PREFIX_TABLE (PREFIX_VEX_380A) },
6625 { PREFIX_TABLE (PREFIX_VEX_380B) },
6626 { PREFIX_TABLE (PREFIX_VEX_380C) },
6627 { PREFIX_TABLE (PREFIX_VEX_380D) },
6628 { PREFIX_TABLE (PREFIX_VEX_380E) },
6629 { PREFIX_TABLE (PREFIX_VEX_380F) },
6631 { "(bad)", { XX } },
6632 { "(bad)", { XX } },
6633 { "(bad)", { XX } },
6634 { "(bad)", { XX } },
6635 { "(bad)", { XX } },
6636 { "(bad)", { XX } },
6637 { "(bad)", { XX } },
6638 { PREFIX_TABLE (PREFIX_VEX_3817) },
6640 { PREFIX_TABLE (PREFIX_VEX_3818) },
6641 { PREFIX_TABLE (PREFIX_VEX_3819) },
6642 { PREFIX_TABLE (PREFIX_VEX_381A) },
6643 { "(bad)", { XX } },
6644 { PREFIX_TABLE (PREFIX_VEX_381C) },
6645 { PREFIX_TABLE (PREFIX_VEX_381D) },
6646 { PREFIX_TABLE (PREFIX_VEX_381E) },
6647 { "(bad)", { XX } },
6649 { PREFIX_TABLE (PREFIX_VEX_3820) },
6650 { PREFIX_TABLE (PREFIX_VEX_3821) },
6651 { PREFIX_TABLE (PREFIX_VEX_3822) },
6652 { PREFIX_TABLE (PREFIX_VEX_3823) },
6653 { PREFIX_TABLE (PREFIX_VEX_3824) },
6654 { PREFIX_TABLE (PREFIX_VEX_3825) },
6655 { "(bad)", { XX } },
6656 { "(bad)", { XX } },
6658 { PREFIX_TABLE (PREFIX_VEX_3828) },
6659 { PREFIX_TABLE (PREFIX_VEX_3829) },
6660 { PREFIX_TABLE (PREFIX_VEX_382A) },
6661 { PREFIX_TABLE (PREFIX_VEX_382B) },
6662 { PREFIX_TABLE (PREFIX_VEX_382C) },
6663 { PREFIX_TABLE (PREFIX_VEX_382D) },
6664 { PREFIX_TABLE (PREFIX_VEX_382E) },
6665 { PREFIX_TABLE (PREFIX_VEX_382F) },
6667 { PREFIX_TABLE (PREFIX_VEX_3830) },
6668 { PREFIX_TABLE (PREFIX_VEX_3831) },
6669 { PREFIX_TABLE (PREFIX_VEX_3832) },
6670 { PREFIX_TABLE (PREFIX_VEX_3833) },
6671 { PREFIX_TABLE (PREFIX_VEX_3834) },
6672 { PREFIX_TABLE (PREFIX_VEX_3835) },
6673 { "(bad)", { XX } },
6674 { PREFIX_TABLE (PREFIX_VEX_3837) },
6676 { PREFIX_TABLE (PREFIX_VEX_3838) },
6677 { PREFIX_TABLE (PREFIX_VEX_3839) },
6678 { PREFIX_TABLE (PREFIX_VEX_383A) },
6679 { PREFIX_TABLE (PREFIX_VEX_383B) },
6680 { PREFIX_TABLE (PREFIX_VEX_383C) },
6681 { PREFIX_TABLE (PREFIX_VEX_383D) },
6682 { PREFIX_TABLE (PREFIX_VEX_383E) },
6683 { PREFIX_TABLE (PREFIX_VEX_383F) },
6685 { PREFIX_TABLE (PREFIX_VEX_3840) },
6686 { PREFIX_TABLE (PREFIX_VEX_3841) },
6687 { "(bad)", { XX } },
6688 { "(bad)", { XX } },
6689 { "(bad)", { XX } },
6690 { "(bad)", { XX } },
6691 { "(bad)", { XX } },
6692 { "(bad)", { XX } },
6694 { "(bad)", { XX } },
6695 { "(bad)", { XX } },
6696 { "(bad)", { XX } },
6697 { "(bad)", { XX } },
6698 { "(bad)", { XX } },
6699 { "(bad)", { XX } },
6700 { "(bad)", { XX } },
6701 { "(bad)", { XX } },
6703 { "(bad)", { XX } },
6704 { "(bad)", { XX } },
6705 { "(bad)", { XX } },
6706 { "(bad)", { XX } },
6707 { "(bad)", { XX } },
6708 { "(bad)", { XX } },
6709 { "(bad)", { XX } },
6710 { "(bad)", { XX } },
6712 { "(bad)", { XX } },
6713 { "(bad)", { XX } },
6714 { "(bad)", { XX } },
6715 { "(bad)", { XX } },
6716 { "(bad)", { XX } },
6717 { "(bad)", { XX } },
6718 { "(bad)", { XX } },
6719 { "(bad)", { XX } },
6721 { "(bad)", { XX } },
6722 { "(bad)", { XX } },
6723 { "(bad)", { XX } },
6724 { "(bad)", { XX } },
6725 { "(bad)", { XX } },
6726 { "(bad)", { XX } },
6727 { "(bad)", { XX } },
6728 { "(bad)", { XX } },
6730 { "(bad)", { XX } },
6731 { "(bad)", { XX } },
6732 { "(bad)", { XX } },
6733 { "(bad)", { XX } },
6734 { "(bad)", { XX } },
6735 { "(bad)", { XX } },
6736 { "(bad)", { XX } },
6737 { "(bad)", { XX } },
6739 { "(bad)", { XX } },
6740 { "(bad)", { XX } },
6741 { "(bad)", { XX } },
6742 { "(bad)", { XX } },
6743 { "(bad)", { XX } },
6744 { "(bad)", { XX } },
6745 { "(bad)", { XX } },
6746 { "(bad)", { XX } },
6748 { "(bad)", { XX } },
6749 { "(bad)", { XX } },
6750 { "(bad)", { XX } },
6751 { "(bad)", { XX } },
6752 { "(bad)", { XX } },
6753 { "(bad)", { XX } },
6754 { "(bad)", { XX } },
6755 { "(bad)", { XX } },
6757 { "(bad)", { XX } },
6758 { "(bad)", { XX } },
6759 { "(bad)", { XX } },
6760 { "(bad)", { XX } },
6761 { "(bad)", { XX } },
6762 { "(bad)", { XX } },
6763 { "(bad)", { XX } },
6764 { "(bad)", { XX } },
6766 { "(bad)", { XX } },
6767 { "(bad)", { XX } },
6768 { "(bad)", { XX } },
6769 { "(bad)", { XX } },
6770 { "(bad)", { XX } },
6771 { "(bad)", { XX } },
6772 { "(bad)", { XX } },
6773 { "(bad)", { XX } },
6775 { "(bad)", { XX } },
6776 { "(bad)", { XX } },
6777 { "(bad)", { XX } },
6778 { "(bad)", { XX } },
6779 { "(bad)", { XX } },
6780 { "(bad)", { XX } },
6781 { PREFIX_TABLE (PREFIX_VEX_3896) },
6782 { PREFIX_TABLE (PREFIX_VEX_3897) },
6784 { PREFIX_TABLE (PREFIX_VEX_3898) },
6785 { PREFIX_TABLE (PREFIX_VEX_3899) },
6786 { PREFIX_TABLE (PREFIX_VEX_389A) },
6787 { PREFIX_TABLE (PREFIX_VEX_389B) },
6788 { PREFIX_TABLE (PREFIX_VEX_389C) },
6789 { PREFIX_TABLE (PREFIX_VEX_389D) },
6790 { PREFIX_TABLE (PREFIX_VEX_389E) },
6791 { PREFIX_TABLE (PREFIX_VEX_389F) },
6793 { "(bad)", { XX } },
6794 { "(bad)", { XX } },
6795 { "(bad)", { XX } },
6796 { "(bad)", { XX } },
6797 { "(bad)", { XX } },
6798 { "(bad)", { XX } },
6799 { PREFIX_TABLE (PREFIX_VEX_38A6) },
6800 { PREFIX_TABLE (PREFIX_VEX_38A7) },
6802 { PREFIX_TABLE (PREFIX_VEX_38A8) },
6803 { PREFIX_TABLE (PREFIX_VEX_38A9) },
6804 { PREFIX_TABLE (PREFIX_VEX_38AA) },
6805 { PREFIX_TABLE (PREFIX_VEX_38AB) },
6806 { PREFIX_TABLE (PREFIX_VEX_38AC) },
6807 { PREFIX_TABLE (PREFIX_VEX_38AD) },
6808 { PREFIX_TABLE (PREFIX_VEX_38AE) },
6809 { PREFIX_TABLE (PREFIX_VEX_38AF) },
6811 { "(bad)", { XX } },
6812 { "(bad)", { XX } },
6813 { "(bad)", { XX } },
6814 { "(bad)", { XX } },
6815 { "(bad)", { XX } },
6816 { "(bad)", { XX } },
6817 { PREFIX_TABLE (PREFIX_VEX_38B6) },
6818 { PREFIX_TABLE (PREFIX_VEX_38B7) },
6820 { PREFIX_TABLE (PREFIX_VEX_38B8) },
6821 { PREFIX_TABLE (PREFIX_VEX_38B9) },
6822 { PREFIX_TABLE (PREFIX_VEX_38BA) },
6823 { PREFIX_TABLE (PREFIX_VEX_38BB) },
6824 { PREFIX_TABLE (PREFIX_VEX_38BC) },
6825 { PREFIX_TABLE (PREFIX_VEX_38BD) },
6826 { PREFIX_TABLE (PREFIX_VEX_38BE) },
6827 { PREFIX_TABLE (PREFIX_VEX_38BF) },
6829 { "(bad)", { XX } },
6830 { "(bad)", { XX } },
6831 { "(bad)", { XX } },
6832 { "(bad)", { XX } },
6833 { "(bad)", { XX } },
6834 { "(bad)", { XX } },
6835 { "(bad)", { XX } },
6836 { "(bad)", { XX } },
6838 { "(bad)", { XX } },
6839 { "(bad)", { XX } },
6840 { "(bad)", { XX } },
6841 { "(bad)", { XX } },
6842 { "(bad)", { XX } },
6843 { "(bad)", { XX } },
6844 { "(bad)", { XX } },
6845 { "(bad)", { XX } },
6847 { "(bad)", { XX } },
6848 { "(bad)", { XX } },
6849 { "(bad)", { XX } },
6850 { "(bad)", { XX } },
6851 { "(bad)", { XX } },
6852 { "(bad)", { XX } },
6853 { "(bad)", { XX } },
6854 { "(bad)", { XX } },
6856 { "(bad)", { XX } },
6857 { "(bad)", { XX } },
6858 { "(bad)", { XX } },
6859 { PREFIX_TABLE (PREFIX_VEX_38DB) },
6860 { PREFIX_TABLE (PREFIX_VEX_38DC) },
6861 { PREFIX_TABLE (PREFIX_VEX_38DD) },
6862 { PREFIX_TABLE (PREFIX_VEX_38DE) },
6863 { PREFIX_TABLE (PREFIX_VEX_38DF) },
6865 { "(bad)", { XX } },
6866 { "(bad)", { XX } },
6867 { "(bad)", { XX } },
6868 { "(bad)", { XX } },
6869 { "(bad)", { XX } },
6870 { "(bad)", { XX } },
6871 { "(bad)", { XX } },
6872 { "(bad)", { XX } },
6874 { "(bad)", { XX } },
6875 { "(bad)", { XX } },
6876 { "(bad)", { XX } },
6877 { "(bad)", { XX } },
6878 { "(bad)", { XX } },
6879 { "(bad)", { XX } },
6880 { "(bad)", { XX } },
6881 { "(bad)", { XX } },
6883 { "(bad)", { XX } },
6884 { "(bad)", { XX } },
6885 { "(bad)", { XX } },
6886 { "(bad)", { XX } },
6887 { "(bad)", { XX } },
6888 { "(bad)", { XX } },
6889 { "(bad)", { XX } },
6890 { "(bad)", { XX } },
6892 { "(bad)", { XX } },
6893 { "(bad)", { XX } },
6894 { "(bad)", { XX } },
6895 { "(bad)", { XX } },
6896 { "(bad)", { XX } },
6897 { "(bad)", { XX } },
6898 { "(bad)", { XX } },
6899 { "(bad)", { XX } },
6904 { "(bad)", { XX } },
6905 { "(bad)", { XX } },
6906 { "(bad)", { XX } },
6907 { "(bad)", { XX } },
6908 { PREFIX_TABLE (PREFIX_VEX_3A04) },
6909 { PREFIX_TABLE (PREFIX_VEX_3A05) },
6910 { PREFIX_TABLE (PREFIX_VEX_3A06) },
6911 { "(bad)", { XX } },
6913 { PREFIX_TABLE (PREFIX_VEX_3A08) },
6914 { PREFIX_TABLE (PREFIX_VEX_3A09) },
6915 { PREFIX_TABLE (PREFIX_VEX_3A0A) },
6916 { PREFIX_TABLE (PREFIX_VEX_3A0B) },
6917 { PREFIX_TABLE (PREFIX_VEX_3A0C) },
6918 { PREFIX_TABLE (PREFIX_VEX_3A0D) },
6919 { PREFIX_TABLE (PREFIX_VEX_3A0E) },
6920 { PREFIX_TABLE (PREFIX_VEX_3A0F) },
6922 { "(bad)", { XX } },
6923 { "(bad)", { XX } },
6924 { "(bad)", { XX } },
6925 { "(bad)", { XX } },
6926 { PREFIX_TABLE (PREFIX_VEX_3A14) },
6927 { PREFIX_TABLE (PREFIX_VEX_3A15) },
6928 { PREFIX_TABLE (PREFIX_VEX_3A16) },
6929 { PREFIX_TABLE (PREFIX_VEX_3A17) },
6931 { PREFIX_TABLE (PREFIX_VEX_3A18) },
6932 { PREFIX_TABLE (PREFIX_VEX_3A19) },
6933 { "(bad)", { XX } },
6934 { "(bad)", { XX } },
6935 { "(bad)", { XX } },
6936 { "(bad)", { XX } },
6937 { "(bad)", { XX } },
6938 { "(bad)", { XX } },
6940 { PREFIX_TABLE (PREFIX_VEX_3A20) },
6941 { PREFIX_TABLE (PREFIX_VEX_3A21) },
6942 { PREFIX_TABLE (PREFIX_VEX_3A22) },
6943 { "(bad)", { XX } },
6944 { "(bad)", { XX } },
6945 { "(bad)", { XX } },
6946 { "(bad)", { XX } },
6947 { "(bad)", { XX } },
6949 { "(bad)", { XX } },
6950 { "(bad)", { XX } },
6951 { "(bad)", { XX } },
6952 { "(bad)", { XX } },
6953 { "(bad)", { XX } },
6954 { "(bad)", { XX } },
6955 { "(bad)", { XX } },
6956 { "(bad)", { XX } },
6958 { "(bad)", { XX } },
6959 { "(bad)", { XX } },
6960 { "(bad)", { XX } },
6961 { "(bad)", { XX } },
6962 { "(bad)", { XX } },
6963 { "(bad)", { XX } },
6964 { "(bad)", { XX } },
6965 { "(bad)", { XX } },
6967 { "(bad)", { XX } },
6968 { "(bad)", { XX } },
6969 { "(bad)", { XX } },
6970 { "(bad)", { XX } },
6971 { "(bad)", { XX } },
6972 { "(bad)", { XX } },
6973 { "(bad)", { XX } },
6974 { "(bad)", { XX } },
6976 { PREFIX_TABLE (PREFIX_VEX_3A40) },
6977 { PREFIX_TABLE (PREFIX_VEX_3A41) },
6978 { PREFIX_TABLE (PREFIX_VEX_3A42) },
6979 { "(bad)", { XX } },
6980 { PREFIX_TABLE (PREFIX_VEX_3A44) },
6981 { "(bad)", { XX } },
6982 { "(bad)", { XX } },
6983 { "(bad)", { XX } },
6985 { "(bad)", { XX } },
6986 { "(bad)", { XX } },
6987 { PREFIX_TABLE (PREFIX_VEX_3A4A) },
6988 { PREFIX_TABLE (PREFIX_VEX_3A4B) },
6989 { PREFIX_TABLE (PREFIX_VEX_3A4C) },
6990 { "(bad)", { XX } },
6991 { "(bad)", { XX } },
6992 { "(bad)", { XX } },
6994 { "(bad)", { XX } },
6995 { "(bad)", { XX } },
6996 { "(bad)", { XX } },
6997 { "(bad)", { XX } },
6998 { "(bad)", { XX } },
6999 { "(bad)", { XX } },
7000 { "(bad)", { XX } },
7001 { "(bad)", { XX } },
7003 { "(bad)", { XX } },
7004 { "(bad)", { XX } },
7005 { "(bad)", { XX } },
7006 { "(bad)", { XX } },
7007 { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7008 { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7009 { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7010 { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7012 { PREFIX_TABLE (PREFIX_VEX_3A60) },
7013 { PREFIX_TABLE (PREFIX_VEX_3A61) },
7014 { PREFIX_TABLE (PREFIX_VEX_3A62) },
7015 { PREFIX_TABLE (PREFIX_VEX_3A63) },
7016 { "(bad)", { XX } },
7017 { "(bad)", { XX } },
7018 { "(bad)", { XX } },
7019 { "(bad)", { XX } },
7021 { PREFIX_TABLE (PREFIX_VEX_3A68) },
7022 { PREFIX_TABLE (PREFIX_VEX_3A69) },
7023 { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7024 { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7025 { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7026 { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7027 { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7028 { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7030 { "(bad)", { XX } },
7031 { "(bad)", { XX } },
7032 { "(bad)", { XX } },
7033 { "(bad)", { XX } },
7034 { "(bad)", { XX } },
7035 { "(bad)", { XX } },
7036 { "(bad)", { XX } },
7037 { "(bad)", { XX } },
7039 { PREFIX_TABLE (PREFIX_VEX_3A78) },
7040 { PREFIX_TABLE (PREFIX_VEX_3A79) },
7041 { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7042 { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7043 { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7044 { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7045 { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7046 { PREFIX_TABLE (PREFIX_VEX_3A7F) },
7048 { "(bad)", { XX } },
7049 { "(bad)", { XX } },
7050 { "(bad)", { XX } },
7051 { "(bad)", { XX } },
7052 { "(bad)", { XX } },
7053 { "(bad)", { XX } },
7054 { "(bad)", { XX } },
7055 { "(bad)", { XX } },
7057 { "(bad)", { XX } },
7058 { "(bad)", { XX } },
7059 { "(bad)", { XX } },
7060 { "(bad)", { XX } },
7061 { "(bad)", { XX } },
7062 { "(bad)", { XX } },
7063 { "(bad)", { XX } },
7064 { "(bad)", { XX } },
7066 { "(bad)", { XX } },
7067 { "(bad)", { XX } },
7068 { "(bad)", { XX } },
7069 { "(bad)", { XX } },
7070 { "(bad)", { XX } },
7071 { "(bad)", { XX } },
7072 { "(bad)", { XX } },
7073 { "(bad)", { XX } },
7075 { "(bad)", { XX } },
7076 { "(bad)", { XX } },
7077 { "(bad)", { XX } },
7078 { "(bad)", { XX } },
7079 { "(bad)", { XX } },
7080 { "(bad)", { XX } },
7081 { "(bad)", { XX } },
7082 { "(bad)", { XX } },
7084 { "(bad)", { XX } },
7085 { "(bad)", { XX } },
7086 { "(bad)", { XX } },
7087 { "(bad)", { XX } },
7088 { "(bad)", { XX } },
7089 { "(bad)", { XX } },
7090 { "(bad)", { XX } },
7091 { "(bad)", { XX } },
7093 { "(bad)", { XX } },
7094 { "(bad)", { XX } },
7095 { "(bad)", { XX } },
7096 { "(bad)", { XX } },
7097 { "(bad)", { XX } },
7098 { "(bad)", { XX } },
7099 { "(bad)", { XX } },
7100 { "(bad)", { XX } },
7102 { "(bad)", { XX } },
7103 { "(bad)", { XX } },
7104 { "(bad)", { XX } },
7105 { "(bad)", { XX } },
7106 { "(bad)", { XX } },
7107 { "(bad)", { XX } },
7108 { "(bad)", { XX } },
7109 { "(bad)", { XX } },
7111 { "(bad)", { XX } },
7112 { "(bad)", { XX } },
7113 { "(bad)", { XX } },
7114 { "(bad)", { XX } },
7115 { "(bad)", { XX } },
7116 { "(bad)", { XX } },
7117 { "(bad)", { XX } },
7118 { "(bad)", { XX } },
7120 { "(bad)", { XX } },
7121 { "(bad)", { XX } },
7122 { "(bad)", { XX } },
7123 { "(bad)", { XX } },
7124 { "(bad)", { XX } },
7125 { "(bad)", { XX } },
7126 { "(bad)", { XX } },
7127 { "(bad)", { XX } },
7129 { "(bad)", { XX } },
7130 { "(bad)", { XX } },
7131 { "(bad)", { XX } },
7132 { "(bad)", { XX } },
7133 { "(bad)", { XX } },
7134 { "(bad)", { XX } },
7135 { "(bad)", { XX } },
7136 { "(bad)", { XX } },
7138 { "(bad)", { XX } },
7139 { "(bad)", { XX } },
7140 { "(bad)", { XX } },
7141 { "(bad)", { XX } },
7142 { "(bad)", { XX } },
7143 { "(bad)", { XX } },
7144 { "(bad)", { XX } },
7145 { "(bad)", { XX } },
7147 { "(bad)", { XX } },
7148 { "(bad)", { XX } },
7149 { "(bad)", { XX } },
7150 { "(bad)", { XX } },
7151 { "(bad)", { XX } },
7152 { "(bad)", { XX } },
7153 { "(bad)", { XX } },
7154 { PREFIX_TABLE (PREFIX_VEX_3ADF) },
7156 { "(bad)", { XX } },
7157 { "(bad)", { XX } },
7158 { "(bad)", { XX } },
7159 { "(bad)", { XX } },
7160 { "(bad)", { XX } },
7161 { "(bad)", { XX } },
7162 { "(bad)", { XX } },
7163 { "(bad)", { XX } },
7165 { "(bad)", { XX } },
7166 { "(bad)", { XX } },
7167 { "(bad)", { XX } },
7168 { "(bad)", { XX } },
7169 { "(bad)", { XX } },
7170 { "(bad)", { XX } },
7171 { "(bad)", { XX } },
7172 { "(bad)", { XX } },
7174 { "(bad)", { XX } },
7175 { "(bad)", { XX } },
7176 { "(bad)", { XX } },
7177 { "(bad)", { XX } },
7178 { "(bad)", { XX } },
7179 { "(bad)", { XX } },
7180 { "(bad)", { XX } },
7181 { "(bad)", { XX } },
7183 { "(bad)", { XX } },
7184 { "(bad)", { XX } },
7185 { "(bad)", { XX } },
7186 { "(bad)", { XX } },
7187 { "(bad)", { XX } },
7188 { "(bad)", { XX } },
7189 { "(bad)", { XX } },
7190 { "(bad)", { XX } },
7194 static const struct dis386 vex_len_table[][2] = {
7195 /* VEX_LEN_10_P_1 */
7197 { "vmovss", { XMVex, Vex128, EXd } },
7198 { "(bad)", { XX } },
7201 /* VEX_LEN_10_P_3 */
7203 { "vmovsd", { XMVex, Vex128, EXq } },
7204 { "(bad)", { XX } },
7207 /* VEX_LEN_11_P_1 */
7209 { "vmovss", { EXdVexS, Vex128, XM } },
7210 { "(bad)", { XX } },
7213 /* VEX_LEN_11_P_3 */
7215 { "vmovsd", { EXqVexS, Vex128, XM } },
7216 { "(bad)", { XX } },
7219 /* VEX_LEN_12_P_0_M_0 */
7221 { "vmovlps", { XM, Vex128, EXq } },
7222 { "(bad)", { XX } },
7225 /* VEX_LEN_12_P_0_M_1 */
7227 { "vmovhlps", { XM, Vex128, EXq } },
7228 { "(bad)", { XX } },
7231 /* VEX_LEN_12_P_2 */
7233 { "vmovlpd", { XM, Vex128, EXq } },
7234 { "(bad)", { XX } },
7237 /* VEX_LEN_13_M_0 */
7239 { "vmovlpX", { EXq, XM } },
7240 { "(bad)", { XX } },
7243 /* VEX_LEN_16_P_0_M_0 */
7245 { "vmovhps", { XM, Vex128, EXq } },
7246 { "(bad)", { XX } },
7249 /* VEX_LEN_16_P_0_M_1 */
7251 { "vmovlhps", { XM, Vex128, EXq } },
7252 { "(bad)", { XX } },
7255 /* VEX_LEN_16_P_2 */
7257 { "vmovhpd", { XM, Vex128, EXq } },
7258 { "(bad)", { XX } },
7261 /* VEX_LEN_17_M_0 */
7263 { "vmovhpX", { EXq, XM } },
7264 { "(bad)", { XX } },
7267 /* VEX_LEN_2A_P_1 */
7269 { "vcvtsi2ss%LQ", { XM, Vex128, Ev } },
7270 { "(bad)", { XX } },
7273 /* VEX_LEN_2A_P_3 */
7275 { "vcvtsi2sd%LQ", { XM, Vex128, Ev } },
7276 { "(bad)", { XX } },
7279 /* VEX_LEN_2C_P_1 */
7281 { "vcvttss2siY", { Gv, EXd } },
7282 { "(bad)", { XX } },
7285 /* VEX_LEN_2C_P_3 */
7287 { "vcvttsd2siY", { Gv, EXq } },
7288 { "(bad)", { XX } },
7291 /* VEX_LEN_2D_P_1 */
7293 { "vcvtss2siY", { Gv, EXd } },
7294 { "(bad)", { XX } },
7297 /* VEX_LEN_2D_P_3 */
7299 { "vcvtsd2siY", { Gv, EXq } },
7300 { "(bad)", { XX } },
7303 /* VEX_LEN_2E_P_0 */
7305 { "vucomiss", { XM, EXd } },
7306 { "(bad)", { XX } },
7309 /* VEX_LEN_2E_P_2 */
7311 { "vucomisd", { XM, EXq } },
7312 { "(bad)", { XX } },
7315 /* VEX_LEN_2F_P_0 */
7317 { "vcomiss", { XM, EXd } },
7318 { "(bad)", { XX } },
7321 /* VEX_LEN_2F_P_2 */
7323 { "vcomisd", { XM, EXq } },
7324 { "(bad)", { XX } },
7327 /* VEX_LEN_51_P_1 */
7329 { "vsqrtss", { XM, Vex128, EXd } },
7330 { "(bad)", { XX } },
7333 /* VEX_LEN_51_P_3 */
7335 { "vsqrtsd", { XM, Vex128, EXq } },
7336 { "(bad)", { XX } },
7339 /* VEX_LEN_52_P_1 */
7341 { "vrsqrtss", { XM, Vex128, EXd } },
7342 { "(bad)", { XX } },
7345 /* VEX_LEN_53_P_1 */
7347 { "vrcpss", { XM, Vex128, EXd } },
7348 { "(bad)", { XX } },
7351 /* VEX_LEN_58_P_1 */
7353 { "vaddss", { XM, Vex128, EXd } },
7354 { "(bad)", { XX } },
7357 /* VEX_LEN_58_P_3 */
7359 { "vaddsd", { XM, Vex128, EXq } },
7360 { "(bad)", { XX } },
7363 /* VEX_LEN_59_P_1 */
7365 { "vmulss", { XM, Vex128, EXd } },
7366 { "(bad)", { XX } },
7369 /* VEX_LEN_59_P_3 */
7371 { "vmulsd", { XM, Vex128, EXq } },
7372 { "(bad)", { XX } },
7375 /* VEX_LEN_5A_P_1 */
7377 { "vcvtss2sd", { XM, Vex128, EXd } },
7378 { "(bad)", { XX } },
7381 /* VEX_LEN_5A_P_3 */
7383 { "vcvtsd2ss", { XM, Vex128, EXq } },
7384 { "(bad)", { XX } },
7387 /* VEX_LEN_5C_P_1 */
7389 { "vsubss", { XM, Vex128, EXd } },
7390 { "(bad)", { XX } },
7393 /* VEX_LEN_5C_P_3 */
7395 { "vsubsd", { XM, Vex128, EXq } },
7396 { "(bad)", { XX } },
7399 /* VEX_LEN_5D_P_1 */
7401 { "vminss", { XM, Vex128, EXd } },
7402 { "(bad)", { XX } },
7405 /* VEX_LEN_5D_P_3 */
7407 { "vminsd", { XM, Vex128, EXq } },
7408 { "(bad)", { XX } },
7411 /* VEX_LEN_5E_P_1 */
7413 { "vdivss", { XM, Vex128, EXd } },
7414 { "(bad)", { XX } },
7417 /* VEX_LEN_5E_P_3 */
7419 { "vdivsd", { XM, Vex128, EXq } },
7420 { "(bad)", { XX } },
7423 /* VEX_LEN_5F_P_1 */
7425 { "vmaxss", { XM, Vex128, EXd } },
7426 { "(bad)", { XX } },
7429 /* VEX_LEN_5F_P_3 */
7431 { "vmaxsd", { XM, Vex128, EXq } },
7432 { "(bad)", { XX } },
7435 /* VEX_LEN_60_P_2 */
7437 { "vpunpcklbw", { XM, Vex128, EXx } },
7438 { "(bad)", { XX } },
7441 /* VEX_LEN_61_P_2 */
7443 { "vpunpcklwd", { XM, Vex128, EXx } },
7444 { "(bad)", { XX } },
7447 /* VEX_LEN_62_P_2 */
7449 { "vpunpckldq", { XM, Vex128, EXx } },
7450 { "(bad)", { XX } },
7453 /* VEX_LEN_63_P_2 */
7455 { "vpacksswb", { XM, Vex128, EXx } },
7456 { "(bad)", { XX } },
7459 /* VEX_LEN_64_P_2 */
7461 { "vpcmpgtb", { XM, Vex128, EXx } },
7462 { "(bad)", { XX } },
7465 /* VEX_LEN_65_P_2 */
7467 { "vpcmpgtw", { XM, Vex128, EXx } },
7468 { "(bad)", { XX } },
7471 /* VEX_LEN_66_P_2 */
7473 { "vpcmpgtd", { XM, Vex128, EXx } },
7474 { "(bad)", { XX } },
7477 /* VEX_LEN_67_P_2 */
7479 { "vpackuswb", { XM, Vex128, EXx } },
7480 { "(bad)", { XX } },
7483 /* VEX_LEN_68_P_2 */
7485 { "vpunpckhbw", { XM, Vex128, EXx } },
7486 { "(bad)", { XX } },
7489 /* VEX_LEN_69_P_2 */
7491 { "vpunpckhwd", { XM, Vex128, EXx } },
7492 { "(bad)", { XX } },
7495 /* VEX_LEN_6A_P_2 */
7497 { "vpunpckhdq", { XM, Vex128, EXx } },
7498 { "(bad)", { XX } },
7501 /* VEX_LEN_6B_P_2 */
7503 { "vpackssdw", { XM, Vex128, EXx } },
7504 { "(bad)", { XX } },
7507 /* VEX_LEN_6C_P_2 */
7509 { "vpunpcklqdq", { XM, Vex128, EXx } },
7510 { "(bad)", { XX } },
7513 /* VEX_LEN_6D_P_2 */
7515 { "vpunpckhqdq", { XM, Vex128, EXx } },
7516 { "(bad)", { XX } },
7519 /* VEX_LEN_6E_P_2 */
7521 { "vmovK", { XM, Edq } },
7522 { "(bad)", { XX } },
7525 /* VEX_LEN_70_P_1 */
7527 { "vpshufhw", { XM, EXx, Ib } },
7528 { "(bad)", { XX } },
7531 /* VEX_LEN_70_P_2 */
7533 { "vpshufd", { XM, EXx, Ib } },
7534 { "(bad)", { XX } },
7537 /* VEX_LEN_70_P_3 */
7539 { "vpshuflw", { XM, EXx, Ib } },
7540 { "(bad)", { XX } },
7543 /* VEX_LEN_71_R_2_P_2 */
7545 { "vpsrlw", { Vex128, XS, Ib } },
7546 { "(bad)", { XX } },
7549 /* VEX_LEN_71_R_4_P_2 */
7551 { "vpsraw", { Vex128, XS, Ib } },
7552 { "(bad)", { XX } },
7555 /* VEX_LEN_71_R_6_P_2 */
7557 { "vpsllw", { Vex128, XS, Ib } },
7558 { "(bad)", { XX } },
7561 /* VEX_LEN_72_R_2_P_2 */
7563 { "vpsrld", { Vex128, XS, Ib } },
7564 { "(bad)", { XX } },
7567 /* VEX_LEN_72_R_4_P_2 */
7569 { "vpsrad", { Vex128, XS, Ib } },
7570 { "(bad)", { XX } },
7573 /* VEX_LEN_72_R_6_P_2 */
7575 { "vpslld", { Vex128, XS, Ib } },
7576 { "(bad)", { XX } },
7579 /* VEX_LEN_73_R_2_P_2 */
7581 { "vpsrlq", { Vex128, XS, Ib } },
7582 { "(bad)", { XX } },
7585 /* VEX_LEN_73_R_3_P_2 */
7587 { "vpsrldq", { Vex128, XS, Ib } },
7588 { "(bad)", { XX } },
7591 /* VEX_LEN_73_R_6_P_2 */
7593 { "vpsllq", { Vex128, XS, Ib } },
7594 { "(bad)", { XX } },
7597 /* VEX_LEN_73_R_7_P_2 */
7599 { "vpslldq", { Vex128, XS, Ib } },
7600 { "(bad)", { XX } },
7603 /* VEX_LEN_74_P_2 */
7605 { "vpcmpeqb", { XM, Vex128, EXx } },
7606 { "(bad)", { XX } },
7609 /* VEX_LEN_75_P_2 */
7611 { "vpcmpeqw", { XM, Vex128, EXx } },
7612 { "(bad)", { XX } },
7615 /* VEX_LEN_76_P_2 */
7617 { "vpcmpeqd", { XM, Vex128, EXx } },
7618 { "(bad)", { XX } },
7621 /* VEX_LEN_7E_P_1 */
7623 { "vmovq", { XM, EXq } },
7624 { "(bad)", { XX } },
7627 /* VEX_LEN_7E_P_2 */
7629 { "vmovK", { Edq, XM } },
7630 { "(bad)", { XX } },
7633 /* VEX_LEN_AE_R_2_M_0 */
7635 { "vldmxcsr", { Md } },
7636 { "(bad)", { XX } },
7639 /* VEX_LEN_AE_R_3_M_0 */
7641 { "vstmxcsr", { Md } },
7642 { "(bad)", { XX } },
7645 /* VEX_LEN_C2_P_1 */
7647 { "vcmpss", { XM, Vex128, EXd, VCMP } },
7648 { "(bad)", { XX } },
7651 /* VEX_LEN_C2_P_3 */
7653 { "vcmpsd", { XM, Vex128, EXq, VCMP } },
7654 { "(bad)", { XX } },
7657 /* VEX_LEN_C4_P_2 */
7659 { "vpinsrw", { XM, Vex128, Edqw, Ib } },
7660 { "(bad)", { XX } },
7663 /* VEX_LEN_C5_P_2 */
7665 { "vpextrw", { Gdq, XS, Ib } },
7666 { "(bad)", { XX } },
7669 /* VEX_LEN_D1_P_2 */
7671 { "vpsrlw", { XM, Vex128, EXx } },
7672 { "(bad)", { XX } },
7675 /* VEX_LEN_D2_P_2 */
7677 { "vpsrld", { XM, Vex128, EXx } },
7678 { "(bad)", { XX } },
7681 /* VEX_LEN_D3_P_2 */
7683 { "vpsrlq", { XM, Vex128, EXx } },
7684 { "(bad)", { XX } },
7687 /* VEX_LEN_D4_P_2 */
7689 { "vpaddq", { XM, Vex128, EXx } },
7690 { "(bad)", { XX } },
7693 /* VEX_LEN_D5_P_2 */
7695 { "vpmullw", { XM, Vex128, EXx } },
7696 { "(bad)", { XX } },
7699 /* VEX_LEN_D6_P_2 */
7701 { "vmovq", { EXqS, XM } },
7702 { "(bad)", { XX } },
7705 /* VEX_LEN_D7_P_2_M_1 */
7707 { "vpmovmskb", { Gdq, XS } },
7708 { "(bad)", { XX } },
7711 /* VEX_LEN_D8_P_2 */
7713 { "vpsubusb", { XM, Vex128, EXx } },
7714 { "(bad)", { XX } },
7717 /* VEX_LEN_D9_P_2 */
7719 { "vpsubusw", { XM, Vex128, EXx } },
7720 { "(bad)", { XX } },
7723 /* VEX_LEN_DA_P_2 */
7725 { "vpminub", { XM, Vex128, EXx } },
7726 { "(bad)", { XX } },
7729 /* VEX_LEN_DB_P_2 */
7731 { "vpand", { XM, Vex128, EXx } },
7732 { "(bad)", { XX } },
7735 /* VEX_LEN_DC_P_2 */
7737 { "vpaddusb", { XM, Vex128, EXx } },
7738 { "(bad)", { XX } },
7741 /* VEX_LEN_DD_P_2 */
7743 { "vpaddusw", { XM, Vex128, EXx } },
7744 { "(bad)", { XX } },
7747 /* VEX_LEN_DE_P_2 */
7749 { "vpmaxub", { XM, Vex128, EXx } },
7750 { "(bad)", { XX } },
7753 /* VEX_LEN_DF_P_2 */
7755 { "vpandn", { XM, Vex128, EXx } },
7756 { "(bad)", { XX } },
7759 /* VEX_LEN_E0_P_2 */
7761 { "vpavgb", { XM, Vex128, EXx } },
7762 { "(bad)", { XX } },
7765 /* VEX_LEN_E1_P_2 */
7767 { "vpsraw", { XM, Vex128, EXx } },
7768 { "(bad)", { XX } },
7771 /* VEX_LEN_E2_P_2 */
7773 { "vpsrad", { XM, Vex128, EXx } },
7774 { "(bad)", { XX } },
7777 /* VEX_LEN_E3_P_2 */
7779 { "vpavgw", { XM, Vex128, EXx } },
7780 { "(bad)", { XX } },
7783 /* VEX_LEN_E4_P_2 */
7785 { "vpmulhuw", { XM, Vex128, EXx } },
7786 { "(bad)", { XX } },
7789 /* VEX_LEN_E5_P_2 */
7791 { "vpmulhw", { XM, Vex128, EXx } },
7792 { "(bad)", { XX } },
7795 /* VEX_LEN_E8_P_2 */
7797 { "vpsubsb", { XM, Vex128, EXx } },
7798 { "(bad)", { XX } },
7801 /* VEX_LEN_E9_P_2 */
7803 { "vpsubsw", { XM, Vex128, EXx } },
7804 { "(bad)", { XX } },
7807 /* VEX_LEN_EA_P_2 */
7809 { "vpminsw", { XM, Vex128, EXx } },
7810 { "(bad)", { XX } },
7813 /* VEX_LEN_EB_P_2 */
7815 { "vpor", { XM, Vex128, EXx } },
7816 { "(bad)", { XX } },
7819 /* VEX_LEN_EC_P_2 */
7821 { "vpaddsb", { XM, Vex128, EXx } },
7822 { "(bad)", { XX } },
7825 /* VEX_LEN_ED_P_2 */
7827 { "vpaddsw", { XM, Vex128, EXx } },
7828 { "(bad)", { XX } },
7831 /* VEX_LEN_EE_P_2 */
7833 { "vpmaxsw", { XM, Vex128, EXx } },
7834 { "(bad)", { XX } },
7837 /* VEX_LEN_EF_P_2 */
7839 { "vpxor", { XM, Vex128, EXx } },
7840 { "(bad)", { XX } },
7843 /* VEX_LEN_F1_P_2 */
7845 { "vpsllw", { XM, Vex128, EXx } },
7846 { "(bad)", { XX } },
7849 /* VEX_LEN_F2_P_2 */
7851 { "vpslld", { XM, Vex128, EXx } },
7852 { "(bad)", { XX } },
7855 /* VEX_LEN_F3_P_2 */
7857 { "vpsllq", { XM, Vex128, EXx } },
7858 { "(bad)", { XX } },
7861 /* VEX_LEN_F4_P_2 */
7863 { "vpmuludq", { XM, Vex128, EXx } },
7864 { "(bad)", { XX } },
7867 /* VEX_LEN_F5_P_2 */
7869 { "vpmaddwd", { XM, Vex128, EXx } },
7870 { "(bad)", { XX } },
7873 /* VEX_LEN_F6_P_2 */
7875 { "vpsadbw", { XM, Vex128, EXx } },
7876 { "(bad)", { XX } },
7879 /* VEX_LEN_F7_P_2 */
7881 { "vmaskmovdqu", { XM, XS } },
7882 { "(bad)", { XX } },
7885 /* VEX_LEN_F8_P_2 */
7887 { "vpsubb", { XM, Vex128, EXx } },
7888 { "(bad)", { XX } },
7891 /* VEX_LEN_F9_P_2 */
7893 { "vpsubw", { XM, Vex128, EXx } },
7894 { "(bad)", { XX } },
7897 /* VEX_LEN_FA_P_2 */
7899 { "vpsubd", { XM, Vex128, EXx } },
7900 { "(bad)", { XX } },
7903 /* VEX_LEN_FB_P_2 */
7905 { "vpsubq", { XM, Vex128, EXx } },
7906 { "(bad)", { XX } },
7909 /* VEX_LEN_FC_P_2 */
7911 { "vpaddb", { XM, Vex128, EXx } },
7912 { "(bad)", { XX } },
7915 /* VEX_LEN_FD_P_2 */
7917 { "vpaddw", { XM, Vex128, EXx } },
7918 { "(bad)", { XX } },
7921 /* VEX_LEN_FE_P_2 */
7923 { "vpaddd", { XM, Vex128, EXx } },
7924 { "(bad)", { XX } },
7927 /* VEX_LEN_3800_P_2 */
7929 { "vpshufb", { XM, Vex128, EXx } },
7930 { "(bad)", { XX } },
7933 /* VEX_LEN_3801_P_2 */
7935 { "vphaddw", { XM, Vex128, EXx } },
7936 { "(bad)", { XX } },
7939 /* VEX_LEN_3802_P_2 */
7941 { "vphaddd", { XM, Vex128, EXx } },
7942 { "(bad)", { XX } },
7945 /* VEX_LEN_3803_P_2 */
7947 { "vphaddsw", { XM, Vex128, EXx } },
7948 { "(bad)", { XX } },
7951 /* VEX_LEN_3804_P_2 */
7953 { "vpmaddubsw", { XM, Vex128, EXx } },
7954 { "(bad)", { XX } },
7957 /* VEX_LEN_3805_P_2 */
7959 { "vphsubw", { XM, Vex128, EXx } },
7960 { "(bad)", { XX } },
7963 /* VEX_LEN_3806_P_2 */
7965 { "vphsubd", { XM, Vex128, EXx } },
7966 { "(bad)", { XX } },
7969 /* VEX_LEN_3807_P_2 */
7971 { "vphsubsw", { XM, Vex128, EXx } },
7972 { "(bad)", { XX } },
7975 /* VEX_LEN_3808_P_2 */
7977 { "vpsignb", { XM, Vex128, EXx } },
7978 { "(bad)", { XX } },
7981 /* VEX_LEN_3809_P_2 */
7983 { "vpsignw", { XM, Vex128, EXx } },
7984 { "(bad)", { XX } },
7987 /* VEX_LEN_380A_P_2 */
7989 { "vpsignd", { XM, Vex128, EXx } },
7990 { "(bad)", { XX } },
7993 /* VEX_LEN_380B_P_2 */
7995 { "vpmulhrsw", { XM, Vex128, EXx } },
7996 { "(bad)", { XX } },
7999 /* VEX_LEN_3819_P_2_M_0 */
8001 { "(bad)", { XX } },
8002 { "vbroadcastsd", { XM, Mq } },
8005 /* VEX_LEN_381A_P_2_M_0 */
8007 { "(bad)", { XX } },
8008 { "vbroadcastf128", { XM, Mxmm } },
8011 /* VEX_LEN_381C_P_2 */
8013 { "vpabsb", { XM, EXx } },
8014 { "(bad)", { XX } },
8017 /* VEX_LEN_381D_P_2 */
8019 { "vpabsw", { XM, EXx } },
8020 { "(bad)", { XX } },
8023 /* VEX_LEN_381E_P_2 */
8025 { "vpabsd", { XM, EXx } },
8026 { "(bad)", { XX } },
8029 /* VEX_LEN_3820_P_2 */
8031 { "vpmovsxbw", { XM, EXq } },
8032 { "(bad)", { XX } },
8035 /* VEX_LEN_3821_P_2 */
8037 { "vpmovsxbd", { XM, EXd } },
8038 { "(bad)", { XX } },
8041 /* VEX_LEN_3822_P_2 */
8043 { "vpmovsxbq", { XM, EXw } },
8044 { "(bad)", { XX } },
8047 /* VEX_LEN_3823_P_2 */
8049 { "vpmovsxwd", { XM, EXq } },
8050 { "(bad)", { XX } },
8053 /* VEX_LEN_3824_P_2 */
8055 { "vpmovsxwq", { XM, EXd } },
8056 { "(bad)", { XX } },
8059 /* VEX_LEN_3825_P_2 */
8061 { "vpmovsxdq", { XM, EXq } },
8062 { "(bad)", { XX } },
8065 /* VEX_LEN_3828_P_2 */
8067 { "vpmuldq", { XM, Vex128, EXx } },
8068 { "(bad)", { XX } },
8071 /* VEX_LEN_3829_P_2 */
8073 { "vpcmpeqq", { XM, Vex128, EXx } },
8074 { "(bad)", { XX } },
8077 /* VEX_LEN_382A_P_2_M_0 */
8079 { "vmovntdqa", { XM, Mx } },
8080 { "(bad)", { XX } },
8083 /* VEX_LEN_382B_P_2 */
8085 { "vpackusdw", { XM, Vex128, EXx } },
8086 { "(bad)", { XX } },
8089 /* VEX_LEN_3830_P_2 */
8091 { "vpmovzxbw", { XM, EXq } },
8092 { "(bad)", { XX } },
8095 /* VEX_LEN_3831_P_2 */
8097 { "vpmovzxbd", { XM, EXd } },
8098 { "(bad)", { XX } },
8101 /* VEX_LEN_3832_P_2 */
8103 { "vpmovzxbq", { XM, EXw } },
8104 { "(bad)", { XX } },
8107 /* VEX_LEN_3833_P_2 */
8109 { "vpmovzxwd", { XM, EXq } },
8110 { "(bad)", { XX } },
8113 /* VEX_LEN_3834_P_2 */
8115 { "vpmovzxwq", { XM, EXd } },
8116 { "(bad)", { XX } },
8119 /* VEX_LEN_3835_P_2 */
8121 { "vpmovzxdq", { XM, EXq } },
8122 { "(bad)", { XX } },
8125 /* VEX_LEN_3837_P_2 */
8127 { "vpcmpgtq", { XM, Vex128, EXx } },
8128 { "(bad)", { XX } },
8131 /* VEX_LEN_3838_P_2 */
8133 { "vpminsb", { XM, Vex128, EXx } },
8134 { "(bad)", { XX } },
8137 /* VEX_LEN_3839_P_2 */
8139 { "vpminsd", { XM, Vex128, EXx } },
8140 { "(bad)", { XX } },
8143 /* VEX_LEN_383A_P_2 */
8145 { "vpminuw", { XM, Vex128, EXx } },
8146 { "(bad)", { XX } },
8149 /* VEX_LEN_383B_P_2 */
8151 { "vpminud", { XM, Vex128, EXx } },
8152 { "(bad)", { XX } },
8155 /* VEX_LEN_383C_P_2 */
8157 { "vpmaxsb", { XM, Vex128, EXx } },
8158 { "(bad)", { XX } },
8161 /* VEX_LEN_383D_P_2 */
8163 { "vpmaxsd", { XM, Vex128, EXx } },
8164 { "(bad)", { XX } },
8167 /* VEX_LEN_383E_P_2 */
8169 { "vpmaxuw", { XM, Vex128, EXx } },
8170 { "(bad)", { XX } },
8173 /* VEX_LEN_383F_P_2 */
8175 { "vpmaxud", { XM, Vex128, EXx } },
8176 { "(bad)", { XX } },
8179 /* VEX_LEN_3840_P_2 */
8181 { "vpmulld", { XM, Vex128, EXx } },
8182 { "(bad)", { XX } },
8185 /* VEX_LEN_3841_P_2 */
8187 { "vphminposuw", { XM, EXx } },
8188 { "(bad)", { XX } },
8191 /* VEX_LEN_38DB_P_2 */
8193 { "vaesimc", { XM, EXx } },
8194 { "(bad)", { XX } },
8197 /* VEX_LEN_38DC_P_2 */
8199 { "vaesenc", { XM, Vex128, EXx } },
8200 { "(bad)", { XX } },
8203 /* VEX_LEN_38DD_P_2 */
8205 { "vaesenclast", { XM, Vex128, EXx } },
8206 { "(bad)", { XX } },
8209 /* VEX_LEN_38DE_P_2 */
8211 { "vaesdec", { XM, Vex128, EXx } },
8212 { "(bad)", { XX } },
8215 /* VEX_LEN_38DF_P_2 */
8217 { "vaesdeclast", { XM, Vex128, EXx } },
8218 { "(bad)", { XX } },
8221 /* VEX_LEN_3A06_P_2 */
8223 { "(bad)", { XX } },
8224 { "vperm2f128", { XM, Vex256, EXx, Ib } },
8227 /* VEX_LEN_3A0A_P_2 */
8229 { "vroundss", { XM, Vex128, EXd, Ib } },
8230 { "(bad)", { XX } },
8233 /* VEX_LEN_3A0B_P_2 */
8235 { "vroundsd", { XM, Vex128, EXq, Ib } },
8236 { "(bad)", { XX } },
8239 /* VEX_LEN_3A0E_P_2 */
8241 { "vpblendw", { XM, Vex128, EXx, Ib } },
8242 { "(bad)", { XX } },
8245 /* VEX_LEN_3A0F_P_2 */
8247 { "vpalignr", { XM, Vex128, EXx, Ib } },
8248 { "(bad)", { XX } },
8251 /* VEX_LEN_3A14_P_2 */
8253 { "vpextrb", { Edqb, XM, Ib } },
8254 { "(bad)", { XX } },
8257 /* VEX_LEN_3A15_P_2 */
8259 { "vpextrw", { Edqw, XM, Ib } },
8260 { "(bad)", { XX } },
8263 /* VEX_LEN_3A16_P_2 */
8265 { "vpextrK", { Edq, XM, Ib } },
8266 { "(bad)", { XX } },
8269 /* VEX_LEN_3A17_P_2 */
8271 { "vextractps", { Edqd, XM, Ib } },
8272 { "(bad)", { XX } },
8275 /* VEX_LEN_3A18_P_2 */
8277 { "(bad)", { XX } },
8278 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },
8281 /* VEX_LEN_3A19_P_2 */
8283 { "(bad)", { XX } },
8284 { "vextractf128", { EXxmm, XM, Ib } },
8287 /* VEX_LEN_3A20_P_2 */
8289 { "vpinsrb", { XM, Vex128, Edqb, Ib } },
8290 { "(bad)", { XX } },
8293 /* VEX_LEN_3A21_P_2 */
8295 { "vinsertps", { XM, Vex128, EXd, Ib } },
8296 { "(bad)", { XX } },
8299 /* VEX_LEN_3A22_P_2 */
8301 { "vpinsrK", { XM, Vex128, Edq, Ib } },
8302 { "(bad)", { XX } },
8305 /* VEX_LEN_3A41_P_2 */
8307 { "vdppd", { XM, Vex128, EXx, Ib } },
8308 { "(bad)", { XX } },
8311 /* VEX_LEN_3A42_P_2 */
8313 { "vmpsadbw", { XM, Vex128, EXx, Ib } },
8314 { "(bad)", { XX } },
8317 /* VEX_LEN_3A44_P_2 */
8319 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } },
8320 { "(bad)", { XX } },
8323 /* VEX_LEN_3A4C_P_2 */
8325 { "vpblendvb", { XM, Vex128, EXx, XMVexI4 } },
8326 { "(bad)", { XX } },
8329 /* VEX_LEN_3A60_P_2 */
8331 { "vpcmpestrm", { XM, EXx, Ib } },
8332 { "(bad)", { XX } },
8335 /* VEX_LEN_3A61_P_2 */
8337 { "vpcmpestri", { XM, EXx, Ib } },
8338 { "(bad)", { XX } },
8341 /* VEX_LEN_3A62_P_2 */
8343 { "vpcmpistrm", { XM, EXx, Ib } },
8344 { "(bad)", { XX } },
8347 /* VEX_LEN_3A63_P_2 */
8349 { "vpcmpistri", { XM, EXx, Ib } },
8350 { "(bad)", { XX } },
8353 /* VEX_LEN_3A6A_P_2 */
8355 { "vfmaddss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
8356 { "(bad)", { XX } },
8359 /* VEX_LEN_3A6B_P_2 */
8361 { "vfmaddsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
8362 { "(bad)", { XX } },
8365 /* VEX_LEN_3A6E_P_2 */
8367 { "vfmsubss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
8368 { "(bad)", { XX } },
8371 /* VEX_LEN_3A6F_P_2 */
8373 { "vfmsubsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
8374 { "(bad)", { XX } },
8377 /* VEX_LEN_3A7A_P_2 */
8379 { "vfnmaddss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
8380 { "(bad)", { XX } },
8383 /* VEX_LEN_3A7B_P_2 */
8385 { "vfnmaddsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
8386 { "(bad)", { XX } },
8389 /* VEX_LEN_3A7E_P_2 */
8391 { "vfnmsubss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
8392 { "(bad)", { XX } },
8395 /* VEX_LEN_3A7F_P_2 */
8397 { "vfnmsubsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
8398 { "(bad)", { XX } },
8401 /* VEX_LEN_3ADF_P_2 */
8403 { "vaeskeygenassist", { XM, EXx, Ib } },
8404 { "(bad)", { XX } },
8408 static const struct dis386 mod_table[][2] = {
8411 { "leaS", { Gv, M } },
8412 { "(bad)", { XX } },
8415 /* MOD_0F01_REG_0 */
8416 { X86_64_TABLE (X86_64_0F01_REG_0) },
8417 { RM_TABLE (RM_0F01_REG_0) },
8420 /* MOD_0F01_REG_1 */
8421 { X86_64_TABLE (X86_64_0F01_REG_1) },
8422 { RM_TABLE (RM_0F01_REG_1) },
8425 /* MOD_0F01_REG_2 */
8426 { X86_64_TABLE (X86_64_0F01_REG_2) },
8427 { RM_TABLE (RM_0F01_REG_2) },
8430 /* MOD_0F01_REG_3 */
8431 { X86_64_TABLE (X86_64_0F01_REG_3) },
8432 { RM_TABLE (RM_0F01_REG_3) },
8435 /* MOD_0F01_REG_7 */
8436 { "invlpg", { Mb } },
8437 { RM_TABLE (RM_0F01_REG_7) },
8440 /* MOD_0F12_PREFIX_0 */
8441 { "movlps", { XM, EXq } },
8442 { "movhlps", { XM, EXq } },
8446 { "movlpX", { EXq, XM } },
8447 { "(bad)", { XX } },
8450 /* MOD_0F16_PREFIX_0 */
8451 { "movhps", { XM, EXq } },
8452 { "movlhps", { XM, EXq } },
8456 { "movhpX", { EXq, XM } },
8457 { "(bad)", { XX } },
8460 /* MOD_0F18_REG_0 */
8461 { "prefetchnta", { Mb } },
8462 { "(bad)", { XX } },
8465 /* MOD_0F18_REG_1 */
8466 { "prefetcht0", { Mb } },
8467 { "(bad)", { XX } },
8470 /* MOD_0F18_REG_2 */
8471 { "prefetcht1", { Mb } },
8472 { "(bad)", { XX } },
8475 /* MOD_0F18_REG_3 */
8476 { "prefetcht2", { Mb } },
8477 { "(bad)", { XX } },
8481 { "(bad)", { XX } },
8482 { "movZ", { Rm, Cm } },
8486 { "(bad)", { XX } },
8487 { "movZ", { Rm, Dm } },
8491 { "(bad)", { XX } },
8492 { "movZ", { Cm, Rm } },
8496 { "(bad)", { XX } },
8497 { "movZ", { Dm, Rm } },
8501 { "(bad)", { XX } },
8502 { "movL", { Rd, Td } },
8506 { "(bad)", { XX } },
8507 { "movL", { Td, Rd } },
8510 /* MOD_0F2B_PREFIX_0 */
8511 {"movntps", { Mx, XM } },
8512 { "(bad)", { XX } },
8515 /* MOD_0F2B_PREFIX_1 */
8516 {"movntss", { Md, XM } },
8517 { "(bad)", { XX } },
8520 /* MOD_0F2B_PREFIX_2 */
8521 {"movntpd", { Mx, XM } },
8522 { "(bad)", { XX } },
8525 /* MOD_0F2B_PREFIX_3 */
8526 {"movntsd", { Mq, XM } },
8527 { "(bad)", { XX } },
8531 { "(bad)", { XX } },
8532 { "movmskpX", { Gdq, XS } },
8535 /* MOD_0F71_REG_2 */
8536 { "(bad)", { XX } },
8537 { "psrlw", { MS, Ib } },
8540 /* MOD_0F71_REG_4 */
8541 { "(bad)", { XX } },
8542 { "psraw", { MS, Ib } },
8545 /* MOD_0F71_REG_6 */
8546 { "(bad)", { XX } },
8547 { "psllw", { MS, Ib } },
8550 /* MOD_0F72_REG_2 */
8551 { "(bad)", { XX } },
8552 { "psrld", { MS, Ib } },
8555 /* MOD_0F72_REG_4 */
8556 { "(bad)", { XX } },
8557 { "psrad", { MS, Ib } },
8560 /* MOD_0F72_REG_6 */
8561 { "(bad)", { XX } },
8562 { "pslld", { MS, Ib } },
8565 /* MOD_0F73_REG_2 */
8566 { "(bad)", { XX } },
8567 { "psrlq", { MS, Ib } },
8570 /* MOD_0F73_REG_3 */
8571 { "(bad)", { XX } },
8572 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
8575 /* MOD_0F73_REG_6 */
8576 { "(bad)", { XX } },
8577 { "psllq", { MS, Ib } },
8580 /* MOD_0F73_REG_7 */
8581 { "(bad)", { XX } },
8582 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
8585 /* MOD_0FAE_REG_0 */
8586 { "fxsave", { M } },
8587 { "(bad)", { XX } },
8590 /* MOD_0FAE_REG_1 */
8591 { "fxrstor", { M } },
8592 { "(bad)", { XX } },
8595 /* MOD_0FAE_REG_2 */
8596 { "ldmxcsr", { Md } },
8597 { "(bad)", { XX } },
8600 /* MOD_0FAE_REG_3 */
8601 { "stmxcsr", { Md } },
8602 { "(bad)", { XX } },
8605 /* MOD_0FAE_REG_4 */
8607 { "(bad)", { XX } },
8610 /* MOD_0FAE_REG_5 */
8611 { "xrstor", { M } },
8612 { RM_TABLE (RM_0FAE_REG_5) },
8615 /* MOD_0FAE_REG_6 */
8616 { "xsaveopt", { M } },
8617 { RM_TABLE (RM_0FAE_REG_6) },
8620 /* MOD_0FAE_REG_7 */
8621 { "clflush", { Mb } },
8622 { RM_TABLE (RM_0FAE_REG_7) },
8626 { "lssS", { Gv, Mp } },
8627 { "(bad)", { XX } },
8631 { "lfsS", { Gv, Mp } },
8632 { "(bad)", { XX } },
8636 { "lgsS", { Gv, Mp } },
8637 { "(bad)", { XX } },
8640 /* MOD_0FC7_REG_6 */
8641 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
8642 { "(bad)", { XX } },
8645 /* MOD_0FC7_REG_7 */
8646 { "vmptrst", { Mq } },
8647 { "(bad)", { XX } },
8651 { "(bad)", { XX } },
8652 { "pmovmskb", { Gdq, MS } },
8655 /* MOD_0FE7_PREFIX_2 */
8656 { "movntdq", { Mx, XM } },
8657 { "(bad)", { XX } },
8660 /* MOD_0FF0_PREFIX_3 */
8661 { "lddqu", { XM, M } },
8662 { "(bad)", { XX } },
8665 /* MOD_0F382A_PREFIX_2 */
8666 { "movntdqa", { XM, Mx } },
8667 { "(bad)", { XX } },
8671 { "bound{S|}", { Gv, Ma } },
8672 { "(bad)", { XX } },
8676 { "lesS", { Gv, Mp } },
8677 { VEX_C4_TABLE (VEX_0F) },
8681 { "ldsS", { Gv, Mp } },
8682 { VEX_C5_TABLE (VEX_0F) },
8685 /* MOD_VEX_12_PREFIX_0 */
8686 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
8687 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
8691 { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
8692 { "(bad)", { XX } },
8695 /* MOD_VEX_16_PREFIX_0 */
8696 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
8697 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
8701 { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
8702 { "(bad)", { XX } },
8706 { "vmovntpX", { Mx, XM } },
8707 { "(bad)", { XX } },
8711 { "(bad)", { XX } },
8712 { "vmovmskpX", { Gdq, XS } },
8715 /* MOD_VEX_71_REG_2 */
8716 { "(bad)", { XX } },
8717 { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
8720 /* MOD_VEX_71_REG_4 */
8721 { "(bad)", { XX } },
8722 { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
8725 /* MOD_VEX_71_REG_6 */
8726 { "(bad)", { XX } },
8727 { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
8730 /* MOD_VEX_72_REG_2 */
8731 { "(bad)", { XX } },
8732 { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
8735 /* MOD_VEX_72_REG_4 */
8736 { "(bad)", { XX } },
8737 { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
8740 /* MOD_VEX_72_REG_6 */
8741 { "(bad)", { XX } },
8742 { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
8745 /* MOD_VEX_73_REG_2 */
8746 { "(bad)", { XX } },
8747 { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
8750 /* MOD_VEX_73_REG_3 */
8751 { "(bad)", { XX } },
8752 { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
8755 /* MOD_VEX_73_REG_6 */
8756 { "(bad)", { XX } },
8757 { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
8760 /* MOD_VEX_73_REG_7 */
8761 { "(bad)", { XX } },
8762 { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
8765 /* MOD_VEX_AE_REG_2 */
8766 { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
8767 { "(bad)", { XX } },
8770 /* MOD_VEX_AE_REG_3 */
8771 { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
8772 { "(bad)", { XX } },
8775 /* MOD_VEX_D7_PREFIX_2 */
8776 { "(bad)", { XX } },
8777 { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
8780 /* MOD_VEX_E7_PREFIX_2 */
8781 { "vmovntdq", { Mx, XM } },
8782 { "(bad)", { XX } },
8785 /* MOD_VEX_F0_PREFIX_3 */
8786 { "vlddqu", { XM, M } },
8787 { "(bad)", { XX } },
8790 /* MOD_VEX_3818_PREFIX_2 */
8791 { "vbroadcastss", { XM, Md } },
8792 { "(bad)", { XX } },
8795 /* MOD_VEX_3819_PREFIX_2 */
8796 { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
8797 { "(bad)", { XX } },
8800 /* MOD_VEX_381A_PREFIX_2 */
8801 { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
8802 { "(bad)", { XX } },
8805 /* MOD_VEX_382A_PREFIX_2 */
8806 { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
8807 { "(bad)", { XX } },
8810 /* MOD_VEX_382C_PREFIX_2 */
8811 { "vmaskmovps", { XM, Vex, Mx } },
8812 { "(bad)", { XX } },
8815 /* MOD_VEX_382D_PREFIX_2 */
8816 { "vmaskmovpd", { XM, Vex, Mx } },
8817 { "(bad)", { XX } },
8820 /* MOD_VEX_382E_PREFIX_2 */
8821 { "vmaskmovps", { Mx, Vex, XM } },
8822 { "(bad)", { XX } },
8825 /* MOD_VEX_382F_PREFIX_2 */
8826 { "vmaskmovpd", { Mx, Vex, XM } },
8827 { "(bad)", { XX } },
8831 static const struct dis386 rm_table[][8] = {
8834 { "(bad)", { XX } },
8835 { "vmcall", { Skip_MODRM } },
8836 { "vmlaunch", { Skip_MODRM } },
8837 { "vmresume", { Skip_MODRM } },
8838 { "vmxoff", { Skip_MODRM } },
8839 { "(bad)", { XX } },
8840 { "(bad)", { XX } },
8841 { "(bad)", { XX } },
8845 { "monitor", { { OP_Monitor, 0 } } },
8846 { "mwait", { { OP_Mwait, 0 } } },
8847 { "(bad)", { XX } },
8848 { "(bad)", { XX } },
8849 { "(bad)", { XX } },
8850 { "(bad)", { XX } },
8851 { "(bad)", { XX } },
8852 { "(bad)", { XX } },
8856 { "xgetbv", { Skip_MODRM } },
8857 { "xsetbv", { Skip_MODRM } },
8858 { "(bad)", { XX } },
8859 { "(bad)", { XX } },
8860 { "(bad)", { XX } },
8861 { "(bad)", { XX } },
8862 { "(bad)", { XX } },
8863 { "(bad)", { XX } },
8867 { "vmrun", { Skip_MODRM } },
8868 { "vmmcall", { Skip_MODRM } },
8869 { "vmload", { Skip_MODRM } },
8870 { "vmsave", { Skip_MODRM } },
8871 { "stgi", { Skip_MODRM } },
8872 { "clgi", { Skip_MODRM } },
8873 { "skinit", { Skip_MODRM } },
8874 { "invlpga", { Skip_MODRM } },
8878 { "swapgs", { Skip_MODRM } },
8879 { "rdtscp", { Skip_MODRM } },
8880 { "(bad)", { XX } },
8881 { "(bad)", { XX } },
8882 { "(bad)", { XX } },
8883 { "(bad)", { XX } },
8884 { "(bad)", { XX } },
8885 { "(bad)", { XX } },
8889 { "lfence", { Skip_MODRM } },
8890 { "(bad)", { XX } },
8891 { "(bad)", { XX } },
8892 { "(bad)", { XX } },
8893 { "(bad)", { XX } },
8894 { "(bad)", { XX } },
8895 { "(bad)", { XX } },
8896 { "(bad)", { XX } },
8900 { "mfence", { Skip_MODRM } },
8901 { "(bad)", { XX } },
8902 { "(bad)", { XX } },
8903 { "(bad)", { XX } },
8904 { "(bad)", { XX } },
8905 { "(bad)", { XX } },
8906 { "(bad)", { XX } },
8907 { "(bad)", { XX } },
8911 { "sfence", { Skip_MODRM } },
8912 { "(bad)", { XX } },
8913 { "(bad)", { XX } },
8914 { "(bad)", { XX } },
8915 { "(bad)", { XX } },
8916 { "(bad)", { XX } },
8917 { "(bad)", { XX } },
8918 { "(bad)", { XX } },
8922 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8936 FETCH_DATA (the_info, codep + 1);
8940 /* REX prefixes family. */
8957 if (address_mode == mode_64bit)
8963 prefixes |= PREFIX_REPZ;
8966 prefixes |= PREFIX_REPNZ;
8969 prefixes |= PREFIX_LOCK;
8972 prefixes |= PREFIX_CS;
8975 prefixes |= PREFIX_SS;
8978 prefixes |= PREFIX_DS;
8981 prefixes |= PREFIX_ES;
8984 prefixes |= PREFIX_FS;
8987 prefixes |= PREFIX_GS;
8990 prefixes |= PREFIX_DATA;
8993 prefixes |= PREFIX_ADDR;
8996 /* fwait is really an instruction. If there are prefixes
8997 before the fwait, they belong to the fwait, *not* to the
8998 following instruction. */
8999 if (prefixes || rex)
9001 prefixes |= PREFIX_FWAIT;
9005 prefixes = PREFIX_FWAIT;
9010 /* Rex is ignored when followed by another prefix. */
9022 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9026 prefix_name (int pref, int sizeflag)
9028 static const char *rexes [16] =
9033 "rex.XB", /* 0x43 */
9035 "rex.RB", /* 0x45 */
9036 "rex.RX", /* 0x46 */
9037 "rex.RXB", /* 0x47 */
9039 "rex.WB", /* 0x49 */
9040 "rex.WX", /* 0x4a */
9041 "rex.WXB", /* 0x4b */
9042 "rex.WR", /* 0x4c */
9043 "rex.WRB", /* 0x4d */
9044 "rex.WRX", /* 0x4e */
9045 "rex.WRXB", /* 0x4f */
9050 /* REX prefixes family. */
9067 return rexes [pref - 0x40];
9087 return (sizeflag & DFLAG) ? "data16" : "data32";
9089 if (address_mode == mode_64bit)
9090 return (sizeflag & AFLAG) ? "addr32" : "addr64";
9092 return (sizeflag & AFLAG) ? "addr16" : "addr32";
9100 static char op_out[MAX_OPERANDS][100];
9101 static int op_ad, op_index[MAX_OPERANDS];
9102 static int two_source_ops;
9103 static bfd_vma op_address[MAX_OPERANDS];
9104 static bfd_vma op_riprel[MAX_OPERANDS];
9105 static bfd_vma start_pc;
9108 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9109 * (see topic "Redundant prefixes" in the "Differences from 8086"
9110 * section of the "Virtual 8086 Mode" chapter.)
9111 * 'pc' should be the address of this instruction, it will
9112 * be used to print the target address if this is a relative jump or call
9113 * The function returns the length of this instruction in bytes.
9116 static char intel_syntax;
9117 static char intel_mnemonic = !SYSV386_COMPAT;
9118 static char open_char;
9119 static char close_char;
9120 static char separator_char;
9121 static char scale_char;
9123 /* Here for backwards compatibility. When gdb stops using
9124 print_insn_i386_att and print_insn_i386_intel these functions can
9125 disappear, and print_insn_i386 be merged into print_insn. */
9127 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9131 return print_insn (pc, info);
9135 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9139 return print_insn (pc, info);
9143 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9147 return print_insn (pc, info);
9151 print_i386_disassembler_options (FILE *stream)
9153 fprintf (stream, _("\n\
9154 The following i386/x86-64 specific disassembler options are supported for use\n\
9155 with the -M switch (multiple options should be separated by commas):\n"));
9157 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
9158 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
9159 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
9160 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
9161 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
9162 fprintf (stream, _(" att-mnemonic\n"
9163 " Display instruction in AT&T mnemonic\n"));
9164 fprintf (stream, _(" intel-mnemonic\n"
9165 " Display instruction in Intel mnemonic\n"));
9166 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
9167 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
9168 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
9169 fprintf (stream, _(" data32 Assume 32bit data size\n"));
9170 fprintf (stream, _(" data16 Assume 16bit data size\n"));
9171 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
9174 /* Get a pointer to struct dis386 with a valid name. */
9176 static const struct dis386 *
9177 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9179 int index, vex_table_index;
9181 if (dp->name != NULL)
9184 switch (dp->op[0].bytemode)
9187 dp = ®_table[dp->op[1].bytemode][modrm.reg];
9191 index = modrm.mod == 0x3 ? 1 : 0;
9192 dp = &mod_table[dp->op[1].bytemode][index];
9196 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9199 case USE_PREFIX_TABLE:
9202 /* The prefix in VEX is implicit. */
9208 case REPE_PREFIX_OPCODE:
9211 case DATA_PREFIX_OPCODE:
9214 case REPNE_PREFIX_OPCODE:
9225 used_prefixes |= (prefixes & PREFIX_REPZ);
9226 if (prefixes & PREFIX_REPZ)
9233 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
9235 used_prefixes |= (prefixes & PREFIX_REPNZ);
9236 if (prefixes & PREFIX_REPNZ)
9239 repnz_prefix = NULL;
9243 used_prefixes |= (prefixes & PREFIX_DATA);
9244 if (prefixes & PREFIX_DATA)
9252 dp = &prefix_table[dp->op[1].bytemode][index];
9255 case USE_X86_64_TABLE:
9256 index = address_mode == mode_64bit ? 1 : 0;
9257 dp = &x86_64_table[dp->op[1].bytemode][index];
9260 case USE_3BYTE_TABLE:
9261 FETCH_DATA (info, codep + 2);
9263 dp = &three_byte_table[dp->op[1].bytemode][index];
9264 modrm.mod = (*codep >> 6) & 3;
9265 modrm.reg = (*codep >> 3) & 7;
9266 modrm.rm = *codep & 7;
9269 case USE_VEX_LEN_TABLE:
9286 dp = &vex_len_table[dp->op[1].bytemode][index];
9289 case USE_VEX_C4_TABLE:
9290 FETCH_DATA (info, codep + 3);
9291 /* All bits in the REX prefix are ignored. */
9293 rex = ~(*codep >> 5) & 0x7;
9294 switch ((*codep & 0x1f))
9299 vex_table_index = 0;
9302 vex_table_index = 1;
9305 vex_table_index = 2;
9309 vex.w = *codep & 0x80;
9310 if (vex.w && address_mode == mode_64bit)
9313 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9314 if (address_mode != mode_64bit
9315 && vex.register_specifier > 0x7)
9318 vex.length = (*codep & 0x4) ? 256 : 128;
9319 switch ((*codep & 0x3))
9325 vex.prefix = DATA_PREFIX_OPCODE;
9328 vex.prefix = REPE_PREFIX_OPCODE;
9331 vex.prefix = REPNE_PREFIX_OPCODE;
9338 dp = &vex_table[vex_table_index][index];
9339 /* There is no MODRM byte for VEX [82|77]. */
9340 if (index != 0x77 && index != 0x82)
9342 FETCH_DATA (info, codep + 1);
9343 modrm.mod = (*codep >> 6) & 3;
9344 modrm.reg = (*codep >> 3) & 7;
9345 modrm.rm = *codep & 7;
9349 case USE_VEX_C5_TABLE:
9350 FETCH_DATA (info, codep + 2);
9351 /* All bits in the REX prefix are ignored. */
9353 rex = (*codep & 0x80) ? 0 : REX_R;
9355 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9356 if (address_mode != mode_64bit
9357 && vex.register_specifier > 0x7)
9360 vex.length = (*codep & 0x4) ? 256 : 128;
9361 switch ((*codep & 0x3))
9367 vex.prefix = DATA_PREFIX_OPCODE;
9370 vex.prefix = REPE_PREFIX_OPCODE;
9373 vex.prefix = REPNE_PREFIX_OPCODE;
9380 dp = &vex_table[dp->op[1].bytemode][index];
9381 /* There is no MODRM byte for VEX [82|77]. */
9382 if (index != 0x77 && index != 0x82)
9384 FETCH_DATA (info, codep + 1);
9385 modrm.mod = (*codep >> 6) & 3;
9386 modrm.reg = (*codep >> 3) & 7;
9387 modrm.rm = *codep & 7;
9395 if (dp->name != NULL)
9398 return get_valid_dis386 (dp, info);
9402 print_insn (bfd_vma pc, disassemble_info *info)
9404 const struct dis386 *dp;
9406 char *op_txt[MAX_OPERANDS];
9410 struct dis_private priv;
9412 char prefix_obuf[32];
9415 if (info->mach == bfd_mach_x86_64_intel_syntax
9416 || info->mach == bfd_mach_x86_64
9417 || info->mach == bfd_mach_l1om
9418 || info->mach == bfd_mach_l1om_intel_syntax)
9419 address_mode = mode_64bit;
9421 address_mode = mode_32bit;
9423 if (intel_syntax == (char) -1)
9424 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
9425 || info->mach == bfd_mach_x86_64_intel_syntax
9426 || info->mach == bfd_mach_l1om_intel_syntax);
9428 if (info->mach == bfd_mach_i386_i386
9429 || info->mach == bfd_mach_x86_64
9430 || info->mach == bfd_mach_l1om
9431 || info->mach == bfd_mach_i386_i386_intel_syntax
9432 || info->mach == bfd_mach_x86_64_intel_syntax
9433 || info->mach == bfd_mach_l1om_intel_syntax)
9434 priv.orig_sizeflag = AFLAG | DFLAG;
9435 else if (info->mach == bfd_mach_i386_i8086)
9436 priv.orig_sizeflag = 0;
9440 for (p = info->disassembler_options; p != NULL; )
9442 if (CONST_STRNEQ (p, "x86-64"))
9444 address_mode = mode_64bit;
9445 priv.orig_sizeflag = AFLAG | DFLAG;
9447 else if (CONST_STRNEQ (p, "i386"))
9449 address_mode = mode_32bit;
9450 priv.orig_sizeflag = AFLAG | DFLAG;
9452 else if (CONST_STRNEQ (p, "i8086"))
9454 address_mode = mode_16bit;
9455 priv.orig_sizeflag = 0;
9457 else if (CONST_STRNEQ (p, "intel"))
9460 if (CONST_STRNEQ (p + 5, "-mnemonic"))
9463 else if (CONST_STRNEQ (p, "att"))
9466 if (CONST_STRNEQ (p + 3, "-mnemonic"))
9469 else if (CONST_STRNEQ (p, "addr"))
9471 if (address_mode == mode_64bit)
9473 if (p[4] == '3' && p[5] == '2')
9474 priv.orig_sizeflag &= ~AFLAG;
9475 else if (p[4] == '6' && p[5] == '4')
9476 priv.orig_sizeflag |= AFLAG;
9480 if (p[4] == '1' && p[5] == '6')
9481 priv.orig_sizeflag &= ~AFLAG;
9482 else if (p[4] == '3' && p[5] == '2')
9483 priv.orig_sizeflag |= AFLAG;
9486 else if (CONST_STRNEQ (p, "data"))
9488 if (p[4] == '1' && p[5] == '6')
9489 priv.orig_sizeflag &= ~DFLAG;
9490 else if (p[4] == '3' && p[5] == '2')
9491 priv.orig_sizeflag |= DFLAG;
9493 else if (CONST_STRNEQ (p, "suffix"))
9494 priv.orig_sizeflag |= SUFFIX_ALWAYS;
9496 p = strchr (p, ',');
9503 names64 = intel_names64;
9504 names32 = intel_names32;
9505 names16 = intel_names16;
9506 names8 = intel_names8;
9507 names8rex = intel_names8rex;
9508 names_seg = intel_names_seg;
9509 index64 = intel_index64;
9510 index32 = intel_index32;
9511 index16 = intel_index16;
9514 separator_char = '+';
9519 names64 = att_names64;
9520 names32 = att_names32;
9521 names16 = att_names16;
9522 names8 = att_names8;
9523 names8rex = att_names8rex;
9524 names_seg = att_names_seg;
9525 index64 = att_index64;
9526 index32 = att_index32;
9527 index16 = att_index16;
9530 separator_char = ',';
9534 /* The output looks better if we put 7 bytes on a line, since that
9535 puts most long word instructions on a single line. Use 8 bytes
9537 if (info->mach == bfd_mach_l1om
9538 || info->mach == bfd_mach_l1om_intel_syntax)
9539 info->bytes_per_line = 8;
9541 info->bytes_per_line = 7;
9543 info->private_data = &priv;
9544 priv.max_fetched = priv.the_buffer;
9545 priv.insn_start = pc;
9548 for (i = 0; i < MAX_OPERANDS; ++i)
9556 start_codep = priv.the_buffer;
9557 codep = priv.the_buffer;
9559 if (setjmp (priv.bailout) != 0)
9563 /* Getting here means we tried for data but didn't get it. That
9564 means we have an incomplete instruction of some sort. Just
9565 print the first byte as a prefix or a .byte pseudo-op. */
9566 if (codep > priv.the_buffer)
9568 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9570 (*info->fprintf_func) (info->stream, "%s", name);
9573 /* Just print the first byte as a .byte instruction. */
9574 (*info->fprintf_func) (info->stream, ".byte 0x%x",
9575 (unsigned int) priv.the_buffer[0]);
9588 sizeflag = priv.orig_sizeflag;
9590 FETCH_DATA (info, codep + 1);
9591 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
9593 if (((prefixes & PREFIX_FWAIT)
9594 && ((*codep < 0xd8) || (*codep > 0xdf)))
9595 || (rex && rex_used))
9599 /* fwait not followed by floating point instruction, or rex followed
9600 by other prefixes. Print the first prefix. */
9601 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9603 name = INTERNAL_DISASSEMBLER_ERROR;
9604 (*info->fprintf_func) (info->stream, "%s", name);
9612 unsigned char threebyte;
9613 FETCH_DATA (info, codep + 2);
9614 threebyte = *++codep;
9615 dp = &dis386_twobyte[threebyte];
9616 need_modrm = twobyte_has_modrm[*codep];
9621 dp = &dis386[*codep];
9622 need_modrm = onebyte_has_modrm[*codep];
9626 if ((prefixes & PREFIX_REPZ))
9628 repz_prefix = "repz ";
9629 used_prefixes |= PREFIX_REPZ;
9634 if ((prefixes & PREFIX_REPNZ))
9636 repnz_prefix = "repnz ";
9637 used_prefixes |= PREFIX_REPNZ;
9640 repnz_prefix = NULL;
9642 if ((prefixes & PREFIX_LOCK))
9644 lock_prefix = "lock ";
9645 used_prefixes |= PREFIX_LOCK;
9651 if (prefixes & PREFIX_ADDR)
9654 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
9656 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
9657 addr_prefix = "addr32 ";
9659 addr_prefix = "addr16 ";
9660 used_prefixes |= PREFIX_ADDR;
9665 if ((prefixes & PREFIX_DATA))
9668 if (dp->op[2].bytemode == cond_jump_mode
9669 && dp->op[0].bytemode == v_mode
9672 if (sizeflag & DFLAG)
9673 data_prefix = "data32 ";
9675 data_prefix = "data16 ";
9676 used_prefixes |= PREFIX_DATA;
9682 FETCH_DATA (info, codep + 1);
9683 modrm.mod = (*codep >> 6) & 3;
9684 modrm.reg = (*codep >> 3) & 7;
9685 modrm.rm = *codep & 7;
9692 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9698 dp = get_valid_dis386 (dp, info);
9699 if (dp != NULL && putop (dp->name, sizeflag) == 0)
9701 for (i = 0; i < MAX_OPERANDS; ++i)
9704 op_ad = MAX_OPERANDS - 1 - i;
9706 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
9711 /* See if any prefixes were not used. If so, print the first one
9712 separately. If we don't do this, we'll wind up printing an
9713 instruction stream which does not precisely correspond to the
9714 bytes we are disassembling. */
9715 if ((prefixes & ~used_prefixes) != 0)
9719 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9721 name = INTERNAL_DISASSEMBLER_ERROR;
9722 (*info->fprintf_func) (info->stream, "%s", name);
9725 if ((rex_original & ~rex_used) || rex_ignored)
9728 name = prefix_name (rex_original, priv.orig_sizeflag);
9730 name = INTERNAL_DISASSEMBLER_ERROR;
9731 (*info->fprintf_func) (info->stream, "%s ", name);
9735 prefix_obufp = prefix_obuf;
9737 prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
9739 prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
9741 prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
9743 prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
9745 prefix_obufp = stpcpy (prefix_obufp, data_prefix);
9747 if (prefix_obuf[0] != 0)
9748 (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
9750 obufp = mnemonicendp;
9751 for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
9754 (*info->fprintf_func) (info->stream, "%s", obuf);
9756 /* The enter and bound instructions are printed with operands in the same
9757 order as the intel book; everything else is printed in reverse order. */
9758 if (intel_syntax || two_source_ops)
9762 for (i = 0; i < MAX_OPERANDS; ++i)
9763 op_txt[i] = op_out[i];
9765 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9767 op_ad = op_index[i];
9768 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
9769 op_index[MAX_OPERANDS - 1 - i] = op_ad;
9770 riprel = op_riprel[i];
9771 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
9772 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9777 for (i = 0; i < MAX_OPERANDS; ++i)
9778 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
9782 for (i = 0; i < MAX_OPERANDS; ++i)
9786 (*info->fprintf_func) (info->stream, ",");
9787 if (op_index[i] != -1 && !op_riprel[i])
9788 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
9790 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
9794 for (i = 0; i < MAX_OPERANDS; i++)
9795 if (op_index[i] != -1 && op_riprel[i])
9797 (*info->fprintf_func) (info->stream, " # ");
9798 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
9799 + op_address[op_index[i]]), info);
9802 return codep - priv.the_buffer;
9805 static const char *float_mem[] = {
9880 static const unsigned char float_mem_mode[] = {
9955 #define ST { OP_ST, 0 }
9956 #define STi { OP_STi, 0 }
9958 #define FGRPd9_2 NULL, { { NULL, 0 } }
9959 #define FGRPd9_4 NULL, { { NULL, 1 } }
9960 #define FGRPd9_5 NULL, { { NULL, 2 } }
9961 #define FGRPd9_6 NULL, { { NULL, 3 } }
9962 #define FGRPd9_7 NULL, { { NULL, 4 } }
9963 #define FGRPda_5 NULL, { { NULL, 5 } }
9964 #define FGRPdb_4 NULL, { { NULL, 6 } }
9965 #define FGRPde_3 NULL, { { NULL, 7 } }
9966 #define FGRPdf_4 NULL, { { NULL, 8 } }
9968 static const struct dis386 float_reg[][8] = {
9971 { "fadd", { ST, STi } },
9972 { "fmul", { ST, STi } },
9973 { "fcom", { STi } },
9974 { "fcomp", { STi } },
9975 { "fsub", { ST, STi } },
9976 { "fsubr", { ST, STi } },
9977 { "fdiv", { ST, STi } },
9978 { "fdivr", { ST, STi } },
9983 { "fxch", { STi } },
9985 { "(bad)", { XX } },
9993 { "fcmovb", { ST, STi } },
9994 { "fcmove", { ST, STi } },
9995 { "fcmovbe",{ ST, STi } },
9996 { "fcmovu", { ST, STi } },
9997 { "(bad)", { XX } },
9999 { "(bad)", { XX } },
10000 { "(bad)", { XX } },
10004 { "fcmovnb",{ ST, STi } },
10005 { "fcmovne",{ ST, STi } },
10006 { "fcmovnbe",{ ST, STi } },
10007 { "fcmovnu",{ ST, STi } },
10009 { "fucomi", { ST, STi } },
10010 { "fcomi", { ST, STi } },
10011 { "(bad)", { XX } },
10015 { "fadd", { STi, ST } },
10016 { "fmul", { STi, ST } },
10017 { "(bad)", { XX } },
10018 { "(bad)", { XX } },
10019 { "fsub!M", { STi, ST } },
10020 { "fsubM", { STi, ST } },
10021 { "fdiv!M", { STi, ST } },
10022 { "fdivM", { STi, ST } },
10026 { "ffree", { STi } },
10027 { "(bad)", { XX } },
10028 { "fst", { STi } },
10029 { "fstp", { STi } },
10030 { "fucom", { STi } },
10031 { "fucomp", { STi } },
10032 { "(bad)", { XX } },
10033 { "(bad)", { XX } },
10037 { "faddp", { STi, ST } },
10038 { "fmulp", { STi, ST } },
10039 { "(bad)", { XX } },
10041 { "fsub!Mp", { STi, ST } },
10042 { "fsubMp", { STi, ST } },
10043 { "fdiv!Mp", { STi, ST } },
10044 { "fdivMp", { STi, ST } },
10048 { "ffreep", { STi } },
10049 { "(bad)", { XX } },
10050 { "(bad)", { XX } },
10051 { "(bad)", { XX } },
10053 { "fucomip", { ST, STi } },
10054 { "fcomip", { ST, STi } },
10055 { "(bad)", { XX } },
10059 static char *fgrps[][8] = {
10062 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10067 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10072 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10077 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10082 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10087 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10092 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10093 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10098 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10103 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10108 swap_operand (void)
10110 mnemonicendp[0] = '.';
10111 mnemonicendp[1] = 's';
10116 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10117 int sizeflag ATTRIBUTE_UNUSED)
10119 /* Skip mod/rm byte. */
10125 dofloat (int sizeflag)
10127 const struct dis386 *dp;
10128 unsigned char floatop;
10130 floatop = codep[-1];
10132 if (modrm.mod != 3)
10134 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10136 putop (float_mem[fp_indx], sizeflag);
10139 OP_E (float_mem_mode[fp_indx], sizeflag);
10142 /* Skip mod/rm byte. */
10146 dp = &float_reg[floatop - 0xd8][modrm.reg];
10147 if (dp->name == NULL)
10149 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10151 /* Instruction fnstsw is only one with strange arg. */
10152 if (floatop == 0xdf && codep[-1] == 0xe0)
10153 strcpy (op_out[0], names16[0]);
10157 putop (dp->name, sizeflag);
10162 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10167 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10172 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10174 oappend ("%st" + intel_syntax);
10178 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10180 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10181 oappend (scratchbuf + intel_syntax);
10184 /* Capital letters in template are macros. */
10186 putop (const char *in_template, int sizeflag)
10191 unsigned int l = 0, len = 1;
10194 #define SAVE_LAST(c) \
10195 if (l < len && l < sizeof (last)) \
10200 for (p = in_template; *p; p++)
10217 while (*++p != '|')
10218 if (*p == '}' || *p == '\0')
10221 /* Fall through. */
10226 while (*++p != '}')
10237 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10243 if (sizeflag & SUFFIX_ALWAYS)
10247 if (intel_syntax && !alt)
10249 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10251 if (sizeflag & DFLAG)
10252 *obufp++ = intel_syntax ? 'd' : 'l';
10254 *obufp++ = intel_syntax ? 'w' : 's';
10255 used_prefixes |= (prefixes & PREFIX_DATA);
10259 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10262 if (modrm.mod == 3)
10266 else if (sizeflag & DFLAG)
10267 *obufp++ = intel_syntax ? 'd' : 'l';
10270 used_prefixes |= (prefixes & PREFIX_DATA);
10275 case 'E': /* For jcxz/jecxz */
10276 if (address_mode == mode_64bit)
10278 if (sizeflag & AFLAG)
10284 if (sizeflag & AFLAG)
10286 used_prefixes |= (prefixes & PREFIX_ADDR);
10291 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10293 if (sizeflag & AFLAG)
10294 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10296 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10297 used_prefixes |= (prefixes & PREFIX_ADDR);
10301 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10303 if ((rex & REX_W) || (sizeflag & DFLAG))
10307 if (!(rex & REX_W))
10308 used_prefixes |= (prefixes & PREFIX_DATA);
10313 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10314 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10316 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10319 if (prefixes & PREFIX_DS)
10340 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
10345 /* Fall through. */
10348 if (l != 0 || len != 1)
10356 if (sizeflag & SUFFIX_ALWAYS)
10360 if (intel_mnemonic != cond)
10364 if ((prefixes & PREFIX_FWAIT) == 0)
10367 used_prefixes |= PREFIX_FWAIT;
10373 else if (intel_syntax && (sizeflag & DFLAG))
10377 if (!(rex & REX_W))
10378 used_prefixes |= (prefixes & PREFIX_DATA);
10383 if (address_mode == mode_64bit && (sizeflag & DFLAG))
10388 /* Fall through. */
10392 if ((prefixes & PREFIX_DATA)
10394 || (sizeflag & SUFFIX_ALWAYS))
10401 if (sizeflag & DFLAG)
10406 used_prefixes |= (prefixes & PREFIX_DATA);
10412 if (address_mode == mode_64bit && (sizeflag & DFLAG))
10414 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10418 /* Fall through. */
10421 if (l == 0 && len == 1)
10424 if (intel_syntax && !alt)
10427 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10433 if (sizeflag & DFLAG)
10434 *obufp++ = intel_syntax ? 'd' : 'l';
10438 used_prefixes |= (prefixes & PREFIX_DATA);
10443 if (l != 1 || len != 2 || last[0] != 'L')
10449 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
10464 else if (sizeflag & DFLAG)
10473 if (intel_syntax && !p[1]
10474 && ((rex & REX_W) || (sizeflag & DFLAG)))
10476 if (!(rex & REX_W))
10477 used_prefixes |= (prefixes & PREFIX_DATA);
10482 if (address_mode == mode_64bit && (sizeflag & DFLAG))
10484 if (sizeflag & SUFFIX_ALWAYS)
10488 /* Fall through. */
10492 if (sizeflag & SUFFIX_ALWAYS)
10498 if (sizeflag & DFLAG)
10502 used_prefixes |= (prefixes & PREFIX_DATA);
10507 if (l != 0 || len != 1)
10512 if (need_vex && vex.prefix)
10514 if (vex.prefix == DATA_PREFIX_OPCODE)
10519 else if (prefixes & PREFIX_DATA)
10523 used_prefixes |= (prefixes & PREFIX_DATA);
10526 if (l == 0 && len == 1)
10528 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10539 if (l != 1 || len != 2 || last[0] != 'X')
10547 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
10549 switch (vex.length)
10563 if (l == 0 && len == 1)
10565 /* operand size flag for cwtl, cbtw */
10574 else if (sizeflag & DFLAG)
10578 if (!(rex & REX_W))
10579 used_prefixes |= (prefixes & PREFIX_DATA);
10583 if (l != 1 || len != 2 || last[0] != 'X')
10590 *obufp++ = vex.w ? 'd': 's';
10597 mnemonicendp = obufp;
10602 oappend (const char *s)
10604 obufp = stpcpy (obufp, s);
10610 if (prefixes & PREFIX_CS)
10612 used_prefixes |= PREFIX_CS;
10613 oappend ("%cs:" + intel_syntax);
10615 if (prefixes & PREFIX_DS)
10617 used_prefixes |= PREFIX_DS;
10618 oappend ("%ds:" + intel_syntax);
10620 if (prefixes & PREFIX_SS)
10622 used_prefixes |= PREFIX_SS;
10623 oappend ("%ss:" + intel_syntax);
10625 if (prefixes & PREFIX_ES)
10627 used_prefixes |= PREFIX_ES;
10628 oappend ("%es:" + intel_syntax);
10630 if (prefixes & PREFIX_FS)
10632 used_prefixes |= PREFIX_FS;
10633 oappend ("%fs:" + intel_syntax);
10635 if (prefixes & PREFIX_GS)
10637 used_prefixes |= PREFIX_GS;
10638 oappend ("%gs:" + intel_syntax);
10643 OP_indirE (int bytemode, int sizeflag)
10647 OP_E (bytemode, sizeflag);
10651 print_operand_value (char *buf, int hex, bfd_vma disp)
10653 if (address_mode == mode_64bit)
10661 sprintf_vma (tmp, disp);
10662 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
10663 strcpy (buf + 2, tmp + i);
10667 bfd_signed_vma v = disp;
10674 /* Check for possible overflow on 0x8000000000000000. */
10677 strcpy (buf, "9223372036854775808");
10691 tmp[28 - i] = (v % 10) + '0';
10695 strcpy (buf, tmp + 29 - i);
10701 sprintf (buf, "0x%x", (unsigned int) disp);
10703 sprintf (buf, "%d", (int) disp);
10707 /* Put DISP in BUF as signed hex number. */
10710 print_displacement (char *buf, bfd_vma disp)
10712 bfd_signed_vma val = disp;
10721 /* Check for possible overflow. */
10724 switch (address_mode)
10727 strcpy (buf + j, "0x8000000000000000");
10730 strcpy (buf + j, "0x80000000");
10733 strcpy (buf + j, "0x8000");
10743 sprintf_vma (tmp, (bfd_vma) val);
10744 for (i = 0; tmp[i] == '0'; i++)
10746 if (tmp[i] == '\0')
10748 strcpy (buf + j, tmp + i);
10752 intel_operand_size (int bytemode, int sizeflag)
10759 oappend ("BYTE PTR ");
10763 oappend ("WORD PTR ");
10766 if (address_mode == mode_64bit && (sizeflag & DFLAG))
10768 oappend ("QWORD PTR ");
10769 used_prefixes |= (prefixes & PREFIX_DATA);
10778 oappend ("QWORD PTR ");
10779 else if ((sizeflag & DFLAG) || bytemode == dq_mode)
10780 oappend ("DWORD PTR ");
10782 oappend ("WORD PTR ");
10783 used_prefixes |= (prefixes & PREFIX_DATA);
10786 if ((rex & REX_W) || (sizeflag & DFLAG))
10788 oappend ("WORD PTR ");
10789 if (!(rex & REX_W))
10790 used_prefixes |= (prefixes & PREFIX_DATA);
10793 if (sizeflag & DFLAG)
10794 oappend ("QWORD PTR ");
10796 oappend ("DWORD PTR ");
10797 used_prefixes |= (prefixes & PREFIX_DATA);
10802 oappend ("DWORD PTR ");
10806 oappend ("QWORD PTR ");
10809 if (address_mode == mode_64bit)
10810 oappend ("QWORD PTR ");
10812 oappend ("DWORD PTR ");
10815 if (sizeflag & DFLAG)
10816 oappend ("FWORD PTR ");
10818 oappend ("DWORD PTR ");
10819 used_prefixes |= (prefixes & PREFIX_DATA);
10822 oappend ("TBYTE PTR ");
10828 switch (vex.length)
10831 oappend ("XMMWORD PTR ");
10834 oappend ("YMMWORD PTR ");
10841 oappend ("XMMWORD PTR ");
10844 oappend ("XMMWORD PTR ");
10850 switch (vex.length)
10853 oappend ("QWORD PTR ");
10856 oappend ("XMMWORD PTR ");
10866 switch (vex.length)
10869 oappend ("QWORD PTR ");
10872 oappend ("YMMWORD PTR ");
10879 oappend ("OWORD PTR ");
10881 case vex_w_dq_mode:
10886 oappend ("QWORD PTR ");
10888 oappend ("DWORD PTR ");
10896 OP_E_register (int bytemode, int sizeflag)
10898 int reg = modrm.rm;
10899 const char **names;
10905 if ((sizeflag & SUFFIX_ALWAYS)
10906 && (bytemode == b_swap_mode || bytemode == v_swap_mode))
10929 names = address_mode == mode_64bit ? names64 : names32;
10932 if (address_mode == mode_64bit && (sizeflag & DFLAG))
10935 used_prefixes |= (prefixes & PREFIX_DATA);
10949 else if ((sizeflag & DFLAG)
10950 || (bytemode != v_mode
10951 && bytemode != v_swap_mode))
10955 used_prefixes |= (prefixes & PREFIX_DATA);
10960 oappend (INTERNAL_DISASSEMBLER_ERROR);
10963 oappend (names[reg]);
10967 OP_E_memory (int bytemode, int sizeflag)
10970 int add = (rex & REX_B) ? 8 : 0;
10975 intel_operand_size (bytemode, sizeflag);
10978 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
10980 /* 32/64 bit address mode */
10998 FETCH_DATA (the_info, codep + 1);
10999 index = (*codep >> 3) & 7;
11000 scale = (*codep >> 6) & 3;
11005 haveindex = index != 4;
11008 rbase = base + add;
11016 if (address_mode == mode_64bit && !havesib)
11022 FETCH_DATA (the_info, codep + 1);
11024 if ((disp & 0x80) != 0)
11032 /* In 32bit mode, we need index register to tell [offset] from
11033 [eiz*1 + offset]. */
11034 needindex = (havesib
11037 && address_mode == mode_32bit);
11038 havedisp = (havebase
11040 || (havesib && (haveindex || scale != 0)));
11043 if (modrm.mod != 0 || base == 5)
11045 if (havedisp || riprel)
11046 print_displacement (scratchbuf, disp);
11048 print_operand_value (scratchbuf, 1, disp);
11049 oappend (scratchbuf);
11053 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
11057 if (havebase || haveindex || riprel)
11058 used_prefixes |= PREFIX_ADDR;
11060 if (havedisp || (intel_syntax && riprel))
11062 *obufp++ = open_char;
11063 if (intel_syntax && riprel)
11066 oappend (sizeflag & AFLAG ? "rip" : "eip");
11070 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
11071 ? names64[rbase] : names32[rbase]);
11074 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11075 print index to tell base + index from base. */
11079 || (havebase && base != ESP_REG_NUM))
11081 if (!intel_syntax || havebase)
11083 *obufp++ = separator_char;
11087 oappend (address_mode == mode_64bit
11088 && (sizeflag & AFLAG)
11089 ? names64[index] : names32[index]);
11091 oappend (address_mode == mode_64bit
11092 && (sizeflag & AFLAG)
11093 ? index64 : index32);
11095 *obufp++ = scale_char;
11097 sprintf (scratchbuf, "%d", 1 << scale);
11098 oappend (scratchbuf);
11102 && (disp || modrm.mod != 0 || base == 5))
11104 if (!havedisp || (bfd_signed_vma) disp >= 0)
11109 else if (modrm.mod != 1 && disp != -disp)
11113 disp = - (bfd_signed_vma) disp;
11117 print_displacement (scratchbuf, disp);
11119 print_operand_value (scratchbuf, 1, disp);
11120 oappend (scratchbuf);
11123 *obufp++ = close_char;
11126 else if (intel_syntax)
11128 if (modrm.mod != 0 || base == 5)
11130 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11131 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11135 oappend (names_seg[ds_reg - es_reg]);
11138 print_operand_value (scratchbuf, 1, disp);
11139 oappend (scratchbuf);
11144 { /* 16 bit address mode */
11151 if ((disp & 0x8000) != 0)
11156 FETCH_DATA (the_info, codep + 1);
11158 if ((disp & 0x80) != 0)
11163 if ((disp & 0x8000) != 0)
11169 if (modrm.mod != 0 || modrm.rm == 6)
11171 print_displacement (scratchbuf, disp);
11172 oappend (scratchbuf);
11175 if (modrm.mod != 0 || modrm.rm != 6)
11177 *obufp++ = open_char;
11179 oappend (index16[modrm.rm]);
11181 && (disp || modrm.mod != 0 || modrm.rm == 6))
11183 if ((bfd_signed_vma) disp >= 0)
11188 else if (modrm.mod != 1)
11192 disp = - (bfd_signed_vma) disp;
11195 print_displacement (scratchbuf, disp);
11196 oappend (scratchbuf);
11199 *obufp++ = close_char;
11202 else if (intel_syntax)
11204 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11205 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11209 oappend (names_seg[ds_reg - es_reg]);
11212 print_operand_value (scratchbuf, 1, disp & 0xffff);
11213 oappend (scratchbuf);
11219 OP_E_extended (int bytemode, int sizeflag)
11221 /* Skip mod/rm byte. */
11225 if (modrm.mod == 3)
11226 OP_E_register (bytemode, sizeflag);
11228 OP_E_memory (bytemode, sizeflag);
11232 OP_E (int bytemode, int sizeflag)
11234 OP_E_extended (bytemode, sizeflag);
11239 OP_G (int bytemode, int sizeflag)
11250 oappend (names8rex[modrm.reg + add]);
11252 oappend (names8[modrm.reg + add]);
11255 oappend (names16[modrm.reg + add]);
11258 oappend (names32[modrm.reg + add]);
11261 oappend (names64[modrm.reg + add]);
11270 oappend (names64[modrm.reg + add]);
11271 else if ((sizeflag & DFLAG) || bytemode != v_mode)
11272 oappend (names32[modrm.reg + add]);
11274 oappend (names16[modrm.reg + add]);
11275 used_prefixes |= (prefixes & PREFIX_DATA);
11278 if (address_mode == mode_64bit)
11279 oappend (names64[modrm.reg + add]);
11281 oappend (names32[modrm.reg + add]);
11284 oappend (INTERNAL_DISASSEMBLER_ERROR);
11297 FETCH_DATA (the_info, codep + 8);
11298 a = *codep++ & 0xff;
11299 a |= (*codep++ & 0xff) << 8;
11300 a |= (*codep++ & 0xff) << 16;
11301 a |= (*codep++ & 0xff) << 24;
11302 b = *codep++ & 0xff;
11303 b |= (*codep++ & 0xff) << 8;
11304 b |= (*codep++ & 0xff) << 16;
11305 b |= (*codep++ & 0xff) << 24;
11306 x = a + ((bfd_vma) b << 32);
11314 static bfd_signed_vma
11317 bfd_signed_vma x = 0;
11319 FETCH_DATA (the_info, codep + 4);
11320 x = *codep++ & (bfd_signed_vma) 0xff;
11321 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11322 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11323 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11327 static bfd_signed_vma
11330 bfd_signed_vma x = 0;
11332 FETCH_DATA (the_info, codep + 4);
11333 x = *codep++ & (bfd_signed_vma) 0xff;
11334 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11335 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11336 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11338 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
11348 FETCH_DATA (the_info, codep + 2);
11349 x = *codep++ & 0xff;
11350 x |= (*codep++ & 0xff) << 8;
11355 set_op (bfd_vma op, int riprel)
11357 op_index[op_ad] = op_ad;
11358 if (address_mode == mode_64bit)
11360 op_address[op_ad] = op;
11361 op_riprel[op_ad] = riprel;
11365 /* Mask to get a 32-bit address. */
11366 op_address[op_ad] = op & 0xffffffff;
11367 op_riprel[op_ad] = riprel & 0xffffffff;
11372 OP_REG (int code, int sizeflag)
11384 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
11385 case sp_reg: case bp_reg: case si_reg: case di_reg:
11386 s = names16[code - ax_reg + add];
11388 case es_reg: case ss_reg: case cs_reg:
11389 case ds_reg: case fs_reg: case gs_reg:
11390 s = names_seg[code - es_reg + add];
11392 case al_reg: case ah_reg: case cl_reg: case ch_reg:
11393 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
11396 s = names8rex[code - al_reg + add];
11398 s = names8[code - al_reg];
11400 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
11401 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
11402 if (address_mode == mode_64bit && (sizeflag & DFLAG))
11404 s = names64[code - rAX_reg + add];
11407 code += eAX_reg - rAX_reg;
11408 /* Fall through. */
11409 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
11410 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
11413 s = names64[code - eAX_reg + add];
11414 else if (sizeflag & DFLAG)
11415 s = names32[code - eAX_reg + add];
11417 s = names16[code - eAX_reg + add];
11418 used_prefixes |= (prefixes & PREFIX_DATA);
11421 s = INTERNAL_DISASSEMBLER_ERROR;
11428 OP_IMREG (int code, int sizeflag)
11440 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
11441 case sp_reg: case bp_reg: case si_reg: case di_reg:
11442 s = names16[code - ax_reg];
11444 case es_reg: case ss_reg: case cs_reg:
11445 case ds_reg: case fs_reg: case gs_reg:
11446 s = names_seg[code - es_reg];
11448 case al_reg: case ah_reg: case cl_reg: case ch_reg:
11449 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
11452 s = names8rex[code - al_reg];
11454 s = names8[code - al_reg];
11456 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
11457 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
11460 s = names64[code - eAX_reg];
11461 else if (sizeflag & DFLAG)
11462 s = names32[code - eAX_reg];
11464 s = names16[code - eAX_reg];
11465 used_prefixes |= (prefixes & PREFIX_DATA);
11467 case z_mode_ax_reg:
11468 if ((rex & REX_W) || (sizeflag & DFLAG))
11472 if (!(rex & REX_W))
11473 used_prefixes |= (prefixes & PREFIX_DATA);
11476 s = INTERNAL_DISASSEMBLER_ERROR;
11483 OP_I (int bytemode, int sizeflag)
11486 bfd_signed_vma mask = -1;
11491 FETCH_DATA (the_info, codep + 1);
11496 if (address_mode == mode_64bit)
11501 /* Fall through. */
11506 else if (sizeflag & DFLAG)
11516 used_prefixes |= (prefixes & PREFIX_DATA);
11527 oappend (INTERNAL_DISASSEMBLER_ERROR);
11532 scratchbuf[0] = '$';
11533 print_operand_value (scratchbuf + 1, 1, op);
11534 oappend (scratchbuf + intel_syntax);
11535 scratchbuf[0] = '\0';
11539 OP_I64 (int bytemode, int sizeflag)
11542 bfd_signed_vma mask = -1;
11544 if (address_mode != mode_64bit)
11546 OP_I (bytemode, sizeflag);
11553 FETCH_DATA (the_info, codep + 1);
11561 else if (sizeflag & DFLAG)
11571 used_prefixes |= (prefixes & PREFIX_DATA);
11578 oappend (INTERNAL_DISASSEMBLER_ERROR);
11583 scratchbuf[0] = '$';
11584 print_operand_value (scratchbuf + 1, 1, op);
11585 oappend (scratchbuf + intel_syntax);
11586 scratchbuf[0] = '\0';
11590 OP_sI (int bytemode, int sizeflag)
11593 bfd_signed_vma mask = -1;
11598 FETCH_DATA (the_info, codep + 1);
11600 if ((op & 0x80) != 0)
11608 else if (sizeflag & DFLAG)
11617 if ((op & 0x8000) != 0)
11620 used_prefixes |= (prefixes & PREFIX_DATA);
11625 if ((op & 0x8000) != 0)
11629 oappend (INTERNAL_DISASSEMBLER_ERROR);
11633 scratchbuf[0] = '$';
11634 print_operand_value (scratchbuf + 1, 1, op);
11635 oappend (scratchbuf + intel_syntax);
11639 OP_J (int bytemode, int sizeflag)
11643 bfd_vma segment = 0;
11648 FETCH_DATA (the_info, codep + 1);
11650 if ((disp & 0x80) != 0)
11654 if ((sizeflag & DFLAG) || (rex & REX_W))
11659 if ((disp & 0x8000) != 0)
11661 /* In 16bit mode, address is wrapped around at 64k within
11662 the same segment. Otherwise, a data16 prefix on a jump
11663 instruction means that the pc is masked to 16 bits after
11664 the displacement is added! */
11666 if ((prefixes & PREFIX_DATA) == 0)
11667 segment = ((start_pc + codep - start_codep)
11668 & ~((bfd_vma) 0xffff));
11670 used_prefixes |= (prefixes & PREFIX_DATA);
11673 oappend (INTERNAL_DISASSEMBLER_ERROR);
11676 disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
11678 print_operand_value (scratchbuf, 1, disp);
11679 oappend (scratchbuf);
11683 OP_SEG (int bytemode, int sizeflag)
11685 if (bytemode == w_mode)
11686 oappend (names_seg[modrm.reg]);
11688 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
11692 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
11696 if (sizeflag & DFLAG)
11706 used_prefixes |= (prefixes & PREFIX_DATA);
11708 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
11710 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
11711 oappend (scratchbuf);
11715 OP_OFF (int bytemode, int sizeflag)
11719 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
11720 intel_operand_size (bytemode, sizeflag);
11723 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11730 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11731 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
11733 oappend (names_seg[ds_reg - es_reg]);
11737 print_operand_value (scratchbuf, 1, off);
11738 oappend (scratchbuf);
11742 OP_OFF64 (int bytemode, int sizeflag)
11746 if (address_mode != mode_64bit
11747 || (prefixes & PREFIX_ADDR))
11749 OP_OFF (bytemode, sizeflag);
11753 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
11754 intel_operand_size (bytemode, sizeflag);
11761 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11762 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
11764 oappend (names_seg[ds_reg - es_reg]);
11768 print_operand_value (scratchbuf, 1, off);
11769 oappend (scratchbuf);
11773 ptr_reg (int code, int sizeflag)
11777 *obufp++ = open_char;
11778 used_prefixes |= (prefixes & PREFIX_ADDR);
11779 if (address_mode == mode_64bit)
11781 if (!(sizeflag & AFLAG))
11782 s = names32[code - eAX_reg];
11784 s = names64[code - eAX_reg];
11786 else if (sizeflag & AFLAG)
11787 s = names32[code - eAX_reg];
11789 s = names16[code - eAX_reg];
11791 *obufp++ = close_char;
11796 OP_ESreg (int code, int sizeflag)
11802 case 0x6d: /* insw/insl */
11803 intel_operand_size (z_mode, sizeflag);
11805 case 0xa5: /* movsw/movsl/movsq */
11806 case 0xa7: /* cmpsw/cmpsl/cmpsq */
11807 case 0xab: /* stosw/stosl */
11808 case 0xaf: /* scasw/scasl */
11809 intel_operand_size (v_mode, sizeflag);
11812 intel_operand_size (b_mode, sizeflag);
11815 oappend ("%es:" + intel_syntax);
11816 ptr_reg (code, sizeflag);
11820 OP_DSreg (int code, int sizeflag)
11826 case 0x6f: /* outsw/outsl */
11827 intel_operand_size (z_mode, sizeflag);
11829 case 0xa5: /* movsw/movsl/movsq */
11830 case 0xa7: /* cmpsw/cmpsl/cmpsq */
11831 case 0xad: /* lodsw/lodsl/lodsq */
11832 intel_operand_size (v_mode, sizeflag);
11835 intel_operand_size (b_mode, sizeflag);
11844 | PREFIX_GS)) == 0)
11845 prefixes |= PREFIX_DS;
11847 ptr_reg (code, sizeflag);
11851 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11859 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
11861 lock_prefix = NULL;
11862 used_prefixes |= PREFIX_LOCK;
11867 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
11868 oappend (scratchbuf + intel_syntax);
11872 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11881 sprintf (scratchbuf, "db%d", modrm.reg + add);
11883 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
11884 oappend (scratchbuf);
11888 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11890 sprintf (scratchbuf, "%%tr%d", modrm.reg);
11891 oappend (scratchbuf + intel_syntax);
11895 OP_R (int bytemode, int sizeflag)
11897 if (modrm.mod == 3)
11898 OP_E (bytemode, sizeflag);
11904 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11906 used_prefixes |= (prefixes & PREFIX_DATA);
11907 if (prefixes & PREFIX_DATA)
11915 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
11918 sprintf (scratchbuf, "%%mm%d", modrm.reg);
11919 oappend (scratchbuf + intel_syntax);
11923 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
11931 if (need_vex && bytemode != xmm_mode)
11933 switch (vex.length)
11936 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
11939 sprintf (scratchbuf, "%%ymm%d", modrm.reg + add);
11946 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
11947 oappend (scratchbuf + intel_syntax);
11951 OP_EM (int bytemode, int sizeflag)
11953 if (modrm.mod != 3)
11956 && (bytemode == v_mode || bytemode == v_swap_mode))
11958 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
11959 used_prefixes |= (prefixes & PREFIX_DATA);
11961 OP_E (bytemode, sizeflag);
11965 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
11968 /* Skip mod/rm byte. */
11971 used_prefixes |= (prefixes & PREFIX_DATA);
11972 if (prefixes & PREFIX_DATA)
11981 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
11984 sprintf (scratchbuf, "%%mm%d", modrm.rm);
11985 oappend (scratchbuf + intel_syntax);
11988 /* cvt* are the only instructions in sse2 which have
11989 both SSE and MMX operands and also have 0x66 prefix
11990 in their opcode. 0x66 was originally used to differentiate
11991 between SSE and MMX instruction(operands). So we have to handle the
11992 cvt* separately using OP_EMC and OP_MXC */
11994 OP_EMC (int bytemode, int sizeflag)
11996 if (modrm.mod != 3)
11998 if (intel_syntax && bytemode == v_mode)
12000 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12001 used_prefixes |= (prefixes & PREFIX_DATA);
12003 OP_E (bytemode, sizeflag);
12007 /* Skip mod/rm byte. */
12010 used_prefixes |= (prefixes & PREFIX_DATA);
12011 sprintf (scratchbuf, "%%mm%d", modrm.rm);
12012 oappend (scratchbuf + intel_syntax);
12016 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12018 used_prefixes |= (prefixes & PREFIX_DATA);
12019 sprintf (scratchbuf, "%%mm%d", modrm.reg);
12020 oappend (scratchbuf + intel_syntax);
12024 OP_EX (int bytemode, int sizeflag)
12028 /* Skip mod/rm byte. */
12032 if (modrm.mod != 3)
12034 OP_E_memory (bytemode, sizeflag);
12044 if ((sizeflag & SUFFIX_ALWAYS)
12045 && (bytemode == x_swap_mode
12046 || bytemode == d_swap_mode
12047 || bytemode == q_swap_mode))
12051 && bytemode != xmm_mode
12052 && bytemode != xmmq_mode)
12054 switch (vex.length)
12057 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12060 sprintf (scratchbuf, "%%ymm%d", modrm.rm + add);
12067 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12068 oappend (scratchbuf + intel_syntax);
12072 OP_MS (int bytemode, int sizeflag)
12074 if (modrm.mod == 3)
12075 OP_EM (bytemode, sizeflag);
12081 OP_XS (int bytemode, int sizeflag)
12083 if (modrm.mod == 3)
12084 OP_EX (bytemode, sizeflag);
12090 OP_M (int bytemode, int sizeflag)
12092 if (modrm.mod == 3)
12093 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12096 OP_E (bytemode, sizeflag);
12100 OP_0f07 (int bytemode, int sizeflag)
12102 if (modrm.mod != 3 || modrm.rm != 0)
12105 OP_E (bytemode, sizeflag);
12108 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12109 32bit mode and "xchg %rax,%rax" in 64bit mode. */
12112 NOP_Fixup1 (int bytemode, int sizeflag)
12114 if ((prefixes & PREFIX_DATA) != 0
12117 && address_mode == mode_64bit))
12118 OP_REG (bytemode, sizeflag);
12120 strcpy (obuf, "nop");
12124 NOP_Fixup2 (int bytemode, int sizeflag)
12126 if ((prefixes & PREFIX_DATA) != 0
12129 && address_mode == mode_64bit))
12130 OP_IMREG (bytemode, sizeflag);
12133 static const char *const Suffix3DNow[] = {
12134 /* 00 */ NULL, NULL, NULL, NULL,
12135 /* 04 */ NULL, NULL, NULL, NULL,
12136 /* 08 */ NULL, NULL, NULL, NULL,
12137 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
12138 /* 10 */ NULL, NULL, NULL, NULL,
12139 /* 14 */ NULL, NULL, NULL, NULL,
12140 /* 18 */ NULL, NULL, NULL, NULL,
12141 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
12142 /* 20 */ NULL, NULL, NULL, NULL,
12143 /* 24 */ NULL, NULL, NULL, NULL,
12144 /* 28 */ NULL, NULL, NULL, NULL,
12145 /* 2C */ NULL, NULL, NULL, NULL,
12146 /* 30 */ NULL, NULL, NULL, NULL,
12147 /* 34 */ NULL, NULL, NULL, NULL,
12148 /* 38 */ NULL, NULL, NULL, NULL,
12149 /* 3C */ NULL, NULL, NULL, NULL,
12150 /* 40 */ NULL, NULL, NULL, NULL,
12151 /* 44 */ NULL, NULL, NULL, NULL,
12152 /* 48 */ NULL, NULL, NULL, NULL,
12153 /* 4C */ NULL, NULL, NULL, NULL,
12154 /* 50 */ NULL, NULL, NULL, NULL,
12155 /* 54 */ NULL, NULL, NULL, NULL,
12156 /* 58 */ NULL, NULL, NULL, NULL,
12157 /* 5C */ NULL, NULL, NULL, NULL,
12158 /* 60 */ NULL, NULL, NULL, NULL,
12159 /* 64 */ NULL, NULL, NULL, NULL,
12160 /* 68 */ NULL, NULL, NULL, NULL,
12161 /* 6C */ NULL, NULL, NULL, NULL,
12162 /* 70 */ NULL, NULL, NULL, NULL,
12163 /* 74 */ NULL, NULL, NULL, NULL,
12164 /* 78 */ NULL, NULL, NULL, NULL,
12165 /* 7C */ NULL, NULL, NULL, NULL,
12166 /* 80 */ NULL, NULL, NULL, NULL,
12167 /* 84 */ NULL, NULL, NULL, NULL,
12168 /* 88 */ NULL, NULL, "pfnacc", NULL,
12169 /* 8C */ NULL, NULL, "pfpnacc", NULL,
12170 /* 90 */ "pfcmpge", NULL, NULL, NULL,
12171 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
12172 /* 98 */ NULL, NULL, "pfsub", NULL,
12173 /* 9C */ NULL, NULL, "pfadd", NULL,
12174 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
12175 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
12176 /* A8 */ NULL, NULL, "pfsubr", NULL,
12177 /* AC */ NULL, NULL, "pfacc", NULL,
12178 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
12179 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
12180 /* B8 */ NULL, NULL, NULL, "pswapd",
12181 /* BC */ NULL, NULL, NULL, "pavgusb",
12182 /* C0 */ NULL, NULL, NULL, NULL,
12183 /* C4 */ NULL, NULL, NULL, NULL,
12184 /* C8 */ NULL, NULL, NULL, NULL,
12185 /* CC */ NULL, NULL, NULL, NULL,
12186 /* D0 */ NULL, NULL, NULL, NULL,
12187 /* D4 */ NULL, NULL, NULL, NULL,
12188 /* D8 */ NULL, NULL, NULL, NULL,
12189 /* DC */ NULL, NULL, NULL, NULL,
12190 /* E0 */ NULL, NULL, NULL, NULL,
12191 /* E4 */ NULL, NULL, NULL, NULL,
12192 /* E8 */ NULL, NULL, NULL, NULL,
12193 /* EC */ NULL, NULL, NULL, NULL,
12194 /* F0 */ NULL, NULL, NULL, NULL,
12195 /* F4 */ NULL, NULL, NULL, NULL,
12196 /* F8 */ NULL, NULL, NULL, NULL,
12197 /* FC */ NULL, NULL, NULL, NULL,
12201 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12203 const char *mnemonic;
12205 FETCH_DATA (the_info, codep + 1);
12206 /* AMD 3DNow! instructions are specified by an opcode suffix in the
12207 place where an 8-bit immediate would normally go. ie. the last
12208 byte of the instruction. */
12209 obufp = mnemonicendp;
12210 mnemonic = Suffix3DNow[*codep++ & 0xff];
12212 oappend (mnemonic);
12215 /* Since a variable sized modrm/sib chunk is between the start
12216 of the opcode (0x0f0f) and the opcode suffix, we need to do
12217 all the modrm processing first, and don't know until now that
12218 we have a bad opcode. This necessitates some cleaning up. */
12219 op_out[0][0] = '\0';
12220 op_out[1][0] = '\0';
12223 mnemonicendp = obufp;
12226 static struct op simd_cmp_op[] =
12228 { STRING_COMMA_LEN ("eq") },
12229 { STRING_COMMA_LEN ("lt") },
12230 { STRING_COMMA_LEN ("le") },
12231 { STRING_COMMA_LEN ("unord") },
12232 { STRING_COMMA_LEN ("neq") },
12233 { STRING_COMMA_LEN ("nlt") },
12234 { STRING_COMMA_LEN ("nle") },
12235 { STRING_COMMA_LEN ("ord") }
12239 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12241 unsigned int cmp_type;
12243 FETCH_DATA (the_info, codep + 1);
12244 cmp_type = *codep++ & 0xff;
12245 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
12248 char *p = mnemonicendp - 2;
12252 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
12253 mnemonicendp += simd_cmp_op[cmp_type].len;
12257 /* We have a reserved extension byte. Output it directly. */
12258 scratchbuf[0] = '$';
12259 print_operand_value (scratchbuf + 1, 1, cmp_type);
12260 oappend (scratchbuf + intel_syntax);
12261 scratchbuf[0] = '\0';
12266 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
12267 int sizeflag ATTRIBUTE_UNUSED)
12269 /* mwait %eax,%ecx */
12272 const char **names = (address_mode == mode_64bit
12273 ? names64 : names32);
12274 strcpy (op_out[0], names[0]);
12275 strcpy (op_out[1], names[1]);
12276 two_source_ops = 1;
12278 /* Skip mod/rm byte. */
12284 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
12285 int sizeflag ATTRIBUTE_UNUSED)
12287 /* monitor %eax,%ecx,%edx" */
12290 const char **op1_names;
12291 const char **names = (address_mode == mode_64bit
12292 ? names64 : names32);
12294 if (!(prefixes & PREFIX_ADDR))
12295 op1_names = (address_mode == mode_16bit
12296 ? names16 : names);
12299 /* Remove "addr16/addr32". */
12300 addr_prefix = NULL;
12301 op1_names = (address_mode != mode_32bit
12302 ? names32 : names16);
12303 used_prefixes |= PREFIX_ADDR;
12305 strcpy (op_out[0], op1_names[0]);
12306 strcpy (op_out[1], names[1]);
12307 strcpy (op_out[2], names[2]);
12308 two_source_ops = 1;
12310 /* Skip mod/rm byte. */
12318 /* Throw away prefixes and 1st. opcode byte. */
12319 codep = insn_codep + 1;
12324 REP_Fixup (int bytemode, int sizeflag)
12326 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
12328 if (prefixes & PREFIX_REPZ)
12329 repz_prefix = "rep ";
12336 OP_IMREG (bytemode, sizeflag);
12339 OP_ESreg (bytemode, sizeflag);
12342 OP_DSreg (bytemode, sizeflag);
12351 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
12356 /* Change cmpxchg8b to cmpxchg16b. */
12357 char *p = mnemonicendp - 2;
12358 mnemonicendp = stpcpy (p, "16b");
12361 OP_M (bytemode, sizeflag);
12365 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
12369 switch (vex.length)
12372 sprintf (scratchbuf, "%%xmm%d", reg);
12375 sprintf (scratchbuf, "%%ymm%d", reg);
12382 sprintf (scratchbuf, "%%xmm%d", reg);
12383 oappend (scratchbuf + intel_syntax);
12387 CRC32_Fixup (int bytemode, int sizeflag)
12389 /* Add proper suffix to "crc32". */
12390 char *p = mnemonicendp;
12407 else if (sizeflag & DFLAG)
12411 used_prefixes |= (prefixes & PREFIX_DATA);
12414 oappend (INTERNAL_DISASSEMBLER_ERROR);
12421 if (modrm.mod == 3)
12425 /* Skip mod/rm byte. */
12430 add = (rex & REX_B) ? 8 : 0;
12431 if (bytemode == b_mode)
12435 oappend (names8rex[modrm.rm + add]);
12437 oappend (names8[modrm.rm + add]);
12443 oappend (names64[modrm.rm + add]);
12444 else if ((prefixes & PREFIX_DATA))
12445 oappend (names16[modrm.rm + add]);
12447 oappend (names32[modrm.rm + add]);
12451 OP_E (bytemode, sizeflag);
12454 /* Display the destination register operand for instructions with
12458 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12466 switch (vex.length)
12479 sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
12492 sprintf (scratchbuf, "%%ymm%d", vex.register_specifier);
12498 oappend (scratchbuf + intel_syntax);
12501 /* Get the VEX immediate byte without moving codep. */
12503 static unsigned char
12504 get_vex_imm8 (int sizeflag)
12506 int bytes_before_imm = 0;
12508 /* Skip mod/rm byte. */
12512 if (modrm.mod != 3)
12514 /* There are SIB/displacement bytes. */
12515 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12517 /* 32/64 bit address mode */
12518 int base = modrm.rm;
12520 /* Check SIB byte. */
12523 FETCH_DATA (the_info, codep + 1);
12525 bytes_before_imm++;
12531 /* When modrm.rm == 5 or modrm.rm == 4 and base in
12532 SIB == 5, there is a 4 byte displacement. */
12534 /* No displacement. */
12537 /* 4 byte displacement. */
12538 bytes_before_imm += 4;
12541 /* 1 byte displacement. */
12542 bytes_before_imm++;
12547 { /* 16 bit address mode */
12551 /* When modrm.rm == 6, there is a 2 byte displacement. */
12553 /* No displacement. */
12556 /* 2 byte displacement. */
12557 bytes_before_imm += 2;
12560 /* 1 byte displacement. */
12561 bytes_before_imm++;
12567 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
12568 return codep [bytes_before_imm];
12572 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
12574 if (reg == -1 && modrm.mod != 3)
12576 OP_E_memory (bytemode, sizeflag);
12588 else if (reg > 7 && address_mode != mode_64bit)
12592 switch (vex.length)
12595 sprintf (scratchbuf, "%%xmm%d", reg);
12598 sprintf (scratchbuf, "%%ymm%d", reg);
12603 oappend (scratchbuf + intel_syntax);
12607 OP_EX_VexW (int bytemode, int sizeflag)
12615 reg = vex.register_specifier;
12620 reg = vex.register_specifier;
12623 OP_EX_VexReg (bytemode, sizeflag, reg);
12627 OP_VEX_FMA (int bytemode, int sizeflag)
12629 int reg = get_vex_imm8 (sizeflag) >> 4;
12631 if (reg > 7 && address_mode != mode_64bit)
12634 switch (vex.length)
12647 sprintf (scratchbuf, "%%xmm%d", reg);
12659 sprintf (scratchbuf, "%%ymm%d", reg);
12664 oappend (scratchbuf + intel_syntax);
12668 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
12669 int sizeflag ATTRIBUTE_UNUSED)
12671 /* Skip the immediate byte and check for invalid bits. */
12672 FETCH_DATA (the_info, codep + 1);
12673 if (*codep++ & 0xf)
12678 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12681 FETCH_DATA (the_info, codep + 1);
12684 if (bytemode != x_mode)
12691 if (reg > 7 && address_mode != mode_64bit)
12694 switch (vex.length)
12697 sprintf (scratchbuf, "%%xmm%d", reg);
12700 sprintf (scratchbuf, "%%ymm%d", reg);
12705 oappend (scratchbuf + intel_syntax);
12709 OP_XMM_VexW (int bytemode, int sizeflag)
12711 /* Turn off the REX.W bit since it is used for swapping operands
12714 OP_XMM (bytemode, sizeflag);
12718 OP_EX_Vex (int bytemode, int sizeflag)
12720 if (modrm.mod != 3)
12722 if (vex.register_specifier != 0)
12726 OP_EX (bytemode, sizeflag);
12730 OP_XMM_Vex (int bytemode, int sizeflag)
12732 if (modrm.mod != 3)
12734 if (vex.register_specifier != 0)
12738 OP_XMM (bytemode, sizeflag);
12742 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12744 switch (vex.length)
12747 mnemonicendp = stpcpy (obuf, "vzeroupper");
12750 mnemonicendp = stpcpy (obuf, "vzeroall");
12757 static struct op vex_cmp_op[] =
12759 { STRING_COMMA_LEN ("eq") },
12760 { STRING_COMMA_LEN ("lt") },
12761 { STRING_COMMA_LEN ("le") },
12762 { STRING_COMMA_LEN ("unord") },
12763 { STRING_COMMA_LEN ("neq") },
12764 { STRING_COMMA_LEN ("nlt") },
12765 { STRING_COMMA_LEN ("nle") },
12766 { STRING_COMMA_LEN ("ord") },
12767 { STRING_COMMA_LEN ("eq_uq") },
12768 { STRING_COMMA_LEN ("nge") },
12769 { STRING_COMMA_LEN ("ngt") },
12770 { STRING_COMMA_LEN ("false") },
12771 { STRING_COMMA_LEN ("neq_oq") },
12772 { STRING_COMMA_LEN ("ge") },
12773 { STRING_COMMA_LEN ("gt") },
12774 { STRING_COMMA_LEN ("true") },
12775 { STRING_COMMA_LEN ("eq_os") },
12776 { STRING_COMMA_LEN ("lt_oq") },
12777 { STRING_COMMA_LEN ("le_oq") },
12778 { STRING_COMMA_LEN ("unord_s") },
12779 { STRING_COMMA_LEN ("neq_us") },
12780 { STRING_COMMA_LEN ("nlt_uq") },
12781 { STRING_COMMA_LEN ("nle_uq") },
12782 { STRING_COMMA_LEN ("ord_s") },
12783 { STRING_COMMA_LEN ("eq_us") },
12784 { STRING_COMMA_LEN ("nge_uq") },
12785 { STRING_COMMA_LEN ("ngt_uq") },
12786 { STRING_COMMA_LEN ("false_os") },
12787 { STRING_COMMA_LEN ("neq_os") },
12788 { STRING_COMMA_LEN ("ge_oq") },
12789 { STRING_COMMA_LEN ("gt_oq") },
12790 { STRING_COMMA_LEN ("true_us") },
12794 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12796 unsigned int cmp_type;
12798 FETCH_DATA (the_info, codep + 1);
12799 cmp_type = *codep++ & 0xff;
12800 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
12803 char *p = mnemonicendp - 2;
12807 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
12808 mnemonicendp += vex_cmp_op[cmp_type].len;
12812 /* We have a reserved extension byte. Output it directly. */
12813 scratchbuf[0] = '$';
12814 print_operand_value (scratchbuf + 1, 1, cmp_type);
12815 oappend (scratchbuf + intel_syntax);
12816 scratchbuf[0] = '\0';
12820 static const struct op pclmul_op[] =
12822 { STRING_COMMA_LEN ("lql") },
12823 { STRING_COMMA_LEN ("hql") },
12824 { STRING_COMMA_LEN ("lqh") },
12825 { STRING_COMMA_LEN ("hqh") }
12829 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
12830 int sizeflag ATTRIBUTE_UNUSED)
12832 unsigned int pclmul_type;
12834 FETCH_DATA (the_info, codep + 1);
12835 pclmul_type = *codep++ & 0xff;
12836 switch (pclmul_type)
12847 if (pclmul_type < ARRAY_SIZE (pclmul_op))
12850 char *p = mnemonicendp - 3;
12855 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
12856 mnemonicendp += pclmul_op[pclmul_type].len;
12860 /* We have a reserved extension byte. Output it directly. */
12861 scratchbuf[0] = '$';
12862 print_operand_value (scratchbuf + 1, 1, pclmul_type);
12863 oappend (scratchbuf + intel_syntax);
12864 scratchbuf[0] = '\0';
12869 MOVBE_Fixup (int bytemode, int sizeflag)
12871 /* Add proper suffix to "movbe". */
12872 char *p = mnemonicendp;
12881 if (sizeflag & SUFFIX_ALWAYS)
12885 else if (sizeflag & DFLAG)
12890 used_prefixes |= (prefixes & PREFIX_DATA);
12893 oappend (INTERNAL_DISASSEMBLER_ERROR);
12900 OP_M (bytemode, sizeflag);