1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2017 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma, disassemble_info *);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma get64 (void);
58 static bfd_signed_vma get32 (void);
59 static bfd_signed_vma get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void OP_Mwaitx (int, int);
106 static void NOP_Fixup1 (int, int);
107 static void NOP_Fixup2 (int, int);
108 static void OP_3DNowSuffix (int, int);
109 static void CMP_Fixup (int, int);
110 static void BadOp (void);
111 static void REP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void NOTRACK_Fixup (int, int);
114 static void HLE_Fixup1 (int, int);
115 static void HLE_Fixup2 (int, int);
116 static void HLE_Fixup3 (int, int);
117 static void CMPXCHG8B_Fixup (int, int);
118 static void XMM_Fixup (int, int);
119 static void CRC32_Fixup (int, int);
120 static void FXSAVE_Fixup (int, int);
121 static void PCMPESTR_Fixup (int, int);
122 static void OP_LWPCB_E (int, int);
123 static void OP_LWP_E (int, int);
124 static void OP_Vex_2src_1 (int, int);
125 static void OP_Vex_2src_2 (int, int);
127 static void MOVBE_Fixup (int, int);
129 static void OP_Mask (int, int);
132 /* Points to first byte not fetched. */
133 bfd_byte *max_fetched;
134 bfd_byte the_buffer[MAX_MNEM_SIZE];
137 OPCODES_SIGJMP_BUF bailout;
147 enum address_mode address_mode;
149 /* Flags for the prefixes for the current instruction. See below. */
152 /* REX prefix the current instruction. See below. */
154 /* Bits of REX we've already used. */
156 /* REX bits in original REX prefix ignored. */
157 static int rex_ignored;
158 /* Mark parts used in the REX prefix. When we are testing for
159 empty prefix (for 8bit register REX extension), just mask it
160 out. Otherwise test for REX bit is excuse for existence of REX
161 only in case value is nonzero. */
162 #define USED_REX(value) \
167 rex_used |= (value) | REX_OPCODE; \
170 rex_used |= REX_OPCODE; \
173 /* Flags for prefixes which we somehow handled when printing the
174 current instruction. */
175 static int used_prefixes;
177 /* Flags stored in PREFIXES. */
178 #define PREFIX_REPZ 1
179 #define PREFIX_REPNZ 2
180 #define PREFIX_LOCK 4
182 #define PREFIX_SS 0x10
183 #define PREFIX_DS 0x20
184 #define PREFIX_ES 0x40
185 #define PREFIX_FS 0x80
186 #define PREFIX_GS 0x100
187 #define PREFIX_DATA 0x200
188 #define PREFIX_ADDR 0x400
189 #define PREFIX_FWAIT 0x800
191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
192 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
194 #define FETCH_DATA(info, addr) \
195 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
196 ? 1 : fetch_data ((info), (addr)))
199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
202 struct dis_private *priv = (struct dis_private *) info->private_data;
203 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
205 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
206 status = (*info->read_memory_func) (start,
208 addr - priv->max_fetched,
214 /* If we did manage to read at least one byte, then
215 print_insn_i386 will do something sensible. Otherwise, print
216 an error. We do that here because this is where we know
218 if (priv->max_fetched == priv->the_buffer)
219 (*info->memory_error_func) (status, start, info);
220 OPCODES_SIGLONGJMP (priv->bailout, 1);
223 priv->max_fetched = addr;
227 /* Possible values for prefix requirement. */
228 #define PREFIX_IGNORED_SHIFT 16
229 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
233 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
235 /* Opcode prefixes. */
236 #define PREFIX_OPCODE (PREFIX_REPZ \
240 /* Prefixes ignored. */
241 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
242 | PREFIX_IGNORED_REPNZ \
243 | PREFIX_IGNORED_DATA)
245 #define XX { NULL, 0 }
246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
248 #define Eb { OP_E, b_mode }
249 #define Ebnd { OP_E, bnd_mode }
250 #define EbS { OP_E, b_swap_mode }
251 #define Ev { OP_E, v_mode }
252 #define Ev_bnd { OP_E, v_bnd_mode }
253 #define EvS { OP_E, v_swap_mode }
254 #define Ed { OP_E, d_mode }
255 #define Edq { OP_E, dq_mode }
256 #define Edqw { OP_E, dqw_mode }
257 #define Edqb { OP_E, dqb_mode }
258 #define Edb { OP_E, db_mode }
259 #define Edw { OP_E, dw_mode }
260 #define Edqd { OP_E, dqd_mode }
261 #define Eq { OP_E, q_mode }
262 #define indirEv { OP_indirE, indir_v_mode }
263 #define indirEp { OP_indirE, f_mode }
264 #define stackEv { OP_E, stack_v_mode }
265 #define Em { OP_E, m_mode }
266 #define Ew { OP_E, w_mode }
267 #define M { OP_M, 0 } /* lea, lgdt, etc. */
268 #define Ma { OP_M, a_mode }
269 #define Mb { OP_M, b_mode }
270 #define Md { OP_M, d_mode }
271 #define Mo { OP_M, o_mode }
272 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
273 #define Mq { OP_M, q_mode }
274 #define Mx { OP_M, x_mode }
275 #define Mxmm { OP_M, xmm_mode }
276 #define Gb { OP_G, b_mode }
277 #define Gbnd { OP_G, bnd_mode }
278 #define Gv { OP_G, v_mode }
279 #define Gd { OP_G, d_mode }
280 #define Gdq { OP_G, dq_mode }
281 #define Gm { OP_G, m_mode }
282 #define Gw { OP_G, w_mode }
283 #define Rd { OP_R, d_mode }
284 #define Rdq { OP_R, dq_mode }
285 #define Rm { OP_R, m_mode }
286 #define Ib { OP_I, b_mode }
287 #define sIb { OP_sI, b_mode } /* sign extened byte */
288 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
289 #define Iv { OP_I, v_mode }
290 #define sIv { OP_sI, v_mode }
291 #define Iq { OP_I, q_mode }
292 #define Iv64 { OP_I64, v_mode }
293 #define Iw { OP_I, w_mode }
294 #define I1 { OP_I, const_1_mode }
295 #define Jb { OP_J, b_mode }
296 #define Jv { OP_J, v_mode }
297 #define Cm { OP_C, m_mode }
298 #define Dm { OP_D, m_mode }
299 #define Td { OP_T, d_mode }
300 #define Skip_MODRM { OP_Skip_MODRM, 0 }
302 #define RMeAX { OP_REG, eAX_reg }
303 #define RMeBX { OP_REG, eBX_reg }
304 #define RMeCX { OP_REG, eCX_reg }
305 #define RMeDX { OP_REG, eDX_reg }
306 #define RMeSP { OP_REG, eSP_reg }
307 #define RMeBP { OP_REG, eBP_reg }
308 #define RMeSI { OP_REG, eSI_reg }
309 #define RMeDI { OP_REG, eDI_reg }
310 #define RMrAX { OP_REG, rAX_reg }
311 #define RMrBX { OP_REG, rBX_reg }
312 #define RMrCX { OP_REG, rCX_reg }
313 #define RMrDX { OP_REG, rDX_reg }
314 #define RMrSP { OP_REG, rSP_reg }
315 #define RMrBP { OP_REG, rBP_reg }
316 #define RMrSI { OP_REG, rSI_reg }
317 #define RMrDI { OP_REG, rDI_reg }
318 #define RMAL { OP_REG, al_reg }
319 #define RMCL { OP_REG, cl_reg }
320 #define RMDL { OP_REG, dl_reg }
321 #define RMBL { OP_REG, bl_reg }
322 #define RMAH { OP_REG, ah_reg }
323 #define RMCH { OP_REG, ch_reg }
324 #define RMDH { OP_REG, dh_reg }
325 #define RMBH { OP_REG, bh_reg }
326 #define RMAX { OP_REG, ax_reg }
327 #define RMDX { OP_REG, dx_reg }
329 #define eAX { OP_IMREG, eAX_reg }
330 #define eBX { OP_IMREG, eBX_reg }
331 #define eCX { OP_IMREG, eCX_reg }
332 #define eDX { OP_IMREG, eDX_reg }
333 #define eSP { OP_IMREG, eSP_reg }
334 #define eBP { OP_IMREG, eBP_reg }
335 #define eSI { OP_IMREG, eSI_reg }
336 #define eDI { OP_IMREG, eDI_reg }
337 #define AL { OP_IMREG, al_reg }
338 #define CL { OP_IMREG, cl_reg }
339 #define DL { OP_IMREG, dl_reg }
340 #define BL { OP_IMREG, bl_reg }
341 #define AH { OP_IMREG, ah_reg }
342 #define CH { OP_IMREG, ch_reg }
343 #define DH { OP_IMREG, dh_reg }
344 #define BH { OP_IMREG, bh_reg }
345 #define AX { OP_IMREG, ax_reg }
346 #define DX { OP_IMREG, dx_reg }
347 #define zAX { OP_IMREG, z_mode_ax_reg }
348 #define indirDX { OP_IMREG, indir_dx_reg }
350 #define Sw { OP_SEG, w_mode }
351 #define Sv { OP_SEG, v_mode }
352 #define Ap { OP_DIR, 0 }
353 #define Ob { OP_OFF64, b_mode }
354 #define Ov { OP_OFF64, v_mode }
355 #define Xb { OP_DSreg, eSI_reg }
356 #define Xv { OP_DSreg, eSI_reg }
357 #define Xz { OP_DSreg, eSI_reg }
358 #define Yb { OP_ESreg, eDI_reg }
359 #define Yv { OP_ESreg, eDI_reg }
360 #define DSBX { OP_DSreg, eBX_reg }
362 #define es { OP_REG, es_reg }
363 #define ss { OP_REG, ss_reg }
364 #define cs { OP_REG, cs_reg }
365 #define ds { OP_REG, ds_reg }
366 #define fs { OP_REG, fs_reg }
367 #define gs { OP_REG, gs_reg }
369 #define MX { OP_MMX, 0 }
370 #define XM { OP_XMM, 0 }
371 #define XMScalar { OP_XMM, scalar_mode }
372 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
373 #define XMM { OP_XMM, xmm_mode }
374 #define XMxmmq { OP_XMM, xmmq_mode }
375 #define EM { OP_EM, v_mode }
376 #define EMS { OP_EM, v_swap_mode }
377 #define EMd { OP_EM, d_mode }
378 #define EMx { OP_EM, x_mode }
379 #define EXbScalar { OP_EX, b_scalar_mode }
380 #define EXw { OP_EX, w_mode }
381 #define EXwScalar { OP_EX, w_scalar_mode }
382 #define EXd { OP_EX, d_mode }
383 #define EXdScalar { OP_EX, d_scalar_mode }
384 #define EXdS { OP_EX, d_swap_mode }
385 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
386 #define EXq { OP_EX, q_mode }
387 #define EXqScalar { OP_EX, q_scalar_mode }
388 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
389 #define EXqS { OP_EX, q_swap_mode }
390 #define EXx { OP_EX, x_mode }
391 #define EXxS { OP_EX, x_swap_mode }
392 #define EXxmm { OP_EX, xmm_mode }
393 #define EXymm { OP_EX, ymm_mode }
394 #define EXxmmq { OP_EX, xmmq_mode }
395 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
396 #define EXxmm_mb { OP_EX, xmm_mb_mode }
397 #define EXxmm_mw { OP_EX, xmm_mw_mode }
398 #define EXxmm_md { OP_EX, xmm_md_mode }
399 #define EXxmm_mq { OP_EX, xmm_mq_mode }
400 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
401 #define EXxmmdw { OP_EX, xmmdw_mode }
402 #define EXxmmqd { OP_EX, xmmqd_mode }
403 #define EXymmq { OP_EX, ymmq_mode }
404 #define EXVexWdq { OP_EX, vex_w_dq_mode }
405 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
406 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
407 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
408 #define MS { OP_MS, v_mode }
409 #define XS { OP_XS, v_mode }
410 #define EMCq { OP_EMC, q_mode }
411 #define MXC { OP_MXC, 0 }
412 #define OPSUF { OP_3DNowSuffix, 0 }
413 #define CMP { CMP_Fixup, 0 }
414 #define XMM0 { XMM_Fixup, 0 }
415 #define FXSAVE { FXSAVE_Fixup, 0 }
416 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
417 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
419 #define Vex { OP_VEX, vex_mode }
420 #define VexScalar { OP_VEX, vex_scalar_mode }
421 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
422 #define Vex128 { OP_VEX, vex128_mode }
423 #define Vex256 { OP_VEX, vex256_mode }
424 #define VexGdq { OP_VEX, dq_mode }
425 #define VexI4 { VEXI4_Fixup, 0}
426 #define EXdVex { OP_EX_Vex, d_mode }
427 #define EXdVexS { OP_EX_Vex, d_swap_mode }
428 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
429 #define EXqVex { OP_EX_Vex, q_mode }
430 #define EXqVexS { OP_EX_Vex, q_swap_mode }
431 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
432 #define EXVexW { OP_EX_VexW, x_mode }
433 #define EXdVexW { OP_EX_VexW, d_mode }
434 #define EXqVexW { OP_EX_VexW, q_mode }
435 #define EXVexImmW { OP_EX_VexImmW, x_mode }
436 #define XMVex { OP_XMM_Vex, 0 }
437 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
438 #define XMVexW { OP_XMM_VexW, 0 }
439 #define XMVexI4 { OP_REG_VexI4, x_mode }
440 #define PCLMUL { PCLMUL_Fixup, 0 }
441 #define VZERO { VZERO_Fixup, 0 }
442 #define VCMP { VCMP_Fixup, 0 }
443 #define VPCMP { VPCMP_Fixup, 0 }
445 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
446 #define EXxEVexS { OP_Rounding, evex_sae_mode }
448 #define XMask { OP_Mask, mask_mode }
449 #define MaskG { OP_G, mask_mode }
450 #define MaskE { OP_E, mask_mode }
451 #define MaskBDE { OP_E, mask_bd_mode }
452 #define MaskR { OP_R, mask_mode }
453 #define MaskVex { OP_VEX, mask_mode }
455 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
456 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
457 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
458 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
460 /* Used handle "rep" prefix for string instructions. */
461 #define Xbr { REP_Fixup, eSI_reg }
462 #define Xvr { REP_Fixup, eSI_reg }
463 #define Ybr { REP_Fixup, eDI_reg }
464 #define Yvr { REP_Fixup, eDI_reg }
465 #define Yzr { REP_Fixup, eDI_reg }
466 #define indirDXr { REP_Fixup, indir_dx_reg }
467 #define ALr { REP_Fixup, al_reg }
468 #define eAXr { REP_Fixup, eAX_reg }
470 /* Used handle HLE prefix for lockable instructions. */
471 #define Ebh1 { HLE_Fixup1, b_mode }
472 #define Evh1 { HLE_Fixup1, v_mode }
473 #define Ebh2 { HLE_Fixup2, b_mode }
474 #define Evh2 { HLE_Fixup2, v_mode }
475 #define Ebh3 { HLE_Fixup3, b_mode }
476 #define Evh3 { HLE_Fixup3, v_mode }
478 #define BND { BND_Fixup, 0 }
479 #define NOTRACK { NOTRACK_Fixup, 0 }
481 #define cond_jump_flag { NULL, cond_jump_mode }
482 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
484 /* bits in sizeflag */
485 #define SUFFIX_ALWAYS 4
493 /* byte operand with operand swapped */
495 /* byte operand, sign extend like 'T' suffix */
497 /* operand size depends on prefixes */
499 /* operand size depends on prefixes with operand swapped */
503 /* double word operand */
505 /* double word operand with operand swapped */
507 /* quad word operand */
509 /* quad word operand with operand swapped */
511 /* ten-byte operand */
513 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
514 broadcast enabled. */
516 /* Similar to x_mode, but with different EVEX mem shifts. */
518 /* Similar to x_mode, but with disabled broadcast. */
520 /* Similar to x_mode, but with operands swapped and disabled broadcast
523 /* 16-byte XMM operand */
525 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
526 memory operand (depending on vector length). Broadcast isn't
529 /* Same as xmmq_mode, but broadcast is allowed. */
530 evex_half_bcst_xmmq_mode,
531 /* XMM register or byte memory operand */
533 /* XMM register or word memory operand */
535 /* XMM register or double word memory operand */
537 /* XMM register or quad word memory operand */
539 /* XMM register or double/quad word memory operand, depending on
542 /* 16-byte XMM, word, double word or quad word operand. */
544 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
546 /* 32-byte YMM operand */
548 /* quad word, ymmword or zmmword memory operand. */
550 /* 32-byte YMM or 16-byte word operand */
552 /* d_mode in 32bit, q_mode in 64bit mode. */
554 /* pair of v_mode operands */
559 /* operand size depends on REX prefixes. */
561 /* registers like dq_mode, memory like w_mode. */
564 /* 4- or 6-byte pointer operand */
567 /* v_mode for indirect branch opcodes. */
569 /* v_mode for stack-related opcodes. */
571 /* non-quad operand size depends on prefixes */
573 /* 16-byte operand */
575 /* registers like dq_mode, memory like b_mode. */
577 /* registers like d_mode, memory like b_mode. */
579 /* registers like d_mode, memory like w_mode. */
581 /* registers like dq_mode, memory like d_mode. */
583 /* normal vex mode */
585 /* 128bit vex mode */
587 /* 256bit vex mode */
589 /* operand size depends on the VEX.W bit. */
592 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
593 vex_vsib_d_w_dq_mode,
594 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
596 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
597 vex_vsib_q_w_dq_mode,
598 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
601 /* scalar, ignore vector length. */
603 /* like b_mode, ignore vector length. */
605 /* like w_mode, ignore vector length. */
607 /* like d_mode, ignore vector length. */
609 /* like d_swap_mode, ignore vector length. */
611 /* like q_mode, ignore vector length. */
613 /* like q_swap_mode, ignore vector length. */
615 /* like vex_mode, ignore vector length. */
617 /* like vex_w_dq_mode, ignore vector length. */
618 vex_scalar_w_dq_mode,
620 /* Static rounding. */
622 /* Supress all exceptions. */
625 /* Mask register operand. */
627 /* Mask register operand. */
694 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
696 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
697 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
698 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
699 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
700 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
701 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
702 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
703 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
704 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
705 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
706 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
707 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
708 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
709 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
710 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
832 MOD_VEX_0F12_PREFIX_0,
834 MOD_VEX_0F16_PREFIX_0,
837 MOD_VEX_W_0_0F41_P_0_LEN_1,
838 MOD_VEX_W_1_0F41_P_0_LEN_1,
839 MOD_VEX_W_0_0F41_P_2_LEN_1,
840 MOD_VEX_W_1_0F41_P_2_LEN_1,
841 MOD_VEX_W_0_0F42_P_0_LEN_1,
842 MOD_VEX_W_1_0F42_P_0_LEN_1,
843 MOD_VEX_W_0_0F42_P_2_LEN_1,
844 MOD_VEX_W_1_0F42_P_2_LEN_1,
845 MOD_VEX_W_0_0F44_P_0_LEN_1,
846 MOD_VEX_W_1_0F44_P_0_LEN_1,
847 MOD_VEX_W_0_0F44_P_2_LEN_1,
848 MOD_VEX_W_1_0F44_P_2_LEN_1,
849 MOD_VEX_W_0_0F45_P_0_LEN_1,
850 MOD_VEX_W_1_0F45_P_0_LEN_1,
851 MOD_VEX_W_0_0F45_P_2_LEN_1,
852 MOD_VEX_W_1_0F45_P_2_LEN_1,
853 MOD_VEX_W_0_0F46_P_0_LEN_1,
854 MOD_VEX_W_1_0F46_P_0_LEN_1,
855 MOD_VEX_W_0_0F46_P_2_LEN_1,
856 MOD_VEX_W_1_0F46_P_2_LEN_1,
857 MOD_VEX_W_0_0F47_P_0_LEN_1,
858 MOD_VEX_W_1_0F47_P_0_LEN_1,
859 MOD_VEX_W_0_0F47_P_2_LEN_1,
860 MOD_VEX_W_1_0F47_P_2_LEN_1,
861 MOD_VEX_W_0_0F4A_P_0_LEN_1,
862 MOD_VEX_W_1_0F4A_P_0_LEN_1,
863 MOD_VEX_W_0_0F4A_P_2_LEN_1,
864 MOD_VEX_W_1_0F4A_P_2_LEN_1,
865 MOD_VEX_W_0_0F4B_P_0_LEN_1,
866 MOD_VEX_W_1_0F4B_P_0_LEN_1,
867 MOD_VEX_W_0_0F4B_P_2_LEN_1,
879 MOD_VEX_W_0_0F91_P_0_LEN_0,
880 MOD_VEX_W_1_0F91_P_0_LEN_0,
881 MOD_VEX_W_0_0F91_P_2_LEN_0,
882 MOD_VEX_W_1_0F91_P_2_LEN_0,
883 MOD_VEX_W_0_0F92_P_0_LEN_0,
884 MOD_VEX_W_0_0F92_P_2_LEN_0,
885 MOD_VEX_W_0_0F92_P_3_LEN_0,
886 MOD_VEX_W_1_0F92_P_3_LEN_0,
887 MOD_VEX_W_0_0F93_P_0_LEN_0,
888 MOD_VEX_W_0_0F93_P_2_LEN_0,
889 MOD_VEX_W_0_0F93_P_3_LEN_0,
890 MOD_VEX_W_1_0F93_P_3_LEN_0,
891 MOD_VEX_W_0_0F98_P_0_LEN_0,
892 MOD_VEX_W_1_0F98_P_0_LEN_0,
893 MOD_VEX_W_0_0F98_P_2_LEN_0,
894 MOD_VEX_W_1_0F98_P_2_LEN_0,
895 MOD_VEX_W_0_0F99_P_0_LEN_0,
896 MOD_VEX_W_1_0F99_P_0_LEN_0,
897 MOD_VEX_W_0_0F99_P_2_LEN_0,
898 MOD_VEX_W_1_0F99_P_2_LEN_0,
901 MOD_VEX_0FD7_PREFIX_2,
902 MOD_VEX_0FE7_PREFIX_2,
903 MOD_VEX_0FF0_PREFIX_3,
904 MOD_VEX_0F381A_PREFIX_2,
905 MOD_VEX_0F382A_PREFIX_2,
906 MOD_VEX_0F382C_PREFIX_2,
907 MOD_VEX_0F382D_PREFIX_2,
908 MOD_VEX_0F382E_PREFIX_2,
909 MOD_VEX_0F382F_PREFIX_2,
910 MOD_VEX_0F385A_PREFIX_2,
911 MOD_VEX_0F388C_PREFIX_2,
912 MOD_VEX_0F388E_PREFIX_2,
913 MOD_VEX_W_0_0F3A30_P_2_LEN_0,
914 MOD_VEX_W_1_0F3A30_P_2_LEN_0,
915 MOD_VEX_W_0_0F3A31_P_2_LEN_0,
916 MOD_VEX_W_1_0F3A31_P_2_LEN_0,
917 MOD_VEX_W_0_0F3A32_P_2_LEN_0,
918 MOD_VEX_W_1_0F3A32_P_2_LEN_0,
919 MOD_VEX_W_0_0F3A33_P_2_LEN_0,
920 MOD_VEX_W_1_0F3A33_P_2_LEN_0,
922 MOD_EVEX_0F10_PREFIX_1,
923 MOD_EVEX_0F10_PREFIX_3,
924 MOD_EVEX_0F11_PREFIX_1,
925 MOD_EVEX_0F11_PREFIX_3,
926 MOD_EVEX_0F12_PREFIX_0,
927 MOD_EVEX_0F16_PREFIX_0,
928 MOD_EVEX_0F38C6_REG_1,
929 MOD_EVEX_0F38C6_REG_2,
930 MOD_EVEX_0F38C6_REG_5,
931 MOD_EVEX_0F38C6_REG_6,
932 MOD_EVEX_0F38C7_REG_1,
933 MOD_EVEX_0F38C7_REG_2,
934 MOD_EVEX_0F38C7_REG_5,
935 MOD_EVEX_0F38C7_REG_6
956 PREFIX_MOD_0_0F01_REG_5,
957 PREFIX_MOD_3_0F01_REG_5_RM_0,
958 PREFIX_MOD_3_0F01_REG_5_RM_2,
1002 PREFIX_MOD_0_0FAE_REG_4,
1003 PREFIX_MOD_3_0FAE_REG_4,
1004 PREFIX_MOD_0_0FAE_REG_5,
1005 PREFIX_MOD_3_0FAE_REG_5,
1013 PREFIX_MOD_0_0FC7_REG_6,
1014 PREFIX_MOD_3_0FC7_REG_6,
1015 PREFIX_MOD_3_0FC7_REG_7,
1143 PREFIX_VEX_0F71_REG_2,
1144 PREFIX_VEX_0F71_REG_4,
1145 PREFIX_VEX_0F71_REG_6,
1146 PREFIX_VEX_0F72_REG_2,
1147 PREFIX_VEX_0F72_REG_4,
1148 PREFIX_VEX_0F72_REG_6,
1149 PREFIX_VEX_0F73_REG_2,
1150 PREFIX_VEX_0F73_REG_3,
1151 PREFIX_VEX_0F73_REG_6,
1152 PREFIX_VEX_0F73_REG_7,
1325 PREFIX_VEX_0F38F3_REG_1,
1326 PREFIX_VEX_0F38F3_REG_2,
1327 PREFIX_VEX_0F38F3_REG_3,
1446 PREFIX_EVEX_0F71_REG_2,
1447 PREFIX_EVEX_0F71_REG_4,
1448 PREFIX_EVEX_0F71_REG_6,
1449 PREFIX_EVEX_0F72_REG_0,
1450 PREFIX_EVEX_0F72_REG_1,
1451 PREFIX_EVEX_0F72_REG_2,
1452 PREFIX_EVEX_0F72_REG_4,
1453 PREFIX_EVEX_0F72_REG_6,
1454 PREFIX_EVEX_0F73_REG_2,
1455 PREFIX_EVEX_0F73_REG_3,
1456 PREFIX_EVEX_0F73_REG_6,
1457 PREFIX_EVEX_0F73_REG_7,
1651 PREFIX_EVEX_0F38C6_REG_1,
1652 PREFIX_EVEX_0F38C6_REG_2,
1653 PREFIX_EVEX_0F38C6_REG_5,
1654 PREFIX_EVEX_0F38C6_REG_6,
1655 PREFIX_EVEX_0F38C7_REG_1,
1656 PREFIX_EVEX_0F38C7_REG_2,
1657 PREFIX_EVEX_0F38C7_REG_5,
1658 PREFIX_EVEX_0F38C7_REG_6,
1760 THREE_BYTE_0F38 = 0,
1787 VEX_LEN_0F10_P_1 = 0,
1791 VEX_LEN_0F12_P_0_M_0,
1792 VEX_LEN_0F12_P_0_M_1,
1795 VEX_LEN_0F16_P_0_M_0,
1796 VEX_LEN_0F16_P_0_M_1,
1860 VEX_LEN_0FAE_R_2_M_0,
1861 VEX_LEN_0FAE_R_3_M_0,
1870 VEX_LEN_0F381A_P_2_M_0,
1873 VEX_LEN_0F385A_P_2_M_0,
1876 VEX_LEN_0F38F3_R_1_P_0,
1877 VEX_LEN_0F38F3_R_2_P_0,
1878 VEX_LEN_0F38F3_R_3_P_0,
1923 VEX_LEN_0FXOP_08_CC,
1924 VEX_LEN_0FXOP_08_CD,
1925 VEX_LEN_0FXOP_08_CE,
1926 VEX_LEN_0FXOP_08_CF,
1927 VEX_LEN_0FXOP_08_EC,
1928 VEX_LEN_0FXOP_08_ED,
1929 VEX_LEN_0FXOP_08_EE,
1930 VEX_LEN_0FXOP_08_EF,
1931 VEX_LEN_0FXOP_09_80,
1965 VEX_W_0F41_P_0_LEN_1,
1966 VEX_W_0F41_P_2_LEN_1,
1967 VEX_W_0F42_P_0_LEN_1,
1968 VEX_W_0F42_P_2_LEN_1,
1969 VEX_W_0F44_P_0_LEN_0,
1970 VEX_W_0F44_P_2_LEN_0,
1971 VEX_W_0F45_P_0_LEN_1,
1972 VEX_W_0F45_P_2_LEN_1,
1973 VEX_W_0F46_P_0_LEN_1,
1974 VEX_W_0F46_P_2_LEN_1,
1975 VEX_W_0F47_P_0_LEN_1,
1976 VEX_W_0F47_P_2_LEN_1,
1977 VEX_W_0F4A_P_0_LEN_1,
1978 VEX_W_0F4A_P_2_LEN_1,
1979 VEX_W_0F4B_P_0_LEN_1,
1980 VEX_W_0F4B_P_2_LEN_1,
2060 VEX_W_0F90_P_0_LEN_0,
2061 VEX_W_0F90_P_2_LEN_0,
2062 VEX_W_0F91_P_0_LEN_0,
2063 VEX_W_0F91_P_2_LEN_0,
2064 VEX_W_0F92_P_0_LEN_0,
2065 VEX_W_0F92_P_2_LEN_0,
2066 VEX_W_0F92_P_3_LEN_0,
2067 VEX_W_0F93_P_0_LEN_0,
2068 VEX_W_0F93_P_2_LEN_0,
2069 VEX_W_0F93_P_3_LEN_0,
2070 VEX_W_0F98_P_0_LEN_0,
2071 VEX_W_0F98_P_2_LEN_0,
2072 VEX_W_0F99_P_0_LEN_0,
2073 VEX_W_0F99_P_2_LEN_0,
2152 VEX_W_0F381A_P_2_M_0,
2164 VEX_W_0F382A_P_2_M_0,
2166 VEX_W_0F382C_P_2_M_0,
2167 VEX_W_0F382D_P_2_M_0,
2168 VEX_W_0F382E_P_2_M_0,
2169 VEX_W_0F382F_P_2_M_0,
2191 VEX_W_0F385A_P_2_M_0,
2216 VEX_W_0F3A30_P_2_LEN_0,
2217 VEX_W_0F3A31_P_2_LEN_0,
2218 VEX_W_0F3A32_P_2_LEN_0,
2219 VEX_W_0F3A33_P_2_LEN_0,
2238 EVEX_W_0F10_P_1_M_0,
2239 EVEX_W_0F10_P_1_M_1,
2241 EVEX_W_0F10_P_3_M_0,
2242 EVEX_W_0F10_P_3_M_1,
2244 EVEX_W_0F11_P_1_M_0,
2245 EVEX_W_0F11_P_1_M_1,
2247 EVEX_W_0F11_P_3_M_0,
2248 EVEX_W_0F11_P_3_M_1,
2249 EVEX_W_0F12_P_0_M_0,
2250 EVEX_W_0F12_P_0_M_1,
2260 EVEX_W_0F16_P_0_M_0,
2261 EVEX_W_0F16_P_0_M_1,
2332 EVEX_W_0F72_R_2_P_2,
2333 EVEX_W_0F72_R_6_P_2,
2334 EVEX_W_0F73_R_2_P_2,
2335 EVEX_W_0F73_R_6_P_2,
2442 EVEX_W_0F38C7_R_1_P_2,
2443 EVEX_W_0F38C7_R_2_P_2,
2444 EVEX_W_0F38C7_R_5_P_2,
2445 EVEX_W_0F38C7_R_6_P_2,
2486 typedef void (*op_rtn) (int bytemode, int sizeflag);
2495 unsigned int prefix_requirement;
2498 /* Upper case letters in the instruction names here are macros.
2499 'A' => print 'b' if no register operands or suffix_always is true
2500 'B' => print 'b' if suffix_always is true
2501 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2503 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2504 suffix_always is true
2505 'E' => print 'e' if 32-bit form of jcxz
2506 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2507 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2508 'H' => print ",pt" or ",pn" branch hint
2509 'I' => honor following macro letter even in Intel mode (implemented only
2510 for some of the macro letters)
2512 'K' => print 'd' or 'q' if rex prefix is present.
2513 'L' => print 'l' if suffix_always is true
2514 'M' => print 'r' if intel_mnemonic is false.
2515 'N' => print 'n' if instruction has no wait "prefix"
2516 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2517 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2518 or suffix_always is true. print 'q' if rex prefix is present.
2519 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2521 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2522 'S' => print 'w', 'l' or 'q' if suffix_always is true
2523 'T' => print 'q' in 64bit mode if instruction has no operand size
2524 prefix and behave as 'P' otherwise
2525 'U' => print 'q' in 64bit mode if instruction has no operand size
2526 prefix and behave as 'Q' otherwise
2527 'V' => print 'q' in 64bit mode if instruction has no operand size
2528 prefix and behave as 'S' otherwise
2529 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2530 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2531 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2532 suffix_always is true.
2533 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2534 '!' => change condition from true to false or from false to true.
2535 '%' => add 1 upper case letter to the macro.
2536 '^' => print 'w' or 'l' depending on operand size prefix or
2537 suffix_always is true (lcall/ljmp).
2538 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2539 on operand size prefix.
2540 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2541 has no operand size prefix for AMD64 ISA, behave as 'P'
2544 2 upper case letter macros:
2545 "XY" => print 'x' or 'y' if suffix_always is true or no register
2546 operands and no broadcast.
2547 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2548 register operands and no broadcast.
2549 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2550 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2551 or suffix_always is true
2552 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2553 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2554 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2555 "LW" => print 'd', 'q' depending on the VEX.W bit
2556 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2557 an operand size prefix, or suffix_always is true. print
2558 'q' if rex prefix is present.
2560 Many of the above letters print nothing in Intel mode. See "putop"
2563 Braces '{' and '}', and vertical bars '|', indicate alternative
2564 mnemonic strings for AT&T and Intel. */
2566 static const struct dis386 dis386[] = {
2568 { "addB", { Ebh1, Gb }, 0 },
2569 { "addS", { Evh1, Gv }, 0 },
2570 { "addB", { Gb, EbS }, 0 },
2571 { "addS", { Gv, EvS }, 0 },
2572 { "addB", { AL, Ib }, 0 },
2573 { "addS", { eAX, Iv }, 0 },
2574 { X86_64_TABLE (X86_64_06) },
2575 { X86_64_TABLE (X86_64_07) },
2577 { "orB", { Ebh1, Gb }, 0 },
2578 { "orS", { Evh1, Gv }, 0 },
2579 { "orB", { Gb, EbS }, 0 },
2580 { "orS", { Gv, EvS }, 0 },
2581 { "orB", { AL, Ib }, 0 },
2582 { "orS", { eAX, Iv }, 0 },
2583 { X86_64_TABLE (X86_64_0D) },
2584 { Bad_Opcode }, /* 0x0f extended opcode escape */
2586 { "adcB", { Ebh1, Gb }, 0 },
2587 { "adcS", { Evh1, Gv }, 0 },
2588 { "adcB", { Gb, EbS }, 0 },
2589 { "adcS", { Gv, EvS }, 0 },
2590 { "adcB", { AL, Ib }, 0 },
2591 { "adcS", { eAX, Iv }, 0 },
2592 { X86_64_TABLE (X86_64_16) },
2593 { X86_64_TABLE (X86_64_17) },
2595 { "sbbB", { Ebh1, Gb }, 0 },
2596 { "sbbS", { Evh1, Gv }, 0 },
2597 { "sbbB", { Gb, EbS }, 0 },
2598 { "sbbS", { Gv, EvS }, 0 },
2599 { "sbbB", { AL, Ib }, 0 },
2600 { "sbbS", { eAX, Iv }, 0 },
2601 { X86_64_TABLE (X86_64_1E) },
2602 { X86_64_TABLE (X86_64_1F) },
2604 { "andB", { Ebh1, Gb }, 0 },
2605 { "andS", { Evh1, Gv }, 0 },
2606 { "andB", { Gb, EbS }, 0 },
2607 { "andS", { Gv, EvS }, 0 },
2608 { "andB", { AL, Ib }, 0 },
2609 { "andS", { eAX, Iv }, 0 },
2610 { Bad_Opcode }, /* SEG ES prefix */
2611 { X86_64_TABLE (X86_64_27) },
2613 { "subB", { Ebh1, Gb }, 0 },
2614 { "subS", { Evh1, Gv }, 0 },
2615 { "subB", { Gb, EbS }, 0 },
2616 { "subS", { Gv, EvS }, 0 },
2617 { "subB", { AL, Ib }, 0 },
2618 { "subS", { eAX, Iv }, 0 },
2619 { Bad_Opcode }, /* SEG CS prefix */
2620 { X86_64_TABLE (X86_64_2F) },
2622 { "xorB", { Ebh1, Gb }, 0 },
2623 { "xorS", { Evh1, Gv }, 0 },
2624 { "xorB", { Gb, EbS }, 0 },
2625 { "xorS", { Gv, EvS }, 0 },
2626 { "xorB", { AL, Ib }, 0 },
2627 { "xorS", { eAX, Iv }, 0 },
2628 { Bad_Opcode }, /* SEG SS prefix */
2629 { X86_64_TABLE (X86_64_37) },
2631 { "cmpB", { Eb, Gb }, 0 },
2632 { "cmpS", { Ev, Gv }, 0 },
2633 { "cmpB", { Gb, EbS }, 0 },
2634 { "cmpS", { Gv, EvS }, 0 },
2635 { "cmpB", { AL, Ib }, 0 },
2636 { "cmpS", { eAX, Iv }, 0 },
2637 { Bad_Opcode }, /* SEG DS prefix */
2638 { X86_64_TABLE (X86_64_3F) },
2640 { "inc{S|}", { RMeAX }, 0 },
2641 { "inc{S|}", { RMeCX }, 0 },
2642 { "inc{S|}", { RMeDX }, 0 },
2643 { "inc{S|}", { RMeBX }, 0 },
2644 { "inc{S|}", { RMeSP }, 0 },
2645 { "inc{S|}", { RMeBP }, 0 },
2646 { "inc{S|}", { RMeSI }, 0 },
2647 { "inc{S|}", { RMeDI }, 0 },
2649 { "dec{S|}", { RMeAX }, 0 },
2650 { "dec{S|}", { RMeCX }, 0 },
2651 { "dec{S|}", { RMeDX }, 0 },
2652 { "dec{S|}", { RMeBX }, 0 },
2653 { "dec{S|}", { RMeSP }, 0 },
2654 { "dec{S|}", { RMeBP }, 0 },
2655 { "dec{S|}", { RMeSI }, 0 },
2656 { "dec{S|}", { RMeDI }, 0 },
2658 { "pushV", { RMrAX }, 0 },
2659 { "pushV", { RMrCX }, 0 },
2660 { "pushV", { RMrDX }, 0 },
2661 { "pushV", { RMrBX }, 0 },
2662 { "pushV", { RMrSP }, 0 },
2663 { "pushV", { RMrBP }, 0 },
2664 { "pushV", { RMrSI }, 0 },
2665 { "pushV", { RMrDI }, 0 },
2667 { "popV", { RMrAX }, 0 },
2668 { "popV", { RMrCX }, 0 },
2669 { "popV", { RMrDX }, 0 },
2670 { "popV", { RMrBX }, 0 },
2671 { "popV", { RMrSP }, 0 },
2672 { "popV", { RMrBP }, 0 },
2673 { "popV", { RMrSI }, 0 },
2674 { "popV", { RMrDI }, 0 },
2676 { X86_64_TABLE (X86_64_60) },
2677 { X86_64_TABLE (X86_64_61) },
2678 { X86_64_TABLE (X86_64_62) },
2679 { X86_64_TABLE (X86_64_63) },
2680 { Bad_Opcode }, /* seg fs */
2681 { Bad_Opcode }, /* seg gs */
2682 { Bad_Opcode }, /* op size prefix */
2683 { Bad_Opcode }, /* adr size prefix */
2685 { "pushT", { sIv }, 0 },
2686 { "imulS", { Gv, Ev, Iv }, 0 },
2687 { "pushT", { sIbT }, 0 },
2688 { "imulS", { Gv, Ev, sIb }, 0 },
2689 { "ins{b|}", { Ybr, indirDX }, 0 },
2690 { X86_64_TABLE (X86_64_6D) },
2691 { "outs{b|}", { indirDXr, Xb }, 0 },
2692 { X86_64_TABLE (X86_64_6F) },
2694 { "joH", { Jb, BND, cond_jump_flag }, 0 },
2695 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
2696 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
2697 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
2698 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
2699 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
2700 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
2701 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
2703 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
2704 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
2705 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
2706 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
2707 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
2708 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
2709 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
2710 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
2712 { REG_TABLE (REG_80) },
2713 { REG_TABLE (REG_81) },
2714 { X86_64_TABLE (X86_64_82) },
2715 { REG_TABLE (REG_83) },
2716 { "testB", { Eb, Gb }, 0 },
2717 { "testS", { Ev, Gv }, 0 },
2718 { "xchgB", { Ebh2, Gb }, 0 },
2719 { "xchgS", { Evh2, Gv }, 0 },
2721 { "movB", { Ebh3, Gb }, 0 },
2722 { "movS", { Evh3, Gv }, 0 },
2723 { "movB", { Gb, EbS }, 0 },
2724 { "movS", { Gv, EvS }, 0 },
2725 { "movD", { Sv, Sw }, 0 },
2726 { MOD_TABLE (MOD_8D) },
2727 { "movD", { Sw, Sv }, 0 },
2728 { REG_TABLE (REG_8F) },
2730 { PREFIX_TABLE (PREFIX_90) },
2731 { "xchgS", { RMeCX, eAX }, 0 },
2732 { "xchgS", { RMeDX, eAX }, 0 },
2733 { "xchgS", { RMeBX, eAX }, 0 },
2734 { "xchgS", { RMeSP, eAX }, 0 },
2735 { "xchgS", { RMeBP, eAX }, 0 },
2736 { "xchgS", { RMeSI, eAX }, 0 },
2737 { "xchgS", { RMeDI, eAX }, 0 },
2739 { "cW{t|}R", { XX }, 0 },
2740 { "cR{t|}O", { XX }, 0 },
2741 { X86_64_TABLE (X86_64_9A) },
2742 { Bad_Opcode }, /* fwait */
2743 { "pushfT", { XX }, 0 },
2744 { "popfT", { XX }, 0 },
2745 { "sahf", { XX }, 0 },
2746 { "lahf", { XX }, 0 },
2748 { "mov%LB", { AL, Ob }, 0 },
2749 { "mov%LS", { eAX, Ov }, 0 },
2750 { "mov%LB", { Ob, AL }, 0 },
2751 { "mov%LS", { Ov, eAX }, 0 },
2752 { "movs{b|}", { Ybr, Xb }, 0 },
2753 { "movs{R|}", { Yvr, Xv }, 0 },
2754 { "cmps{b|}", { Xb, Yb }, 0 },
2755 { "cmps{R|}", { Xv, Yv }, 0 },
2757 { "testB", { AL, Ib }, 0 },
2758 { "testS", { eAX, Iv }, 0 },
2759 { "stosB", { Ybr, AL }, 0 },
2760 { "stosS", { Yvr, eAX }, 0 },
2761 { "lodsB", { ALr, Xb }, 0 },
2762 { "lodsS", { eAXr, Xv }, 0 },
2763 { "scasB", { AL, Yb }, 0 },
2764 { "scasS", { eAX, Yv }, 0 },
2766 { "movB", { RMAL, Ib }, 0 },
2767 { "movB", { RMCL, Ib }, 0 },
2768 { "movB", { RMDL, Ib }, 0 },
2769 { "movB", { RMBL, Ib }, 0 },
2770 { "movB", { RMAH, Ib }, 0 },
2771 { "movB", { RMCH, Ib }, 0 },
2772 { "movB", { RMDH, Ib }, 0 },
2773 { "movB", { RMBH, Ib }, 0 },
2775 { "mov%LV", { RMeAX, Iv64 }, 0 },
2776 { "mov%LV", { RMeCX, Iv64 }, 0 },
2777 { "mov%LV", { RMeDX, Iv64 }, 0 },
2778 { "mov%LV", { RMeBX, Iv64 }, 0 },
2779 { "mov%LV", { RMeSP, Iv64 }, 0 },
2780 { "mov%LV", { RMeBP, Iv64 }, 0 },
2781 { "mov%LV", { RMeSI, Iv64 }, 0 },
2782 { "mov%LV", { RMeDI, Iv64 }, 0 },
2784 { REG_TABLE (REG_C0) },
2785 { REG_TABLE (REG_C1) },
2786 { "retT", { Iw, BND }, 0 },
2787 { "retT", { BND }, 0 },
2788 { X86_64_TABLE (X86_64_C4) },
2789 { X86_64_TABLE (X86_64_C5) },
2790 { REG_TABLE (REG_C6) },
2791 { REG_TABLE (REG_C7) },
2793 { "enterT", { Iw, Ib }, 0 },
2794 { "leaveT", { XX }, 0 },
2795 { "Jret{|f}P", { Iw }, 0 },
2796 { "Jret{|f}P", { XX }, 0 },
2797 { "int3", { XX }, 0 },
2798 { "int", { Ib }, 0 },
2799 { X86_64_TABLE (X86_64_CE) },
2800 { "iret%LP", { XX }, 0 },
2802 { REG_TABLE (REG_D0) },
2803 { REG_TABLE (REG_D1) },
2804 { REG_TABLE (REG_D2) },
2805 { REG_TABLE (REG_D3) },
2806 { X86_64_TABLE (X86_64_D4) },
2807 { X86_64_TABLE (X86_64_D5) },
2809 { "xlat", { DSBX }, 0 },
2820 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2821 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2822 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2823 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2824 { "inB", { AL, Ib }, 0 },
2825 { "inG", { zAX, Ib }, 0 },
2826 { "outB", { Ib, AL }, 0 },
2827 { "outG", { Ib, zAX }, 0 },
2829 { X86_64_TABLE (X86_64_E8) },
2830 { X86_64_TABLE (X86_64_E9) },
2831 { X86_64_TABLE (X86_64_EA) },
2832 { "jmp", { Jb, BND }, 0 },
2833 { "inB", { AL, indirDX }, 0 },
2834 { "inG", { zAX, indirDX }, 0 },
2835 { "outB", { indirDX, AL }, 0 },
2836 { "outG", { indirDX, zAX }, 0 },
2838 { Bad_Opcode }, /* lock prefix */
2839 { "icebp", { XX }, 0 },
2840 { Bad_Opcode }, /* repne */
2841 { Bad_Opcode }, /* repz */
2842 { "hlt", { XX }, 0 },
2843 { "cmc", { XX }, 0 },
2844 { REG_TABLE (REG_F6) },
2845 { REG_TABLE (REG_F7) },
2847 { "clc", { XX }, 0 },
2848 { "stc", { XX }, 0 },
2849 { "cli", { XX }, 0 },
2850 { "sti", { XX }, 0 },
2851 { "cld", { XX }, 0 },
2852 { "std", { XX }, 0 },
2853 { REG_TABLE (REG_FE) },
2854 { REG_TABLE (REG_FF) },
2857 static const struct dis386 dis386_twobyte[] = {
2859 { REG_TABLE (REG_0F00 ) },
2860 { REG_TABLE (REG_0F01 ) },
2861 { "larS", { Gv, Ew }, 0 },
2862 { "lslS", { Gv, Ew }, 0 },
2864 { "syscall", { XX }, 0 },
2865 { "clts", { XX }, 0 },
2866 { "sysret%LP", { XX }, 0 },
2868 { "invd", { XX }, 0 },
2869 { "wbinvd", { XX }, 0 },
2871 { "ud2", { XX }, 0 },
2873 { REG_TABLE (REG_0F0D) },
2874 { "femms", { XX }, 0 },
2875 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2877 { PREFIX_TABLE (PREFIX_0F10) },
2878 { PREFIX_TABLE (PREFIX_0F11) },
2879 { PREFIX_TABLE (PREFIX_0F12) },
2880 { MOD_TABLE (MOD_0F13) },
2881 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2882 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2883 { PREFIX_TABLE (PREFIX_0F16) },
2884 { MOD_TABLE (MOD_0F17) },
2886 { REG_TABLE (REG_0F18) },
2887 { "nopQ", { Ev }, 0 },
2888 { PREFIX_TABLE (PREFIX_0F1A) },
2889 { PREFIX_TABLE (PREFIX_0F1B) },
2890 { "nopQ", { Ev }, 0 },
2891 { "nopQ", { Ev }, 0 },
2892 { PREFIX_TABLE (PREFIX_0F1E) },
2893 { "nopQ", { Ev }, 0 },
2895 { "movZ", { Rm, Cm }, 0 },
2896 { "movZ", { Rm, Dm }, 0 },
2897 { "movZ", { Cm, Rm }, 0 },
2898 { "movZ", { Dm, Rm }, 0 },
2899 { MOD_TABLE (MOD_0F24) },
2901 { MOD_TABLE (MOD_0F26) },
2904 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2905 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2906 { PREFIX_TABLE (PREFIX_0F2A) },
2907 { PREFIX_TABLE (PREFIX_0F2B) },
2908 { PREFIX_TABLE (PREFIX_0F2C) },
2909 { PREFIX_TABLE (PREFIX_0F2D) },
2910 { PREFIX_TABLE (PREFIX_0F2E) },
2911 { PREFIX_TABLE (PREFIX_0F2F) },
2913 { "wrmsr", { XX }, 0 },
2914 { "rdtsc", { XX }, 0 },
2915 { "rdmsr", { XX }, 0 },
2916 { "rdpmc", { XX }, 0 },
2917 { "sysenter", { XX }, 0 },
2918 { "sysexit", { XX }, 0 },
2920 { "getsec", { XX }, 0 },
2922 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2924 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2931 { "cmovoS", { Gv, Ev }, 0 },
2932 { "cmovnoS", { Gv, Ev }, 0 },
2933 { "cmovbS", { Gv, Ev }, 0 },
2934 { "cmovaeS", { Gv, Ev }, 0 },
2935 { "cmoveS", { Gv, Ev }, 0 },
2936 { "cmovneS", { Gv, Ev }, 0 },
2937 { "cmovbeS", { Gv, Ev }, 0 },
2938 { "cmovaS", { Gv, Ev }, 0 },
2940 { "cmovsS", { Gv, Ev }, 0 },
2941 { "cmovnsS", { Gv, Ev }, 0 },
2942 { "cmovpS", { Gv, Ev }, 0 },
2943 { "cmovnpS", { Gv, Ev }, 0 },
2944 { "cmovlS", { Gv, Ev }, 0 },
2945 { "cmovgeS", { Gv, Ev }, 0 },
2946 { "cmovleS", { Gv, Ev }, 0 },
2947 { "cmovgS", { Gv, Ev }, 0 },
2949 { MOD_TABLE (MOD_0F51) },
2950 { PREFIX_TABLE (PREFIX_0F51) },
2951 { PREFIX_TABLE (PREFIX_0F52) },
2952 { PREFIX_TABLE (PREFIX_0F53) },
2953 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2954 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2955 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2956 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2958 { PREFIX_TABLE (PREFIX_0F58) },
2959 { PREFIX_TABLE (PREFIX_0F59) },
2960 { PREFIX_TABLE (PREFIX_0F5A) },
2961 { PREFIX_TABLE (PREFIX_0F5B) },
2962 { PREFIX_TABLE (PREFIX_0F5C) },
2963 { PREFIX_TABLE (PREFIX_0F5D) },
2964 { PREFIX_TABLE (PREFIX_0F5E) },
2965 { PREFIX_TABLE (PREFIX_0F5F) },
2967 { PREFIX_TABLE (PREFIX_0F60) },
2968 { PREFIX_TABLE (PREFIX_0F61) },
2969 { PREFIX_TABLE (PREFIX_0F62) },
2970 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2971 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2972 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2973 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2974 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2976 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2977 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2978 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2979 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2980 { PREFIX_TABLE (PREFIX_0F6C) },
2981 { PREFIX_TABLE (PREFIX_0F6D) },
2982 { "movK", { MX, Edq }, PREFIX_OPCODE },
2983 { PREFIX_TABLE (PREFIX_0F6F) },
2985 { PREFIX_TABLE (PREFIX_0F70) },
2986 { REG_TABLE (REG_0F71) },
2987 { REG_TABLE (REG_0F72) },
2988 { REG_TABLE (REG_0F73) },
2989 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2990 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2991 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2992 { "emms", { XX }, PREFIX_OPCODE },
2994 { PREFIX_TABLE (PREFIX_0F78) },
2995 { PREFIX_TABLE (PREFIX_0F79) },
2998 { PREFIX_TABLE (PREFIX_0F7C) },
2999 { PREFIX_TABLE (PREFIX_0F7D) },
3000 { PREFIX_TABLE (PREFIX_0F7E) },
3001 { PREFIX_TABLE (PREFIX_0F7F) },
3003 { "joH", { Jv, BND, cond_jump_flag }, 0 },
3004 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
3005 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
3006 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
3007 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
3008 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
3009 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
3010 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
3012 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
3013 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
3014 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
3015 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
3016 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
3017 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
3018 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
3019 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
3021 { "seto", { Eb }, 0 },
3022 { "setno", { Eb }, 0 },
3023 { "setb", { Eb }, 0 },
3024 { "setae", { Eb }, 0 },
3025 { "sete", { Eb }, 0 },
3026 { "setne", { Eb }, 0 },
3027 { "setbe", { Eb }, 0 },
3028 { "seta", { Eb }, 0 },
3030 { "sets", { Eb }, 0 },
3031 { "setns", { Eb }, 0 },
3032 { "setp", { Eb }, 0 },
3033 { "setnp", { Eb }, 0 },
3034 { "setl", { Eb }, 0 },
3035 { "setge", { Eb }, 0 },
3036 { "setle", { Eb }, 0 },
3037 { "setg", { Eb }, 0 },
3039 { "pushT", { fs }, 0 },
3040 { "popT", { fs }, 0 },
3041 { "cpuid", { XX }, 0 },
3042 { "btS", { Ev, Gv }, 0 },
3043 { "shldS", { Ev, Gv, Ib }, 0 },
3044 { "shldS", { Ev, Gv, CL }, 0 },
3045 { REG_TABLE (REG_0FA6) },
3046 { REG_TABLE (REG_0FA7) },
3048 { "pushT", { gs }, 0 },
3049 { "popT", { gs }, 0 },
3050 { "rsm", { XX }, 0 },
3051 { "btsS", { Evh1, Gv }, 0 },
3052 { "shrdS", { Ev, Gv, Ib }, 0 },
3053 { "shrdS", { Ev, Gv, CL }, 0 },
3054 { REG_TABLE (REG_0FAE) },
3055 { "imulS", { Gv, Ev }, 0 },
3057 { "cmpxchgB", { Ebh1, Gb }, 0 },
3058 { "cmpxchgS", { Evh1, Gv }, 0 },
3059 { MOD_TABLE (MOD_0FB2) },
3060 { "btrS", { Evh1, Gv }, 0 },
3061 { MOD_TABLE (MOD_0FB4) },
3062 { MOD_TABLE (MOD_0FB5) },
3063 { "movz{bR|x}", { Gv, Eb }, 0 },
3064 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3066 { PREFIX_TABLE (PREFIX_0FB8) },
3067 { "ud1", { XX }, 0 },
3068 { REG_TABLE (REG_0FBA) },
3069 { "btcS", { Evh1, Gv }, 0 },
3070 { PREFIX_TABLE (PREFIX_0FBC) },
3071 { PREFIX_TABLE (PREFIX_0FBD) },
3072 { "movs{bR|x}", { Gv, Eb }, 0 },
3073 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3075 { "xaddB", { Ebh1, Gb }, 0 },
3076 { "xaddS", { Evh1, Gv }, 0 },
3077 { PREFIX_TABLE (PREFIX_0FC2) },
3078 { MOD_TABLE (MOD_0FC3) },
3079 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
3080 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
3081 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
3082 { REG_TABLE (REG_0FC7) },
3084 { "bswap", { RMeAX }, 0 },
3085 { "bswap", { RMeCX }, 0 },
3086 { "bswap", { RMeDX }, 0 },
3087 { "bswap", { RMeBX }, 0 },
3088 { "bswap", { RMeSP }, 0 },
3089 { "bswap", { RMeBP }, 0 },
3090 { "bswap", { RMeSI }, 0 },
3091 { "bswap", { RMeDI }, 0 },
3093 { PREFIX_TABLE (PREFIX_0FD0) },
3094 { "psrlw", { MX, EM }, PREFIX_OPCODE },
3095 { "psrld", { MX, EM }, PREFIX_OPCODE },
3096 { "psrlq", { MX, EM }, PREFIX_OPCODE },
3097 { "paddq", { MX, EM }, PREFIX_OPCODE },
3098 { "pmullw", { MX, EM }, PREFIX_OPCODE },
3099 { PREFIX_TABLE (PREFIX_0FD6) },
3100 { MOD_TABLE (MOD_0FD7) },
3102 { "psubusb", { MX, EM }, PREFIX_OPCODE },
3103 { "psubusw", { MX, EM }, PREFIX_OPCODE },
3104 { "pminub", { MX, EM }, PREFIX_OPCODE },
3105 { "pand", { MX, EM }, PREFIX_OPCODE },
3106 { "paddusb", { MX, EM }, PREFIX_OPCODE },
3107 { "paddusw", { MX, EM }, PREFIX_OPCODE },
3108 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
3109 { "pandn", { MX, EM }, PREFIX_OPCODE },
3111 { "pavgb", { MX, EM }, PREFIX_OPCODE },
3112 { "psraw", { MX, EM }, PREFIX_OPCODE },
3113 { "psrad", { MX, EM }, PREFIX_OPCODE },
3114 { "pavgw", { MX, EM }, PREFIX_OPCODE },
3115 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
3116 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
3117 { PREFIX_TABLE (PREFIX_0FE6) },
3118 { PREFIX_TABLE (PREFIX_0FE7) },
3120 { "psubsb", { MX, EM }, PREFIX_OPCODE },
3121 { "psubsw", { MX, EM }, PREFIX_OPCODE },
3122 { "pminsw", { MX, EM }, PREFIX_OPCODE },
3123 { "por", { MX, EM }, PREFIX_OPCODE },
3124 { "paddsb", { MX, EM }, PREFIX_OPCODE },
3125 { "paddsw", { MX, EM }, PREFIX_OPCODE },
3126 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
3127 { "pxor", { MX, EM }, PREFIX_OPCODE },
3129 { PREFIX_TABLE (PREFIX_0FF0) },
3130 { "psllw", { MX, EM }, PREFIX_OPCODE },
3131 { "pslld", { MX, EM }, PREFIX_OPCODE },
3132 { "psllq", { MX, EM }, PREFIX_OPCODE },
3133 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
3134 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
3135 { "psadbw", { MX, EM }, PREFIX_OPCODE },
3136 { PREFIX_TABLE (PREFIX_0FF7) },
3138 { "psubb", { MX, EM }, PREFIX_OPCODE },
3139 { "psubw", { MX, EM }, PREFIX_OPCODE },
3140 { "psubd", { MX, EM }, PREFIX_OPCODE },
3141 { "psubq", { MX, EM }, PREFIX_OPCODE },
3142 { "paddb", { MX, EM }, PREFIX_OPCODE },
3143 { "paddw", { MX, EM }, PREFIX_OPCODE },
3144 { "paddd", { MX, EM }, PREFIX_OPCODE },
3148 static const unsigned char onebyte_has_modrm[256] = {
3149 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3150 /* ------------------------------- */
3151 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3152 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3153 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3154 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3155 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3156 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3157 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3158 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3159 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3160 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3161 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3162 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3163 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3164 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3165 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3166 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3167 /* ------------------------------- */
3168 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3171 static const unsigned char twobyte_has_modrm[256] = {
3172 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3173 /* ------------------------------- */
3174 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3175 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3176 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3177 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3178 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3179 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3180 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3181 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3182 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3183 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3184 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3185 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3186 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3187 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3188 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3189 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3190 /* ------------------------------- */
3191 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3194 static char obuf[100];
3196 static char *mnemonicendp;
3197 static char scratchbuf[100];
3198 static unsigned char *start_codep;
3199 static unsigned char *insn_codep;
3200 static unsigned char *codep;
3201 static unsigned char *end_codep;
3202 static int last_lock_prefix;
3203 static int last_repz_prefix;
3204 static int last_repnz_prefix;
3205 static int last_data_prefix;
3206 static int last_addr_prefix;
3207 static int last_rex_prefix;
3208 static int last_seg_prefix;
3209 static int fwait_prefix;
3210 /* The active segment register prefix. */
3211 static int active_seg_prefix;
3212 #define MAX_CODE_LENGTH 15
3213 /* We can up to 14 prefixes since the maximum instruction length is
3215 static int all_prefixes[MAX_CODE_LENGTH - 1];
3216 static disassemble_info *the_info;
3224 static unsigned char need_modrm;
3234 int register_specifier;
3241 int mask_register_specifier;
3247 static unsigned char need_vex;
3248 static unsigned char need_vex_reg;
3249 static unsigned char vex_w_done;
3257 /* If we are accessing mod/rm/reg without need_modrm set, then the
3258 values are stale. Hitting this abort likely indicates that you
3259 need to update onebyte_has_modrm or twobyte_has_modrm. */
3260 #define MODRM_CHECK if (!need_modrm) abort ()
3262 static const char **names64;
3263 static const char **names32;
3264 static const char **names16;
3265 static const char **names8;
3266 static const char **names8rex;
3267 static const char **names_seg;
3268 static const char *index64;
3269 static const char *index32;
3270 static const char **index16;
3271 static const char **names_bnd;
3273 static const char *intel_names64[] = {
3274 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3275 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3277 static const char *intel_names32[] = {
3278 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3279 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3281 static const char *intel_names16[] = {
3282 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3283 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3285 static const char *intel_names8[] = {
3286 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3288 static const char *intel_names8rex[] = {
3289 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3290 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3292 static const char *intel_names_seg[] = {
3293 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3295 static const char *intel_index64 = "riz";
3296 static const char *intel_index32 = "eiz";
3297 static const char *intel_index16[] = {
3298 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3301 static const char *att_names64[] = {
3302 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3303 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3305 static const char *att_names32[] = {
3306 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3307 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3309 static const char *att_names16[] = {
3310 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3311 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3313 static const char *att_names8[] = {
3314 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3316 static const char *att_names8rex[] = {
3317 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3318 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3320 static const char *att_names_seg[] = {
3321 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3323 static const char *att_index64 = "%riz";
3324 static const char *att_index32 = "%eiz";
3325 static const char *att_index16[] = {
3326 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3329 static const char **names_mm;
3330 static const char *intel_names_mm[] = {
3331 "mm0", "mm1", "mm2", "mm3",
3332 "mm4", "mm5", "mm6", "mm7"
3334 static const char *att_names_mm[] = {
3335 "%mm0", "%mm1", "%mm2", "%mm3",
3336 "%mm4", "%mm5", "%mm6", "%mm7"
3339 static const char *intel_names_bnd[] = {
3340 "bnd0", "bnd1", "bnd2", "bnd3"
3343 static const char *att_names_bnd[] = {
3344 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3347 static const char **names_xmm;
3348 static const char *intel_names_xmm[] = {
3349 "xmm0", "xmm1", "xmm2", "xmm3",
3350 "xmm4", "xmm5", "xmm6", "xmm7",
3351 "xmm8", "xmm9", "xmm10", "xmm11",
3352 "xmm12", "xmm13", "xmm14", "xmm15",
3353 "xmm16", "xmm17", "xmm18", "xmm19",
3354 "xmm20", "xmm21", "xmm22", "xmm23",
3355 "xmm24", "xmm25", "xmm26", "xmm27",
3356 "xmm28", "xmm29", "xmm30", "xmm31"
3358 static const char *att_names_xmm[] = {
3359 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3360 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3361 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3362 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3363 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3364 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3365 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3366 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3369 static const char **names_ymm;
3370 static const char *intel_names_ymm[] = {
3371 "ymm0", "ymm1", "ymm2", "ymm3",
3372 "ymm4", "ymm5", "ymm6", "ymm7",
3373 "ymm8", "ymm9", "ymm10", "ymm11",
3374 "ymm12", "ymm13", "ymm14", "ymm15",
3375 "ymm16", "ymm17", "ymm18", "ymm19",
3376 "ymm20", "ymm21", "ymm22", "ymm23",
3377 "ymm24", "ymm25", "ymm26", "ymm27",
3378 "ymm28", "ymm29", "ymm30", "ymm31"
3380 static const char *att_names_ymm[] = {
3381 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3382 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3383 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3384 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3385 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3386 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3387 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3388 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3391 static const char **names_zmm;
3392 static const char *intel_names_zmm[] = {
3393 "zmm0", "zmm1", "zmm2", "zmm3",
3394 "zmm4", "zmm5", "zmm6", "zmm7",
3395 "zmm8", "zmm9", "zmm10", "zmm11",
3396 "zmm12", "zmm13", "zmm14", "zmm15",
3397 "zmm16", "zmm17", "zmm18", "zmm19",
3398 "zmm20", "zmm21", "zmm22", "zmm23",
3399 "zmm24", "zmm25", "zmm26", "zmm27",
3400 "zmm28", "zmm29", "zmm30", "zmm31"
3402 static const char *att_names_zmm[] = {
3403 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3404 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3405 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3406 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3407 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3408 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3409 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3410 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3413 static const char **names_mask;
3414 static const char *intel_names_mask[] = {
3415 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3417 static const char *att_names_mask[] = {
3418 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3421 static const char *names_rounding[] =
3429 static const struct dis386 reg_table[][8] = {
3432 { "addA", { Ebh1, Ib }, 0 },
3433 { "orA", { Ebh1, Ib }, 0 },
3434 { "adcA", { Ebh1, Ib }, 0 },
3435 { "sbbA", { Ebh1, Ib }, 0 },
3436 { "andA", { Ebh1, Ib }, 0 },
3437 { "subA", { Ebh1, Ib }, 0 },
3438 { "xorA", { Ebh1, Ib }, 0 },
3439 { "cmpA", { Eb, Ib }, 0 },
3443 { "addQ", { Evh1, Iv }, 0 },
3444 { "orQ", { Evh1, Iv }, 0 },
3445 { "adcQ", { Evh1, Iv }, 0 },
3446 { "sbbQ", { Evh1, Iv }, 0 },
3447 { "andQ", { Evh1, Iv }, 0 },
3448 { "subQ", { Evh1, Iv }, 0 },
3449 { "xorQ", { Evh1, Iv }, 0 },
3450 { "cmpQ", { Ev, Iv }, 0 },
3454 { "addQ", { Evh1, sIb }, 0 },
3455 { "orQ", { Evh1, sIb }, 0 },
3456 { "adcQ", { Evh1, sIb }, 0 },
3457 { "sbbQ", { Evh1, sIb }, 0 },
3458 { "andQ", { Evh1, sIb }, 0 },
3459 { "subQ", { Evh1, sIb }, 0 },
3460 { "xorQ", { Evh1, sIb }, 0 },
3461 { "cmpQ", { Ev, sIb }, 0 },
3465 { "popU", { stackEv }, 0 },
3466 { XOP_8F_TABLE (XOP_09) },
3470 { XOP_8F_TABLE (XOP_09) },
3474 { "rolA", { Eb, Ib }, 0 },
3475 { "rorA", { Eb, Ib }, 0 },
3476 { "rclA", { Eb, Ib }, 0 },
3477 { "rcrA", { Eb, Ib }, 0 },
3478 { "shlA", { Eb, Ib }, 0 },
3479 { "shrA", { Eb, Ib }, 0 },
3480 { "shlA", { Eb, Ib }, 0 },
3481 { "sarA", { Eb, Ib }, 0 },
3485 { "rolQ", { Ev, Ib }, 0 },
3486 { "rorQ", { Ev, Ib }, 0 },
3487 { "rclQ", { Ev, Ib }, 0 },
3488 { "rcrQ", { Ev, Ib }, 0 },
3489 { "shlQ", { Ev, Ib }, 0 },
3490 { "shrQ", { Ev, Ib }, 0 },
3491 { "shlQ", { Ev, Ib }, 0 },
3492 { "sarQ", { Ev, Ib }, 0 },
3496 { "movA", { Ebh3, Ib }, 0 },
3503 { MOD_TABLE (MOD_C6_REG_7) },
3507 { "movQ", { Evh3, Iv }, 0 },
3514 { MOD_TABLE (MOD_C7_REG_7) },
3518 { "rolA", { Eb, I1 }, 0 },
3519 { "rorA", { Eb, I1 }, 0 },
3520 { "rclA", { Eb, I1 }, 0 },
3521 { "rcrA", { Eb, I1 }, 0 },
3522 { "shlA", { Eb, I1 }, 0 },
3523 { "shrA", { Eb, I1 }, 0 },
3524 { "shlA", { Eb, I1 }, 0 },
3525 { "sarA", { Eb, I1 }, 0 },
3529 { "rolQ", { Ev, I1 }, 0 },
3530 { "rorQ", { Ev, I1 }, 0 },
3531 { "rclQ", { Ev, I1 }, 0 },
3532 { "rcrQ", { Ev, I1 }, 0 },
3533 { "shlQ", { Ev, I1 }, 0 },
3534 { "shrQ", { Ev, I1 }, 0 },
3535 { "shlQ", { Ev, I1 }, 0 },
3536 { "sarQ", { Ev, I1 }, 0 },
3540 { "rolA", { Eb, CL }, 0 },
3541 { "rorA", { Eb, CL }, 0 },
3542 { "rclA", { Eb, CL }, 0 },
3543 { "rcrA", { Eb, CL }, 0 },
3544 { "shlA", { Eb, CL }, 0 },
3545 { "shrA", { Eb, CL }, 0 },
3546 { "shlA", { Eb, CL }, 0 },
3547 { "sarA", { Eb, CL }, 0 },
3551 { "rolQ", { Ev, CL }, 0 },
3552 { "rorQ", { Ev, CL }, 0 },
3553 { "rclQ", { Ev, CL }, 0 },
3554 { "rcrQ", { Ev, CL }, 0 },
3555 { "shlQ", { Ev, CL }, 0 },
3556 { "shrQ", { Ev, CL }, 0 },
3557 { "shlQ", { Ev, CL }, 0 },
3558 { "sarQ", { Ev, CL }, 0 },
3562 { "testA", { Eb, Ib }, 0 },
3563 { "testA", { Eb, Ib }, 0 },
3564 { "notA", { Ebh1 }, 0 },
3565 { "negA", { Ebh1 }, 0 },
3566 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
3567 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
3568 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
3569 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
3573 { "testQ", { Ev, Iv }, 0 },
3574 { "testQ", { Ev, Iv }, 0 },
3575 { "notQ", { Evh1 }, 0 },
3576 { "negQ", { Evh1 }, 0 },
3577 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
3578 { "imulQ", { Ev }, 0 },
3579 { "divQ", { Ev }, 0 },
3580 { "idivQ", { Ev }, 0 },
3584 { "incA", { Ebh1 }, 0 },
3585 { "decA", { Ebh1 }, 0 },
3589 { "incQ", { Evh1 }, 0 },
3590 { "decQ", { Evh1 }, 0 },
3591 { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3592 { MOD_TABLE (MOD_FF_REG_3) },
3593 { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3594 { MOD_TABLE (MOD_FF_REG_5) },
3595 { "pushU", { stackEv }, 0 },
3600 { "sldtD", { Sv }, 0 },
3601 { "strD", { Sv }, 0 },
3602 { "lldt", { Ew }, 0 },
3603 { "ltr", { Ew }, 0 },
3604 { "verr", { Ew }, 0 },
3605 { "verw", { Ew }, 0 },
3611 { MOD_TABLE (MOD_0F01_REG_0) },
3612 { MOD_TABLE (MOD_0F01_REG_1) },
3613 { MOD_TABLE (MOD_0F01_REG_2) },
3614 { MOD_TABLE (MOD_0F01_REG_3) },
3615 { "smswD", { Sv }, 0 },
3616 { MOD_TABLE (MOD_0F01_REG_5) },
3617 { "lmsw", { Ew }, 0 },
3618 { MOD_TABLE (MOD_0F01_REG_7) },
3622 { "prefetch", { Mb }, 0 },
3623 { "prefetchw", { Mb }, 0 },
3624 { "prefetchwt1", { Mb }, 0 },
3625 { "prefetch", { Mb }, 0 },
3626 { "prefetch", { Mb }, 0 },
3627 { "prefetch", { Mb }, 0 },
3628 { "prefetch", { Mb }, 0 },
3629 { "prefetch", { Mb }, 0 },
3633 { MOD_TABLE (MOD_0F18_REG_0) },
3634 { MOD_TABLE (MOD_0F18_REG_1) },
3635 { MOD_TABLE (MOD_0F18_REG_2) },
3636 { MOD_TABLE (MOD_0F18_REG_3) },
3637 { MOD_TABLE (MOD_0F18_REG_4) },
3638 { MOD_TABLE (MOD_0F18_REG_5) },
3639 { MOD_TABLE (MOD_0F18_REG_6) },
3640 { MOD_TABLE (MOD_0F18_REG_7) },
3642 /* REG_0F1E_MOD_3 */
3644 { "nopQ", { Ev }, 0 },
3645 { "rdsspK", { Rdq }, PREFIX_OPCODE },
3646 { "nopQ", { Ev }, 0 },
3647 { "nopQ", { Ev }, 0 },
3648 { "nopQ", { Ev }, 0 },
3649 { "nopQ", { Ev }, 0 },
3650 { "nopQ", { Ev }, 0 },
3651 { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3657 { MOD_TABLE (MOD_0F71_REG_2) },
3659 { MOD_TABLE (MOD_0F71_REG_4) },
3661 { MOD_TABLE (MOD_0F71_REG_6) },
3667 { MOD_TABLE (MOD_0F72_REG_2) },
3669 { MOD_TABLE (MOD_0F72_REG_4) },
3671 { MOD_TABLE (MOD_0F72_REG_6) },
3677 { MOD_TABLE (MOD_0F73_REG_2) },
3678 { MOD_TABLE (MOD_0F73_REG_3) },
3681 { MOD_TABLE (MOD_0F73_REG_6) },
3682 { MOD_TABLE (MOD_0F73_REG_7) },
3686 { "montmul", { { OP_0f07, 0 } }, 0 },
3687 { "xsha1", { { OP_0f07, 0 } }, 0 },
3688 { "xsha256", { { OP_0f07, 0 } }, 0 },
3692 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
3693 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
3694 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
3695 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
3696 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
3697 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
3701 { MOD_TABLE (MOD_0FAE_REG_0) },
3702 { MOD_TABLE (MOD_0FAE_REG_1) },
3703 { MOD_TABLE (MOD_0FAE_REG_2) },
3704 { MOD_TABLE (MOD_0FAE_REG_3) },
3705 { MOD_TABLE (MOD_0FAE_REG_4) },
3706 { MOD_TABLE (MOD_0FAE_REG_5) },
3707 { MOD_TABLE (MOD_0FAE_REG_6) },
3708 { MOD_TABLE (MOD_0FAE_REG_7) },
3716 { "btQ", { Ev, Ib }, 0 },
3717 { "btsQ", { Evh1, Ib }, 0 },
3718 { "btrQ", { Evh1, Ib }, 0 },
3719 { "btcQ", { Evh1, Ib }, 0 },
3724 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3726 { MOD_TABLE (MOD_0FC7_REG_3) },
3727 { MOD_TABLE (MOD_0FC7_REG_4) },
3728 { MOD_TABLE (MOD_0FC7_REG_5) },
3729 { MOD_TABLE (MOD_0FC7_REG_6) },
3730 { MOD_TABLE (MOD_0FC7_REG_7) },
3736 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3738 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3740 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3746 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3748 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3750 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3756 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3757 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3760 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3761 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3767 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3768 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3770 /* REG_VEX_0F38F3 */
3773 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3774 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3775 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3779 { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3780 { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3784 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3785 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3787 /* REG_XOP_TBM_01 */
3790 { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3791 { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3792 { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 },
3793 { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3794 { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 },
3795 { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 },
3796 { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3798 /* REG_XOP_TBM_02 */
3801 { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3806 { "blci", { { OP_LWP_E, 0 }, Ev }, 0 },
3808 #define NEED_REG_TABLE
3809 #include "i386-dis-evex.h"
3810 #undef NEED_REG_TABLE
3813 static const struct dis386 prefix_table[][4] = {
3816 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3817 { "pause", { XX }, 0 },
3818 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3819 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3822 /* PREFIX_MOD_0_0F01_REG_5 */
3825 { "rstorssp", { Mq }, PREFIX_OPCODE },
3828 /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3831 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3834 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3837 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3842 { "movups", { XM, EXx }, PREFIX_OPCODE },
3843 { "movss", { XM, EXd }, PREFIX_OPCODE },
3844 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3845 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3850 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3851 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3852 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3853 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3858 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3859 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3860 { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3861 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3866 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3867 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3868 { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3873 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3874 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3875 { "bndmov", { Gbnd, Ebnd }, 0 },
3876 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3881 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3882 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3883 { "bndmov", { Ebnd, Gbnd }, 0 },
3884 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3889 { "nopQ", { Ev }, PREFIX_OPCODE },
3890 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3891 { "nopQ", { Ev }, PREFIX_OPCODE },
3892 { "nopQ", { Ev }, PREFIX_OPCODE },
3897 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3898 { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3899 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3900 { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3905 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3906 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3907 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3908 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3913 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3914 { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3915 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3916 { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3921 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3922 { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3923 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3924 { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3929 { "ucomiss",{ XM, EXd }, 0 },
3931 { "ucomisd",{ XM, EXq }, 0 },
3936 { "comiss", { XM, EXd }, 0 },
3938 { "comisd", { XM, EXq }, 0 },
3943 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3944 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3945 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3946 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3951 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3952 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3957 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3958 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3963 { "addps", { XM, EXx }, PREFIX_OPCODE },
3964 { "addss", { XM, EXd }, PREFIX_OPCODE },
3965 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3966 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3971 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3972 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3973 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3974 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3979 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3980 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3981 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3982 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3987 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3988 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3989 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3994 { "subps", { XM, EXx }, PREFIX_OPCODE },
3995 { "subss", { XM, EXd }, PREFIX_OPCODE },
3996 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3997 { "subsd", { XM, EXq }, PREFIX_OPCODE },
4002 { "minps", { XM, EXx }, PREFIX_OPCODE },
4003 { "minss", { XM, EXd }, PREFIX_OPCODE },
4004 { "minpd", { XM, EXx }, PREFIX_OPCODE },
4005 { "minsd", { XM, EXq }, PREFIX_OPCODE },
4010 { "divps", { XM, EXx }, PREFIX_OPCODE },
4011 { "divss", { XM, EXd }, PREFIX_OPCODE },
4012 { "divpd", { XM, EXx }, PREFIX_OPCODE },
4013 { "divsd", { XM, EXq }, PREFIX_OPCODE },
4018 { "maxps", { XM, EXx }, PREFIX_OPCODE },
4019 { "maxss", { XM, EXd }, PREFIX_OPCODE },
4020 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
4021 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
4026 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
4028 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
4033 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
4035 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
4040 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
4042 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
4049 { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
4056 { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
4061 { "movq", { MX, EM }, PREFIX_OPCODE },
4062 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
4063 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4068 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4069 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4070 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4071 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4074 /* PREFIX_0F73_REG_3 */
4078 { "psrldq", { XS, Ib }, 0 },
4081 /* PREFIX_0F73_REG_7 */
4085 { "pslldq", { XS, Ib }, 0 },
4090 {"vmread", { Em, Gm }, 0 },
4092 {"extrq", { XS, Ib, Ib }, 0 },
4093 {"insertq", { XM, XS, Ib, Ib }, 0 },
4098 {"vmwrite", { Gm, Em }, 0 },
4100 {"extrq", { XM, XS }, 0 },
4101 {"insertq", { XM, XS }, 0 },
4108 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4109 { "haddps", { XM, EXx }, PREFIX_OPCODE },
4116 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4117 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4122 { "movK", { Edq, MX }, PREFIX_OPCODE },
4123 { "movq", { XM, EXq }, PREFIX_OPCODE },
4124 { "movK", { Edq, XM }, PREFIX_OPCODE },
4129 { "movq", { EMS, MX }, PREFIX_OPCODE },
4130 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4131 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4134 /* PREFIX_0FAE_REG_0 */
4137 { "rdfsbase", { Ev }, 0 },
4140 /* PREFIX_0FAE_REG_1 */
4143 { "rdgsbase", { Ev }, 0 },
4146 /* PREFIX_0FAE_REG_2 */
4149 { "wrfsbase", { Ev }, 0 },
4152 /* PREFIX_0FAE_REG_3 */
4155 { "wrgsbase", { Ev }, 0 },
4158 /* PREFIX_MOD_0_0FAE_REG_4 */
4160 { "xsave", { FXSAVE }, 0 },
4161 { "ptwrite%LQ", { Edq }, 0 },
4164 /* PREFIX_MOD_3_0FAE_REG_4 */
4167 { "ptwrite%LQ", { Edq }, 0 },
4170 /* PREFIX_MOD_0_0FAE_REG_5 */
4172 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
4175 /* PREFIX_MOD_3_0FAE_REG_5 */
4177 { "lfence", { Skip_MODRM }, 0 },
4178 { "incsspK", { Rdq }, PREFIX_OPCODE },
4181 /* PREFIX_0FAE_REG_6 */
4183 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
4184 { "clrssbsy", { Mq }, PREFIX_OPCODE },
4185 { "clwb", { Mb }, PREFIX_OPCODE },
4188 /* PREFIX_0FAE_REG_7 */
4190 { "clflush", { Mb }, 0 },
4192 { "clflushopt", { Mb }, 0 },
4198 { "popcntS", { Gv, Ev }, 0 },
4203 { "bsfS", { Gv, Ev }, 0 },
4204 { "tzcntS", { Gv, Ev }, 0 },
4205 { "bsfS", { Gv, Ev }, 0 },
4210 { "bsrS", { Gv, Ev }, 0 },
4211 { "lzcntS", { Gv, Ev }, 0 },
4212 { "bsrS", { Gv, Ev }, 0 },
4217 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
4218 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
4219 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
4220 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
4223 /* PREFIX_MOD_0_0FC3 */
4225 { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4228 /* PREFIX_MOD_0_0FC7_REG_6 */
4230 { "vmptrld",{ Mq }, 0 },
4231 { "vmxon", { Mq }, 0 },
4232 { "vmclear",{ Mq }, 0 },
4235 /* PREFIX_MOD_3_0FC7_REG_6 */
4237 { "rdrand", { Ev }, 0 },
4239 { "rdrand", { Ev }, 0 }
4242 /* PREFIX_MOD_3_0FC7_REG_7 */
4244 { "rdseed", { Ev }, 0 },
4245 { "rdpid", { Em }, 0 },
4246 { "rdseed", { Ev }, 0 },
4253 { "addsubpd", { XM, EXx }, 0 },
4254 { "addsubps", { XM, EXx }, 0 },
4260 { "movq2dq",{ XM, MS }, 0 },
4261 { "movq", { EXqS, XM }, 0 },
4262 { "movdq2q",{ MX, XS }, 0 },
4268 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4269 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4270 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4275 { "movntq", { Mq, MX }, PREFIX_OPCODE },
4277 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4285 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4290 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4292 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4299 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4306 { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4313 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4320 { "ptest", { XM, EXx }, PREFIX_OPCODE },
4327 { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4334 { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4341 { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4348 { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4355 { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4362 { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4369 { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4376 { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4383 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4390 { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4397 { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4404 { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4411 { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4418 { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4425 { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4432 { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4439 { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4446 { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4453 { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4460 { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4467 { "pminud", { XM, EXx }, PREFIX_OPCODE },
4474 { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4481 { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4488 { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4495 { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4502 { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4509 { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4516 { "invept", { Gm, Mo }, PREFIX_OPCODE },
4523 { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4530 { "invpcid", { Gm, M }, PREFIX_OPCODE },
4535 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4540 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4545 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4550 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4555 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4560 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4567 { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4574 { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4581 { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4588 { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4595 { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4602 { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4607 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4609 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4610 { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4615 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4617 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4618 { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4625 { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4630 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4631 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
4632 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
4640 { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4647 { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4654 { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4661 { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4668 { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4675 { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4682 { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4689 { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4696 { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4703 { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4710 { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4717 { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4724 { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4731 { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4738 { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE },
4745 { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE },
4752 { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4759 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4766 { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4773 { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4780 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4787 { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4792 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4799 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4806 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4813 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4816 /* PREFIX_VEX_0F10 */
4818 { VEX_W_TABLE (VEX_W_0F10_P_0) },
4819 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4820 { VEX_W_TABLE (VEX_W_0F10_P_2) },
4821 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4824 /* PREFIX_VEX_0F11 */
4826 { VEX_W_TABLE (VEX_W_0F11_P_0) },
4827 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4828 { VEX_W_TABLE (VEX_W_0F11_P_2) },
4829 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4832 /* PREFIX_VEX_0F12 */
4834 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4835 { VEX_W_TABLE (VEX_W_0F12_P_1) },
4836 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4837 { VEX_W_TABLE (VEX_W_0F12_P_3) },
4840 /* PREFIX_VEX_0F16 */
4842 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4843 { VEX_W_TABLE (VEX_W_0F16_P_1) },
4844 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4847 /* PREFIX_VEX_0F2A */
4850 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4852 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4855 /* PREFIX_VEX_0F2C */
4858 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4860 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4863 /* PREFIX_VEX_0F2D */
4866 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4868 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4871 /* PREFIX_VEX_0F2E */
4873 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4875 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4878 /* PREFIX_VEX_0F2F */
4880 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4882 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4885 /* PREFIX_VEX_0F41 */
4887 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4889 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4892 /* PREFIX_VEX_0F42 */
4894 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4896 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4899 /* PREFIX_VEX_0F44 */
4901 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4903 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4906 /* PREFIX_VEX_0F45 */
4908 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4910 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4913 /* PREFIX_VEX_0F46 */
4915 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4917 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4920 /* PREFIX_VEX_0F47 */
4922 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4924 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4927 /* PREFIX_VEX_0F4A */
4929 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4931 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4934 /* PREFIX_VEX_0F4B */
4936 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4938 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4941 /* PREFIX_VEX_0F51 */
4943 { VEX_W_TABLE (VEX_W_0F51_P_0) },
4944 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4945 { VEX_W_TABLE (VEX_W_0F51_P_2) },
4946 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4949 /* PREFIX_VEX_0F52 */
4951 { VEX_W_TABLE (VEX_W_0F52_P_0) },
4952 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4955 /* PREFIX_VEX_0F53 */
4957 { VEX_W_TABLE (VEX_W_0F53_P_0) },
4958 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4961 /* PREFIX_VEX_0F58 */
4963 { VEX_W_TABLE (VEX_W_0F58_P_0) },
4964 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4965 { VEX_W_TABLE (VEX_W_0F58_P_2) },
4966 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4969 /* PREFIX_VEX_0F59 */
4971 { VEX_W_TABLE (VEX_W_0F59_P_0) },
4972 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4973 { VEX_W_TABLE (VEX_W_0F59_P_2) },
4974 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4977 /* PREFIX_VEX_0F5A */
4979 { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4980 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4981 { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4982 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4985 /* PREFIX_VEX_0F5B */
4987 { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4988 { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4989 { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4992 /* PREFIX_VEX_0F5C */
4994 { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4995 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4996 { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4997 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
5000 /* PREFIX_VEX_0F5D */
5002 { VEX_W_TABLE (VEX_W_0F5D_P_0) },
5003 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
5004 { VEX_W_TABLE (VEX_W_0F5D_P_2) },
5005 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
5008 /* PREFIX_VEX_0F5E */
5010 { VEX_W_TABLE (VEX_W_0F5E_P_0) },
5011 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
5012 { VEX_W_TABLE (VEX_W_0F5E_P_2) },
5013 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
5016 /* PREFIX_VEX_0F5F */
5018 { VEX_W_TABLE (VEX_W_0F5F_P_0) },
5019 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
5020 { VEX_W_TABLE (VEX_W_0F5F_P_2) },
5021 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
5024 /* PREFIX_VEX_0F60 */
5028 { VEX_W_TABLE (VEX_W_0F60_P_2) },
5031 /* PREFIX_VEX_0F61 */
5035 { VEX_W_TABLE (VEX_W_0F61_P_2) },
5038 /* PREFIX_VEX_0F62 */
5042 { VEX_W_TABLE (VEX_W_0F62_P_2) },
5045 /* PREFIX_VEX_0F63 */
5049 { VEX_W_TABLE (VEX_W_0F63_P_2) },
5052 /* PREFIX_VEX_0F64 */
5056 { VEX_W_TABLE (VEX_W_0F64_P_2) },
5059 /* PREFIX_VEX_0F65 */
5063 { VEX_W_TABLE (VEX_W_0F65_P_2) },
5066 /* PREFIX_VEX_0F66 */
5070 { VEX_W_TABLE (VEX_W_0F66_P_2) },
5073 /* PREFIX_VEX_0F67 */
5077 { VEX_W_TABLE (VEX_W_0F67_P_2) },
5080 /* PREFIX_VEX_0F68 */
5084 { VEX_W_TABLE (VEX_W_0F68_P_2) },
5087 /* PREFIX_VEX_0F69 */
5091 { VEX_W_TABLE (VEX_W_0F69_P_2) },
5094 /* PREFIX_VEX_0F6A */
5098 { VEX_W_TABLE (VEX_W_0F6A_P_2) },
5101 /* PREFIX_VEX_0F6B */
5105 { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5108 /* PREFIX_VEX_0F6C */
5112 { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5115 /* PREFIX_VEX_0F6D */
5119 { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5122 /* PREFIX_VEX_0F6E */
5126 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5129 /* PREFIX_VEX_0F6F */
5132 { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5133 { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5136 /* PREFIX_VEX_0F70 */
5139 { VEX_W_TABLE (VEX_W_0F70_P_1) },
5140 { VEX_W_TABLE (VEX_W_0F70_P_2) },
5141 { VEX_W_TABLE (VEX_W_0F70_P_3) },
5144 /* PREFIX_VEX_0F71_REG_2 */
5148 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5151 /* PREFIX_VEX_0F71_REG_4 */
5155 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5158 /* PREFIX_VEX_0F71_REG_6 */
5162 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5165 /* PREFIX_VEX_0F72_REG_2 */
5169 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5172 /* PREFIX_VEX_0F72_REG_4 */
5176 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5179 /* PREFIX_VEX_0F72_REG_6 */
5183 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5186 /* PREFIX_VEX_0F73_REG_2 */
5190 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5193 /* PREFIX_VEX_0F73_REG_3 */
5197 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5200 /* PREFIX_VEX_0F73_REG_6 */
5204 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5207 /* PREFIX_VEX_0F73_REG_7 */
5211 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5214 /* PREFIX_VEX_0F74 */
5218 { VEX_W_TABLE (VEX_W_0F74_P_2) },
5221 /* PREFIX_VEX_0F75 */
5225 { VEX_W_TABLE (VEX_W_0F75_P_2) },
5228 /* PREFIX_VEX_0F76 */
5232 { VEX_W_TABLE (VEX_W_0F76_P_2) },
5235 /* PREFIX_VEX_0F77 */
5237 { VEX_W_TABLE (VEX_W_0F77_P_0) },
5240 /* PREFIX_VEX_0F7C */
5244 { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5245 { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5248 /* PREFIX_VEX_0F7D */
5252 { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5253 { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5256 /* PREFIX_VEX_0F7E */
5259 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5260 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5263 /* PREFIX_VEX_0F7F */
5266 { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5267 { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5270 /* PREFIX_VEX_0F90 */
5272 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5274 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5277 /* PREFIX_VEX_0F91 */
5279 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5281 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5284 /* PREFIX_VEX_0F92 */
5286 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5288 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5289 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5292 /* PREFIX_VEX_0F93 */
5294 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5296 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5297 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5300 /* PREFIX_VEX_0F98 */
5302 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5304 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5307 /* PREFIX_VEX_0F99 */
5309 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5311 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5314 /* PREFIX_VEX_0FC2 */
5316 { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5317 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5318 { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5319 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5322 /* PREFIX_VEX_0FC4 */
5326 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5329 /* PREFIX_VEX_0FC5 */
5333 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5336 /* PREFIX_VEX_0FD0 */
5340 { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5341 { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5344 /* PREFIX_VEX_0FD1 */
5348 { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5351 /* PREFIX_VEX_0FD2 */
5355 { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5358 /* PREFIX_VEX_0FD3 */
5362 { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5365 /* PREFIX_VEX_0FD4 */
5369 { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5372 /* PREFIX_VEX_0FD5 */
5376 { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5379 /* PREFIX_VEX_0FD6 */
5383 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5386 /* PREFIX_VEX_0FD7 */
5390 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5393 /* PREFIX_VEX_0FD8 */
5397 { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5400 /* PREFIX_VEX_0FD9 */
5404 { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5407 /* PREFIX_VEX_0FDA */
5411 { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5414 /* PREFIX_VEX_0FDB */
5418 { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5421 /* PREFIX_VEX_0FDC */
5425 { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5428 /* PREFIX_VEX_0FDD */
5432 { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5435 /* PREFIX_VEX_0FDE */
5439 { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5442 /* PREFIX_VEX_0FDF */
5446 { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5449 /* PREFIX_VEX_0FE0 */
5453 { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5456 /* PREFIX_VEX_0FE1 */
5460 { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5463 /* PREFIX_VEX_0FE2 */
5467 { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5470 /* PREFIX_VEX_0FE3 */
5474 { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5477 /* PREFIX_VEX_0FE4 */
5481 { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5484 /* PREFIX_VEX_0FE5 */
5488 { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5491 /* PREFIX_VEX_0FE6 */
5494 { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5495 { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5496 { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5499 /* PREFIX_VEX_0FE7 */
5503 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5506 /* PREFIX_VEX_0FE8 */
5510 { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5513 /* PREFIX_VEX_0FE9 */
5517 { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5520 /* PREFIX_VEX_0FEA */
5524 { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5527 /* PREFIX_VEX_0FEB */
5531 { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5534 /* PREFIX_VEX_0FEC */
5538 { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5541 /* PREFIX_VEX_0FED */
5545 { VEX_W_TABLE (VEX_W_0FED_P_2) },
5548 /* PREFIX_VEX_0FEE */
5552 { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5555 /* PREFIX_VEX_0FEF */
5559 { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5562 /* PREFIX_VEX_0FF0 */
5567 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5570 /* PREFIX_VEX_0FF1 */
5574 { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5577 /* PREFIX_VEX_0FF2 */
5581 { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5584 /* PREFIX_VEX_0FF3 */
5588 { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5591 /* PREFIX_VEX_0FF4 */
5595 { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5598 /* PREFIX_VEX_0FF5 */
5602 { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5605 /* PREFIX_VEX_0FF6 */
5609 { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5612 /* PREFIX_VEX_0FF7 */
5616 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5619 /* PREFIX_VEX_0FF8 */
5623 { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5626 /* PREFIX_VEX_0FF9 */
5630 { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5633 /* PREFIX_VEX_0FFA */
5637 { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5640 /* PREFIX_VEX_0FFB */
5644 { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5647 /* PREFIX_VEX_0FFC */
5651 { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5654 /* PREFIX_VEX_0FFD */
5658 { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5661 /* PREFIX_VEX_0FFE */
5665 { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5668 /* PREFIX_VEX_0F3800 */
5672 { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5675 /* PREFIX_VEX_0F3801 */
5679 { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5682 /* PREFIX_VEX_0F3802 */
5686 { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5689 /* PREFIX_VEX_0F3803 */
5693 { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5696 /* PREFIX_VEX_0F3804 */
5700 { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5703 /* PREFIX_VEX_0F3805 */
5707 { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5710 /* PREFIX_VEX_0F3806 */
5714 { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5717 /* PREFIX_VEX_0F3807 */
5721 { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5724 /* PREFIX_VEX_0F3808 */
5728 { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5731 /* PREFIX_VEX_0F3809 */
5735 { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5738 /* PREFIX_VEX_0F380A */
5742 { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5745 /* PREFIX_VEX_0F380B */
5749 { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5752 /* PREFIX_VEX_0F380C */
5756 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5759 /* PREFIX_VEX_0F380D */
5763 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5766 /* PREFIX_VEX_0F380E */
5770 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5773 /* PREFIX_VEX_0F380F */
5777 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5780 /* PREFIX_VEX_0F3813 */
5784 { "vcvtph2ps", { XM, EXxmmq }, 0 },
5787 /* PREFIX_VEX_0F3816 */
5791 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5794 /* PREFIX_VEX_0F3817 */
5798 { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5801 /* PREFIX_VEX_0F3818 */
5805 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5808 /* PREFIX_VEX_0F3819 */
5812 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5815 /* PREFIX_VEX_0F381A */
5819 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5822 /* PREFIX_VEX_0F381C */
5826 { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5829 /* PREFIX_VEX_0F381D */
5833 { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5836 /* PREFIX_VEX_0F381E */
5840 { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5843 /* PREFIX_VEX_0F3820 */
5847 { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5850 /* PREFIX_VEX_0F3821 */
5854 { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5857 /* PREFIX_VEX_0F3822 */
5861 { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5864 /* PREFIX_VEX_0F3823 */
5868 { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5871 /* PREFIX_VEX_0F3824 */
5875 { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5878 /* PREFIX_VEX_0F3825 */
5882 { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5885 /* PREFIX_VEX_0F3828 */
5889 { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5892 /* PREFIX_VEX_0F3829 */
5896 { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5899 /* PREFIX_VEX_0F382A */
5903 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5906 /* PREFIX_VEX_0F382B */
5910 { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5913 /* PREFIX_VEX_0F382C */
5917 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5920 /* PREFIX_VEX_0F382D */
5924 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5927 /* PREFIX_VEX_0F382E */
5931 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5934 /* PREFIX_VEX_0F382F */
5938 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5941 /* PREFIX_VEX_0F3830 */
5945 { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5948 /* PREFIX_VEX_0F3831 */
5952 { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5955 /* PREFIX_VEX_0F3832 */
5959 { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5962 /* PREFIX_VEX_0F3833 */
5966 { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5969 /* PREFIX_VEX_0F3834 */
5973 { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5976 /* PREFIX_VEX_0F3835 */
5980 { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5983 /* PREFIX_VEX_0F3836 */
5987 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5990 /* PREFIX_VEX_0F3837 */
5994 { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5997 /* PREFIX_VEX_0F3838 */
6001 { VEX_W_TABLE (VEX_W_0F3838_P_2) },
6004 /* PREFIX_VEX_0F3839 */
6008 { VEX_W_TABLE (VEX_W_0F3839_P_2) },
6011 /* PREFIX_VEX_0F383A */
6015 { VEX_W_TABLE (VEX_W_0F383A_P_2) },
6018 /* PREFIX_VEX_0F383B */
6022 { VEX_W_TABLE (VEX_W_0F383B_P_2) },
6025 /* PREFIX_VEX_0F383C */
6029 { VEX_W_TABLE (VEX_W_0F383C_P_2) },
6032 /* PREFIX_VEX_0F383D */
6036 { VEX_W_TABLE (VEX_W_0F383D_P_2) },
6039 /* PREFIX_VEX_0F383E */
6043 { VEX_W_TABLE (VEX_W_0F383E_P_2) },
6046 /* PREFIX_VEX_0F383F */
6050 { VEX_W_TABLE (VEX_W_0F383F_P_2) },
6053 /* PREFIX_VEX_0F3840 */
6057 { VEX_W_TABLE (VEX_W_0F3840_P_2) },
6060 /* PREFIX_VEX_0F3841 */
6064 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
6067 /* PREFIX_VEX_0F3845 */
6071 { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
6074 /* PREFIX_VEX_0F3846 */
6078 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
6081 /* PREFIX_VEX_0F3847 */
6085 { "vpsllv%LW", { XM, Vex, EXx }, 0 },
6088 /* PREFIX_VEX_0F3858 */
6092 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
6095 /* PREFIX_VEX_0F3859 */
6099 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
6102 /* PREFIX_VEX_0F385A */
6106 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6109 /* PREFIX_VEX_0F3878 */
6113 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6116 /* PREFIX_VEX_0F3879 */
6120 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6123 /* PREFIX_VEX_0F388C */
6127 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6130 /* PREFIX_VEX_0F388E */
6134 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6137 /* PREFIX_VEX_0F3890 */
6141 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6144 /* PREFIX_VEX_0F3891 */
6148 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6151 /* PREFIX_VEX_0F3892 */
6155 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6158 /* PREFIX_VEX_0F3893 */
6162 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6165 /* PREFIX_VEX_0F3896 */
6169 { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6172 /* PREFIX_VEX_0F3897 */
6176 { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6179 /* PREFIX_VEX_0F3898 */
6183 { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6186 /* PREFIX_VEX_0F3899 */
6190 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6193 /* PREFIX_VEX_0F389A */
6197 { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6200 /* PREFIX_VEX_0F389B */
6204 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6207 /* PREFIX_VEX_0F389C */
6211 { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6214 /* PREFIX_VEX_0F389D */
6218 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6221 /* PREFIX_VEX_0F389E */
6225 { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6228 /* PREFIX_VEX_0F389F */
6232 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6235 /* PREFIX_VEX_0F38A6 */
6239 { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6243 /* PREFIX_VEX_0F38A7 */
6247 { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6250 /* PREFIX_VEX_0F38A8 */
6254 { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6257 /* PREFIX_VEX_0F38A9 */
6261 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6264 /* PREFIX_VEX_0F38AA */
6268 { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6271 /* PREFIX_VEX_0F38AB */
6275 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6278 /* PREFIX_VEX_0F38AC */
6282 { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6285 /* PREFIX_VEX_0F38AD */
6289 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6292 /* PREFIX_VEX_0F38AE */
6296 { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6299 /* PREFIX_VEX_0F38AF */
6303 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6306 /* PREFIX_VEX_0F38B6 */
6310 { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6313 /* PREFIX_VEX_0F38B7 */
6317 { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6320 /* PREFIX_VEX_0F38B8 */
6324 { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6327 /* PREFIX_VEX_0F38B9 */
6331 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6334 /* PREFIX_VEX_0F38BA */
6338 { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6341 /* PREFIX_VEX_0F38BB */
6345 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6348 /* PREFIX_VEX_0F38BC */
6352 { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6355 /* PREFIX_VEX_0F38BD */
6359 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6362 /* PREFIX_VEX_0F38BE */
6366 { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6369 /* PREFIX_VEX_0F38BF */
6373 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6376 /* PREFIX_VEX_0F38CF */
6380 { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6383 /* PREFIX_VEX_0F38DB */
6387 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6390 /* PREFIX_VEX_0F38DC */
6394 { "vaesenc", { XM, Vex, EXx }, 0 },
6397 /* PREFIX_VEX_0F38DD */
6401 { "vaesenclast", { XM, Vex, EXx }, 0 },
6404 /* PREFIX_VEX_0F38DE */
6408 { "vaesdec", { XM, Vex, EXx }, 0 },
6411 /* PREFIX_VEX_0F38DF */
6415 { "vaesdeclast", { XM, Vex, EXx }, 0 },
6418 /* PREFIX_VEX_0F38F2 */
6420 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6423 /* PREFIX_VEX_0F38F3_REG_1 */
6425 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6428 /* PREFIX_VEX_0F38F3_REG_2 */
6430 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6433 /* PREFIX_VEX_0F38F3_REG_3 */
6435 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6438 /* PREFIX_VEX_0F38F5 */
6440 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6441 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6443 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6446 /* PREFIX_VEX_0F38F6 */
6451 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6454 /* PREFIX_VEX_0F38F7 */
6456 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6457 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6458 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6459 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6462 /* PREFIX_VEX_0F3A00 */
6466 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6469 /* PREFIX_VEX_0F3A01 */
6473 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6476 /* PREFIX_VEX_0F3A02 */
6480 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6483 /* PREFIX_VEX_0F3A04 */
6487 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6490 /* PREFIX_VEX_0F3A05 */
6494 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6497 /* PREFIX_VEX_0F3A06 */
6501 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6504 /* PREFIX_VEX_0F3A08 */
6508 { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6511 /* PREFIX_VEX_0F3A09 */
6515 { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6518 /* PREFIX_VEX_0F3A0A */
6522 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6525 /* PREFIX_VEX_0F3A0B */
6529 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6532 /* PREFIX_VEX_0F3A0C */
6536 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6539 /* PREFIX_VEX_0F3A0D */
6543 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6546 /* PREFIX_VEX_0F3A0E */
6550 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6553 /* PREFIX_VEX_0F3A0F */
6557 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6560 /* PREFIX_VEX_0F3A14 */
6564 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6567 /* PREFIX_VEX_0F3A15 */
6571 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6574 /* PREFIX_VEX_0F3A16 */
6578 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6581 /* PREFIX_VEX_0F3A17 */
6585 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6588 /* PREFIX_VEX_0F3A18 */
6592 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6595 /* PREFIX_VEX_0F3A19 */
6599 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6602 /* PREFIX_VEX_0F3A1D */
6606 { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6609 /* PREFIX_VEX_0F3A20 */
6613 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6616 /* PREFIX_VEX_0F3A21 */
6620 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6623 /* PREFIX_VEX_0F3A22 */
6627 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6630 /* PREFIX_VEX_0F3A30 */
6634 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6637 /* PREFIX_VEX_0F3A31 */
6641 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6644 /* PREFIX_VEX_0F3A32 */
6648 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6651 /* PREFIX_VEX_0F3A33 */
6655 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6658 /* PREFIX_VEX_0F3A38 */
6662 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6665 /* PREFIX_VEX_0F3A39 */
6669 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6672 /* PREFIX_VEX_0F3A40 */
6676 { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6679 /* PREFIX_VEX_0F3A41 */
6683 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6686 /* PREFIX_VEX_0F3A42 */
6690 { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6693 /* PREFIX_VEX_0F3A44 */
6697 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 },
6700 /* PREFIX_VEX_0F3A46 */
6704 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6707 /* PREFIX_VEX_0F3A48 */
6711 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6714 /* PREFIX_VEX_0F3A49 */
6718 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6721 /* PREFIX_VEX_0F3A4A */
6725 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6728 /* PREFIX_VEX_0F3A4B */
6732 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6735 /* PREFIX_VEX_0F3A4C */
6739 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6742 /* PREFIX_VEX_0F3A5C */
6746 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6749 /* PREFIX_VEX_0F3A5D */
6753 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6756 /* PREFIX_VEX_0F3A5E */
6760 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6763 /* PREFIX_VEX_0F3A5F */
6767 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6770 /* PREFIX_VEX_0F3A60 */
6774 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6778 /* PREFIX_VEX_0F3A61 */
6782 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6785 /* PREFIX_VEX_0F3A62 */
6789 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6792 /* PREFIX_VEX_0F3A63 */
6796 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6799 /* PREFIX_VEX_0F3A68 */
6803 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6806 /* PREFIX_VEX_0F3A69 */
6810 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6813 /* PREFIX_VEX_0F3A6A */
6817 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6820 /* PREFIX_VEX_0F3A6B */
6824 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6827 /* PREFIX_VEX_0F3A6C */
6831 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6834 /* PREFIX_VEX_0F3A6D */
6838 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6841 /* PREFIX_VEX_0F3A6E */
6845 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6848 /* PREFIX_VEX_0F3A6F */
6852 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6855 /* PREFIX_VEX_0F3A78 */
6859 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6862 /* PREFIX_VEX_0F3A79 */
6866 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6869 /* PREFIX_VEX_0F3A7A */
6873 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6876 /* PREFIX_VEX_0F3A7B */
6880 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6883 /* PREFIX_VEX_0F3A7C */
6887 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6891 /* PREFIX_VEX_0F3A7D */
6895 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6898 /* PREFIX_VEX_0F3A7E */
6902 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6905 /* PREFIX_VEX_0F3A7F */
6909 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6912 /* PREFIX_VEX_0F3ACE */
6916 { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6919 /* PREFIX_VEX_0F3ACF */
6923 { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6926 /* PREFIX_VEX_0F3ADF */
6930 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6933 /* PREFIX_VEX_0F3AF0 */
6938 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6941 #define NEED_PREFIX_TABLE
6942 #include "i386-dis-evex.h"
6943 #undef NEED_PREFIX_TABLE
6946 static const struct dis386 x86_64_table[][2] = {
6949 { "pushP", { es }, 0 },
6954 { "popP", { es }, 0 },
6959 { "pushP", { cs }, 0 },
6964 { "pushP", { ss }, 0 },
6969 { "popP", { ss }, 0 },
6974 { "pushP", { ds }, 0 },
6979 { "popP", { ds }, 0 },
6984 { "daa", { XX }, 0 },
6989 { "das", { XX }, 0 },
6994 { "aaa", { XX }, 0 },
6999 { "aas", { XX }, 0 },
7004 { "pushaP", { XX }, 0 },
7009 { "popaP", { XX }, 0 },
7014 { MOD_TABLE (MOD_62_32BIT) },
7015 { EVEX_TABLE (EVEX_0F) },
7020 { "arpl", { Ew, Gw }, 0 },
7021 { "movs{lq|xd}", { Gv, Ed }, 0 },
7026 { "ins{R|}", { Yzr, indirDX }, 0 },
7027 { "ins{G|}", { Yzr, indirDX }, 0 },
7032 { "outs{R|}", { indirDXr, Xz }, 0 },
7033 { "outs{G|}", { indirDXr, Xz }, 0 },
7038 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
7039 { REG_TABLE (REG_80) },
7044 { "Jcall{T|}", { Ap }, 0 },
7049 { MOD_TABLE (MOD_C4_32BIT) },
7050 { VEX_C4_TABLE (VEX_0F) },
7055 { MOD_TABLE (MOD_C5_32BIT) },
7056 { VEX_C5_TABLE (VEX_0F) },
7061 { "into", { XX }, 0 },
7066 { "aam", { Ib }, 0 },
7071 { "aad", { Ib }, 0 },
7076 { "callP", { Jv, BND }, 0 },
7077 { "call@", { Jv, BND }, 0 }
7082 { "jmpP", { Jv, BND }, 0 },
7083 { "jmp@", { Jv, BND }, 0 }
7088 { "Jjmp{T|}", { Ap }, 0 },
7091 /* X86_64_0F01_REG_0 */
7093 { "sgdt{Q|IQ}", { M }, 0 },
7094 { "sgdt", { M }, 0 },
7097 /* X86_64_0F01_REG_1 */
7099 { "sidt{Q|IQ}", { M }, 0 },
7100 { "sidt", { M }, 0 },
7103 /* X86_64_0F01_REG_2 */
7105 { "lgdt{Q|Q}", { M }, 0 },
7106 { "lgdt", { M }, 0 },
7109 /* X86_64_0F01_REG_3 */
7111 { "lidt{Q|Q}", { M }, 0 },
7112 { "lidt", { M }, 0 },
7116 static const struct dis386 three_byte_table[][256] = {
7118 /* THREE_BYTE_0F38 */
7121 { "pshufb", { MX, EM }, PREFIX_OPCODE },
7122 { "phaddw", { MX, EM }, PREFIX_OPCODE },
7123 { "phaddd", { MX, EM }, PREFIX_OPCODE },
7124 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
7125 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
7126 { "phsubw", { MX, EM }, PREFIX_OPCODE },
7127 { "phsubd", { MX, EM }, PREFIX_OPCODE },
7128 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
7130 { "psignb", { MX, EM }, PREFIX_OPCODE },
7131 { "psignw", { MX, EM }, PREFIX_OPCODE },
7132 { "psignd", { MX, EM }, PREFIX_OPCODE },
7133 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
7139 { PREFIX_TABLE (PREFIX_0F3810) },
7143 { PREFIX_TABLE (PREFIX_0F3814) },
7144 { PREFIX_TABLE (PREFIX_0F3815) },
7146 { PREFIX_TABLE (PREFIX_0F3817) },
7152 { "pabsb", { MX, EM }, PREFIX_OPCODE },
7153 { "pabsw", { MX, EM }, PREFIX_OPCODE },
7154 { "pabsd", { MX, EM }, PREFIX_OPCODE },
7157 { PREFIX_TABLE (PREFIX_0F3820) },
7158 { PREFIX_TABLE (PREFIX_0F3821) },
7159 { PREFIX_TABLE (PREFIX_0F3822) },
7160 { PREFIX_TABLE (PREFIX_0F3823) },
7161 { PREFIX_TABLE (PREFIX_0F3824) },
7162 { PREFIX_TABLE (PREFIX_0F3825) },
7166 { PREFIX_TABLE (PREFIX_0F3828) },
7167 { PREFIX_TABLE (PREFIX_0F3829) },
7168 { PREFIX_TABLE (PREFIX_0F382A) },
7169 { PREFIX_TABLE (PREFIX_0F382B) },
7175 { PREFIX_TABLE (PREFIX_0F3830) },
7176 { PREFIX_TABLE (PREFIX_0F3831) },
7177 { PREFIX_TABLE (PREFIX_0F3832) },
7178 { PREFIX_TABLE (PREFIX_0F3833) },
7179 { PREFIX_TABLE (PREFIX_0F3834) },
7180 { PREFIX_TABLE (PREFIX_0F3835) },
7182 { PREFIX_TABLE (PREFIX_0F3837) },
7184 { PREFIX_TABLE (PREFIX_0F3838) },
7185 { PREFIX_TABLE (PREFIX_0F3839) },
7186 { PREFIX_TABLE (PREFIX_0F383A) },
7187 { PREFIX_TABLE (PREFIX_0F383B) },
7188 { PREFIX_TABLE (PREFIX_0F383C) },
7189 { PREFIX_TABLE (PREFIX_0F383D) },
7190 { PREFIX_TABLE (PREFIX_0F383E) },
7191 { PREFIX_TABLE (PREFIX_0F383F) },
7193 { PREFIX_TABLE (PREFIX_0F3840) },
7194 { PREFIX_TABLE (PREFIX_0F3841) },
7265 { PREFIX_TABLE (PREFIX_0F3880) },
7266 { PREFIX_TABLE (PREFIX_0F3881) },
7267 { PREFIX_TABLE (PREFIX_0F3882) },
7346 { PREFIX_TABLE (PREFIX_0F38C8) },
7347 { PREFIX_TABLE (PREFIX_0F38C9) },
7348 { PREFIX_TABLE (PREFIX_0F38CA) },
7349 { PREFIX_TABLE (PREFIX_0F38CB) },
7350 { PREFIX_TABLE (PREFIX_0F38CC) },
7351 { PREFIX_TABLE (PREFIX_0F38CD) },
7353 { PREFIX_TABLE (PREFIX_0F38CF) },
7367 { PREFIX_TABLE (PREFIX_0F38DB) },
7368 { PREFIX_TABLE (PREFIX_0F38DC) },
7369 { PREFIX_TABLE (PREFIX_0F38DD) },
7370 { PREFIX_TABLE (PREFIX_0F38DE) },
7371 { PREFIX_TABLE (PREFIX_0F38DF) },
7391 { PREFIX_TABLE (PREFIX_0F38F0) },
7392 { PREFIX_TABLE (PREFIX_0F38F1) },
7396 { PREFIX_TABLE (PREFIX_0F38F5) },
7397 { PREFIX_TABLE (PREFIX_0F38F6) },
7409 /* THREE_BYTE_0F3A */
7421 { PREFIX_TABLE (PREFIX_0F3A08) },
7422 { PREFIX_TABLE (PREFIX_0F3A09) },
7423 { PREFIX_TABLE (PREFIX_0F3A0A) },
7424 { PREFIX_TABLE (PREFIX_0F3A0B) },
7425 { PREFIX_TABLE (PREFIX_0F3A0C) },
7426 { PREFIX_TABLE (PREFIX_0F3A0D) },
7427 { PREFIX_TABLE (PREFIX_0F3A0E) },
7428 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
7434 { PREFIX_TABLE (PREFIX_0F3A14) },
7435 { PREFIX_TABLE (PREFIX_0F3A15) },
7436 { PREFIX_TABLE (PREFIX_0F3A16) },
7437 { PREFIX_TABLE (PREFIX_0F3A17) },
7448 { PREFIX_TABLE (PREFIX_0F3A20) },
7449 { PREFIX_TABLE (PREFIX_0F3A21) },
7450 { PREFIX_TABLE (PREFIX_0F3A22) },
7484 { PREFIX_TABLE (PREFIX_0F3A40) },
7485 { PREFIX_TABLE (PREFIX_0F3A41) },
7486 { PREFIX_TABLE (PREFIX_0F3A42) },
7488 { PREFIX_TABLE (PREFIX_0F3A44) },
7520 { PREFIX_TABLE (PREFIX_0F3A60) },
7521 { PREFIX_TABLE (PREFIX_0F3A61) },
7522 { PREFIX_TABLE (PREFIX_0F3A62) },
7523 { PREFIX_TABLE (PREFIX_0F3A63) },
7641 { PREFIX_TABLE (PREFIX_0F3ACC) },
7643 { PREFIX_TABLE (PREFIX_0F3ACE) },
7644 { PREFIX_TABLE (PREFIX_0F3ACF) },
7662 { PREFIX_TABLE (PREFIX_0F3ADF) },
7702 static const struct dis386 xop_table[][256] = {
7855 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7856 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7857 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7865 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7866 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7873 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7874 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7875 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7883 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7884 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7888 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7889 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7892 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7910 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7922 { "vprotb", { XM, Vex_2src_1, Ib }, 0 },
7923 { "vprotw", { XM, Vex_2src_1, Ib }, 0 },
7924 { "vprotd", { XM, Vex_2src_1, Ib }, 0 },
7925 { "vprotq", { XM, Vex_2src_1, Ib }, 0 },
7935 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7936 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7937 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7938 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7971 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7972 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7973 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7974 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7998 { REG_TABLE (REG_XOP_TBM_01) },
7999 { REG_TABLE (REG_XOP_TBM_02) },
8017 { REG_TABLE (REG_XOP_LWPCB) },
8141 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8142 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8143 { "vfrczss", { XM, EXd }, 0 },
8144 { "vfrczsd", { XM, EXq }, 0 },
8159 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8160 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8161 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8162 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8163 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8164 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8165 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8166 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8168 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8169 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8170 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8171 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8214 { "vphaddbw", { XM, EXxmm }, 0 },
8215 { "vphaddbd", { XM, EXxmm }, 0 },
8216 { "vphaddbq", { XM, EXxmm }, 0 },
8219 { "vphaddwd", { XM, EXxmm }, 0 },
8220 { "vphaddwq", { XM, EXxmm }, 0 },
8225 { "vphadddq", { XM, EXxmm }, 0 },
8232 { "vphaddubw", { XM, EXxmm }, 0 },
8233 { "vphaddubd", { XM, EXxmm }, 0 },
8234 { "vphaddubq", { XM, EXxmm }, 0 },
8237 { "vphadduwd", { XM, EXxmm }, 0 },
8238 { "vphadduwq", { XM, EXxmm }, 0 },
8243 { "vphaddudq", { XM, EXxmm }, 0 },
8250 { "vphsubbw", { XM, EXxmm }, 0 },
8251 { "vphsubwd", { XM, EXxmm }, 0 },
8252 { "vphsubdq", { XM, EXxmm }, 0 },
8306 { "bextr", { Gv, Ev, Iq }, 0 },
8308 { REG_TABLE (REG_XOP_LWP) },
8578 static const struct dis386 vex_table[][256] = {
8600 { PREFIX_TABLE (PREFIX_VEX_0F10) },
8601 { PREFIX_TABLE (PREFIX_VEX_0F11) },
8602 { PREFIX_TABLE (PREFIX_VEX_0F12) },
8603 { MOD_TABLE (MOD_VEX_0F13) },
8604 { VEX_W_TABLE (VEX_W_0F14) },
8605 { VEX_W_TABLE (VEX_W_0F15) },
8606 { PREFIX_TABLE (PREFIX_VEX_0F16) },
8607 { MOD_TABLE (MOD_VEX_0F17) },
8627 { VEX_W_TABLE (VEX_W_0F28) },
8628 { VEX_W_TABLE (VEX_W_0F29) },
8629 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8630 { MOD_TABLE (MOD_VEX_0F2B) },
8631 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8632 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8633 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8634 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8655 { PREFIX_TABLE (PREFIX_VEX_0F41) },
8656 { PREFIX_TABLE (PREFIX_VEX_0F42) },
8658 { PREFIX_TABLE (PREFIX_VEX_0F44) },
8659 { PREFIX_TABLE (PREFIX_VEX_0F45) },
8660 { PREFIX_TABLE (PREFIX_VEX_0F46) },
8661 { PREFIX_TABLE (PREFIX_VEX_0F47) },
8665 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8666 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8672 { MOD_TABLE (MOD_VEX_0F50) },
8673 { PREFIX_TABLE (PREFIX_VEX_0F51) },
8674 { PREFIX_TABLE (PREFIX_VEX_0F52) },
8675 { PREFIX_TABLE (PREFIX_VEX_0F53) },
8676 { "vandpX", { XM, Vex, EXx }, 0 },
8677 { "vandnpX", { XM, Vex, EXx }, 0 },
8678 { "vorpX", { XM, Vex, EXx }, 0 },
8679 { "vxorpX", { XM, Vex, EXx }, 0 },
8681 { PREFIX_TABLE (PREFIX_VEX_0F58) },
8682 { PREFIX_TABLE (PREFIX_VEX_0F59) },
8683 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8684 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8685 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8686 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8687 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8688 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8690 { PREFIX_TABLE (PREFIX_VEX_0F60) },
8691 { PREFIX_TABLE (PREFIX_VEX_0F61) },
8692 { PREFIX_TABLE (PREFIX_VEX_0F62) },
8693 { PREFIX_TABLE (PREFIX_VEX_0F63) },
8694 { PREFIX_TABLE (PREFIX_VEX_0F64) },
8695 { PREFIX_TABLE (PREFIX_VEX_0F65) },
8696 { PREFIX_TABLE (PREFIX_VEX_0F66) },
8697 { PREFIX_TABLE (PREFIX_VEX_0F67) },
8699 { PREFIX_TABLE (PREFIX_VEX_0F68) },
8700 { PREFIX_TABLE (PREFIX_VEX_0F69) },
8701 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8702 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8703 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8704 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8705 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8706 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8708 { PREFIX_TABLE (PREFIX_VEX_0F70) },
8709 { REG_TABLE (REG_VEX_0F71) },
8710 { REG_TABLE (REG_VEX_0F72) },
8711 { REG_TABLE (REG_VEX_0F73) },
8712 { PREFIX_TABLE (PREFIX_VEX_0F74) },
8713 { PREFIX_TABLE (PREFIX_VEX_0F75) },
8714 { PREFIX_TABLE (PREFIX_VEX_0F76) },
8715 { PREFIX_TABLE (PREFIX_VEX_0F77) },
8721 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8722 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8723 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8724 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8744 { PREFIX_TABLE (PREFIX_VEX_0F90) },
8745 { PREFIX_TABLE (PREFIX_VEX_0F91) },
8746 { PREFIX_TABLE (PREFIX_VEX_0F92) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F93) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F98) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F99) },
8777 { REG_TABLE (REG_VEX_0FAE) },
8800 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8802 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8803 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8804 { "vshufpX", { XM, Vex, EXx, Ib }, 0 },
8816 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8817 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8818 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8819 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8820 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8821 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8822 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8823 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8825 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8826 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8827 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8828 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8829 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8830 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8831 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8832 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8834 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8835 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8836 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8837 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8838 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8839 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8840 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8841 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8843 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8844 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8845 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8846 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8847 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8848 { PREFIX_TABLE (PREFIX_VEX_0FED) },
8849 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8850 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8852 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8853 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8854 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8855 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8856 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8857 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8858 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8859 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8861 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8862 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8863 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8864 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8865 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8866 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8867 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8873 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8874 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8875 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8876 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8877 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8878 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8879 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8880 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8882 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8883 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8884 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8885 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8886 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8905 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8909 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8923 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8924 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8925 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8927 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8928 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8929 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8972 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8973 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8974 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9008 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9009 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9030 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9032 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9035 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9036 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9037 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9038 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9046 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9047 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9048 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9049 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9050 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9051 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9059 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9062 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9063 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9064 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9065 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9066 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9067 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9068 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9077 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9078 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9080 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9081 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9082 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9083 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9084 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9085 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9086 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9087 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9105 { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
9119 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9120 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9121 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9122 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9123 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9145 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9146 { REG_TABLE (REG_VEX_0F38F3) },
9148 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9149 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9150 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9164 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9165 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9166 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9168 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9169 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9170 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9173 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9174 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9175 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9176 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9177 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9178 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9179 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9180 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9186 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9187 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9188 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9189 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9191 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9192 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9196 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9200 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9201 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9202 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9218 { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9219 { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9220 { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9221 { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9227 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9228 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9236 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9237 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9238 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9240 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9242 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9245 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9246 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9247 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9248 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9249 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9267 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9268 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9269 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9270 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9272 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9273 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9274 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9275 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9281 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9282 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9283 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9284 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9285 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9286 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9287 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9288 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9299 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9300 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9301 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9302 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9303 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9304 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9305 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9306 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9395 { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9396 { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9414 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9434 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9454 #define NEED_OPCODE_TABLE
9455 #include "i386-dis-evex.h"
9456 #undef NEED_OPCODE_TABLE
9457 static const struct dis386 vex_len_table[][2] = {
9458 /* VEX_LEN_0F10_P_1 */
9460 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9461 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9464 /* VEX_LEN_0F10_P_3 */
9466 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9467 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9470 /* VEX_LEN_0F11_P_1 */
9472 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9473 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9476 /* VEX_LEN_0F11_P_3 */
9478 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9479 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9482 /* VEX_LEN_0F12_P_0_M_0 */
9484 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9487 /* VEX_LEN_0F12_P_0_M_1 */
9489 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9492 /* VEX_LEN_0F12_P_2 */
9494 { VEX_W_TABLE (VEX_W_0F12_P_2) },
9497 /* VEX_LEN_0F13_M_0 */
9499 { VEX_W_TABLE (VEX_W_0F13_M_0) },
9502 /* VEX_LEN_0F16_P_0_M_0 */
9504 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9507 /* VEX_LEN_0F16_P_0_M_1 */
9509 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9512 /* VEX_LEN_0F16_P_2 */
9514 { VEX_W_TABLE (VEX_W_0F16_P_2) },
9517 /* VEX_LEN_0F17_M_0 */
9519 { VEX_W_TABLE (VEX_W_0F17_M_0) },
9522 /* VEX_LEN_0F2A_P_1 */
9524 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9525 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9528 /* VEX_LEN_0F2A_P_3 */
9530 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9531 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9534 /* VEX_LEN_0F2C_P_1 */
9536 { "vcvttss2siY", { Gv, EXdScalar }, 0 },
9537 { "vcvttss2siY", { Gv, EXdScalar }, 0 },
9540 /* VEX_LEN_0F2C_P_3 */
9542 { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
9543 { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
9546 /* VEX_LEN_0F2D_P_1 */
9548 { "vcvtss2siY", { Gv, EXdScalar }, 0 },
9549 { "vcvtss2siY", { Gv, EXdScalar }, 0 },
9552 /* VEX_LEN_0F2D_P_3 */
9554 { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
9555 { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
9558 /* VEX_LEN_0F2E_P_0 */
9560 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9561 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9564 /* VEX_LEN_0F2E_P_2 */
9566 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9567 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9570 /* VEX_LEN_0F2F_P_0 */
9572 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9573 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9576 /* VEX_LEN_0F2F_P_2 */
9578 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9579 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9582 /* VEX_LEN_0F41_P_0 */
9585 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9587 /* VEX_LEN_0F41_P_2 */
9590 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9592 /* VEX_LEN_0F42_P_0 */
9595 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9597 /* VEX_LEN_0F42_P_2 */
9600 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9602 /* VEX_LEN_0F44_P_0 */
9604 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9606 /* VEX_LEN_0F44_P_2 */
9608 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9610 /* VEX_LEN_0F45_P_0 */
9613 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9615 /* VEX_LEN_0F45_P_2 */
9618 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9620 /* VEX_LEN_0F46_P_0 */
9623 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9625 /* VEX_LEN_0F46_P_2 */
9628 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9630 /* VEX_LEN_0F47_P_0 */
9633 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9635 /* VEX_LEN_0F47_P_2 */
9638 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9640 /* VEX_LEN_0F4A_P_0 */
9643 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9645 /* VEX_LEN_0F4A_P_2 */
9648 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9650 /* VEX_LEN_0F4B_P_0 */
9653 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9655 /* VEX_LEN_0F4B_P_2 */
9658 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9661 /* VEX_LEN_0F51_P_1 */
9663 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9664 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9667 /* VEX_LEN_0F51_P_3 */
9669 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9670 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9673 /* VEX_LEN_0F52_P_1 */
9675 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9676 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9679 /* VEX_LEN_0F53_P_1 */
9681 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9682 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9685 /* VEX_LEN_0F58_P_1 */
9687 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9688 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9691 /* VEX_LEN_0F58_P_3 */
9693 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9694 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9697 /* VEX_LEN_0F59_P_1 */
9699 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9700 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9703 /* VEX_LEN_0F59_P_3 */
9705 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9706 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9709 /* VEX_LEN_0F5A_P_1 */
9711 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9712 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9715 /* VEX_LEN_0F5A_P_3 */
9717 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9718 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9721 /* VEX_LEN_0F5C_P_1 */
9723 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9724 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9727 /* VEX_LEN_0F5C_P_3 */
9729 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9730 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9733 /* VEX_LEN_0F5D_P_1 */
9735 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9736 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9739 /* VEX_LEN_0F5D_P_3 */
9741 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9742 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9745 /* VEX_LEN_0F5E_P_1 */
9747 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9748 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9751 /* VEX_LEN_0F5E_P_3 */
9753 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9754 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9757 /* VEX_LEN_0F5F_P_1 */
9759 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9760 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9763 /* VEX_LEN_0F5F_P_3 */
9765 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9766 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9769 /* VEX_LEN_0F6E_P_2 */
9771 { "vmovK", { XMScalar, Edq }, 0 },
9772 { "vmovK", { XMScalar, Edq }, 0 },
9775 /* VEX_LEN_0F7E_P_1 */
9777 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9778 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9781 /* VEX_LEN_0F7E_P_2 */
9783 { "vmovK", { Edq, XMScalar }, 0 },
9784 { "vmovK", { Edq, XMScalar }, 0 },
9787 /* VEX_LEN_0F90_P_0 */
9789 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9792 /* VEX_LEN_0F90_P_2 */
9794 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9797 /* VEX_LEN_0F91_P_0 */
9799 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9802 /* VEX_LEN_0F91_P_2 */
9804 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9807 /* VEX_LEN_0F92_P_0 */
9809 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9812 /* VEX_LEN_0F92_P_2 */
9814 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9817 /* VEX_LEN_0F92_P_3 */
9819 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9822 /* VEX_LEN_0F93_P_0 */
9824 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9827 /* VEX_LEN_0F93_P_2 */
9829 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9832 /* VEX_LEN_0F93_P_3 */
9834 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9837 /* VEX_LEN_0F98_P_0 */
9839 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9842 /* VEX_LEN_0F98_P_2 */
9844 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9847 /* VEX_LEN_0F99_P_0 */
9849 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9852 /* VEX_LEN_0F99_P_2 */
9854 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9857 /* VEX_LEN_0FAE_R_2_M_0 */
9859 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9862 /* VEX_LEN_0FAE_R_3_M_0 */
9864 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9867 /* VEX_LEN_0FC2_P_1 */
9869 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9870 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9873 /* VEX_LEN_0FC2_P_3 */
9875 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9876 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9879 /* VEX_LEN_0FC4_P_2 */
9881 { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9884 /* VEX_LEN_0FC5_P_2 */
9886 { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9889 /* VEX_LEN_0FD6_P_2 */
9891 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9892 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9895 /* VEX_LEN_0FF7_P_2 */
9897 { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9900 /* VEX_LEN_0F3816_P_2 */
9903 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9906 /* VEX_LEN_0F3819_P_2 */
9909 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9912 /* VEX_LEN_0F381A_P_2_M_0 */
9915 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9918 /* VEX_LEN_0F3836_P_2 */
9921 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9924 /* VEX_LEN_0F3841_P_2 */
9926 { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9929 /* VEX_LEN_0F385A_P_2_M_0 */
9932 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9935 /* VEX_LEN_0F38DB_P_2 */
9937 { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9940 /* VEX_LEN_0F38F2_P_0 */
9942 { "andnS", { Gdq, VexGdq, Edq }, 0 },
9945 /* VEX_LEN_0F38F3_R_1_P_0 */
9947 { "blsrS", { VexGdq, Edq }, 0 },
9950 /* VEX_LEN_0F38F3_R_2_P_0 */
9952 { "blsmskS", { VexGdq, Edq }, 0 },
9955 /* VEX_LEN_0F38F3_R_3_P_0 */
9957 { "blsiS", { VexGdq, Edq }, 0 },
9960 /* VEX_LEN_0F38F5_P_0 */
9962 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
9965 /* VEX_LEN_0F38F5_P_1 */
9967 { "pextS", { Gdq, VexGdq, Edq }, 0 },
9970 /* VEX_LEN_0F38F5_P_3 */
9972 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
9975 /* VEX_LEN_0F38F6_P_3 */
9977 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
9980 /* VEX_LEN_0F38F7_P_0 */
9982 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
9985 /* VEX_LEN_0F38F7_P_1 */
9987 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
9990 /* VEX_LEN_0F38F7_P_2 */
9992 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
9995 /* VEX_LEN_0F38F7_P_3 */
9997 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
10000 /* VEX_LEN_0F3A00_P_2 */
10003 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10006 /* VEX_LEN_0F3A01_P_2 */
10009 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10012 /* VEX_LEN_0F3A06_P_2 */
10015 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10018 /* VEX_LEN_0F3A0A_P_2 */
10020 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10021 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10024 /* VEX_LEN_0F3A0B_P_2 */
10026 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10027 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10030 /* VEX_LEN_0F3A14_P_2 */
10032 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10035 /* VEX_LEN_0F3A15_P_2 */
10037 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10040 /* VEX_LEN_0F3A16_P_2 */
10042 { "vpextrK", { Edq, XM, Ib }, 0 },
10045 /* VEX_LEN_0F3A17_P_2 */
10047 { "vextractps", { Edqd, XM, Ib }, 0 },
10050 /* VEX_LEN_0F3A18_P_2 */
10053 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10056 /* VEX_LEN_0F3A19_P_2 */
10059 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10062 /* VEX_LEN_0F3A20_P_2 */
10064 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10067 /* VEX_LEN_0F3A21_P_2 */
10069 { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10072 /* VEX_LEN_0F3A22_P_2 */
10074 { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 },
10077 /* VEX_LEN_0F3A30_P_2 */
10079 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10082 /* VEX_LEN_0F3A31_P_2 */
10084 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10087 /* VEX_LEN_0F3A32_P_2 */
10089 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10092 /* VEX_LEN_0F3A33_P_2 */
10094 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10097 /* VEX_LEN_0F3A38_P_2 */
10100 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10103 /* VEX_LEN_0F3A39_P_2 */
10106 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10109 /* VEX_LEN_0F3A41_P_2 */
10111 { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10114 /* VEX_LEN_0F3A46_P_2 */
10117 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10120 /* VEX_LEN_0F3A60_P_2 */
10122 { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10125 /* VEX_LEN_0F3A61_P_2 */
10127 { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10130 /* VEX_LEN_0F3A62_P_2 */
10132 { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10135 /* VEX_LEN_0F3A63_P_2 */
10137 { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10140 /* VEX_LEN_0F3A6A_P_2 */
10142 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10145 /* VEX_LEN_0F3A6B_P_2 */
10147 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10150 /* VEX_LEN_0F3A6E_P_2 */
10152 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10155 /* VEX_LEN_0F3A6F_P_2 */
10157 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10160 /* VEX_LEN_0F3A7A_P_2 */
10162 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10165 /* VEX_LEN_0F3A7B_P_2 */
10167 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10170 /* VEX_LEN_0F3A7E_P_2 */
10172 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10175 /* VEX_LEN_0F3A7F_P_2 */
10177 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10180 /* VEX_LEN_0F3ADF_P_2 */
10182 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10185 /* VEX_LEN_0F3AF0_P_3 */
10187 { "rorxS", { Gdq, Edq, Ib }, 0 },
10190 /* VEX_LEN_0FXOP_08_CC */
10192 { "vpcomb", { XM, Vex128, EXx, Ib }, 0 },
10195 /* VEX_LEN_0FXOP_08_CD */
10197 { "vpcomw", { XM, Vex128, EXx, Ib }, 0 },
10200 /* VEX_LEN_0FXOP_08_CE */
10202 { "vpcomd", { XM, Vex128, EXx, Ib }, 0 },
10205 /* VEX_LEN_0FXOP_08_CF */
10207 { "vpcomq", { XM, Vex128, EXx, Ib }, 0 },
10210 /* VEX_LEN_0FXOP_08_EC */
10212 { "vpcomub", { XM, Vex128, EXx, Ib }, 0 },
10215 /* VEX_LEN_0FXOP_08_ED */
10217 { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 },
10220 /* VEX_LEN_0FXOP_08_EE */
10222 { "vpcomud", { XM, Vex128, EXx, Ib }, 0 },
10225 /* VEX_LEN_0FXOP_08_EF */
10227 { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 },
10230 /* VEX_LEN_0FXOP_09_80 */
10232 { "vfrczps", { XM, EXxmm }, 0 },
10233 { "vfrczps", { XM, EXymmq }, 0 },
10236 /* VEX_LEN_0FXOP_09_81 */
10238 { "vfrczpd", { XM, EXxmm }, 0 },
10239 { "vfrczpd", { XM, EXymmq }, 0 },
10243 static const struct dis386 vex_w_table[][2] = {
10245 /* VEX_W_0F10_P_0 */
10246 { "vmovups", { XM, EXx }, 0 },
10249 /* VEX_W_0F10_P_1 */
10250 { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
10253 /* VEX_W_0F10_P_2 */
10254 { "vmovupd", { XM, EXx }, 0 },
10257 /* VEX_W_0F10_P_3 */
10258 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
10261 /* VEX_W_0F11_P_0 */
10262 { "vmovups", { EXxS, XM }, 0 },
10265 /* VEX_W_0F11_P_1 */
10266 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10269 /* VEX_W_0F11_P_2 */
10270 { "vmovupd", { EXxS, XM }, 0 },
10273 /* VEX_W_0F11_P_3 */
10274 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10277 /* VEX_W_0F12_P_0_M_0 */
10278 { "vmovlps", { XM, Vex128, EXq }, 0 },
10281 /* VEX_W_0F12_P_0_M_1 */
10282 { "vmovhlps", { XM, Vex128, EXq }, 0 },
10285 /* VEX_W_0F12_P_1 */
10286 { "vmovsldup", { XM, EXx }, 0 },
10289 /* VEX_W_0F12_P_2 */
10290 { "vmovlpd", { XM, Vex128, EXq }, 0 },
10293 /* VEX_W_0F12_P_3 */
10294 { "vmovddup", { XM, EXymmq }, 0 },
10297 /* VEX_W_0F13_M_0 */
10298 { "vmovlpX", { EXq, XM }, 0 },
10302 { "vunpcklpX", { XM, Vex, EXx }, 0 },
10306 { "vunpckhpX", { XM, Vex, EXx }, 0 },
10309 /* VEX_W_0F16_P_0_M_0 */
10310 { "vmovhps", { XM, Vex128, EXq }, 0 },
10313 /* VEX_W_0F16_P_0_M_1 */
10314 { "vmovlhps", { XM, Vex128, EXq }, 0 },
10317 /* VEX_W_0F16_P_1 */
10318 { "vmovshdup", { XM, EXx }, 0 },
10321 /* VEX_W_0F16_P_2 */
10322 { "vmovhpd", { XM, Vex128, EXq }, 0 },
10325 /* VEX_W_0F17_M_0 */
10326 { "vmovhpX", { EXq, XM }, 0 },
10330 { "vmovapX", { XM, EXx }, 0 },
10334 { "vmovapX", { EXxS, XM }, 0 },
10337 /* VEX_W_0F2B_M_0 */
10338 { "vmovntpX", { Mx, XM }, 0 },
10341 /* VEX_W_0F2E_P_0 */
10342 { "vucomiss", { XMScalar, EXdScalar }, 0 },
10345 /* VEX_W_0F2E_P_2 */
10346 { "vucomisd", { XMScalar, EXqScalar }, 0 },
10349 /* VEX_W_0F2F_P_0 */
10350 { "vcomiss", { XMScalar, EXdScalar }, 0 },
10353 /* VEX_W_0F2F_P_2 */
10354 { "vcomisd", { XMScalar, EXqScalar }, 0 },
10357 /* VEX_W_0F41_P_0_LEN_1 */
10358 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10359 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10362 /* VEX_W_0F41_P_2_LEN_1 */
10363 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10364 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10367 /* VEX_W_0F42_P_0_LEN_1 */
10368 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10369 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10372 /* VEX_W_0F42_P_2_LEN_1 */
10373 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10374 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10377 /* VEX_W_0F44_P_0_LEN_0 */
10378 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10379 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10382 /* VEX_W_0F44_P_2_LEN_0 */
10383 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10384 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10387 /* VEX_W_0F45_P_0_LEN_1 */
10388 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10389 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10392 /* VEX_W_0F45_P_2_LEN_1 */
10393 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10394 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10397 /* VEX_W_0F46_P_0_LEN_1 */
10398 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10399 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10402 /* VEX_W_0F46_P_2_LEN_1 */
10403 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10404 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10407 /* VEX_W_0F47_P_0_LEN_1 */
10408 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10409 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10412 /* VEX_W_0F47_P_2_LEN_1 */
10413 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10414 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10417 /* VEX_W_0F4A_P_0_LEN_1 */
10418 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10419 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10422 /* VEX_W_0F4A_P_2_LEN_1 */
10423 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10424 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10427 /* VEX_W_0F4B_P_0_LEN_1 */
10428 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10429 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10432 /* VEX_W_0F4B_P_2_LEN_1 */
10433 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10436 /* VEX_W_0F50_M_0 */
10437 { "vmovmskpX", { Gdq, XS }, 0 },
10440 /* VEX_W_0F51_P_0 */
10441 { "vsqrtps", { XM, EXx }, 0 },
10444 /* VEX_W_0F51_P_1 */
10445 { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10448 /* VEX_W_0F51_P_2 */
10449 { "vsqrtpd", { XM, EXx }, 0 },
10452 /* VEX_W_0F51_P_3 */
10453 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10456 /* VEX_W_0F52_P_0 */
10457 { "vrsqrtps", { XM, EXx }, 0 },
10460 /* VEX_W_0F52_P_1 */
10461 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10464 /* VEX_W_0F53_P_0 */
10465 { "vrcpps", { XM, EXx }, 0 },
10468 /* VEX_W_0F53_P_1 */
10469 { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
10472 /* VEX_W_0F58_P_0 */
10473 { "vaddps", { XM, Vex, EXx }, 0 },
10476 /* VEX_W_0F58_P_1 */
10477 { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
10480 /* VEX_W_0F58_P_2 */
10481 { "vaddpd", { XM, Vex, EXx }, 0 },
10484 /* VEX_W_0F58_P_3 */
10485 { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10488 /* VEX_W_0F59_P_0 */
10489 { "vmulps", { XM, Vex, EXx }, 0 },
10492 /* VEX_W_0F59_P_1 */
10493 { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
10496 /* VEX_W_0F59_P_2 */
10497 { "vmulpd", { XM, Vex, EXx }, 0 },
10500 /* VEX_W_0F59_P_3 */
10501 { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10504 /* VEX_W_0F5A_P_0 */
10505 { "vcvtps2pd", { XM, EXxmmq }, 0 },
10508 /* VEX_W_0F5A_P_1 */
10509 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
10512 /* VEX_W_0F5A_P_3 */
10513 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
10516 /* VEX_W_0F5B_P_0 */
10517 { "vcvtdq2ps", { XM, EXx }, 0 },
10520 /* VEX_W_0F5B_P_1 */
10521 { "vcvttps2dq", { XM, EXx }, 0 },
10524 /* VEX_W_0F5B_P_2 */
10525 { "vcvtps2dq", { XM, EXx }, 0 },
10528 /* VEX_W_0F5C_P_0 */
10529 { "vsubps", { XM, Vex, EXx }, 0 },
10532 /* VEX_W_0F5C_P_1 */
10533 { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
10536 /* VEX_W_0F5C_P_2 */
10537 { "vsubpd", { XM, Vex, EXx }, 0 },
10540 /* VEX_W_0F5C_P_3 */
10541 { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10544 /* VEX_W_0F5D_P_0 */
10545 { "vminps", { XM, Vex, EXx }, 0 },
10548 /* VEX_W_0F5D_P_1 */
10549 { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
10552 /* VEX_W_0F5D_P_2 */
10553 { "vminpd", { XM, Vex, EXx }, 0 },
10556 /* VEX_W_0F5D_P_3 */
10557 { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10560 /* VEX_W_0F5E_P_0 */
10561 { "vdivps", { XM, Vex, EXx }, 0 },
10564 /* VEX_W_0F5E_P_1 */
10565 { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
10568 /* VEX_W_0F5E_P_2 */
10569 { "vdivpd", { XM, Vex, EXx }, 0 },
10572 /* VEX_W_0F5E_P_3 */
10573 { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10576 /* VEX_W_0F5F_P_0 */
10577 { "vmaxps", { XM, Vex, EXx }, 0 },
10580 /* VEX_W_0F5F_P_1 */
10581 { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
10584 /* VEX_W_0F5F_P_2 */
10585 { "vmaxpd", { XM, Vex, EXx }, 0 },
10588 /* VEX_W_0F5F_P_3 */
10589 { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10592 /* VEX_W_0F60_P_2 */
10593 { "vpunpcklbw", { XM, Vex, EXx }, 0 },
10596 /* VEX_W_0F61_P_2 */
10597 { "vpunpcklwd", { XM, Vex, EXx }, 0 },
10600 /* VEX_W_0F62_P_2 */
10601 { "vpunpckldq", { XM, Vex, EXx }, 0 },
10604 /* VEX_W_0F63_P_2 */
10605 { "vpacksswb", { XM, Vex, EXx }, 0 },
10608 /* VEX_W_0F64_P_2 */
10609 { "vpcmpgtb", { XM, Vex, EXx }, 0 },
10612 /* VEX_W_0F65_P_2 */
10613 { "vpcmpgtw", { XM, Vex, EXx }, 0 },
10616 /* VEX_W_0F66_P_2 */
10617 { "vpcmpgtd", { XM, Vex, EXx }, 0 },
10620 /* VEX_W_0F67_P_2 */
10621 { "vpackuswb", { XM, Vex, EXx }, 0 },
10624 /* VEX_W_0F68_P_2 */
10625 { "vpunpckhbw", { XM, Vex, EXx }, 0 },
10628 /* VEX_W_0F69_P_2 */
10629 { "vpunpckhwd", { XM, Vex, EXx }, 0 },
10632 /* VEX_W_0F6A_P_2 */
10633 { "vpunpckhdq", { XM, Vex, EXx }, 0 },
10636 /* VEX_W_0F6B_P_2 */
10637 { "vpackssdw", { XM, Vex, EXx }, 0 },
10640 /* VEX_W_0F6C_P_2 */
10641 { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
10644 /* VEX_W_0F6D_P_2 */
10645 { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
10648 /* VEX_W_0F6F_P_1 */
10649 { "vmovdqu", { XM, EXx }, 0 },
10652 /* VEX_W_0F6F_P_2 */
10653 { "vmovdqa", { XM, EXx }, 0 },
10656 /* VEX_W_0F70_P_1 */
10657 { "vpshufhw", { XM, EXx, Ib }, 0 },
10660 /* VEX_W_0F70_P_2 */
10661 { "vpshufd", { XM, EXx, Ib }, 0 },
10664 /* VEX_W_0F70_P_3 */
10665 { "vpshuflw", { XM, EXx, Ib }, 0 },
10668 /* VEX_W_0F71_R_2_P_2 */
10669 { "vpsrlw", { Vex, XS, Ib }, 0 },
10672 /* VEX_W_0F71_R_4_P_2 */
10673 { "vpsraw", { Vex, XS, Ib }, 0 },
10676 /* VEX_W_0F71_R_6_P_2 */
10677 { "vpsllw", { Vex, XS, Ib }, 0 },
10680 /* VEX_W_0F72_R_2_P_2 */
10681 { "vpsrld", { Vex, XS, Ib }, 0 },
10684 /* VEX_W_0F72_R_4_P_2 */
10685 { "vpsrad", { Vex, XS, Ib }, 0 },
10688 /* VEX_W_0F72_R_6_P_2 */
10689 { "vpslld", { Vex, XS, Ib }, 0 },
10692 /* VEX_W_0F73_R_2_P_2 */
10693 { "vpsrlq", { Vex, XS, Ib }, 0 },
10696 /* VEX_W_0F73_R_3_P_2 */
10697 { "vpsrldq", { Vex, XS, Ib }, 0 },
10700 /* VEX_W_0F73_R_6_P_2 */
10701 { "vpsllq", { Vex, XS, Ib }, 0 },
10704 /* VEX_W_0F73_R_7_P_2 */
10705 { "vpslldq", { Vex, XS, Ib }, 0 },
10708 /* VEX_W_0F74_P_2 */
10709 { "vpcmpeqb", { XM, Vex, EXx }, 0 },
10712 /* VEX_W_0F75_P_2 */
10713 { "vpcmpeqw", { XM, Vex, EXx }, 0 },
10716 /* VEX_W_0F76_P_2 */
10717 { "vpcmpeqd", { XM, Vex, EXx }, 0 },
10720 /* VEX_W_0F77_P_0 */
10721 { "", { VZERO }, 0 },
10724 /* VEX_W_0F7C_P_2 */
10725 { "vhaddpd", { XM, Vex, EXx }, 0 },
10728 /* VEX_W_0F7C_P_3 */
10729 { "vhaddps", { XM, Vex, EXx }, 0 },
10732 /* VEX_W_0F7D_P_2 */
10733 { "vhsubpd", { XM, Vex, EXx }, 0 },
10736 /* VEX_W_0F7D_P_3 */
10737 { "vhsubps", { XM, Vex, EXx }, 0 },
10740 /* VEX_W_0F7E_P_1 */
10741 { "vmovq", { XMScalar, EXqScalar }, 0 },
10744 /* VEX_W_0F7F_P_1 */
10745 { "vmovdqu", { EXxS, XM }, 0 },
10748 /* VEX_W_0F7F_P_2 */
10749 { "vmovdqa", { EXxS, XM }, 0 },
10752 /* VEX_W_0F90_P_0_LEN_0 */
10753 { "kmovw", { MaskG, MaskE }, 0 },
10754 { "kmovq", { MaskG, MaskE }, 0 },
10757 /* VEX_W_0F90_P_2_LEN_0 */
10758 { "kmovb", { MaskG, MaskBDE }, 0 },
10759 { "kmovd", { MaskG, MaskBDE }, 0 },
10762 /* VEX_W_0F91_P_0_LEN_0 */
10763 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10764 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10767 /* VEX_W_0F91_P_2_LEN_0 */
10768 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10769 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10772 /* VEX_W_0F92_P_0_LEN_0 */
10773 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10776 /* VEX_W_0F92_P_2_LEN_0 */
10777 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10780 /* VEX_W_0F92_P_3_LEN_0 */
10781 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10782 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10785 /* VEX_W_0F93_P_0_LEN_0 */
10786 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10789 /* VEX_W_0F93_P_2_LEN_0 */
10790 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10793 /* VEX_W_0F93_P_3_LEN_0 */
10794 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10795 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10798 /* VEX_W_0F98_P_0_LEN_0 */
10799 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10800 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10803 /* VEX_W_0F98_P_2_LEN_0 */
10804 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10805 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10808 /* VEX_W_0F99_P_0_LEN_0 */
10809 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10810 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10813 /* VEX_W_0F99_P_2_LEN_0 */
10814 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10815 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10818 /* VEX_W_0FAE_R_2_M_0 */
10819 { "vldmxcsr", { Md }, 0 },
10822 /* VEX_W_0FAE_R_3_M_0 */
10823 { "vstmxcsr", { Md }, 0 },
10826 /* VEX_W_0FC2_P_0 */
10827 { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
10830 /* VEX_W_0FC2_P_1 */
10831 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10834 /* VEX_W_0FC2_P_2 */
10835 { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
10838 /* VEX_W_0FC2_P_3 */
10839 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10842 /* VEX_W_0FC4_P_2 */
10843 { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
10846 /* VEX_W_0FC5_P_2 */
10847 { "vpextrw", { Gdq, XS, Ib }, 0 },
10850 /* VEX_W_0FD0_P_2 */
10851 { "vaddsubpd", { XM, Vex, EXx }, 0 },
10854 /* VEX_W_0FD0_P_3 */
10855 { "vaddsubps", { XM, Vex, EXx }, 0 },
10858 /* VEX_W_0FD1_P_2 */
10859 { "vpsrlw", { XM, Vex, EXxmm }, 0 },
10862 /* VEX_W_0FD2_P_2 */
10863 { "vpsrld", { XM, Vex, EXxmm }, 0 },
10866 /* VEX_W_0FD3_P_2 */
10867 { "vpsrlq", { XM, Vex, EXxmm }, 0 },
10870 /* VEX_W_0FD4_P_2 */
10871 { "vpaddq", { XM, Vex, EXx }, 0 },
10874 /* VEX_W_0FD5_P_2 */
10875 { "vpmullw", { XM, Vex, EXx }, 0 },
10878 /* VEX_W_0FD6_P_2 */
10879 { "vmovq", { EXqScalarS, XMScalar }, 0 },
10882 /* VEX_W_0FD7_P_2_M_1 */
10883 { "vpmovmskb", { Gdq, XS }, 0 },
10886 /* VEX_W_0FD8_P_2 */
10887 { "vpsubusb", { XM, Vex, EXx }, 0 },
10890 /* VEX_W_0FD9_P_2 */
10891 { "vpsubusw", { XM, Vex, EXx }, 0 },
10894 /* VEX_W_0FDA_P_2 */
10895 { "vpminub", { XM, Vex, EXx }, 0 },
10898 /* VEX_W_0FDB_P_2 */
10899 { "vpand", { XM, Vex, EXx }, 0 },
10902 /* VEX_W_0FDC_P_2 */
10903 { "vpaddusb", { XM, Vex, EXx }, 0 },
10906 /* VEX_W_0FDD_P_2 */
10907 { "vpaddusw", { XM, Vex, EXx }, 0 },
10910 /* VEX_W_0FDE_P_2 */
10911 { "vpmaxub", { XM, Vex, EXx }, 0 },
10914 /* VEX_W_0FDF_P_2 */
10915 { "vpandn", { XM, Vex, EXx }, 0 },
10918 /* VEX_W_0FE0_P_2 */
10919 { "vpavgb", { XM, Vex, EXx }, 0 },
10922 /* VEX_W_0FE1_P_2 */
10923 { "vpsraw", { XM, Vex, EXxmm }, 0 },
10926 /* VEX_W_0FE2_P_2 */
10927 { "vpsrad", { XM, Vex, EXxmm }, 0 },
10930 /* VEX_W_0FE3_P_2 */
10931 { "vpavgw", { XM, Vex, EXx }, 0 },
10934 /* VEX_W_0FE4_P_2 */
10935 { "vpmulhuw", { XM, Vex, EXx }, 0 },
10938 /* VEX_W_0FE5_P_2 */
10939 { "vpmulhw", { XM, Vex, EXx }, 0 },
10942 /* VEX_W_0FE6_P_1 */
10943 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
10946 /* VEX_W_0FE6_P_2 */
10947 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
10950 /* VEX_W_0FE6_P_3 */
10951 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
10954 /* VEX_W_0FE7_P_2_M_0 */
10955 { "vmovntdq", { Mx, XM }, 0 },
10958 /* VEX_W_0FE8_P_2 */
10959 { "vpsubsb", { XM, Vex, EXx }, 0 },
10962 /* VEX_W_0FE9_P_2 */
10963 { "vpsubsw", { XM, Vex, EXx }, 0 },
10966 /* VEX_W_0FEA_P_2 */
10967 { "vpminsw", { XM, Vex, EXx }, 0 },
10970 /* VEX_W_0FEB_P_2 */
10971 { "vpor", { XM, Vex, EXx }, 0 },
10974 /* VEX_W_0FEC_P_2 */
10975 { "vpaddsb", { XM, Vex, EXx }, 0 },
10978 /* VEX_W_0FED_P_2 */
10979 { "vpaddsw", { XM, Vex, EXx }, 0 },
10982 /* VEX_W_0FEE_P_2 */
10983 { "vpmaxsw", { XM, Vex, EXx }, 0 },
10986 /* VEX_W_0FEF_P_2 */
10987 { "vpxor", { XM, Vex, EXx }, 0 },
10990 /* VEX_W_0FF0_P_3_M_0 */
10991 { "vlddqu", { XM, M }, 0 },
10994 /* VEX_W_0FF1_P_2 */
10995 { "vpsllw", { XM, Vex, EXxmm }, 0 },
10998 /* VEX_W_0FF2_P_2 */
10999 { "vpslld", { XM, Vex, EXxmm }, 0 },
11002 /* VEX_W_0FF3_P_2 */
11003 { "vpsllq", { XM, Vex, EXxmm }, 0 },
11006 /* VEX_W_0FF4_P_2 */
11007 { "vpmuludq", { XM, Vex, EXx }, 0 },
11010 /* VEX_W_0FF5_P_2 */
11011 { "vpmaddwd", { XM, Vex, EXx }, 0 },
11014 /* VEX_W_0FF6_P_2 */
11015 { "vpsadbw", { XM, Vex, EXx }, 0 },
11018 /* VEX_W_0FF7_P_2 */
11019 { "vmaskmovdqu", { XM, XS }, 0 },
11022 /* VEX_W_0FF8_P_2 */
11023 { "vpsubb", { XM, Vex, EXx }, 0 },
11026 /* VEX_W_0FF9_P_2 */
11027 { "vpsubw", { XM, Vex, EXx }, 0 },
11030 /* VEX_W_0FFA_P_2 */
11031 { "vpsubd", { XM, Vex, EXx }, 0 },
11034 /* VEX_W_0FFB_P_2 */
11035 { "vpsubq", { XM, Vex, EXx }, 0 },
11038 /* VEX_W_0FFC_P_2 */
11039 { "vpaddb", { XM, Vex, EXx }, 0 },
11042 /* VEX_W_0FFD_P_2 */
11043 { "vpaddw", { XM, Vex, EXx }, 0 },
11046 /* VEX_W_0FFE_P_2 */
11047 { "vpaddd", { XM, Vex, EXx }, 0 },
11050 /* VEX_W_0F3800_P_2 */
11051 { "vpshufb", { XM, Vex, EXx }, 0 },
11054 /* VEX_W_0F3801_P_2 */
11055 { "vphaddw", { XM, Vex, EXx }, 0 },
11058 /* VEX_W_0F3802_P_2 */
11059 { "vphaddd", { XM, Vex, EXx }, 0 },
11062 /* VEX_W_0F3803_P_2 */
11063 { "vphaddsw", { XM, Vex, EXx }, 0 },
11066 /* VEX_W_0F3804_P_2 */
11067 { "vpmaddubsw", { XM, Vex, EXx }, 0 },
11070 /* VEX_W_0F3805_P_2 */
11071 { "vphsubw", { XM, Vex, EXx }, 0 },
11074 /* VEX_W_0F3806_P_2 */
11075 { "vphsubd", { XM, Vex, EXx }, 0 },
11078 /* VEX_W_0F3807_P_2 */
11079 { "vphsubsw", { XM, Vex, EXx }, 0 },
11082 /* VEX_W_0F3808_P_2 */
11083 { "vpsignb", { XM, Vex, EXx }, 0 },
11086 /* VEX_W_0F3809_P_2 */
11087 { "vpsignw", { XM, Vex, EXx }, 0 },
11090 /* VEX_W_0F380A_P_2 */
11091 { "vpsignd", { XM, Vex, EXx }, 0 },
11094 /* VEX_W_0F380B_P_2 */
11095 { "vpmulhrsw", { XM, Vex, EXx }, 0 },
11098 /* VEX_W_0F380C_P_2 */
11099 { "vpermilps", { XM, Vex, EXx }, 0 },
11102 /* VEX_W_0F380D_P_2 */
11103 { "vpermilpd", { XM, Vex, EXx }, 0 },
11106 /* VEX_W_0F380E_P_2 */
11107 { "vtestps", { XM, EXx }, 0 },
11110 /* VEX_W_0F380F_P_2 */
11111 { "vtestpd", { XM, EXx }, 0 },
11114 /* VEX_W_0F3816_P_2 */
11115 { "vpermps", { XM, Vex, EXx }, 0 },
11118 /* VEX_W_0F3817_P_2 */
11119 { "vptest", { XM, EXx }, 0 },
11122 /* VEX_W_0F3818_P_2 */
11123 { "vbroadcastss", { XM, EXxmm_md }, 0 },
11126 /* VEX_W_0F3819_P_2 */
11127 { "vbroadcastsd", { XM, EXxmm_mq }, 0 },
11130 /* VEX_W_0F381A_P_2_M_0 */
11131 { "vbroadcastf128", { XM, Mxmm }, 0 },
11134 /* VEX_W_0F381C_P_2 */
11135 { "vpabsb", { XM, EXx }, 0 },
11138 /* VEX_W_0F381D_P_2 */
11139 { "vpabsw", { XM, EXx }, 0 },
11142 /* VEX_W_0F381E_P_2 */
11143 { "vpabsd", { XM, EXx }, 0 },
11146 /* VEX_W_0F3820_P_2 */
11147 { "vpmovsxbw", { XM, EXxmmq }, 0 },
11150 /* VEX_W_0F3821_P_2 */
11151 { "vpmovsxbd", { XM, EXxmmqd }, 0 },
11154 /* VEX_W_0F3822_P_2 */
11155 { "vpmovsxbq", { XM, EXxmmdw }, 0 },
11158 /* VEX_W_0F3823_P_2 */
11159 { "vpmovsxwd", { XM, EXxmmq }, 0 },
11162 /* VEX_W_0F3824_P_2 */
11163 { "vpmovsxwq", { XM, EXxmmqd }, 0 },
11166 /* VEX_W_0F3825_P_2 */
11167 { "vpmovsxdq", { XM, EXxmmq }, 0 },
11170 /* VEX_W_0F3828_P_2 */
11171 { "vpmuldq", { XM, Vex, EXx }, 0 },
11174 /* VEX_W_0F3829_P_2 */
11175 { "vpcmpeqq", { XM, Vex, EXx }, 0 },
11178 /* VEX_W_0F382A_P_2_M_0 */
11179 { "vmovntdqa", { XM, Mx }, 0 },
11182 /* VEX_W_0F382B_P_2 */
11183 { "vpackusdw", { XM, Vex, EXx }, 0 },
11186 /* VEX_W_0F382C_P_2_M_0 */
11187 { "vmaskmovps", { XM, Vex, Mx }, 0 },
11190 /* VEX_W_0F382D_P_2_M_0 */
11191 { "vmaskmovpd", { XM, Vex, Mx }, 0 },
11194 /* VEX_W_0F382E_P_2_M_0 */
11195 { "vmaskmovps", { Mx, Vex, XM }, 0 },
11198 /* VEX_W_0F382F_P_2_M_0 */
11199 { "vmaskmovpd", { Mx, Vex, XM }, 0 },
11202 /* VEX_W_0F3830_P_2 */
11203 { "vpmovzxbw", { XM, EXxmmq }, 0 },
11206 /* VEX_W_0F3831_P_2 */
11207 { "vpmovzxbd", { XM, EXxmmqd }, 0 },
11210 /* VEX_W_0F3832_P_2 */
11211 { "vpmovzxbq", { XM, EXxmmdw }, 0 },
11214 /* VEX_W_0F3833_P_2 */
11215 { "vpmovzxwd", { XM, EXxmmq }, 0 },
11218 /* VEX_W_0F3834_P_2 */
11219 { "vpmovzxwq", { XM, EXxmmqd }, 0 },
11222 /* VEX_W_0F3835_P_2 */
11223 { "vpmovzxdq", { XM, EXxmmq }, 0 },
11226 /* VEX_W_0F3836_P_2 */
11227 { "vpermd", { XM, Vex, EXx }, 0 },
11230 /* VEX_W_0F3837_P_2 */
11231 { "vpcmpgtq", { XM, Vex, EXx }, 0 },
11234 /* VEX_W_0F3838_P_2 */
11235 { "vpminsb", { XM, Vex, EXx }, 0 },
11238 /* VEX_W_0F3839_P_2 */
11239 { "vpminsd", { XM, Vex, EXx }, 0 },
11242 /* VEX_W_0F383A_P_2 */
11243 { "vpminuw", { XM, Vex, EXx }, 0 },
11246 /* VEX_W_0F383B_P_2 */
11247 { "vpminud", { XM, Vex, EXx }, 0 },
11250 /* VEX_W_0F383C_P_2 */
11251 { "vpmaxsb", { XM, Vex, EXx }, 0 },
11254 /* VEX_W_0F383D_P_2 */
11255 { "vpmaxsd", { XM, Vex, EXx }, 0 },
11258 /* VEX_W_0F383E_P_2 */
11259 { "vpmaxuw", { XM, Vex, EXx }, 0 },
11262 /* VEX_W_0F383F_P_2 */
11263 { "vpmaxud", { XM, Vex, EXx }, 0 },
11266 /* VEX_W_0F3840_P_2 */
11267 { "vpmulld", { XM, Vex, EXx }, 0 },
11270 /* VEX_W_0F3841_P_2 */
11271 { "vphminposuw", { XM, EXx }, 0 },
11274 /* VEX_W_0F3846_P_2 */
11275 { "vpsravd", { XM, Vex, EXx }, 0 },
11278 /* VEX_W_0F3858_P_2 */
11279 { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11282 /* VEX_W_0F3859_P_2 */
11283 { "vpbroadcastq", { XM, EXxmm_mq }, 0 },
11286 /* VEX_W_0F385A_P_2_M_0 */
11287 { "vbroadcasti128", { XM, Mxmm }, 0 },
11290 /* VEX_W_0F3878_P_2 */
11291 { "vpbroadcastb", { XM, EXxmm_mb }, 0 },
11294 /* VEX_W_0F3879_P_2 */
11295 { "vpbroadcastw", { XM, EXxmm_mw }, 0 },
11298 /* VEX_W_0F38CF_P_2 */
11299 { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
11302 /* VEX_W_0F38DB_P_2 */
11303 { "vaesimc", { XM, EXx }, 0 },
11306 /* VEX_W_0F3A00_P_2 */
11308 { "vpermq", { XM, EXx, Ib }, 0 },
11311 /* VEX_W_0F3A01_P_2 */
11313 { "vpermpd", { XM, EXx, Ib }, 0 },
11316 /* VEX_W_0F3A02_P_2 */
11317 { "vpblendd", { XM, Vex, EXx, Ib }, 0 },
11320 /* VEX_W_0F3A04_P_2 */
11321 { "vpermilps", { XM, EXx, Ib }, 0 },
11324 /* VEX_W_0F3A05_P_2 */
11325 { "vpermilpd", { XM, EXx, Ib }, 0 },
11328 /* VEX_W_0F3A06_P_2 */
11329 { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 },
11332 /* VEX_W_0F3A08_P_2 */
11333 { "vroundps", { XM, EXx, Ib }, 0 },
11336 /* VEX_W_0F3A09_P_2 */
11337 { "vroundpd", { XM, EXx, Ib }, 0 },
11340 /* VEX_W_0F3A0A_P_2 */
11341 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11344 /* VEX_W_0F3A0B_P_2 */
11345 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11348 /* VEX_W_0F3A0C_P_2 */
11349 { "vblendps", { XM, Vex, EXx, Ib }, 0 },
11352 /* VEX_W_0F3A0D_P_2 */
11353 { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
11356 /* VEX_W_0F3A0E_P_2 */
11357 { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
11360 /* VEX_W_0F3A0F_P_2 */
11361 { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
11364 /* VEX_W_0F3A14_P_2 */
11365 { "vpextrb", { Edqb, XM, Ib }, 0 },
11368 /* VEX_W_0F3A15_P_2 */
11369 { "vpextrw", { Edqw, XM, Ib }, 0 },
11372 /* VEX_W_0F3A18_P_2 */
11373 { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 },
11376 /* VEX_W_0F3A19_P_2 */
11377 { "vextractf128", { EXxmm, XM, Ib }, 0 },
11380 /* VEX_W_0F3A20_P_2 */
11381 { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
11384 /* VEX_W_0F3A21_P_2 */
11385 { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
11388 /* VEX_W_0F3A30_P_2_LEN_0 */
11389 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11390 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11393 /* VEX_W_0F3A31_P_2_LEN_0 */
11394 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11395 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11398 /* VEX_W_0F3A32_P_2_LEN_0 */
11399 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11400 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11403 /* VEX_W_0F3A33_P_2_LEN_0 */
11404 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11405 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11408 /* VEX_W_0F3A38_P_2 */
11409 { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 },
11412 /* VEX_W_0F3A39_P_2 */
11413 { "vextracti128", { EXxmm, XM, Ib }, 0 },
11416 /* VEX_W_0F3A40_P_2 */
11417 { "vdpps", { XM, Vex, EXx, Ib }, 0 },
11420 /* VEX_W_0F3A41_P_2 */
11421 { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
11424 /* VEX_W_0F3A42_P_2 */
11425 { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
11428 /* VEX_W_0F3A46_P_2 */
11429 { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
11432 /* VEX_W_0F3A48_P_2 */
11433 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11434 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11437 /* VEX_W_0F3A49_P_2 */
11438 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11439 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11442 /* VEX_W_0F3A4A_P_2 */
11443 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 },
11446 /* VEX_W_0F3A4B_P_2 */
11447 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 },
11450 /* VEX_W_0F3A4C_P_2 */
11451 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
11454 /* VEX_W_0F3A62_P_2 */
11455 { "vpcmpistrm", { XM, EXx, Ib }, 0 },
11458 /* VEX_W_0F3A63_P_2 */
11459 { "vpcmpistri", { XM, EXx, Ib }, 0 },
11462 /* VEX_W_0F3ACE_P_2 */
11464 { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
11467 /* VEX_W_0F3ACF_P_2 */
11469 { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 },
11472 /* VEX_W_0F3ADF_P_2 */
11473 { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11475 #define NEED_VEX_W_TABLE
11476 #include "i386-dis-evex.h"
11477 #undef NEED_VEX_W_TABLE
11480 static const struct dis386 mod_table[][2] = {
11483 { "leaS", { Gv, M }, 0 },
11488 { RM_TABLE (RM_C6_REG_7) },
11493 { RM_TABLE (RM_C7_REG_7) },
11497 { "Jcall^", { indirEp }, 0 },
11501 { "Jjmp^", { indirEp }, 0 },
11504 /* MOD_0F01_REG_0 */
11505 { X86_64_TABLE (X86_64_0F01_REG_0) },
11506 { RM_TABLE (RM_0F01_REG_0) },
11509 /* MOD_0F01_REG_1 */
11510 { X86_64_TABLE (X86_64_0F01_REG_1) },
11511 { RM_TABLE (RM_0F01_REG_1) },
11514 /* MOD_0F01_REG_2 */
11515 { X86_64_TABLE (X86_64_0F01_REG_2) },
11516 { RM_TABLE (RM_0F01_REG_2) },
11519 /* MOD_0F01_REG_3 */
11520 { X86_64_TABLE (X86_64_0F01_REG_3) },
11521 { RM_TABLE (RM_0F01_REG_3) },
11524 /* MOD_0F01_REG_5 */
11525 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
11526 { RM_TABLE (RM_0F01_REG_5) },
11529 /* MOD_0F01_REG_7 */
11530 { "invlpg", { Mb }, 0 },
11531 { RM_TABLE (RM_0F01_REG_7) },
11534 /* MOD_0F12_PREFIX_0 */
11535 { "movlps", { XM, EXq }, PREFIX_OPCODE },
11536 { "movhlps", { XM, EXq }, PREFIX_OPCODE },
11540 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
11543 /* MOD_0F16_PREFIX_0 */
11544 { "movhps", { XM, EXq }, 0 },
11545 { "movlhps", { XM, EXq }, 0 },
11549 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
11552 /* MOD_0F18_REG_0 */
11553 { "prefetchnta", { Mb }, 0 },
11556 /* MOD_0F18_REG_1 */
11557 { "prefetcht0", { Mb }, 0 },
11560 /* MOD_0F18_REG_2 */
11561 { "prefetcht1", { Mb }, 0 },
11564 /* MOD_0F18_REG_3 */
11565 { "prefetcht2", { Mb }, 0 },
11568 /* MOD_0F18_REG_4 */
11569 { "nop/reserved", { Mb }, 0 },
11572 /* MOD_0F18_REG_5 */
11573 { "nop/reserved", { Mb }, 0 },
11576 /* MOD_0F18_REG_6 */
11577 { "nop/reserved", { Mb }, 0 },
11580 /* MOD_0F18_REG_7 */
11581 { "nop/reserved", { Mb }, 0 },
11584 /* MOD_0F1A_PREFIX_0 */
11585 { "bndldx", { Gbnd, Ev_bnd }, 0 },
11586 { "nopQ", { Ev }, 0 },
11589 /* MOD_0F1B_PREFIX_0 */
11590 { "bndstx", { Ev_bnd, Gbnd }, 0 },
11591 { "nopQ", { Ev }, 0 },
11594 /* MOD_0F1B_PREFIX_1 */
11595 { "bndmk", { Gbnd, Ev_bnd }, 0 },
11596 { "nopQ", { Ev }, 0 },
11599 /* MOD_0F1E_PREFIX_1 */
11600 { "nopQ", { Ev }, 0 },
11601 { REG_TABLE (REG_0F1E_MOD_3) },
11606 { "movL", { Rd, Td }, 0 },
11611 { "movL", { Td, Rd }, 0 },
11614 /* MOD_0F2B_PREFIX_0 */
11615 {"movntps", { Mx, XM }, PREFIX_OPCODE },
11618 /* MOD_0F2B_PREFIX_1 */
11619 {"movntss", { Md, XM }, PREFIX_OPCODE },
11622 /* MOD_0F2B_PREFIX_2 */
11623 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
11626 /* MOD_0F2B_PREFIX_3 */
11627 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
11632 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
11635 /* MOD_0F71_REG_2 */
11637 { "psrlw", { MS, Ib }, 0 },
11640 /* MOD_0F71_REG_4 */
11642 { "psraw", { MS, Ib }, 0 },
11645 /* MOD_0F71_REG_6 */
11647 { "psllw", { MS, Ib }, 0 },
11650 /* MOD_0F72_REG_2 */
11652 { "psrld", { MS, Ib }, 0 },
11655 /* MOD_0F72_REG_4 */
11657 { "psrad", { MS, Ib }, 0 },
11660 /* MOD_0F72_REG_6 */
11662 { "pslld", { MS, Ib }, 0 },
11665 /* MOD_0F73_REG_2 */
11667 { "psrlq", { MS, Ib }, 0 },
11670 /* MOD_0F73_REG_3 */
11672 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11675 /* MOD_0F73_REG_6 */
11677 { "psllq", { MS, Ib }, 0 },
11680 /* MOD_0F73_REG_7 */
11682 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11685 /* MOD_0FAE_REG_0 */
11686 { "fxsave", { FXSAVE }, 0 },
11687 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11690 /* MOD_0FAE_REG_1 */
11691 { "fxrstor", { FXSAVE }, 0 },
11692 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11695 /* MOD_0FAE_REG_2 */
11696 { "ldmxcsr", { Md }, 0 },
11697 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11700 /* MOD_0FAE_REG_3 */
11701 { "stmxcsr", { Md }, 0 },
11702 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11705 /* MOD_0FAE_REG_4 */
11706 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11707 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11710 /* MOD_0FAE_REG_5 */
11711 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
11712 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
11715 /* MOD_0FAE_REG_6 */
11716 { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11717 { RM_TABLE (RM_0FAE_REG_6) },
11720 /* MOD_0FAE_REG_7 */
11721 { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11722 { RM_TABLE (RM_0FAE_REG_7) },
11726 { "lssS", { Gv, Mp }, 0 },
11730 { "lfsS", { Gv, Mp }, 0 },
11734 { "lgsS", { Gv, Mp }, 0 },
11738 { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11741 /* MOD_0FC7_REG_3 */
11742 { "xrstors", { FXSAVE }, 0 },
11745 /* MOD_0FC7_REG_4 */
11746 { "xsavec", { FXSAVE }, 0 },
11749 /* MOD_0FC7_REG_5 */
11750 { "xsaves", { FXSAVE }, 0 },
11753 /* MOD_0FC7_REG_6 */
11754 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11755 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11758 /* MOD_0FC7_REG_7 */
11759 { "vmptrst", { Mq }, 0 },
11760 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11765 { "pmovmskb", { Gdq, MS }, 0 },
11768 /* MOD_0FE7_PREFIX_2 */
11769 { "movntdq", { Mx, XM }, 0 },
11772 /* MOD_0FF0_PREFIX_3 */
11773 { "lddqu", { XM, M }, 0 },
11776 /* MOD_0F382A_PREFIX_2 */
11777 { "movntdqa", { XM, Mx }, 0 },
11780 /* MOD_0F38F5_PREFIX_2 */
11781 { "wrussK", { M, Gdq }, PREFIX_OPCODE },
11784 /* MOD_0F38F6_PREFIX_0 */
11785 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
11789 { "bound{S|}", { Gv, Ma }, 0 },
11790 { EVEX_TABLE (EVEX_0F) },
11794 { "lesS", { Gv, Mp }, 0 },
11795 { VEX_C4_TABLE (VEX_0F) },
11799 { "ldsS", { Gv, Mp }, 0 },
11800 { VEX_C5_TABLE (VEX_0F) },
11803 /* MOD_VEX_0F12_PREFIX_0 */
11804 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11805 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11809 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11812 /* MOD_VEX_0F16_PREFIX_0 */
11813 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11814 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11818 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11822 { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11825 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11827 { "kandw", { MaskG, MaskVex, MaskR }, 0 },
11830 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11832 { "kandq", { MaskG, MaskVex, MaskR }, 0 },
11835 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11837 { "kandb", { MaskG, MaskVex, MaskR }, 0 },
11840 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11842 { "kandd", { MaskG, MaskVex, MaskR }, 0 },
11845 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11847 { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
11850 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11852 { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
11855 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11857 { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
11860 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11862 { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
11865 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11867 { "knotw", { MaskG, MaskR }, 0 },
11870 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11872 { "knotq", { MaskG, MaskR }, 0 },
11875 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11877 { "knotb", { MaskG, MaskR }, 0 },
11880 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11882 { "knotd", { MaskG, MaskR }, 0 },
11885 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11887 { "korw", { MaskG, MaskVex, MaskR }, 0 },
11890 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11892 { "korq", { MaskG, MaskVex, MaskR }, 0 },
11895 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11897 { "korb", { MaskG, MaskVex, MaskR }, 0 },
11900 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11902 { "kord", { MaskG, MaskVex, MaskR }, 0 },
11905 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11907 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
11910 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11912 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
11915 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11917 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
11920 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11922 { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
11925 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11927 { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
11930 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11932 { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
11935 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11937 { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
11940 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11942 { "kxord", { MaskG, MaskVex, MaskR }, 0 },
11945 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11947 { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
11950 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11952 { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
11955 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11957 { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
11960 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11962 { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
11965 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11967 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
11970 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11972 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
11975 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11977 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
11982 { VEX_W_TABLE (VEX_W_0F50_M_0) },
11985 /* MOD_VEX_0F71_REG_2 */
11987 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11990 /* MOD_VEX_0F71_REG_4 */
11992 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11995 /* MOD_VEX_0F71_REG_6 */
11997 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
12000 /* MOD_VEX_0F72_REG_2 */
12002 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12005 /* MOD_VEX_0F72_REG_4 */
12007 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12010 /* MOD_VEX_0F72_REG_6 */
12012 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12015 /* MOD_VEX_0F73_REG_2 */
12017 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12020 /* MOD_VEX_0F73_REG_3 */
12022 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12025 /* MOD_VEX_0F73_REG_6 */
12027 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12030 /* MOD_VEX_0F73_REG_7 */
12032 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12035 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12036 { "kmovw", { Ew, MaskG }, 0 },
12040 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12041 { "kmovq", { Eq, MaskG }, 0 },
12045 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12046 { "kmovb", { Eb, MaskG }, 0 },
12050 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12051 { "kmovd", { Ed, MaskG }, 0 },
12055 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12057 { "kmovw", { MaskG, Rdq }, 0 },
12060 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12062 { "kmovb", { MaskG, Rdq }, 0 },
12065 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12067 { "kmovd", { MaskG, Rdq }, 0 },
12070 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12072 { "kmovq", { MaskG, Rdq }, 0 },
12075 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12077 { "kmovw", { Gdq, MaskR }, 0 },
12080 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12082 { "kmovb", { Gdq, MaskR }, 0 },
12085 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12087 { "kmovd", { Gdq, MaskR }, 0 },
12090 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12092 { "kmovq", { Gdq, MaskR }, 0 },
12095 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12097 { "kortestw", { MaskG, MaskR }, 0 },
12100 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12102 { "kortestq", { MaskG, MaskR }, 0 },
12105 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12107 { "kortestb", { MaskG, MaskR }, 0 },
12110 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12112 { "kortestd", { MaskG, MaskR }, 0 },
12115 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12117 { "ktestw", { MaskG, MaskR }, 0 },
12120 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12122 { "ktestq", { MaskG, MaskR }, 0 },
12125 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12127 { "ktestb", { MaskG, MaskR }, 0 },
12130 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12132 { "ktestd", { MaskG, MaskR }, 0 },
12135 /* MOD_VEX_0FAE_REG_2 */
12136 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12139 /* MOD_VEX_0FAE_REG_3 */
12140 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12143 /* MOD_VEX_0FD7_PREFIX_2 */
12145 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12148 /* MOD_VEX_0FE7_PREFIX_2 */
12149 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12152 /* MOD_VEX_0FF0_PREFIX_3 */
12153 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12156 /* MOD_VEX_0F381A_PREFIX_2 */
12157 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12160 /* MOD_VEX_0F382A_PREFIX_2 */
12161 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12164 /* MOD_VEX_0F382C_PREFIX_2 */
12165 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12168 /* MOD_VEX_0F382D_PREFIX_2 */
12169 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12172 /* MOD_VEX_0F382E_PREFIX_2 */
12173 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12176 /* MOD_VEX_0F382F_PREFIX_2 */
12177 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12180 /* MOD_VEX_0F385A_PREFIX_2 */
12181 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12184 /* MOD_VEX_0F388C_PREFIX_2 */
12185 { "vpmaskmov%LW", { XM, Vex, Mx }, 0 },
12188 /* MOD_VEX_0F388E_PREFIX_2 */
12189 { "vpmaskmov%LW", { Mx, Vex, XM }, 0 },
12192 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12194 { "kshiftrb", { MaskG, MaskR, Ib }, 0 },
12197 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12199 { "kshiftrw", { MaskG, MaskR, Ib }, 0 },
12202 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12204 { "kshiftrd", { MaskG, MaskR, Ib }, 0 },
12207 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12209 { "kshiftrq", { MaskG, MaskR, Ib }, 0 },
12212 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12214 { "kshiftlb", { MaskG, MaskR, Ib }, 0 },
12217 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12219 { "kshiftlw", { MaskG, MaskR, Ib }, 0 },
12222 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12224 { "kshiftld", { MaskG, MaskR, Ib }, 0 },
12227 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12229 { "kshiftlq", { MaskG, MaskR, Ib }, 0 },
12231 #define NEED_MOD_TABLE
12232 #include "i386-dis-evex.h"
12233 #undef NEED_MOD_TABLE
12236 static const struct dis386 rm_table[][8] = {
12239 { "xabort", { Skip_MODRM, Ib }, 0 },
12243 { "xbeginT", { Skip_MODRM, Jv }, 0 },
12246 /* RM_0F01_REG_0 */
12248 { "vmcall", { Skip_MODRM }, 0 },
12249 { "vmlaunch", { Skip_MODRM }, 0 },
12250 { "vmresume", { Skip_MODRM }, 0 },
12251 { "vmxoff", { Skip_MODRM }, 0 },
12254 /* RM_0F01_REG_1 */
12255 { "monitor", { { OP_Monitor, 0 } }, 0 },
12256 { "mwait", { { OP_Mwait, 0 } }, 0 },
12257 { "clac", { Skip_MODRM }, 0 },
12258 { "stac", { Skip_MODRM }, 0 },
12262 { "encls", { Skip_MODRM }, 0 },
12265 /* RM_0F01_REG_2 */
12266 { "xgetbv", { Skip_MODRM }, 0 },
12267 { "xsetbv", { Skip_MODRM }, 0 },
12270 { "vmfunc", { Skip_MODRM }, 0 },
12271 { "xend", { Skip_MODRM }, 0 },
12272 { "xtest", { Skip_MODRM }, 0 },
12273 { "enclu", { Skip_MODRM }, 0 },
12276 /* RM_0F01_REG_3 */
12277 { "vmrun", { Skip_MODRM }, 0 },
12278 { "vmmcall", { Skip_MODRM }, 0 },
12279 { "vmload", { Skip_MODRM }, 0 },
12280 { "vmsave", { Skip_MODRM }, 0 },
12281 { "stgi", { Skip_MODRM }, 0 },
12282 { "clgi", { Skip_MODRM }, 0 },
12283 { "skinit", { Skip_MODRM }, 0 },
12284 { "invlpga", { Skip_MODRM }, 0 },
12287 /* RM_0F01_REG_5 */
12288 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
12290 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
12294 { "rdpkru", { Skip_MODRM }, 0 },
12295 { "wrpkru", { Skip_MODRM }, 0 },
12298 /* RM_0F01_REG_7 */
12299 { "swapgs", { Skip_MODRM }, 0 },
12300 { "rdtscp", { Skip_MODRM }, 0 },
12301 { "monitorx", { { OP_Monitor, 0 } }, 0 },
12302 { "mwaitx", { { OP_Mwaitx, 0 } }, 0 },
12303 { "clzero", { Skip_MODRM }, 0 },
12306 /* RM_0F1E_MOD_3_REG_7 */
12307 { "nopQ", { Ev }, 0 },
12308 { "nopQ", { Ev }, 0 },
12309 { "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
12310 { "endbr32", { Skip_MODRM }, PREFIX_OPCODE },
12311 { "nopQ", { Ev }, 0 },
12312 { "nopQ", { Ev }, 0 },
12313 { "nopQ", { Ev }, 0 },
12314 { "nopQ", { Ev }, 0 },
12317 /* RM_0FAE_REG_6 */
12318 { "mfence", { Skip_MODRM }, 0 },
12321 /* RM_0FAE_REG_7 */
12322 { "sfence", { Skip_MODRM }, 0 },
12327 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12329 /* We use the high bit to indicate different name for the same
12331 #define REP_PREFIX (0xf3 | 0x100)
12332 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12333 #define XRELEASE_PREFIX (0xf3 | 0x400)
12334 #define BND_PREFIX (0xf2 | 0x400)
12335 #define NOTRACK_PREFIX (0x3e | 0x100)
12340 int newrex, i, length;
12346 last_lock_prefix = -1;
12347 last_repz_prefix = -1;
12348 last_repnz_prefix = -1;
12349 last_data_prefix = -1;
12350 last_addr_prefix = -1;
12351 last_rex_prefix = -1;
12352 last_seg_prefix = -1;
12354 active_seg_prefix = 0;
12355 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12356 all_prefixes[i] = 0;
12359 /* The maximum instruction length is 15bytes. */
12360 while (length < MAX_CODE_LENGTH - 1)
12362 FETCH_DATA (the_info, codep + 1);
12366 /* REX prefixes family. */
12383 if (address_mode == mode_64bit)
12387 last_rex_prefix = i;
12390 prefixes |= PREFIX_REPZ;
12391 last_repz_prefix = i;
12394 prefixes |= PREFIX_REPNZ;
12395 last_repnz_prefix = i;
12398 prefixes |= PREFIX_LOCK;
12399 last_lock_prefix = i;
12402 prefixes |= PREFIX_CS;
12403 last_seg_prefix = i;
12404 active_seg_prefix = PREFIX_CS;
12407 prefixes |= PREFIX_SS;
12408 last_seg_prefix = i;
12409 active_seg_prefix = PREFIX_SS;
12412 prefixes |= PREFIX_DS;
12413 last_seg_prefix = i;
12414 active_seg_prefix = PREFIX_DS;
12417 prefixes |= PREFIX_ES;
12418 last_seg_prefix = i;
12419 active_seg_prefix = PREFIX_ES;
12422 prefixes |= PREFIX_FS;
12423 last_seg_prefix = i;
12424 active_seg_prefix = PREFIX_FS;
12427 prefixes |= PREFIX_GS;
12428 last_seg_prefix = i;
12429 active_seg_prefix = PREFIX_GS;
12432 prefixes |= PREFIX_DATA;
12433 last_data_prefix = i;
12436 prefixes |= PREFIX_ADDR;
12437 last_addr_prefix = i;
12440 /* fwait is really an instruction. If there are prefixes
12441 before the fwait, they belong to the fwait, *not* to the
12442 following instruction. */
12444 if (prefixes || rex)
12446 prefixes |= PREFIX_FWAIT;
12448 /* This ensures that the previous REX prefixes are noticed
12449 as unused prefixes, as in the return case below. */
12453 prefixes = PREFIX_FWAIT;
12458 /* Rex is ignored when followed by another prefix. */
12464 if (*codep != FWAIT_OPCODE)
12465 all_prefixes[i++] = *codep;
12473 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12476 static const char *
12477 prefix_name (int pref, int sizeflag)
12479 static const char *rexes [16] =
12482 "rex.B", /* 0x41 */
12483 "rex.X", /* 0x42 */
12484 "rex.XB", /* 0x43 */
12485 "rex.R", /* 0x44 */
12486 "rex.RB", /* 0x45 */
12487 "rex.RX", /* 0x46 */
12488 "rex.RXB", /* 0x47 */
12489 "rex.W", /* 0x48 */
12490 "rex.WB", /* 0x49 */
12491 "rex.WX", /* 0x4a */
12492 "rex.WXB", /* 0x4b */
12493 "rex.WR", /* 0x4c */
12494 "rex.WRB", /* 0x4d */
12495 "rex.WRX", /* 0x4e */
12496 "rex.WRXB", /* 0x4f */
12501 /* REX prefixes family. */
12518 return rexes [pref - 0x40];
12538 return (sizeflag & DFLAG) ? "data16" : "data32";
12540 if (address_mode == mode_64bit)
12541 return (sizeflag & AFLAG) ? "addr32" : "addr64";
12543 return (sizeflag & AFLAG) ? "addr16" : "addr32";
12548 case XACQUIRE_PREFIX:
12550 case XRELEASE_PREFIX:
12554 case NOTRACK_PREFIX:
12561 static char op_out[MAX_OPERANDS][100];
12562 static int op_ad, op_index[MAX_OPERANDS];
12563 static int two_source_ops;
12564 static bfd_vma op_address[MAX_OPERANDS];
12565 static bfd_vma op_riprel[MAX_OPERANDS];
12566 static bfd_vma start_pc;
12569 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12570 * (see topic "Redundant prefixes" in the "Differences from 8086"
12571 * section of the "Virtual 8086 Mode" chapter.)
12572 * 'pc' should be the address of this instruction, it will
12573 * be used to print the target address if this is a relative jump or call
12574 * The function returns the length of this instruction in bytes.
12577 static char intel_syntax;
12578 static char intel_mnemonic = !SYSV386_COMPAT;
12579 static char open_char;
12580 static char close_char;
12581 static char separator_char;
12582 static char scale_char;
12590 static enum x86_64_isa isa64;
12592 /* Here for backwards compatibility. When gdb stops using
12593 print_insn_i386_att and print_insn_i386_intel these functions can
12594 disappear, and print_insn_i386 be merged into print_insn. */
12596 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12600 return print_insn (pc, info);
12604 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12608 return print_insn (pc, info);
12612 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12616 return print_insn (pc, info);
12620 print_i386_disassembler_options (FILE *stream)
12622 fprintf (stream, _("\n\
12623 The following i386/x86-64 specific disassembler options are supported for use\n\
12624 with the -M switch (multiple options should be separated by commas):\n"));
12626 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
12627 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
12628 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
12629 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
12630 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
12631 fprintf (stream, _(" att-mnemonic\n"
12632 " Display instruction in AT&T mnemonic\n"));
12633 fprintf (stream, _(" intel-mnemonic\n"
12634 " Display instruction in Intel mnemonic\n"));
12635 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
12636 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
12637 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
12638 fprintf (stream, _(" data32 Assume 32bit data size\n"));
12639 fprintf (stream, _(" data16 Assume 16bit data size\n"));
12640 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12641 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
12642 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
12646 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12648 /* Get a pointer to struct dis386 with a valid name. */
12650 static const struct dis386 *
12651 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12653 int vindex, vex_table_index;
12655 if (dp->name != NULL)
12658 switch (dp->op[0].bytemode)
12660 case USE_REG_TABLE:
12661 dp = ®_table[dp->op[1].bytemode][modrm.reg];
12664 case USE_MOD_TABLE:
12665 vindex = modrm.mod == 0x3 ? 1 : 0;
12666 dp = &mod_table[dp->op[1].bytemode][vindex];
12670 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12673 case USE_PREFIX_TABLE:
12676 /* The prefix in VEX is implicit. */
12677 switch (vex.prefix)
12682 case REPE_PREFIX_OPCODE:
12685 case DATA_PREFIX_OPCODE:
12688 case REPNE_PREFIX_OPCODE:
12698 int last_prefix = -1;
12701 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12702 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12704 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12706 if (last_repz_prefix > last_repnz_prefix)
12709 prefix = PREFIX_REPZ;
12710 last_prefix = last_repz_prefix;
12715 prefix = PREFIX_REPNZ;
12716 last_prefix = last_repnz_prefix;
12719 /* Check if prefix should be ignored. */
12720 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12721 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12726 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12729 prefix = PREFIX_DATA;
12730 last_prefix = last_data_prefix;
12735 used_prefixes |= prefix;
12736 all_prefixes[last_prefix] = 0;
12739 dp = &prefix_table[dp->op[1].bytemode][vindex];
12742 case USE_X86_64_TABLE:
12743 vindex = address_mode == mode_64bit ? 1 : 0;
12744 dp = &x86_64_table[dp->op[1].bytemode][vindex];
12747 case USE_3BYTE_TABLE:
12748 FETCH_DATA (info, codep + 2);
12750 dp = &three_byte_table[dp->op[1].bytemode][vindex];
12752 modrm.mod = (*codep >> 6) & 3;
12753 modrm.reg = (*codep >> 3) & 7;
12754 modrm.rm = *codep & 7;
12757 case USE_VEX_LEN_TABLE:
12761 switch (vex.length)
12774 dp = &vex_len_table[dp->op[1].bytemode][vindex];
12777 case USE_XOP_8F_TABLE:
12778 FETCH_DATA (info, codep + 3);
12779 /* All bits in the REX prefix are ignored. */
12781 rex = ~(*codep >> 5) & 0x7;
12783 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12784 switch ((*codep & 0x1f))
12790 vex_table_index = XOP_08;
12793 vex_table_index = XOP_09;
12796 vex_table_index = XOP_0A;
12800 vex.w = *codep & 0x80;
12801 if (vex.w && address_mode == mode_64bit)
12804 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12805 if (address_mode != mode_64bit)
12807 /* In 16/32-bit mode REX_B is silently ignored. */
12809 if (vex.register_specifier > 0x7)
12816 vex.length = (*codep & 0x4) ? 256 : 128;
12817 switch ((*codep & 0x3))
12823 vex.prefix = DATA_PREFIX_OPCODE;
12826 vex.prefix = REPE_PREFIX_OPCODE;
12829 vex.prefix = REPNE_PREFIX_OPCODE;
12836 dp = &xop_table[vex_table_index][vindex];
12839 FETCH_DATA (info, codep + 1);
12840 modrm.mod = (*codep >> 6) & 3;
12841 modrm.reg = (*codep >> 3) & 7;
12842 modrm.rm = *codep & 7;
12845 case USE_VEX_C4_TABLE:
12847 FETCH_DATA (info, codep + 3);
12848 /* All bits in the REX prefix are ignored. */
12850 rex = ~(*codep >> 5) & 0x7;
12851 switch ((*codep & 0x1f))
12857 vex_table_index = VEX_0F;
12860 vex_table_index = VEX_0F38;
12863 vex_table_index = VEX_0F3A;
12867 vex.w = *codep & 0x80;
12868 if (address_mode == mode_64bit)
12872 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12876 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12877 is ignored, other REX bits are 0 and the highest bit in
12878 VEX.vvvv is also ignored. */
12880 vex.register_specifier = (~(*codep >> 3)) & 0x7;
12882 vex.length = (*codep & 0x4) ? 256 : 128;
12883 switch ((*codep & 0x3))
12889 vex.prefix = DATA_PREFIX_OPCODE;
12892 vex.prefix = REPE_PREFIX_OPCODE;
12895 vex.prefix = REPNE_PREFIX_OPCODE;
12902 dp = &vex_table[vex_table_index][vindex];
12904 /* There is no MODRM byte for VEX0F 77. */
12905 if (vex_table_index != VEX_0F || vindex != 0x77)
12907 FETCH_DATA (info, codep + 1);
12908 modrm.mod = (*codep >> 6) & 3;
12909 modrm.reg = (*codep >> 3) & 7;
12910 modrm.rm = *codep & 7;
12914 case USE_VEX_C5_TABLE:
12916 FETCH_DATA (info, codep + 2);
12917 /* All bits in the REX prefix are ignored. */
12919 rex = (*codep & 0x80) ? 0 : REX_R;
12921 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12923 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12925 vex.length = (*codep & 0x4) ? 256 : 128;
12926 switch ((*codep & 0x3))
12932 vex.prefix = DATA_PREFIX_OPCODE;
12935 vex.prefix = REPE_PREFIX_OPCODE;
12938 vex.prefix = REPNE_PREFIX_OPCODE;
12945 dp = &vex_table[dp->op[1].bytemode][vindex];
12947 /* There is no MODRM byte for VEX 77. */
12948 if (vindex != 0x77)
12950 FETCH_DATA (info, codep + 1);
12951 modrm.mod = (*codep >> 6) & 3;
12952 modrm.reg = (*codep >> 3) & 7;
12953 modrm.rm = *codep & 7;
12957 case USE_VEX_W_TABLE:
12961 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12964 case USE_EVEX_TABLE:
12965 two_source_ops = 0;
12968 FETCH_DATA (info, codep + 4);
12969 /* All bits in the REX prefix are ignored. */
12971 /* The first byte after 0x62. */
12972 rex = ~(*codep >> 5) & 0x7;
12973 vex.r = *codep & 0x10;
12974 switch ((*codep & 0xf))
12977 return &bad_opcode;
12979 vex_table_index = EVEX_0F;
12982 vex_table_index = EVEX_0F38;
12985 vex_table_index = EVEX_0F3A;
12989 /* The second byte after 0x62. */
12991 vex.w = *codep & 0x80;
12992 if (vex.w && address_mode == mode_64bit)
12995 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12996 if (address_mode != mode_64bit)
12998 /* In 16/32-bit mode silently ignore following bits. */
13002 vex.register_specifier &= 0x7;
13006 if (!(*codep & 0x4))
13007 return &bad_opcode;
13009 switch ((*codep & 0x3))
13015 vex.prefix = DATA_PREFIX_OPCODE;
13018 vex.prefix = REPE_PREFIX_OPCODE;
13021 vex.prefix = REPNE_PREFIX_OPCODE;
13025 /* The third byte after 0x62. */
13028 /* Remember the static rounding bits. */
13029 vex.ll = (*codep >> 5) & 3;
13030 vex.b = (*codep & 0x10) != 0;
13032 vex.v = *codep & 0x8;
13033 vex.mask_register_specifier = *codep & 0x7;
13034 vex.zeroing = *codep & 0x80;
13040 dp = &evex_table[vex_table_index][vindex];
13042 FETCH_DATA (info, codep + 1);
13043 modrm.mod = (*codep >> 6) & 3;
13044 modrm.reg = (*codep >> 3) & 7;
13045 modrm.rm = *codep & 7;
13047 /* Set vector length. */
13048 if (modrm.mod == 3 && vex.b)
13064 return &bad_opcode;
13077 if (dp->name != NULL)
13080 return get_valid_dis386 (dp, info);
13084 get_sib (disassemble_info *info, int sizeflag)
13086 /* If modrm.mod == 3, operand must be register. */
13088 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13092 FETCH_DATA (info, codep + 2);
13093 sib.index = (codep [1] >> 3) & 7;
13094 sib.scale = (codep [1] >> 6) & 3;
13095 sib.base = codep [1] & 7;
13100 print_insn (bfd_vma pc, disassemble_info *info)
13102 const struct dis386 *dp;
13104 char *op_txt[MAX_OPERANDS];
13106 int sizeflag, orig_sizeflag;
13108 struct dis_private priv;
13111 priv.orig_sizeflag = AFLAG | DFLAG;
13112 if ((info->mach & bfd_mach_i386_i386) != 0)
13113 address_mode = mode_32bit;
13114 else if (info->mach == bfd_mach_i386_i8086)
13116 address_mode = mode_16bit;
13117 priv.orig_sizeflag = 0;
13120 address_mode = mode_64bit;
13122 if (intel_syntax == (char) -1)
13123 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13125 for (p = info->disassembler_options; p != NULL; )
13127 if (CONST_STRNEQ (p, "amd64"))
13129 else if (CONST_STRNEQ (p, "intel64"))
13131 else if (CONST_STRNEQ (p, "x86-64"))
13133 address_mode = mode_64bit;
13134 priv.orig_sizeflag = AFLAG | DFLAG;
13136 else if (CONST_STRNEQ (p, "i386"))
13138 address_mode = mode_32bit;
13139 priv.orig_sizeflag = AFLAG | DFLAG;
13141 else if (CONST_STRNEQ (p, "i8086"))
13143 address_mode = mode_16bit;
13144 priv.orig_sizeflag = 0;
13146 else if (CONST_STRNEQ (p, "intel"))
13149 if (CONST_STRNEQ (p + 5, "-mnemonic"))
13150 intel_mnemonic = 1;
13152 else if (CONST_STRNEQ (p, "att"))
13155 if (CONST_STRNEQ (p + 3, "-mnemonic"))
13156 intel_mnemonic = 0;
13158 else if (CONST_STRNEQ (p, "addr"))
13160 if (address_mode == mode_64bit)
13162 if (p[4] == '3' && p[5] == '2')
13163 priv.orig_sizeflag &= ~AFLAG;
13164 else if (p[4] == '6' && p[5] == '4')
13165 priv.orig_sizeflag |= AFLAG;
13169 if (p[4] == '1' && p[5] == '6')
13170 priv.orig_sizeflag &= ~AFLAG;
13171 else if (p[4] == '3' && p[5] == '2')
13172 priv.orig_sizeflag |= AFLAG;
13175 else if (CONST_STRNEQ (p, "data"))
13177 if (p[4] == '1' && p[5] == '6')
13178 priv.orig_sizeflag &= ~DFLAG;
13179 else if (p[4] == '3' && p[5] == '2')
13180 priv.orig_sizeflag |= DFLAG;
13182 else if (CONST_STRNEQ (p, "suffix"))
13183 priv.orig_sizeflag |= SUFFIX_ALWAYS;
13185 p = strchr (p, ',');
13190 if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13192 (*info->fprintf_func) (info->stream,
13193 _("64-bit address is disabled"));
13199 names64 = intel_names64;
13200 names32 = intel_names32;
13201 names16 = intel_names16;
13202 names8 = intel_names8;
13203 names8rex = intel_names8rex;
13204 names_seg = intel_names_seg;
13205 names_mm = intel_names_mm;
13206 names_bnd = intel_names_bnd;
13207 names_xmm = intel_names_xmm;
13208 names_ymm = intel_names_ymm;
13209 names_zmm = intel_names_zmm;
13210 index64 = intel_index64;
13211 index32 = intel_index32;
13212 names_mask = intel_names_mask;
13213 index16 = intel_index16;
13216 separator_char = '+';
13221 names64 = att_names64;
13222 names32 = att_names32;
13223 names16 = att_names16;
13224 names8 = att_names8;
13225 names8rex = att_names8rex;
13226 names_seg = att_names_seg;
13227 names_mm = att_names_mm;
13228 names_bnd = att_names_bnd;
13229 names_xmm = att_names_xmm;
13230 names_ymm = att_names_ymm;
13231 names_zmm = att_names_zmm;
13232 index64 = att_index64;
13233 index32 = att_index32;
13234 names_mask = att_names_mask;
13235 index16 = att_index16;
13238 separator_char = ',';
13242 /* The output looks better if we put 7 bytes on a line, since that
13243 puts most long word instructions on a single line. Use 8 bytes
13245 if ((info->mach & bfd_mach_l1om) != 0)
13246 info->bytes_per_line = 8;
13248 info->bytes_per_line = 7;
13250 info->private_data = &priv;
13251 priv.max_fetched = priv.the_buffer;
13252 priv.insn_start = pc;
13255 for (i = 0; i < MAX_OPERANDS; ++i)
13263 start_codep = priv.the_buffer;
13264 codep = priv.the_buffer;
13266 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13270 /* Getting here means we tried for data but didn't get it. That
13271 means we have an incomplete instruction of some sort. Just
13272 print the first byte as a prefix or a .byte pseudo-op. */
13273 if (codep > priv.the_buffer)
13275 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13277 (*info->fprintf_func) (info->stream, "%s", name);
13280 /* Just print the first byte as a .byte instruction. */
13281 (*info->fprintf_func) (info->stream, ".byte 0x%x",
13282 (unsigned int) priv.the_buffer[0]);
13292 sizeflag = priv.orig_sizeflag;
13294 if (!ckprefix () || rex_used)
13296 /* Too many prefixes or unused REX prefixes. */
13298 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13300 (*info->fprintf_func) (info->stream, "%s%s",
13302 prefix_name (all_prefixes[i], sizeflag));
13306 insn_codep = codep;
13308 FETCH_DATA (info, codep + 1);
13309 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13311 if (((prefixes & PREFIX_FWAIT)
13312 && ((*codep < 0xd8) || (*codep > 0xdf))))
13314 /* Handle prefixes before fwait. */
13315 for (i = 0; i < fwait_prefix && all_prefixes[i];
13317 (*info->fprintf_func) (info->stream, "%s ",
13318 prefix_name (all_prefixes[i], sizeflag));
13319 (*info->fprintf_func) (info->stream, "fwait");
13323 if (*codep == 0x0f)
13325 unsigned char threebyte;
13328 FETCH_DATA (info, codep + 1);
13329 threebyte = *codep;
13330 dp = &dis386_twobyte[threebyte];
13331 need_modrm = twobyte_has_modrm[*codep];
13336 dp = &dis386[*codep];
13337 need_modrm = onebyte_has_modrm[*codep];
13341 /* Save sizeflag for printing the extra prefixes later before updating
13342 it for mnemonic and operand processing. The prefix names depend
13343 only on the address mode. */
13344 orig_sizeflag = sizeflag;
13345 if (prefixes & PREFIX_ADDR)
13347 if ((prefixes & PREFIX_DATA))
13353 FETCH_DATA (info, codep + 1);
13354 modrm.mod = (*codep >> 6) & 3;
13355 modrm.reg = (*codep >> 3) & 7;
13356 modrm.rm = *codep & 7;
13364 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13366 get_sib (info, sizeflag);
13367 dofloat (sizeflag);
13371 dp = get_valid_dis386 (dp, info);
13372 if (dp != NULL && putop (dp->name, sizeflag) == 0)
13374 get_sib (info, sizeflag);
13375 for (i = 0; i < MAX_OPERANDS; ++i)
13378 op_ad = MAX_OPERANDS - 1 - i;
13380 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13381 /* For EVEX instruction after the last operand masking
13382 should be printed. */
13383 if (i == 0 && vex.evex)
13385 /* Don't print {%k0}. */
13386 if (vex.mask_register_specifier)
13389 oappend (names_mask[vex.mask_register_specifier]);
13399 /* Check if the REX prefix is used. */
13400 if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13401 all_prefixes[last_rex_prefix] = 0;
13403 /* Check if the SEG prefix is used. */
13404 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13405 | PREFIX_FS | PREFIX_GS)) != 0
13406 && (used_prefixes & active_seg_prefix) != 0)
13407 all_prefixes[last_seg_prefix] = 0;
13409 /* Check if the ADDR prefix is used. */
13410 if ((prefixes & PREFIX_ADDR) != 0
13411 && (used_prefixes & PREFIX_ADDR) != 0)
13412 all_prefixes[last_addr_prefix] = 0;
13414 /* Check if the DATA prefix is used. */
13415 if ((prefixes & PREFIX_DATA) != 0
13416 && (used_prefixes & PREFIX_DATA) != 0)
13417 all_prefixes[last_data_prefix] = 0;
13419 /* Print the extra prefixes. */
13421 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13422 if (all_prefixes[i])
13425 name = prefix_name (all_prefixes[i], orig_sizeflag);
13428 prefix_length += strlen (name) + 1;
13429 (*info->fprintf_func) (info->stream, "%s ", name);
13432 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13433 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13434 used by putop and MMX/SSE operand and may be overriden by the
13435 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13437 if (dp->prefix_requirement == PREFIX_OPCODE
13438 && dp != &bad_opcode
13440 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13442 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13444 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13446 && (used_prefixes & PREFIX_DATA) == 0))))
13448 (*info->fprintf_func) (info->stream, "(bad)");
13449 return end_codep - priv.the_buffer;
13452 /* Check maximum code length. */
13453 if ((codep - start_codep) > MAX_CODE_LENGTH)
13455 (*info->fprintf_func) (info->stream, "(bad)");
13456 return MAX_CODE_LENGTH;
13459 obufp = mnemonicendp;
13460 for (i = strlen (obuf) + prefix_length; i < 6; i++)
13463 (*info->fprintf_func) (info->stream, "%s", obuf);
13465 /* The enter and bound instructions are printed with operands in the same
13466 order as the intel book; everything else is printed in reverse order. */
13467 if (intel_syntax || two_source_ops)
13471 for (i = 0; i < MAX_OPERANDS; ++i)
13472 op_txt[i] = op_out[i];
13474 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13475 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13477 op_txt[2] = op_out[3];
13478 op_txt[3] = op_out[2];
13481 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13483 op_ad = op_index[i];
13484 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13485 op_index[MAX_OPERANDS - 1 - i] = op_ad;
13486 riprel = op_riprel[i];
13487 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13488 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13493 for (i = 0; i < MAX_OPERANDS; ++i)
13494 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13498 for (i = 0; i < MAX_OPERANDS; ++i)
13502 (*info->fprintf_func) (info->stream, ",");
13503 if (op_index[i] != -1 && !op_riprel[i])
13504 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13506 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13510 for (i = 0; i < MAX_OPERANDS; i++)
13511 if (op_index[i] != -1 && op_riprel[i])
13513 (*info->fprintf_func) (info->stream, " # ");
13514 (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13515 + op_address[op_index[i]]), info);
13518 return codep - priv.the_buffer;
13521 static const char *float_mem[] = {
13596 static const unsigned char float_mem_mode[] = {
13671 #define ST { OP_ST, 0 }
13672 #define STi { OP_STi, 0 }
13674 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13675 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13676 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13677 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13678 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13679 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13680 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13681 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13682 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13684 static const struct dis386 float_reg[][8] = {
13687 { "fadd", { ST, STi }, 0 },
13688 { "fmul", { ST, STi }, 0 },
13689 { "fcom", { STi }, 0 },
13690 { "fcomp", { STi }, 0 },
13691 { "fsub", { ST, STi }, 0 },
13692 { "fsubr", { ST, STi }, 0 },
13693 { "fdiv", { ST, STi }, 0 },
13694 { "fdivr", { ST, STi }, 0 },
13698 { "fld", { STi }, 0 },
13699 { "fxch", { STi }, 0 },
13709 { "fcmovb", { ST, STi }, 0 },
13710 { "fcmove", { ST, STi }, 0 },
13711 { "fcmovbe",{ ST, STi }, 0 },
13712 { "fcmovu", { ST, STi }, 0 },
13720 { "fcmovnb",{ ST, STi }, 0 },
13721 { "fcmovne",{ ST, STi }, 0 },
13722 { "fcmovnbe",{ ST, STi }, 0 },
13723 { "fcmovnu",{ ST, STi }, 0 },
13725 { "fucomi", { ST, STi }, 0 },
13726 { "fcomi", { ST, STi }, 0 },
13731 { "fadd", { STi, ST }, 0 },
13732 { "fmul", { STi, ST }, 0 },
13735 { "fsub!M", { STi, ST }, 0 },
13736 { "fsubM", { STi, ST }, 0 },
13737 { "fdiv!M", { STi, ST }, 0 },
13738 { "fdivM", { STi, ST }, 0 },
13742 { "ffree", { STi }, 0 },
13744 { "fst", { STi }, 0 },
13745 { "fstp", { STi }, 0 },
13746 { "fucom", { STi }, 0 },
13747 { "fucomp", { STi }, 0 },
13753 { "faddp", { STi, ST }, 0 },
13754 { "fmulp", { STi, ST }, 0 },
13757 { "fsub!Mp", { STi, ST }, 0 },
13758 { "fsubMp", { STi, ST }, 0 },
13759 { "fdiv!Mp", { STi, ST }, 0 },
13760 { "fdivMp", { STi, ST }, 0 },
13764 { "ffreep", { STi }, 0 },
13769 { "fucomip", { ST, STi }, 0 },
13770 { "fcomip", { ST, STi }, 0 },
13775 static char *fgrps[][8] = {
13778 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13783 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13788 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13793 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13798 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13803 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13808 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13813 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13814 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13819 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13824 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13829 swap_operand (void)
13831 mnemonicendp[0] = '.';
13832 mnemonicendp[1] = 's';
13837 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13838 int sizeflag ATTRIBUTE_UNUSED)
13840 /* Skip mod/rm byte. */
13846 dofloat (int sizeflag)
13848 const struct dis386 *dp;
13849 unsigned char floatop;
13851 floatop = codep[-1];
13853 if (modrm.mod != 3)
13855 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13857 putop (float_mem[fp_indx], sizeflag);
13860 OP_E (float_mem_mode[fp_indx], sizeflag);
13863 /* Skip mod/rm byte. */
13867 dp = &float_reg[floatop - 0xd8][modrm.reg];
13868 if (dp->name == NULL)
13870 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13872 /* Instruction fnstsw is only one with strange arg. */
13873 if (floatop == 0xdf && codep[-1] == 0xe0)
13874 strcpy (op_out[0], names16[0]);
13878 putop (dp->name, sizeflag);
13883 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13888 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13892 /* Like oappend (below), but S is a string starting with '%'.
13893 In Intel syntax, the '%' is elided. */
13895 oappend_maybe_intel (const char *s)
13897 oappend (s + intel_syntax);
13901 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13903 oappend_maybe_intel ("%st");
13907 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13909 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13910 oappend_maybe_intel (scratchbuf);
13913 /* Capital letters in template are macros. */
13915 putop (const char *in_template, int sizeflag)
13920 unsigned int l = 0, len = 1;
13923 #define SAVE_LAST(c) \
13924 if (l < len && l < sizeof (last)) \
13929 for (p = in_template; *p; p++)
13945 while (*++p != '|')
13946 if (*p == '}' || *p == '\0')
13949 /* Fall through. */
13954 while (*++p != '}')
13965 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13969 if (l == 0 && len == 1)
13974 if (sizeflag & SUFFIX_ALWAYS)
13987 if (address_mode == mode_64bit
13988 && !(prefixes & PREFIX_ADDR))
13999 if (intel_syntax && !alt)
14001 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14003 if (sizeflag & DFLAG)
14004 *obufp++ = intel_syntax ? 'd' : 'l';
14006 *obufp++ = intel_syntax ? 'w' : 's';
14007 used_prefixes |= (prefixes & PREFIX_DATA);
14011 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14014 if (modrm.mod == 3)
14020 if (sizeflag & DFLAG)
14021 *obufp++ = intel_syntax ? 'd' : 'l';
14024 used_prefixes |= (prefixes & PREFIX_DATA);
14030 case 'E': /* For jcxz/jecxz */
14031 if (address_mode == mode_64bit)
14033 if (sizeflag & AFLAG)
14039 if (sizeflag & AFLAG)
14041 used_prefixes |= (prefixes & PREFIX_ADDR);
14046 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14048 if (sizeflag & AFLAG)
14049 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14051 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14052 used_prefixes |= (prefixes & PREFIX_ADDR);
14056 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14058 if ((rex & REX_W) || (sizeflag & DFLAG))
14062 if (!(rex & REX_W))
14063 used_prefixes |= (prefixes & PREFIX_DATA);
14068 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14069 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14071 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14074 if (prefixes & PREFIX_DS)
14093 if (l != 0 || len != 1)
14095 if (l != 1 || len != 2 || last[0] != 'X')
14100 if (!need_vex || !vex.evex)
14103 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14105 switch (vex.length)
14123 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14128 /* Fall through. */
14131 if (l != 0 || len != 1)
14139 if (sizeflag & SUFFIX_ALWAYS)
14143 if (intel_mnemonic != cond)
14147 if ((prefixes & PREFIX_FWAIT) == 0)
14150 used_prefixes |= PREFIX_FWAIT;
14156 else if (intel_syntax && (sizeflag & DFLAG))
14160 if (!(rex & REX_W))
14161 used_prefixes |= (prefixes & PREFIX_DATA);
14165 && address_mode == mode_64bit
14166 && isa64 == intel64)
14171 /* Fall through. */
14174 && address_mode == mode_64bit
14175 && ((sizeflag & DFLAG) || (rex & REX_W)))
14180 /* Fall through. */
14183 if (l == 0 && len == 1)
14188 if ((rex & REX_W) == 0
14189 && (prefixes & PREFIX_DATA))
14191 if ((sizeflag & DFLAG) == 0)
14193 used_prefixes |= (prefixes & PREFIX_DATA);
14197 if ((prefixes & PREFIX_DATA)
14199 || (sizeflag & SUFFIX_ALWAYS))
14206 if (sizeflag & DFLAG)
14210 used_prefixes |= (prefixes & PREFIX_DATA);
14216 if (l != 1 || len != 2 || last[0] != 'L')
14222 if ((prefixes & PREFIX_DATA)
14224 || (sizeflag & SUFFIX_ALWAYS))
14231 if (sizeflag & DFLAG)
14232 *obufp++ = intel_syntax ? 'd' : 'l';
14235 used_prefixes |= (prefixes & PREFIX_DATA);
14243 if (address_mode == mode_64bit
14244 && ((sizeflag & DFLAG) || (rex & REX_W)))
14246 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14250 /* Fall through. */
14253 if (l == 0 && len == 1)
14256 if (intel_syntax && !alt)
14259 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14265 if (sizeflag & DFLAG)
14266 *obufp++ = intel_syntax ? 'd' : 'l';
14269 used_prefixes |= (prefixes & PREFIX_DATA);
14275 if (l != 1 || len != 2 || last[0] != 'L')
14281 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14296 else if (sizeflag & DFLAG)
14305 if (intel_syntax && !p[1]
14306 && ((rex & REX_W) || (sizeflag & DFLAG)))
14308 if (!(rex & REX_W))
14309 used_prefixes |= (prefixes & PREFIX_DATA);
14312 if (l == 0 && len == 1)
14316 if (address_mode == mode_64bit
14317 && ((sizeflag & DFLAG) || (rex & REX_W)))
14319 if (sizeflag & SUFFIX_ALWAYS)
14341 /* Fall through. */
14344 if (l == 0 && len == 1)
14349 if (sizeflag & SUFFIX_ALWAYS)
14355 if (sizeflag & DFLAG)
14359 used_prefixes |= (prefixes & PREFIX_DATA);
14373 if (address_mode == mode_64bit
14374 && !(prefixes & PREFIX_ADDR))
14385 if (l != 0 || len != 1)
14390 if (need_vex && vex.prefix)
14392 if (vex.prefix == DATA_PREFIX_OPCODE)
14399 if (prefixes & PREFIX_DATA)
14403 used_prefixes |= (prefixes & PREFIX_DATA);
14407 if (l == 0 && len == 1)
14409 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14420 if (l != 1 || len != 2 || last[0] != 'X')
14428 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14430 switch (vex.length)
14446 if (l == 0 && len == 1)
14448 /* operand size flag for cwtl, cbtw */
14457 else if (sizeflag & DFLAG)
14461 if (!(rex & REX_W))
14462 used_prefixes |= (prefixes & PREFIX_DATA);
14469 && last[0] != 'L'))
14476 if (last[0] == 'X')
14477 *obufp++ = vex.w ? 'd': 's';
14479 *obufp++ = vex.w ? 'q': 'd';
14485 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14487 if (sizeflag & DFLAG)
14491 used_prefixes |= (prefixes & PREFIX_DATA);
14497 if (address_mode == mode_64bit
14498 && (isa64 == intel64
14499 || ((sizeflag & DFLAG) || (rex & REX_W))))
14501 else if ((prefixes & PREFIX_DATA))
14503 if (!(sizeflag & DFLAG))
14505 used_prefixes |= (prefixes & PREFIX_DATA);
14512 mnemonicendp = obufp;
14517 oappend (const char *s)
14519 obufp = stpcpy (obufp, s);
14525 /* Only print the active segment register. */
14526 if (!active_seg_prefix)
14529 used_prefixes |= active_seg_prefix;
14530 switch (active_seg_prefix)
14533 oappend_maybe_intel ("%cs:");
14536 oappend_maybe_intel ("%ds:");
14539 oappend_maybe_intel ("%ss:");
14542 oappend_maybe_intel ("%es:");
14545 oappend_maybe_intel ("%fs:");
14548 oappend_maybe_intel ("%gs:");
14556 OP_indirE (int bytemode, int sizeflag)
14560 OP_E (bytemode, sizeflag);
14564 print_operand_value (char *buf, int hex, bfd_vma disp)
14566 if (address_mode == mode_64bit)
14574 sprintf_vma (tmp, disp);
14575 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14576 strcpy (buf + 2, tmp + i);
14580 bfd_signed_vma v = disp;
14587 /* Check for possible overflow on 0x8000000000000000. */
14590 strcpy (buf, "9223372036854775808");
14604 tmp[28 - i] = (v % 10) + '0';
14608 strcpy (buf, tmp + 29 - i);
14614 sprintf (buf, "0x%x", (unsigned int) disp);
14616 sprintf (buf, "%d", (int) disp);
14620 /* Put DISP in BUF as signed hex number. */
14623 print_displacement (char *buf, bfd_vma disp)
14625 bfd_signed_vma val = disp;
14634 /* Check for possible overflow. */
14637 switch (address_mode)
14640 strcpy (buf + j, "0x8000000000000000");
14643 strcpy (buf + j, "0x80000000");
14646 strcpy (buf + j, "0x8000");
14656 sprintf_vma (tmp, (bfd_vma) val);
14657 for (i = 0; tmp[i] == '0'; i++)
14659 if (tmp[i] == '\0')
14661 strcpy (buf + j, tmp + i);
14665 intel_operand_size (int bytemode, int sizeflag)
14669 && (bytemode == x_mode
14670 || bytemode == evex_half_bcst_xmmq_mode))
14673 oappend ("QWORD PTR ");
14675 oappend ("DWORD PTR ");
14684 oappend ("BYTE PTR ");
14689 oappend ("WORD PTR ");
14692 if (address_mode == mode_64bit && isa64 == intel64)
14694 oappend ("QWORD PTR ");
14697 /* Fall through. */
14699 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14701 oappend ("QWORD PTR ");
14704 /* Fall through. */
14710 oappend ("QWORD PTR ");
14713 if ((sizeflag & DFLAG) || bytemode == dq_mode)
14714 oappend ("DWORD PTR ");
14716 oappend ("WORD PTR ");
14717 used_prefixes |= (prefixes & PREFIX_DATA);
14721 if ((rex & REX_W) || (sizeflag & DFLAG))
14723 oappend ("WORD PTR ");
14724 if (!(rex & REX_W))
14725 used_prefixes |= (prefixes & PREFIX_DATA);
14728 if (sizeflag & DFLAG)
14729 oappend ("QWORD PTR ");
14731 oappend ("DWORD PTR ");
14732 used_prefixes |= (prefixes & PREFIX_DATA);
14735 case d_scalar_mode:
14736 case d_scalar_swap_mode:
14739 oappend ("DWORD PTR ");
14742 case q_scalar_mode:
14743 case q_scalar_swap_mode:
14745 oappend ("QWORD PTR ");
14748 if (address_mode == mode_64bit)
14749 oappend ("QWORD PTR ");
14751 oappend ("DWORD PTR ");
14754 if (sizeflag & DFLAG)
14755 oappend ("FWORD PTR ");
14757 oappend ("DWORD PTR ");
14758 used_prefixes |= (prefixes & PREFIX_DATA);
14761 oappend ("TBYTE PTR ");
14765 case evex_x_gscat_mode:
14766 case evex_x_nobcst_mode:
14767 case b_scalar_mode:
14768 case w_scalar_mode:
14771 switch (vex.length)
14774 oappend ("XMMWORD PTR ");
14777 oappend ("YMMWORD PTR ");
14780 oappend ("ZMMWORD PTR ");
14787 oappend ("XMMWORD PTR ");
14790 oappend ("XMMWORD PTR ");
14793 oappend ("YMMWORD PTR ");
14796 case evex_half_bcst_xmmq_mode:
14800 switch (vex.length)
14803 oappend ("QWORD PTR ");
14806 oappend ("XMMWORD PTR ");
14809 oappend ("YMMWORD PTR ");
14819 switch (vex.length)
14824 oappend ("BYTE PTR ");
14834 switch (vex.length)
14839 oappend ("WORD PTR ");
14849 switch (vex.length)
14854 oappend ("DWORD PTR ");
14864 switch (vex.length)
14869 oappend ("QWORD PTR ");
14879 switch (vex.length)
14882 oappend ("WORD PTR ");
14885 oappend ("DWORD PTR ");
14888 oappend ("QWORD PTR ");
14898 switch (vex.length)
14901 oappend ("DWORD PTR ");
14904 oappend ("QWORD PTR ");
14907 oappend ("XMMWORD PTR ");
14917 switch (vex.length)
14920 oappend ("QWORD PTR ");
14923 oappend ("YMMWORD PTR ");
14926 oappend ("ZMMWORD PTR ");
14936 switch (vex.length)
14940 oappend ("XMMWORD PTR ");
14947 oappend ("OWORD PTR ");
14950 case vex_w_dq_mode:
14951 case vex_scalar_w_dq_mode:
14956 oappend ("QWORD PTR ");
14958 oappend ("DWORD PTR ");
14960 case vex_vsib_d_w_dq_mode:
14961 case vex_vsib_q_w_dq_mode:
14968 oappend ("QWORD PTR ");
14970 oappend ("DWORD PTR ");
14974 switch (vex.length)
14977 oappend ("XMMWORD PTR ");
14980 oappend ("YMMWORD PTR ");
14983 oappend ("ZMMWORD PTR ");
14990 case vex_vsib_q_w_d_mode:
14991 case vex_vsib_d_w_d_mode:
14992 if (!need_vex || !vex.evex)
14995 switch (vex.length)
14998 oappend ("QWORD PTR ");
15001 oappend ("XMMWORD PTR ");
15004 oappend ("YMMWORD PTR ");
15012 if (!need_vex || vex.length != 128)
15015 oappend ("DWORD PTR ");
15017 oappend ("BYTE PTR ");
15023 oappend ("QWORD PTR ");
15025 oappend ("WORD PTR ");
15034 OP_E_register (int bytemode, int sizeflag)
15036 int reg = modrm.rm;
15037 const char **names;
15043 if ((sizeflag & SUFFIX_ALWAYS)
15044 && (bytemode == b_swap_mode
15045 || bytemode == v_swap_mode))
15071 names = address_mode == mode_64bit ? names64 : names32;
15082 if (address_mode == mode_64bit && isa64 == intel64)
15087 /* Fall through. */
15089 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15095 /* Fall through. */
15107 if ((sizeflag & DFLAG)
15108 || (bytemode != v_mode
15109 && bytemode != v_swap_mode))
15113 used_prefixes |= (prefixes & PREFIX_DATA);
15123 names = names_mask;
15128 oappend (INTERNAL_DISASSEMBLER_ERROR);
15131 oappend (names[reg]);
15135 OP_E_memory (int bytemode, int sizeflag)
15138 int add = (rex & REX_B) ? 8 : 0;
15144 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
15146 && bytemode != x_mode
15147 && bytemode != xmmq_mode
15148 && bytemode != evex_half_bcst_xmmq_mode)
15163 case vex_vsib_d_w_dq_mode:
15164 case vex_vsib_d_w_d_mode:
15165 case vex_vsib_q_w_dq_mode:
15166 case vex_vsib_q_w_d_mode:
15167 case evex_x_gscat_mode:
15169 shift = vex.w ? 3 : 2;
15172 case evex_half_bcst_xmmq_mode:
15176 shift = vex.w ? 3 : 2;
15179 /* Fall through. */
15183 case evex_x_nobcst_mode:
15185 switch (vex.length)
15208 case q_scalar_mode:
15210 case q_scalar_swap_mode:
15216 case d_scalar_mode:
15218 case d_scalar_swap_mode:
15221 case w_scalar_mode:
15225 case b_scalar_mode:
15232 /* Make necessary corrections to shift for modes that need it.
15233 For these modes we currently have shift 4, 5 or 6 depending on
15234 vex.length (it corresponds to xmmword, ymmword or zmmword
15235 operand). We might want to make it 3, 4 or 5 (e.g. for
15236 xmmq_mode). In case of broadcast enabled the corrections
15237 aren't needed, as element size is always 32 or 64 bits. */
15239 && (bytemode == xmmq_mode
15240 || bytemode == evex_half_bcst_xmmq_mode))
15242 else if (bytemode == xmmqd_mode)
15244 else if (bytemode == xmmdw_mode)
15246 else if (bytemode == ymmq_mode && vex.length == 128)
15254 intel_operand_size (bytemode, sizeflag);
15257 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15259 /* 32/64 bit address mode */
15268 int addr32flag = !((sizeflag & AFLAG)
15269 || bytemode == v_bnd_mode
15270 || bytemode == bnd_mode);
15271 const char **indexes64 = names64;
15272 const char **indexes32 = names32;
15282 vindex = sib.index;
15288 case vex_vsib_d_w_dq_mode:
15289 case vex_vsib_d_w_d_mode:
15290 case vex_vsib_q_w_dq_mode:
15291 case vex_vsib_q_w_d_mode:
15301 switch (vex.length)
15304 indexes64 = indexes32 = names_xmm;
15308 || bytemode == vex_vsib_q_w_dq_mode
15309 || bytemode == vex_vsib_q_w_d_mode)
15310 indexes64 = indexes32 = names_ymm;
15312 indexes64 = indexes32 = names_xmm;
15316 || bytemode == vex_vsib_q_w_dq_mode
15317 || bytemode == vex_vsib_q_w_d_mode)
15318 indexes64 = indexes32 = names_zmm;
15320 indexes64 = indexes32 = names_ymm;
15327 haveindex = vindex != 4;
15334 rbase = base + add;
15342 if (address_mode == mode_64bit && !havesib)
15348 FETCH_DATA (the_info, codep + 1);
15350 if ((disp & 0x80) != 0)
15352 if (vex.evex && shift > 0)
15360 /* In 32bit mode, we need index register to tell [offset] from
15361 [eiz*1 + offset]. */
15362 needindex = (havesib
15365 && address_mode == mode_32bit);
15366 havedisp = (havebase
15368 || (havesib && (haveindex || scale != 0)));
15371 if (modrm.mod != 0 || base == 5)
15373 if (havedisp || riprel)
15374 print_displacement (scratchbuf, disp);
15376 print_operand_value (scratchbuf, 1, disp);
15377 oappend (scratchbuf);
15381 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15385 if ((havebase || haveindex || riprel)
15386 && (bytemode != v_bnd_mode)
15387 && (bytemode != bnd_mode))
15388 used_prefixes |= PREFIX_ADDR;
15390 if (havedisp || (intel_syntax && riprel))
15392 *obufp++ = open_char;
15393 if (intel_syntax && riprel)
15396 oappend (!addr32flag ? "rip" : "eip");
15400 oappend (address_mode == mode_64bit && !addr32flag
15401 ? names64[rbase] : names32[rbase]);
15404 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15405 print index to tell base + index from base. */
15409 || (havebase && base != ESP_REG_NUM))
15411 if (!intel_syntax || havebase)
15413 *obufp++ = separator_char;
15417 oappend (address_mode == mode_64bit && !addr32flag
15418 ? indexes64[vindex] : indexes32[vindex]);
15420 oappend (address_mode == mode_64bit && !addr32flag
15421 ? index64 : index32);
15423 *obufp++ = scale_char;
15425 sprintf (scratchbuf, "%d", 1 << scale);
15426 oappend (scratchbuf);
15430 && (disp || modrm.mod != 0 || base == 5))
15432 if (!havedisp || (bfd_signed_vma) disp >= 0)
15437 else if (modrm.mod != 1 && disp != -disp)
15441 disp = - (bfd_signed_vma) disp;
15445 print_displacement (scratchbuf, disp);
15447 print_operand_value (scratchbuf, 1, disp);
15448 oappend (scratchbuf);
15451 *obufp++ = close_char;
15454 else if (intel_syntax)
15456 if (modrm.mod != 0 || base == 5)
15458 if (!active_seg_prefix)
15460 oappend (names_seg[ds_reg - es_reg]);
15463 print_operand_value (scratchbuf, 1, disp);
15464 oappend (scratchbuf);
15470 /* 16 bit address mode */
15471 used_prefixes |= prefixes & PREFIX_ADDR;
15478 if ((disp & 0x8000) != 0)
15483 FETCH_DATA (the_info, codep + 1);
15485 if ((disp & 0x80) != 0)
15490 if ((disp & 0x8000) != 0)
15496 if (modrm.mod != 0 || modrm.rm == 6)
15498 print_displacement (scratchbuf, disp);
15499 oappend (scratchbuf);
15502 if (modrm.mod != 0 || modrm.rm != 6)
15504 *obufp++ = open_char;
15506 oappend (index16[modrm.rm]);
15508 && (disp || modrm.mod != 0 || modrm.rm == 6))
15510 if ((bfd_signed_vma) disp >= 0)
15515 else if (modrm.mod != 1)
15519 disp = - (bfd_signed_vma) disp;
15522 print_displacement (scratchbuf, disp);
15523 oappend (scratchbuf);
15526 *obufp++ = close_char;
15529 else if (intel_syntax)
15531 if (!active_seg_prefix)
15533 oappend (names_seg[ds_reg - es_reg]);
15536 print_operand_value (scratchbuf, 1, disp & 0xffff);
15537 oappend (scratchbuf);
15540 if (vex.evex && vex.b
15541 && (bytemode == x_mode
15542 || bytemode == xmmq_mode
15543 || bytemode == evex_half_bcst_xmmq_mode))
15546 || bytemode == xmmq_mode
15547 || bytemode == evex_half_bcst_xmmq_mode)
15549 switch (vex.length)
15552 oappend ("{1to2}");
15555 oappend ("{1to4}");
15558 oappend ("{1to8}");
15566 switch (vex.length)
15569 oappend ("{1to4}");
15572 oappend ("{1to8}");
15575 oappend ("{1to16}");
15585 OP_E (int bytemode, int sizeflag)
15587 /* Skip mod/rm byte. */
15591 if (modrm.mod == 3)
15592 OP_E_register (bytemode, sizeflag);
15594 OP_E_memory (bytemode, sizeflag);
15598 OP_G (int bytemode, int sizeflag)
15609 oappend (names8rex[modrm.reg + add]);
15611 oappend (names8[modrm.reg + add]);
15614 oappend (names16[modrm.reg + add]);
15619 oappend (names32[modrm.reg + add]);
15622 oappend (names64[modrm.reg + add]);
15625 if (modrm.reg > 0x3)
15630 oappend (names_bnd[modrm.reg]);
15639 oappend (names64[modrm.reg + add]);
15642 if ((sizeflag & DFLAG) || bytemode != v_mode)
15643 oappend (names32[modrm.reg + add]);
15645 oappend (names16[modrm.reg + add]);
15646 used_prefixes |= (prefixes & PREFIX_DATA);
15650 if (address_mode == mode_64bit)
15651 oappend (names64[modrm.reg + add]);
15653 oappend (names32[modrm.reg + add]);
15657 if ((modrm.reg + add) > 0x7)
15662 oappend (names_mask[modrm.reg + add]);
15665 oappend (INTERNAL_DISASSEMBLER_ERROR);
15678 FETCH_DATA (the_info, codep + 8);
15679 a = *codep++ & 0xff;
15680 a |= (*codep++ & 0xff) << 8;
15681 a |= (*codep++ & 0xff) << 16;
15682 a |= (*codep++ & 0xffu) << 24;
15683 b = *codep++ & 0xff;
15684 b |= (*codep++ & 0xff) << 8;
15685 b |= (*codep++ & 0xff) << 16;
15686 b |= (*codep++ & 0xffu) << 24;
15687 x = a + ((bfd_vma) b << 32);
15695 static bfd_signed_vma
15698 bfd_signed_vma x = 0;
15700 FETCH_DATA (the_info, codep + 4);
15701 x = *codep++ & (bfd_signed_vma) 0xff;
15702 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15703 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15704 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15708 static bfd_signed_vma
15711 bfd_signed_vma x = 0;
15713 FETCH_DATA (the_info, codep + 4);
15714 x = *codep++ & (bfd_signed_vma) 0xff;
15715 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15716 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15717 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15719 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15729 FETCH_DATA (the_info, codep + 2);
15730 x = *codep++ & 0xff;
15731 x |= (*codep++ & 0xff) << 8;
15736 set_op (bfd_vma op, int riprel)
15738 op_index[op_ad] = op_ad;
15739 if (address_mode == mode_64bit)
15741 op_address[op_ad] = op;
15742 op_riprel[op_ad] = riprel;
15746 /* Mask to get a 32-bit address. */
15747 op_address[op_ad] = op & 0xffffffff;
15748 op_riprel[op_ad] = riprel & 0xffffffff;
15753 OP_REG (int code, int sizeflag)
15760 case es_reg: case ss_reg: case cs_reg:
15761 case ds_reg: case fs_reg: case gs_reg:
15762 oappend (names_seg[code - es_reg]);
15774 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15775 case sp_reg: case bp_reg: case si_reg: case di_reg:
15776 s = names16[code - ax_reg + add];
15778 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15779 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15782 s = names8rex[code - al_reg + add];
15784 s = names8[code - al_reg];
15786 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15787 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15788 if (address_mode == mode_64bit
15789 && ((sizeflag & DFLAG) || (rex & REX_W)))
15791 s = names64[code - rAX_reg + add];
15794 code += eAX_reg - rAX_reg;
15795 /* Fall through. */
15796 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15797 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15800 s = names64[code - eAX_reg + add];
15803 if (sizeflag & DFLAG)
15804 s = names32[code - eAX_reg + add];
15806 s = names16[code - eAX_reg + add];
15807 used_prefixes |= (prefixes & PREFIX_DATA);
15811 s = INTERNAL_DISASSEMBLER_ERROR;
15818 OP_IMREG (int code, int sizeflag)
15830 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15831 case sp_reg: case bp_reg: case si_reg: case di_reg:
15832 s = names16[code - ax_reg];
15834 case es_reg: case ss_reg: case cs_reg:
15835 case ds_reg: case fs_reg: case gs_reg:
15836 s = names_seg[code - es_reg];
15838 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15839 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15842 s = names8rex[code - al_reg];
15844 s = names8[code - al_reg];
15846 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15847 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15850 s = names64[code - eAX_reg];
15853 if (sizeflag & DFLAG)
15854 s = names32[code - eAX_reg];
15856 s = names16[code - eAX_reg];
15857 used_prefixes |= (prefixes & PREFIX_DATA);
15860 case z_mode_ax_reg:
15861 if ((rex & REX_W) || (sizeflag & DFLAG))
15865 if (!(rex & REX_W))
15866 used_prefixes |= (prefixes & PREFIX_DATA);
15869 s = INTERNAL_DISASSEMBLER_ERROR;
15876 OP_I (int bytemode, int sizeflag)
15879 bfd_signed_vma mask = -1;
15884 FETCH_DATA (the_info, codep + 1);
15889 if (address_mode == mode_64bit)
15894 /* Fall through. */
15901 if (sizeflag & DFLAG)
15911 used_prefixes |= (prefixes & PREFIX_DATA);
15923 oappend (INTERNAL_DISASSEMBLER_ERROR);
15928 scratchbuf[0] = '$';
15929 print_operand_value (scratchbuf + 1, 1, op);
15930 oappend_maybe_intel (scratchbuf);
15931 scratchbuf[0] = '\0';
15935 OP_I64 (int bytemode, int sizeflag)
15938 bfd_signed_vma mask = -1;
15940 if (address_mode != mode_64bit)
15942 OP_I (bytemode, sizeflag);
15949 FETCH_DATA (the_info, codep + 1);
15959 if (sizeflag & DFLAG)
15969 used_prefixes |= (prefixes & PREFIX_DATA);
15977 oappend (INTERNAL_DISASSEMBLER_ERROR);
15982 scratchbuf[0] = '$';
15983 print_operand_value (scratchbuf + 1, 1, op);
15984 oappend_maybe_intel (scratchbuf);
15985 scratchbuf[0] = '\0';
15989 OP_sI (int bytemode, int sizeflag)
15997 FETCH_DATA (the_info, codep + 1);
15999 if ((op & 0x80) != 0)
16001 if (bytemode == b_T_mode)
16003 if (address_mode != mode_64bit
16004 || !((sizeflag & DFLAG) || (rex & REX_W)))
16006 /* The operand-size prefix is overridden by a REX prefix. */
16007 if ((sizeflag & DFLAG) || (rex & REX_W))
16015 if (!(rex & REX_W))
16017 if (sizeflag & DFLAG)
16025 /* The operand-size prefix is overridden by a REX prefix. */
16026 if ((sizeflag & DFLAG) || (rex & REX_W))
16032 oappend (INTERNAL_DISASSEMBLER_ERROR);
16036 scratchbuf[0] = '$';
16037 print_operand_value (scratchbuf + 1, 1, op);
16038 oappend_maybe_intel (scratchbuf);
16042 OP_J (int bytemode, int sizeflag)
16046 bfd_vma segment = 0;
16051 FETCH_DATA (the_info, codep + 1);
16053 if ((disp & 0x80) != 0)
16057 if (isa64 == amd64)
16059 if ((sizeflag & DFLAG)
16060 || (address_mode == mode_64bit
16061 && (isa64 != amd64 || (rex & REX_W))))
16066 if ((disp & 0x8000) != 0)
16068 /* In 16bit mode, address is wrapped around at 64k within
16069 the same segment. Otherwise, a data16 prefix on a jump
16070 instruction means that the pc is masked to 16 bits after
16071 the displacement is added! */
16073 if ((prefixes & PREFIX_DATA) == 0)
16074 segment = ((start_pc + (codep - start_codep))
16075 & ~((bfd_vma) 0xffff));
16077 if (address_mode != mode_64bit
16078 || (isa64 == amd64 && !(rex & REX_W)))
16079 used_prefixes |= (prefixes & PREFIX_DATA);
16082 oappend (INTERNAL_DISASSEMBLER_ERROR);
16085 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16087 print_operand_value (scratchbuf, 1, disp);
16088 oappend (scratchbuf);
16092 OP_SEG (int bytemode, int sizeflag)
16094 if (bytemode == w_mode)
16095 oappend (names_seg[modrm.reg]);
16097 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16101 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16105 if (sizeflag & DFLAG)
16115 used_prefixes |= (prefixes & PREFIX_DATA);
16117 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16119 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16120 oappend (scratchbuf);
16124 OP_OFF (int bytemode, int sizeflag)
16128 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16129 intel_operand_size (bytemode, sizeflag);
16132 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16139 if (!active_seg_prefix)
16141 oappend (names_seg[ds_reg - es_reg]);
16145 print_operand_value (scratchbuf, 1, off);
16146 oappend (scratchbuf);
16150 OP_OFF64 (int bytemode, int sizeflag)
16154 if (address_mode != mode_64bit
16155 || (prefixes & PREFIX_ADDR))
16157 OP_OFF (bytemode, sizeflag);
16161 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16162 intel_operand_size (bytemode, sizeflag);
16169 if (!active_seg_prefix)
16171 oappend (names_seg[ds_reg - es_reg]);
16175 print_operand_value (scratchbuf, 1, off);
16176 oappend (scratchbuf);
16180 ptr_reg (int code, int sizeflag)
16184 *obufp++ = open_char;
16185 used_prefixes |= (prefixes & PREFIX_ADDR);
16186 if (address_mode == mode_64bit)
16188 if (!(sizeflag & AFLAG))
16189 s = names32[code - eAX_reg];
16191 s = names64[code - eAX_reg];
16193 else if (sizeflag & AFLAG)
16194 s = names32[code - eAX_reg];
16196 s = names16[code - eAX_reg];
16198 *obufp++ = close_char;
16203 OP_ESreg (int code, int sizeflag)
16209 case 0x6d: /* insw/insl */
16210 intel_operand_size (z_mode, sizeflag);
16212 case 0xa5: /* movsw/movsl/movsq */
16213 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16214 case 0xab: /* stosw/stosl */
16215 case 0xaf: /* scasw/scasl */
16216 intel_operand_size (v_mode, sizeflag);
16219 intel_operand_size (b_mode, sizeflag);
16222 oappend_maybe_intel ("%es:");
16223 ptr_reg (code, sizeflag);
16227 OP_DSreg (int code, int sizeflag)
16233 case 0x6f: /* outsw/outsl */
16234 intel_operand_size (z_mode, sizeflag);
16236 case 0xa5: /* movsw/movsl/movsq */
16237 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16238 case 0xad: /* lodsw/lodsl/lodsq */
16239 intel_operand_size (v_mode, sizeflag);
16242 intel_operand_size (b_mode, sizeflag);
16245 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16246 default segment register DS is printed. */
16247 if (!active_seg_prefix)
16248 active_seg_prefix = PREFIX_DS;
16250 ptr_reg (code, sizeflag);
16254 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16262 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16264 all_prefixes[last_lock_prefix] = 0;
16265 used_prefixes |= PREFIX_LOCK;
16270 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16271 oappend_maybe_intel (scratchbuf);
16275 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16284 sprintf (scratchbuf, "db%d", modrm.reg + add);
16286 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16287 oappend (scratchbuf);
16291 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16293 sprintf (scratchbuf, "%%tr%d", modrm.reg);
16294 oappend_maybe_intel (scratchbuf);
16298 OP_R (int bytemode, int sizeflag)
16300 /* Skip mod/rm byte. */
16303 OP_E_register (bytemode, sizeflag);
16307 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16309 int reg = modrm.reg;
16310 const char **names;
16312 used_prefixes |= (prefixes & PREFIX_DATA);
16313 if (prefixes & PREFIX_DATA)
16322 oappend (names[reg]);
16326 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16328 int reg = modrm.reg;
16329 const char **names;
16341 && bytemode != xmm_mode
16342 && bytemode != xmmq_mode
16343 && bytemode != evex_half_bcst_xmmq_mode
16344 && bytemode != ymm_mode
16345 && bytemode != scalar_mode)
16347 switch (vex.length)
16354 || (bytemode != vex_vsib_q_w_dq_mode
16355 && bytemode != vex_vsib_q_w_d_mode))
16367 else if (bytemode == xmmq_mode
16368 || bytemode == evex_half_bcst_xmmq_mode)
16370 switch (vex.length)
16383 else if (bytemode == ymm_mode)
16387 oappend (names[reg]);
16391 OP_EM (int bytemode, int sizeflag)
16394 const char **names;
16396 if (modrm.mod != 3)
16399 && (bytemode == v_mode || bytemode == v_swap_mode))
16401 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16402 used_prefixes |= (prefixes & PREFIX_DATA);
16404 OP_E (bytemode, sizeflag);
16408 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16411 /* Skip mod/rm byte. */
16414 used_prefixes |= (prefixes & PREFIX_DATA);
16416 if (prefixes & PREFIX_DATA)
16425 oappend (names[reg]);
16428 /* cvt* are the only instructions in sse2 which have
16429 both SSE and MMX operands and also have 0x66 prefix
16430 in their opcode. 0x66 was originally used to differentiate
16431 between SSE and MMX instruction(operands). So we have to handle the
16432 cvt* separately using OP_EMC and OP_MXC */
16434 OP_EMC (int bytemode, int sizeflag)
16436 if (modrm.mod != 3)
16438 if (intel_syntax && bytemode == v_mode)
16440 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16441 used_prefixes |= (prefixes & PREFIX_DATA);
16443 OP_E (bytemode, sizeflag);
16447 /* Skip mod/rm byte. */
16450 used_prefixes |= (prefixes & PREFIX_DATA);
16451 oappend (names_mm[modrm.rm]);
16455 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16457 used_prefixes |= (prefixes & PREFIX_DATA);
16458 oappend (names_mm[modrm.reg]);
16462 OP_EX (int bytemode, int sizeflag)
16465 const char **names;
16467 /* Skip mod/rm byte. */
16471 if (modrm.mod != 3)
16473 OP_E_memory (bytemode, sizeflag);
16488 if ((sizeflag & SUFFIX_ALWAYS)
16489 && (bytemode == x_swap_mode
16490 || bytemode == d_swap_mode
16491 || bytemode == d_scalar_swap_mode
16492 || bytemode == q_swap_mode
16493 || bytemode == q_scalar_swap_mode))
16497 && bytemode != xmm_mode
16498 && bytemode != xmmdw_mode
16499 && bytemode != xmmqd_mode
16500 && bytemode != xmm_mb_mode
16501 && bytemode != xmm_mw_mode
16502 && bytemode != xmm_md_mode
16503 && bytemode != xmm_mq_mode
16504 && bytemode != xmm_mdq_mode
16505 && bytemode != xmmq_mode
16506 && bytemode != evex_half_bcst_xmmq_mode
16507 && bytemode != ymm_mode
16508 && bytemode != d_scalar_mode
16509 && bytemode != d_scalar_swap_mode
16510 && bytemode != q_scalar_mode
16511 && bytemode != q_scalar_swap_mode
16512 && bytemode != vex_scalar_w_dq_mode)
16514 switch (vex.length)
16529 else if (bytemode == xmmq_mode
16530 || bytemode == evex_half_bcst_xmmq_mode)
16532 switch (vex.length)
16545 else if (bytemode == ymm_mode)
16549 oappend (names[reg]);
16553 OP_MS (int bytemode, int sizeflag)
16555 if (modrm.mod == 3)
16556 OP_EM (bytemode, sizeflag);
16562 OP_XS (int bytemode, int sizeflag)
16564 if (modrm.mod == 3)
16565 OP_EX (bytemode, sizeflag);
16571 OP_M (int bytemode, int sizeflag)
16573 if (modrm.mod == 3)
16574 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16577 OP_E (bytemode, sizeflag);
16581 OP_0f07 (int bytemode, int sizeflag)
16583 if (modrm.mod != 3 || modrm.rm != 0)
16586 OP_E (bytemode, sizeflag);
16589 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16590 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16593 NOP_Fixup1 (int bytemode, int sizeflag)
16595 if ((prefixes & PREFIX_DATA) != 0
16598 && address_mode == mode_64bit))
16599 OP_REG (bytemode, sizeflag);
16601 strcpy (obuf, "nop");
16605 NOP_Fixup2 (int bytemode, int sizeflag)
16607 if ((prefixes & PREFIX_DATA) != 0
16610 && address_mode == mode_64bit))
16611 OP_IMREG (bytemode, sizeflag);
16614 static const char *const Suffix3DNow[] = {
16615 /* 00 */ NULL, NULL, NULL, NULL,
16616 /* 04 */ NULL, NULL, NULL, NULL,
16617 /* 08 */ NULL, NULL, NULL, NULL,
16618 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
16619 /* 10 */ NULL, NULL, NULL, NULL,
16620 /* 14 */ NULL, NULL, NULL, NULL,
16621 /* 18 */ NULL, NULL, NULL, NULL,
16622 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
16623 /* 20 */ NULL, NULL, NULL, NULL,
16624 /* 24 */ NULL, NULL, NULL, NULL,
16625 /* 28 */ NULL, NULL, NULL, NULL,
16626 /* 2C */ NULL, NULL, NULL, NULL,
16627 /* 30 */ NULL, NULL, NULL, NULL,
16628 /* 34 */ NULL, NULL, NULL, NULL,
16629 /* 38 */ NULL, NULL, NULL, NULL,
16630 /* 3C */ NULL, NULL, NULL, NULL,
16631 /* 40 */ NULL, NULL, NULL, NULL,
16632 /* 44 */ NULL, NULL, NULL, NULL,
16633 /* 48 */ NULL, NULL, NULL, NULL,
16634 /* 4C */ NULL, NULL, NULL, NULL,
16635 /* 50 */ NULL, NULL, NULL, NULL,
16636 /* 54 */ NULL, NULL, NULL, NULL,
16637 /* 58 */ NULL, NULL, NULL, NULL,
16638 /* 5C */ NULL, NULL, NULL, NULL,
16639 /* 60 */ NULL, NULL, NULL, NULL,
16640 /* 64 */ NULL, NULL, NULL, NULL,
16641 /* 68 */ NULL, NULL, NULL, NULL,
16642 /* 6C */ NULL, NULL, NULL, NULL,
16643 /* 70 */ NULL, NULL, NULL, NULL,
16644 /* 74 */ NULL, NULL, NULL, NULL,
16645 /* 78 */ NULL, NULL, NULL, NULL,
16646 /* 7C */ NULL, NULL, NULL, NULL,
16647 /* 80 */ NULL, NULL, NULL, NULL,
16648 /* 84 */ NULL, NULL, NULL, NULL,
16649 /* 88 */ NULL, NULL, "pfnacc", NULL,
16650 /* 8C */ NULL, NULL, "pfpnacc", NULL,
16651 /* 90 */ "pfcmpge", NULL, NULL, NULL,
16652 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
16653 /* 98 */ NULL, NULL, "pfsub", NULL,
16654 /* 9C */ NULL, NULL, "pfadd", NULL,
16655 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
16656 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
16657 /* A8 */ NULL, NULL, "pfsubr", NULL,
16658 /* AC */ NULL, NULL, "pfacc", NULL,
16659 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
16660 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
16661 /* B8 */ NULL, NULL, NULL, "pswapd",
16662 /* BC */ NULL, NULL, NULL, "pavgusb",
16663 /* C0 */ NULL, NULL, NULL, NULL,
16664 /* C4 */ NULL, NULL, NULL, NULL,
16665 /* C8 */ NULL, NULL, NULL, NULL,
16666 /* CC */ NULL, NULL, NULL, NULL,
16667 /* D0 */ NULL, NULL, NULL, NULL,
16668 /* D4 */ NULL, NULL, NULL, NULL,
16669 /* D8 */ NULL, NULL, NULL, NULL,
16670 /* DC */ NULL, NULL, NULL, NULL,
16671 /* E0 */ NULL, NULL, NULL, NULL,
16672 /* E4 */ NULL, NULL, NULL, NULL,
16673 /* E8 */ NULL, NULL, NULL, NULL,
16674 /* EC */ NULL, NULL, NULL, NULL,
16675 /* F0 */ NULL, NULL, NULL, NULL,
16676 /* F4 */ NULL, NULL, NULL, NULL,
16677 /* F8 */ NULL, NULL, NULL, NULL,
16678 /* FC */ NULL, NULL, NULL, NULL,
16682 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16684 const char *mnemonic;
16686 FETCH_DATA (the_info, codep + 1);
16687 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16688 place where an 8-bit immediate would normally go. ie. the last
16689 byte of the instruction. */
16690 obufp = mnemonicendp;
16691 mnemonic = Suffix3DNow[*codep++ & 0xff];
16693 oappend (mnemonic);
16696 /* Since a variable sized modrm/sib chunk is between the start
16697 of the opcode (0x0f0f) and the opcode suffix, we need to do
16698 all the modrm processing first, and don't know until now that
16699 we have a bad opcode. This necessitates some cleaning up. */
16700 op_out[0][0] = '\0';
16701 op_out[1][0] = '\0';
16704 mnemonicendp = obufp;
16707 static struct op simd_cmp_op[] =
16709 { STRING_COMMA_LEN ("eq") },
16710 { STRING_COMMA_LEN ("lt") },
16711 { STRING_COMMA_LEN ("le") },
16712 { STRING_COMMA_LEN ("unord") },
16713 { STRING_COMMA_LEN ("neq") },
16714 { STRING_COMMA_LEN ("nlt") },
16715 { STRING_COMMA_LEN ("nle") },
16716 { STRING_COMMA_LEN ("ord") }
16720 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16722 unsigned int cmp_type;
16724 FETCH_DATA (the_info, codep + 1);
16725 cmp_type = *codep++ & 0xff;
16726 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16729 char *p = mnemonicendp - 2;
16733 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16734 mnemonicendp += simd_cmp_op[cmp_type].len;
16738 /* We have a reserved extension byte. Output it directly. */
16739 scratchbuf[0] = '$';
16740 print_operand_value (scratchbuf + 1, 1, cmp_type);
16741 oappend_maybe_intel (scratchbuf);
16742 scratchbuf[0] = '\0';
16747 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16748 int sizeflag ATTRIBUTE_UNUSED)
16750 /* mwaitx %eax,%ecx,%ebx */
16753 const char **names = (address_mode == mode_64bit
16754 ? names64 : names32);
16755 strcpy (op_out[0], names[0]);
16756 strcpy (op_out[1], names[1]);
16757 strcpy (op_out[2], names[3]);
16758 two_source_ops = 1;
16760 /* Skip mod/rm byte. */
16766 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16767 int sizeflag ATTRIBUTE_UNUSED)
16769 /* mwait %eax,%ecx */
16772 const char **names = (address_mode == mode_64bit
16773 ? names64 : names32);
16774 strcpy (op_out[0], names[0]);
16775 strcpy (op_out[1], names[1]);
16776 two_source_ops = 1;
16778 /* Skip mod/rm byte. */
16784 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16785 int sizeflag ATTRIBUTE_UNUSED)
16787 /* monitor %eax,%ecx,%edx" */
16790 const char **op1_names;
16791 const char **names = (address_mode == mode_64bit
16792 ? names64 : names32);
16794 if (!(prefixes & PREFIX_ADDR))
16795 op1_names = (address_mode == mode_16bit
16796 ? names16 : names);
16799 /* Remove "addr16/addr32". */
16800 all_prefixes[last_addr_prefix] = 0;
16801 op1_names = (address_mode != mode_32bit
16802 ? names32 : names16);
16803 used_prefixes |= PREFIX_ADDR;
16805 strcpy (op_out[0], op1_names[0]);
16806 strcpy (op_out[1], names[1]);
16807 strcpy (op_out[2], names[2]);
16808 two_source_ops = 1;
16810 /* Skip mod/rm byte. */
16818 /* Throw away prefixes and 1st. opcode byte. */
16819 codep = insn_codep + 1;
16824 REP_Fixup (int bytemode, int sizeflag)
16826 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16828 if (prefixes & PREFIX_REPZ)
16829 all_prefixes[last_repz_prefix] = REP_PREFIX;
16836 OP_IMREG (bytemode, sizeflag);
16839 OP_ESreg (bytemode, sizeflag);
16842 OP_DSreg (bytemode, sizeflag);
16850 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16854 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16856 if (prefixes & PREFIX_REPNZ)
16857 all_prefixes[last_repnz_prefix] = BND_PREFIX;
16860 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16864 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16865 int sizeflag ATTRIBUTE_UNUSED)
16867 if (active_seg_prefix == PREFIX_DS
16868 && (address_mode != mode_64bit || last_data_prefix < 0))
16870 /* NOTRACK prefix is only valid on indirect branch instructions.
16871 NB: DATA prefix is unsupported for Intel64. */
16872 active_seg_prefix = 0;
16873 all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
16877 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16878 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16882 HLE_Fixup1 (int bytemode, int sizeflag)
16885 && (prefixes & PREFIX_LOCK) != 0)
16887 if (prefixes & PREFIX_REPZ)
16888 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16889 if (prefixes & PREFIX_REPNZ)
16890 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16893 OP_E (bytemode, sizeflag);
16896 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16897 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16901 HLE_Fixup2 (int bytemode, int sizeflag)
16903 if (modrm.mod != 3)
16905 if (prefixes & PREFIX_REPZ)
16906 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16907 if (prefixes & PREFIX_REPNZ)
16908 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16911 OP_E (bytemode, sizeflag);
16914 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16915 "xrelease" for memory operand. No check for LOCK prefix. */
16918 HLE_Fixup3 (int bytemode, int sizeflag)
16921 && last_repz_prefix > last_repnz_prefix
16922 && (prefixes & PREFIX_REPZ) != 0)
16923 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16925 OP_E (bytemode, sizeflag);
16929 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16934 /* Change cmpxchg8b to cmpxchg16b. */
16935 char *p = mnemonicendp - 2;
16936 mnemonicendp = stpcpy (p, "16b");
16939 else if ((prefixes & PREFIX_LOCK) != 0)
16941 if (prefixes & PREFIX_REPZ)
16942 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16943 if (prefixes & PREFIX_REPNZ)
16944 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16947 OP_M (bytemode, sizeflag);
16951 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16953 const char **names;
16957 switch (vex.length)
16971 oappend (names[reg]);
16975 CRC32_Fixup (int bytemode, int sizeflag)
16977 /* Add proper suffix to "crc32". */
16978 char *p = mnemonicendp;
16997 if (sizeflag & DFLAG)
17001 used_prefixes |= (prefixes & PREFIX_DATA);
17005 oappend (INTERNAL_DISASSEMBLER_ERROR);
17012 if (modrm.mod == 3)
17016 /* Skip mod/rm byte. */
17021 add = (rex & REX_B) ? 8 : 0;
17022 if (bytemode == b_mode)
17026 oappend (names8rex[modrm.rm + add]);
17028 oappend (names8[modrm.rm + add]);
17034 oappend (names64[modrm.rm + add]);
17035 else if ((prefixes & PREFIX_DATA))
17036 oappend (names16[modrm.rm + add]);
17038 oappend (names32[modrm.rm + add]);
17042 OP_E (bytemode, sizeflag);
17046 FXSAVE_Fixup (int bytemode, int sizeflag)
17048 /* Add proper suffix to "fxsave" and "fxrstor". */
17052 char *p = mnemonicendp;
17058 OP_M (bytemode, sizeflag);
17062 PCMPESTR_Fixup (int bytemode, int sizeflag)
17064 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
17067 char *p = mnemonicendp;
17072 else if (sizeflag & SUFFIX_ALWAYS)
17079 OP_EX (bytemode, sizeflag);
17082 /* Display the destination register operand for instructions with
17086 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17089 const char **names;
17097 reg = vex.register_specifier;
17104 if (bytemode == vex_scalar_mode)
17106 oappend (names_xmm[reg]);
17110 switch (vex.length)
17117 case vex_vsib_q_w_dq_mode:
17118 case vex_vsib_q_w_d_mode:
17134 names = names_mask;
17148 case vex_vsib_q_w_dq_mode:
17149 case vex_vsib_q_w_d_mode:
17150 names = vex.w ? names_ymm : names_xmm;
17159 names = names_mask;
17162 /* See PR binutils/20893 for a reproducer. */
17174 oappend (names[reg]);
17177 /* Get the VEX immediate byte without moving codep. */
17179 static unsigned char
17180 get_vex_imm8 (int sizeflag, int opnum)
17182 int bytes_before_imm = 0;
17184 if (modrm.mod != 3)
17186 /* There are SIB/displacement bytes. */
17187 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17189 /* 32/64 bit address mode */
17190 int base = modrm.rm;
17192 /* Check SIB byte. */
17195 FETCH_DATA (the_info, codep + 1);
17197 /* When decoding the third source, don't increase
17198 bytes_before_imm as this has already been incremented
17199 by one in OP_E_memory while decoding the second
17202 bytes_before_imm++;
17205 /* Don't increase bytes_before_imm when decoding the third source,
17206 it has already been incremented by OP_E_memory while decoding
17207 the second source operand. */
17213 /* When modrm.rm == 5 or modrm.rm == 4 and base in
17214 SIB == 5, there is a 4 byte displacement. */
17216 /* No displacement. */
17218 /* Fall through. */
17220 /* 4 byte displacement. */
17221 bytes_before_imm += 4;
17224 /* 1 byte displacement. */
17225 bytes_before_imm++;
17232 /* 16 bit address mode */
17233 /* Don't increase bytes_before_imm when decoding the third source,
17234 it has already been incremented by OP_E_memory while decoding
17235 the second source operand. */
17241 /* When modrm.rm == 6, there is a 2 byte displacement. */
17243 /* No displacement. */
17245 /* Fall through. */
17247 /* 2 byte displacement. */
17248 bytes_before_imm += 2;
17251 /* 1 byte displacement: when decoding the third source,
17252 don't increase bytes_before_imm as this has already
17253 been incremented by one in OP_E_memory while decoding
17254 the second source operand. */
17256 bytes_before_imm++;
17264 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17265 return codep [bytes_before_imm];
17269 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17271 const char **names;
17273 if (reg == -1 && modrm.mod != 3)
17275 OP_E_memory (bytemode, sizeflag);
17287 else if (reg > 7 && address_mode != mode_64bit)
17291 switch (vex.length)
17302 oappend (names[reg]);
17306 OP_EX_VexImmW (int bytemode, int sizeflag)
17309 static unsigned char vex_imm8;
17311 if (vex_w_done == 0)
17315 /* Skip mod/rm byte. */
17319 vex_imm8 = get_vex_imm8 (sizeflag, 0);
17322 reg = vex_imm8 >> 4;
17324 OP_EX_VexReg (bytemode, sizeflag, reg);
17326 else if (vex_w_done == 1)
17331 reg = vex_imm8 >> 4;
17333 OP_EX_VexReg (bytemode, sizeflag, reg);
17337 /* Output the imm8 directly. */
17338 scratchbuf[0] = '$';
17339 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17340 oappend_maybe_intel (scratchbuf);
17341 scratchbuf[0] = '\0';
17347 OP_Vex_2src (int bytemode, int sizeflag)
17349 if (modrm.mod == 3)
17351 int reg = modrm.rm;
17355 oappend (names_xmm[reg]);
17360 && (bytemode == v_mode || bytemode == v_swap_mode))
17362 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17363 used_prefixes |= (prefixes & PREFIX_DATA);
17365 OP_E (bytemode, sizeflag);
17370 OP_Vex_2src_1 (int bytemode, int sizeflag)
17372 if (modrm.mod == 3)
17374 /* Skip mod/rm byte. */
17380 oappend (names_xmm[vex.register_specifier]);
17382 OP_Vex_2src (bytemode, sizeflag);
17386 OP_Vex_2src_2 (int bytemode, int sizeflag)
17389 OP_Vex_2src (bytemode, sizeflag);
17391 oappend (names_xmm[vex.register_specifier]);
17395 OP_EX_VexW (int bytemode, int sizeflag)
17403 /* Skip mod/rm byte. */
17408 reg = get_vex_imm8 (sizeflag, 0) >> 4;
17413 reg = get_vex_imm8 (sizeflag, 1) >> 4;
17416 OP_EX_VexReg (bytemode, sizeflag, reg);
17420 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17421 int sizeflag ATTRIBUTE_UNUSED)
17423 /* Skip the immediate byte and check for invalid bits. */
17424 FETCH_DATA (the_info, codep + 1);
17425 if (*codep++ & 0xf)
17430 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17433 const char **names;
17435 FETCH_DATA (the_info, codep + 1);
17438 if (bytemode != x_mode)
17445 if (reg > 7 && address_mode != mode_64bit)
17448 switch (vex.length)
17459 oappend (names[reg]);
17463 OP_XMM_VexW (int bytemode, int sizeflag)
17465 /* Turn off the REX.W bit since it is used for swapping operands
17468 OP_XMM (bytemode, sizeflag);
17472 OP_EX_Vex (int bytemode, int sizeflag)
17474 if (modrm.mod != 3)
17476 if (vex.register_specifier != 0)
17480 OP_EX (bytemode, sizeflag);
17484 OP_XMM_Vex (int bytemode, int sizeflag)
17486 if (modrm.mod != 3)
17488 if (vex.register_specifier != 0)
17492 OP_XMM (bytemode, sizeflag);
17496 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17498 switch (vex.length)
17501 mnemonicendp = stpcpy (obuf, "vzeroupper");
17504 mnemonicendp = stpcpy (obuf, "vzeroall");
17511 static struct op vex_cmp_op[] =
17513 { STRING_COMMA_LEN ("eq") },
17514 { STRING_COMMA_LEN ("lt") },
17515 { STRING_COMMA_LEN ("le") },
17516 { STRING_COMMA_LEN ("unord") },
17517 { STRING_COMMA_LEN ("neq") },
17518 { STRING_COMMA_LEN ("nlt") },
17519 { STRING_COMMA_LEN ("nle") },
17520 { STRING_COMMA_LEN ("ord") },
17521 { STRING_COMMA_LEN ("eq_uq") },
17522 { STRING_COMMA_LEN ("nge") },
17523 { STRING_COMMA_LEN ("ngt") },
17524 { STRING_COMMA_LEN ("false") },
17525 { STRING_COMMA_LEN ("neq_oq") },
17526 { STRING_COMMA_LEN ("ge") },
17527 { STRING_COMMA_LEN ("gt") },
17528 { STRING_COMMA_LEN ("true") },
17529 { STRING_COMMA_LEN ("eq_os") },
17530 { STRING_COMMA_LEN ("lt_oq") },
17531 { STRING_COMMA_LEN ("le_oq") },
17532 { STRING_COMMA_LEN ("unord_s") },
17533 { STRING_COMMA_LEN ("neq_us") },
17534 { STRING_COMMA_LEN ("nlt_uq") },
17535 { STRING_COMMA_LEN ("nle_uq") },
17536 { STRING_COMMA_LEN ("ord_s") },
17537 { STRING_COMMA_LEN ("eq_us") },
17538 { STRING_COMMA_LEN ("nge_uq") },
17539 { STRING_COMMA_LEN ("ngt_uq") },
17540 { STRING_COMMA_LEN ("false_os") },
17541 { STRING_COMMA_LEN ("neq_os") },
17542 { STRING_COMMA_LEN ("ge_oq") },
17543 { STRING_COMMA_LEN ("gt_oq") },
17544 { STRING_COMMA_LEN ("true_us") },
17548 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17550 unsigned int cmp_type;
17552 FETCH_DATA (the_info, codep + 1);
17553 cmp_type = *codep++ & 0xff;
17554 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17557 char *p = mnemonicendp - 2;
17561 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17562 mnemonicendp += vex_cmp_op[cmp_type].len;
17566 /* We have a reserved extension byte. Output it directly. */
17567 scratchbuf[0] = '$';
17568 print_operand_value (scratchbuf + 1, 1, cmp_type);
17569 oappend_maybe_intel (scratchbuf);
17570 scratchbuf[0] = '\0';
17575 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17576 int sizeflag ATTRIBUTE_UNUSED)
17578 unsigned int cmp_type;
17583 FETCH_DATA (the_info, codep + 1);
17584 cmp_type = *codep++ & 0xff;
17585 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17586 If it's the case, print suffix, otherwise - print the immediate. */
17587 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17592 char *p = mnemonicendp - 2;
17594 /* vpcmp* can have both one- and two-lettered suffix. */
17608 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17609 mnemonicendp += simd_cmp_op[cmp_type].len;
17613 /* We have a reserved extension byte. Output it directly. */
17614 scratchbuf[0] = '$';
17615 print_operand_value (scratchbuf + 1, 1, cmp_type);
17616 oappend_maybe_intel (scratchbuf);
17617 scratchbuf[0] = '\0';
17621 static const struct op pclmul_op[] =
17623 { STRING_COMMA_LEN ("lql") },
17624 { STRING_COMMA_LEN ("hql") },
17625 { STRING_COMMA_LEN ("lqh") },
17626 { STRING_COMMA_LEN ("hqh") }
17630 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17631 int sizeflag ATTRIBUTE_UNUSED)
17633 unsigned int pclmul_type;
17635 FETCH_DATA (the_info, codep + 1);
17636 pclmul_type = *codep++ & 0xff;
17637 switch (pclmul_type)
17648 if (pclmul_type < ARRAY_SIZE (pclmul_op))
17651 char *p = mnemonicendp - 3;
17656 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17657 mnemonicendp += pclmul_op[pclmul_type].len;
17661 /* We have a reserved extension byte. Output it directly. */
17662 scratchbuf[0] = '$';
17663 print_operand_value (scratchbuf + 1, 1, pclmul_type);
17664 oappend_maybe_intel (scratchbuf);
17665 scratchbuf[0] = '\0';
17670 MOVBE_Fixup (int bytemode, int sizeflag)
17672 /* Add proper suffix to "movbe". */
17673 char *p = mnemonicendp;
17682 if (sizeflag & SUFFIX_ALWAYS)
17688 if (sizeflag & DFLAG)
17692 used_prefixes |= (prefixes & PREFIX_DATA);
17697 oappend (INTERNAL_DISASSEMBLER_ERROR);
17704 OP_M (bytemode, sizeflag);
17708 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17711 const char **names;
17713 /* Skip mod/rm byte. */
17727 oappend (names[reg]);
17731 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17733 const char **names;
17740 oappend (names[vex.register_specifier]);
17744 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17747 || (bytemode != mask_mode && bytemode != mask_bd_mode))
17751 if ((rex & REX_R) != 0 || !vex.r)
17757 oappend (names_mask [modrm.reg]);
17761 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17764 || (bytemode != evex_rounding_mode
17765 && bytemode != evex_sae_mode))
17767 if (modrm.mod == 3 && vex.b)
17770 case evex_rounding_mode:
17771 oappend (names_rounding[vex.ll]);
17773 case evex_sae_mode: