1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
23 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
25 modified by John Hassey (hassey@dg-rtp.dg.com)
26 x86-64 support added by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
29 /* The main tables describing the instructions is essentially a copy
30 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
31 Programmers Manual. Usually, there is a capital letter, followed
32 by a small letter. The capital letter tell the addressing mode,
33 and the small letter tells about the operand size. Refer to
34 the Intel manual for details. */
39 #include "opcode/i386.h"
40 #include "libiberty.h"
44 static int fetch_data (struct disassemble_info *, bfd_byte *);
45 static void ckprefix (void);
46 static const char *prefix_name (int, int);
47 static int print_insn (bfd_vma, disassemble_info *);
48 static void dofloat (int);
49 static void OP_ST (int, int);
50 static void OP_STi (int, int);
51 static int putop (const char *, int);
52 static void oappend (const char *);
53 static void append_seg (void);
54 static void OP_indirE (int, int);
55 static void print_operand_value (char *, int, bfd_vma);
56 static void OP_E_extended (int, int, int);
57 static void print_displacement (char *, bfd_vma);
58 static void OP_E (int, int);
59 static void OP_G (int, int);
60 static bfd_vma get64 (void);
61 static bfd_signed_vma get32 (void);
62 static bfd_signed_vma get32s (void);
63 static int get16 (void);
64 static void set_op (bfd_vma, int);
65 static void OP_Skip_MODRM (int, int);
66 static void OP_REG (int, int);
67 static void OP_IMREG (int, int);
68 static void OP_I (int, int);
69 static void OP_I64 (int, int);
70 static void OP_sI (int, int);
71 static void OP_J (int, int);
72 static void OP_SEG (int, int);
73 static void OP_DIR (int, int);
74 static void OP_OFF (int, int);
75 static void OP_OFF64 (int, int);
76 static void ptr_reg (int, int);
77 static void OP_ESreg (int, int);
78 static void OP_DSreg (int, int);
79 static void OP_C (int, int);
80 static void OP_D (int, int);
81 static void OP_T (int, int);
82 static void OP_R (int, int);
83 static void OP_MMX (int, int);
84 static void OP_XMM (int, int);
85 static void OP_EM (int, int);
86 static void OP_EX (int, int);
87 static void OP_EMC (int,int);
88 static void OP_MXC (int,int);
89 static void OP_MS (int, int);
90 static void OP_XS (int, int);
91 static void OP_M (int, int);
92 static void OP_0f07 (int, int);
93 static void OP_Monitor (int, int);
94 static void OP_Mwait (int, int);
95 static void NOP_Fixup1 (int, int);
96 static void NOP_Fixup2 (int, int);
97 static void OP_3DNowSuffix (int, int);
98 static void OP_SIMD_Suffix (int, int);
99 static void BadOp (void);
100 static void REP_Fixup (int, int);
101 static void CMPXCHG8B_Fixup (int, int);
102 static void XMM_Fixup (int, int);
103 static void CRC32_Fixup (int, int);
104 static void print_drex_arg (unsigned int, int, int);
105 static void OP_DREX4 (int, int);
106 static void OP_DREX3 (int, int);
107 static void OP_DREX_ICMP (int, int);
108 static void OP_DREX_FCMP (int, int);
111 /* Points to first byte not fetched. */
112 bfd_byte *max_fetched;
113 bfd_byte the_buffer[MAX_MNEM_SIZE];
126 enum address_mode address_mode;
128 /* Flags for the prefixes for the current instruction. See below. */
131 /* REX prefix the current instruction. See below. */
133 /* Bits of REX we've already used. */
135 /* Mark parts used in the REX prefix. When we are testing for
136 empty prefix (for 8bit register REX extension), just mask it
137 out. Otherwise test for REX bit is excuse for existence of REX
138 only in case value is nonzero. */
139 #define USED_REX(value) \
144 rex_used |= (value) | REX_OPCODE; \
147 rex_used |= REX_OPCODE; \
150 /* Special 'registers' for DREX handling */
151 #define DREX_REG_UNKNOWN 1000 /* not initialized */
152 #define DREX_REG_MEMORY 1001 /* use MODRM/SIB/OFFSET memory */
154 /* The DREX byte has the following fields:
155 Bits 7-4 -- DREX.Dest, xmm destination register
156 Bit 3 -- DREX.OC0, operand config bit defines operand order
157 Bit 2 -- DREX.R, equivalent to REX_R bit, to extend ModRM register
158 Bit 1 -- DREX.X, equivalent to REX_X bit, to extend SIB index field
159 Bit 0 -- DREX.W, equivalent to REX_B bit, to extend ModRM r/m field,
160 SIB base field, or opcode reg field. */
161 #define DREX_XMM(drex) ((drex >> 4) & 0xf)
162 #define DREX_OC0(drex) ((drex >> 3) & 0x1)
164 /* Flags for prefixes which we somehow handled when printing the
165 current instruction. */
166 static int used_prefixes;
168 /* Flags stored in PREFIXES. */
169 #define PREFIX_REPZ 1
170 #define PREFIX_REPNZ 2
171 #define PREFIX_LOCK 4
173 #define PREFIX_SS 0x10
174 #define PREFIX_DS 0x20
175 #define PREFIX_ES 0x40
176 #define PREFIX_FS 0x80
177 #define PREFIX_GS 0x100
178 #define PREFIX_DATA 0x200
179 #define PREFIX_ADDR 0x400
180 #define PREFIX_FWAIT 0x800
182 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
183 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
185 #define FETCH_DATA(info, addr) \
186 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
187 ? 1 : fetch_data ((info), (addr)))
190 fetch_data (struct disassemble_info *info, bfd_byte *addr)
193 struct dis_private *priv = (struct dis_private *) info->private_data;
194 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
196 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
197 status = (*info->read_memory_func) (start,
199 addr - priv->max_fetched,
205 /* If we did manage to read at least one byte, then
206 print_insn_i386 will do something sensible. Otherwise, print
207 an error. We do that here because this is where we know
209 if (priv->max_fetched == priv->the_buffer)
210 (*info->memory_error_func) (status, start, info);
211 longjmp (priv->bailout, 1);
214 priv->max_fetched = addr;
218 #define XX { NULL, 0 }
220 #define Eb { OP_E, b_mode }
221 #define Ev { OP_E, v_mode }
222 #define Ed { OP_E, d_mode }
223 #define Edq { OP_E, dq_mode }
224 #define Edqw { OP_E, dqw_mode }
225 #define Edqb { OP_E, dqb_mode }
226 #define Edqd { OP_E, dqd_mode }
227 #define Eq { OP_E, q_mode }
228 #define indirEv { OP_indirE, stack_v_mode }
229 #define indirEp { OP_indirE, f_mode }
230 #define stackEv { OP_E, stack_v_mode }
231 #define Em { OP_E, m_mode }
232 #define Ew { OP_E, w_mode }
233 #define M { OP_M, 0 } /* lea, lgdt, etc. */
234 #define Ma { OP_M, v_mode }
235 #define Mb { OP_M, b_mode }
236 #define Md { OP_M, d_mode }
237 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
238 #define Mq { OP_M, q_mode }
239 #define Gb { OP_G, b_mode }
240 #define Gv { OP_G, v_mode }
241 #define Gd { OP_G, d_mode }
242 #define Gdq { OP_G, dq_mode }
243 #define Gm { OP_G, m_mode }
244 #define Gw { OP_G, w_mode }
245 #define Rd { OP_R, d_mode }
246 #define Rm { OP_R, m_mode }
247 #define Ib { OP_I, b_mode }
248 #define sIb { OP_sI, b_mode } /* sign extened byte */
249 #define Iv { OP_I, v_mode }
250 #define Iq { OP_I, q_mode }
251 #define Iv64 { OP_I64, v_mode }
252 #define Iw { OP_I, w_mode }
253 #define I1 { OP_I, const_1_mode }
254 #define Jb { OP_J, b_mode }
255 #define Jv { OP_J, v_mode }
256 #define Cm { OP_C, m_mode }
257 #define Dm { OP_D, m_mode }
258 #define Td { OP_T, d_mode }
259 #define Skip_MODRM { OP_Skip_MODRM, 0 }
261 #define RMeAX { OP_REG, eAX_reg }
262 #define RMeBX { OP_REG, eBX_reg }
263 #define RMeCX { OP_REG, eCX_reg }
264 #define RMeDX { OP_REG, eDX_reg }
265 #define RMeSP { OP_REG, eSP_reg }
266 #define RMeBP { OP_REG, eBP_reg }
267 #define RMeSI { OP_REG, eSI_reg }
268 #define RMeDI { OP_REG, eDI_reg }
269 #define RMrAX { OP_REG, rAX_reg }
270 #define RMrBX { OP_REG, rBX_reg }
271 #define RMrCX { OP_REG, rCX_reg }
272 #define RMrDX { OP_REG, rDX_reg }
273 #define RMrSP { OP_REG, rSP_reg }
274 #define RMrBP { OP_REG, rBP_reg }
275 #define RMrSI { OP_REG, rSI_reg }
276 #define RMrDI { OP_REG, rDI_reg }
277 #define RMAL { OP_REG, al_reg }
278 #define RMAL { OP_REG, al_reg }
279 #define RMCL { OP_REG, cl_reg }
280 #define RMDL { OP_REG, dl_reg }
281 #define RMBL { OP_REG, bl_reg }
282 #define RMAH { OP_REG, ah_reg }
283 #define RMCH { OP_REG, ch_reg }
284 #define RMDH { OP_REG, dh_reg }
285 #define RMBH { OP_REG, bh_reg }
286 #define RMAX { OP_REG, ax_reg }
287 #define RMDX { OP_REG, dx_reg }
289 #define eAX { OP_IMREG, eAX_reg }
290 #define eBX { OP_IMREG, eBX_reg }
291 #define eCX { OP_IMREG, eCX_reg }
292 #define eDX { OP_IMREG, eDX_reg }
293 #define eSP { OP_IMREG, eSP_reg }
294 #define eBP { OP_IMREG, eBP_reg }
295 #define eSI { OP_IMREG, eSI_reg }
296 #define eDI { OP_IMREG, eDI_reg }
297 #define AL { OP_IMREG, al_reg }
298 #define CL { OP_IMREG, cl_reg }
299 #define DL { OP_IMREG, dl_reg }
300 #define BL { OP_IMREG, bl_reg }
301 #define AH { OP_IMREG, ah_reg }
302 #define CH { OP_IMREG, ch_reg }
303 #define DH { OP_IMREG, dh_reg }
304 #define BH { OP_IMREG, bh_reg }
305 #define AX { OP_IMREG, ax_reg }
306 #define DX { OP_IMREG, dx_reg }
307 #define zAX { OP_IMREG, z_mode_ax_reg }
308 #define indirDX { OP_IMREG, indir_dx_reg }
310 #define Sw { OP_SEG, w_mode }
311 #define Sv { OP_SEG, v_mode }
312 #define Ap { OP_DIR, 0 }
313 #define Ob { OP_OFF64, b_mode }
314 #define Ov { OP_OFF64, v_mode }
315 #define Xb { OP_DSreg, eSI_reg }
316 #define Xv { OP_DSreg, eSI_reg }
317 #define Xz { OP_DSreg, eSI_reg }
318 #define Yb { OP_ESreg, eDI_reg }
319 #define Yv { OP_ESreg, eDI_reg }
320 #define DSBX { OP_DSreg, eBX_reg }
322 #define es { OP_REG, es_reg }
323 #define ss { OP_REG, ss_reg }
324 #define cs { OP_REG, cs_reg }
325 #define ds { OP_REG, ds_reg }
326 #define fs { OP_REG, fs_reg }
327 #define gs { OP_REG, gs_reg }
329 #define MX { OP_MMX, 0 }
330 #define XM { OP_XMM, 0 }
331 #define EM { OP_EM, v_mode }
332 #define EMd { OP_EM, d_mode }
333 #define EMx { OP_EM, x_mode }
334 #define EXw { OP_EX, w_mode }
335 #define EXd { OP_EX, d_mode }
336 #define EXq { OP_EX, q_mode }
337 #define EXx { OP_EX, x_mode }
338 #define MS { OP_MS, v_mode }
339 #define XS { OP_XS, v_mode }
340 #define EMCq { OP_EMC, q_mode }
341 #define MXC { OP_MXC, 0 }
342 #define OPSUF { OP_3DNowSuffix, 0 }
343 #define OPSIMD { OP_SIMD_Suffix, 0 }
344 #define XMM0 { XMM_Fixup, 0 }
346 /* Used handle "rep" prefix for string instructions. */
347 #define Xbr { REP_Fixup, eSI_reg }
348 #define Xvr { REP_Fixup, eSI_reg }
349 #define Ybr { REP_Fixup, eDI_reg }
350 #define Yvr { REP_Fixup, eDI_reg }
351 #define Yzr { REP_Fixup, eDI_reg }
352 #define indirDXr { REP_Fixup, indir_dx_reg }
353 #define ALr { REP_Fixup, al_reg }
354 #define eAXr { REP_Fixup, eAX_reg }
356 #define cond_jump_flag { NULL, cond_jump_mode }
357 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
359 /* bits in sizeflag */
360 #define SUFFIX_ALWAYS 4
364 #define b_mode 1 /* byte operand */
365 #define v_mode 2 /* operand size depends on prefixes */
366 #define w_mode 3 /* word operand */
367 #define d_mode 4 /* double word operand */
368 #define q_mode 5 /* quad word operand */
369 #define t_mode 6 /* ten-byte operand */
370 #define x_mode 7 /* 16-byte XMM operand */
371 #define m_mode 8 /* d_mode in 32bit, q_mode in 64bit mode. */
372 #define cond_jump_mode 9
373 #define loop_jcxz_mode 10
374 #define dq_mode 11 /* operand size depends on REX prefixes. */
375 #define dqw_mode 12 /* registers like dq_mode, memory like w_mode. */
376 #define f_mode 13 /* 4- or 6-byte pointer operand */
377 #define const_1_mode 14
378 #define stack_v_mode 15 /* v_mode for stack-related opcodes. */
379 #define z_mode 16 /* non-quad operand size depends on prefixes */
380 #define o_mode 17 /* 16-byte operand */
381 #define dqb_mode 18 /* registers like dq_mode, memory like b_mode. */
382 #define dqd_mode 19 /* registers like dq_mode, memory like d_mode. */
384 /* Flags that are OR'ed into the bytemode field to pass extra information. */
385 #define DREX_OC1 0x4000 /* OC1 bit set */
386 #define DREX_NO_OC0 0x2000 /* OC0 bit not used */
387 #define DREX_MASK 0x6000 /* mask to delete */
432 #define z_mode_ax_reg 149
433 #define indir_dx_reg 150
436 #define USE_REG_TABLE 2
437 #define USE_MOD_TABLE 3
438 #define USE_RM_TABLE 4
439 #define USE_PREFIX_TABLE 5
440 #define USE_X86_64_TABLE 6
441 #define USE_3BYTE_TABLE 7
443 #define FLOAT NULL, { { NULL, FLOATCODE } }
445 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
446 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
447 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
448 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
449 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
450 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
451 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
454 #define REG_81 (REG_80 + 1)
455 #define REG_82 (REG_81 + 1)
456 #define REG_8F (REG_82 + 1)
457 #define REG_C0 (REG_8F + 1)
458 #define REG_C1 (REG_C0 + 1)
459 #define REG_C6 (REG_C1 + 1)
460 #define REG_C7 (REG_C6 + 1)
461 #define REG_D0 (REG_C7 + 1)
462 #define REG_D1 (REG_D0 + 1)
463 #define REG_D2 (REG_D1 + 1)
464 #define REG_D3 (REG_D2 + 1)
465 #define REG_F6 (REG_D3 + 1)
466 #define REG_F7 (REG_F6 + 1)
467 #define REG_FE (REG_F7 + 1)
468 #define REG_FF (REG_FE + 1)
469 #define REG_0F00 (REG_FF + 1)
470 #define REG_0F01 (REG_0F00 + 1)
471 #define REG_0F0E (REG_0F01 + 1)
472 #define REG_0F18 (REG_0F0E + 1)
473 #define REG_0F71 (REG_0F18 + 1)
474 #define REG_0F72 (REG_0F71 + 1)
475 #define REG_0F73 (REG_0F72 + 1)
476 #define REG_0FA6 (REG_0F73 + 1)
477 #define REG_0FA7 (REG_0FA6 + 1)
478 #define REG_0FAE (REG_0FA7 + 1)
479 #define REG_0FBA (REG_0FAE + 1)
480 #define REG_0FC7 (REG_0FBA + 1)
483 #define MOD_0F13 (MOD_8D + 1)
484 #define MOD_0F17 (MOD_0F13 + 1)
485 #define MOD_0F20 (MOD_0F17 + 1)
486 #define MOD_0F21 (MOD_0F20 + 1)
487 #define MOD_0F22 (MOD_0F21 + 1)
488 #define MOD_0F23 (MOD_0F22 + 1)
489 #define MOD_0F24 (MOD_0F23 + 1)
490 #define MOD_0F26 (MOD_0F24 + 1)
491 #define MOD_0FB2 (MOD_0F26 + 1)
492 #define MOD_0FB4 (MOD_0FB2 + 1)
493 #define MOD_0FB5 (MOD_0FB4 + 1)
494 #define MOD_0F01_REG_0 (MOD_0FB5 + 1)
495 #define MOD_0F01_REG_1 (MOD_0F01_REG_0 + 1)
496 #define MOD_0F01_REG_2 (MOD_0F01_REG_1 + 1)
497 #define MOD_0F01_REG_3 (MOD_0F01_REG_2 + 1)
498 #define MOD_0F01_REG_7 (MOD_0F01_REG_3 + 1)
499 #define MOD_0F18_REG_0 (MOD_0F01_REG_7 + 1)
500 #define MOD_0F18_REG_1 (MOD_0F18_REG_0 + 1)
501 #define MOD_0F18_REG_2 (MOD_0F18_REG_1 + 1)
502 #define MOD_0F18_REG_3 (MOD_0F18_REG_2 + 1)
503 #define MOD_0F71_REG_2 (MOD_0F18_REG_3 + 1)
504 #define MOD_0F71_REG_4 (MOD_0F71_REG_2 + 1)
505 #define MOD_0F71_REG_6 (MOD_0F71_REG_4 + 1)
506 #define MOD_0F72_REG_2 (MOD_0F71_REG_6 + 1)
507 #define MOD_0F72_REG_4 (MOD_0F72_REG_2 + 1)
508 #define MOD_0F72_REG_6 (MOD_0F72_REG_4 + 1)
509 #define MOD_0F73_REG_2 (MOD_0F72_REG_6 + 1)
510 #define MOD_0F73_REG_3 (MOD_0F73_REG_2 + 1)
511 #define MOD_0F73_REG_6 (MOD_0F73_REG_3 + 1)
512 #define MOD_0F73_REG_7 (MOD_0F73_REG_6 + 1)
513 #define MOD_0FAE_REG_0 (MOD_0F73_REG_7 + 1)
514 #define MOD_0FAE_REG_1 (MOD_0FAE_REG_0 + 1)
515 #define MOD_0FAE_REG_2 (MOD_0FAE_REG_1 + 1)
516 #define MOD_0FAE_REG_3 (MOD_0FAE_REG_2 + 1)
517 #define MOD_0FAE_REG_5 (MOD_0FAE_REG_3 + 1)
518 #define MOD_0FAE_REG_6 (MOD_0FAE_REG_5 + 1)
519 #define MOD_0FAE_REG_7 (MOD_0FAE_REG_6 + 1)
520 #define MOD_0FC7_REG_6 (MOD_0FAE_REG_7 + 1)
521 #define MOD_0FC7_REG_7 (MOD_0FC7_REG_6 + 1)
522 #define MOD_0F12_PREFIX_0 (MOD_0FC7_REG_7 + 1)
523 #define MOD_0F16_PREFIX_0 (MOD_0F12_PREFIX_0 + 1)
524 #define MOD_0FF0_PREFIX_3 (MOD_0F16_PREFIX_0 + 1)
525 #define MOD_62_32BIT (MOD_0FF0_PREFIX_3 + 1)
526 #define MOD_C4_32BIT (MOD_62_32BIT + 1)
527 #define MOD_C5_32BIT (MOD_C4_32BIT + 1)
529 #define RM_0F01_REG_0 0
530 #define RM_0F01_REG_1 (RM_0F01_REG_0 + 1)
531 #define RM_0F01_REG_3 (RM_0F01_REG_1 + 1)
532 #define RM_0F01_REG_7 (RM_0F01_REG_3 + 1)
533 #define RM_0FAE_REG_5 (RM_0F01_REG_7 + 1)
534 #define RM_0FAE_REG_6 (RM_0FAE_REG_5 + 1)
535 #define RM_0FAE_REG_7 (RM_0FAE_REG_6 + 1)
538 #define PREFIX_0F10 (PREFIX_90 + 1)
539 #define PREFIX_0F11 (PREFIX_0F10 + 1)
540 #define PREFIX_0F12 (PREFIX_0F11 + 1)
541 #define PREFIX_0F16 (PREFIX_0F12 + 1)
542 #define PREFIX_0F2A (PREFIX_0F16 + 1)
543 #define PREFIX_0F2B (PREFIX_0F2A + 1)
544 #define PREFIX_0F2C (PREFIX_0F2B + 1)
545 #define PREFIX_0F2D (PREFIX_0F2C + 1)
546 #define PREFIX_0F2E (PREFIX_0F2D + 1)
547 #define PREFIX_0F2F (PREFIX_0F2E + 1)
548 #define PREFIX_0F51 (PREFIX_0F2F + 1)
549 #define PREFIX_0F52 (PREFIX_0F51 + 1)
550 #define PREFIX_0F53 (PREFIX_0F52 + 1)
551 #define PREFIX_0F58 (PREFIX_0F53 + 1)
552 #define PREFIX_0F59 (PREFIX_0F58 + 1)
553 #define PREFIX_0F5A (PREFIX_0F59 + 1)
554 #define PREFIX_0F5B (PREFIX_0F5A + 1)
555 #define PREFIX_0F5C (PREFIX_0F5B + 1)
556 #define PREFIX_0F5D (PREFIX_0F5C + 1)
557 #define PREFIX_0F5E (PREFIX_0F5D + 1)
558 #define PREFIX_0F5F (PREFIX_0F5E + 1)
559 #define PREFIX_0F60 (PREFIX_0F5F + 1)
560 #define PREFIX_0F61 (PREFIX_0F60 + 1)
561 #define PREFIX_0F62 (PREFIX_0F61 + 1)
562 #define PREFIX_0F6C (PREFIX_0F62 + 1)
563 #define PREFIX_0F6D (PREFIX_0F6C + 1)
564 #define PREFIX_0F6F (PREFIX_0F6D + 1)
565 #define PREFIX_0F70 (PREFIX_0F6F + 1)
566 #define PREFIX_0F78 (PREFIX_0F70 + 1)
567 #define PREFIX_0F79 (PREFIX_0F78 + 1)
568 #define PREFIX_0F7C (PREFIX_0F79 + 1)
569 #define PREFIX_0F7D (PREFIX_0F7C + 1)
570 #define PREFIX_0F7E (PREFIX_0F7D + 1)
571 #define PREFIX_0F7F (PREFIX_0F7E + 1)
572 #define PREFIX_0FB8 (PREFIX_0F7F + 1)
573 #define PREFIX_0FBD (PREFIX_0FB8 + 1)
574 #define PREFIX_0FC2 (PREFIX_0FBD + 1)
575 #define PREFIX_0FD0 (PREFIX_0FC2 + 1)
576 #define PREFIX_0FD6 (PREFIX_0FD0 + 1)
577 #define PREFIX_0FE6 (PREFIX_0FD6 + 1)
578 #define PREFIX_0FE7 (PREFIX_0FE6 + 1)
579 #define PREFIX_0FF0 (PREFIX_0FE7 + 1)
580 #define PREFIX_0FF7 (PREFIX_0FF0 + 1)
581 #define PREFIX_0F3810 (PREFIX_0FF7 + 1)
582 #define PREFIX_0F3814 (PREFIX_0F3810 + 1)
583 #define PREFIX_0F3815 (PREFIX_0F3814 + 1)
584 #define PREFIX_0F3817 (PREFIX_0F3815 + 1)
585 #define PREFIX_0F3820 (PREFIX_0F3817 + 1)
586 #define PREFIX_0F3821 (PREFIX_0F3820 + 1)
587 #define PREFIX_0F3822 (PREFIX_0F3821 + 1)
588 #define PREFIX_0F3823 (PREFIX_0F3822 + 1)
589 #define PREFIX_0F3824 (PREFIX_0F3823 + 1)
590 #define PREFIX_0F3825 (PREFIX_0F3824 + 1)
591 #define PREFIX_0F3828 (PREFIX_0F3825 + 1)
592 #define PREFIX_0F3829 (PREFIX_0F3828 + 1)
593 #define PREFIX_0F382A (PREFIX_0F3829 + 1)
594 #define PREFIX_0F382B (PREFIX_0F382A + 1)
595 #define PREFIX_0F3830 (PREFIX_0F382B + 1)
596 #define PREFIX_0F3831 (PREFIX_0F3830 + 1)
597 #define PREFIX_0F3832 (PREFIX_0F3831 + 1)
598 #define PREFIX_0F3833 (PREFIX_0F3832 + 1)
599 #define PREFIX_0F3834 (PREFIX_0F3833 + 1)
600 #define PREFIX_0F3835 (PREFIX_0F3834 + 1)
601 #define PREFIX_0F3837 (PREFIX_0F3835 + 1)
602 #define PREFIX_0F3838 (PREFIX_0F3837 + 1)
603 #define PREFIX_0F3839 (PREFIX_0F3838 + 1)
604 #define PREFIX_0F383A (PREFIX_0F3839 + 1)
605 #define PREFIX_0F383B (PREFIX_0F383A + 1)
606 #define PREFIX_0F383C (PREFIX_0F383B + 1)
607 #define PREFIX_0F383D (PREFIX_0F383C + 1)
608 #define PREFIX_0F383E (PREFIX_0F383D + 1)
609 #define PREFIX_0F383F (PREFIX_0F383E + 1)
610 #define PREFIX_0F3840 (PREFIX_0F383F + 1)
611 #define PREFIX_0F3841 (PREFIX_0F3840 + 1)
612 #define PREFIX_0F38F0 (PREFIX_0F3841 + 1)
613 #define PREFIX_0F38F1 (PREFIX_0F38F0 + 1)
614 #define PREFIX_0F3A08 (PREFIX_0F38F1 + 1)
615 #define PREFIX_0F3A09 (PREFIX_0F3A08 + 1)
616 #define PREFIX_0F3A0A (PREFIX_0F3A09 + 1)
617 #define PREFIX_0F3A0B (PREFIX_0F3A0A + 1)
618 #define PREFIX_0F3A0C (PREFIX_0F3A0B + 1)
619 #define PREFIX_0F3A0D (PREFIX_0F3A0C + 1)
620 #define PREFIX_0F3A0E (PREFIX_0F3A0D + 1)
621 #define PREFIX_0F3A14 (PREFIX_0F3A0E + 1)
622 #define PREFIX_0F3A15 (PREFIX_0F3A14 + 1)
623 #define PREFIX_0F3A16 (PREFIX_0F3A15 + 1)
624 #define PREFIX_0F3A17 (PREFIX_0F3A16 + 1)
625 #define PREFIX_0F3A20 (PREFIX_0F3A17 + 1)
626 #define PREFIX_0F3A21 (PREFIX_0F3A20 + 1)
627 #define PREFIX_0F3A22 (PREFIX_0F3A21 + 1)
628 #define PREFIX_0F3A40 (PREFIX_0F3A22 + 1)
629 #define PREFIX_0F3A41 (PREFIX_0F3A40 + 1)
630 #define PREFIX_0F3A42 (PREFIX_0F3A41 + 1)
631 #define PREFIX_0F3A60 (PREFIX_0F3A42 + 1)
632 #define PREFIX_0F3A61 (PREFIX_0F3A60 + 1)
633 #define PREFIX_0F3A62 (PREFIX_0F3A61 + 1)
634 #define PREFIX_0F3A63 (PREFIX_0F3A62 + 1)
635 #define PREFIX_0F73_REG_3 (PREFIX_0F3A63 + 1)
636 #define PREFIX_0F73_REG_7 (PREFIX_0F73_REG_3 + 1)
637 #define PREFIX_0FC7_REG_6 (PREFIX_0F73_REG_7 + 1)
640 #define X86_64_07 (X86_64_06 + 1)
641 #define X86_64_0D (X86_64_07 + 1)
642 #define X86_64_16 (X86_64_0D + 1)
643 #define X86_64_17 (X86_64_16 + 1)
644 #define X86_64_1E (X86_64_17 + 1)
645 #define X86_64_1F (X86_64_1E + 1)
646 #define X86_64_27 (X86_64_1F + 1)
647 #define X86_64_2F (X86_64_27 + 1)
648 #define X86_64_37 (X86_64_2F + 1)
649 #define X86_64_3F (X86_64_37 + 1)
650 #define X86_64_60 (X86_64_3F + 1)
651 #define X86_64_61 (X86_64_60 + 1)
652 #define X86_64_62 (X86_64_61 + 1)
653 #define X86_64_63 (X86_64_62 + 1)
654 #define X86_64_6D (X86_64_63 + 1)
655 #define X86_64_6F (X86_64_6D + 1)
656 #define X86_64_9A (X86_64_6F + 1)
657 #define X86_64_C4 (X86_64_9A + 1)
658 #define X86_64_C5 (X86_64_C4 + 1)
659 #define X86_64_CE (X86_64_C5 + 1)
660 #define X86_64_D4 (X86_64_CE + 1)
661 #define X86_64_D5 (X86_64_D4 + 1)
662 #define X86_64_EA (X86_64_D5 + 1)
663 #define X86_64_0F01_REG_0 (X86_64_EA + 1)
664 #define X86_64_0F01_REG_1 (X86_64_0F01_REG_0 + 1)
665 #define X86_64_0F01_REG_2 (X86_64_0F01_REG_1 + 1)
666 #define X86_64_0F01_REG_3 (X86_64_0F01_REG_2 + 1)
668 #define THREE_BYTE_0F24 0
669 #define THREE_BYTE_0F25 (THREE_BYTE_0F24 + 1)
670 #define THREE_BYTE_0F38 (THREE_BYTE_0F25 + 1)
671 #define THREE_BYTE_0F3A (THREE_BYTE_0F38 + 1)
672 #define THREE_BYTE_0F7A (THREE_BYTE_0F3A + 1)
673 #define THREE_BYTE_0F7B (THREE_BYTE_0F7A + 1)
675 typedef void (*op_rtn) (int bytemode, int sizeflag);
686 /* Upper case letters in the instruction names here are macros.
687 'A' => print 'b' if no register operands or suffix_always is true
688 'B' => print 'b' if suffix_always is true
689 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
691 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
692 . suffix_always is true
693 'E' => print 'e' if 32-bit form of jcxz
694 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
695 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
696 'H' => print ",pt" or ",pn" branch hint
697 'I' => honor following macro letter even in Intel mode (implemented only
698 . for some of the macro letters)
700 'K' => print 'd' or 'q' if rex prefix is present.
701 'L' => print 'l' if suffix_always is true
702 'N' => print 'n' if instruction has no wait "prefix"
703 'O' => print 'd' or 'o' (or 'q' in Intel mode)
704 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
705 . or suffix_always is true. print 'q' if rex prefix is present.
706 'Q' => print 'w', 'l' or 'q' if no register operands or suffix_always
708 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
709 'S' => print 'w', 'l' or 'q' if suffix_always is true
710 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
711 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
712 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
713 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
714 'X' => print 's', 'd' depending on data16 prefix (for XMM)
715 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
716 suffix_always is true.
717 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
719 Many of the above letters print nothing in Intel mode. See "putop"
722 Braces '{' and '}', and vertical bars '|', indicate alternative
723 mnemonic strings for AT&T and Intel. */
725 static const struct dis386 dis386[] = {
727 { "addB", { Eb, Gb } },
728 { "addS", { Ev, Gv } },
729 { "addB", { Gb, Eb } },
730 { "addS", { Gv, Ev } },
731 { "addB", { AL, Ib } },
732 { "addS", { eAX, Iv } },
733 { X86_64_TABLE (X86_64_06) },
734 { X86_64_TABLE (X86_64_07) },
736 { "orB", { Eb, Gb } },
737 { "orS", { Ev, Gv } },
738 { "orB", { Gb, Eb } },
739 { "orS", { Gv, Ev } },
740 { "orB", { AL, Ib } },
741 { "orS", { eAX, Iv } },
742 { X86_64_TABLE (X86_64_0D) },
743 { "(bad)", { XX } }, /* 0x0f extended opcode escape */
745 { "adcB", { Eb, Gb } },
746 { "adcS", { Ev, Gv } },
747 { "adcB", { Gb, Eb } },
748 { "adcS", { Gv, Ev } },
749 { "adcB", { AL, Ib } },
750 { "adcS", { eAX, Iv } },
751 { X86_64_TABLE (X86_64_16) },
752 { X86_64_TABLE (X86_64_17) },
754 { "sbbB", { Eb, Gb } },
755 { "sbbS", { Ev, Gv } },
756 { "sbbB", { Gb, Eb } },
757 { "sbbS", { Gv, Ev } },
758 { "sbbB", { AL, Ib } },
759 { "sbbS", { eAX, Iv } },
760 { X86_64_TABLE (X86_64_1E) },
761 { X86_64_TABLE (X86_64_1F) },
763 { "andB", { Eb, Gb } },
764 { "andS", { Ev, Gv } },
765 { "andB", { Gb, Eb } },
766 { "andS", { Gv, Ev } },
767 { "andB", { AL, Ib } },
768 { "andS", { eAX, Iv } },
769 { "(bad)", { XX } }, /* SEG ES prefix */
770 { X86_64_TABLE (X86_64_27) },
772 { "subB", { Eb, Gb } },
773 { "subS", { Ev, Gv } },
774 { "subB", { Gb, Eb } },
775 { "subS", { Gv, Ev } },
776 { "subB", { AL, Ib } },
777 { "subS", { eAX, Iv } },
778 { "(bad)", { XX } }, /* SEG CS prefix */
779 { X86_64_TABLE (X86_64_2F) },
781 { "xorB", { Eb, Gb } },
782 { "xorS", { Ev, Gv } },
783 { "xorB", { Gb, Eb } },
784 { "xorS", { Gv, Ev } },
785 { "xorB", { AL, Ib } },
786 { "xorS", { eAX, Iv } },
787 { "(bad)", { XX } }, /* SEG SS prefix */
788 { X86_64_TABLE (X86_64_37) },
790 { "cmpB", { Eb, Gb } },
791 { "cmpS", { Ev, Gv } },
792 { "cmpB", { Gb, Eb } },
793 { "cmpS", { Gv, Ev } },
794 { "cmpB", { AL, Ib } },
795 { "cmpS", { eAX, Iv } },
796 { "(bad)", { XX } }, /* SEG DS prefix */
797 { X86_64_TABLE (X86_64_3F) },
799 { "inc{S|}", { RMeAX } },
800 { "inc{S|}", { RMeCX } },
801 { "inc{S|}", { RMeDX } },
802 { "inc{S|}", { RMeBX } },
803 { "inc{S|}", { RMeSP } },
804 { "inc{S|}", { RMeBP } },
805 { "inc{S|}", { RMeSI } },
806 { "inc{S|}", { RMeDI } },
808 { "dec{S|}", { RMeAX } },
809 { "dec{S|}", { RMeCX } },
810 { "dec{S|}", { RMeDX } },
811 { "dec{S|}", { RMeBX } },
812 { "dec{S|}", { RMeSP } },
813 { "dec{S|}", { RMeBP } },
814 { "dec{S|}", { RMeSI } },
815 { "dec{S|}", { RMeDI } },
817 { "pushV", { RMrAX } },
818 { "pushV", { RMrCX } },
819 { "pushV", { RMrDX } },
820 { "pushV", { RMrBX } },
821 { "pushV", { RMrSP } },
822 { "pushV", { RMrBP } },
823 { "pushV", { RMrSI } },
824 { "pushV", { RMrDI } },
826 { "popV", { RMrAX } },
827 { "popV", { RMrCX } },
828 { "popV", { RMrDX } },
829 { "popV", { RMrBX } },
830 { "popV", { RMrSP } },
831 { "popV", { RMrBP } },
832 { "popV", { RMrSI } },
833 { "popV", { RMrDI } },
835 { X86_64_TABLE (X86_64_60) },
836 { X86_64_TABLE (X86_64_61) },
837 { X86_64_TABLE (X86_64_62) },
838 { X86_64_TABLE (X86_64_63) },
839 { "(bad)", { XX } }, /* seg fs */
840 { "(bad)", { XX } }, /* seg gs */
841 { "(bad)", { XX } }, /* op size prefix */
842 { "(bad)", { XX } }, /* adr size prefix */
845 { "imulS", { Gv, Ev, Iv } },
846 { "pushT", { sIb } },
847 { "imulS", { Gv, Ev, sIb } },
848 { "ins{b|}", { Ybr, indirDX } },
849 { X86_64_TABLE (X86_64_6D) },
850 { "outs{b|}", { indirDXr, Xb } },
851 { X86_64_TABLE (X86_64_6F) },
853 { "joH", { Jb, XX, cond_jump_flag } },
854 { "jnoH", { Jb, XX, cond_jump_flag } },
855 { "jbH", { Jb, XX, cond_jump_flag } },
856 { "jaeH", { Jb, XX, cond_jump_flag } },
857 { "jeH", { Jb, XX, cond_jump_flag } },
858 { "jneH", { Jb, XX, cond_jump_flag } },
859 { "jbeH", { Jb, XX, cond_jump_flag } },
860 { "jaH", { Jb, XX, cond_jump_flag } },
862 { "jsH", { Jb, XX, cond_jump_flag } },
863 { "jnsH", { Jb, XX, cond_jump_flag } },
864 { "jpH", { Jb, XX, cond_jump_flag } },
865 { "jnpH", { Jb, XX, cond_jump_flag } },
866 { "jlH", { Jb, XX, cond_jump_flag } },
867 { "jgeH", { Jb, XX, cond_jump_flag } },
868 { "jleH", { Jb, XX, cond_jump_flag } },
869 { "jgH", { Jb, XX, cond_jump_flag } },
871 { REG_TABLE (REG_80) },
872 { REG_TABLE (REG_81) },
874 { REG_TABLE (REG_82) },
875 { "testB", { Eb, Gb } },
876 { "testS", { Ev, Gv } },
877 { "xchgB", { Eb, Gb } },
878 { "xchgS", { Ev, Gv } },
880 { "movB", { Eb, Gb } },
881 { "movS", { Ev, Gv } },
882 { "movB", { Gb, Eb } },
883 { "movS", { Gv, Ev } },
884 { "movD", { Sv, Sw } },
885 { MOD_TABLE (MOD_8D) },
886 { "movD", { Sw, Sv } },
887 { REG_TABLE (REG_8F) },
889 { PREFIX_TABLE (PREFIX_90) },
890 { "xchgS", { RMeCX, eAX } },
891 { "xchgS", { RMeDX, eAX } },
892 { "xchgS", { RMeBX, eAX } },
893 { "xchgS", { RMeSP, eAX } },
894 { "xchgS", { RMeBP, eAX } },
895 { "xchgS", { RMeSI, eAX } },
896 { "xchgS", { RMeDI, eAX } },
898 { "cW{t|}R", { XX } },
899 { "cR{t|}O", { XX } },
900 { X86_64_TABLE (X86_64_9A) },
901 { "(bad)", { XX } }, /* fwait */
902 { "pushfT", { XX } },
907 { "movB", { AL, Ob } },
908 { "movS", { eAX, Ov } },
909 { "movB", { Ob, AL } },
910 { "movS", { Ov, eAX } },
911 { "movs{b|}", { Ybr, Xb } },
912 { "movs{R|}", { Yvr, Xv } },
913 { "cmps{b|}", { Xb, Yb } },
914 { "cmps{R|}", { Xv, Yv } },
916 { "testB", { AL, Ib } },
917 { "testS", { eAX, Iv } },
918 { "stosB", { Ybr, AL } },
919 { "stosS", { Yvr, eAX } },
920 { "lodsB", { ALr, Xb } },
921 { "lodsS", { eAXr, Xv } },
922 { "scasB", { AL, Yb } },
923 { "scasS", { eAX, Yv } },
925 { "movB", { RMAL, Ib } },
926 { "movB", { RMCL, Ib } },
927 { "movB", { RMDL, Ib } },
928 { "movB", { RMBL, Ib } },
929 { "movB", { RMAH, Ib } },
930 { "movB", { RMCH, Ib } },
931 { "movB", { RMDH, Ib } },
932 { "movB", { RMBH, Ib } },
934 { "movS", { RMeAX, Iv64 } },
935 { "movS", { RMeCX, Iv64 } },
936 { "movS", { RMeDX, Iv64 } },
937 { "movS", { RMeBX, Iv64 } },
938 { "movS", { RMeSP, Iv64 } },
939 { "movS", { RMeBP, Iv64 } },
940 { "movS", { RMeSI, Iv64 } },
941 { "movS", { RMeDI, Iv64 } },
943 { REG_TABLE (REG_C0) },
944 { REG_TABLE (REG_C1) },
947 { X86_64_TABLE (X86_64_C4) },
948 { X86_64_TABLE (X86_64_C5) },
949 { REG_TABLE (REG_C6) },
950 { REG_TABLE (REG_C7) },
952 { "enterT", { Iw, Ib } },
953 { "leaveT", { XX } },
958 { X86_64_TABLE (X86_64_CE) },
961 { REG_TABLE (REG_D0) },
962 { REG_TABLE (REG_D1) },
963 { REG_TABLE (REG_D2) },
964 { REG_TABLE (REG_D3) },
965 { X86_64_TABLE (X86_64_D4) },
966 { X86_64_TABLE (X86_64_D5) },
968 { "xlat", { DSBX } },
979 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
980 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
981 { "loopFH", { Jb, XX, loop_jcxz_flag } },
982 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
983 { "inB", { AL, Ib } },
984 { "inG", { zAX, Ib } },
985 { "outB", { Ib, AL } },
986 { "outG", { Ib, zAX } },
990 { X86_64_TABLE (X86_64_EA) },
992 { "inB", { AL, indirDX } },
993 { "inG", { zAX, indirDX } },
994 { "outB", { indirDX, AL } },
995 { "outG", { indirDX, zAX } },
997 { "(bad)", { XX } }, /* lock prefix */
999 { "(bad)", { XX } }, /* repne */
1000 { "(bad)", { XX } }, /* repz */
1003 { REG_TABLE (REG_F6) },
1004 { REG_TABLE (REG_F7) },
1012 { REG_TABLE (REG_FE) },
1013 { REG_TABLE (REG_FF) },
1016 static const struct dis386 dis386_twobyte[] = {
1018 { REG_TABLE (REG_0F00 ) },
1019 { REG_TABLE (REG_0F01 ) },
1020 { "larS", { Gv, Ew } },
1021 { "lslS", { Gv, Ew } },
1022 { "(bad)", { XX } },
1023 { "syscall", { XX } },
1025 { "sysretP", { XX } },
1028 { "wbinvd", { XX } },
1029 { "(bad)", { XX } },
1031 { "(bad)", { XX } },
1032 { REG_TABLE (REG_0F0E) },
1033 { "femms", { XX } },
1034 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
1036 { PREFIX_TABLE (PREFIX_0F10) },
1037 { PREFIX_TABLE (PREFIX_0F11) },
1038 { PREFIX_TABLE (PREFIX_0F12) },
1039 { MOD_TABLE (MOD_0F13) },
1040 { "unpcklpX", { XM, EXx } },
1041 { "unpckhpX", { XM, EXx } },
1042 { PREFIX_TABLE (PREFIX_0F16) },
1043 { MOD_TABLE (MOD_0F17) },
1045 { REG_TABLE (REG_0F18) },
1046 { "(bad)", { XX } },
1047 { "(bad)", { XX } },
1048 { "(bad)", { XX } },
1049 { "(bad)", { XX } },
1050 { "(bad)", { XX } },
1051 { "(bad)", { XX } },
1054 { MOD_TABLE (MOD_0F20) },
1055 { MOD_TABLE (MOD_0F21) },
1056 { MOD_TABLE (MOD_0F22) },
1057 { MOD_TABLE (MOD_0F23) },
1058 { MOD_TABLE (MOD_0F24) },
1059 { THREE_BYTE_TABLE (THREE_BYTE_0F25) },
1060 { MOD_TABLE (MOD_0F26) },
1061 { "(bad)", { XX } },
1063 { "movapX", { XM, EXx } },
1064 { "movapX", { EXx, XM } },
1065 { PREFIX_TABLE (PREFIX_0F2A) },
1066 { PREFIX_TABLE (PREFIX_0F2B) },
1067 { PREFIX_TABLE (PREFIX_0F2C) },
1068 { PREFIX_TABLE (PREFIX_0F2D) },
1069 { PREFIX_TABLE (PREFIX_0F2E) },
1070 { PREFIX_TABLE (PREFIX_0F2F) },
1072 { "wrmsr", { XX } },
1073 { "rdtsc", { XX } },
1074 { "rdmsr", { XX } },
1075 { "rdpmc", { XX } },
1076 { "sysenter", { XX } },
1077 { "sysexit", { XX } },
1078 { "(bad)", { XX } },
1079 { "getsec", { XX } },
1081 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
1082 { "(bad)", { XX } },
1083 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
1084 { "(bad)", { XX } },
1085 { "(bad)", { XX } },
1086 { "(bad)", { XX } },
1087 { "(bad)", { XX } },
1088 { "(bad)", { XX } },
1090 { "cmovo", { Gv, Ev } },
1091 { "cmovno", { Gv, Ev } },
1092 { "cmovb", { Gv, Ev } },
1093 { "cmovae", { Gv, Ev } },
1094 { "cmove", { Gv, Ev } },
1095 { "cmovne", { Gv, Ev } },
1096 { "cmovbe", { Gv, Ev } },
1097 { "cmova", { Gv, Ev } },
1099 { "cmovs", { Gv, Ev } },
1100 { "cmovns", { Gv, Ev } },
1101 { "cmovp", { Gv, Ev } },
1102 { "cmovnp", { Gv, Ev } },
1103 { "cmovl", { Gv, Ev } },
1104 { "cmovge", { Gv, Ev } },
1105 { "cmovle", { Gv, Ev } },
1106 { "cmovg", { Gv, Ev } },
1108 { "movmskpX", { Gdq, XS } },
1109 { PREFIX_TABLE (PREFIX_0F51) },
1110 { PREFIX_TABLE (PREFIX_0F52) },
1111 { PREFIX_TABLE (PREFIX_0F53) },
1112 { "andpX", { XM, EXx } },
1113 { "andnpX", { XM, EXx } },
1114 { "orpX", { XM, EXx } },
1115 { "xorpX", { XM, EXx } },
1117 { PREFIX_TABLE (PREFIX_0F58) },
1118 { PREFIX_TABLE (PREFIX_0F59) },
1119 { PREFIX_TABLE (PREFIX_0F5A) },
1120 { PREFIX_TABLE (PREFIX_0F5B) },
1121 { PREFIX_TABLE (PREFIX_0F5C) },
1122 { PREFIX_TABLE (PREFIX_0F5D) },
1123 { PREFIX_TABLE (PREFIX_0F5E) },
1124 { PREFIX_TABLE (PREFIX_0F5F) },
1126 { PREFIX_TABLE (PREFIX_0F60) },
1127 { PREFIX_TABLE (PREFIX_0F61) },
1128 { PREFIX_TABLE (PREFIX_0F62) },
1129 { "packsswb", { MX, EM } },
1130 { "pcmpgtb", { MX, EM } },
1131 { "pcmpgtw", { MX, EM } },
1132 { "pcmpgtd", { MX, EM } },
1133 { "packuswb", { MX, EM } },
1135 { "punpckhbw", { MX, EM } },
1136 { "punpckhwd", { MX, EM } },
1137 { "punpckhdq", { MX, EM } },
1138 { "packssdw", { MX, EM } },
1139 { PREFIX_TABLE (PREFIX_0F6C) },
1140 { PREFIX_TABLE (PREFIX_0F6D) },
1141 { "movK", { MX, Edq } },
1142 { PREFIX_TABLE (PREFIX_0F6F) },
1144 { PREFIX_TABLE (PREFIX_0F70) },
1145 { REG_TABLE (REG_0F71) },
1146 { REG_TABLE (REG_0F72) },
1147 { REG_TABLE (REG_0F73) },
1148 { "pcmpeqb", { MX, EM } },
1149 { "pcmpeqw", { MX, EM } },
1150 { "pcmpeqd", { MX, EM } },
1153 { PREFIX_TABLE (PREFIX_0F78) },
1154 { PREFIX_TABLE (PREFIX_0F79) },
1155 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
1156 { THREE_BYTE_TABLE (THREE_BYTE_0F7B) },
1157 { PREFIX_TABLE (PREFIX_0F7C) },
1158 { PREFIX_TABLE (PREFIX_0F7D) },
1159 { PREFIX_TABLE (PREFIX_0F7E) },
1160 { PREFIX_TABLE (PREFIX_0F7F) },
1162 { "joH", { Jv, XX, cond_jump_flag } },
1163 { "jnoH", { Jv, XX, cond_jump_flag } },
1164 { "jbH", { Jv, XX, cond_jump_flag } },
1165 { "jaeH", { Jv, XX, cond_jump_flag } },
1166 { "jeH", { Jv, XX, cond_jump_flag } },
1167 { "jneH", { Jv, XX, cond_jump_flag } },
1168 { "jbeH", { Jv, XX, cond_jump_flag } },
1169 { "jaH", { Jv, XX, cond_jump_flag } },
1171 { "jsH", { Jv, XX, cond_jump_flag } },
1172 { "jnsH", { Jv, XX, cond_jump_flag } },
1173 { "jpH", { Jv, XX, cond_jump_flag } },
1174 { "jnpH", { Jv, XX, cond_jump_flag } },
1175 { "jlH", { Jv, XX, cond_jump_flag } },
1176 { "jgeH", { Jv, XX, cond_jump_flag } },
1177 { "jleH", { Jv, XX, cond_jump_flag } },
1178 { "jgH", { Jv, XX, cond_jump_flag } },
1181 { "setno", { Eb } },
1183 { "setae", { Eb } },
1185 { "setne", { Eb } },
1186 { "setbe", { Eb } },
1190 { "setns", { Eb } },
1192 { "setnp", { Eb } },
1194 { "setge", { Eb } },
1195 { "setle", { Eb } },
1198 { "pushT", { fs } },
1200 { "cpuid", { XX } },
1201 { "btS", { Ev, Gv } },
1202 { "shldS", { Ev, Gv, Ib } },
1203 { "shldS", { Ev, Gv, CL } },
1204 { REG_TABLE (REG_0FA6) },
1205 { REG_TABLE (REG_0FA7) },
1207 { "pushT", { gs } },
1210 { "btsS", { Ev, Gv } },
1211 { "shrdS", { Ev, Gv, Ib } },
1212 { "shrdS", { Ev, Gv, CL } },
1213 { REG_TABLE (REG_0FAE) },
1214 { "imulS", { Gv, Ev } },
1216 { "cmpxchgB", { Eb, Gb } },
1217 { "cmpxchgS", { Ev, Gv } },
1218 { MOD_TABLE (MOD_0FB2) },
1219 { "btrS", { Ev, Gv } },
1220 { MOD_TABLE (MOD_0FB4) },
1221 { MOD_TABLE (MOD_0FB5) },
1222 { "movz{bR|x}", { Gv, Eb } },
1223 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
1225 { PREFIX_TABLE (PREFIX_0FB8) },
1227 { REG_TABLE (REG_0FBA) },
1228 { "btcS", { Ev, Gv } },
1229 { "bsfS", { Gv, Ev } },
1230 { PREFIX_TABLE (PREFIX_0FBD) },
1231 { "movs{bR|x}", { Gv, Eb } },
1232 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
1234 { "xaddB", { Eb, Gb } },
1235 { "xaddS", { Ev, Gv } },
1236 { PREFIX_TABLE (PREFIX_0FC2) },
1237 { "movntiS", { Ev, Gv } },
1238 { "pinsrw", { MX, Edqw, Ib } },
1239 { "pextrw", { Gdq, MS, Ib } },
1240 { "shufpX", { XM, EXx, Ib } },
1241 { REG_TABLE (REG_0FC7) },
1243 { "bswap", { RMeAX } },
1244 { "bswap", { RMeCX } },
1245 { "bswap", { RMeDX } },
1246 { "bswap", { RMeBX } },
1247 { "bswap", { RMeSP } },
1248 { "bswap", { RMeBP } },
1249 { "bswap", { RMeSI } },
1250 { "bswap", { RMeDI } },
1252 { PREFIX_TABLE (PREFIX_0FD0) },
1253 { "psrlw", { MX, EM } },
1254 { "psrld", { MX, EM } },
1255 { "psrlq", { MX, EM } },
1256 { "paddq", { MX, EM } },
1257 { "pmullw", { MX, EM } },
1258 { PREFIX_TABLE (PREFIX_0FD6) },
1259 { "pmovmskb", { Gdq, MS } },
1261 { "psubusb", { MX, EM } },
1262 { "psubusw", { MX, EM } },
1263 { "pminub", { MX, EM } },
1264 { "pand", { MX, EM } },
1265 { "paddusb", { MX, EM } },
1266 { "paddusw", { MX, EM } },
1267 { "pmaxub", { MX, EM } },
1268 { "pandn", { MX, EM } },
1270 { "pavgb", { MX, EM } },
1271 { "psraw", { MX, EM } },
1272 { "psrad", { MX, EM } },
1273 { "pavgw", { MX, EM } },
1274 { "pmulhuw", { MX, EM } },
1275 { "pmulhw", { MX, EM } },
1276 { PREFIX_TABLE (PREFIX_0FE6) },
1277 { PREFIX_TABLE (PREFIX_0FE7) },
1279 { "psubsb", { MX, EM } },
1280 { "psubsw", { MX, EM } },
1281 { "pminsw", { MX, EM } },
1282 { "por", { MX, EM } },
1283 { "paddsb", { MX, EM } },
1284 { "paddsw", { MX, EM } },
1285 { "pmaxsw", { MX, EM } },
1286 { "pxor", { MX, EM } },
1288 { PREFIX_TABLE (PREFIX_0FF0) },
1289 { "psllw", { MX, EM } },
1290 { "pslld", { MX, EM } },
1291 { "psllq", { MX, EM } },
1292 { "pmuludq", { MX, EM } },
1293 { "pmaddwd", { MX, EM } },
1294 { "psadbw", { MX, EM } },
1295 { PREFIX_TABLE (PREFIX_0FF7) },
1297 { "psubb", { MX, EM } },
1298 { "psubw", { MX, EM } },
1299 { "psubd", { MX, EM } },
1300 { "psubq", { MX, EM } },
1301 { "paddb", { MX, EM } },
1302 { "paddw", { MX, EM } },
1303 { "paddd", { MX, EM } },
1304 { "(bad)", { XX } },
1307 static const unsigned char onebyte_has_modrm[256] = {
1308 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1309 /* ------------------------------- */
1310 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1311 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1312 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1313 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1314 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1315 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1316 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1317 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1318 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1319 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1320 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1321 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1322 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1323 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1324 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1325 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1326 /* ------------------------------- */
1327 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1330 static const unsigned char twobyte_has_modrm[256] = {
1331 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1332 /* ------------------------------- */
1333 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1334 /* 10 */ 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,1, /* 1f */
1335 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1336 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1337 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1338 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1339 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1340 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1341 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1342 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1343 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1344 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1345 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1346 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1347 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1348 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1349 /* ------------------------------- */
1350 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1353 static char obuf[100];
1355 static char scratchbuf[100];
1356 static unsigned char *start_codep;
1357 static unsigned char *insn_codep;
1358 static unsigned char *codep;
1359 static const char *lock_prefix;
1360 static const char *data_prefix;
1361 static const char *addr_prefix;
1362 static const char *repz_prefix;
1363 static const char *repnz_prefix;
1364 static disassemble_info *the_info;
1372 static unsigned char need_modrm;
1374 /* If we are accessing mod/rm/reg without need_modrm set, then the
1375 values are stale. Hitting this abort likely indicates that you
1376 need to update onebyte_has_modrm or twobyte_has_modrm. */
1377 #define MODRM_CHECK if (!need_modrm) abort ()
1379 static const char **names64;
1380 static const char **names32;
1381 static const char **names16;
1382 static const char **names8;
1383 static const char **names8rex;
1384 static const char **names_seg;
1385 static const char *index64;
1386 static const char *index32;
1387 static const char **index16;
1389 static const char *intel_names64[] = {
1390 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
1391 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
1393 static const char *intel_names32[] = {
1394 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
1395 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
1397 static const char *intel_names16[] = {
1398 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
1399 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
1401 static const char *intel_names8[] = {
1402 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
1404 static const char *intel_names8rex[] = {
1405 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
1406 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
1408 static const char *intel_names_seg[] = {
1409 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
1411 static const char *intel_index64 = "riz";
1412 static const char *intel_index32 = "eiz";
1413 static const char *intel_index16[] = {
1414 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
1417 static const char *att_names64[] = {
1418 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
1419 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
1421 static const char *att_names32[] = {
1422 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
1423 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
1425 static const char *att_names16[] = {
1426 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
1427 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
1429 static const char *att_names8[] = {
1430 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
1432 static const char *att_names8rex[] = {
1433 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
1434 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
1436 static const char *att_names_seg[] = {
1437 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
1439 static const char *att_index64 = "%riz";
1440 static const char *att_index32 = "%eiz";
1441 static const char *att_index16[] = {
1442 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
1445 static const struct dis386 reg_table[][8] = {
1448 { "addA", { Eb, Ib } },
1449 { "orA", { Eb, Ib } },
1450 { "adcA", { Eb, Ib } },
1451 { "sbbA", { Eb, Ib } },
1452 { "andA", { Eb, Ib } },
1453 { "subA", { Eb, Ib } },
1454 { "xorA", { Eb, Ib } },
1455 { "cmpA", { Eb, Ib } },
1459 { "addQ", { Ev, Iv } },
1460 { "orQ", { Ev, Iv } },
1461 { "adcQ", { Ev, Iv } },
1462 { "sbbQ", { Ev, Iv } },
1463 { "andQ", { Ev, Iv } },
1464 { "subQ", { Ev, Iv } },
1465 { "xorQ", { Ev, Iv } },
1466 { "cmpQ", { Ev, Iv } },
1470 { "addQ", { Ev, sIb } },
1471 { "orQ", { Ev, sIb } },
1472 { "adcQ", { Ev, sIb } },
1473 { "sbbQ", { Ev, sIb } },
1474 { "andQ", { Ev, sIb } },
1475 { "subQ", { Ev, sIb } },
1476 { "xorQ", { Ev, sIb } },
1477 { "cmpQ", { Ev, sIb } },
1481 { "popU", { stackEv } },
1482 { "(bad)", { XX } },
1483 { "(bad)", { XX } },
1484 { "(bad)", { XX } },
1485 { "(bad)", { XX } },
1486 { "(bad)", { XX } },
1487 { "(bad)", { XX } },
1488 { "(bad)", { XX } },
1492 { "rolA", { Eb, Ib } },
1493 { "rorA", { Eb, Ib } },
1494 { "rclA", { Eb, Ib } },
1495 { "rcrA", { Eb, Ib } },
1496 { "shlA", { Eb, Ib } },
1497 { "shrA", { Eb, Ib } },
1498 { "(bad)", { XX } },
1499 { "sarA", { Eb, Ib } },
1503 { "rolQ", { Ev, Ib } },
1504 { "rorQ", { Ev, Ib } },
1505 { "rclQ", { Ev, Ib } },
1506 { "rcrQ", { Ev, Ib } },
1507 { "shlQ", { Ev, Ib } },
1508 { "shrQ", { Ev, Ib } },
1509 { "(bad)", { XX } },
1510 { "sarQ", { Ev, Ib } },
1514 { "movA", { Eb, Ib } },
1515 { "(bad)", { XX } },
1516 { "(bad)", { XX } },
1517 { "(bad)", { XX } },
1518 { "(bad)", { XX } },
1519 { "(bad)", { XX } },
1520 { "(bad)", { XX } },
1521 { "(bad)", { XX } },
1525 { "movQ", { Ev, Iv } },
1526 { "(bad)", { XX } },
1527 { "(bad)", { XX } },
1528 { "(bad)", { XX } },
1529 { "(bad)", { XX } },
1530 { "(bad)", { XX } },
1531 { "(bad)", { XX } },
1532 { "(bad)", { XX } },
1536 { "rolA", { Eb, I1 } },
1537 { "rorA", { Eb, I1 } },
1538 { "rclA", { Eb, I1 } },
1539 { "rcrA", { Eb, I1 } },
1540 { "shlA", { Eb, I1 } },
1541 { "shrA", { Eb, I1 } },
1542 { "(bad)", { XX } },
1543 { "sarA", { Eb, I1 } },
1547 { "rolQ", { Ev, I1 } },
1548 { "rorQ", { Ev, I1 } },
1549 { "rclQ", { Ev, I1 } },
1550 { "rcrQ", { Ev, I1 } },
1551 { "shlQ", { Ev, I1 } },
1552 { "shrQ", { Ev, I1 } },
1553 { "(bad)", { XX } },
1554 { "sarQ", { Ev, I1 } },
1558 { "rolA", { Eb, CL } },
1559 { "rorA", { Eb, CL } },
1560 { "rclA", { Eb, CL } },
1561 { "rcrA", { Eb, CL } },
1562 { "shlA", { Eb, CL } },
1563 { "shrA", { Eb, CL } },
1564 { "(bad)", { XX } },
1565 { "sarA", { Eb, CL } },
1569 { "rolQ", { Ev, CL } },
1570 { "rorQ", { Ev, CL } },
1571 { "rclQ", { Ev, CL } },
1572 { "rcrQ", { Ev, CL } },
1573 { "shlQ", { Ev, CL } },
1574 { "shrQ", { Ev, CL } },
1575 { "(bad)", { XX } },
1576 { "sarQ", { Ev, CL } },
1580 { "testA", { Eb, Ib } },
1581 { "(bad)", { XX } },
1584 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
1585 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
1586 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
1587 { "idivA", { Eb } }, /* and idiv for consistency. */
1591 { "testQ", { Ev, Iv } },
1592 { "(bad)", { XX } },
1595 { "mulQ", { Ev } }, /* Don't print the implicit register. */
1596 { "imulQ", { Ev } },
1598 { "idivQ", { Ev } },
1604 { "(bad)", { XX } },
1605 { "(bad)", { XX } },
1606 { "(bad)", { XX } },
1607 { "(bad)", { XX } },
1608 { "(bad)", { XX } },
1609 { "(bad)", { XX } },
1615 { "callT", { indirEv } },
1616 { "JcallT", { indirEp } },
1617 { "jmpT", { indirEv } },
1618 { "JjmpT", { indirEp } },
1619 { "pushU", { stackEv } },
1620 { "(bad)", { XX } },
1624 { "sldtD", { Sv } },
1630 { "(bad)", { XX } },
1631 { "(bad)", { XX } },
1635 { MOD_TABLE (MOD_0F01_REG_0) },
1636 { MOD_TABLE (MOD_0F01_REG_1) },
1637 { MOD_TABLE (MOD_0F01_REG_2) },
1638 { MOD_TABLE (MOD_0F01_REG_3) },
1639 { "smswD", { Sv } },
1640 { "(bad)", { XX } },
1642 { MOD_TABLE (MOD_0F01_REG_7) },
1646 { "prefetch", { Eb } },
1647 { "prefetchw", { Eb } },
1648 { "(bad)", { XX } },
1649 { "(bad)", { XX } },
1650 { "(bad)", { XX } },
1651 { "(bad)", { XX } },
1652 { "(bad)", { XX } },
1653 { "(bad)", { XX } },
1657 { MOD_TABLE (MOD_0F18_REG_0) },
1658 { MOD_TABLE (MOD_0F18_REG_1) },
1659 { MOD_TABLE (MOD_0F18_REG_2) },
1660 { MOD_TABLE (MOD_0F18_REG_3) },
1661 { "(bad)", { XX } },
1662 { "(bad)", { XX } },
1663 { "(bad)", { XX } },
1664 { "(bad)", { XX } },
1668 { "(bad)", { XX } },
1669 { "(bad)", { XX } },
1670 { MOD_TABLE (MOD_0F71_REG_2) },
1671 { "(bad)", { XX } },
1672 { MOD_TABLE (MOD_0F71_REG_4) },
1673 { "(bad)", { XX } },
1674 { MOD_TABLE (MOD_0F71_REG_6) },
1675 { "(bad)", { XX } },
1679 { "(bad)", { XX } },
1680 { "(bad)", { XX } },
1681 { MOD_TABLE (MOD_0F72_REG_2) },
1682 { "(bad)", { XX } },
1683 { MOD_TABLE (MOD_0F72_REG_4) },
1684 { "(bad)", { XX } },
1685 { MOD_TABLE (MOD_0F72_REG_6) },
1686 { "(bad)", { XX } },
1690 { "(bad)", { XX } },
1691 { "(bad)", { XX } },
1692 { MOD_TABLE (MOD_0F73_REG_2) },
1693 { MOD_TABLE (MOD_0F73_REG_3) },
1694 { "(bad)", { XX } },
1695 { "(bad)", { XX } },
1696 { MOD_TABLE (MOD_0F73_REG_6) },
1697 { MOD_TABLE (MOD_0F73_REG_7) },
1701 { "montmul", { { OP_0f07, 0 } } },
1702 { "xsha1", { { OP_0f07, 0 } } },
1703 { "xsha256", { { OP_0f07, 0 } } },
1704 { "(bad)", { { OP_0f07, 0 } } },
1705 { "(bad)", { { OP_0f07, 0 } } },
1706 { "(bad)", { { OP_0f07, 0 } } },
1707 { "(bad)", { { OP_0f07, 0 } } },
1708 { "(bad)", { { OP_0f07, 0 } } },
1712 { "xstore-rng", { { OP_0f07, 0 } } },
1713 { "xcrypt-ecb", { { OP_0f07, 0 } } },
1714 { "xcrypt-cbc", { { OP_0f07, 0 } } },
1715 { "xcrypt-ctr", { { OP_0f07, 0 } } },
1716 { "xcrypt-cfb", { { OP_0f07, 0 } } },
1717 { "xcrypt-ofb", { { OP_0f07, 0 } } },
1718 { "(bad)", { { OP_0f07, 0 } } },
1719 { "(bad)", { { OP_0f07, 0 } } },
1723 { MOD_TABLE (MOD_0FAE_REG_0) },
1724 { MOD_TABLE (MOD_0FAE_REG_1) },
1725 { MOD_TABLE (MOD_0FAE_REG_2) },
1726 { MOD_TABLE (MOD_0FAE_REG_3) },
1727 { "(bad)", { XX } },
1728 { MOD_TABLE (MOD_0FAE_REG_5) },
1729 { MOD_TABLE (MOD_0FAE_REG_6) },
1730 { MOD_TABLE (MOD_0FAE_REG_7) },
1734 { "(bad)", { XX } },
1735 { "(bad)", { XX } },
1736 { "(bad)", { XX } },
1737 { "(bad)", { XX } },
1738 { "btQ", { Ev, Ib } },
1739 { "btsQ", { Ev, Ib } },
1740 { "btrQ", { Ev, Ib } },
1741 { "btcQ", { Ev, Ib } },
1745 { "(bad)", { XX } },
1746 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
1747 { "(bad)", { XX } },
1748 { "(bad)", { XX } },
1749 { "(bad)", { XX } },
1750 { "(bad)", { XX } },
1751 { MOD_TABLE (MOD_0FC7_REG_6) },
1752 { MOD_TABLE (MOD_0FC7_REG_7) },
1756 static const struct dis386 prefix_table[][4] = {
1759 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
1760 { "pause", { XX } },
1761 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
1762 { "(bad)", { XX } },
1767 { "movups", { XM, EXx } },
1768 { "movss", { XM, EXd } },
1769 { "movupd", { XM, EXx } },
1770 { "movsd", { XM, EXq } },
1775 { "movups", { EXx, XM } },
1776 { "movss", { EXd, XM } },
1777 { "movupd", { EXx, XM } },
1778 { "movsd", { EXq, XM } },
1783 { MOD_TABLE (MOD_0F12_PREFIX_0) },
1784 { "movsldup", { XM, EXx } },
1785 { "movlpd", { XM, EXq } },
1786 { "movddup", { XM, EXq } },
1791 { MOD_TABLE (MOD_0F16_PREFIX_0) },
1792 { "movshdup", { XM, EXx } },
1793 { "movhpd", { XM, EXq } },
1794 { "(bad)", { XX } },
1799 { "cvtpi2ps", { XM, EMCq } },
1800 { "cvtsi2ssY", { XM, Ev } },
1801 { "cvtpi2pd", { XM, EMCq } },
1802 { "cvtsi2sdY", { XM, Ev } },
1807 {"movntps", { Ev, XM } },
1808 {"movntss", { Ed, XM } },
1809 {"movntpd", { Ev, XM } },
1810 {"movntsd", { Eq, XM } },
1815 { "cvttps2pi", { MXC, EXq } },
1816 { "cvttss2siY", { Gv, EXd } },
1817 { "cvttpd2pi", { MXC, EXx } },
1818 { "cvttsd2siY", { Gv, EXq } },
1823 { "cvtps2pi", { MXC, EXq } },
1824 { "cvtss2siY", { Gv, EXd } },
1825 { "cvtpd2pi", { MXC, EXx } },
1826 { "cvtsd2siY", { Gv, EXq } },
1831 { "ucomiss",{ XM, EXd } },
1832 { "(bad)", { XX } },
1833 { "ucomisd",{ XM, EXq } },
1834 { "(bad)", { XX } },
1839 { "comiss", { XM, EXd } },
1840 { "(bad)", { XX } },
1841 { "comisd", { XM, EXq } },
1842 { "(bad)", { XX } },
1847 { "sqrtps", { XM, EXx } },
1848 { "sqrtss", { XM, EXd } },
1849 { "sqrtpd", { XM, EXx } },
1850 { "sqrtsd", { XM, EXq } },
1855 { "rsqrtps",{ XM, EXx } },
1856 { "rsqrtss",{ XM, EXd } },
1857 { "(bad)", { XX } },
1858 { "(bad)", { XX } },
1863 { "rcpps", { XM, EXx } },
1864 { "rcpss", { XM, EXd } },
1865 { "(bad)", { XX } },
1866 { "(bad)", { XX } },
1871 { "addps", { XM, EXx } },
1872 { "addss", { XM, EXd } },
1873 { "addpd", { XM, EXx } },
1874 { "addsd", { XM, EXq } },
1879 { "mulps", { XM, EXx } },
1880 { "mulss", { XM, EXd } },
1881 { "mulpd", { XM, EXx } },
1882 { "mulsd", { XM, EXq } },
1887 { "cvtps2pd", { XM, EXq } },
1888 { "cvtss2sd", { XM, EXd } },
1889 { "cvtpd2ps", { XM, EXx } },
1890 { "cvtsd2ss", { XM, EXq } },
1895 { "cvtdq2ps", { XM, EXx } },
1896 { "cvttps2dq", { XM, EXx } },
1897 { "cvtps2dq", { XM, EXx } },
1898 { "(bad)", { XX } },
1903 { "subps", { XM, EXx } },
1904 { "subss", { XM, EXd } },
1905 { "subpd", { XM, EXx } },
1906 { "subsd", { XM, EXq } },
1911 { "minps", { XM, EXx } },
1912 { "minss", { XM, EXd } },
1913 { "minpd", { XM, EXx } },
1914 { "minsd", { XM, EXq } },
1919 { "divps", { XM, EXx } },
1920 { "divss", { XM, EXd } },
1921 { "divpd", { XM, EXx } },
1922 { "divsd", { XM, EXq } },
1927 { "maxps", { XM, EXx } },
1928 { "maxss", { XM, EXd } },
1929 { "maxpd", { XM, EXx } },
1930 { "maxsd", { XM, EXq } },
1935 { "punpcklbw",{ MX, EMd } },
1936 { "(bad)", { XX } },
1937 { "punpcklbw",{ MX, EMx } },
1938 { "(bad)", { XX } },
1943 { "punpcklwd",{ MX, EMd } },
1944 { "(bad)", { XX } },
1945 { "punpcklwd",{ MX, EMx } },
1946 { "(bad)", { XX } },
1951 { "punpckldq",{ MX, EMd } },
1952 { "(bad)", { XX } },
1953 { "punpckldq",{ MX, EMx } },
1954 { "(bad)", { XX } },
1959 { "(bad)", { XX } },
1960 { "(bad)", { XX } },
1961 { "punpcklqdq", { XM, EXx } },
1962 { "(bad)", { XX } },
1967 { "(bad)", { XX } },
1968 { "(bad)", { XX } },
1969 { "punpckhqdq", { XM, EXx } },
1970 { "(bad)", { XX } },
1975 { "movq", { MX, EM } },
1976 { "movdqu", { XM, EXx } },
1977 { "movdqa", { XM, EXx } },
1978 { "(bad)", { XX } },
1983 { "pshufw", { MX, EM, Ib } },
1984 { "pshufhw",{ XM, EXx, Ib } },
1985 { "pshufd", { XM, EXx, Ib } },
1986 { "pshuflw",{ XM, EXx, Ib } },
1991 {"vmread", { Em, Gm } },
1993 {"extrq", { XS, Ib, Ib } },
1994 {"insertq", { XM, XS, Ib, Ib } },
1999 {"vmwrite", { Gm, Em } },
2001 {"extrq", { XM, XS } },
2002 {"insertq", { XM, XS } },
2007 { "(bad)", { XX } },
2008 { "(bad)", { XX } },
2009 { "haddpd", { XM, EXx } },
2010 { "haddps", { XM, EXx } },
2015 { "(bad)", { XX } },
2016 { "(bad)", { XX } },
2017 { "hsubpd", { XM, EXx } },
2018 { "hsubps", { XM, EXx } },
2023 { "movK", { Edq, MX } },
2024 { "movq", { XM, EXq } },
2025 { "movK", { Edq, XM } },
2026 { "(bad)", { XX } },
2031 { "movq", { EM, MX } },
2032 { "movdqu", { EXx, XM } },
2033 { "movdqa", { EXx, XM } },
2034 { "(bad)", { XX } },
2039 { "(bad)", { XX } },
2040 { "popcntS", { Gv, Ev } },
2041 { "(bad)", { XX } },
2042 { "(bad)", { XX } },
2047 { "bsrS", { Gv, Ev } },
2048 { "lzcntS", { Gv, Ev } },
2049 { "bsrS", { Gv, Ev } },
2050 { "(bad)", { XX } },
2055 { "", { XM, EXx, OPSIMD } }, /* See OP_SIMD_SUFFIX. */
2056 { "", { XM, EXd, OPSIMD } },
2057 { "", { XM, EXx, OPSIMD } },
2058 { "", { XM, EXq, OPSIMD } },
2063 { "(bad)", { XX } },
2064 { "(bad)", { XX } },
2065 { "addsubpd", { XM, EXx } },
2066 { "addsubps", { XM, EXx } },
2071 { "(bad)", { XX } },
2072 { "movq2dq",{ XM, MS } },
2073 { "movq", { EXq, XM } },
2074 { "movdq2q",{ MX, XS } },
2079 { "(bad)", { XX } },
2080 { "cvtdq2pd", { XM, EXq } },
2081 { "cvttpd2dq", { XM, EXx } },
2082 { "cvtpd2dq", { XM, EXx } },
2087 { "movntq", { EM, MX } },
2088 { "(bad)", { XX } },
2089 { "movntdq",{ EM, XM } },
2090 { "(bad)", { XX } },
2095 { "(bad)", { XX } },
2096 { "(bad)", { XX } },
2097 { "(bad)", { XX } },
2098 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
2103 { "maskmovq", { MX, MS } },
2104 { "(bad)", { XX } },
2105 { "maskmovdqu", { XM, XS } },
2106 { "(bad)", { XX } },
2111 { "(bad)", { XX } },
2112 { "(bad)", { XX } },
2113 { "pblendvb", {XM, EXx, XMM0 } },
2114 { "(bad)", { XX } },
2119 { "(bad)", { XX } },
2120 { "(bad)", { XX } },
2121 { "blendvps", {XM, EXx, XMM0 } },
2122 { "(bad)", { XX } },
2127 { "(bad)", { XX } },
2128 { "(bad)", { XX } },
2129 { "blendvpd", { XM, EXx, XMM0 } },
2130 { "(bad)", { XX } },
2135 { "(bad)", { XX } },
2136 { "(bad)", { XX } },
2137 { "ptest", { XM, EXx } },
2138 { "(bad)", { XX } },
2143 { "(bad)", { XX } },
2144 { "(bad)", { XX } },
2145 { "pmovsxbw", { XM, EXq } },
2146 { "(bad)", { XX } },
2151 { "(bad)", { XX } },
2152 { "(bad)", { XX } },
2153 { "pmovsxbd", { XM, EXd } },
2154 { "(bad)", { XX } },
2159 { "(bad)", { XX } },
2160 { "(bad)", { XX } },
2161 { "pmovsxbq", { XM, EXw } },
2162 { "(bad)", { XX } },
2167 { "(bad)", { XX } },
2168 { "(bad)", { XX } },
2169 { "pmovsxwd", { XM, EXq } },
2170 { "(bad)", { XX } },
2175 { "(bad)", { XX } },
2176 { "(bad)", { XX } },
2177 { "pmovsxwq", { XM, EXd } },
2178 { "(bad)", { XX } },
2183 { "(bad)", { XX } },
2184 { "(bad)", { XX } },
2185 { "pmovsxdq", { XM, EXq } },
2186 { "(bad)", { XX } },
2191 { "(bad)", { XX } },
2192 { "(bad)", { XX } },
2193 { "pmuldq", { XM, EXx } },
2194 { "(bad)", { XX } },
2199 { "(bad)", { XX } },
2200 { "(bad)", { XX } },
2201 { "pcmpeqq", { XM, EXx } },
2202 { "(bad)", { XX } },
2207 { "(bad)", { XX } },
2208 { "(bad)", { XX } },
2209 { "movntdqa", { XM, EM } },
2210 { "(bad)", { XX } },
2215 { "(bad)", { XX } },
2216 { "(bad)", { XX } },
2217 { "packusdw", { XM, EXx } },
2218 { "(bad)", { XX } },
2223 { "(bad)", { XX } },
2224 { "(bad)", { XX } },
2225 { "pmovzxbw", { XM, EXq } },
2226 { "(bad)", { XX } },
2231 { "(bad)", { XX } },
2232 { "(bad)", { XX } },
2233 { "pmovzxbd", { XM, EXd } },
2234 { "(bad)", { XX } },
2239 { "(bad)", { XX } },
2240 { "(bad)", { XX } },
2241 { "pmovzxbq", { XM, EXw } },
2242 { "(bad)", { XX } },
2247 { "(bad)", { XX } },
2248 { "(bad)", { XX } },
2249 { "pmovzxwd", { XM, EXq } },
2250 { "(bad)", { XX } },
2255 { "(bad)", { XX } },
2256 { "(bad)", { XX } },
2257 { "pmovzxwq", { XM, EXd } },
2258 { "(bad)", { XX } },
2263 { "(bad)", { XX } },
2264 { "(bad)", { XX } },
2265 { "pmovzxdq", { XM, EXq } },
2266 { "(bad)", { XX } },
2271 { "(bad)", { XX } },
2272 { "(bad)", { XX } },
2273 { "pcmpgtq", { XM, EXx } },
2274 { "(bad)", { XX } },
2279 { "(bad)", { XX } },
2280 { "(bad)", { XX } },
2281 { "pminsb", { XM, EXx } },
2282 { "(bad)", { XX } },
2287 { "(bad)", { XX } },
2288 { "(bad)", { XX } },
2289 { "pminsd", { XM, EXx } },
2290 { "(bad)", { XX } },
2295 { "(bad)", { XX } },
2296 { "(bad)", { XX } },
2297 { "pminuw", { XM, EXx } },
2298 { "(bad)", { XX } },
2303 { "(bad)", { XX } },
2304 { "(bad)", { XX } },
2305 { "pminud", { XM, EXx } },
2306 { "(bad)", { XX } },
2311 { "(bad)", { XX } },
2312 { "(bad)", { XX } },
2313 { "pmaxsb", { XM, EXx } },
2314 { "(bad)", { XX } },
2319 { "(bad)", { XX } },
2320 { "(bad)", { XX } },
2321 { "pmaxsd", { XM, EXx } },
2322 { "(bad)", { XX } },
2327 { "(bad)", { XX } },
2328 { "(bad)", { XX } },
2329 { "pmaxuw", { XM, EXx } },
2330 { "(bad)", { XX } },
2335 { "(bad)", { XX } },
2336 { "(bad)", { XX } },
2337 { "pmaxud", { XM, EXx } },
2338 { "(bad)", { XX } },
2343 { "(bad)", { XX } },
2344 { "(bad)", { XX } },
2345 { "pmulld", { XM, EXx } },
2346 { "(bad)", { XX } },
2351 { "(bad)", { XX } },
2352 { "(bad)", { XX } },
2353 { "phminposuw", { XM, EXx } },
2354 { "(bad)", { XX } },
2359 { "(bad)", { XX } },
2360 { "(bad)", { XX } },
2361 { "(bad)", { XX } },
2362 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
2367 { "(bad)", { XX } },
2368 { "(bad)", { XX } },
2369 { "(bad)", { XX } },
2370 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
2375 { "(bad)", { XX } },
2376 { "(bad)", { XX } },
2377 { "roundps", { XM, EXx, Ib } },
2378 { "(bad)", { XX } },
2383 { "(bad)", { XX } },
2384 { "(bad)", { XX } },
2385 { "roundpd", { XM, EXx, Ib } },
2386 { "(bad)", { XX } },
2391 { "(bad)", { XX } },
2392 { "(bad)", { XX } },
2393 { "roundss", { XM, EXd, Ib } },
2394 { "(bad)", { XX } },
2399 { "(bad)", { XX } },
2400 { "(bad)", { XX } },
2401 { "roundsd", { XM, EXq, Ib } },
2402 { "(bad)", { XX } },
2407 { "(bad)", { XX } },
2408 { "(bad)", { XX } },
2409 { "blendps", { XM, EXx, Ib } },
2410 { "(bad)", { XX } },
2415 { "(bad)", { XX } },
2416 { "(bad)", { XX } },
2417 { "blendpd", { XM, EXx, Ib } },
2418 { "(bad)", { XX } },
2423 { "(bad)", { XX } },
2424 { "(bad)", { XX } },
2425 { "pblendw", { XM, EXx, Ib } },
2426 { "(bad)", { XX } },
2431 { "(bad)", { XX } },
2432 { "(bad)", { XX } },
2433 { "pextrb", { Edqb, XM, Ib } },
2434 { "(bad)", { XX } },
2439 { "(bad)", { XX } },
2440 { "(bad)", { XX } },
2441 { "pextrw", { Edqw, XM, Ib } },
2442 { "(bad)", { XX } },
2447 { "(bad)", { XX } },
2448 { "(bad)", { XX } },
2449 { "pextrK", { Edq, XM, Ib } },
2450 { "(bad)", { XX } },
2455 { "(bad)", { XX } },
2456 { "(bad)", { XX } },
2457 { "extractps", { Edqd, XM, Ib } },
2458 { "(bad)", { XX } },
2463 { "(bad)", { XX } },
2464 { "(bad)", { XX } },
2465 { "pinsrb", { XM, Edqb, Ib } },
2466 { "(bad)", { XX } },
2471 { "(bad)", { XX } },
2472 { "(bad)", { XX } },
2473 { "insertps", { XM, EXd, Ib } },
2474 { "(bad)", { XX } },
2479 { "(bad)", { XX } },
2480 { "(bad)", { XX } },
2481 { "pinsrK", { XM, Edq, Ib } },
2482 { "(bad)", { XX } },
2487 { "(bad)", { XX } },
2488 { "(bad)", { XX } },
2489 { "dpps", { XM, EXx, Ib } },
2490 { "(bad)", { XX } },
2495 { "(bad)", { XX } },
2496 { "(bad)", { XX } },
2497 { "dppd", { XM, EXx, Ib } },
2498 { "(bad)", { XX } },
2503 { "(bad)", { XX } },
2504 { "(bad)", { XX } },
2505 { "mpsadbw", { XM, EXx, Ib } },
2506 { "(bad)", { XX } },
2511 { "(bad)", { XX } },
2512 { "(bad)", { XX } },
2513 { "pcmpestrm", { XM, EXx, Ib } },
2514 { "(bad)", { XX } },
2519 { "(bad)", { XX } },
2520 { "(bad)", { XX } },
2521 { "pcmpestri", { XM, EXx, Ib } },
2522 { "(bad)", { XX } },
2527 { "(bad)", { XX } },
2528 { "(bad)", { XX } },
2529 { "pcmpistrm", { XM, EXx, Ib } },
2530 { "(bad)", { XX } },
2535 { "(bad)", { XX } },
2536 { "(bad)", { XX } },
2537 { "pcmpistri", { XM, EXx, Ib } },
2538 { "(bad)", { XX } },
2541 /* PREFIX_0F73_REG_3 */
2543 { "(bad)", { XX } },
2544 { "(bad)", { XX } },
2545 { "psrldq", { MS, Ib } },
2546 { "(bad)", { XX } },
2549 /* PREFIX_0F73_REG_7 */
2551 { "(bad)", { XX } },
2552 { "(bad)", { XX } },
2553 { "pslldq", { MS, Ib } },
2554 { "(bad)", { XX } },
2557 /* PREFIX_0FC7_REG_6 */
2559 { "vmptrld",{ Mq } },
2560 { "vmxon", { Mq } },
2561 { "vmclear",{ Mq } },
2562 { "(bad)", { XX } },
2566 static const struct dis386 x86_64_table[][2] = {
2569 { "push{T|}", { es } },
2570 { "(bad)", { XX } },
2575 { "pop{T|}", { es } },
2576 { "(bad)", { XX } },
2581 { "push{T|}", { cs } },
2582 { "(bad)", { XX } },
2587 { "push{T|}", { ss } },
2588 { "(bad)", { XX } },
2593 { "pop{T|}", { ss } },
2594 { "(bad)", { XX } },
2599 { "push{T|}", { ds } },
2600 { "(bad)", { XX } },
2605 { "pop{T|}", { ds } },
2606 { "(bad)", { XX } },
2612 { "(bad)", { XX } },
2618 { "(bad)", { XX } },
2624 { "(bad)", { XX } },
2630 { "(bad)", { XX } },
2635 { "pusha{P|}", { XX } },
2636 { "(bad)", { XX } },
2641 { "popa{P|}", { XX } },
2642 { "(bad)", { XX } },
2647 { MOD_TABLE (MOD_62_32BIT) },
2648 { "(bad)", { XX } },
2653 { "arpl", { Ew, Gw } },
2654 { "movs{lq|xd}", { Gv, Ed } },
2659 { "ins{R|}", { Yzr, indirDX } },
2660 { "ins{G|}", { Yzr, indirDX } },
2665 { "outs{R|}", { indirDXr, Xz } },
2666 { "outs{G|}", { indirDXr, Xz } },
2671 { "Jcall{T|}", { Ap } },
2672 { "(bad)", { XX } },
2677 { MOD_TABLE (MOD_C4_32BIT) },
2678 { "(bad)", { XX } },
2683 { MOD_TABLE (MOD_C5_32BIT) },
2684 { "(bad)", { XX } },
2690 { "(bad)", { XX } },
2696 { "(bad)", { XX } },
2702 { "(bad)", { XX } },
2707 { "Jjmp{T|}", { Ap } },
2708 { "(bad)", { XX } },
2711 /* X86_64_0F01_REG_0 */
2713 { "sgdt{Q|IQ}", { M } },
2717 /* X86_64_0F01_REG_1 */
2719 { "sidt{Q|IQ}", { M } },
2723 /* X86_64_0F01_REG_2 */
2725 { "lgdt{Q|Q}", { M } },
2729 /* X86_64_0F01_REG_3 */
2731 { "lidt{Q|Q}", { M } },
2736 static const struct dis386 three_byte_table[][256] = {
2737 /* THREE_BYTE_0F24 */
2740 { "fmaddps", { { OP_DREX4, q_mode } } },
2741 { "fmaddpd", { { OP_DREX4, q_mode } } },
2742 { "fmaddss", { { OP_DREX4, w_mode } } },
2743 { "fmaddsd", { { OP_DREX4, d_mode } } },
2744 { "fmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2745 { "fmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2746 { "fmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2747 { "fmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
2749 { "fmsubps", { { OP_DREX4, q_mode } } },
2750 { "fmsubpd", { { OP_DREX4, q_mode } } },
2751 { "fmsubss", { { OP_DREX4, w_mode } } },
2752 { "fmsubsd", { { OP_DREX4, d_mode } } },
2753 { "fmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2754 { "fmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2755 { "fmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2756 { "fmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
2758 { "fnmaddps", { { OP_DREX4, q_mode } } },
2759 { "fnmaddpd", { { OP_DREX4, q_mode } } },
2760 { "fnmaddss", { { OP_DREX4, w_mode } } },
2761 { "fnmaddsd", { { OP_DREX4, d_mode } } },
2762 { "fnmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2763 { "fnmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2764 { "fnmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2765 { "fnmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
2767 { "fnmsubps", { { OP_DREX4, q_mode } } },
2768 { "fnmsubpd", { { OP_DREX4, q_mode } } },
2769 { "fnmsubss", { { OP_DREX4, w_mode } } },
2770 { "fnmsubsd", { { OP_DREX4, d_mode } } },
2771 { "fnmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2772 { "fnmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2773 { "fnmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2774 { "fnmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
2776 { "permps", { { OP_DREX4, q_mode } } },
2777 { "permpd", { { OP_DREX4, q_mode } } },
2778 { "pcmov", { { OP_DREX4, q_mode } } },
2779 { "pperm", { { OP_DREX4, q_mode } } },
2780 { "permps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2781 { "permpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2782 { "pcmov", { { OP_DREX4, DREX_OC1 + w_mode } } },
2783 { "pperm", { { OP_DREX4, DREX_OC1 + d_mode } } },
2785 { "(bad)", { XX } },
2786 { "(bad)", { XX } },
2787 { "(bad)", { XX } },
2788 { "(bad)", { XX } },
2789 { "(bad)", { XX } },
2790 { "(bad)", { XX } },
2791 { "(bad)", { XX } },
2792 { "(bad)", { XX } },
2794 { "(bad)", { XX } },
2795 { "(bad)", { XX } },
2796 { "(bad)", { XX } },
2797 { "(bad)", { XX } },
2798 { "(bad)", { XX } },
2799 { "(bad)", { XX } },
2800 { "(bad)", { XX } },
2801 { "(bad)", { XX } },
2803 { "(bad)", { XX } },
2804 { "(bad)", { XX } },
2805 { "(bad)", { XX } },
2806 { "(bad)", { XX } },
2807 { "(bad)", { XX } },
2808 { "(bad)", { XX } },
2809 { "(bad)", { XX } },
2810 { "(bad)", { XX } },
2812 { "protb", { { OP_DREX3, q_mode } } },
2813 { "protw", { { OP_DREX3, q_mode } } },
2814 { "protd", { { OP_DREX3, q_mode } } },
2815 { "protq", { { OP_DREX3, q_mode } } },
2816 { "pshlb", { { OP_DREX3, q_mode } } },
2817 { "pshlw", { { OP_DREX3, q_mode } } },
2818 { "pshld", { { OP_DREX3, q_mode } } },
2819 { "pshlq", { { OP_DREX3, q_mode } } },
2821 { "pshab", { { OP_DREX3, q_mode } } },
2822 { "pshaw", { { OP_DREX3, q_mode } } },
2823 { "pshad", { { OP_DREX3, q_mode } } },
2824 { "pshaq", { { OP_DREX3, q_mode } } },
2825 { "(bad)", { XX } },
2826 { "(bad)", { XX } },
2827 { "(bad)", { XX } },
2828 { "(bad)", { XX } },
2830 { "(bad)", { XX } },
2831 { "(bad)", { XX } },
2832 { "(bad)", { XX } },
2833 { "(bad)", { XX } },
2834 { "(bad)", { XX } },
2835 { "(bad)", { XX } },
2836 { "(bad)", { XX } },
2837 { "(bad)", { XX } },
2839 { "(bad)", { XX } },
2840 { "(bad)", { XX } },
2841 { "(bad)", { XX } },
2842 { "(bad)", { XX } },
2843 { "(bad)", { XX } },
2844 { "(bad)", { XX } },
2845 { "(bad)", { XX } },
2846 { "(bad)", { XX } },
2848 { "(bad)", { XX } },
2849 { "(bad)", { XX } },
2850 { "(bad)", { XX } },
2851 { "(bad)", { XX } },
2852 { "(bad)", { XX } },
2853 { "(bad)", { XX } },
2854 { "(bad)", { XX } },
2855 { "(bad)", { XX } },
2857 { "(bad)", { XX } },
2858 { "(bad)", { XX } },
2859 { "(bad)", { XX } },
2860 { "(bad)", { XX } },
2861 { "(bad)", { XX } },
2862 { "(bad)", { XX } },
2863 { "(bad)", { XX } },
2864 { "(bad)", { XX } },
2866 { "(bad)", { XX } },
2867 { "(bad)", { XX } },
2868 { "(bad)", { XX } },
2869 { "(bad)", { XX } },
2870 { "(bad)", { XX } },
2871 { "(bad)", { XX } },
2872 { "(bad)", { XX } },
2873 { "(bad)", { XX } },
2875 { "(bad)", { XX } },
2876 { "(bad)", { XX } },
2877 { "(bad)", { XX } },
2878 { "(bad)", { XX } },
2879 { "(bad)", { XX } },
2880 { "(bad)", { XX } },
2881 { "(bad)", { XX } },
2882 { "(bad)", { XX } },
2884 { "(bad)", { XX } },
2885 { "(bad)", { XX } },
2886 { "(bad)", { XX } },
2887 { "(bad)", { XX } },
2888 { "(bad)", { XX } },
2889 { "pmacssww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2890 { "pmacsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2891 { "pmacssdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2893 { "(bad)", { XX } },
2894 { "(bad)", { XX } },
2895 { "(bad)", { XX } },
2896 { "(bad)", { XX } },
2897 { "(bad)", { XX } },
2898 { "(bad)", { XX } },
2899 { "pmacssdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2900 { "pmacssdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2902 { "(bad)", { XX } },
2903 { "(bad)", { XX } },
2904 { "(bad)", { XX } },
2905 { "(bad)", { XX } },
2906 { "(bad)", { XX } },
2907 { "pmacsww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2908 { "pmacswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2909 { "pmacsdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2911 { "(bad)", { XX } },
2912 { "(bad)", { XX } },
2913 { "(bad)", { XX } },
2914 { "(bad)", { XX } },
2915 { "(bad)", { XX } },
2916 { "(bad)", { XX } },
2917 { "pmacsdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2918 { "pmacsdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2920 { "(bad)", { XX } },
2921 { "(bad)", { XX } },
2922 { "(bad)", { XX } },
2923 { "(bad)", { XX } },
2924 { "(bad)", { XX } },
2925 { "(bad)", { XX } },
2926 { "pmadcsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2927 { "(bad)", { XX } },
2929 { "(bad)", { XX } },
2930 { "(bad)", { XX } },
2931 { "(bad)", { XX } },
2932 { "(bad)", { XX } },
2933 { "(bad)", { XX } },
2934 { "(bad)", { XX } },
2935 { "(bad)", { XX } },
2936 { "(bad)", { XX } },
2938 { "(bad)", { XX } },
2939 { "(bad)", { XX } },
2940 { "(bad)", { XX } },
2941 { "(bad)", { XX } },
2942 { "(bad)", { XX } },
2943 { "(bad)", { XX } },
2944 { "pmadcswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2945 { "(bad)", { XX } },
2947 { "(bad)", { XX } },
2948 { "(bad)", { XX } },
2949 { "(bad)", { XX } },
2950 { "(bad)", { XX } },
2951 { "(bad)", { XX } },
2952 { "(bad)", { XX } },
2953 { "(bad)", { XX } },
2954 { "(bad)", { XX } },
2956 { "(bad)", { XX } },
2957 { "(bad)", { XX } },
2958 { "(bad)", { XX } },
2959 { "(bad)", { XX } },
2960 { "(bad)", { XX } },
2961 { "(bad)", { XX } },
2962 { "(bad)", { XX } },
2963 { "(bad)", { XX } },
2965 { "(bad)", { XX } },
2966 { "(bad)", { XX } },
2967 { "(bad)", { XX } },
2968 { "(bad)", { XX } },
2969 { "(bad)", { XX } },
2970 { "(bad)", { XX } },
2971 { "(bad)", { XX } },
2972 { "(bad)", { XX } },
2974 { "(bad)", { XX } },
2975 { "(bad)", { XX } },
2976 { "(bad)", { XX } },
2977 { "(bad)", { XX } },
2978 { "(bad)", { XX } },
2979 { "(bad)", { XX } },
2980 { "(bad)", { XX } },
2981 { "(bad)", { XX } },
2983 { "(bad)", { XX } },
2984 { "(bad)", { XX } },
2985 { "(bad)", { XX } },
2986 { "(bad)", { XX } },
2987 { "(bad)", { XX } },
2988 { "(bad)", { XX } },
2989 { "(bad)", { XX } },
2990 { "(bad)", { XX } },
2992 { "(bad)", { XX } },
2993 { "(bad)", { XX } },
2994 { "(bad)", { XX } },
2995 { "(bad)", { XX } },
2996 { "(bad)", { XX } },
2997 { "(bad)", { XX } },
2998 { "(bad)", { XX } },
2999 { "(bad)", { XX } },
3001 { "(bad)", { XX } },
3002 { "(bad)", { XX } },
3003 { "(bad)", { XX } },
3004 { "(bad)", { XX } },
3005 { "(bad)", { XX } },
3006 { "(bad)", { XX } },
3007 { "(bad)", { XX } },
3008 { "(bad)", { XX } },
3010 { "(bad)", { XX } },
3011 { "(bad)", { XX } },
3012 { "(bad)", { XX } },
3013 { "(bad)", { XX } },
3014 { "(bad)", { XX } },
3015 { "(bad)", { XX } },
3016 { "(bad)", { XX } },
3017 { "(bad)", { XX } },
3019 { "(bad)", { XX } },
3020 { "(bad)", { XX } },
3021 { "(bad)", { XX } },
3022 { "(bad)", { XX } },
3023 { "(bad)", { XX } },
3024 { "(bad)", { XX } },
3025 { "(bad)", { XX } },
3026 { "(bad)", { XX } },
3028 /* THREE_BYTE_0F25 */
3031 { "(bad)", { XX } },
3032 { "(bad)", { XX } },
3033 { "(bad)", { XX } },
3034 { "(bad)", { XX } },
3035 { "(bad)", { XX } },
3036 { "(bad)", { XX } },
3037 { "(bad)", { XX } },
3038 { "(bad)", { XX } },
3040 { "(bad)", { XX } },
3041 { "(bad)", { XX } },
3042 { "(bad)", { XX } },
3043 { "(bad)", { XX } },
3044 { "(bad)", { XX } },
3045 { "(bad)", { XX } },
3046 { "(bad)", { XX } },
3047 { "(bad)", { XX } },
3049 { "(bad)", { XX } },
3050 { "(bad)", { XX } },
3051 { "(bad)", { XX } },
3052 { "(bad)", { XX } },
3053 { "(bad)", { XX } },
3054 { "(bad)", { XX } },
3055 { "(bad)", { XX } },
3056 { "(bad)", { XX } },
3058 { "(bad)", { XX } },
3059 { "(bad)", { XX } },
3060 { "(bad)", { XX } },
3061 { "(bad)", { XX } },
3062 { "(bad)", { XX } },
3063 { "(bad)", { XX } },
3064 { "(bad)", { XX } },
3065 { "(bad)", { XX } },
3067 { "(bad)", { XX } },
3068 { "(bad)", { XX } },
3069 { "(bad)", { XX } },
3070 { "(bad)", { XX } },
3071 { "(bad)", { XX } },
3072 { "(bad)", { XX } },
3073 { "(bad)", { XX } },
3074 { "(bad)", { XX } },
3076 { "(bad)", { XX } },
3077 { "(bad)", { XX } },
3078 { "(bad)", { XX } },
3079 { "(bad)", { XX } },
3080 { "comps", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
3081 { "compd", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
3082 { "comss", { { OP_DREX3, w_mode }, { OP_DREX_FCMP, b_mode } } },
3083 { "comsd", { { OP_DREX3, d_mode }, { OP_DREX_FCMP, b_mode } } },
3085 { "(bad)", { XX } },
3086 { "(bad)", { XX } },
3087 { "(bad)", { XX } },
3088 { "(bad)", { XX } },
3089 { "(bad)", { XX } },
3090 { "(bad)", { XX } },
3091 { "(bad)", { XX } },
3092 { "(bad)", { XX } },
3094 { "(bad)", { XX } },
3095 { "(bad)", { XX } },
3096 { "(bad)", { XX } },
3097 { "(bad)", { XX } },
3098 { "(bad)", { XX } },
3099 { "(bad)", { XX } },
3100 { "(bad)", { XX } },
3101 { "(bad)", { XX } },
3103 { "(bad)", { XX } },
3104 { "(bad)", { XX } },
3105 { "(bad)", { XX } },
3106 { "(bad)", { XX } },
3107 { "(bad)", { XX } },
3108 { "(bad)", { XX } },
3109 { "(bad)", { XX } },
3110 { "(bad)", { XX } },
3112 { "(bad)", { XX } },
3113 { "(bad)", { XX } },
3114 { "(bad)", { XX } },
3115 { "(bad)", { XX } },
3116 { "pcomb", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3117 { "pcomw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3118 { "pcomd", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3119 { "pcomq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3121 { "(bad)", { XX } },
3122 { "(bad)", { XX } },
3123 { "(bad)", { XX } },
3124 { "(bad)", { XX } },
3125 { "(bad)", { XX } },
3126 { "(bad)", { XX } },
3127 { "(bad)", { XX } },
3128 { "(bad)", { XX } },
3130 { "(bad)", { XX } },
3131 { "(bad)", { XX } },
3132 { "(bad)", { XX } },
3133 { "(bad)", { XX } },
3134 { "(bad)", { XX } },
3135 { "(bad)", { XX } },
3136 { "(bad)", { XX } },
3137 { "(bad)", { XX } },
3139 { "(bad)", { XX } },
3140 { "(bad)", { XX } },
3141 { "(bad)", { XX } },
3142 { "(bad)", { XX } },
3143 { "(bad)", { XX } },
3144 { "(bad)", { XX } },
3145 { "(bad)", { XX } },
3146 { "(bad)", { XX } },
3148 { "(bad)", { XX } },
3149 { "(bad)", { XX } },
3150 { "(bad)", { XX } },
3151 { "(bad)", { XX } },
3152 { "pcomub", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3153 { "pcomuw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3154 { "pcomud", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3155 { "pcomuq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3157 { "(bad)", { XX } },
3158 { "(bad)", { XX } },
3159 { "(bad)", { XX } },
3160 { "(bad)", { XX } },
3161 { "(bad)", { XX } },
3162 { "(bad)", { XX } },
3163 { "(bad)", { XX } },
3164 { "(bad)", { XX } },
3166 { "(bad)", { XX } },
3167 { "(bad)", { XX } },
3168 { "(bad)", { XX } },
3169 { "(bad)", { XX } },
3170 { "(bad)", { XX } },
3171 { "(bad)", { XX } },
3172 { "(bad)", { XX } },
3173 { "(bad)", { XX } },
3175 { "(bad)", { XX } },
3176 { "(bad)", { XX } },
3177 { "(bad)", { XX } },
3178 { "(bad)", { XX } },
3179 { "(bad)", { XX } },
3180 { "(bad)", { XX } },
3181 { "(bad)", { XX } },
3182 { "(bad)", { XX } },
3184 { "(bad)", { XX } },
3185 { "(bad)", { XX } },
3186 { "(bad)", { XX } },
3187 { "(bad)", { XX } },
3188 { "(bad)", { XX } },
3189 { "(bad)", { XX } },
3190 { "(bad)", { XX } },
3191 { "(bad)", { XX } },
3193 { "(bad)", { XX } },
3194 { "(bad)", { XX } },
3195 { "(bad)", { XX } },
3196 { "(bad)", { XX } },
3197 { "(bad)", { XX } },
3198 { "(bad)", { XX } },
3199 { "(bad)", { XX } },
3200 { "(bad)", { XX } },
3202 { "(bad)", { XX } },
3203 { "(bad)", { XX } },
3204 { "(bad)", { XX } },
3205 { "(bad)", { XX } },
3206 { "(bad)", { XX } },
3207 { "(bad)", { XX } },
3208 { "(bad)", { XX } },
3209 { "(bad)", { XX } },
3211 { "(bad)", { XX } },
3212 { "(bad)", { XX } },
3213 { "(bad)", { XX } },
3214 { "(bad)", { XX } },
3215 { "(bad)", { XX } },
3216 { "(bad)", { XX } },
3217 { "(bad)", { XX } },
3218 { "(bad)", { XX } },
3220 { "(bad)", { XX } },
3221 { "(bad)", { XX } },
3222 { "(bad)", { XX } },
3223 { "(bad)", { XX } },
3224 { "(bad)", { XX } },
3225 { "(bad)", { XX } },
3226 { "(bad)", { XX } },
3227 { "(bad)", { XX } },
3229 { "(bad)", { XX } },
3230 { "(bad)", { XX } },
3231 { "(bad)", { XX } },
3232 { "(bad)", { XX } },
3233 { "(bad)", { XX } },
3234 { "(bad)", { XX } },
3235 { "(bad)", { XX } },
3236 { "(bad)", { XX } },
3238 { "(bad)", { XX } },
3239 { "(bad)", { XX } },
3240 { "(bad)", { XX } },
3241 { "(bad)", { XX } },
3242 { "(bad)", { XX } },
3243 { "(bad)", { XX } },
3244 { "(bad)", { XX } },
3245 { "(bad)", { XX } },
3247 { "(bad)", { XX } },
3248 { "(bad)", { XX } },
3249 { "(bad)", { XX } },
3250 { "(bad)", { XX } },
3251 { "(bad)", { XX } },
3252 { "(bad)", { XX } },
3253 { "(bad)", { XX } },
3254 { "(bad)", { XX } },
3256 { "(bad)", { XX } },
3257 { "(bad)", { XX } },
3258 { "(bad)", { XX } },
3259 { "(bad)", { XX } },
3260 { "(bad)", { XX } },
3261 { "(bad)", { XX } },
3262 { "(bad)", { XX } },
3263 { "(bad)", { XX } },
3265 { "(bad)", { XX } },
3266 { "(bad)", { XX } },
3267 { "(bad)", { XX } },
3268 { "(bad)", { XX } },
3269 { "(bad)", { XX } },
3270 { "(bad)", { XX } },
3271 { "(bad)", { XX } },
3272 { "(bad)", { XX } },
3274 { "(bad)", { XX } },
3275 { "(bad)", { XX } },
3276 { "(bad)", { XX } },
3277 { "(bad)", { XX } },
3278 { "(bad)", { XX } },
3279 { "(bad)", { XX } },
3280 { "(bad)", { XX } },
3281 { "(bad)", { XX } },
3283 { "(bad)", { XX } },
3284 { "(bad)", { XX } },
3285 { "(bad)", { XX } },
3286 { "(bad)", { XX } },
3287 { "(bad)", { XX } },
3288 { "(bad)", { XX } },
3289 { "(bad)", { XX } },
3290 { "(bad)", { XX } },
3292 { "(bad)", { XX } },
3293 { "(bad)", { XX } },
3294 { "(bad)", { XX } },
3295 { "(bad)", { XX } },
3296 { "(bad)", { XX } },
3297 { "(bad)", { XX } },
3298 { "(bad)", { XX } },
3299 { "(bad)", { XX } },
3301 { "(bad)", { XX } },
3302 { "(bad)", { XX } },
3303 { "(bad)", { XX } },
3304 { "(bad)", { XX } },
3305 { "(bad)", { XX } },
3306 { "(bad)", { XX } },
3307 { "(bad)", { XX } },
3308 { "(bad)", { XX } },
3310 { "(bad)", { XX } },
3311 { "(bad)", { XX } },
3312 { "(bad)", { XX } },
3313 { "(bad)", { XX } },
3314 { "(bad)", { XX } },
3315 { "(bad)", { XX } },
3316 { "(bad)", { XX } },
3317 { "(bad)", { XX } },
3319 /* THREE_BYTE_0F38 */
3322 { "pshufb", { MX, EM } },
3323 { "phaddw", { MX, EM } },
3324 { "phaddd", { MX, EM } },
3325 { "phaddsw", { MX, EM } },
3326 { "pmaddubsw", { MX, EM } },
3327 { "phsubw", { MX, EM } },
3328 { "phsubd", { MX, EM } },
3329 { "phsubsw", { MX, EM } },
3331 { "psignb", { MX, EM } },
3332 { "psignw", { MX, EM } },
3333 { "psignd", { MX, EM } },
3334 { "pmulhrsw", { MX, EM } },
3335 { "(bad)", { XX } },
3336 { "(bad)", { XX } },
3337 { "(bad)", { XX } },
3338 { "(bad)", { XX } },
3340 { PREFIX_TABLE (PREFIX_0F3810) },
3341 { "(bad)", { XX } },
3342 { "(bad)", { XX } },
3343 { "(bad)", { XX } },
3344 { PREFIX_TABLE (PREFIX_0F3814) },
3345 { PREFIX_TABLE (PREFIX_0F3815) },
3346 { "(bad)", { XX } },
3347 { PREFIX_TABLE (PREFIX_0F3817) },
3349 { "(bad)", { XX } },
3350 { "(bad)", { XX } },
3351 { "(bad)", { XX } },
3352 { "(bad)", { XX } },
3353 { "pabsb", { MX, EM } },
3354 { "pabsw", { MX, EM } },
3355 { "pabsd", { MX, EM } },
3356 { "(bad)", { XX } },
3358 { PREFIX_TABLE (PREFIX_0F3820) },
3359 { PREFIX_TABLE (PREFIX_0F3821) },
3360 { PREFIX_TABLE (PREFIX_0F3822) },
3361 { PREFIX_TABLE (PREFIX_0F3823) },
3362 { PREFIX_TABLE (PREFIX_0F3824) },
3363 { PREFIX_TABLE (PREFIX_0F3825) },
3364 { "(bad)", { XX } },
3365 { "(bad)", { XX } },
3367 { PREFIX_TABLE (PREFIX_0F3828) },
3368 { PREFIX_TABLE (PREFIX_0F3829) },
3369 { PREFIX_TABLE (PREFIX_0F382A) },
3370 { PREFIX_TABLE (PREFIX_0F382B) },
3371 { "(bad)", { XX } },
3372 { "(bad)", { XX } },
3373 { "(bad)", { XX } },
3374 { "(bad)", { XX } },
3376 { PREFIX_TABLE (PREFIX_0F3830) },
3377 { PREFIX_TABLE (PREFIX_0F3831) },
3378 { PREFIX_TABLE (PREFIX_0F3832) },
3379 { PREFIX_TABLE (PREFIX_0F3833) },
3380 { PREFIX_TABLE (PREFIX_0F3834) },
3381 { PREFIX_TABLE (PREFIX_0F3835) },
3382 { "(bad)", { XX } },
3383 { PREFIX_TABLE (PREFIX_0F3837) },
3385 { PREFIX_TABLE (PREFIX_0F3838) },
3386 { PREFIX_TABLE (PREFIX_0F3839) },
3387 { PREFIX_TABLE (PREFIX_0F383A) },
3388 { PREFIX_TABLE (PREFIX_0F383B) },
3389 { PREFIX_TABLE (PREFIX_0F383C) },
3390 { PREFIX_TABLE (PREFIX_0F383D) },
3391 { PREFIX_TABLE (PREFIX_0F383E) },
3392 { PREFIX_TABLE (PREFIX_0F383F) },
3394 { PREFIX_TABLE (PREFIX_0F3840) },
3395 { PREFIX_TABLE (PREFIX_0F3841) },
3396 { "(bad)", { XX } },
3397 { "(bad)", { XX } },
3398 { "(bad)", { XX } },
3399 { "(bad)", { XX } },
3400 { "(bad)", { XX } },
3401 { "(bad)", { XX } },
3403 { "(bad)", { XX } },
3404 { "(bad)", { XX } },
3405 { "(bad)", { XX } },
3406 { "(bad)", { XX } },
3407 { "(bad)", { XX } },
3408 { "(bad)", { XX } },
3409 { "(bad)", { XX } },
3410 { "(bad)", { XX } },
3412 { "(bad)", { XX } },
3413 { "(bad)", { XX } },
3414 { "(bad)", { XX } },
3415 { "(bad)", { XX } },
3416 { "(bad)", { XX } },
3417 { "(bad)", { XX } },
3418 { "(bad)", { XX } },
3419 { "(bad)", { XX } },
3421 { "(bad)", { XX } },
3422 { "(bad)", { XX } },
3423 { "(bad)", { XX } },
3424 { "(bad)", { XX } },
3425 { "(bad)", { XX } },
3426 { "(bad)", { XX } },
3427 { "(bad)", { XX } },
3428 { "(bad)", { XX } },
3430 { "(bad)", { XX } },
3431 { "(bad)", { XX } },
3432 { "(bad)", { XX } },
3433 { "(bad)", { XX } },
3434 { "(bad)", { XX } },
3435 { "(bad)", { XX } },
3436 { "(bad)", { XX } },
3437 { "(bad)", { XX } },
3439 { "(bad)", { XX } },
3440 { "(bad)", { XX } },
3441 { "(bad)", { XX } },
3442 { "(bad)", { XX } },
3443 { "(bad)", { XX } },
3444 { "(bad)", { XX } },
3445 { "(bad)", { XX } },
3446 { "(bad)", { XX } },
3448 { "(bad)", { XX } },
3449 { "(bad)", { XX } },
3450 { "(bad)", { XX } },
3451 { "(bad)", { XX } },
3452 { "(bad)", { XX } },
3453 { "(bad)", { XX } },
3454 { "(bad)", { XX } },
3455 { "(bad)", { XX } },
3457 { "(bad)", { XX } },
3458 { "(bad)", { XX } },
3459 { "(bad)", { XX } },
3460 { "(bad)", { XX } },
3461 { "(bad)", { XX } },
3462 { "(bad)", { XX } },
3463 { "(bad)", { XX } },
3464 { "(bad)", { XX } },
3466 { "(bad)", { XX } },
3467 { "(bad)", { XX } },
3468 { "(bad)", { XX } },
3469 { "(bad)", { XX } },
3470 { "(bad)", { XX } },
3471 { "(bad)", { XX } },
3472 { "(bad)", { XX } },
3473 { "(bad)", { XX } },
3475 { "(bad)", { XX } },
3476 { "(bad)", { XX } },
3477 { "(bad)", { XX } },
3478 { "(bad)", { XX } },
3479 { "(bad)", { XX } },
3480 { "(bad)", { XX } },
3481 { "(bad)", { XX } },
3482 { "(bad)", { XX } },
3484 { "(bad)", { XX } },
3485 { "(bad)", { XX } },
3486 { "(bad)", { XX } },
3487 { "(bad)", { XX } },
3488 { "(bad)", { XX } },
3489 { "(bad)", { XX } },
3490 { "(bad)", { XX } },
3491 { "(bad)", { XX } },
3493 { "(bad)", { XX } },
3494 { "(bad)", { XX } },
3495 { "(bad)", { XX } },
3496 { "(bad)", { XX } },
3497 { "(bad)", { XX } },
3498 { "(bad)", { XX } },
3499 { "(bad)", { XX } },
3500 { "(bad)", { XX } },
3502 { "(bad)", { XX } },
3503 { "(bad)", { XX } },
3504 { "(bad)", { XX } },
3505 { "(bad)", { XX } },
3506 { "(bad)", { XX } },
3507 { "(bad)", { XX } },
3508 { "(bad)", { XX } },
3509 { "(bad)", { XX } },
3511 { "(bad)", { XX } },
3512 { "(bad)", { XX } },
3513 { "(bad)", { XX } },
3514 { "(bad)", { XX } },
3515 { "(bad)", { XX } },
3516 { "(bad)", { XX } },
3517 { "(bad)", { XX } },
3518 { "(bad)", { XX } },
3520 { "(bad)", { XX } },
3521 { "(bad)", { XX } },
3522 { "(bad)", { XX } },
3523 { "(bad)", { XX } },
3524 { "(bad)", { XX } },
3525 { "(bad)", { XX } },
3526 { "(bad)", { XX } },
3527 { "(bad)", { XX } },
3529 { "(bad)", { XX } },
3530 { "(bad)", { XX } },
3531 { "(bad)", { XX } },
3532 { "(bad)", { XX } },
3533 { "(bad)", { XX } },
3534 { "(bad)", { XX } },
3535 { "(bad)", { XX } },
3536 { "(bad)", { XX } },
3538 { "(bad)", { XX } },
3539 { "(bad)", { XX } },
3540 { "(bad)", { XX } },
3541 { "(bad)", { XX } },
3542 { "(bad)", { XX } },
3543 { "(bad)", { XX } },
3544 { "(bad)", { XX } },
3545 { "(bad)", { XX } },
3547 { "(bad)", { XX } },
3548 { "(bad)", { XX } },
3549 { "(bad)", { XX } },
3550 { "(bad)", { XX } },
3551 { "(bad)", { XX } },
3552 { "(bad)", { XX } },
3553 { "(bad)", { XX } },
3554 { "(bad)", { XX } },
3556 { "(bad)", { XX } },
3557 { "(bad)", { XX } },
3558 { "(bad)", { XX } },
3559 { "(bad)", { XX } },
3560 { "(bad)", { XX } },
3561 { "(bad)", { XX } },
3562 { "(bad)", { XX } },
3563 { "(bad)", { XX } },
3565 { "(bad)", { XX } },
3566 { "(bad)", { XX } },
3567 { "(bad)", { XX } },
3568 { "(bad)", { XX } },
3569 { "(bad)", { XX } },
3570 { "(bad)", { XX } },
3571 { "(bad)", { XX } },
3572 { "(bad)", { XX } },
3574 { "(bad)", { XX } },
3575 { "(bad)", { XX } },
3576 { "(bad)", { XX } },
3577 { "(bad)", { XX } },
3578 { "(bad)", { XX } },
3579 { "(bad)", { XX } },
3580 { "(bad)", { XX } },
3581 { "(bad)", { XX } },
3583 { "(bad)", { XX } },
3584 { "(bad)", { XX } },
3585 { "(bad)", { XX } },
3586 { "(bad)", { XX } },
3587 { "(bad)", { XX } },
3588 { "(bad)", { XX } },
3589 { "(bad)", { XX } },
3590 { "(bad)", { XX } },
3592 { PREFIX_TABLE (PREFIX_0F38F0) },
3593 { PREFIX_TABLE (PREFIX_0F38F1) },
3594 { "(bad)", { XX } },
3595 { "(bad)", { XX } },
3596 { "(bad)", { XX } },
3597 { "(bad)", { XX } },
3598 { "(bad)", { XX } },
3599 { "(bad)", { XX } },
3601 { "(bad)", { XX } },
3602 { "(bad)", { XX } },
3603 { "(bad)", { XX } },
3604 { "(bad)", { XX } },
3605 { "(bad)", { XX } },
3606 { "(bad)", { XX } },
3607 { "(bad)", { XX } },
3608 { "(bad)", { XX } },
3610 /* THREE_BYTE_0F3A */
3613 { "(bad)", { XX } },
3614 { "(bad)", { XX } },
3615 { "(bad)", { XX } },
3616 { "(bad)", { XX } },
3617 { "(bad)", { XX } },
3618 { "(bad)", { XX } },
3619 { "(bad)", { XX } },
3620 { "(bad)", { XX } },
3622 { PREFIX_TABLE (PREFIX_0F3A08) },
3623 { PREFIX_TABLE (PREFIX_0F3A09) },
3624 { PREFIX_TABLE (PREFIX_0F3A0A) },
3625 { PREFIX_TABLE (PREFIX_0F3A0B) },
3626 { PREFIX_TABLE (PREFIX_0F3A0C) },
3627 { PREFIX_TABLE (PREFIX_0F3A0D) },
3628 { PREFIX_TABLE (PREFIX_0F3A0E) },
3629 { "palignr", { MX, EM, Ib } },
3631 { "(bad)", { XX } },
3632 { "(bad)", { XX } },
3633 { "(bad)", { XX } },
3634 { "(bad)", { XX } },
3635 { PREFIX_TABLE (PREFIX_0F3A14) },
3636 { PREFIX_TABLE (PREFIX_0F3A15) },
3637 { PREFIX_TABLE (PREFIX_0F3A16) },
3638 { PREFIX_TABLE (PREFIX_0F3A17) },
3640 { "(bad)", { XX } },
3641 { "(bad)", { XX } },
3642 { "(bad)", { XX } },
3643 { "(bad)", { XX } },
3644 { "(bad)", { XX } },
3645 { "(bad)", { XX } },
3646 { "(bad)", { XX } },
3647 { "(bad)", { XX } },
3649 { PREFIX_TABLE (PREFIX_0F3A20) },
3650 { PREFIX_TABLE (PREFIX_0F3A21) },
3651 { PREFIX_TABLE (PREFIX_0F3A22) },
3652 { "(bad)", { XX } },
3653 { "(bad)", { XX } },
3654 { "(bad)", { XX } },
3655 { "(bad)", { XX } },
3656 { "(bad)", { XX } },
3658 { "(bad)", { XX } },
3659 { "(bad)", { XX } },
3660 { "(bad)", { XX } },
3661 { "(bad)", { XX } },
3662 { "(bad)", { XX } },
3663 { "(bad)", { XX } },
3664 { "(bad)", { XX } },
3665 { "(bad)", { XX } },
3667 { "(bad)", { XX } },
3668 { "(bad)", { XX } },
3669 { "(bad)", { XX } },
3670 { "(bad)", { XX } },
3671 { "(bad)", { XX } },
3672 { "(bad)", { XX } },
3673 { "(bad)", { XX } },
3674 { "(bad)", { XX } },
3676 { "(bad)", { XX } },
3677 { "(bad)", { XX } },
3678 { "(bad)", { XX } },
3679 { "(bad)", { XX } },
3680 { "(bad)", { XX } },
3681 { "(bad)", { XX } },
3682 { "(bad)", { XX } },
3683 { "(bad)", { XX } },
3685 { PREFIX_TABLE (PREFIX_0F3A40) },
3686 { PREFIX_TABLE (PREFIX_0F3A41) },
3687 { PREFIX_TABLE (PREFIX_0F3A42) },
3688 { "(bad)", { XX } },
3689 { "(bad)", { XX } },
3690 { "(bad)", { XX } },
3691 { "(bad)", { XX } },
3692 { "(bad)", { XX } },
3694 { "(bad)", { XX } },
3695 { "(bad)", { XX } },
3696 { "(bad)", { XX } },
3697 { "(bad)", { XX } },
3698 { "(bad)", { XX } },
3699 { "(bad)", { XX } },
3700 { "(bad)", { XX } },
3701 { "(bad)", { XX } },
3703 { "(bad)", { XX } },
3704 { "(bad)", { XX } },
3705 { "(bad)", { XX } },
3706 { "(bad)", { XX } },
3707 { "(bad)", { XX } },
3708 { "(bad)", { XX } },
3709 { "(bad)", { XX } },
3710 { "(bad)", { XX } },
3712 { "(bad)", { XX } },
3713 { "(bad)", { XX } },
3714 { "(bad)", { XX } },
3715 { "(bad)", { XX } },
3716 { "(bad)", { XX } },
3717 { "(bad)", { XX } },
3718 { "(bad)", { XX } },
3719 { "(bad)", { XX } },
3721 { PREFIX_TABLE (PREFIX_0F3A60) },
3722 { PREFIX_TABLE (PREFIX_0F3A61) },
3723 { PREFIX_TABLE (PREFIX_0F3A62) },
3724 { PREFIX_TABLE (PREFIX_0F3A63) },
3725 { "(bad)", { XX } },
3726 { "(bad)", { XX } },
3727 { "(bad)", { XX } },
3728 { "(bad)", { XX } },
3730 { "(bad)", { XX } },
3731 { "(bad)", { XX } },
3732 { "(bad)", { XX } },
3733 { "(bad)", { XX } },
3734 { "(bad)", { XX } },
3735 { "(bad)", { XX } },
3736 { "(bad)", { XX } },
3737 { "(bad)", { XX } },
3739 { "(bad)", { XX } },
3740 { "(bad)", { XX } },
3741 { "(bad)", { XX } },
3742 { "(bad)", { XX } },
3743 { "(bad)", { XX } },
3744 { "(bad)", { XX } },
3745 { "(bad)", { XX } },
3746 { "(bad)", { XX } },
3748 { "(bad)", { XX } },
3749 { "(bad)", { XX } },
3750 { "(bad)", { XX } },
3751 { "(bad)", { XX } },
3752 { "(bad)", { XX } },
3753 { "(bad)", { XX } },
3754 { "(bad)", { XX } },
3755 { "(bad)", { XX } },
3757 { "(bad)", { XX } },
3758 { "(bad)", { XX } },
3759 { "(bad)", { XX } },
3760 { "(bad)", { XX } },
3761 { "(bad)", { XX } },
3762 { "(bad)", { XX } },
3763 { "(bad)", { XX } },
3764 { "(bad)", { XX } },
3766 { "(bad)", { XX } },
3767 { "(bad)", { XX } },
3768 { "(bad)", { XX } },
3769 { "(bad)", { XX } },
3770 { "(bad)", { XX } },
3771 { "(bad)", { XX } },
3772 { "(bad)", { XX } },
3773 { "(bad)", { XX } },
3775 { "(bad)", { XX } },
3776 { "(bad)", { XX } },
3777 { "(bad)", { XX } },
3778 { "(bad)", { XX } },
3779 { "(bad)", { XX } },
3780 { "(bad)", { XX } },
3781 { "(bad)", { XX } },
3782 { "(bad)", { XX } },
3784 { "(bad)", { XX } },
3785 { "(bad)", { XX } },
3786 { "(bad)", { XX } },
3787 { "(bad)", { XX } },
3788 { "(bad)", { XX } },
3789 { "(bad)", { XX } },
3790 { "(bad)", { XX } },
3791 { "(bad)", { XX } },
3793 { "(bad)", { XX } },
3794 { "(bad)", { XX } },
3795 { "(bad)", { XX } },
3796 { "(bad)", { XX } },
3797 { "(bad)", { XX } },
3798 { "(bad)", { XX } },
3799 { "(bad)", { XX } },
3800 { "(bad)", { XX } },
3802 { "(bad)", { XX } },
3803 { "(bad)", { XX } },
3804 { "(bad)", { XX } },
3805 { "(bad)", { XX } },
3806 { "(bad)", { XX } },
3807 { "(bad)", { XX } },
3808 { "(bad)", { XX } },
3809 { "(bad)", { XX } },
3811 { "(bad)", { XX } },
3812 { "(bad)", { XX } },
3813 { "(bad)", { XX } },
3814 { "(bad)", { XX } },
3815 { "(bad)", { XX } },
3816 { "(bad)", { XX } },
3817 { "(bad)", { XX } },
3818 { "(bad)", { XX } },
3820 { "(bad)", { XX } },
3821 { "(bad)", { XX } },
3822 { "(bad)", { XX } },
3823 { "(bad)", { XX } },
3824 { "(bad)", { XX } },
3825 { "(bad)", { XX } },
3826 { "(bad)", { XX } },
3827 { "(bad)", { XX } },
3829 { "(bad)", { XX } },
3830 { "(bad)", { XX } },
3831 { "(bad)", { XX } },
3832 { "(bad)", { XX } },
3833 { "(bad)", { XX } },
3834 { "(bad)", { XX } },
3835 { "(bad)", { XX } },
3836 { "(bad)", { XX } },
3838 { "(bad)", { XX } },
3839 { "(bad)", { XX } },
3840 { "(bad)", { XX } },
3841 { "(bad)", { XX } },
3842 { "(bad)", { XX } },
3843 { "(bad)", { XX } },
3844 { "(bad)", { XX } },
3845 { "(bad)", { XX } },
3847 { "(bad)", { XX } },
3848 { "(bad)", { XX } },
3849 { "(bad)", { XX } },
3850 { "(bad)", { XX } },
3851 { "(bad)", { XX } },
3852 { "(bad)", { XX } },
3853 { "(bad)", { XX } },
3854 { "(bad)", { XX } },
3856 { "(bad)", { XX } },
3857 { "(bad)", { XX } },
3858 { "(bad)", { XX } },
3859 { "(bad)", { XX } },
3860 { "(bad)", { XX } },
3861 { "(bad)", { XX } },
3862 { "(bad)", { XX } },
3863 { "(bad)", { XX } },
3865 { "(bad)", { XX } },
3866 { "(bad)", { XX } },
3867 { "(bad)", { XX } },
3868 { "(bad)", { XX } },
3869 { "(bad)", { XX } },
3870 { "(bad)", { XX } },
3871 { "(bad)", { XX } },
3872 { "(bad)", { XX } },
3874 { "(bad)", { XX } },
3875 { "(bad)", { XX } },
3876 { "(bad)", { XX } },
3877 { "(bad)", { XX } },
3878 { "(bad)", { XX } },
3879 { "(bad)", { XX } },
3880 { "(bad)", { XX } },
3881 { "(bad)", { XX } },
3883 { "(bad)", { XX } },
3884 { "(bad)", { XX } },
3885 { "(bad)", { XX } },
3886 { "(bad)", { XX } },
3887 { "(bad)", { XX } },
3888 { "(bad)", { XX } },
3889 { "(bad)", { XX } },
3890 { "(bad)", { XX } },
3892 { "(bad)", { XX } },
3893 { "(bad)", { XX } },
3894 { "(bad)", { XX } },
3895 { "(bad)", { XX } },
3896 { "(bad)", { XX } },
3897 { "(bad)", { XX } },
3898 { "(bad)", { XX } },
3899 { "(bad)", { XX } },
3901 /* THREE_BYTE_0F7A */
3904 { "(bad)", { XX } },
3905 { "(bad)", { XX } },
3906 { "(bad)", { XX } },
3907 { "(bad)", { XX } },
3908 { "(bad)", { XX } },
3909 { "(bad)", { XX } },
3910 { "(bad)", { XX } },
3911 { "(bad)", { XX } },
3913 { "(bad)", { XX } },
3914 { "(bad)", { XX } },
3915 { "(bad)", { XX } },
3916 { "(bad)", { XX } },
3917 { "(bad)", { XX } },
3918 { "(bad)", { XX } },
3919 { "(bad)", { XX } },
3920 { "(bad)", { XX } },
3922 { "frczps", { XM, EXq } },
3923 { "frczpd", { XM, EXq } },
3924 { "frczss", { XM, EXq } },
3925 { "frczsd", { XM, EXq } },
3926 { "(bad)", { XX } },
3927 { "(bad)", { XX } },
3928 { "(bad)", { XX } },
3929 { "(bad)", { XX } },
3931 { "(bad)", { XX } },
3932 { "(bad)", { XX } },
3933 { "(bad)", { XX } },
3934 { "(bad)", { XX } },
3935 { "(bad)", { XX } },
3936 { "(bad)", { XX } },
3937 { "(bad)", { XX } },
3938 { "(bad)", { XX } },
3940 { "ptest", { XX } },
3941 { "(bad)", { XX } },
3942 { "(bad)", { XX } },
3943 { "(bad)", { XX } },
3944 { "(bad)", { XX } },
3945 { "(bad)", { XX } },
3946 { "(bad)", { XX } },
3947 { "(bad)", { XX } },
3949 { "(bad)", { XX } },
3950 { "(bad)", { XX } },
3951 { "(bad)", { XX } },
3952 { "(bad)", { XX } },
3953 { "(bad)", { XX } },
3954 { "(bad)", { XX } },
3955 { "(bad)", { XX } },
3956 { "(bad)", { XX } },
3958 { "cvtph2ps", { XM, EXd } },
3959 { "cvtps2ph", { EXd, XM } },
3960 { "(bad)", { XX } },
3961 { "(bad)", { XX } },
3962 { "(bad)", { XX } },
3963 { "(bad)", { XX } },
3964 { "(bad)", { XX } },
3965 { "(bad)", { XX } },
3967 { "(bad)", { XX } },
3968 { "(bad)", { XX } },
3969 { "(bad)", { XX } },
3970 { "(bad)", { XX } },
3971 { "(bad)", { XX } },
3972 { "(bad)", { XX } },
3973 { "(bad)", { XX } },
3974 { "(bad)", { XX } },
3976 { "(bad)", { XX } },
3977 { "phaddbw", { XM, EXq } },
3978 { "phaddbd", { XM, EXq } },
3979 { "phaddbq", { XM, EXq } },
3980 { "(bad)", { XX } },
3981 { "(bad)", { XX } },
3982 { "phaddwd", { XM, EXq } },
3983 { "phaddwq", { XM, EXq } },
3985 { "(bad)", { XX } },
3986 { "(bad)", { XX } },
3987 { "(bad)", { XX } },
3988 { "phadddq", { XM, EXq } },
3989 { "(bad)", { XX } },
3990 { "(bad)", { XX } },
3991 { "(bad)", { XX } },
3992 { "(bad)", { XX } },
3994 { "(bad)", { XX } },
3995 { "phaddubw", { XM, EXq } },
3996 { "phaddubd", { XM, EXq } },
3997 { "phaddubq", { XM, EXq } },
3998 { "(bad)", { XX } },
3999 { "(bad)", { XX } },
4000 { "phadduwd", { XM, EXq } },
4001 { "phadduwq", { XM, EXq } },
4003 { "(bad)", { XX } },
4004 { "(bad)", { XX } },
4005 { "(bad)", { XX } },
4006 { "phaddudq", { XM, EXq } },
4007 { "(bad)", { XX } },
4008 { "(bad)", { XX } },
4009 { "(bad)", { XX } },
4010 { "(bad)", { XX } },
4012 { "(bad)", { XX } },
4013 { "phsubbw", { XM, EXq } },
4014 { "phsubbd", { XM, EXq } },
4015 { "phsubbq", { XM, EXq } },
4016 { "(bad)", { XX } },
4017 { "(bad)", { XX } },
4018 { "(bad)", { XX } },
4019 { "(bad)", { XX } },
4021 { "(bad)", { XX } },
4022 { "(bad)", { XX } },
4023 { "(bad)", { XX } },
4024 { "(bad)", { XX } },
4025 { "(bad)", { XX } },
4026 { "(bad)", { XX } },
4027 { "(bad)", { XX } },
4028 { "(bad)", { XX } },
4030 { "(bad)", { XX } },
4031 { "(bad)", { XX } },
4032 { "(bad)", { XX } },
4033 { "(bad)", { XX } },
4034 { "(bad)", { XX } },
4035 { "(bad)", { XX } },
4036 { "(bad)", { XX } },
4037 { "(bad)", { XX } },
4039 { "(bad)", { XX } },
4040 { "(bad)", { XX } },
4041 { "(bad)", { XX } },
4042 { "(bad)", { XX } },
4043 { "(bad)", { XX } },
4044 { "(bad)", { XX } },
4045 { "(bad)", { XX } },
4046 { "(bad)", { XX } },
4048 { "(bad)", { XX } },
4049 { "(bad)", { XX } },
4050 { "(bad)", { XX } },
4051 { "(bad)", { XX } },
4052 { "(bad)", { XX } },
4053 { "(bad)", { XX } },
4054 { "(bad)", { XX } },
4055 { "(bad)", { XX } },
4057 { "(bad)", { XX } },
4058 { "(bad)", { XX } },
4059 { "(bad)", { XX } },
4060 { "(bad)", { XX } },
4061 { "(bad)", { XX } },
4062 { "(bad)", { XX } },
4063 { "(bad)", { XX } },
4064 { "(bad)", { XX } },
4066 { "(bad)", { XX } },
4067 { "(bad)", { XX } },
4068 { "(bad)", { XX } },
4069 { "(bad)", { XX } },
4070 { "(bad)", { XX } },
4071 { "(bad)", { XX } },
4072 { "(bad)", { XX } },
4073 { "(bad)", { XX } },
4075 { "(bad)", { XX } },
4076 { "(bad)", { XX } },
4077 { "(bad)", { XX } },
4078 { "(bad)", { XX } },
4079 { "(bad)", { XX } },
4080 { "(bad)", { XX } },
4081 { "(bad)", { XX } },
4082 { "(bad)", { XX } },
4084 { "(bad)", { XX } },
4085 { "(bad)", { XX } },
4086 { "(bad)", { XX } },
4087 { "(bad)", { XX } },
4088 { "(bad)", { XX } },
4089 { "(bad)", { XX } },
4090 { "(bad)", { XX } },
4091 { "(bad)", { XX } },
4093 { "(bad)", { XX } },
4094 { "(bad)", { XX } },
4095 { "(bad)", { XX } },
4096 { "(bad)", { XX } },
4097 { "(bad)", { XX } },
4098 { "(bad)", { XX } },
4099 { "(bad)", { XX } },
4100 { "(bad)", { XX } },
4102 { "(bad)", { XX } },
4103 { "(bad)", { XX } },
4104 { "(bad)", { XX } },
4105 { "(bad)", { XX } },
4106 { "(bad)", { XX } },
4107 { "(bad)", { XX } },
4108 { "(bad)", { XX } },
4109 { "(bad)", { XX } },
4111 { "(bad)", { XX } },
4112 { "(bad)", { XX } },
4113 { "(bad)", { XX } },
4114 { "(bad)", { XX } },
4115 { "(bad)", { XX } },
4116 { "(bad)", { XX } },
4117 { "(bad)", { XX } },
4118 { "(bad)", { XX } },
4120 { "(bad)", { XX } },
4121 { "(bad)", { XX } },
4122 { "(bad)", { XX } },
4123 { "(bad)", { XX } },
4124 { "(bad)", { XX } },
4125 { "(bad)", { XX } },
4126 { "(bad)", { XX } },
4127 { "(bad)", { XX } },
4129 { "(bad)", { XX } },
4130 { "(bad)", { XX } },
4131 { "(bad)", { XX } },
4132 { "(bad)", { XX } },
4133 { "(bad)", { XX } },
4134 { "(bad)", { XX } },
4135 { "(bad)", { XX } },
4136 { "(bad)", { XX } },
4138 { "(bad)", { XX } },
4139 { "(bad)", { XX } },
4140 { "(bad)", { XX } },
4141 { "(bad)", { XX } },
4142 { "(bad)", { XX } },
4143 { "(bad)", { XX } },
4144 { "(bad)", { XX } },
4145 { "(bad)", { XX } },
4147 { "(bad)", { XX } },
4148 { "(bad)", { XX } },
4149 { "(bad)", { XX } },
4150 { "(bad)", { XX } },
4151 { "(bad)", { XX } },
4152 { "(bad)", { XX } },
4153 { "(bad)", { XX } },
4154 { "(bad)", { XX } },
4156 { "(bad)", { XX } },
4157 { "(bad)", { XX } },
4158 { "(bad)", { XX } },
4159 { "(bad)", { XX } },
4160 { "(bad)", { XX } },
4161 { "(bad)", { XX } },
4162 { "(bad)", { XX } },
4163 { "(bad)", { XX } },
4165 { "(bad)", { XX } },
4166 { "(bad)", { XX } },
4167 { "(bad)", { XX } },
4168 { "(bad)", { XX } },
4169 { "(bad)", { XX } },
4170 { "(bad)", { XX } },
4171 { "(bad)", { XX } },
4172 { "(bad)", { XX } },
4174 { "(bad)", { XX } },
4175 { "(bad)", { XX } },
4176 { "(bad)", { XX } },
4177 { "(bad)", { XX } },
4178 { "(bad)", { XX } },
4179 { "(bad)", { XX } },
4180 { "(bad)", { XX } },
4181 { "(bad)", { XX } },
4183 { "(bad)", { XX } },
4184 { "(bad)", { XX } },
4185 { "(bad)", { XX } },
4186 { "(bad)", { XX } },
4187 { "(bad)", { XX } },
4188 { "(bad)", { XX } },
4189 { "(bad)", { XX } },
4190 { "(bad)", { XX } },
4192 /* THREE_BYTE_0F7B */
4195 { "(bad)", { XX } },
4196 { "(bad)", { XX } },
4197 { "(bad)", { XX } },
4198 { "(bad)", { XX } },
4199 { "(bad)", { XX } },
4200 { "(bad)", { XX } },
4201 { "(bad)", { XX } },
4202 { "(bad)", { XX } },
4204 { "(bad)", { XX } },
4205 { "(bad)", { XX } },
4206 { "(bad)", { XX } },
4207 { "(bad)", { XX } },
4208 { "(bad)", { XX } },
4209 { "(bad)", { XX } },
4210 { "(bad)", { XX } },
4211 { "(bad)", { XX } },
4213 { "(bad)", { XX } },
4214 { "(bad)", { XX } },
4215 { "(bad)", { XX } },
4216 { "(bad)", { XX } },
4217 { "(bad)", { XX } },
4218 { "(bad)", { XX } },
4219 { "(bad)", { XX } },
4220 { "(bad)", { XX } },
4222 { "(bad)", { XX } },
4223 { "(bad)", { XX } },
4224 { "(bad)", { XX } },
4225 { "(bad)", { XX } },
4226 { "(bad)", { XX } },
4227 { "(bad)", { XX } },
4228 { "(bad)", { XX } },
4229 { "(bad)", { XX } },
4231 { "(bad)", { XX } },
4232 { "(bad)", { XX } },
4233 { "(bad)", { XX } },
4234 { "(bad)", { XX } },
4235 { "(bad)", { XX } },
4236 { "(bad)", { XX } },
4237 { "(bad)", { XX } },
4238 { "(bad)", { XX } },
4240 { "(bad)", { XX } },
4241 { "(bad)", { XX } },
4242 { "(bad)", { XX } },
4243 { "(bad)", { XX } },
4244 { "(bad)", { XX } },
4245 { "(bad)", { XX } },
4246 { "(bad)", { XX } },
4247 { "(bad)", { XX } },
4249 { "(bad)", { XX } },
4250 { "(bad)", { XX } },
4251 { "(bad)", { XX } },
4252 { "(bad)", { XX } },
4253 { "(bad)", { XX } },
4254 { "(bad)", { XX } },
4255 { "(bad)", { XX } },
4256 { "(bad)", { XX } },
4258 { "(bad)", { XX } },
4259 { "(bad)", { XX } },
4260 { "(bad)", { XX } },
4261 { "(bad)", { XX } },
4262 { "(bad)", { XX } },
4263 { "(bad)", { XX } },
4264 { "(bad)", { XX } },
4265 { "(bad)", { XX } },
4267 { "protb", { XM, EXq, Ib } },
4268 { "protw", { XM, EXq, Ib } },
4269 { "protd", { XM, EXq, Ib } },
4270 { "protq", { XM, EXq, Ib } },
4271 { "pshlb", { XM, EXq, Ib } },
4272 { "pshlw", { XM, EXq, Ib } },
4273 { "pshld", { XM, EXq, Ib } },
4274 { "pshlq", { XM, EXq, Ib } },
4276 { "pshab", { XM, EXq, Ib } },
4277 { "pshaw", { XM, EXq, Ib } },
4278 { "pshad", { XM, EXq, Ib } },
4279 { "pshaq", { XM, EXq, Ib } },
4280 { "(bad)", { XX } },
4281 { "(bad)", { XX } },
4282 { "(bad)", { XX } },
4283 { "(bad)", { XX } },
4285 { "(bad)", { XX } },
4286 { "(bad)", { XX } },
4287 { "(bad)", { XX } },
4288 { "(bad)", { XX } },
4289 { "(bad)", { XX } },
4290 { "(bad)", { XX } },
4291 { "(bad)", { XX } },
4292 { "(bad)", { XX } },
4294 { "(bad)", { XX } },
4295 { "(bad)", { XX } },
4296 { "(bad)", { XX } },
4297 { "(bad)", { XX } },
4298 { "(bad)", { XX } },
4299 { "(bad)", { XX } },
4300 { "(bad)", { XX } },
4301 { "(bad)", { XX } },
4303 { "(bad)", { XX } },
4304 { "(bad)", { XX } },
4305 { "(bad)", { XX } },
4306 { "(bad)", { XX } },
4307 { "(bad)", { XX } },
4308 { "(bad)", { XX } },
4309 { "(bad)", { XX } },
4310 { "(bad)", { XX } },
4312 { "(bad)", { XX } },
4313 { "(bad)", { XX } },
4314 { "(bad)", { XX } },
4315 { "(bad)", { XX } },
4316 { "(bad)", { XX } },
4317 { "(bad)", { XX } },
4318 { "(bad)", { XX } },
4319 { "(bad)", { XX } },
4321 { "(bad)", { XX } },
4322 { "(bad)", { XX } },
4323 { "(bad)", { XX } },
4324 { "(bad)", { XX } },
4325 { "(bad)", { XX } },
4326 { "(bad)", { XX } },
4327 { "(bad)", { XX } },
4328 { "(bad)", { XX } },
4330 { "(bad)", { XX } },
4331 { "(bad)", { XX } },
4332 { "(bad)", { XX } },
4333 { "(bad)", { XX } },
4334 { "(bad)", { XX } },
4335 { "(bad)", { XX } },
4336 { "(bad)", { XX } },
4337 { "(bad)", { XX } },
4339 { "(bad)", { XX } },
4340 { "(bad)", { XX } },
4341 { "(bad)", { XX } },
4342 { "(bad)", { XX } },
4343 { "(bad)", { XX } },
4344 { "(bad)", { XX } },
4345 { "(bad)", { XX } },
4346 { "(bad)", { XX } },
4348 { "(bad)", { XX } },
4349 { "(bad)", { XX } },
4350 { "(bad)", { XX } },
4351 { "(bad)", { XX } },
4352 { "(bad)", { XX } },
4353 { "(bad)", { XX } },
4354 { "(bad)", { XX } },
4355 { "(bad)", { XX } },
4357 { "(bad)", { XX } },
4358 { "(bad)", { XX } },
4359 { "(bad)", { XX } },
4360 { "(bad)", { XX } },
4361 { "(bad)", { XX } },
4362 { "(bad)", { XX } },
4363 { "(bad)", { XX } },
4364 { "(bad)", { XX } },
4366 { "(bad)", { XX } },
4367 { "(bad)", { XX } },
4368 { "(bad)", { XX } },
4369 { "(bad)", { XX } },
4370 { "(bad)", { XX } },
4371 { "(bad)", { XX } },
4372 { "(bad)", { XX } },
4373 { "(bad)", { XX } },
4375 { "(bad)", { XX } },
4376 { "(bad)", { XX } },
4377 { "(bad)", { XX } },
4378 { "(bad)", { XX } },
4379 { "(bad)", { XX } },
4380 { "(bad)", { XX } },
4381 { "(bad)", { XX } },
4382 { "(bad)", { XX } },
4384 { "(bad)", { XX } },
4385 { "(bad)", { XX } },
4386 { "(bad)", { XX } },
4387 { "(bad)", { XX } },
4388 { "(bad)", { XX } },
4389 { "(bad)", { XX } },
4390 { "(bad)", { XX } },
4391 { "(bad)", { XX } },
4393 { "(bad)", { XX } },
4394 { "(bad)", { XX } },
4395 { "(bad)", { XX } },
4396 { "(bad)", { XX } },
4397 { "(bad)", { XX } },
4398 { "(bad)", { XX } },
4399 { "(bad)", { XX } },
4400 { "(bad)", { XX } },
4402 { "(bad)", { XX } },
4403 { "(bad)", { XX } },
4404 { "(bad)", { XX } },
4405 { "(bad)", { XX } },
4406 { "(bad)", { XX } },
4407 { "(bad)", { XX } },
4408 { "(bad)", { XX } },
4409 { "(bad)", { XX } },
4411 { "(bad)", { XX } },
4412 { "(bad)", { XX } },
4413 { "(bad)", { XX } },
4414 { "(bad)", { XX } },
4415 { "(bad)", { XX } },
4416 { "(bad)", { XX } },
4417 { "(bad)", { XX } },
4418 { "(bad)", { XX } },
4420 { "(bad)", { XX } },
4421 { "(bad)", { XX } },
4422 { "(bad)", { XX } },
4423 { "(bad)", { XX } },
4424 { "(bad)", { XX } },
4425 { "(bad)", { XX } },
4426 { "(bad)", { XX } },
4427 { "(bad)", { XX } },
4429 { "(bad)", { XX } },
4430 { "(bad)", { XX } },
4431 { "(bad)", { XX } },
4432 { "(bad)", { XX } },
4433 { "(bad)", { XX } },
4434 { "(bad)", { XX } },
4435 { "(bad)", { XX } },
4436 { "(bad)", { XX } },
4438 { "(bad)", { XX } },
4439 { "(bad)", { XX } },
4440 { "(bad)", { XX } },
4441 { "(bad)", { XX } },
4442 { "(bad)", { XX } },
4443 { "(bad)", { XX } },
4444 { "(bad)", { XX } },
4445 { "(bad)", { XX } },
4447 { "(bad)", { XX } },
4448 { "(bad)", { XX } },
4449 { "(bad)", { XX } },
4450 { "(bad)", { XX } },
4451 { "(bad)", { XX } },
4452 { "(bad)", { XX } },
4453 { "(bad)", { XX } },
4454 { "(bad)", { XX } },
4456 { "(bad)", { XX } },
4457 { "(bad)", { XX } },
4458 { "(bad)", { XX } },
4459 { "(bad)", { XX } },
4460 { "(bad)", { XX } },
4461 { "(bad)", { XX } },
4462 { "(bad)", { XX } },
4463 { "(bad)", { XX } },
4465 { "(bad)", { XX } },
4466 { "(bad)", { XX } },
4467 { "(bad)", { XX } },
4468 { "(bad)", { XX } },
4469 { "(bad)", { XX } },
4470 { "(bad)", { XX } },
4471 { "(bad)", { XX } },
4472 { "(bad)", { XX } },
4474 { "(bad)", { XX } },
4475 { "(bad)", { XX } },
4476 { "(bad)", { XX } },
4477 { "(bad)", { XX } },
4478 { "(bad)", { XX } },
4479 { "(bad)", { XX } },
4480 { "(bad)", { XX } },
4481 { "(bad)", { XX } },
4485 static const struct dis386 mod_table[][2] = {
4488 { "leaS", { Gv, M } },
4489 { "(bad)", { XX } },
4493 { "movlpX", { EXq, XM } },
4494 { "(bad)", { XX } },
4498 { "movhpX", { EXq, XM } },
4499 { "(bad)", { XX } },
4503 { "(bad)", { XX } },
4504 { "movZ", { Rm, Cm } },
4508 { "(bad)", { XX } },
4509 { "movZ", { Rm, Dm } },
4513 { "(bad)", { XX } },
4514 { "movZ", { Cm, Rm } },
4518 { "(bad)", { XX } },
4519 { "movZ", { Dm, Rm } },
4523 { THREE_BYTE_TABLE (THREE_BYTE_0F24) },
4524 { "movL", { Rd, Td } },
4528 { "(bad)", { XX } },
4529 { "movL", { Td, Rd } },
4533 { "lssS", { Gv, Mp } },
4534 { "(bad)", { XX } },
4538 { "lfsS", { Gv, Mp } },
4539 { "(bad)", { XX } },
4543 { "lgsS", { Gv, Mp } },
4544 { "(bad)", { XX } },
4547 /* MOD_0F01_REG_0 */
4548 { X86_64_TABLE (X86_64_0F01_REG_0) },
4549 { RM_TABLE (RM_0F01_REG_0) },
4552 /* MOD_0F01_REG_1 */
4553 { X86_64_TABLE (X86_64_0F01_REG_1) },
4554 { RM_TABLE (RM_0F01_REG_1) },
4557 /* MOD_0F01_REG_2 */
4558 { X86_64_TABLE (X86_64_0F01_REG_2) },
4559 { "(bad)", { XX } },
4562 /* MOD_0F01_REG_3 */
4563 { X86_64_TABLE (X86_64_0F01_REG_3) },
4564 { RM_TABLE (RM_0F01_REG_3) },
4567 /* MOD_0F01_REG_7 */
4568 { "invlpg", { Mb } },
4569 { RM_TABLE (RM_0F01_REG_7) },
4572 /* MOD_0F18_REG_0 */
4573 { "prefetchnta", { Mb } },
4574 { "(bad)", { XX } },
4577 /* MOD_0F18_REG_1 */
4578 { "prefetcht0", { Mb } },
4579 { "(bad)", { XX } },
4582 /* MOD_0F18_REG_2 */
4583 { "prefetcht1", { Mb } },
4584 { "(bad)", { XX } },
4587 /* MOD_0F18_REG_3 */
4588 { "prefetcht2", { Mb } },
4589 { "(bad)", { XX } },
4592 /* MOD_0F71_REG_2 */
4593 { "(bad)", { XX } },
4594 { "psrlw", { MS, Ib } },
4597 /* MOD_0F71_REG_4 */
4598 { "(bad)", { XX } },
4599 { "psraw", { MS, Ib } },
4602 /* MOD_0F71_REG_6 */
4603 { "(bad)", { XX } },
4604 { "psllw", { MS, Ib } },
4607 /* MOD_0F72_REG_2 */
4608 { "(bad)", { XX } },
4609 { "psrld", { MS, Ib } },
4612 /* MOD_0F72_REG_4 */
4613 { "(bad)", { XX } },
4614 { "psrad", { MS, Ib } },
4617 /* MOD_0F72_REG_6 */
4618 { "(bad)", { XX } },
4619 { "pslld", { MS, Ib } },
4622 /* MOD_0F73_REG_2 */
4623 { "(bad)", { XX } },
4624 { "psrlq", { MS, Ib } },
4627 /* MOD_0F73_REG_3 */
4628 { "(bad)", { XX } },
4629 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
4632 /* MOD_0F73_REG_6 */
4633 { "(bad)", { XX } },
4634 { "psllq", { MS, Ib } },
4637 /* MOD_0F73_REG_7 */
4638 { "(bad)", { XX } },
4639 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
4642 /* MOD_0FAE_REG_0 */
4643 { "fxsave", { M } },
4644 { "(bad)", { XX } },
4647 /* MOD_0FAE_REG_1 */
4648 { "fxrstor", { M } },
4649 { "(bad)", { XX } },
4652 /* MOD_0FAE_REG_2 */
4653 { "ldmxcsr", { Md } },
4654 { "(bad)", { XX } },
4657 /* MOD_0FAE_REG_3 */
4658 { "stmxcsr", { Md } },
4659 { "(bad)", { XX } },
4662 /* MOD_0FAE_REG_5 */
4663 { "(bad)", { XX } },
4664 { RM_TABLE (RM_0FAE_REG_5) },
4667 /* MOD_0FAE_REG_6 */
4668 { "(bad)", { XX } },
4669 { RM_TABLE (RM_0FAE_REG_6) },
4672 /* MOD_0FAE_REG_7 */
4673 { "clflush", { Mb } },
4674 { RM_TABLE (RM_0FAE_REG_7) },
4677 /* MOD_0FC7_REG_6 */
4678 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
4679 { "(bad)", { XX } },
4682 /* MOD_0FC7_REG_7 */
4683 { "vmptrst", { Mq } },
4684 { "(bad)", { XX } },
4687 /* MOD_0F12_PREFIX_0 */
4688 { "movlps", { XM, EXq } },
4689 { "movhlps", { XM, EXq } },
4692 /* MOD_0F16_PREFIX_0 */
4693 { "movhps", { XM, EXq } },
4694 { "movlhps", { XM, EXq } },
4697 /* MOD_0FF0_PREFIX_3 */
4698 { "lddqu", { XM, M } },
4699 { "(bad)", { XX } },
4703 { "bound{S|}", { Gv, Ma } },
4704 { "(bad)", { XX } },
4708 { "lesS", { Gv, Mp } },
4709 { "(bad)", { XX } },
4713 { "ldsS", { Gv, Mp } },
4714 { "(bad)", { XX } },
4718 static const struct dis386 rm_table[][8] = {
4721 { "(bad)", { XX } },
4722 { "vmcall", { Skip_MODRM } },
4723 { "vmlaunch", { Skip_MODRM } },
4724 { "vmresume", { Skip_MODRM } },
4725 { "vmxoff", { Skip_MODRM } },
4726 { "(bad)", { XX } },
4727 { "(bad)", { XX } },
4728 { "(bad)", { XX } },
4732 { "monitor", { { OP_Monitor, 0 } } },
4733 { "mwait", { { OP_Mwait, 0 } } },
4734 { "(bad)", { XX } },
4735 { "(bad)", { XX } },
4736 { "(bad)", { XX } },
4737 { "(bad)", { XX } },
4738 { "(bad)", { XX } },
4739 { "(bad)", { XX } },
4743 { "vmrun", { Skip_MODRM } },
4744 { "vmmcall", { Skip_MODRM } },
4745 { "vmload", { Skip_MODRM } },
4746 { "vmsave", { Skip_MODRM } },
4747 { "stgi", { Skip_MODRM } },
4748 { "clgi", { Skip_MODRM } },
4749 { "skinit", { Skip_MODRM } },
4750 { "invlpga", { Skip_MODRM } },
4754 { "swapgs", { Skip_MODRM } },
4755 { "rdtscp", { Skip_MODRM } },
4756 { "(bad)", { XX } },
4757 { "(bad)", { XX } },
4758 { "(bad)", { XX } },
4759 { "(bad)", { XX } },
4760 { "(bad)", { XX } },
4761 { "(bad)", { XX } },
4765 { "lfence", { Skip_MODRM } },
4766 { "(bad)", { XX } },
4767 { "(bad)", { XX } },
4768 { "(bad)", { XX } },
4769 { "(bad)", { XX } },
4770 { "(bad)", { XX } },
4771 { "(bad)", { XX } },
4772 { "(bad)", { XX } },
4776 { "mfence", { Skip_MODRM } },
4777 { "(bad)", { XX } },
4778 { "(bad)", { XX } },
4779 { "(bad)", { XX } },
4780 { "(bad)", { XX } },
4781 { "(bad)", { XX } },
4782 { "(bad)", { XX } },
4783 { "(bad)", { XX } },
4787 { "sfence", { Skip_MODRM } },
4788 { "(bad)", { XX } },
4789 { "(bad)", { XX } },
4790 { "(bad)", { XX } },
4791 { "(bad)", { XX } },
4792 { "(bad)", { XX } },
4793 { "(bad)", { XX } },
4794 { "(bad)", { XX } },
4798 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
4810 FETCH_DATA (the_info, codep + 1);
4814 /* REX prefixes family. */
4831 if (address_mode == mode_64bit)
4837 prefixes |= PREFIX_REPZ;
4840 prefixes |= PREFIX_REPNZ;
4843 prefixes |= PREFIX_LOCK;
4846 prefixes |= PREFIX_CS;
4849 prefixes |= PREFIX_SS;
4852 prefixes |= PREFIX_DS;
4855 prefixes |= PREFIX_ES;
4858 prefixes |= PREFIX_FS;
4861 prefixes |= PREFIX_GS;
4864 prefixes |= PREFIX_DATA;
4867 prefixes |= PREFIX_ADDR;
4870 /* fwait is really an instruction. If there are prefixes
4871 before the fwait, they belong to the fwait, *not* to the
4872 following instruction. */
4873 if (prefixes || rex)
4875 prefixes |= PREFIX_FWAIT;
4879 prefixes = PREFIX_FWAIT;
4884 /* Rex is ignored when followed by another prefix. */
4895 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
4899 prefix_name (int pref, int sizeflag)
4901 static const char *rexes [16] =
4906 "rex.XB", /* 0x43 */
4908 "rex.RB", /* 0x45 */
4909 "rex.RX", /* 0x46 */
4910 "rex.RXB", /* 0x47 */
4912 "rex.WB", /* 0x49 */
4913 "rex.WX", /* 0x4a */
4914 "rex.WXB", /* 0x4b */
4915 "rex.WR", /* 0x4c */
4916 "rex.WRB", /* 0x4d */
4917 "rex.WRX", /* 0x4e */
4918 "rex.WRXB", /* 0x4f */
4923 /* REX prefixes family. */
4940 return rexes [pref - 0x40];
4960 return (sizeflag & DFLAG) ? "data16" : "data32";
4962 if (address_mode == mode_64bit)
4963 return (sizeflag & AFLAG) ? "addr32" : "addr64";
4965 return (sizeflag & AFLAG) ? "addr16" : "addr32";
4973 static char op_out[MAX_OPERANDS][100];
4974 static int op_ad, op_index[MAX_OPERANDS];
4975 static int two_source_ops;
4976 static bfd_vma op_address[MAX_OPERANDS];
4977 static bfd_vma op_riprel[MAX_OPERANDS];
4978 static bfd_vma start_pc;
4981 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
4982 * (see topic "Redundant prefixes" in the "Differences from 8086"
4983 * section of the "Virtual 8086 Mode" chapter.)
4984 * 'pc' should be the address of this instruction, it will
4985 * be used to print the target address if this is a relative jump or call
4986 * The function returns the length of this instruction in bytes.
4989 static char intel_syntax;
4990 static char open_char;
4991 static char close_char;
4992 static char separator_char;
4993 static char scale_char;
4995 /* Here for backwards compatibility. When gdb stops using
4996 print_insn_i386_att and print_insn_i386_intel these functions can
4997 disappear, and print_insn_i386 be merged into print_insn. */
4999 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
5003 return print_insn (pc, info);
5007 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
5011 return print_insn (pc, info);
5015 print_insn_i386 (bfd_vma pc, disassemble_info *info)
5019 return print_insn (pc, info);
5023 print_i386_disassembler_options (FILE *stream)
5025 fprintf (stream, _("\n\
5026 The following i386/x86-64 specific disassembler options are supported for use\n\
5027 with the -M switch (multiple options should be separated by commas):\n"));
5029 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
5030 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
5031 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
5032 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
5033 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
5034 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
5035 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
5036 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
5037 fprintf (stream, _(" data32 Assume 32bit data size\n"));
5038 fprintf (stream, _(" data16 Assume 16bit data size\n"));
5039 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
5042 /* Get a pointer to struct dis386 with a valid name. */
5044 static const struct dis386 *
5045 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
5049 if (dp->name != NULL)
5052 switch (dp->op[0].bytemode)
5055 dp = ®_table[dp->op[1].bytemode][modrm.reg];
5059 index = modrm.mod == 0x3 ? 1 : 0;
5060 dp = &mod_table[dp->op[1].bytemode][index];
5064 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
5067 case USE_PREFIX_TABLE:
5069 used_prefixes |= (prefixes & PREFIX_REPZ);
5070 if (prefixes & PREFIX_REPZ)
5077 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
5079 used_prefixes |= (prefixes & PREFIX_REPNZ);
5080 if (prefixes & PREFIX_REPNZ)
5083 repnz_prefix = NULL;
5087 used_prefixes |= (prefixes & PREFIX_DATA);
5088 if (prefixes & PREFIX_DATA)
5095 dp = &prefix_table[dp->op[1].bytemode][index];
5098 case USE_X86_64_TABLE:
5099 index = address_mode == mode_64bit ? 1 : 0;
5100 dp = &x86_64_table[dp->op[1].bytemode][index];
5103 case USE_3BYTE_TABLE:
5104 FETCH_DATA (info, codep + 2);
5106 dp = &three_byte_table[dp->op[1].bytemode][index];
5107 modrm.mod = (*codep >> 6) & 3;
5108 modrm.reg = (*codep >> 3) & 7;
5109 modrm.rm = *codep & 7;
5113 oappend (INTERNAL_DISASSEMBLER_ERROR);
5117 if (dp->name != NULL)
5120 return get_valid_dis386 (dp, info);
5124 print_insn (bfd_vma pc, disassemble_info *info)
5126 const struct dis386 *dp;
5128 char *op_txt[MAX_OPERANDS];
5132 struct dis_private priv;
5134 char prefix_obuf[32];
5137 if (info->mach == bfd_mach_x86_64_intel_syntax
5138 || info->mach == bfd_mach_x86_64)
5139 address_mode = mode_64bit;
5141 address_mode = mode_32bit;
5143 if (intel_syntax == (char) -1)
5144 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
5145 || info->mach == bfd_mach_x86_64_intel_syntax);
5147 if (info->mach == bfd_mach_i386_i386
5148 || info->mach == bfd_mach_x86_64
5149 || info->mach == bfd_mach_i386_i386_intel_syntax
5150 || info->mach == bfd_mach_x86_64_intel_syntax)
5151 priv.orig_sizeflag = AFLAG | DFLAG;
5152 else if (info->mach == bfd_mach_i386_i8086)
5153 priv.orig_sizeflag = 0;
5157 for (p = info->disassembler_options; p != NULL; )
5159 if (CONST_STRNEQ (p, "x86-64"))
5161 address_mode = mode_64bit;
5162 priv.orig_sizeflag = AFLAG | DFLAG;
5164 else if (CONST_STRNEQ (p, "i386"))
5166 address_mode = mode_32bit;
5167 priv.orig_sizeflag = AFLAG | DFLAG;
5169 else if (CONST_STRNEQ (p, "i8086"))
5171 address_mode = mode_16bit;
5172 priv.orig_sizeflag = 0;
5174 else if (CONST_STRNEQ (p, "intel"))
5178 else if (CONST_STRNEQ (p, "att"))
5182 else if (CONST_STRNEQ (p, "addr"))
5184 if (address_mode == mode_64bit)
5186 if (p[4] == '3' && p[5] == '2')
5187 priv.orig_sizeflag &= ~AFLAG;
5188 else if (p[4] == '6' && p[5] == '4')
5189 priv.orig_sizeflag |= AFLAG;
5193 if (p[4] == '1' && p[5] == '6')
5194 priv.orig_sizeflag &= ~AFLAG;
5195 else if (p[4] == '3' && p[5] == '2')
5196 priv.orig_sizeflag |= AFLAG;
5199 else if (CONST_STRNEQ (p, "data"))
5201 if (p[4] == '1' && p[5] == '6')
5202 priv.orig_sizeflag &= ~DFLAG;
5203 else if (p[4] == '3' && p[5] == '2')
5204 priv.orig_sizeflag |= DFLAG;
5206 else if (CONST_STRNEQ (p, "suffix"))
5207 priv.orig_sizeflag |= SUFFIX_ALWAYS;
5209 p = strchr (p, ',');
5216 names64 = intel_names64;
5217 names32 = intel_names32;
5218 names16 = intel_names16;
5219 names8 = intel_names8;
5220 names8rex = intel_names8rex;
5221 names_seg = intel_names_seg;
5222 index64 = intel_index64;
5223 index32 = intel_index32;
5224 index16 = intel_index16;
5227 separator_char = '+';
5232 names64 = att_names64;
5233 names32 = att_names32;
5234 names16 = att_names16;
5235 names8 = att_names8;
5236 names8rex = att_names8rex;
5237 names_seg = att_names_seg;
5238 index64 = att_index64;
5239 index32 = att_index32;
5240 index16 = att_index16;
5243 separator_char = ',';
5247 /* The output looks better if we put 7 bytes on a line, since that
5248 puts most long word instructions on a single line. */
5249 info->bytes_per_line = 7;
5251 info->private_data = &priv;
5252 priv.max_fetched = priv.the_buffer;
5253 priv.insn_start = pc;
5256 for (i = 0; i < MAX_OPERANDS; ++i)
5264 start_codep = priv.the_buffer;
5265 codep = priv.the_buffer;
5267 if (setjmp (priv.bailout) != 0)
5271 /* Getting here means we tried for data but didn't get it. That
5272 means we have an incomplete instruction of some sort. Just
5273 print the first byte as a prefix or a .byte pseudo-op. */
5274 if (codep > priv.the_buffer)
5276 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
5278 (*info->fprintf_func) (info->stream, "%s", name);
5281 /* Just print the first byte as a .byte instruction. */
5282 (*info->fprintf_func) (info->stream, ".byte 0x%x",
5283 (unsigned int) priv.the_buffer[0]);
5296 sizeflag = priv.orig_sizeflag;
5298 FETCH_DATA (info, codep + 1);
5299 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
5301 if (((prefixes & PREFIX_FWAIT)
5302 && ((*codep < 0xd8) || (*codep > 0xdf)))
5303 || (rex && rex_used))
5307 /* fwait not followed by floating point instruction, or rex followed
5308 by other prefixes. Print the first prefix. */
5309 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
5311 name = INTERNAL_DISASSEMBLER_ERROR;
5312 (*info->fprintf_func) (info->stream, "%s", name);
5319 unsigned char threebyte;
5320 FETCH_DATA (info, codep + 2);
5321 threebyte = *++codep;
5322 dp = &dis386_twobyte[threebyte];
5323 need_modrm = twobyte_has_modrm[*codep];
5328 dp = &dis386[*codep];
5329 need_modrm = onebyte_has_modrm[*codep];
5333 if ((prefixes & PREFIX_REPZ))
5335 repz_prefix = "repz ";
5336 used_prefixes |= PREFIX_REPZ;
5341 if ((prefixes & PREFIX_REPNZ))
5343 repnz_prefix = "repnz ";
5344 used_prefixes |= PREFIX_REPNZ;
5347 repnz_prefix = NULL;
5349 if ((prefixes & PREFIX_LOCK))
5351 lock_prefix = "lock ";
5352 used_prefixes |= PREFIX_LOCK;
5358 if (prefixes & PREFIX_ADDR)
5361 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
5363 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
5364 addr_prefix = "addr32 ";
5366 addr_prefix = "addr16 ";
5367 used_prefixes |= PREFIX_ADDR;
5372 if ((prefixes & PREFIX_DATA))
5375 if (dp->op[2].bytemode == cond_jump_mode
5376 && dp->op[0].bytemode == v_mode
5379 if (sizeflag & DFLAG)
5380 data_prefix = "data32 ";
5382 data_prefix = "data16 ";
5383 used_prefixes |= PREFIX_DATA;
5389 FETCH_DATA (info, codep + 1);
5390 modrm.mod = (*codep >> 6) & 3;
5391 modrm.reg = (*codep >> 3) & 7;
5392 modrm.rm = *codep & 7;
5395 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
5401 dp = get_valid_dis386 (dp, info);
5402 if (dp != NULL && putop (dp->name, sizeflag) == 0)
5404 for (i = 0; i < MAX_OPERANDS; ++i)
5407 op_ad = MAX_OPERANDS - 1 - i;
5409 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
5414 /* See if any prefixes were not used. If so, print the first one
5415 separately. If we don't do this, we'll wind up printing an
5416 instruction stream which does not precisely correspond to the
5417 bytes we are disassembling. */
5418 if ((prefixes & ~used_prefixes) != 0)
5422 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
5424 name = INTERNAL_DISASSEMBLER_ERROR;
5425 (*info->fprintf_func) (info->stream, "%s", name);
5428 if (rex & ~rex_used)
5431 name = prefix_name (rex | 0x40, priv.orig_sizeflag);
5433 name = INTERNAL_DISASSEMBLER_ERROR;
5434 (*info->fprintf_func) (info->stream, "%s ", name);
5438 prefix_obufp = prefix_obuf;
5440 prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
5442 prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
5444 prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
5446 prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
5448 prefix_obufp = stpcpy (prefix_obufp, data_prefix);
5450 if (prefix_obuf[0] != 0)
5451 (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
5453 obufp = obuf + strlen (obuf);
5454 for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
5457 (*info->fprintf_func) (info->stream, "%s", obuf);
5459 /* The enter and bound instructions are printed with operands in the same
5460 order as the intel book; everything else is printed in reverse order. */
5461 if (intel_syntax || two_source_ops)
5465 for (i = 0; i < MAX_OPERANDS; ++i)
5466 op_txt[i] = op_out[i];
5468 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
5470 op_ad = op_index[i];
5471 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
5472 op_index[MAX_OPERANDS - 1 - i] = op_ad;
5473 riprel = op_riprel[i];
5474 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
5475 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
5480 for (i = 0; i < MAX_OPERANDS; ++i)
5481 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
5485 for (i = 0; i < MAX_OPERANDS; ++i)
5489 (*info->fprintf_func) (info->stream, ",");
5490 if (op_index[i] != -1 && !op_riprel[i])
5491 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
5493 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
5497 for (i = 0; i < MAX_OPERANDS; i++)
5498 if (op_index[i] != -1 && op_riprel[i])
5500 (*info->fprintf_func) (info->stream, " # ");
5501 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
5502 + op_address[op_index[i]]), info);
5505 return codep - priv.the_buffer;
5508 static const char *float_mem[] = {
5583 static const unsigned char float_mem_mode[] = {
5658 #define ST { OP_ST, 0 }
5659 #define STi { OP_STi, 0 }
5661 #define FGRPd9_2 NULL, { { NULL, 0 } }
5662 #define FGRPd9_4 NULL, { { NULL, 1 } }
5663 #define FGRPd9_5 NULL, { { NULL, 2 } }
5664 #define FGRPd9_6 NULL, { { NULL, 3 } }
5665 #define FGRPd9_7 NULL, { { NULL, 4 } }
5666 #define FGRPda_5 NULL, { { NULL, 5 } }
5667 #define FGRPdb_4 NULL, { { NULL, 6 } }
5668 #define FGRPde_3 NULL, { { NULL, 7 } }
5669 #define FGRPdf_4 NULL, { { NULL, 8 } }
5671 static const struct dis386 float_reg[][8] = {
5674 { "fadd", { ST, STi } },
5675 { "fmul", { ST, STi } },
5676 { "fcom", { STi } },
5677 { "fcomp", { STi } },
5678 { "fsub", { ST, STi } },
5679 { "fsubr", { ST, STi } },
5680 { "fdiv", { ST, STi } },
5681 { "fdivr", { ST, STi } },
5686 { "fxch", { STi } },
5688 { "(bad)", { XX } },
5696 { "fcmovb", { ST, STi } },
5697 { "fcmove", { ST, STi } },
5698 { "fcmovbe",{ ST, STi } },
5699 { "fcmovu", { ST, STi } },
5700 { "(bad)", { XX } },
5702 { "(bad)", { XX } },
5703 { "(bad)", { XX } },
5707 { "fcmovnb",{ ST, STi } },
5708 { "fcmovne",{ ST, STi } },
5709 { "fcmovnbe",{ ST, STi } },
5710 { "fcmovnu",{ ST, STi } },
5712 { "fucomi", { ST, STi } },
5713 { "fcomi", { ST, STi } },
5714 { "(bad)", { XX } },
5718 { "fadd", { STi, ST } },
5719 { "fmul", { STi, ST } },
5720 { "(bad)", { XX } },
5721 { "(bad)", { XX } },
5723 { "fsub", { STi, ST } },
5724 { "fsubr", { STi, ST } },
5725 { "fdiv", { STi, ST } },
5726 { "fdivr", { STi, ST } },
5728 { "fsubr", { STi, ST } },
5729 { "fsub", { STi, ST } },
5730 { "fdivr", { STi, ST } },
5731 { "fdiv", { STi, ST } },
5736 { "ffree", { STi } },
5737 { "(bad)", { XX } },
5739 { "fstp", { STi } },
5740 { "fucom", { STi } },
5741 { "fucomp", { STi } },
5742 { "(bad)", { XX } },
5743 { "(bad)", { XX } },
5747 { "faddp", { STi, ST } },
5748 { "fmulp", { STi, ST } },
5749 { "(bad)", { XX } },
5752 { "fsubp", { STi, ST } },
5753 { "fsubrp", { STi, ST } },
5754 { "fdivp", { STi, ST } },
5755 { "fdivrp", { STi, ST } },
5757 { "fsubrp", { STi, ST } },
5758 { "fsubp", { STi, ST } },
5759 { "fdivrp", { STi, ST } },
5760 { "fdivp", { STi, ST } },
5765 { "ffreep", { STi } },
5766 { "(bad)", { XX } },
5767 { "(bad)", { XX } },
5768 { "(bad)", { XX } },
5770 { "fucomip", { ST, STi } },
5771 { "fcomip", { ST, STi } },
5772 { "(bad)", { XX } },
5776 static char *fgrps[][8] = {
5779 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5784 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
5789 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
5794 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
5799 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
5804 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5809 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
5810 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
5815 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5820 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5825 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
5826 int sizeflag ATTRIBUTE_UNUSED)
5828 /* Skip mod/rm byte. */
5834 dofloat (int sizeflag)
5836 const struct dis386 *dp;
5837 unsigned char floatop;
5839 floatop = codep[-1];
5843 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
5845 putop (float_mem[fp_indx], sizeflag);
5848 OP_E (float_mem_mode[fp_indx], sizeflag);
5851 /* Skip mod/rm byte. */
5855 dp = &float_reg[floatop - 0xd8][modrm.reg];
5856 if (dp->name == NULL)
5858 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
5860 /* Instruction fnstsw is only one with strange arg. */
5861 if (floatop == 0xdf && codep[-1] == 0xe0)
5862 strcpy (op_out[0], names16[0]);
5866 putop (dp->name, sizeflag);
5871 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
5876 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
5881 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
5883 oappend ("%st" + intel_syntax);
5887 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
5889 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
5890 oappend (scratchbuf + intel_syntax);
5893 /* Capital letters in template are macros. */
5895 putop (const char *template, int sizeflag)
5900 for (p = template; *p; p++)
5912 if (*p == '}' || *p == '\0')
5931 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
5937 if (sizeflag & SUFFIX_ALWAYS)
5941 if (intel_syntax && !alt)
5943 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
5945 if (sizeflag & DFLAG)
5946 *obufp++ = intel_syntax ? 'd' : 'l';
5948 *obufp++ = intel_syntax ? 'w' : 's';
5949 used_prefixes |= (prefixes & PREFIX_DATA);
5953 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
5960 else if (sizeflag & DFLAG)
5961 *obufp++ = intel_syntax ? 'd' : 'l';
5964 used_prefixes |= (prefixes & PREFIX_DATA);
5969 case 'E': /* For jcxz/jecxz */
5970 if (address_mode == mode_64bit)
5972 if (sizeflag & AFLAG)
5978 if (sizeflag & AFLAG)
5980 used_prefixes |= (prefixes & PREFIX_ADDR);
5985 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
5987 if (sizeflag & AFLAG)
5988 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
5990 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
5991 used_prefixes |= (prefixes & PREFIX_ADDR);
5995 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
5997 if ((rex & REX_W) || (sizeflag & DFLAG))
6002 used_prefixes |= (prefixes & PREFIX_DATA);
6007 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
6008 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
6010 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
6013 if (prefixes & PREFIX_DS)
6034 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
6043 if (sizeflag & SUFFIX_ALWAYS)
6047 if ((prefixes & PREFIX_FWAIT) == 0)
6050 used_prefixes |= PREFIX_FWAIT;
6056 else if (intel_syntax && (sizeflag & DFLAG))
6061 used_prefixes |= (prefixes & PREFIX_DATA);
6066 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6075 if ((prefixes & PREFIX_DATA)
6077 || (sizeflag & SUFFIX_ALWAYS))
6084 if (sizeflag & DFLAG)
6089 used_prefixes |= (prefixes & PREFIX_DATA);
6095 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6097 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
6103 if (intel_syntax && !alt)
6106 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
6112 if (sizeflag & DFLAG)
6113 *obufp++ = intel_syntax ? 'd' : 'l';
6117 used_prefixes |= (prefixes & PREFIX_DATA);
6124 else if (sizeflag & DFLAG)
6133 if (intel_syntax && !p[1]
6134 && ((rex & REX_W) || (sizeflag & DFLAG)))
6137 used_prefixes |= (prefixes & PREFIX_DATA);
6142 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6144 if (sizeflag & SUFFIX_ALWAYS)
6152 if (sizeflag & SUFFIX_ALWAYS)
6158 if (sizeflag & DFLAG)
6162 used_prefixes |= (prefixes & PREFIX_DATA);
6167 if (prefixes & PREFIX_DATA)
6171 used_prefixes |= (prefixes & PREFIX_DATA);
6174 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
6182 /* implicit operand size 'l' for i386 or 'q' for x86-64 */
6184 /* operand size flag for cwtl, cbtw */
6193 else if (sizeflag & DFLAG)
6198 used_prefixes |= (prefixes & PREFIX_DATA);
6208 oappend (const char *s)
6211 obufp += strlen (s);
6217 if (prefixes & PREFIX_CS)
6219 used_prefixes |= PREFIX_CS;
6220 oappend ("%cs:" + intel_syntax);
6222 if (prefixes & PREFIX_DS)
6224 used_prefixes |= PREFIX_DS;
6225 oappend ("%ds:" + intel_syntax);
6227 if (prefixes & PREFIX_SS)
6229 used_prefixes |= PREFIX_SS;
6230 oappend ("%ss:" + intel_syntax);
6232 if (prefixes & PREFIX_ES)
6234 used_prefixes |= PREFIX_ES;
6235 oappend ("%es:" + intel_syntax);
6237 if (prefixes & PREFIX_FS)
6239 used_prefixes |= PREFIX_FS;
6240 oappend ("%fs:" + intel_syntax);
6242 if (prefixes & PREFIX_GS)
6244 used_prefixes |= PREFIX_GS;
6245 oappend ("%gs:" + intel_syntax);
6250 OP_indirE (int bytemode, int sizeflag)
6254 OP_E (bytemode, sizeflag);
6258 print_operand_value (char *buf, int hex, bfd_vma disp)
6260 if (address_mode == mode_64bit)
6268 sprintf_vma (tmp, disp);
6269 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
6270 strcpy (buf + 2, tmp + i);
6274 bfd_signed_vma v = disp;
6281 /* Check for possible overflow on 0x8000000000000000. */
6284 strcpy (buf, "9223372036854775808");
6298 tmp[28 - i] = (v % 10) + '0';
6302 strcpy (buf, tmp + 29 - i);
6308 sprintf (buf, "0x%x", (unsigned int) disp);
6310 sprintf (buf, "%d", (int) disp);
6314 /* Put DISP in BUF as signed hex number. */
6317 print_displacement (char *buf, bfd_vma disp)
6319 bfd_signed_vma val = disp;
6328 /* Check for possible overflow. */
6331 switch (address_mode)
6334 strcpy (buf + j, "0x8000000000000000");
6337 strcpy (buf + j, "0x80000000");
6340 strcpy (buf + j, "0x8000");
6350 sprintf_vma (tmp, val);
6351 for (i = 0; tmp[i] == '0'; i++)
6355 strcpy (buf + j, tmp + i);
6359 intel_operand_size (int bytemode, int sizeflag)
6365 oappend ("BYTE PTR ");
6369 oappend ("WORD PTR ");
6372 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6374 oappend ("QWORD PTR ");
6375 used_prefixes |= (prefixes & PREFIX_DATA);
6383 oappend ("QWORD PTR ");
6384 else if ((sizeflag & DFLAG) || bytemode == dq_mode)
6385 oappend ("DWORD PTR ");
6387 oappend ("WORD PTR ");
6388 used_prefixes |= (prefixes & PREFIX_DATA);
6391 if ((rex & REX_W) || (sizeflag & DFLAG))
6393 oappend ("WORD PTR ");
6395 used_prefixes |= (prefixes & PREFIX_DATA);
6399 oappend ("DWORD PTR ");
6402 oappend ("QWORD PTR ");
6405 if (address_mode == mode_64bit)
6406 oappend ("QWORD PTR ");
6408 oappend ("DWORD PTR ");
6411 if (sizeflag & DFLAG)
6412 oappend ("FWORD PTR ");
6414 oappend ("DWORD PTR ");
6415 used_prefixes |= (prefixes & PREFIX_DATA);
6418 oappend ("TBYTE PTR ");
6421 oappend ("XMMWORD PTR ");
6424 oappend ("OWORD PTR ");
6432 OP_E_extended (int bytemode, int sizeflag, int has_drex)
6441 /* Skip mod/rm byte. */
6452 oappend (names8rex[modrm.rm + add]);
6454 oappend (names8[modrm.rm + add]);
6457 oappend (names16[modrm.rm + add]);
6460 oappend (names32[modrm.rm + add]);
6463 oappend (names64[modrm.rm + add]);
6466 if (address_mode == mode_64bit)
6467 oappend (names64[modrm.rm + add]);
6469 oappend (names32[modrm.rm + add]);
6472 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6474 oappend (names64[modrm.rm + add]);
6475 used_prefixes |= (prefixes & PREFIX_DATA);
6487 oappend (names64[modrm.rm + add]);
6488 else if ((sizeflag & DFLAG) || bytemode != v_mode)
6489 oappend (names32[modrm.rm + add]);
6491 oappend (names16[modrm.rm + add]);
6492 used_prefixes |= (prefixes & PREFIX_DATA);
6497 oappend (INTERNAL_DISASSEMBLER_ERROR);
6505 intel_operand_size (bytemode, sizeflag);
6508 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
6510 /* 32/64 bit address mode */
6528 FETCH_DATA (the_info, codep + 1);
6529 index = (*codep >> 3) & 7;
6530 scale = (*codep >> 6) & 3;
6535 haveindex = index != 4;
6540 /* If we have a DREX byte, skip it now
6541 (it has already been handled) */
6544 FETCH_DATA (the_info, codep + 1);
6551 if ((base & 7) == 5)
6554 if (address_mode == mode_64bit && !havesib)
6560 FETCH_DATA (the_info, codep + 1);
6562 if ((disp & 0x80) != 0)
6570 /* In 32bit mode, we need index register to tell [offset] from
6571 [eiz*1 + offset]. */
6572 needindex = (havesib
6575 && address_mode == mode_32bit);
6576 havedisp = (havebase
6578 || (havesib && (haveindex || scale != 0)));
6581 if (modrm.mod != 0 || (base & 7) == 5)
6583 if (havedisp || riprel)
6584 print_displacement (scratchbuf, disp);
6586 print_operand_value (scratchbuf, 1, disp);
6587 oappend (scratchbuf);
6591 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
6595 if (havebase || haveindex || riprel)
6596 used_prefixes |= PREFIX_ADDR;
6598 if (havedisp || (intel_syntax && riprel))
6600 *obufp++ = open_char;
6601 if (intel_syntax && riprel)
6604 oappend (sizeflag & AFLAG ? "rip" : "eip");
6608 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
6609 ? names64[base] : names32[base]);
6612 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
6613 print index to tell base + index from base. */
6617 || (havebase && base != ESP_REG_NUM))
6619 if (!intel_syntax || havebase)
6621 *obufp++ = separator_char;
6625 oappend (address_mode == mode_64bit
6626 && (sizeflag & AFLAG)
6627 ? names64[index] : names32[index]);
6629 oappend (address_mode == mode_64bit
6630 && (sizeflag & AFLAG)
6631 ? index64 : index32);
6633 *obufp++ = scale_char;
6635 sprintf (scratchbuf, "%d", 1 << scale);
6636 oappend (scratchbuf);
6640 && (disp || modrm.mod != 0 || (base & 7) == 5))
6642 if (!havedisp || (bfd_signed_vma) disp >= 0)
6647 else if (modrm.mod != 1)
6651 disp = - (bfd_signed_vma) disp;
6655 print_displacement (scratchbuf, disp);
6657 print_operand_value (scratchbuf, 1, disp);
6658 oappend (scratchbuf);
6661 *obufp++ = close_char;
6664 else if (intel_syntax)
6666 if (modrm.mod != 0 || (base & 7) == 5)
6668 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
6669 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
6673 oappend (names_seg[ds_reg - es_reg]);
6676 print_operand_value (scratchbuf, 1, disp);
6677 oappend (scratchbuf);
6682 { /* 16 bit address mode */
6689 if ((disp & 0x8000) != 0)
6694 FETCH_DATA (the_info, codep + 1);
6696 if ((disp & 0x80) != 0)
6701 if ((disp & 0x8000) != 0)
6707 if (modrm.mod != 0 || modrm.rm == 6)
6709 print_displacement (scratchbuf, disp);
6710 oappend (scratchbuf);
6713 if (modrm.mod != 0 || modrm.rm != 6)
6715 *obufp++ = open_char;
6717 oappend (index16[modrm.rm]);
6719 && (disp || modrm.mod != 0 || modrm.rm == 6))
6721 if ((bfd_signed_vma) disp >= 0)
6726 else if (modrm.mod != 1)
6730 disp = - (bfd_signed_vma) disp;
6733 print_displacement (scratchbuf, disp);
6734 oappend (scratchbuf);
6737 *obufp++ = close_char;
6740 else if (intel_syntax)
6742 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
6743 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
6747 oappend (names_seg[ds_reg - es_reg]);
6750 print_operand_value (scratchbuf, 1, disp & 0xffff);
6751 oappend (scratchbuf);
6757 OP_E (int bytemode, int sizeflag)
6759 OP_E_extended (bytemode, sizeflag, 0);
6764 OP_G (int bytemode, int sizeflag)
6775 oappend (names8rex[modrm.reg + add]);
6777 oappend (names8[modrm.reg + add]);
6780 oappend (names16[modrm.reg + add]);
6783 oappend (names32[modrm.reg + add]);
6786 oappend (names64[modrm.reg + add]);
6795 oappend (names64[modrm.reg + add]);
6796 else if ((sizeflag & DFLAG) || bytemode != v_mode)
6797 oappend (names32[modrm.reg + add]);
6799 oappend (names16[modrm.reg + add]);
6800 used_prefixes |= (prefixes & PREFIX_DATA);
6803 if (address_mode == mode_64bit)
6804 oappend (names64[modrm.reg + add]);
6806 oappend (names32[modrm.reg + add]);
6809 oappend (INTERNAL_DISASSEMBLER_ERROR);
6822 FETCH_DATA (the_info, codep + 8);
6823 a = *codep++ & 0xff;
6824 a |= (*codep++ & 0xff) << 8;
6825 a |= (*codep++ & 0xff) << 16;
6826 a |= (*codep++ & 0xff) << 24;
6827 b = *codep++ & 0xff;
6828 b |= (*codep++ & 0xff) << 8;
6829 b |= (*codep++ & 0xff) << 16;
6830 b |= (*codep++ & 0xff) << 24;
6831 x = a + ((bfd_vma) b << 32);
6839 static bfd_signed_vma
6842 bfd_signed_vma x = 0;
6844 FETCH_DATA (the_info, codep + 4);
6845 x = *codep++ & (bfd_signed_vma) 0xff;
6846 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
6847 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
6848 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
6852 static bfd_signed_vma
6855 bfd_signed_vma x = 0;
6857 FETCH_DATA (the_info, codep + 4);
6858 x = *codep++ & (bfd_signed_vma) 0xff;
6859 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
6860 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
6861 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
6863 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
6873 FETCH_DATA (the_info, codep + 2);
6874 x = *codep++ & 0xff;
6875 x |= (*codep++ & 0xff) << 8;
6880 set_op (bfd_vma op, int riprel)
6882 op_index[op_ad] = op_ad;
6883 if (address_mode == mode_64bit)
6885 op_address[op_ad] = op;
6886 op_riprel[op_ad] = riprel;
6890 /* Mask to get a 32-bit address. */
6891 op_address[op_ad] = op & 0xffffffff;
6892 op_riprel[op_ad] = riprel & 0xffffffff;
6897 OP_REG (int code, int sizeflag)
6909 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
6910 case sp_reg: case bp_reg: case si_reg: case di_reg:
6911 s = names16[code - ax_reg + add];
6913 case es_reg: case ss_reg: case cs_reg:
6914 case ds_reg: case fs_reg: case gs_reg:
6915 s = names_seg[code - es_reg + add];
6917 case al_reg: case ah_reg: case cl_reg: case ch_reg:
6918 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
6921 s = names8rex[code - al_reg + add];
6923 s = names8[code - al_reg];
6925 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
6926 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
6927 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6929 s = names64[code - rAX_reg + add];
6932 code += eAX_reg - rAX_reg;
6934 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
6935 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
6938 s = names64[code - eAX_reg + add];
6939 else if (sizeflag & DFLAG)
6940 s = names32[code - eAX_reg + add];
6942 s = names16[code - eAX_reg + add];
6943 used_prefixes |= (prefixes & PREFIX_DATA);
6946 s = INTERNAL_DISASSEMBLER_ERROR;
6953 OP_IMREG (int code, int sizeflag)
6965 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
6966 case sp_reg: case bp_reg: case si_reg: case di_reg:
6967 s = names16[code - ax_reg];
6969 case es_reg: case ss_reg: case cs_reg:
6970 case ds_reg: case fs_reg: case gs_reg:
6971 s = names_seg[code - es_reg];
6973 case al_reg: case ah_reg: case cl_reg: case ch_reg:
6974 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
6977 s = names8rex[code - al_reg];
6979 s = names8[code - al_reg];
6981 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
6982 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
6985 s = names64[code - eAX_reg];
6986 else if (sizeflag & DFLAG)
6987 s = names32[code - eAX_reg];
6989 s = names16[code - eAX_reg];
6990 used_prefixes |= (prefixes & PREFIX_DATA);
6993 if ((rex & REX_W) || (sizeflag & DFLAG))
6998 used_prefixes |= (prefixes & PREFIX_DATA);
7001 s = INTERNAL_DISASSEMBLER_ERROR;
7008 OP_I (int bytemode, int sizeflag)
7011 bfd_signed_vma mask = -1;
7016 FETCH_DATA (the_info, codep + 1);
7021 if (address_mode == mode_64bit)
7031 else if (sizeflag & DFLAG)
7041 used_prefixes |= (prefixes & PREFIX_DATA);
7052 oappend (INTERNAL_DISASSEMBLER_ERROR);
7057 scratchbuf[0] = '$';
7058 print_operand_value (scratchbuf + 1, 1, op);
7059 oappend (scratchbuf + intel_syntax);
7060 scratchbuf[0] = '\0';
7064 OP_I64 (int bytemode, int sizeflag)
7067 bfd_signed_vma mask = -1;
7069 if (address_mode != mode_64bit)
7071 OP_I (bytemode, sizeflag);
7078 FETCH_DATA (the_info, codep + 1);
7086 else if (sizeflag & DFLAG)
7096 used_prefixes |= (prefixes & PREFIX_DATA);
7103 oappend (INTERNAL_DISASSEMBLER_ERROR);
7108 scratchbuf[0] = '$';
7109 print_operand_value (scratchbuf + 1, 1, op);
7110 oappend (scratchbuf + intel_syntax);
7111 scratchbuf[0] = '\0';
7115 OP_sI (int bytemode, int sizeflag)
7118 bfd_signed_vma mask = -1;
7123 FETCH_DATA (the_info, codep + 1);
7125 if ((op & 0x80) != 0)
7133 else if (sizeflag & DFLAG)
7142 if ((op & 0x8000) != 0)
7145 used_prefixes |= (prefixes & PREFIX_DATA);
7150 if ((op & 0x8000) != 0)
7154 oappend (INTERNAL_DISASSEMBLER_ERROR);
7158 scratchbuf[0] = '$';
7159 print_operand_value (scratchbuf + 1, 1, op);
7160 oappend (scratchbuf + intel_syntax);
7164 OP_J (int bytemode, int sizeflag)
7168 bfd_vma segment = 0;
7173 FETCH_DATA (the_info, codep + 1);
7175 if ((disp & 0x80) != 0)
7179 if ((sizeflag & DFLAG) || (rex & REX_W))
7184 if ((disp & 0x8000) != 0)
7186 /* In 16bit mode, address is wrapped around at 64k within
7187 the same segment. Otherwise, a data16 prefix on a jump
7188 instruction means that the pc is masked to 16 bits after
7189 the displacement is added! */
7191 if ((prefixes & PREFIX_DATA) == 0)
7192 segment = ((start_pc + codep - start_codep)
7193 & ~((bfd_vma) 0xffff));
7195 used_prefixes |= (prefixes & PREFIX_DATA);
7198 oappend (INTERNAL_DISASSEMBLER_ERROR);
7201 disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
7203 print_operand_value (scratchbuf, 1, disp);
7204 oappend (scratchbuf);
7208 OP_SEG (int bytemode, int sizeflag)
7210 if (bytemode == w_mode)
7211 oappend (names_seg[modrm.reg]);
7213 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
7217 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
7221 if (sizeflag & DFLAG)
7231 used_prefixes |= (prefixes & PREFIX_DATA);
7233 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
7235 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
7236 oappend (scratchbuf);
7240 OP_OFF (int bytemode, int sizeflag)
7244 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
7245 intel_operand_size (bytemode, sizeflag);
7248 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
7255 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
7256 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
7258 oappend (names_seg[ds_reg - es_reg]);
7262 print_operand_value (scratchbuf, 1, off);
7263 oappend (scratchbuf);
7267 OP_OFF64 (int bytemode, int sizeflag)
7271 if (address_mode != mode_64bit
7272 || (prefixes & PREFIX_ADDR))
7274 OP_OFF (bytemode, sizeflag);
7278 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
7279 intel_operand_size (bytemode, sizeflag);
7286 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
7287 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
7289 oappend (names_seg[ds_reg - es_reg]);
7293 print_operand_value (scratchbuf, 1, off);
7294 oappend (scratchbuf);
7298 ptr_reg (int code, int sizeflag)
7302 *obufp++ = open_char;
7303 used_prefixes |= (prefixes & PREFIX_ADDR);
7304 if (address_mode == mode_64bit)
7306 if (!(sizeflag & AFLAG))
7307 s = names32[code - eAX_reg];
7309 s = names64[code - eAX_reg];
7311 else if (sizeflag & AFLAG)
7312 s = names32[code - eAX_reg];
7314 s = names16[code - eAX_reg];
7316 *obufp++ = close_char;
7321 OP_ESreg (int code, int sizeflag)
7327 case 0x6d: /* insw/insl */
7328 intel_operand_size (z_mode, sizeflag);
7330 case 0xa5: /* movsw/movsl/movsq */
7331 case 0xa7: /* cmpsw/cmpsl/cmpsq */
7332 case 0xab: /* stosw/stosl */
7333 case 0xaf: /* scasw/scasl */
7334 intel_operand_size (v_mode, sizeflag);
7337 intel_operand_size (b_mode, sizeflag);
7340 oappend ("%es:" + intel_syntax);
7341 ptr_reg (code, sizeflag);
7345 OP_DSreg (int code, int sizeflag)
7351 case 0x6f: /* outsw/outsl */
7352 intel_operand_size (z_mode, sizeflag);
7354 case 0xa5: /* movsw/movsl/movsq */
7355 case 0xa7: /* cmpsw/cmpsl/cmpsq */
7356 case 0xad: /* lodsw/lodsl/lodsq */
7357 intel_operand_size (v_mode, sizeflag);
7360 intel_operand_size (b_mode, sizeflag);
7370 prefixes |= PREFIX_DS;
7372 ptr_reg (code, sizeflag);
7376 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
7384 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
7387 used_prefixes |= PREFIX_LOCK;
7392 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
7393 oappend (scratchbuf + intel_syntax);
7397 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
7406 sprintf (scratchbuf, "db%d", modrm.reg + add);
7408 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
7409 oappend (scratchbuf);
7413 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
7415 sprintf (scratchbuf, "%%tr%d", modrm.reg);
7416 oappend (scratchbuf + intel_syntax);
7420 OP_R (int bytemode, int sizeflag)
7423 OP_E (bytemode, sizeflag);
7429 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
7431 used_prefixes |= (prefixes & PREFIX_DATA);
7432 if (prefixes & PREFIX_DATA)
7440 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
7443 sprintf (scratchbuf, "%%mm%d", modrm.reg);
7444 oappend (scratchbuf + intel_syntax);
7448 OP_XMM (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
7456 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
7457 oappend (scratchbuf + intel_syntax);
7461 OP_EM (int bytemode, int sizeflag)
7465 if (intel_syntax && bytemode == v_mode)
7467 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
7468 used_prefixes |= (prefixes & PREFIX_DATA);
7470 OP_E (bytemode, sizeflag);
7474 /* Skip mod/rm byte. */
7477 used_prefixes |= (prefixes & PREFIX_DATA);
7478 if (prefixes & PREFIX_DATA)
7487 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
7490 sprintf (scratchbuf, "%%mm%d", modrm.rm);
7491 oappend (scratchbuf + intel_syntax);
7494 /* cvt* are the only instructions in sse2 which have
7495 both SSE and MMX operands and also have 0x66 prefix
7496 in their opcode. 0x66 was originally used to differentiate
7497 between SSE and MMX instruction(operands). So we have to handle the
7498 cvt* separately using OP_EMC and OP_MXC */
7500 OP_EMC (int bytemode, int sizeflag)
7504 if (intel_syntax && bytemode == v_mode)
7506 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
7507 used_prefixes |= (prefixes & PREFIX_DATA);
7509 OP_E (bytemode, sizeflag);
7513 /* Skip mod/rm byte. */
7516 used_prefixes |= (prefixes & PREFIX_DATA);
7517 sprintf (scratchbuf, "%%mm%d", modrm.rm);
7518 oappend (scratchbuf + intel_syntax);
7522 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
7524 used_prefixes |= (prefixes & PREFIX_DATA);
7525 sprintf (scratchbuf, "%%mm%d", modrm.reg);
7526 oappend (scratchbuf + intel_syntax);
7530 OP_EX (int bytemode, int sizeflag)
7535 OP_E (bytemode, sizeflag);
7544 /* Skip mod/rm byte. */
7547 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
7548 oappend (scratchbuf + intel_syntax);
7552 OP_MS (int bytemode, int sizeflag)
7555 OP_EM (bytemode, sizeflag);
7561 OP_XS (int bytemode, int sizeflag)
7564 OP_EX (bytemode, sizeflag);
7570 OP_M (int bytemode, int sizeflag)
7573 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
7576 OP_E (bytemode, sizeflag);
7580 OP_0f07 (int bytemode, int sizeflag)
7582 if (modrm.mod != 3 || modrm.rm != 0)
7585 OP_E (bytemode, sizeflag);
7588 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
7589 32bit mode and "xchg %rax,%rax" in 64bit mode. */
7592 NOP_Fixup1 (int bytemode, int sizeflag)
7594 if ((prefixes & PREFIX_DATA) != 0
7597 && address_mode == mode_64bit))
7598 OP_REG (bytemode, sizeflag);
7600 strcpy (obuf, "nop");
7604 NOP_Fixup2 (int bytemode, int sizeflag)
7606 if ((prefixes & PREFIX_DATA) != 0
7609 && address_mode == mode_64bit))
7610 OP_IMREG (bytemode, sizeflag);
7613 static const char *const Suffix3DNow[] = {
7614 /* 00 */ NULL, NULL, NULL, NULL,
7615 /* 04 */ NULL, NULL, NULL, NULL,
7616 /* 08 */ NULL, NULL, NULL, NULL,
7617 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
7618 /* 10 */ NULL, NULL, NULL, NULL,
7619 /* 14 */ NULL, NULL, NULL, NULL,
7620 /* 18 */ NULL, NULL, NULL, NULL,
7621 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
7622 /* 20 */ NULL, NULL, NULL, NULL,
7623 /* 24 */ NULL, NULL, NULL, NULL,
7624 /* 28 */ NULL, NULL, NULL, NULL,
7625 /* 2C */ NULL, NULL, NULL, NULL,
7626 /* 30 */ NULL, NULL, NULL, NULL,
7627 /* 34 */ NULL, NULL, NULL, NULL,
7628 /* 38 */ NULL, NULL, NULL, NULL,
7629 /* 3C */ NULL, NULL, NULL, NULL,
7630 /* 40 */ NULL, NULL, NULL, NULL,
7631 /* 44 */ NULL, NULL, NULL, NULL,
7632 /* 48 */ NULL, NULL, NULL, NULL,
7633 /* 4C */ NULL, NULL, NULL, NULL,
7634 /* 50 */ NULL, NULL, NULL, NULL,
7635 /* 54 */ NULL, NULL, NULL, NULL,
7636 /* 58 */ NULL, NULL, NULL, NULL,
7637 /* 5C */ NULL, NULL, NULL, NULL,
7638 /* 60 */ NULL, NULL, NULL, NULL,
7639 /* 64 */ NULL, NULL, NULL, NULL,
7640 /* 68 */ NULL, NULL, NULL, NULL,
7641 /* 6C */ NULL, NULL, NULL, NULL,
7642 /* 70 */ NULL, NULL, NULL, NULL,
7643 /* 74 */ NULL, NULL, NULL, NULL,
7644 /* 78 */ NULL, NULL, NULL, NULL,
7645 /* 7C */ NULL, NULL, NULL, NULL,
7646 /* 80 */ NULL, NULL, NULL, NULL,
7647 /* 84 */ NULL, NULL, NULL, NULL,
7648 /* 88 */ NULL, NULL, "pfnacc", NULL,
7649 /* 8C */ NULL, NULL, "pfpnacc", NULL,
7650 /* 90 */ "pfcmpge", NULL, NULL, NULL,
7651 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
7652 /* 98 */ NULL, NULL, "pfsub", NULL,
7653 /* 9C */ NULL, NULL, "pfadd", NULL,
7654 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
7655 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
7656 /* A8 */ NULL, NULL, "pfsubr", NULL,
7657 /* AC */ NULL, NULL, "pfacc", NULL,
7658 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
7659 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
7660 /* B8 */ NULL, NULL, NULL, "pswapd",
7661 /* BC */ NULL, NULL, NULL, "pavgusb",
7662 /* C0 */ NULL, NULL, NULL, NULL,
7663 /* C4 */ NULL, NULL, NULL, NULL,
7664 /* C8 */ NULL, NULL, NULL, NULL,
7665 /* CC */ NULL, NULL, NULL, NULL,
7666 /* D0 */ NULL, NULL, NULL, NULL,
7667 /* D4 */ NULL, NULL, NULL, NULL,
7668 /* D8 */ NULL, NULL, NULL, NULL,
7669 /* DC */ NULL, NULL, NULL, NULL,
7670 /* E0 */ NULL, NULL, NULL, NULL,
7671 /* E4 */ NULL, NULL, NULL, NULL,
7672 /* E8 */ NULL, NULL, NULL, NULL,
7673 /* EC */ NULL, NULL, NULL, NULL,
7674 /* F0 */ NULL, NULL, NULL, NULL,
7675 /* F4 */ NULL, NULL, NULL, NULL,
7676 /* F8 */ NULL, NULL, NULL, NULL,
7677 /* FC */ NULL, NULL, NULL, NULL,
7681 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
7683 const char *mnemonic;
7685 FETCH_DATA (the_info, codep + 1);
7686 /* AMD 3DNow! instructions are specified by an opcode suffix in the
7687 place where an 8-bit immediate would normally go. ie. the last
7688 byte of the instruction. */
7689 obufp = obuf + strlen (obuf);
7690 mnemonic = Suffix3DNow[*codep++ & 0xff];
7695 /* Since a variable sized modrm/sib chunk is between the start
7696 of the opcode (0x0f0f) and the opcode suffix, we need to do
7697 all the modrm processing first, and don't know until now that
7698 we have a bad opcode. This necessitates some cleaning up. */
7699 op_out[0][0] = '\0';
7700 op_out[1][0] = '\0';
7705 static const char *simd_cmp_op[] = {
7717 OP_SIMD_Suffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
7719 unsigned int cmp_type;
7721 FETCH_DATA (the_info, codep + 1);
7722 obufp = obuf + strlen (obuf);
7723 cmp_type = *codep++ & 0xff;
7726 char suffix1 = 'p', suffix2 = 's';
7727 used_prefixes |= (prefixes & PREFIX_REPZ);
7728 if (prefixes & PREFIX_REPZ)
7732 used_prefixes |= (prefixes & PREFIX_DATA);
7733 if (prefixes & PREFIX_DATA)
7737 used_prefixes |= (prefixes & PREFIX_REPNZ);
7738 if (prefixes & PREFIX_REPNZ)
7739 suffix1 = 's', suffix2 = 'd';
7742 sprintf (scratchbuf, "cmp%s%c%c",
7743 simd_cmp_op[cmp_type], suffix1, suffix2);
7744 used_prefixes |= (prefixes & PREFIX_REPZ);
7745 oappend (scratchbuf);
7749 /* We have a bad extension byte. Clean up. */
7750 op_out[0][0] = '\0';
7751 op_out[1][0] = '\0';
7757 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
7758 int sizeflag ATTRIBUTE_UNUSED)
7760 /* mwait %eax,%ecx */
7763 const char **names = (address_mode == mode_64bit
7764 ? names64 : names32);
7765 strcpy (op_out[0], names[0]);
7766 strcpy (op_out[1], names[1]);
7769 /* Skip mod/rm byte. */
7775 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
7776 int sizeflag ATTRIBUTE_UNUSED)
7778 /* monitor %eax,%ecx,%edx" */
7781 const char **op1_names;
7782 const char **names = (address_mode == mode_64bit
7783 ? names64 : names32);
7785 if (!(prefixes & PREFIX_ADDR))
7786 op1_names = (address_mode == mode_16bit
7790 /* Remove "addr16/addr32". */
7792 op1_names = (address_mode != mode_32bit
7793 ? names32 : names16);
7794 used_prefixes |= PREFIX_ADDR;
7796 strcpy (op_out[0], op1_names[0]);
7797 strcpy (op_out[1], names[1]);
7798 strcpy (op_out[2], names[2]);
7801 /* Skip mod/rm byte. */
7809 /* Throw away prefixes and 1st. opcode byte. */
7810 codep = insn_codep + 1;
7815 REP_Fixup (int bytemode, int sizeflag)
7817 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
7819 if (prefixes & PREFIX_REPZ)
7820 repz_prefix = "rep ";
7827 OP_IMREG (bytemode, sizeflag);
7830 OP_ESreg (bytemode, sizeflag);
7833 OP_DSreg (bytemode, sizeflag);
7842 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
7847 /* Change cmpxchg8b to cmpxchg16b. */
7848 char *p = obuf + strlen (obuf) - 2;
7852 OP_M (bytemode, sizeflag);
7856 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
7858 sprintf (scratchbuf, "%%xmm%d", reg);
7859 oappend (scratchbuf + intel_syntax);
7863 CRC32_Fixup (int bytemode, int sizeflag)
7865 /* Add proper suffix to "crc32". */
7866 char *p = obuf + strlen (obuf);
7883 else if (sizeflag & DFLAG)
7887 used_prefixes |= (prefixes & PREFIX_DATA);
7890 oappend (INTERNAL_DISASSEMBLER_ERROR);
7899 /* Skip mod/rm byte. */
7904 add = (rex & REX_B) ? 8 : 0;
7905 if (bytemode == b_mode)
7909 oappend (names8rex[modrm.rm + add]);
7911 oappend (names8[modrm.rm + add]);
7917 oappend (names64[modrm.rm + add]);
7918 else if ((prefixes & PREFIX_DATA))
7919 oappend (names16[modrm.rm + add]);
7921 oappend (names32[modrm.rm + add]);
7925 OP_E (bytemode, sizeflag);
7928 /* Print a DREX argument as either a register or memory operation. */
7930 print_drex_arg (unsigned int reg, int bytemode, int sizeflag)
7932 if (reg == DREX_REG_UNKNOWN)
7935 else if (reg != DREX_REG_MEMORY)
7937 sprintf (scratchbuf, "%%xmm%d", reg);
7938 oappend (scratchbuf + intel_syntax);
7942 OP_E_extended (bytemode, sizeflag, 1);
7945 /* SSE5 instructions that have 4 arguments are encoded as:
7946 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>.
7948 The <sub-opcode> byte has 1 bit (0x4) that is combined with 1 bit in
7949 the DREX field (0x8) to determine how the arguments are laid out.
7950 The destination register must be the same register as one of the
7951 inputs, and it is encoded in the DREX byte. No REX prefix is used
7952 for these instructions, since the DREX field contains the 3 extension
7953 bits provided by the REX prefix.
7955 The bytemode argument adds 2 extra bits for passing extra information:
7956 DREX_OC1 -- Set the OC1 bit to indicate dest == 1st arg
7957 DREX_NO_OC0 -- OC0 in DREX is invalid
7958 (but pretend it is set). */
7961 OP_DREX4 (int flag_bytemode, int sizeflag)
7963 unsigned int drex_byte;
7964 unsigned int regs[4];
7965 unsigned int modrm_regmem;
7966 unsigned int modrm_reg;
7967 unsigned int drex_reg;
7970 int rex_used_save = rex_used;
7972 int oc1 = (flag_bytemode & DREX_OC1) ? 2 : 0;
7976 bytemode = flag_bytemode & ~ DREX_MASK;
7978 for (i = 0; i < 4; i++)
7979 regs[i] = DREX_REG_UNKNOWN;
7981 /* Determine if we have a SIB byte in addition to MODRM before the
7983 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
7988 /* Get the DREX byte. */
7989 FETCH_DATA (the_info, codep + 2 + has_sib);
7990 drex_byte = codep[has_sib+1];
7991 drex_reg = DREX_XMM (drex_byte);
7992 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
7994 /* Is OC0 legal? If not, hardwire oc0 == 1. */
7995 if (flag_bytemode & DREX_NO_OC0)
7998 if (DREX_OC0 (drex_byte))
8002 oc0 = DREX_OC0 (drex_byte);
8006 /* regmem == register */
8007 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
8009 /* skip modrm/drex since we don't call OP_E_extended */
8014 /* regmem == memory, fill in appropriate REX bits */
8015 modrm_regmem = DREX_REG_MEMORY;
8016 rex = drex_byte & (REX_B | REX_X | REX_R);
8022 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
8031 regs[0] = modrm_regmem;
8032 regs[1] = modrm_reg;
8038 regs[0] = modrm_reg;
8039 regs[1] = modrm_regmem;
8046 regs[1] = modrm_regmem;
8047 regs[2] = modrm_reg;
8053 regs[1] = modrm_reg;
8054 regs[2] = modrm_regmem;
8059 /* Print out the arguments. */
8060 for (i = 0; i < 4; i++)
8062 int j = (intel_syntax) ? 3 - i : i;
8069 print_drex_arg (regs[j], bytemode, sizeflag);
8073 rex_used = rex_used_save;
8076 /* SSE5 instructions that have 3 arguments, and are encoded as:
8077 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset> (or)
8078 0f 25 <sub-opcode> <modrm> <optional-sib> <drex> <offset> <cmp-byte>
8080 The DREX field has 1 bit (0x8) to determine how the arguments are
8081 laid out. The destination register is encoded in the DREX byte.
8082 No REX prefix is used for these instructions, since the DREX field
8083 contains the 3 extension bits provided by the REX prefix. */
8086 OP_DREX3 (int flag_bytemode, int sizeflag)
8088 unsigned int drex_byte;
8089 unsigned int regs[3];
8090 unsigned int modrm_regmem;
8091 unsigned int modrm_reg;
8092 unsigned int drex_reg;
8095 int rex_used_save = rex_used;
8100 bytemode = flag_bytemode & ~ DREX_MASK;
8102 for (i = 0; i < 3; i++)
8103 regs[i] = DREX_REG_UNKNOWN;
8105 /* Determine if we have a SIB byte in addition to MODRM before the
8107 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
8112 /* Get the DREX byte. */
8113 FETCH_DATA (the_info, codep + 2 + has_sib);
8114 drex_byte = codep[has_sib+1];
8115 drex_reg = DREX_XMM (drex_byte);
8116 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
8118 /* Is OC0 legal? If not, hardwire oc0 == 0 */
8119 oc0 = DREX_OC0 (drex_byte);
8120 if ((flag_bytemode & DREX_NO_OC0) && oc0)
8125 /* regmem == register */
8126 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
8128 /* skip modrm/drex since we don't call OP_E_extended. */
8133 /* regmem == memory, fill in appropriate REX bits. */
8134 modrm_regmem = DREX_REG_MEMORY;
8135 rex = drex_byte & (REX_B | REX_X | REX_R);
8141 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
8150 regs[0] = modrm_regmem;
8151 regs[1] = modrm_reg;
8156 regs[0] = modrm_reg;
8157 regs[1] = modrm_regmem;
8162 /* Print out the arguments. */
8163 for (i = 0; i < 3; i++)
8165 int j = (intel_syntax) ? 2 - i : i;
8172 print_drex_arg (regs[j], bytemode, sizeflag);
8176 rex_used = rex_used_save;
8179 /* Emit a floating point comparison for comp<xx> instructions. */
8182 OP_DREX_FCMP (int bytemode ATTRIBUTE_UNUSED,
8183 int sizeflag ATTRIBUTE_UNUSED)
8187 static const char *const cmp_test[] = {
8206 FETCH_DATA (the_info, codep + 1);
8207 byte = *codep & 0xff;
8209 if (byte >= ARRAY_SIZE (cmp_test)
8214 /* The instruction isn't one we know about, so just append the
8215 extension byte as a numeric value. */
8221 sprintf (scratchbuf, "com%s%s", cmp_test[byte], obuf+3);
8222 strcpy (obuf, scratchbuf);
8227 /* Emit an integer point comparison for pcom<xx> instructions,
8228 rewriting the instruction to have the test inside of it. */
8231 OP_DREX_ICMP (int bytemode ATTRIBUTE_UNUSED,
8232 int sizeflag ATTRIBUTE_UNUSED)
8236 static const char *const cmp_test[] = {
8247 FETCH_DATA (the_info, codep + 1);
8248 byte = *codep & 0xff;
8250 if (byte >= ARRAY_SIZE (cmp_test)
8256 /* The instruction isn't one we know about, so just print the
8257 comparison test byte as a numeric value. */
8263 sprintf (scratchbuf, "pcom%s%s", cmp_test[byte], obuf+4);
8264 strcpy (obuf, scratchbuf);