1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
30 /* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
40 #include "opcode/i386.h"
41 #include "libiberty.h"
45 static int print_insn (bfd_vma, disassemble_info *);
46 static void dofloat (int);
47 static void OP_ST (int, int);
48 static void OP_STi (int, int);
49 static int putop (const char *, int);
50 static void oappend (const char *);
51 static void append_seg (void);
52 static void OP_indirE (int, int);
53 static void print_operand_value (char *, int, bfd_vma);
54 static void OP_E_register (int, int);
55 static void OP_E_memory (int, int);
56 static void print_displacement (char *, bfd_vma);
57 static void OP_E (int, int);
58 static void OP_G (int, int);
59 static bfd_vma get64 (void);
60 static bfd_signed_vma get32 (void);
61 static bfd_signed_vma get32s (void);
62 static int get16 (void);
63 static void set_op (bfd_vma, int);
64 static void OP_Skip_MODRM (int, int);
65 static void OP_REG (int, int);
66 static void OP_IMREG (int, int);
67 static void OP_I (int, int);
68 static void OP_I64 (int, int);
69 static void OP_sI (int, int);
70 static void OP_J (int, int);
71 static void OP_SEG (int, int);
72 static void OP_DIR (int, int);
73 static void OP_OFF (int, int);
74 static void OP_OFF64 (int, int);
75 static void ptr_reg (int, int);
76 static void OP_ESreg (int, int);
77 static void OP_DSreg (int, int);
78 static void OP_C (int, int);
79 static void OP_D (int, int);
80 static void OP_T (int, int);
81 static void OP_R (int, int);
82 static void OP_MMX (int, int);
83 static void OP_XMM (int, int);
84 static void OP_EM (int, int);
85 static void OP_EX (int, int);
86 static void OP_EMC (int,int);
87 static void OP_MXC (int,int);
88 static void OP_MS (int, int);
89 static void OP_XS (int, int);
90 static void OP_M (int, int);
91 static void OP_VEX (int, int);
92 static void OP_EX_Vex (int, int);
93 static void OP_EX_VexW (int, int);
94 static void OP_EX_VexImmW (int, int);
95 static void OP_XMM_Vex (int, int);
96 static void OP_XMM_VexW (int, int);
97 static void OP_REG_VexI4 (int, int);
98 static void PCLMUL_Fixup (int, int);
99 static void VEXI4_Fixup (int, int);
100 static void VZERO_Fixup (int, int);
101 static void VCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void HLE_Fixup1 (int, int);
113 static void HLE_Fixup2 (int, int);
114 static void HLE_Fixup3 (int, int);
115 static void CMPXCHG8B_Fixup (int, int);
116 static void XMM_Fixup (int, int);
117 static void CRC32_Fixup (int, int);
118 static void FXSAVE_Fixup (int, int);
119 static void OP_LWPCB_E (int, int);
120 static void OP_LWP_E (int, int);
121 static void OP_Vex_2src_1 (int, int);
122 static void OP_Vex_2src_2 (int, int);
124 static void MOVBE_Fixup (int, int);
127 /* Points to first byte not fetched. */
128 bfd_byte *max_fetched;
129 bfd_byte the_buffer[MAX_MNEM_SIZE];
142 enum address_mode address_mode;
144 /* Flags for the prefixes for the current instruction. See below. */
147 /* REX prefix the current instruction. See below. */
149 /* Bits of REX we've already used. */
151 /* REX bits in original REX prefix ignored. */
152 static int rex_ignored;
153 /* Mark parts used in the REX prefix. When we are testing for
154 empty prefix (for 8bit register REX extension), just mask it
155 out. Otherwise test for REX bit is excuse for existence of REX
156 only in case value is nonzero. */
157 #define USED_REX(value) \
162 rex_used |= (value) | REX_OPCODE; \
165 rex_used |= REX_OPCODE; \
168 /* Flags for prefixes which we somehow handled when printing the
169 current instruction. */
170 static int used_prefixes;
172 /* Flags stored in PREFIXES. */
173 #define PREFIX_REPZ 1
174 #define PREFIX_REPNZ 2
175 #define PREFIX_LOCK 4
177 #define PREFIX_SS 0x10
178 #define PREFIX_DS 0x20
179 #define PREFIX_ES 0x40
180 #define PREFIX_FS 0x80
181 #define PREFIX_GS 0x100
182 #define PREFIX_DATA 0x200
183 #define PREFIX_ADDR 0x400
184 #define PREFIX_FWAIT 0x800
186 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
187 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
189 #define FETCH_DATA(info, addr) \
190 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
191 ? 1 : fetch_data ((info), (addr)))
194 fetch_data (struct disassemble_info *info, bfd_byte *addr)
197 struct dis_private *priv = (struct dis_private *) info->private_data;
198 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
200 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
201 status = (*info->read_memory_func) (start,
203 addr - priv->max_fetched,
209 /* If we did manage to read at least one byte, then
210 print_insn_i386 will do something sensible. Otherwise, print
211 an error. We do that here because this is where we know
213 if (priv->max_fetched == priv->the_buffer)
214 (*info->memory_error_func) (status, start, info);
215 longjmp (priv->bailout, 1);
218 priv->max_fetched = addr;
222 #define XX { NULL, 0 }
223 #define Bad_Opcode NULL, { { NULL, 0 } }
225 #define Eb { OP_E, b_mode }
226 #define Ebnd { OP_E, bnd_mode }
227 #define EbS { OP_E, b_swap_mode }
228 #define Ev { OP_E, v_mode }
229 #define Ev_bnd { OP_E, v_bnd_mode }
230 #define EvS { OP_E, v_swap_mode }
231 #define Ed { OP_E, d_mode }
232 #define Edq { OP_E, dq_mode }
233 #define Edqw { OP_E, dqw_mode }
234 #define Edqb { OP_E, dqb_mode }
235 #define Edqd { OP_E, dqd_mode }
236 #define Eq { OP_E, q_mode }
237 #define indirEv { OP_indirE, stack_v_mode }
238 #define indirEp { OP_indirE, f_mode }
239 #define stackEv { OP_E, stack_v_mode }
240 #define Em { OP_E, m_mode }
241 #define Ew { OP_E, w_mode }
242 #define M { OP_M, 0 } /* lea, lgdt, etc. */
243 #define Ma { OP_M, a_mode }
244 #define Mb { OP_M, b_mode }
245 #define Md { OP_M, d_mode }
246 #define Mo { OP_M, o_mode }
247 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
248 #define Mq { OP_M, q_mode }
249 #define Mx { OP_M, x_mode }
250 #define Mxmm { OP_M, xmm_mode }
251 #define Gb { OP_G, b_mode }
252 #define Gbnd { OP_G, bnd_mode }
253 #define Gv { OP_G, v_mode }
254 #define Gd { OP_G, d_mode }
255 #define Gdq { OP_G, dq_mode }
256 #define Gm { OP_G, m_mode }
257 #define Gw { OP_G, w_mode }
258 #define Rd { OP_R, d_mode }
259 #define Rm { OP_R, m_mode }
260 #define Ib { OP_I, b_mode }
261 #define sIb { OP_sI, b_mode } /* sign extened byte */
262 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
263 #define Iv { OP_I, v_mode }
264 #define sIv { OP_sI, v_mode }
265 #define Iq { OP_I, q_mode }
266 #define Iv64 { OP_I64, v_mode }
267 #define Iw { OP_I, w_mode }
268 #define I1 { OP_I, const_1_mode }
269 #define Jb { OP_J, b_mode }
270 #define Jv { OP_J, v_mode }
271 #define Cm { OP_C, m_mode }
272 #define Dm { OP_D, m_mode }
273 #define Td { OP_T, d_mode }
274 #define Skip_MODRM { OP_Skip_MODRM, 0 }
276 #define RMeAX { OP_REG, eAX_reg }
277 #define RMeBX { OP_REG, eBX_reg }
278 #define RMeCX { OP_REG, eCX_reg }
279 #define RMeDX { OP_REG, eDX_reg }
280 #define RMeSP { OP_REG, eSP_reg }
281 #define RMeBP { OP_REG, eBP_reg }
282 #define RMeSI { OP_REG, eSI_reg }
283 #define RMeDI { OP_REG, eDI_reg }
284 #define RMrAX { OP_REG, rAX_reg }
285 #define RMrBX { OP_REG, rBX_reg }
286 #define RMrCX { OP_REG, rCX_reg }
287 #define RMrDX { OP_REG, rDX_reg }
288 #define RMrSP { OP_REG, rSP_reg }
289 #define RMrBP { OP_REG, rBP_reg }
290 #define RMrSI { OP_REG, rSI_reg }
291 #define RMrDI { OP_REG, rDI_reg }
292 #define RMAL { OP_REG, al_reg }
293 #define RMCL { OP_REG, cl_reg }
294 #define RMDL { OP_REG, dl_reg }
295 #define RMBL { OP_REG, bl_reg }
296 #define RMAH { OP_REG, ah_reg }
297 #define RMCH { OP_REG, ch_reg }
298 #define RMDH { OP_REG, dh_reg }
299 #define RMBH { OP_REG, bh_reg }
300 #define RMAX { OP_REG, ax_reg }
301 #define RMDX { OP_REG, dx_reg }
303 #define eAX { OP_IMREG, eAX_reg }
304 #define eBX { OP_IMREG, eBX_reg }
305 #define eCX { OP_IMREG, eCX_reg }
306 #define eDX { OP_IMREG, eDX_reg }
307 #define eSP { OP_IMREG, eSP_reg }
308 #define eBP { OP_IMREG, eBP_reg }
309 #define eSI { OP_IMREG, eSI_reg }
310 #define eDI { OP_IMREG, eDI_reg }
311 #define AL { OP_IMREG, al_reg }
312 #define CL { OP_IMREG, cl_reg }
313 #define DL { OP_IMREG, dl_reg }
314 #define BL { OP_IMREG, bl_reg }
315 #define AH { OP_IMREG, ah_reg }
316 #define CH { OP_IMREG, ch_reg }
317 #define DH { OP_IMREG, dh_reg }
318 #define BH { OP_IMREG, bh_reg }
319 #define AX { OP_IMREG, ax_reg }
320 #define DX { OP_IMREG, dx_reg }
321 #define zAX { OP_IMREG, z_mode_ax_reg }
322 #define indirDX { OP_IMREG, indir_dx_reg }
324 #define Sw { OP_SEG, w_mode }
325 #define Sv { OP_SEG, v_mode }
326 #define Ap { OP_DIR, 0 }
327 #define Ob { OP_OFF64, b_mode }
328 #define Ov { OP_OFF64, v_mode }
329 #define Xb { OP_DSreg, eSI_reg }
330 #define Xv { OP_DSreg, eSI_reg }
331 #define Xz { OP_DSreg, eSI_reg }
332 #define Yb { OP_ESreg, eDI_reg }
333 #define Yv { OP_ESreg, eDI_reg }
334 #define DSBX { OP_DSreg, eBX_reg }
336 #define es { OP_REG, es_reg }
337 #define ss { OP_REG, ss_reg }
338 #define cs { OP_REG, cs_reg }
339 #define ds { OP_REG, ds_reg }
340 #define fs { OP_REG, fs_reg }
341 #define gs { OP_REG, gs_reg }
343 #define MX { OP_MMX, 0 }
344 #define XM { OP_XMM, 0 }
345 #define XMScalar { OP_XMM, scalar_mode }
346 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
347 #define XMM { OP_XMM, xmm_mode }
348 #define EM { OP_EM, v_mode }
349 #define EMS { OP_EM, v_swap_mode }
350 #define EMd { OP_EM, d_mode }
351 #define EMx { OP_EM, x_mode }
352 #define EXw { OP_EX, w_mode }
353 #define EXd { OP_EX, d_mode }
354 #define EXdScalar { OP_EX, d_scalar_mode }
355 #define EXdS { OP_EX, d_swap_mode }
356 #define EXq { OP_EX, q_mode }
357 #define EXqScalar { OP_EX, q_scalar_mode }
358 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
359 #define EXqS { OP_EX, q_swap_mode }
360 #define EXx { OP_EX, x_mode }
361 #define EXxS { OP_EX, x_swap_mode }
362 #define EXxmm { OP_EX, xmm_mode }
363 #define EXxmmq { OP_EX, xmmq_mode }
364 #define EXxmm_mb { OP_EX, xmm_mb_mode }
365 #define EXxmm_mw { OP_EX, xmm_mw_mode }
366 #define EXxmm_md { OP_EX, xmm_md_mode }
367 #define EXxmm_mq { OP_EX, xmm_mq_mode }
368 #define EXxmmdw { OP_EX, xmmdw_mode }
369 #define EXxmmqd { OP_EX, xmmqd_mode }
370 #define EXymmq { OP_EX, ymmq_mode }
371 #define EXVexWdq { OP_EX, vex_w_dq_mode }
372 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
373 #define MS { OP_MS, v_mode }
374 #define XS { OP_XS, v_mode }
375 #define EMCq { OP_EMC, q_mode }
376 #define MXC { OP_MXC, 0 }
377 #define OPSUF { OP_3DNowSuffix, 0 }
378 #define CMP { CMP_Fixup, 0 }
379 #define XMM0 { XMM_Fixup, 0 }
380 #define FXSAVE { FXSAVE_Fixup, 0 }
381 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
382 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
384 #define Vex { OP_VEX, vex_mode }
385 #define VexScalar { OP_VEX, vex_scalar_mode }
386 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
387 #define Vex128 { OP_VEX, vex128_mode }
388 #define Vex256 { OP_VEX, vex256_mode }
389 #define VexGdq { OP_VEX, dq_mode }
390 #define VexI4 { VEXI4_Fixup, 0}
391 #define EXdVex { OP_EX_Vex, d_mode }
392 #define EXdVexS { OP_EX_Vex, d_swap_mode }
393 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
394 #define EXqVex { OP_EX_Vex, q_mode }
395 #define EXqVexS { OP_EX_Vex, q_swap_mode }
396 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
397 #define EXVexW { OP_EX_VexW, x_mode }
398 #define EXdVexW { OP_EX_VexW, d_mode }
399 #define EXqVexW { OP_EX_VexW, q_mode }
400 #define EXVexImmW { OP_EX_VexImmW, x_mode }
401 #define XMVex { OP_XMM_Vex, 0 }
402 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
403 #define XMVexW { OP_XMM_VexW, 0 }
404 #define XMVexI4 { OP_REG_VexI4, x_mode }
405 #define PCLMUL { PCLMUL_Fixup, 0 }
406 #define VZERO { VZERO_Fixup, 0 }
407 #define VCMP { VCMP_Fixup, 0 }
409 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
410 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
412 /* Used handle "rep" prefix for string instructions. */
413 #define Xbr { REP_Fixup, eSI_reg }
414 #define Xvr { REP_Fixup, eSI_reg }
415 #define Ybr { REP_Fixup, eDI_reg }
416 #define Yvr { REP_Fixup, eDI_reg }
417 #define Yzr { REP_Fixup, eDI_reg }
418 #define indirDXr { REP_Fixup, indir_dx_reg }
419 #define ALr { REP_Fixup, al_reg }
420 #define eAXr { REP_Fixup, eAX_reg }
422 /* Used handle HLE prefix for lockable instructions. */
423 #define Ebh1 { HLE_Fixup1, b_mode }
424 #define Evh1 { HLE_Fixup1, v_mode }
425 #define Ebh2 { HLE_Fixup2, b_mode }
426 #define Evh2 { HLE_Fixup2, v_mode }
427 #define Ebh3 { HLE_Fixup3, b_mode }
428 #define Evh3 { HLE_Fixup3, v_mode }
430 #define BND { BND_Fixup, 0 }
432 #define cond_jump_flag { NULL, cond_jump_mode }
433 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
435 /* bits in sizeflag */
436 #define SUFFIX_ALWAYS 4
444 /* byte operand with operand swapped */
446 /* byte operand, sign extend like 'T' suffix */
448 /* operand size depends on prefixes */
450 /* operand size depends on prefixes with operand swapped */
454 /* double word operand */
456 /* double word operand with operand swapped */
458 /* quad word operand */
460 /* quad word operand with operand swapped */
462 /* ten-byte operand */
464 /* 16-byte XMM or 32-byte YMM operand */
466 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
468 /* 16-byte XMM operand */
470 /* 16-byte XMM or quad word operand */
472 /* XMM register or byte memory operand */
474 /* XMM register or word memory operand */
476 /* XMM register or double word memory operand */
478 /* XMM register or quad word memory operand */
480 /* 16-byte XMM, word or double word operand */
482 /* 16-byte XMM, double word or quad word operand */
484 /* 32-byte YMM or quad word operand */
486 /* 32-byte YMM or 16-byte word operand */
488 /* d_mode in 32bit, q_mode in 64bit mode. */
490 /* pair of v_mode operands */
495 /* operand size depends on REX prefixes. */
497 /* registers like dq_mode, memory like w_mode. */
500 /* 4- or 6-byte pointer operand */
503 /* v_mode for stack-related opcodes. */
505 /* non-quad operand size depends on prefixes */
507 /* 16-byte operand */
509 /* registers like dq_mode, memory like b_mode. */
511 /* registers like dq_mode, memory like d_mode. */
513 /* normal vex mode */
515 /* 128bit vex mode */
517 /* 256bit vex mode */
519 /* operand size depends on the VEX.W bit. */
522 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
523 vex_vsib_d_w_dq_mode,
524 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
525 vex_vsib_q_w_dq_mode,
527 /* scalar, ignore vector length. */
529 /* like d_mode, ignore vector length. */
531 /* like d_swap_mode, ignore vector length. */
533 /* like q_mode, ignore vector length. */
535 /* like q_swap_mode, ignore vector length. */
537 /* like vex_mode, ignore vector length. */
539 /* like vex_w_dq_mode, ignore vector length. */
540 vex_scalar_w_dq_mode,
605 #define FLOAT NULL, { { NULL, FLOATCODE } }
607 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
608 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
609 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
610 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
611 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
612 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
613 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
614 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
615 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
616 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
617 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
618 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
727 MOD_VEX_0F12_PREFIX_0,
729 MOD_VEX_0F16_PREFIX_0,
745 MOD_VEX_0FD7_PREFIX_2,
746 MOD_VEX_0FE7_PREFIX_2,
747 MOD_VEX_0FF0_PREFIX_3,
748 MOD_VEX_0F381A_PREFIX_2,
749 MOD_VEX_0F382A_PREFIX_2,
750 MOD_VEX_0F382C_PREFIX_2,
751 MOD_VEX_0F382D_PREFIX_2,
752 MOD_VEX_0F382E_PREFIX_2,
753 MOD_VEX_0F382F_PREFIX_2,
754 MOD_VEX_0F385A_PREFIX_2,
755 MOD_VEX_0F388C_PREFIX_2,
756 MOD_VEX_0F388E_PREFIX_2,
932 PREFIX_VEX_0F71_REG_2,
933 PREFIX_VEX_0F71_REG_4,
934 PREFIX_VEX_0F71_REG_6,
935 PREFIX_VEX_0F72_REG_2,
936 PREFIX_VEX_0F72_REG_4,
937 PREFIX_VEX_0F72_REG_6,
938 PREFIX_VEX_0F73_REG_2,
939 PREFIX_VEX_0F73_REG_3,
940 PREFIX_VEX_0F73_REG_6,
941 PREFIX_VEX_0F73_REG_7,
1107 PREFIX_VEX_0F38F3_REG_1,
1108 PREFIX_VEX_0F38F3_REG_2,
1109 PREFIX_VEX_0F38F3_REG_3,
1211 THREE_BYTE_0F38 = 0,
1232 VEX_LEN_0F10_P_1 = 0,
1236 VEX_LEN_0F12_P_0_M_0,
1237 VEX_LEN_0F12_P_0_M_1,
1240 VEX_LEN_0F16_P_0_M_0,
1241 VEX_LEN_0F16_P_0_M_1,
1275 VEX_LEN_0FAE_R_2_M_0,
1276 VEX_LEN_0FAE_R_3_M_0,
1285 VEX_LEN_0F381A_P_2_M_0,
1288 VEX_LEN_0F385A_P_2_M_0,
1295 VEX_LEN_0F38F3_R_1_P_0,
1296 VEX_LEN_0F38F3_R_2_P_0,
1297 VEX_LEN_0F38F3_R_3_P_0,
1339 VEX_LEN_0FXOP_08_CC,
1340 VEX_LEN_0FXOP_08_CD,
1341 VEX_LEN_0FXOP_08_CE,
1342 VEX_LEN_0FXOP_08_CF,
1343 VEX_LEN_0FXOP_08_EC,
1344 VEX_LEN_0FXOP_08_ED,
1345 VEX_LEN_0FXOP_08_EE,
1346 VEX_LEN_0FXOP_08_EF,
1347 VEX_LEN_0FXOP_09_80,
1538 VEX_W_0F381A_P_2_M_0,
1550 VEX_W_0F382A_P_2_M_0,
1552 VEX_W_0F382C_P_2_M_0,
1553 VEX_W_0F382D_P_2_M_0,
1554 VEX_W_0F382E_P_2_M_0,
1555 VEX_W_0F382F_P_2_M_0,
1577 VEX_W_0F385A_P_2_M_0,
1624 typedef void (*op_rtn) (int bytemode, int sizeflag);
1635 /* Upper case letters in the instruction names here are macros.
1636 'A' => print 'b' if no register operands or suffix_always is true
1637 'B' => print 'b' if suffix_always is true
1638 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1640 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1641 suffix_always is true
1642 'E' => print 'e' if 32-bit form of jcxz
1643 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1644 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1645 'H' => print ",pt" or ",pn" branch hint
1646 'I' => honor following macro letter even in Intel mode (implemented only
1647 for some of the macro letters)
1649 'K' => print 'd' or 'q' if rex prefix is present.
1650 'L' => print 'l' if suffix_always is true
1651 'M' => print 'r' if intel_mnemonic is false.
1652 'N' => print 'n' if instruction has no wait "prefix"
1653 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1654 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1655 or suffix_always is true. print 'q' if rex prefix is present.
1656 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1658 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1659 'S' => print 'w', 'l' or 'q' if suffix_always is true
1660 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1661 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1662 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1663 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1664 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1665 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1666 suffix_always is true.
1667 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1668 '!' => change condition from true to false or from false to true.
1669 '%' => add 1 upper case letter to the macro.
1671 2 upper case letter macros:
1672 "XY" => print 'x' or 'y' if no register operands or suffix_always
1674 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1675 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1676 or suffix_always is true
1677 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1678 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1679 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1680 "LW" => print 'd', 'q' depending on the VEX.W bit
1682 Many of the above letters print nothing in Intel mode. See "putop"
1685 Braces '{' and '}', and vertical bars '|', indicate alternative
1686 mnemonic strings for AT&T and Intel. */
1688 static const struct dis386 dis386[] = {
1690 { "addB", { Ebh1, Gb } },
1691 { "addS", { Evh1, Gv } },
1692 { "addB", { Gb, EbS } },
1693 { "addS", { Gv, EvS } },
1694 { "addB", { AL, Ib } },
1695 { "addS", { eAX, Iv } },
1696 { X86_64_TABLE (X86_64_06) },
1697 { X86_64_TABLE (X86_64_07) },
1699 { "orB", { Ebh1, Gb } },
1700 { "orS", { Evh1, Gv } },
1701 { "orB", { Gb, EbS } },
1702 { "orS", { Gv, EvS } },
1703 { "orB", { AL, Ib } },
1704 { "orS", { eAX, Iv } },
1705 { X86_64_TABLE (X86_64_0D) },
1706 { Bad_Opcode }, /* 0x0f extended opcode escape */
1708 { "adcB", { Ebh1, Gb } },
1709 { "adcS", { Evh1, Gv } },
1710 { "adcB", { Gb, EbS } },
1711 { "adcS", { Gv, EvS } },
1712 { "adcB", { AL, Ib } },
1713 { "adcS", { eAX, Iv } },
1714 { X86_64_TABLE (X86_64_16) },
1715 { X86_64_TABLE (X86_64_17) },
1717 { "sbbB", { Ebh1, Gb } },
1718 { "sbbS", { Evh1, Gv } },
1719 { "sbbB", { Gb, EbS } },
1720 { "sbbS", { Gv, EvS } },
1721 { "sbbB", { AL, Ib } },
1722 { "sbbS", { eAX, Iv } },
1723 { X86_64_TABLE (X86_64_1E) },
1724 { X86_64_TABLE (X86_64_1F) },
1726 { "andB", { Ebh1, Gb } },
1727 { "andS", { Evh1, Gv } },
1728 { "andB", { Gb, EbS } },
1729 { "andS", { Gv, EvS } },
1730 { "andB", { AL, Ib } },
1731 { "andS", { eAX, Iv } },
1732 { Bad_Opcode }, /* SEG ES prefix */
1733 { X86_64_TABLE (X86_64_27) },
1735 { "subB", { Ebh1, Gb } },
1736 { "subS", { Evh1, Gv } },
1737 { "subB", { Gb, EbS } },
1738 { "subS", { Gv, EvS } },
1739 { "subB", { AL, Ib } },
1740 { "subS", { eAX, Iv } },
1741 { Bad_Opcode }, /* SEG CS prefix */
1742 { X86_64_TABLE (X86_64_2F) },
1744 { "xorB", { Ebh1, Gb } },
1745 { "xorS", { Evh1, Gv } },
1746 { "xorB", { Gb, EbS } },
1747 { "xorS", { Gv, EvS } },
1748 { "xorB", { AL, Ib } },
1749 { "xorS", { eAX, Iv } },
1750 { Bad_Opcode }, /* SEG SS prefix */
1751 { X86_64_TABLE (X86_64_37) },
1753 { "cmpB", { Eb, Gb } },
1754 { "cmpS", { Ev, Gv } },
1755 { "cmpB", { Gb, EbS } },
1756 { "cmpS", { Gv, EvS } },
1757 { "cmpB", { AL, Ib } },
1758 { "cmpS", { eAX, Iv } },
1759 { Bad_Opcode }, /* SEG DS prefix */
1760 { X86_64_TABLE (X86_64_3F) },
1762 { "inc{S|}", { RMeAX } },
1763 { "inc{S|}", { RMeCX } },
1764 { "inc{S|}", { RMeDX } },
1765 { "inc{S|}", { RMeBX } },
1766 { "inc{S|}", { RMeSP } },
1767 { "inc{S|}", { RMeBP } },
1768 { "inc{S|}", { RMeSI } },
1769 { "inc{S|}", { RMeDI } },
1771 { "dec{S|}", { RMeAX } },
1772 { "dec{S|}", { RMeCX } },
1773 { "dec{S|}", { RMeDX } },
1774 { "dec{S|}", { RMeBX } },
1775 { "dec{S|}", { RMeSP } },
1776 { "dec{S|}", { RMeBP } },
1777 { "dec{S|}", { RMeSI } },
1778 { "dec{S|}", { RMeDI } },
1780 { "pushV", { RMrAX } },
1781 { "pushV", { RMrCX } },
1782 { "pushV", { RMrDX } },
1783 { "pushV", { RMrBX } },
1784 { "pushV", { RMrSP } },
1785 { "pushV", { RMrBP } },
1786 { "pushV", { RMrSI } },
1787 { "pushV", { RMrDI } },
1789 { "popV", { RMrAX } },
1790 { "popV", { RMrCX } },
1791 { "popV", { RMrDX } },
1792 { "popV", { RMrBX } },
1793 { "popV", { RMrSP } },
1794 { "popV", { RMrBP } },
1795 { "popV", { RMrSI } },
1796 { "popV", { RMrDI } },
1798 { X86_64_TABLE (X86_64_60) },
1799 { X86_64_TABLE (X86_64_61) },
1800 { X86_64_TABLE (X86_64_62) },
1801 { X86_64_TABLE (X86_64_63) },
1802 { Bad_Opcode }, /* seg fs */
1803 { Bad_Opcode }, /* seg gs */
1804 { Bad_Opcode }, /* op size prefix */
1805 { Bad_Opcode }, /* adr size prefix */
1807 { "pushT", { sIv } },
1808 { "imulS", { Gv, Ev, Iv } },
1809 { "pushT", { sIbT } },
1810 { "imulS", { Gv, Ev, sIb } },
1811 { "ins{b|}", { Ybr, indirDX } },
1812 { X86_64_TABLE (X86_64_6D) },
1813 { "outs{b|}", { indirDXr, Xb } },
1814 { X86_64_TABLE (X86_64_6F) },
1816 { "joH", { Jb, BND, cond_jump_flag } },
1817 { "jnoH", { Jb, BND, cond_jump_flag } },
1818 { "jbH", { Jb, BND, cond_jump_flag } },
1819 { "jaeH", { Jb, BND, cond_jump_flag } },
1820 { "jeH", { Jb, BND, cond_jump_flag } },
1821 { "jneH", { Jb, BND, cond_jump_flag } },
1822 { "jbeH", { Jb, BND, cond_jump_flag } },
1823 { "jaH", { Jb, BND, cond_jump_flag } },
1825 { "jsH", { Jb, BND, cond_jump_flag } },
1826 { "jnsH", { Jb, BND, cond_jump_flag } },
1827 { "jpH", { Jb, BND, cond_jump_flag } },
1828 { "jnpH", { Jb, BND, cond_jump_flag } },
1829 { "jlH", { Jb, BND, cond_jump_flag } },
1830 { "jgeH", { Jb, BND, cond_jump_flag } },
1831 { "jleH", { Jb, BND, cond_jump_flag } },
1832 { "jgH", { Jb, BND, cond_jump_flag } },
1834 { REG_TABLE (REG_80) },
1835 { REG_TABLE (REG_81) },
1837 { REG_TABLE (REG_82) },
1838 { "testB", { Eb, Gb } },
1839 { "testS", { Ev, Gv } },
1840 { "xchgB", { Ebh2, Gb } },
1841 { "xchgS", { Evh2, Gv } },
1843 { "movB", { Ebh3, Gb } },
1844 { "movS", { Evh3, Gv } },
1845 { "movB", { Gb, EbS } },
1846 { "movS", { Gv, EvS } },
1847 { "movD", { Sv, Sw } },
1848 { MOD_TABLE (MOD_8D) },
1849 { "movD", { Sw, Sv } },
1850 { REG_TABLE (REG_8F) },
1852 { PREFIX_TABLE (PREFIX_90) },
1853 { "xchgS", { RMeCX, eAX } },
1854 { "xchgS", { RMeDX, eAX } },
1855 { "xchgS", { RMeBX, eAX } },
1856 { "xchgS", { RMeSP, eAX } },
1857 { "xchgS", { RMeBP, eAX } },
1858 { "xchgS", { RMeSI, eAX } },
1859 { "xchgS", { RMeDI, eAX } },
1861 { "cW{t|}R", { XX } },
1862 { "cR{t|}O", { XX } },
1863 { X86_64_TABLE (X86_64_9A) },
1864 { Bad_Opcode }, /* fwait */
1865 { "pushfT", { XX } },
1866 { "popfT", { XX } },
1870 { "mov%LB", { AL, Ob } },
1871 { "mov%LS", { eAX, Ov } },
1872 { "mov%LB", { Ob, AL } },
1873 { "mov%LS", { Ov, eAX } },
1874 { "movs{b|}", { Ybr, Xb } },
1875 { "movs{R|}", { Yvr, Xv } },
1876 { "cmps{b|}", { Xb, Yb } },
1877 { "cmps{R|}", { Xv, Yv } },
1879 { "testB", { AL, Ib } },
1880 { "testS", { eAX, Iv } },
1881 { "stosB", { Ybr, AL } },
1882 { "stosS", { Yvr, eAX } },
1883 { "lodsB", { ALr, Xb } },
1884 { "lodsS", { eAXr, Xv } },
1885 { "scasB", { AL, Yb } },
1886 { "scasS", { eAX, Yv } },
1888 { "movB", { RMAL, Ib } },
1889 { "movB", { RMCL, Ib } },
1890 { "movB", { RMDL, Ib } },
1891 { "movB", { RMBL, Ib } },
1892 { "movB", { RMAH, Ib } },
1893 { "movB", { RMCH, Ib } },
1894 { "movB", { RMDH, Ib } },
1895 { "movB", { RMBH, Ib } },
1897 { "mov%LV", { RMeAX, Iv64 } },
1898 { "mov%LV", { RMeCX, Iv64 } },
1899 { "mov%LV", { RMeDX, Iv64 } },
1900 { "mov%LV", { RMeBX, Iv64 } },
1901 { "mov%LV", { RMeSP, Iv64 } },
1902 { "mov%LV", { RMeBP, Iv64 } },
1903 { "mov%LV", { RMeSI, Iv64 } },
1904 { "mov%LV", { RMeDI, Iv64 } },
1906 { REG_TABLE (REG_C0) },
1907 { REG_TABLE (REG_C1) },
1908 { "retT", { Iw, BND } },
1909 { "retT", { BND } },
1910 { X86_64_TABLE (X86_64_C4) },
1911 { X86_64_TABLE (X86_64_C5) },
1912 { REG_TABLE (REG_C6) },
1913 { REG_TABLE (REG_C7) },
1915 { "enterT", { Iw, Ib } },
1916 { "leaveT", { XX } },
1917 { "Jret{|f}P", { Iw } },
1918 { "Jret{|f}P", { XX } },
1921 { X86_64_TABLE (X86_64_CE) },
1922 { "iretP", { XX } },
1924 { REG_TABLE (REG_D0) },
1925 { REG_TABLE (REG_D1) },
1926 { REG_TABLE (REG_D2) },
1927 { REG_TABLE (REG_D3) },
1928 { X86_64_TABLE (X86_64_D4) },
1929 { X86_64_TABLE (X86_64_D5) },
1931 { "xlat", { DSBX } },
1942 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
1943 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
1944 { "loopFH", { Jb, XX, loop_jcxz_flag } },
1945 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
1946 { "inB", { AL, Ib } },
1947 { "inG", { zAX, Ib } },
1948 { "outB", { Ib, AL } },
1949 { "outG", { Ib, zAX } },
1951 { "callT", { Jv, BND } },
1952 { "jmpT", { Jv, BND } },
1953 { X86_64_TABLE (X86_64_EA) },
1954 { "jmp", { Jb, BND } },
1955 { "inB", { AL, indirDX } },
1956 { "inG", { zAX, indirDX } },
1957 { "outB", { indirDX, AL } },
1958 { "outG", { indirDX, zAX } },
1960 { Bad_Opcode }, /* lock prefix */
1961 { "icebp", { XX } },
1962 { Bad_Opcode }, /* repne */
1963 { Bad_Opcode }, /* repz */
1966 { REG_TABLE (REG_F6) },
1967 { REG_TABLE (REG_F7) },
1975 { REG_TABLE (REG_FE) },
1976 { REG_TABLE (REG_FF) },
1979 static const struct dis386 dis386_twobyte[] = {
1981 { REG_TABLE (REG_0F00 ) },
1982 { REG_TABLE (REG_0F01 ) },
1983 { "larS", { Gv, Ew } },
1984 { "lslS", { Gv, Ew } },
1986 { "syscall", { XX } },
1988 { "sysretP", { XX } },
1991 { "wbinvd", { XX } },
1995 { REG_TABLE (REG_0F0D) },
1996 { "femms", { XX } },
1997 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
1999 { PREFIX_TABLE (PREFIX_0F10) },
2000 { PREFIX_TABLE (PREFIX_0F11) },
2001 { PREFIX_TABLE (PREFIX_0F12) },
2002 { MOD_TABLE (MOD_0F13) },
2003 { "unpcklpX", { XM, EXx } },
2004 { "unpckhpX", { XM, EXx } },
2005 { PREFIX_TABLE (PREFIX_0F16) },
2006 { MOD_TABLE (MOD_0F17) },
2008 { REG_TABLE (REG_0F18) },
2010 { PREFIX_TABLE (PREFIX_0F1A) },
2011 { PREFIX_TABLE (PREFIX_0F1B) },
2017 { MOD_TABLE (MOD_0F20) },
2018 { MOD_TABLE (MOD_0F21) },
2019 { MOD_TABLE (MOD_0F22) },
2020 { MOD_TABLE (MOD_0F23) },
2021 { MOD_TABLE (MOD_0F24) },
2023 { MOD_TABLE (MOD_0F26) },
2026 { "movapX", { XM, EXx } },
2027 { "movapX", { EXxS, XM } },
2028 { PREFIX_TABLE (PREFIX_0F2A) },
2029 { PREFIX_TABLE (PREFIX_0F2B) },
2030 { PREFIX_TABLE (PREFIX_0F2C) },
2031 { PREFIX_TABLE (PREFIX_0F2D) },
2032 { PREFIX_TABLE (PREFIX_0F2E) },
2033 { PREFIX_TABLE (PREFIX_0F2F) },
2035 { "wrmsr", { XX } },
2036 { "rdtsc", { XX } },
2037 { "rdmsr", { XX } },
2038 { "rdpmc", { XX } },
2039 { "sysenter", { XX } },
2040 { "sysexit", { XX } },
2042 { "getsec", { XX } },
2044 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2046 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2053 { "cmovoS", { Gv, Ev } },
2054 { "cmovnoS", { Gv, Ev } },
2055 { "cmovbS", { Gv, Ev } },
2056 { "cmovaeS", { Gv, Ev } },
2057 { "cmoveS", { Gv, Ev } },
2058 { "cmovneS", { Gv, Ev } },
2059 { "cmovbeS", { Gv, Ev } },
2060 { "cmovaS", { Gv, Ev } },
2062 { "cmovsS", { Gv, Ev } },
2063 { "cmovnsS", { Gv, Ev } },
2064 { "cmovpS", { Gv, Ev } },
2065 { "cmovnpS", { Gv, Ev } },
2066 { "cmovlS", { Gv, Ev } },
2067 { "cmovgeS", { Gv, Ev } },
2068 { "cmovleS", { Gv, Ev } },
2069 { "cmovgS", { Gv, Ev } },
2071 { MOD_TABLE (MOD_0F51) },
2072 { PREFIX_TABLE (PREFIX_0F51) },
2073 { PREFIX_TABLE (PREFIX_0F52) },
2074 { PREFIX_TABLE (PREFIX_0F53) },
2075 { "andpX", { XM, EXx } },
2076 { "andnpX", { XM, EXx } },
2077 { "orpX", { XM, EXx } },
2078 { "xorpX", { XM, EXx } },
2080 { PREFIX_TABLE (PREFIX_0F58) },
2081 { PREFIX_TABLE (PREFIX_0F59) },
2082 { PREFIX_TABLE (PREFIX_0F5A) },
2083 { PREFIX_TABLE (PREFIX_0F5B) },
2084 { PREFIX_TABLE (PREFIX_0F5C) },
2085 { PREFIX_TABLE (PREFIX_0F5D) },
2086 { PREFIX_TABLE (PREFIX_0F5E) },
2087 { PREFIX_TABLE (PREFIX_0F5F) },
2089 { PREFIX_TABLE (PREFIX_0F60) },
2090 { PREFIX_TABLE (PREFIX_0F61) },
2091 { PREFIX_TABLE (PREFIX_0F62) },
2092 { "packsswb", { MX, EM } },
2093 { "pcmpgtb", { MX, EM } },
2094 { "pcmpgtw", { MX, EM } },
2095 { "pcmpgtd", { MX, EM } },
2096 { "packuswb", { MX, EM } },
2098 { "punpckhbw", { MX, EM } },
2099 { "punpckhwd", { MX, EM } },
2100 { "punpckhdq", { MX, EM } },
2101 { "packssdw", { MX, EM } },
2102 { PREFIX_TABLE (PREFIX_0F6C) },
2103 { PREFIX_TABLE (PREFIX_0F6D) },
2104 { "movK", { MX, Edq } },
2105 { PREFIX_TABLE (PREFIX_0F6F) },
2107 { PREFIX_TABLE (PREFIX_0F70) },
2108 { REG_TABLE (REG_0F71) },
2109 { REG_TABLE (REG_0F72) },
2110 { REG_TABLE (REG_0F73) },
2111 { "pcmpeqb", { MX, EM } },
2112 { "pcmpeqw", { MX, EM } },
2113 { "pcmpeqd", { MX, EM } },
2116 { PREFIX_TABLE (PREFIX_0F78) },
2117 { PREFIX_TABLE (PREFIX_0F79) },
2118 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2120 { PREFIX_TABLE (PREFIX_0F7C) },
2121 { PREFIX_TABLE (PREFIX_0F7D) },
2122 { PREFIX_TABLE (PREFIX_0F7E) },
2123 { PREFIX_TABLE (PREFIX_0F7F) },
2125 { "joH", { Jv, BND, cond_jump_flag } },
2126 { "jnoH", { Jv, BND, cond_jump_flag } },
2127 { "jbH", { Jv, BND, cond_jump_flag } },
2128 { "jaeH", { Jv, BND, cond_jump_flag } },
2129 { "jeH", { Jv, BND, cond_jump_flag } },
2130 { "jneH", { Jv, BND, cond_jump_flag } },
2131 { "jbeH", { Jv, BND, cond_jump_flag } },
2132 { "jaH", { Jv, BND, cond_jump_flag } },
2134 { "jsH", { Jv, BND, cond_jump_flag } },
2135 { "jnsH", { Jv, BND, cond_jump_flag } },
2136 { "jpH", { Jv, BND, cond_jump_flag } },
2137 { "jnpH", { Jv, BND, cond_jump_flag } },
2138 { "jlH", { Jv, BND, cond_jump_flag } },
2139 { "jgeH", { Jv, BND, cond_jump_flag } },
2140 { "jleH", { Jv, BND, cond_jump_flag } },
2141 { "jgH", { Jv, BND, cond_jump_flag } },
2144 { "setno", { Eb } },
2146 { "setae", { Eb } },
2148 { "setne", { Eb } },
2149 { "setbe", { Eb } },
2153 { "setns", { Eb } },
2155 { "setnp", { Eb } },
2157 { "setge", { Eb } },
2158 { "setle", { Eb } },
2161 { "pushT", { fs } },
2163 { "cpuid", { XX } },
2164 { "btS", { Ev, Gv } },
2165 { "shldS", { Ev, Gv, Ib } },
2166 { "shldS", { Ev, Gv, CL } },
2167 { REG_TABLE (REG_0FA6) },
2168 { REG_TABLE (REG_0FA7) },
2170 { "pushT", { gs } },
2173 { "btsS", { Evh1, Gv } },
2174 { "shrdS", { Ev, Gv, Ib } },
2175 { "shrdS", { Ev, Gv, CL } },
2176 { REG_TABLE (REG_0FAE) },
2177 { "imulS", { Gv, Ev } },
2179 { "cmpxchgB", { Ebh1, Gb } },
2180 { "cmpxchgS", { Evh1, Gv } },
2181 { MOD_TABLE (MOD_0FB2) },
2182 { "btrS", { Evh1, Gv } },
2183 { MOD_TABLE (MOD_0FB4) },
2184 { MOD_TABLE (MOD_0FB5) },
2185 { "movz{bR|x}", { Gv, Eb } },
2186 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
2188 { PREFIX_TABLE (PREFIX_0FB8) },
2190 { REG_TABLE (REG_0FBA) },
2191 { "btcS", { Evh1, Gv } },
2192 { PREFIX_TABLE (PREFIX_0FBC) },
2193 { PREFIX_TABLE (PREFIX_0FBD) },
2194 { "movs{bR|x}", { Gv, Eb } },
2195 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
2197 { "xaddB", { Ebh1, Gb } },
2198 { "xaddS", { Evh1, Gv } },
2199 { PREFIX_TABLE (PREFIX_0FC2) },
2200 { PREFIX_TABLE (PREFIX_0FC3) },
2201 { "pinsrw", { MX, Edqw, Ib } },
2202 { "pextrw", { Gdq, MS, Ib } },
2203 { "shufpX", { XM, EXx, Ib } },
2204 { REG_TABLE (REG_0FC7) },
2206 { "bswap", { RMeAX } },
2207 { "bswap", { RMeCX } },
2208 { "bswap", { RMeDX } },
2209 { "bswap", { RMeBX } },
2210 { "bswap", { RMeSP } },
2211 { "bswap", { RMeBP } },
2212 { "bswap", { RMeSI } },
2213 { "bswap", { RMeDI } },
2215 { PREFIX_TABLE (PREFIX_0FD0) },
2216 { "psrlw", { MX, EM } },
2217 { "psrld", { MX, EM } },
2218 { "psrlq", { MX, EM } },
2219 { "paddq", { MX, EM } },
2220 { "pmullw", { MX, EM } },
2221 { PREFIX_TABLE (PREFIX_0FD6) },
2222 { MOD_TABLE (MOD_0FD7) },
2224 { "psubusb", { MX, EM } },
2225 { "psubusw", { MX, EM } },
2226 { "pminub", { MX, EM } },
2227 { "pand", { MX, EM } },
2228 { "paddusb", { MX, EM } },
2229 { "paddusw", { MX, EM } },
2230 { "pmaxub", { MX, EM } },
2231 { "pandn", { MX, EM } },
2233 { "pavgb", { MX, EM } },
2234 { "psraw", { MX, EM } },
2235 { "psrad", { MX, EM } },
2236 { "pavgw", { MX, EM } },
2237 { "pmulhuw", { MX, EM } },
2238 { "pmulhw", { MX, EM } },
2239 { PREFIX_TABLE (PREFIX_0FE6) },
2240 { PREFIX_TABLE (PREFIX_0FE7) },
2242 { "psubsb", { MX, EM } },
2243 { "psubsw", { MX, EM } },
2244 { "pminsw", { MX, EM } },
2245 { "por", { MX, EM } },
2246 { "paddsb", { MX, EM } },
2247 { "paddsw", { MX, EM } },
2248 { "pmaxsw", { MX, EM } },
2249 { "pxor", { MX, EM } },
2251 { PREFIX_TABLE (PREFIX_0FF0) },
2252 { "psllw", { MX, EM } },
2253 { "pslld", { MX, EM } },
2254 { "psllq", { MX, EM } },
2255 { "pmuludq", { MX, EM } },
2256 { "pmaddwd", { MX, EM } },
2257 { "psadbw", { MX, EM } },
2258 { PREFIX_TABLE (PREFIX_0FF7) },
2260 { "psubb", { MX, EM } },
2261 { "psubw", { MX, EM } },
2262 { "psubd", { MX, EM } },
2263 { "psubq", { MX, EM } },
2264 { "paddb", { MX, EM } },
2265 { "paddw", { MX, EM } },
2266 { "paddd", { MX, EM } },
2270 static const unsigned char onebyte_has_modrm[256] = {
2271 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2272 /* ------------------------------- */
2273 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2274 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2275 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2276 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2277 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2278 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2279 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2280 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2281 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2282 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2283 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2284 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2285 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2286 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2287 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2288 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2289 /* ------------------------------- */
2290 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2293 static const unsigned char twobyte_has_modrm[256] = {
2294 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2295 /* ------------------------------- */
2296 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2297 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2298 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2299 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2300 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2301 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2302 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2303 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2304 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2305 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2306 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2307 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2308 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2309 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2310 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2311 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
2312 /* ------------------------------- */
2313 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2316 static char obuf[100];
2318 static char *mnemonicendp;
2319 static char scratchbuf[100];
2320 static unsigned char *start_codep;
2321 static unsigned char *insn_codep;
2322 static unsigned char *codep;
2323 static int last_lock_prefix;
2324 static int last_repz_prefix;
2325 static int last_repnz_prefix;
2326 static int last_data_prefix;
2327 static int last_addr_prefix;
2328 static int last_rex_prefix;
2329 static int last_seg_prefix;
2330 #define MAX_CODE_LENGTH 15
2331 /* We can up to 14 prefixes since the maximum instruction length is
2333 static int all_prefixes[MAX_CODE_LENGTH - 1];
2334 static disassemble_info *the_info;
2342 static unsigned char need_modrm;
2352 int register_specifier;
2358 static unsigned char need_vex;
2359 static unsigned char need_vex_reg;
2360 static unsigned char vex_w_done;
2368 /* If we are accessing mod/rm/reg without need_modrm set, then the
2369 values are stale. Hitting this abort likely indicates that you
2370 need to update onebyte_has_modrm or twobyte_has_modrm. */
2371 #define MODRM_CHECK if (!need_modrm) abort ()
2373 static const char **names64;
2374 static const char **names32;
2375 static const char **names16;
2376 static const char **names8;
2377 static const char **names8rex;
2378 static const char **names_seg;
2379 static const char *index64;
2380 static const char *index32;
2381 static const char **index16;
2382 static const char **names_bnd;
2384 static const char *intel_names64[] = {
2385 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2386 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2388 static const char *intel_names32[] = {
2389 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2390 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2392 static const char *intel_names16[] = {
2393 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2394 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2396 static const char *intel_names8[] = {
2397 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2399 static const char *intel_names8rex[] = {
2400 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2401 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2403 static const char *intel_names_seg[] = {
2404 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2406 static const char *intel_index64 = "riz";
2407 static const char *intel_index32 = "eiz";
2408 static const char *intel_index16[] = {
2409 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2412 static const char *att_names64[] = {
2413 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2414 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2416 static const char *att_names32[] = {
2417 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2418 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2420 static const char *att_names16[] = {
2421 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2422 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2424 static const char *att_names8[] = {
2425 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2427 static const char *att_names8rex[] = {
2428 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2429 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2431 static const char *att_names_seg[] = {
2432 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2434 static const char *att_index64 = "%riz";
2435 static const char *att_index32 = "%eiz";
2436 static const char *att_index16[] = {
2437 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2440 static const char **names_mm;
2441 static const char *intel_names_mm[] = {
2442 "mm0", "mm1", "mm2", "mm3",
2443 "mm4", "mm5", "mm6", "mm7"
2445 static const char *att_names_mm[] = {
2446 "%mm0", "%mm1", "%mm2", "%mm3",
2447 "%mm4", "%mm5", "%mm6", "%mm7"
2450 static const char *intel_names_bnd[] = {
2451 "bnd0", "bnd1", "bnd2", "bnd3"
2454 static const char *att_names_bnd[] = {
2455 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2458 static const char **names_xmm;
2459 static const char *intel_names_xmm[] = {
2460 "xmm0", "xmm1", "xmm2", "xmm3",
2461 "xmm4", "xmm5", "xmm6", "xmm7",
2462 "xmm8", "xmm9", "xmm10", "xmm11",
2463 "xmm12", "xmm13", "xmm14", "xmm15"
2465 static const char *att_names_xmm[] = {
2466 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2467 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2468 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2469 "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2472 static const char **names_ymm;
2473 static const char *intel_names_ymm[] = {
2474 "ymm0", "ymm1", "ymm2", "ymm3",
2475 "ymm4", "ymm5", "ymm6", "ymm7",
2476 "ymm8", "ymm9", "ymm10", "ymm11",
2477 "ymm12", "ymm13", "ymm14", "ymm15"
2479 static const char *att_names_ymm[] = {
2480 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2481 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2482 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2483 "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2486 static const struct dis386 reg_table[][8] = {
2489 { "addA", { Ebh1, Ib } },
2490 { "orA", { Ebh1, Ib } },
2491 { "adcA", { Ebh1, Ib } },
2492 { "sbbA", { Ebh1, Ib } },
2493 { "andA", { Ebh1, Ib } },
2494 { "subA", { Ebh1, Ib } },
2495 { "xorA", { Ebh1, Ib } },
2496 { "cmpA", { Eb, Ib } },
2500 { "addQ", { Evh1, Iv } },
2501 { "orQ", { Evh1, Iv } },
2502 { "adcQ", { Evh1, Iv } },
2503 { "sbbQ", { Evh1, Iv } },
2504 { "andQ", { Evh1, Iv } },
2505 { "subQ", { Evh1, Iv } },
2506 { "xorQ", { Evh1, Iv } },
2507 { "cmpQ", { Ev, Iv } },
2511 { "addQ", { Evh1, sIb } },
2512 { "orQ", { Evh1, sIb } },
2513 { "adcQ", { Evh1, sIb } },
2514 { "sbbQ", { Evh1, sIb } },
2515 { "andQ", { Evh1, sIb } },
2516 { "subQ", { Evh1, sIb } },
2517 { "xorQ", { Evh1, sIb } },
2518 { "cmpQ", { Ev, sIb } },
2522 { "popU", { stackEv } },
2523 { XOP_8F_TABLE (XOP_09) },
2527 { XOP_8F_TABLE (XOP_09) },
2531 { "rolA", { Eb, Ib } },
2532 { "rorA", { Eb, Ib } },
2533 { "rclA", { Eb, Ib } },
2534 { "rcrA", { Eb, Ib } },
2535 { "shlA", { Eb, Ib } },
2536 { "shrA", { Eb, Ib } },
2538 { "sarA", { Eb, Ib } },
2542 { "rolQ", { Ev, Ib } },
2543 { "rorQ", { Ev, Ib } },
2544 { "rclQ", { Ev, Ib } },
2545 { "rcrQ", { Ev, Ib } },
2546 { "shlQ", { Ev, Ib } },
2547 { "shrQ", { Ev, Ib } },
2549 { "sarQ", { Ev, Ib } },
2553 { "movA", { Ebh3, Ib } },
2560 { MOD_TABLE (MOD_C6_REG_7) },
2564 { "movQ", { Evh3, Iv } },
2571 { MOD_TABLE (MOD_C7_REG_7) },
2575 { "rolA", { Eb, I1 } },
2576 { "rorA", { Eb, I1 } },
2577 { "rclA", { Eb, I1 } },
2578 { "rcrA", { Eb, I1 } },
2579 { "shlA", { Eb, I1 } },
2580 { "shrA", { Eb, I1 } },
2582 { "sarA", { Eb, I1 } },
2586 { "rolQ", { Ev, I1 } },
2587 { "rorQ", { Ev, I1 } },
2588 { "rclQ", { Ev, I1 } },
2589 { "rcrQ", { Ev, I1 } },
2590 { "shlQ", { Ev, I1 } },
2591 { "shrQ", { Ev, I1 } },
2593 { "sarQ", { Ev, I1 } },
2597 { "rolA", { Eb, CL } },
2598 { "rorA", { Eb, CL } },
2599 { "rclA", { Eb, CL } },
2600 { "rcrA", { Eb, CL } },
2601 { "shlA", { Eb, CL } },
2602 { "shrA", { Eb, CL } },
2604 { "sarA", { Eb, CL } },
2608 { "rolQ", { Ev, CL } },
2609 { "rorQ", { Ev, CL } },
2610 { "rclQ", { Ev, CL } },
2611 { "rcrQ", { Ev, CL } },
2612 { "shlQ", { Ev, CL } },
2613 { "shrQ", { Ev, CL } },
2615 { "sarQ", { Ev, CL } },
2619 { "testA", { Eb, Ib } },
2621 { "notA", { Ebh1 } },
2622 { "negA", { Ebh1 } },
2623 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
2624 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
2625 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
2626 { "idivA", { Eb } }, /* and idiv for consistency. */
2630 { "testQ", { Ev, Iv } },
2632 { "notQ", { Evh1 } },
2633 { "negQ", { Evh1 } },
2634 { "mulQ", { Ev } }, /* Don't print the implicit register. */
2635 { "imulQ", { Ev } },
2637 { "idivQ", { Ev } },
2641 { "incA", { Ebh1 } },
2642 { "decA", { Ebh1 } },
2646 { "incQ", { Evh1 } },
2647 { "decQ", { Evh1 } },
2648 { "call{T|}", { indirEv, BND } },
2649 { "Jcall{T|}", { indirEp } },
2650 { "jmp{T|}", { indirEv, BND } },
2651 { "Jjmp{T|}", { indirEp } },
2652 { "pushU", { stackEv } },
2657 { "sldtD", { Sv } },
2668 { MOD_TABLE (MOD_0F01_REG_0) },
2669 { MOD_TABLE (MOD_0F01_REG_1) },
2670 { MOD_TABLE (MOD_0F01_REG_2) },
2671 { MOD_TABLE (MOD_0F01_REG_3) },
2672 { "smswD", { Sv } },
2675 { MOD_TABLE (MOD_0F01_REG_7) },
2679 { "prefetch", { Mb } },
2680 { "prefetchw", { Mb } },
2681 { "prefetch", { Mb } },
2682 { "prefetch", { Mb } },
2683 { "prefetch", { Mb } },
2684 { "prefetch", { Mb } },
2685 { "prefetch", { Mb } },
2686 { "prefetch", { Mb } },
2690 { MOD_TABLE (MOD_0F18_REG_0) },
2691 { MOD_TABLE (MOD_0F18_REG_1) },
2692 { MOD_TABLE (MOD_0F18_REG_2) },
2693 { MOD_TABLE (MOD_0F18_REG_3) },
2694 { MOD_TABLE (MOD_0F18_REG_4) },
2695 { MOD_TABLE (MOD_0F18_REG_5) },
2696 { MOD_TABLE (MOD_0F18_REG_6) },
2697 { MOD_TABLE (MOD_0F18_REG_7) },
2703 { MOD_TABLE (MOD_0F71_REG_2) },
2705 { MOD_TABLE (MOD_0F71_REG_4) },
2707 { MOD_TABLE (MOD_0F71_REG_6) },
2713 { MOD_TABLE (MOD_0F72_REG_2) },
2715 { MOD_TABLE (MOD_0F72_REG_4) },
2717 { MOD_TABLE (MOD_0F72_REG_6) },
2723 { MOD_TABLE (MOD_0F73_REG_2) },
2724 { MOD_TABLE (MOD_0F73_REG_3) },
2727 { MOD_TABLE (MOD_0F73_REG_6) },
2728 { MOD_TABLE (MOD_0F73_REG_7) },
2732 { "montmul", { { OP_0f07, 0 } } },
2733 { "xsha1", { { OP_0f07, 0 } } },
2734 { "xsha256", { { OP_0f07, 0 } } },
2738 { "xstore-rng", { { OP_0f07, 0 } } },
2739 { "xcrypt-ecb", { { OP_0f07, 0 } } },
2740 { "xcrypt-cbc", { { OP_0f07, 0 } } },
2741 { "xcrypt-ctr", { { OP_0f07, 0 } } },
2742 { "xcrypt-cfb", { { OP_0f07, 0 } } },
2743 { "xcrypt-ofb", { { OP_0f07, 0 } } },
2747 { MOD_TABLE (MOD_0FAE_REG_0) },
2748 { MOD_TABLE (MOD_0FAE_REG_1) },
2749 { MOD_TABLE (MOD_0FAE_REG_2) },
2750 { MOD_TABLE (MOD_0FAE_REG_3) },
2751 { MOD_TABLE (MOD_0FAE_REG_4) },
2752 { MOD_TABLE (MOD_0FAE_REG_5) },
2753 { MOD_TABLE (MOD_0FAE_REG_6) },
2754 { MOD_TABLE (MOD_0FAE_REG_7) },
2762 { "btQ", { Ev, Ib } },
2763 { "btsQ", { Evh1, Ib } },
2764 { "btrQ", { Evh1, Ib } },
2765 { "btcQ", { Evh1, Ib } },
2770 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2775 { MOD_TABLE (MOD_0FC7_REG_6) },
2776 { MOD_TABLE (MOD_0FC7_REG_7) },
2782 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
2784 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
2786 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
2792 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
2794 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
2796 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
2802 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
2803 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
2806 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
2807 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
2813 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2814 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2816 /* REG_VEX_0F38F3 */
2819 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
2820 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
2821 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
2825 { "llwpcb", { { OP_LWPCB_E, 0 } } },
2826 { "slwpcb", { { OP_LWPCB_E, 0 } } },
2830 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
2831 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
2833 /* REG_XOP_TBM_01 */
2836 { "blcfill", { { OP_LWP_E, 0 }, Ev } },
2837 { "blsfill", { { OP_LWP_E, 0 }, Ev } },
2838 { "blcs", { { OP_LWP_E, 0 }, Ev } },
2839 { "tzmsk", { { OP_LWP_E, 0 }, Ev } },
2840 { "blcic", { { OP_LWP_E, 0 }, Ev } },
2841 { "blsic", { { OP_LWP_E, 0 }, Ev } },
2842 { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
2844 /* REG_XOP_TBM_02 */
2847 { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
2852 { "blci", { { OP_LWP_E, 0 }, Ev } },
2856 static const struct dis386 prefix_table[][4] = {
2859 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2860 { "pause", { XX } },
2861 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2866 { "movups", { XM, EXx } },
2867 { "movss", { XM, EXd } },
2868 { "movupd", { XM, EXx } },
2869 { "movsd", { XM, EXq } },
2874 { "movups", { EXxS, XM } },
2875 { "movss", { EXdS, XM } },
2876 { "movupd", { EXxS, XM } },
2877 { "movsd", { EXqS, XM } },
2882 { MOD_TABLE (MOD_0F12_PREFIX_0) },
2883 { "movsldup", { XM, EXx } },
2884 { "movlpd", { XM, EXq } },
2885 { "movddup", { XM, EXq } },
2890 { MOD_TABLE (MOD_0F16_PREFIX_0) },
2891 { "movshdup", { XM, EXx } },
2892 { "movhpd", { XM, EXq } },
2897 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
2898 { "bndcl", { Gbnd, Ev_bnd } },
2899 { "bndmov", { Gbnd, Ebnd } },
2900 { "bndcu", { Gbnd, Ev_bnd } },
2905 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
2906 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
2907 { "bndmov", { Ebnd, Gbnd } },
2908 { "bndcn", { Gbnd, Ev_bnd } },
2913 { "cvtpi2ps", { XM, EMCq } },
2914 { "cvtsi2ss%LQ", { XM, Ev } },
2915 { "cvtpi2pd", { XM, EMCq } },
2916 { "cvtsi2sd%LQ", { XM, Ev } },
2921 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2922 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2923 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2924 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2929 { "cvttps2pi", { MXC, EXq } },
2930 { "cvttss2siY", { Gv, EXd } },
2931 { "cvttpd2pi", { MXC, EXx } },
2932 { "cvttsd2siY", { Gv, EXq } },
2937 { "cvtps2pi", { MXC, EXq } },
2938 { "cvtss2siY", { Gv, EXd } },
2939 { "cvtpd2pi", { MXC, EXx } },
2940 { "cvtsd2siY", { Gv, EXq } },
2945 { "ucomiss",{ XM, EXd } },
2947 { "ucomisd",{ XM, EXq } },
2952 { "comiss", { XM, EXd } },
2954 { "comisd", { XM, EXq } },
2959 { "sqrtps", { XM, EXx } },
2960 { "sqrtss", { XM, EXd } },
2961 { "sqrtpd", { XM, EXx } },
2962 { "sqrtsd", { XM, EXq } },
2967 { "rsqrtps",{ XM, EXx } },
2968 { "rsqrtss",{ XM, EXd } },
2973 { "rcpps", { XM, EXx } },
2974 { "rcpss", { XM, EXd } },
2979 { "addps", { XM, EXx } },
2980 { "addss", { XM, EXd } },
2981 { "addpd", { XM, EXx } },
2982 { "addsd", { XM, EXq } },
2987 { "mulps", { XM, EXx } },
2988 { "mulss", { XM, EXd } },
2989 { "mulpd", { XM, EXx } },
2990 { "mulsd", { XM, EXq } },
2995 { "cvtps2pd", { XM, EXq } },
2996 { "cvtss2sd", { XM, EXd } },
2997 { "cvtpd2ps", { XM, EXx } },
2998 { "cvtsd2ss", { XM, EXq } },
3003 { "cvtdq2ps", { XM, EXx } },
3004 { "cvttps2dq", { XM, EXx } },
3005 { "cvtps2dq", { XM, EXx } },
3010 { "subps", { XM, EXx } },
3011 { "subss", { XM, EXd } },
3012 { "subpd", { XM, EXx } },
3013 { "subsd", { XM, EXq } },
3018 { "minps", { XM, EXx } },
3019 { "minss", { XM, EXd } },
3020 { "minpd", { XM, EXx } },
3021 { "minsd", { XM, EXq } },
3026 { "divps", { XM, EXx } },
3027 { "divss", { XM, EXd } },
3028 { "divpd", { XM, EXx } },
3029 { "divsd", { XM, EXq } },
3034 { "maxps", { XM, EXx } },
3035 { "maxss", { XM, EXd } },
3036 { "maxpd", { XM, EXx } },
3037 { "maxsd", { XM, EXq } },
3042 { "punpcklbw",{ MX, EMd } },
3044 { "punpcklbw",{ MX, EMx } },
3049 { "punpcklwd",{ MX, EMd } },
3051 { "punpcklwd",{ MX, EMx } },
3056 { "punpckldq",{ MX, EMd } },
3058 { "punpckldq",{ MX, EMx } },
3065 { "punpcklqdq", { XM, EXx } },
3072 { "punpckhqdq", { XM, EXx } },
3077 { "movq", { MX, EM } },
3078 { "movdqu", { XM, EXx } },
3079 { "movdqa", { XM, EXx } },
3084 { "pshufw", { MX, EM, Ib } },
3085 { "pshufhw",{ XM, EXx, Ib } },
3086 { "pshufd", { XM, EXx, Ib } },
3087 { "pshuflw",{ XM, EXx, Ib } },
3090 /* PREFIX_0F73_REG_3 */
3094 { "psrldq", { XS, Ib } },
3097 /* PREFIX_0F73_REG_7 */
3101 { "pslldq", { XS, Ib } },
3106 {"vmread", { Em, Gm } },
3108 {"extrq", { XS, Ib, Ib } },
3109 {"insertq", { XM, XS, Ib, Ib } },
3114 {"vmwrite", { Gm, Em } },
3116 {"extrq", { XM, XS } },
3117 {"insertq", { XM, XS } },
3124 { "haddpd", { XM, EXx } },
3125 { "haddps", { XM, EXx } },
3132 { "hsubpd", { XM, EXx } },
3133 { "hsubps", { XM, EXx } },
3138 { "movK", { Edq, MX } },
3139 { "movq", { XM, EXq } },
3140 { "movK", { Edq, XM } },
3145 { "movq", { EMS, MX } },
3146 { "movdqu", { EXxS, XM } },
3147 { "movdqa", { EXxS, XM } },
3150 /* PREFIX_0FAE_REG_0 */
3153 { "rdfsbase", { Ev } },
3156 /* PREFIX_0FAE_REG_1 */
3159 { "rdgsbase", { Ev } },
3162 /* PREFIX_0FAE_REG_2 */
3165 { "wrfsbase", { Ev } },
3168 /* PREFIX_0FAE_REG_3 */
3171 { "wrgsbase", { Ev } },
3177 { "popcntS", { Gv, Ev } },
3182 { "bsfS", { Gv, Ev } },
3183 { "tzcntS", { Gv, Ev } },
3184 { "bsfS", { Gv, Ev } },
3189 { "bsrS", { Gv, Ev } },
3190 { "lzcntS", { Gv, Ev } },
3191 { "bsrS", { Gv, Ev } },
3196 { "cmpps", { XM, EXx, CMP } },
3197 { "cmpss", { XM, EXd, CMP } },
3198 { "cmppd", { XM, EXx, CMP } },
3199 { "cmpsd", { XM, EXq, CMP } },
3204 { "movntiS", { Ma, Gv } },
3207 /* PREFIX_0FC7_REG_6 */
3209 { "vmptrld",{ Mq } },
3210 { "vmxon", { Mq } },
3211 { "vmclear",{ Mq } },
3218 { "addsubpd", { XM, EXx } },
3219 { "addsubps", { XM, EXx } },
3225 { "movq2dq",{ XM, MS } },
3226 { "movq", { EXqS, XM } },
3227 { "movdq2q",{ MX, XS } },
3233 { "cvtdq2pd", { XM, EXq } },
3234 { "cvttpd2dq", { XM, EXx } },
3235 { "cvtpd2dq", { XM, EXx } },
3240 { "movntq", { Mq, MX } },
3242 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3250 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3255 { "maskmovq", { MX, MS } },
3257 { "maskmovdqu", { XM, XS } },
3264 { "pblendvb", { XM, EXx, XMM0 } },
3271 { "blendvps", { XM, EXx, XMM0 } },
3278 { "blendvpd", { XM, EXx, XMM0 } },
3285 { "ptest", { XM, EXx } },
3292 { "pmovsxbw", { XM, EXq } },
3299 { "pmovsxbd", { XM, EXd } },
3306 { "pmovsxbq", { XM, EXw } },
3313 { "pmovsxwd", { XM, EXq } },
3320 { "pmovsxwq", { XM, EXd } },
3327 { "pmovsxdq", { XM, EXq } },
3334 { "pmuldq", { XM, EXx } },
3341 { "pcmpeqq", { XM, EXx } },
3348 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3355 { "packusdw", { XM, EXx } },
3362 { "pmovzxbw", { XM, EXq } },
3369 { "pmovzxbd", { XM, EXd } },
3376 { "pmovzxbq", { XM, EXw } },
3383 { "pmovzxwd", { XM, EXq } },
3390 { "pmovzxwq", { XM, EXd } },
3397 { "pmovzxdq", { XM, EXq } },
3404 { "pcmpgtq", { XM, EXx } },
3411 { "pminsb", { XM, EXx } },
3418 { "pminsd", { XM, EXx } },
3425 { "pminuw", { XM, EXx } },
3432 { "pminud", { XM, EXx } },
3439 { "pmaxsb", { XM, EXx } },
3446 { "pmaxsd", { XM, EXx } },
3453 { "pmaxuw", { XM, EXx } },
3460 { "pmaxud", { XM, EXx } },
3467 { "pmulld", { XM, EXx } },
3474 { "phminposuw", { XM, EXx } },
3481 { "invept", { Gm, Mo } },
3488 { "invvpid", { Gm, Mo } },
3495 { "invpcid", { Gm, M } },
3502 { "aesimc", { XM, EXx } },
3509 { "aesenc", { XM, EXx } },
3516 { "aesenclast", { XM, EXx } },
3523 { "aesdec", { XM, EXx } },
3530 { "aesdeclast", { XM, EXx } },
3535 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3537 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3538 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
3543 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3545 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3546 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
3552 { "adoxS", { Gdq, Edq} },
3553 { "adcxS", { Gdq, Edq} },
3561 { "roundps", { XM, EXx, Ib } },
3568 { "roundpd", { XM, EXx, Ib } },
3575 { "roundss", { XM, EXd, Ib } },
3582 { "roundsd", { XM, EXq, Ib } },
3589 { "blendps", { XM, EXx, Ib } },
3596 { "blendpd", { XM, EXx, Ib } },
3603 { "pblendw", { XM, EXx, Ib } },
3610 { "pextrb", { Edqb, XM, Ib } },
3617 { "pextrw", { Edqw, XM, Ib } },
3624 { "pextrK", { Edq, XM, Ib } },
3631 { "extractps", { Edqd, XM, Ib } },
3638 { "pinsrb", { XM, Edqb, Ib } },
3645 { "insertps", { XM, EXd, Ib } },
3652 { "pinsrK", { XM, Edq, Ib } },
3659 { "dpps", { XM, EXx, Ib } },
3666 { "dppd", { XM, EXx, Ib } },
3673 { "mpsadbw", { XM, EXx, Ib } },
3680 { "pclmulqdq", { XM, EXx, PCLMUL } },
3687 { "pcmpestrm", { XM, EXx, Ib } },
3694 { "pcmpestri", { XM, EXx, Ib } },
3701 { "pcmpistrm", { XM, EXx, Ib } },
3708 { "pcmpistri", { XM, EXx, Ib } },
3715 { "aeskeygenassist", { XM, EXx, Ib } },
3718 /* PREFIX_VEX_0F10 */
3720 { VEX_W_TABLE (VEX_W_0F10_P_0) },
3721 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
3722 { VEX_W_TABLE (VEX_W_0F10_P_2) },
3723 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
3726 /* PREFIX_VEX_0F11 */
3728 { VEX_W_TABLE (VEX_W_0F11_P_0) },
3729 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
3730 { VEX_W_TABLE (VEX_W_0F11_P_2) },
3731 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
3734 /* PREFIX_VEX_0F12 */
3736 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3737 { VEX_W_TABLE (VEX_W_0F12_P_1) },
3738 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
3739 { VEX_W_TABLE (VEX_W_0F12_P_3) },
3742 /* PREFIX_VEX_0F16 */
3744 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3745 { VEX_W_TABLE (VEX_W_0F16_P_1) },
3746 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
3749 /* PREFIX_VEX_0F2A */
3752 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
3754 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
3757 /* PREFIX_VEX_0F2C */
3760 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
3762 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
3765 /* PREFIX_VEX_0F2D */
3768 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
3770 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
3773 /* PREFIX_VEX_0F2E */
3775 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
3777 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
3780 /* PREFIX_VEX_0F2F */
3782 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
3784 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
3787 /* PREFIX_VEX_0F51 */
3789 { VEX_W_TABLE (VEX_W_0F51_P_0) },
3790 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
3791 { VEX_W_TABLE (VEX_W_0F51_P_2) },
3792 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
3795 /* PREFIX_VEX_0F52 */
3797 { VEX_W_TABLE (VEX_W_0F52_P_0) },
3798 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
3801 /* PREFIX_VEX_0F53 */
3803 { VEX_W_TABLE (VEX_W_0F53_P_0) },
3804 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
3807 /* PREFIX_VEX_0F58 */
3809 { VEX_W_TABLE (VEX_W_0F58_P_0) },
3810 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
3811 { VEX_W_TABLE (VEX_W_0F58_P_2) },
3812 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
3815 /* PREFIX_VEX_0F59 */
3817 { VEX_W_TABLE (VEX_W_0F59_P_0) },
3818 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
3819 { VEX_W_TABLE (VEX_W_0F59_P_2) },
3820 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
3823 /* PREFIX_VEX_0F5A */
3825 { VEX_W_TABLE (VEX_W_0F5A_P_0) },
3826 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
3827 { "vcvtpd2ps%XY", { XMM, EXx } },
3828 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
3831 /* PREFIX_VEX_0F5B */
3833 { VEX_W_TABLE (VEX_W_0F5B_P_0) },
3834 { VEX_W_TABLE (VEX_W_0F5B_P_1) },
3835 { VEX_W_TABLE (VEX_W_0F5B_P_2) },
3838 /* PREFIX_VEX_0F5C */
3840 { VEX_W_TABLE (VEX_W_0F5C_P_0) },
3841 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
3842 { VEX_W_TABLE (VEX_W_0F5C_P_2) },
3843 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
3846 /* PREFIX_VEX_0F5D */
3848 { VEX_W_TABLE (VEX_W_0F5D_P_0) },
3849 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
3850 { VEX_W_TABLE (VEX_W_0F5D_P_2) },
3851 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
3854 /* PREFIX_VEX_0F5E */
3856 { VEX_W_TABLE (VEX_W_0F5E_P_0) },
3857 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
3858 { VEX_W_TABLE (VEX_W_0F5E_P_2) },
3859 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
3862 /* PREFIX_VEX_0F5F */
3864 { VEX_W_TABLE (VEX_W_0F5F_P_0) },
3865 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
3866 { VEX_W_TABLE (VEX_W_0F5F_P_2) },
3867 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
3870 /* PREFIX_VEX_0F60 */
3874 { VEX_W_TABLE (VEX_W_0F60_P_2) },
3877 /* PREFIX_VEX_0F61 */
3881 { VEX_W_TABLE (VEX_W_0F61_P_2) },
3884 /* PREFIX_VEX_0F62 */
3888 { VEX_W_TABLE (VEX_W_0F62_P_2) },
3891 /* PREFIX_VEX_0F63 */
3895 { VEX_W_TABLE (VEX_W_0F63_P_2) },
3898 /* PREFIX_VEX_0F64 */
3902 { VEX_W_TABLE (VEX_W_0F64_P_2) },
3905 /* PREFIX_VEX_0F65 */
3909 { VEX_W_TABLE (VEX_W_0F65_P_2) },
3912 /* PREFIX_VEX_0F66 */
3916 { VEX_W_TABLE (VEX_W_0F66_P_2) },
3919 /* PREFIX_VEX_0F67 */
3923 { VEX_W_TABLE (VEX_W_0F67_P_2) },
3926 /* PREFIX_VEX_0F68 */
3930 { VEX_W_TABLE (VEX_W_0F68_P_2) },
3933 /* PREFIX_VEX_0F69 */
3937 { VEX_W_TABLE (VEX_W_0F69_P_2) },
3940 /* PREFIX_VEX_0F6A */
3944 { VEX_W_TABLE (VEX_W_0F6A_P_2) },
3947 /* PREFIX_VEX_0F6B */
3951 { VEX_W_TABLE (VEX_W_0F6B_P_2) },
3954 /* PREFIX_VEX_0F6C */
3958 { VEX_W_TABLE (VEX_W_0F6C_P_2) },
3961 /* PREFIX_VEX_0F6D */
3965 { VEX_W_TABLE (VEX_W_0F6D_P_2) },
3968 /* PREFIX_VEX_0F6E */
3972 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
3975 /* PREFIX_VEX_0F6F */
3978 { VEX_W_TABLE (VEX_W_0F6F_P_1) },
3979 { VEX_W_TABLE (VEX_W_0F6F_P_2) },
3982 /* PREFIX_VEX_0F70 */
3985 { VEX_W_TABLE (VEX_W_0F70_P_1) },
3986 { VEX_W_TABLE (VEX_W_0F70_P_2) },
3987 { VEX_W_TABLE (VEX_W_0F70_P_3) },
3990 /* PREFIX_VEX_0F71_REG_2 */
3994 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
3997 /* PREFIX_VEX_0F71_REG_4 */
4001 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4004 /* PREFIX_VEX_0F71_REG_6 */
4008 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4011 /* PREFIX_VEX_0F72_REG_2 */
4015 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4018 /* PREFIX_VEX_0F72_REG_4 */
4022 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4025 /* PREFIX_VEX_0F72_REG_6 */
4029 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4032 /* PREFIX_VEX_0F73_REG_2 */
4036 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4039 /* PREFIX_VEX_0F73_REG_3 */
4043 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4046 /* PREFIX_VEX_0F73_REG_6 */
4050 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4053 /* PREFIX_VEX_0F73_REG_7 */
4057 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4060 /* PREFIX_VEX_0F74 */
4064 { VEX_W_TABLE (VEX_W_0F74_P_2) },
4067 /* PREFIX_VEX_0F75 */
4071 { VEX_W_TABLE (VEX_W_0F75_P_2) },
4074 /* PREFIX_VEX_0F76 */
4078 { VEX_W_TABLE (VEX_W_0F76_P_2) },
4081 /* PREFIX_VEX_0F77 */
4083 { VEX_W_TABLE (VEX_W_0F77_P_0) },
4086 /* PREFIX_VEX_0F7C */
4090 { VEX_W_TABLE (VEX_W_0F7C_P_2) },
4091 { VEX_W_TABLE (VEX_W_0F7C_P_3) },
4094 /* PREFIX_VEX_0F7D */
4098 { VEX_W_TABLE (VEX_W_0F7D_P_2) },
4099 { VEX_W_TABLE (VEX_W_0F7D_P_3) },
4102 /* PREFIX_VEX_0F7E */
4105 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4106 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4109 /* PREFIX_VEX_0F7F */
4112 { VEX_W_TABLE (VEX_W_0F7F_P_1) },
4113 { VEX_W_TABLE (VEX_W_0F7F_P_2) },
4116 /* PREFIX_VEX_0FC2 */
4118 { VEX_W_TABLE (VEX_W_0FC2_P_0) },
4119 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
4120 { VEX_W_TABLE (VEX_W_0FC2_P_2) },
4121 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
4124 /* PREFIX_VEX_0FC4 */
4128 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
4131 /* PREFIX_VEX_0FC5 */
4135 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
4138 /* PREFIX_VEX_0FD0 */
4142 { VEX_W_TABLE (VEX_W_0FD0_P_2) },
4143 { VEX_W_TABLE (VEX_W_0FD0_P_3) },
4146 /* PREFIX_VEX_0FD1 */
4150 { VEX_W_TABLE (VEX_W_0FD1_P_2) },
4153 /* PREFIX_VEX_0FD2 */
4157 { VEX_W_TABLE (VEX_W_0FD2_P_2) },
4160 /* PREFIX_VEX_0FD3 */
4164 { VEX_W_TABLE (VEX_W_0FD3_P_2) },
4167 /* PREFIX_VEX_0FD4 */
4171 { VEX_W_TABLE (VEX_W_0FD4_P_2) },
4174 /* PREFIX_VEX_0FD5 */
4178 { VEX_W_TABLE (VEX_W_0FD5_P_2) },
4181 /* PREFIX_VEX_0FD6 */
4185 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
4188 /* PREFIX_VEX_0FD7 */
4192 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
4195 /* PREFIX_VEX_0FD8 */
4199 { VEX_W_TABLE (VEX_W_0FD8_P_2) },
4202 /* PREFIX_VEX_0FD9 */
4206 { VEX_W_TABLE (VEX_W_0FD9_P_2) },
4209 /* PREFIX_VEX_0FDA */
4213 { VEX_W_TABLE (VEX_W_0FDA_P_2) },
4216 /* PREFIX_VEX_0FDB */
4220 { VEX_W_TABLE (VEX_W_0FDB_P_2) },
4223 /* PREFIX_VEX_0FDC */
4227 { VEX_W_TABLE (VEX_W_0FDC_P_2) },
4230 /* PREFIX_VEX_0FDD */
4234 { VEX_W_TABLE (VEX_W_0FDD_P_2) },
4237 /* PREFIX_VEX_0FDE */
4241 { VEX_W_TABLE (VEX_W_0FDE_P_2) },
4244 /* PREFIX_VEX_0FDF */
4248 { VEX_W_TABLE (VEX_W_0FDF_P_2) },
4251 /* PREFIX_VEX_0FE0 */
4255 { VEX_W_TABLE (VEX_W_0FE0_P_2) },
4258 /* PREFIX_VEX_0FE1 */
4262 { VEX_W_TABLE (VEX_W_0FE1_P_2) },
4265 /* PREFIX_VEX_0FE2 */
4269 { VEX_W_TABLE (VEX_W_0FE2_P_2) },
4272 /* PREFIX_VEX_0FE3 */
4276 { VEX_W_TABLE (VEX_W_0FE3_P_2) },
4279 /* PREFIX_VEX_0FE4 */
4283 { VEX_W_TABLE (VEX_W_0FE4_P_2) },
4286 /* PREFIX_VEX_0FE5 */
4290 { VEX_W_TABLE (VEX_W_0FE5_P_2) },
4293 /* PREFIX_VEX_0FE6 */
4296 { VEX_W_TABLE (VEX_W_0FE6_P_1) },
4297 { VEX_W_TABLE (VEX_W_0FE6_P_2) },
4298 { VEX_W_TABLE (VEX_W_0FE6_P_3) },
4301 /* PREFIX_VEX_0FE7 */
4305 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
4308 /* PREFIX_VEX_0FE8 */
4312 { VEX_W_TABLE (VEX_W_0FE8_P_2) },
4315 /* PREFIX_VEX_0FE9 */
4319 { VEX_W_TABLE (VEX_W_0FE9_P_2) },
4322 /* PREFIX_VEX_0FEA */
4326 { VEX_W_TABLE (VEX_W_0FEA_P_2) },
4329 /* PREFIX_VEX_0FEB */
4333 { VEX_W_TABLE (VEX_W_0FEB_P_2) },
4336 /* PREFIX_VEX_0FEC */
4340 { VEX_W_TABLE (VEX_W_0FEC_P_2) },
4343 /* PREFIX_VEX_0FED */
4347 { VEX_W_TABLE (VEX_W_0FED_P_2) },
4350 /* PREFIX_VEX_0FEE */
4354 { VEX_W_TABLE (VEX_W_0FEE_P_2) },
4357 /* PREFIX_VEX_0FEF */
4361 { VEX_W_TABLE (VEX_W_0FEF_P_2) },
4364 /* PREFIX_VEX_0FF0 */
4369 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4372 /* PREFIX_VEX_0FF1 */
4376 { VEX_W_TABLE (VEX_W_0FF1_P_2) },
4379 /* PREFIX_VEX_0FF2 */
4383 { VEX_W_TABLE (VEX_W_0FF2_P_2) },
4386 /* PREFIX_VEX_0FF3 */
4390 { VEX_W_TABLE (VEX_W_0FF3_P_2) },
4393 /* PREFIX_VEX_0FF4 */
4397 { VEX_W_TABLE (VEX_W_0FF4_P_2) },
4400 /* PREFIX_VEX_0FF5 */
4404 { VEX_W_TABLE (VEX_W_0FF5_P_2) },
4407 /* PREFIX_VEX_0FF6 */
4411 { VEX_W_TABLE (VEX_W_0FF6_P_2) },
4414 /* PREFIX_VEX_0FF7 */
4418 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
4421 /* PREFIX_VEX_0FF8 */
4425 { VEX_W_TABLE (VEX_W_0FF8_P_2) },
4428 /* PREFIX_VEX_0FF9 */
4432 { VEX_W_TABLE (VEX_W_0FF9_P_2) },
4435 /* PREFIX_VEX_0FFA */
4439 { VEX_W_TABLE (VEX_W_0FFA_P_2) },
4442 /* PREFIX_VEX_0FFB */
4446 { VEX_W_TABLE (VEX_W_0FFB_P_2) },
4449 /* PREFIX_VEX_0FFC */
4453 { VEX_W_TABLE (VEX_W_0FFC_P_2) },
4456 /* PREFIX_VEX_0FFD */
4460 { VEX_W_TABLE (VEX_W_0FFD_P_2) },
4463 /* PREFIX_VEX_0FFE */
4467 { VEX_W_TABLE (VEX_W_0FFE_P_2) },
4470 /* PREFIX_VEX_0F3800 */
4474 { VEX_W_TABLE (VEX_W_0F3800_P_2) },
4477 /* PREFIX_VEX_0F3801 */
4481 { VEX_W_TABLE (VEX_W_0F3801_P_2) },
4484 /* PREFIX_VEX_0F3802 */
4488 { VEX_W_TABLE (VEX_W_0F3802_P_2) },
4491 /* PREFIX_VEX_0F3803 */
4495 { VEX_W_TABLE (VEX_W_0F3803_P_2) },
4498 /* PREFIX_VEX_0F3804 */
4502 { VEX_W_TABLE (VEX_W_0F3804_P_2) },
4505 /* PREFIX_VEX_0F3805 */
4509 { VEX_W_TABLE (VEX_W_0F3805_P_2) },
4512 /* PREFIX_VEX_0F3806 */
4516 { VEX_W_TABLE (VEX_W_0F3806_P_2) },
4519 /* PREFIX_VEX_0F3807 */
4523 { VEX_W_TABLE (VEX_W_0F3807_P_2) },
4526 /* PREFIX_VEX_0F3808 */
4530 { VEX_W_TABLE (VEX_W_0F3808_P_2) },
4533 /* PREFIX_VEX_0F3809 */
4537 { VEX_W_TABLE (VEX_W_0F3809_P_2) },
4540 /* PREFIX_VEX_0F380A */
4544 { VEX_W_TABLE (VEX_W_0F380A_P_2) },
4547 /* PREFIX_VEX_0F380B */
4551 { VEX_W_TABLE (VEX_W_0F380B_P_2) },
4554 /* PREFIX_VEX_0F380C */
4558 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
4561 /* PREFIX_VEX_0F380D */
4565 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
4568 /* PREFIX_VEX_0F380E */
4572 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
4575 /* PREFIX_VEX_0F380F */
4579 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
4582 /* PREFIX_VEX_0F3813 */
4586 { "vcvtph2ps", { XM, EXxmmq } },
4589 /* PREFIX_VEX_0F3816 */
4593 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
4596 /* PREFIX_VEX_0F3817 */
4600 { VEX_W_TABLE (VEX_W_0F3817_P_2) },
4603 /* PREFIX_VEX_0F3818 */
4607 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
4610 /* PREFIX_VEX_0F3819 */
4614 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
4617 /* PREFIX_VEX_0F381A */
4621 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
4624 /* PREFIX_VEX_0F381C */
4628 { VEX_W_TABLE (VEX_W_0F381C_P_2) },
4631 /* PREFIX_VEX_0F381D */
4635 { VEX_W_TABLE (VEX_W_0F381D_P_2) },
4638 /* PREFIX_VEX_0F381E */
4642 { VEX_W_TABLE (VEX_W_0F381E_P_2) },
4645 /* PREFIX_VEX_0F3820 */
4649 { VEX_W_TABLE (VEX_W_0F3820_P_2) },
4652 /* PREFIX_VEX_0F3821 */
4656 { VEX_W_TABLE (VEX_W_0F3821_P_2) },
4659 /* PREFIX_VEX_0F3822 */
4663 { VEX_W_TABLE (VEX_W_0F3822_P_2) },
4666 /* PREFIX_VEX_0F3823 */
4670 { VEX_W_TABLE (VEX_W_0F3823_P_2) },
4673 /* PREFIX_VEX_0F3824 */
4677 { VEX_W_TABLE (VEX_W_0F3824_P_2) },
4680 /* PREFIX_VEX_0F3825 */
4684 { VEX_W_TABLE (VEX_W_0F3825_P_2) },
4687 /* PREFIX_VEX_0F3828 */
4691 { VEX_W_TABLE (VEX_W_0F3828_P_2) },
4694 /* PREFIX_VEX_0F3829 */
4698 { VEX_W_TABLE (VEX_W_0F3829_P_2) },
4701 /* PREFIX_VEX_0F382A */
4705 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
4708 /* PREFIX_VEX_0F382B */
4712 { VEX_W_TABLE (VEX_W_0F382B_P_2) },
4715 /* PREFIX_VEX_0F382C */
4719 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
4722 /* PREFIX_VEX_0F382D */
4726 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
4729 /* PREFIX_VEX_0F382E */
4733 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
4736 /* PREFIX_VEX_0F382F */
4740 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
4743 /* PREFIX_VEX_0F3830 */
4747 { VEX_W_TABLE (VEX_W_0F3830_P_2) },
4750 /* PREFIX_VEX_0F3831 */
4754 { VEX_W_TABLE (VEX_W_0F3831_P_2) },
4757 /* PREFIX_VEX_0F3832 */
4761 { VEX_W_TABLE (VEX_W_0F3832_P_2) },
4764 /* PREFIX_VEX_0F3833 */
4768 { VEX_W_TABLE (VEX_W_0F3833_P_2) },
4771 /* PREFIX_VEX_0F3834 */
4775 { VEX_W_TABLE (VEX_W_0F3834_P_2) },
4778 /* PREFIX_VEX_0F3835 */
4782 { VEX_W_TABLE (VEX_W_0F3835_P_2) },
4785 /* PREFIX_VEX_0F3836 */
4789 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
4792 /* PREFIX_VEX_0F3837 */
4796 { VEX_W_TABLE (VEX_W_0F3837_P_2) },
4799 /* PREFIX_VEX_0F3838 */
4803 { VEX_W_TABLE (VEX_W_0F3838_P_2) },
4806 /* PREFIX_VEX_0F3839 */
4810 { VEX_W_TABLE (VEX_W_0F3839_P_2) },
4813 /* PREFIX_VEX_0F383A */
4817 { VEX_W_TABLE (VEX_W_0F383A_P_2) },
4820 /* PREFIX_VEX_0F383B */
4824 { VEX_W_TABLE (VEX_W_0F383B_P_2) },
4827 /* PREFIX_VEX_0F383C */
4831 { VEX_W_TABLE (VEX_W_0F383C_P_2) },
4834 /* PREFIX_VEX_0F383D */
4838 { VEX_W_TABLE (VEX_W_0F383D_P_2) },
4841 /* PREFIX_VEX_0F383E */
4845 { VEX_W_TABLE (VEX_W_0F383E_P_2) },
4848 /* PREFIX_VEX_0F383F */
4852 { VEX_W_TABLE (VEX_W_0F383F_P_2) },
4855 /* PREFIX_VEX_0F3840 */
4859 { VEX_W_TABLE (VEX_W_0F3840_P_2) },
4862 /* PREFIX_VEX_0F3841 */
4866 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
4869 /* PREFIX_VEX_0F3845 */
4873 { "vpsrlv%LW", { XM, Vex, EXx } },
4876 /* PREFIX_VEX_0F3846 */
4880 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
4883 /* PREFIX_VEX_0F3847 */
4887 { "vpsllv%LW", { XM, Vex, EXx } },
4890 /* PREFIX_VEX_0F3858 */
4894 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
4897 /* PREFIX_VEX_0F3859 */
4901 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
4904 /* PREFIX_VEX_0F385A */
4908 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
4911 /* PREFIX_VEX_0F3878 */
4915 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
4918 /* PREFIX_VEX_0F3879 */
4922 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
4925 /* PREFIX_VEX_0F388C */
4929 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
4932 /* PREFIX_VEX_0F388E */
4936 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
4939 /* PREFIX_VEX_0F3890 */
4943 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
4946 /* PREFIX_VEX_0F3891 */
4950 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
4953 /* PREFIX_VEX_0F3892 */
4957 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
4960 /* PREFIX_VEX_0F3893 */
4964 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
4967 /* PREFIX_VEX_0F3896 */
4971 { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4974 /* PREFIX_VEX_0F3897 */
4978 { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4981 /* PREFIX_VEX_0F3898 */
4985 { "vfmadd132p%XW", { XM, Vex, EXx } },
4988 /* PREFIX_VEX_0F3899 */
4992 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4995 /* PREFIX_VEX_0F389A */
4999 { "vfmsub132p%XW", { XM, Vex, EXx } },
5002 /* PREFIX_VEX_0F389B */
5006 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5009 /* PREFIX_VEX_0F389C */
5013 { "vfnmadd132p%XW", { XM, Vex, EXx } },
5016 /* PREFIX_VEX_0F389D */
5020 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5023 /* PREFIX_VEX_0F389E */
5027 { "vfnmsub132p%XW", { XM, Vex, EXx } },
5030 /* PREFIX_VEX_0F389F */
5034 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5037 /* PREFIX_VEX_0F38A6 */
5041 { "vfmaddsub213p%XW", { XM, Vex, EXx } },
5045 /* PREFIX_VEX_0F38A7 */
5049 { "vfmsubadd213p%XW", { XM, Vex, EXx } },
5052 /* PREFIX_VEX_0F38A8 */
5056 { "vfmadd213p%XW", { XM, Vex, EXx } },
5059 /* PREFIX_VEX_0F38A9 */
5063 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5066 /* PREFIX_VEX_0F38AA */
5070 { "vfmsub213p%XW", { XM, Vex, EXx } },
5073 /* PREFIX_VEX_0F38AB */
5077 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5080 /* PREFIX_VEX_0F38AC */
5084 { "vfnmadd213p%XW", { XM, Vex, EXx } },
5087 /* PREFIX_VEX_0F38AD */
5091 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5094 /* PREFIX_VEX_0F38AE */
5098 { "vfnmsub213p%XW", { XM, Vex, EXx } },
5101 /* PREFIX_VEX_0F38AF */
5105 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5108 /* PREFIX_VEX_0F38B6 */
5112 { "vfmaddsub231p%XW", { XM, Vex, EXx } },
5115 /* PREFIX_VEX_0F38B7 */
5119 { "vfmsubadd231p%XW", { XM, Vex, EXx } },
5122 /* PREFIX_VEX_0F38B8 */
5126 { "vfmadd231p%XW", { XM, Vex, EXx } },
5129 /* PREFIX_VEX_0F38B9 */
5133 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5136 /* PREFIX_VEX_0F38BA */
5140 { "vfmsub231p%XW", { XM, Vex, EXx } },
5143 /* PREFIX_VEX_0F38BB */
5147 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5150 /* PREFIX_VEX_0F38BC */
5154 { "vfnmadd231p%XW", { XM, Vex, EXx } },
5157 /* PREFIX_VEX_0F38BD */
5161 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5164 /* PREFIX_VEX_0F38BE */
5168 { "vfnmsub231p%XW", { XM, Vex, EXx } },
5171 /* PREFIX_VEX_0F38BF */
5175 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5178 /* PREFIX_VEX_0F38DB */
5182 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
5185 /* PREFIX_VEX_0F38DC */
5189 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
5192 /* PREFIX_VEX_0F38DD */
5196 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
5199 /* PREFIX_VEX_0F38DE */
5203 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
5206 /* PREFIX_VEX_0F38DF */
5210 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
5213 /* PREFIX_VEX_0F38F2 */
5215 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
5218 /* PREFIX_VEX_0F38F3_REG_1 */
5220 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
5223 /* PREFIX_VEX_0F38F3_REG_2 */
5225 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
5228 /* PREFIX_VEX_0F38F3_REG_3 */
5230 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
5233 /* PREFIX_VEX_0F38F5 */
5235 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
5236 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
5238 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
5241 /* PREFIX_VEX_0F38F6 */
5246 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
5249 /* PREFIX_VEX_0F38F7 */
5251 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
5252 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
5253 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
5254 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
5257 /* PREFIX_VEX_0F3A00 */
5261 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
5264 /* PREFIX_VEX_0F3A01 */
5268 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
5271 /* PREFIX_VEX_0F3A02 */
5275 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
5278 /* PREFIX_VEX_0F3A04 */
5282 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
5285 /* PREFIX_VEX_0F3A05 */
5289 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
5292 /* PREFIX_VEX_0F3A06 */
5296 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
5299 /* PREFIX_VEX_0F3A08 */
5303 { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
5306 /* PREFIX_VEX_0F3A09 */
5310 { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
5313 /* PREFIX_VEX_0F3A0A */
5317 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
5320 /* PREFIX_VEX_0F3A0B */
5324 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
5327 /* PREFIX_VEX_0F3A0C */
5331 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
5334 /* PREFIX_VEX_0F3A0D */
5338 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
5341 /* PREFIX_VEX_0F3A0E */
5345 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
5348 /* PREFIX_VEX_0F3A0F */
5352 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
5355 /* PREFIX_VEX_0F3A14 */
5359 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
5362 /* PREFIX_VEX_0F3A15 */
5366 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
5369 /* PREFIX_VEX_0F3A16 */
5373 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
5376 /* PREFIX_VEX_0F3A17 */
5380 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
5383 /* PREFIX_VEX_0F3A18 */
5387 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
5390 /* PREFIX_VEX_0F3A19 */
5394 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
5397 /* PREFIX_VEX_0F3A1D */
5401 { "vcvtps2ph", { EXxmmq, XM, Ib } },
5404 /* PREFIX_VEX_0F3A20 */
5408 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
5411 /* PREFIX_VEX_0F3A21 */
5415 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
5418 /* PREFIX_VEX_0F3A22 */
5422 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
5425 /* PREFIX_VEX_0F3A38 */
5429 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
5432 /* PREFIX_VEX_0F3A39 */
5436 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
5439 /* PREFIX_VEX_0F3A40 */
5443 { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
5446 /* PREFIX_VEX_0F3A41 */
5450 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
5453 /* PREFIX_VEX_0F3A42 */
5457 { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
5460 /* PREFIX_VEX_0F3A44 */
5464 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
5467 /* PREFIX_VEX_0F3A46 */
5471 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
5474 /* PREFIX_VEX_0F3A48 */
5478 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
5481 /* PREFIX_VEX_0F3A49 */
5485 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
5488 /* PREFIX_VEX_0F3A4A */
5492 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
5495 /* PREFIX_VEX_0F3A4B */
5499 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
5502 /* PREFIX_VEX_0F3A4C */
5506 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
5509 /* PREFIX_VEX_0F3A5C */
5513 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5516 /* PREFIX_VEX_0F3A5D */
5520 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5523 /* PREFIX_VEX_0F3A5E */
5527 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5530 /* PREFIX_VEX_0F3A5F */
5534 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5537 /* PREFIX_VEX_0F3A60 */
5541 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
5545 /* PREFIX_VEX_0F3A61 */
5549 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
5552 /* PREFIX_VEX_0F3A62 */
5556 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
5559 /* PREFIX_VEX_0F3A63 */
5563 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
5566 /* PREFIX_VEX_0F3A68 */
5570 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5573 /* PREFIX_VEX_0F3A69 */
5577 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5580 /* PREFIX_VEX_0F3A6A */
5584 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
5587 /* PREFIX_VEX_0F3A6B */
5591 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
5594 /* PREFIX_VEX_0F3A6C */
5598 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5601 /* PREFIX_VEX_0F3A6D */
5605 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5608 /* PREFIX_VEX_0F3A6E */
5612 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
5615 /* PREFIX_VEX_0F3A6F */
5619 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
5622 /* PREFIX_VEX_0F3A78 */
5626 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5629 /* PREFIX_VEX_0F3A79 */
5633 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5636 /* PREFIX_VEX_0F3A7A */
5640 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
5643 /* PREFIX_VEX_0F3A7B */
5647 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
5650 /* PREFIX_VEX_0F3A7C */
5654 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5658 /* PREFIX_VEX_0F3A7D */
5662 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5665 /* PREFIX_VEX_0F3A7E */
5669 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
5672 /* PREFIX_VEX_0F3A7F */
5676 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
5679 /* PREFIX_VEX_0F3ADF */
5683 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
5686 /* PREFIX_VEX_0F3AF0 */
5691 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
5695 static const struct dis386 x86_64_table[][2] = {
5698 { "pushP", { es } },
5708 { "pushP", { cs } },
5713 { "pushP", { ss } },
5723 { "pushP", { ds } },
5753 { "pushaP", { XX } },
5758 { "popaP", { XX } },
5763 { MOD_TABLE (MOD_62_32BIT) },
5768 { "arpl", { Ew, Gw } },
5769 { "movs{lq|xd}", { Gv, Ed } },
5774 { "ins{R|}", { Yzr, indirDX } },
5775 { "ins{G|}", { Yzr, indirDX } },
5780 { "outs{R|}", { indirDXr, Xz } },
5781 { "outs{G|}", { indirDXr, Xz } },
5786 { "Jcall{T|}", { Ap } },
5791 { MOD_TABLE (MOD_C4_32BIT) },
5792 { VEX_C4_TABLE (VEX_0F) },
5797 { MOD_TABLE (MOD_C5_32BIT) },
5798 { VEX_C5_TABLE (VEX_0F) },
5818 { "Jjmp{T|}", { Ap } },
5821 /* X86_64_0F01_REG_0 */
5823 { "sgdt{Q|IQ}", { M } },
5827 /* X86_64_0F01_REG_1 */
5829 { "sidt{Q|IQ}", { M } },
5833 /* X86_64_0F01_REG_2 */
5835 { "lgdt{Q|Q}", { M } },
5839 /* X86_64_0F01_REG_3 */
5841 { "lidt{Q|Q}", { M } },
5846 static const struct dis386 three_byte_table[][256] = {
5848 /* THREE_BYTE_0F38 */
5851 { "pshufb", { MX, EM } },
5852 { "phaddw", { MX, EM } },
5853 { "phaddd", { MX, EM } },
5854 { "phaddsw", { MX, EM } },
5855 { "pmaddubsw", { MX, EM } },
5856 { "phsubw", { MX, EM } },
5857 { "phsubd", { MX, EM } },
5858 { "phsubsw", { MX, EM } },
5860 { "psignb", { MX, EM } },
5861 { "psignw", { MX, EM } },
5862 { "psignd", { MX, EM } },
5863 { "pmulhrsw", { MX, EM } },
5869 { PREFIX_TABLE (PREFIX_0F3810) },
5873 { PREFIX_TABLE (PREFIX_0F3814) },
5874 { PREFIX_TABLE (PREFIX_0F3815) },
5876 { PREFIX_TABLE (PREFIX_0F3817) },
5882 { "pabsb", { MX, EM } },
5883 { "pabsw", { MX, EM } },
5884 { "pabsd", { MX, EM } },
5887 { PREFIX_TABLE (PREFIX_0F3820) },
5888 { PREFIX_TABLE (PREFIX_0F3821) },
5889 { PREFIX_TABLE (PREFIX_0F3822) },
5890 { PREFIX_TABLE (PREFIX_0F3823) },
5891 { PREFIX_TABLE (PREFIX_0F3824) },
5892 { PREFIX_TABLE (PREFIX_0F3825) },
5896 { PREFIX_TABLE (PREFIX_0F3828) },
5897 { PREFIX_TABLE (PREFIX_0F3829) },
5898 { PREFIX_TABLE (PREFIX_0F382A) },
5899 { PREFIX_TABLE (PREFIX_0F382B) },
5905 { PREFIX_TABLE (PREFIX_0F3830) },
5906 { PREFIX_TABLE (PREFIX_0F3831) },
5907 { PREFIX_TABLE (PREFIX_0F3832) },
5908 { PREFIX_TABLE (PREFIX_0F3833) },
5909 { PREFIX_TABLE (PREFIX_0F3834) },
5910 { PREFIX_TABLE (PREFIX_0F3835) },
5912 { PREFIX_TABLE (PREFIX_0F3837) },
5914 { PREFIX_TABLE (PREFIX_0F3838) },
5915 { PREFIX_TABLE (PREFIX_0F3839) },
5916 { PREFIX_TABLE (PREFIX_0F383A) },
5917 { PREFIX_TABLE (PREFIX_0F383B) },
5918 { PREFIX_TABLE (PREFIX_0F383C) },
5919 { PREFIX_TABLE (PREFIX_0F383D) },
5920 { PREFIX_TABLE (PREFIX_0F383E) },
5921 { PREFIX_TABLE (PREFIX_0F383F) },
5923 { PREFIX_TABLE (PREFIX_0F3840) },
5924 { PREFIX_TABLE (PREFIX_0F3841) },
5995 { PREFIX_TABLE (PREFIX_0F3880) },
5996 { PREFIX_TABLE (PREFIX_0F3881) },
5997 { PREFIX_TABLE (PREFIX_0F3882) },
6097 { PREFIX_TABLE (PREFIX_0F38DB) },
6098 { PREFIX_TABLE (PREFIX_0F38DC) },
6099 { PREFIX_TABLE (PREFIX_0F38DD) },
6100 { PREFIX_TABLE (PREFIX_0F38DE) },
6101 { PREFIX_TABLE (PREFIX_0F38DF) },
6121 { PREFIX_TABLE (PREFIX_0F38F0) },
6122 { PREFIX_TABLE (PREFIX_0F38F1) },
6127 { PREFIX_TABLE (PREFIX_0F38F6) },
6139 /* THREE_BYTE_0F3A */
6151 { PREFIX_TABLE (PREFIX_0F3A08) },
6152 { PREFIX_TABLE (PREFIX_0F3A09) },
6153 { PREFIX_TABLE (PREFIX_0F3A0A) },
6154 { PREFIX_TABLE (PREFIX_0F3A0B) },
6155 { PREFIX_TABLE (PREFIX_0F3A0C) },
6156 { PREFIX_TABLE (PREFIX_0F3A0D) },
6157 { PREFIX_TABLE (PREFIX_0F3A0E) },
6158 { "palignr", { MX, EM, Ib } },
6164 { PREFIX_TABLE (PREFIX_0F3A14) },
6165 { PREFIX_TABLE (PREFIX_0F3A15) },
6166 { PREFIX_TABLE (PREFIX_0F3A16) },
6167 { PREFIX_TABLE (PREFIX_0F3A17) },
6178 { PREFIX_TABLE (PREFIX_0F3A20) },
6179 { PREFIX_TABLE (PREFIX_0F3A21) },
6180 { PREFIX_TABLE (PREFIX_0F3A22) },
6214 { PREFIX_TABLE (PREFIX_0F3A40) },
6215 { PREFIX_TABLE (PREFIX_0F3A41) },
6216 { PREFIX_TABLE (PREFIX_0F3A42) },
6218 { PREFIX_TABLE (PREFIX_0F3A44) },
6250 { PREFIX_TABLE (PREFIX_0F3A60) },
6251 { PREFIX_TABLE (PREFIX_0F3A61) },
6252 { PREFIX_TABLE (PREFIX_0F3A62) },
6253 { PREFIX_TABLE (PREFIX_0F3A63) },
6392 { PREFIX_TABLE (PREFIX_0F3ADF) },
6431 /* THREE_BYTE_0F7A */
6470 { "ptest", { XX } },
6507 { "phaddbw", { XM, EXq } },
6508 { "phaddbd", { XM, EXq } },
6509 { "phaddbq", { XM, EXq } },
6512 { "phaddwd", { XM, EXq } },
6513 { "phaddwq", { XM, EXq } },
6518 { "phadddq", { XM, EXq } },
6525 { "phaddubw", { XM, EXq } },
6526 { "phaddubd", { XM, EXq } },
6527 { "phaddubq", { XM, EXq } },
6530 { "phadduwd", { XM, EXq } },
6531 { "phadduwq", { XM, EXq } },
6536 { "phaddudq", { XM, EXq } },
6543 { "phsubbw", { XM, EXq } },
6544 { "phsubbd", { XM, EXq } },
6545 { "phsubbq", { XM, EXq } },
6724 static const struct dis386 xop_table[][256] = {
6877 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6878 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6879 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6887 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6888 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6895 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6896 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6897 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6905 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6906 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6910 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6911 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6914 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6932 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6944 { "vprotb", { XM, Vex_2src_1, Ib } },
6945 { "vprotw", { XM, Vex_2src_1, Ib } },
6946 { "vprotd", { XM, Vex_2src_1, Ib } },
6947 { "vprotq", { XM, Vex_2src_1, Ib } },
6957 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
6958 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
6959 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
6960 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
6993 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
6994 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
6995 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
6996 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7020 { REG_TABLE (REG_XOP_TBM_01) },
7021 { REG_TABLE (REG_XOP_TBM_02) },
7039 { REG_TABLE (REG_XOP_LWPCB) },
7163 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7164 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7165 { "vfrczss", { XM, EXd } },
7166 { "vfrczsd", { XM, EXq } },
7181 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } },
7182 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } },
7183 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } },
7184 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } },
7185 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } },
7186 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } },
7187 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } },
7188 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } },
7190 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } },
7191 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } },
7192 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } },
7193 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } },
7236 { "vphaddbw", { XM, EXxmm } },
7237 { "vphaddbd", { XM, EXxmm } },
7238 { "vphaddbq", { XM, EXxmm } },
7241 { "vphaddwd", { XM, EXxmm } },
7242 { "vphaddwq", { XM, EXxmm } },
7247 { "vphadddq", { XM, EXxmm } },
7254 { "vphaddubw", { XM, EXxmm } },
7255 { "vphaddubd", { XM, EXxmm } },
7256 { "vphaddubq", { XM, EXxmm } },
7259 { "vphadduwd", { XM, EXxmm } },
7260 { "vphadduwq", { XM, EXxmm } },
7265 { "vphaddudq", { XM, EXxmm } },
7272 { "vphsubbw", { XM, EXxmm } },
7273 { "vphsubwd", { XM, EXxmm } },
7274 { "vphsubdq", { XM, EXxmm } },
7328 { "bextr", { Gv, Ev, Iq } },
7330 { REG_TABLE (REG_XOP_LWP) },
7600 static const struct dis386 vex_table[][256] = {
7622 { PREFIX_TABLE (PREFIX_VEX_0F10) },
7623 { PREFIX_TABLE (PREFIX_VEX_0F11) },
7624 { PREFIX_TABLE (PREFIX_VEX_0F12) },
7625 { MOD_TABLE (MOD_VEX_0F13) },
7626 { VEX_W_TABLE (VEX_W_0F14) },
7627 { VEX_W_TABLE (VEX_W_0F15) },
7628 { PREFIX_TABLE (PREFIX_VEX_0F16) },
7629 { MOD_TABLE (MOD_VEX_0F17) },
7649 { VEX_W_TABLE (VEX_W_0F28) },
7650 { VEX_W_TABLE (VEX_W_0F29) },
7651 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
7652 { MOD_TABLE (MOD_VEX_0F2B) },
7653 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
7654 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
7655 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
7656 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
7694 { MOD_TABLE (MOD_VEX_0F50) },
7695 { PREFIX_TABLE (PREFIX_VEX_0F51) },
7696 { PREFIX_TABLE (PREFIX_VEX_0F52) },
7697 { PREFIX_TABLE (PREFIX_VEX_0F53) },
7698 { "vandpX", { XM, Vex, EXx } },
7699 { "vandnpX", { XM, Vex, EXx } },
7700 { "vorpX", { XM, Vex, EXx } },
7701 { "vxorpX", { XM, Vex, EXx } },
7703 { PREFIX_TABLE (PREFIX_VEX_0F58) },
7704 { PREFIX_TABLE (PREFIX_VEX_0F59) },
7705 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
7706 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
7707 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
7708 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
7709 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
7710 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
7712 { PREFIX_TABLE (PREFIX_VEX_0F60) },
7713 { PREFIX_TABLE (PREFIX_VEX_0F61) },
7714 { PREFIX_TABLE (PREFIX_VEX_0F62) },
7715 { PREFIX_TABLE (PREFIX_VEX_0F63) },
7716 { PREFIX_TABLE (PREFIX_VEX_0F64) },
7717 { PREFIX_TABLE (PREFIX_VEX_0F65) },
7718 { PREFIX_TABLE (PREFIX_VEX_0F66) },
7719 { PREFIX_TABLE (PREFIX_VEX_0F67) },
7721 { PREFIX_TABLE (PREFIX_VEX_0F68) },
7722 { PREFIX_TABLE (PREFIX_VEX_0F69) },
7723 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
7724 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
7725 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
7726 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
7727 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
7728 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
7730 { PREFIX_TABLE (PREFIX_VEX_0F70) },
7731 { REG_TABLE (REG_VEX_0F71) },
7732 { REG_TABLE (REG_VEX_0F72) },
7733 { REG_TABLE (REG_VEX_0F73) },
7734 { PREFIX_TABLE (PREFIX_VEX_0F74) },
7735 { PREFIX_TABLE (PREFIX_VEX_0F75) },
7736 { PREFIX_TABLE (PREFIX_VEX_0F76) },
7737 { PREFIX_TABLE (PREFIX_VEX_0F77) },
7743 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
7744 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
7745 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
7746 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
7799 { REG_TABLE (REG_VEX_0FAE) },
7822 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
7824 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
7825 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
7826 { "vshufpX", { XM, Vex, EXx, Ib } },
7838 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
7839 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
7840 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
7841 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
7842 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
7843 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
7844 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
7845 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
7847 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
7848 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
7849 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
7850 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
7851 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
7852 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
7853 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
7854 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
7856 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
7857 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
7858 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
7859 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
7860 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
7861 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
7862 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
7863 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
7865 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
7866 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
7867 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
7868 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
7869 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
7870 { PREFIX_TABLE (PREFIX_VEX_0FED) },
7871 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
7872 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
7874 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
7875 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
7876 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
7877 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
7878 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
7879 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
7880 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
7881 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
7883 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
7884 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
7885 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
7886 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
7887 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
7888 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
7889 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
7895 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
7896 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
7897 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
7898 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
7899 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
7900 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
7901 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
7902 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
7904 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
7905 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
7906 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
7907 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
7908 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
7909 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
7910 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
7911 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
7916 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
7919 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
7920 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
7922 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
7923 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
7924 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
7926 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
7927 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
7928 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
7931 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
7932 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
7933 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
7934 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
7935 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
7936 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
7940 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
7941 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
7942 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
7943 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
7944 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
7945 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
7946 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
7947 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
7949 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
7950 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
7951 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
7952 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
7953 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
7954 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
7955 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
7956 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
7958 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
7959 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
7960 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
7961 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
7962 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
7963 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
7964 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
7965 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
7967 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
7968 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
7972 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
7973 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
7974 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
7994 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
7995 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
7996 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8030 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8031 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8052 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8054 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8057 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8058 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8059 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8060 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8063 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8064 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8066 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8067 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8068 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8069 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8070 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8071 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8072 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8073 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8081 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8082 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8084 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8085 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8086 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8087 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8088 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8089 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8090 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8091 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8099 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8100 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8102 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8103 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8104 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8105 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8106 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8107 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8108 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8109 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8141 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8142 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8143 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8144 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8145 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8167 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8168 { REG_TABLE (REG_VEX_0F38F3) },
8170 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8171 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8172 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8186 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8187 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8188 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8190 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8191 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8192 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8195 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8196 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8197 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8198 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8199 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8200 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8201 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8202 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8208 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8209 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8210 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8211 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8213 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8214 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8218 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8222 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8223 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8224 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8249 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8250 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8258 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8259 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8260 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8262 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8264 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8267 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8268 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8269 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8270 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8271 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8289 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
8290 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
8291 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
8292 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
8294 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
8295 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
8296 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
8297 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
8303 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
8304 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
8305 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
8306 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
8307 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
8308 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
8309 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
8310 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
8321 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
8322 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
8323 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
8324 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
8325 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
8326 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
8327 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
8328 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
8436 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
8456 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
8476 static const struct dis386 vex_len_table[][2] = {
8477 /* VEX_LEN_0F10_P_1 */
8479 { VEX_W_TABLE (VEX_W_0F10_P_1) },
8480 { VEX_W_TABLE (VEX_W_0F10_P_1) },
8483 /* VEX_LEN_0F10_P_3 */
8485 { VEX_W_TABLE (VEX_W_0F10_P_3) },
8486 { VEX_W_TABLE (VEX_W_0F10_P_3) },
8489 /* VEX_LEN_0F11_P_1 */
8491 { VEX_W_TABLE (VEX_W_0F11_P_1) },
8492 { VEX_W_TABLE (VEX_W_0F11_P_1) },
8495 /* VEX_LEN_0F11_P_3 */
8497 { VEX_W_TABLE (VEX_W_0F11_P_3) },
8498 { VEX_W_TABLE (VEX_W_0F11_P_3) },
8501 /* VEX_LEN_0F12_P_0_M_0 */
8503 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
8506 /* VEX_LEN_0F12_P_0_M_1 */
8508 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
8511 /* VEX_LEN_0F12_P_2 */
8513 { VEX_W_TABLE (VEX_W_0F12_P_2) },
8516 /* VEX_LEN_0F13_M_0 */
8518 { VEX_W_TABLE (VEX_W_0F13_M_0) },
8521 /* VEX_LEN_0F16_P_0_M_0 */
8523 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
8526 /* VEX_LEN_0F16_P_0_M_1 */
8528 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
8531 /* VEX_LEN_0F16_P_2 */
8533 { VEX_W_TABLE (VEX_W_0F16_P_2) },
8536 /* VEX_LEN_0F17_M_0 */
8538 { VEX_W_TABLE (VEX_W_0F17_M_0) },
8541 /* VEX_LEN_0F2A_P_1 */
8543 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
8544 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
8547 /* VEX_LEN_0F2A_P_3 */
8549 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
8550 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
8553 /* VEX_LEN_0F2C_P_1 */
8555 { "vcvttss2siY", { Gv, EXdScalar } },
8556 { "vcvttss2siY", { Gv, EXdScalar } },
8559 /* VEX_LEN_0F2C_P_3 */
8561 { "vcvttsd2siY", { Gv, EXqScalar } },
8562 { "vcvttsd2siY", { Gv, EXqScalar } },
8565 /* VEX_LEN_0F2D_P_1 */
8567 { "vcvtss2siY", { Gv, EXdScalar } },
8568 { "vcvtss2siY", { Gv, EXdScalar } },
8571 /* VEX_LEN_0F2D_P_3 */
8573 { "vcvtsd2siY", { Gv, EXqScalar } },
8574 { "vcvtsd2siY", { Gv, EXqScalar } },
8577 /* VEX_LEN_0F2E_P_0 */
8579 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
8580 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
8583 /* VEX_LEN_0F2E_P_2 */
8585 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
8586 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
8589 /* VEX_LEN_0F2F_P_0 */
8591 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
8592 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
8595 /* VEX_LEN_0F2F_P_2 */
8597 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
8598 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
8601 /* VEX_LEN_0F51_P_1 */
8603 { VEX_W_TABLE (VEX_W_0F51_P_1) },
8604 { VEX_W_TABLE (VEX_W_0F51_P_1) },
8607 /* VEX_LEN_0F51_P_3 */
8609 { VEX_W_TABLE (VEX_W_0F51_P_3) },
8610 { VEX_W_TABLE (VEX_W_0F51_P_3) },
8613 /* VEX_LEN_0F52_P_1 */
8615 { VEX_W_TABLE (VEX_W_0F52_P_1) },
8616 { VEX_W_TABLE (VEX_W_0F52_P_1) },
8619 /* VEX_LEN_0F53_P_1 */
8621 { VEX_W_TABLE (VEX_W_0F53_P_1) },
8622 { VEX_W_TABLE (VEX_W_0F53_P_1) },
8625 /* VEX_LEN_0F58_P_1 */
8627 { VEX_W_TABLE (VEX_W_0F58_P_1) },
8628 { VEX_W_TABLE (VEX_W_0F58_P_1) },
8631 /* VEX_LEN_0F58_P_3 */
8633 { VEX_W_TABLE (VEX_W_0F58_P_3) },
8634 { VEX_W_TABLE (VEX_W_0F58_P_3) },
8637 /* VEX_LEN_0F59_P_1 */
8639 { VEX_W_TABLE (VEX_W_0F59_P_1) },
8640 { VEX_W_TABLE (VEX_W_0F59_P_1) },
8643 /* VEX_LEN_0F59_P_3 */
8645 { VEX_W_TABLE (VEX_W_0F59_P_3) },
8646 { VEX_W_TABLE (VEX_W_0F59_P_3) },
8649 /* VEX_LEN_0F5A_P_1 */
8651 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
8652 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
8655 /* VEX_LEN_0F5A_P_3 */
8657 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
8658 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
8661 /* VEX_LEN_0F5C_P_1 */
8663 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
8664 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
8667 /* VEX_LEN_0F5C_P_3 */
8669 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
8670 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
8673 /* VEX_LEN_0F5D_P_1 */
8675 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
8676 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
8679 /* VEX_LEN_0F5D_P_3 */
8681 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
8682 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
8685 /* VEX_LEN_0F5E_P_1 */
8687 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
8688 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
8691 /* VEX_LEN_0F5E_P_3 */
8693 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
8694 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
8697 /* VEX_LEN_0F5F_P_1 */
8699 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
8700 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
8703 /* VEX_LEN_0F5F_P_3 */
8705 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
8706 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
8709 /* VEX_LEN_0F6E_P_2 */
8711 { "vmovK", { XMScalar, Edq } },
8712 { "vmovK", { XMScalar, Edq } },
8715 /* VEX_LEN_0F7E_P_1 */
8717 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
8718 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
8721 /* VEX_LEN_0F7E_P_2 */
8723 { "vmovK", { Edq, XMScalar } },
8724 { "vmovK", { Edq, XMScalar } },
8727 /* VEX_LEN_0FAE_R_2_M_0 */
8729 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
8732 /* VEX_LEN_0FAE_R_3_M_0 */
8734 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
8737 /* VEX_LEN_0FC2_P_1 */
8739 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
8740 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
8743 /* VEX_LEN_0FC2_P_3 */
8745 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
8746 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
8749 /* VEX_LEN_0FC4_P_2 */
8751 { VEX_W_TABLE (VEX_W_0FC4_P_2) },
8754 /* VEX_LEN_0FC5_P_2 */
8756 { VEX_W_TABLE (VEX_W_0FC5_P_2) },
8759 /* VEX_LEN_0FD6_P_2 */
8761 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
8762 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
8765 /* VEX_LEN_0FF7_P_2 */
8767 { VEX_W_TABLE (VEX_W_0FF7_P_2) },
8770 /* VEX_LEN_0F3816_P_2 */
8773 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
8776 /* VEX_LEN_0F3819_P_2 */
8779 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
8782 /* VEX_LEN_0F381A_P_2_M_0 */
8785 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
8788 /* VEX_LEN_0F3836_P_2 */
8791 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
8794 /* VEX_LEN_0F3841_P_2 */
8796 { VEX_W_TABLE (VEX_W_0F3841_P_2) },
8799 /* VEX_LEN_0F385A_P_2_M_0 */
8802 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
8805 /* VEX_LEN_0F38DB_P_2 */
8807 { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
8810 /* VEX_LEN_0F38DC_P_2 */
8812 { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
8815 /* VEX_LEN_0F38DD_P_2 */
8817 { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
8820 /* VEX_LEN_0F38DE_P_2 */
8822 { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
8825 /* VEX_LEN_0F38DF_P_2 */
8827 { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
8830 /* VEX_LEN_0F38F2_P_0 */
8832 { "andnS", { Gdq, VexGdq, Edq } },
8835 /* VEX_LEN_0F38F3_R_1_P_0 */
8837 { "blsrS", { VexGdq, Edq } },
8840 /* VEX_LEN_0F38F3_R_2_P_0 */
8842 { "blsmskS", { VexGdq, Edq } },
8845 /* VEX_LEN_0F38F3_R_3_P_0 */
8847 { "blsiS", { VexGdq, Edq } },
8850 /* VEX_LEN_0F38F5_P_0 */
8852 { "bzhiS", { Gdq, Edq, VexGdq } },
8855 /* VEX_LEN_0F38F5_P_1 */
8857 { "pextS", { Gdq, VexGdq, Edq } },
8860 /* VEX_LEN_0F38F5_P_3 */
8862 { "pdepS", { Gdq, VexGdq, Edq } },
8865 /* VEX_LEN_0F38F6_P_3 */
8867 { "mulxS", { Gdq, VexGdq, Edq } },
8870 /* VEX_LEN_0F38F7_P_0 */
8872 { "bextrS", { Gdq, Edq, VexGdq } },
8875 /* VEX_LEN_0F38F7_P_1 */
8877 { "sarxS", { Gdq, Edq, VexGdq } },
8880 /* VEX_LEN_0F38F7_P_2 */
8882 { "shlxS", { Gdq, Edq, VexGdq } },
8885 /* VEX_LEN_0F38F7_P_3 */
8887 { "shrxS", { Gdq, Edq, VexGdq } },
8890 /* VEX_LEN_0F3A00_P_2 */
8893 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
8896 /* VEX_LEN_0F3A01_P_2 */
8899 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
8902 /* VEX_LEN_0F3A06_P_2 */
8905 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
8908 /* VEX_LEN_0F3A0A_P_2 */
8910 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
8911 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
8914 /* VEX_LEN_0F3A0B_P_2 */
8916 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
8917 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
8920 /* VEX_LEN_0F3A14_P_2 */
8922 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
8925 /* VEX_LEN_0F3A15_P_2 */
8927 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
8930 /* VEX_LEN_0F3A16_P_2 */
8932 { "vpextrK", { Edq, XM, Ib } },
8935 /* VEX_LEN_0F3A17_P_2 */
8937 { "vextractps", { Edqd, XM, Ib } },
8940 /* VEX_LEN_0F3A18_P_2 */
8943 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
8946 /* VEX_LEN_0F3A19_P_2 */
8949 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
8952 /* VEX_LEN_0F3A20_P_2 */
8954 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
8957 /* VEX_LEN_0F3A21_P_2 */
8959 { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
8962 /* VEX_LEN_0F3A22_P_2 */
8964 { "vpinsrK", { XM, Vex128, Edq, Ib } },
8967 /* VEX_LEN_0F3A38_P_2 */
8970 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
8973 /* VEX_LEN_0F3A39_P_2 */
8976 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
8979 /* VEX_LEN_0F3A41_P_2 */
8981 { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
8984 /* VEX_LEN_0F3A44_P_2 */
8986 { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
8989 /* VEX_LEN_0F3A46_P_2 */
8992 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
8995 /* VEX_LEN_0F3A60_P_2 */
8997 { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
9000 /* VEX_LEN_0F3A61_P_2 */
9002 { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
9005 /* VEX_LEN_0F3A62_P_2 */
9007 { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
9010 /* VEX_LEN_0F3A63_P_2 */
9012 { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
9015 /* VEX_LEN_0F3A6A_P_2 */
9017 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9020 /* VEX_LEN_0F3A6B_P_2 */
9022 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9025 /* VEX_LEN_0F3A6E_P_2 */
9027 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9030 /* VEX_LEN_0F3A6F_P_2 */
9032 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9035 /* VEX_LEN_0F3A7A_P_2 */
9037 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9040 /* VEX_LEN_0F3A7B_P_2 */
9042 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9045 /* VEX_LEN_0F3A7E_P_2 */
9047 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9050 /* VEX_LEN_0F3A7F_P_2 */
9052 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9055 /* VEX_LEN_0F3ADF_P_2 */
9057 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
9060 /* VEX_LEN_0F3AF0_P_3 */
9062 { "rorxS", { Gdq, Edq, Ib } },
9065 /* VEX_LEN_0FXOP_08_CC */
9067 { "vpcomb", { XM, Vex128, EXx, Ib } },
9070 /* VEX_LEN_0FXOP_08_CD */
9072 { "vpcomw", { XM, Vex128, EXx, Ib } },
9075 /* VEX_LEN_0FXOP_08_CE */
9077 { "vpcomd", { XM, Vex128, EXx, Ib } },
9080 /* VEX_LEN_0FXOP_08_CF */
9082 { "vpcomq", { XM, Vex128, EXx, Ib } },
9085 /* VEX_LEN_0FXOP_08_EC */
9087 { "vpcomub", { XM, Vex128, EXx, Ib } },
9090 /* VEX_LEN_0FXOP_08_ED */
9092 { "vpcomuw", { XM, Vex128, EXx, Ib } },
9095 /* VEX_LEN_0FXOP_08_EE */
9097 { "vpcomud", { XM, Vex128, EXx, Ib } },
9100 /* VEX_LEN_0FXOP_08_EF */
9102 { "vpcomuq", { XM, Vex128, EXx, Ib } },
9105 /* VEX_LEN_0FXOP_09_80 */
9107 { "vfrczps", { XM, EXxmm } },
9108 { "vfrczps", { XM, EXymmq } },
9111 /* VEX_LEN_0FXOP_09_81 */
9113 { "vfrczpd", { XM, EXxmm } },
9114 { "vfrczpd", { XM, EXymmq } },
9118 static const struct dis386 vex_w_table[][2] = {
9120 /* VEX_W_0F10_P_0 */
9121 { "vmovups", { XM, EXx } },
9124 /* VEX_W_0F10_P_1 */
9125 { "vmovss", { XMVexScalar, VexScalar, EXdScalar } },
9128 /* VEX_W_0F10_P_2 */
9129 { "vmovupd", { XM, EXx } },
9132 /* VEX_W_0F10_P_3 */
9133 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } },
9136 /* VEX_W_0F11_P_0 */
9137 { "vmovups", { EXxS, XM } },
9140 /* VEX_W_0F11_P_1 */
9141 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } },
9144 /* VEX_W_0F11_P_2 */
9145 { "vmovupd", { EXxS, XM } },
9148 /* VEX_W_0F11_P_3 */
9149 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } },
9152 /* VEX_W_0F12_P_0_M_0 */
9153 { "vmovlps", { XM, Vex128, EXq } },
9156 /* VEX_W_0F12_P_0_M_1 */
9157 { "vmovhlps", { XM, Vex128, EXq } },
9160 /* VEX_W_0F12_P_1 */
9161 { "vmovsldup", { XM, EXx } },
9164 /* VEX_W_0F12_P_2 */
9165 { "vmovlpd", { XM, Vex128, EXq } },
9168 /* VEX_W_0F12_P_3 */
9169 { "vmovddup", { XM, EXymmq } },
9172 /* VEX_W_0F13_M_0 */
9173 { "vmovlpX", { EXq, XM } },
9177 { "vunpcklpX", { XM, Vex, EXx } },
9181 { "vunpckhpX", { XM, Vex, EXx } },
9184 /* VEX_W_0F16_P_0_M_0 */
9185 { "vmovhps", { XM, Vex128, EXq } },
9188 /* VEX_W_0F16_P_0_M_1 */
9189 { "vmovlhps", { XM, Vex128, EXq } },
9192 /* VEX_W_0F16_P_1 */
9193 { "vmovshdup", { XM, EXx } },
9196 /* VEX_W_0F16_P_2 */
9197 { "vmovhpd", { XM, Vex128, EXq } },
9200 /* VEX_W_0F17_M_0 */
9201 { "vmovhpX", { EXq, XM } },
9205 { "vmovapX", { XM, EXx } },
9209 { "vmovapX", { EXxS, XM } },
9212 /* VEX_W_0F2B_M_0 */
9213 { "vmovntpX", { Mx, XM } },
9216 /* VEX_W_0F2E_P_0 */
9217 { "vucomiss", { XMScalar, EXdScalar } },
9220 /* VEX_W_0F2E_P_2 */
9221 { "vucomisd", { XMScalar, EXqScalar } },
9224 /* VEX_W_0F2F_P_0 */
9225 { "vcomiss", { XMScalar, EXdScalar } },
9228 /* VEX_W_0F2F_P_2 */
9229 { "vcomisd", { XMScalar, EXqScalar } },
9232 /* VEX_W_0F50_M_0 */
9233 { "vmovmskpX", { Gdq, XS } },
9236 /* VEX_W_0F51_P_0 */
9237 { "vsqrtps", { XM, EXx } },
9240 /* VEX_W_0F51_P_1 */
9241 { "vsqrtss", { XMScalar, VexScalar, EXdScalar } },
9244 /* VEX_W_0F51_P_2 */
9245 { "vsqrtpd", { XM, EXx } },
9248 /* VEX_W_0F51_P_3 */
9249 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar } },
9252 /* VEX_W_0F52_P_0 */
9253 { "vrsqrtps", { XM, EXx } },
9256 /* VEX_W_0F52_P_1 */
9257 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar } },
9260 /* VEX_W_0F53_P_0 */
9261 { "vrcpps", { XM, EXx } },
9264 /* VEX_W_0F53_P_1 */
9265 { "vrcpss", { XMScalar, VexScalar, EXdScalar } },
9268 /* VEX_W_0F58_P_0 */
9269 { "vaddps", { XM, Vex, EXx } },
9272 /* VEX_W_0F58_P_1 */
9273 { "vaddss", { XMScalar, VexScalar, EXdScalar } },
9276 /* VEX_W_0F58_P_2 */
9277 { "vaddpd", { XM, Vex, EXx } },
9280 /* VEX_W_0F58_P_3 */
9281 { "vaddsd", { XMScalar, VexScalar, EXqScalar } },
9284 /* VEX_W_0F59_P_0 */
9285 { "vmulps", { XM, Vex, EXx } },
9288 /* VEX_W_0F59_P_1 */
9289 { "vmulss", { XMScalar, VexScalar, EXdScalar } },
9292 /* VEX_W_0F59_P_2 */
9293 { "vmulpd", { XM, Vex, EXx } },
9296 /* VEX_W_0F59_P_3 */
9297 { "vmulsd", { XMScalar, VexScalar, EXqScalar } },
9300 /* VEX_W_0F5A_P_0 */
9301 { "vcvtps2pd", { XM, EXxmmq } },
9304 /* VEX_W_0F5A_P_1 */
9305 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar } },
9308 /* VEX_W_0F5A_P_3 */
9309 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar } },
9312 /* VEX_W_0F5B_P_0 */
9313 { "vcvtdq2ps", { XM, EXx } },
9316 /* VEX_W_0F5B_P_1 */
9317 { "vcvttps2dq", { XM, EXx } },
9320 /* VEX_W_0F5B_P_2 */
9321 { "vcvtps2dq", { XM, EXx } },
9324 /* VEX_W_0F5C_P_0 */
9325 { "vsubps", { XM, Vex, EXx } },
9328 /* VEX_W_0F5C_P_1 */
9329 { "vsubss", { XMScalar, VexScalar, EXdScalar } },
9332 /* VEX_W_0F5C_P_2 */
9333 { "vsubpd", { XM, Vex, EXx } },
9336 /* VEX_W_0F5C_P_3 */
9337 { "vsubsd", { XMScalar, VexScalar, EXqScalar } },
9340 /* VEX_W_0F5D_P_0 */
9341 { "vminps", { XM, Vex, EXx } },
9344 /* VEX_W_0F5D_P_1 */
9345 { "vminss", { XMScalar, VexScalar, EXdScalar } },
9348 /* VEX_W_0F5D_P_2 */
9349 { "vminpd", { XM, Vex, EXx } },
9352 /* VEX_W_0F5D_P_3 */
9353 { "vminsd", { XMScalar, VexScalar, EXqScalar } },
9356 /* VEX_W_0F5E_P_0 */
9357 { "vdivps", { XM, Vex, EXx } },
9360 /* VEX_W_0F5E_P_1 */
9361 { "vdivss", { XMScalar, VexScalar, EXdScalar } },
9364 /* VEX_W_0F5E_P_2 */
9365 { "vdivpd", { XM, Vex, EXx } },
9368 /* VEX_W_0F5E_P_3 */
9369 { "vdivsd", { XMScalar, VexScalar, EXqScalar } },
9372 /* VEX_W_0F5F_P_0 */
9373 { "vmaxps", { XM, Vex, EXx } },
9376 /* VEX_W_0F5F_P_1 */
9377 { "vmaxss", { XMScalar, VexScalar, EXdScalar } },
9380 /* VEX_W_0F5F_P_2 */
9381 { "vmaxpd", { XM, Vex, EXx } },
9384 /* VEX_W_0F5F_P_3 */
9385 { "vmaxsd", { XMScalar, VexScalar, EXqScalar } },
9388 /* VEX_W_0F60_P_2 */
9389 { "vpunpcklbw", { XM, Vex, EXx } },
9392 /* VEX_W_0F61_P_2 */
9393 { "vpunpcklwd", { XM, Vex, EXx } },
9396 /* VEX_W_0F62_P_2 */
9397 { "vpunpckldq", { XM, Vex, EXx } },
9400 /* VEX_W_0F63_P_2 */
9401 { "vpacksswb", { XM, Vex, EXx } },
9404 /* VEX_W_0F64_P_2 */
9405 { "vpcmpgtb", { XM, Vex, EXx } },
9408 /* VEX_W_0F65_P_2 */
9409 { "vpcmpgtw", { XM, Vex, EXx } },
9412 /* VEX_W_0F66_P_2 */
9413 { "vpcmpgtd", { XM, Vex, EXx } },
9416 /* VEX_W_0F67_P_2 */
9417 { "vpackuswb", { XM, Vex, EXx } },
9420 /* VEX_W_0F68_P_2 */
9421 { "vpunpckhbw", { XM, Vex, EXx } },
9424 /* VEX_W_0F69_P_2 */
9425 { "vpunpckhwd", { XM, Vex, EXx } },
9428 /* VEX_W_0F6A_P_2 */
9429 { "vpunpckhdq", { XM, Vex, EXx } },
9432 /* VEX_W_0F6B_P_2 */
9433 { "vpackssdw", { XM, Vex, EXx } },
9436 /* VEX_W_0F6C_P_2 */
9437 { "vpunpcklqdq", { XM, Vex, EXx } },
9440 /* VEX_W_0F6D_P_2 */
9441 { "vpunpckhqdq", { XM, Vex, EXx } },
9444 /* VEX_W_0F6F_P_1 */
9445 { "vmovdqu", { XM, EXx } },
9448 /* VEX_W_0F6F_P_2 */
9449 { "vmovdqa", { XM, EXx } },
9452 /* VEX_W_0F70_P_1 */
9453 { "vpshufhw", { XM, EXx, Ib } },
9456 /* VEX_W_0F70_P_2 */
9457 { "vpshufd", { XM, EXx, Ib } },
9460 /* VEX_W_0F70_P_3 */
9461 { "vpshuflw", { XM, EXx, Ib } },
9464 /* VEX_W_0F71_R_2_P_2 */
9465 { "vpsrlw", { Vex, XS, Ib } },
9468 /* VEX_W_0F71_R_4_P_2 */
9469 { "vpsraw", { Vex, XS, Ib } },
9472 /* VEX_W_0F71_R_6_P_2 */
9473 { "vpsllw", { Vex, XS, Ib } },
9476 /* VEX_W_0F72_R_2_P_2 */
9477 { "vpsrld", { Vex, XS, Ib } },
9480 /* VEX_W_0F72_R_4_P_2 */
9481 { "vpsrad", { Vex, XS, Ib } },
9484 /* VEX_W_0F72_R_6_P_2 */
9485 { "vpslld", { Vex, XS, Ib } },
9488 /* VEX_W_0F73_R_2_P_2 */
9489 { "vpsrlq", { Vex, XS, Ib } },
9492 /* VEX_W_0F73_R_3_P_2 */
9493 { "vpsrldq", { Vex, XS, Ib } },
9496 /* VEX_W_0F73_R_6_P_2 */
9497 { "vpsllq", { Vex, XS, Ib } },
9500 /* VEX_W_0F73_R_7_P_2 */
9501 { "vpslldq", { Vex, XS, Ib } },
9504 /* VEX_W_0F74_P_2 */
9505 { "vpcmpeqb", { XM, Vex, EXx } },
9508 /* VEX_W_0F75_P_2 */
9509 { "vpcmpeqw", { XM, Vex, EXx } },
9512 /* VEX_W_0F76_P_2 */
9513 { "vpcmpeqd", { XM, Vex, EXx } },
9516 /* VEX_W_0F77_P_0 */
9520 /* VEX_W_0F7C_P_2 */
9521 { "vhaddpd", { XM, Vex, EXx } },
9524 /* VEX_W_0F7C_P_3 */
9525 { "vhaddps", { XM, Vex, EXx } },
9528 /* VEX_W_0F7D_P_2 */
9529 { "vhsubpd", { XM, Vex, EXx } },
9532 /* VEX_W_0F7D_P_3 */
9533 { "vhsubps", { XM, Vex, EXx } },
9536 /* VEX_W_0F7E_P_1 */
9537 { "vmovq", { XMScalar, EXqScalar } },
9540 /* VEX_W_0F7F_P_1 */
9541 { "vmovdqu", { EXxS, XM } },
9544 /* VEX_W_0F7F_P_2 */
9545 { "vmovdqa", { EXxS, XM } },
9548 /* VEX_W_0FAE_R_2_M_0 */
9549 { "vldmxcsr", { Md } },
9552 /* VEX_W_0FAE_R_3_M_0 */
9553 { "vstmxcsr", { Md } },
9556 /* VEX_W_0FC2_P_0 */
9557 { "vcmpps", { XM, Vex, EXx, VCMP } },
9560 /* VEX_W_0FC2_P_1 */
9561 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP } },
9564 /* VEX_W_0FC2_P_2 */
9565 { "vcmppd", { XM, Vex, EXx, VCMP } },
9568 /* VEX_W_0FC2_P_3 */
9569 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP } },
9572 /* VEX_W_0FC4_P_2 */
9573 { "vpinsrw", { XM, Vex128, Edqw, Ib } },
9576 /* VEX_W_0FC5_P_2 */
9577 { "vpextrw", { Gdq, XS, Ib } },
9580 /* VEX_W_0FD0_P_2 */
9581 { "vaddsubpd", { XM, Vex, EXx } },
9584 /* VEX_W_0FD0_P_3 */
9585 { "vaddsubps", { XM, Vex, EXx } },
9588 /* VEX_W_0FD1_P_2 */
9589 { "vpsrlw", { XM, Vex, EXxmm } },
9592 /* VEX_W_0FD2_P_2 */
9593 { "vpsrld", { XM, Vex, EXxmm } },
9596 /* VEX_W_0FD3_P_2 */
9597 { "vpsrlq", { XM, Vex, EXxmm } },
9600 /* VEX_W_0FD4_P_2 */
9601 { "vpaddq", { XM, Vex, EXx } },
9604 /* VEX_W_0FD5_P_2 */
9605 { "vpmullw", { XM, Vex, EXx } },
9608 /* VEX_W_0FD6_P_2 */
9609 { "vmovq", { EXqScalarS, XMScalar } },
9612 /* VEX_W_0FD7_P_2_M_1 */
9613 { "vpmovmskb", { Gdq, XS } },
9616 /* VEX_W_0FD8_P_2 */
9617 { "vpsubusb", { XM, Vex, EXx } },
9620 /* VEX_W_0FD9_P_2 */
9621 { "vpsubusw", { XM, Vex, EXx } },
9624 /* VEX_W_0FDA_P_2 */
9625 { "vpminub", { XM, Vex, EXx } },
9628 /* VEX_W_0FDB_P_2 */
9629 { "vpand", { XM, Vex, EXx } },
9632 /* VEX_W_0FDC_P_2 */
9633 { "vpaddusb", { XM, Vex, EXx } },
9636 /* VEX_W_0FDD_P_2 */
9637 { "vpaddusw", { XM, Vex, EXx } },
9640 /* VEX_W_0FDE_P_2 */
9641 { "vpmaxub", { XM, Vex, EXx } },
9644 /* VEX_W_0FDF_P_2 */
9645 { "vpandn", { XM, Vex, EXx } },
9648 /* VEX_W_0FE0_P_2 */
9649 { "vpavgb", { XM, Vex, EXx } },
9652 /* VEX_W_0FE1_P_2 */
9653 { "vpsraw", { XM, Vex, EXxmm } },
9656 /* VEX_W_0FE2_P_2 */
9657 { "vpsrad", { XM, Vex, EXxmm } },
9660 /* VEX_W_0FE3_P_2 */
9661 { "vpavgw", { XM, Vex, EXx } },
9664 /* VEX_W_0FE4_P_2 */
9665 { "vpmulhuw", { XM, Vex, EXx } },
9668 /* VEX_W_0FE5_P_2 */
9669 { "vpmulhw", { XM, Vex, EXx } },
9672 /* VEX_W_0FE6_P_1 */
9673 { "vcvtdq2pd", { XM, EXxmmq } },
9676 /* VEX_W_0FE6_P_2 */
9677 { "vcvttpd2dq%XY", { XMM, EXx } },
9680 /* VEX_W_0FE6_P_3 */
9681 { "vcvtpd2dq%XY", { XMM, EXx } },
9684 /* VEX_W_0FE7_P_2_M_0 */
9685 { "vmovntdq", { Mx, XM } },
9688 /* VEX_W_0FE8_P_2 */
9689 { "vpsubsb", { XM, Vex, EXx } },
9692 /* VEX_W_0FE9_P_2 */
9693 { "vpsubsw", { XM, Vex, EXx } },
9696 /* VEX_W_0FEA_P_2 */
9697 { "vpminsw", { XM, Vex, EXx } },
9700 /* VEX_W_0FEB_P_2 */
9701 { "vpor", { XM, Vex, EXx } },
9704 /* VEX_W_0FEC_P_2 */
9705 { "vpaddsb", { XM, Vex, EXx } },
9708 /* VEX_W_0FED_P_2 */
9709 { "vpaddsw", { XM, Vex, EXx } },
9712 /* VEX_W_0FEE_P_2 */
9713 { "vpmaxsw", { XM, Vex, EXx } },
9716 /* VEX_W_0FEF_P_2 */
9717 { "vpxor", { XM, Vex, EXx } },
9720 /* VEX_W_0FF0_P_3_M_0 */
9721 { "vlddqu", { XM, M } },
9724 /* VEX_W_0FF1_P_2 */
9725 { "vpsllw", { XM, Vex, EXxmm } },
9728 /* VEX_W_0FF2_P_2 */
9729 { "vpslld", { XM, Vex, EXxmm } },
9732 /* VEX_W_0FF3_P_2 */
9733 { "vpsllq", { XM, Vex, EXxmm } },
9736 /* VEX_W_0FF4_P_2 */
9737 { "vpmuludq", { XM, Vex, EXx } },
9740 /* VEX_W_0FF5_P_2 */
9741 { "vpmaddwd", { XM, Vex, EXx } },
9744 /* VEX_W_0FF6_P_2 */
9745 { "vpsadbw", { XM, Vex, EXx } },
9748 /* VEX_W_0FF7_P_2 */
9749 { "vmaskmovdqu", { XM, XS } },
9752 /* VEX_W_0FF8_P_2 */
9753 { "vpsubb", { XM, Vex, EXx } },
9756 /* VEX_W_0FF9_P_2 */
9757 { "vpsubw", { XM, Vex, EXx } },
9760 /* VEX_W_0FFA_P_2 */
9761 { "vpsubd", { XM, Vex, EXx } },
9764 /* VEX_W_0FFB_P_2 */
9765 { "vpsubq", { XM, Vex, EXx } },
9768 /* VEX_W_0FFC_P_2 */
9769 { "vpaddb", { XM, Vex, EXx } },
9772 /* VEX_W_0FFD_P_2 */
9773 { "vpaddw", { XM, Vex, EXx } },
9776 /* VEX_W_0FFE_P_2 */
9777 { "vpaddd", { XM, Vex, EXx } },
9780 /* VEX_W_0F3800_P_2 */
9781 { "vpshufb", { XM, Vex, EXx } },
9784 /* VEX_W_0F3801_P_2 */
9785 { "vphaddw", { XM, Vex, EXx } },
9788 /* VEX_W_0F3802_P_2 */
9789 { "vphaddd", { XM, Vex, EXx } },
9792 /* VEX_W_0F3803_P_2 */
9793 { "vphaddsw", { XM, Vex, EXx } },
9796 /* VEX_W_0F3804_P_2 */
9797 { "vpmaddubsw", { XM, Vex, EXx } },
9800 /* VEX_W_0F3805_P_2 */
9801 { "vphsubw", { XM, Vex, EXx } },
9804 /* VEX_W_0F3806_P_2 */
9805 { "vphsubd", { XM, Vex, EXx } },
9808 /* VEX_W_0F3807_P_2 */
9809 { "vphsubsw", { XM, Vex, EXx } },
9812 /* VEX_W_0F3808_P_2 */
9813 { "vpsignb", { XM, Vex, EXx } },
9816 /* VEX_W_0F3809_P_2 */
9817 { "vpsignw", { XM, Vex, EXx } },
9820 /* VEX_W_0F380A_P_2 */
9821 { "vpsignd", { XM, Vex, EXx } },
9824 /* VEX_W_0F380B_P_2 */
9825 { "vpmulhrsw", { XM, Vex, EXx } },
9828 /* VEX_W_0F380C_P_2 */
9829 { "vpermilps", { XM, Vex, EXx } },
9832 /* VEX_W_0F380D_P_2 */
9833 { "vpermilpd", { XM, Vex, EXx } },
9836 /* VEX_W_0F380E_P_2 */
9837 { "vtestps", { XM, EXx } },
9840 /* VEX_W_0F380F_P_2 */
9841 { "vtestpd", { XM, EXx } },
9844 /* VEX_W_0F3816_P_2 */
9845 { "vpermps", { XM, Vex, EXx } },
9848 /* VEX_W_0F3817_P_2 */
9849 { "vptest", { XM, EXx } },
9852 /* VEX_W_0F3818_P_2 */
9853 { "vbroadcastss", { XM, EXxmm_md } },
9856 /* VEX_W_0F3819_P_2 */
9857 { "vbroadcastsd", { XM, EXxmm_mq } },
9860 /* VEX_W_0F381A_P_2_M_0 */
9861 { "vbroadcastf128", { XM, Mxmm } },
9864 /* VEX_W_0F381C_P_2 */
9865 { "vpabsb", { XM, EXx } },
9868 /* VEX_W_0F381D_P_2 */
9869 { "vpabsw", { XM, EXx } },
9872 /* VEX_W_0F381E_P_2 */
9873 { "vpabsd", { XM, EXx } },
9876 /* VEX_W_0F3820_P_2 */
9877 { "vpmovsxbw", { XM, EXxmmq } },
9880 /* VEX_W_0F3821_P_2 */
9881 { "vpmovsxbd", { XM, EXxmmqd } },
9884 /* VEX_W_0F3822_P_2 */
9885 { "vpmovsxbq", { XM, EXxmmdw } },
9888 /* VEX_W_0F3823_P_2 */
9889 { "vpmovsxwd", { XM, EXxmmq } },
9892 /* VEX_W_0F3824_P_2 */
9893 { "vpmovsxwq", { XM, EXxmmqd } },
9896 /* VEX_W_0F3825_P_2 */
9897 { "vpmovsxdq", { XM, EXxmmq } },
9900 /* VEX_W_0F3828_P_2 */
9901 { "vpmuldq", { XM, Vex, EXx } },
9904 /* VEX_W_0F3829_P_2 */
9905 { "vpcmpeqq", { XM, Vex, EXx } },
9908 /* VEX_W_0F382A_P_2_M_0 */
9909 { "vmovntdqa", { XM, Mx } },
9912 /* VEX_W_0F382B_P_2 */
9913 { "vpackusdw", { XM, Vex, EXx } },
9916 /* VEX_W_0F382C_P_2_M_0 */
9917 { "vmaskmovps", { XM, Vex, Mx } },
9920 /* VEX_W_0F382D_P_2_M_0 */
9921 { "vmaskmovpd", { XM, Vex, Mx } },
9924 /* VEX_W_0F382E_P_2_M_0 */
9925 { "vmaskmovps", { Mx, Vex, XM } },
9928 /* VEX_W_0F382F_P_2_M_0 */
9929 { "vmaskmovpd", { Mx, Vex, XM } },
9932 /* VEX_W_0F3830_P_2 */
9933 { "vpmovzxbw", { XM, EXxmmq } },
9936 /* VEX_W_0F3831_P_2 */
9937 { "vpmovzxbd", { XM, EXxmmqd } },
9940 /* VEX_W_0F3832_P_2 */
9941 { "vpmovzxbq", { XM, EXxmmdw } },
9944 /* VEX_W_0F3833_P_2 */
9945 { "vpmovzxwd", { XM, EXxmmq } },
9948 /* VEX_W_0F3834_P_2 */
9949 { "vpmovzxwq", { XM, EXxmmqd } },
9952 /* VEX_W_0F3835_P_2 */
9953 { "vpmovzxdq", { XM, EXxmmq } },
9956 /* VEX_W_0F3836_P_2 */
9957 { "vpermd", { XM, Vex, EXx } },
9960 /* VEX_W_0F3837_P_2 */
9961 { "vpcmpgtq", { XM, Vex, EXx } },
9964 /* VEX_W_0F3838_P_2 */
9965 { "vpminsb", { XM, Vex, EXx } },
9968 /* VEX_W_0F3839_P_2 */
9969 { "vpminsd", { XM, Vex, EXx } },
9972 /* VEX_W_0F383A_P_2 */
9973 { "vpminuw", { XM, Vex, EXx } },
9976 /* VEX_W_0F383B_P_2 */
9977 { "vpminud", { XM, Vex, EXx } },
9980 /* VEX_W_0F383C_P_2 */
9981 { "vpmaxsb", { XM, Vex, EXx } },
9984 /* VEX_W_0F383D_P_2 */
9985 { "vpmaxsd", { XM, Vex, EXx } },
9988 /* VEX_W_0F383E_P_2 */
9989 { "vpmaxuw", { XM, Vex, EXx } },
9992 /* VEX_W_0F383F_P_2 */
9993 { "vpmaxud", { XM, Vex, EXx } },
9996 /* VEX_W_0F3840_P_2 */
9997 { "vpmulld", { XM, Vex, EXx } },
10000 /* VEX_W_0F3841_P_2 */
10001 { "vphminposuw", { XM, EXx } },
10004 /* VEX_W_0F3846_P_2 */
10005 { "vpsravd", { XM, Vex, EXx } },
10008 /* VEX_W_0F3858_P_2 */
10009 { "vpbroadcastd", { XM, EXxmm_md } },
10012 /* VEX_W_0F3859_P_2 */
10013 { "vpbroadcastq", { XM, EXxmm_mq } },
10016 /* VEX_W_0F385A_P_2_M_0 */
10017 { "vbroadcasti128", { XM, Mxmm } },
10020 /* VEX_W_0F3878_P_2 */
10021 { "vpbroadcastb", { XM, EXxmm_mb } },
10024 /* VEX_W_0F3879_P_2 */
10025 { "vpbroadcastw", { XM, EXxmm_mw } },
10028 /* VEX_W_0F38DB_P_2 */
10029 { "vaesimc", { XM, EXx } },
10032 /* VEX_W_0F38DC_P_2 */
10033 { "vaesenc", { XM, Vex128, EXx } },
10036 /* VEX_W_0F38DD_P_2 */
10037 { "vaesenclast", { XM, Vex128, EXx } },
10040 /* VEX_W_0F38DE_P_2 */
10041 { "vaesdec", { XM, Vex128, EXx } },
10044 /* VEX_W_0F38DF_P_2 */
10045 { "vaesdeclast", { XM, Vex128, EXx } },
10048 /* VEX_W_0F3A00_P_2 */
10050 { "vpermq", { XM, EXx, Ib } },
10053 /* VEX_W_0F3A01_P_2 */
10055 { "vpermpd", { XM, EXx, Ib } },
10058 /* VEX_W_0F3A02_P_2 */
10059 { "vpblendd", { XM, Vex, EXx, Ib } },
10062 /* VEX_W_0F3A04_P_2 */
10063 { "vpermilps", { XM, EXx, Ib } },
10066 /* VEX_W_0F3A05_P_2 */
10067 { "vpermilpd", { XM, EXx, Ib } },
10070 /* VEX_W_0F3A06_P_2 */
10071 { "vperm2f128", { XM, Vex256, EXx, Ib } },
10074 /* VEX_W_0F3A08_P_2 */
10075 { "vroundps", { XM, EXx, Ib } },
10078 /* VEX_W_0F3A09_P_2 */
10079 { "vroundpd", { XM, EXx, Ib } },
10082 /* VEX_W_0F3A0A_P_2 */
10083 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib } },
10086 /* VEX_W_0F3A0B_P_2 */
10087 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib } },
10090 /* VEX_W_0F3A0C_P_2 */
10091 { "vblendps", { XM, Vex, EXx, Ib } },
10094 /* VEX_W_0F3A0D_P_2 */
10095 { "vblendpd", { XM, Vex, EXx, Ib } },
10098 /* VEX_W_0F3A0E_P_2 */
10099 { "vpblendw", { XM, Vex, EXx, Ib } },
10102 /* VEX_W_0F3A0F_P_2 */
10103 { "vpalignr", { XM, Vex, EXx, Ib } },
10106 /* VEX_W_0F3A14_P_2 */
10107 { "vpextrb", { Edqb, XM, Ib } },
10110 /* VEX_W_0F3A15_P_2 */
10111 { "vpextrw", { Edqw, XM, Ib } },
10114 /* VEX_W_0F3A18_P_2 */
10115 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },
10118 /* VEX_W_0F3A19_P_2 */
10119 { "vextractf128", { EXxmm, XM, Ib } },
10122 /* VEX_W_0F3A20_P_2 */
10123 { "vpinsrb", { XM, Vex128, Edqb, Ib } },
10126 /* VEX_W_0F3A21_P_2 */
10127 { "vinsertps", { XM, Vex128, EXd, Ib } },
10130 /* VEX_W_0F3A38_P_2 */
10131 { "vinserti128", { XM, Vex256, EXxmm, Ib } },
10134 /* VEX_W_0F3A39_P_2 */
10135 { "vextracti128", { EXxmm, XM, Ib } },
10138 /* VEX_W_0F3A40_P_2 */
10139 { "vdpps", { XM, Vex, EXx, Ib } },
10142 /* VEX_W_0F3A41_P_2 */
10143 { "vdppd", { XM, Vex128, EXx, Ib } },
10146 /* VEX_W_0F3A42_P_2 */
10147 { "vmpsadbw", { XM, Vex, EXx, Ib } },
10150 /* VEX_W_0F3A44_P_2 */
10151 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } },
10154 /* VEX_W_0F3A46_P_2 */
10155 { "vperm2i128", { XM, Vex256, EXx, Ib } },
10158 /* VEX_W_0F3A48_P_2 */
10159 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10160 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10163 /* VEX_W_0F3A49_P_2 */
10164 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10165 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10168 /* VEX_W_0F3A4A_P_2 */
10169 { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
10172 /* VEX_W_0F3A4B_P_2 */
10173 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
10176 /* VEX_W_0F3A4C_P_2 */
10177 { "vpblendvb", { XM, Vex, EXx, XMVexI4 } },
10180 /* VEX_W_0F3A60_P_2 */
10181 { "vpcmpestrm", { XM, EXx, Ib } },
10184 /* VEX_W_0F3A61_P_2 */
10185 { "vpcmpestri", { XM, EXx, Ib } },
10188 /* VEX_W_0F3A62_P_2 */
10189 { "vpcmpistrm", { XM, EXx, Ib } },
10192 /* VEX_W_0F3A63_P_2 */
10193 { "vpcmpistri", { XM, EXx, Ib } },
10196 /* VEX_W_0F3ADF_P_2 */
10197 { "vaeskeygenassist", { XM, EXx, Ib } },
10201 static const struct dis386 mod_table[][2] = {
10204 { "leaS", { Gv, M } },
10209 { RM_TABLE (RM_C6_REG_7) },
10214 { RM_TABLE (RM_C7_REG_7) },
10217 /* MOD_0F01_REG_0 */
10218 { X86_64_TABLE (X86_64_0F01_REG_0) },
10219 { RM_TABLE (RM_0F01_REG_0) },
10222 /* MOD_0F01_REG_1 */
10223 { X86_64_TABLE (X86_64_0F01_REG_1) },
10224 { RM_TABLE (RM_0F01_REG_1) },
10227 /* MOD_0F01_REG_2 */
10228 { X86_64_TABLE (X86_64_0F01_REG_2) },
10229 { RM_TABLE (RM_0F01_REG_2) },
10232 /* MOD_0F01_REG_3 */
10233 { X86_64_TABLE (X86_64_0F01_REG_3) },
10234 { RM_TABLE (RM_0F01_REG_3) },
10237 /* MOD_0F01_REG_7 */
10238 { "invlpg", { Mb } },
10239 { RM_TABLE (RM_0F01_REG_7) },
10242 /* MOD_0F12_PREFIX_0 */
10243 { "movlps", { XM, EXq } },
10244 { "movhlps", { XM, EXq } },
10248 { "movlpX", { EXq, XM } },
10251 /* MOD_0F16_PREFIX_0 */
10252 { "movhps", { XM, EXq } },
10253 { "movlhps", { XM, EXq } },
10257 { "movhpX", { EXq, XM } },
10260 /* MOD_0F18_REG_0 */
10261 { "prefetchnta", { Mb } },
10264 /* MOD_0F18_REG_1 */
10265 { "prefetcht0", { Mb } },
10268 /* MOD_0F18_REG_2 */
10269 { "prefetcht1", { Mb } },
10272 /* MOD_0F18_REG_3 */
10273 { "prefetcht2", { Mb } },
10276 /* MOD_0F18_REG_4 */
10277 { "nop/reserved", { Mb } },
10280 /* MOD_0F18_REG_5 */
10281 { "nop/reserved", { Mb } },
10284 /* MOD_0F18_REG_6 */
10285 { "nop/reserved", { Mb } },
10288 /* MOD_0F18_REG_7 */
10289 { "nop/reserved", { Mb } },
10292 /* MOD_0F1A_PREFIX_0 */
10293 { "bndldx", { Gbnd, Ev_bnd } },
10294 { "nopQ", { Ev } },
10297 /* MOD_0F1B_PREFIX_0 */
10298 { "bndstx", { Ev_bnd, Gbnd } },
10299 { "nopQ", { Ev } },
10302 /* MOD_0F1B_PREFIX_1 */
10303 { "bndmk", { Gbnd, Ev_bnd } },
10304 { "nopQ", { Ev } },
10309 { "movZ", { Rm, Cm } },
10314 { "movZ", { Rm, Dm } },
10319 { "movZ", { Cm, Rm } },
10324 { "movZ", { Dm, Rm } },
10329 { "movL", { Rd, Td } },
10334 { "movL", { Td, Rd } },
10337 /* MOD_0F2B_PREFIX_0 */
10338 {"movntps", { Mx, XM } },
10341 /* MOD_0F2B_PREFIX_1 */
10342 {"movntss", { Md, XM } },
10345 /* MOD_0F2B_PREFIX_2 */
10346 {"movntpd", { Mx, XM } },
10349 /* MOD_0F2B_PREFIX_3 */
10350 {"movntsd", { Mq, XM } },
10355 { "movmskpX", { Gdq, XS } },
10358 /* MOD_0F71_REG_2 */
10360 { "psrlw", { MS, Ib } },
10363 /* MOD_0F71_REG_4 */
10365 { "psraw", { MS, Ib } },
10368 /* MOD_0F71_REG_6 */
10370 { "psllw", { MS, Ib } },
10373 /* MOD_0F72_REG_2 */
10375 { "psrld", { MS, Ib } },
10378 /* MOD_0F72_REG_4 */
10380 { "psrad", { MS, Ib } },
10383 /* MOD_0F72_REG_6 */
10385 { "pslld", { MS, Ib } },
10388 /* MOD_0F73_REG_2 */
10390 { "psrlq", { MS, Ib } },
10393 /* MOD_0F73_REG_3 */
10395 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10398 /* MOD_0F73_REG_6 */
10400 { "psllq", { MS, Ib } },
10403 /* MOD_0F73_REG_7 */
10405 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10408 /* MOD_0FAE_REG_0 */
10409 { "fxsave", { FXSAVE } },
10410 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10413 /* MOD_0FAE_REG_1 */
10414 { "fxrstor", { FXSAVE } },
10415 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10418 /* MOD_0FAE_REG_2 */
10419 { "ldmxcsr", { Md } },
10420 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10423 /* MOD_0FAE_REG_3 */
10424 { "stmxcsr", { Md } },
10425 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10428 /* MOD_0FAE_REG_4 */
10429 { "xsave", { FXSAVE } },
10432 /* MOD_0FAE_REG_5 */
10433 { "xrstor", { FXSAVE } },
10434 { RM_TABLE (RM_0FAE_REG_5) },
10437 /* MOD_0FAE_REG_6 */
10438 { "xsaveopt", { FXSAVE } },
10439 { RM_TABLE (RM_0FAE_REG_6) },
10442 /* MOD_0FAE_REG_7 */
10443 { "clflush", { Mb } },
10444 { RM_TABLE (RM_0FAE_REG_7) },
10448 { "lssS", { Gv, Mp } },
10452 { "lfsS", { Gv, Mp } },
10456 { "lgsS", { Gv, Mp } },
10459 /* MOD_0FC7_REG_6 */
10460 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
10461 { "rdrand", { Ev } },
10464 /* MOD_0FC7_REG_7 */
10465 { "vmptrst", { Mq } },
10466 { "rdseed", { Ev } },
10471 { "pmovmskb", { Gdq, MS } },
10474 /* MOD_0FE7_PREFIX_2 */
10475 { "movntdq", { Mx, XM } },
10478 /* MOD_0FF0_PREFIX_3 */
10479 { "lddqu", { XM, M } },
10482 /* MOD_0F382A_PREFIX_2 */
10483 { "movntdqa", { XM, Mx } },
10487 { "bound{S|}", { Gv, Ma } },
10491 { "lesS", { Gv, Mp } },
10492 { VEX_C4_TABLE (VEX_0F) },
10496 { "ldsS", { Gv, Mp } },
10497 { VEX_C5_TABLE (VEX_0F) },
10500 /* MOD_VEX_0F12_PREFIX_0 */
10501 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10502 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10506 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10509 /* MOD_VEX_0F16_PREFIX_0 */
10510 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10511 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10515 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10519 { VEX_W_TABLE (VEX_W_0F2B_M_0) },
10524 { VEX_W_TABLE (VEX_W_0F50_M_0) },
10527 /* MOD_VEX_0F71_REG_2 */
10529 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10532 /* MOD_VEX_0F71_REG_4 */
10534 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10537 /* MOD_VEX_0F71_REG_6 */
10539 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10542 /* MOD_VEX_0F72_REG_2 */
10544 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10547 /* MOD_VEX_0F72_REG_4 */
10549 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10552 /* MOD_VEX_0F72_REG_6 */
10554 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10557 /* MOD_VEX_0F73_REG_2 */
10559 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10562 /* MOD_VEX_0F73_REG_3 */
10564 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10567 /* MOD_VEX_0F73_REG_6 */
10569 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10572 /* MOD_VEX_0F73_REG_7 */
10574 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10577 /* MOD_VEX_0FAE_REG_2 */
10578 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10581 /* MOD_VEX_0FAE_REG_3 */
10582 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10585 /* MOD_VEX_0FD7_PREFIX_2 */
10587 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
10590 /* MOD_VEX_0FE7_PREFIX_2 */
10591 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
10594 /* MOD_VEX_0FF0_PREFIX_3 */
10595 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
10598 /* MOD_VEX_0F381A_PREFIX_2 */
10599 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10602 /* MOD_VEX_0F382A_PREFIX_2 */
10603 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
10606 /* MOD_VEX_0F382C_PREFIX_2 */
10607 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10610 /* MOD_VEX_0F382D_PREFIX_2 */
10611 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10614 /* MOD_VEX_0F382E_PREFIX_2 */
10615 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10618 /* MOD_VEX_0F382F_PREFIX_2 */
10619 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10622 /* MOD_VEX_0F385A_PREFIX_2 */
10623 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10626 /* MOD_VEX_0F388C_PREFIX_2 */
10627 { "vpmaskmov%LW", { XM, Vex, Mx } },
10630 /* MOD_VEX_0F388E_PREFIX_2 */
10631 { "vpmaskmov%LW", { Mx, Vex, XM } },
10635 static const struct dis386 rm_table[][8] = {
10638 { "xabort", { Skip_MODRM, Ib } },
10642 { "xbeginT", { Skip_MODRM, Jv } },
10645 /* RM_0F01_REG_0 */
10647 { "vmcall", { Skip_MODRM } },
10648 { "vmlaunch", { Skip_MODRM } },
10649 { "vmresume", { Skip_MODRM } },
10650 { "vmxoff", { Skip_MODRM } },
10653 /* RM_0F01_REG_1 */
10654 { "monitor", { { OP_Monitor, 0 } } },
10655 { "mwait", { { OP_Mwait, 0 } } },
10656 { "clac", { Skip_MODRM } },
10657 { "stac", { Skip_MODRM } },
10660 /* RM_0F01_REG_2 */
10661 { "xgetbv", { Skip_MODRM } },
10662 { "xsetbv", { Skip_MODRM } },
10665 { "vmfunc", { Skip_MODRM } },
10666 { "xend", { Skip_MODRM } },
10667 { "xtest", { Skip_MODRM } },
10671 /* RM_0F01_REG_3 */
10672 { "vmrun", { Skip_MODRM } },
10673 { "vmmcall", { Skip_MODRM } },
10674 { "vmload", { Skip_MODRM } },
10675 { "vmsave", { Skip_MODRM } },
10676 { "stgi", { Skip_MODRM } },
10677 { "clgi", { Skip_MODRM } },
10678 { "skinit", { Skip_MODRM } },
10679 { "invlpga", { Skip_MODRM } },
10682 /* RM_0F01_REG_7 */
10683 { "swapgs", { Skip_MODRM } },
10684 { "rdtscp", { Skip_MODRM } },
10687 /* RM_0FAE_REG_5 */
10688 { "lfence", { Skip_MODRM } },
10691 /* RM_0FAE_REG_6 */
10692 { "mfence", { Skip_MODRM } },
10695 /* RM_0FAE_REG_7 */
10696 { "sfence", { Skip_MODRM } },
10700 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10702 /* We use the high bit to indicate different name for the same
10704 #define ADDR16_PREFIX (0x67 | 0x100)
10705 #define ADDR32_PREFIX (0x67 | 0x200)
10706 #define DATA16_PREFIX (0x66 | 0x100)
10707 #define DATA32_PREFIX (0x66 | 0x200)
10708 #define REP_PREFIX (0xf3 | 0x100)
10709 #define XACQUIRE_PREFIX (0xf2 | 0x200)
10710 #define XRELEASE_PREFIX (0xf3 | 0x400)
10711 #define BND_PREFIX (0xf2 | 0x400)
10716 int newrex, i, length;
10722 last_lock_prefix = -1;
10723 last_repz_prefix = -1;
10724 last_repnz_prefix = -1;
10725 last_data_prefix = -1;
10726 last_addr_prefix = -1;
10727 last_rex_prefix = -1;
10728 last_seg_prefix = -1;
10729 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10730 all_prefixes[i] = 0;
10733 /* The maximum instruction length is 15bytes. */
10734 while (length < MAX_CODE_LENGTH - 1)
10736 FETCH_DATA (the_info, codep + 1);
10740 /* REX prefixes family. */
10757 if (address_mode == mode_64bit)
10761 last_rex_prefix = i;
10764 prefixes |= PREFIX_REPZ;
10765 last_repz_prefix = i;
10768 prefixes |= PREFIX_REPNZ;
10769 last_repnz_prefix = i;
10772 prefixes |= PREFIX_LOCK;
10773 last_lock_prefix = i;
10776 prefixes |= PREFIX_CS;
10777 last_seg_prefix = i;
10780 prefixes |= PREFIX_SS;
10781 last_seg_prefix = i;
10784 prefixes |= PREFIX_DS;
10785 last_seg_prefix = i;
10788 prefixes |= PREFIX_ES;
10789 last_seg_prefix = i;
10792 prefixes |= PREFIX_FS;
10793 last_seg_prefix = i;
10796 prefixes |= PREFIX_GS;
10797 last_seg_prefix = i;
10800 prefixes |= PREFIX_DATA;
10801 last_data_prefix = i;
10804 prefixes |= PREFIX_ADDR;
10805 last_addr_prefix = i;
10808 /* fwait is really an instruction. If there are prefixes
10809 before the fwait, they belong to the fwait, *not* to the
10810 following instruction. */
10811 if (prefixes || rex)
10813 prefixes |= PREFIX_FWAIT;
10815 /* This ensures that the previous REX prefixes are noticed
10816 as unused prefixes, as in the return case below. */
10820 prefixes = PREFIX_FWAIT;
10825 /* Rex is ignored when followed by another prefix. */
10831 if (*codep != FWAIT_OPCODE)
10832 all_prefixes[i++] = *codep;
10841 seg_prefix (int pref)
10862 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10865 static const char *
10866 prefix_name (int pref, int sizeflag)
10868 static const char *rexes [16] =
10871 "rex.B", /* 0x41 */
10872 "rex.X", /* 0x42 */
10873 "rex.XB", /* 0x43 */
10874 "rex.R", /* 0x44 */
10875 "rex.RB", /* 0x45 */
10876 "rex.RX", /* 0x46 */
10877 "rex.RXB", /* 0x47 */
10878 "rex.W", /* 0x48 */
10879 "rex.WB", /* 0x49 */
10880 "rex.WX", /* 0x4a */
10881 "rex.WXB", /* 0x4b */
10882 "rex.WR", /* 0x4c */
10883 "rex.WRB", /* 0x4d */
10884 "rex.WRX", /* 0x4e */
10885 "rex.WRXB", /* 0x4f */
10890 /* REX prefixes family. */
10907 return rexes [pref - 0x40];
10927 return (sizeflag & DFLAG) ? "data16" : "data32";
10929 if (address_mode == mode_64bit)
10930 return (sizeflag & AFLAG) ? "addr32" : "addr64";
10932 return (sizeflag & AFLAG) ? "addr16" : "addr32";
10935 case ADDR16_PREFIX:
10937 case ADDR32_PREFIX:
10939 case DATA16_PREFIX:
10941 case DATA32_PREFIX:
10945 case XACQUIRE_PREFIX:
10947 case XRELEASE_PREFIX:
10956 static char op_out[MAX_OPERANDS][100];
10957 static int op_ad, op_index[MAX_OPERANDS];
10958 static int two_source_ops;
10959 static bfd_vma op_address[MAX_OPERANDS];
10960 static bfd_vma op_riprel[MAX_OPERANDS];
10961 static bfd_vma start_pc;
10964 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10965 * (see topic "Redundant prefixes" in the "Differences from 8086"
10966 * section of the "Virtual 8086 Mode" chapter.)
10967 * 'pc' should be the address of this instruction, it will
10968 * be used to print the target address if this is a relative jump or call
10969 * The function returns the length of this instruction in bytes.
10972 static char intel_syntax;
10973 static char intel_mnemonic = !SYSV386_COMPAT;
10974 static char open_char;
10975 static char close_char;
10976 static char separator_char;
10977 static char scale_char;
10979 /* Here for backwards compatibility. When gdb stops using
10980 print_insn_i386_att and print_insn_i386_intel these functions can
10981 disappear, and print_insn_i386 be merged into print_insn. */
10983 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10987 return print_insn (pc, info);
10991 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10995 return print_insn (pc, info);
10999 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11003 return print_insn (pc, info);
11007 print_i386_disassembler_options (FILE *stream)
11009 fprintf (stream, _("\n\
11010 The following i386/x86-64 specific disassembler options are supported for use\n\
11011 with the -M switch (multiple options should be separated by commas):\n"));
11013 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
11014 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
11015 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
11016 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
11017 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
11018 fprintf (stream, _(" att-mnemonic\n"
11019 " Display instruction in AT&T mnemonic\n"));
11020 fprintf (stream, _(" intel-mnemonic\n"
11021 " Display instruction in Intel mnemonic\n"));
11022 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
11023 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
11024 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
11025 fprintf (stream, _(" data32 Assume 32bit data size\n"));
11026 fprintf (stream, _(" data16 Assume 16bit data size\n"));
11027 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11031 static const struct dis386 bad_opcode = { "(bad)", { XX } };
11033 /* Get a pointer to struct dis386 with a valid name. */
11035 static const struct dis386 *
11036 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11038 int vindex, vex_table_index;
11040 if (dp->name != NULL)
11043 switch (dp->op[0].bytemode)
11045 case USE_REG_TABLE:
11046 dp = ®_table[dp->op[1].bytemode][modrm.reg];
11049 case USE_MOD_TABLE:
11050 vindex = modrm.mod == 0x3 ? 1 : 0;
11051 dp = &mod_table[dp->op[1].bytemode][vindex];
11055 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11058 case USE_PREFIX_TABLE:
11061 /* The prefix in VEX is implicit. */
11062 switch (vex.prefix)
11067 case REPE_PREFIX_OPCODE:
11070 case DATA_PREFIX_OPCODE:
11073 case REPNE_PREFIX_OPCODE:
11084 used_prefixes |= (prefixes & PREFIX_REPZ);
11085 if (prefixes & PREFIX_REPZ)
11088 all_prefixes[last_repz_prefix] = 0;
11092 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11094 used_prefixes |= (prefixes & PREFIX_REPNZ);
11095 if (prefixes & PREFIX_REPNZ)
11098 all_prefixes[last_repnz_prefix] = 0;
11102 used_prefixes |= (prefixes & PREFIX_DATA);
11103 if (prefixes & PREFIX_DATA)
11106 all_prefixes[last_data_prefix] = 0;
11111 dp = &prefix_table[dp->op[1].bytemode][vindex];
11114 case USE_X86_64_TABLE:
11115 vindex = address_mode == mode_64bit ? 1 : 0;
11116 dp = &x86_64_table[dp->op[1].bytemode][vindex];
11119 case USE_3BYTE_TABLE:
11120 FETCH_DATA (info, codep + 2);
11122 dp = &three_byte_table[dp->op[1].bytemode][vindex];
11123 modrm.mod = (*codep >> 6) & 3;
11124 modrm.reg = (*codep >> 3) & 7;
11125 modrm.rm = *codep & 7;
11128 case USE_VEX_LEN_TABLE:
11132 switch (vex.length)
11145 dp = &vex_len_table[dp->op[1].bytemode][vindex];
11148 case USE_XOP_8F_TABLE:
11149 FETCH_DATA (info, codep + 3);
11150 /* All bits in the REX prefix are ignored. */
11152 rex = ~(*codep >> 5) & 0x7;
11154 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11155 switch ((*codep & 0x1f))
11161 vex_table_index = XOP_08;
11164 vex_table_index = XOP_09;
11167 vex_table_index = XOP_0A;
11171 vex.w = *codep & 0x80;
11172 if (vex.w && address_mode == mode_64bit)
11175 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11176 if (address_mode != mode_64bit
11177 && vex.register_specifier > 0x7)
11183 vex.length = (*codep & 0x4) ? 256 : 128;
11184 switch ((*codep & 0x3))
11190 vex.prefix = DATA_PREFIX_OPCODE;
11193 vex.prefix = REPE_PREFIX_OPCODE;
11196 vex.prefix = REPNE_PREFIX_OPCODE;
11203 dp = &xop_table[vex_table_index][vindex];
11205 FETCH_DATA (info, codep + 1);
11206 modrm.mod = (*codep >> 6) & 3;
11207 modrm.reg = (*codep >> 3) & 7;
11208 modrm.rm = *codep & 7;
11211 case USE_VEX_C4_TABLE:
11212 FETCH_DATA (info, codep + 3);
11213 /* All bits in the REX prefix are ignored. */
11215 rex = ~(*codep >> 5) & 0x7;
11216 switch ((*codep & 0x1f))
11222 vex_table_index = VEX_0F;
11225 vex_table_index = VEX_0F38;
11228 vex_table_index = VEX_0F3A;
11232 vex.w = *codep & 0x80;
11233 if (vex.w && address_mode == mode_64bit)
11236 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11237 if (address_mode != mode_64bit
11238 && vex.register_specifier > 0x7)
11244 vex.length = (*codep & 0x4) ? 256 : 128;
11245 switch ((*codep & 0x3))
11251 vex.prefix = DATA_PREFIX_OPCODE;
11254 vex.prefix = REPE_PREFIX_OPCODE;
11257 vex.prefix = REPNE_PREFIX_OPCODE;
11264 dp = &vex_table[vex_table_index][vindex];
11265 /* There is no MODRM byte for VEX [82|77]. */
11266 if (vindex != 0x77 && vindex != 0x82)
11268 FETCH_DATA (info, codep + 1);
11269 modrm.mod = (*codep >> 6) & 3;
11270 modrm.reg = (*codep >> 3) & 7;
11271 modrm.rm = *codep & 7;
11275 case USE_VEX_C5_TABLE:
11276 FETCH_DATA (info, codep + 2);
11277 /* All bits in the REX prefix are ignored. */
11279 rex = (*codep & 0x80) ? 0 : REX_R;
11281 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11282 if (address_mode != mode_64bit
11283 && vex.register_specifier > 0x7)
11291 vex.length = (*codep & 0x4) ? 256 : 128;
11292 switch ((*codep & 0x3))
11298 vex.prefix = DATA_PREFIX_OPCODE;
11301 vex.prefix = REPE_PREFIX_OPCODE;
11304 vex.prefix = REPNE_PREFIX_OPCODE;
11311 dp = &vex_table[dp->op[1].bytemode][vindex];
11312 /* There is no MODRM byte for VEX [82|77]. */
11313 if (vindex != 0x77 && vindex != 0x82)
11315 FETCH_DATA (info, codep + 1);
11316 modrm.mod = (*codep >> 6) & 3;
11317 modrm.reg = (*codep >> 3) & 7;
11318 modrm.rm = *codep & 7;
11322 case USE_VEX_W_TABLE:
11326 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11337 if (dp->name != NULL)
11340 return get_valid_dis386 (dp, info);
11344 get_sib (disassemble_info *info, int sizeflag)
11346 /* If modrm.mod == 3, operand must be register. */
11348 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11352 FETCH_DATA (info, codep + 2);
11353 sib.index = (codep [1] >> 3) & 7;
11354 sib.scale = (codep [1] >> 6) & 3;
11355 sib.base = codep [1] & 7;
11360 print_insn (bfd_vma pc, disassemble_info *info)
11362 const struct dis386 *dp;
11364 char *op_txt[MAX_OPERANDS];
11368 struct dis_private priv;
11370 int default_prefixes;
11372 priv.orig_sizeflag = AFLAG | DFLAG;
11373 if ((info->mach & bfd_mach_i386_i386) != 0)
11374 address_mode = mode_32bit;
11375 else if (info->mach == bfd_mach_i386_i8086)
11377 address_mode = mode_16bit;
11378 priv.orig_sizeflag = 0;
11381 address_mode = mode_64bit;
11383 if (intel_syntax == (char) -1)
11384 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11386 for (p = info->disassembler_options; p != NULL; )
11388 if (CONST_STRNEQ (p, "x86-64"))
11390 address_mode = mode_64bit;
11391 priv.orig_sizeflag = AFLAG | DFLAG;
11393 else if (CONST_STRNEQ (p, "i386"))
11395 address_mode = mode_32bit;
11396 priv.orig_sizeflag = AFLAG | DFLAG;
11398 else if (CONST_STRNEQ (p, "i8086"))
11400 address_mode = mode_16bit;
11401 priv.orig_sizeflag = 0;
11403 else if (CONST_STRNEQ (p, "intel"))
11406 if (CONST_STRNEQ (p + 5, "-mnemonic"))
11407 intel_mnemonic = 1;
11409 else if (CONST_STRNEQ (p, "att"))
11412 if (CONST_STRNEQ (p + 3, "-mnemonic"))
11413 intel_mnemonic = 0;
11415 else if (CONST_STRNEQ (p, "addr"))
11417 if (address_mode == mode_64bit)
11419 if (p[4] == '3' && p[5] == '2')
11420 priv.orig_sizeflag &= ~AFLAG;
11421 else if (p[4] == '6' && p[5] == '4')
11422 priv.orig_sizeflag |= AFLAG;
11426 if (p[4] == '1' && p[5] == '6')
11427 priv.orig_sizeflag &= ~AFLAG;
11428 else if (p[4] == '3' && p[5] == '2')
11429 priv.orig_sizeflag |= AFLAG;
11432 else if (CONST_STRNEQ (p, "data"))
11434 if (p[4] == '1' && p[5] == '6')
11435 priv.orig_sizeflag &= ~DFLAG;
11436 else if (p[4] == '3' && p[5] == '2')
11437 priv.orig_sizeflag |= DFLAG;
11439 else if (CONST_STRNEQ (p, "suffix"))
11440 priv.orig_sizeflag |= SUFFIX_ALWAYS;
11442 p = strchr (p, ',');
11449 names64 = intel_names64;
11450 names32 = intel_names32;
11451 names16 = intel_names16;
11452 names8 = intel_names8;
11453 names8rex = intel_names8rex;
11454 names_seg = intel_names_seg;
11455 names_mm = intel_names_mm;
11456 names_bnd = intel_names_bnd;
11457 names_xmm = intel_names_xmm;
11458 names_ymm = intel_names_ymm;
11459 index64 = intel_index64;
11460 index32 = intel_index32;
11461 index16 = intel_index16;
11464 separator_char = '+';
11469 names64 = att_names64;
11470 names32 = att_names32;
11471 names16 = att_names16;
11472 names8 = att_names8;
11473 names8rex = att_names8rex;
11474 names_seg = att_names_seg;
11475 names_mm = att_names_mm;
11476 names_bnd = att_names_bnd;
11477 names_xmm = att_names_xmm;
11478 names_ymm = att_names_ymm;
11479 index64 = att_index64;
11480 index32 = att_index32;
11481 index16 = att_index16;
11484 separator_char = ',';
11488 /* The output looks better if we put 7 bytes on a line, since that
11489 puts most long word instructions on a single line. Use 8 bytes
11491 if ((info->mach & bfd_mach_l1om) != 0)
11492 info->bytes_per_line = 8;
11494 info->bytes_per_line = 7;
11496 info->private_data = &priv;
11497 priv.max_fetched = priv.the_buffer;
11498 priv.insn_start = pc;
11501 for (i = 0; i < MAX_OPERANDS; ++i)
11509 start_codep = priv.the_buffer;
11510 codep = priv.the_buffer;
11512 if (setjmp (priv.bailout) != 0)
11516 /* Getting here means we tried for data but didn't get it. That
11517 means we have an incomplete instruction of some sort. Just
11518 print the first byte as a prefix or a .byte pseudo-op. */
11519 if (codep > priv.the_buffer)
11521 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11523 (*info->fprintf_func) (info->stream, "%s", name);
11526 /* Just print the first byte as a .byte instruction. */
11527 (*info->fprintf_func) (info->stream, ".byte 0x%x",
11528 (unsigned int) priv.the_buffer[0]);
11538 sizeflag = priv.orig_sizeflag;
11540 if (!ckprefix () || rex_used)
11542 /* Too many prefixes or unused REX prefixes. */
11544 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
11546 (*info->fprintf_func) (info->stream, "%s%s",
11548 prefix_name (all_prefixes[i], sizeflag));
11552 insn_codep = codep;
11554 FETCH_DATA (info, codep + 1);
11555 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11557 if (((prefixes & PREFIX_FWAIT)
11558 && ((*codep < 0xd8) || (*codep > 0xdf))))
11560 (*info->fprintf_func) (info->stream, "fwait");
11564 if (*codep == 0x0f)
11566 unsigned char threebyte;
11567 FETCH_DATA (info, codep + 2);
11568 threebyte = *++codep;
11569 dp = &dis386_twobyte[threebyte];
11570 need_modrm = twobyte_has_modrm[*codep];
11575 dp = &dis386[*codep];
11576 need_modrm = onebyte_has_modrm[*codep];
11580 if ((prefixes & PREFIX_REPZ))
11581 used_prefixes |= PREFIX_REPZ;
11582 if ((prefixes & PREFIX_REPNZ))
11583 used_prefixes |= PREFIX_REPNZ;
11584 if ((prefixes & PREFIX_LOCK))
11585 used_prefixes |= PREFIX_LOCK;
11587 default_prefixes = 0;
11588 if (prefixes & PREFIX_ADDR)
11591 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
11593 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11594 all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
11596 all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
11597 default_prefixes |= PREFIX_ADDR;
11601 if ((prefixes & PREFIX_DATA))
11604 if (dp->op[2].bytemode == cond_jump_mode
11605 && dp->op[0].bytemode == v_mode
11608 if (sizeflag & DFLAG)
11609 all_prefixes[last_data_prefix] = DATA32_PREFIX;
11611 all_prefixes[last_data_prefix] = DATA16_PREFIX;
11612 default_prefixes |= PREFIX_DATA;
11614 else if (rex & REX_W)
11616 /* REX_W will override PREFIX_DATA. */
11617 default_prefixes |= PREFIX_DATA;
11623 FETCH_DATA (info, codep + 1);
11624 modrm.mod = (*codep >> 6) & 3;
11625 modrm.reg = (*codep >> 3) & 7;
11626 modrm.rm = *codep & 7;
11633 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11635 get_sib (info, sizeflag);
11636 dofloat (sizeflag);
11640 dp = get_valid_dis386 (dp, info);
11641 if (dp != NULL && putop (dp->name, sizeflag) == 0)
11643 get_sib (info, sizeflag);
11644 for (i = 0; i < MAX_OPERANDS; ++i)
11647 op_ad = MAX_OPERANDS - 1 - i;
11649 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
11654 /* See if any prefixes were not used. If so, print the first one
11655 separately. If we don't do this, we'll wind up printing an
11656 instruction stream which does not precisely correspond to the
11657 bytes we are disassembling. */
11658 if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
11660 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11661 if (all_prefixes[i])
11664 name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
11666 name = INTERNAL_DISASSEMBLER_ERROR;
11667 (*info->fprintf_func) (info->stream, "%s", name);
11672 /* Check if the REX prefix is used. */
11673 if (rex_ignored == 0 && (rex ^ rex_used) == 0)
11674 all_prefixes[last_rex_prefix] = 0;
11676 /* Check if the SEG prefix is used. */
11677 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
11678 | PREFIX_FS | PREFIX_GS)) != 0
11680 & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
11681 all_prefixes[last_seg_prefix] = 0;
11683 /* Check if the ADDR prefix is used. */
11684 if ((prefixes & PREFIX_ADDR) != 0
11685 && (used_prefixes & PREFIX_ADDR) != 0)
11686 all_prefixes[last_addr_prefix] = 0;
11688 /* Check if the DATA prefix is used. */
11689 if ((prefixes & PREFIX_DATA) != 0
11690 && (used_prefixes & PREFIX_DATA) != 0)
11691 all_prefixes[last_data_prefix] = 0;
11694 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11695 if (all_prefixes[i])
11698 name = prefix_name (all_prefixes[i], sizeflag);
11701 prefix_length += strlen (name) + 1;
11702 (*info->fprintf_func) (info->stream, "%s ", name);
11705 /* Check maximum code length. */
11706 if ((codep - start_codep) > MAX_CODE_LENGTH)
11708 (*info->fprintf_func) (info->stream, "(bad)");
11709 return MAX_CODE_LENGTH;
11712 obufp = mnemonicendp;
11713 for (i = strlen (obuf) + prefix_length; i < 6; i++)
11716 (*info->fprintf_func) (info->stream, "%s", obuf);
11718 /* The enter and bound instructions are printed with operands in the same
11719 order as the intel book; everything else is printed in reverse order. */
11720 if (intel_syntax || two_source_ops)
11724 for (i = 0; i < MAX_OPERANDS; ++i)
11725 op_txt[i] = op_out[i];
11727 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
11729 op_ad = op_index[i];
11730 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
11731 op_index[MAX_OPERANDS - 1 - i] = op_ad;
11732 riprel = op_riprel[i];
11733 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
11734 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
11739 for (i = 0; i < MAX_OPERANDS; ++i)
11740 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
11744 for (i = 0; i < MAX_OPERANDS; ++i)
11748 (*info->fprintf_func) (info->stream, ",");
11749 if (op_index[i] != -1 && !op_riprel[i])
11750 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
11752 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
11756 for (i = 0; i < MAX_OPERANDS; i++)
11757 if (op_index[i] != -1 && op_riprel[i])
11759 (*info->fprintf_func) (info->stream, " # ");
11760 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
11761 + op_address[op_index[i]]), info);
11764 return codep - priv.the_buffer;
11767 static const char *float_mem[] = {
11842 static const unsigned char float_mem_mode[] = {
11917 #define ST { OP_ST, 0 }
11918 #define STi { OP_STi, 0 }
11920 #define FGRPd9_2 NULL, { { NULL, 0 } }
11921 #define FGRPd9_4 NULL, { { NULL, 1 } }
11922 #define FGRPd9_5 NULL, { { NULL, 2 } }
11923 #define FGRPd9_6 NULL, { { NULL, 3 } }
11924 #define FGRPd9_7 NULL, { { NULL, 4 } }
11925 #define FGRPda_5 NULL, { { NULL, 5 } }
11926 #define FGRPdb_4 NULL, { { NULL, 6 } }
11927 #define FGRPde_3 NULL, { { NULL, 7 } }
11928 #define FGRPdf_4 NULL, { { NULL, 8 } }
11930 static const struct dis386 float_reg[][8] = {
11933 { "fadd", { ST, STi } },
11934 { "fmul", { ST, STi } },
11935 { "fcom", { STi } },
11936 { "fcomp", { STi } },
11937 { "fsub", { ST, STi } },
11938 { "fsubr", { ST, STi } },
11939 { "fdiv", { ST, STi } },
11940 { "fdivr", { ST, STi } },
11944 { "fld", { STi } },
11945 { "fxch", { STi } },
11955 { "fcmovb", { ST, STi } },
11956 { "fcmove", { ST, STi } },
11957 { "fcmovbe",{ ST, STi } },
11958 { "fcmovu", { ST, STi } },
11966 { "fcmovnb",{ ST, STi } },
11967 { "fcmovne",{ ST, STi } },
11968 { "fcmovnbe",{ ST, STi } },
11969 { "fcmovnu",{ ST, STi } },
11971 { "fucomi", { ST, STi } },
11972 { "fcomi", { ST, STi } },
11977 { "fadd", { STi, ST } },
11978 { "fmul", { STi, ST } },
11981 { "fsub!M", { STi, ST } },
11982 { "fsubM", { STi, ST } },
11983 { "fdiv!M", { STi, ST } },
11984 { "fdivM", { STi, ST } },
11988 { "ffree", { STi } },
11990 { "fst", { STi } },
11991 { "fstp", { STi } },
11992 { "fucom", { STi } },
11993 { "fucomp", { STi } },
11999 { "faddp", { STi, ST } },
12000 { "fmulp", { STi, ST } },
12003 { "fsub!Mp", { STi, ST } },
12004 { "fsubMp", { STi, ST } },
12005 { "fdiv!Mp", { STi, ST } },
12006 { "fdivMp", { STi, ST } },
12010 { "ffreep", { STi } },
12015 { "fucomip", { ST, STi } },
12016 { "fcomip", { ST, STi } },
12021 static char *fgrps[][8] = {
12024 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12029 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12034 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12039 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12044 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12049 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12054 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12055 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12060 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12065 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12070 swap_operand (void)
12072 mnemonicendp[0] = '.';
12073 mnemonicendp[1] = 's';
12078 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12079 int sizeflag ATTRIBUTE_UNUSED)
12081 /* Skip mod/rm byte. */
12087 dofloat (int sizeflag)
12089 const struct dis386 *dp;
12090 unsigned char floatop;
12092 floatop = codep[-1];
12094 if (modrm.mod != 3)
12096 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12098 putop (float_mem[fp_indx], sizeflag);
12101 OP_E (float_mem_mode[fp_indx], sizeflag);
12104 /* Skip mod/rm byte. */
12108 dp = &float_reg[floatop - 0xd8][modrm.reg];
12109 if (dp->name == NULL)
12111 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12113 /* Instruction fnstsw is only one with strange arg. */
12114 if (floatop == 0xdf && codep[-1] == 0xe0)
12115 strcpy (op_out[0], names16[0]);
12119 putop (dp->name, sizeflag);
12124 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12129 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12134 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12136 oappend ("%st" + intel_syntax);
12140 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12142 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12143 oappend (scratchbuf + intel_syntax);
12146 /* Capital letters in template are macros. */
12148 putop (const char *in_template, int sizeflag)
12153 unsigned int l = 0, len = 1;
12156 #define SAVE_LAST(c) \
12157 if (l < len && l < sizeof (last)) \
12162 for (p = in_template; *p; p++)
12179 while (*++p != '|')
12180 if (*p == '}' || *p == '\0')
12183 /* Fall through. */
12188 while (*++p != '}')
12199 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12203 if (l == 0 && len == 1)
12208 if (sizeflag & SUFFIX_ALWAYS)
12221 if (address_mode == mode_64bit
12222 && !(prefixes & PREFIX_ADDR))
12233 if (intel_syntax && !alt)
12235 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12237 if (sizeflag & DFLAG)
12238 *obufp++ = intel_syntax ? 'd' : 'l';
12240 *obufp++ = intel_syntax ? 'w' : 's';
12241 used_prefixes |= (prefixes & PREFIX_DATA);
12245 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12248 if (modrm.mod == 3)
12254 if (sizeflag & DFLAG)
12255 *obufp++ = intel_syntax ? 'd' : 'l';
12258 used_prefixes |= (prefixes & PREFIX_DATA);
12264 case 'E': /* For jcxz/jecxz */
12265 if (address_mode == mode_64bit)
12267 if (sizeflag & AFLAG)
12273 if (sizeflag & AFLAG)
12275 used_prefixes |= (prefixes & PREFIX_ADDR);
12280 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12282 if (sizeflag & AFLAG)
12283 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12285 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12286 used_prefixes |= (prefixes & PREFIX_ADDR);
12290 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12292 if ((rex & REX_W) || (sizeflag & DFLAG))
12296 if (!(rex & REX_W))
12297 used_prefixes |= (prefixes & PREFIX_DATA);
12302 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12303 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12305 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12308 if (prefixes & PREFIX_DS)
12329 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12334 /* Fall through. */
12337 if (l != 0 || len != 1)
12345 if (sizeflag & SUFFIX_ALWAYS)
12349 if (intel_mnemonic != cond)
12353 if ((prefixes & PREFIX_FWAIT) == 0)
12356 used_prefixes |= PREFIX_FWAIT;
12362 else if (intel_syntax && (sizeflag & DFLAG))
12366 if (!(rex & REX_W))
12367 used_prefixes |= (prefixes & PREFIX_DATA);
12371 && address_mode == mode_64bit
12372 && ((sizeflag & DFLAG) || (rex & REX_W)))
12377 /* Fall through. */
12381 if ((rex & REX_W) == 0
12382 && (prefixes & PREFIX_DATA))
12384 if ((sizeflag & DFLAG) == 0)
12386 used_prefixes |= (prefixes & PREFIX_DATA);
12390 if ((prefixes & PREFIX_DATA)
12392 || (sizeflag & SUFFIX_ALWAYS))
12399 if (sizeflag & DFLAG)
12403 used_prefixes |= (prefixes & PREFIX_DATA);
12410 if (address_mode == mode_64bit
12411 && ((sizeflag & DFLAG) || (rex & REX_W)))
12413 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12417 /* Fall through. */
12420 if (l == 0 && len == 1)
12423 if (intel_syntax && !alt)
12426 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12432 if (sizeflag & DFLAG)
12433 *obufp++ = intel_syntax ? 'd' : 'l';
12436 used_prefixes |= (prefixes & PREFIX_DATA);
12442 if (l != 1 || len != 2 || last[0] != 'L')
12448 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12463 else if (sizeflag & DFLAG)
12472 if (intel_syntax && !p[1]
12473 && ((rex & REX_W) || (sizeflag & DFLAG)))
12475 if (!(rex & REX_W))
12476 used_prefixes |= (prefixes & PREFIX_DATA);
12479 if (l == 0 && len == 1)
12483 if (address_mode == mode_64bit
12484 && ((sizeflag & DFLAG) || (rex & REX_W)))
12486 if (sizeflag & SUFFIX_ALWAYS)
12508 /* Fall through. */
12511 if (l == 0 && len == 1)
12516 if (sizeflag & SUFFIX_ALWAYS)
12522 if (sizeflag & DFLAG)
12526 used_prefixes |= (prefixes & PREFIX_DATA);
12540 if (address_mode == mode_64bit
12541 && !(prefixes & PREFIX_ADDR))
12552 if (l != 0 || len != 1)
12557 if (need_vex && vex.prefix)
12559 if (vex.prefix == DATA_PREFIX_OPCODE)
12566 if (prefixes & PREFIX_DATA)
12570 used_prefixes |= (prefixes & PREFIX_DATA);
12574 if (l == 0 && len == 1)
12576 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12587 if (l != 1 || len != 2 || last[0] != 'X')
12595 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12597 switch (vex.length)
12611 if (l == 0 && len == 1)
12613 /* operand size flag for cwtl, cbtw */
12622 else if (sizeflag & DFLAG)
12626 if (!(rex & REX_W))
12627 used_prefixes |= (prefixes & PREFIX_DATA);
12634 && last[0] != 'L'))
12641 if (last[0] == 'X')
12642 *obufp++ = vex.w ? 'd': 's';
12644 *obufp++ = vex.w ? 'q': 'd';
12651 mnemonicendp = obufp;
12656 oappend (const char *s)
12658 obufp = stpcpy (obufp, s);
12664 if (prefixes & PREFIX_CS)
12666 used_prefixes |= PREFIX_CS;
12667 oappend ("%cs:" + intel_syntax);
12669 if (prefixes & PREFIX_DS)
12671 used_prefixes |= PREFIX_DS;
12672 oappend ("%ds:" + intel_syntax);
12674 if (prefixes & PREFIX_SS)
12676 used_prefixes |= PREFIX_SS;
12677 oappend ("%ss:" + intel_syntax);
12679 if (prefixes & PREFIX_ES)
12681 used_prefixes |= PREFIX_ES;
12682 oappend ("%es:" + intel_syntax);
12684 if (prefixes & PREFIX_FS)
12686 used_prefixes |= PREFIX_FS;
12687 oappend ("%fs:" + intel_syntax);
12689 if (prefixes & PREFIX_GS)
12691 used_prefixes |= PREFIX_GS;
12692 oappend ("%gs:" + intel_syntax);
12697 OP_indirE (int bytemode, int sizeflag)
12701 OP_E (bytemode, sizeflag);
12705 print_operand_value (char *buf, int hex, bfd_vma disp)
12707 if (address_mode == mode_64bit)
12715 sprintf_vma (tmp, disp);
12716 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
12717 strcpy (buf + 2, tmp + i);
12721 bfd_signed_vma v = disp;
12728 /* Check for possible overflow on 0x8000000000000000. */
12731 strcpy (buf, "9223372036854775808");
12745 tmp[28 - i] = (v % 10) + '0';
12749 strcpy (buf, tmp + 29 - i);
12755 sprintf (buf, "0x%x", (unsigned int) disp);
12757 sprintf (buf, "%d", (int) disp);
12761 /* Put DISP in BUF as signed hex number. */
12764 print_displacement (char *buf, bfd_vma disp)
12766 bfd_signed_vma val = disp;
12775 /* Check for possible overflow. */
12778 switch (address_mode)
12781 strcpy (buf + j, "0x8000000000000000");
12784 strcpy (buf + j, "0x80000000");
12787 strcpy (buf + j, "0x8000");
12797 sprintf_vma (tmp, (bfd_vma) val);
12798 for (i = 0; tmp[i] == '0'; i++)
12800 if (tmp[i] == '\0')
12802 strcpy (buf + j, tmp + i);
12806 intel_operand_size (int bytemode, int sizeflag)
12813 oappend ("BYTE PTR ");
12817 oappend ("WORD PTR ");
12820 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
12822 oappend ("QWORD PTR ");
12832 oappend ("QWORD PTR ");
12835 if ((sizeflag & DFLAG) || bytemode == dq_mode)
12836 oappend ("DWORD PTR ");
12838 oappend ("WORD PTR ");
12839 used_prefixes |= (prefixes & PREFIX_DATA);
12843 if ((rex & REX_W) || (sizeflag & DFLAG))
12845 oappend ("WORD PTR ");
12846 if (!(rex & REX_W))
12847 used_prefixes |= (prefixes & PREFIX_DATA);
12850 if (sizeflag & DFLAG)
12851 oappend ("QWORD PTR ");
12853 oappend ("DWORD PTR ");
12854 used_prefixes |= (prefixes & PREFIX_DATA);
12857 case d_scalar_mode:
12858 case d_scalar_swap_mode:
12861 oappend ("DWORD PTR ");
12864 case q_scalar_mode:
12865 case q_scalar_swap_mode:
12867 oappend ("QWORD PTR ");
12870 if (address_mode == mode_64bit)
12871 oappend ("QWORD PTR ");
12873 oappend ("DWORD PTR ");
12876 if (sizeflag & DFLAG)
12877 oappend ("FWORD PTR ");
12879 oappend ("DWORD PTR ");
12880 used_prefixes |= (prefixes & PREFIX_DATA);
12883 oappend ("TBYTE PTR ");
12889 switch (vex.length)
12892 oappend ("XMMWORD PTR ");
12895 oappend ("YMMWORD PTR ");
12902 oappend ("XMMWORD PTR ");
12905 oappend ("XMMWORD PTR ");
12911 switch (vex.length)
12914 oappend ("QWORD PTR ");
12917 oappend ("XMMWORD PTR ");
12927 switch (vex.length)
12931 oappend ("BYTE PTR ");
12941 switch (vex.length)
12945 oappend ("WORD PTR ");
12955 switch (vex.length)
12959 oappend ("DWORD PTR ");
12969 switch (vex.length)
12973 oappend ("QWORD PTR ");
12983 switch (vex.length)
12986 oappend ("WORD PTR ");
12989 oappend ("DWORD PTR ");
12999 switch (vex.length)
13002 oappend ("DWORD PTR ");
13005 oappend ("QWORD PTR ");
13015 switch (vex.length)
13018 oappend ("QWORD PTR ");
13021 oappend ("YMMWORD PTR ");
13031 switch (vex.length)
13035 oappend ("XMMWORD PTR ");
13042 oappend ("OWORD PTR ");
13044 case vex_w_dq_mode:
13045 case vex_scalar_w_dq_mode:
13046 case vex_vsib_d_w_dq_mode:
13047 case vex_vsib_q_w_dq_mode:
13052 oappend ("QWORD PTR ");
13054 oappend ("DWORD PTR ");
13062 OP_E_register (int bytemode, int sizeflag)
13064 int reg = modrm.rm;
13065 const char **names;
13071 if ((sizeflag & SUFFIX_ALWAYS)
13072 && (bytemode == b_swap_mode || bytemode == v_swap_mode))
13095 names = address_mode == mode_64bit ? names64 : names32;
13101 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13120 if ((sizeflag & DFLAG)
13121 || (bytemode != v_mode
13122 && bytemode != v_swap_mode))
13126 used_prefixes |= (prefixes & PREFIX_DATA);
13132 oappend (INTERNAL_DISASSEMBLER_ERROR);
13135 oappend (names[reg]);
13139 OP_E_memory (int bytemode, int sizeflag)
13142 int add = (rex & REX_B) ? 8 : 0;
13147 intel_operand_size (bytemode, sizeflag);
13150 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13152 /* 32/64 bit address mode */
13161 int addr32flag = !((sizeflag & AFLAG)
13162 || bytemode == v_bnd_mode
13163 || bytemode == bnd_mode);
13164 const char **indexes64 = names64;
13165 const char **indexes32 = names32;
13175 vindex = sib.index;
13181 case vex_vsib_d_w_dq_mode:
13182 case vex_vsib_q_w_dq_mode:
13187 switch (vex.length)
13190 indexes64 = indexes32 = names_xmm;
13193 if (!vex.w || bytemode == vex_vsib_q_w_dq_mode)
13194 indexes64 = indexes32 = names_ymm;
13196 indexes64 = indexes32 = names_xmm;
13203 haveindex = vindex != 4;
13210 rbase = base + add;
13218 if (address_mode == mode_64bit && !havesib)
13224 FETCH_DATA (the_info, codep + 1);
13226 if ((disp & 0x80) != 0)
13234 /* In 32bit mode, we need index register to tell [offset] from
13235 [eiz*1 + offset]. */
13236 needindex = (havesib
13239 && address_mode == mode_32bit);
13240 havedisp = (havebase
13242 || (havesib && (haveindex || scale != 0)));
13245 if (modrm.mod != 0 || base == 5)
13247 if (havedisp || riprel)
13248 print_displacement (scratchbuf, disp);
13250 print_operand_value (scratchbuf, 1, disp);
13251 oappend (scratchbuf);
13255 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
13259 if ((havebase || haveindex || riprel)
13260 && (bytemode != v_bnd_mode)
13261 && (bytemode != bnd_mode))
13262 used_prefixes |= PREFIX_ADDR;
13264 if (havedisp || (intel_syntax && riprel))
13266 *obufp++ = open_char;
13267 if (intel_syntax && riprel)
13270 oappend (sizeflag & AFLAG ? "rip" : "eip");
13274 oappend (address_mode == mode_64bit && !addr32flag
13275 ? names64[rbase] : names32[rbase]);
13278 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
13279 print index to tell base + index from base. */
13283 || (havebase && base != ESP_REG_NUM))
13285 if (!intel_syntax || havebase)
13287 *obufp++ = separator_char;
13291 oappend (address_mode == mode_64bit && !addr32flag
13292 ? indexes64[vindex] : indexes32[vindex]);
13294 oappend (address_mode == mode_64bit && !addr32flag
13295 ? index64 : index32);
13297 *obufp++ = scale_char;
13299 sprintf (scratchbuf, "%d", 1 << scale);
13300 oappend (scratchbuf);
13304 && (disp || modrm.mod != 0 || base == 5))
13306 if (!havedisp || (bfd_signed_vma) disp >= 0)
13311 else if (modrm.mod != 1 && disp != -disp)
13315 disp = - (bfd_signed_vma) disp;
13319 print_displacement (scratchbuf, disp);
13321 print_operand_value (scratchbuf, 1, disp);
13322 oappend (scratchbuf);
13325 *obufp++ = close_char;
13328 else if (intel_syntax)
13330 if (modrm.mod != 0 || base == 5)
13332 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13333 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13337 oappend (names_seg[ds_reg - es_reg]);
13340 print_operand_value (scratchbuf, 1, disp);
13341 oappend (scratchbuf);
13347 /* 16 bit address mode */
13348 used_prefixes |= prefixes & PREFIX_ADDR;
13355 if ((disp & 0x8000) != 0)
13360 FETCH_DATA (the_info, codep + 1);
13362 if ((disp & 0x80) != 0)
13367 if ((disp & 0x8000) != 0)
13373 if (modrm.mod != 0 || modrm.rm == 6)
13375 print_displacement (scratchbuf, disp);
13376 oappend (scratchbuf);
13379 if (modrm.mod != 0 || modrm.rm != 6)
13381 *obufp++ = open_char;
13383 oappend (index16[modrm.rm]);
13385 && (disp || modrm.mod != 0 || modrm.rm == 6))
13387 if ((bfd_signed_vma) disp >= 0)
13392 else if (modrm.mod != 1)
13396 disp = - (bfd_signed_vma) disp;
13399 print_displacement (scratchbuf, disp);
13400 oappend (scratchbuf);
13403 *obufp++ = close_char;
13406 else if (intel_syntax)
13408 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13409 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13413 oappend (names_seg[ds_reg - es_reg]);
13416 print_operand_value (scratchbuf, 1, disp & 0xffff);
13417 oappend (scratchbuf);
13423 OP_E (int bytemode, int sizeflag)
13425 /* Skip mod/rm byte. */
13429 if (modrm.mod == 3)
13430 OP_E_register (bytemode, sizeflag);
13432 OP_E_memory (bytemode, sizeflag);
13436 OP_G (int bytemode, int sizeflag)
13447 oappend (names8rex[modrm.reg + add]);
13449 oappend (names8[modrm.reg + add]);
13452 oappend (names16[modrm.reg + add]);
13455 oappend (names32[modrm.reg + add]);
13458 oappend (names64[modrm.reg + add]);
13461 oappend (names_bnd[modrm.reg]);
13470 oappend (names64[modrm.reg + add]);
13473 if ((sizeflag & DFLAG) || bytemode != v_mode)
13474 oappend (names32[modrm.reg + add]);
13476 oappend (names16[modrm.reg + add]);
13477 used_prefixes |= (prefixes & PREFIX_DATA);
13481 if (address_mode == mode_64bit)
13482 oappend (names64[modrm.reg + add]);
13484 oappend (names32[modrm.reg + add]);
13487 oappend (INTERNAL_DISASSEMBLER_ERROR);
13500 FETCH_DATA (the_info, codep + 8);
13501 a = *codep++ & 0xff;
13502 a |= (*codep++ & 0xff) << 8;
13503 a |= (*codep++ & 0xff) << 16;
13504 a |= (*codep++ & 0xff) << 24;
13505 b = *codep++ & 0xff;
13506 b |= (*codep++ & 0xff) << 8;
13507 b |= (*codep++ & 0xff) << 16;
13508 b |= (*codep++ & 0xff) << 24;
13509 x = a + ((bfd_vma) b << 32);
13517 static bfd_signed_vma
13520 bfd_signed_vma x = 0;
13522 FETCH_DATA (the_info, codep + 4);
13523 x = *codep++ & (bfd_signed_vma) 0xff;
13524 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13525 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13526 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13530 static bfd_signed_vma
13533 bfd_signed_vma x = 0;
13535 FETCH_DATA (the_info, codep + 4);
13536 x = *codep++ & (bfd_signed_vma) 0xff;
13537 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13538 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13539 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13541 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
13551 FETCH_DATA (the_info, codep + 2);
13552 x = *codep++ & 0xff;
13553 x |= (*codep++ & 0xff) << 8;
13558 set_op (bfd_vma op, int riprel)
13560 op_index[op_ad] = op_ad;
13561 if (address_mode == mode_64bit)
13563 op_address[op_ad] = op;
13564 op_riprel[op_ad] = riprel;
13568 /* Mask to get a 32-bit address. */
13569 op_address[op_ad] = op & 0xffffffff;
13570 op_riprel[op_ad] = riprel & 0xffffffff;
13575 OP_REG (int code, int sizeflag)
13582 case es_reg: case ss_reg: case cs_reg:
13583 case ds_reg: case fs_reg: case gs_reg:
13584 oappend (names_seg[code - es_reg]);
13596 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13597 case sp_reg: case bp_reg: case si_reg: case di_reg:
13598 s = names16[code - ax_reg + add];
13600 case al_reg: case ah_reg: case cl_reg: case ch_reg:
13601 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13604 s = names8rex[code - al_reg + add];
13606 s = names8[code - al_reg];
13608 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
13609 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
13610 if (address_mode == mode_64bit
13611 && ((sizeflag & DFLAG) || (rex & REX_W)))
13613 s = names64[code - rAX_reg + add];
13616 code += eAX_reg - rAX_reg;
13617 /* Fall through. */
13618 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13619 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13622 s = names64[code - eAX_reg + add];
13625 if (sizeflag & DFLAG)
13626 s = names32[code - eAX_reg + add];
13628 s = names16[code - eAX_reg + add];
13629 used_prefixes |= (prefixes & PREFIX_DATA);
13633 s = INTERNAL_DISASSEMBLER_ERROR;
13640 OP_IMREG (int code, int sizeflag)
13652 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13653 case sp_reg: case bp_reg: case si_reg: case di_reg:
13654 s = names16[code - ax_reg];
13656 case es_reg: case ss_reg: case cs_reg:
13657 case ds_reg: case fs_reg: case gs_reg:
13658 s = names_seg[code - es_reg];
13660 case al_reg: case ah_reg: case cl_reg: case ch_reg:
13661 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13664 s = names8rex[code - al_reg];
13666 s = names8[code - al_reg];
13668 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13669 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13672 s = names64[code - eAX_reg];
13675 if (sizeflag & DFLAG)
13676 s = names32[code - eAX_reg];
13678 s = names16[code - eAX_reg];
13679 used_prefixes |= (prefixes & PREFIX_DATA);
13682 case z_mode_ax_reg:
13683 if ((rex & REX_W) || (sizeflag & DFLAG))
13687 if (!(rex & REX_W))
13688 used_prefixes |= (prefixes & PREFIX_DATA);
13691 s = INTERNAL_DISASSEMBLER_ERROR;
13698 OP_I (int bytemode, int sizeflag)
13701 bfd_signed_vma mask = -1;
13706 FETCH_DATA (the_info, codep + 1);
13711 if (address_mode == mode_64bit)
13716 /* Fall through. */
13723 if (sizeflag & DFLAG)
13733 used_prefixes |= (prefixes & PREFIX_DATA);
13745 oappend (INTERNAL_DISASSEMBLER_ERROR);
13750 scratchbuf[0] = '$';
13751 print_operand_value (scratchbuf + 1, 1, op);
13752 oappend (scratchbuf + intel_syntax);
13753 scratchbuf[0] = '\0';
13757 OP_I64 (int bytemode, int sizeflag)
13760 bfd_signed_vma mask = -1;
13762 if (address_mode != mode_64bit)
13764 OP_I (bytemode, sizeflag);
13771 FETCH_DATA (the_info, codep + 1);
13781 if (sizeflag & DFLAG)
13791 used_prefixes |= (prefixes & PREFIX_DATA);
13799 oappend (INTERNAL_DISASSEMBLER_ERROR);
13804 scratchbuf[0] = '$';
13805 print_operand_value (scratchbuf + 1, 1, op);
13806 oappend (scratchbuf + intel_syntax);
13807 scratchbuf[0] = '\0';
13811 OP_sI (int bytemode, int sizeflag)
13819 FETCH_DATA (the_info, codep + 1);
13821 if ((op & 0x80) != 0)
13823 if (bytemode == b_T_mode)
13825 if (address_mode != mode_64bit
13826 || !((sizeflag & DFLAG) || (rex & REX_W)))
13828 /* The operand-size prefix is overridden by a REX prefix. */
13829 if ((sizeflag & DFLAG) || (rex & REX_W))
13837 if (!(rex & REX_W))
13839 if (sizeflag & DFLAG)
13847 /* The operand-size prefix is overridden by a REX prefix. */
13848 if ((sizeflag & DFLAG) || (rex & REX_W))
13854 oappend (INTERNAL_DISASSEMBLER_ERROR);
13858 scratchbuf[0] = '$';
13859 print_operand_value (scratchbuf + 1, 1, op);
13860 oappend (scratchbuf + intel_syntax);
13864 OP_J (int bytemode, int sizeflag)
13868 bfd_vma segment = 0;
13873 FETCH_DATA (the_info, codep + 1);
13875 if ((disp & 0x80) != 0)
13880 if ((sizeflag & DFLAG) || (rex & REX_W))
13885 if ((disp & 0x8000) != 0)
13887 /* In 16bit mode, address is wrapped around at 64k within
13888 the same segment. Otherwise, a data16 prefix on a jump
13889 instruction means that the pc is masked to 16 bits after
13890 the displacement is added! */
13892 if ((prefixes & PREFIX_DATA) == 0)
13893 segment = ((start_pc + codep - start_codep)
13894 & ~((bfd_vma) 0xffff));
13896 if (!(rex & REX_W))
13897 used_prefixes |= (prefixes & PREFIX_DATA);
13900 oappend (INTERNAL_DISASSEMBLER_ERROR);
13903 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
13905 print_operand_value (scratchbuf, 1, disp);
13906 oappend (scratchbuf);
13910 OP_SEG (int bytemode, int sizeflag)
13912 if (bytemode == w_mode)
13913 oappend (names_seg[modrm.reg]);
13915 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
13919 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
13923 if (sizeflag & DFLAG)
13933 used_prefixes |= (prefixes & PREFIX_DATA);
13935 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
13937 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
13938 oappend (scratchbuf);
13942 OP_OFF (int bytemode, int sizeflag)
13946 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13947 intel_operand_size (bytemode, sizeflag);
13950 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13957 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13958 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13960 oappend (names_seg[ds_reg - es_reg]);
13964 print_operand_value (scratchbuf, 1, off);
13965 oappend (scratchbuf);
13969 OP_OFF64 (int bytemode, int sizeflag)
13973 if (address_mode != mode_64bit
13974 || (prefixes & PREFIX_ADDR))
13976 OP_OFF (bytemode, sizeflag);
13980 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13981 intel_operand_size (bytemode, sizeflag);
13988 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13989 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13991 oappend (names_seg[ds_reg - es_reg]);
13995 print_operand_value (scratchbuf, 1, off);
13996 oappend (scratchbuf);
14000 ptr_reg (int code, int sizeflag)
14004 *obufp++ = open_char;
14005 used_prefixes |= (prefixes & PREFIX_ADDR);
14006 if (address_mode == mode_64bit)
14008 if (!(sizeflag & AFLAG))
14009 s = names32[code - eAX_reg];
14011 s = names64[code - eAX_reg];
14013 else if (sizeflag & AFLAG)
14014 s = names32[code - eAX_reg];
14016 s = names16[code - eAX_reg];
14018 *obufp++ = close_char;
14023 OP_ESreg (int code, int sizeflag)
14029 case 0x6d: /* insw/insl */
14030 intel_operand_size (z_mode, sizeflag);
14032 case 0xa5: /* movsw/movsl/movsq */
14033 case 0xa7: /* cmpsw/cmpsl/cmpsq */
14034 case 0xab: /* stosw/stosl */
14035 case 0xaf: /* scasw/scasl */
14036 intel_operand_size (v_mode, sizeflag);
14039 intel_operand_size (b_mode, sizeflag);
14042 oappend ("%es:" + intel_syntax);
14043 ptr_reg (code, sizeflag);
14047 OP_DSreg (int code, int sizeflag)
14053 case 0x6f: /* outsw/outsl */
14054 intel_operand_size (z_mode, sizeflag);
14056 case 0xa5: /* movsw/movsl/movsq */
14057 case 0xa7: /* cmpsw/cmpsl/cmpsq */
14058 case 0xad: /* lodsw/lodsl/lodsq */
14059 intel_operand_size (v_mode, sizeflag);
14062 intel_operand_size (b_mode, sizeflag);
14071 | PREFIX_GS)) == 0)
14072 prefixes |= PREFIX_DS;
14074 ptr_reg (code, sizeflag);
14078 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14086 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
14088 all_prefixes[last_lock_prefix] = 0;
14089 used_prefixes |= PREFIX_LOCK;
14094 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
14095 oappend (scratchbuf + intel_syntax);
14099 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14108 sprintf (scratchbuf, "db%d", modrm.reg + add);
14110 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
14111 oappend (scratchbuf);
14115 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14117 sprintf (scratchbuf, "%%tr%d", modrm.reg);
14118 oappend (scratchbuf + intel_syntax);
14122 OP_R (int bytemode, int sizeflag)
14124 if (modrm.mod == 3)
14125 OP_E (bytemode, sizeflag);
14131 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14133 int reg = modrm.reg;
14134 const char **names;
14136 used_prefixes |= (prefixes & PREFIX_DATA);
14137 if (prefixes & PREFIX_DATA)
14146 oappend (names[reg]);
14150 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14152 int reg = modrm.reg;
14153 const char **names;
14159 && bytemode != xmm_mode
14160 && bytemode != scalar_mode)
14162 switch (vex.length)
14168 if (vex.w || bytemode != vex_vsib_q_w_dq_mode)
14179 oappend (names[reg]);
14183 OP_EM (int bytemode, int sizeflag)
14186 const char **names;
14188 if (modrm.mod != 3)
14191 && (bytemode == v_mode || bytemode == v_swap_mode))
14193 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14194 used_prefixes |= (prefixes & PREFIX_DATA);
14196 OP_E (bytemode, sizeflag);
14200 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
14203 /* Skip mod/rm byte. */
14206 used_prefixes |= (prefixes & PREFIX_DATA);
14208 if (prefixes & PREFIX_DATA)
14217 oappend (names[reg]);
14220 /* cvt* are the only instructions in sse2 which have
14221 both SSE and MMX operands and also have 0x66 prefix
14222 in their opcode. 0x66 was originally used to differentiate
14223 between SSE and MMX instruction(operands). So we have to handle the
14224 cvt* separately using OP_EMC and OP_MXC */
14226 OP_EMC (int bytemode, int sizeflag)
14228 if (modrm.mod != 3)
14230 if (intel_syntax && bytemode == v_mode)
14232 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14233 used_prefixes |= (prefixes & PREFIX_DATA);
14235 OP_E (bytemode, sizeflag);
14239 /* Skip mod/rm byte. */
14242 used_prefixes |= (prefixes & PREFIX_DATA);
14243 oappend (names_mm[modrm.rm]);
14247 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14249 used_prefixes |= (prefixes & PREFIX_DATA);
14250 oappend (names_mm[modrm.reg]);
14254 OP_EX (int bytemode, int sizeflag)
14257 const char **names;
14259 /* Skip mod/rm byte. */
14263 if (modrm.mod != 3)
14265 OP_E_memory (bytemode, sizeflag);
14274 if ((sizeflag & SUFFIX_ALWAYS)
14275 && (bytemode == x_swap_mode
14276 || bytemode == d_swap_mode
14277 || bytemode == d_scalar_swap_mode
14278 || bytemode == q_swap_mode
14279 || bytemode == q_scalar_swap_mode))
14283 && bytemode != xmm_mode
14284 && bytemode != xmmdw_mode
14285 && bytemode != xmmqd_mode
14286 && bytemode != xmm_mb_mode
14287 && bytemode != xmm_mw_mode
14288 && bytemode != xmm_md_mode
14289 && bytemode != xmm_mq_mode
14290 && bytemode != xmmq_mode
14291 && bytemode != d_scalar_mode
14292 && bytemode != d_scalar_swap_mode
14293 && bytemode != q_scalar_mode
14294 && bytemode != q_scalar_swap_mode
14295 && bytemode != vex_scalar_w_dq_mode)
14297 switch (vex.length)
14311 oappend (names[reg]);
14315 OP_MS (int bytemode, int sizeflag)
14317 if (modrm.mod == 3)
14318 OP_EM (bytemode, sizeflag);
14324 OP_XS (int bytemode, int sizeflag)
14326 if (modrm.mod == 3)
14327 OP_EX (bytemode, sizeflag);
14333 OP_M (int bytemode, int sizeflag)
14335 if (modrm.mod == 3)
14336 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14339 OP_E (bytemode, sizeflag);
14343 OP_0f07 (int bytemode, int sizeflag)
14345 if (modrm.mod != 3 || modrm.rm != 0)
14348 OP_E (bytemode, sizeflag);
14351 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
14352 32bit mode and "xchg %rax,%rax" in 64bit mode. */
14355 NOP_Fixup1 (int bytemode, int sizeflag)
14357 if ((prefixes & PREFIX_DATA) != 0
14360 && address_mode == mode_64bit))
14361 OP_REG (bytemode, sizeflag);
14363 strcpy (obuf, "nop");
14367 NOP_Fixup2 (int bytemode, int sizeflag)
14369 if ((prefixes & PREFIX_DATA) != 0
14372 && address_mode == mode_64bit))
14373 OP_IMREG (bytemode, sizeflag);
14376 static const char *const Suffix3DNow[] = {
14377 /* 00 */ NULL, NULL, NULL, NULL,
14378 /* 04 */ NULL, NULL, NULL, NULL,
14379 /* 08 */ NULL, NULL, NULL, NULL,
14380 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
14381 /* 10 */ NULL, NULL, NULL, NULL,
14382 /* 14 */ NULL, NULL, NULL, NULL,
14383 /* 18 */ NULL, NULL, NULL, NULL,
14384 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
14385 /* 20 */ NULL, NULL, NULL, NULL,
14386 /* 24 */ NULL, NULL, NULL, NULL,
14387 /* 28 */ NULL, NULL, NULL, NULL,
14388 /* 2C */ NULL, NULL, NULL, NULL,
14389 /* 30 */ NULL, NULL, NULL, NULL,
14390 /* 34 */ NULL, NULL, NULL, NULL,
14391 /* 38 */ NULL, NULL, NULL, NULL,
14392 /* 3C */ NULL, NULL, NULL, NULL,
14393 /* 40 */ NULL, NULL, NULL, NULL,
14394 /* 44 */ NULL, NULL, NULL, NULL,
14395 /* 48 */ NULL, NULL, NULL, NULL,
14396 /* 4C */ NULL, NULL, NULL, NULL,
14397 /* 50 */ NULL, NULL, NULL, NULL,
14398 /* 54 */ NULL, NULL, NULL, NULL,
14399 /* 58 */ NULL, NULL, NULL, NULL,
14400 /* 5C */ NULL, NULL, NULL, NULL,
14401 /* 60 */ NULL, NULL, NULL, NULL,
14402 /* 64 */ NULL, NULL, NULL, NULL,
14403 /* 68 */ NULL, NULL, NULL, NULL,
14404 /* 6C */ NULL, NULL, NULL, NULL,
14405 /* 70 */ NULL, NULL, NULL, NULL,
14406 /* 74 */ NULL, NULL, NULL, NULL,
14407 /* 78 */ NULL, NULL, NULL, NULL,
14408 /* 7C */ NULL, NULL, NULL, NULL,
14409 /* 80 */ NULL, NULL, NULL, NULL,
14410 /* 84 */ NULL, NULL, NULL, NULL,
14411 /* 88 */ NULL, NULL, "pfnacc", NULL,
14412 /* 8C */ NULL, NULL, "pfpnacc", NULL,
14413 /* 90 */ "pfcmpge", NULL, NULL, NULL,
14414 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
14415 /* 98 */ NULL, NULL, "pfsub", NULL,
14416 /* 9C */ NULL, NULL, "pfadd", NULL,
14417 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
14418 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
14419 /* A8 */ NULL, NULL, "pfsubr", NULL,
14420 /* AC */ NULL, NULL, "pfacc", NULL,
14421 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
14422 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
14423 /* B8 */ NULL, NULL, NULL, "pswapd",
14424 /* BC */ NULL, NULL, NULL, "pavgusb",
14425 /* C0 */ NULL, NULL, NULL, NULL,
14426 /* C4 */ NULL, NULL, NULL, NULL,
14427 /* C8 */ NULL, NULL, NULL, NULL,
14428 /* CC */ NULL, NULL, NULL, NULL,
14429 /* D0 */ NULL, NULL, NULL, NULL,
14430 /* D4 */ NULL, NULL, NULL, NULL,
14431 /* D8 */ NULL, NULL, NULL, NULL,
14432 /* DC */ NULL, NULL, NULL, NULL,
14433 /* E0 */ NULL, NULL, NULL, NULL,
14434 /* E4 */ NULL, NULL, NULL, NULL,
14435 /* E8 */ NULL, NULL, NULL, NULL,
14436 /* EC */ NULL, NULL, NULL, NULL,
14437 /* F0 */ NULL, NULL, NULL, NULL,
14438 /* F4 */ NULL, NULL, NULL, NULL,
14439 /* F8 */ NULL, NULL, NULL, NULL,
14440 /* FC */ NULL, NULL, NULL, NULL,
14444 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14446 const char *mnemonic;
14448 FETCH_DATA (the_info, codep + 1);
14449 /* AMD 3DNow! instructions are specified by an opcode suffix in the
14450 place where an 8-bit immediate would normally go. ie. the last
14451 byte of the instruction. */
14452 obufp = mnemonicendp;
14453 mnemonic = Suffix3DNow[*codep++ & 0xff];
14455 oappend (mnemonic);
14458 /* Since a variable sized modrm/sib chunk is between the start
14459 of the opcode (0x0f0f) and the opcode suffix, we need to do
14460 all the modrm processing first, and don't know until now that
14461 we have a bad opcode. This necessitates some cleaning up. */
14462 op_out[0][0] = '\0';
14463 op_out[1][0] = '\0';
14466 mnemonicendp = obufp;
14469 static struct op simd_cmp_op[] =
14471 { STRING_COMMA_LEN ("eq") },
14472 { STRING_COMMA_LEN ("lt") },
14473 { STRING_COMMA_LEN ("le") },
14474 { STRING_COMMA_LEN ("unord") },
14475 { STRING_COMMA_LEN ("neq") },
14476 { STRING_COMMA_LEN ("nlt") },
14477 { STRING_COMMA_LEN ("nle") },
14478 { STRING_COMMA_LEN ("ord") }
14482 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14484 unsigned int cmp_type;
14486 FETCH_DATA (the_info, codep + 1);
14487 cmp_type = *codep++ & 0xff;
14488 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
14491 char *p = mnemonicendp - 2;
14495 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14496 mnemonicendp += simd_cmp_op[cmp_type].len;
14500 /* We have a reserved extension byte. Output it directly. */
14501 scratchbuf[0] = '$';
14502 print_operand_value (scratchbuf + 1, 1, cmp_type);
14503 oappend (scratchbuf + intel_syntax);
14504 scratchbuf[0] = '\0';
14509 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
14510 int sizeflag ATTRIBUTE_UNUSED)
14512 /* mwait %eax,%ecx */
14515 const char **names = (address_mode == mode_64bit
14516 ? names64 : names32);
14517 strcpy (op_out[0], names[0]);
14518 strcpy (op_out[1], names[1]);
14519 two_source_ops = 1;
14521 /* Skip mod/rm byte. */
14527 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
14528 int sizeflag ATTRIBUTE_UNUSED)
14530 /* monitor %eax,%ecx,%edx" */
14533 const char **op1_names;
14534 const char **names = (address_mode == mode_64bit
14535 ? names64 : names32);
14537 if (!(prefixes & PREFIX_ADDR))
14538 op1_names = (address_mode == mode_16bit
14539 ? names16 : names);
14542 /* Remove "addr16/addr32". */
14543 all_prefixes[last_addr_prefix] = 0;
14544 op1_names = (address_mode != mode_32bit
14545 ? names32 : names16);
14546 used_prefixes |= PREFIX_ADDR;
14548 strcpy (op_out[0], op1_names[0]);
14549 strcpy (op_out[1], names[1]);
14550 strcpy (op_out[2], names[2]);
14551 two_source_ops = 1;
14553 /* Skip mod/rm byte. */
14561 /* Throw away prefixes and 1st. opcode byte. */
14562 codep = insn_codep + 1;
14567 REP_Fixup (int bytemode, int sizeflag)
14569 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14571 if (prefixes & PREFIX_REPZ)
14572 all_prefixes[last_repz_prefix] = REP_PREFIX;
14579 OP_IMREG (bytemode, sizeflag);
14582 OP_ESreg (bytemode, sizeflag);
14585 OP_DSreg (bytemode, sizeflag);
14593 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
14597 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14599 if (prefixes & PREFIX_REPNZ)
14600 all_prefixes[last_repnz_prefix] = BND_PREFIX;
14603 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
14604 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
14608 HLE_Fixup1 (int bytemode, int sizeflag)
14611 && (prefixes & PREFIX_LOCK) != 0)
14613 if (prefixes & PREFIX_REPZ)
14614 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14615 if (prefixes & PREFIX_REPNZ)
14616 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
14619 OP_E (bytemode, sizeflag);
14622 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
14623 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
14627 HLE_Fixup2 (int bytemode, int sizeflag)
14629 if (modrm.mod != 3)
14631 if (prefixes & PREFIX_REPZ)
14632 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14633 if (prefixes & PREFIX_REPNZ)
14634 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
14637 OP_E (bytemode, sizeflag);
14640 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
14641 "xrelease" for memory operand. No check for LOCK prefix. */
14644 HLE_Fixup3 (int bytemode, int sizeflag)
14647 && last_repz_prefix > last_repnz_prefix
14648 && (prefixes & PREFIX_REPZ) != 0)
14649 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14651 OP_E (bytemode, sizeflag);
14655 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
14660 /* Change cmpxchg8b to cmpxchg16b. */
14661 char *p = mnemonicendp - 2;
14662 mnemonicendp = stpcpy (p, "16b");
14665 else if ((prefixes & PREFIX_LOCK) != 0)
14667 if (prefixes & PREFIX_REPZ)
14668 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14669 if (prefixes & PREFIX_REPNZ)
14670 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
14673 OP_M (bytemode, sizeflag);
14677 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
14679 const char **names;
14683 switch (vex.length)
14697 oappend (names[reg]);
14701 CRC32_Fixup (int bytemode, int sizeflag)
14703 /* Add proper suffix to "crc32". */
14704 char *p = mnemonicendp;
14723 if (sizeflag & DFLAG)
14727 used_prefixes |= (prefixes & PREFIX_DATA);
14731 oappend (INTERNAL_DISASSEMBLER_ERROR);
14738 if (modrm.mod == 3)
14742 /* Skip mod/rm byte. */
14747 add = (rex & REX_B) ? 8 : 0;
14748 if (bytemode == b_mode)
14752 oappend (names8rex[modrm.rm + add]);
14754 oappend (names8[modrm.rm + add]);
14760 oappend (names64[modrm.rm + add]);
14761 else if ((prefixes & PREFIX_DATA))
14762 oappend (names16[modrm.rm + add]);
14764 oappend (names32[modrm.rm + add]);
14768 OP_E (bytemode, sizeflag);
14772 FXSAVE_Fixup (int bytemode, int sizeflag)
14774 /* Add proper suffix to "fxsave" and "fxrstor". */
14778 char *p = mnemonicendp;
14784 OP_M (bytemode, sizeflag);
14787 /* Display the destination register operand for instructions with
14791 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14794 const char **names;
14802 reg = vex.register_specifier;
14803 if (bytemode == vex_scalar_mode)
14805 oappend (names_xmm[reg]);
14809 switch (vex.length)
14816 case vex_vsib_q_w_dq_mode:
14837 case vex_vsib_q_w_dq_mode:
14838 names = vex.w ? names_ymm : names_xmm;
14849 oappend (names[reg]);
14852 /* Get the VEX immediate byte without moving codep. */
14854 static unsigned char
14855 get_vex_imm8 (int sizeflag, int opnum)
14857 int bytes_before_imm = 0;
14859 if (modrm.mod != 3)
14861 /* There are SIB/displacement bytes. */
14862 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14864 /* 32/64 bit address mode */
14865 int base = modrm.rm;
14867 /* Check SIB byte. */
14870 FETCH_DATA (the_info, codep + 1);
14872 /* When decoding the third source, don't increase
14873 bytes_before_imm as this has already been incremented
14874 by one in OP_E_memory while decoding the second
14877 bytes_before_imm++;
14880 /* Don't increase bytes_before_imm when decoding the third source,
14881 it has already been incremented by OP_E_memory while decoding
14882 the second source operand. */
14888 /* When modrm.rm == 5 or modrm.rm == 4 and base in
14889 SIB == 5, there is a 4 byte displacement. */
14891 /* No displacement. */
14894 /* 4 byte displacement. */
14895 bytes_before_imm += 4;
14898 /* 1 byte displacement. */
14899 bytes_before_imm++;
14906 /* 16 bit address mode */
14907 /* Don't increase bytes_before_imm when decoding the third source,
14908 it has already been incremented by OP_E_memory while decoding
14909 the second source operand. */
14915 /* When modrm.rm == 6, there is a 2 byte displacement. */
14917 /* No displacement. */
14920 /* 2 byte displacement. */
14921 bytes_before_imm += 2;
14924 /* 1 byte displacement: when decoding the third source,
14925 don't increase bytes_before_imm as this has already
14926 been incremented by one in OP_E_memory while decoding
14927 the second source operand. */
14929 bytes_before_imm++;
14937 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
14938 return codep [bytes_before_imm];
14942 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
14944 const char **names;
14946 if (reg == -1 && modrm.mod != 3)
14948 OP_E_memory (bytemode, sizeflag);
14960 else if (reg > 7 && address_mode != mode_64bit)
14964 switch (vex.length)
14975 oappend (names[reg]);
14979 OP_EX_VexImmW (int bytemode, int sizeflag)
14982 static unsigned char vex_imm8;
14984 if (vex_w_done == 0)
14988 /* Skip mod/rm byte. */
14992 vex_imm8 = get_vex_imm8 (sizeflag, 0);
14995 reg = vex_imm8 >> 4;
14997 OP_EX_VexReg (bytemode, sizeflag, reg);
14999 else if (vex_w_done == 1)
15004 reg = vex_imm8 >> 4;
15006 OP_EX_VexReg (bytemode, sizeflag, reg);
15010 /* Output the imm8 directly. */
15011 scratchbuf[0] = '$';
15012 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
15013 oappend (scratchbuf + intel_syntax);
15014 scratchbuf[0] = '\0';
15020 OP_Vex_2src (int bytemode, int sizeflag)
15022 if (modrm.mod == 3)
15024 int reg = modrm.rm;
15028 oappend (names_xmm[reg]);
15033 && (bytemode == v_mode || bytemode == v_swap_mode))
15035 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15036 used_prefixes |= (prefixes & PREFIX_DATA);
15038 OP_E (bytemode, sizeflag);
15043 OP_Vex_2src_1 (int bytemode, int sizeflag)
15045 if (modrm.mod == 3)
15047 /* Skip mod/rm byte. */
15053 oappend (names_xmm[vex.register_specifier]);
15055 OP_Vex_2src (bytemode, sizeflag);
15059 OP_Vex_2src_2 (int bytemode, int sizeflag)
15062 OP_Vex_2src (bytemode, sizeflag);
15064 oappend (names_xmm[vex.register_specifier]);
15068 OP_EX_VexW (int bytemode, int sizeflag)
15076 /* Skip mod/rm byte. */
15081 reg = get_vex_imm8 (sizeflag, 0) >> 4;
15086 reg = get_vex_imm8 (sizeflag, 1) >> 4;
15089 OP_EX_VexReg (bytemode, sizeflag, reg);
15093 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
15094 int sizeflag ATTRIBUTE_UNUSED)
15096 /* Skip the immediate byte and check for invalid bits. */
15097 FETCH_DATA (the_info, codep + 1);
15098 if (*codep++ & 0xf)
15103 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15106 const char **names;
15108 FETCH_DATA (the_info, codep + 1);
15111 if (bytemode != x_mode)
15118 if (reg > 7 && address_mode != mode_64bit)
15121 switch (vex.length)
15132 oappend (names[reg]);
15136 OP_XMM_VexW (int bytemode, int sizeflag)
15138 /* Turn off the REX.W bit since it is used for swapping operands
15141 OP_XMM (bytemode, sizeflag);
15145 OP_EX_Vex (int bytemode, int sizeflag)
15147 if (modrm.mod != 3)
15149 if (vex.register_specifier != 0)
15153 OP_EX (bytemode, sizeflag);
15157 OP_XMM_Vex (int bytemode, int sizeflag)
15159 if (modrm.mod != 3)
15161 if (vex.register_specifier != 0)
15165 OP_XMM (bytemode, sizeflag);
15169 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15171 switch (vex.length)
15174 mnemonicendp = stpcpy (obuf, "vzeroupper");
15177 mnemonicendp = stpcpy (obuf, "vzeroall");
15184 static struct op vex_cmp_op[] =
15186 { STRING_COMMA_LEN ("eq") },
15187 { STRING_COMMA_LEN ("lt") },
15188 { STRING_COMMA_LEN ("le") },
15189 { STRING_COMMA_LEN ("unord") },
15190 { STRING_COMMA_LEN ("neq") },
15191 { STRING_COMMA_LEN ("nlt") },
15192 { STRING_COMMA_LEN ("nle") },
15193 { STRING_COMMA_LEN ("ord") },
15194 { STRING_COMMA_LEN ("eq_uq") },
15195 { STRING_COMMA_LEN ("nge") },
15196 { STRING_COMMA_LEN ("ngt") },
15197 { STRING_COMMA_LEN ("false") },
15198 { STRING_COMMA_LEN ("neq_oq") },
15199 { STRING_COMMA_LEN ("ge") },
15200 { STRING_COMMA_LEN ("gt") },
15201 { STRING_COMMA_LEN ("true") },
15202 { STRING_COMMA_LEN ("eq_os") },
15203 { STRING_COMMA_LEN ("lt_oq") },
15204 { STRING_COMMA_LEN ("le_oq") },
15205 { STRING_COMMA_LEN ("unord_s") },
15206 { STRING_COMMA_LEN ("neq_us") },
15207 { STRING_COMMA_LEN ("nlt_uq") },
15208 { STRING_COMMA_LEN ("nle_uq") },
15209 { STRING_COMMA_LEN ("ord_s") },
15210 { STRING_COMMA_LEN ("eq_us") },
15211 { STRING_COMMA_LEN ("nge_uq") },
15212 { STRING_COMMA_LEN ("ngt_uq") },
15213 { STRING_COMMA_LEN ("false_os") },
15214 { STRING_COMMA_LEN ("neq_os") },
15215 { STRING_COMMA_LEN ("ge_oq") },
15216 { STRING_COMMA_LEN ("gt_oq") },
15217 { STRING_COMMA_LEN ("true_us") },
15221 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15223 unsigned int cmp_type;
15225 FETCH_DATA (the_info, codep + 1);
15226 cmp_type = *codep++ & 0xff;
15227 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
15230 char *p = mnemonicendp - 2;
15234 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
15235 mnemonicendp += vex_cmp_op[cmp_type].len;
15239 /* We have a reserved extension byte. Output it directly. */
15240 scratchbuf[0] = '$';
15241 print_operand_value (scratchbuf + 1, 1, cmp_type);
15242 oappend (scratchbuf + intel_syntax);
15243 scratchbuf[0] = '\0';
15247 static const struct op pclmul_op[] =
15249 { STRING_COMMA_LEN ("lql") },
15250 { STRING_COMMA_LEN ("hql") },
15251 { STRING_COMMA_LEN ("lqh") },
15252 { STRING_COMMA_LEN ("hqh") }
15256 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
15257 int sizeflag ATTRIBUTE_UNUSED)
15259 unsigned int pclmul_type;
15261 FETCH_DATA (the_info, codep + 1);
15262 pclmul_type = *codep++ & 0xff;
15263 switch (pclmul_type)
15274 if (pclmul_type < ARRAY_SIZE (pclmul_op))
15277 char *p = mnemonicendp - 3;
15282 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
15283 mnemonicendp += pclmul_op[pclmul_type].len;
15287 /* We have a reserved extension byte. Output it directly. */
15288 scratchbuf[0] = '$';
15289 print_operand_value (scratchbuf + 1, 1, pclmul_type);
15290 oappend (scratchbuf + intel_syntax);
15291 scratchbuf[0] = '\0';
15296 MOVBE_Fixup (int bytemode, int sizeflag)
15298 /* Add proper suffix to "movbe". */
15299 char *p = mnemonicendp;
15308 if (sizeflag & SUFFIX_ALWAYS)
15314 if (sizeflag & DFLAG)
15318 used_prefixes |= (prefixes & PREFIX_DATA);
15323 oappend (INTERNAL_DISASSEMBLER_ERROR);
15330 OP_M (bytemode, sizeflag);
15334 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15337 const char **names;
15339 /* Skip mod/rm byte. */
15353 oappend (names[reg]);
15357 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15359 const char **names;
15366 oappend (names[vex.register_specifier]);