1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2016 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma, disassemble_info *);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma get64 (void);
58 static bfd_signed_vma get32 (void);
59 static bfd_signed_vma get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void OP_Mwaitx (int, int);
106 static void NOP_Fixup1 (int, int);
107 static void NOP_Fixup2 (int, int);
108 static void OP_3DNowSuffix (int, int);
109 static void CMP_Fixup (int, int);
110 static void BadOp (void);
111 static void REP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void OP_LWPCB_E (int, int);
121 static void OP_LWP_E (int, int);
122 static void OP_Vex_2src_1 (int, int);
123 static void OP_Vex_2src_2 (int, int);
125 static void MOVBE_Fixup (int, int);
127 static void OP_Mask (int, int);
130 /* Points to first byte not fetched. */
131 bfd_byte *max_fetched;
132 bfd_byte the_buffer[MAX_MNEM_SIZE];
135 OPCODES_SIGJMP_BUF bailout;
145 enum address_mode address_mode;
147 /* Flags for the prefixes for the current instruction. See below. */
150 /* REX prefix the current instruction. See below. */
152 /* Bits of REX we've already used. */
154 /* REX bits in original REX prefix ignored. */
155 static int rex_ignored;
156 /* Mark parts used in the REX prefix. When we are testing for
157 empty prefix (for 8bit register REX extension), just mask it
158 out. Otherwise test for REX bit is excuse for existence of REX
159 only in case value is nonzero. */
160 #define USED_REX(value) \
165 rex_used |= (value) | REX_OPCODE; \
168 rex_used |= REX_OPCODE; \
171 /* Flags for prefixes which we somehow handled when printing the
172 current instruction. */
173 static int used_prefixes;
175 /* Flags stored in PREFIXES. */
176 #define PREFIX_REPZ 1
177 #define PREFIX_REPNZ 2
178 #define PREFIX_LOCK 4
180 #define PREFIX_SS 0x10
181 #define PREFIX_DS 0x20
182 #define PREFIX_ES 0x40
183 #define PREFIX_FS 0x80
184 #define PREFIX_GS 0x100
185 #define PREFIX_DATA 0x200
186 #define PREFIX_ADDR 0x400
187 #define PREFIX_FWAIT 0x800
189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
190 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
192 #define FETCH_DATA(info, addr) \
193 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
194 ? 1 : fetch_data ((info), (addr)))
197 fetch_data (struct disassemble_info *info, bfd_byte *addr)
200 struct dis_private *priv = (struct dis_private *) info->private_data;
201 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
203 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
204 status = (*info->read_memory_func) (start,
206 addr - priv->max_fetched,
212 /* If we did manage to read at least one byte, then
213 print_insn_i386 will do something sensible. Otherwise, print
214 an error. We do that here because this is where we know
216 if (priv->max_fetched == priv->the_buffer)
217 (*info->memory_error_func) (status, start, info);
218 OPCODES_SIGLONGJMP (priv->bailout, 1);
221 priv->max_fetched = addr;
225 /* Possible values for prefix requirement. */
226 #define PREFIX_IGNORED_SHIFT 16
227 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
228 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
233 /* Opcode prefixes. */
234 #define PREFIX_OPCODE (PREFIX_REPZ \
238 /* Prefixes ignored. */
239 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
240 | PREFIX_IGNORED_REPNZ \
241 | PREFIX_IGNORED_DATA)
243 #define XX { NULL, 0 }
244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
246 #define Eb { OP_E, b_mode }
247 #define Ebnd { OP_E, bnd_mode }
248 #define EbS { OP_E, b_swap_mode }
249 #define Ev { OP_E, v_mode }
250 #define Ev_bnd { OP_E, v_bnd_mode }
251 #define EvS { OP_E, v_swap_mode }
252 #define Ed { OP_E, d_mode }
253 #define Edq { OP_E, dq_mode }
254 #define Edqw { OP_E, dqw_mode }
255 #define EdqwS { OP_E, dqw_swap_mode }
256 #define Edqb { OP_E, dqb_mode }
257 #define Edb { OP_E, db_mode }
258 #define Edw { OP_E, dw_mode }
259 #define Edqd { OP_E, dqd_mode }
260 #define Eq { OP_E, q_mode }
261 #define indirEv { OP_indirE, indir_v_mode }
262 #define indirEp { OP_indirE, f_mode }
263 #define stackEv { OP_E, stack_v_mode }
264 #define Em { OP_E, m_mode }
265 #define Ew { OP_E, w_mode }
266 #define M { OP_M, 0 } /* lea, lgdt, etc. */
267 #define Ma { OP_M, a_mode }
268 #define Mb { OP_M, b_mode }
269 #define Md { OP_M, d_mode }
270 #define Mo { OP_M, o_mode }
271 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
272 #define Mq { OP_M, q_mode }
273 #define Mx { OP_M, x_mode }
274 #define Mxmm { OP_M, xmm_mode }
275 #define Gb { OP_G, b_mode }
276 #define Gbnd { OP_G, bnd_mode }
277 #define Gv { OP_G, v_mode }
278 #define Gd { OP_G, d_mode }
279 #define Gdq { OP_G, dq_mode }
280 #define Gm { OP_G, m_mode }
281 #define Gw { OP_G, w_mode }
282 #define Rd { OP_R, d_mode }
283 #define Rdq { OP_R, dq_mode }
284 #define Rm { OP_R, m_mode }
285 #define Ib { OP_I, b_mode }
286 #define sIb { OP_sI, b_mode } /* sign extened byte */
287 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
288 #define Iv { OP_I, v_mode }
289 #define sIv { OP_sI, v_mode }
290 #define Iq { OP_I, q_mode }
291 #define Iv64 { OP_I64, v_mode }
292 #define Iw { OP_I, w_mode }
293 #define I1 { OP_I, const_1_mode }
294 #define Jb { OP_J, b_mode }
295 #define Jv { OP_J, v_mode }
296 #define Cm { OP_C, m_mode }
297 #define Dm { OP_D, m_mode }
298 #define Td { OP_T, d_mode }
299 #define Skip_MODRM { OP_Skip_MODRM, 0 }
301 #define RMeAX { OP_REG, eAX_reg }
302 #define RMeBX { OP_REG, eBX_reg }
303 #define RMeCX { OP_REG, eCX_reg }
304 #define RMeDX { OP_REG, eDX_reg }
305 #define RMeSP { OP_REG, eSP_reg }
306 #define RMeBP { OP_REG, eBP_reg }
307 #define RMeSI { OP_REG, eSI_reg }
308 #define RMeDI { OP_REG, eDI_reg }
309 #define RMrAX { OP_REG, rAX_reg }
310 #define RMrBX { OP_REG, rBX_reg }
311 #define RMrCX { OP_REG, rCX_reg }
312 #define RMrDX { OP_REG, rDX_reg }
313 #define RMrSP { OP_REG, rSP_reg }
314 #define RMrBP { OP_REG, rBP_reg }
315 #define RMrSI { OP_REG, rSI_reg }
316 #define RMrDI { OP_REG, rDI_reg }
317 #define RMAL { OP_REG, al_reg }
318 #define RMCL { OP_REG, cl_reg }
319 #define RMDL { OP_REG, dl_reg }
320 #define RMBL { OP_REG, bl_reg }
321 #define RMAH { OP_REG, ah_reg }
322 #define RMCH { OP_REG, ch_reg }
323 #define RMDH { OP_REG, dh_reg }
324 #define RMBH { OP_REG, bh_reg }
325 #define RMAX { OP_REG, ax_reg }
326 #define RMDX { OP_REG, dx_reg }
328 #define eAX { OP_IMREG, eAX_reg }
329 #define eBX { OP_IMREG, eBX_reg }
330 #define eCX { OP_IMREG, eCX_reg }
331 #define eDX { OP_IMREG, eDX_reg }
332 #define eSP { OP_IMREG, eSP_reg }
333 #define eBP { OP_IMREG, eBP_reg }
334 #define eSI { OP_IMREG, eSI_reg }
335 #define eDI { OP_IMREG, eDI_reg }
336 #define AL { OP_IMREG, al_reg }
337 #define CL { OP_IMREG, cl_reg }
338 #define DL { OP_IMREG, dl_reg }
339 #define BL { OP_IMREG, bl_reg }
340 #define AH { OP_IMREG, ah_reg }
341 #define CH { OP_IMREG, ch_reg }
342 #define DH { OP_IMREG, dh_reg }
343 #define BH { OP_IMREG, bh_reg }
344 #define AX { OP_IMREG, ax_reg }
345 #define DX { OP_IMREG, dx_reg }
346 #define zAX { OP_IMREG, z_mode_ax_reg }
347 #define indirDX { OP_IMREG, indir_dx_reg }
349 #define Sw { OP_SEG, w_mode }
350 #define Sv { OP_SEG, v_mode }
351 #define Ap { OP_DIR, 0 }
352 #define Ob { OP_OFF64, b_mode }
353 #define Ov { OP_OFF64, v_mode }
354 #define Xb { OP_DSreg, eSI_reg }
355 #define Xv { OP_DSreg, eSI_reg }
356 #define Xz { OP_DSreg, eSI_reg }
357 #define Yb { OP_ESreg, eDI_reg }
358 #define Yv { OP_ESreg, eDI_reg }
359 #define DSBX { OP_DSreg, eBX_reg }
361 #define es { OP_REG, es_reg }
362 #define ss { OP_REG, ss_reg }
363 #define cs { OP_REG, cs_reg }
364 #define ds { OP_REG, ds_reg }
365 #define fs { OP_REG, fs_reg }
366 #define gs { OP_REG, gs_reg }
368 #define MX { OP_MMX, 0 }
369 #define XM { OP_XMM, 0 }
370 #define XMScalar { OP_XMM, scalar_mode }
371 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
372 #define XMM { OP_XMM, xmm_mode }
373 #define XMxmmq { OP_XMM, xmmq_mode }
374 #define EM { OP_EM, v_mode }
375 #define EMS { OP_EM, v_swap_mode }
376 #define EMd { OP_EM, d_mode }
377 #define EMx { OP_EM, x_mode }
378 #define EXw { OP_EX, w_mode }
379 #define EXd { OP_EX, d_mode }
380 #define EXdScalar { OP_EX, d_scalar_mode }
381 #define EXdS { OP_EX, d_swap_mode }
382 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
383 #define EXq { OP_EX, q_mode }
384 #define EXqScalar { OP_EX, q_scalar_mode }
385 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
386 #define EXqS { OP_EX, q_swap_mode }
387 #define EXx { OP_EX, x_mode }
388 #define EXxS { OP_EX, x_swap_mode }
389 #define EXxmm { OP_EX, xmm_mode }
390 #define EXymm { OP_EX, ymm_mode }
391 #define EXxmmq { OP_EX, xmmq_mode }
392 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
393 #define EXxmm_mb { OP_EX, xmm_mb_mode }
394 #define EXxmm_mw { OP_EX, xmm_mw_mode }
395 #define EXxmm_md { OP_EX, xmm_md_mode }
396 #define EXxmm_mq { OP_EX, xmm_mq_mode }
397 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
398 #define EXxmmdw { OP_EX, xmmdw_mode }
399 #define EXxmmqd { OP_EX, xmmqd_mode }
400 #define EXymmq { OP_EX, ymmq_mode }
401 #define EXVexWdq { OP_EX, vex_w_dq_mode }
402 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
403 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
404 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
405 #define MS { OP_MS, v_mode }
406 #define XS { OP_XS, v_mode }
407 #define EMCq { OP_EMC, q_mode }
408 #define MXC { OP_MXC, 0 }
409 #define OPSUF { OP_3DNowSuffix, 0 }
410 #define CMP { CMP_Fixup, 0 }
411 #define XMM0 { XMM_Fixup, 0 }
412 #define FXSAVE { FXSAVE_Fixup, 0 }
413 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
414 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
416 #define Vex { OP_VEX, vex_mode }
417 #define VexScalar { OP_VEX, vex_scalar_mode }
418 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
419 #define Vex128 { OP_VEX, vex128_mode }
420 #define Vex256 { OP_VEX, vex256_mode }
421 #define VexGdq { OP_VEX, dq_mode }
422 #define VexI4 { VEXI4_Fixup, 0}
423 #define EXdVex { OP_EX_Vex, d_mode }
424 #define EXdVexS { OP_EX_Vex, d_swap_mode }
425 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
426 #define EXqVex { OP_EX_Vex, q_mode }
427 #define EXqVexS { OP_EX_Vex, q_swap_mode }
428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
429 #define EXVexW { OP_EX_VexW, x_mode }
430 #define EXdVexW { OP_EX_VexW, d_mode }
431 #define EXqVexW { OP_EX_VexW, q_mode }
432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
433 #define XMVex { OP_XMM_Vex, 0 }
434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
435 #define XMVexW { OP_XMM_VexW, 0 }
436 #define XMVexI4 { OP_REG_VexI4, x_mode }
437 #define PCLMUL { PCLMUL_Fixup, 0 }
438 #define VZERO { VZERO_Fixup, 0 }
439 #define VCMP { VCMP_Fixup, 0 }
440 #define VPCMP { VPCMP_Fixup, 0 }
442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
445 #define XMask { OP_Mask, mask_mode }
446 #define MaskG { OP_G, mask_mode }
447 #define MaskE { OP_E, mask_mode }
448 #define MaskBDE { OP_E, mask_bd_mode }
449 #define MaskR { OP_R, mask_mode }
450 #define MaskVex { OP_VEX, mask_mode }
452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
457 /* Used handle "rep" prefix for string instructions. */
458 #define Xbr { REP_Fixup, eSI_reg }
459 #define Xvr { REP_Fixup, eSI_reg }
460 #define Ybr { REP_Fixup, eDI_reg }
461 #define Yvr { REP_Fixup, eDI_reg }
462 #define Yzr { REP_Fixup, eDI_reg }
463 #define indirDXr { REP_Fixup, indir_dx_reg }
464 #define ALr { REP_Fixup, al_reg }
465 #define eAXr { REP_Fixup, eAX_reg }
467 /* Used handle HLE prefix for lockable instructions. */
468 #define Ebh1 { HLE_Fixup1, b_mode }
469 #define Evh1 { HLE_Fixup1, v_mode }
470 #define Ebh2 { HLE_Fixup2, b_mode }
471 #define Evh2 { HLE_Fixup2, v_mode }
472 #define Ebh3 { HLE_Fixup3, b_mode }
473 #define Evh3 { HLE_Fixup3, v_mode }
475 #define BND { BND_Fixup, 0 }
477 #define cond_jump_flag { NULL, cond_jump_mode }
478 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
480 /* bits in sizeflag */
481 #define SUFFIX_ALWAYS 4
489 /* byte operand with operand swapped */
491 /* byte operand, sign extend like 'T' suffix */
493 /* operand size depends on prefixes */
495 /* operand size depends on prefixes with operand swapped */
499 /* double word operand */
501 /* double word operand with operand swapped */
503 /* quad word operand */
505 /* quad word operand with operand swapped */
507 /* ten-byte operand */
509 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
510 broadcast enabled. */
512 /* Similar to x_mode, but with different EVEX mem shifts. */
514 /* Similar to x_mode, but with disabled broadcast. */
516 /* Similar to x_mode, but with operands swapped and disabled broadcast
519 /* 16-byte XMM operand */
521 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
522 memory operand (depending on vector length). Broadcast isn't
525 /* Same as xmmq_mode, but broadcast is allowed. */
526 evex_half_bcst_xmmq_mode,
527 /* XMM register or byte memory operand */
529 /* XMM register or word memory operand */
531 /* XMM register or double word memory operand */
533 /* XMM register or quad word memory operand */
535 /* XMM register or double/quad word memory operand, depending on
538 /* 16-byte XMM, word, double word or quad word operand. */
540 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
542 /* 32-byte YMM operand */
544 /* quad word, ymmword or zmmword memory operand. */
546 /* 32-byte YMM or 16-byte word operand */
548 /* d_mode in 32bit, q_mode in 64bit mode. */
550 /* pair of v_mode operands */
555 /* operand size depends on REX prefixes. */
557 /* registers like dq_mode, memory like w_mode. */
561 /* 4- or 6-byte pointer operand */
564 /* v_mode for indirect branch opcodes. */
566 /* v_mode for stack-related opcodes. */
568 /* non-quad operand size depends on prefixes */
570 /* 16-byte operand */
572 /* registers like dq_mode, memory like b_mode. */
574 /* registers like d_mode, memory like b_mode. */
576 /* registers like d_mode, memory like w_mode. */
578 /* registers like dq_mode, memory like d_mode. */
580 /* normal vex mode */
582 /* 128bit vex mode */
584 /* 256bit vex mode */
586 /* operand size depends on the VEX.W bit. */
589 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
590 vex_vsib_d_w_dq_mode,
591 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
593 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
594 vex_vsib_q_w_dq_mode,
595 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
598 /* scalar, ignore vector length. */
600 /* like d_mode, ignore vector length. */
602 /* like d_swap_mode, ignore vector length. */
604 /* like q_mode, ignore vector length. */
606 /* like q_swap_mode, ignore vector length. */
608 /* like vex_mode, ignore vector length. */
610 /* like vex_w_dq_mode, ignore vector length. */
611 vex_scalar_w_dq_mode,
613 /* Static rounding. */
615 /* Supress all exceptions. */
618 /* Mask register operand. */
620 /* Mask register operand. */
687 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
689 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
690 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
691 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
692 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
693 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
694 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
695 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
696 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
697 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
698 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
699 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
700 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
701 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
702 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
703 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
821 MOD_VEX_0F12_PREFIX_0,
823 MOD_VEX_0F16_PREFIX_0,
826 MOD_VEX_W_0_0F41_P_0_LEN_1,
827 MOD_VEX_W_1_0F41_P_0_LEN_1,
828 MOD_VEX_W_0_0F41_P_2_LEN_1,
829 MOD_VEX_W_1_0F41_P_2_LEN_1,
830 MOD_VEX_W_0_0F42_P_0_LEN_1,
831 MOD_VEX_W_1_0F42_P_0_LEN_1,
832 MOD_VEX_W_0_0F42_P_2_LEN_1,
833 MOD_VEX_W_1_0F42_P_2_LEN_1,
834 MOD_VEX_W_0_0F44_P_0_LEN_1,
835 MOD_VEX_W_1_0F44_P_0_LEN_1,
836 MOD_VEX_W_0_0F44_P_2_LEN_1,
837 MOD_VEX_W_1_0F44_P_2_LEN_1,
838 MOD_VEX_W_0_0F45_P_0_LEN_1,
839 MOD_VEX_W_1_0F45_P_0_LEN_1,
840 MOD_VEX_W_0_0F45_P_2_LEN_1,
841 MOD_VEX_W_1_0F45_P_2_LEN_1,
842 MOD_VEX_W_0_0F46_P_0_LEN_1,
843 MOD_VEX_W_1_0F46_P_0_LEN_1,
844 MOD_VEX_W_0_0F46_P_2_LEN_1,
845 MOD_VEX_W_1_0F46_P_2_LEN_1,
846 MOD_VEX_W_0_0F47_P_0_LEN_1,
847 MOD_VEX_W_1_0F47_P_0_LEN_1,
848 MOD_VEX_W_0_0F47_P_2_LEN_1,
849 MOD_VEX_W_1_0F47_P_2_LEN_1,
850 MOD_VEX_W_0_0F4A_P_0_LEN_1,
851 MOD_VEX_W_1_0F4A_P_0_LEN_1,
852 MOD_VEX_W_0_0F4A_P_2_LEN_1,
853 MOD_VEX_W_1_0F4A_P_2_LEN_1,
854 MOD_VEX_W_0_0F4B_P_0_LEN_1,
855 MOD_VEX_W_1_0F4B_P_0_LEN_1,
856 MOD_VEX_W_0_0F4B_P_2_LEN_1,
868 MOD_VEX_W_0_0F91_P_0_LEN_0,
869 MOD_VEX_W_1_0F91_P_0_LEN_0,
870 MOD_VEX_W_0_0F91_P_2_LEN_0,
871 MOD_VEX_W_1_0F91_P_2_LEN_0,
872 MOD_VEX_W_0_0F92_P_0_LEN_0,
873 MOD_VEX_W_0_0F92_P_2_LEN_0,
874 MOD_VEX_W_0_0F92_P_3_LEN_0,
875 MOD_VEX_W_1_0F92_P_3_LEN_0,
876 MOD_VEX_W_0_0F93_P_0_LEN_0,
877 MOD_VEX_W_0_0F93_P_2_LEN_0,
878 MOD_VEX_W_0_0F93_P_3_LEN_0,
879 MOD_VEX_W_1_0F93_P_3_LEN_0,
880 MOD_VEX_W_0_0F98_P_0_LEN_0,
881 MOD_VEX_W_1_0F98_P_0_LEN_0,
882 MOD_VEX_W_0_0F98_P_2_LEN_0,
883 MOD_VEX_W_1_0F98_P_2_LEN_0,
884 MOD_VEX_W_0_0F99_P_0_LEN_0,
885 MOD_VEX_W_1_0F99_P_0_LEN_0,
886 MOD_VEX_W_0_0F99_P_2_LEN_0,
887 MOD_VEX_W_1_0F99_P_2_LEN_0,
890 MOD_VEX_0FD7_PREFIX_2,
891 MOD_VEX_0FE7_PREFIX_2,
892 MOD_VEX_0FF0_PREFIX_3,
893 MOD_VEX_0F381A_PREFIX_2,
894 MOD_VEX_0F382A_PREFIX_2,
895 MOD_VEX_0F382C_PREFIX_2,
896 MOD_VEX_0F382D_PREFIX_2,
897 MOD_VEX_0F382E_PREFIX_2,
898 MOD_VEX_0F382F_PREFIX_2,
899 MOD_VEX_0F385A_PREFIX_2,
900 MOD_VEX_0F388C_PREFIX_2,
901 MOD_VEX_0F388E_PREFIX_2,
902 MOD_VEX_W_0_0F3A30_P_2_LEN_0,
903 MOD_VEX_W_1_0F3A30_P_2_LEN_0,
904 MOD_VEX_W_0_0F3A31_P_2_LEN_0,
905 MOD_VEX_W_1_0F3A31_P_2_LEN_0,
906 MOD_VEX_W_0_0F3A32_P_2_LEN_0,
907 MOD_VEX_W_1_0F3A32_P_2_LEN_0,
908 MOD_VEX_W_0_0F3A33_P_2_LEN_0,
909 MOD_VEX_W_1_0F3A33_P_2_LEN_0,
911 MOD_EVEX_0F10_PREFIX_1,
912 MOD_EVEX_0F10_PREFIX_3,
913 MOD_EVEX_0F11_PREFIX_1,
914 MOD_EVEX_0F11_PREFIX_3,
915 MOD_EVEX_0F12_PREFIX_0,
916 MOD_EVEX_0F16_PREFIX_0,
917 MOD_EVEX_0F38C6_REG_1,
918 MOD_EVEX_0F38C6_REG_2,
919 MOD_EVEX_0F38C6_REG_5,
920 MOD_EVEX_0F38C6_REG_6,
921 MOD_EVEX_0F38C7_REG_1,
922 MOD_EVEX_0F38C7_REG_2,
923 MOD_EVEX_0F38C7_REG_5,
924 MOD_EVEX_0F38C7_REG_6
987 PREFIX_MOD_0_0FAE_REG_4,
988 PREFIX_MOD_3_0FAE_REG_4,
996 PREFIX_MOD_0_0FC7_REG_6,
997 PREFIX_MOD_3_0FC7_REG_6,
998 PREFIX_MOD_3_0FC7_REG_7,
1122 PREFIX_VEX_0F71_REG_2,
1123 PREFIX_VEX_0F71_REG_4,
1124 PREFIX_VEX_0F71_REG_6,
1125 PREFIX_VEX_0F72_REG_2,
1126 PREFIX_VEX_0F72_REG_4,
1127 PREFIX_VEX_0F72_REG_6,
1128 PREFIX_VEX_0F73_REG_2,
1129 PREFIX_VEX_0F73_REG_3,
1130 PREFIX_VEX_0F73_REG_6,
1131 PREFIX_VEX_0F73_REG_7,
1303 PREFIX_VEX_0F38F3_REG_1,
1304 PREFIX_VEX_0F38F3_REG_2,
1305 PREFIX_VEX_0F38F3_REG_3,
1422 PREFIX_EVEX_0F71_REG_2,
1423 PREFIX_EVEX_0F71_REG_4,
1424 PREFIX_EVEX_0F71_REG_6,
1425 PREFIX_EVEX_0F72_REG_0,
1426 PREFIX_EVEX_0F72_REG_1,
1427 PREFIX_EVEX_0F72_REG_2,
1428 PREFIX_EVEX_0F72_REG_4,
1429 PREFIX_EVEX_0F72_REG_6,
1430 PREFIX_EVEX_0F73_REG_2,
1431 PREFIX_EVEX_0F73_REG_3,
1432 PREFIX_EVEX_0F73_REG_6,
1433 PREFIX_EVEX_0F73_REG_7,
1618 PREFIX_EVEX_0F38C6_REG_1,
1619 PREFIX_EVEX_0F38C6_REG_2,
1620 PREFIX_EVEX_0F38C6_REG_5,
1621 PREFIX_EVEX_0F38C6_REG_6,
1622 PREFIX_EVEX_0F38C7_REG_1,
1623 PREFIX_EVEX_0F38C7_REG_2,
1624 PREFIX_EVEX_0F38C7_REG_5,
1625 PREFIX_EVEX_0F38C7_REG_6,
1714 THREE_BYTE_0F38 = 0,
1742 VEX_LEN_0F10_P_1 = 0,
1746 VEX_LEN_0F12_P_0_M_0,
1747 VEX_LEN_0F12_P_0_M_1,
1750 VEX_LEN_0F16_P_0_M_0,
1751 VEX_LEN_0F16_P_0_M_1,
1815 VEX_LEN_0FAE_R_2_M_0,
1816 VEX_LEN_0FAE_R_3_M_0,
1825 VEX_LEN_0F381A_P_2_M_0,
1828 VEX_LEN_0F385A_P_2_M_0,
1835 VEX_LEN_0F38F3_R_1_P_0,
1836 VEX_LEN_0F38F3_R_2_P_0,
1837 VEX_LEN_0F38F3_R_3_P_0,
1883 VEX_LEN_0FXOP_08_CC,
1884 VEX_LEN_0FXOP_08_CD,
1885 VEX_LEN_0FXOP_08_CE,
1886 VEX_LEN_0FXOP_08_CF,
1887 VEX_LEN_0FXOP_08_EC,
1888 VEX_LEN_0FXOP_08_ED,
1889 VEX_LEN_0FXOP_08_EE,
1890 VEX_LEN_0FXOP_08_EF,
1891 VEX_LEN_0FXOP_09_80,
1925 VEX_W_0F41_P_0_LEN_1,
1926 VEX_W_0F41_P_2_LEN_1,
1927 VEX_W_0F42_P_0_LEN_1,
1928 VEX_W_0F42_P_2_LEN_1,
1929 VEX_W_0F44_P_0_LEN_0,
1930 VEX_W_0F44_P_2_LEN_0,
1931 VEX_W_0F45_P_0_LEN_1,
1932 VEX_W_0F45_P_2_LEN_1,
1933 VEX_W_0F46_P_0_LEN_1,
1934 VEX_W_0F46_P_2_LEN_1,
1935 VEX_W_0F47_P_0_LEN_1,
1936 VEX_W_0F47_P_2_LEN_1,
1937 VEX_W_0F4A_P_0_LEN_1,
1938 VEX_W_0F4A_P_2_LEN_1,
1939 VEX_W_0F4B_P_0_LEN_1,
1940 VEX_W_0F4B_P_2_LEN_1,
2020 VEX_W_0F90_P_0_LEN_0,
2021 VEX_W_0F90_P_2_LEN_0,
2022 VEX_W_0F91_P_0_LEN_0,
2023 VEX_W_0F91_P_2_LEN_0,
2024 VEX_W_0F92_P_0_LEN_0,
2025 VEX_W_0F92_P_2_LEN_0,
2026 VEX_W_0F92_P_3_LEN_0,
2027 VEX_W_0F93_P_0_LEN_0,
2028 VEX_W_0F93_P_2_LEN_0,
2029 VEX_W_0F93_P_3_LEN_0,
2030 VEX_W_0F98_P_0_LEN_0,
2031 VEX_W_0F98_P_2_LEN_0,
2032 VEX_W_0F99_P_0_LEN_0,
2033 VEX_W_0F99_P_2_LEN_0,
2112 VEX_W_0F381A_P_2_M_0,
2124 VEX_W_0F382A_P_2_M_0,
2126 VEX_W_0F382C_P_2_M_0,
2127 VEX_W_0F382D_P_2_M_0,
2128 VEX_W_0F382E_P_2_M_0,
2129 VEX_W_0F382F_P_2_M_0,
2151 VEX_W_0F385A_P_2_M_0,
2179 VEX_W_0F3A30_P_2_LEN_0,
2180 VEX_W_0F3A31_P_2_LEN_0,
2181 VEX_W_0F3A32_P_2_LEN_0,
2182 VEX_W_0F3A33_P_2_LEN_0,
2202 EVEX_W_0F10_P_1_M_0,
2203 EVEX_W_0F10_P_1_M_1,
2205 EVEX_W_0F10_P_3_M_0,
2206 EVEX_W_0F10_P_3_M_1,
2208 EVEX_W_0F11_P_1_M_0,
2209 EVEX_W_0F11_P_1_M_1,
2211 EVEX_W_0F11_P_3_M_0,
2212 EVEX_W_0F11_P_3_M_1,
2213 EVEX_W_0F12_P_0_M_0,
2214 EVEX_W_0F12_P_0_M_1,
2224 EVEX_W_0F16_P_0_M_0,
2225 EVEX_W_0F16_P_0_M_1,
2296 EVEX_W_0F72_R_2_P_2,
2297 EVEX_W_0F72_R_6_P_2,
2298 EVEX_W_0F73_R_2_P_2,
2299 EVEX_W_0F73_R_6_P_2,
2399 EVEX_W_0F38C7_R_1_P_2,
2400 EVEX_W_0F38C7_R_2_P_2,
2401 EVEX_W_0F38C7_R_5_P_2,
2402 EVEX_W_0F38C7_R_6_P_2,
2437 typedef void (*op_rtn) (int bytemode, int sizeflag);
2446 unsigned int prefix_requirement;
2449 /* Upper case letters in the instruction names here are macros.
2450 'A' => print 'b' if no register operands or suffix_always is true
2451 'B' => print 'b' if suffix_always is true
2452 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2454 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2455 suffix_always is true
2456 'E' => print 'e' if 32-bit form of jcxz
2457 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2458 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2459 'H' => print ",pt" or ",pn" branch hint
2460 'I' => honor following macro letter even in Intel mode (implemented only
2461 for some of the macro letters)
2463 'K' => print 'd' or 'q' if rex prefix is present.
2464 'L' => print 'l' if suffix_always is true
2465 'M' => print 'r' if intel_mnemonic is false.
2466 'N' => print 'n' if instruction has no wait "prefix"
2467 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2468 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2469 or suffix_always is true. print 'q' if rex prefix is present.
2470 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2472 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2473 'S' => print 'w', 'l' or 'q' if suffix_always is true
2474 'T' => print 'q' in 64bit mode if instruction has no operand size
2475 prefix and behave as 'P' otherwise
2476 'U' => print 'q' in 64bit mode if instruction has no operand size
2477 prefix and behave as 'Q' otherwise
2478 'V' => print 'q' in 64bit mode if instruction has no operand size
2479 prefix and behave as 'S' otherwise
2480 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2481 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2482 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2483 suffix_always is true.
2484 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2485 '!' => change condition from true to false or from false to true.
2486 '%' => add 1 upper case letter to the macro.
2487 '^' => print 'w' or 'l' depending on operand size prefix or
2488 suffix_always is true (lcall/ljmp).
2489 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2490 on operand size prefix.
2491 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2492 has no operand size prefix for AMD64 ISA, behave as 'P'
2495 2 upper case letter macros:
2496 "XY" => print 'x' or 'y' if suffix_always is true or no register
2497 operands and no broadcast.
2498 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2499 register operands and no broadcast.
2500 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2501 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2502 or suffix_always is true
2503 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2504 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2505 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2506 "LW" => print 'd', 'q' depending on the VEX.W bit
2507 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2508 an operand size prefix, or suffix_always is true. print
2509 'q' if rex prefix is present.
2511 Many of the above letters print nothing in Intel mode. See "putop"
2514 Braces '{' and '}', and vertical bars '|', indicate alternative
2515 mnemonic strings for AT&T and Intel. */
2517 static const struct dis386 dis386[] = {
2519 { "addB", { Ebh1, Gb }, 0 },
2520 { "addS", { Evh1, Gv }, 0 },
2521 { "addB", { Gb, EbS }, 0 },
2522 { "addS", { Gv, EvS }, 0 },
2523 { "addB", { AL, Ib }, 0 },
2524 { "addS", { eAX, Iv }, 0 },
2525 { X86_64_TABLE (X86_64_06) },
2526 { X86_64_TABLE (X86_64_07) },
2528 { "orB", { Ebh1, Gb }, 0 },
2529 { "orS", { Evh1, Gv }, 0 },
2530 { "orB", { Gb, EbS }, 0 },
2531 { "orS", { Gv, EvS }, 0 },
2532 { "orB", { AL, Ib }, 0 },
2533 { "orS", { eAX, Iv }, 0 },
2534 { X86_64_TABLE (X86_64_0D) },
2535 { Bad_Opcode }, /* 0x0f extended opcode escape */
2537 { "adcB", { Ebh1, Gb }, 0 },
2538 { "adcS", { Evh1, Gv }, 0 },
2539 { "adcB", { Gb, EbS }, 0 },
2540 { "adcS", { Gv, EvS }, 0 },
2541 { "adcB", { AL, Ib }, 0 },
2542 { "adcS", { eAX, Iv }, 0 },
2543 { X86_64_TABLE (X86_64_16) },
2544 { X86_64_TABLE (X86_64_17) },
2546 { "sbbB", { Ebh1, Gb }, 0 },
2547 { "sbbS", { Evh1, Gv }, 0 },
2548 { "sbbB", { Gb, EbS }, 0 },
2549 { "sbbS", { Gv, EvS }, 0 },
2550 { "sbbB", { AL, Ib }, 0 },
2551 { "sbbS", { eAX, Iv }, 0 },
2552 { X86_64_TABLE (X86_64_1E) },
2553 { X86_64_TABLE (X86_64_1F) },
2555 { "andB", { Ebh1, Gb }, 0 },
2556 { "andS", { Evh1, Gv }, 0 },
2557 { "andB", { Gb, EbS }, 0 },
2558 { "andS", { Gv, EvS }, 0 },
2559 { "andB", { AL, Ib }, 0 },
2560 { "andS", { eAX, Iv }, 0 },
2561 { Bad_Opcode }, /* SEG ES prefix */
2562 { X86_64_TABLE (X86_64_27) },
2564 { "subB", { Ebh1, Gb }, 0 },
2565 { "subS", { Evh1, Gv }, 0 },
2566 { "subB", { Gb, EbS }, 0 },
2567 { "subS", { Gv, EvS }, 0 },
2568 { "subB", { AL, Ib }, 0 },
2569 { "subS", { eAX, Iv }, 0 },
2570 { Bad_Opcode }, /* SEG CS prefix */
2571 { X86_64_TABLE (X86_64_2F) },
2573 { "xorB", { Ebh1, Gb }, 0 },
2574 { "xorS", { Evh1, Gv }, 0 },
2575 { "xorB", { Gb, EbS }, 0 },
2576 { "xorS", { Gv, EvS }, 0 },
2577 { "xorB", { AL, Ib }, 0 },
2578 { "xorS", { eAX, Iv }, 0 },
2579 { Bad_Opcode }, /* SEG SS prefix */
2580 { X86_64_TABLE (X86_64_37) },
2582 { "cmpB", { Eb, Gb }, 0 },
2583 { "cmpS", { Ev, Gv }, 0 },
2584 { "cmpB", { Gb, EbS }, 0 },
2585 { "cmpS", { Gv, EvS }, 0 },
2586 { "cmpB", { AL, Ib }, 0 },
2587 { "cmpS", { eAX, Iv }, 0 },
2588 { Bad_Opcode }, /* SEG DS prefix */
2589 { X86_64_TABLE (X86_64_3F) },
2591 { "inc{S|}", { RMeAX }, 0 },
2592 { "inc{S|}", { RMeCX }, 0 },
2593 { "inc{S|}", { RMeDX }, 0 },
2594 { "inc{S|}", { RMeBX }, 0 },
2595 { "inc{S|}", { RMeSP }, 0 },
2596 { "inc{S|}", { RMeBP }, 0 },
2597 { "inc{S|}", { RMeSI }, 0 },
2598 { "inc{S|}", { RMeDI }, 0 },
2600 { "dec{S|}", { RMeAX }, 0 },
2601 { "dec{S|}", { RMeCX }, 0 },
2602 { "dec{S|}", { RMeDX }, 0 },
2603 { "dec{S|}", { RMeBX }, 0 },
2604 { "dec{S|}", { RMeSP }, 0 },
2605 { "dec{S|}", { RMeBP }, 0 },
2606 { "dec{S|}", { RMeSI }, 0 },
2607 { "dec{S|}", { RMeDI }, 0 },
2609 { "pushV", { RMrAX }, 0 },
2610 { "pushV", { RMrCX }, 0 },
2611 { "pushV", { RMrDX }, 0 },
2612 { "pushV", { RMrBX }, 0 },
2613 { "pushV", { RMrSP }, 0 },
2614 { "pushV", { RMrBP }, 0 },
2615 { "pushV", { RMrSI }, 0 },
2616 { "pushV", { RMrDI }, 0 },
2618 { "popV", { RMrAX }, 0 },
2619 { "popV", { RMrCX }, 0 },
2620 { "popV", { RMrDX }, 0 },
2621 { "popV", { RMrBX }, 0 },
2622 { "popV", { RMrSP }, 0 },
2623 { "popV", { RMrBP }, 0 },
2624 { "popV", { RMrSI }, 0 },
2625 { "popV", { RMrDI }, 0 },
2627 { X86_64_TABLE (X86_64_60) },
2628 { X86_64_TABLE (X86_64_61) },
2629 { X86_64_TABLE (X86_64_62) },
2630 { X86_64_TABLE (X86_64_63) },
2631 { Bad_Opcode }, /* seg fs */
2632 { Bad_Opcode }, /* seg gs */
2633 { Bad_Opcode }, /* op size prefix */
2634 { Bad_Opcode }, /* adr size prefix */
2636 { "pushT", { sIv }, 0 },
2637 { "imulS", { Gv, Ev, Iv }, 0 },
2638 { "pushT", { sIbT }, 0 },
2639 { "imulS", { Gv, Ev, sIb }, 0 },
2640 { "ins{b|}", { Ybr, indirDX }, 0 },
2641 { X86_64_TABLE (X86_64_6D) },
2642 { "outs{b|}", { indirDXr, Xb }, 0 },
2643 { X86_64_TABLE (X86_64_6F) },
2645 { "joH", { Jb, BND, cond_jump_flag }, 0 },
2646 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
2647 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
2648 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
2649 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
2650 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
2651 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
2652 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
2654 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
2655 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
2656 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
2657 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
2658 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
2659 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
2660 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
2661 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
2663 { REG_TABLE (REG_80) },
2664 { REG_TABLE (REG_81) },
2666 { REG_TABLE (REG_83) },
2667 { "testB", { Eb, Gb }, 0 },
2668 { "testS", { Ev, Gv }, 0 },
2669 { "xchgB", { Ebh2, Gb }, 0 },
2670 { "xchgS", { Evh2, Gv }, 0 },
2672 { "movB", { Ebh3, Gb }, 0 },
2673 { "movS", { Evh3, Gv }, 0 },
2674 { "movB", { Gb, EbS }, 0 },
2675 { "movS", { Gv, EvS }, 0 },
2676 { "movD", { Sv, Sw }, 0 },
2677 { MOD_TABLE (MOD_8D) },
2678 { "movD", { Sw, Sv }, 0 },
2679 { REG_TABLE (REG_8F) },
2681 { PREFIX_TABLE (PREFIX_90) },
2682 { "xchgS", { RMeCX, eAX }, 0 },
2683 { "xchgS", { RMeDX, eAX }, 0 },
2684 { "xchgS", { RMeBX, eAX }, 0 },
2685 { "xchgS", { RMeSP, eAX }, 0 },
2686 { "xchgS", { RMeBP, eAX }, 0 },
2687 { "xchgS", { RMeSI, eAX }, 0 },
2688 { "xchgS", { RMeDI, eAX }, 0 },
2690 { "cW{t|}R", { XX }, 0 },
2691 { "cR{t|}O", { XX }, 0 },
2692 { X86_64_TABLE (X86_64_9A) },
2693 { Bad_Opcode }, /* fwait */
2694 { "pushfT", { XX }, 0 },
2695 { "popfT", { XX }, 0 },
2696 { "sahf", { XX }, 0 },
2697 { "lahf", { XX }, 0 },
2699 { "mov%LB", { AL, Ob }, 0 },
2700 { "mov%LS", { eAX, Ov }, 0 },
2701 { "mov%LB", { Ob, AL }, 0 },
2702 { "mov%LS", { Ov, eAX }, 0 },
2703 { "movs{b|}", { Ybr, Xb }, 0 },
2704 { "movs{R|}", { Yvr, Xv }, 0 },
2705 { "cmps{b|}", { Xb, Yb }, 0 },
2706 { "cmps{R|}", { Xv, Yv }, 0 },
2708 { "testB", { AL, Ib }, 0 },
2709 { "testS", { eAX, Iv }, 0 },
2710 { "stosB", { Ybr, AL }, 0 },
2711 { "stosS", { Yvr, eAX }, 0 },
2712 { "lodsB", { ALr, Xb }, 0 },
2713 { "lodsS", { eAXr, Xv }, 0 },
2714 { "scasB", { AL, Yb }, 0 },
2715 { "scasS", { eAX, Yv }, 0 },
2717 { "movB", { RMAL, Ib }, 0 },
2718 { "movB", { RMCL, Ib }, 0 },
2719 { "movB", { RMDL, Ib }, 0 },
2720 { "movB", { RMBL, Ib }, 0 },
2721 { "movB", { RMAH, Ib }, 0 },
2722 { "movB", { RMCH, Ib }, 0 },
2723 { "movB", { RMDH, Ib }, 0 },
2724 { "movB", { RMBH, Ib }, 0 },
2726 { "mov%LV", { RMeAX, Iv64 }, 0 },
2727 { "mov%LV", { RMeCX, Iv64 }, 0 },
2728 { "mov%LV", { RMeDX, Iv64 }, 0 },
2729 { "mov%LV", { RMeBX, Iv64 }, 0 },
2730 { "mov%LV", { RMeSP, Iv64 }, 0 },
2731 { "mov%LV", { RMeBP, Iv64 }, 0 },
2732 { "mov%LV", { RMeSI, Iv64 }, 0 },
2733 { "mov%LV", { RMeDI, Iv64 }, 0 },
2735 { REG_TABLE (REG_C0) },
2736 { REG_TABLE (REG_C1) },
2737 { "retT", { Iw, BND }, 0 },
2738 { "retT", { BND }, 0 },
2739 { X86_64_TABLE (X86_64_C4) },
2740 { X86_64_TABLE (X86_64_C5) },
2741 { REG_TABLE (REG_C6) },
2742 { REG_TABLE (REG_C7) },
2744 { "enterT", { Iw, Ib }, 0 },
2745 { "leaveT", { XX }, 0 },
2746 { "Jret{|f}P", { Iw }, 0 },
2747 { "Jret{|f}P", { XX }, 0 },
2748 { "int3", { XX }, 0 },
2749 { "int", { Ib }, 0 },
2750 { X86_64_TABLE (X86_64_CE) },
2751 { "iret%LP", { XX }, 0 },
2753 { REG_TABLE (REG_D0) },
2754 { REG_TABLE (REG_D1) },
2755 { REG_TABLE (REG_D2) },
2756 { REG_TABLE (REG_D3) },
2757 { X86_64_TABLE (X86_64_D4) },
2758 { X86_64_TABLE (X86_64_D5) },
2760 { "xlat", { DSBX }, 0 },
2771 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2772 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2773 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2774 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2775 { "inB", { AL, Ib }, 0 },
2776 { "inG", { zAX, Ib }, 0 },
2777 { "outB", { Ib, AL }, 0 },
2778 { "outG", { Ib, zAX }, 0 },
2780 { X86_64_TABLE (X86_64_E8) },
2781 { X86_64_TABLE (X86_64_E9) },
2782 { X86_64_TABLE (X86_64_EA) },
2783 { "jmp", { Jb, BND }, 0 },
2784 { "inB", { AL, indirDX }, 0 },
2785 { "inG", { zAX, indirDX }, 0 },
2786 { "outB", { indirDX, AL }, 0 },
2787 { "outG", { indirDX, zAX }, 0 },
2789 { Bad_Opcode }, /* lock prefix */
2790 { "icebp", { XX }, 0 },
2791 { Bad_Opcode }, /* repne */
2792 { Bad_Opcode }, /* repz */
2793 { "hlt", { XX }, 0 },
2794 { "cmc", { XX }, 0 },
2795 { REG_TABLE (REG_F6) },
2796 { REG_TABLE (REG_F7) },
2798 { "clc", { XX }, 0 },
2799 { "stc", { XX }, 0 },
2800 { "cli", { XX }, 0 },
2801 { "sti", { XX }, 0 },
2802 { "cld", { XX }, 0 },
2803 { "std", { XX }, 0 },
2804 { REG_TABLE (REG_FE) },
2805 { REG_TABLE (REG_FF) },
2808 static const struct dis386 dis386_twobyte[] = {
2810 { REG_TABLE (REG_0F00 ) },
2811 { REG_TABLE (REG_0F01 ) },
2812 { "larS", { Gv, Ew }, 0 },
2813 { "lslS", { Gv, Ew }, 0 },
2815 { "syscall", { XX }, 0 },
2816 { "clts", { XX }, 0 },
2817 { "sysret%LP", { XX }, 0 },
2819 { "invd", { XX }, 0 },
2820 { "wbinvd", { XX }, 0 },
2822 { "ud2", { XX }, 0 },
2824 { REG_TABLE (REG_0F0D) },
2825 { "femms", { XX }, 0 },
2826 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2828 { PREFIX_TABLE (PREFIX_0F10) },
2829 { PREFIX_TABLE (PREFIX_0F11) },
2830 { PREFIX_TABLE (PREFIX_0F12) },
2831 { MOD_TABLE (MOD_0F13) },
2832 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2833 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2834 { PREFIX_TABLE (PREFIX_0F16) },
2835 { MOD_TABLE (MOD_0F17) },
2837 { REG_TABLE (REG_0F18) },
2838 { "nopQ", { Ev }, 0 },
2839 { PREFIX_TABLE (PREFIX_0F1A) },
2840 { PREFIX_TABLE (PREFIX_0F1B) },
2841 { "nopQ", { Ev }, 0 },
2842 { "nopQ", { Ev }, 0 },
2843 { "nopQ", { Ev }, 0 },
2844 { "nopQ", { Ev }, 0 },
2846 { "movZ", { Rm, Cm }, 0 },
2847 { "movZ", { Rm, Dm }, 0 },
2848 { "movZ", { Cm, Rm }, 0 },
2849 { "movZ", { Dm, Rm }, 0 },
2850 { MOD_TABLE (MOD_0F24) },
2852 { MOD_TABLE (MOD_0F26) },
2855 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2856 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2857 { PREFIX_TABLE (PREFIX_0F2A) },
2858 { PREFIX_TABLE (PREFIX_0F2B) },
2859 { PREFIX_TABLE (PREFIX_0F2C) },
2860 { PREFIX_TABLE (PREFIX_0F2D) },
2861 { PREFIX_TABLE (PREFIX_0F2E) },
2862 { PREFIX_TABLE (PREFIX_0F2F) },
2864 { "wrmsr", { XX }, 0 },
2865 { "rdtsc", { XX }, 0 },
2866 { "rdmsr", { XX }, 0 },
2867 { "rdpmc", { XX }, 0 },
2868 { "sysenter", { XX }, 0 },
2869 { "sysexit", { XX }, 0 },
2871 { "getsec", { XX }, 0 },
2873 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2875 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2882 { "cmovoS", { Gv, Ev }, 0 },
2883 { "cmovnoS", { Gv, Ev }, 0 },
2884 { "cmovbS", { Gv, Ev }, 0 },
2885 { "cmovaeS", { Gv, Ev }, 0 },
2886 { "cmoveS", { Gv, Ev }, 0 },
2887 { "cmovneS", { Gv, Ev }, 0 },
2888 { "cmovbeS", { Gv, Ev }, 0 },
2889 { "cmovaS", { Gv, Ev }, 0 },
2891 { "cmovsS", { Gv, Ev }, 0 },
2892 { "cmovnsS", { Gv, Ev }, 0 },
2893 { "cmovpS", { Gv, Ev }, 0 },
2894 { "cmovnpS", { Gv, Ev }, 0 },
2895 { "cmovlS", { Gv, Ev }, 0 },
2896 { "cmovgeS", { Gv, Ev }, 0 },
2897 { "cmovleS", { Gv, Ev }, 0 },
2898 { "cmovgS", { Gv, Ev }, 0 },
2900 { MOD_TABLE (MOD_0F51) },
2901 { PREFIX_TABLE (PREFIX_0F51) },
2902 { PREFIX_TABLE (PREFIX_0F52) },
2903 { PREFIX_TABLE (PREFIX_0F53) },
2904 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2905 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2906 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2907 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2909 { PREFIX_TABLE (PREFIX_0F58) },
2910 { PREFIX_TABLE (PREFIX_0F59) },
2911 { PREFIX_TABLE (PREFIX_0F5A) },
2912 { PREFIX_TABLE (PREFIX_0F5B) },
2913 { PREFIX_TABLE (PREFIX_0F5C) },
2914 { PREFIX_TABLE (PREFIX_0F5D) },
2915 { PREFIX_TABLE (PREFIX_0F5E) },
2916 { PREFIX_TABLE (PREFIX_0F5F) },
2918 { PREFIX_TABLE (PREFIX_0F60) },
2919 { PREFIX_TABLE (PREFIX_0F61) },
2920 { PREFIX_TABLE (PREFIX_0F62) },
2921 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2922 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2923 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2924 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2925 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2927 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2928 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2929 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2930 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2931 { PREFIX_TABLE (PREFIX_0F6C) },
2932 { PREFIX_TABLE (PREFIX_0F6D) },
2933 { "movK", { MX, Edq }, PREFIX_OPCODE },
2934 { PREFIX_TABLE (PREFIX_0F6F) },
2936 { PREFIX_TABLE (PREFIX_0F70) },
2937 { REG_TABLE (REG_0F71) },
2938 { REG_TABLE (REG_0F72) },
2939 { REG_TABLE (REG_0F73) },
2940 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2941 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2942 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2943 { "emms", { XX }, PREFIX_OPCODE },
2945 { PREFIX_TABLE (PREFIX_0F78) },
2946 { PREFIX_TABLE (PREFIX_0F79) },
2947 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2949 { PREFIX_TABLE (PREFIX_0F7C) },
2950 { PREFIX_TABLE (PREFIX_0F7D) },
2951 { PREFIX_TABLE (PREFIX_0F7E) },
2952 { PREFIX_TABLE (PREFIX_0F7F) },
2954 { "joH", { Jv, BND, cond_jump_flag }, 0 },
2955 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
2956 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
2957 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
2958 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
2959 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
2960 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
2961 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
2963 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
2964 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
2965 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
2966 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
2967 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
2968 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
2969 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
2970 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
2972 { "seto", { Eb }, 0 },
2973 { "setno", { Eb }, 0 },
2974 { "setb", { Eb }, 0 },
2975 { "setae", { Eb }, 0 },
2976 { "sete", { Eb }, 0 },
2977 { "setne", { Eb }, 0 },
2978 { "setbe", { Eb }, 0 },
2979 { "seta", { Eb }, 0 },
2981 { "sets", { Eb }, 0 },
2982 { "setns", { Eb }, 0 },
2983 { "setp", { Eb }, 0 },
2984 { "setnp", { Eb }, 0 },
2985 { "setl", { Eb }, 0 },
2986 { "setge", { Eb }, 0 },
2987 { "setle", { Eb }, 0 },
2988 { "setg", { Eb }, 0 },
2990 { "pushT", { fs }, 0 },
2991 { "popT", { fs }, 0 },
2992 { "cpuid", { XX }, 0 },
2993 { "btS", { Ev, Gv }, 0 },
2994 { "shldS", { Ev, Gv, Ib }, 0 },
2995 { "shldS", { Ev, Gv, CL }, 0 },
2996 { REG_TABLE (REG_0FA6) },
2997 { REG_TABLE (REG_0FA7) },
2999 { "pushT", { gs }, 0 },
3000 { "popT", { gs }, 0 },
3001 { "rsm", { XX }, 0 },
3002 { "btsS", { Evh1, Gv }, 0 },
3003 { "shrdS", { Ev, Gv, Ib }, 0 },
3004 { "shrdS", { Ev, Gv, CL }, 0 },
3005 { REG_TABLE (REG_0FAE) },
3006 { "imulS", { Gv, Ev }, 0 },
3008 { "cmpxchgB", { Ebh1, Gb }, 0 },
3009 { "cmpxchgS", { Evh1, Gv }, 0 },
3010 { MOD_TABLE (MOD_0FB2) },
3011 { "btrS", { Evh1, Gv }, 0 },
3012 { MOD_TABLE (MOD_0FB4) },
3013 { MOD_TABLE (MOD_0FB5) },
3014 { "movz{bR|x}", { Gv, Eb }, 0 },
3015 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3017 { PREFIX_TABLE (PREFIX_0FB8) },
3018 { "ud1", { XX }, 0 },
3019 { REG_TABLE (REG_0FBA) },
3020 { "btcS", { Evh1, Gv }, 0 },
3021 { PREFIX_TABLE (PREFIX_0FBC) },
3022 { PREFIX_TABLE (PREFIX_0FBD) },
3023 { "movs{bR|x}", { Gv, Eb }, 0 },
3024 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3026 { "xaddB", { Ebh1, Gb }, 0 },
3027 { "xaddS", { Evh1, Gv }, 0 },
3028 { PREFIX_TABLE (PREFIX_0FC2) },
3029 { MOD_TABLE (MOD_0FC3) },
3030 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
3031 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
3032 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
3033 { REG_TABLE (REG_0FC7) },
3035 { "bswap", { RMeAX }, 0 },
3036 { "bswap", { RMeCX }, 0 },
3037 { "bswap", { RMeDX }, 0 },
3038 { "bswap", { RMeBX }, 0 },
3039 { "bswap", { RMeSP }, 0 },
3040 { "bswap", { RMeBP }, 0 },
3041 { "bswap", { RMeSI }, 0 },
3042 { "bswap", { RMeDI }, 0 },
3044 { PREFIX_TABLE (PREFIX_0FD0) },
3045 { "psrlw", { MX, EM }, PREFIX_OPCODE },
3046 { "psrld", { MX, EM }, PREFIX_OPCODE },
3047 { "psrlq", { MX, EM }, PREFIX_OPCODE },
3048 { "paddq", { MX, EM }, PREFIX_OPCODE },
3049 { "pmullw", { MX, EM }, PREFIX_OPCODE },
3050 { PREFIX_TABLE (PREFIX_0FD6) },
3051 { MOD_TABLE (MOD_0FD7) },
3053 { "psubusb", { MX, EM }, PREFIX_OPCODE },
3054 { "psubusw", { MX, EM }, PREFIX_OPCODE },
3055 { "pminub", { MX, EM }, PREFIX_OPCODE },
3056 { "pand", { MX, EM }, PREFIX_OPCODE },
3057 { "paddusb", { MX, EM }, PREFIX_OPCODE },
3058 { "paddusw", { MX, EM }, PREFIX_OPCODE },
3059 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
3060 { "pandn", { MX, EM }, PREFIX_OPCODE },
3062 { "pavgb", { MX, EM }, PREFIX_OPCODE },
3063 { "psraw", { MX, EM }, PREFIX_OPCODE },
3064 { "psrad", { MX, EM }, PREFIX_OPCODE },
3065 { "pavgw", { MX, EM }, PREFIX_OPCODE },
3066 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
3067 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
3068 { PREFIX_TABLE (PREFIX_0FE6) },
3069 { PREFIX_TABLE (PREFIX_0FE7) },
3071 { "psubsb", { MX, EM }, PREFIX_OPCODE },
3072 { "psubsw", { MX, EM }, PREFIX_OPCODE },
3073 { "pminsw", { MX, EM }, PREFIX_OPCODE },
3074 { "por", { MX, EM }, PREFIX_OPCODE },
3075 { "paddsb", { MX, EM }, PREFIX_OPCODE },
3076 { "paddsw", { MX, EM }, PREFIX_OPCODE },
3077 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
3078 { "pxor", { MX, EM }, PREFIX_OPCODE },
3080 { PREFIX_TABLE (PREFIX_0FF0) },
3081 { "psllw", { MX, EM }, PREFIX_OPCODE },
3082 { "pslld", { MX, EM }, PREFIX_OPCODE },
3083 { "psllq", { MX, EM }, PREFIX_OPCODE },
3084 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
3085 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
3086 { "psadbw", { MX, EM }, PREFIX_OPCODE },
3087 { PREFIX_TABLE (PREFIX_0FF7) },
3089 { "psubb", { MX, EM }, PREFIX_OPCODE },
3090 { "psubw", { MX, EM }, PREFIX_OPCODE },
3091 { "psubd", { MX, EM }, PREFIX_OPCODE },
3092 { "psubq", { MX, EM }, PREFIX_OPCODE },
3093 { "paddb", { MX, EM }, PREFIX_OPCODE },
3094 { "paddw", { MX, EM }, PREFIX_OPCODE },
3095 { "paddd", { MX, EM }, PREFIX_OPCODE },
3099 static const unsigned char onebyte_has_modrm[256] = {
3100 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3101 /* ------------------------------- */
3102 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3103 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3104 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3105 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3106 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3107 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3108 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3109 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3110 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3111 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3112 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3113 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3114 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3115 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3116 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3117 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3118 /* ------------------------------- */
3119 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3122 static const unsigned char twobyte_has_modrm[256] = {
3123 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3124 /* ------------------------------- */
3125 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3126 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3127 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3128 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3129 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3130 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3131 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3132 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3133 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3134 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3135 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3136 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3137 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3138 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3139 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3140 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3141 /* ------------------------------- */
3142 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3145 static char obuf[100];
3147 static char *mnemonicendp;
3148 static char scratchbuf[100];
3149 static unsigned char *start_codep;
3150 static unsigned char *insn_codep;
3151 static unsigned char *codep;
3152 static unsigned char *end_codep;
3153 static int last_lock_prefix;
3154 static int last_repz_prefix;
3155 static int last_repnz_prefix;
3156 static int last_data_prefix;
3157 static int last_addr_prefix;
3158 static int last_rex_prefix;
3159 static int last_seg_prefix;
3160 static int fwait_prefix;
3161 /* The active segment register prefix. */
3162 static int active_seg_prefix;
3163 #define MAX_CODE_LENGTH 15
3164 /* We can up to 14 prefixes since the maximum instruction length is
3166 static int all_prefixes[MAX_CODE_LENGTH - 1];
3167 static disassemble_info *the_info;
3175 static unsigned char need_modrm;
3185 int register_specifier;
3192 int mask_register_specifier;
3198 static unsigned char need_vex;
3199 static unsigned char need_vex_reg;
3200 static unsigned char vex_w_done;
3208 /* If we are accessing mod/rm/reg without need_modrm set, then the
3209 values are stale. Hitting this abort likely indicates that you
3210 need to update onebyte_has_modrm or twobyte_has_modrm. */
3211 #define MODRM_CHECK if (!need_modrm) abort ()
3213 static const char **names64;
3214 static const char **names32;
3215 static const char **names16;
3216 static const char **names8;
3217 static const char **names8rex;
3218 static const char **names_seg;
3219 static const char *index64;
3220 static const char *index32;
3221 static const char **index16;
3222 static const char **names_bnd;
3224 static const char *intel_names64[] = {
3225 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3226 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3228 static const char *intel_names32[] = {
3229 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3230 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3232 static const char *intel_names16[] = {
3233 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3234 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3236 static const char *intel_names8[] = {
3237 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3239 static const char *intel_names8rex[] = {
3240 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3241 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3243 static const char *intel_names_seg[] = {
3244 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3246 static const char *intel_index64 = "riz";
3247 static const char *intel_index32 = "eiz";
3248 static const char *intel_index16[] = {
3249 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3252 static const char *att_names64[] = {
3253 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3254 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3256 static const char *att_names32[] = {
3257 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3258 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3260 static const char *att_names16[] = {
3261 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3262 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3264 static const char *att_names8[] = {
3265 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3267 static const char *att_names8rex[] = {
3268 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3269 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3271 static const char *att_names_seg[] = {
3272 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3274 static const char *att_index64 = "%riz";
3275 static const char *att_index32 = "%eiz";
3276 static const char *att_index16[] = {
3277 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3280 static const char **names_mm;
3281 static const char *intel_names_mm[] = {
3282 "mm0", "mm1", "mm2", "mm3",
3283 "mm4", "mm5", "mm6", "mm7"
3285 static const char *att_names_mm[] = {
3286 "%mm0", "%mm1", "%mm2", "%mm3",
3287 "%mm4", "%mm5", "%mm6", "%mm7"
3290 static const char *intel_names_bnd[] = {
3291 "bnd0", "bnd1", "bnd2", "bnd3"
3294 static const char *att_names_bnd[] = {
3295 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3298 static const char **names_xmm;
3299 static const char *intel_names_xmm[] = {
3300 "xmm0", "xmm1", "xmm2", "xmm3",
3301 "xmm4", "xmm5", "xmm6", "xmm7",
3302 "xmm8", "xmm9", "xmm10", "xmm11",
3303 "xmm12", "xmm13", "xmm14", "xmm15",
3304 "xmm16", "xmm17", "xmm18", "xmm19",
3305 "xmm20", "xmm21", "xmm22", "xmm23",
3306 "xmm24", "xmm25", "xmm26", "xmm27",
3307 "xmm28", "xmm29", "xmm30", "xmm31"
3309 static const char *att_names_xmm[] = {
3310 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3311 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3312 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3313 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3314 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3315 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3316 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3317 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3320 static const char **names_ymm;
3321 static const char *intel_names_ymm[] = {
3322 "ymm0", "ymm1", "ymm2", "ymm3",
3323 "ymm4", "ymm5", "ymm6", "ymm7",
3324 "ymm8", "ymm9", "ymm10", "ymm11",
3325 "ymm12", "ymm13", "ymm14", "ymm15",
3326 "ymm16", "ymm17", "ymm18", "ymm19",
3327 "ymm20", "ymm21", "ymm22", "ymm23",
3328 "ymm24", "ymm25", "ymm26", "ymm27",
3329 "ymm28", "ymm29", "ymm30", "ymm31"
3331 static const char *att_names_ymm[] = {
3332 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3333 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3334 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3335 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3336 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3337 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3338 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3339 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3342 static const char **names_zmm;
3343 static const char *intel_names_zmm[] = {
3344 "zmm0", "zmm1", "zmm2", "zmm3",
3345 "zmm4", "zmm5", "zmm6", "zmm7",
3346 "zmm8", "zmm9", "zmm10", "zmm11",
3347 "zmm12", "zmm13", "zmm14", "zmm15",
3348 "zmm16", "zmm17", "zmm18", "zmm19",
3349 "zmm20", "zmm21", "zmm22", "zmm23",
3350 "zmm24", "zmm25", "zmm26", "zmm27",
3351 "zmm28", "zmm29", "zmm30", "zmm31"
3353 static const char *att_names_zmm[] = {
3354 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3355 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3356 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3357 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3358 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3359 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3360 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3361 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3364 static const char **names_mask;
3365 static const char *intel_names_mask[] = {
3366 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3368 static const char *att_names_mask[] = {
3369 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3372 static const char *names_rounding[] =
3380 static const struct dis386 reg_table[][8] = {
3383 { "addA", { Ebh1, Ib }, 0 },
3384 { "orA", { Ebh1, Ib }, 0 },
3385 { "adcA", { Ebh1, Ib }, 0 },
3386 { "sbbA", { Ebh1, Ib }, 0 },
3387 { "andA", { Ebh1, Ib }, 0 },
3388 { "subA", { Ebh1, Ib }, 0 },
3389 { "xorA", { Ebh1, Ib }, 0 },
3390 { "cmpA", { Eb, Ib }, 0 },
3394 { "addQ", { Evh1, Iv }, 0 },
3395 { "orQ", { Evh1, Iv }, 0 },
3396 { "adcQ", { Evh1, Iv }, 0 },
3397 { "sbbQ", { Evh1, Iv }, 0 },
3398 { "andQ", { Evh1, Iv }, 0 },
3399 { "subQ", { Evh1, Iv }, 0 },
3400 { "xorQ", { Evh1, Iv }, 0 },
3401 { "cmpQ", { Ev, Iv }, 0 },
3405 { "addQ", { Evh1, sIb }, 0 },
3406 { "orQ", { Evh1, sIb }, 0 },
3407 { "adcQ", { Evh1, sIb }, 0 },
3408 { "sbbQ", { Evh1, sIb }, 0 },
3409 { "andQ", { Evh1, sIb }, 0 },
3410 { "subQ", { Evh1, sIb }, 0 },
3411 { "xorQ", { Evh1, sIb }, 0 },
3412 { "cmpQ", { Ev, sIb }, 0 },
3416 { "popU", { stackEv }, 0 },
3417 { XOP_8F_TABLE (XOP_09) },
3421 { XOP_8F_TABLE (XOP_09) },
3425 { "rolA", { Eb, Ib }, 0 },
3426 { "rorA", { Eb, Ib }, 0 },
3427 { "rclA", { Eb, Ib }, 0 },
3428 { "rcrA", { Eb, Ib }, 0 },
3429 { "shlA", { Eb, Ib }, 0 },
3430 { "shrA", { Eb, Ib }, 0 },
3432 { "sarA", { Eb, Ib }, 0 },
3436 { "rolQ", { Ev, Ib }, 0 },
3437 { "rorQ", { Ev, Ib }, 0 },
3438 { "rclQ", { Ev, Ib }, 0 },
3439 { "rcrQ", { Ev, Ib }, 0 },
3440 { "shlQ", { Ev, Ib }, 0 },
3441 { "shrQ", { Ev, Ib }, 0 },
3443 { "sarQ", { Ev, Ib }, 0 },
3447 { "movA", { Ebh3, Ib }, 0 },
3454 { MOD_TABLE (MOD_C6_REG_7) },
3458 { "movQ", { Evh3, Iv }, 0 },
3465 { MOD_TABLE (MOD_C7_REG_7) },
3469 { "rolA", { Eb, I1 }, 0 },
3470 { "rorA", { Eb, I1 }, 0 },
3471 { "rclA", { Eb, I1 }, 0 },
3472 { "rcrA", { Eb, I1 }, 0 },
3473 { "shlA", { Eb, I1 }, 0 },
3474 { "shrA", { Eb, I1 }, 0 },
3476 { "sarA", { Eb, I1 }, 0 },
3480 { "rolQ", { Ev, I1 }, 0 },
3481 { "rorQ", { Ev, I1 }, 0 },
3482 { "rclQ", { Ev, I1 }, 0 },
3483 { "rcrQ", { Ev, I1 }, 0 },
3484 { "shlQ", { Ev, I1 }, 0 },
3485 { "shrQ", { Ev, I1 }, 0 },
3487 { "sarQ", { Ev, I1 }, 0 },
3491 { "rolA", { Eb, CL }, 0 },
3492 { "rorA", { Eb, CL }, 0 },
3493 { "rclA", { Eb, CL }, 0 },
3494 { "rcrA", { Eb, CL }, 0 },
3495 { "shlA", { Eb, CL }, 0 },
3496 { "shrA", { Eb, CL }, 0 },
3498 { "sarA", { Eb, CL }, 0 },
3502 { "rolQ", { Ev, CL }, 0 },
3503 { "rorQ", { Ev, CL }, 0 },
3504 { "rclQ", { Ev, CL }, 0 },
3505 { "rcrQ", { Ev, CL }, 0 },
3506 { "shlQ", { Ev, CL }, 0 },
3507 { "shrQ", { Ev, CL }, 0 },
3509 { "sarQ", { Ev, CL }, 0 },
3513 { "testA", { Eb, Ib }, 0 },
3515 { "notA", { Ebh1 }, 0 },
3516 { "negA", { Ebh1 }, 0 },
3517 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
3518 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
3519 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
3520 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
3524 { "testQ", { Ev, Iv }, 0 },
3526 { "notQ", { Evh1 }, 0 },
3527 { "negQ", { Evh1 }, 0 },
3528 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
3529 { "imulQ", { Ev }, 0 },
3530 { "divQ", { Ev }, 0 },
3531 { "idivQ", { Ev }, 0 },
3535 { "incA", { Ebh1 }, 0 },
3536 { "decA", { Ebh1 }, 0 },
3540 { "incQ", { Evh1 }, 0 },
3541 { "decQ", { Evh1 }, 0 },
3542 { "call{&|}", { indirEv, BND }, 0 },
3543 { MOD_TABLE (MOD_FF_REG_3) },
3544 { "jmp{&|}", { indirEv, BND }, 0 },
3545 { MOD_TABLE (MOD_FF_REG_5) },
3546 { "pushU", { stackEv }, 0 },
3551 { "sldtD", { Sv }, 0 },
3552 { "strD", { Sv }, 0 },
3553 { "lldt", { Ew }, 0 },
3554 { "ltr", { Ew }, 0 },
3555 { "verr", { Ew }, 0 },
3556 { "verw", { Ew }, 0 },
3562 { MOD_TABLE (MOD_0F01_REG_0) },
3563 { MOD_TABLE (MOD_0F01_REG_1) },
3564 { MOD_TABLE (MOD_0F01_REG_2) },
3565 { MOD_TABLE (MOD_0F01_REG_3) },
3566 { "smswD", { Sv }, 0 },
3567 { MOD_TABLE (MOD_0F01_REG_5) },
3568 { "lmsw", { Ew }, 0 },
3569 { MOD_TABLE (MOD_0F01_REG_7) },
3573 { "prefetch", { Mb }, 0 },
3574 { "prefetchw", { Mb }, 0 },
3575 { "prefetchwt1", { Mb }, 0 },
3576 { "prefetch", { Mb }, 0 },
3577 { "prefetch", { Mb }, 0 },
3578 { "prefetch", { Mb }, 0 },
3579 { "prefetch", { Mb }, 0 },
3580 { "prefetch", { Mb }, 0 },
3584 { MOD_TABLE (MOD_0F18_REG_0) },
3585 { MOD_TABLE (MOD_0F18_REG_1) },
3586 { MOD_TABLE (MOD_0F18_REG_2) },
3587 { MOD_TABLE (MOD_0F18_REG_3) },
3588 { MOD_TABLE (MOD_0F18_REG_4) },
3589 { MOD_TABLE (MOD_0F18_REG_5) },
3590 { MOD_TABLE (MOD_0F18_REG_6) },
3591 { MOD_TABLE (MOD_0F18_REG_7) },
3597 { MOD_TABLE (MOD_0F71_REG_2) },
3599 { MOD_TABLE (MOD_0F71_REG_4) },
3601 { MOD_TABLE (MOD_0F71_REG_6) },
3607 { MOD_TABLE (MOD_0F72_REG_2) },
3609 { MOD_TABLE (MOD_0F72_REG_4) },
3611 { MOD_TABLE (MOD_0F72_REG_6) },
3617 { MOD_TABLE (MOD_0F73_REG_2) },
3618 { MOD_TABLE (MOD_0F73_REG_3) },
3621 { MOD_TABLE (MOD_0F73_REG_6) },
3622 { MOD_TABLE (MOD_0F73_REG_7) },
3626 { "montmul", { { OP_0f07, 0 } }, 0 },
3627 { "xsha1", { { OP_0f07, 0 } }, 0 },
3628 { "xsha256", { { OP_0f07, 0 } }, 0 },
3632 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
3633 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
3634 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
3635 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
3636 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
3637 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
3641 { MOD_TABLE (MOD_0FAE_REG_0) },
3642 { MOD_TABLE (MOD_0FAE_REG_1) },
3643 { MOD_TABLE (MOD_0FAE_REG_2) },
3644 { MOD_TABLE (MOD_0FAE_REG_3) },
3645 { MOD_TABLE (MOD_0FAE_REG_4) },
3646 { MOD_TABLE (MOD_0FAE_REG_5) },
3647 { MOD_TABLE (MOD_0FAE_REG_6) },
3648 { MOD_TABLE (MOD_0FAE_REG_7) },
3656 { "btQ", { Ev, Ib }, 0 },
3657 { "btsQ", { Evh1, Ib }, 0 },
3658 { "btrQ", { Evh1, Ib }, 0 },
3659 { "btcQ", { Evh1, Ib }, 0 },
3664 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3666 { MOD_TABLE (MOD_0FC7_REG_3) },
3667 { MOD_TABLE (MOD_0FC7_REG_4) },
3668 { MOD_TABLE (MOD_0FC7_REG_5) },
3669 { MOD_TABLE (MOD_0FC7_REG_6) },
3670 { MOD_TABLE (MOD_0FC7_REG_7) },
3676 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3678 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3680 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3686 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3688 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3690 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3696 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3697 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3700 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3701 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3707 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3708 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3710 /* REG_VEX_0F38F3 */
3713 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3714 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3715 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3719 { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3720 { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3724 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3725 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3727 /* REG_XOP_TBM_01 */
3730 { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3731 { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3732 { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 },
3733 { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3734 { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 },
3735 { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 },
3736 { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3738 /* REG_XOP_TBM_02 */
3741 { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3746 { "blci", { { OP_LWP_E, 0 }, Ev }, 0 },
3748 #define NEED_REG_TABLE
3749 #include "i386-dis-evex.h"
3750 #undef NEED_REG_TABLE
3753 static const struct dis386 prefix_table[][4] = {
3756 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3757 { "pause", { XX }, 0 },
3758 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3759 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3764 { "movups", { XM, EXx }, PREFIX_OPCODE },
3765 { "movss", { XM, EXd }, PREFIX_OPCODE },
3766 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3767 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3772 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3773 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3774 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3775 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3780 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3781 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3782 { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3783 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3788 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3789 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3790 { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3795 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3796 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3797 { "bndmov", { Gbnd, Ebnd }, 0 },
3798 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3803 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3804 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3805 { "bndmov", { Ebnd, Gbnd }, 0 },
3806 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3811 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3812 { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3813 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3814 { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3819 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3820 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3821 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3822 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3827 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3828 { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3829 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3830 { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3835 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3836 { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3837 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3838 { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3843 { "ucomiss",{ XM, EXd }, 0 },
3845 { "ucomisd",{ XM, EXq }, 0 },
3850 { "comiss", { XM, EXd }, 0 },
3852 { "comisd", { XM, EXq }, 0 },
3857 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3858 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3859 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3860 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3865 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3866 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3871 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3872 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3877 { "addps", { XM, EXx }, PREFIX_OPCODE },
3878 { "addss", { XM, EXd }, PREFIX_OPCODE },
3879 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3880 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3885 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3886 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3887 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3888 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3893 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3894 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3895 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3896 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3901 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3902 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3903 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3908 { "subps", { XM, EXx }, PREFIX_OPCODE },
3909 { "subss", { XM, EXd }, PREFIX_OPCODE },
3910 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3911 { "subsd", { XM, EXq }, PREFIX_OPCODE },
3916 { "minps", { XM, EXx }, PREFIX_OPCODE },
3917 { "minss", { XM, EXd }, PREFIX_OPCODE },
3918 { "minpd", { XM, EXx }, PREFIX_OPCODE },
3919 { "minsd", { XM, EXq }, PREFIX_OPCODE },
3924 { "divps", { XM, EXx }, PREFIX_OPCODE },
3925 { "divss", { XM, EXd }, PREFIX_OPCODE },
3926 { "divpd", { XM, EXx }, PREFIX_OPCODE },
3927 { "divsd", { XM, EXq }, PREFIX_OPCODE },
3932 { "maxps", { XM, EXx }, PREFIX_OPCODE },
3933 { "maxss", { XM, EXd }, PREFIX_OPCODE },
3934 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
3935 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
3940 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3942 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3947 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3949 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3954 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3956 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3963 { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3970 { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3975 { "movq", { MX, EM }, PREFIX_OPCODE },
3976 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3977 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3982 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3983 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3984 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3985 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3988 /* PREFIX_0F73_REG_3 */
3992 { "psrldq", { XS, Ib }, 0 },
3995 /* PREFIX_0F73_REG_7 */
3999 { "pslldq", { XS, Ib }, 0 },
4004 {"vmread", { Em, Gm }, 0 },
4006 {"extrq", { XS, Ib, Ib }, 0 },
4007 {"insertq", { XM, XS, Ib, Ib }, 0 },
4012 {"vmwrite", { Gm, Em }, 0 },
4014 {"extrq", { XM, XS }, 0 },
4015 {"insertq", { XM, XS }, 0 },
4022 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4023 { "haddps", { XM, EXx }, PREFIX_OPCODE },
4030 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4031 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4036 { "movK", { Edq, MX }, PREFIX_OPCODE },
4037 { "movq", { XM, EXq }, PREFIX_OPCODE },
4038 { "movK", { Edq, XM }, PREFIX_OPCODE },
4043 { "movq", { EMS, MX }, PREFIX_OPCODE },
4044 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4045 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4048 /* PREFIX_0FAE_REG_0 */
4051 { "rdfsbase", { Ev }, 0 },
4054 /* PREFIX_0FAE_REG_1 */
4057 { "rdgsbase", { Ev }, 0 },
4060 /* PREFIX_0FAE_REG_2 */
4063 { "wrfsbase", { Ev }, 0 },
4066 /* PREFIX_0FAE_REG_3 */
4069 { "wrgsbase", { Ev }, 0 },
4072 /* PREFIX_MOD_0_0FAE_REG_4 */
4074 { "xsave", { FXSAVE }, 0 },
4075 { "ptwrite%LQ", { Edq }, 0 },
4078 /* PREFIX_MOD_3_0FAE_REG_4 */
4081 { "ptwrite%LQ", { Edq }, 0 },
4084 /* PREFIX_0FAE_REG_6 */
4086 { "xsaveopt", { FXSAVE }, 0 },
4088 { "clwb", { Mb }, 0 },
4091 /* PREFIX_0FAE_REG_7 */
4093 { "clflush", { Mb }, 0 },
4095 { "clflushopt", { Mb }, 0 },
4101 { "popcntS", { Gv, Ev }, 0 },
4106 { "bsfS", { Gv, Ev }, 0 },
4107 { "tzcntS", { Gv, Ev }, 0 },
4108 { "bsfS", { Gv, Ev }, 0 },
4113 { "bsrS", { Gv, Ev }, 0 },
4114 { "lzcntS", { Gv, Ev }, 0 },
4115 { "bsrS", { Gv, Ev }, 0 },
4120 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
4121 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
4122 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
4123 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
4126 /* PREFIX_MOD_0_0FC3 */
4128 { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4131 /* PREFIX_MOD_0_0FC7_REG_6 */
4133 { "vmptrld",{ Mq }, 0 },
4134 { "vmxon", { Mq }, 0 },
4135 { "vmclear",{ Mq }, 0 },
4138 /* PREFIX_MOD_3_0FC7_REG_6 */
4140 { "rdrand", { Ev }, 0 },
4142 { "rdrand", { Ev }, 0 }
4145 /* PREFIX_MOD_3_0FC7_REG_7 */
4147 { "rdseed", { Ev }, 0 },
4148 { "rdpid", { Em }, 0 },
4149 { "rdseed", { Ev }, 0 },
4156 { "addsubpd", { XM, EXx }, 0 },
4157 { "addsubps", { XM, EXx }, 0 },
4163 { "movq2dq",{ XM, MS }, 0 },
4164 { "movq", { EXqS, XM }, 0 },
4165 { "movdq2q",{ MX, XS }, 0 },
4171 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4172 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4173 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4178 { "movntq", { Mq, MX }, PREFIX_OPCODE },
4180 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4188 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4193 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4195 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4202 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4209 { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4216 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4223 { "ptest", { XM, EXx }, PREFIX_OPCODE },
4230 { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4237 { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4244 { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4251 { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4258 { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4265 { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4272 { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4279 { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4286 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4293 { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4300 { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4307 { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4314 { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4321 { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4328 { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4335 { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4342 { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4349 { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4356 { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4363 { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4370 { "pminud", { XM, EXx }, PREFIX_OPCODE },
4377 { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4384 { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4391 { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4398 { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4405 { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4412 { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4419 { "invept", { Gm, Mo }, PREFIX_OPCODE },
4426 { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4433 { "invpcid", { Gm, M }, PREFIX_OPCODE },
4438 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4443 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4448 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4453 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4458 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4463 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4470 { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4477 { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4484 { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4491 { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4498 { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4503 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4505 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4506 { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4511 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4513 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4514 { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4520 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
4521 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
4529 { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4536 { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4543 { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4550 { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4557 { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4564 { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4571 { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4578 { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4585 { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4592 { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4599 { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4606 { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4613 { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4620 { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4627 { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE },
4634 { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE },
4641 { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4648 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4655 { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4662 { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE },
4669 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4676 { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4681 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4688 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4691 /* PREFIX_VEX_0F10 */
4693 { VEX_W_TABLE (VEX_W_0F10_P_0) },
4694 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4695 { VEX_W_TABLE (VEX_W_0F10_P_2) },
4696 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4699 /* PREFIX_VEX_0F11 */
4701 { VEX_W_TABLE (VEX_W_0F11_P_0) },
4702 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4703 { VEX_W_TABLE (VEX_W_0F11_P_2) },
4704 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4707 /* PREFIX_VEX_0F12 */
4709 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4710 { VEX_W_TABLE (VEX_W_0F12_P_1) },
4711 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4712 { VEX_W_TABLE (VEX_W_0F12_P_3) },
4715 /* PREFIX_VEX_0F16 */
4717 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4718 { VEX_W_TABLE (VEX_W_0F16_P_1) },
4719 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4722 /* PREFIX_VEX_0F2A */
4725 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4727 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4730 /* PREFIX_VEX_0F2C */
4733 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4735 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4738 /* PREFIX_VEX_0F2D */
4741 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4743 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4746 /* PREFIX_VEX_0F2E */
4748 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4750 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4753 /* PREFIX_VEX_0F2F */
4755 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4757 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4760 /* PREFIX_VEX_0F41 */
4762 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4764 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4767 /* PREFIX_VEX_0F42 */
4769 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4771 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4774 /* PREFIX_VEX_0F44 */
4776 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4778 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4781 /* PREFIX_VEX_0F45 */
4783 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4785 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4788 /* PREFIX_VEX_0F46 */
4790 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4792 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4795 /* PREFIX_VEX_0F47 */
4797 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4799 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4802 /* PREFIX_VEX_0F4A */
4804 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4806 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4809 /* PREFIX_VEX_0F4B */
4811 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4813 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4816 /* PREFIX_VEX_0F51 */
4818 { VEX_W_TABLE (VEX_W_0F51_P_0) },
4819 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4820 { VEX_W_TABLE (VEX_W_0F51_P_2) },
4821 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4824 /* PREFIX_VEX_0F52 */
4826 { VEX_W_TABLE (VEX_W_0F52_P_0) },
4827 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4830 /* PREFIX_VEX_0F53 */
4832 { VEX_W_TABLE (VEX_W_0F53_P_0) },
4833 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4836 /* PREFIX_VEX_0F58 */
4838 { VEX_W_TABLE (VEX_W_0F58_P_0) },
4839 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4840 { VEX_W_TABLE (VEX_W_0F58_P_2) },
4841 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4844 /* PREFIX_VEX_0F59 */
4846 { VEX_W_TABLE (VEX_W_0F59_P_0) },
4847 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4848 { VEX_W_TABLE (VEX_W_0F59_P_2) },
4849 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4852 /* PREFIX_VEX_0F5A */
4854 { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4855 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4856 { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4857 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4860 /* PREFIX_VEX_0F5B */
4862 { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4863 { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4864 { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4867 /* PREFIX_VEX_0F5C */
4869 { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4870 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4871 { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4872 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4875 /* PREFIX_VEX_0F5D */
4877 { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4878 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4879 { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4880 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4883 /* PREFIX_VEX_0F5E */
4885 { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4886 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4887 { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4888 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4891 /* PREFIX_VEX_0F5F */
4893 { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4894 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4895 { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4896 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4899 /* PREFIX_VEX_0F60 */
4903 { VEX_W_TABLE (VEX_W_0F60_P_2) },
4906 /* PREFIX_VEX_0F61 */
4910 { VEX_W_TABLE (VEX_W_0F61_P_2) },
4913 /* PREFIX_VEX_0F62 */
4917 { VEX_W_TABLE (VEX_W_0F62_P_2) },
4920 /* PREFIX_VEX_0F63 */
4924 { VEX_W_TABLE (VEX_W_0F63_P_2) },
4927 /* PREFIX_VEX_0F64 */
4931 { VEX_W_TABLE (VEX_W_0F64_P_2) },
4934 /* PREFIX_VEX_0F65 */
4938 { VEX_W_TABLE (VEX_W_0F65_P_2) },
4941 /* PREFIX_VEX_0F66 */
4945 { VEX_W_TABLE (VEX_W_0F66_P_2) },
4948 /* PREFIX_VEX_0F67 */
4952 { VEX_W_TABLE (VEX_W_0F67_P_2) },
4955 /* PREFIX_VEX_0F68 */
4959 { VEX_W_TABLE (VEX_W_0F68_P_2) },
4962 /* PREFIX_VEX_0F69 */
4966 { VEX_W_TABLE (VEX_W_0F69_P_2) },
4969 /* PREFIX_VEX_0F6A */
4973 { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4976 /* PREFIX_VEX_0F6B */
4980 { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4983 /* PREFIX_VEX_0F6C */
4987 { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4990 /* PREFIX_VEX_0F6D */
4994 { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4997 /* PREFIX_VEX_0F6E */
5001 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5004 /* PREFIX_VEX_0F6F */
5007 { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5008 { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5011 /* PREFIX_VEX_0F70 */
5014 { VEX_W_TABLE (VEX_W_0F70_P_1) },
5015 { VEX_W_TABLE (VEX_W_0F70_P_2) },
5016 { VEX_W_TABLE (VEX_W_0F70_P_3) },
5019 /* PREFIX_VEX_0F71_REG_2 */
5023 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5026 /* PREFIX_VEX_0F71_REG_4 */
5030 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5033 /* PREFIX_VEX_0F71_REG_6 */
5037 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5040 /* PREFIX_VEX_0F72_REG_2 */
5044 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5047 /* PREFIX_VEX_0F72_REG_4 */
5051 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5054 /* PREFIX_VEX_0F72_REG_6 */
5058 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5061 /* PREFIX_VEX_0F73_REG_2 */
5065 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5068 /* PREFIX_VEX_0F73_REG_3 */
5072 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5075 /* PREFIX_VEX_0F73_REG_6 */
5079 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5082 /* PREFIX_VEX_0F73_REG_7 */
5086 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5089 /* PREFIX_VEX_0F74 */
5093 { VEX_W_TABLE (VEX_W_0F74_P_2) },
5096 /* PREFIX_VEX_0F75 */
5100 { VEX_W_TABLE (VEX_W_0F75_P_2) },
5103 /* PREFIX_VEX_0F76 */
5107 { VEX_W_TABLE (VEX_W_0F76_P_2) },
5110 /* PREFIX_VEX_0F77 */
5112 { VEX_W_TABLE (VEX_W_0F77_P_0) },
5115 /* PREFIX_VEX_0F7C */
5119 { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5120 { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5123 /* PREFIX_VEX_0F7D */
5127 { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5128 { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5131 /* PREFIX_VEX_0F7E */
5134 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5135 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5138 /* PREFIX_VEX_0F7F */
5141 { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5142 { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5145 /* PREFIX_VEX_0F90 */
5147 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5149 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5152 /* PREFIX_VEX_0F91 */
5154 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5156 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5159 /* PREFIX_VEX_0F92 */
5161 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5163 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5164 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5167 /* PREFIX_VEX_0F93 */
5169 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5171 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5172 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5175 /* PREFIX_VEX_0F98 */
5177 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5179 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5182 /* PREFIX_VEX_0F99 */
5184 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5186 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5189 /* PREFIX_VEX_0FC2 */
5191 { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5192 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5193 { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5194 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5197 /* PREFIX_VEX_0FC4 */
5201 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5204 /* PREFIX_VEX_0FC5 */
5208 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5211 /* PREFIX_VEX_0FD0 */
5215 { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5216 { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5219 /* PREFIX_VEX_0FD1 */
5223 { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5226 /* PREFIX_VEX_0FD2 */
5230 { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5233 /* PREFIX_VEX_0FD3 */
5237 { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5240 /* PREFIX_VEX_0FD4 */
5244 { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5247 /* PREFIX_VEX_0FD5 */
5251 { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5254 /* PREFIX_VEX_0FD6 */
5258 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5261 /* PREFIX_VEX_0FD7 */
5265 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5268 /* PREFIX_VEX_0FD8 */
5272 { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5275 /* PREFIX_VEX_0FD9 */
5279 { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5282 /* PREFIX_VEX_0FDA */
5286 { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5289 /* PREFIX_VEX_0FDB */
5293 { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5296 /* PREFIX_VEX_0FDC */
5300 { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5303 /* PREFIX_VEX_0FDD */
5307 { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5310 /* PREFIX_VEX_0FDE */
5314 { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5317 /* PREFIX_VEX_0FDF */
5321 { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5324 /* PREFIX_VEX_0FE0 */
5328 { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5331 /* PREFIX_VEX_0FE1 */
5335 { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5338 /* PREFIX_VEX_0FE2 */
5342 { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5345 /* PREFIX_VEX_0FE3 */
5349 { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5352 /* PREFIX_VEX_0FE4 */
5356 { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5359 /* PREFIX_VEX_0FE5 */
5363 { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5366 /* PREFIX_VEX_0FE6 */
5369 { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5370 { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5371 { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5374 /* PREFIX_VEX_0FE7 */
5378 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5381 /* PREFIX_VEX_0FE8 */
5385 { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5388 /* PREFIX_VEX_0FE9 */
5392 { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5395 /* PREFIX_VEX_0FEA */
5399 { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5402 /* PREFIX_VEX_0FEB */
5406 { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5409 /* PREFIX_VEX_0FEC */
5413 { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5416 /* PREFIX_VEX_0FED */
5420 { VEX_W_TABLE (VEX_W_0FED_P_2) },
5423 /* PREFIX_VEX_0FEE */
5427 { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5430 /* PREFIX_VEX_0FEF */
5434 { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5437 /* PREFIX_VEX_0FF0 */
5442 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5445 /* PREFIX_VEX_0FF1 */
5449 { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5452 /* PREFIX_VEX_0FF2 */
5456 { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5459 /* PREFIX_VEX_0FF3 */
5463 { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5466 /* PREFIX_VEX_0FF4 */
5470 { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5473 /* PREFIX_VEX_0FF5 */
5477 { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5480 /* PREFIX_VEX_0FF6 */
5484 { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5487 /* PREFIX_VEX_0FF7 */
5491 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5494 /* PREFIX_VEX_0FF8 */
5498 { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5501 /* PREFIX_VEX_0FF9 */
5505 { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5508 /* PREFIX_VEX_0FFA */
5512 { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5515 /* PREFIX_VEX_0FFB */
5519 { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5522 /* PREFIX_VEX_0FFC */
5526 { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5529 /* PREFIX_VEX_0FFD */
5533 { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5536 /* PREFIX_VEX_0FFE */
5540 { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5543 /* PREFIX_VEX_0F3800 */
5547 { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5550 /* PREFIX_VEX_0F3801 */
5554 { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5557 /* PREFIX_VEX_0F3802 */
5561 { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5564 /* PREFIX_VEX_0F3803 */
5568 { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5571 /* PREFIX_VEX_0F3804 */
5575 { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5578 /* PREFIX_VEX_0F3805 */
5582 { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5585 /* PREFIX_VEX_0F3806 */
5589 { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5592 /* PREFIX_VEX_0F3807 */
5596 { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5599 /* PREFIX_VEX_0F3808 */
5603 { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5606 /* PREFIX_VEX_0F3809 */
5610 { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5613 /* PREFIX_VEX_0F380A */
5617 { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5620 /* PREFIX_VEX_0F380B */
5624 { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5627 /* PREFIX_VEX_0F380C */
5631 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5634 /* PREFIX_VEX_0F380D */
5638 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5641 /* PREFIX_VEX_0F380E */
5645 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5648 /* PREFIX_VEX_0F380F */
5652 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5655 /* PREFIX_VEX_0F3813 */
5659 { "vcvtph2ps", { XM, EXxmmq }, 0 },
5662 /* PREFIX_VEX_0F3816 */
5666 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5669 /* PREFIX_VEX_0F3817 */
5673 { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5676 /* PREFIX_VEX_0F3818 */
5680 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5683 /* PREFIX_VEX_0F3819 */
5687 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5690 /* PREFIX_VEX_0F381A */
5694 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5697 /* PREFIX_VEX_0F381C */
5701 { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5704 /* PREFIX_VEX_0F381D */
5708 { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5711 /* PREFIX_VEX_0F381E */
5715 { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5718 /* PREFIX_VEX_0F3820 */
5722 { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5725 /* PREFIX_VEX_0F3821 */
5729 { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5732 /* PREFIX_VEX_0F3822 */
5736 { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5739 /* PREFIX_VEX_0F3823 */
5743 { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5746 /* PREFIX_VEX_0F3824 */
5750 { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5753 /* PREFIX_VEX_0F3825 */
5757 { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5760 /* PREFIX_VEX_0F3828 */
5764 { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5767 /* PREFIX_VEX_0F3829 */
5771 { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5774 /* PREFIX_VEX_0F382A */
5778 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5781 /* PREFIX_VEX_0F382B */
5785 { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5788 /* PREFIX_VEX_0F382C */
5792 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5795 /* PREFIX_VEX_0F382D */
5799 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5802 /* PREFIX_VEX_0F382E */
5806 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5809 /* PREFIX_VEX_0F382F */
5813 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5816 /* PREFIX_VEX_0F3830 */
5820 { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5823 /* PREFIX_VEX_0F3831 */
5827 { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5830 /* PREFIX_VEX_0F3832 */
5834 { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5837 /* PREFIX_VEX_0F3833 */
5841 { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5844 /* PREFIX_VEX_0F3834 */
5848 { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5851 /* PREFIX_VEX_0F3835 */
5855 { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5858 /* PREFIX_VEX_0F3836 */
5862 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5865 /* PREFIX_VEX_0F3837 */
5869 { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5872 /* PREFIX_VEX_0F3838 */
5876 { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5879 /* PREFIX_VEX_0F3839 */
5883 { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5886 /* PREFIX_VEX_0F383A */
5890 { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5893 /* PREFIX_VEX_0F383B */
5897 { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5900 /* PREFIX_VEX_0F383C */
5904 { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5907 /* PREFIX_VEX_0F383D */
5911 { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5914 /* PREFIX_VEX_0F383E */
5918 { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5921 /* PREFIX_VEX_0F383F */
5925 { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5928 /* PREFIX_VEX_0F3840 */
5932 { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5935 /* PREFIX_VEX_0F3841 */
5939 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5942 /* PREFIX_VEX_0F3845 */
5946 { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5949 /* PREFIX_VEX_0F3846 */
5953 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5956 /* PREFIX_VEX_0F3847 */
5960 { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5963 /* PREFIX_VEX_0F3858 */
5967 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5970 /* PREFIX_VEX_0F3859 */
5974 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5977 /* PREFIX_VEX_0F385A */
5981 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5984 /* PREFIX_VEX_0F3878 */
5988 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5991 /* PREFIX_VEX_0F3879 */
5995 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5998 /* PREFIX_VEX_0F388C */
6002 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6005 /* PREFIX_VEX_0F388E */
6009 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6012 /* PREFIX_VEX_0F3890 */
6016 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6019 /* PREFIX_VEX_0F3891 */
6023 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6026 /* PREFIX_VEX_0F3892 */
6030 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6033 /* PREFIX_VEX_0F3893 */
6037 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6040 /* PREFIX_VEX_0F3896 */
6044 { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6047 /* PREFIX_VEX_0F3897 */
6051 { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6054 /* PREFIX_VEX_0F3898 */
6058 { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6061 /* PREFIX_VEX_0F3899 */
6065 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6068 /* PREFIX_VEX_0F389A */
6072 { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6075 /* PREFIX_VEX_0F389B */
6079 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6082 /* PREFIX_VEX_0F389C */
6086 { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6089 /* PREFIX_VEX_0F389D */
6093 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6096 /* PREFIX_VEX_0F389E */
6100 { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6103 /* PREFIX_VEX_0F389F */
6107 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6110 /* PREFIX_VEX_0F38A6 */
6114 { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6118 /* PREFIX_VEX_0F38A7 */
6122 { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6125 /* PREFIX_VEX_0F38A8 */
6129 { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6132 /* PREFIX_VEX_0F38A9 */
6136 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6139 /* PREFIX_VEX_0F38AA */
6143 { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6146 /* PREFIX_VEX_0F38AB */
6150 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6153 /* PREFIX_VEX_0F38AC */
6157 { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6160 /* PREFIX_VEX_0F38AD */
6164 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6167 /* PREFIX_VEX_0F38AE */
6171 { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6174 /* PREFIX_VEX_0F38AF */
6178 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6181 /* PREFIX_VEX_0F38B6 */
6185 { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6188 /* PREFIX_VEX_0F38B7 */
6192 { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6195 /* PREFIX_VEX_0F38B8 */
6199 { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6202 /* PREFIX_VEX_0F38B9 */
6206 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6209 /* PREFIX_VEX_0F38BA */
6213 { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6216 /* PREFIX_VEX_0F38BB */
6220 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6223 /* PREFIX_VEX_0F38BC */
6227 { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6230 /* PREFIX_VEX_0F38BD */
6234 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6237 /* PREFIX_VEX_0F38BE */
6241 { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6244 /* PREFIX_VEX_0F38BF */
6248 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6251 /* PREFIX_VEX_0F38DB */
6255 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6258 /* PREFIX_VEX_0F38DC */
6262 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6265 /* PREFIX_VEX_0F38DD */
6269 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6272 /* PREFIX_VEX_0F38DE */
6276 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6279 /* PREFIX_VEX_0F38DF */
6283 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6286 /* PREFIX_VEX_0F38F2 */
6288 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6291 /* PREFIX_VEX_0F38F3_REG_1 */
6293 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6296 /* PREFIX_VEX_0F38F3_REG_2 */
6298 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6301 /* PREFIX_VEX_0F38F3_REG_3 */
6303 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6306 /* PREFIX_VEX_0F38F5 */
6308 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6309 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6311 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6314 /* PREFIX_VEX_0F38F6 */
6319 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6322 /* PREFIX_VEX_0F38F7 */
6324 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6325 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6326 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6327 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6330 /* PREFIX_VEX_0F3A00 */
6334 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6337 /* PREFIX_VEX_0F3A01 */
6341 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6344 /* PREFIX_VEX_0F3A02 */
6348 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6351 /* PREFIX_VEX_0F3A04 */
6355 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6358 /* PREFIX_VEX_0F3A05 */
6362 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6365 /* PREFIX_VEX_0F3A06 */
6369 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6372 /* PREFIX_VEX_0F3A08 */
6376 { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6379 /* PREFIX_VEX_0F3A09 */
6383 { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6386 /* PREFIX_VEX_0F3A0A */
6390 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6393 /* PREFIX_VEX_0F3A0B */
6397 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6400 /* PREFIX_VEX_0F3A0C */
6404 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6407 /* PREFIX_VEX_0F3A0D */
6411 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6414 /* PREFIX_VEX_0F3A0E */
6418 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6421 /* PREFIX_VEX_0F3A0F */
6425 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6428 /* PREFIX_VEX_0F3A14 */
6432 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6435 /* PREFIX_VEX_0F3A15 */
6439 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6442 /* PREFIX_VEX_0F3A16 */
6446 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6449 /* PREFIX_VEX_0F3A17 */
6453 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6456 /* PREFIX_VEX_0F3A18 */
6460 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6463 /* PREFIX_VEX_0F3A19 */
6467 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6470 /* PREFIX_VEX_0F3A1D */
6474 { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6477 /* PREFIX_VEX_0F3A20 */
6481 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6484 /* PREFIX_VEX_0F3A21 */
6488 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6491 /* PREFIX_VEX_0F3A22 */
6495 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6498 /* PREFIX_VEX_0F3A30 */
6502 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6505 /* PREFIX_VEX_0F3A31 */
6509 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6512 /* PREFIX_VEX_0F3A32 */
6516 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6519 /* PREFIX_VEX_0F3A33 */
6523 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6526 /* PREFIX_VEX_0F3A38 */
6530 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6533 /* PREFIX_VEX_0F3A39 */
6537 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6540 /* PREFIX_VEX_0F3A40 */
6544 { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6547 /* PREFIX_VEX_0F3A41 */
6551 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6554 /* PREFIX_VEX_0F3A42 */
6558 { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6561 /* PREFIX_VEX_0F3A44 */
6565 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6568 /* PREFIX_VEX_0F3A46 */
6572 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6575 /* PREFIX_VEX_0F3A48 */
6579 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6582 /* PREFIX_VEX_0F3A49 */
6586 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6589 /* PREFIX_VEX_0F3A4A */
6593 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6596 /* PREFIX_VEX_0F3A4B */
6600 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6603 /* PREFIX_VEX_0F3A4C */
6607 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6610 /* PREFIX_VEX_0F3A5C */
6614 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6617 /* PREFIX_VEX_0F3A5D */
6621 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6624 /* PREFIX_VEX_0F3A5E */
6628 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6631 /* PREFIX_VEX_0F3A5F */
6635 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6638 /* PREFIX_VEX_0F3A60 */
6642 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6646 /* PREFIX_VEX_0F3A61 */
6650 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6653 /* PREFIX_VEX_0F3A62 */
6657 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6660 /* PREFIX_VEX_0F3A63 */
6664 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6667 /* PREFIX_VEX_0F3A68 */
6671 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6674 /* PREFIX_VEX_0F3A69 */
6678 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6681 /* PREFIX_VEX_0F3A6A */
6685 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6688 /* PREFIX_VEX_0F3A6B */
6692 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6695 /* PREFIX_VEX_0F3A6C */
6699 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6702 /* PREFIX_VEX_0F3A6D */
6706 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6709 /* PREFIX_VEX_0F3A6E */
6713 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6716 /* PREFIX_VEX_0F3A6F */
6720 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6723 /* PREFIX_VEX_0F3A78 */
6727 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6730 /* PREFIX_VEX_0F3A79 */
6734 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6737 /* PREFIX_VEX_0F3A7A */
6741 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6744 /* PREFIX_VEX_0F3A7B */
6748 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6751 /* PREFIX_VEX_0F3A7C */
6755 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6759 /* PREFIX_VEX_0F3A7D */
6763 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6766 /* PREFIX_VEX_0F3A7E */
6770 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6773 /* PREFIX_VEX_0F3A7F */
6777 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6780 /* PREFIX_VEX_0F3ADF */
6784 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6787 /* PREFIX_VEX_0F3AF0 */
6792 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6795 #define NEED_PREFIX_TABLE
6796 #include "i386-dis-evex.h"
6797 #undef NEED_PREFIX_TABLE
6800 static const struct dis386 x86_64_table[][2] = {
6803 { "pushP", { es }, 0 },
6808 { "popP", { es }, 0 },
6813 { "pushP", { cs }, 0 },
6818 { "pushP", { ss }, 0 },
6823 { "popP", { ss }, 0 },
6828 { "pushP", { ds }, 0 },
6833 { "popP", { ds }, 0 },
6838 { "daa", { XX }, 0 },
6843 { "das", { XX }, 0 },
6848 { "aaa", { XX }, 0 },
6853 { "aas", { XX }, 0 },
6858 { "pushaP", { XX }, 0 },
6863 { "popaP", { XX }, 0 },
6868 { MOD_TABLE (MOD_62_32BIT) },
6869 { EVEX_TABLE (EVEX_0F) },
6874 { "arpl", { Ew, Gw }, 0 },
6875 { "movs{lq|xd}", { Gv, Ed }, 0 },
6880 { "ins{R|}", { Yzr, indirDX }, 0 },
6881 { "ins{G|}", { Yzr, indirDX }, 0 },
6886 { "outs{R|}", { indirDXr, Xz }, 0 },
6887 { "outs{G|}", { indirDXr, Xz }, 0 },
6892 { "Jcall{T|}", { Ap }, 0 },
6897 { MOD_TABLE (MOD_C4_32BIT) },
6898 { VEX_C4_TABLE (VEX_0F) },
6903 { MOD_TABLE (MOD_C5_32BIT) },
6904 { VEX_C5_TABLE (VEX_0F) },
6909 { "into", { XX }, 0 },
6914 { "aam", { Ib }, 0 },
6919 { "aad", { Ib }, 0 },
6924 { "callP", { Jv, BND }, 0 },
6925 { "call@", { Jv, BND }, 0 }
6930 { "jmpP", { Jv, BND }, 0 },
6931 { "jmp@", { Jv, BND }, 0 }
6936 { "Jjmp{T|}", { Ap }, 0 },
6939 /* X86_64_0F01_REG_0 */
6941 { "sgdt{Q|IQ}", { M }, 0 },
6942 { "sgdt", { M }, 0 },
6945 /* X86_64_0F01_REG_1 */
6947 { "sidt{Q|IQ}", { M }, 0 },
6948 { "sidt", { M }, 0 },
6951 /* X86_64_0F01_REG_2 */
6953 { "lgdt{Q|Q}", { M }, 0 },
6954 { "lgdt", { M }, 0 },
6957 /* X86_64_0F01_REG_3 */
6959 { "lidt{Q|Q}", { M }, 0 },
6960 { "lidt", { M }, 0 },
6964 static const struct dis386 three_byte_table[][256] = {
6966 /* THREE_BYTE_0F38 */
6969 { "pshufb", { MX, EM }, PREFIX_OPCODE },
6970 { "phaddw", { MX, EM }, PREFIX_OPCODE },
6971 { "phaddd", { MX, EM }, PREFIX_OPCODE },
6972 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
6973 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
6974 { "phsubw", { MX, EM }, PREFIX_OPCODE },
6975 { "phsubd", { MX, EM }, PREFIX_OPCODE },
6976 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
6978 { "psignb", { MX, EM }, PREFIX_OPCODE },
6979 { "psignw", { MX, EM }, PREFIX_OPCODE },
6980 { "psignd", { MX, EM }, PREFIX_OPCODE },
6981 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
6987 { PREFIX_TABLE (PREFIX_0F3810) },
6991 { PREFIX_TABLE (PREFIX_0F3814) },
6992 { PREFIX_TABLE (PREFIX_0F3815) },
6994 { PREFIX_TABLE (PREFIX_0F3817) },
7000 { "pabsb", { MX, EM }, PREFIX_OPCODE },
7001 { "pabsw", { MX, EM }, PREFIX_OPCODE },
7002 { "pabsd", { MX, EM }, PREFIX_OPCODE },
7005 { PREFIX_TABLE (PREFIX_0F3820) },
7006 { PREFIX_TABLE (PREFIX_0F3821) },
7007 { PREFIX_TABLE (PREFIX_0F3822) },
7008 { PREFIX_TABLE (PREFIX_0F3823) },
7009 { PREFIX_TABLE (PREFIX_0F3824) },
7010 { PREFIX_TABLE (PREFIX_0F3825) },
7014 { PREFIX_TABLE (PREFIX_0F3828) },
7015 { PREFIX_TABLE (PREFIX_0F3829) },
7016 { PREFIX_TABLE (PREFIX_0F382A) },
7017 { PREFIX_TABLE (PREFIX_0F382B) },
7023 { PREFIX_TABLE (PREFIX_0F3830) },
7024 { PREFIX_TABLE (PREFIX_0F3831) },
7025 { PREFIX_TABLE (PREFIX_0F3832) },
7026 { PREFIX_TABLE (PREFIX_0F3833) },
7027 { PREFIX_TABLE (PREFIX_0F3834) },
7028 { PREFIX_TABLE (PREFIX_0F3835) },
7030 { PREFIX_TABLE (PREFIX_0F3837) },
7032 { PREFIX_TABLE (PREFIX_0F3838) },
7033 { PREFIX_TABLE (PREFIX_0F3839) },
7034 { PREFIX_TABLE (PREFIX_0F383A) },
7035 { PREFIX_TABLE (PREFIX_0F383B) },
7036 { PREFIX_TABLE (PREFIX_0F383C) },
7037 { PREFIX_TABLE (PREFIX_0F383D) },
7038 { PREFIX_TABLE (PREFIX_0F383E) },
7039 { PREFIX_TABLE (PREFIX_0F383F) },
7041 { PREFIX_TABLE (PREFIX_0F3840) },
7042 { PREFIX_TABLE (PREFIX_0F3841) },
7113 { PREFIX_TABLE (PREFIX_0F3880) },
7114 { PREFIX_TABLE (PREFIX_0F3881) },
7115 { PREFIX_TABLE (PREFIX_0F3882) },
7194 { PREFIX_TABLE (PREFIX_0F38C8) },
7195 { PREFIX_TABLE (PREFIX_0F38C9) },
7196 { PREFIX_TABLE (PREFIX_0F38CA) },
7197 { PREFIX_TABLE (PREFIX_0F38CB) },
7198 { PREFIX_TABLE (PREFIX_0F38CC) },
7199 { PREFIX_TABLE (PREFIX_0F38CD) },
7215 { PREFIX_TABLE (PREFIX_0F38DB) },
7216 { PREFIX_TABLE (PREFIX_0F38DC) },
7217 { PREFIX_TABLE (PREFIX_0F38DD) },
7218 { PREFIX_TABLE (PREFIX_0F38DE) },
7219 { PREFIX_TABLE (PREFIX_0F38DF) },
7239 { PREFIX_TABLE (PREFIX_0F38F0) },
7240 { PREFIX_TABLE (PREFIX_0F38F1) },
7245 { PREFIX_TABLE (PREFIX_0F38F6) },
7257 /* THREE_BYTE_0F3A */
7269 { PREFIX_TABLE (PREFIX_0F3A08) },
7270 { PREFIX_TABLE (PREFIX_0F3A09) },
7271 { PREFIX_TABLE (PREFIX_0F3A0A) },
7272 { PREFIX_TABLE (PREFIX_0F3A0B) },
7273 { PREFIX_TABLE (PREFIX_0F3A0C) },
7274 { PREFIX_TABLE (PREFIX_0F3A0D) },
7275 { PREFIX_TABLE (PREFIX_0F3A0E) },
7276 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
7282 { PREFIX_TABLE (PREFIX_0F3A14) },
7283 { PREFIX_TABLE (PREFIX_0F3A15) },
7284 { PREFIX_TABLE (PREFIX_0F3A16) },
7285 { PREFIX_TABLE (PREFIX_0F3A17) },
7296 { PREFIX_TABLE (PREFIX_0F3A20) },
7297 { PREFIX_TABLE (PREFIX_0F3A21) },
7298 { PREFIX_TABLE (PREFIX_0F3A22) },
7332 { PREFIX_TABLE (PREFIX_0F3A40) },
7333 { PREFIX_TABLE (PREFIX_0F3A41) },
7334 { PREFIX_TABLE (PREFIX_0F3A42) },
7336 { PREFIX_TABLE (PREFIX_0F3A44) },
7368 { PREFIX_TABLE (PREFIX_0F3A60) },
7369 { PREFIX_TABLE (PREFIX_0F3A61) },
7370 { PREFIX_TABLE (PREFIX_0F3A62) },
7371 { PREFIX_TABLE (PREFIX_0F3A63) },
7489 { PREFIX_TABLE (PREFIX_0F3ACC) },
7510 { PREFIX_TABLE (PREFIX_0F3ADF) },
7549 /* THREE_BYTE_0F7A */
7625 { "phaddbw", { XM, EXq }, PREFIX_OPCODE },
7626 { "phaddbd", { XM, EXq }, PREFIX_OPCODE },
7627 { "phaddbq", { XM, EXq }, PREFIX_OPCODE },
7630 { "phaddwd", { XM, EXq }, PREFIX_OPCODE },
7631 { "phaddwq", { XM, EXq }, PREFIX_OPCODE },
7636 { "phadddq", { XM, EXq }, PREFIX_OPCODE },
7643 { "phaddubw", { XM, EXq }, PREFIX_OPCODE },
7644 { "phaddubd", { XM, EXq }, PREFIX_OPCODE },
7645 { "phaddubq", { XM, EXq }, PREFIX_OPCODE },
7648 { "phadduwd", { XM, EXq }, PREFIX_OPCODE },
7649 { "phadduwq", { XM, EXq }, PREFIX_OPCODE },
7654 { "phaddudq", { XM, EXq }, PREFIX_OPCODE },
7661 { "phsubbw", { XM, EXq }, PREFIX_OPCODE },
7662 { "phsubbd", { XM, EXq }, PREFIX_OPCODE },
7663 { "phsubbq", { XM, EXq }, PREFIX_OPCODE },
7842 static const struct dis386 xop_table[][256] = {
7995 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7996 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7997 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8005 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8006 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8013 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8014 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8015 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8023 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8024 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8028 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8029 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8032 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8050 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8062 { "vprotb", { XM, Vex_2src_1, Ib }, 0 },
8063 { "vprotw", { XM, Vex_2src_1, Ib }, 0 },
8064 { "vprotd", { XM, Vex_2src_1, Ib }, 0 },
8065 { "vprotq", { XM, Vex_2src_1, Ib }, 0 },
8075 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
8076 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
8077 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
8078 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
8111 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8112 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8113 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8114 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8138 { REG_TABLE (REG_XOP_TBM_01) },
8139 { REG_TABLE (REG_XOP_TBM_02) },
8157 { REG_TABLE (REG_XOP_LWPCB) },
8281 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8282 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8283 { "vfrczss", { XM, EXd }, 0 },
8284 { "vfrczsd", { XM, EXq }, 0 },
8299 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8300 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8301 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8302 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8303 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8304 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8305 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8306 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8308 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8309 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8310 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8311 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8354 { "vphaddbw", { XM, EXxmm }, 0 },
8355 { "vphaddbd", { XM, EXxmm }, 0 },
8356 { "vphaddbq", { XM, EXxmm }, 0 },
8359 { "vphaddwd", { XM, EXxmm }, 0 },
8360 { "vphaddwq", { XM, EXxmm }, 0 },
8365 { "vphadddq", { XM, EXxmm }, 0 },
8372 { "vphaddubw", { XM, EXxmm }, 0 },
8373 { "vphaddubd", { XM, EXxmm }, 0 },
8374 { "vphaddubq", { XM, EXxmm }, 0 },
8377 { "vphadduwd", { XM, EXxmm }, 0 },
8378 { "vphadduwq", { XM, EXxmm }, 0 },
8383 { "vphaddudq", { XM, EXxmm }, 0 },
8390 { "vphsubbw", { XM, EXxmm }, 0 },
8391 { "vphsubwd", { XM, EXxmm }, 0 },
8392 { "vphsubdq", { XM, EXxmm }, 0 },
8446 { "bextr", { Gv, Ev, Iq }, 0 },
8448 { REG_TABLE (REG_XOP_LWP) },
8718 static const struct dis386 vex_table[][256] = {
8740 { PREFIX_TABLE (PREFIX_VEX_0F10) },
8741 { PREFIX_TABLE (PREFIX_VEX_0F11) },
8742 { PREFIX_TABLE (PREFIX_VEX_0F12) },
8743 { MOD_TABLE (MOD_VEX_0F13) },
8744 { VEX_W_TABLE (VEX_W_0F14) },
8745 { VEX_W_TABLE (VEX_W_0F15) },
8746 { PREFIX_TABLE (PREFIX_VEX_0F16) },
8747 { MOD_TABLE (MOD_VEX_0F17) },
8767 { VEX_W_TABLE (VEX_W_0F28) },
8768 { VEX_W_TABLE (VEX_W_0F29) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8770 { MOD_TABLE (MOD_VEX_0F2B) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8795 { PREFIX_TABLE (PREFIX_VEX_0F41) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F42) },
8798 { PREFIX_TABLE (PREFIX_VEX_0F44) },
8799 { PREFIX_TABLE (PREFIX_VEX_0F45) },
8800 { PREFIX_TABLE (PREFIX_VEX_0F46) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F47) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8806 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8812 { MOD_TABLE (MOD_VEX_0F50) },
8813 { PREFIX_TABLE (PREFIX_VEX_0F51) },
8814 { PREFIX_TABLE (PREFIX_VEX_0F52) },
8815 { PREFIX_TABLE (PREFIX_VEX_0F53) },
8816 { "vandpX", { XM, Vex, EXx }, 0 },
8817 { "vandnpX", { XM, Vex, EXx }, 0 },
8818 { "vorpX", { XM, Vex, EXx }, 0 },
8819 { "vxorpX", { XM, Vex, EXx }, 0 },
8821 { PREFIX_TABLE (PREFIX_VEX_0F58) },
8822 { PREFIX_TABLE (PREFIX_VEX_0F59) },
8823 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8824 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8825 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8826 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8827 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8828 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8830 { PREFIX_TABLE (PREFIX_VEX_0F60) },
8831 { PREFIX_TABLE (PREFIX_VEX_0F61) },
8832 { PREFIX_TABLE (PREFIX_VEX_0F62) },
8833 { PREFIX_TABLE (PREFIX_VEX_0F63) },
8834 { PREFIX_TABLE (PREFIX_VEX_0F64) },
8835 { PREFIX_TABLE (PREFIX_VEX_0F65) },
8836 { PREFIX_TABLE (PREFIX_VEX_0F66) },
8837 { PREFIX_TABLE (PREFIX_VEX_0F67) },
8839 { PREFIX_TABLE (PREFIX_VEX_0F68) },
8840 { PREFIX_TABLE (PREFIX_VEX_0F69) },
8841 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8842 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8843 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8844 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8845 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8846 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8848 { PREFIX_TABLE (PREFIX_VEX_0F70) },
8849 { REG_TABLE (REG_VEX_0F71) },
8850 { REG_TABLE (REG_VEX_0F72) },
8851 { REG_TABLE (REG_VEX_0F73) },
8852 { PREFIX_TABLE (PREFIX_VEX_0F74) },
8853 { PREFIX_TABLE (PREFIX_VEX_0F75) },
8854 { PREFIX_TABLE (PREFIX_VEX_0F76) },
8855 { PREFIX_TABLE (PREFIX_VEX_0F77) },
8861 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8862 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8863 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8864 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8884 { PREFIX_TABLE (PREFIX_VEX_0F90) },
8885 { PREFIX_TABLE (PREFIX_VEX_0F91) },
8886 { PREFIX_TABLE (PREFIX_VEX_0F92) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F93) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F98) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F99) },
8917 { REG_TABLE (REG_VEX_0FAE) },
8940 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8942 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8943 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8944 { "vshufpX", { XM, Vex, EXx, Ib }, 0 },
8956 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8957 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8958 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8959 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8960 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8961 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8962 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8963 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8965 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8966 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8967 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8968 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8969 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8970 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8971 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8972 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8974 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8975 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8976 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8977 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8978 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8979 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8980 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8981 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8983 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8984 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8985 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8986 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8987 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8988 { PREFIX_TABLE (PREFIX_VEX_0FED) },
8989 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8990 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8992 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8993 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8994 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8995 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8996 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8997 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8998 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8999 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
9001 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
9002 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
9003 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
9004 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
9005 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
9006 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
9007 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
9013 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
9014 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
9015 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
9017 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
9020 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
9022 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
9024 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
9026 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
9027 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
9028 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
9029 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
9034 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
9037 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
9038 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
9046 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
9049 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
9050 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
9051 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
9052 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
9053 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
9054 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
9058 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
9059 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
9061 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
9062 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
9063 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
9064 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
9065 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
9067 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
9068 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
9077 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
9078 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
9079 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
9080 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
9081 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
9082 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
9083 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
9085 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
9086 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
9112 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9113 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9114 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9148 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9149 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9170 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9172 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9175 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9176 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9177 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9178 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9181 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9182 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9184 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9185 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9186 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9187 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9188 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9189 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9190 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9191 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9199 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9200 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9202 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9203 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9204 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9205 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9206 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9207 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9208 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9209 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9217 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9218 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9220 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9221 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9222 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9223 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9224 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9225 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9226 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9227 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9259 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9260 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9261 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9262 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9263 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9285 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9286 { REG_TABLE (REG_VEX_0F38F3) },
9288 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9289 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9290 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9304 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9305 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9306 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9308 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9309 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9310 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9313 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9314 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9315 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9316 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9317 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9318 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9319 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9320 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9326 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9327 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9328 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9329 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9331 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9332 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9336 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9340 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9341 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9342 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9358 { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9359 { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9360 { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9361 { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9367 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9368 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9376 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9377 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9378 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9380 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9382 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9385 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9386 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9387 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9388 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9389 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9407 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9408 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9409 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9410 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9412 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9413 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9414 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9415 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9421 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9422 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9423 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9424 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9425 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9426 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9427 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9428 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9439 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9440 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9441 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9442 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9443 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9444 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9445 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9446 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9554 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9574 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9594 #define NEED_OPCODE_TABLE
9595 #include "i386-dis-evex.h"
9596 #undef NEED_OPCODE_TABLE
9597 static const struct dis386 vex_len_table[][2] = {
9598 /* VEX_LEN_0F10_P_1 */
9600 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9601 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9604 /* VEX_LEN_0F10_P_3 */
9606 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9607 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9610 /* VEX_LEN_0F11_P_1 */
9612 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9613 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9616 /* VEX_LEN_0F11_P_3 */
9618 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9619 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9622 /* VEX_LEN_0F12_P_0_M_0 */
9624 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9627 /* VEX_LEN_0F12_P_0_M_1 */
9629 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9632 /* VEX_LEN_0F12_P_2 */
9634 { VEX_W_TABLE (VEX_W_0F12_P_2) },
9637 /* VEX_LEN_0F13_M_0 */
9639 { VEX_W_TABLE (VEX_W_0F13_M_0) },
9642 /* VEX_LEN_0F16_P_0_M_0 */
9644 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9647 /* VEX_LEN_0F16_P_0_M_1 */
9649 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9652 /* VEX_LEN_0F16_P_2 */
9654 { VEX_W_TABLE (VEX_W_0F16_P_2) },
9657 /* VEX_LEN_0F17_M_0 */
9659 { VEX_W_TABLE (VEX_W_0F17_M_0) },
9662 /* VEX_LEN_0F2A_P_1 */
9664 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9665 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9668 /* VEX_LEN_0F2A_P_3 */
9670 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9671 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9674 /* VEX_LEN_0F2C_P_1 */
9676 { "vcvttss2siY", { Gv, EXdScalar }, 0 },
9677 { "vcvttss2siY", { Gv, EXdScalar }, 0 },
9680 /* VEX_LEN_0F2C_P_3 */
9682 { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
9683 { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
9686 /* VEX_LEN_0F2D_P_1 */
9688 { "vcvtss2siY", { Gv, EXdScalar }, 0 },
9689 { "vcvtss2siY", { Gv, EXdScalar }, 0 },
9692 /* VEX_LEN_0F2D_P_3 */
9694 { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
9695 { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
9698 /* VEX_LEN_0F2E_P_0 */
9700 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9701 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9704 /* VEX_LEN_0F2E_P_2 */
9706 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9707 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9710 /* VEX_LEN_0F2F_P_0 */
9712 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9713 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9716 /* VEX_LEN_0F2F_P_2 */
9718 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9719 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9722 /* VEX_LEN_0F41_P_0 */
9725 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9727 /* VEX_LEN_0F41_P_2 */
9730 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9732 /* VEX_LEN_0F42_P_0 */
9735 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9737 /* VEX_LEN_0F42_P_2 */
9740 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9742 /* VEX_LEN_0F44_P_0 */
9744 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9746 /* VEX_LEN_0F44_P_2 */
9748 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9750 /* VEX_LEN_0F45_P_0 */
9753 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9755 /* VEX_LEN_0F45_P_2 */
9758 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9760 /* VEX_LEN_0F46_P_0 */
9763 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9765 /* VEX_LEN_0F46_P_2 */
9768 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9770 /* VEX_LEN_0F47_P_0 */
9773 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9775 /* VEX_LEN_0F47_P_2 */
9778 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9780 /* VEX_LEN_0F4A_P_0 */
9783 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9785 /* VEX_LEN_0F4A_P_2 */
9788 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9790 /* VEX_LEN_0F4B_P_0 */
9793 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9795 /* VEX_LEN_0F4B_P_2 */
9798 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9801 /* VEX_LEN_0F51_P_1 */
9803 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9804 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9807 /* VEX_LEN_0F51_P_3 */
9809 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9810 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9813 /* VEX_LEN_0F52_P_1 */
9815 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9816 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9819 /* VEX_LEN_0F53_P_1 */
9821 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9822 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9825 /* VEX_LEN_0F58_P_1 */
9827 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9828 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9831 /* VEX_LEN_0F58_P_3 */
9833 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9834 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9837 /* VEX_LEN_0F59_P_1 */
9839 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9840 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9843 /* VEX_LEN_0F59_P_3 */
9845 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9846 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9849 /* VEX_LEN_0F5A_P_1 */
9851 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9852 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9855 /* VEX_LEN_0F5A_P_3 */
9857 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9858 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9861 /* VEX_LEN_0F5C_P_1 */
9863 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9864 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9867 /* VEX_LEN_0F5C_P_3 */
9869 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9870 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9873 /* VEX_LEN_0F5D_P_1 */
9875 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9876 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9879 /* VEX_LEN_0F5D_P_3 */
9881 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9882 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9885 /* VEX_LEN_0F5E_P_1 */
9887 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9888 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9891 /* VEX_LEN_0F5E_P_3 */
9893 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9894 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9897 /* VEX_LEN_0F5F_P_1 */
9899 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9900 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9903 /* VEX_LEN_0F5F_P_3 */
9905 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9906 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9909 /* VEX_LEN_0F6E_P_2 */
9911 { "vmovK", { XMScalar, Edq }, 0 },
9912 { "vmovK", { XMScalar, Edq }, 0 },
9915 /* VEX_LEN_0F7E_P_1 */
9917 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9918 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9921 /* VEX_LEN_0F7E_P_2 */
9923 { "vmovK", { Edq, XMScalar }, 0 },
9924 { "vmovK", { Edq, XMScalar }, 0 },
9927 /* VEX_LEN_0F90_P_0 */
9929 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9932 /* VEX_LEN_0F90_P_2 */
9934 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9937 /* VEX_LEN_0F91_P_0 */
9939 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9942 /* VEX_LEN_0F91_P_2 */
9944 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9947 /* VEX_LEN_0F92_P_0 */
9949 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9952 /* VEX_LEN_0F92_P_2 */
9954 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9957 /* VEX_LEN_0F92_P_3 */
9959 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9962 /* VEX_LEN_0F93_P_0 */
9964 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9967 /* VEX_LEN_0F93_P_2 */
9969 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9972 /* VEX_LEN_0F93_P_3 */
9974 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9977 /* VEX_LEN_0F98_P_0 */
9979 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9982 /* VEX_LEN_0F98_P_2 */
9984 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9987 /* VEX_LEN_0F99_P_0 */
9989 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9992 /* VEX_LEN_0F99_P_2 */
9994 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9997 /* VEX_LEN_0FAE_R_2_M_0 */
9999 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
10002 /* VEX_LEN_0FAE_R_3_M_0 */
10004 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
10007 /* VEX_LEN_0FC2_P_1 */
10009 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
10010 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
10013 /* VEX_LEN_0FC2_P_3 */
10015 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
10016 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
10019 /* VEX_LEN_0FC4_P_2 */
10021 { VEX_W_TABLE (VEX_W_0FC4_P_2) },
10024 /* VEX_LEN_0FC5_P_2 */
10026 { VEX_W_TABLE (VEX_W_0FC5_P_2) },
10029 /* VEX_LEN_0FD6_P_2 */
10031 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
10032 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
10035 /* VEX_LEN_0FF7_P_2 */
10037 { VEX_W_TABLE (VEX_W_0FF7_P_2) },
10040 /* VEX_LEN_0F3816_P_2 */
10043 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
10046 /* VEX_LEN_0F3819_P_2 */
10049 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
10052 /* VEX_LEN_0F381A_P_2_M_0 */
10055 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
10058 /* VEX_LEN_0F3836_P_2 */
10061 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
10064 /* VEX_LEN_0F3841_P_2 */
10066 { VEX_W_TABLE (VEX_W_0F3841_P_2) },
10069 /* VEX_LEN_0F385A_P_2_M_0 */
10072 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
10075 /* VEX_LEN_0F38DB_P_2 */
10077 { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
10080 /* VEX_LEN_0F38DC_P_2 */
10082 { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
10085 /* VEX_LEN_0F38DD_P_2 */
10087 { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
10090 /* VEX_LEN_0F38DE_P_2 */
10092 { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
10095 /* VEX_LEN_0F38DF_P_2 */
10097 { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
10100 /* VEX_LEN_0F38F2_P_0 */
10102 { "andnS", { Gdq, VexGdq, Edq }, 0 },
10105 /* VEX_LEN_0F38F3_R_1_P_0 */
10107 { "blsrS", { VexGdq, Edq }, 0 },
10110 /* VEX_LEN_0F38F3_R_2_P_0 */
10112 { "blsmskS", { VexGdq, Edq }, 0 },
10115 /* VEX_LEN_0F38F3_R_3_P_0 */
10117 { "blsiS", { VexGdq, Edq }, 0 },
10120 /* VEX_LEN_0F38F5_P_0 */
10122 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
10125 /* VEX_LEN_0F38F5_P_1 */
10127 { "pextS", { Gdq, VexGdq, Edq }, 0 },
10130 /* VEX_LEN_0F38F5_P_3 */
10132 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
10135 /* VEX_LEN_0F38F6_P_3 */
10137 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
10140 /* VEX_LEN_0F38F7_P_0 */
10142 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
10145 /* VEX_LEN_0F38F7_P_1 */
10147 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
10150 /* VEX_LEN_0F38F7_P_2 */
10152 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
10155 /* VEX_LEN_0F38F7_P_3 */
10157 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
10160 /* VEX_LEN_0F3A00_P_2 */
10163 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10166 /* VEX_LEN_0F3A01_P_2 */
10169 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10172 /* VEX_LEN_0F3A06_P_2 */
10175 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10178 /* VEX_LEN_0F3A0A_P_2 */
10180 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10181 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10184 /* VEX_LEN_0F3A0B_P_2 */
10186 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10187 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10190 /* VEX_LEN_0F3A14_P_2 */
10192 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10195 /* VEX_LEN_0F3A15_P_2 */
10197 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10200 /* VEX_LEN_0F3A16_P_2 */
10202 { "vpextrK", { Edq, XM, Ib }, 0 },
10205 /* VEX_LEN_0F3A17_P_2 */
10207 { "vextractps", { Edqd, XM, Ib }, 0 },
10210 /* VEX_LEN_0F3A18_P_2 */
10213 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10216 /* VEX_LEN_0F3A19_P_2 */
10219 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10222 /* VEX_LEN_0F3A20_P_2 */
10224 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10227 /* VEX_LEN_0F3A21_P_2 */
10229 { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10232 /* VEX_LEN_0F3A22_P_2 */
10234 { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 },
10237 /* VEX_LEN_0F3A30_P_2 */
10239 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10242 /* VEX_LEN_0F3A31_P_2 */
10244 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10247 /* VEX_LEN_0F3A32_P_2 */
10249 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10252 /* VEX_LEN_0F3A33_P_2 */
10254 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10257 /* VEX_LEN_0F3A38_P_2 */
10260 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10263 /* VEX_LEN_0F3A39_P_2 */
10266 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10269 /* VEX_LEN_0F3A41_P_2 */
10271 { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10274 /* VEX_LEN_0F3A44_P_2 */
10276 { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10279 /* VEX_LEN_0F3A46_P_2 */
10282 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10285 /* VEX_LEN_0F3A60_P_2 */
10287 { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10290 /* VEX_LEN_0F3A61_P_2 */
10292 { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10295 /* VEX_LEN_0F3A62_P_2 */
10297 { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10300 /* VEX_LEN_0F3A63_P_2 */
10302 { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10305 /* VEX_LEN_0F3A6A_P_2 */
10307 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10310 /* VEX_LEN_0F3A6B_P_2 */
10312 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10315 /* VEX_LEN_0F3A6E_P_2 */
10317 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10320 /* VEX_LEN_0F3A6F_P_2 */
10322 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10325 /* VEX_LEN_0F3A7A_P_2 */
10327 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10330 /* VEX_LEN_0F3A7B_P_2 */
10332 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10335 /* VEX_LEN_0F3A7E_P_2 */
10337 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10340 /* VEX_LEN_0F3A7F_P_2 */
10342 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10345 /* VEX_LEN_0F3ADF_P_2 */
10347 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10350 /* VEX_LEN_0F3AF0_P_3 */
10352 { "rorxS", { Gdq, Edq, Ib }, 0 },
10355 /* VEX_LEN_0FXOP_08_CC */
10357 { "vpcomb", { XM, Vex128, EXx, Ib }, 0 },
10360 /* VEX_LEN_0FXOP_08_CD */
10362 { "vpcomw", { XM, Vex128, EXx, Ib }, 0 },
10365 /* VEX_LEN_0FXOP_08_CE */
10367 { "vpcomd", { XM, Vex128, EXx, Ib }, 0 },
10370 /* VEX_LEN_0FXOP_08_CF */
10372 { "vpcomq", { XM, Vex128, EXx, Ib }, 0 },
10375 /* VEX_LEN_0FXOP_08_EC */
10377 { "vpcomub", { XM, Vex128, EXx, Ib }, 0 },
10380 /* VEX_LEN_0FXOP_08_ED */
10382 { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 },
10385 /* VEX_LEN_0FXOP_08_EE */
10387 { "vpcomud", { XM, Vex128, EXx, Ib }, 0 },
10390 /* VEX_LEN_0FXOP_08_EF */
10392 { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 },
10395 /* VEX_LEN_0FXOP_09_80 */
10397 { "vfrczps", { XM, EXxmm }, 0 },
10398 { "vfrczps", { XM, EXymmq }, 0 },
10401 /* VEX_LEN_0FXOP_09_81 */
10403 { "vfrczpd", { XM, EXxmm }, 0 },
10404 { "vfrczpd", { XM, EXymmq }, 0 },
10408 static const struct dis386 vex_w_table[][2] = {
10410 /* VEX_W_0F10_P_0 */
10411 { "vmovups", { XM, EXx }, 0 },
10414 /* VEX_W_0F10_P_1 */
10415 { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
10418 /* VEX_W_0F10_P_2 */
10419 { "vmovupd", { XM, EXx }, 0 },
10422 /* VEX_W_0F10_P_3 */
10423 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
10426 /* VEX_W_0F11_P_0 */
10427 { "vmovups", { EXxS, XM }, 0 },
10430 /* VEX_W_0F11_P_1 */
10431 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10434 /* VEX_W_0F11_P_2 */
10435 { "vmovupd", { EXxS, XM }, 0 },
10438 /* VEX_W_0F11_P_3 */
10439 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10442 /* VEX_W_0F12_P_0_M_0 */
10443 { "vmovlps", { XM, Vex128, EXq }, 0 },
10446 /* VEX_W_0F12_P_0_M_1 */
10447 { "vmovhlps", { XM, Vex128, EXq }, 0 },
10450 /* VEX_W_0F12_P_1 */
10451 { "vmovsldup", { XM, EXx }, 0 },
10454 /* VEX_W_0F12_P_2 */
10455 { "vmovlpd", { XM, Vex128, EXq }, 0 },
10458 /* VEX_W_0F12_P_3 */
10459 { "vmovddup", { XM, EXymmq }, 0 },
10462 /* VEX_W_0F13_M_0 */
10463 { "vmovlpX", { EXq, XM }, 0 },
10467 { "vunpcklpX", { XM, Vex, EXx }, 0 },
10471 { "vunpckhpX", { XM, Vex, EXx }, 0 },
10474 /* VEX_W_0F16_P_0_M_0 */
10475 { "vmovhps", { XM, Vex128, EXq }, 0 },
10478 /* VEX_W_0F16_P_0_M_1 */
10479 { "vmovlhps", { XM, Vex128, EXq }, 0 },
10482 /* VEX_W_0F16_P_1 */
10483 { "vmovshdup", { XM, EXx }, 0 },
10486 /* VEX_W_0F16_P_2 */
10487 { "vmovhpd", { XM, Vex128, EXq }, 0 },
10490 /* VEX_W_0F17_M_0 */
10491 { "vmovhpX", { EXq, XM }, 0 },
10495 { "vmovapX", { XM, EXx }, 0 },
10499 { "vmovapX", { EXxS, XM }, 0 },
10502 /* VEX_W_0F2B_M_0 */
10503 { "vmovntpX", { Mx, XM }, 0 },
10506 /* VEX_W_0F2E_P_0 */
10507 { "vucomiss", { XMScalar, EXdScalar }, 0 },
10510 /* VEX_W_0F2E_P_2 */
10511 { "vucomisd", { XMScalar, EXqScalar }, 0 },
10514 /* VEX_W_0F2F_P_0 */
10515 { "vcomiss", { XMScalar, EXdScalar }, 0 },
10518 /* VEX_W_0F2F_P_2 */
10519 { "vcomisd", { XMScalar, EXqScalar }, 0 },
10522 /* VEX_W_0F41_P_0_LEN_1 */
10523 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10524 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10527 /* VEX_W_0F41_P_2_LEN_1 */
10528 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10529 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10532 /* VEX_W_0F42_P_0_LEN_1 */
10533 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10534 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10537 /* VEX_W_0F42_P_2_LEN_1 */
10538 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10539 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10542 /* VEX_W_0F44_P_0_LEN_0 */
10543 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10544 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10547 /* VEX_W_0F44_P_2_LEN_0 */
10548 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10549 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10552 /* VEX_W_0F45_P_0_LEN_1 */
10553 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10554 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10557 /* VEX_W_0F45_P_2_LEN_1 */
10558 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10559 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10562 /* VEX_W_0F46_P_0_LEN_1 */
10563 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10564 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10567 /* VEX_W_0F46_P_2_LEN_1 */
10568 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10569 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10572 /* VEX_W_0F47_P_0_LEN_1 */
10573 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10574 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10577 /* VEX_W_0F47_P_2_LEN_1 */
10578 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10579 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10582 /* VEX_W_0F4A_P_0_LEN_1 */
10583 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10584 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10587 /* VEX_W_0F4A_P_2_LEN_1 */
10588 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10589 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10592 /* VEX_W_0F4B_P_0_LEN_1 */
10593 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10594 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10597 /* VEX_W_0F4B_P_2_LEN_1 */
10598 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10601 /* VEX_W_0F50_M_0 */
10602 { "vmovmskpX", { Gdq, XS }, 0 },
10605 /* VEX_W_0F51_P_0 */
10606 { "vsqrtps", { XM, EXx }, 0 },
10609 /* VEX_W_0F51_P_1 */
10610 { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10613 /* VEX_W_0F51_P_2 */
10614 { "vsqrtpd", { XM, EXx }, 0 },
10617 /* VEX_W_0F51_P_3 */
10618 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10621 /* VEX_W_0F52_P_0 */
10622 { "vrsqrtps", { XM, EXx }, 0 },
10625 /* VEX_W_0F52_P_1 */
10626 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10629 /* VEX_W_0F53_P_0 */
10630 { "vrcpps", { XM, EXx }, 0 },
10633 /* VEX_W_0F53_P_1 */
10634 { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
10637 /* VEX_W_0F58_P_0 */
10638 { "vaddps", { XM, Vex, EXx }, 0 },
10641 /* VEX_W_0F58_P_1 */
10642 { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
10645 /* VEX_W_0F58_P_2 */
10646 { "vaddpd", { XM, Vex, EXx }, 0 },
10649 /* VEX_W_0F58_P_3 */
10650 { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10653 /* VEX_W_0F59_P_0 */
10654 { "vmulps", { XM, Vex, EXx }, 0 },
10657 /* VEX_W_0F59_P_1 */
10658 { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
10661 /* VEX_W_0F59_P_2 */
10662 { "vmulpd", { XM, Vex, EXx }, 0 },
10665 /* VEX_W_0F59_P_3 */
10666 { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10669 /* VEX_W_0F5A_P_0 */
10670 { "vcvtps2pd", { XM, EXxmmq }, 0 },
10673 /* VEX_W_0F5A_P_1 */
10674 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
10677 /* VEX_W_0F5A_P_3 */
10678 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
10681 /* VEX_W_0F5B_P_0 */
10682 { "vcvtdq2ps", { XM, EXx }, 0 },
10685 /* VEX_W_0F5B_P_1 */
10686 { "vcvttps2dq", { XM, EXx }, 0 },
10689 /* VEX_W_0F5B_P_2 */
10690 { "vcvtps2dq", { XM, EXx }, 0 },
10693 /* VEX_W_0F5C_P_0 */
10694 { "vsubps", { XM, Vex, EXx }, 0 },
10697 /* VEX_W_0F5C_P_1 */
10698 { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
10701 /* VEX_W_0F5C_P_2 */
10702 { "vsubpd", { XM, Vex, EXx }, 0 },
10705 /* VEX_W_0F5C_P_3 */
10706 { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10709 /* VEX_W_0F5D_P_0 */
10710 { "vminps", { XM, Vex, EXx }, 0 },
10713 /* VEX_W_0F5D_P_1 */
10714 { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
10717 /* VEX_W_0F5D_P_2 */
10718 { "vminpd", { XM, Vex, EXx }, 0 },
10721 /* VEX_W_0F5D_P_3 */
10722 { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10725 /* VEX_W_0F5E_P_0 */
10726 { "vdivps", { XM, Vex, EXx }, 0 },
10729 /* VEX_W_0F5E_P_1 */
10730 { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
10733 /* VEX_W_0F5E_P_2 */
10734 { "vdivpd", { XM, Vex, EXx }, 0 },
10737 /* VEX_W_0F5E_P_3 */
10738 { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10741 /* VEX_W_0F5F_P_0 */
10742 { "vmaxps", { XM, Vex, EXx }, 0 },
10745 /* VEX_W_0F5F_P_1 */
10746 { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
10749 /* VEX_W_0F5F_P_2 */
10750 { "vmaxpd", { XM, Vex, EXx }, 0 },
10753 /* VEX_W_0F5F_P_3 */
10754 { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10757 /* VEX_W_0F60_P_2 */
10758 { "vpunpcklbw", { XM, Vex, EXx }, 0 },
10761 /* VEX_W_0F61_P_2 */
10762 { "vpunpcklwd", { XM, Vex, EXx }, 0 },
10765 /* VEX_W_0F62_P_2 */
10766 { "vpunpckldq", { XM, Vex, EXx }, 0 },
10769 /* VEX_W_0F63_P_2 */
10770 { "vpacksswb", { XM, Vex, EXx }, 0 },
10773 /* VEX_W_0F64_P_2 */
10774 { "vpcmpgtb", { XM, Vex, EXx }, 0 },
10777 /* VEX_W_0F65_P_2 */
10778 { "vpcmpgtw", { XM, Vex, EXx }, 0 },
10781 /* VEX_W_0F66_P_2 */
10782 { "vpcmpgtd", { XM, Vex, EXx }, 0 },
10785 /* VEX_W_0F67_P_2 */
10786 { "vpackuswb", { XM, Vex, EXx }, 0 },
10789 /* VEX_W_0F68_P_2 */
10790 { "vpunpckhbw", { XM, Vex, EXx }, 0 },
10793 /* VEX_W_0F69_P_2 */
10794 { "vpunpckhwd", { XM, Vex, EXx }, 0 },
10797 /* VEX_W_0F6A_P_2 */
10798 { "vpunpckhdq", { XM, Vex, EXx }, 0 },
10801 /* VEX_W_0F6B_P_2 */
10802 { "vpackssdw", { XM, Vex, EXx }, 0 },
10805 /* VEX_W_0F6C_P_2 */
10806 { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
10809 /* VEX_W_0F6D_P_2 */
10810 { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
10813 /* VEX_W_0F6F_P_1 */
10814 { "vmovdqu", { XM, EXx }, 0 },
10817 /* VEX_W_0F6F_P_2 */
10818 { "vmovdqa", { XM, EXx }, 0 },
10821 /* VEX_W_0F70_P_1 */
10822 { "vpshufhw", { XM, EXx, Ib }, 0 },
10825 /* VEX_W_0F70_P_2 */
10826 { "vpshufd", { XM, EXx, Ib }, 0 },
10829 /* VEX_W_0F70_P_3 */
10830 { "vpshuflw", { XM, EXx, Ib }, 0 },
10833 /* VEX_W_0F71_R_2_P_2 */
10834 { "vpsrlw", { Vex, XS, Ib }, 0 },
10837 /* VEX_W_0F71_R_4_P_2 */
10838 { "vpsraw", { Vex, XS, Ib }, 0 },
10841 /* VEX_W_0F71_R_6_P_2 */
10842 { "vpsllw", { Vex, XS, Ib }, 0 },
10845 /* VEX_W_0F72_R_2_P_2 */
10846 { "vpsrld", { Vex, XS, Ib }, 0 },
10849 /* VEX_W_0F72_R_4_P_2 */
10850 { "vpsrad", { Vex, XS, Ib }, 0 },
10853 /* VEX_W_0F72_R_6_P_2 */
10854 { "vpslld", { Vex, XS, Ib }, 0 },
10857 /* VEX_W_0F73_R_2_P_2 */
10858 { "vpsrlq", { Vex, XS, Ib }, 0 },
10861 /* VEX_W_0F73_R_3_P_2 */
10862 { "vpsrldq", { Vex, XS, Ib }, 0 },
10865 /* VEX_W_0F73_R_6_P_2 */
10866 { "vpsllq", { Vex, XS, Ib }, 0 },
10869 /* VEX_W_0F73_R_7_P_2 */
10870 { "vpslldq", { Vex, XS, Ib }, 0 },
10873 /* VEX_W_0F74_P_2 */
10874 { "vpcmpeqb", { XM, Vex, EXx }, 0 },
10877 /* VEX_W_0F75_P_2 */
10878 { "vpcmpeqw", { XM, Vex, EXx }, 0 },
10881 /* VEX_W_0F76_P_2 */
10882 { "vpcmpeqd", { XM, Vex, EXx }, 0 },
10885 /* VEX_W_0F77_P_0 */
10886 { "", { VZERO }, 0 },
10889 /* VEX_W_0F7C_P_2 */
10890 { "vhaddpd", { XM, Vex, EXx }, 0 },
10893 /* VEX_W_0F7C_P_3 */
10894 { "vhaddps", { XM, Vex, EXx }, 0 },
10897 /* VEX_W_0F7D_P_2 */
10898 { "vhsubpd", { XM, Vex, EXx }, 0 },
10901 /* VEX_W_0F7D_P_3 */
10902 { "vhsubps", { XM, Vex, EXx }, 0 },
10905 /* VEX_W_0F7E_P_1 */
10906 { "vmovq", { XMScalar, EXqScalar }, 0 },
10909 /* VEX_W_0F7F_P_1 */
10910 { "vmovdqu", { EXxS, XM }, 0 },
10913 /* VEX_W_0F7F_P_2 */
10914 { "vmovdqa", { EXxS, XM }, 0 },
10917 /* VEX_W_0F90_P_0_LEN_0 */
10918 { "kmovw", { MaskG, MaskE }, 0 },
10919 { "kmovq", { MaskG, MaskE }, 0 },
10922 /* VEX_W_0F90_P_2_LEN_0 */
10923 { "kmovb", { MaskG, MaskBDE }, 0 },
10924 { "kmovd", { MaskG, MaskBDE }, 0 },
10927 /* VEX_W_0F91_P_0_LEN_0 */
10928 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10929 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10932 /* VEX_W_0F91_P_2_LEN_0 */
10933 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10934 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10937 /* VEX_W_0F92_P_0_LEN_0 */
10938 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10941 /* VEX_W_0F92_P_2_LEN_0 */
10942 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10945 /* VEX_W_0F92_P_3_LEN_0 */
10946 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10947 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10950 /* VEX_W_0F93_P_0_LEN_0 */
10951 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10954 /* VEX_W_0F93_P_2_LEN_0 */
10955 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10958 /* VEX_W_0F93_P_3_LEN_0 */
10959 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10960 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10963 /* VEX_W_0F98_P_0_LEN_0 */
10964 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10965 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10968 /* VEX_W_0F98_P_2_LEN_0 */
10969 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10970 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10973 /* VEX_W_0F99_P_0_LEN_0 */
10974 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10975 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10978 /* VEX_W_0F99_P_2_LEN_0 */
10979 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10980 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10983 /* VEX_W_0FAE_R_2_M_0 */
10984 { "vldmxcsr", { Md }, 0 },
10987 /* VEX_W_0FAE_R_3_M_0 */
10988 { "vstmxcsr", { Md }, 0 },
10991 /* VEX_W_0FC2_P_0 */
10992 { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
10995 /* VEX_W_0FC2_P_1 */
10996 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10999 /* VEX_W_0FC2_P_2 */
11000 { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
11003 /* VEX_W_0FC2_P_3 */
11004 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
11007 /* VEX_W_0FC4_P_2 */
11008 { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
11011 /* VEX_W_0FC5_P_2 */
11012 { "vpextrw", { Gdq, XS, Ib }, 0 },
11015 /* VEX_W_0FD0_P_2 */
11016 { "vaddsubpd", { XM, Vex, EXx }, 0 },
11019 /* VEX_W_0FD0_P_3 */
11020 { "vaddsubps", { XM, Vex, EXx }, 0 },
11023 /* VEX_W_0FD1_P_2 */
11024 { "vpsrlw", { XM, Vex, EXxmm }, 0 },
11027 /* VEX_W_0FD2_P_2 */
11028 { "vpsrld", { XM, Vex, EXxmm }, 0 },
11031 /* VEX_W_0FD3_P_2 */
11032 { "vpsrlq", { XM, Vex, EXxmm }, 0 },
11035 /* VEX_W_0FD4_P_2 */
11036 { "vpaddq", { XM, Vex, EXx }, 0 },
11039 /* VEX_W_0FD5_P_2 */
11040 { "vpmullw", { XM, Vex, EXx }, 0 },
11043 /* VEX_W_0FD6_P_2 */
11044 { "vmovq", { EXqScalarS, XMScalar }, 0 },
11047 /* VEX_W_0FD7_P_2_M_1 */
11048 { "vpmovmskb", { Gdq, XS }, 0 },
11051 /* VEX_W_0FD8_P_2 */
11052 { "vpsubusb", { XM, Vex, EXx }, 0 },
11055 /* VEX_W_0FD9_P_2 */
11056 { "vpsubusw", { XM, Vex, EXx }, 0 },
11059 /* VEX_W_0FDA_P_2 */
11060 { "vpminub", { XM, Vex, EXx }, 0 },
11063 /* VEX_W_0FDB_P_2 */
11064 { "vpand", { XM, Vex, EXx }, 0 },
11067 /* VEX_W_0FDC_P_2 */
11068 { "vpaddusb", { XM, Vex, EXx }, 0 },
11071 /* VEX_W_0FDD_P_2 */
11072 { "vpaddusw", { XM, Vex, EXx }, 0 },
11075 /* VEX_W_0FDE_P_2 */
11076 { "vpmaxub", { XM, Vex, EXx }, 0 },
11079 /* VEX_W_0FDF_P_2 */
11080 { "vpandn", { XM, Vex, EXx }, 0 },
11083 /* VEX_W_0FE0_P_2 */
11084 { "vpavgb", { XM, Vex, EXx }, 0 },
11087 /* VEX_W_0FE1_P_2 */
11088 { "vpsraw", { XM, Vex, EXxmm }, 0 },
11091 /* VEX_W_0FE2_P_2 */
11092 { "vpsrad", { XM, Vex, EXxmm }, 0 },
11095 /* VEX_W_0FE3_P_2 */
11096 { "vpavgw", { XM, Vex, EXx }, 0 },
11099 /* VEX_W_0FE4_P_2 */
11100 { "vpmulhuw", { XM, Vex, EXx }, 0 },
11103 /* VEX_W_0FE5_P_2 */
11104 { "vpmulhw", { XM, Vex, EXx }, 0 },
11107 /* VEX_W_0FE6_P_1 */
11108 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
11111 /* VEX_W_0FE6_P_2 */
11112 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
11115 /* VEX_W_0FE6_P_3 */
11116 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
11119 /* VEX_W_0FE7_P_2_M_0 */
11120 { "vmovntdq", { Mx, XM }, 0 },
11123 /* VEX_W_0FE8_P_2 */
11124 { "vpsubsb", { XM, Vex, EXx }, 0 },
11127 /* VEX_W_0FE9_P_2 */
11128 { "vpsubsw", { XM, Vex, EXx }, 0 },
11131 /* VEX_W_0FEA_P_2 */
11132 { "vpminsw", { XM, Vex, EXx }, 0 },
11135 /* VEX_W_0FEB_P_2 */
11136 { "vpor", { XM, Vex, EXx }, 0 },
11139 /* VEX_W_0FEC_P_2 */
11140 { "vpaddsb", { XM, Vex, EXx }, 0 },
11143 /* VEX_W_0FED_P_2 */
11144 { "vpaddsw", { XM, Vex, EXx }, 0 },
11147 /* VEX_W_0FEE_P_2 */
11148 { "vpmaxsw", { XM, Vex, EXx }, 0 },
11151 /* VEX_W_0FEF_P_2 */
11152 { "vpxor", { XM, Vex, EXx }, 0 },
11155 /* VEX_W_0FF0_P_3_M_0 */
11156 { "vlddqu", { XM, M }, 0 },
11159 /* VEX_W_0FF1_P_2 */
11160 { "vpsllw", { XM, Vex, EXxmm }, 0 },
11163 /* VEX_W_0FF2_P_2 */
11164 { "vpslld", { XM, Vex, EXxmm }, 0 },
11167 /* VEX_W_0FF3_P_2 */
11168 { "vpsllq", { XM, Vex, EXxmm }, 0 },
11171 /* VEX_W_0FF4_P_2 */
11172 { "vpmuludq", { XM, Vex, EXx }, 0 },
11175 /* VEX_W_0FF5_P_2 */
11176 { "vpmaddwd", { XM, Vex, EXx }, 0 },
11179 /* VEX_W_0FF6_P_2 */
11180 { "vpsadbw", { XM, Vex, EXx }, 0 },
11183 /* VEX_W_0FF7_P_2 */
11184 { "vmaskmovdqu", { XM, XS }, 0 },
11187 /* VEX_W_0FF8_P_2 */
11188 { "vpsubb", { XM, Vex, EXx }, 0 },
11191 /* VEX_W_0FF9_P_2 */
11192 { "vpsubw", { XM, Vex, EXx }, 0 },
11195 /* VEX_W_0FFA_P_2 */
11196 { "vpsubd", { XM, Vex, EXx }, 0 },
11199 /* VEX_W_0FFB_P_2 */
11200 { "vpsubq", { XM, Vex, EXx }, 0 },
11203 /* VEX_W_0FFC_P_2 */
11204 { "vpaddb", { XM, Vex, EXx }, 0 },
11207 /* VEX_W_0FFD_P_2 */
11208 { "vpaddw", { XM, Vex, EXx }, 0 },
11211 /* VEX_W_0FFE_P_2 */
11212 { "vpaddd", { XM, Vex, EXx }, 0 },
11215 /* VEX_W_0F3800_P_2 */
11216 { "vpshufb", { XM, Vex, EXx }, 0 },
11219 /* VEX_W_0F3801_P_2 */
11220 { "vphaddw", { XM, Vex, EXx }, 0 },
11223 /* VEX_W_0F3802_P_2 */
11224 { "vphaddd", { XM, Vex, EXx }, 0 },
11227 /* VEX_W_0F3803_P_2 */
11228 { "vphaddsw", { XM, Vex, EXx }, 0 },
11231 /* VEX_W_0F3804_P_2 */
11232 { "vpmaddubsw", { XM, Vex, EXx }, 0 },
11235 /* VEX_W_0F3805_P_2 */
11236 { "vphsubw", { XM, Vex, EXx }, 0 },
11239 /* VEX_W_0F3806_P_2 */
11240 { "vphsubd", { XM, Vex, EXx }, 0 },
11243 /* VEX_W_0F3807_P_2 */
11244 { "vphsubsw", { XM, Vex, EXx }, 0 },
11247 /* VEX_W_0F3808_P_2 */
11248 { "vpsignb", { XM, Vex, EXx }, 0 },
11251 /* VEX_W_0F3809_P_2 */
11252 { "vpsignw", { XM, Vex, EXx }, 0 },
11255 /* VEX_W_0F380A_P_2 */
11256 { "vpsignd", { XM, Vex, EXx }, 0 },
11259 /* VEX_W_0F380B_P_2 */
11260 { "vpmulhrsw", { XM, Vex, EXx }, 0 },
11263 /* VEX_W_0F380C_P_2 */
11264 { "vpermilps", { XM, Vex, EXx }, 0 },
11267 /* VEX_W_0F380D_P_2 */
11268 { "vpermilpd", { XM, Vex, EXx }, 0 },
11271 /* VEX_W_0F380E_P_2 */
11272 { "vtestps", { XM, EXx }, 0 },
11275 /* VEX_W_0F380F_P_2 */
11276 { "vtestpd", { XM, EXx }, 0 },
11279 /* VEX_W_0F3816_P_2 */
11280 { "vpermps", { XM, Vex, EXx }, 0 },
11283 /* VEX_W_0F3817_P_2 */
11284 { "vptest", { XM, EXx }, 0 },
11287 /* VEX_W_0F3818_P_2 */
11288 { "vbroadcastss", { XM, EXxmm_md }, 0 },
11291 /* VEX_W_0F3819_P_2 */
11292 { "vbroadcastsd", { XM, EXxmm_mq }, 0 },
11295 /* VEX_W_0F381A_P_2_M_0 */
11296 { "vbroadcastf128", { XM, Mxmm }, 0 },
11299 /* VEX_W_0F381C_P_2 */
11300 { "vpabsb", { XM, EXx }, 0 },
11303 /* VEX_W_0F381D_P_2 */
11304 { "vpabsw", { XM, EXx }, 0 },
11307 /* VEX_W_0F381E_P_2 */
11308 { "vpabsd", { XM, EXx }, 0 },
11311 /* VEX_W_0F3820_P_2 */
11312 { "vpmovsxbw", { XM, EXxmmq }, 0 },
11315 /* VEX_W_0F3821_P_2 */
11316 { "vpmovsxbd", { XM, EXxmmqd }, 0 },
11319 /* VEX_W_0F3822_P_2 */
11320 { "vpmovsxbq", { XM, EXxmmdw }, 0 },
11323 /* VEX_W_0F3823_P_2 */
11324 { "vpmovsxwd", { XM, EXxmmq }, 0 },
11327 /* VEX_W_0F3824_P_2 */
11328 { "vpmovsxwq", { XM, EXxmmqd }, 0 },
11331 /* VEX_W_0F3825_P_2 */
11332 { "vpmovsxdq", { XM, EXxmmq }, 0 },
11335 /* VEX_W_0F3828_P_2 */
11336 { "vpmuldq", { XM, Vex, EXx }, 0 },
11339 /* VEX_W_0F3829_P_2 */
11340 { "vpcmpeqq", { XM, Vex, EXx }, 0 },
11343 /* VEX_W_0F382A_P_2_M_0 */
11344 { "vmovntdqa", { XM, Mx }, 0 },
11347 /* VEX_W_0F382B_P_2 */
11348 { "vpackusdw", { XM, Vex, EXx }, 0 },
11351 /* VEX_W_0F382C_P_2_M_0 */
11352 { "vmaskmovps", { XM, Vex, Mx }, 0 },
11355 /* VEX_W_0F382D_P_2_M_0 */
11356 { "vmaskmovpd", { XM, Vex, Mx }, 0 },
11359 /* VEX_W_0F382E_P_2_M_0 */
11360 { "vmaskmovps", { Mx, Vex, XM }, 0 },
11363 /* VEX_W_0F382F_P_2_M_0 */
11364 { "vmaskmovpd", { Mx, Vex, XM }, 0 },
11367 /* VEX_W_0F3830_P_2 */
11368 { "vpmovzxbw", { XM, EXxmmq }, 0 },
11371 /* VEX_W_0F3831_P_2 */
11372 { "vpmovzxbd", { XM, EXxmmqd }, 0 },
11375 /* VEX_W_0F3832_P_2 */
11376 { "vpmovzxbq", { XM, EXxmmdw }, 0 },
11379 /* VEX_W_0F3833_P_2 */
11380 { "vpmovzxwd", { XM, EXxmmq }, 0 },
11383 /* VEX_W_0F3834_P_2 */
11384 { "vpmovzxwq", { XM, EXxmmqd }, 0 },
11387 /* VEX_W_0F3835_P_2 */
11388 { "vpmovzxdq", { XM, EXxmmq }, 0 },
11391 /* VEX_W_0F3836_P_2 */
11392 { "vpermd", { XM, Vex, EXx }, 0 },
11395 /* VEX_W_0F3837_P_2 */
11396 { "vpcmpgtq", { XM, Vex, EXx }, 0 },
11399 /* VEX_W_0F3838_P_2 */
11400 { "vpminsb", { XM, Vex, EXx }, 0 },
11403 /* VEX_W_0F3839_P_2 */
11404 { "vpminsd", { XM, Vex, EXx }, 0 },
11407 /* VEX_W_0F383A_P_2 */
11408 { "vpminuw", { XM, Vex, EXx }, 0 },
11411 /* VEX_W_0F383B_P_2 */
11412 { "vpminud", { XM, Vex, EXx }, 0 },
11415 /* VEX_W_0F383C_P_2 */
11416 { "vpmaxsb", { XM, Vex, EXx }, 0 },
11419 /* VEX_W_0F383D_P_2 */
11420 { "vpmaxsd", { XM, Vex, EXx }, 0 },
11423 /* VEX_W_0F383E_P_2 */
11424 { "vpmaxuw", { XM, Vex, EXx }, 0 },
11427 /* VEX_W_0F383F_P_2 */
11428 { "vpmaxud", { XM, Vex, EXx }, 0 },
11431 /* VEX_W_0F3840_P_2 */
11432 { "vpmulld", { XM, Vex, EXx }, 0 },
11435 /* VEX_W_0F3841_P_2 */
11436 { "vphminposuw", { XM, EXx }, 0 },
11439 /* VEX_W_0F3846_P_2 */
11440 { "vpsravd", { XM, Vex, EXx }, 0 },
11443 /* VEX_W_0F3858_P_2 */
11444 { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11447 /* VEX_W_0F3859_P_2 */
11448 { "vpbroadcastq", { XM, EXxmm_mq }, 0 },
11451 /* VEX_W_0F385A_P_2_M_0 */
11452 { "vbroadcasti128", { XM, Mxmm }, 0 },
11455 /* VEX_W_0F3878_P_2 */
11456 { "vpbroadcastb", { XM, EXxmm_mb }, 0 },
11459 /* VEX_W_0F3879_P_2 */
11460 { "vpbroadcastw", { XM, EXxmm_mw }, 0 },
11463 /* VEX_W_0F38DB_P_2 */
11464 { "vaesimc", { XM, EXx }, 0 },
11467 /* VEX_W_0F38DC_P_2 */
11468 { "vaesenc", { XM, Vex128, EXx }, 0 },
11471 /* VEX_W_0F38DD_P_2 */
11472 { "vaesenclast", { XM, Vex128, EXx }, 0 },
11475 /* VEX_W_0F38DE_P_2 */
11476 { "vaesdec", { XM, Vex128, EXx }, 0 },
11479 /* VEX_W_0F38DF_P_2 */
11480 { "vaesdeclast", { XM, Vex128, EXx }, 0 },
11483 /* VEX_W_0F3A00_P_2 */
11485 { "vpermq", { XM, EXx, Ib }, 0 },
11488 /* VEX_W_0F3A01_P_2 */
11490 { "vpermpd", { XM, EXx, Ib }, 0 },
11493 /* VEX_W_0F3A02_P_2 */
11494 { "vpblendd", { XM, Vex, EXx, Ib }, 0 },
11497 /* VEX_W_0F3A04_P_2 */
11498 { "vpermilps", { XM, EXx, Ib }, 0 },
11501 /* VEX_W_0F3A05_P_2 */
11502 { "vpermilpd", { XM, EXx, Ib }, 0 },
11505 /* VEX_W_0F3A06_P_2 */
11506 { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 },
11509 /* VEX_W_0F3A08_P_2 */
11510 { "vroundps", { XM, EXx, Ib }, 0 },
11513 /* VEX_W_0F3A09_P_2 */
11514 { "vroundpd", { XM, EXx, Ib }, 0 },
11517 /* VEX_W_0F3A0A_P_2 */
11518 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11521 /* VEX_W_0F3A0B_P_2 */
11522 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11525 /* VEX_W_0F3A0C_P_2 */
11526 { "vblendps", { XM, Vex, EXx, Ib }, 0 },
11529 /* VEX_W_0F3A0D_P_2 */
11530 { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
11533 /* VEX_W_0F3A0E_P_2 */
11534 { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
11537 /* VEX_W_0F3A0F_P_2 */
11538 { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
11541 /* VEX_W_0F3A14_P_2 */
11542 { "vpextrb", { Edqb, XM, Ib }, 0 },
11545 /* VEX_W_0F3A15_P_2 */
11546 { "vpextrw", { Edqw, XM, Ib }, 0 },
11549 /* VEX_W_0F3A18_P_2 */
11550 { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 },
11553 /* VEX_W_0F3A19_P_2 */
11554 { "vextractf128", { EXxmm, XM, Ib }, 0 },
11557 /* VEX_W_0F3A20_P_2 */
11558 { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
11561 /* VEX_W_0F3A21_P_2 */
11562 { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
11565 /* VEX_W_0F3A30_P_2_LEN_0 */
11566 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11567 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11570 /* VEX_W_0F3A31_P_2_LEN_0 */
11571 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11572 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11575 /* VEX_W_0F3A32_P_2_LEN_0 */
11576 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11577 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11580 /* VEX_W_0F3A33_P_2_LEN_0 */
11581 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11582 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11585 /* VEX_W_0F3A38_P_2 */
11586 { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 },
11589 /* VEX_W_0F3A39_P_2 */
11590 { "vextracti128", { EXxmm, XM, Ib }, 0 },
11593 /* VEX_W_0F3A40_P_2 */
11594 { "vdpps", { XM, Vex, EXx, Ib }, 0 },
11597 /* VEX_W_0F3A41_P_2 */
11598 { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
11601 /* VEX_W_0F3A42_P_2 */
11602 { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
11605 /* VEX_W_0F3A44_P_2 */
11606 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL }, 0 },
11609 /* VEX_W_0F3A46_P_2 */
11610 { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
11613 /* VEX_W_0F3A48_P_2 */
11614 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11615 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11618 /* VEX_W_0F3A49_P_2 */
11619 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11620 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11623 /* VEX_W_0F3A4A_P_2 */
11624 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 },
11627 /* VEX_W_0F3A4B_P_2 */
11628 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 },
11631 /* VEX_W_0F3A4C_P_2 */
11632 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
11635 /* VEX_W_0F3A60_P_2 */
11636 { "vpcmpestrm", { XM, EXx, Ib }, 0 },
11639 /* VEX_W_0F3A61_P_2 */
11640 { "vpcmpestri", { XM, EXx, Ib }, 0 },
11643 /* VEX_W_0F3A62_P_2 */
11644 { "vpcmpistrm", { XM, EXx, Ib }, 0 },
11647 /* VEX_W_0F3A63_P_2 */
11648 { "vpcmpistri", { XM, EXx, Ib }, 0 },
11651 /* VEX_W_0F3ADF_P_2 */
11652 { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11654 #define NEED_VEX_W_TABLE
11655 #include "i386-dis-evex.h"
11656 #undef NEED_VEX_W_TABLE
11659 static const struct dis386 mod_table[][2] = {
11662 { "leaS", { Gv, M }, 0 },
11667 { RM_TABLE (RM_C6_REG_7) },
11672 { RM_TABLE (RM_C7_REG_7) },
11676 { "Jcall^", { indirEp }, 0 },
11680 { "Jjmp^", { indirEp }, 0 },
11683 /* MOD_0F01_REG_0 */
11684 { X86_64_TABLE (X86_64_0F01_REG_0) },
11685 { RM_TABLE (RM_0F01_REG_0) },
11688 /* MOD_0F01_REG_1 */
11689 { X86_64_TABLE (X86_64_0F01_REG_1) },
11690 { RM_TABLE (RM_0F01_REG_1) },
11693 /* MOD_0F01_REG_2 */
11694 { X86_64_TABLE (X86_64_0F01_REG_2) },
11695 { RM_TABLE (RM_0F01_REG_2) },
11698 /* MOD_0F01_REG_3 */
11699 { X86_64_TABLE (X86_64_0F01_REG_3) },
11700 { RM_TABLE (RM_0F01_REG_3) },
11703 /* MOD_0F01_REG_5 */
11705 { RM_TABLE (RM_0F01_REG_5) },
11708 /* MOD_0F01_REG_7 */
11709 { "invlpg", { Mb }, 0 },
11710 { RM_TABLE (RM_0F01_REG_7) },
11713 /* MOD_0F12_PREFIX_0 */
11714 { "movlps", { XM, EXq }, PREFIX_OPCODE },
11715 { "movhlps", { XM, EXq }, PREFIX_OPCODE },
11719 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
11722 /* MOD_0F16_PREFIX_0 */
11723 { "movhps", { XM, EXq }, 0 },
11724 { "movlhps", { XM, EXq }, 0 },
11728 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
11731 /* MOD_0F18_REG_0 */
11732 { "prefetchnta", { Mb }, 0 },
11735 /* MOD_0F18_REG_1 */
11736 { "prefetcht0", { Mb }, 0 },
11739 /* MOD_0F18_REG_2 */
11740 { "prefetcht1", { Mb }, 0 },
11743 /* MOD_0F18_REG_3 */
11744 { "prefetcht2", { Mb }, 0 },
11747 /* MOD_0F18_REG_4 */
11748 { "nop/reserved", { Mb }, 0 },
11751 /* MOD_0F18_REG_5 */
11752 { "nop/reserved", { Mb }, 0 },
11755 /* MOD_0F18_REG_6 */
11756 { "nop/reserved", { Mb }, 0 },
11759 /* MOD_0F18_REG_7 */
11760 { "nop/reserved", { Mb }, 0 },
11763 /* MOD_0F1A_PREFIX_0 */
11764 { "bndldx", { Gbnd, Ev_bnd }, 0 },
11765 { "nopQ", { Ev }, 0 },
11768 /* MOD_0F1B_PREFIX_0 */
11769 { "bndstx", { Ev_bnd, Gbnd }, 0 },
11770 { "nopQ", { Ev }, 0 },
11773 /* MOD_0F1B_PREFIX_1 */
11774 { "bndmk", { Gbnd, Ev_bnd }, 0 },
11775 { "nopQ", { Ev }, 0 },
11780 { "movL", { Rd, Td }, 0 },
11785 { "movL", { Td, Rd }, 0 },
11788 /* MOD_0F2B_PREFIX_0 */
11789 {"movntps", { Mx, XM }, PREFIX_OPCODE },
11792 /* MOD_0F2B_PREFIX_1 */
11793 {"movntss", { Md, XM }, PREFIX_OPCODE },
11796 /* MOD_0F2B_PREFIX_2 */
11797 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
11800 /* MOD_0F2B_PREFIX_3 */
11801 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
11806 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
11809 /* MOD_0F71_REG_2 */
11811 { "psrlw", { MS, Ib }, 0 },
11814 /* MOD_0F71_REG_4 */
11816 { "psraw", { MS, Ib }, 0 },
11819 /* MOD_0F71_REG_6 */
11821 { "psllw", { MS, Ib }, 0 },
11824 /* MOD_0F72_REG_2 */
11826 { "psrld", { MS, Ib }, 0 },
11829 /* MOD_0F72_REG_4 */
11831 { "psrad", { MS, Ib }, 0 },
11834 /* MOD_0F72_REG_6 */
11836 { "pslld", { MS, Ib }, 0 },
11839 /* MOD_0F73_REG_2 */
11841 { "psrlq", { MS, Ib }, 0 },
11844 /* MOD_0F73_REG_3 */
11846 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11849 /* MOD_0F73_REG_6 */
11851 { "psllq", { MS, Ib }, 0 },
11854 /* MOD_0F73_REG_7 */
11856 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11859 /* MOD_0FAE_REG_0 */
11860 { "fxsave", { FXSAVE }, 0 },
11861 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11864 /* MOD_0FAE_REG_1 */
11865 { "fxrstor", { FXSAVE }, 0 },
11866 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11869 /* MOD_0FAE_REG_2 */
11870 { "ldmxcsr", { Md }, 0 },
11871 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11874 /* MOD_0FAE_REG_3 */
11875 { "stmxcsr", { Md }, 0 },
11876 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11879 /* MOD_0FAE_REG_4 */
11880 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11881 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11884 /* MOD_0FAE_REG_5 */
11885 { "xrstor", { FXSAVE }, 0 },
11886 { RM_TABLE (RM_0FAE_REG_5) },
11889 /* MOD_0FAE_REG_6 */
11890 { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11891 { RM_TABLE (RM_0FAE_REG_6) },
11894 /* MOD_0FAE_REG_7 */
11895 { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11896 { RM_TABLE (RM_0FAE_REG_7) },
11900 { "lssS", { Gv, Mp }, 0 },
11904 { "lfsS", { Gv, Mp }, 0 },
11908 { "lgsS", { Gv, Mp }, 0 },
11912 { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11915 /* MOD_0FC7_REG_3 */
11916 { "xrstors", { FXSAVE }, 0 },
11919 /* MOD_0FC7_REG_4 */
11920 { "xsavec", { FXSAVE }, 0 },
11923 /* MOD_0FC7_REG_5 */
11924 { "xsaves", { FXSAVE }, 0 },
11927 /* MOD_0FC7_REG_6 */
11928 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11929 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11932 /* MOD_0FC7_REG_7 */
11933 { "vmptrst", { Mq }, 0 },
11934 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11939 { "pmovmskb", { Gdq, MS }, 0 },
11942 /* MOD_0FE7_PREFIX_2 */
11943 { "movntdq", { Mx, XM }, 0 },
11946 /* MOD_0FF0_PREFIX_3 */
11947 { "lddqu", { XM, M }, 0 },
11950 /* MOD_0F382A_PREFIX_2 */
11951 { "movntdqa", { XM, Mx }, 0 },
11955 { "bound{S|}", { Gv, Ma }, 0 },
11956 { EVEX_TABLE (EVEX_0F) },
11960 { "lesS", { Gv, Mp }, 0 },
11961 { VEX_C4_TABLE (VEX_0F) },
11965 { "ldsS", { Gv, Mp }, 0 },
11966 { VEX_C5_TABLE (VEX_0F) },
11969 /* MOD_VEX_0F12_PREFIX_0 */
11970 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11971 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11975 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11978 /* MOD_VEX_0F16_PREFIX_0 */
11979 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11980 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11984 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11988 { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11991 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11993 { "kandw", { MaskG, MaskVex, MaskR }, 0 },
11996 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11998 { "kandq", { MaskG, MaskVex, MaskR }, 0 },
12001 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
12003 { "kandb", { MaskG, MaskVex, MaskR }, 0 },
12006 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
12008 { "kandd", { MaskG, MaskVex, MaskR }, 0 },
12011 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
12013 { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
12016 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
12018 { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
12021 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
12023 { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
12026 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
12028 { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
12031 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
12033 { "knotw", { MaskG, MaskR }, 0 },
12036 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
12038 { "knotq", { MaskG, MaskR }, 0 },
12041 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
12043 { "knotb", { MaskG, MaskR }, 0 },
12046 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
12048 { "knotd", { MaskG, MaskR }, 0 },
12051 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
12053 { "korw", { MaskG, MaskVex, MaskR }, 0 },
12056 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
12058 { "korq", { MaskG, MaskVex, MaskR }, 0 },
12061 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
12063 { "korb", { MaskG, MaskVex, MaskR }, 0 },
12066 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
12068 { "kord", { MaskG, MaskVex, MaskR }, 0 },
12071 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
12073 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
12076 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
12078 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
12081 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
12083 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
12086 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
12088 { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
12091 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
12093 { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
12096 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
12098 { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
12101 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
12103 { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
12106 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
12108 { "kxord", { MaskG, MaskVex, MaskR }, 0 },
12111 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
12113 { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
12116 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
12118 { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
12121 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
12123 { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
12126 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
12128 { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
12131 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
12133 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
12136 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
12138 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
12141 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
12143 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
12148 { VEX_W_TABLE (VEX_W_0F50_M_0) },
12151 /* MOD_VEX_0F71_REG_2 */
12153 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
12156 /* MOD_VEX_0F71_REG_4 */
12158 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
12161 /* MOD_VEX_0F71_REG_6 */
12163 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
12166 /* MOD_VEX_0F72_REG_2 */
12168 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12171 /* MOD_VEX_0F72_REG_4 */
12173 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12176 /* MOD_VEX_0F72_REG_6 */
12178 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12181 /* MOD_VEX_0F73_REG_2 */
12183 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12186 /* MOD_VEX_0F73_REG_3 */
12188 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12191 /* MOD_VEX_0F73_REG_6 */
12193 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12196 /* MOD_VEX_0F73_REG_7 */
12198 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12201 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12202 { "kmovw", { Ew, MaskG }, 0 },
12206 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12207 { "kmovq", { Eq, MaskG }, 0 },
12211 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12212 { "kmovb", { Eb, MaskG }, 0 },
12216 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12217 { "kmovd", { Ed, MaskG }, 0 },
12221 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12223 { "kmovw", { MaskG, Rdq }, 0 },
12226 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12228 { "kmovb", { MaskG, Rdq }, 0 },
12231 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12233 { "kmovd", { MaskG, Rdq }, 0 },
12236 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12238 { "kmovq", { MaskG, Rdq }, 0 },
12241 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12243 { "kmovw", { Gdq, MaskR }, 0 },
12246 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12248 { "kmovb", { Gdq, MaskR }, 0 },
12251 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12253 { "kmovd", { Gdq, MaskR }, 0 },
12256 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12258 { "kmovq", { Gdq, MaskR }, 0 },
12261 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12263 { "kortestw", { MaskG, MaskR }, 0 },
12266 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12268 { "kortestq", { MaskG, MaskR }, 0 },
12271 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12273 { "kortestb", { MaskG, MaskR }, 0 },
12276 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12278 { "kortestd", { MaskG, MaskR }, 0 },
12281 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12283 { "ktestw", { MaskG, MaskR }, 0 },
12286 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12288 { "ktestq", { MaskG, MaskR }, 0 },
12291 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12293 { "ktestb", { MaskG, MaskR }, 0 },
12296 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12298 { "ktestd", { MaskG, MaskR }, 0 },
12301 /* MOD_VEX_0FAE_REG_2 */
12302 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12305 /* MOD_VEX_0FAE_REG_3 */
12306 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12309 /* MOD_VEX_0FD7_PREFIX_2 */
12311 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12314 /* MOD_VEX_0FE7_PREFIX_2 */
12315 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12318 /* MOD_VEX_0FF0_PREFIX_3 */
12319 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12322 /* MOD_VEX_0F381A_PREFIX_2 */
12323 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12326 /* MOD_VEX_0F382A_PREFIX_2 */
12327 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12330 /* MOD_VEX_0F382C_PREFIX_2 */
12331 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12334 /* MOD_VEX_0F382D_PREFIX_2 */
12335 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12338 /* MOD_VEX_0F382E_PREFIX_2 */
12339 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12342 /* MOD_VEX_0F382F_PREFIX_2 */
12343 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12346 /* MOD_VEX_0F385A_PREFIX_2 */
12347 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12350 /* MOD_VEX_0F388C_PREFIX_2 */
12351 { "vpmaskmov%LW", { XM, Vex, Mx }, 0 },
12354 /* MOD_VEX_0F388E_PREFIX_2 */
12355 { "vpmaskmov%LW", { Mx, Vex, XM }, 0 },
12358 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12360 { "kshiftrb", { MaskG, MaskR, Ib }, 0 },
12363 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12365 { "kshiftrw", { MaskG, MaskR, Ib }, 0 },
12368 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12370 { "kshiftrd", { MaskG, MaskR, Ib }, 0 },
12373 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12375 { "kshiftrq", { MaskG, MaskR, Ib }, 0 },
12378 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12380 { "kshiftlb", { MaskG, MaskR, Ib }, 0 },
12383 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12385 { "kshiftlw", { MaskG, MaskR, Ib }, 0 },
12388 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12390 { "kshiftld", { MaskG, MaskR, Ib }, 0 },
12393 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12395 { "kshiftlq", { MaskG, MaskR, Ib }, 0 },
12397 #define NEED_MOD_TABLE
12398 #include "i386-dis-evex.h"
12399 #undef NEED_MOD_TABLE
12402 static const struct dis386 rm_table[][8] = {
12405 { "xabort", { Skip_MODRM, Ib }, 0 },
12409 { "xbeginT", { Skip_MODRM, Jv }, 0 },
12412 /* RM_0F01_REG_0 */
12414 { "vmcall", { Skip_MODRM }, 0 },
12415 { "vmlaunch", { Skip_MODRM }, 0 },
12416 { "vmresume", { Skip_MODRM }, 0 },
12417 { "vmxoff", { Skip_MODRM }, 0 },
12420 /* RM_0F01_REG_1 */
12421 { "monitor", { { OP_Monitor, 0 } }, 0 },
12422 { "mwait", { { OP_Mwait, 0 } }, 0 },
12423 { "clac", { Skip_MODRM }, 0 },
12424 { "stac", { Skip_MODRM }, 0 },
12428 { "encls", { Skip_MODRM }, 0 },
12431 /* RM_0F01_REG_2 */
12432 { "xgetbv", { Skip_MODRM }, 0 },
12433 { "xsetbv", { Skip_MODRM }, 0 },
12436 { "vmfunc", { Skip_MODRM }, 0 },
12437 { "xend", { Skip_MODRM }, 0 },
12438 { "xtest", { Skip_MODRM }, 0 },
12439 { "enclu", { Skip_MODRM }, 0 },
12442 /* RM_0F01_REG_3 */
12443 { "vmrun", { Skip_MODRM }, 0 },
12444 { "vmmcall", { Skip_MODRM }, 0 },
12445 { "vmload", { Skip_MODRM }, 0 },
12446 { "vmsave", { Skip_MODRM }, 0 },
12447 { "stgi", { Skip_MODRM }, 0 },
12448 { "clgi", { Skip_MODRM }, 0 },
12449 { "skinit", { Skip_MODRM }, 0 },
12450 { "invlpga", { Skip_MODRM }, 0 },
12453 /* RM_0F01_REG_5 */
12460 { "rdpkru", { Skip_MODRM }, 0 },
12461 { "wrpkru", { Skip_MODRM }, 0 },
12464 /* RM_0F01_REG_7 */
12465 { "swapgs", { Skip_MODRM }, 0 },
12466 { "rdtscp", { Skip_MODRM }, 0 },
12467 { "monitorx", { { OP_Monitor, 0 } }, 0 },
12468 { "mwaitx", { { OP_Mwaitx, 0 } }, 0 },
12469 { "clzero", { Skip_MODRM }, 0 },
12472 /* RM_0FAE_REG_5 */
12473 { "lfence", { Skip_MODRM }, 0 },
12476 /* RM_0FAE_REG_6 */
12477 { "mfence", { Skip_MODRM }, 0 },
12480 /* RM_0FAE_REG_7 */
12481 { "sfence", { Skip_MODRM }, 0 },
12486 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12488 /* We use the high bit to indicate different name for the same
12490 #define REP_PREFIX (0xf3 | 0x100)
12491 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12492 #define XRELEASE_PREFIX (0xf3 | 0x400)
12493 #define BND_PREFIX (0xf2 | 0x400)
12498 int newrex, i, length;
12504 last_lock_prefix = -1;
12505 last_repz_prefix = -1;
12506 last_repnz_prefix = -1;
12507 last_data_prefix = -1;
12508 last_addr_prefix = -1;
12509 last_rex_prefix = -1;
12510 last_seg_prefix = -1;
12512 active_seg_prefix = 0;
12513 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12514 all_prefixes[i] = 0;
12517 /* The maximum instruction length is 15bytes. */
12518 while (length < MAX_CODE_LENGTH - 1)
12520 FETCH_DATA (the_info, codep + 1);
12524 /* REX prefixes family. */
12541 if (address_mode == mode_64bit)
12545 last_rex_prefix = i;
12548 prefixes |= PREFIX_REPZ;
12549 last_repz_prefix = i;
12552 prefixes |= PREFIX_REPNZ;
12553 last_repnz_prefix = i;
12556 prefixes |= PREFIX_LOCK;
12557 last_lock_prefix = i;
12560 prefixes |= PREFIX_CS;
12561 last_seg_prefix = i;
12562 active_seg_prefix = PREFIX_CS;
12565 prefixes |= PREFIX_SS;
12566 last_seg_prefix = i;
12567 active_seg_prefix = PREFIX_SS;
12570 prefixes |= PREFIX_DS;
12571 last_seg_prefix = i;
12572 active_seg_prefix = PREFIX_DS;
12575 prefixes |= PREFIX_ES;
12576 last_seg_prefix = i;
12577 active_seg_prefix = PREFIX_ES;
12580 prefixes |= PREFIX_FS;
12581 last_seg_prefix = i;
12582 active_seg_prefix = PREFIX_FS;
12585 prefixes |= PREFIX_GS;
12586 last_seg_prefix = i;
12587 active_seg_prefix = PREFIX_GS;
12590 prefixes |= PREFIX_DATA;
12591 last_data_prefix = i;
12594 prefixes |= PREFIX_ADDR;
12595 last_addr_prefix = i;
12598 /* fwait is really an instruction. If there are prefixes
12599 before the fwait, they belong to the fwait, *not* to the
12600 following instruction. */
12602 if (prefixes || rex)
12604 prefixes |= PREFIX_FWAIT;
12606 /* This ensures that the previous REX prefixes are noticed
12607 as unused prefixes, as in the return case below. */
12611 prefixes = PREFIX_FWAIT;
12616 /* Rex is ignored when followed by another prefix. */
12622 if (*codep != FWAIT_OPCODE)
12623 all_prefixes[i++] = *codep;
12631 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12634 static const char *
12635 prefix_name (int pref, int sizeflag)
12637 static const char *rexes [16] =
12640 "rex.B", /* 0x41 */
12641 "rex.X", /* 0x42 */
12642 "rex.XB", /* 0x43 */
12643 "rex.R", /* 0x44 */
12644 "rex.RB", /* 0x45 */
12645 "rex.RX", /* 0x46 */
12646 "rex.RXB", /* 0x47 */
12647 "rex.W", /* 0x48 */
12648 "rex.WB", /* 0x49 */
12649 "rex.WX", /* 0x4a */
12650 "rex.WXB", /* 0x4b */
12651 "rex.WR", /* 0x4c */
12652 "rex.WRB", /* 0x4d */
12653 "rex.WRX", /* 0x4e */
12654 "rex.WRXB", /* 0x4f */
12659 /* REX prefixes family. */
12676 return rexes [pref - 0x40];
12696 return (sizeflag & DFLAG) ? "data16" : "data32";
12698 if (address_mode == mode_64bit)
12699 return (sizeflag & AFLAG) ? "addr32" : "addr64";
12701 return (sizeflag & AFLAG) ? "addr16" : "addr32";
12706 case XACQUIRE_PREFIX:
12708 case XRELEASE_PREFIX:
12717 static char op_out[MAX_OPERANDS][100];
12718 static int op_ad, op_index[MAX_OPERANDS];
12719 static int two_source_ops;
12720 static bfd_vma op_address[MAX_OPERANDS];
12721 static bfd_vma op_riprel[MAX_OPERANDS];
12722 static bfd_vma start_pc;
12725 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12726 * (see topic "Redundant prefixes" in the "Differences from 8086"
12727 * section of the "Virtual 8086 Mode" chapter.)
12728 * 'pc' should be the address of this instruction, it will
12729 * be used to print the target address if this is a relative jump or call
12730 * The function returns the length of this instruction in bytes.
12733 static char intel_syntax;
12734 static char intel_mnemonic = !SYSV386_COMPAT;
12735 static char open_char;
12736 static char close_char;
12737 static char separator_char;
12738 static char scale_char;
12746 static enum x86_64_isa isa64;
12748 /* Here for backwards compatibility. When gdb stops using
12749 print_insn_i386_att and print_insn_i386_intel these functions can
12750 disappear, and print_insn_i386 be merged into print_insn. */
12752 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12756 return print_insn (pc, info);
12760 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12764 return print_insn (pc, info);
12768 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12772 return print_insn (pc, info);
12776 print_i386_disassembler_options (FILE *stream)
12778 fprintf (stream, _("\n\
12779 The following i386/x86-64 specific disassembler options are supported for use\n\
12780 with the -M switch (multiple options should be separated by commas):\n"));
12782 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
12783 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
12784 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
12785 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
12786 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
12787 fprintf (stream, _(" att-mnemonic\n"
12788 " Display instruction in AT&T mnemonic\n"));
12789 fprintf (stream, _(" intel-mnemonic\n"
12790 " Display instruction in Intel mnemonic\n"));
12791 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
12792 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
12793 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
12794 fprintf (stream, _(" data32 Assume 32bit data size\n"));
12795 fprintf (stream, _(" data16 Assume 16bit data size\n"));
12796 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12797 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
12798 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
12802 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12804 /* Get a pointer to struct dis386 with a valid name. */
12806 static const struct dis386 *
12807 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12809 int vindex, vex_table_index;
12811 if (dp->name != NULL)
12814 switch (dp->op[0].bytemode)
12816 case USE_REG_TABLE:
12817 dp = ®_table[dp->op[1].bytemode][modrm.reg];
12820 case USE_MOD_TABLE:
12821 vindex = modrm.mod == 0x3 ? 1 : 0;
12822 dp = &mod_table[dp->op[1].bytemode][vindex];
12826 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12829 case USE_PREFIX_TABLE:
12832 /* The prefix in VEX is implicit. */
12833 switch (vex.prefix)
12838 case REPE_PREFIX_OPCODE:
12841 case DATA_PREFIX_OPCODE:
12844 case REPNE_PREFIX_OPCODE:
12854 int last_prefix = -1;
12857 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12858 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12860 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12862 if (last_repz_prefix > last_repnz_prefix)
12865 prefix = PREFIX_REPZ;
12866 last_prefix = last_repz_prefix;
12871 prefix = PREFIX_REPNZ;
12872 last_prefix = last_repnz_prefix;
12875 /* Check if prefix should be ignored. */
12876 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12877 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12882 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12885 prefix = PREFIX_DATA;
12886 last_prefix = last_data_prefix;
12891 used_prefixes |= prefix;
12892 all_prefixes[last_prefix] = 0;
12895 dp = &prefix_table[dp->op[1].bytemode][vindex];
12898 case USE_X86_64_TABLE:
12899 vindex = address_mode == mode_64bit ? 1 : 0;
12900 dp = &x86_64_table[dp->op[1].bytemode][vindex];
12903 case USE_3BYTE_TABLE:
12904 FETCH_DATA (info, codep + 2);
12906 dp = &three_byte_table[dp->op[1].bytemode][vindex];
12908 modrm.mod = (*codep >> 6) & 3;
12909 modrm.reg = (*codep >> 3) & 7;
12910 modrm.rm = *codep & 7;
12913 case USE_VEX_LEN_TABLE:
12917 switch (vex.length)
12930 dp = &vex_len_table[dp->op[1].bytemode][vindex];
12933 case USE_XOP_8F_TABLE:
12934 FETCH_DATA (info, codep + 3);
12935 /* All bits in the REX prefix are ignored. */
12937 rex = ~(*codep >> 5) & 0x7;
12939 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12940 switch ((*codep & 0x1f))
12946 vex_table_index = XOP_08;
12949 vex_table_index = XOP_09;
12952 vex_table_index = XOP_0A;
12956 vex.w = *codep & 0x80;
12957 if (vex.w && address_mode == mode_64bit)
12960 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12961 if (address_mode != mode_64bit
12962 && vex.register_specifier > 0x7)
12968 vex.length = (*codep & 0x4) ? 256 : 128;
12969 switch ((*codep & 0x3))
12975 vex.prefix = DATA_PREFIX_OPCODE;
12978 vex.prefix = REPE_PREFIX_OPCODE;
12981 vex.prefix = REPNE_PREFIX_OPCODE;
12988 dp = &xop_table[vex_table_index][vindex];
12991 FETCH_DATA (info, codep + 1);
12992 modrm.mod = (*codep >> 6) & 3;
12993 modrm.reg = (*codep >> 3) & 7;
12994 modrm.rm = *codep & 7;
12997 case USE_VEX_C4_TABLE:
12999 FETCH_DATA (info, codep + 3);
13000 /* All bits in the REX prefix are ignored. */
13002 rex = ~(*codep >> 5) & 0x7;
13003 switch ((*codep & 0x1f))
13009 vex_table_index = VEX_0F;
13012 vex_table_index = VEX_0F38;
13015 vex_table_index = VEX_0F3A;
13019 vex.w = *codep & 0x80;
13020 if (address_mode == mode_64bit)
13024 vex.register_specifier = (~(*codep >> 3)) & 0xf;
13028 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
13029 is ignored, other REX bits are 0 and the highest bit in
13030 VEX.vvvv is also ignored. */
13032 vex.register_specifier = (~(*codep >> 3)) & 0x7;
13034 vex.length = (*codep & 0x4) ? 256 : 128;
13035 switch ((*codep & 0x3))
13041 vex.prefix = DATA_PREFIX_OPCODE;
13044 vex.prefix = REPE_PREFIX_OPCODE;
13047 vex.prefix = REPNE_PREFIX_OPCODE;
13054 dp = &vex_table[vex_table_index][vindex];
13056 /* There is no MODRM byte for VEX [82|77]. */
13057 if (vindex != 0x77 && vindex != 0x82)
13059 FETCH_DATA (info, codep + 1);
13060 modrm.mod = (*codep >> 6) & 3;
13061 modrm.reg = (*codep >> 3) & 7;
13062 modrm.rm = *codep & 7;
13066 case USE_VEX_C5_TABLE:
13068 FETCH_DATA (info, codep + 2);
13069 /* All bits in the REX prefix are ignored. */
13071 rex = (*codep & 0x80) ? 0 : REX_R;
13073 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
13075 vex.register_specifier = (~(*codep >> 3)) & 0xf;
13077 vex.length = (*codep & 0x4) ? 256 : 128;
13078 switch ((*codep & 0x3))
13084 vex.prefix = DATA_PREFIX_OPCODE;
13087 vex.prefix = REPE_PREFIX_OPCODE;
13090 vex.prefix = REPNE_PREFIX_OPCODE;
13097 dp = &vex_table[dp->op[1].bytemode][vindex];
13099 /* There is no MODRM byte for VEX [82|77]. */
13100 if (vindex != 0x77 && vindex != 0x82)
13102 FETCH_DATA (info, codep + 1);
13103 modrm.mod = (*codep >> 6) & 3;
13104 modrm.reg = (*codep >> 3) & 7;
13105 modrm.rm = *codep & 7;
13109 case USE_VEX_W_TABLE:
13113 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
13116 case USE_EVEX_TABLE:
13117 two_source_ops = 0;
13120 FETCH_DATA (info, codep + 4);
13121 /* All bits in the REX prefix are ignored. */
13123 /* The first byte after 0x62. */
13124 rex = ~(*codep >> 5) & 0x7;
13125 vex.r = *codep & 0x10;
13126 switch ((*codep & 0xf))
13129 return &bad_opcode;
13131 vex_table_index = EVEX_0F;
13134 vex_table_index = EVEX_0F38;
13137 vex_table_index = EVEX_0F3A;
13141 /* The second byte after 0x62. */
13143 vex.w = *codep & 0x80;
13144 if (vex.w && address_mode == mode_64bit)
13147 vex.register_specifier = (~(*codep >> 3)) & 0xf;
13148 if (address_mode != mode_64bit)
13150 /* In 16/32-bit mode silently ignore following bits. */
13154 vex.register_specifier &= 0x7;
13158 if (!(*codep & 0x4))
13159 return &bad_opcode;
13161 switch ((*codep & 0x3))
13167 vex.prefix = DATA_PREFIX_OPCODE;
13170 vex.prefix = REPE_PREFIX_OPCODE;
13173 vex.prefix = REPNE_PREFIX_OPCODE;
13177 /* The third byte after 0x62. */
13180 /* Remember the static rounding bits. */
13181 vex.ll = (*codep >> 5) & 3;
13182 vex.b = (*codep & 0x10) != 0;
13184 vex.v = *codep & 0x8;
13185 vex.mask_register_specifier = *codep & 0x7;
13186 vex.zeroing = *codep & 0x80;
13192 dp = &evex_table[vex_table_index][vindex];
13194 FETCH_DATA (info, codep + 1);
13195 modrm.mod = (*codep >> 6) & 3;
13196 modrm.reg = (*codep >> 3) & 7;
13197 modrm.rm = *codep & 7;
13199 /* Set vector length. */
13200 if (modrm.mod == 3 && vex.b)
13216 return &bad_opcode;
13229 if (dp->name != NULL)
13232 return get_valid_dis386 (dp, info);
13236 get_sib (disassemble_info *info, int sizeflag)
13238 /* If modrm.mod == 3, operand must be register. */
13240 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13244 FETCH_DATA (info, codep + 2);
13245 sib.index = (codep [1] >> 3) & 7;
13246 sib.scale = (codep [1] >> 6) & 3;
13247 sib.base = codep [1] & 7;
13252 print_insn (bfd_vma pc, disassemble_info *info)
13254 const struct dis386 *dp;
13256 char *op_txt[MAX_OPERANDS];
13258 int sizeflag, orig_sizeflag;
13260 struct dis_private priv;
13263 priv.orig_sizeflag = AFLAG | DFLAG;
13264 if ((info->mach & bfd_mach_i386_i386) != 0)
13265 address_mode = mode_32bit;
13266 else if (info->mach == bfd_mach_i386_i8086)
13268 address_mode = mode_16bit;
13269 priv.orig_sizeflag = 0;
13272 address_mode = mode_64bit;
13274 if (intel_syntax == (char) -1)
13275 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13277 for (p = info->disassembler_options; p != NULL; )
13279 if (CONST_STRNEQ (p, "amd64"))
13281 else if (CONST_STRNEQ (p, "intel64"))
13283 else if (CONST_STRNEQ (p, "x86-64"))
13285 address_mode = mode_64bit;
13286 priv.orig_sizeflag = AFLAG | DFLAG;
13288 else if (CONST_STRNEQ (p, "i386"))
13290 address_mode = mode_32bit;
13291 priv.orig_sizeflag = AFLAG | DFLAG;
13293 else if (CONST_STRNEQ (p, "i8086"))
13295 address_mode = mode_16bit;
13296 priv.orig_sizeflag = 0;
13298 else if (CONST_STRNEQ (p, "intel"))
13301 if (CONST_STRNEQ (p + 5, "-mnemonic"))
13302 intel_mnemonic = 1;
13304 else if (CONST_STRNEQ (p, "att"))
13307 if (CONST_STRNEQ (p + 3, "-mnemonic"))
13308 intel_mnemonic = 0;
13310 else if (CONST_STRNEQ (p, "addr"))
13312 if (address_mode == mode_64bit)
13314 if (p[4] == '3' && p[5] == '2')
13315 priv.orig_sizeflag &= ~AFLAG;
13316 else if (p[4] == '6' && p[5] == '4')
13317 priv.orig_sizeflag |= AFLAG;
13321 if (p[4] == '1' && p[5] == '6')
13322 priv.orig_sizeflag &= ~AFLAG;
13323 else if (p[4] == '3' && p[5] == '2')
13324 priv.orig_sizeflag |= AFLAG;
13327 else if (CONST_STRNEQ (p, "data"))
13329 if (p[4] == '1' && p[5] == '6')
13330 priv.orig_sizeflag &= ~DFLAG;
13331 else if (p[4] == '3' && p[5] == '2')
13332 priv.orig_sizeflag |= DFLAG;
13334 else if (CONST_STRNEQ (p, "suffix"))
13335 priv.orig_sizeflag |= SUFFIX_ALWAYS;
13337 p = strchr (p, ',');
13342 if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13344 (*info->fprintf_func) (info->stream,
13345 _("64-bit address is disabled"));
13351 names64 = intel_names64;
13352 names32 = intel_names32;
13353 names16 = intel_names16;
13354 names8 = intel_names8;
13355 names8rex = intel_names8rex;
13356 names_seg = intel_names_seg;
13357 names_mm = intel_names_mm;
13358 names_bnd = intel_names_bnd;
13359 names_xmm = intel_names_xmm;
13360 names_ymm = intel_names_ymm;
13361 names_zmm = intel_names_zmm;
13362 index64 = intel_index64;
13363 index32 = intel_index32;
13364 names_mask = intel_names_mask;
13365 index16 = intel_index16;
13368 separator_char = '+';
13373 names64 = att_names64;
13374 names32 = att_names32;
13375 names16 = att_names16;
13376 names8 = att_names8;
13377 names8rex = att_names8rex;
13378 names_seg = att_names_seg;
13379 names_mm = att_names_mm;
13380 names_bnd = att_names_bnd;
13381 names_xmm = att_names_xmm;
13382 names_ymm = att_names_ymm;
13383 names_zmm = att_names_zmm;
13384 index64 = att_index64;
13385 index32 = att_index32;
13386 names_mask = att_names_mask;
13387 index16 = att_index16;
13390 separator_char = ',';
13394 /* The output looks better if we put 7 bytes on a line, since that
13395 puts most long word instructions on a single line. Use 8 bytes
13397 if ((info->mach & bfd_mach_l1om) != 0)
13398 info->bytes_per_line = 8;
13400 info->bytes_per_line = 7;
13402 info->private_data = &priv;
13403 priv.max_fetched = priv.the_buffer;
13404 priv.insn_start = pc;
13407 for (i = 0; i < MAX_OPERANDS; ++i)
13415 start_codep = priv.the_buffer;
13416 codep = priv.the_buffer;
13418 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13422 /* Getting here means we tried for data but didn't get it. That
13423 means we have an incomplete instruction of some sort. Just
13424 print the first byte as a prefix or a .byte pseudo-op. */
13425 if (codep > priv.the_buffer)
13427 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13429 (*info->fprintf_func) (info->stream, "%s", name);
13432 /* Just print the first byte as a .byte instruction. */
13433 (*info->fprintf_func) (info->stream, ".byte 0x%x",
13434 (unsigned int) priv.the_buffer[0]);
13444 sizeflag = priv.orig_sizeflag;
13446 if (!ckprefix () || rex_used)
13448 /* Too many prefixes or unused REX prefixes. */
13450 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13452 (*info->fprintf_func) (info->stream, "%s%s",
13454 prefix_name (all_prefixes[i], sizeflag));
13458 insn_codep = codep;
13460 FETCH_DATA (info, codep + 1);
13461 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13463 if (((prefixes & PREFIX_FWAIT)
13464 && ((*codep < 0xd8) || (*codep > 0xdf))))
13466 /* Handle prefixes before fwait. */
13467 for (i = 0; i < fwait_prefix && all_prefixes[i];
13469 (*info->fprintf_func) (info->stream, "%s ",
13470 prefix_name (all_prefixes[i], sizeflag));
13471 (*info->fprintf_func) (info->stream, "fwait");
13475 if (*codep == 0x0f)
13477 unsigned char threebyte;
13480 FETCH_DATA (info, codep + 1);
13481 threebyte = *codep;
13482 dp = &dis386_twobyte[threebyte];
13483 need_modrm = twobyte_has_modrm[*codep];
13488 dp = &dis386[*codep];
13489 need_modrm = onebyte_has_modrm[*codep];
13493 /* Save sizeflag for printing the extra prefixes later before updating
13494 it for mnemonic and operand processing. The prefix names depend
13495 only on the address mode. */
13496 orig_sizeflag = sizeflag;
13497 if (prefixes & PREFIX_ADDR)
13499 if ((prefixes & PREFIX_DATA))
13505 FETCH_DATA (info, codep + 1);
13506 modrm.mod = (*codep >> 6) & 3;
13507 modrm.reg = (*codep >> 3) & 7;
13508 modrm.rm = *codep & 7;
13516 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13518 get_sib (info, sizeflag);
13519 dofloat (sizeflag);
13523 dp = get_valid_dis386 (dp, info);
13524 if (dp != NULL && putop (dp->name, sizeflag) == 0)
13526 get_sib (info, sizeflag);
13527 for (i = 0; i < MAX_OPERANDS; ++i)
13530 op_ad = MAX_OPERANDS - 1 - i;
13532 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13533 /* For EVEX instruction after the last operand masking
13534 should be printed. */
13535 if (i == 0 && vex.evex)
13537 /* Don't print {%k0}. */
13538 if (vex.mask_register_specifier)
13541 oappend (names_mask[vex.mask_register_specifier]);
13551 /* Check if the REX prefix is used. */
13552 if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13553 all_prefixes[last_rex_prefix] = 0;
13555 /* Check if the SEG prefix is used. */
13556 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13557 | PREFIX_FS | PREFIX_GS)) != 0
13558 && (used_prefixes & active_seg_prefix) != 0)
13559 all_prefixes[last_seg_prefix] = 0;
13561 /* Check if the ADDR prefix is used. */
13562 if ((prefixes & PREFIX_ADDR) != 0
13563 && (used_prefixes & PREFIX_ADDR) != 0)
13564 all_prefixes[last_addr_prefix] = 0;
13566 /* Check if the DATA prefix is used. */
13567 if ((prefixes & PREFIX_DATA) != 0
13568 && (used_prefixes & PREFIX_DATA) != 0)
13569 all_prefixes[last_data_prefix] = 0;
13571 /* Print the extra prefixes. */
13573 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13574 if (all_prefixes[i])
13577 name = prefix_name (all_prefixes[i], orig_sizeflag);
13580 prefix_length += strlen (name) + 1;
13581 (*info->fprintf_func) (info->stream, "%s ", name);
13584 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13585 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13586 used by putop and MMX/SSE operand and may be overriden by the
13587 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13589 if (dp->prefix_requirement == PREFIX_OPCODE
13590 && dp != &bad_opcode
13592 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13594 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13596 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13598 && (used_prefixes & PREFIX_DATA) == 0))))
13600 (*info->fprintf_func) (info->stream, "(bad)");
13601 return end_codep - priv.the_buffer;
13604 /* Check maximum code length. */
13605 if ((codep - start_codep) > MAX_CODE_LENGTH)
13607 (*info->fprintf_func) (info->stream, "(bad)");
13608 return MAX_CODE_LENGTH;
13611 obufp = mnemonicendp;
13612 for (i = strlen (obuf) + prefix_length; i < 6; i++)
13615 (*info->fprintf_func) (info->stream, "%s", obuf);
13617 /* The enter and bound instructions are printed with operands in the same
13618 order as the intel book; everything else is printed in reverse order. */
13619 if (intel_syntax || two_source_ops)
13623 for (i = 0; i < MAX_OPERANDS; ++i)
13624 op_txt[i] = op_out[i];
13626 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13627 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13629 op_txt[2] = op_out[3];
13630 op_txt[3] = op_out[2];
13633 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13635 op_ad = op_index[i];
13636 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13637 op_index[MAX_OPERANDS - 1 - i] = op_ad;
13638 riprel = op_riprel[i];
13639 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13640 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13645 for (i = 0; i < MAX_OPERANDS; ++i)
13646 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13650 for (i = 0; i < MAX_OPERANDS; ++i)
13654 (*info->fprintf_func) (info->stream, ",");
13655 if (op_index[i] != -1 && !op_riprel[i])
13656 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13658 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13662 for (i = 0; i < MAX_OPERANDS; i++)
13663 if (op_index[i] != -1 && op_riprel[i])
13665 (*info->fprintf_func) (info->stream, " # ");
13666 (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13667 + op_address[op_index[i]]), info);
13670 return codep - priv.the_buffer;
13673 static const char *float_mem[] = {
13748 static const unsigned char float_mem_mode[] = {
13823 #define ST { OP_ST, 0 }
13824 #define STi { OP_STi, 0 }
13826 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13827 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13828 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13829 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13830 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13831 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13832 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13833 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13834 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13836 static const struct dis386 float_reg[][8] = {
13839 { "fadd", { ST, STi }, 0 },
13840 { "fmul", { ST, STi }, 0 },
13841 { "fcom", { STi }, 0 },
13842 { "fcomp", { STi }, 0 },
13843 { "fsub", { ST, STi }, 0 },
13844 { "fsubr", { ST, STi }, 0 },
13845 { "fdiv", { ST, STi }, 0 },
13846 { "fdivr", { ST, STi }, 0 },
13850 { "fld", { STi }, 0 },
13851 { "fxch", { STi }, 0 },
13861 { "fcmovb", { ST, STi }, 0 },
13862 { "fcmove", { ST, STi }, 0 },
13863 { "fcmovbe",{ ST, STi }, 0 },
13864 { "fcmovu", { ST, STi }, 0 },
13872 { "fcmovnb",{ ST, STi }, 0 },
13873 { "fcmovne",{ ST, STi }, 0 },
13874 { "fcmovnbe",{ ST, STi }, 0 },
13875 { "fcmovnu",{ ST, STi }, 0 },
13877 { "fucomi", { ST, STi }, 0 },
13878 { "fcomi", { ST, STi }, 0 },
13883 { "fadd", { STi, ST }, 0 },
13884 { "fmul", { STi, ST }, 0 },
13887 { "fsub!M", { STi, ST }, 0 },
13888 { "fsubM", { STi, ST }, 0 },
13889 { "fdiv!M", { STi, ST }, 0 },
13890 { "fdivM", { STi, ST }, 0 },
13894 { "ffree", { STi }, 0 },
13896 { "fst", { STi }, 0 },
13897 { "fstp", { STi }, 0 },
13898 { "fucom", { STi }, 0 },
13899 { "fucomp", { STi }, 0 },
13905 { "faddp", { STi, ST }, 0 },
13906 { "fmulp", { STi, ST }, 0 },
13909 { "fsub!Mp", { STi, ST }, 0 },
13910 { "fsubMp", { STi, ST }, 0 },
13911 { "fdiv!Mp", { STi, ST }, 0 },
13912 { "fdivMp", { STi, ST }, 0 },
13916 { "ffreep", { STi }, 0 },
13921 { "fucomip", { ST, STi }, 0 },
13922 { "fcomip", { ST, STi }, 0 },
13927 static char *fgrps[][8] = {
13930 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13935 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13940 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13945 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13950 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13955 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13960 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13961 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13966 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13971 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13976 swap_operand (void)
13978 mnemonicendp[0] = '.';
13979 mnemonicendp[1] = 's';
13984 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13985 int sizeflag ATTRIBUTE_UNUSED)
13987 /* Skip mod/rm byte. */
13993 dofloat (int sizeflag)
13995 const struct dis386 *dp;
13996 unsigned char floatop;
13998 floatop = codep[-1];
14000 if (modrm.mod != 3)
14002 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
14004 putop (float_mem[fp_indx], sizeflag);
14007 OP_E (float_mem_mode[fp_indx], sizeflag);
14010 /* Skip mod/rm byte. */
14014 dp = &float_reg[floatop - 0xd8][modrm.reg];
14015 if (dp->name == NULL)
14017 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
14019 /* Instruction fnstsw is only one with strange arg. */
14020 if (floatop == 0xdf && codep[-1] == 0xe0)
14021 strcpy (op_out[0], names16[0]);
14025 putop (dp->name, sizeflag);
14030 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
14035 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
14039 /* Like oappend (below), but S is a string starting with '%'.
14040 In Intel syntax, the '%' is elided. */
14042 oappend_maybe_intel (const char *s)
14044 oappend (s + intel_syntax);
14048 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14050 oappend_maybe_intel ("%st");
14054 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14056 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
14057 oappend_maybe_intel (scratchbuf);
14060 /* Capital letters in template are macros. */
14062 putop (const char *in_template, int sizeflag)
14067 unsigned int l = 0, len = 1;
14070 #define SAVE_LAST(c) \
14071 if (l < len && l < sizeof (last)) \
14076 for (p = in_template; *p; p++)
14092 while (*++p != '|')
14093 if (*p == '}' || *p == '\0')
14096 /* Fall through. */
14101 while (*++p != '}')
14112 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14116 if (l == 0 && len == 1)
14121 if (sizeflag & SUFFIX_ALWAYS)
14134 if (address_mode == mode_64bit
14135 && !(prefixes & PREFIX_ADDR))
14146 if (intel_syntax && !alt)
14148 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14150 if (sizeflag & DFLAG)
14151 *obufp++ = intel_syntax ? 'd' : 'l';
14153 *obufp++ = intel_syntax ? 'w' : 's';
14154 used_prefixes |= (prefixes & PREFIX_DATA);
14158 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14161 if (modrm.mod == 3)
14167 if (sizeflag & DFLAG)
14168 *obufp++ = intel_syntax ? 'd' : 'l';
14171 used_prefixes |= (prefixes & PREFIX_DATA);
14177 case 'E': /* For jcxz/jecxz */
14178 if (address_mode == mode_64bit)
14180 if (sizeflag & AFLAG)
14186 if (sizeflag & AFLAG)
14188 used_prefixes |= (prefixes & PREFIX_ADDR);
14193 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14195 if (sizeflag & AFLAG)
14196 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14198 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14199 used_prefixes |= (prefixes & PREFIX_ADDR);
14203 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14205 if ((rex & REX_W) || (sizeflag & DFLAG))
14209 if (!(rex & REX_W))
14210 used_prefixes |= (prefixes & PREFIX_DATA);
14215 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14216 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14218 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14221 if (prefixes & PREFIX_DS)
14240 if (l != 0 || len != 1)
14242 if (l != 1 || len != 2 || last[0] != 'X')
14247 if (!need_vex || !vex.evex)
14250 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14252 switch (vex.length)
14270 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14275 /* Fall through. */
14278 if (l != 0 || len != 1)
14286 if (sizeflag & SUFFIX_ALWAYS)
14290 if (intel_mnemonic != cond)
14294 if ((prefixes & PREFIX_FWAIT) == 0)
14297 used_prefixes |= PREFIX_FWAIT;
14303 else if (intel_syntax && (sizeflag & DFLAG))
14307 if (!(rex & REX_W))
14308 used_prefixes |= (prefixes & PREFIX_DATA);
14312 && address_mode == mode_64bit
14313 && isa64 == intel64)
14318 /* Fall through. */
14321 && address_mode == mode_64bit
14322 && ((sizeflag & DFLAG) || (rex & REX_W)))
14327 /* Fall through. */
14330 if (l == 0 && len == 1)
14335 if ((rex & REX_W) == 0
14336 && (prefixes & PREFIX_DATA))
14338 if ((sizeflag & DFLAG) == 0)
14340 used_prefixes |= (prefixes & PREFIX_DATA);
14344 if ((prefixes & PREFIX_DATA)
14346 || (sizeflag & SUFFIX_ALWAYS))
14353 if (sizeflag & DFLAG)
14357 used_prefixes |= (prefixes & PREFIX_DATA);
14363 if (l != 1 || len != 2 || last[0] != 'L')
14369 if ((prefixes & PREFIX_DATA)
14371 || (sizeflag & SUFFIX_ALWAYS))
14378 if (sizeflag & DFLAG)
14379 *obufp++ = intel_syntax ? 'd' : 'l';
14382 used_prefixes |= (prefixes & PREFIX_DATA);
14390 if (address_mode == mode_64bit
14391 && ((sizeflag & DFLAG) || (rex & REX_W)))
14393 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14397 /* Fall through. */
14400 if (l == 0 && len == 1)
14403 if (intel_syntax && !alt)
14406 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14412 if (sizeflag & DFLAG)
14413 *obufp++ = intel_syntax ? 'd' : 'l';
14416 used_prefixes |= (prefixes & PREFIX_DATA);
14422 if (l != 1 || len != 2 || last[0] != 'L')
14428 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14443 else if (sizeflag & DFLAG)
14452 if (intel_syntax && !p[1]
14453 && ((rex & REX_W) || (sizeflag & DFLAG)))
14455 if (!(rex & REX_W))
14456 used_prefixes |= (prefixes & PREFIX_DATA);
14459 if (l == 0 && len == 1)
14463 if (address_mode == mode_64bit
14464 && ((sizeflag & DFLAG) || (rex & REX_W)))
14466 if (sizeflag & SUFFIX_ALWAYS)
14488 /* Fall through. */
14491 if (l == 0 && len == 1)
14496 if (sizeflag & SUFFIX_ALWAYS)
14502 if (sizeflag & DFLAG)
14506 used_prefixes |= (prefixes & PREFIX_DATA);
14520 if (address_mode == mode_64bit
14521 && !(prefixes & PREFIX_ADDR))
14532 if (l != 0 || len != 1)
14537 if (need_vex && vex.prefix)
14539 if (vex.prefix == DATA_PREFIX_OPCODE)
14546 if (prefixes & PREFIX_DATA)
14550 used_prefixes |= (prefixes & PREFIX_DATA);
14554 if (l == 0 && len == 1)
14556 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14567 if (l != 1 || len != 2 || last[0] != 'X')
14575 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14577 switch (vex.length)
14593 if (l == 0 && len == 1)
14595 /* operand size flag for cwtl, cbtw */
14604 else if (sizeflag & DFLAG)
14608 if (!(rex & REX_W))
14609 used_prefixes |= (prefixes & PREFIX_DATA);
14616 && last[0] != 'L'))
14623 if (last[0] == 'X')
14624 *obufp++ = vex.w ? 'd': 's';
14626 *obufp++ = vex.w ? 'q': 'd';
14632 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14634 if (sizeflag & DFLAG)
14638 used_prefixes |= (prefixes & PREFIX_DATA);
14644 if (address_mode == mode_64bit
14645 && (isa64 == intel64
14646 || ((sizeflag & DFLAG) || (rex & REX_W))))
14648 else if ((prefixes & PREFIX_DATA))
14650 if (!(sizeflag & DFLAG))
14652 used_prefixes |= (prefixes & PREFIX_DATA);
14659 mnemonicendp = obufp;
14664 oappend (const char *s)
14666 obufp = stpcpy (obufp, s);
14672 /* Only print the active segment register. */
14673 if (!active_seg_prefix)
14676 used_prefixes |= active_seg_prefix;
14677 switch (active_seg_prefix)
14680 oappend_maybe_intel ("%cs:");
14683 oappend_maybe_intel ("%ds:");
14686 oappend_maybe_intel ("%ss:");
14689 oappend_maybe_intel ("%es:");
14692 oappend_maybe_intel ("%fs:");
14695 oappend_maybe_intel ("%gs:");
14703 OP_indirE (int bytemode, int sizeflag)
14707 OP_E (bytemode, sizeflag);
14711 print_operand_value (char *buf, int hex, bfd_vma disp)
14713 if (address_mode == mode_64bit)
14721 sprintf_vma (tmp, disp);
14722 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14723 strcpy (buf + 2, tmp + i);
14727 bfd_signed_vma v = disp;
14734 /* Check for possible overflow on 0x8000000000000000. */
14737 strcpy (buf, "9223372036854775808");
14751 tmp[28 - i] = (v % 10) + '0';
14755 strcpy (buf, tmp + 29 - i);
14761 sprintf (buf, "0x%x", (unsigned int) disp);
14763 sprintf (buf, "%d", (int) disp);
14767 /* Put DISP in BUF as signed hex number. */
14770 print_displacement (char *buf, bfd_vma disp)
14772 bfd_signed_vma val = disp;
14781 /* Check for possible overflow. */
14784 switch (address_mode)
14787 strcpy (buf + j, "0x8000000000000000");
14790 strcpy (buf + j, "0x80000000");
14793 strcpy (buf + j, "0x8000");
14803 sprintf_vma (tmp, (bfd_vma) val);
14804 for (i = 0; tmp[i] == '0'; i++)
14806 if (tmp[i] == '\0')
14808 strcpy (buf + j, tmp + i);
14812 intel_operand_size (int bytemode, int sizeflag)
14816 && (bytemode == x_mode
14817 || bytemode == evex_half_bcst_xmmq_mode))
14820 oappend ("QWORD PTR ");
14822 oappend ("DWORD PTR ");
14831 oappend ("BYTE PTR ");
14836 case dqw_swap_mode:
14837 oappend ("WORD PTR ");
14840 if (address_mode == mode_64bit && isa64 == intel64)
14842 oappend ("QWORD PTR ");
14845 /* Fall through. */
14847 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14849 oappend ("QWORD PTR ");
14852 /* Fall through. */
14858 oappend ("QWORD PTR ");
14861 if ((sizeflag & DFLAG) || bytemode == dq_mode)
14862 oappend ("DWORD PTR ");
14864 oappend ("WORD PTR ");
14865 used_prefixes |= (prefixes & PREFIX_DATA);
14869 if ((rex & REX_W) || (sizeflag & DFLAG))
14871 oappend ("WORD PTR ");
14872 if (!(rex & REX_W))
14873 used_prefixes |= (prefixes & PREFIX_DATA);
14876 if (sizeflag & DFLAG)
14877 oappend ("QWORD PTR ");
14879 oappend ("DWORD PTR ");
14880 used_prefixes |= (prefixes & PREFIX_DATA);
14883 case d_scalar_mode:
14884 case d_scalar_swap_mode:
14887 oappend ("DWORD PTR ");
14890 case q_scalar_mode:
14891 case q_scalar_swap_mode:
14893 oappend ("QWORD PTR ");
14896 if (address_mode == mode_64bit)
14897 oappend ("QWORD PTR ");
14899 oappend ("DWORD PTR ");
14902 if (sizeflag & DFLAG)
14903 oappend ("FWORD PTR ");
14905 oappend ("DWORD PTR ");
14906 used_prefixes |= (prefixes & PREFIX_DATA);
14909 oappend ("TBYTE PTR ");
14913 case evex_x_gscat_mode:
14914 case evex_x_nobcst_mode:
14917 switch (vex.length)
14920 oappend ("XMMWORD PTR ");
14923 oappend ("YMMWORD PTR ");
14926 oappend ("ZMMWORD PTR ");
14933 oappend ("XMMWORD PTR ");
14936 oappend ("XMMWORD PTR ");
14939 oappend ("YMMWORD PTR ");
14942 case evex_half_bcst_xmmq_mode:
14946 switch (vex.length)
14949 oappend ("QWORD PTR ");
14952 oappend ("XMMWORD PTR ");
14955 oappend ("YMMWORD PTR ");
14965 switch (vex.length)
14970 oappend ("BYTE PTR ");
14980 switch (vex.length)
14985 oappend ("WORD PTR ");
14995 switch (vex.length)
15000 oappend ("DWORD PTR ");
15010 switch (vex.length)
15015 oappend ("QWORD PTR ");
15025 switch (vex.length)
15028 oappend ("WORD PTR ");
15031 oappend ("DWORD PTR ");
15034 oappend ("QWORD PTR ");
15044 switch (vex.length)
15047 oappend ("DWORD PTR ");
15050 oappend ("QWORD PTR ");
15053 oappend ("XMMWORD PTR ");
15063 switch (vex.length)
15066 oappend ("QWORD PTR ");
15069 oappend ("YMMWORD PTR ");
15072 oappend ("ZMMWORD PTR ");
15082 switch (vex.length)
15086 oappend ("XMMWORD PTR ");
15093 oappend ("OWORD PTR ");
15096 case vex_w_dq_mode:
15097 case vex_scalar_w_dq_mode:
15102 oappend ("QWORD PTR ");
15104 oappend ("DWORD PTR ");
15106 case vex_vsib_d_w_dq_mode:
15107 case vex_vsib_q_w_dq_mode:
15114 oappend ("QWORD PTR ");
15116 oappend ("DWORD PTR ");
15120 switch (vex.length)
15123 oappend ("XMMWORD PTR ");
15126 oappend ("YMMWORD PTR ");
15129 oappend ("ZMMWORD PTR ");
15136 case vex_vsib_q_w_d_mode:
15137 case vex_vsib_d_w_d_mode:
15138 if (!need_vex || !vex.evex)
15141 switch (vex.length)
15144 oappend ("QWORD PTR ");
15147 oappend ("XMMWORD PTR ");
15150 oappend ("YMMWORD PTR ");
15158 if (!need_vex || vex.length != 128)
15161 oappend ("DWORD PTR ");
15163 oappend ("BYTE PTR ");
15169 oappend ("QWORD PTR ");
15171 oappend ("WORD PTR ");
15180 OP_E_register (int bytemode, int sizeflag)
15182 int reg = modrm.rm;
15183 const char **names;
15189 if ((sizeflag & SUFFIX_ALWAYS)
15190 && (bytemode == b_swap_mode
15191 || bytemode == v_swap_mode
15192 || bytemode == dqw_swap_mode))
15218 names = address_mode == mode_64bit ? names64 : names32;
15224 if (address_mode == mode_64bit && isa64 == intel64)
15229 /* Fall through. */
15231 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15237 /* Fall through. */
15244 case dqw_swap_mode:
15250 if ((sizeflag & DFLAG)
15251 || (bytemode != v_mode
15252 && bytemode != v_swap_mode))
15256 used_prefixes |= (prefixes & PREFIX_DATA);
15266 names = names_mask;
15271 oappend (INTERNAL_DISASSEMBLER_ERROR);
15274 oappend (names[reg]);
15278 OP_E_memory (int bytemode, int sizeflag)
15281 int add = (rex & REX_B) ? 8 : 0;
15287 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
15289 && bytemode != x_mode
15290 && bytemode != xmmq_mode
15291 && bytemode != evex_half_bcst_xmmq_mode)
15300 case dqw_swap_mode:
15307 case vex_vsib_d_w_dq_mode:
15308 case vex_vsib_d_w_d_mode:
15309 case vex_vsib_q_w_dq_mode:
15310 case vex_vsib_q_w_d_mode:
15311 case evex_x_gscat_mode:
15313 shift = vex.w ? 3 : 2;
15316 case evex_half_bcst_xmmq_mode:
15320 shift = vex.w ? 3 : 2;
15323 /* Fall through. */
15327 case evex_x_nobcst_mode:
15329 switch (vex.length)
15352 case q_scalar_mode:
15354 case q_scalar_swap_mode:
15360 case d_scalar_mode:
15362 case d_scalar_swap_mode:
15374 /* Make necessary corrections to shift for modes that need it.
15375 For these modes we currently have shift 4, 5 or 6 depending on
15376 vex.length (it corresponds to xmmword, ymmword or zmmword
15377 operand). We might want to make it 3, 4 or 5 (e.g. for
15378 xmmq_mode). In case of broadcast enabled the corrections
15379 aren't needed, as element size is always 32 or 64 bits. */
15381 && (bytemode == xmmq_mode
15382 || bytemode == evex_half_bcst_xmmq_mode))
15384 else if (bytemode == xmmqd_mode)
15386 else if (bytemode == xmmdw_mode)
15388 else if (bytemode == ymmq_mode && vex.length == 128)
15396 intel_operand_size (bytemode, sizeflag);
15399 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15401 /* 32/64 bit address mode */
15410 int addr32flag = !((sizeflag & AFLAG)
15411 || bytemode == v_bnd_mode
15412 || bytemode == bnd_mode);
15413 const char **indexes64 = names64;
15414 const char **indexes32 = names32;
15424 vindex = sib.index;
15430 case vex_vsib_d_w_dq_mode:
15431 case vex_vsib_d_w_d_mode:
15432 case vex_vsib_q_w_dq_mode:
15433 case vex_vsib_q_w_d_mode:
15443 switch (vex.length)
15446 indexes64 = indexes32 = names_xmm;
15450 || bytemode == vex_vsib_q_w_dq_mode
15451 || bytemode == vex_vsib_q_w_d_mode)
15452 indexes64 = indexes32 = names_ymm;
15454 indexes64 = indexes32 = names_xmm;
15458 || bytemode == vex_vsib_q_w_dq_mode
15459 || bytemode == vex_vsib_q_w_d_mode)
15460 indexes64 = indexes32 = names_zmm;
15462 indexes64 = indexes32 = names_ymm;
15469 haveindex = vindex != 4;
15476 rbase = base + add;
15484 if (address_mode == mode_64bit && !havesib)
15490 FETCH_DATA (the_info, codep + 1);
15492 if ((disp & 0x80) != 0)
15494 if (vex.evex && shift > 0)
15502 /* In 32bit mode, we need index register to tell [offset] from
15503 [eiz*1 + offset]. */
15504 needindex = (havesib
15507 && address_mode == mode_32bit);
15508 havedisp = (havebase
15510 || (havesib && (haveindex || scale != 0)));
15513 if (modrm.mod != 0 || base == 5)
15515 if (havedisp || riprel)
15516 print_displacement (scratchbuf, disp);
15518 print_operand_value (scratchbuf, 1, disp);
15519 oappend (scratchbuf);
15523 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15527 if ((havebase || haveindex || riprel)
15528 && (bytemode != v_bnd_mode)
15529 && (bytemode != bnd_mode))
15530 used_prefixes |= PREFIX_ADDR;
15532 if (havedisp || (intel_syntax && riprel))
15534 *obufp++ = open_char;
15535 if (intel_syntax && riprel)
15538 oappend (!addr32flag ? "rip" : "eip");
15542 oappend (address_mode == mode_64bit && !addr32flag
15543 ? names64[rbase] : names32[rbase]);
15546 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15547 print index to tell base + index from base. */
15551 || (havebase && base != ESP_REG_NUM))
15553 if (!intel_syntax || havebase)
15555 *obufp++ = separator_char;
15559 oappend (address_mode == mode_64bit && !addr32flag
15560 ? indexes64[vindex] : indexes32[vindex]);
15562 oappend (address_mode == mode_64bit && !addr32flag
15563 ? index64 : index32);
15565 *obufp++ = scale_char;
15567 sprintf (scratchbuf, "%d", 1 << scale);
15568 oappend (scratchbuf);
15572 && (disp || modrm.mod != 0 || base == 5))
15574 if (!havedisp || (bfd_signed_vma) disp >= 0)
15579 else if (modrm.mod != 1 && disp != -disp)
15583 disp = - (bfd_signed_vma) disp;
15587 print_displacement (scratchbuf, disp);
15589 print_operand_value (scratchbuf, 1, disp);
15590 oappend (scratchbuf);
15593 *obufp++ = close_char;
15596 else if (intel_syntax)
15598 if (modrm.mod != 0 || base == 5)
15600 if (!active_seg_prefix)
15602 oappend (names_seg[ds_reg - es_reg]);
15605 print_operand_value (scratchbuf, 1, disp);
15606 oappend (scratchbuf);
15612 /* 16 bit address mode */
15613 used_prefixes |= prefixes & PREFIX_ADDR;
15620 if ((disp & 0x8000) != 0)
15625 FETCH_DATA (the_info, codep + 1);
15627 if ((disp & 0x80) != 0)
15632 if ((disp & 0x8000) != 0)
15638 if (modrm.mod != 0 || modrm.rm == 6)
15640 print_displacement (scratchbuf, disp);
15641 oappend (scratchbuf);
15644 if (modrm.mod != 0 || modrm.rm != 6)
15646 *obufp++ = open_char;
15648 oappend (index16[modrm.rm]);
15650 && (disp || modrm.mod != 0 || modrm.rm == 6))
15652 if ((bfd_signed_vma) disp >= 0)
15657 else if (modrm.mod != 1)
15661 disp = - (bfd_signed_vma) disp;
15664 print_displacement (scratchbuf, disp);
15665 oappend (scratchbuf);
15668 *obufp++ = close_char;
15671 else if (intel_syntax)
15673 if (!active_seg_prefix)
15675 oappend (names_seg[ds_reg - es_reg]);
15678 print_operand_value (scratchbuf, 1, disp & 0xffff);
15679 oappend (scratchbuf);
15682 if (vex.evex && vex.b
15683 && (bytemode == x_mode
15684 || bytemode == xmmq_mode
15685 || bytemode == evex_half_bcst_xmmq_mode))
15688 || bytemode == xmmq_mode
15689 || bytemode == evex_half_bcst_xmmq_mode)
15691 switch (vex.length)
15694 oappend ("{1to2}");
15697 oappend ("{1to4}");
15700 oappend ("{1to8}");
15708 switch (vex.length)
15711 oappend ("{1to4}");
15714 oappend ("{1to8}");
15717 oappend ("{1to16}");
15727 OP_E (int bytemode, int sizeflag)
15729 /* Skip mod/rm byte. */
15733 if (modrm.mod == 3)
15734 OP_E_register (bytemode, sizeflag);
15736 OP_E_memory (bytemode, sizeflag);
15740 OP_G (int bytemode, int sizeflag)
15751 oappend (names8rex[modrm.reg + add]);
15753 oappend (names8[modrm.reg + add]);
15756 oappend (names16[modrm.reg + add]);
15761 oappend (names32[modrm.reg + add]);
15764 oappend (names64[modrm.reg + add]);
15767 oappend (names_bnd[modrm.reg]);
15774 case dqw_swap_mode:
15777 oappend (names64[modrm.reg + add]);
15780 if ((sizeflag & DFLAG) || bytemode != v_mode)
15781 oappend (names32[modrm.reg + add]);
15783 oappend (names16[modrm.reg + add]);
15784 used_prefixes |= (prefixes & PREFIX_DATA);
15788 if (address_mode == mode_64bit)
15789 oappend (names64[modrm.reg + add]);
15791 oappend (names32[modrm.reg + add]);
15795 if ((modrm.reg + add) > 0x7)
15800 oappend (names_mask[modrm.reg + add]);
15803 oappend (INTERNAL_DISASSEMBLER_ERROR);
15816 FETCH_DATA (the_info, codep + 8);
15817 a = *codep++ & 0xff;
15818 a |= (*codep++ & 0xff) << 8;
15819 a |= (*codep++ & 0xff) << 16;
15820 a |= (*codep++ & 0xffu) << 24;
15821 b = *codep++ & 0xff;
15822 b |= (*codep++ & 0xff) << 8;
15823 b |= (*codep++ & 0xff) << 16;
15824 b |= (*codep++ & 0xffu) << 24;
15825 x = a + ((bfd_vma) b << 32);
15833 static bfd_signed_vma
15836 bfd_signed_vma x = 0;
15838 FETCH_DATA (the_info, codep + 4);
15839 x = *codep++ & (bfd_signed_vma) 0xff;
15840 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15841 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15842 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15846 static bfd_signed_vma
15849 bfd_signed_vma x = 0;
15851 FETCH_DATA (the_info, codep + 4);
15852 x = *codep++ & (bfd_signed_vma) 0xff;
15853 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15854 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15855 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15857 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15867 FETCH_DATA (the_info, codep + 2);
15868 x = *codep++ & 0xff;
15869 x |= (*codep++ & 0xff) << 8;
15874 set_op (bfd_vma op, int riprel)
15876 op_index[op_ad] = op_ad;
15877 if (address_mode == mode_64bit)
15879 op_address[op_ad] = op;
15880 op_riprel[op_ad] = riprel;
15884 /* Mask to get a 32-bit address. */
15885 op_address[op_ad] = op & 0xffffffff;
15886 op_riprel[op_ad] = riprel & 0xffffffff;
15891 OP_REG (int code, int sizeflag)
15898 case es_reg: case ss_reg: case cs_reg:
15899 case ds_reg: case fs_reg: case gs_reg:
15900 oappend (names_seg[code - es_reg]);
15912 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15913 case sp_reg: case bp_reg: case si_reg: case di_reg:
15914 s = names16[code - ax_reg + add];
15916 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15917 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15920 s = names8rex[code - al_reg + add];
15922 s = names8[code - al_reg];
15924 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15925 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15926 if (address_mode == mode_64bit
15927 && ((sizeflag & DFLAG) || (rex & REX_W)))
15929 s = names64[code - rAX_reg + add];
15932 code += eAX_reg - rAX_reg;
15933 /* Fall through. */
15934 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15935 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15938 s = names64[code - eAX_reg + add];
15941 if (sizeflag & DFLAG)
15942 s = names32[code - eAX_reg + add];
15944 s = names16[code - eAX_reg + add];
15945 used_prefixes |= (prefixes & PREFIX_DATA);
15949 s = INTERNAL_DISASSEMBLER_ERROR;
15956 OP_IMREG (int code, int sizeflag)
15968 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15969 case sp_reg: case bp_reg: case si_reg: case di_reg:
15970 s = names16[code - ax_reg];
15972 case es_reg: case ss_reg: case cs_reg:
15973 case ds_reg: case fs_reg: case gs_reg:
15974 s = names_seg[code - es_reg];
15976 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15977 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15980 s = names8rex[code - al_reg];
15982 s = names8[code - al_reg];
15984 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15985 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15988 s = names64[code - eAX_reg];
15991 if (sizeflag & DFLAG)
15992 s = names32[code - eAX_reg];
15994 s = names16[code - eAX_reg];
15995 used_prefixes |= (prefixes & PREFIX_DATA);
15998 case z_mode_ax_reg:
15999 if ((rex & REX_W) || (sizeflag & DFLAG))
16003 if (!(rex & REX_W))
16004 used_prefixes |= (prefixes & PREFIX_DATA);
16007 s = INTERNAL_DISASSEMBLER_ERROR;
16014 OP_I (int bytemode, int sizeflag)
16017 bfd_signed_vma mask = -1;
16022 FETCH_DATA (the_info, codep + 1);
16027 if (address_mode == mode_64bit)
16032 /* Fall through. */
16039 if (sizeflag & DFLAG)
16049 used_prefixes |= (prefixes & PREFIX_DATA);
16061 oappend (INTERNAL_DISASSEMBLER_ERROR);
16066 scratchbuf[0] = '$';
16067 print_operand_value (scratchbuf + 1, 1, op);
16068 oappend_maybe_intel (scratchbuf);
16069 scratchbuf[0] = '\0';
16073 OP_I64 (int bytemode, int sizeflag)
16076 bfd_signed_vma mask = -1;
16078 if (address_mode != mode_64bit)
16080 OP_I (bytemode, sizeflag);
16087 FETCH_DATA (the_info, codep + 1);
16097 if (sizeflag & DFLAG)
16107 used_prefixes |= (prefixes & PREFIX_DATA);
16115 oappend (INTERNAL_DISASSEMBLER_ERROR);
16120 scratchbuf[0] = '$';
16121 print_operand_value (scratchbuf + 1, 1, op);
16122 oappend_maybe_intel (scratchbuf);
16123 scratchbuf[0] = '\0';
16127 OP_sI (int bytemode, int sizeflag)
16135 FETCH_DATA (the_info, codep + 1);
16137 if ((op & 0x80) != 0)
16139 if (bytemode == b_T_mode)
16141 if (address_mode != mode_64bit
16142 || !((sizeflag & DFLAG) || (rex & REX_W)))
16144 /* The operand-size prefix is overridden by a REX prefix. */
16145 if ((sizeflag & DFLAG) || (rex & REX_W))
16153 if (!(rex & REX_W))
16155 if (sizeflag & DFLAG)
16163 /* The operand-size prefix is overridden by a REX prefix. */
16164 if ((sizeflag & DFLAG) || (rex & REX_W))
16170 oappend (INTERNAL_DISASSEMBLER_ERROR);
16174 scratchbuf[0] = '$';
16175 print_operand_value (scratchbuf + 1, 1, op);
16176 oappend_maybe_intel (scratchbuf);
16180 OP_J (int bytemode, int sizeflag)
16184 bfd_vma segment = 0;
16189 FETCH_DATA (the_info, codep + 1);
16191 if ((disp & 0x80) != 0)
16195 if (isa64 == amd64)
16197 if ((sizeflag & DFLAG)
16198 || (address_mode == mode_64bit
16199 && (isa64 != amd64 || (rex & REX_W))))
16204 if ((disp & 0x8000) != 0)
16206 /* In 16bit mode, address is wrapped around at 64k within
16207 the same segment. Otherwise, a data16 prefix on a jump
16208 instruction means that the pc is masked to 16 bits after
16209 the displacement is added! */
16211 if ((prefixes & PREFIX_DATA) == 0)
16212 segment = ((start_pc + (codep - start_codep))
16213 & ~((bfd_vma) 0xffff));
16215 if (address_mode != mode_64bit
16216 || (isa64 == amd64 && !(rex & REX_W)))
16217 used_prefixes |= (prefixes & PREFIX_DATA);
16220 oappend (INTERNAL_DISASSEMBLER_ERROR);
16223 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16225 print_operand_value (scratchbuf, 1, disp);
16226 oappend (scratchbuf);
16230 OP_SEG (int bytemode, int sizeflag)
16232 if (bytemode == w_mode)
16233 oappend (names_seg[modrm.reg]);
16235 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16239 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16243 if (sizeflag & DFLAG)
16253 used_prefixes |= (prefixes & PREFIX_DATA);
16255 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16257 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16258 oappend (scratchbuf);
16262 OP_OFF (int bytemode, int sizeflag)
16266 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16267 intel_operand_size (bytemode, sizeflag);
16270 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16277 if (!active_seg_prefix)
16279 oappend (names_seg[ds_reg - es_reg]);
16283 print_operand_value (scratchbuf, 1, off);
16284 oappend (scratchbuf);
16288 OP_OFF64 (int bytemode, int sizeflag)
16292 if (address_mode != mode_64bit
16293 || (prefixes & PREFIX_ADDR))
16295 OP_OFF (bytemode, sizeflag);
16299 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16300 intel_operand_size (bytemode, sizeflag);
16307 if (!active_seg_prefix)
16309 oappend (names_seg[ds_reg - es_reg]);
16313 print_operand_value (scratchbuf, 1, off);
16314 oappend (scratchbuf);
16318 ptr_reg (int code, int sizeflag)
16322 *obufp++ = open_char;
16323 used_prefixes |= (prefixes & PREFIX_ADDR);
16324 if (address_mode == mode_64bit)
16326 if (!(sizeflag & AFLAG))
16327 s = names32[code - eAX_reg];
16329 s = names64[code - eAX_reg];
16331 else if (sizeflag & AFLAG)
16332 s = names32[code - eAX_reg];
16334 s = names16[code - eAX_reg];
16336 *obufp++ = close_char;
16341 OP_ESreg (int code, int sizeflag)
16347 case 0x6d: /* insw/insl */
16348 intel_operand_size (z_mode, sizeflag);
16350 case 0xa5: /* movsw/movsl/movsq */
16351 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16352 case 0xab: /* stosw/stosl */
16353 case 0xaf: /* scasw/scasl */
16354 intel_operand_size (v_mode, sizeflag);
16357 intel_operand_size (b_mode, sizeflag);
16360 oappend_maybe_intel ("%es:");
16361 ptr_reg (code, sizeflag);
16365 OP_DSreg (int code, int sizeflag)
16371 case 0x6f: /* outsw/outsl */
16372 intel_operand_size (z_mode, sizeflag);
16374 case 0xa5: /* movsw/movsl/movsq */
16375 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16376 case 0xad: /* lodsw/lodsl/lodsq */
16377 intel_operand_size (v_mode, sizeflag);
16380 intel_operand_size (b_mode, sizeflag);
16383 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16384 default segment register DS is printed. */
16385 if (!active_seg_prefix)
16386 active_seg_prefix = PREFIX_DS;
16388 ptr_reg (code, sizeflag);
16392 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16400 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16402 all_prefixes[last_lock_prefix] = 0;
16403 used_prefixes |= PREFIX_LOCK;
16408 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16409 oappend_maybe_intel (scratchbuf);
16413 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16422 sprintf (scratchbuf, "db%d", modrm.reg + add);
16424 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16425 oappend (scratchbuf);
16429 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16431 sprintf (scratchbuf, "%%tr%d", modrm.reg);
16432 oappend_maybe_intel (scratchbuf);
16436 OP_R (int bytemode, int sizeflag)
16438 /* Skip mod/rm byte. */
16441 OP_E_register (bytemode, sizeflag);
16445 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16447 int reg = modrm.reg;
16448 const char **names;
16450 used_prefixes |= (prefixes & PREFIX_DATA);
16451 if (prefixes & PREFIX_DATA)
16460 oappend (names[reg]);
16464 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16466 int reg = modrm.reg;
16467 const char **names;
16479 && bytemode != xmm_mode
16480 && bytemode != xmmq_mode
16481 && bytemode != evex_half_bcst_xmmq_mode
16482 && bytemode != ymm_mode
16483 && bytemode != scalar_mode)
16485 switch (vex.length)
16492 || (bytemode != vex_vsib_q_w_dq_mode
16493 && bytemode != vex_vsib_q_w_d_mode))
16505 else if (bytemode == xmmq_mode
16506 || bytemode == evex_half_bcst_xmmq_mode)
16508 switch (vex.length)
16521 else if (bytemode == ymm_mode)
16525 oappend (names[reg]);
16529 OP_EM (int bytemode, int sizeflag)
16532 const char **names;
16534 if (modrm.mod != 3)
16537 && (bytemode == v_mode || bytemode == v_swap_mode))
16539 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16540 used_prefixes |= (prefixes & PREFIX_DATA);
16542 OP_E (bytemode, sizeflag);
16546 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16549 /* Skip mod/rm byte. */
16552 used_prefixes |= (prefixes & PREFIX_DATA);
16554 if (prefixes & PREFIX_DATA)
16563 oappend (names[reg]);
16566 /* cvt* are the only instructions in sse2 which have
16567 both SSE and MMX operands and also have 0x66 prefix
16568 in their opcode. 0x66 was originally used to differentiate
16569 between SSE and MMX instruction(operands). So we have to handle the
16570 cvt* separately using OP_EMC and OP_MXC */
16572 OP_EMC (int bytemode, int sizeflag)
16574 if (modrm.mod != 3)
16576 if (intel_syntax && bytemode == v_mode)
16578 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16579 used_prefixes |= (prefixes & PREFIX_DATA);
16581 OP_E (bytemode, sizeflag);
16585 /* Skip mod/rm byte. */
16588 used_prefixes |= (prefixes & PREFIX_DATA);
16589 oappend (names_mm[modrm.rm]);
16593 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16595 used_prefixes |= (prefixes & PREFIX_DATA);
16596 oappend (names_mm[modrm.reg]);
16600 OP_EX (int bytemode, int sizeflag)
16603 const char **names;
16605 /* Skip mod/rm byte. */
16609 if (modrm.mod != 3)
16611 OP_E_memory (bytemode, sizeflag);
16626 if ((sizeflag & SUFFIX_ALWAYS)
16627 && (bytemode == x_swap_mode
16628 || bytemode == d_swap_mode
16629 || bytemode == dqw_swap_mode
16630 || bytemode == d_scalar_swap_mode
16631 || bytemode == q_swap_mode
16632 || bytemode == q_scalar_swap_mode))
16636 && bytemode != xmm_mode
16637 && bytemode != xmmdw_mode
16638 && bytemode != xmmqd_mode
16639 && bytemode != xmm_mb_mode
16640 && bytemode != xmm_mw_mode
16641 && bytemode != xmm_md_mode
16642 && bytemode != xmm_mq_mode
16643 && bytemode != xmm_mdq_mode
16644 && bytemode != xmmq_mode
16645 && bytemode != evex_half_bcst_xmmq_mode
16646 && bytemode != ymm_mode
16647 && bytemode != d_scalar_mode
16648 && bytemode != d_scalar_swap_mode
16649 && bytemode != q_scalar_mode
16650 && bytemode != q_scalar_swap_mode
16651 && bytemode != vex_scalar_w_dq_mode)
16653 switch (vex.length)
16668 else if (bytemode == xmmq_mode
16669 || bytemode == evex_half_bcst_xmmq_mode)
16671 switch (vex.length)
16684 else if (bytemode == ymm_mode)
16688 oappend (names[reg]);
16692 OP_MS (int bytemode, int sizeflag)
16694 if (modrm.mod == 3)
16695 OP_EM (bytemode, sizeflag);
16701 OP_XS (int bytemode, int sizeflag)
16703 if (modrm.mod == 3)
16704 OP_EX (bytemode, sizeflag);
16710 OP_M (int bytemode, int sizeflag)
16712 if (modrm.mod == 3)
16713 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16716 OP_E (bytemode, sizeflag);
16720 OP_0f07 (int bytemode, int sizeflag)
16722 if (modrm.mod != 3 || modrm.rm != 0)
16725 OP_E (bytemode, sizeflag);
16728 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16729 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16732 NOP_Fixup1 (int bytemode, int sizeflag)
16734 if ((prefixes & PREFIX_DATA) != 0
16737 && address_mode == mode_64bit))
16738 OP_REG (bytemode, sizeflag);
16740 strcpy (obuf, "nop");
16744 NOP_Fixup2 (int bytemode, int sizeflag)
16746 if ((prefixes & PREFIX_DATA) != 0
16749 && address_mode == mode_64bit))
16750 OP_IMREG (bytemode, sizeflag);
16753 static const char *const Suffix3DNow[] = {
16754 /* 00 */ NULL, NULL, NULL, NULL,
16755 /* 04 */ NULL, NULL, NULL, NULL,
16756 /* 08 */ NULL, NULL, NULL, NULL,
16757 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
16758 /* 10 */ NULL, NULL, NULL, NULL,
16759 /* 14 */ NULL, NULL, NULL, NULL,
16760 /* 18 */ NULL, NULL, NULL, NULL,
16761 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
16762 /* 20 */ NULL, NULL, NULL, NULL,
16763 /* 24 */ NULL, NULL, NULL, NULL,
16764 /* 28 */ NULL, NULL, NULL, NULL,
16765 /* 2C */ NULL, NULL, NULL, NULL,
16766 /* 30 */ NULL, NULL, NULL, NULL,
16767 /* 34 */ NULL, NULL, NULL, NULL,
16768 /* 38 */ NULL, NULL, NULL, NULL,
16769 /* 3C */ NULL, NULL, NULL, NULL,
16770 /* 40 */ NULL, NULL, NULL, NULL,
16771 /* 44 */ NULL, NULL, NULL, NULL,
16772 /* 48 */ NULL, NULL, NULL, NULL,
16773 /* 4C */ NULL, NULL, NULL, NULL,
16774 /* 50 */ NULL, NULL, NULL, NULL,
16775 /* 54 */ NULL, NULL, NULL, NULL,
16776 /* 58 */ NULL, NULL, NULL, NULL,
16777 /* 5C */ NULL, NULL, NULL, NULL,
16778 /* 60 */ NULL, NULL, NULL, NULL,
16779 /* 64 */ NULL, NULL, NULL, NULL,
16780 /* 68 */ NULL, NULL, NULL, NULL,
16781 /* 6C */ NULL, NULL, NULL, NULL,
16782 /* 70 */ NULL, NULL, NULL, NULL,
16783 /* 74 */ NULL, NULL, NULL, NULL,
16784 /* 78 */ NULL, NULL, NULL, NULL,
16785 /* 7C */ NULL, NULL, NULL, NULL,
16786 /* 80 */ NULL, NULL, NULL, NULL,
16787 /* 84 */ NULL, NULL, NULL, NULL,
16788 /* 88 */ NULL, NULL, "pfnacc", NULL,
16789 /* 8C */ NULL, NULL, "pfpnacc", NULL,
16790 /* 90 */ "pfcmpge", NULL, NULL, NULL,
16791 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
16792 /* 98 */ NULL, NULL, "pfsub", NULL,
16793 /* 9C */ NULL, NULL, "pfadd", NULL,
16794 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
16795 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
16796 /* A8 */ NULL, NULL, "pfsubr", NULL,
16797 /* AC */ NULL, NULL, "pfacc", NULL,
16798 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
16799 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
16800 /* B8 */ NULL, NULL, NULL, "pswapd",
16801 /* BC */ NULL, NULL, NULL, "pavgusb",
16802 /* C0 */ NULL, NULL, NULL, NULL,
16803 /* C4 */ NULL, NULL, NULL, NULL,
16804 /* C8 */ NULL, NULL, NULL, NULL,
16805 /* CC */ NULL, NULL, NULL, NULL,
16806 /* D0 */ NULL, NULL, NULL, NULL,
16807 /* D4 */ NULL, NULL, NULL, NULL,
16808 /* D8 */ NULL, NULL, NULL, NULL,
16809 /* DC */ NULL, NULL, NULL, NULL,
16810 /* E0 */ NULL, NULL, NULL, NULL,
16811 /* E4 */ NULL, NULL, NULL, NULL,
16812 /* E8 */ NULL, NULL, NULL, NULL,
16813 /* EC */ NULL, NULL, NULL, NULL,
16814 /* F0 */ NULL, NULL, NULL, NULL,
16815 /* F4 */ NULL, NULL, NULL, NULL,
16816 /* F8 */ NULL, NULL, NULL, NULL,
16817 /* FC */ NULL, NULL, NULL, NULL,
16821 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16823 const char *mnemonic;
16825 FETCH_DATA (the_info, codep + 1);
16826 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16827 place where an 8-bit immediate would normally go. ie. the last
16828 byte of the instruction. */
16829 obufp = mnemonicendp;
16830 mnemonic = Suffix3DNow[*codep++ & 0xff];
16832 oappend (mnemonic);
16835 /* Since a variable sized modrm/sib chunk is between the start
16836 of the opcode (0x0f0f) and the opcode suffix, we need to do
16837 all the modrm processing first, and don't know until now that
16838 we have a bad opcode. This necessitates some cleaning up. */
16839 op_out[0][0] = '\0';
16840 op_out[1][0] = '\0';
16843 mnemonicendp = obufp;
16846 static struct op simd_cmp_op[] =
16848 { STRING_COMMA_LEN ("eq") },
16849 { STRING_COMMA_LEN ("lt") },
16850 { STRING_COMMA_LEN ("le") },
16851 { STRING_COMMA_LEN ("unord") },
16852 { STRING_COMMA_LEN ("neq") },
16853 { STRING_COMMA_LEN ("nlt") },
16854 { STRING_COMMA_LEN ("nle") },
16855 { STRING_COMMA_LEN ("ord") }
16859 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16861 unsigned int cmp_type;
16863 FETCH_DATA (the_info, codep + 1);
16864 cmp_type = *codep++ & 0xff;
16865 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16868 char *p = mnemonicendp - 2;
16872 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16873 mnemonicendp += simd_cmp_op[cmp_type].len;
16877 /* We have a reserved extension byte. Output it directly. */
16878 scratchbuf[0] = '$';
16879 print_operand_value (scratchbuf + 1, 1, cmp_type);
16880 oappend_maybe_intel (scratchbuf);
16881 scratchbuf[0] = '\0';
16886 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16887 int sizeflag ATTRIBUTE_UNUSED)
16889 /* mwaitx %eax,%ecx,%ebx */
16892 const char **names = (address_mode == mode_64bit
16893 ? names64 : names32);
16894 strcpy (op_out[0], names[0]);
16895 strcpy (op_out[1], names[1]);
16896 strcpy (op_out[2], names[3]);
16897 two_source_ops = 1;
16899 /* Skip mod/rm byte. */
16905 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16906 int sizeflag ATTRIBUTE_UNUSED)
16908 /* mwait %eax,%ecx */
16911 const char **names = (address_mode == mode_64bit
16912 ? names64 : names32);
16913 strcpy (op_out[0], names[0]);
16914 strcpy (op_out[1], names[1]);
16915 two_source_ops = 1;
16917 /* Skip mod/rm byte. */
16923 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16924 int sizeflag ATTRIBUTE_UNUSED)
16926 /* monitor %eax,%ecx,%edx" */
16929 const char **op1_names;
16930 const char **names = (address_mode == mode_64bit
16931 ? names64 : names32);
16933 if (!(prefixes & PREFIX_ADDR))
16934 op1_names = (address_mode == mode_16bit
16935 ? names16 : names);
16938 /* Remove "addr16/addr32". */
16939 all_prefixes[last_addr_prefix] = 0;
16940 op1_names = (address_mode != mode_32bit
16941 ? names32 : names16);
16942 used_prefixes |= PREFIX_ADDR;
16944 strcpy (op_out[0], op1_names[0]);
16945 strcpy (op_out[1], names[1]);
16946 strcpy (op_out[2], names[2]);
16947 two_source_ops = 1;
16949 /* Skip mod/rm byte. */
16957 /* Throw away prefixes and 1st. opcode byte. */
16958 codep = insn_codep + 1;
16963 REP_Fixup (int bytemode, int sizeflag)
16965 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16967 if (prefixes & PREFIX_REPZ)
16968 all_prefixes[last_repz_prefix] = REP_PREFIX;
16975 OP_IMREG (bytemode, sizeflag);
16978 OP_ESreg (bytemode, sizeflag);
16981 OP_DSreg (bytemode, sizeflag);
16989 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16993 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16995 if (prefixes & PREFIX_REPNZ)
16996 all_prefixes[last_repnz_prefix] = BND_PREFIX;
16999 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
17000 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
17004 HLE_Fixup1 (int bytemode, int sizeflag)
17007 && (prefixes & PREFIX_LOCK) != 0)
17009 if (prefixes & PREFIX_REPZ)
17010 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17011 if (prefixes & PREFIX_REPNZ)
17012 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17015 OP_E (bytemode, sizeflag);
17018 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
17019 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
17023 HLE_Fixup2 (int bytemode, int sizeflag)
17025 if (modrm.mod != 3)
17027 if (prefixes & PREFIX_REPZ)
17028 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17029 if (prefixes & PREFIX_REPNZ)
17030 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17033 OP_E (bytemode, sizeflag);
17036 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
17037 "xrelease" for memory operand. No check for LOCK prefix. */
17040 HLE_Fixup3 (int bytemode, int sizeflag)
17043 && last_repz_prefix > last_repnz_prefix
17044 && (prefixes & PREFIX_REPZ) != 0)
17045 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17047 OP_E (bytemode, sizeflag);
17051 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
17056 /* Change cmpxchg8b to cmpxchg16b. */
17057 char *p = mnemonicendp - 2;
17058 mnemonicendp = stpcpy (p, "16b");
17061 else if ((prefixes & PREFIX_LOCK) != 0)
17063 if (prefixes & PREFIX_REPZ)
17064 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17065 if (prefixes & PREFIX_REPNZ)
17066 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17069 OP_M (bytemode, sizeflag);
17073 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
17075 const char **names;
17079 switch (vex.length)
17093 oappend (names[reg]);
17097 CRC32_Fixup (int bytemode, int sizeflag)
17099 /* Add proper suffix to "crc32". */
17100 char *p = mnemonicendp;
17119 if (sizeflag & DFLAG)
17123 used_prefixes |= (prefixes & PREFIX_DATA);
17127 oappend (INTERNAL_DISASSEMBLER_ERROR);
17134 if (modrm.mod == 3)
17138 /* Skip mod/rm byte. */
17143 add = (rex & REX_B) ? 8 : 0;
17144 if (bytemode == b_mode)
17148 oappend (names8rex[modrm.rm + add]);
17150 oappend (names8[modrm.rm + add]);
17156 oappend (names64[modrm.rm + add]);
17157 else if ((prefixes & PREFIX_DATA))
17158 oappend (names16[modrm.rm + add]);
17160 oappend (names32[modrm.rm + add]);
17164 OP_E (bytemode, sizeflag);
17168 FXSAVE_Fixup (int bytemode, int sizeflag)
17170 /* Add proper suffix to "fxsave" and "fxrstor". */
17174 char *p = mnemonicendp;
17180 OP_M (bytemode, sizeflag);
17183 /* Display the destination register operand for instructions with
17187 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17190 const char **names;
17198 reg = vex.register_specifier;
17205 if (bytemode == vex_scalar_mode)
17207 oappend (names_xmm[reg]);
17211 switch (vex.length)
17218 case vex_vsib_q_w_dq_mode:
17219 case vex_vsib_q_w_d_mode:
17235 names = names_mask;
17249 case vex_vsib_q_w_dq_mode:
17250 case vex_vsib_q_w_d_mode:
17251 names = vex.w ? names_ymm : names_xmm;
17260 names = names_mask;
17274 oappend (names[reg]);
17277 /* Get the VEX immediate byte without moving codep. */
17279 static unsigned char
17280 get_vex_imm8 (int sizeflag, int opnum)
17282 int bytes_before_imm = 0;
17284 if (modrm.mod != 3)
17286 /* There are SIB/displacement bytes. */
17287 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17289 /* 32/64 bit address mode */
17290 int base = modrm.rm;
17292 /* Check SIB byte. */
17295 FETCH_DATA (the_info, codep + 1);
17297 /* When decoding the third source, don't increase
17298 bytes_before_imm as this has already been incremented
17299 by one in OP_E_memory while decoding the second
17302 bytes_before_imm++;
17305 /* Don't increase bytes_before_imm when decoding the third source,
17306 it has already been incremented by OP_E_memory while decoding
17307 the second source operand. */
17313 /* When modrm.rm == 5 or modrm.rm == 4 and base in
17314 SIB == 5, there is a 4 byte displacement. */
17316 /* No displacement. */
17318 /* Fall through. */
17320 /* 4 byte displacement. */
17321 bytes_before_imm += 4;
17324 /* 1 byte displacement. */
17325 bytes_before_imm++;
17332 /* 16 bit address mode */
17333 /* Don't increase bytes_before_imm when decoding the third source,
17334 it has already been incremented by OP_E_memory while decoding
17335 the second source operand. */
17341 /* When modrm.rm == 6, there is a 2 byte displacement. */
17343 /* No displacement. */
17345 /* Fall through. */
17347 /* 2 byte displacement. */
17348 bytes_before_imm += 2;
17351 /* 1 byte displacement: when decoding the third source,
17352 don't increase bytes_before_imm as this has already
17353 been incremented by one in OP_E_memory while decoding
17354 the second source operand. */
17356 bytes_before_imm++;
17364 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17365 return codep [bytes_before_imm];
17369 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17371 const char **names;
17373 if (reg == -1 && modrm.mod != 3)
17375 OP_E_memory (bytemode, sizeflag);
17387 else if (reg > 7 && address_mode != mode_64bit)
17391 switch (vex.length)
17402 oappend (names[reg]);
17406 OP_EX_VexImmW (int bytemode, int sizeflag)
17409 static unsigned char vex_imm8;
17411 if (vex_w_done == 0)
17415 /* Skip mod/rm byte. */
17419 vex_imm8 = get_vex_imm8 (sizeflag, 0);
17422 reg = vex_imm8 >> 4;
17424 OP_EX_VexReg (bytemode, sizeflag, reg);
17426 else if (vex_w_done == 1)
17431 reg = vex_imm8 >> 4;
17433 OP_EX_VexReg (bytemode, sizeflag, reg);
17437 /* Output the imm8 directly. */
17438 scratchbuf[0] = '$';
17439 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17440 oappend_maybe_intel (scratchbuf);
17441 scratchbuf[0] = '\0';
17447 OP_Vex_2src (int bytemode, int sizeflag)
17449 if (modrm.mod == 3)
17451 int reg = modrm.rm;
17455 oappend (names_xmm[reg]);
17460 && (bytemode == v_mode || bytemode == v_swap_mode))
17462 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17463 used_prefixes |= (prefixes & PREFIX_DATA);
17465 OP_E (bytemode, sizeflag);
17470 OP_Vex_2src_1 (int bytemode, int sizeflag)
17472 if (modrm.mod == 3)
17474 /* Skip mod/rm byte. */
17480 oappend (names_xmm[vex.register_specifier]);
17482 OP_Vex_2src (bytemode, sizeflag);
17486 OP_Vex_2src_2 (int bytemode, int sizeflag)
17489 OP_Vex_2src (bytemode, sizeflag);
17491 oappend (names_xmm[vex.register_specifier]);
17495 OP_EX_VexW (int bytemode, int sizeflag)
17503 /* Skip mod/rm byte. */
17508 reg = get_vex_imm8 (sizeflag, 0) >> 4;
17513 reg = get_vex_imm8 (sizeflag, 1) >> 4;
17516 OP_EX_VexReg (bytemode, sizeflag, reg);
17520 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17521 int sizeflag ATTRIBUTE_UNUSED)
17523 /* Skip the immediate byte and check for invalid bits. */
17524 FETCH_DATA (the_info, codep + 1);
17525 if (*codep++ & 0xf)
17530 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17533 const char **names;
17535 FETCH_DATA (the_info, codep + 1);
17538 if (bytemode != x_mode)
17545 if (reg > 7 && address_mode != mode_64bit)
17548 switch (vex.length)
17559 oappend (names[reg]);
17563 OP_XMM_VexW (int bytemode, int sizeflag)
17565 /* Turn off the REX.W bit since it is used for swapping operands
17568 OP_XMM (bytemode, sizeflag);
17572 OP_EX_Vex (int bytemode, int sizeflag)
17574 if (modrm.mod != 3)
17576 if (vex.register_specifier != 0)
17580 OP_EX (bytemode, sizeflag);
17584 OP_XMM_Vex (int bytemode, int sizeflag)
17586 if (modrm.mod != 3)
17588 if (vex.register_specifier != 0)
17592 OP_XMM (bytemode, sizeflag);
17596 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17598 switch (vex.length)
17601 mnemonicendp = stpcpy (obuf, "vzeroupper");
17604 mnemonicendp = stpcpy (obuf, "vzeroall");
17611 static struct op vex_cmp_op[] =
17613 { STRING_COMMA_LEN ("eq") },
17614 { STRING_COMMA_LEN ("lt") },
17615 { STRING_COMMA_LEN ("le") },
17616 { STRING_COMMA_LEN ("unord") },
17617 { STRING_COMMA_LEN ("neq") },
17618 { STRING_COMMA_LEN ("nlt") },
17619 { STRING_COMMA_LEN ("nle") },
17620 { STRING_COMMA_LEN ("ord") },
17621 { STRING_COMMA_LEN ("eq_uq") },
17622 { STRING_COMMA_LEN ("nge") },
17623 { STRING_COMMA_LEN ("ngt") },
17624 { STRING_COMMA_LEN ("false") },
17625 { STRING_COMMA_LEN ("neq_oq") },
17626 { STRING_COMMA_LEN ("ge") },
17627 { STRING_COMMA_LEN ("gt") },
17628 { STRING_COMMA_LEN ("true") },
17629 { STRING_COMMA_LEN ("eq_os") },
17630 { STRING_COMMA_LEN ("lt_oq") },
17631 { STRING_COMMA_LEN ("le_oq") },
17632 { STRING_COMMA_LEN ("unord_s") },
17633 { STRING_COMMA_LEN ("neq_us") },
17634 { STRING_COMMA_LEN ("nlt_uq") },
17635 { STRING_COMMA_LEN ("nle_uq") },
17636 { STRING_COMMA_LEN ("ord_s") },
17637 { STRING_COMMA_LEN ("eq_us") },
17638 { STRING_COMMA_LEN ("nge_uq") },
17639 { STRING_COMMA_LEN ("ngt_uq") },
17640 { STRING_COMMA_LEN ("false_os") },
17641 { STRING_COMMA_LEN ("neq_os") },
17642 { STRING_COMMA_LEN ("ge_oq") },
17643 { STRING_COMMA_LEN ("gt_oq") },
17644 { STRING_COMMA_LEN ("true_us") },
17648 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17650 unsigned int cmp_type;
17652 FETCH_DATA (the_info, codep + 1);
17653 cmp_type = *codep++ & 0xff;
17654 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17657 char *p = mnemonicendp - 2;
17661 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17662 mnemonicendp += vex_cmp_op[cmp_type].len;
17666 /* We have a reserved extension byte. Output it directly. */
17667 scratchbuf[0] = '$';
17668 print_operand_value (scratchbuf + 1, 1, cmp_type);
17669 oappend_maybe_intel (scratchbuf);
17670 scratchbuf[0] = '\0';
17675 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17676 int sizeflag ATTRIBUTE_UNUSED)
17678 unsigned int cmp_type;
17683 FETCH_DATA (the_info, codep + 1);
17684 cmp_type = *codep++ & 0xff;
17685 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17686 If it's the case, print suffix, otherwise - print the immediate. */
17687 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17692 char *p = mnemonicendp - 2;
17694 /* vpcmp* can have both one- and two-lettered suffix. */
17708 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17709 mnemonicendp += simd_cmp_op[cmp_type].len;
17713 /* We have a reserved extension byte. Output it directly. */
17714 scratchbuf[0] = '$';
17715 print_operand_value (scratchbuf + 1, 1, cmp_type);
17716 oappend_maybe_intel (scratchbuf);
17717 scratchbuf[0] = '\0';
17721 static const struct op pclmul_op[] =
17723 { STRING_COMMA_LEN ("lql") },
17724 { STRING_COMMA_LEN ("hql") },
17725 { STRING_COMMA_LEN ("lqh") },
17726 { STRING_COMMA_LEN ("hqh") }
17730 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17731 int sizeflag ATTRIBUTE_UNUSED)
17733 unsigned int pclmul_type;
17735 FETCH_DATA (the_info, codep + 1);
17736 pclmul_type = *codep++ & 0xff;
17737 switch (pclmul_type)
17748 if (pclmul_type < ARRAY_SIZE (pclmul_op))
17751 char *p = mnemonicendp - 3;
17756 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17757 mnemonicendp += pclmul_op[pclmul_type].len;
17761 /* We have a reserved extension byte. Output it directly. */
17762 scratchbuf[0] = '$';
17763 print_operand_value (scratchbuf + 1, 1, pclmul_type);
17764 oappend_maybe_intel (scratchbuf);
17765 scratchbuf[0] = '\0';
17770 MOVBE_Fixup (int bytemode, int sizeflag)
17772 /* Add proper suffix to "movbe". */
17773 char *p = mnemonicendp;
17782 if (sizeflag & SUFFIX_ALWAYS)
17788 if (sizeflag & DFLAG)
17792 used_prefixes |= (prefixes & PREFIX_DATA);
17797 oappend (INTERNAL_DISASSEMBLER_ERROR);
17804 OP_M (bytemode, sizeflag);
17808 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17811 const char **names;
17813 /* Skip mod/rm byte. */
17827 oappend (names[reg]);
17831 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17833 const char **names;
17840 oappend (names[vex.register_specifier]);
17844 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17847 || (bytemode != mask_mode && bytemode != mask_bd_mode))
17851 if ((rex & REX_R) != 0 || !vex.r)
17857 oappend (names_mask [modrm.reg]);
17861 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17864 || (bytemode != evex_rounding_mode
17865 && bytemode != evex_sae_mode))
17867 if (modrm.mod == 3 && vex.b)
17870 case evex_rounding_mode:
17871 oappend (names_rounding[vex.ll]);
17873 case evex_sae_mode: