1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma, disassemble_info *);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma get64 (void);
58 static bfd_signed_vma get32 (void);
59 static bfd_signed_vma get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void HLE_Fixup1 (int, int);
113 static void HLE_Fixup2 (int, int);
114 static void HLE_Fixup3 (int, int);
115 static void CMPXCHG8B_Fixup (int, int);
116 static void XMM_Fixup (int, int);
117 static void CRC32_Fixup (int, int);
118 static void FXSAVE_Fixup (int, int);
119 static void OP_LWPCB_E (int, int);
120 static void OP_LWP_E (int, int);
121 static void OP_Vex_2src_1 (int, int);
122 static void OP_Vex_2src_2 (int, int);
124 static void MOVBE_Fixup (int, int);
126 static void OP_Mask (int, int);
129 /* Points to first byte not fetched. */
130 bfd_byte *max_fetched;
131 bfd_byte the_buffer[MAX_MNEM_SIZE];
134 OPCODES_SIGJMP_BUF bailout;
144 enum address_mode address_mode;
146 /* Flags for the prefixes for the current instruction. See below. */
149 /* REX prefix the current instruction. See below. */
151 /* Bits of REX we've already used. */
153 /* REX bits in original REX prefix ignored. */
154 static int rex_ignored;
155 /* Mark parts used in the REX prefix. When we are testing for
156 empty prefix (for 8bit register REX extension), just mask it
157 out. Otherwise test for REX bit is excuse for existence of REX
158 only in case value is nonzero. */
159 #define USED_REX(value) \
164 rex_used |= (value) | REX_OPCODE; \
167 rex_used |= REX_OPCODE; \
170 /* Flags for prefixes which we somehow handled when printing the
171 current instruction. */
172 static int used_prefixes;
174 /* Flags stored in PREFIXES. */
175 #define PREFIX_REPZ 1
176 #define PREFIX_REPNZ 2
177 #define PREFIX_LOCK 4
179 #define PREFIX_SS 0x10
180 #define PREFIX_DS 0x20
181 #define PREFIX_ES 0x40
182 #define PREFIX_FS 0x80
183 #define PREFIX_GS 0x100
184 #define PREFIX_DATA 0x200
185 #define PREFIX_ADDR 0x400
186 #define PREFIX_FWAIT 0x800
188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
189 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
191 #define FETCH_DATA(info, addr) \
192 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
193 ? 1 : fetch_data ((info), (addr)))
196 fetch_data (struct disassemble_info *info, bfd_byte *addr)
199 struct dis_private *priv = (struct dis_private *) info->private_data;
200 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
202 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
203 status = (*info->read_memory_func) (start,
205 addr - priv->max_fetched,
211 /* If we did manage to read at least one byte, then
212 print_insn_i386 will do something sensible. Otherwise, print
213 an error. We do that here because this is where we know
215 if (priv->max_fetched == priv->the_buffer)
216 (*info->memory_error_func) (status, start, info);
217 OPCODES_SIGLONGJMP (priv->bailout, 1);
220 priv->max_fetched = addr;
224 #define XX { NULL, 0 }
225 #define Bad_Opcode NULL, { { NULL, 0 } }
227 #define Eb { OP_E, b_mode }
228 #define Ebnd { OP_E, bnd_mode }
229 #define EbS { OP_E, b_swap_mode }
230 #define Ev { OP_E, v_mode }
231 #define Ev_bnd { OP_E, v_bnd_mode }
232 #define EvS { OP_E, v_swap_mode }
233 #define Ed { OP_E, d_mode }
234 #define Edq { OP_E, dq_mode }
235 #define Edqw { OP_E, dqw_mode }
236 #define EdqwS { OP_E, dqw_swap_mode }
237 #define Edqb { OP_E, dqb_mode }
238 #define Edb { OP_E, db_mode }
239 #define Edw { OP_E, dw_mode }
240 #define Edqd { OP_E, dqd_mode }
241 #define Eq { OP_E, q_mode }
242 #define indirEv { OP_indirE, stack_v_mode }
243 #define indirEp { OP_indirE, f_mode }
244 #define stackEv { OP_E, stack_v_mode }
245 #define Em { OP_E, m_mode }
246 #define Ew { OP_E, w_mode }
247 #define M { OP_M, 0 } /* lea, lgdt, etc. */
248 #define Ma { OP_M, a_mode }
249 #define Mb { OP_M, b_mode }
250 #define Md { OP_M, d_mode }
251 #define Mo { OP_M, o_mode }
252 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
253 #define Mq { OP_M, q_mode }
254 #define Mx { OP_M, x_mode }
255 #define Mxmm { OP_M, xmm_mode }
256 #define Gb { OP_G, b_mode }
257 #define Gbnd { OP_G, bnd_mode }
258 #define Gv { OP_G, v_mode }
259 #define Gd { OP_G, d_mode }
260 #define Gdq { OP_G, dq_mode }
261 #define Gm { OP_G, m_mode }
262 #define Gw { OP_G, w_mode }
263 #define Rd { OP_R, d_mode }
264 #define Rdq { OP_R, dq_mode }
265 #define Rm { OP_R, m_mode }
266 #define Ib { OP_I, b_mode }
267 #define sIb { OP_sI, b_mode } /* sign extened byte */
268 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
269 #define Iv { OP_I, v_mode }
270 #define sIv { OP_sI, v_mode }
271 #define Iq { OP_I, q_mode }
272 #define Iv64 { OP_I64, v_mode }
273 #define Iw { OP_I, w_mode }
274 #define I1 { OP_I, const_1_mode }
275 #define Jb { OP_J, b_mode }
276 #define Jv { OP_J, v_mode }
277 #define Cm { OP_C, m_mode }
278 #define Dm { OP_D, m_mode }
279 #define Td { OP_T, d_mode }
280 #define Skip_MODRM { OP_Skip_MODRM, 0 }
282 #define RMeAX { OP_REG, eAX_reg }
283 #define RMeBX { OP_REG, eBX_reg }
284 #define RMeCX { OP_REG, eCX_reg }
285 #define RMeDX { OP_REG, eDX_reg }
286 #define RMeSP { OP_REG, eSP_reg }
287 #define RMeBP { OP_REG, eBP_reg }
288 #define RMeSI { OP_REG, eSI_reg }
289 #define RMeDI { OP_REG, eDI_reg }
290 #define RMrAX { OP_REG, rAX_reg }
291 #define RMrBX { OP_REG, rBX_reg }
292 #define RMrCX { OP_REG, rCX_reg }
293 #define RMrDX { OP_REG, rDX_reg }
294 #define RMrSP { OP_REG, rSP_reg }
295 #define RMrBP { OP_REG, rBP_reg }
296 #define RMrSI { OP_REG, rSI_reg }
297 #define RMrDI { OP_REG, rDI_reg }
298 #define RMAL { OP_REG, al_reg }
299 #define RMCL { OP_REG, cl_reg }
300 #define RMDL { OP_REG, dl_reg }
301 #define RMBL { OP_REG, bl_reg }
302 #define RMAH { OP_REG, ah_reg }
303 #define RMCH { OP_REG, ch_reg }
304 #define RMDH { OP_REG, dh_reg }
305 #define RMBH { OP_REG, bh_reg }
306 #define RMAX { OP_REG, ax_reg }
307 #define RMDX { OP_REG, dx_reg }
309 #define eAX { OP_IMREG, eAX_reg }
310 #define eBX { OP_IMREG, eBX_reg }
311 #define eCX { OP_IMREG, eCX_reg }
312 #define eDX { OP_IMREG, eDX_reg }
313 #define eSP { OP_IMREG, eSP_reg }
314 #define eBP { OP_IMREG, eBP_reg }
315 #define eSI { OP_IMREG, eSI_reg }
316 #define eDI { OP_IMREG, eDI_reg }
317 #define AL { OP_IMREG, al_reg }
318 #define CL { OP_IMREG, cl_reg }
319 #define DL { OP_IMREG, dl_reg }
320 #define BL { OP_IMREG, bl_reg }
321 #define AH { OP_IMREG, ah_reg }
322 #define CH { OP_IMREG, ch_reg }
323 #define DH { OP_IMREG, dh_reg }
324 #define BH { OP_IMREG, bh_reg }
325 #define AX { OP_IMREG, ax_reg }
326 #define DX { OP_IMREG, dx_reg }
327 #define zAX { OP_IMREG, z_mode_ax_reg }
328 #define indirDX { OP_IMREG, indir_dx_reg }
330 #define Sw { OP_SEG, w_mode }
331 #define Sv { OP_SEG, v_mode }
332 #define Ap { OP_DIR, 0 }
333 #define Ob { OP_OFF64, b_mode }
334 #define Ov { OP_OFF64, v_mode }
335 #define Xb { OP_DSreg, eSI_reg }
336 #define Xv { OP_DSreg, eSI_reg }
337 #define Xz { OP_DSreg, eSI_reg }
338 #define Yb { OP_ESreg, eDI_reg }
339 #define Yv { OP_ESreg, eDI_reg }
340 #define DSBX { OP_DSreg, eBX_reg }
342 #define es { OP_REG, es_reg }
343 #define ss { OP_REG, ss_reg }
344 #define cs { OP_REG, cs_reg }
345 #define ds { OP_REG, ds_reg }
346 #define fs { OP_REG, fs_reg }
347 #define gs { OP_REG, gs_reg }
349 #define MX { OP_MMX, 0 }
350 #define XM { OP_XMM, 0 }
351 #define XMScalar { OP_XMM, scalar_mode }
352 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
353 #define XMM { OP_XMM, xmm_mode }
354 #define XMxmmq { OP_XMM, xmmq_mode }
355 #define EM { OP_EM, v_mode }
356 #define EMS { OP_EM, v_swap_mode }
357 #define EMd { OP_EM, d_mode }
358 #define EMx { OP_EM, x_mode }
359 #define EXw { OP_EX, w_mode }
360 #define EXd { OP_EX, d_mode }
361 #define EXdScalar { OP_EX, d_scalar_mode }
362 #define EXdS { OP_EX, d_swap_mode }
363 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
364 #define EXq { OP_EX, q_mode }
365 #define EXqScalar { OP_EX, q_scalar_mode }
366 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
367 #define EXqS { OP_EX, q_swap_mode }
368 #define EXx { OP_EX, x_mode }
369 #define EXxS { OP_EX, x_swap_mode }
370 #define EXxmm { OP_EX, xmm_mode }
371 #define EXymm { OP_EX, ymm_mode }
372 #define EXxmmq { OP_EX, xmmq_mode }
373 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
374 #define EXxmm_mb { OP_EX, xmm_mb_mode }
375 #define EXxmm_mw { OP_EX, xmm_mw_mode }
376 #define EXxmm_md { OP_EX, xmm_md_mode }
377 #define EXxmm_mq { OP_EX, xmm_mq_mode }
378 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
379 #define EXxmmdw { OP_EX, xmmdw_mode }
380 #define EXxmmqd { OP_EX, xmmqd_mode }
381 #define EXymmq { OP_EX, ymmq_mode }
382 #define EXVexWdq { OP_EX, vex_w_dq_mode }
383 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
384 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
385 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
386 #define MS { OP_MS, v_mode }
387 #define XS { OP_XS, v_mode }
388 #define EMCq { OP_EMC, q_mode }
389 #define MXC { OP_MXC, 0 }
390 #define OPSUF { OP_3DNowSuffix, 0 }
391 #define CMP { CMP_Fixup, 0 }
392 #define XMM0 { XMM_Fixup, 0 }
393 #define FXSAVE { FXSAVE_Fixup, 0 }
394 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
395 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
397 #define Vex { OP_VEX, vex_mode }
398 #define VexScalar { OP_VEX, vex_scalar_mode }
399 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
400 #define Vex128 { OP_VEX, vex128_mode }
401 #define Vex256 { OP_VEX, vex256_mode }
402 #define VexGdq { OP_VEX, dq_mode }
403 #define VexI4 { VEXI4_Fixup, 0}
404 #define EXdVex { OP_EX_Vex, d_mode }
405 #define EXdVexS { OP_EX_Vex, d_swap_mode }
406 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
407 #define EXqVex { OP_EX_Vex, q_mode }
408 #define EXqVexS { OP_EX_Vex, q_swap_mode }
409 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
410 #define EXVexW { OP_EX_VexW, x_mode }
411 #define EXdVexW { OP_EX_VexW, d_mode }
412 #define EXqVexW { OP_EX_VexW, q_mode }
413 #define EXVexImmW { OP_EX_VexImmW, x_mode }
414 #define XMVex { OP_XMM_Vex, 0 }
415 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
416 #define XMVexW { OP_XMM_VexW, 0 }
417 #define XMVexI4 { OP_REG_VexI4, x_mode }
418 #define PCLMUL { PCLMUL_Fixup, 0 }
419 #define VZERO { VZERO_Fixup, 0 }
420 #define VCMP { VCMP_Fixup, 0 }
421 #define VPCMP { VPCMP_Fixup, 0 }
423 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
424 #define EXxEVexS { OP_Rounding, evex_sae_mode }
426 #define XMask { OP_Mask, mask_mode }
427 #define MaskG { OP_G, mask_mode }
428 #define MaskE { OP_E, mask_mode }
429 #define MaskBDE { OP_E, mask_bd_mode }
430 #define MaskR { OP_R, mask_mode }
431 #define MaskVex { OP_VEX, mask_mode }
433 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
434 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
435 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
436 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
438 /* Used handle "rep" prefix for string instructions. */
439 #define Xbr { REP_Fixup, eSI_reg }
440 #define Xvr { REP_Fixup, eSI_reg }
441 #define Ybr { REP_Fixup, eDI_reg }
442 #define Yvr { REP_Fixup, eDI_reg }
443 #define Yzr { REP_Fixup, eDI_reg }
444 #define indirDXr { REP_Fixup, indir_dx_reg }
445 #define ALr { REP_Fixup, al_reg }
446 #define eAXr { REP_Fixup, eAX_reg }
448 /* Used handle HLE prefix for lockable instructions. */
449 #define Ebh1 { HLE_Fixup1, b_mode }
450 #define Evh1 { HLE_Fixup1, v_mode }
451 #define Ebh2 { HLE_Fixup2, b_mode }
452 #define Evh2 { HLE_Fixup2, v_mode }
453 #define Ebh3 { HLE_Fixup3, b_mode }
454 #define Evh3 { HLE_Fixup3, v_mode }
456 #define BND { BND_Fixup, 0 }
458 #define cond_jump_flag { NULL, cond_jump_mode }
459 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
461 /* bits in sizeflag */
462 #define SUFFIX_ALWAYS 4
470 /* byte operand with operand swapped */
472 /* byte operand, sign extend like 'T' suffix */
474 /* operand size depends on prefixes */
476 /* operand size depends on prefixes with operand swapped */
480 /* double word operand */
482 /* double word operand with operand swapped */
484 /* quad word operand */
486 /* quad word operand with operand swapped */
488 /* ten-byte operand */
490 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
491 broadcast enabled. */
493 /* Similar to x_mode, but with different EVEX mem shifts. */
495 /* Similar to x_mode, but with disabled broadcast. */
497 /* Similar to x_mode, but with operands swapped and disabled broadcast
500 /* 16-byte XMM operand */
502 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
503 memory operand (depending on vector length). Broadcast isn't
506 /* Same as xmmq_mode, but broadcast is allowed. */
507 evex_half_bcst_xmmq_mode,
508 /* XMM register or byte memory operand */
510 /* XMM register or word memory operand */
512 /* XMM register or double word memory operand */
514 /* XMM register or quad word memory operand */
516 /* XMM register or double/quad word memory operand, depending on
519 /* 16-byte XMM, word, double word or quad word operand. */
521 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
523 /* 32-byte YMM operand */
525 /* quad word, ymmword or zmmword memory operand. */
527 /* 32-byte YMM or 16-byte word operand */
529 /* d_mode in 32bit, q_mode in 64bit mode. */
531 /* pair of v_mode operands */
536 /* operand size depends on REX prefixes. */
538 /* registers like dq_mode, memory like w_mode. */
542 /* 4- or 6-byte pointer operand */
545 /* v_mode for stack-related opcodes. */
547 /* non-quad operand size depends on prefixes */
549 /* 16-byte operand */
551 /* registers like dq_mode, memory like b_mode. */
553 /* registers like d_mode, memory like b_mode. */
555 /* registers like d_mode, memory like w_mode. */
557 /* registers like dq_mode, memory like d_mode. */
559 /* normal vex mode */
561 /* 128bit vex mode */
563 /* 256bit vex mode */
565 /* operand size depends on the VEX.W bit. */
568 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
569 vex_vsib_d_w_dq_mode,
570 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
572 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
573 vex_vsib_q_w_dq_mode,
574 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
577 /* scalar, ignore vector length. */
579 /* like d_mode, ignore vector length. */
581 /* like d_swap_mode, ignore vector length. */
583 /* like q_mode, ignore vector length. */
585 /* like q_swap_mode, ignore vector length. */
587 /* like vex_mode, ignore vector length. */
589 /* like vex_w_dq_mode, ignore vector length. */
590 vex_scalar_w_dq_mode,
592 /* Static rounding. */
594 /* Supress all exceptions. */
597 /* Mask register operand. */
599 /* Mask register operand. */
666 #define FLOAT NULL, { { NULL, FLOATCODE } }
668 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
669 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
670 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
671 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
672 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
673 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
674 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
675 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
676 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
677 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
678 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
679 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
680 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
796 MOD_VEX_0F12_PREFIX_0,
798 MOD_VEX_0F16_PREFIX_0,
814 MOD_VEX_0FD7_PREFIX_2,
815 MOD_VEX_0FE7_PREFIX_2,
816 MOD_VEX_0FF0_PREFIX_3,
817 MOD_VEX_0F381A_PREFIX_2,
818 MOD_VEX_0F382A_PREFIX_2,
819 MOD_VEX_0F382C_PREFIX_2,
820 MOD_VEX_0F382D_PREFIX_2,
821 MOD_VEX_0F382E_PREFIX_2,
822 MOD_VEX_0F382F_PREFIX_2,
823 MOD_VEX_0F385A_PREFIX_2,
824 MOD_VEX_0F388C_PREFIX_2,
825 MOD_VEX_0F388E_PREFIX_2,
827 MOD_EVEX_0F10_PREFIX_1,
828 MOD_EVEX_0F10_PREFIX_3,
829 MOD_EVEX_0F11_PREFIX_1,
830 MOD_EVEX_0F11_PREFIX_3,
831 MOD_EVEX_0F12_PREFIX_0,
832 MOD_EVEX_0F16_PREFIX_0,
833 MOD_EVEX_0F38C6_REG_1,
834 MOD_EVEX_0F38C6_REG_2,
835 MOD_EVEX_0F38C6_REG_5,
836 MOD_EVEX_0F38C6_REG_6,
837 MOD_EVEX_0F38C7_REG_1,
838 MOD_EVEX_0F38C7_REG_2,
839 MOD_EVEX_0F38C7_REG_5,
840 MOD_EVEX_0F38C7_REG_6
1032 PREFIX_VEX_0F71_REG_2,
1033 PREFIX_VEX_0F71_REG_4,
1034 PREFIX_VEX_0F71_REG_6,
1035 PREFIX_VEX_0F72_REG_2,
1036 PREFIX_VEX_0F72_REG_4,
1037 PREFIX_VEX_0F72_REG_6,
1038 PREFIX_VEX_0F73_REG_2,
1039 PREFIX_VEX_0F73_REG_3,
1040 PREFIX_VEX_0F73_REG_6,
1041 PREFIX_VEX_0F73_REG_7,
1213 PREFIX_VEX_0F38F3_REG_1,
1214 PREFIX_VEX_0F38F3_REG_2,
1215 PREFIX_VEX_0F38F3_REG_3,
1332 PREFIX_EVEX_0F71_REG_2,
1333 PREFIX_EVEX_0F71_REG_4,
1334 PREFIX_EVEX_0F71_REG_6,
1335 PREFIX_EVEX_0F72_REG_0,
1336 PREFIX_EVEX_0F72_REG_1,
1337 PREFIX_EVEX_0F72_REG_2,
1338 PREFIX_EVEX_0F72_REG_4,
1339 PREFIX_EVEX_0F72_REG_6,
1340 PREFIX_EVEX_0F73_REG_2,
1341 PREFIX_EVEX_0F73_REG_3,
1342 PREFIX_EVEX_0F73_REG_6,
1343 PREFIX_EVEX_0F73_REG_7,
1523 PREFIX_EVEX_0F38C6_REG_1,
1524 PREFIX_EVEX_0F38C6_REG_2,
1525 PREFIX_EVEX_0F38C6_REG_5,
1526 PREFIX_EVEX_0F38C6_REG_6,
1527 PREFIX_EVEX_0F38C7_REG_1,
1528 PREFIX_EVEX_0F38C7_REG_2,
1529 PREFIX_EVEX_0F38C7_REG_5,
1530 PREFIX_EVEX_0F38C7_REG_6,
1617 THREE_BYTE_0F38 = 0,
1645 VEX_LEN_0F10_P_1 = 0,
1649 VEX_LEN_0F12_P_0_M_0,
1650 VEX_LEN_0F12_P_0_M_1,
1653 VEX_LEN_0F16_P_0_M_0,
1654 VEX_LEN_0F16_P_0_M_1,
1718 VEX_LEN_0FAE_R_2_M_0,
1719 VEX_LEN_0FAE_R_3_M_0,
1728 VEX_LEN_0F381A_P_2_M_0,
1731 VEX_LEN_0F385A_P_2_M_0,
1738 VEX_LEN_0F38F3_R_1_P_0,
1739 VEX_LEN_0F38F3_R_2_P_0,
1740 VEX_LEN_0F38F3_R_3_P_0,
1786 VEX_LEN_0FXOP_08_CC,
1787 VEX_LEN_0FXOP_08_CD,
1788 VEX_LEN_0FXOP_08_CE,
1789 VEX_LEN_0FXOP_08_CF,
1790 VEX_LEN_0FXOP_08_EC,
1791 VEX_LEN_0FXOP_08_ED,
1792 VEX_LEN_0FXOP_08_EE,
1793 VEX_LEN_0FXOP_08_EF,
1794 VEX_LEN_0FXOP_09_80,
1828 VEX_W_0F41_P_0_LEN_1,
1829 VEX_W_0F41_P_2_LEN_1,
1830 VEX_W_0F42_P_0_LEN_1,
1831 VEX_W_0F42_P_2_LEN_1,
1832 VEX_W_0F44_P_0_LEN_0,
1833 VEX_W_0F44_P_2_LEN_0,
1834 VEX_W_0F45_P_0_LEN_1,
1835 VEX_W_0F45_P_2_LEN_1,
1836 VEX_W_0F46_P_0_LEN_1,
1837 VEX_W_0F46_P_2_LEN_1,
1838 VEX_W_0F47_P_0_LEN_1,
1839 VEX_W_0F47_P_2_LEN_1,
1840 VEX_W_0F4A_P_0_LEN_1,
1841 VEX_W_0F4A_P_2_LEN_1,
1842 VEX_W_0F4B_P_0_LEN_1,
1843 VEX_W_0F4B_P_2_LEN_1,
1923 VEX_W_0F90_P_0_LEN_0,
1924 VEX_W_0F90_P_2_LEN_0,
1925 VEX_W_0F91_P_0_LEN_0,
1926 VEX_W_0F91_P_2_LEN_0,
1927 VEX_W_0F92_P_0_LEN_0,
1928 VEX_W_0F92_P_2_LEN_0,
1929 VEX_W_0F92_P_3_LEN_0,
1930 VEX_W_0F93_P_0_LEN_0,
1931 VEX_W_0F93_P_2_LEN_0,
1932 VEX_W_0F93_P_3_LEN_0,
1933 VEX_W_0F98_P_0_LEN_0,
1934 VEX_W_0F98_P_2_LEN_0,
1935 VEX_W_0F99_P_0_LEN_0,
1936 VEX_W_0F99_P_2_LEN_0,
2015 VEX_W_0F381A_P_2_M_0,
2027 VEX_W_0F382A_P_2_M_0,
2029 VEX_W_0F382C_P_2_M_0,
2030 VEX_W_0F382D_P_2_M_0,
2031 VEX_W_0F382E_P_2_M_0,
2032 VEX_W_0F382F_P_2_M_0,
2054 VEX_W_0F385A_P_2_M_0,
2082 VEX_W_0F3A30_P_2_LEN_0,
2083 VEX_W_0F3A31_P_2_LEN_0,
2084 VEX_W_0F3A32_P_2_LEN_0,
2085 VEX_W_0F3A33_P_2_LEN_0,
2105 EVEX_W_0F10_P_1_M_0,
2106 EVEX_W_0F10_P_1_M_1,
2108 EVEX_W_0F10_P_3_M_0,
2109 EVEX_W_0F10_P_3_M_1,
2111 EVEX_W_0F11_P_1_M_0,
2112 EVEX_W_0F11_P_1_M_1,
2114 EVEX_W_0F11_P_3_M_0,
2115 EVEX_W_0F11_P_3_M_1,
2116 EVEX_W_0F12_P_0_M_0,
2117 EVEX_W_0F12_P_0_M_1,
2127 EVEX_W_0F16_P_0_M_0,
2128 EVEX_W_0F16_P_0_M_1,
2199 EVEX_W_0F72_R_2_P_2,
2200 EVEX_W_0F72_R_6_P_2,
2201 EVEX_W_0F73_R_2_P_2,
2202 EVEX_W_0F73_R_6_P_2,
2301 EVEX_W_0F38C7_R_1_P_2,
2302 EVEX_W_0F38C7_R_2_P_2,
2303 EVEX_W_0F38C7_R_5_P_2,
2304 EVEX_W_0F38C7_R_6_P_2,
2339 typedef void (*op_rtn) (int bytemode, int sizeflag);
2350 /* Upper case letters in the instruction names here are macros.
2351 'A' => print 'b' if no register operands or suffix_always is true
2352 'B' => print 'b' if suffix_always is true
2353 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2355 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2356 suffix_always is true
2357 'E' => print 'e' if 32-bit form of jcxz
2358 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2359 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2360 'H' => print ",pt" or ",pn" branch hint
2361 'I' => honor following macro letter even in Intel mode (implemented only
2362 for some of the macro letters)
2364 'K' => print 'd' or 'q' if rex prefix is present.
2365 'L' => print 'l' if suffix_always is true
2366 'M' => print 'r' if intel_mnemonic is false.
2367 'N' => print 'n' if instruction has no wait "prefix"
2368 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2369 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2370 or suffix_always is true. print 'q' if rex prefix is present.
2371 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2373 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2374 'S' => print 'w', 'l' or 'q' if suffix_always is true
2375 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2376 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2377 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2378 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2379 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2380 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2381 suffix_always is true.
2382 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2383 '!' => change condition from true to false or from false to true.
2384 '%' => add 1 upper case letter to the macro.
2386 2 upper case letter macros:
2387 "XY" => print 'x' or 'y' if no register operands or suffix_always
2389 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2390 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2391 or suffix_always is true
2392 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2393 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2394 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2395 "LW" => print 'd', 'q' depending on the VEX.W bit
2396 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2397 an operand size prefix, or suffix_always is true. print
2398 'q' if rex prefix is present.
2400 Many of the above letters print nothing in Intel mode. See "putop"
2403 Braces '{' and '}', and vertical bars '|', indicate alternative
2404 mnemonic strings for AT&T and Intel. */
2406 static const struct dis386 dis386[] = {
2408 { "addB", { Ebh1, Gb } },
2409 { "addS", { Evh1, Gv } },
2410 { "addB", { Gb, EbS } },
2411 { "addS", { Gv, EvS } },
2412 { "addB", { AL, Ib } },
2413 { "addS", { eAX, Iv } },
2414 { X86_64_TABLE (X86_64_06) },
2415 { X86_64_TABLE (X86_64_07) },
2417 { "orB", { Ebh1, Gb } },
2418 { "orS", { Evh1, Gv } },
2419 { "orB", { Gb, EbS } },
2420 { "orS", { Gv, EvS } },
2421 { "orB", { AL, Ib } },
2422 { "orS", { eAX, Iv } },
2423 { X86_64_TABLE (X86_64_0D) },
2424 { Bad_Opcode }, /* 0x0f extended opcode escape */
2426 { "adcB", { Ebh1, Gb } },
2427 { "adcS", { Evh1, Gv } },
2428 { "adcB", { Gb, EbS } },
2429 { "adcS", { Gv, EvS } },
2430 { "adcB", { AL, Ib } },
2431 { "adcS", { eAX, Iv } },
2432 { X86_64_TABLE (X86_64_16) },
2433 { X86_64_TABLE (X86_64_17) },
2435 { "sbbB", { Ebh1, Gb } },
2436 { "sbbS", { Evh1, Gv } },
2437 { "sbbB", { Gb, EbS } },
2438 { "sbbS", { Gv, EvS } },
2439 { "sbbB", { AL, Ib } },
2440 { "sbbS", { eAX, Iv } },
2441 { X86_64_TABLE (X86_64_1E) },
2442 { X86_64_TABLE (X86_64_1F) },
2444 { "andB", { Ebh1, Gb } },
2445 { "andS", { Evh1, Gv } },
2446 { "andB", { Gb, EbS } },
2447 { "andS", { Gv, EvS } },
2448 { "andB", { AL, Ib } },
2449 { "andS", { eAX, Iv } },
2450 { Bad_Opcode }, /* SEG ES prefix */
2451 { X86_64_TABLE (X86_64_27) },
2453 { "subB", { Ebh1, Gb } },
2454 { "subS", { Evh1, Gv } },
2455 { "subB", { Gb, EbS } },
2456 { "subS", { Gv, EvS } },
2457 { "subB", { AL, Ib } },
2458 { "subS", { eAX, Iv } },
2459 { Bad_Opcode }, /* SEG CS prefix */
2460 { X86_64_TABLE (X86_64_2F) },
2462 { "xorB", { Ebh1, Gb } },
2463 { "xorS", { Evh1, Gv } },
2464 { "xorB", { Gb, EbS } },
2465 { "xorS", { Gv, EvS } },
2466 { "xorB", { AL, Ib } },
2467 { "xorS", { eAX, Iv } },
2468 { Bad_Opcode }, /* SEG SS prefix */
2469 { X86_64_TABLE (X86_64_37) },
2471 { "cmpB", { Eb, Gb } },
2472 { "cmpS", { Ev, Gv } },
2473 { "cmpB", { Gb, EbS } },
2474 { "cmpS", { Gv, EvS } },
2475 { "cmpB", { AL, Ib } },
2476 { "cmpS", { eAX, Iv } },
2477 { Bad_Opcode }, /* SEG DS prefix */
2478 { X86_64_TABLE (X86_64_3F) },
2480 { "inc{S|}", { RMeAX } },
2481 { "inc{S|}", { RMeCX } },
2482 { "inc{S|}", { RMeDX } },
2483 { "inc{S|}", { RMeBX } },
2484 { "inc{S|}", { RMeSP } },
2485 { "inc{S|}", { RMeBP } },
2486 { "inc{S|}", { RMeSI } },
2487 { "inc{S|}", { RMeDI } },
2489 { "dec{S|}", { RMeAX } },
2490 { "dec{S|}", { RMeCX } },
2491 { "dec{S|}", { RMeDX } },
2492 { "dec{S|}", { RMeBX } },
2493 { "dec{S|}", { RMeSP } },
2494 { "dec{S|}", { RMeBP } },
2495 { "dec{S|}", { RMeSI } },
2496 { "dec{S|}", { RMeDI } },
2498 { "pushV", { RMrAX } },
2499 { "pushV", { RMrCX } },
2500 { "pushV", { RMrDX } },
2501 { "pushV", { RMrBX } },
2502 { "pushV", { RMrSP } },
2503 { "pushV", { RMrBP } },
2504 { "pushV", { RMrSI } },
2505 { "pushV", { RMrDI } },
2507 { "popV", { RMrAX } },
2508 { "popV", { RMrCX } },
2509 { "popV", { RMrDX } },
2510 { "popV", { RMrBX } },
2511 { "popV", { RMrSP } },
2512 { "popV", { RMrBP } },
2513 { "popV", { RMrSI } },
2514 { "popV", { RMrDI } },
2516 { X86_64_TABLE (X86_64_60) },
2517 { X86_64_TABLE (X86_64_61) },
2518 { X86_64_TABLE (X86_64_62) },
2519 { X86_64_TABLE (X86_64_63) },
2520 { Bad_Opcode }, /* seg fs */
2521 { Bad_Opcode }, /* seg gs */
2522 { Bad_Opcode }, /* op size prefix */
2523 { Bad_Opcode }, /* adr size prefix */
2525 { "pushT", { sIv } },
2526 { "imulS", { Gv, Ev, Iv } },
2527 { "pushT", { sIbT } },
2528 { "imulS", { Gv, Ev, sIb } },
2529 { "ins{b|}", { Ybr, indirDX } },
2530 { X86_64_TABLE (X86_64_6D) },
2531 { "outs{b|}", { indirDXr, Xb } },
2532 { X86_64_TABLE (X86_64_6F) },
2534 { "joH", { Jb, BND, cond_jump_flag } },
2535 { "jnoH", { Jb, BND, cond_jump_flag } },
2536 { "jbH", { Jb, BND, cond_jump_flag } },
2537 { "jaeH", { Jb, BND, cond_jump_flag } },
2538 { "jeH", { Jb, BND, cond_jump_flag } },
2539 { "jneH", { Jb, BND, cond_jump_flag } },
2540 { "jbeH", { Jb, BND, cond_jump_flag } },
2541 { "jaH", { Jb, BND, cond_jump_flag } },
2543 { "jsH", { Jb, BND, cond_jump_flag } },
2544 { "jnsH", { Jb, BND, cond_jump_flag } },
2545 { "jpH", { Jb, BND, cond_jump_flag } },
2546 { "jnpH", { Jb, BND, cond_jump_flag } },
2547 { "jlH", { Jb, BND, cond_jump_flag } },
2548 { "jgeH", { Jb, BND, cond_jump_flag } },
2549 { "jleH", { Jb, BND, cond_jump_flag } },
2550 { "jgH", { Jb, BND, cond_jump_flag } },
2552 { REG_TABLE (REG_80) },
2553 { REG_TABLE (REG_81) },
2555 { REG_TABLE (REG_82) },
2556 { "testB", { Eb, Gb } },
2557 { "testS", { Ev, Gv } },
2558 { "xchgB", { Ebh2, Gb } },
2559 { "xchgS", { Evh2, Gv } },
2561 { "movB", { Ebh3, Gb } },
2562 { "movS", { Evh3, Gv } },
2563 { "movB", { Gb, EbS } },
2564 { "movS", { Gv, EvS } },
2565 { "movD", { Sv, Sw } },
2566 { MOD_TABLE (MOD_8D) },
2567 { "movD", { Sw, Sv } },
2568 { REG_TABLE (REG_8F) },
2570 { PREFIX_TABLE (PREFIX_90) },
2571 { "xchgS", { RMeCX, eAX } },
2572 { "xchgS", { RMeDX, eAX } },
2573 { "xchgS", { RMeBX, eAX } },
2574 { "xchgS", { RMeSP, eAX } },
2575 { "xchgS", { RMeBP, eAX } },
2576 { "xchgS", { RMeSI, eAX } },
2577 { "xchgS", { RMeDI, eAX } },
2579 { "cW{t|}R", { XX } },
2580 { "cR{t|}O", { XX } },
2581 { X86_64_TABLE (X86_64_9A) },
2582 { Bad_Opcode }, /* fwait */
2583 { "pushfT", { XX } },
2584 { "popfT", { XX } },
2588 { "mov%LB", { AL, Ob } },
2589 { "mov%LS", { eAX, Ov } },
2590 { "mov%LB", { Ob, AL } },
2591 { "mov%LS", { Ov, eAX } },
2592 { "movs{b|}", { Ybr, Xb } },
2593 { "movs{R|}", { Yvr, Xv } },
2594 { "cmps{b|}", { Xb, Yb } },
2595 { "cmps{R|}", { Xv, Yv } },
2597 { "testB", { AL, Ib } },
2598 { "testS", { eAX, Iv } },
2599 { "stosB", { Ybr, AL } },
2600 { "stosS", { Yvr, eAX } },
2601 { "lodsB", { ALr, Xb } },
2602 { "lodsS", { eAXr, Xv } },
2603 { "scasB", { AL, Yb } },
2604 { "scasS", { eAX, Yv } },
2606 { "movB", { RMAL, Ib } },
2607 { "movB", { RMCL, Ib } },
2608 { "movB", { RMDL, Ib } },
2609 { "movB", { RMBL, Ib } },
2610 { "movB", { RMAH, Ib } },
2611 { "movB", { RMCH, Ib } },
2612 { "movB", { RMDH, Ib } },
2613 { "movB", { RMBH, Ib } },
2615 { "mov%LV", { RMeAX, Iv64 } },
2616 { "mov%LV", { RMeCX, Iv64 } },
2617 { "mov%LV", { RMeDX, Iv64 } },
2618 { "mov%LV", { RMeBX, Iv64 } },
2619 { "mov%LV", { RMeSP, Iv64 } },
2620 { "mov%LV", { RMeBP, Iv64 } },
2621 { "mov%LV", { RMeSI, Iv64 } },
2622 { "mov%LV", { RMeDI, Iv64 } },
2624 { REG_TABLE (REG_C0) },
2625 { REG_TABLE (REG_C1) },
2626 { "retT", { Iw, BND } },
2627 { "retT", { BND } },
2628 { X86_64_TABLE (X86_64_C4) },
2629 { X86_64_TABLE (X86_64_C5) },
2630 { REG_TABLE (REG_C6) },
2631 { REG_TABLE (REG_C7) },
2633 { "enterT", { Iw, Ib } },
2634 { "leaveT", { XX } },
2635 { "Jret{|f}P", { Iw } },
2636 { "Jret{|f}P", { XX } },
2639 { X86_64_TABLE (X86_64_CE) },
2640 { "iret%LP", { XX } },
2642 { REG_TABLE (REG_D0) },
2643 { REG_TABLE (REG_D1) },
2644 { REG_TABLE (REG_D2) },
2645 { REG_TABLE (REG_D3) },
2646 { X86_64_TABLE (X86_64_D4) },
2647 { X86_64_TABLE (X86_64_D5) },
2649 { "xlat", { DSBX } },
2660 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
2661 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
2662 { "loopFH", { Jb, XX, loop_jcxz_flag } },
2663 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
2664 { "inB", { AL, Ib } },
2665 { "inG", { zAX, Ib } },
2666 { "outB", { Ib, AL } },
2667 { "outG", { Ib, zAX } },
2669 { "callT", { Jv, BND } },
2670 { "jmpT", { Jv, BND } },
2671 { X86_64_TABLE (X86_64_EA) },
2672 { "jmp", { Jb, BND } },
2673 { "inB", { AL, indirDX } },
2674 { "inG", { zAX, indirDX } },
2675 { "outB", { indirDX, AL } },
2676 { "outG", { indirDX, zAX } },
2678 { Bad_Opcode }, /* lock prefix */
2679 { "icebp", { XX } },
2680 { Bad_Opcode }, /* repne */
2681 { Bad_Opcode }, /* repz */
2684 { REG_TABLE (REG_F6) },
2685 { REG_TABLE (REG_F7) },
2693 { REG_TABLE (REG_FE) },
2694 { REG_TABLE (REG_FF) },
2697 static const struct dis386 dis386_twobyte[] = {
2699 { REG_TABLE (REG_0F00 ) },
2700 { REG_TABLE (REG_0F01 ) },
2701 { "larS", { Gv, Ew } },
2702 { "lslS", { Gv, Ew } },
2704 { "syscall", { XX } },
2706 { "sysret%LP", { XX } },
2709 { "wbinvd", { XX } },
2713 { REG_TABLE (REG_0F0D) },
2714 { "femms", { XX } },
2715 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
2717 { PREFIX_TABLE (PREFIX_0F10) },
2718 { PREFIX_TABLE (PREFIX_0F11) },
2719 { PREFIX_TABLE (PREFIX_0F12) },
2720 { MOD_TABLE (MOD_0F13) },
2721 { "unpcklpX", { XM, EXx } },
2722 { "unpckhpX", { XM, EXx } },
2723 { PREFIX_TABLE (PREFIX_0F16) },
2724 { MOD_TABLE (MOD_0F17) },
2726 { REG_TABLE (REG_0F18) },
2728 { PREFIX_TABLE (PREFIX_0F1A) },
2729 { PREFIX_TABLE (PREFIX_0F1B) },
2735 { "movZ", { Rm, Cm } },
2736 { "movZ", { Rm, Dm } },
2737 { "movZ", { Cm, Rm } },
2738 { "movZ", { Dm, Rm } },
2739 { MOD_TABLE (MOD_0F24) },
2741 { MOD_TABLE (MOD_0F26) },
2744 { "movapX", { XM, EXx } },
2745 { "movapX", { EXxS, XM } },
2746 { PREFIX_TABLE (PREFIX_0F2A) },
2747 { PREFIX_TABLE (PREFIX_0F2B) },
2748 { PREFIX_TABLE (PREFIX_0F2C) },
2749 { PREFIX_TABLE (PREFIX_0F2D) },
2750 { PREFIX_TABLE (PREFIX_0F2E) },
2751 { PREFIX_TABLE (PREFIX_0F2F) },
2753 { "wrmsr", { XX } },
2754 { "rdtsc", { XX } },
2755 { "rdmsr", { XX } },
2756 { "rdpmc", { XX } },
2757 { "sysenter", { XX } },
2758 { "sysexit", { XX } },
2760 { "getsec", { XX } },
2762 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2764 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2771 { "cmovoS", { Gv, Ev } },
2772 { "cmovnoS", { Gv, Ev } },
2773 { "cmovbS", { Gv, Ev } },
2774 { "cmovaeS", { Gv, Ev } },
2775 { "cmoveS", { Gv, Ev } },
2776 { "cmovneS", { Gv, Ev } },
2777 { "cmovbeS", { Gv, Ev } },
2778 { "cmovaS", { Gv, Ev } },
2780 { "cmovsS", { Gv, Ev } },
2781 { "cmovnsS", { Gv, Ev } },
2782 { "cmovpS", { Gv, Ev } },
2783 { "cmovnpS", { Gv, Ev } },
2784 { "cmovlS", { Gv, Ev } },
2785 { "cmovgeS", { Gv, Ev } },
2786 { "cmovleS", { Gv, Ev } },
2787 { "cmovgS", { Gv, Ev } },
2789 { MOD_TABLE (MOD_0F51) },
2790 { PREFIX_TABLE (PREFIX_0F51) },
2791 { PREFIX_TABLE (PREFIX_0F52) },
2792 { PREFIX_TABLE (PREFIX_0F53) },
2793 { "andpX", { XM, EXx } },
2794 { "andnpX", { XM, EXx } },
2795 { "orpX", { XM, EXx } },
2796 { "xorpX", { XM, EXx } },
2798 { PREFIX_TABLE (PREFIX_0F58) },
2799 { PREFIX_TABLE (PREFIX_0F59) },
2800 { PREFIX_TABLE (PREFIX_0F5A) },
2801 { PREFIX_TABLE (PREFIX_0F5B) },
2802 { PREFIX_TABLE (PREFIX_0F5C) },
2803 { PREFIX_TABLE (PREFIX_0F5D) },
2804 { PREFIX_TABLE (PREFIX_0F5E) },
2805 { PREFIX_TABLE (PREFIX_0F5F) },
2807 { PREFIX_TABLE (PREFIX_0F60) },
2808 { PREFIX_TABLE (PREFIX_0F61) },
2809 { PREFIX_TABLE (PREFIX_0F62) },
2810 { "packsswb", { MX, EM } },
2811 { "pcmpgtb", { MX, EM } },
2812 { "pcmpgtw", { MX, EM } },
2813 { "pcmpgtd", { MX, EM } },
2814 { "packuswb", { MX, EM } },
2816 { "punpckhbw", { MX, EM } },
2817 { "punpckhwd", { MX, EM } },
2818 { "punpckhdq", { MX, EM } },
2819 { "packssdw", { MX, EM } },
2820 { PREFIX_TABLE (PREFIX_0F6C) },
2821 { PREFIX_TABLE (PREFIX_0F6D) },
2822 { "movK", { MX, Edq } },
2823 { PREFIX_TABLE (PREFIX_0F6F) },
2825 { PREFIX_TABLE (PREFIX_0F70) },
2826 { REG_TABLE (REG_0F71) },
2827 { REG_TABLE (REG_0F72) },
2828 { REG_TABLE (REG_0F73) },
2829 { "pcmpeqb", { MX, EM } },
2830 { "pcmpeqw", { MX, EM } },
2831 { "pcmpeqd", { MX, EM } },
2834 { PREFIX_TABLE (PREFIX_0F78) },
2835 { PREFIX_TABLE (PREFIX_0F79) },
2836 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2838 { PREFIX_TABLE (PREFIX_0F7C) },
2839 { PREFIX_TABLE (PREFIX_0F7D) },
2840 { PREFIX_TABLE (PREFIX_0F7E) },
2841 { PREFIX_TABLE (PREFIX_0F7F) },
2843 { "joH", { Jv, BND, cond_jump_flag } },
2844 { "jnoH", { Jv, BND, cond_jump_flag } },
2845 { "jbH", { Jv, BND, cond_jump_flag } },
2846 { "jaeH", { Jv, BND, cond_jump_flag } },
2847 { "jeH", { Jv, BND, cond_jump_flag } },
2848 { "jneH", { Jv, BND, cond_jump_flag } },
2849 { "jbeH", { Jv, BND, cond_jump_flag } },
2850 { "jaH", { Jv, BND, cond_jump_flag } },
2852 { "jsH", { Jv, BND, cond_jump_flag } },
2853 { "jnsH", { Jv, BND, cond_jump_flag } },
2854 { "jpH", { Jv, BND, cond_jump_flag } },
2855 { "jnpH", { Jv, BND, cond_jump_flag } },
2856 { "jlH", { Jv, BND, cond_jump_flag } },
2857 { "jgeH", { Jv, BND, cond_jump_flag } },
2858 { "jleH", { Jv, BND, cond_jump_flag } },
2859 { "jgH", { Jv, BND, cond_jump_flag } },
2862 { "setno", { Eb } },
2864 { "setae", { Eb } },
2866 { "setne", { Eb } },
2867 { "setbe", { Eb } },
2871 { "setns", { Eb } },
2873 { "setnp", { Eb } },
2875 { "setge", { Eb } },
2876 { "setle", { Eb } },
2879 { "pushT", { fs } },
2881 { "cpuid", { XX } },
2882 { "btS", { Ev, Gv } },
2883 { "shldS", { Ev, Gv, Ib } },
2884 { "shldS", { Ev, Gv, CL } },
2885 { REG_TABLE (REG_0FA6) },
2886 { REG_TABLE (REG_0FA7) },
2888 { "pushT", { gs } },
2891 { "btsS", { Evh1, Gv } },
2892 { "shrdS", { Ev, Gv, Ib } },
2893 { "shrdS", { Ev, Gv, CL } },
2894 { REG_TABLE (REG_0FAE) },
2895 { "imulS", { Gv, Ev } },
2897 { "cmpxchgB", { Ebh1, Gb } },
2898 { "cmpxchgS", { Evh1, Gv } },
2899 { MOD_TABLE (MOD_0FB2) },
2900 { "btrS", { Evh1, Gv } },
2901 { MOD_TABLE (MOD_0FB4) },
2902 { MOD_TABLE (MOD_0FB5) },
2903 { "movz{bR|x}", { Gv, Eb } },
2904 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
2906 { PREFIX_TABLE (PREFIX_0FB8) },
2908 { REG_TABLE (REG_0FBA) },
2909 { "btcS", { Evh1, Gv } },
2910 { PREFIX_TABLE (PREFIX_0FBC) },
2911 { PREFIX_TABLE (PREFIX_0FBD) },
2912 { "movs{bR|x}", { Gv, Eb } },
2913 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
2915 { "xaddB", { Ebh1, Gb } },
2916 { "xaddS", { Evh1, Gv } },
2917 { PREFIX_TABLE (PREFIX_0FC2) },
2918 { PREFIX_TABLE (PREFIX_0FC3) },
2919 { "pinsrw", { MX, Edqw, Ib } },
2920 { "pextrw", { Gdq, MS, Ib } },
2921 { "shufpX", { XM, EXx, Ib } },
2922 { REG_TABLE (REG_0FC7) },
2924 { "bswap", { RMeAX } },
2925 { "bswap", { RMeCX } },
2926 { "bswap", { RMeDX } },
2927 { "bswap", { RMeBX } },
2928 { "bswap", { RMeSP } },
2929 { "bswap", { RMeBP } },
2930 { "bswap", { RMeSI } },
2931 { "bswap", { RMeDI } },
2933 { PREFIX_TABLE (PREFIX_0FD0) },
2934 { "psrlw", { MX, EM } },
2935 { "psrld", { MX, EM } },
2936 { "psrlq", { MX, EM } },
2937 { "paddq", { MX, EM } },
2938 { "pmullw", { MX, EM } },
2939 { PREFIX_TABLE (PREFIX_0FD6) },
2940 { MOD_TABLE (MOD_0FD7) },
2942 { "psubusb", { MX, EM } },
2943 { "psubusw", { MX, EM } },
2944 { "pminub", { MX, EM } },
2945 { "pand", { MX, EM } },
2946 { "paddusb", { MX, EM } },
2947 { "paddusw", { MX, EM } },
2948 { "pmaxub", { MX, EM } },
2949 { "pandn", { MX, EM } },
2951 { "pavgb", { MX, EM } },
2952 { "psraw", { MX, EM } },
2953 { "psrad", { MX, EM } },
2954 { "pavgw", { MX, EM } },
2955 { "pmulhuw", { MX, EM } },
2956 { "pmulhw", { MX, EM } },
2957 { PREFIX_TABLE (PREFIX_0FE6) },
2958 { PREFIX_TABLE (PREFIX_0FE7) },
2960 { "psubsb", { MX, EM } },
2961 { "psubsw", { MX, EM } },
2962 { "pminsw", { MX, EM } },
2963 { "por", { MX, EM } },
2964 { "paddsb", { MX, EM } },
2965 { "paddsw", { MX, EM } },
2966 { "pmaxsw", { MX, EM } },
2967 { "pxor", { MX, EM } },
2969 { PREFIX_TABLE (PREFIX_0FF0) },
2970 { "psllw", { MX, EM } },
2971 { "pslld", { MX, EM } },
2972 { "psllq", { MX, EM } },
2973 { "pmuludq", { MX, EM } },
2974 { "pmaddwd", { MX, EM } },
2975 { "psadbw", { MX, EM } },
2976 { PREFIX_TABLE (PREFIX_0FF7) },
2978 { "psubb", { MX, EM } },
2979 { "psubw", { MX, EM } },
2980 { "psubd", { MX, EM } },
2981 { "psubq", { MX, EM } },
2982 { "paddb", { MX, EM } },
2983 { "paddw", { MX, EM } },
2984 { "paddd", { MX, EM } },
2988 static const unsigned char onebyte_has_modrm[256] = {
2989 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2990 /* ------------------------------- */
2991 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2992 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2993 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2994 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2995 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2996 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2997 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2998 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2999 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3000 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3001 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3002 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3003 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3004 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3005 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3006 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3007 /* ------------------------------- */
3008 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3011 static const unsigned char twobyte_has_modrm[256] = {
3012 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3013 /* ------------------------------- */
3014 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3015 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3016 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3017 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3018 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3019 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3020 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3021 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3022 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3023 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3024 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3025 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3026 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3027 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3028 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3029 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3030 /* ------------------------------- */
3031 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3034 static const unsigned char twobyte_has_mandatory_prefix[256] = {
3035 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3036 /* ------------------------------- */
3037 /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
3038 /* 10 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 1f */
3039 /* 20 */ 0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0, /* 2f */
3040 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3041 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
3042 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3043 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3044 /* 70 */ 1,0,0,0,1,1,1,1,0,0,1,1,1,1,1,1, /* 7f */
3045 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3046 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
3047 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
3048 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
3049 /* c0 */ 0,0,1,1,1,1,1,0,0,0,0,0,0,0,0,0, /* cf */
3050 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3051 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3052 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3053 /* ------------------------------- */
3054 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3057 static char obuf[100];
3059 static char *mnemonicendp;
3060 static char scratchbuf[100];
3061 static unsigned char *start_codep;
3062 static unsigned char *insn_codep;
3063 static unsigned char *codep;
3064 static unsigned char *end_codep;
3065 static int last_lock_prefix;
3066 static int last_repz_prefix;
3067 static int last_repnz_prefix;
3068 static int last_data_prefix;
3069 static int last_addr_prefix;
3070 static int last_rex_prefix;
3071 static int last_seg_prefix;
3072 static int fwait_prefix;
3073 /* The PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is mandatory. */
3074 static int mandatory_prefix;
3075 /* The active segment register prefix. */
3076 static int active_seg_prefix;
3077 #define MAX_CODE_LENGTH 15
3078 /* We can up to 14 prefixes since the maximum instruction length is
3080 static int all_prefixes[MAX_CODE_LENGTH - 1];
3081 static disassemble_info *the_info;
3089 static unsigned char need_modrm;
3099 int register_specifier;
3106 int mask_register_specifier;
3112 static unsigned char need_vex;
3113 static unsigned char need_vex_reg;
3114 static unsigned char vex_w_done;
3122 /* If we are accessing mod/rm/reg without need_modrm set, then the
3123 values are stale. Hitting this abort likely indicates that you
3124 need to update onebyte_has_modrm or twobyte_has_modrm. */
3125 #define MODRM_CHECK if (!need_modrm) abort ()
3127 static const char **names64;
3128 static const char **names32;
3129 static const char **names16;
3130 static const char **names8;
3131 static const char **names8rex;
3132 static const char **names_seg;
3133 static const char *index64;
3134 static const char *index32;
3135 static const char **index16;
3136 static const char **names_bnd;
3138 static const char *intel_names64[] = {
3139 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3140 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3142 static const char *intel_names32[] = {
3143 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3144 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3146 static const char *intel_names16[] = {
3147 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3148 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3150 static const char *intel_names8[] = {
3151 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3153 static const char *intel_names8rex[] = {
3154 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3155 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3157 static const char *intel_names_seg[] = {
3158 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3160 static const char *intel_index64 = "riz";
3161 static const char *intel_index32 = "eiz";
3162 static const char *intel_index16[] = {
3163 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3166 static const char *att_names64[] = {
3167 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3168 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3170 static const char *att_names32[] = {
3171 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3172 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3174 static const char *att_names16[] = {
3175 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3176 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3178 static const char *att_names8[] = {
3179 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3181 static const char *att_names8rex[] = {
3182 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3183 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3185 static const char *att_names_seg[] = {
3186 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3188 static const char *att_index64 = "%riz";
3189 static const char *att_index32 = "%eiz";
3190 static const char *att_index16[] = {
3191 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3194 static const char **names_mm;
3195 static const char *intel_names_mm[] = {
3196 "mm0", "mm1", "mm2", "mm3",
3197 "mm4", "mm5", "mm6", "mm7"
3199 static const char *att_names_mm[] = {
3200 "%mm0", "%mm1", "%mm2", "%mm3",
3201 "%mm4", "%mm5", "%mm6", "%mm7"
3204 static const char *intel_names_bnd[] = {
3205 "bnd0", "bnd1", "bnd2", "bnd3"
3208 static const char *att_names_bnd[] = {
3209 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3212 static const char **names_xmm;
3213 static const char *intel_names_xmm[] = {
3214 "xmm0", "xmm1", "xmm2", "xmm3",
3215 "xmm4", "xmm5", "xmm6", "xmm7",
3216 "xmm8", "xmm9", "xmm10", "xmm11",
3217 "xmm12", "xmm13", "xmm14", "xmm15",
3218 "xmm16", "xmm17", "xmm18", "xmm19",
3219 "xmm20", "xmm21", "xmm22", "xmm23",
3220 "xmm24", "xmm25", "xmm26", "xmm27",
3221 "xmm28", "xmm29", "xmm30", "xmm31"
3223 static const char *att_names_xmm[] = {
3224 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3225 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3226 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3227 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3228 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3229 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3230 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3231 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3234 static const char **names_ymm;
3235 static const char *intel_names_ymm[] = {
3236 "ymm0", "ymm1", "ymm2", "ymm3",
3237 "ymm4", "ymm5", "ymm6", "ymm7",
3238 "ymm8", "ymm9", "ymm10", "ymm11",
3239 "ymm12", "ymm13", "ymm14", "ymm15",
3240 "ymm16", "ymm17", "ymm18", "ymm19",
3241 "ymm20", "ymm21", "ymm22", "ymm23",
3242 "ymm24", "ymm25", "ymm26", "ymm27",
3243 "ymm28", "ymm29", "ymm30", "ymm31"
3245 static const char *att_names_ymm[] = {
3246 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3247 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3248 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3249 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3250 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3251 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3252 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3253 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3256 static const char **names_zmm;
3257 static const char *intel_names_zmm[] = {
3258 "zmm0", "zmm1", "zmm2", "zmm3",
3259 "zmm4", "zmm5", "zmm6", "zmm7",
3260 "zmm8", "zmm9", "zmm10", "zmm11",
3261 "zmm12", "zmm13", "zmm14", "zmm15",
3262 "zmm16", "zmm17", "zmm18", "zmm19",
3263 "zmm20", "zmm21", "zmm22", "zmm23",
3264 "zmm24", "zmm25", "zmm26", "zmm27",
3265 "zmm28", "zmm29", "zmm30", "zmm31"
3267 static const char *att_names_zmm[] = {
3268 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3269 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3270 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3271 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3272 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3273 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3274 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3275 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3278 static const char **names_mask;
3279 static const char *intel_names_mask[] = {
3280 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3282 static const char *att_names_mask[] = {
3283 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3286 static const char *names_rounding[] =
3294 static const struct dis386 reg_table[][8] = {
3297 { "addA", { Ebh1, Ib } },
3298 { "orA", { Ebh1, Ib } },
3299 { "adcA", { Ebh1, Ib } },
3300 { "sbbA", { Ebh1, Ib } },
3301 { "andA", { Ebh1, Ib } },
3302 { "subA", { Ebh1, Ib } },
3303 { "xorA", { Ebh1, Ib } },
3304 { "cmpA", { Eb, Ib } },
3308 { "addQ", { Evh1, Iv } },
3309 { "orQ", { Evh1, Iv } },
3310 { "adcQ", { Evh1, Iv } },
3311 { "sbbQ", { Evh1, Iv } },
3312 { "andQ", { Evh1, Iv } },
3313 { "subQ", { Evh1, Iv } },
3314 { "xorQ", { Evh1, Iv } },
3315 { "cmpQ", { Ev, Iv } },
3319 { "addQ", { Evh1, sIb } },
3320 { "orQ", { Evh1, sIb } },
3321 { "adcQ", { Evh1, sIb } },
3322 { "sbbQ", { Evh1, sIb } },
3323 { "andQ", { Evh1, sIb } },
3324 { "subQ", { Evh1, sIb } },
3325 { "xorQ", { Evh1, sIb } },
3326 { "cmpQ", { Ev, sIb } },
3330 { "popU", { stackEv } },
3331 { XOP_8F_TABLE (XOP_09) },
3335 { XOP_8F_TABLE (XOP_09) },
3339 { "rolA", { Eb, Ib } },
3340 { "rorA", { Eb, Ib } },
3341 { "rclA", { Eb, Ib } },
3342 { "rcrA", { Eb, Ib } },
3343 { "shlA", { Eb, Ib } },
3344 { "shrA", { Eb, Ib } },
3346 { "sarA", { Eb, Ib } },
3350 { "rolQ", { Ev, Ib } },
3351 { "rorQ", { Ev, Ib } },
3352 { "rclQ", { Ev, Ib } },
3353 { "rcrQ", { Ev, Ib } },
3354 { "shlQ", { Ev, Ib } },
3355 { "shrQ", { Ev, Ib } },
3357 { "sarQ", { Ev, Ib } },
3361 { "movA", { Ebh3, Ib } },
3368 { MOD_TABLE (MOD_C6_REG_7) },
3372 { "movQ", { Evh3, Iv } },
3379 { MOD_TABLE (MOD_C7_REG_7) },
3383 { "rolA", { Eb, I1 } },
3384 { "rorA", { Eb, I1 } },
3385 { "rclA", { Eb, I1 } },
3386 { "rcrA", { Eb, I1 } },
3387 { "shlA", { Eb, I1 } },
3388 { "shrA", { Eb, I1 } },
3390 { "sarA", { Eb, I1 } },
3394 { "rolQ", { Ev, I1 } },
3395 { "rorQ", { Ev, I1 } },
3396 { "rclQ", { Ev, I1 } },
3397 { "rcrQ", { Ev, I1 } },
3398 { "shlQ", { Ev, I1 } },
3399 { "shrQ", { Ev, I1 } },
3401 { "sarQ", { Ev, I1 } },
3405 { "rolA", { Eb, CL } },
3406 { "rorA", { Eb, CL } },
3407 { "rclA", { Eb, CL } },
3408 { "rcrA", { Eb, CL } },
3409 { "shlA", { Eb, CL } },
3410 { "shrA", { Eb, CL } },
3412 { "sarA", { Eb, CL } },
3416 { "rolQ", { Ev, CL } },
3417 { "rorQ", { Ev, CL } },
3418 { "rclQ", { Ev, CL } },
3419 { "rcrQ", { Ev, CL } },
3420 { "shlQ", { Ev, CL } },
3421 { "shrQ", { Ev, CL } },
3423 { "sarQ", { Ev, CL } },
3427 { "testA", { Eb, Ib } },
3429 { "notA", { Ebh1 } },
3430 { "negA", { Ebh1 } },
3431 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
3432 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
3433 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
3434 { "idivA", { Eb } }, /* and idiv for consistency. */
3438 { "testQ", { Ev, Iv } },
3440 { "notQ", { Evh1 } },
3441 { "negQ", { Evh1 } },
3442 { "mulQ", { Ev } }, /* Don't print the implicit register. */
3443 { "imulQ", { Ev } },
3445 { "idivQ", { Ev } },
3449 { "incA", { Ebh1 } },
3450 { "decA", { Ebh1 } },
3454 { "incQ", { Evh1 } },
3455 { "decQ", { Evh1 } },
3456 { "call{T|}", { indirEv, BND } },
3457 { MOD_TABLE (MOD_FF_REG_3) },
3458 { "jmp{T|}", { indirEv, BND } },
3459 { MOD_TABLE (MOD_FF_REG_5) },
3460 { "pushU", { stackEv } },
3465 { "sldtD", { Sv } },
3476 { MOD_TABLE (MOD_0F01_REG_0) },
3477 { MOD_TABLE (MOD_0F01_REG_1) },
3478 { MOD_TABLE (MOD_0F01_REG_2) },
3479 { MOD_TABLE (MOD_0F01_REG_3) },
3480 { "smswD", { Sv } },
3483 { MOD_TABLE (MOD_0F01_REG_7) },
3487 { "prefetch", { Mb } },
3488 { "prefetchw", { Mb } },
3489 { "prefetchwt1", { Mb } },
3490 { "prefetch", { Mb } },
3491 { "prefetch", { Mb } },
3492 { "prefetch", { Mb } },
3493 { "prefetch", { Mb } },
3494 { "prefetch", { Mb } },
3498 { MOD_TABLE (MOD_0F18_REG_0) },
3499 { MOD_TABLE (MOD_0F18_REG_1) },
3500 { MOD_TABLE (MOD_0F18_REG_2) },
3501 { MOD_TABLE (MOD_0F18_REG_3) },
3502 { MOD_TABLE (MOD_0F18_REG_4) },
3503 { MOD_TABLE (MOD_0F18_REG_5) },
3504 { MOD_TABLE (MOD_0F18_REG_6) },
3505 { MOD_TABLE (MOD_0F18_REG_7) },
3511 { MOD_TABLE (MOD_0F71_REG_2) },
3513 { MOD_TABLE (MOD_0F71_REG_4) },
3515 { MOD_TABLE (MOD_0F71_REG_6) },
3521 { MOD_TABLE (MOD_0F72_REG_2) },
3523 { MOD_TABLE (MOD_0F72_REG_4) },
3525 { MOD_TABLE (MOD_0F72_REG_6) },
3531 { MOD_TABLE (MOD_0F73_REG_2) },
3532 { MOD_TABLE (MOD_0F73_REG_3) },
3535 { MOD_TABLE (MOD_0F73_REG_6) },
3536 { MOD_TABLE (MOD_0F73_REG_7) },
3540 { "montmul", { { OP_0f07, 0 } } },
3541 { "xsha1", { { OP_0f07, 0 } } },
3542 { "xsha256", { { OP_0f07, 0 } } },
3546 { "xstore-rng", { { OP_0f07, 0 } } },
3547 { "xcrypt-ecb", { { OP_0f07, 0 } } },
3548 { "xcrypt-cbc", { { OP_0f07, 0 } } },
3549 { "xcrypt-ctr", { { OP_0f07, 0 } } },
3550 { "xcrypt-cfb", { { OP_0f07, 0 } } },
3551 { "xcrypt-ofb", { { OP_0f07, 0 } } },
3555 { MOD_TABLE (MOD_0FAE_REG_0) },
3556 { MOD_TABLE (MOD_0FAE_REG_1) },
3557 { MOD_TABLE (MOD_0FAE_REG_2) },
3558 { MOD_TABLE (MOD_0FAE_REG_3) },
3559 { MOD_TABLE (MOD_0FAE_REG_4) },
3560 { MOD_TABLE (MOD_0FAE_REG_5) },
3561 { MOD_TABLE (MOD_0FAE_REG_6) },
3562 { MOD_TABLE (MOD_0FAE_REG_7) },
3570 { "btQ", { Ev, Ib } },
3571 { "btsQ", { Evh1, Ib } },
3572 { "btrQ", { Evh1, Ib } },
3573 { "btcQ", { Evh1, Ib } },
3578 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
3580 { MOD_TABLE (MOD_0FC7_REG_3) },
3581 { MOD_TABLE (MOD_0FC7_REG_4) },
3582 { MOD_TABLE (MOD_0FC7_REG_5) },
3583 { MOD_TABLE (MOD_0FC7_REG_6) },
3584 { MOD_TABLE (MOD_0FC7_REG_7) },
3590 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3592 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3594 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3600 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3602 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3604 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3610 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3611 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3614 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3615 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3621 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3622 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3624 /* REG_VEX_0F38F3 */
3627 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3628 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3629 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3633 { "llwpcb", { { OP_LWPCB_E, 0 } } },
3634 { "slwpcb", { { OP_LWPCB_E, 0 } } },
3638 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
3639 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
3641 /* REG_XOP_TBM_01 */
3644 { "blcfill", { { OP_LWP_E, 0 }, Ev } },
3645 { "blsfill", { { OP_LWP_E, 0 }, Ev } },
3646 { "blcs", { { OP_LWP_E, 0 }, Ev } },
3647 { "tzmsk", { { OP_LWP_E, 0 }, Ev } },
3648 { "blcic", { { OP_LWP_E, 0 }, Ev } },
3649 { "blsic", { { OP_LWP_E, 0 }, Ev } },
3650 { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
3652 /* REG_XOP_TBM_02 */
3655 { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
3660 { "blci", { { OP_LWP_E, 0 }, Ev } },
3662 #define NEED_REG_TABLE
3663 #include "i386-dis-evex.h"
3664 #undef NEED_REG_TABLE
3667 static const struct dis386 prefix_table[][4] = {
3670 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3671 { "pause", { XX } },
3672 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3677 { "movups", { XM, EXx } },
3678 { "movss", { XM, EXd } },
3679 { "movupd", { XM, EXx } },
3680 { "movsd", { XM, EXq } },
3685 { "movups", { EXxS, XM } },
3686 { "movss", { EXdS, XM } },
3687 { "movupd", { EXxS, XM } },
3688 { "movsd", { EXqS, XM } },
3693 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3694 { "movsldup", { XM, EXx } },
3695 { "movlpd", { XM, EXq } },
3696 { "movddup", { XM, EXq } },
3701 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3702 { "movshdup", { XM, EXx } },
3703 { "movhpd", { XM, EXq } },
3708 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3709 { "bndcl", { Gbnd, Ev_bnd } },
3710 { "bndmov", { Gbnd, Ebnd } },
3711 { "bndcu", { Gbnd, Ev_bnd } },
3716 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3717 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3718 { "bndmov", { Ebnd, Gbnd } },
3719 { "bndcn", { Gbnd, Ev_bnd } },
3724 { "cvtpi2ps", { XM, EMCq } },
3725 { "cvtsi2ss%LQ", { XM, Ev } },
3726 { "cvtpi2pd", { XM, EMCq } },
3727 { "cvtsi2sd%LQ", { XM, Ev } },
3732 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3733 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3734 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3735 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3740 { "cvttps2pi", { MXC, EXq } },
3741 { "cvttss2siY", { Gv, EXd } },
3742 { "cvttpd2pi", { MXC, EXx } },
3743 { "cvttsd2siY", { Gv, EXq } },
3748 { "cvtps2pi", { MXC, EXq } },
3749 { "cvtss2siY", { Gv, EXd } },
3750 { "cvtpd2pi", { MXC, EXx } },
3751 { "cvtsd2siY", { Gv, EXq } },
3756 { "ucomiss",{ XM, EXd } },
3758 { "ucomisd",{ XM, EXq } },
3763 { "comiss", { XM, EXd } },
3765 { "comisd", { XM, EXq } },
3770 { "sqrtps", { XM, EXx } },
3771 { "sqrtss", { XM, EXd } },
3772 { "sqrtpd", { XM, EXx } },
3773 { "sqrtsd", { XM, EXq } },
3778 { "rsqrtps",{ XM, EXx } },
3779 { "rsqrtss",{ XM, EXd } },
3784 { "rcpps", { XM, EXx } },
3785 { "rcpss", { XM, EXd } },
3790 { "addps", { XM, EXx } },
3791 { "addss", { XM, EXd } },
3792 { "addpd", { XM, EXx } },
3793 { "addsd", { XM, EXq } },
3798 { "mulps", { XM, EXx } },
3799 { "mulss", { XM, EXd } },
3800 { "mulpd", { XM, EXx } },
3801 { "mulsd", { XM, EXq } },
3806 { "cvtps2pd", { XM, EXq } },
3807 { "cvtss2sd", { XM, EXd } },
3808 { "cvtpd2ps", { XM, EXx } },
3809 { "cvtsd2ss", { XM, EXq } },
3814 { "cvtdq2ps", { XM, EXx } },
3815 { "cvttps2dq", { XM, EXx } },
3816 { "cvtps2dq", { XM, EXx } },
3821 { "subps", { XM, EXx } },
3822 { "subss", { XM, EXd } },
3823 { "subpd", { XM, EXx } },
3824 { "subsd", { XM, EXq } },
3829 { "minps", { XM, EXx } },
3830 { "minss", { XM, EXd } },
3831 { "minpd", { XM, EXx } },
3832 { "minsd", { XM, EXq } },
3837 { "divps", { XM, EXx } },
3838 { "divss", { XM, EXd } },
3839 { "divpd", { XM, EXx } },
3840 { "divsd", { XM, EXq } },
3845 { "maxps", { XM, EXx } },
3846 { "maxss", { XM, EXd } },
3847 { "maxpd", { XM, EXx } },
3848 { "maxsd", { XM, EXq } },
3853 { "punpcklbw",{ MX, EMd } },
3855 { "punpcklbw",{ MX, EMx } },
3860 { "punpcklwd",{ MX, EMd } },
3862 { "punpcklwd",{ MX, EMx } },
3867 { "punpckldq",{ MX, EMd } },
3869 { "punpckldq",{ MX, EMx } },
3876 { "punpcklqdq", { XM, EXx } },
3883 { "punpckhqdq", { XM, EXx } },
3888 { "movq", { MX, EM } },
3889 { "movdqu", { XM, EXx } },
3890 { "movdqa", { XM, EXx } },
3895 { "pshufw", { MX, EM, Ib } },
3896 { "pshufhw",{ XM, EXx, Ib } },
3897 { "pshufd", { XM, EXx, Ib } },
3898 { "pshuflw",{ XM, EXx, Ib } },
3901 /* PREFIX_0F73_REG_3 */
3905 { "psrldq", { XS, Ib } },
3908 /* PREFIX_0F73_REG_7 */
3912 { "pslldq", { XS, Ib } },
3917 {"vmread", { Em, Gm } },
3919 {"extrq", { XS, Ib, Ib } },
3920 {"insertq", { XM, XS, Ib, Ib } },
3925 {"vmwrite", { Gm, Em } },
3927 {"extrq", { XM, XS } },
3928 {"insertq", { XM, XS } },
3935 { "haddpd", { XM, EXx } },
3936 { "haddps", { XM, EXx } },
3943 { "hsubpd", { XM, EXx } },
3944 { "hsubps", { XM, EXx } },
3949 { "movK", { Edq, MX } },
3950 { "movq", { XM, EXq } },
3951 { "movK", { Edq, XM } },
3956 { "movq", { EMS, MX } },
3957 { "movdqu", { EXxS, XM } },
3958 { "movdqa", { EXxS, XM } },
3961 /* PREFIX_0FAE_REG_0 */
3964 { "rdfsbase", { Ev } },
3967 /* PREFIX_0FAE_REG_1 */
3970 { "rdgsbase", { Ev } },
3973 /* PREFIX_0FAE_REG_2 */
3976 { "wrfsbase", { Ev } },
3979 /* PREFIX_0FAE_REG_3 */
3982 { "wrgsbase", { Ev } },
3985 /* PREFIX_0FAE_REG_7 */
3987 { "clflush", { Mb } },
3989 { "clflushopt", { Mb } },
3995 { "popcntS", { Gv, Ev } },
4000 { "bsfS", { Gv, Ev } },
4001 { "tzcntS", { Gv, Ev } },
4002 { "bsfS", { Gv, Ev } },
4007 { "bsrS", { Gv, Ev } },
4008 { "lzcntS", { Gv, Ev } },
4009 { "bsrS", { Gv, Ev } },
4014 { "cmpps", { XM, EXx, CMP } },
4015 { "cmpss", { XM, EXd, CMP } },
4016 { "cmppd", { XM, EXx, CMP } },
4017 { "cmpsd", { XM, EXq, CMP } },
4022 { "movntiS", { Ma, Gv } },
4025 /* PREFIX_0FC7_REG_6 */
4027 { "vmptrld",{ Mq } },
4028 { "vmxon", { Mq } },
4029 { "vmclear",{ Mq } },
4036 { "addsubpd", { XM, EXx } },
4037 { "addsubps", { XM, EXx } },
4043 { "movq2dq",{ XM, MS } },
4044 { "movq", { EXqS, XM } },
4045 { "movdq2q",{ MX, XS } },
4051 { "cvtdq2pd", { XM, EXq } },
4052 { "cvttpd2dq", { XM, EXx } },
4053 { "cvtpd2dq", { XM, EXx } },
4058 { "movntq", { Mq, MX } },
4060 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4068 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4073 { "maskmovq", { MX, MS } },
4075 { "maskmovdqu", { XM, XS } },
4082 { "pblendvb", { XM, EXx, XMM0 } },
4089 { "blendvps", { XM, EXx, XMM0 } },
4096 { "blendvpd", { XM, EXx, XMM0 } },
4103 { "ptest", { XM, EXx } },
4110 { "pmovsxbw", { XM, EXq } },
4117 { "pmovsxbd", { XM, EXd } },
4124 { "pmovsxbq", { XM, EXw } },
4131 { "pmovsxwd", { XM, EXq } },
4138 { "pmovsxwq", { XM, EXd } },
4145 { "pmovsxdq", { XM, EXq } },
4152 { "pmuldq", { XM, EXx } },
4159 { "pcmpeqq", { XM, EXx } },
4166 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4173 { "packusdw", { XM, EXx } },
4180 { "pmovzxbw", { XM, EXq } },
4187 { "pmovzxbd", { XM, EXd } },
4194 { "pmovzxbq", { XM, EXw } },
4201 { "pmovzxwd", { XM, EXq } },
4208 { "pmovzxwq", { XM, EXd } },
4215 { "pmovzxdq", { XM, EXq } },
4222 { "pcmpgtq", { XM, EXx } },
4229 { "pminsb", { XM, EXx } },
4236 { "pminsd", { XM, EXx } },
4243 { "pminuw", { XM, EXx } },
4250 { "pminud", { XM, EXx } },
4257 { "pmaxsb", { XM, EXx } },
4264 { "pmaxsd", { XM, EXx } },
4271 { "pmaxuw", { XM, EXx } },
4278 { "pmaxud", { XM, EXx } },
4285 { "pmulld", { XM, EXx } },
4292 { "phminposuw", { XM, EXx } },
4299 { "invept", { Gm, Mo } },
4306 { "invvpid", { Gm, Mo } },
4313 { "invpcid", { Gm, M } },
4318 { "sha1nexte", { XM, EXxmm } },
4323 { "sha1msg1", { XM, EXxmm } },
4328 { "sha1msg2", { XM, EXxmm } },
4333 { "sha256rnds2", { XM, EXxmm, XMM0 } },
4338 { "sha256msg1", { XM, EXxmm } },
4343 { "sha256msg2", { XM, EXxmm } },
4350 { "aesimc", { XM, EXx } },
4357 { "aesenc", { XM, EXx } },
4364 { "aesenclast", { XM, EXx } },
4371 { "aesdec", { XM, EXx } },
4378 { "aesdeclast", { XM, EXx } },
4383 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4385 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4386 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
4391 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4393 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4394 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
4400 { "adoxS", { Gdq, Edq} },
4401 { "adcxS", { Gdq, Edq} },
4409 { "roundps", { XM, EXx, Ib } },
4416 { "roundpd", { XM, EXx, Ib } },
4423 { "roundss", { XM, EXd, Ib } },
4430 { "roundsd", { XM, EXq, Ib } },
4437 { "blendps", { XM, EXx, Ib } },
4444 { "blendpd", { XM, EXx, Ib } },
4451 { "pblendw", { XM, EXx, Ib } },
4458 { "pextrb", { Edqb, XM, Ib } },
4465 { "pextrw", { Edqw, XM, Ib } },
4472 { "pextrK", { Edq, XM, Ib } },
4479 { "extractps", { Edqd, XM, Ib } },
4486 { "pinsrb", { XM, Edqb, Ib } },
4493 { "insertps", { XM, EXd, Ib } },
4500 { "pinsrK", { XM, Edq, Ib } },
4507 { "dpps", { XM, EXx, Ib } },
4514 { "dppd", { XM, EXx, Ib } },
4521 { "mpsadbw", { XM, EXx, Ib } },
4528 { "pclmulqdq", { XM, EXx, PCLMUL } },
4535 { "pcmpestrm", { XM, EXx, Ib } },
4542 { "pcmpestri", { XM, EXx, Ib } },
4549 { "pcmpistrm", { XM, EXx, Ib } },
4556 { "pcmpistri", { XM, EXx, Ib } },
4561 { "sha1rnds4", { XM, EXxmm, Ib } },
4568 { "aeskeygenassist", { XM, EXx, Ib } },
4571 /* PREFIX_VEX_0F10 */
4573 { VEX_W_TABLE (VEX_W_0F10_P_0) },
4574 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4575 { VEX_W_TABLE (VEX_W_0F10_P_2) },
4576 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4579 /* PREFIX_VEX_0F11 */
4581 { VEX_W_TABLE (VEX_W_0F11_P_0) },
4582 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4583 { VEX_W_TABLE (VEX_W_0F11_P_2) },
4584 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4587 /* PREFIX_VEX_0F12 */
4589 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4590 { VEX_W_TABLE (VEX_W_0F12_P_1) },
4591 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4592 { VEX_W_TABLE (VEX_W_0F12_P_3) },
4595 /* PREFIX_VEX_0F16 */
4597 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4598 { VEX_W_TABLE (VEX_W_0F16_P_1) },
4599 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4602 /* PREFIX_VEX_0F2A */
4605 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4607 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4610 /* PREFIX_VEX_0F2C */
4613 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4615 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4618 /* PREFIX_VEX_0F2D */
4621 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4623 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4626 /* PREFIX_VEX_0F2E */
4628 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4630 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4633 /* PREFIX_VEX_0F2F */
4635 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4637 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4640 /* PREFIX_VEX_0F41 */
4642 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4644 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4647 /* PREFIX_VEX_0F42 */
4649 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4651 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4654 /* PREFIX_VEX_0F44 */
4656 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4658 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4661 /* PREFIX_VEX_0F45 */
4663 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4665 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4668 /* PREFIX_VEX_0F46 */
4670 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4672 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4675 /* PREFIX_VEX_0F47 */
4677 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4679 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4682 /* PREFIX_VEX_0F4A */
4684 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4686 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4689 /* PREFIX_VEX_0F4B */
4691 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4693 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4696 /* PREFIX_VEX_0F51 */
4698 { VEX_W_TABLE (VEX_W_0F51_P_0) },
4699 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4700 { VEX_W_TABLE (VEX_W_0F51_P_2) },
4701 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4704 /* PREFIX_VEX_0F52 */
4706 { VEX_W_TABLE (VEX_W_0F52_P_0) },
4707 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4710 /* PREFIX_VEX_0F53 */
4712 { VEX_W_TABLE (VEX_W_0F53_P_0) },
4713 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4716 /* PREFIX_VEX_0F58 */
4718 { VEX_W_TABLE (VEX_W_0F58_P_0) },
4719 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4720 { VEX_W_TABLE (VEX_W_0F58_P_2) },
4721 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4724 /* PREFIX_VEX_0F59 */
4726 { VEX_W_TABLE (VEX_W_0F59_P_0) },
4727 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4728 { VEX_W_TABLE (VEX_W_0F59_P_2) },
4729 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4732 /* PREFIX_VEX_0F5A */
4734 { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4735 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4736 { "vcvtpd2ps%XY", { XMM, EXx } },
4737 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4740 /* PREFIX_VEX_0F5B */
4742 { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4743 { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4744 { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4747 /* PREFIX_VEX_0F5C */
4749 { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4750 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4751 { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4752 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4755 /* PREFIX_VEX_0F5D */
4757 { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4758 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4759 { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4760 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4763 /* PREFIX_VEX_0F5E */
4765 { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4766 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4767 { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4768 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4771 /* PREFIX_VEX_0F5F */
4773 { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4774 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4775 { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4776 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4779 /* PREFIX_VEX_0F60 */
4783 { VEX_W_TABLE (VEX_W_0F60_P_2) },
4786 /* PREFIX_VEX_0F61 */
4790 { VEX_W_TABLE (VEX_W_0F61_P_2) },
4793 /* PREFIX_VEX_0F62 */
4797 { VEX_W_TABLE (VEX_W_0F62_P_2) },
4800 /* PREFIX_VEX_0F63 */
4804 { VEX_W_TABLE (VEX_W_0F63_P_2) },
4807 /* PREFIX_VEX_0F64 */
4811 { VEX_W_TABLE (VEX_W_0F64_P_2) },
4814 /* PREFIX_VEX_0F65 */
4818 { VEX_W_TABLE (VEX_W_0F65_P_2) },
4821 /* PREFIX_VEX_0F66 */
4825 { VEX_W_TABLE (VEX_W_0F66_P_2) },
4828 /* PREFIX_VEX_0F67 */
4832 { VEX_W_TABLE (VEX_W_0F67_P_2) },
4835 /* PREFIX_VEX_0F68 */
4839 { VEX_W_TABLE (VEX_W_0F68_P_2) },
4842 /* PREFIX_VEX_0F69 */
4846 { VEX_W_TABLE (VEX_W_0F69_P_2) },
4849 /* PREFIX_VEX_0F6A */
4853 { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4856 /* PREFIX_VEX_0F6B */
4860 { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4863 /* PREFIX_VEX_0F6C */
4867 { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4870 /* PREFIX_VEX_0F6D */
4874 { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4877 /* PREFIX_VEX_0F6E */
4881 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4884 /* PREFIX_VEX_0F6F */
4887 { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4888 { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4891 /* PREFIX_VEX_0F70 */
4894 { VEX_W_TABLE (VEX_W_0F70_P_1) },
4895 { VEX_W_TABLE (VEX_W_0F70_P_2) },
4896 { VEX_W_TABLE (VEX_W_0F70_P_3) },
4899 /* PREFIX_VEX_0F71_REG_2 */
4903 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4906 /* PREFIX_VEX_0F71_REG_4 */
4910 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4913 /* PREFIX_VEX_0F71_REG_6 */
4917 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4920 /* PREFIX_VEX_0F72_REG_2 */
4924 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4927 /* PREFIX_VEX_0F72_REG_4 */
4931 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4934 /* PREFIX_VEX_0F72_REG_6 */
4938 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4941 /* PREFIX_VEX_0F73_REG_2 */
4945 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4948 /* PREFIX_VEX_0F73_REG_3 */
4952 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4955 /* PREFIX_VEX_0F73_REG_6 */
4959 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4962 /* PREFIX_VEX_0F73_REG_7 */
4966 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4969 /* PREFIX_VEX_0F74 */
4973 { VEX_W_TABLE (VEX_W_0F74_P_2) },
4976 /* PREFIX_VEX_0F75 */
4980 { VEX_W_TABLE (VEX_W_0F75_P_2) },
4983 /* PREFIX_VEX_0F76 */
4987 { VEX_W_TABLE (VEX_W_0F76_P_2) },
4990 /* PREFIX_VEX_0F77 */
4992 { VEX_W_TABLE (VEX_W_0F77_P_0) },
4995 /* PREFIX_VEX_0F7C */
4999 { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5000 { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5003 /* PREFIX_VEX_0F7D */
5007 { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5008 { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5011 /* PREFIX_VEX_0F7E */
5014 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5015 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5018 /* PREFIX_VEX_0F7F */
5021 { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5022 { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5025 /* PREFIX_VEX_0F90 */
5027 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5029 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5032 /* PREFIX_VEX_0F91 */
5034 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5036 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5039 /* PREFIX_VEX_0F92 */
5041 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5043 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5044 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5047 /* PREFIX_VEX_0F93 */
5049 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5051 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5052 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5055 /* PREFIX_VEX_0F98 */
5057 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5059 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5062 /* PREFIX_VEX_0F99 */
5064 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5066 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5069 /* PREFIX_VEX_0FC2 */
5071 { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5072 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5073 { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5074 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5077 /* PREFIX_VEX_0FC4 */
5081 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5084 /* PREFIX_VEX_0FC5 */
5088 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5091 /* PREFIX_VEX_0FD0 */
5095 { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5096 { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5099 /* PREFIX_VEX_0FD1 */
5103 { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5106 /* PREFIX_VEX_0FD2 */
5110 { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5113 /* PREFIX_VEX_0FD3 */
5117 { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5120 /* PREFIX_VEX_0FD4 */
5124 { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5127 /* PREFIX_VEX_0FD5 */
5131 { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5134 /* PREFIX_VEX_0FD6 */
5138 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5141 /* PREFIX_VEX_0FD7 */
5145 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5148 /* PREFIX_VEX_0FD8 */
5152 { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5155 /* PREFIX_VEX_0FD9 */
5159 { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5162 /* PREFIX_VEX_0FDA */
5166 { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5169 /* PREFIX_VEX_0FDB */
5173 { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5176 /* PREFIX_VEX_0FDC */
5180 { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5183 /* PREFIX_VEX_0FDD */
5187 { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5190 /* PREFIX_VEX_0FDE */
5194 { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5197 /* PREFIX_VEX_0FDF */
5201 { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5204 /* PREFIX_VEX_0FE0 */
5208 { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5211 /* PREFIX_VEX_0FE1 */
5215 { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5218 /* PREFIX_VEX_0FE2 */
5222 { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5225 /* PREFIX_VEX_0FE3 */
5229 { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5232 /* PREFIX_VEX_0FE4 */
5236 { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5239 /* PREFIX_VEX_0FE5 */
5243 { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5246 /* PREFIX_VEX_0FE6 */
5249 { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5250 { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5251 { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5254 /* PREFIX_VEX_0FE7 */
5258 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5261 /* PREFIX_VEX_0FE8 */
5265 { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5268 /* PREFIX_VEX_0FE9 */
5272 { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5275 /* PREFIX_VEX_0FEA */
5279 { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5282 /* PREFIX_VEX_0FEB */
5286 { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5289 /* PREFIX_VEX_0FEC */
5293 { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5296 /* PREFIX_VEX_0FED */
5300 { VEX_W_TABLE (VEX_W_0FED_P_2) },
5303 /* PREFIX_VEX_0FEE */
5307 { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5310 /* PREFIX_VEX_0FEF */
5314 { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5317 /* PREFIX_VEX_0FF0 */
5322 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5325 /* PREFIX_VEX_0FF1 */
5329 { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5332 /* PREFIX_VEX_0FF2 */
5336 { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5339 /* PREFIX_VEX_0FF3 */
5343 { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5346 /* PREFIX_VEX_0FF4 */
5350 { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5353 /* PREFIX_VEX_0FF5 */
5357 { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5360 /* PREFIX_VEX_0FF6 */
5364 { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5367 /* PREFIX_VEX_0FF7 */
5371 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5374 /* PREFIX_VEX_0FF8 */
5378 { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5381 /* PREFIX_VEX_0FF9 */
5385 { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5388 /* PREFIX_VEX_0FFA */
5392 { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5395 /* PREFIX_VEX_0FFB */
5399 { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5402 /* PREFIX_VEX_0FFC */
5406 { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5409 /* PREFIX_VEX_0FFD */
5413 { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5416 /* PREFIX_VEX_0FFE */
5420 { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5423 /* PREFIX_VEX_0F3800 */
5427 { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5430 /* PREFIX_VEX_0F3801 */
5434 { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5437 /* PREFIX_VEX_0F3802 */
5441 { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5444 /* PREFIX_VEX_0F3803 */
5448 { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5451 /* PREFIX_VEX_0F3804 */
5455 { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5458 /* PREFIX_VEX_0F3805 */
5462 { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5465 /* PREFIX_VEX_0F3806 */
5469 { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5472 /* PREFIX_VEX_0F3807 */
5476 { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5479 /* PREFIX_VEX_0F3808 */
5483 { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5486 /* PREFIX_VEX_0F3809 */
5490 { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5493 /* PREFIX_VEX_0F380A */
5497 { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5500 /* PREFIX_VEX_0F380B */
5504 { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5507 /* PREFIX_VEX_0F380C */
5511 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5514 /* PREFIX_VEX_0F380D */
5518 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5521 /* PREFIX_VEX_0F380E */
5525 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5528 /* PREFIX_VEX_0F380F */
5532 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5535 /* PREFIX_VEX_0F3813 */
5539 { "vcvtph2ps", { XM, EXxmmq } },
5542 /* PREFIX_VEX_0F3816 */
5546 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5549 /* PREFIX_VEX_0F3817 */
5553 { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5556 /* PREFIX_VEX_0F3818 */
5560 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5563 /* PREFIX_VEX_0F3819 */
5567 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5570 /* PREFIX_VEX_0F381A */
5574 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5577 /* PREFIX_VEX_0F381C */
5581 { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5584 /* PREFIX_VEX_0F381D */
5588 { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5591 /* PREFIX_VEX_0F381E */
5595 { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5598 /* PREFIX_VEX_0F3820 */
5602 { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5605 /* PREFIX_VEX_0F3821 */
5609 { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5612 /* PREFIX_VEX_0F3822 */
5616 { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5619 /* PREFIX_VEX_0F3823 */
5623 { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5626 /* PREFIX_VEX_0F3824 */
5630 { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5633 /* PREFIX_VEX_0F3825 */
5637 { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5640 /* PREFIX_VEX_0F3828 */
5644 { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5647 /* PREFIX_VEX_0F3829 */
5651 { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5654 /* PREFIX_VEX_0F382A */
5658 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5661 /* PREFIX_VEX_0F382B */
5665 { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5668 /* PREFIX_VEX_0F382C */
5672 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5675 /* PREFIX_VEX_0F382D */
5679 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5682 /* PREFIX_VEX_0F382E */
5686 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5689 /* PREFIX_VEX_0F382F */
5693 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5696 /* PREFIX_VEX_0F3830 */
5700 { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5703 /* PREFIX_VEX_0F3831 */
5707 { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5710 /* PREFIX_VEX_0F3832 */
5714 { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5717 /* PREFIX_VEX_0F3833 */
5721 { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5724 /* PREFIX_VEX_0F3834 */
5728 { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5731 /* PREFIX_VEX_0F3835 */
5735 { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5738 /* PREFIX_VEX_0F3836 */
5742 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5745 /* PREFIX_VEX_0F3837 */
5749 { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5752 /* PREFIX_VEX_0F3838 */
5756 { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5759 /* PREFIX_VEX_0F3839 */
5763 { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5766 /* PREFIX_VEX_0F383A */
5770 { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5773 /* PREFIX_VEX_0F383B */
5777 { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5780 /* PREFIX_VEX_0F383C */
5784 { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5787 /* PREFIX_VEX_0F383D */
5791 { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5794 /* PREFIX_VEX_0F383E */
5798 { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5801 /* PREFIX_VEX_0F383F */
5805 { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5808 /* PREFIX_VEX_0F3840 */
5812 { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5815 /* PREFIX_VEX_0F3841 */
5819 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5822 /* PREFIX_VEX_0F3845 */
5826 { "vpsrlv%LW", { XM, Vex, EXx } },
5829 /* PREFIX_VEX_0F3846 */
5833 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5836 /* PREFIX_VEX_0F3847 */
5840 { "vpsllv%LW", { XM, Vex, EXx } },
5843 /* PREFIX_VEX_0F3858 */
5847 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5850 /* PREFIX_VEX_0F3859 */
5854 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5857 /* PREFIX_VEX_0F385A */
5861 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5864 /* PREFIX_VEX_0F3878 */
5868 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5871 /* PREFIX_VEX_0F3879 */
5875 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5878 /* PREFIX_VEX_0F388C */
5882 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5885 /* PREFIX_VEX_0F388E */
5889 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5892 /* PREFIX_VEX_0F3890 */
5896 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
5899 /* PREFIX_VEX_0F3891 */
5903 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5906 /* PREFIX_VEX_0F3892 */
5910 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
5913 /* PREFIX_VEX_0F3893 */
5917 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5920 /* PREFIX_VEX_0F3896 */
5924 { "vfmaddsub132p%XW", { XM, Vex, EXx } },
5927 /* PREFIX_VEX_0F3897 */
5931 { "vfmsubadd132p%XW", { XM, Vex, EXx } },
5934 /* PREFIX_VEX_0F3898 */
5938 { "vfmadd132p%XW", { XM, Vex, EXx } },
5941 /* PREFIX_VEX_0F3899 */
5945 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5948 /* PREFIX_VEX_0F389A */
5952 { "vfmsub132p%XW", { XM, Vex, EXx } },
5955 /* PREFIX_VEX_0F389B */
5959 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5962 /* PREFIX_VEX_0F389C */
5966 { "vfnmadd132p%XW", { XM, Vex, EXx } },
5969 /* PREFIX_VEX_0F389D */
5973 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5976 /* PREFIX_VEX_0F389E */
5980 { "vfnmsub132p%XW", { XM, Vex, EXx } },
5983 /* PREFIX_VEX_0F389F */
5987 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5990 /* PREFIX_VEX_0F38A6 */
5994 { "vfmaddsub213p%XW", { XM, Vex, EXx } },
5998 /* PREFIX_VEX_0F38A7 */
6002 { "vfmsubadd213p%XW", { XM, Vex, EXx } },
6005 /* PREFIX_VEX_0F38A8 */
6009 { "vfmadd213p%XW", { XM, Vex, EXx } },
6012 /* PREFIX_VEX_0F38A9 */
6016 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6019 /* PREFIX_VEX_0F38AA */
6023 { "vfmsub213p%XW", { XM, Vex, EXx } },
6026 /* PREFIX_VEX_0F38AB */
6030 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6033 /* PREFIX_VEX_0F38AC */
6037 { "vfnmadd213p%XW", { XM, Vex, EXx } },
6040 /* PREFIX_VEX_0F38AD */
6044 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6047 /* PREFIX_VEX_0F38AE */
6051 { "vfnmsub213p%XW", { XM, Vex, EXx } },
6054 /* PREFIX_VEX_0F38AF */
6058 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6061 /* PREFIX_VEX_0F38B6 */
6065 { "vfmaddsub231p%XW", { XM, Vex, EXx } },
6068 /* PREFIX_VEX_0F38B7 */
6072 { "vfmsubadd231p%XW", { XM, Vex, EXx } },
6075 /* PREFIX_VEX_0F38B8 */
6079 { "vfmadd231p%XW", { XM, Vex, EXx } },
6082 /* PREFIX_VEX_0F38B9 */
6086 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6089 /* PREFIX_VEX_0F38BA */
6093 { "vfmsub231p%XW", { XM, Vex, EXx } },
6096 /* PREFIX_VEX_0F38BB */
6100 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6103 /* PREFIX_VEX_0F38BC */
6107 { "vfnmadd231p%XW", { XM, Vex, EXx } },
6110 /* PREFIX_VEX_0F38BD */
6114 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6117 /* PREFIX_VEX_0F38BE */
6121 { "vfnmsub231p%XW", { XM, Vex, EXx } },
6124 /* PREFIX_VEX_0F38BF */
6128 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6131 /* PREFIX_VEX_0F38DB */
6135 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6138 /* PREFIX_VEX_0F38DC */
6142 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6145 /* PREFIX_VEX_0F38DD */
6149 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6152 /* PREFIX_VEX_0F38DE */
6156 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6159 /* PREFIX_VEX_0F38DF */
6163 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6166 /* PREFIX_VEX_0F38F2 */
6168 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6171 /* PREFIX_VEX_0F38F3_REG_1 */
6173 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6176 /* PREFIX_VEX_0F38F3_REG_2 */
6178 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6181 /* PREFIX_VEX_0F38F3_REG_3 */
6183 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6186 /* PREFIX_VEX_0F38F5 */
6188 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6189 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6191 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6194 /* PREFIX_VEX_0F38F6 */
6199 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6202 /* PREFIX_VEX_0F38F7 */
6204 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6205 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6206 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6207 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6210 /* PREFIX_VEX_0F3A00 */
6214 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6217 /* PREFIX_VEX_0F3A01 */
6221 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6224 /* PREFIX_VEX_0F3A02 */
6228 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6231 /* PREFIX_VEX_0F3A04 */
6235 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6238 /* PREFIX_VEX_0F3A05 */
6242 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6245 /* PREFIX_VEX_0F3A06 */
6249 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6252 /* PREFIX_VEX_0F3A08 */
6256 { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6259 /* PREFIX_VEX_0F3A09 */
6263 { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6266 /* PREFIX_VEX_0F3A0A */
6270 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6273 /* PREFIX_VEX_0F3A0B */
6277 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6280 /* PREFIX_VEX_0F3A0C */
6284 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6287 /* PREFIX_VEX_0F3A0D */
6291 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6294 /* PREFIX_VEX_0F3A0E */
6298 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6301 /* PREFIX_VEX_0F3A0F */
6305 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6308 /* PREFIX_VEX_0F3A14 */
6312 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6315 /* PREFIX_VEX_0F3A15 */
6319 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6322 /* PREFIX_VEX_0F3A16 */
6326 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6329 /* PREFIX_VEX_0F3A17 */
6333 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6336 /* PREFIX_VEX_0F3A18 */
6340 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6343 /* PREFIX_VEX_0F3A19 */
6347 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6350 /* PREFIX_VEX_0F3A1D */
6354 { "vcvtps2ph", { EXxmmq, XM, Ib } },
6357 /* PREFIX_VEX_0F3A20 */
6361 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6364 /* PREFIX_VEX_0F3A21 */
6368 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6371 /* PREFIX_VEX_0F3A22 */
6375 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6378 /* PREFIX_VEX_0F3A30 */
6382 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6385 /* PREFIX_VEX_0F3A31 */
6389 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6392 /* PREFIX_VEX_0F3A32 */
6396 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6399 /* PREFIX_VEX_0F3A33 */
6403 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6406 /* PREFIX_VEX_0F3A38 */
6410 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6413 /* PREFIX_VEX_0F3A39 */
6417 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6420 /* PREFIX_VEX_0F3A40 */
6424 { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6427 /* PREFIX_VEX_0F3A41 */
6431 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6434 /* PREFIX_VEX_0F3A42 */
6438 { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6441 /* PREFIX_VEX_0F3A44 */
6445 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6448 /* PREFIX_VEX_0F3A46 */
6452 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6455 /* PREFIX_VEX_0F3A48 */
6459 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6462 /* PREFIX_VEX_0F3A49 */
6466 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6469 /* PREFIX_VEX_0F3A4A */
6473 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6476 /* PREFIX_VEX_0F3A4B */
6480 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6483 /* PREFIX_VEX_0F3A4C */
6487 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6490 /* PREFIX_VEX_0F3A5C */
6494 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6497 /* PREFIX_VEX_0F3A5D */
6501 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6504 /* PREFIX_VEX_0F3A5E */
6508 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6511 /* PREFIX_VEX_0F3A5F */
6515 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6518 /* PREFIX_VEX_0F3A60 */
6522 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6526 /* PREFIX_VEX_0F3A61 */
6530 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6533 /* PREFIX_VEX_0F3A62 */
6537 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6540 /* PREFIX_VEX_0F3A63 */
6544 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6547 /* PREFIX_VEX_0F3A68 */
6551 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6554 /* PREFIX_VEX_0F3A69 */
6558 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6561 /* PREFIX_VEX_0F3A6A */
6565 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6568 /* PREFIX_VEX_0F3A6B */
6572 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6575 /* PREFIX_VEX_0F3A6C */
6579 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6582 /* PREFIX_VEX_0F3A6D */
6586 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6589 /* PREFIX_VEX_0F3A6E */
6593 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6596 /* PREFIX_VEX_0F3A6F */
6600 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6603 /* PREFIX_VEX_0F3A78 */
6607 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6610 /* PREFIX_VEX_0F3A79 */
6614 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6617 /* PREFIX_VEX_0F3A7A */
6621 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6624 /* PREFIX_VEX_0F3A7B */
6628 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6631 /* PREFIX_VEX_0F3A7C */
6635 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6639 /* PREFIX_VEX_0F3A7D */
6643 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6646 /* PREFIX_VEX_0F3A7E */
6650 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6653 /* PREFIX_VEX_0F3A7F */
6657 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6660 /* PREFIX_VEX_0F3ADF */
6664 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6667 /* PREFIX_VEX_0F3AF0 */
6672 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6675 #define NEED_PREFIX_TABLE
6676 #include "i386-dis-evex.h"
6677 #undef NEED_PREFIX_TABLE
6680 static const struct dis386 x86_64_table[][2] = {
6683 { "pushP", { es } },
6693 { "pushP", { cs } },
6698 { "pushP", { ss } },
6708 { "pushP", { ds } },
6738 { "pushaP", { XX } },
6743 { "popaP", { XX } },
6748 { MOD_TABLE (MOD_62_32BIT) },
6749 { EVEX_TABLE (EVEX_0F) },
6754 { "arpl", { Ew, Gw } },
6755 { "movs{lq|xd}", { Gv, Ed } },
6760 { "ins{R|}", { Yzr, indirDX } },
6761 { "ins{G|}", { Yzr, indirDX } },
6766 { "outs{R|}", { indirDXr, Xz } },
6767 { "outs{G|}", { indirDXr, Xz } },
6772 { "Jcall{T|}", { Ap } },
6777 { MOD_TABLE (MOD_C4_32BIT) },
6778 { VEX_C4_TABLE (VEX_0F) },
6783 { MOD_TABLE (MOD_C5_32BIT) },
6784 { VEX_C5_TABLE (VEX_0F) },
6804 { "Jjmp{T|}", { Ap } },
6807 /* X86_64_0F01_REG_0 */
6809 { "sgdt{Q|IQ}", { M } },
6813 /* X86_64_0F01_REG_1 */
6815 { "sidt{Q|IQ}", { M } },
6819 /* X86_64_0F01_REG_2 */
6821 { "lgdt{Q|Q}", { M } },
6825 /* X86_64_0F01_REG_3 */
6827 { "lidt{Q|Q}", { M } },
6832 static const struct dis386 three_byte_table[][256] = {
6834 /* THREE_BYTE_0F38 */
6837 { "pshufb", { MX, EM } },
6838 { "phaddw", { MX, EM } },
6839 { "phaddd", { MX, EM } },
6840 { "phaddsw", { MX, EM } },
6841 { "pmaddubsw", { MX, EM } },
6842 { "phsubw", { MX, EM } },
6843 { "phsubd", { MX, EM } },
6844 { "phsubsw", { MX, EM } },
6846 { "psignb", { MX, EM } },
6847 { "psignw", { MX, EM } },
6848 { "psignd", { MX, EM } },
6849 { "pmulhrsw", { MX, EM } },
6855 { PREFIX_TABLE (PREFIX_0F3810) },
6859 { PREFIX_TABLE (PREFIX_0F3814) },
6860 { PREFIX_TABLE (PREFIX_0F3815) },
6862 { PREFIX_TABLE (PREFIX_0F3817) },
6868 { "pabsb", { MX, EM } },
6869 { "pabsw", { MX, EM } },
6870 { "pabsd", { MX, EM } },
6873 { PREFIX_TABLE (PREFIX_0F3820) },
6874 { PREFIX_TABLE (PREFIX_0F3821) },
6875 { PREFIX_TABLE (PREFIX_0F3822) },
6876 { PREFIX_TABLE (PREFIX_0F3823) },
6877 { PREFIX_TABLE (PREFIX_0F3824) },
6878 { PREFIX_TABLE (PREFIX_0F3825) },
6882 { PREFIX_TABLE (PREFIX_0F3828) },
6883 { PREFIX_TABLE (PREFIX_0F3829) },
6884 { PREFIX_TABLE (PREFIX_0F382A) },
6885 { PREFIX_TABLE (PREFIX_0F382B) },
6891 { PREFIX_TABLE (PREFIX_0F3830) },
6892 { PREFIX_TABLE (PREFIX_0F3831) },
6893 { PREFIX_TABLE (PREFIX_0F3832) },
6894 { PREFIX_TABLE (PREFIX_0F3833) },
6895 { PREFIX_TABLE (PREFIX_0F3834) },
6896 { PREFIX_TABLE (PREFIX_0F3835) },
6898 { PREFIX_TABLE (PREFIX_0F3837) },
6900 { PREFIX_TABLE (PREFIX_0F3838) },
6901 { PREFIX_TABLE (PREFIX_0F3839) },
6902 { PREFIX_TABLE (PREFIX_0F383A) },
6903 { PREFIX_TABLE (PREFIX_0F383B) },
6904 { PREFIX_TABLE (PREFIX_0F383C) },
6905 { PREFIX_TABLE (PREFIX_0F383D) },
6906 { PREFIX_TABLE (PREFIX_0F383E) },
6907 { PREFIX_TABLE (PREFIX_0F383F) },
6909 { PREFIX_TABLE (PREFIX_0F3840) },
6910 { PREFIX_TABLE (PREFIX_0F3841) },
6981 { PREFIX_TABLE (PREFIX_0F3880) },
6982 { PREFIX_TABLE (PREFIX_0F3881) },
6983 { PREFIX_TABLE (PREFIX_0F3882) },
7062 { PREFIX_TABLE (PREFIX_0F38C8) },
7063 { PREFIX_TABLE (PREFIX_0F38C9) },
7064 { PREFIX_TABLE (PREFIX_0F38CA) },
7065 { PREFIX_TABLE (PREFIX_0F38CB) },
7066 { PREFIX_TABLE (PREFIX_0F38CC) },
7067 { PREFIX_TABLE (PREFIX_0F38CD) },
7083 { PREFIX_TABLE (PREFIX_0F38DB) },
7084 { PREFIX_TABLE (PREFIX_0F38DC) },
7085 { PREFIX_TABLE (PREFIX_0F38DD) },
7086 { PREFIX_TABLE (PREFIX_0F38DE) },
7087 { PREFIX_TABLE (PREFIX_0F38DF) },
7107 { PREFIX_TABLE (PREFIX_0F38F0) },
7108 { PREFIX_TABLE (PREFIX_0F38F1) },
7113 { PREFIX_TABLE (PREFIX_0F38F6) },
7125 /* THREE_BYTE_0F3A */
7137 { PREFIX_TABLE (PREFIX_0F3A08) },
7138 { PREFIX_TABLE (PREFIX_0F3A09) },
7139 { PREFIX_TABLE (PREFIX_0F3A0A) },
7140 { PREFIX_TABLE (PREFIX_0F3A0B) },
7141 { PREFIX_TABLE (PREFIX_0F3A0C) },
7142 { PREFIX_TABLE (PREFIX_0F3A0D) },
7143 { PREFIX_TABLE (PREFIX_0F3A0E) },
7144 { "palignr", { MX, EM, Ib } },
7150 { PREFIX_TABLE (PREFIX_0F3A14) },
7151 { PREFIX_TABLE (PREFIX_0F3A15) },
7152 { PREFIX_TABLE (PREFIX_0F3A16) },
7153 { PREFIX_TABLE (PREFIX_0F3A17) },
7164 { PREFIX_TABLE (PREFIX_0F3A20) },
7165 { PREFIX_TABLE (PREFIX_0F3A21) },
7166 { PREFIX_TABLE (PREFIX_0F3A22) },
7200 { PREFIX_TABLE (PREFIX_0F3A40) },
7201 { PREFIX_TABLE (PREFIX_0F3A41) },
7202 { PREFIX_TABLE (PREFIX_0F3A42) },
7204 { PREFIX_TABLE (PREFIX_0F3A44) },
7236 { PREFIX_TABLE (PREFIX_0F3A60) },
7237 { PREFIX_TABLE (PREFIX_0F3A61) },
7238 { PREFIX_TABLE (PREFIX_0F3A62) },
7239 { PREFIX_TABLE (PREFIX_0F3A63) },
7357 { PREFIX_TABLE (PREFIX_0F3ACC) },
7378 { PREFIX_TABLE (PREFIX_0F3ADF) },
7417 /* THREE_BYTE_0F7A */
7456 { "ptest", { XX } },
7493 { "phaddbw", { XM, EXq } },
7494 { "phaddbd", { XM, EXq } },
7495 { "phaddbq", { XM, EXq } },
7498 { "phaddwd", { XM, EXq } },
7499 { "phaddwq", { XM, EXq } },
7504 { "phadddq", { XM, EXq } },
7511 { "phaddubw", { XM, EXq } },
7512 { "phaddubd", { XM, EXq } },
7513 { "phaddubq", { XM, EXq } },
7516 { "phadduwd", { XM, EXq } },
7517 { "phadduwq", { XM, EXq } },
7522 { "phaddudq", { XM, EXq } },
7529 { "phsubbw", { XM, EXq } },
7530 { "phsubbd", { XM, EXq } },
7531 { "phsubbq", { XM, EXq } },
7710 static const struct dis386 xop_table[][256] = {
7863 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7864 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7865 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7873 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7874 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7881 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7882 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7883 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7891 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7892 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7896 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7897 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7900 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7918 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7930 { "vprotb", { XM, Vex_2src_1, Ib } },
7931 { "vprotw", { XM, Vex_2src_1, Ib } },
7932 { "vprotd", { XM, Vex_2src_1, Ib } },
7933 { "vprotq", { XM, Vex_2src_1, Ib } },
7943 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7944 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7945 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7946 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7979 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7980 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7981 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7982 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8006 { REG_TABLE (REG_XOP_TBM_01) },
8007 { REG_TABLE (REG_XOP_TBM_02) },
8025 { REG_TABLE (REG_XOP_LWPCB) },
8149 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8150 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8151 { "vfrczss", { XM, EXd } },
8152 { "vfrczsd", { XM, EXq } },
8167 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } },
8168 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } },
8169 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } },
8170 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } },
8171 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } },
8172 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } },
8173 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } },
8174 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } },
8176 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } },
8177 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } },
8178 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } },
8179 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } },
8222 { "vphaddbw", { XM, EXxmm } },
8223 { "vphaddbd", { XM, EXxmm } },
8224 { "vphaddbq", { XM, EXxmm } },
8227 { "vphaddwd", { XM, EXxmm } },
8228 { "vphaddwq", { XM, EXxmm } },
8233 { "vphadddq", { XM, EXxmm } },
8240 { "vphaddubw", { XM, EXxmm } },
8241 { "vphaddubd", { XM, EXxmm } },
8242 { "vphaddubq", { XM, EXxmm } },
8245 { "vphadduwd", { XM, EXxmm } },
8246 { "vphadduwq", { XM, EXxmm } },
8251 { "vphaddudq", { XM, EXxmm } },
8258 { "vphsubbw", { XM, EXxmm } },
8259 { "vphsubwd", { XM, EXxmm } },
8260 { "vphsubdq", { XM, EXxmm } },
8314 { "bextr", { Gv, Ev, Iq } },
8316 { REG_TABLE (REG_XOP_LWP) },
8586 static const struct dis386 vex_table[][256] = {
8608 { PREFIX_TABLE (PREFIX_VEX_0F10) },
8609 { PREFIX_TABLE (PREFIX_VEX_0F11) },
8610 { PREFIX_TABLE (PREFIX_VEX_0F12) },
8611 { MOD_TABLE (MOD_VEX_0F13) },
8612 { VEX_W_TABLE (VEX_W_0F14) },
8613 { VEX_W_TABLE (VEX_W_0F15) },
8614 { PREFIX_TABLE (PREFIX_VEX_0F16) },
8615 { MOD_TABLE (MOD_VEX_0F17) },
8635 { VEX_W_TABLE (VEX_W_0F28) },
8636 { VEX_W_TABLE (VEX_W_0F29) },
8637 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8638 { MOD_TABLE (MOD_VEX_0F2B) },
8639 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8640 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8641 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8642 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8663 { PREFIX_TABLE (PREFIX_VEX_0F41) },
8664 { PREFIX_TABLE (PREFIX_VEX_0F42) },
8666 { PREFIX_TABLE (PREFIX_VEX_0F44) },
8667 { PREFIX_TABLE (PREFIX_VEX_0F45) },
8668 { PREFIX_TABLE (PREFIX_VEX_0F46) },
8669 { PREFIX_TABLE (PREFIX_VEX_0F47) },
8673 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8674 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8680 { MOD_TABLE (MOD_VEX_0F50) },
8681 { PREFIX_TABLE (PREFIX_VEX_0F51) },
8682 { PREFIX_TABLE (PREFIX_VEX_0F52) },
8683 { PREFIX_TABLE (PREFIX_VEX_0F53) },
8684 { "vandpX", { XM, Vex, EXx } },
8685 { "vandnpX", { XM, Vex, EXx } },
8686 { "vorpX", { XM, Vex, EXx } },
8687 { "vxorpX", { XM, Vex, EXx } },
8689 { PREFIX_TABLE (PREFIX_VEX_0F58) },
8690 { PREFIX_TABLE (PREFIX_VEX_0F59) },
8691 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8692 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8693 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8694 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8695 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8696 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8698 { PREFIX_TABLE (PREFIX_VEX_0F60) },
8699 { PREFIX_TABLE (PREFIX_VEX_0F61) },
8700 { PREFIX_TABLE (PREFIX_VEX_0F62) },
8701 { PREFIX_TABLE (PREFIX_VEX_0F63) },
8702 { PREFIX_TABLE (PREFIX_VEX_0F64) },
8703 { PREFIX_TABLE (PREFIX_VEX_0F65) },
8704 { PREFIX_TABLE (PREFIX_VEX_0F66) },
8705 { PREFIX_TABLE (PREFIX_VEX_0F67) },
8707 { PREFIX_TABLE (PREFIX_VEX_0F68) },
8708 { PREFIX_TABLE (PREFIX_VEX_0F69) },
8709 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8710 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8711 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8712 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8713 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8714 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8716 { PREFIX_TABLE (PREFIX_VEX_0F70) },
8717 { REG_TABLE (REG_VEX_0F71) },
8718 { REG_TABLE (REG_VEX_0F72) },
8719 { REG_TABLE (REG_VEX_0F73) },
8720 { PREFIX_TABLE (PREFIX_VEX_0F74) },
8721 { PREFIX_TABLE (PREFIX_VEX_0F75) },
8722 { PREFIX_TABLE (PREFIX_VEX_0F76) },
8723 { PREFIX_TABLE (PREFIX_VEX_0F77) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F90) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F91) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F92) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F93) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F98) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F99) },
8785 { REG_TABLE (REG_VEX_0FAE) },
8808 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8810 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8811 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8812 { "vshufpX", { XM, Vex, EXx, Ib } },
8824 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8825 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8826 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8827 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8828 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8829 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8830 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8831 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8833 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8834 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8835 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8836 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8837 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8838 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8839 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8840 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8842 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8843 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8844 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8845 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8846 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8847 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8848 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8849 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8851 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8852 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8853 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8854 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8855 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8856 { PREFIX_TABLE (PREFIX_VEX_0FED) },
8857 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8858 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8860 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8861 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8862 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8863 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8864 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8865 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8866 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8867 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8869 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8870 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8871 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8872 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8873 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8874 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8875 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8881 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8882 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8883 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8884 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8885 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8886 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8895 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8896 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8905 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8909 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8926 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8927 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8928 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8929 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8954 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8959 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8960 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8980 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8981 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8982 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9017 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9038 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9046 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9049 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9050 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9052 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9053 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9054 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9055 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9056 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9057 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9058 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9059 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9067 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9068 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9077 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9085 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9086 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9088 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9094 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9127 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9128 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9129 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9130 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9131 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9153 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9154 { REG_TABLE (REG_VEX_0F38F3) },
9156 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9157 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9158 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9172 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9173 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9174 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9176 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9177 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9178 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9181 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9182 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9183 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9184 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9185 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9186 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9187 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9188 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9194 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9195 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9196 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9197 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9199 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9200 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9204 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9208 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9209 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9210 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9226 { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9227 { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9228 { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9229 { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9235 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9236 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9244 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9245 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9246 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9248 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9250 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9253 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9254 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9255 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9256 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9257 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9275 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9276 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9277 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9278 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9280 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9281 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9282 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9283 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9289 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9290 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9291 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9292 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9293 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9294 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9295 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9296 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9307 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9308 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9309 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9310 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9311 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9312 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9313 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9314 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9422 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9442 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9462 #define NEED_OPCODE_TABLE
9463 #include "i386-dis-evex.h"
9464 #undef NEED_OPCODE_TABLE
9465 static const struct dis386 vex_len_table[][2] = {
9466 /* VEX_LEN_0F10_P_1 */
9468 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9469 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9472 /* VEX_LEN_0F10_P_3 */
9474 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9475 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9478 /* VEX_LEN_0F11_P_1 */
9480 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9481 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9484 /* VEX_LEN_0F11_P_3 */
9486 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9487 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9490 /* VEX_LEN_0F12_P_0_M_0 */
9492 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9495 /* VEX_LEN_0F12_P_0_M_1 */
9497 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9500 /* VEX_LEN_0F12_P_2 */
9502 { VEX_W_TABLE (VEX_W_0F12_P_2) },
9505 /* VEX_LEN_0F13_M_0 */
9507 { VEX_W_TABLE (VEX_W_0F13_M_0) },
9510 /* VEX_LEN_0F16_P_0_M_0 */
9512 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9515 /* VEX_LEN_0F16_P_0_M_1 */
9517 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9520 /* VEX_LEN_0F16_P_2 */
9522 { VEX_W_TABLE (VEX_W_0F16_P_2) },
9525 /* VEX_LEN_0F17_M_0 */
9527 { VEX_W_TABLE (VEX_W_0F17_M_0) },
9530 /* VEX_LEN_0F2A_P_1 */
9532 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
9533 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
9536 /* VEX_LEN_0F2A_P_3 */
9538 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
9539 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
9542 /* VEX_LEN_0F2C_P_1 */
9544 { "vcvttss2siY", { Gv, EXdScalar } },
9545 { "vcvttss2siY", { Gv, EXdScalar } },
9548 /* VEX_LEN_0F2C_P_3 */
9550 { "vcvttsd2siY", { Gv, EXqScalar } },
9551 { "vcvttsd2siY", { Gv, EXqScalar } },
9554 /* VEX_LEN_0F2D_P_1 */
9556 { "vcvtss2siY", { Gv, EXdScalar } },
9557 { "vcvtss2siY", { Gv, EXdScalar } },
9560 /* VEX_LEN_0F2D_P_3 */
9562 { "vcvtsd2siY", { Gv, EXqScalar } },
9563 { "vcvtsd2siY", { Gv, EXqScalar } },
9566 /* VEX_LEN_0F2E_P_0 */
9568 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9569 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9572 /* VEX_LEN_0F2E_P_2 */
9574 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9575 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9578 /* VEX_LEN_0F2F_P_0 */
9580 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9581 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9584 /* VEX_LEN_0F2F_P_2 */
9586 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9587 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9590 /* VEX_LEN_0F41_P_0 */
9593 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9595 /* VEX_LEN_0F41_P_2 */
9598 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9600 /* VEX_LEN_0F42_P_0 */
9603 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9605 /* VEX_LEN_0F42_P_2 */
9608 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9610 /* VEX_LEN_0F44_P_0 */
9612 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9614 /* VEX_LEN_0F44_P_2 */
9616 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9618 /* VEX_LEN_0F45_P_0 */
9621 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9623 /* VEX_LEN_0F45_P_2 */
9626 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9628 /* VEX_LEN_0F46_P_0 */
9631 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9633 /* VEX_LEN_0F46_P_2 */
9636 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9638 /* VEX_LEN_0F47_P_0 */
9641 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9643 /* VEX_LEN_0F47_P_2 */
9646 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9648 /* VEX_LEN_0F4A_P_0 */
9651 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9653 /* VEX_LEN_0F4A_P_2 */
9656 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9658 /* VEX_LEN_0F4B_P_0 */
9661 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9663 /* VEX_LEN_0F4B_P_2 */
9666 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9669 /* VEX_LEN_0F51_P_1 */
9671 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9672 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9675 /* VEX_LEN_0F51_P_3 */
9677 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9678 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9681 /* VEX_LEN_0F52_P_1 */
9683 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9684 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9687 /* VEX_LEN_0F53_P_1 */
9689 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9690 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9693 /* VEX_LEN_0F58_P_1 */
9695 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9696 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9699 /* VEX_LEN_0F58_P_3 */
9701 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9702 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9705 /* VEX_LEN_0F59_P_1 */
9707 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9708 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9711 /* VEX_LEN_0F59_P_3 */
9713 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9714 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9717 /* VEX_LEN_0F5A_P_1 */
9719 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9720 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9723 /* VEX_LEN_0F5A_P_3 */
9725 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9726 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9729 /* VEX_LEN_0F5C_P_1 */
9731 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9732 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9735 /* VEX_LEN_0F5C_P_3 */
9737 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9738 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9741 /* VEX_LEN_0F5D_P_1 */
9743 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9744 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9747 /* VEX_LEN_0F5D_P_3 */
9749 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9750 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9753 /* VEX_LEN_0F5E_P_1 */
9755 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9756 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9759 /* VEX_LEN_0F5E_P_3 */
9761 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9762 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9765 /* VEX_LEN_0F5F_P_1 */
9767 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9768 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9771 /* VEX_LEN_0F5F_P_3 */
9773 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9774 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9777 /* VEX_LEN_0F6E_P_2 */
9779 { "vmovK", { XMScalar, Edq } },
9780 { "vmovK", { XMScalar, Edq } },
9783 /* VEX_LEN_0F7E_P_1 */
9785 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9786 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9789 /* VEX_LEN_0F7E_P_2 */
9791 { "vmovK", { Edq, XMScalar } },
9792 { "vmovK", { Edq, XMScalar } },
9795 /* VEX_LEN_0F90_P_0 */
9797 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9800 /* VEX_LEN_0F90_P_2 */
9802 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9805 /* VEX_LEN_0F91_P_0 */
9807 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9810 /* VEX_LEN_0F91_P_2 */
9812 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9815 /* VEX_LEN_0F92_P_0 */
9817 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9820 /* VEX_LEN_0F92_P_2 */
9822 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9825 /* VEX_LEN_0F92_P_3 */
9827 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9830 /* VEX_LEN_0F93_P_0 */
9832 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9835 /* VEX_LEN_0F93_P_2 */
9837 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9840 /* VEX_LEN_0F93_P_3 */
9842 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9845 /* VEX_LEN_0F98_P_0 */
9847 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9850 /* VEX_LEN_0F98_P_2 */
9852 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9855 /* VEX_LEN_0F99_P_0 */
9857 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9860 /* VEX_LEN_0F99_P_2 */
9862 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9865 /* VEX_LEN_0FAE_R_2_M_0 */
9867 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9870 /* VEX_LEN_0FAE_R_3_M_0 */
9872 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9875 /* VEX_LEN_0FC2_P_1 */
9877 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9878 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9881 /* VEX_LEN_0FC2_P_3 */
9883 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9884 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9887 /* VEX_LEN_0FC4_P_2 */
9889 { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9892 /* VEX_LEN_0FC5_P_2 */
9894 { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9897 /* VEX_LEN_0FD6_P_2 */
9899 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9900 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9903 /* VEX_LEN_0FF7_P_2 */
9905 { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9908 /* VEX_LEN_0F3816_P_2 */
9911 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9914 /* VEX_LEN_0F3819_P_2 */
9917 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9920 /* VEX_LEN_0F381A_P_2_M_0 */
9923 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9926 /* VEX_LEN_0F3836_P_2 */
9929 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9932 /* VEX_LEN_0F3841_P_2 */
9934 { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9937 /* VEX_LEN_0F385A_P_2_M_0 */
9940 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9943 /* VEX_LEN_0F38DB_P_2 */
9945 { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9948 /* VEX_LEN_0F38DC_P_2 */
9950 { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9953 /* VEX_LEN_0F38DD_P_2 */
9955 { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9958 /* VEX_LEN_0F38DE_P_2 */
9960 { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9963 /* VEX_LEN_0F38DF_P_2 */
9965 { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9968 /* VEX_LEN_0F38F2_P_0 */
9970 { "andnS", { Gdq, VexGdq, Edq } },
9973 /* VEX_LEN_0F38F3_R_1_P_0 */
9975 { "blsrS", { VexGdq, Edq } },
9978 /* VEX_LEN_0F38F3_R_2_P_0 */
9980 { "blsmskS", { VexGdq, Edq } },
9983 /* VEX_LEN_0F38F3_R_3_P_0 */
9985 { "blsiS", { VexGdq, Edq } },
9988 /* VEX_LEN_0F38F5_P_0 */
9990 { "bzhiS", { Gdq, Edq, VexGdq } },
9993 /* VEX_LEN_0F38F5_P_1 */
9995 { "pextS", { Gdq, VexGdq, Edq } },
9998 /* VEX_LEN_0F38F5_P_3 */
10000 { "pdepS", { Gdq, VexGdq, Edq } },
10003 /* VEX_LEN_0F38F6_P_3 */
10005 { "mulxS", { Gdq, VexGdq, Edq } },
10008 /* VEX_LEN_0F38F7_P_0 */
10010 { "bextrS", { Gdq, Edq, VexGdq } },
10013 /* VEX_LEN_0F38F7_P_1 */
10015 { "sarxS", { Gdq, Edq, VexGdq } },
10018 /* VEX_LEN_0F38F7_P_2 */
10020 { "shlxS", { Gdq, Edq, VexGdq } },
10023 /* VEX_LEN_0F38F7_P_3 */
10025 { "shrxS", { Gdq, Edq, VexGdq } },
10028 /* VEX_LEN_0F3A00_P_2 */
10031 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10034 /* VEX_LEN_0F3A01_P_2 */
10037 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10040 /* VEX_LEN_0F3A06_P_2 */
10043 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10046 /* VEX_LEN_0F3A0A_P_2 */
10048 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10049 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10052 /* VEX_LEN_0F3A0B_P_2 */
10054 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10055 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10058 /* VEX_LEN_0F3A14_P_2 */
10060 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10063 /* VEX_LEN_0F3A15_P_2 */
10065 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10068 /* VEX_LEN_0F3A16_P_2 */
10070 { "vpextrK", { Edq, XM, Ib } },
10073 /* VEX_LEN_0F3A17_P_2 */
10075 { "vextractps", { Edqd, XM, Ib } },
10078 /* VEX_LEN_0F3A18_P_2 */
10081 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10084 /* VEX_LEN_0F3A19_P_2 */
10087 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10090 /* VEX_LEN_0F3A20_P_2 */
10092 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10095 /* VEX_LEN_0F3A21_P_2 */
10097 { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10100 /* VEX_LEN_0F3A22_P_2 */
10102 { "vpinsrK", { XM, Vex128, Edq, Ib } },
10105 /* VEX_LEN_0F3A30_P_2 */
10107 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10110 /* VEX_LEN_0F3A31_P_2 */
10112 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10115 /* VEX_LEN_0F3A32_P_2 */
10117 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10120 /* VEX_LEN_0F3A33_P_2 */
10122 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10125 /* VEX_LEN_0F3A38_P_2 */
10128 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10131 /* VEX_LEN_0F3A39_P_2 */
10134 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10137 /* VEX_LEN_0F3A41_P_2 */
10139 { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10142 /* VEX_LEN_0F3A44_P_2 */
10144 { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10147 /* VEX_LEN_0F3A46_P_2 */
10150 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10153 /* VEX_LEN_0F3A60_P_2 */
10155 { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10158 /* VEX_LEN_0F3A61_P_2 */
10160 { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10163 /* VEX_LEN_0F3A62_P_2 */
10165 { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10168 /* VEX_LEN_0F3A63_P_2 */
10170 { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10173 /* VEX_LEN_0F3A6A_P_2 */
10175 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10178 /* VEX_LEN_0F3A6B_P_2 */
10180 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10183 /* VEX_LEN_0F3A6E_P_2 */
10185 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10188 /* VEX_LEN_0F3A6F_P_2 */
10190 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10193 /* VEX_LEN_0F3A7A_P_2 */
10195 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10198 /* VEX_LEN_0F3A7B_P_2 */
10200 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10203 /* VEX_LEN_0F3A7E_P_2 */
10205 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10208 /* VEX_LEN_0F3A7F_P_2 */
10210 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10213 /* VEX_LEN_0F3ADF_P_2 */
10215 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10218 /* VEX_LEN_0F3AF0_P_3 */
10220 { "rorxS", { Gdq, Edq, Ib } },
10223 /* VEX_LEN_0FXOP_08_CC */
10225 { "vpcomb", { XM, Vex128, EXx, Ib } },
10228 /* VEX_LEN_0FXOP_08_CD */
10230 { "vpcomw", { XM, Vex128, EXx, Ib } },
10233 /* VEX_LEN_0FXOP_08_CE */
10235 { "vpcomd", { XM, Vex128, EXx, Ib } },
10238 /* VEX_LEN_0FXOP_08_CF */
10240 { "vpcomq", { XM, Vex128, EXx, Ib } },
10243 /* VEX_LEN_0FXOP_08_EC */
10245 { "vpcomub", { XM, Vex128, EXx, Ib } },
10248 /* VEX_LEN_0FXOP_08_ED */
10250 { "vpcomuw", { XM, Vex128, EXx, Ib } },
10253 /* VEX_LEN_0FXOP_08_EE */
10255 { "vpcomud", { XM, Vex128, EXx, Ib } },
10258 /* VEX_LEN_0FXOP_08_EF */
10260 { "vpcomuq", { XM, Vex128, EXx, Ib } },
10263 /* VEX_LEN_0FXOP_09_80 */
10265 { "vfrczps", { XM, EXxmm } },
10266 { "vfrczps", { XM, EXymmq } },
10269 /* VEX_LEN_0FXOP_09_81 */
10271 { "vfrczpd", { XM, EXxmm } },
10272 { "vfrczpd", { XM, EXymmq } },
10276 static const struct dis386 vex_w_table[][2] = {
10278 /* VEX_W_0F10_P_0 */
10279 { "vmovups", { XM, EXx } },
10282 /* VEX_W_0F10_P_1 */
10283 { "vmovss", { XMVexScalar, VexScalar, EXdScalar } },
10286 /* VEX_W_0F10_P_2 */
10287 { "vmovupd", { XM, EXx } },
10290 /* VEX_W_0F10_P_3 */
10291 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } },
10294 /* VEX_W_0F11_P_0 */
10295 { "vmovups", { EXxS, XM } },
10298 /* VEX_W_0F11_P_1 */
10299 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } },
10302 /* VEX_W_0F11_P_2 */
10303 { "vmovupd", { EXxS, XM } },
10306 /* VEX_W_0F11_P_3 */
10307 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } },
10310 /* VEX_W_0F12_P_0_M_0 */
10311 { "vmovlps", { XM, Vex128, EXq } },
10314 /* VEX_W_0F12_P_0_M_1 */
10315 { "vmovhlps", { XM, Vex128, EXq } },
10318 /* VEX_W_0F12_P_1 */
10319 { "vmovsldup", { XM, EXx } },
10322 /* VEX_W_0F12_P_2 */
10323 { "vmovlpd", { XM, Vex128, EXq } },
10326 /* VEX_W_0F12_P_3 */
10327 { "vmovddup", { XM, EXymmq } },
10330 /* VEX_W_0F13_M_0 */
10331 { "vmovlpX", { EXq, XM } },
10335 { "vunpcklpX", { XM, Vex, EXx } },
10339 { "vunpckhpX", { XM, Vex, EXx } },
10342 /* VEX_W_0F16_P_0_M_0 */
10343 { "vmovhps", { XM, Vex128, EXq } },
10346 /* VEX_W_0F16_P_0_M_1 */
10347 { "vmovlhps", { XM, Vex128, EXq } },
10350 /* VEX_W_0F16_P_1 */
10351 { "vmovshdup", { XM, EXx } },
10354 /* VEX_W_0F16_P_2 */
10355 { "vmovhpd", { XM, Vex128, EXq } },
10358 /* VEX_W_0F17_M_0 */
10359 { "vmovhpX", { EXq, XM } },
10363 { "vmovapX", { XM, EXx } },
10367 { "vmovapX", { EXxS, XM } },
10370 /* VEX_W_0F2B_M_0 */
10371 { "vmovntpX", { Mx, XM } },
10374 /* VEX_W_0F2E_P_0 */
10375 { "vucomiss", { XMScalar, EXdScalar } },
10378 /* VEX_W_0F2E_P_2 */
10379 { "vucomisd", { XMScalar, EXqScalar } },
10382 /* VEX_W_0F2F_P_0 */
10383 { "vcomiss", { XMScalar, EXdScalar } },
10386 /* VEX_W_0F2F_P_2 */
10387 { "vcomisd", { XMScalar, EXqScalar } },
10390 /* VEX_W_0F41_P_0_LEN_1 */
10391 { "kandw", { MaskG, MaskVex, MaskR } },
10392 { "kandq", { MaskG, MaskVex, MaskR } },
10395 /* VEX_W_0F41_P_2_LEN_1 */
10396 { "kandb", { MaskG, MaskVex, MaskR } },
10397 { "kandd", { MaskG, MaskVex, MaskR } },
10400 /* VEX_W_0F42_P_0_LEN_1 */
10401 { "kandnw", { MaskG, MaskVex, MaskR } },
10402 { "kandnq", { MaskG, MaskVex, MaskR } },
10405 /* VEX_W_0F42_P_2_LEN_1 */
10406 { "kandnb", { MaskG, MaskVex, MaskR } },
10407 { "kandnd", { MaskG, MaskVex, MaskR } },
10410 /* VEX_W_0F44_P_0_LEN_0 */
10411 { "knotw", { MaskG, MaskR } },
10412 { "knotq", { MaskG, MaskR } },
10415 /* VEX_W_0F44_P_2_LEN_0 */
10416 { "knotb", { MaskG, MaskR } },
10417 { "knotd", { MaskG, MaskR } },
10420 /* VEX_W_0F45_P_0_LEN_1 */
10421 { "korw", { MaskG, MaskVex, MaskR } },
10422 { "korq", { MaskG, MaskVex, MaskR } },
10425 /* VEX_W_0F45_P_2_LEN_1 */
10426 { "korb", { MaskG, MaskVex, MaskR } },
10427 { "kord", { MaskG, MaskVex, MaskR } },
10430 /* VEX_W_0F46_P_0_LEN_1 */
10431 { "kxnorw", { MaskG, MaskVex, MaskR } },
10432 { "kxnorq", { MaskG, MaskVex, MaskR } },
10435 /* VEX_W_0F46_P_2_LEN_1 */
10436 { "kxnorb", { MaskG, MaskVex, MaskR } },
10437 { "kxnord", { MaskG, MaskVex, MaskR } },
10440 /* VEX_W_0F47_P_0_LEN_1 */
10441 { "kxorw", { MaskG, MaskVex, MaskR } },
10442 { "kxorq", { MaskG, MaskVex, MaskR } },
10445 /* VEX_W_0F47_P_2_LEN_1 */
10446 { "kxorb", { MaskG, MaskVex, MaskR } },
10447 { "kxord", { MaskG, MaskVex, MaskR } },
10450 /* VEX_W_0F4A_P_0_LEN_1 */
10451 { "kaddw", { MaskG, MaskVex, MaskR } },
10452 { "kaddq", { MaskG, MaskVex, MaskR } },
10455 /* VEX_W_0F4A_P_2_LEN_1 */
10456 { "kaddb", { MaskG, MaskVex, MaskR } },
10457 { "kaddd", { MaskG, MaskVex, MaskR } },
10460 /* VEX_W_0F4B_P_0_LEN_1 */
10461 { "kunpckwd", { MaskG, MaskVex, MaskR } },
10462 { "kunpckdq", { MaskG, MaskVex, MaskR } },
10465 /* VEX_W_0F4B_P_2_LEN_1 */
10466 { "kunpckbw", { MaskG, MaskVex, MaskR } },
10469 /* VEX_W_0F50_M_0 */
10470 { "vmovmskpX", { Gdq, XS } },
10473 /* VEX_W_0F51_P_0 */
10474 { "vsqrtps", { XM, EXx } },
10477 /* VEX_W_0F51_P_1 */
10478 { "vsqrtss", { XMScalar, VexScalar, EXdScalar } },
10481 /* VEX_W_0F51_P_2 */
10482 { "vsqrtpd", { XM, EXx } },
10485 /* VEX_W_0F51_P_3 */
10486 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar } },
10489 /* VEX_W_0F52_P_0 */
10490 { "vrsqrtps", { XM, EXx } },
10493 /* VEX_W_0F52_P_1 */
10494 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar } },
10497 /* VEX_W_0F53_P_0 */
10498 { "vrcpps", { XM, EXx } },
10501 /* VEX_W_0F53_P_1 */
10502 { "vrcpss", { XMScalar, VexScalar, EXdScalar } },
10505 /* VEX_W_0F58_P_0 */
10506 { "vaddps", { XM, Vex, EXx } },
10509 /* VEX_W_0F58_P_1 */
10510 { "vaddss", { XMScalar, VexScalar, EXdScalar } },
10513 /* VEX_W_0F58_P_2 */
10514 { "vaddpd", { XM, Vex, EXx } },
10517 /* VEX_W_0F58_P_3 */
10518 { "vaddsd", { XMScalar, VexScalar, EXqScalar } },
10521 /* VEX_W_0F59_P_0 */
10522 { "vmulps", { XM, Vex, EXx } },
10525 /* VEX_W_0F59_P_1 */
10526 { "vmulss", { XMScalar, VexScalar, EXdScalar } },
10529 /* VEX_W_0F59_P_2 */
10530 { "vmulpd", { XM, Vex, EXx } },
10533 /* VEX_W_0F59_P_3 */
10534 { "vmulsd", { XMScalar, VexScalar, EXqScalar } },
10537 /* VEX_W_0F5A_P_0 */
10538 { "vcvtps2pd", { XM, EXxmmq } },
10541 /* VEX_W_0F5A_P_1 */
10542 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar } },
10545 /* VEX_W_0F5A_P_3 */
10546 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar } },
10549 /* VEX_W_0F5B_P_0 */
10550 { "vcvtdq2ps", { XM, EXx } },
10553 /* VEX_W_0F5B_P_1 */
10554 { "vcvttps2dq", { XM, EXx } },
10557 /* VEX_W_0F5B_P_2 */
10558 { "vcvtps2dq", { XM, EXx } },
10561 /* VEX_W_0F5C_P_0 */
10562 { "vsubps", { XM, Vex, EXx } },
10565 /* VEX_W_0F5C_P_1 */
10566 { "vsubss", { XMScalar, VexScalar, EXdScalar } },
10569 /* VEX_W_0F5C_P_2 */
10570 { "vsubpd", { XM, Vex, EXx } },
10573 /* VEX_W_0F5C_P_3 */
10574 { "vsubsd", { XMScalar, VexScalar, EXqScalar } },
10577 /* VEX_W_0F5D_P_0 */
10578 { "vminps", { XM, Vex, EXx } },
10581 /* VEX_W_0F5D_P_1 */
10582 { "vminss", { XMScalar, VexScalar, EXdScalar } },
10585 /* VEX_W_0F5D_P_2 */
10586 { "vminpd", { XM, Vex, EXx } },
10589 /* VEX_W_0F5D_P_3 */
10590 { "vminsd", { XMScalar, VexScalar, EXqScalar } },
10593 /* VEX_W_0F5E_P_0 */
10594 { "vdivps", { XM, Vex, EXx } },
10597 /* VEX_W_0F5E_P_1 */
10598 { "vdivss", { XMScalar, VexScalar, EXdScalar } },
10601 /* VEX_W_0F5E_P_2 */
10602 { "vdivpd", { XM, Vex, EXx } },
10605 /* VEX_W_0F5E_P_3 */
10606 { "vdivsd", { XMScalar, VexScalar, EXqScalar } },
10609 /* VEX_W_0F5F_P_0 */
10610 { "vmaxps", { XM, Vex, EXx } },
10613 /* VEX_W_0F5F_P_1 */
10614 { "vmaxss", { XMScalar, VexScalar, EXdScalar } },
10617 /* VEX_W_0F5F_P_2 */
10618 { "vmaxpd", { XM, Vex, EXx } },
10621 /* VEX_W_0F5F_P_3 */
10622 { "vmaxsd", { XMScalar, VexScalar, EXqScalar } },
10625 /* VEX_W_0F60_P_2 */
10626 { "vpunpcklbw", { XM, Vex, EXx } },
10629 /* VEX_W_0F61_P_2 */
10630 { "vpunpcklwd", { XM, Vex, EXx } },
10633 /* VEX_W_0F62_P_2 */
10634 { "vpunpckldq", { XM, Vex, EXx } },
10637 /* VEX_W_0F63_P_2 */
10638 { "vpacksswb", { XM, Vex, EXx } },
10641 /* VEX_W_0F64_P_2 */
10642 { "vpcmpgtb", { XM, Vex, EXx } },
10645 /* VEX_W_0F65_P_2 */
10646 { "vpcmpgtw", { XM, Vex, EXx } },
10649 /* VEX_W_0F66_P_2 */
10650 { "vpcmpgtd", { XM, Vex, EXx } },
10653 /* VEX_W_0F67_P_2 */
10654 { "vpackuswb", { XM, Vex, EXx } },
10657 /* VEX_W_0F68_P_2 */
10658 { "vpunpckhbw", { XM, Vex, EXx } },
10661 /* VEX_W_0F69_P_2 */
10662 { "vpunpckhwd", { XM, Vex, EXx } },
10665 /* VEX_W_0F6A_P_2 */
10666 { "vpunpckhdq", { XM, Vex, EXx } },
10669 /* VEX_W_0F6B_P_2 */
10670 { "vpackssdw", { XM, Vex, EXx } },
10673 /* VEX_W_0F6C_P_2 */
10674 { "vpunpcklqdq", { XM, Vex, EXx } },
10677 /* VEX_W_0F6D_P_2 */
10678 { "vpunpckhqdq", { XM, Vex, EXx } },
10681 /* VEX_W_0F6F_P_1 */
10682 { "vmovdqu", { XM, EXx } },
10685 /* VEX_W_0F6F_P_2 */
10686 { "vmovdqa", { XM, EXx } },
10689 /* VEX_W_0F70_P_1 */
10690 { "vpshufhw", { XM, EXx, Ib } },
10693 /* VEX_W_0F70_P_2 */
10694 { "vpshufd", { XM, EXx, Ib } },
10697 /* VEX_W_0F70_P_3 */
10698 { "vpshuflw", { XM, EXx, Ib } },
10701 /* VEX_W_0F71_R_2_P_2 */
10702 { "vpsrlw", { Vex, XS, Ib } },
10705 /* VEX_W_0F71_R_4_P_2 */
10706 { "vpsraw", { Vex, XS, Ib } },
10709 /* VEX_W_0F71_R_6_P_2 */
10710 { "vpsllw", { Vex, XS, Ib } },
10713 /* VEX_W_0F72_R_2_P_2 */
10714 { "vpsrld", { Vex, XS, Ib } },
10717 /* VEX_W_0F72_R_4_P_2 */
10718 { "vpsrad", { Vex, XS, Ib } },
10721 /* VEX_W_0F72_R_6_P_2 */
10722 { "vpslld", { Vex, XS, Ib } },
10725 /* VEX_W_0F73_R_2_P_2 */
10726 { "vpsrlq", { Vex, XS, Ib } },
10729 /* VEX_W_0F73_R_3_P_2 */
10730 { "vpsrldq", { Vex, XS, Ib } },
10733 /* VEX_W_0F73_R_6_P_2 */
10734 { "vpsllq", { Vex, XS, Ib } },
10737 /* VEX_W_0F73_R_7_P_2 */
10738 { "vpslldq", { Vex, XS, Ib } },
10741 /* VEX_W_0F74_P_2 */
10742 { "vpcmpeqb", { XM, Vex, EXx } },
10745 /* VEX_W_0F75_P_2 */
10746 { "vpcmpeqw", { XM, Vex, EXx } },
10749 /* VEX_W_0F76_P_2 */
10750 { "vpcmpeqd", { XM, Vex, EXx } },
10753 /* VEX_W_0F77_P_0 */
10757 /* VEX_W_0F7C_P_2 */
10758 { "vhaddpd", { XM, Vex, EXx } },
10761 /* VEX_W_0F7C_P_3 */
10762 { "vhaddps", { XM, Vex, EXx } },
10765 /* VEX_W_0F7D_P_2 */
10766 { "vhsubpd", { XM, Vex, EXx } },
10769 /* VEX_W_0F7D_P_3 */
10770 { "vhsubps", { XM, Vex, EXx } },
10773 /* VEX_W_0F7E_P_1 */
10774 { "vmovq", { XMScalar, EXqScalar } },
10777 /* VEX_W_0F7F_P_1 */
10778 { "vmovdqu", { EXxS, XM } },
10781 /* VEX_W_0F7F_P_2 */
10782 { "vmovdqa", { EXxS, XM } },
10785 /* VEX_W_0F90_P_0_LEN_0 */
10786 { "kmovw", { MaskG, MaskE } },
10787 { "kmovq", { MaskG, MaskE } },
10790 /* VEX_W_0F90_P_2_LEN_0 */
10791 { "kmovb", { MaskG, MaskBDE } },
10792 { "kmovd", { MaskG, MaskBDE } },
10795 /* VEX_W_0F91_P_0_LEN_0 */
10796 { "kmovw", { Ew, MaskG } },
10797 { "kmovq", { Eq, MaskG } },
10800 /* VEX_W_0F91_P_2_LEN_0 */
10801 { "kmovb", { Eb, MaskG } },
10802 { "kmovd", { Ed, MaskG } },
10805 /* VEX_W_0F92_P_0_LEN_0 */
10806 { "kmovw", { MaskG, Rdq } },
10809 /* VEX_W_0F92_P_2_LEN_0 */
10810 { "kmovb", { MaskG, Rdq } },
10813 /* VEX_W_0F92_P_3_LEN_0 */
10814 { "kmovd", { MaskG, Rdq } },
10815 { "kmovq", { MaskG, Rdq } },
10818 /* VEX_W_0F93_P_0_LEN_0 */
10819 { "kmovw", { Gdq, MaskR } },
10822 /* VEX_W_0F93_P_2_LEN_0 */
10823 { "kmovb", { Gdq, MaskR } },
10826 /* VEX_W_0F93_P_3_LEN_0 */
10827 { "kmovd", { Gdq, MaskR } },
10828 { "kmovq", { Gdq, MaskR } },
10831 /* VEX_W_0F98_P_0_LEN_0 */
10832 { "kortestw", { MaskG, MaskR } },
10833 { "kortestq", { MaskG, MaskR } },
10836 /* VEX_W_0F98_P_2_LEN_0 */
10837 { "kortestb", { MaskG, MaskR } },
10838 { "kortestd", { MaskG, MaskR } },
10841 /* VEX_W_0F99_P_0_LEN_0 */
10842 { "ktestw", { MaskG, MaskR } },
10843 { "ktestq", { MaskG, MaskR } },
10846 /* VEX_W_0F99_P_2_LEN_0 */
10847 { "ktestb", { MaskG, MaskR } },
10848 { "ktestd", { MaskG, MaskR } },
10851 /* VEX_W_0FAE_R_2_M_0 */
10852 { "vldmxcsr", { Md } },
10855 /* VEX_W_0FAE_R_3_M_0 */
10856 { "vstmxcsr", { Md } },
10859 /* VEX_W_0FC2_P_0 */
10860 { "vcmpps", { XM, Vex, EXx, VCMP } },
10863 /* VEX_W_0FC2_P_1 */
10864 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP } },
10867 /* VEX_W_0FC2_P_2 */
10868 { "vcmppd", { XM, Vex, EXx, VCMP } },
10871 /* VEX_W_0FC2_P_3 */
10872 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP } },
10875 /* VEX_W_0FC4_P_2 */
10876 { "vpinsrw", { XM, Vex128, Edqw, Ib } },
10879 /* VEX_W_0FC5_P_2 */
10880 { "vpextrw", { Gdq, XS, Ib } },
10883 /* VEX_W_0FD0_P_2 */
10884 { "vaddsubpd", { XM, Vex, EXx } },
10887 /* VEX_W_0FD0_P_3 */
10888 { "vaddsubps", { XM, Vex, EXx } },
10891 /* VEX_W_0FD1_P_2 */
10892 { "vpsrlw", { XM, Vex, EXxmm } },
10895 /* VEX_W_0FD2_P_2 */
10896 { "vpsrld", { XM, Vex, EXxmm } },
10899 /* VEX_W_0FD3_P_2 */
10900 { "vpsrlq", { XM, Vex, EXxmm } },
10903 /* VEX_W_0FD4_P_2 */
10904 { "vpaddq", { XM, Vex, EXx } },
10907 /* VEX_W_0FD5_P_2 */
10908 { "vpmullw", { XM, Vex, EXx } },
10911 /* VEX_W_0FD6_P_2 */
10912 { "vmovq", { EXqScalarS, XMScalar } },
10915 /* VEX_W_0FD7_P_2_M_1 */
10916 { "vpmovmskb", { Gdq, XS } },
10919 /* VEX_W_0FD8_P_2 */
10920 { "vpsubusb", { XM, Vex, EXx } },
10923 /* VEX_W_0FD9_P_2 */
10924 { "vpsubusw", { XM, Vex, EXx } },
10927 /* VEX_W_0FDA_P_2 */
10928 { "vpminub", { XM, Vex, EXx } },
10931 /* VEX_W_0FDB_P_2 */
10932 { "vpand", { XM, Vex, EXx } },
10935 /* VEX_W_0FDC_P_2 */
10936 { "vpaddusb", { XM, Vex, EXx } },
10939 /* VEX_W_0FDD_P_2 */
10940 { "vpaddusw", { XM, Vex, EXx } },
10943 /* VEX_W_0FDE_P_2 */
10944 { "vpmaxub", { XM, Vex, EXx } },
10947 /* VEX_W_0FDF_P_2 */
10948 { "vpandn", { XM, Vex, EXx } },
10951 /* VEX_W_0FE0_P_2 */
10952 { "vpavgb", { XM, Vex, EXx } },
10955 /* VEX_W_0FE1_P_2 */
10956 { "vpsraw", { XM, Vex, EXxmm } },
10959 /* VEX_W_0FE2_P_2 */
10960 { "vpsrad", { XM, Vex, EXxmm } },
10963 /* VEX_W_0FE3_P_2 */
10964 { "vpavgw", { XM, Vex, EXx } },
10967 /* VEX_W_0FE4_P_2 */
10968 { "vpmulhuw", { XM, Vex, EXx } },
10971 /* VEX_W_0FE5_P_2 */
10972 { "vpmulhw", { XM, Vex, EXx } },
10975 /* VEX_W_0FE6_P_1 */
10976 { "vcvtdq2pd", { XM, EXxmmq } },
10979 /* VEX_W_0FE6_P_2 */
10980 { "vcvttpd2dq%XY", { XMM, EXx } },
10983 /* VEX_W_0FE6_P_3 */
10984 { "vcvtpd2dq%XY", { XMM, EXx } },
10987 /* VEX_W_0FE7_P_2_M_0 */
10988 { "vmovntdq", { Mx, XM } },
10991 /* VEX_W_0FE8_P_2 */
10992 { "vpsubsb", { XM, Vex, EXx } },
10995 /* VEX_W_0FE9_P_2 */
10996 { "vpsubsw", { XM, Vex, EXx } },
10999 /* VEX_W_0FEA_P_2 */
11000 { "vpminsw", { XM, Vex, EXx } },
11003 /* VEX_W_0FEB_P_2 */
11004 { "vpor", { XM, Vex, EXx } },
11007 /* VEX_W_0FEC_P_2 */
11008 { "vpaddsb", { XM, Vex, EXx } },
11011 /* VEX_W_0FED_P_2 */
11012 { "vpaddsw", { XM, Vex, EXx } },
11015 /* VEX_W_0FEE_P_2 */
11016 { "vpmaxsw", { XM, Vex, EXx } },
11019 /* VEX_W_0FEF_P_2 */
11020 { "vpxor", { XM, Vex, EXx } },
11023 /* VEX_W_0FF0_P_3_M_0 */
11024 { "vlddqu", { XM, M } },
11027 /* VEX_W_0FF1_P_2 */
11028 { "vpsllw", { XM, Vex, EXxmm } },
11031 /* VEX_W_0FF2_P_2 */
11032 { "vpslld", { XM, Vex, EXxmm } },
11035 /* VEX_W_0FF3_P_2 */
11036 { "vpsllq", { XM, Vex, EXxmm } },
11039 /* VEX_W_0FF4_P_2 */
11040 { "vpmuludq", { XM, Vex, EXx } },
11043 /* VEX_W_0FF5_P_2 */
11044 { "vpmaddwd", { XM, Vex, EXx } },
11047 /* VEX_W_0FF6_P_2 */
11048 { "vpsadbw", { XM, Vex, EXx } },
11051 /* VEX_W_0FF7_P_2 */
11052 { "vmaskmovdqu", { XM, XS } },
11055 /* VEX_W_0FF8_P_2 */
11056 { "vpsubb", { XM, Vex, EXx } },
11059 /* VEX_W_0FF9_P_2 */
11060 { "vpsubw", { XM, Vex, EXx } },
11063 /* VEX_W_0FFA_P_2 */
11064 { "vpsubd", { XM, Vex, EXx } },
11067 /* VEX_W_0FFB_P_2 */
11068 { "vpsubq", { XM, Vex, EXx } },
11071 /* VEX_W_0FFC_P_2 */
11072 { "vpaddb", { XM, Vex, EXx } },
11075 /* VEX_W_0FFD_P_2 */
11076 { "vpaddw", { XM, Vex, EXx } },
11079 /* VEX_W_0FFE_P_2 */
11080 { "vpaddd", { XM, Vex, EXx } },
11083 /* VEX_W_0F3800_P_2 */
11084 { "vpshufb", { XM, Vex, EXx } },
11087 /* VEX_W_0F3801_P_2 */
11088 { "vphaddw", { XM, Vex, EXx } },
11091 /* VEX_W_0F3802_P_2 */
11092 { "vphaddd", { XM, Vex, EXx } },
11095 /* VEX_W_0F3803_P_2 */
11096 { "vphaddsw", { XM, Vex, EXx } },
11099 /* VEX_W_0F3804_P_2 */
11100 { "vpmaddubsw", { XM, Vex, EXx } },
11103 /* VEX_W_0F3805_P_2 */
11104 { "vphsubw", { XM, Vex, EXx } },
11107 /* VEX_W_0F3806_P_2 */
11108 { "vphsubd", { XM, Vex, EXx } },
11111 /* VEX_W_0F3807_P_2 */
11112 { "vphsubsw", { XM, Vex, EXx } },
11115 /* VEX_W_0F3808_P_2 */
11116 { "vpsignb", { XM, Vex, EXx } },
11119 /* VEX_W_0F3809_P_2 */
11120 { "vpsignw", { XM, Vex, EXx } },
11123 /* VEX_W_0F380A_P_2 */
11124 { "vpsignd", { XM, Vex, EXx } },
11127 /* VEX_W_0F380B_P_2 */
11128 { "vpmulhrsw", { XM, Vex, EXx } },
11131 /* VEX_W_0F380C_P_2 */
11132 { "vpermilps", { XM, Vex, EXx } },
11135 /* VEX_W_0F380D_P_2 */
11136 { "vpermilpd", { XM, Vex, EXx } },
11139 /* VEX_W_0F380E_P_2 */
11140 { "vtestps", { XM, EXx } },
11143 /* VEX_W_0F380F_P_2 */
11144 { "vtestpd", { XM, EXx } },
11147 /* VEX_W_0F3816_P_2 */
11148 { "vpermps", { XM, Vex, EXx } },
11151 /* VEX_W_0F3817_P_2 */
11152 { "vptest", { XM, EXx } },
11155 /* VEX_W_0F3818_P_2 */
11156 { "vbroadcastss", { XM, EXxmm_md } },
11159 /* VEX_W_0F3819_P_2 */
11160 { "vbroadcastsd", { XM, EXxmm_mq } },
11163 /* VEX_W_0F381A_P_2_M_0 */
11164 { "vbroadcastf128", { XM, Mxmm } },
11167 /* VEX_W_0F381C_P_2 */
11168 { "vpabsb", { XM, EXx } },
11171 /* VEX_W_0F381D_P_2 */
11172 { "vpabsw", { XM, EXx } },
11175 /* VEX_W_0F381E_P_2 */
11176 { "vpabsd", { XM, EXx } },
11179 /* VEX_W_0F3820_P_2 */
11180 { "vpmovsxbw", { XM, EXxmmq } },
11183 /* VEX_W_0F3821_P_2 */
11184 { "vpmovsxbd", { XM, EXxmmqd } },
11187 /* VEX_W_0F3822_P_2 */
11188 { "vpmovsxbq", { XM, EXxmmdw } },
11191 /* VEX_W_0F3823_P_2 */
11192 { "vpmovsxwd", { XM, EXxmmq } },
11195 /* VEX_W_0F3824_P_2 */
11196 { "vpmovsxwq", { XM, EXxmmqd } },
11199 /* VEX_W_0F3825_P_2 */
11200 { "vpmovsxdq", { XM, EXxmmq } },
11203 /* VEX_W_0F3828_P_2 */
11204 { "vpmuldq", { XM, Vex, EXx } },
11207 /* VEX_W_0F3829_P_2 */
11208 { "vpcmpeqq", { XM, Vex, EXx } },
11211 /* VEX_W_0F382A_P_2_M_0 */
11212 { "vmovntdqa", { XM, Mx } },
11215 /* VEX_W_0F382B_P_2 */
11216 { "vpackusdw", { XM, Vex, EXx } },
11219 /* VEX_W_0F382C_P_2_M_0 */
11220 { "vmaskmovps", { XM, Vex, Mx } },
11223 /* VEX_W_0F382D_P_2_M_0 */
11224 { "vmaskmovpd", { XM, Vex, Mx } },
11227 /* VEX_W_0F382E_P_2_M_0 */
11228 { "vmaskmovps", { Mx, Vex, XM } },
11231 /* VEX_W_0F382F_P_2_M_0 */
11232 { "vmaskmovpd", { Mx, Vex, XM } },
11235 /* VEX_W_0F3830_P_2 */
11236 { "vpmovzxbw", { XM, EXxmmq } },
11239 /* VEX_W_0F3831_P_2 */
11240 { "vpmovzxbd", { XM, EXxmmqd } },
11243 /* VEX_W_0F3832_P_2 */
11244 { "vpmovzxbq", { XM, EXxmmdw } },
11247 /* VEX_W_0F3833_P_2 */
11248 { "vpmovzxwd", { XM, EXxmmq } },
11251 /* VEX_W_0F3834_P_2 */
11252 { "vpmovzxwq", { XM, EXxmmqd } },
11255 /* VEX_W_0F3835_P_2 */
11256 { "vpmovzxdq", { XM, EXxmmq } },
11259 /* VEX_W_0F3836_P_2 */
11260 { "vpermd", { XM, Vex, EXx } },
11263 /* VEX_W_0F3837_P_2 */
11264 { "vpcmpgtq", { XM, Vex, EXx } },
11267 /* VEX_W_0F3838_P_2 */
11268 { "vpminsb", { XM, Vex, EXx } },
11271 /* VEX_W_0F3839_P_2 */
11272 { "vpminsd", { XM, Vex, EXx } },
11275 /* VEX_W_0F383A_P_2 */
11276 { "vpminuw", { XM, Vex, EXx } },
11279 /* VEX_W_0F383B_P_2 */
11280 { "vpminud", { XM, Vex, EXx } },
11283 /* VEX_W_0F383C_P_2 */
11284 { "vpmaxsb", { XM, Vex, EXx } },
11287 /* VEX_W_0F383D_P_2 */
11288 { "vpmaxsd", { XM, Vex, EXx } },
11291 /* VEX_W_0F383E_P_2 */
11292 { "vpmaxuw", { XM, Vex, EXx } },
11295 /* VEX_W_0F383F_P_2 */
11296 { "vpmaxud", { XM, Vex, EXx } },
11299 /* VEX_W_0F3840_P_2 */
11300 { "vpmulld", { XM, Vex, EXx } },
11303 /* VEX_W_0F3841_P_2 */
11304 { "vphminposuw", { XM, EXx } },
11307 /* VEX_W_0F3846_P_2 */
11308 { "vpsravd", { XM, Vex, EXx } },
11311 /* VEX_W_0F3858_P_2 */
11312 { "vpbroadcastd", { XM, EXxmm_md } },
11315 /* VEX_W_0F3859_P_2 */
11316 { "vpbroadcastq", { XM, EXxmm_mq } },
11319 /* VEX_W_0F385A_P_2_M_0 */
11320 { "vbroadcasti128", { XM, Mxmm } },
11323 /* VEX_W_0F3878_P_2 */
11324 { "vpbroadcastb", { XM, EXxmm_mb } },
11327 /* VEX_W_0F3879_P_2 */
11328 { "vpbroadcastw", { XM, EXxmm_mw } },
11331 /* VEX_W_0F38DB_P_2 */
11332 { "vaesimc", { XM, EXx } },
11335 /* VEX_W_0F38DC_P_2 */
11336 { "vaesenc", { XM, Vex128, EXx } },
11339 /* VEX_W_0F38DD_P_2 */
11340 { "vaesenclast", { XM, Vex128, EXx } },
11343 /* VEX_W_0F38DE_P_2 */
11344 { "vaesdec", { XM, Vex128, EXx } },
11347 /* VEX_W_0F38DF_P_2 */
11348 { "vaesdeclast", { XM, Vex128, EXx } },
11351 /* VEX_W_0F3A00_P_2 */
11353 { "vpermq", { XM, EXx, Ib } },
11356 /* VEX_W_0F3A01_P_2 */
11358 { "vpermpd", { XM, EXx, Ib } },
11361 /* VEX_W_0F3A02_P_2 */
11362 { "vpblendd", { XM, Vex, EXx, Ib } },
11365 /* VEX_W_0F3A04_P_2 */
11366 { "vpermilps", { XM, EXx, Ib } },
11369 /* VEX_W_0F3A05_P_2 */
11370 { "vpermilpd", { XM, EXx, Ib } },
11373 /* VEX_W_0F3A06_P_2 */
11374 { "vperm2f128", { XM, Vex256, EXx, Ib } },
11377 /* VEX_W_0F3A08_P_2 */
11378 { "vroundps", { XM, EXx, Ib } },
11381 /* VEX_W_0F3A09_P_2 */
11382 { "vroundpd", { XM, EXx, Ib } },
11385 /* VEX_W_0F3A0A_P_2 */
11386 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib } },
11389 /* VEX_W_0F3A0B_P_2 */
11390 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib } },
11393 /* VEX_W_0F3A0C_P_2 */
11394 { "vblendps", { XM, Vex, EXx, Ib } },
11397 /* VEX_W_0F3A0D_P_2 */
11398 { "vblendpd", { XM, Vex, EXx, Ib } },
11401 /* VEX_W_0F3A0E_P_2 */
11402 { "vpblendw", { XM, Vex, EXx, Ib } },
11405 /* VEX_W_0F3A0F_P_2 */
11406 { "vpalignr", { XM, Vex, EXx, Ib } },
11409 /* VEX_W_0F3A14_P_2 */
11410 { "vpextrb", { Edqb, XM, Ib } },
11413 /* VEX_W_0F3A15_P_2 */
11414 { "vpextrw", { Edqw, XM, Ib } },
11417 /* VEX_W_0F3A18_P_2 */
11418 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },
11421 /* VEX_W_0F3A19_P_2 */
11422 { "vextractf128", { EXxmm, XM, Ib } },
11425 /* VEX_W_0F3A20_P_2 */
11426 { "vpinsrb", { XM, Vex128, Edqb, Ib } },
11429 /* VEX_W_0F3A21_P_2 */
11430 { "vinsertps", { XM, Vex128, EXd, Ib } },
11433 /* VEX_W_0F3A30_P_2_LEN_0 */
11434 { "kshiftrb", { MaskG, MaskR, Ib } },
11435 { "kshiftrw", { MaskG, MaskR, Ib } },
11438 /* VEX_W_0F3A31_P_2_LEN_0 */
11439 { "kshiftrd", { MaskG, MaskR, Ib } },
11440 { "kshiftrq", { MaskG, MaskR, Ib } },
11443 /* VEX_W_0F3A32_P_2_LEN_0 */
11444 { "kshiftlb", { MaskG, MaskR, Ib } },
11445 { "kshiftlw", { MaskG, MaskR, Ib } },
11448 /* VEX_W_0F3A33_P_2_LEN_0 */
11449 { "kshiftld", { MaskG, MaskR, Ib } },
11450 { "kshiftlq", { MaskG, MaskR, Ib } },
11453 /* VEX_W_0F3A38_P_2 */
11454 { "vinserti128", { XM, Vex256, EXxmm, Ib } },
11457 /* VEX_W_0F3A39_P_2 */
11458 { "vextracti128", { EXxmm, XM, Ib } },
11461 /* VEX_W_0F3A40_P_2 */
11462 { "vdpps", { XM, Vex, EXx, Ib } },
11465 /* VEX_W_0F3A41_P_2 */
11466 { "vdppd", { XM, Vex128, EXx, Ib } },
11469 /* VEX_W_0F3A42_P_2 */
11470 { "vmpsadbw", { XM, Vex, EXx, Ib } },
11473 /* VEX_W_0F3A44_P_2 */
11474 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } },
11477 /* VEX_W_0F3A46_P_2 */
11478 { "vperm2i128", { XM, Vex256, EXx, Ib } },
11481 /* VEX_W_0F3A48_P_2 */
11482 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11483 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11486 /* VEX_W_0F3A49_P_2 */
11487 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11488 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11491 /* VEX_W_0F3A4A_P_2 */
11492 { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
11495 /* VEX_W_0F3A4B_P_2 */
11496 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
11499 /* VEX_W_0F3A4C_P_2 */
11500 { "vpblendvb", { XM, Vex, EXx, XMVexI4 } },
11503 /* VEX_W_0F3A60_P_2 */
11504 { "vpcmpestrm", { XM, EXx, Ib } },
11507 /* VEX_W_0F3A61_P_2 */
11508 { "vpcmpestri", { XM, EXx, Ib } },
11511 /* VEX_W_0F3A62_P_2 */
11512 { "vpcmpistrm", { XM, EXx, Ib } },
11515 /* VEX_W_0F3A63_P_2 */
11516 { "vpcmpistri", { XM, EXx, Ib } },
11519 /* VEX_W_0F3ADF_P_2 */
11520 { "vaeskeygenassist", { XM, EXx, Ib } },
11522 #define NEED_VEX_W_TABLE
11523 #include "i386-dis-evex.h"
11524 #undef NEED_VEX_W_TABLE
11527 static const struct dis386 mod_table[][2] = {
11530 { "leaS", { Gv, M } },
11535 { RM_TABLE (RM_C6_REG_7) },
11540 { RM_TABLE (RM_C7_REG_7) },
11544 { "Jcall{T|}", { indirEp } },
11548 { "Jjmp{T|}", { indirEp } },
11551 /* MOD_0F01_REG_0 */
11552 { X86_64_TABLE (X86_64_0F01_REG_0) },
11553 { RM_TABLE (RM_0F01_REG_0) },
11556 /* MOD_0F01_REG_1 */
11557 { X86_64_TABLE (X86_64_0F01_REG_1) },
11558 { RM_TABLE (RM_0F01_REG_1) },
11561 /* MOD_0F01_REG_2 */
11562 { X86_64_TABLE (X86_64_0F01_REG_2) },
11563 { RM_TABLE (RM_0F01_REG_2) },
11566 /* MOD_0F01_REG_3 */
11567 { X86_64_TABLE (X86_64_0F01_REG_3) },
11568 { RM_TABLE (RM_0F01_REG_3) },
11571 /* MOD_0F01_REG_7 */
11572 { "invlpg", { Mb } },
11573 { RM_TABLE (RM_0F01_REG_7) },
11576 /* MOD_0F12_PREFIX_0 */
11577 { "movlps", { XM, EXq } },
11578 { "movhlps", { XM, EXq } },
11582 { "movlpX", { EXq, XM } },
11585 /* MOD_0F16_PREFIX_0 */
11586 { "movhps", { XM, EXq } },
11587 { "movlhps", { XM, EXq } },
11591 { "movhpX", { EXq, XM } },
11594 /* MOD_0F18_REG_0 */
11595 { "prefetchnta", { Mb } },
11598 /* MOD_0F18_REG_1 */
11599 { "prefetcht0", { Mb } },
11602 /* MOD_0F18_REG_2 */
11603 { "prefetcht1", { Mb } },
11606 /* MOD_0F18_REG_3 */
11607 { "prefetcht2", { Mb } },
11610 /* MOD_0F18_REG_4 */
11611 { "nop/reserved", { Mb } },
11614 /* MOD_0F18_REG_5 */
11615 { "nop/reserved", { Mb } },
11618 /* MOD_0F18_REG_6 */
11619 { "nop/reserved", { Mb } },
11622 /* MOD_0F18_REG_7 */
11623 { "nop/reserved", { Mb } },
11626 /* MOD_0F1A_PREFIX_0 */
11627 { "bndldx", { Gbnd, Ev_bnd } },
11628 { "nopQ", { Ev } },
11631 /* MOD_0F1B_PREFIX_0 */
11632 { "bndstx", { Ev_bnd, Gbnd } },
11633 { "nopQ", { Ev } },
11636 /* MOD_0F1B_PREFIX_1 */
11637 { "bndmk", { Gbnd, Ev_bnd } },
11638 { "nopQ", { Ev } },
11643 { "movL", { Rd, Td } },
11648 { "movL", { Td, Rd } },
11651 /* MOD_0F2B_PREFIX_0 */
11652 {"movntps", { Mx, XM } },
11655 /* MOD_0F2B_PREFIX_1 */
11656 {"movntss", { Md, XM } },
11659 /* MOD_0F2B_PREFIX_2 */
11660 {"movntpd", { Mx, XM } },
11663 /* MOD_0F2B_PREFIX_3 */
11664 {"movntsd", { Mq, XM } },
11669 { "movmskpX", { Gdq, XS } },
11672 /* MOD_0F71_REG_2 */
11674 { "psrlw", { MS, Ib } },
11677 /* MOD_0F71_REG_4 */
11679 { "psraw", { MS, Ib } },
11682 /* MOD_0F71_REG_6 */
11684 { "psllw", { MS, Ib } },
11687 /* MOD_0F72_REG_2 */
11689 { "psrld", { MS, Ib } },
11692 /* MOD_0F72_REG_4 */
11694 { "psrad", { MS, Ib } },
11697 /* MOD_0F72_REG_6 */
11699 { "pslld", { MS, Ib } },
11702 /* MOD_0F73_REG_2 */
11704 { "psrlq", { MS, Ib } },
11707 /* MOD_0F73_REG_3 */
11709 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11712 /* MOD_0F73_REG_6 */
11714 { "psllq", { MS, Ib } },
11717 /* MOD_0F73_REG_7 */
11719 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11722 /* MOD_0FAE_REG_0 */
11723 { "fxsave", { FXSAVE } },
11724 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11727 /* MOD_0FAE_REG_1 */
11728 { "fxrstor", { FXSAVE } },
11729 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11732 /* MOD_0FAE_REG_2 */
11733 { "ldmxcsr", { Md } },
11734 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11737 /* MOD_0FAE_REG_3 */
11738 { "stmxcsr", { Md } },
11739 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11742 /* MOD_0FAE_REG_4 */
11743 { "xsave", { FXSAVE } },
11746 /* MOD_0FAE_REG_5 */
11747 { "xrstor", { FXSAVE } },
11748 { RM_TABLE (RM_0FAE_REG_5) },
11751 /* MOD_0FAE_REG_6 */
11752 { "xsaveopt", { FXSAVE } },
11753 { RM_TABLE (RM_0FAE_REG_6) },
11756 /* MOD_0FAE_REG_7 */
11757 { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11758 { RM_TABLE (RM_0FAE_REG_7) },
11762 { "lssS", { Gv, Mp } },
11766 { "lfsS", { Gv, Mp } },
11770 { "lgsS", { Gv, Mp } },
11773 /* MOD_0FC7_REG_3 */
11774 { "xrstors", { FXSAVE } },
11777 /* MOD_0FC7_REG_4 */
11778 { "xsavec", { FXSAVE } },
11781 /* MOD_0FC7_REG_5 */
11782 { "xsaves", { FXSAVE } },
11785 /* MOD_0FC7_REG_6 */
11786 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
11787 { "rdrand", { Ev } },
11790 /* MOD_0FC7_REG_7 */
11791 { "vmptrst", { Mq } },
11792 { "rdseed", { Ev } },
11797 { "pmovmskb", { Gdq, MS } },
11800 /* MOD_0FE7_PREFIX_2 */
11801 { "movntdq", { Mx, XM } },
11804 /* MOD_0FF0_PREFIX_3 */
11805 { "lddqu", { XM, M } },
11808 /* MOD_0F382A_PREFIX_2 */
11809 { "movntdqa", { XM, Mx } },
11813 { "bound{S|}", { Gv, Ma } },
11814 { EVEX_TABLE (EVEX_0F) },
11818 { "lesS", { Gv, Mp } },
11819 { VEX_C4_TABLE (VEX_0F) },
11823 { "ldsS", { Gv, Mp } },
11824 { VEX_C5_TABLE (VEX_0F) },
11827 /* MOD_VEX_0F12_PREFIX_0 */
11828 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11829 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11833 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11836 /* MOD_VEX_0F16_PREFIX_0 */
11837 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11838 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11842 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11846 { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11851 { VEX_W_TABLE (VEX_W_0F50_M_0) },
11854 /* MOD_VEX_0F71_REG_2 */
11856 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11859 /* MOD_VEX_0F71_REG_4 */
11861 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11864 /* MOD_VEX_0F71_REG_6 */
11866 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11869 /* MOD_VEX_0F72_REG_2 */
11871 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11874 /* MOD_VEX_0F72_REG_4 */
11876 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11879 /* MOD_VEX_0F72_REG_6 */
11881 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11884 /* MOD_VEX_0F73_REG_2 */
11886 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11889 /* MOD_VEX_0F73_REG_3 */
11891 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11894 /* MOD_VEX_0F73_REG_6 */
11896 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11899 /* MOD_VEX_0F73_REG_7 */
11901 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11904 /* MOD_VEX_0FAE_REG_2 */
11905 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11908 /* MOD_VEX_0FAE_REG_3 */
11909 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11912 /* MOD_VEX_0FD7_PREFIX_2 */
11914 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11917 /* MOD_VEX_0FE7_PREFIX_2 */
11918 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11921 /* MOD_VEX_0FF0_PREFIX_3 */
11922 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11925 /* MOD_VEX_0F381A_PREFIX_2 */
11926 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11929 /* MOD_VEX_0F382A_PREFIX_2 */
11930 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11933 /* MOD_VEX_0F382C_PREFIX_2 */
11934 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11937 /* MOD_VEX_0F382D_PREFIX_2 */
11938 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11941 /* MOD_VEX_0F382E_PREFIX_2 */
11942 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11945 /* MOD_VEX_0F382F_PREFIX_2 */
11946 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11949 /* MOD_VEX_0F385A_PREFIX_2 */
11950 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11953 /* MOD_VEX_0F388C_PREFIX_2 */
11954 { "vpmaskmov%LW", { XM, Vex, Mx } },
11957 /* MOD_VEX_0F388E_PREFIX_2 */
11958 { "vpmaskmov%LW", { Mx, Vex, XM } },
11960 #define NEED_MOD_TABLE
11961 #include "i386-dis-evex.h"
11962 #undef NEED_MOD_TABLE
11965 static const struct dis386 rm_table[][8] = {
11968 { "xabort", { Skip_MODRM, Ib } },
11972 { "xbeginT", { Skip_MODRM, Jv } },
11975 /* RM_0F01_REG_0 */
11977 { "vmcall", { Skip_MODRM } },
11978 { "vmlaunch", { Skip_MODRM } },
11979 { "vmresume", { Skip_MODRM } },
11980 { "vmxoff", { Skip_MODRM } },
11983 /* RM_0F01_REG_1 */
11984 { "monitor", { { OP_Monitor, 0 } } },
11985 { "mwait", { { OP_Mwait, 0 } } },
11986 { "clac", { Skip_MODRM } },
11987 { "stac", { Skip_MODRM } },
11991 { "encls", { Skip_MODRM } },
11994 /* RM_0F01_REG_2 */
11995 { "xgetbv", { Skip_MODRM } },
11996 { "xsetbv", { Skip_MODRM } },
11999 { "vmfunc", { Skip_MODRM } },
12000 { "xend", { Skip_MODRM } },
12001 { "xtest", { Skip_MODRM } },
12002 { "enclu", { Skip_MODRM } },
12005 /* RM_0F01_REG_3 */
12006 { "vmrun", { Skip_MODRM } },
12007 { "vmmcall", { Skip_MODRM } },
12008 { "vmload", { Skip_MODRM } },
12009 { "vmsave", { Skip_MODRM } },
12010 { "stgi", { Skip_MODRM } },
12011 { "clgi", { Skip_MODRM } },
12012 { "skinit", { Skip_MODRM } },
12013 { "invlpga", { Skip_MODRM } },
12016 /* RM_0F01_REG_7 */
12017 { "swapgs", { Skip_MODRM } },
12018 { "rdtscp", { Skip_MODRM } },
12021 /* RM_0FAE_REG_5 */
12022 { "lfence", { Skip_MODRM } },
12025 /* RM_0FAE_REG_6 */
12026 { "mfence", { Skip_MODRM } },
12029 /* RM_0FAE_REG_7 */
12030 { "sfence", { Skip_MODRM } },
12034 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12036 /* We use the high bit to indicate different name for the same
12038 #define REP_PREFIX (0xf3 | 0x100)
12039 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12040 #define XRELEASE_PREFIX (0xf3 | 0x400)
12041 #define BND_PREFIX (0xf2 | 0x400)
12046 int newrex, i, length;
12052 last_lock_prefix = -1;
12053 last_repz_prefix = -1;
12054 last_repnz_prefix = -1;
12055 last_data_prefix = -1;
12056 last_addr_prefix = -1;
12057 last_rex_prefix = -1;
12058 last_seg_prefix = -1;
12060 active_seg_prefix = 0;
12061 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12062 all_prefixes[i] = 0;
12065 /* The maximum instruction length is 15bytes. */
12066 while (length < MAX_CODE_LENGTH - 1)
12068 FETCH_DATA (the_info, codep + 1);
12072 /* REX prefixes family. */
12089 if (address_mode == mode_64bit)
12093 last_rex_prefix = i;
12096 prefixes |= PREFIX_REPZ;
12097 last_repz_prefix = i;
12100 prefixes |= PREFIX_REPNZ;
12101 last_repnz_prefix = i;
12104 prefixes |= PREFIX_LOCK;
12105 last_lock_prefix = i;
12108 prefixes |= PREFIX_CS;
12109 last_seg_prefix = i;
12110 active_seg_prefix = PREFIX_CS;
12113 prefixes |= PREFIX_SS;
12114 last_seg_prefix = i;
12115 active_seg_prefix = PREFIX_SS;
12118 prefixes |= PREFIX_DS;
12119 last_seg_prefix = i;
12120 active_seg_prefix = PREFIX_DS;
12123 prefixes |= PREFIX_ES;
12124 last_seg_prefix = i;
12125 active_seg_prefix = PREFIX_ES;
12128 prefixes |= PREFIX_FS;
12129 last_seg_prefix = i;
12130 active_seg_prefix = PREFIX_FS;
12133 prefixes |= PREFIX_GS;
12134 last_seg_prefix = i;
12135 active_seg_prefix = PREFIX_GS;
12138 prefixes |= PREFIX_DATA;
12139 last_data_prefix = i;
12142 prefixes |= PREFIX_ADDR;
12143 last_addr_prefix = i;
12146 /* fwait is really an instruction. If there are prefixes
12147 before the fwait, they belong to the fwait, *not* to the
12148 following instruction. */
12150 if (prefixes || rex)
12152 prefixes |= PREFIX_FWAIT;
12154 /* This ensures that the previous REX prefixes are noticed
12155 as unused prefixes, as in the return case below. */
12159 prefixes = PREFIX_FWAIT;
12164 /* Rex is ignored when followed by another prefix. */
12170 if (*codep != FWAIT_OPCODE)
12171 all_prefixes[i++] = *codep;
12179 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12182 static const char *
12183 prefix_name (int pref, int sizeflag)
12185 static const char *rexes [16] =
12188 "rex.B", /* 0x41 */
12189 "rex.X", /* 0x42 */
12190 "rex.XB", /* 0x43 */
12191 "rex.R", /* 0x44 */
12192 "rex.RB", /* 0x45 */
12193 "rex.RX", /* 0x46 */
12194 "rex.RXB", /* 0x47 */
12195 "rex.W", /* 0x48 */
12196 "rex.WB", /* 0x49 */
12197 "rex.WX", /* 0x4a */
12198 "rex.WXB", /* 0x4b */
12199 "rex.WR", /* 0x4c */
12200 "rex.WRB", /* 0x4d */
12201 "rex.WRX", /* 0x4e */
12202 "rex.WRXB", /* 0x4f */
12207 /* REX prefixes family. */
12224 return rexes [pref - 0x40];
12244 return (sizeflag & DFLAG) ? "data16" : "data32";
12246 if (address_mode == mode_64bit)
12247 return (sizeflag & AFLAG) ? "addr32" : "addr64";
12249 return (sizeflag & AFLAG) ? "addr16" : "addr32";
12254 case XACQUIRE_PREFIX:
12256 case XRELEASE_PREFIX:
12265 static char op_out[MAX_OPERANDS][100];
12266 static int op_ad, op_index[MAX_OPERANDS];
12267 static int two_source_ops;
12268 static bfd_vma op_address[MAX_OPERANDS];
12269 static bfd_vma op_riprel[MAX_OPERANDS];
12270 static bfd_vma start_pc;
12273 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12274 * (see topic "Redundant prefixes" in the "Differences from 8086"
12275 * section of the "Virtual 8086 Mode" chapter.)
12276 * 'pc' should be the address of this instruction, it will
12277 * be used to print the target address if this is a relative jump or call
12278 * The function returns the length of this instruction in bytes.
12281 static char intel_syntax;
12282 static char intel_mnemonic = !SYSV386_COMPAT;
12283 static char open_char;
12284 static char close_char;
12285 static char separator_char;
12286 static char scale_char;
12288 /* Here for backwards compatibility. When gdb stops using
12289 print_insn_i386_att and print_insn_i386_intel these functions can
12290 disappear, and print_insn_i386 be merged into print_insn. */
12292 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12296 return print_insn (pc, info);
12300 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12304 return print_insn (pc, info);
12308 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12312 return print_insn (pc, info);
12316 print_i386_disassembler_options (FILE *stream)
12318 fprintf (stream, _("\n\
12319 The following i386/x86-64 specific disassembler options are supported for use\n\
12320 with the -M switch (multiple options should be separated by commas):\n"));
12322 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
12323 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
12324 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
12325 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
12326 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
12327 fprintf (stream, _(" att-mnemonic\n"
12328 " Display instruction in AT&T mnemonic\n"));
12329 fprintf (stream, _(" intel-mnemonic\n"
12330 " Display instruction in Intel mnemonic\n"));
12331 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
12332 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
12333 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
12334 fprintf (stream, _(" data32 Assume 32bit data size\n"));
12335 fprintf (stream, _(" data16 Assume 16bit data size\n"));
12336 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12340 static const struct dis386 bad_opcode = { "(bad)", { XX } };
12342 /* Get a pointer to struct dis386 with a valid name. */
12344 static const struct dis386 *
12345 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12347 int vindex, vex_table_index;
12349 if (dp->name != NULL)
12352 switch (dp->op[0].bytemode)
12354 case USE_REG_TABLE:
12355 dp = ®_table[dp->op[1].bytemode][modrm.reg];
12358 case USE_MOD_TABLE:
12359 vindex = modrm.mod == 0x3 ? 1 : 0;
12360 dp = &mod_table[dp->op[1].bytemode][vindex];
12364 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12367 case USE_PREFIX_TABLE:
12370 /* The prefix in VEX is implicit. */
12371 switch (vex.prefix)
12376 case REPE_PREFIX_OPCODE:
12379 case DATA_PREFIX_OPCODE:
12382 case REPNE_PREFIX_OPCODE:
12392 int last_prefix = -1;
12395 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12396 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12398 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12400 if (last_repz_prefix > last_repnz_prefix)
12403 prefix = PREFIX_REPZ;
12404 last_prefix = last_repz_prefix;
12409 prefix = PREFIX_REPNZ;
12410 last_prefix = last_repnz_prefix;
12413 /* Ignore the invalid index if it isn't mandatory. */
12414 if (!mandatory_prefix
12415 && (prefix_table[dp->op[1].bytemode][vindex].name
12417 && (prefix_table[dp->op[1].bytemode][vindex].op[0].bytemode
12422 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12425 prefix = PREFIX_DATA;
12426 last_prefix = last_data_prefix;
12431 used_prefixes |= prefix;
12432 all_prefixes[last_prefix] = 0;
12435 dp = &prefix_table[dp->op[1].bytemode][vindex];
12438 case USE_X86_64_TABLE:
12439 vindex = address_mode == mode_64bit ? 1 : 0;
12440 dp = &x86_64_table[dp->op[1].bytemode][vindex];
12443 case USE_3BYTE_TABLE:
12444 FETCH_DATA (info, codep + 2);
12446 dp = &three_byte_table[dp->op[1].bytemode][vindex];
12448 modrm.mod = (*codep >> 6) & 3;
12449 modrm.reg = (*codep >> 3) & 7;
12450 modrm.rm = *codep & 7;
12453 case USE_VEX_LEN_TABLE:
12457 switch (vex.length)
12470 dp = &vex_len_table[dp->op[1].bytemode][vindex];
12473 case USE_XOP_8F_TABLE:
12474 FETCH_DATA (info, codep + 3);
12475 /* All bits in the REX prefix are ignored. */
12477 rex = ~(*codep >> 5) & 0x7;
12479 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12480 switch ((*codep & 0x1f))
12486 vex_table_index = XOP_08;
12489 vex_table_index = XOP_09;
12492 vex_table_index = XOP_0A;
12496 vex.w = *codep & 0x80;
12497 if (vex.w && address_mode == mode_64bit)
12500 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12501 if (address_mode != mode_64bit
12502 && vex.register_specifier > 0x7)
12508 vex.length = (*codep & 0x4) ? 256 : 128;
12509 switch ((*codep & 0x3))
12515 vex.prefix = DATA_PREFIX_OPCODE;
12518 vex.prefix = REPE_PREFIX_OPCODE;
12521 vex.prefix = REPNE_PREFIX_OPCODE;
12528 dp = &xop_table[vex_table_index][vindex];
12531 FETCH_DATA (info, codep + 1);
12532 modrm.mod = (*codep >> 6) & 3;
12533 modrm.reg = (*codep >> 3) & 7;
12534 modrm.rm = *codep & 7;
12537 case USE_VEX_C4_TABLE:
12539 FETCH_DATA (info, codep + 3);
12540 /* All bits in the REX prefix are ignored. */
12542 rex = ~(*codep >> 5) & 0x7;
12543 switch ((*codep & 0x1f))
12549 vex_table_index = VEX_0F;
12552 vex_table_index = VEX_0F38;
12555 vex_table_index = VEX_0F3A;
12559 vex.w = *codep & 0x80;
12560 if (vex.w && address_mode == mode_64bit)
12563 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12564 if (address_mode != mode_64bit
12565 && vex.register_specifier > 0x7)
12571 vex.length = (*codep & 0x4) ? 256 : 128;
12572 switch ((*codep & 0x3))
12578 vex.prefix = DATA_PREFIX_OPCODE;
12581 vex.prefix = REPE_PREFIX_OPCODE;
12584 vex.prefix = REPNE_PREFIX_OPCODE;
12591 dp = &vex_table[vex_table_index][vindex];
12593 /* There is no MODRM byte for VEX [82|77]. */
12594 if (vindex != 0x77 && vindex != 0x82)
12596 FETCH_DATA (info, codep + 1);
12597 modrm.mod = (*codep >> 6) & 3;
12598 modrm.reg = (*codep >> 3) & 7;
12599 modrm.rm = *codep & 7;
12603 case USE_VEX_C5_TABLE:
12605 FETCH_DATA (info, codep + 2);
12606 /* All bits in the REX prefix are ignored. */
12608 rex = (*codep & 0x80) ? 0 : REX_R;
12610 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12611 if (address_mode != mode_64bit
12612 && vex.register_specifier > 0x7)
12620 vex.length = (*codep & 0x4) ? 256 : 128;
12621 switch ((*codep & 0x3))
12627 vex.prefix = DATA_PREFIX_OPCODE;
12630 vex.prefix = REPE_PREFIX_OPCODE;
12633 vex.prefix = REPNE_PREFIX_OPCODE;
12640 dp = &vex_table[dp->op[1].bytemode][vindex];
12642 /* There is no MODRM byte for VEX [82|77]. */
12643 if (vindex != 0x77 && vindex != 0x82)
12645 FETCH_DATA (info, codep + 1);
12646 modrm.mod = (*codep >> 6) & 3;
12647 modrm.reg = (*codep >> 3) & 7;
12648 modrm.rm = *codep & 7;
12652 case USE_VEX_W_TABLE:
12656 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12659 case USE_EVEX_TABLE:
12660 two_source_ops = 0;
12663 FETCH_DATA (info, codep + 4);
12664 /* All bits in the REX prefix are ignored. */
12666 /* The first byte after 0x62. */
12667 rex = ~(*codep >> 5) & 0x7;
12668 vex.r = *codep & 0x10;
12669 switch ((*codep & 0xf))
12672 return &bad_opcode;
12674 vex_table_index = EVEX_0F;
12677 vex_table_index = EVEX_0F38;
12680 vex_table_index = EVEX_0F3A;
12684 /* The second byte after 0x62. */
12686 vex.w = *codep & 0x80;
12687 if (vex.w && address_mode == mode_64bit)
12690 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12691 if (address_mode != mode_64bit)
12693 /* In 16/32-bit mode silently ignore following bits. */
12697 vex.register_specifier &= 0x7;
12701 if (!(*codep & 0x4))
12702 return &bad_opcode;
12704 switch ((*codep & 0x3))
12710 vex.prefix = DATA_PREFIX_OPCODE;
12713 vex.prefix = REPE_PREFIX_OPCODE;
12716 vex.prefix = REPNE_PREFIX_OPCODE;
12720 /* The third byte after 0x62. */
12723 /* Remember the static rounding bits. */
12724 vex.ll = (*codep >> 5) & 3;
12725 vex.b = (*codep & 0x10) != 0;
12727 vex.v = *codep & 0x8;
12728 vex.mask_register_specifier = *codep & 0x7;
12729 vex.zeroing = *codep & 0x80;
12735 dp = &evex_table[vex_table_index][vindex];
12737 FETCH_DATA (info, codep + 1);
12738 modrm.mod = (*codep >> 6) & 3;
12739 modrm.reg = (*codep >> 3) & 7;
12740 modrm.rm = *codep & 7;
12742 /* Set vector length. */
12743 if (modrm.mod == 3 && vex.b)
12759 return &bad_opcode;
12772 if (dp->name != NULL)
12775 return get_valid_dis386 (dp, info);
12779 get_sib (disassemble_info *info, int sizeflag)
12781 /* If modrm.mod == 3, operand must be register. */
12783 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12787 FETCH_DATA (info, codep + 2);
12788 sib.index = (codep [1] >> 3) & 7;
12789 sib.scale = (codep [1] >> 6) & 3;
12790 sib.base = codep [1] & 7;
12795 print_insn (bfd_vma pc, disassemble_info *info)
12797 const struct dis386 *dp;
12799 char *op_txt[MAX_OPERANDS];
12801 int sizeflag, orig_sizeflag;
12803 struct dis_private priv;
12806 priv.orig_sizeflag = AFLAG | DFLAG;
12807 if ((info->mach & bfd_mach_i386_i386) != 0)
12808 address_mode = mode_32bit;
12809 else if (info->mach == bfd_mach_i386_i8086)
12811 address_mode = mode_16bit;
12812 priv.orig_sizeflag = 0;
12815 address_mode = mode_64bit;
12817 if (intel_syntax == (char) -1)
12818 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12820 for (p = info->disassembler_options; p != NULL; )
12822 if (CONST_STRNEQ (p, "x86-64"))
12824 address_mode = mode_64bit;
12825 priv.orig_sizeflag = AFLAG | DFLAG;
12827 else if (CONST_STRNEQ (p, "i386"))
12829 address_mode = mode_32bit;
12830 priv.orig_sizeflag = AFLAG | DFLAG;
12832 else if (CONST_STRNEQ (p, "i8086"))
12834 address_mode = mode_16bit;
12835 priv.orig_sizeflag = 0;
12837 else if (CONST_STRNEQ (p, "intel"))
12840 if (CONST_STRNEQ (p + 5, "-mnemonic"))
12841 intel_mnemonic = 1;
12843 else if (CONST_STRNEQ (p, "att"))
12846 if (CONST_STRNEQ (p + 3, "-mnemonic"))
12847 intel_mnemonic = 0;
12849 else if (CONST_STRNEQ (p, "addr"))
12851 if (address_mode == mode_64bit)
12853 if (p[4] == '3' && p[5] == '2')
12854 priv.orig_sizeflag &= ~AFLAG;
12855 else if (p[4] == '6' && p[5] == '4')
12856 priv.orig_sizeflag |= AFLAG;
12860 if (p[4] == '1' && p[5] == '6')
12861 priv.orig_sizeflag &= ~AFLAG;
12862 else if (p[4] == '3' && p[5] == '2')
12863 priv.orig_sizeflag |= AFLAG;
12866 else if (CONST_STRNEQ (p, "data"))
12868 if (p[4] == '1' && p[5] == '6')
12869 priv.orig_sizeflag &= ~DFLAG;
12870 else if (p[4] == '3' && p[5] == '2')
12871 priv.orig_sizeflag |= DFLAG;
12873 else if (CONST_STRNEQ (p, "suffix"))
12874 priv.orig_sizeflag |= SUFFIX_ALWAYS;
12876 p = strchr (p, ',');
12883 names64 = intel_names64;
12884 names32 = intel_names32;
12885 names16 = intel_names16;
12886 names8 = intel_names8;
12887 names8rex = intel_names8rex;
12888 names_seg = intel_names_seg;
12889 names_mm = intel_names_mm;
12890 names_bnd = intel_names_bnd;
12891 names_xmm = intel_names_xmm;
12892 names_ymm = intel_names_ymm;
12893 names_zmm = intel_names_zmm;
12894 index64 = intel_index64;
12895 index32 = intel_index32;
12896 names_mask = intel_names_mask;
12897 index16 = intel_index16;
12900 separator_char = '+';
12905 names64 = att_names64;
12906 names32 = att_names32;
12907 names16 = att_names16;
12908 names8 = att_names8;
12909 names8rex = att_names8rex;
12910 names_seg = att_names_seg;
12911 names_mm = att_names_mm;
12912 names_bnd = att_names_bnd;
12913 names_xmm = att_names_xmm;
12914 names_ymm = att_names_ymm;
12915 names_zmm = att_names_zmm;
12916 index64 = att_index64;
12917 index32 = att_index32;
12918 names_mask = att_names_mask;
12919 index16 = att_index16;
12922 separator_char = ',';
12926 /* The output looks better if we put 7 bytes on a line, since that
12927 puts most long word instructions on a single line. Use 8 bytes
12929 if ((info->mach & bfd_mach_l1om) != 0)
12930 info->bytes_per_line = 8;
12932 info->bytes_per_line = 7;
12934 info->private_data = &priv;
12935 priv.max_fetched = priv.the_buffer;
12936 priv.insn_start = pc;
12939 for (i = 0; i < MAX_OPERANDS; ++i)
12947 start_codep = priv.the_buffer;
12948 codep = priv.the_buffer;
12950 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12954 /* Getting here means we tried for data but didn't get it. That
12955 means we have an incomplete instruction of some sort. Just
12956 print the first byte as a prefix or a .byte pseudo-op. */
12957 if (codep > priv.the_buffer)
12959 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12961 (*info->fprintf_func) (info->stream, "%s", name);
12964 /* Just print the first byte as a .byte instruction. */
12965 (*info->fprintf_func) (info->stream, ".byte 0x%x",
12966 (unsigned int) priv.the_buffer[0]);
12976 sizeflag = priv.orig_sizeflag;
12978 if (!ckprefix () || rex_used)
12980 /* Too many prefixes or unused REX prefixes. */
12982 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12984 (*info->fprintf_func) (info->stream, "%s%s",
12986 prefix_name (all_prefixes[i], sizeflag));
12990 insn_codep = codep;
12992 FETCH_DATA (info, codep + 1);
12993 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12995 if (((prefixes & PREFIX_FWAIT)
12996 && ((*codep < 0xd8) || (*codep > 0xdf))))
12998 /* Handle prefixes before fwait. */
12999 for (i = 0; i < fwait_prefix && all_prefixes[i];
13001 (*info->fprintf_func) (info->stream, "%s ",
13002 prefix_name (all_prefixes[i], sizeflag));
13003 (*info->fprintf_func) (info->stream, "fwait");
13007 if (*codep == 0x0f)
13009 unsigned char threebyte;
13010 FETCH_DATA (info, codep + 2);
13011 threebyte = *++codep;
13012 dp = &dis386_twobyte[threebyte];
13013 need_modrm = twobyte_has_modrm[*codep];
13014 mandatory_prefix = twobyte_has_mandatory_prefix[*codep];
13019 dp = &dis386[*codep];
13020 need_modrm = onebyte_has_modrm[*codep];
13021 mandatory_prefix = 0;
13025 /* Save sizeflag for printing the extra prefixes later before updating
13026 it for mnemonic and operand processing. The prefix names depend
13027 only on the address mode. */
13028 orig_sizeflag = sizeflag;
13029 if (prefixes & PREFIX_ADDR)
13031 if ((prefixes & PREFIX_DATA))
13037 FETCH_DATA (info, codep + 1);
13038 modrm.mod = (*codep >> 6) & 3;
13039 modrm.reg = (*codep >> 3) & 7;
13040 modrm.rm = *codep & 7;
13048 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13050 get_sib (info, sizeflag);
13051 dofloat (sizeflag);
13055 dp = get_valid_dis386 (dp, info);
13056 if (dp != NULL && putop (dp->name, sizeflag) == 0)
13058 get_sib (info, sizeflag);
13059 for (i = 0; i < MAX_OPERANDS; ++i)
13062 op_ad = MAX_OPERANDS - 1 - i;
13064 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13065 /* For EVEX instruction after the last operand masking
13066 should be printed. */
13067 if (i == 0 && vex.evex)
13069 /* Don't print {%k0}. */
13070 if (vex.mask_register_specifier)
13073 oappend (names_mask[vex.mask_register_specifier]);
13083 /* Check if the REX prefix is used. */
13084 if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13085 all_prefixes[last_rex_prefix] = 0;
13087 /* Check if the SEG prefix is used. */
13088 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13089 | PREFIX_FS | PREFIX_GS)) != 0
13090 && (used_prefixes & active_seg_prefix) != 0)
13091 all_prefixes[last_seg_prefix] = 0;
13093 /* Check if the ADDR prefix is used. */
13094 if ((prefixes & PREFIX_ADDR) != 0
13095 && (used_prefixes & PREFIX_ADDR) != 0)
13096 all_prefixes[last_addr_prefix] = 0;
13098 /* Check if the DATA prefix is used. */
13099 if ((prefixes & PREFIX_DATA) != 0
13100 && (used_prefixes & PREFIX_DATA) != 0)
13101 all_prefixes[last_data_prefix] = 0;
13103 /* Print the extra prefixes. */
13105 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13106 if (all_prefixes[i])
13109 name = prefix_name (all_prefixes[i], orig_sizeflag);
13112 prefix_length += strlen (name) + 1;
13113 (*info->fprintf_func) (info->stream, "%s ", name);
13116 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13117 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13118 used by putop and MMX/SSE operand and may be overriden by the
13119 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13121 if (mandatory_prefix
13122 && dp != &bad_opcode
13124 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13126 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13128 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13130 && (used_prefixes & PREFIX_DATA) == 0))))
13132 (*info->fprintf_func) (info->stream, "(bad)");
13133 return end_codep - priv.the_buffer;
13136 /* Check maximum code length. */
13137 if ((codep - start_codep) > MAX_CODE_LENGTH)
13139 (*info->fprintf_func) (info->stream, "(bad)");
13140 return MAX_CODE_LENGTH;
13143 obufp = mnemonicendp;
13144 for (i = strlen (obuf) + prefix_length; i < 6; i++)
13147 (*info->fprintf_func) (info->stream, "%s", obuf);
13149 /* The enter and bound instructions are printed with operands in the same
13150 order as the intel book; everything else is printed in reverse order. */
13151 if (intel_syntax || two_source_ops)
13155 for (i = 0; i < MAX_OPERANDS; ++i)
13156 op_txt[i] = op_out[i];
13158 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13160 op_ad = op_index[i];
13161 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13162 op_index[MAX_OPERANDS - 1 - i] = op_ad;
13163 riprel = op_riprel[i];
13164 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13165 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13170 for (i = 0; i < MAX_OPERANDS; ++i)
13171 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13175 for (i = 0; i < MAX_OPERANDS; ++i)
13179 (*info->fprintf_func) (info->stream, ",");
13180 if (op_index[i] != -1 && !op_riprel[i])
13181 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13183 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13187 for (i = 0; i < MAX_OPERANDS; i++)
13188 if (op_index[i] != -1 && op_riprel[i])
13190 (*info->fprintf_func) (info->stream, " # ");
13191 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
13192 + op_address[op_index[i]]), info);
13195 return codep - priv.the_buffer;
13198 static const char *float_mem[] = {
13273 static const unsigned char float_mem_mode[] = {
13348 #define ST { OP_ST, 0 }
13349 #define STi { OP_STi, 0 }
13351 #define FGRPd9_2 NULL, { { NULL, 0 } }
13352 #define FGRPd9_4 NULL, { { NULL, 1 } }
13353 #define FGRPd9_5 NULL, { { NULL, 2 } }
13354 #define FGRPd9_6 NULL, { { NULL, 3 } }
13355 #define FGRPd9_7 NULL, { { NULL, 4 } }
13356 #define FGRPda_5 NULL, { { NULL, 5 } }
13357 #define FGRPdb_4 NULL, { { NULL, 6 } }
13358 #define FGRPde_3 NULL, { { NULL, 7 } }
13359 #define FGRPdf_4 NULL, { { NULL, 8 } }
13361 static const struct dis386 float_reg[][8] = {
13364 { "fadd", { ST, STi } },
13365 { "fmul", { ST, STi } },
13366 { "fcom", { STi } },
13367 { "fcomp", { STi } },
13368 { "fsub", { ST, STi } },
13369 { "fsubr", { ST, STi } },
13370 { "fdiv", { ST, STi } },
13371 { "fdivr", { ST, STi } },
13375 { "fld", { STi } },
13376 { "fxch", { STi } },
13386 { "fcmovb", { ST, STi } },
13387 { "fcmove", { ST, STi } },
13388 { "fcmovbe",{ ST, STi } },
13389 { "fcmovu", { ST, STi } },
13397 { "fcmovnb",{ ST, STi } },
13398 { "fcmovne",{ ST, STi } },
13399 { "fcmovnbe",{ ST, STi } },
13400 { "fcmovnu",{ ST, STi } },
13402 { "fucomi", { ST, STi } },
13403 { "fcomi", { ST, STi } },
13408 { "fadd", { STi, ST } },
13409 { "fmul", { STi, ST } },
13412 { "fsub!M", { STi, ST } },
13413 { "fsubM", { STi, ST } },
13414 { "fdiv!M", { STi, ST } },
13415 { "fdivM", { STi, ST } },
13419 { "ffree", { STi } },
13421 { "fst", { STi } },
13422 { "fstp", { STi } },
13423 { "fucom", { STi } },
13424 { "fucomp", { STi } },
13430 { "faddp", { STi, ST } },
13431 { "fmulp", { STi, ST } },
13434 { "fsub!Mp", { STi, ST } },
13435 { "fsubMp", { STi, ST } },
13436 { "fdiv!Mp", { STi, ST } },
13437 { "fdivMp", { STi, ST } },
13441 { "ffreep", { STi } },
13446 { "fucomip", { ST, STi } },
13447 { "fcomip", { ST, STi } },
13452 static char *fgrps[][8] = {
13455 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13460 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13465 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13470 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13475 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13480 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13485 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13486 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13491 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13496 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13501 swap_operand (void)
13503 mnemonicendp[0] = '.';
13504 mnemonicendp[1] = 's';
13509 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13510 int sizeflag ATTRIBUTE_UNUSED)
13512 /* Skip mod/rm byte. */
13518 dofloat (int sizeflag)
13520 const struct dis386 *dp;
13521 unsigned char floatop;
13523 floatop = codep[-1];
13525 if (modrm.mod != 3)
13527 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13529 putop (float_mem[fp_indx], sizeflag);
13532 OP_E (float_mem_mode[fp_indx], sizeflag);
13535 /* Skip mod/rm byte. */
13539 dp = &float_reg[floatop - 0xd8][modrm.reg];
13540 if (dp->name == NULL)
13542 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13544 /* Instruction fnstsw is only one with strange arg. */
13545 if (floatop == 0xdf && codep[-1] == 0xe0)
13546 strcpy (op_out[0], names16[0]);
13550 putop (dp->name, sizeflag);
13555 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13560 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13564 /* Like oappend (below), but S is a string starting with '%'.
13565 In Intel syntax, the '%' is elided. */
13567 oappend_maybe_intel (const char *s)
13569 oappend (s + intel_syntax);
13573 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13575 oappend_maybe_intel ("%st");
13579 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13581 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13582 oappend_maybe_intel (scratchbuf);
13585 /* Capital letters in template are macros. */
13587 putop (const char *in_template, int sizeflag)
13592 unsigned int l = 0, len = 1;
13595 #define SAVE_LAST(c) \
13596 if (l < len && l < sizeof (last)) \
13601 for (p = in_template; *p; p++)
13618 while (*++p != '|')
13619 if (*p == '}' || *p == '\0')
13622 /* Fall through. */
13627 while (*++p != '}')
13638 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13642 if (l == 0 && len == 1)
13647 if (sizeflag & SUFFIX_ALWAYS)
13660 if (address_mode == mode_64bit
13661 && !(prefixes & PREFIX_ADDR))
13672 if (intel_syntax && !alt)
13674 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13676 if (sizeflag & DFLAG)
13677 *obufp++ = intel_syntax ? 'd' : 'l';
13679 *obufp++ = intel_syntax ? 'w' : 's';
13680 used_prefixes |= (prefixes & PREFIX_DATA);
13684 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13687 if (modrm.mod == 3)
13693 if (sizeflag & DFLAG)
13694 *obufp++ = intel_syntax ? 'd' : 'l';
13697 used_prefixes |= (prefixes & PREFIX_DATA);
13703 case 'E': /* For jcxz/jecxz */
13704 if (address_mode == mode_64bit)
13706 if (sizeflag & AFLAG)
13712 if (sizeflag & AFLAG)
13714 used_prefixes |= (prefixes & PREFIX_ADDR);
13719 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13721 if (sizeflag & AFLAG)
13722 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13724 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13725 used_prefixes |= (prefixes & PREFIX_ADDR);
13729 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13731 if ((rex & REX_W) || (sizeflag & DFLAG))
13735 if (!(rex & REX_W))
13736 used_prefixes |= (prefixes & PREFIX_DATA);
13741 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13742 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13744 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13747 if (prefixes & PREFIX_DS)
13768 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13773 /* Fall through. */
13776 if (l != 0 || len != 1)
13784 if (sizeflag & SUFFIX_ALWAYS)
13788 if (intel_mnemonic != cond)
13792 if ((prefixes & PREFIX_FWAIT) == 0)
13795 used_prefixes |= PREFIX_FWAIT;
13801 else if (intel_syntax && (sizeflag & DFLAG))
13805 if (!(rex & REX_W))
13806 used_prefixes |= (prefixes & PREFIX_DATA);
13810 && address_mode == mode_64bit
13811 && ((sizeflag & DFLAG) || (rex & REX_W)))
13816 /* Fall through. */
13819 if (l == 0 && len == 1)
13824 if ((rex & REX_W) == 0
13825 && (prefixes & PREFIX_DATA))
13827 if ((sizeflag & DFLAG) == 0)
13829 used_prefixes |= (prefixes & PREFIX_DATA);
13833 if ((prefixes & PREFIX_DATA)
13835 || (sizeflag & SUFFIX_ALWAYS))
13842 if (sizeflag & DFLAG)
13846 used_prefixes |= (prefixes & PREFIX_DATA);
13852 if (l != 1 || len != 2 || last[0] != 'L')
13858 if ((prefixes & PREFIX_DATA)
13860 || (sizeflag & SUFFIX_ALWAYS))
13867 if (sizeflag & DFLAG)
13868 *obufp++ = intel_syntax ? 'd' : 'l';
13871 used_prefixes |= (prefixes & PREFIX_DATA);
13879 if (address_mode == mode_64bit
13880 && ((sizeflag & DFLAG) || (rex & REX_W)))
13882 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13886 /* Fall through. */
13889 if (l == 0 && len == 1)
13892 if (intel_syntax && !alt)
13895 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13901 if (sizeflag & DFLAG)
13902 *obufp++ = intel_syntax ? 'd' : 'l';
13905 used_prefixes |= (prefixes & PREFIX_DATA);
13911 if (l != 1 || len != 2 || last[0] != 'L')
13917 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13932 else if (sizeflag & DFLAG)
13941 if (intel_syntax && !p[1]
13942 && ((rex & REX_W) || (sizeflag & DFLAG)))
13944 if (!(rex & REX_W))
13945 used_prefixes |= (prefixes & PREFIX_DATA);
13948 if (l == 0 && len == 1)
13952 if (address_mode == mode_64bit
13953 && ((sizeflag & DFLAG) || (rex & REX_W)))
13955 if (sizeflag & SUFFIX_ALWAYS)
13977 /* Fall through. */
13980 if (l == 0 && len == 1)
13985 if (sizeflag & SUFFIX_ALWAYS)
13991 if (sizeflag & DFLAG)
13995 used_prefixes |= (prefixes & PREFIX_DATA);
14009 if (address_mode == mode_64bit
14010 && !(prefixes & PREFIX_ADDR))
14021 if (l != 0 || len != 1)
14026 if (need_vex && vex.prefix)
14028 if (vex.prefix == DATA_PREFIX_OPCODE)
14035 if (prefixes & PREFIX_DATA)
14039 used_prefixes |= (prefixes & PREFIX_DATA);
14043 if (l == 0 && len == 1)
14045 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14056 if (l != 1 || len != 2 || last[0] != 'X')
14064 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14066 switch (vex.length)
14080 if (l == 0 && len == 1)
14082 /* operand size flag for cwtl, cbtw */
14091 else if (sizeflag & DFLAG)
14095 if (!(rex & REX_W))
14096 used_prefixes |= (prefixes & PREFIX_DATA);
14103 && last[0] != 'L'))
14110 if (last[0] == 'X')
14111 *obufp++ = vex.w ? 'd': 's';
14113 *obufp++ = vex.w ? 'q': 'd';
14120 mnemonicendp = obufp;
14125 oappend (const char *s)
14127 obufp = stpcpy (obufp, s);
14133 /* Only print the active segment register. */
14134 if (!active_seg_prefix)
14137 used_prefixes |= active_seg_prefix;
14138 switch (active_seg_prefix)
14141 oappend_maybe_intel ("%cs:");
14144 oappend_maybe_intel ("%ds:");
14147 oappend_maybe_intel ("%ss:");
14150 oappend_maybe_intel ("%es:");
14153 oappend_maybe_intel ("%fs:");
14156 oappend_maybe_intel ("%gs:");
14164 OP_indirE (int bytemode, int sizeflag)
14168 OP_E (bytemode, sizeflag);
14172 print_operand_value (char *buf, int hex, bfd_vma disp)
14174 if (address_mode == mode_64bit)
14182 sprintf_vma (tmp, disp);
14183 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14184 strcpy (buf + 2, tmp + i);
14188 bfd_signed_vma v = disp;
14195 /* Check for possible overflow on 0x8000000000000000. */
14198 strcpy (buf, "9223372036854775808");
14212 tmp[28 - i] = (v % 10) + '0';
14216 strcpy (buf, tmp + 29 - i);
14222 sprintf (buf, "0x%x", (unsigned int) disp);
14224 sprintf (buf, "%d", (int) disp);
14228 /* Put DISP in BUF as signed hex number. */
14231 print_displacement (char *buf, bfd_vma disp)
14233 bfd_signed_vma val = disp;
14242 /* Check for possible overflow. */
14245 switch (address_mode)
14248 strcpy (buf + j, "0x8000000000000000");
14251 strcpy (buf + j, "0x80000000");
14254 strcpy (buf + j, "0x8000");
14264 sprintf_vma (tmp, (bfd_vma) val);
14265 for (i = 0; tmp[i] == '0'; i++)
14267 if (tmp[i] == '\0')
14269 strcpy (buf + j, tmp + i);
14273 intel_operand_size (int bytemode, int sizeflag)
14277 && (bytemode == x_mode
14278 || bytemode == evex_half_bcst_xmmq_mode))
14281 oappend ("QWORD PTR ");
14283 oappend ("DWORD PTR ");
14292 oappend ("BYTE PTR ");
14297 case dqw_swap_mode:
14298 oappend ("WORD PTR ");
14301 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14303 oappend ("QWORD PTR ");
14312 oappend ("QWORD PTR ");
14315 if ((sizeflag & DFLAG) || bytemode == dq_mode)
14316 oappend ("DWORD PTR ");
14318 oappend ("WORD PTR ");
14319 used_prefixes |= (prefixes & PREFIX_DATA);
14323 if ((rex & REX_W) || (sizeflag & DFLAG))
14325 oappend ("WORD PTR ");
14326 if (!(rex & REX_W))
14327 used_prefixes |= (prefixes & PREFIX_DATA);
14330 if (sizeflag & DFLAG)
14331 oappend ("QWORD PTR ");
14333 oappend ("DWORD PTR ");
14334 used_prefixes |= (prefixes & PREFIX_DATA);
14337 case d_scalar_mode:
14338 case d_scalar_swap_mode:
14341 oappend ("DWORD PTR ");
14344 case q_scalar_mode:
14345 case q_scalar_swap_mode:
14347 oappend ("QWORD PTR ");
14350 if (address_mode == mode_64bit)
14351 oappend ("QWORD PTR ");
14353 oappend ("DWORD PTR ");
14356 if (sizeflag & DFLAG)
14357 oappend ("FWORD PTR ");
14359 oappend ("DWORD PTR ");
14360 used_prefixes |= (prefixes & PREFIX_DATA);
14363 oappend ("TBYTE PTR ");
14367 case evex_x_gscat_mode:
14368 case evex_x_nobcst_mode:
14371 switch (vex.length)
14374 oappend ("XMMWORD PTR ");
14377 oappend ("YMMWORD PTR ");
14380 oappend ("ZMMWORD PTR ");
14387 oappend ("XMMWORD PTR ");
14390 oappend ("XMMWORD PTR ");
14393 oappend ("YMMWORD PTR ");
14396 case evex_half_bcst_xmmq_mode:
14400 switch (vex.length)
14403 oappend ("QWORD PTR ");
14406 oappend ("XMMWORD PTR ");
14409 oappend ("YMMWORD PTR ");
14419 switch (vex.length)
14424 oappend ("BYTE PTR ");
14434 switch (vex.length)
14439 oappend ("WORD PTR ");
14449 switch (vex.length)
14454 oappend ("DWORD PTR ");
14464 switch (vex.length)
14469 oappend ("QWORD PTR ");
14479 switch (vex.length)
14482 oappend ("WORD PTR ");
14485 oappend ("DWORD PTR ");
14488 oappend ("QWORD PTR ");
14498 switch (vex.length)
14501 oappend ("DWORD PTR ");
14504 oappend ("QWORD PTR ");
14507 oappend ("XMMWORD PTR ");
14517 switch (vex.length)
14520 oappend ("QWORD PTR ");
14523 oappend ("YMMWORD PTR ");
14526 oappend ("ZMMWORD PTR ");
14536 switch (vex.length)
14540 oappend ("XMMWORD PTR ");
14547 oappend ("OWORD PTR ");
14550 case vex_w_dq_mode:
14551 case vex_scalar_w_dq_mode:
14556 oappend ("QWORD PTR ");
14558 oappend ("DWORD PTR ");
14560 case vex_vsib_d_w_dq_mode:
14561 case vex_vsib_q_w_dq_mode:
14568 oappend ("QWORD PTR ");
14570 oappend ("DWORD PTR ");
14574 switch (vex.length)
14577 oappend ("XMMWORD PTR ");
14580 oappend ("YMMWORD PTR ");
14583 oappend ("ZMMWORD PTR ");
14590 case vex_vsib_q_w_d_mode:
14591 case vex_vsib_d_w_d_mode:
14592 if (!need_vex || !vex.evex)
14595 switch (vex.length)
14598 oappend ("QWORD PTR ");
14601 oappend ("XMMWORD PTR ");
14604 oappend ("YMMWORD PTR ");
14612 if (!need_vex || vex.length != 128)
14615 oappend ("DWORD PTR ");
14617 oappend ("BYTE PTR ");
14623 oappend ("QWORD PTR ");
14625 oappend ("WORD PTR ");
14634 OP_E_register (int bytemode, int sizeflag)
14636 int reg = modrm.rm;
14637 const char **names;
14643 if ((sizeflag & SUFFIX_ALWAYS)
14644 && (bytemode == b_swap_mode
14645 || bytemode == v_swap_mode
14646 || bytemode == dqw_swap_mode))
14672 names = address_mode == mode_64bit ? names64 : names32;
14678 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14691 case dqw_swap_mode:
14697 if ((sizeflag & DFLAG)
14698 || (bytemode != v_mode
14699 && bytemode != v_swap_mode))
14703 used_prefixes |= (prefixes & PREFIX_DATA);
14708 names = names_mask;
14713 oappend (INTERNAL_DISASSEMBLER_ERROR);
14716 oappend (names[reg]);
14720 OP_E_memory (int bytemode, int sizeflag)
14723 int add = (rex & REX_B) ? 8 : 0;
14729 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
14731 && bytemode != x_mode
14732 && bytemode != xmmq_mode
14733 && bytemode != evex_half_bcst_xmmq_mode)
14742 case dqw_swap_mode:
14749 case vex_vsib_d_w_dq_mode:
14750 case vex_vsib_d_w_d_mode:
14751 case vex_vsib_q_w_dq_mode:
14752 case vex_vsib_q_w_d_mode:
14753 case evex_x_gscat_mode:
14755 shift = vex.w ? 3 : 2;
14758 case evex_half_bcst_xmmq_mode:
14762 shift = vex.w ? 3 : 2;
14765 /* Fall through if vex.b == 0. */
14769 case evex_x_nobcst_mode:
14771 switch (vex.length)
14794 case q_scalar_mode:
14796 case q_scalar_swap_mode:
14802 case d_scalar_mode:
14804 case d_scalar_swap_mode:
14816 /* Make necessary corrections to shift for modes that need it.
14817 For these modes we currently have shift 4, 5 or 6 depending on
14818 vex.length (it corresponds to xmmword, ymmword or zmmword
14819 operand). We might want to make it 3, 4 or 5 (e.g. for
14820 xmmq_mode). In case of broadcast enabled the corrections
14821 aren't needed, as element size is always 32 or 64 bits. */
14823 && (bytemode == xmmq_mode
14824 || bytemode == evex_half_bcst_xmmq_mode))
14826 else if (bytemode == xmmqd_mode)
14828 else if (bytemode == xmmdw_mode)
14830 else if (bytemode == ymmq_mode && vex.length == 128)
14838 intel_operand_size (bytemode, sizeflag);
14841 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14843 /* 32/64 bit address mode */
14852 int addr32flag = !((sizeflag & AFLAG)
14853 || bytemode == v_bnd_mode
14854 || bytemode == bnd_mode);
14855 const char **indexes64 = names64;
14856 const char **indexes32 = names32;
14866 vindex = sib.index;
14872 case vex_vsib_d_w_dq_mode:
14873 case vex_vsib_d_w_d_mode:
14874 case vex_vsib_q_w_dq_mode:
14875 case vex_vsib_q_w_d_mode:
14885 switch (vex.length)
14888 indexes64 = indexes32 = names_xmm;
14892 || bytemode == vex_vsib_q_w_dq_mode
14893 || bytemode == vex_vsib_q_w_d_mode)
14894 indexes64 = indexes32 = names_ymm;
14896 indexes64 = indexes32 = names_xmm;
14900 || bytemode == vex_vsib_q_w_dq_mode
14901 || bytemode == vex_vsib_q_w_d_mode)
14902 indexes64 = indexes32 = names_zmm;
14904 indexes64 = indexes32 = names_ymm;
14911 haveindex = vindex != 4;
14918 rbase = base + add;
14926 if (address_mode == mode_64bit && !havesib)
14932 FETCH_DATA (the_info, codep + 1);
14934 if ((disp & 0x80) != 0)
14936 if (vex.evex && shift > 0)
14944 /* In 32bit mode, we need index register to tell [offset] from
14945 [eiz*1 + offset]. */
14946 needindex = (havesib
14949 && address_mode == mode_32bit);
14950 havedisp = (havebase
14952 || (havesib && (haveindex || scale != 0)));
14955 if (modrm.mod != 0 || base == 5)
14957 if (havedisp || riprel)
14958 print_displacement (scratchbuf, disp);
14960 print_operand_value (scratchbuf, 1, disp);
14961 oappend (scratchbuf);
14965 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
14969 if ((havebase || haveindex || riprel)
14970 && (bytemode != v_bnd_mode)
14971 && (bytemode != bnd_mode))
14972 used_prefixes |= PREFIX_ADDR;
14974 if (havedisp || (intel_syntax && riprel))
14976 *obufp++ = open_char;
14977 if (intel_syntax && riprel)
14980 oappend (sizeflag & AFLAG ? "rip" : "eip");
14984 oappend (address_mode == mode_64bit && !addr32flag
14985 ? names64[rbase] : names32[rbase]);
14988 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14989 print index to tell base + index from base. */
14993 || (havebase && base != ESP_REG_NUM))
14995 if (!intel_syntax || havebase)
14997 *obufp++ = separator_char;
15001 oappend (address_mode == mode_64bit && !addr32flag
15002 ? indexes64[vindex] : indexes32[vindex]);
15004 oappend (address_mode == mode_64bit && !addr32flag
15005 ? index64 : index32);
15007 *obufp++ = scale_char;
15009 sprintf (scratchbuf, "%d", 1 << scale);
15010 oappend (scratchbuf);
15014 && (disp || modrm.mod != 0 || base == 5))
15016 if (!havedisp || (bfd_signed_vma) disp >= 0)
15021 else if (modrm.mod != 1 && disp != -disp)
15025 disp = - (bfd_signed_vma) disp;
15029 print_displacement (scratchbuf, disp);
15031 print_operand_value (scratchbuf, 1, disp);
15032 oappend (scratchbuf);
15035 *obufp++ = close_char;
15038 else if (intel_syntax)
15040 if (modrm.mod != 0 || base == 5)
15042 if (!active_seg_prefix)
15044 oappend (names_seg[ds_reg - es_reg]);
15047 print_operand_value (scratchbuf, 1, disp);
15048 oappend (scratchbuf);
15054 /* 16 bit address mode */
15055 used_prefixes |= prefixes & PREFIX_ADDR;
15062 if ((disp & 0x8000) != 0)
15067 FETCH_DATA (the_info, codep + 1);
15069 if ((disp & 0x80) != 0)
15074 if ((disp & 0x8000) != 0)
15080 if (modrm.mod != 0 || modrm.rm == 6)
15082 print_displacement (scratchbuf, disp);
15083 oappend (scratchbuf);
15086 if (modrm.mod != 0 || modrm.rm != 6)
15088 *obufp++ = open_char;
15090 oappend (index16[modrm.rm]);
15092 && (disp || modrm.mod != 0 || modrm.rm == 6))
15094 if ((bfd_signed_vma) disp >= 0)
15099 else if (modrm.mod != 1)
15103 disp = - (bfd_signed_vma) disp;
15106 print_displacement (scratchbuf, disp);
15107 oappend (scratchbuf);
15110 *obufp++ = close_char;
15113 else if (intel_syntax)
15115 if (!active_seg_prefix)
15117 oappend (names_seg[ds_reg - es_reg]);
15120 print_operand_value (scratchbuf, 1, disp & 0xffff);
15121 oappend (scratchbuf);
15124 if (vex.evex && vex.b
15125 && (bytemode == x_mode
15126 || bytemode == xmmq_mode
15127 || bytemode == evex_half_bcst_xmmq_mode))
15130 || bytemode == xmmq_mode
15131 || bytemode == evex_half_bcst_xmmq_mode)
15133 switch (vex.length)
15136 oappend ("{1to2}");
15139 oappend ("{1to4}");
15142 oappend ("{1to8}");
15150 switch (vex.length)
15153 oappend ("{1to4}");
15156 oappend ("{1to8}");
15159 oappend ("{1to16}");
15169 OP_E (int bytemode, int sizeflag)
15171 /* Skip mod/rm byte. */
15175 if (modrm.mod == 3)
15176 OP_E_register (bytemode, sizeflag);
15178 OP_E_memory (bytemode, sizeflag);
15182 OP_G (int bytemode, int sizeflag)
15193 oappend (names8rex[modrm.reg + add]);
15195 oappend (names8[modrm.reg + add]);
15198 oappend (names16[modrm.reg + add]);
15203 oappend (names32[modrm.reg + add]);
15206 oappend (names64[modrm.reg + add]);
15209 oappend (names_bnd[modrm.reg]);
15216 case dqw_swap_mode:
15219 oappend (names64[modrm.reg + add]);
15222 if ((sizeflag & DFLAG) || bytemode != v_mode)
15223 oappend (names32[modrm.reg + add]);
15225 oappend (names16[modrm.reg + add]);
15226 used_prefixes |= (prefixes & PREFIX_DATA);
15230 if (address_mode == mode_64bit)
15231 oappend (names64[modrm.reg + add]);
15233 oappend (names32[modrm.reg + add]);
15237 oappend (names_mask[modrm.reg + add]);
15240 oappend (INTERNAL_DISASSEMBLER_ERROR);
15253 FETCH_DATA (the_info, codep + 8);
15254 a = *codep++ & 0xff;
15255 a |= (*codep++ & 0xff) << 8;
15256 a |= (*codep++ & 0xff) << 16;
15257 a |= (*codep++ & 0xff) << 24;
15258 b = *codep++ & 0xff;
15259 b |= (*codep++ & 0xff) << 8;
15260 b |= (*codep++ & 0xff) << 16;
15261 b |= (*codep++ & 0xff) << 24;
15262 x = a + ((bfd_vma) b << 32);
15270 static bfd_signed_vma
15273 bfd_signed_vma x = 0;
15275 FETCH_DATA (the_info, codep + 4);
15276 x = *codep++ & (bfd_signed_vma) 0xff;
15277 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15278 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15279 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15283 static bfd_signed_vma
15286 bfd_signed_vma x = 0;
15288 FETCH_DATA (the_info, codep + 4);
15289 x = *codep++ & (bfd_signed_vma) 0xff;
15290 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15291 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15292 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15294 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15304 FETCH_DATA (the_info, codep + 2);
15305 x = *codep++ & 0xff;
15306 x |= (*codep++ & 0xff) << 8;
15311 set_op (bfd_vma op, int riprel)
15313 op_index[op_ad] = op_ad;
15314 if (address_mode == mode_64bit)
15316 op_address[op_ad] = op;
15317 op_riprel[op_ad] = riprel;
15321 /* Mask to get a 32-bit address. */
15322 op_address[op_ad] = op & 0xffffffff;
15323 op_riprel[op_ad] = riprel & 0xffffffff;
15328 OP_REG (int code, int sizeflag)
15335 case es_reg: case ss_reg: case cs_reg:
15336 case ds_reg: case fs_reg: case gs_reg:
15337 oappend (names_seg[code - es_reg]);
15349 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15350 case sp_reg: case bp_reg: case si_reg: case di_reg:
15351 s = names16[code - ax_reg + add];
15353 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15354 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15357 s = names8rex[code - al_reg + add];
15359 s = names8[code - al_reg];
15361 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15362 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15363 if (address_mode == mode_64bit
15364 && ((sizeflag & DFLAG) || (rex & REX_W)))
15366 s = names64[code - rAX_reg + add];
15369 code += eAX_reg - rAX_reg;
15370 /* Fall through. */
15371 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15372 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15375 s = names64[code - eAX_reg + add];
15378 if (sizeflag & DFLAG)
15379 s = names32[code - eAX_reg + add];
15381 s = names16[code - eAX_reg + add];
15382 used_prefixes |= (prefixes & PREFIX_DATA);
15386 s = INTERNAL_DISASSEMBLER_ERROR;
15393 OP_IMREG (int code, int sizeflag)
15405 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15406 case sp_reg: case bp_reg: case si_reg: case di_reg:
15407 s = names16[code - ax_reg];
15409 case es_reg: case ss_reg: case cs_reg:
15410 case ds_reg: case fs_reg: case gs_reg:
15411 s = names_seg[code - es_reg];
15413 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15414 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15417 s = names8rex[code - al_reg];
15419 s = names8[code - al_reg];
15421 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15422 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15425 s = names64[code - eAX_reg];
15428 if (sizeflag & DFLAG)
15429 s = names32[code - eAX_reg];
15431 s = names16[code - eAX_reg];
15432 used_prefixes |= (prefixes & PREFIX_DATA);
15435 case z_mode_ax_reg:
15436 if ((rex & REX_W) || (sizeflag & DFLAG))
15440 if (!(rex & REX_W))
15441 used_prefixes |= (prefixes & PREFIX_DATA);
15444 s = INTERNAL_DISASSEMBLER_ERROR;
15451 OP_I (int bytemode, int sizeflag)
15454 bfd_signed_vma mask = -1;
15459 FETCH_DATA (the_info, codep + 1);
15464 if (address_mode == mode_64bit)
15469 /* Fall through. */
15476 if (sizeflag & DFLAG)
15486 used_prefixes |= (prefixes & PREFIX_DATA);
15498 oappend (INTERNAL_DISASSEMBLER_ERROR);
15503 scratchbuf[0] = '$';
15504 print_operand_value (scratchbuf + 1, 1, op);
15505 oappend_maybe_intel (scratchbuf);
15506 scratchbuf[0] = '\0';
15510 OP_I64 (int bytemode, int sizeflag)
15513 bfd_signed_vma mask = -1;
15515 if (address_mode != mode_64bit)
15517 OP_I (bytemode, sizeflag);
15524 FETCH_DATA (the_info, codep + 1);
15534 if (sizeflag & DFLAG)
15544 used_prefixes |= (prefixes & PREFIX_DATA);
15552 oappend (INTERNAL_DISASSEMBLER_ERROR);
15557 scratchbuf[0] = '$';
15558 print_operand_value (scratchbuf + 1, 1, op);
15559 oappend_maybe_intel (scratchbuf);
15560 scratchbuf[0] = '\0';
15564 OP_sI (int bytemode, int sizeflag)
15572 FETCH_DATA (the_info, codep + 1);
15574 if ((op & 0x80) != 0)
15576 if (bytemode == b_T_mode)
15578 if (address_mode != mode_64bit
15579 || !((sizeflag & DFLAG) || (rex & REX_W)))
15581 /* The operand-size prefix is overridden by a REX prefix. */
15582 if ((sizeflag & DFLAG) || (rex & REX_W))
15590 if (!(rex & REX_W))
15592 if (sizeflag & DFLAG)
15600 /* The operand-size prefix is overridden by a REX prefix. */
15601 if ((sizeflag & DFLAG) || (rex & REX_W))
15607 oappend (INTERNAL_DISASSEMBLER_ERROR);
15611 scratchbuf[0] = '$';
15612 print_operand_value (scratchbuf + 1, 1, op);
15613 oappend_maybe_intel (scratchbuf);
15617 OP_J (int bytemode, int sizeflag)
15621 bfd_vma segment = 0;
15626 FETCH_DATA (the_info, codep + 1);
15628 if ((disp & 0x80) != 0)
15633 if ((sizeflag & DFLAG) || (rex & REX_W))
15638 if ((disp & 0x8000) != 0)
15640 /* In 16bit mode, address is wrapped around at 64k within
15641 the same segment. Otherwise, a data16 prefix on a jump
15642 instruction means that the pc is masked to 16 bits after
15643 the displacement is added! */
15645 if ((prefixes & PREFIX_DATA) == 0)
15646 segment = ((start_pc + codep - start_codep)
15647 & ~((bfd_vma) 0xffff));
15649 if (!(rex & REX_W))
15650 used_prefixes |= (prefixes & PREFIX_DATA);
15653 oappend (INTERNAL_DISASSEMBLER_ERROR);
15656 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15658 print_operand_value (scratchbuf, 1, disp);
15659 oappend (scratchbuf);
15663 OP_SEG (int bytemode, int sizeflag)
15665 if (bytemode == w_mode)
15666 oappend (names_seg[modrm.reg]);
15668 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15672 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15676 if (sizeflag & DFLAG)
15686 used_prefixes |= (prefixes & PREFIX_DATA);
15688 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15690 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15691 oappend (scratchbuf);
15695 OP_OFF (int bytemode, int sizeflag)
15699 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15700 intel_operand_size (bytemode, sizeflag);
15703 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15710 if (!active_seg_prefix)
15712 oappend (names_seg[ds_reg - es_reg]);
15716 print_operand_value (scratchbuf, 1, off);
15717 oappend (scratchbuf);
15721 OP_OFF64 (int bytemode, int sizeflag)
15725 if (address_mode != mode_64bit
15726 || (prefixes & PREFIX_ADDR))
15728 OP_OFF (bytemode, sizeflag);
15732 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15733 intel_operand_size (bytemode, sizeflag);
15740 if (!active_seg_prefix)
15742 oappend (names_seg[ds_reg - es_reg]);
15746 print_operand_value (scratchbuf, 1, off);
15747 oappend (scratchbuf);
15751 ptr_reg (int code, int sizeflag)
15755 *obufp++ = open_char;
15756 used_prefixes |= (prefixes & PREFIX_ADDR);
15757 if (address_mode == mode_64bit)
15759 if (!(sizeflag & AFLAG))
15760 s = names32[code - eAX_reg];
15762 s = names64[code - eAX_reg];
15764 else if (sizeflag & AFLAG)
15765 s = names32[code - eAX_reg];
15767 s = names16[code - eAX_reg];
15769 *obufp++ = close_char;
15774 OP_ESreg (int code, int sizeflag)
15780 case 0x6d: /* insw/insl */
15781 intel_operand_size (z_mode, sizeflag);
15783 case 0xa5: /* movsw/movsl/movsq */
15784 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15785 case 0xab: /* stosw/stosl */
15786 case 0xaf: /* scasw/scasl */
15787 intel_operand_size (v_mode, sizeflag);
15790 intel_operand_size (b_mode, sizeflag);
15793 oappend_maybe_intel ("%es:");
15794 ptr_reg (code, sizeflag);
15798 OP_DSreg (int code, int sizeflag)
15804 case 0x6f: /* outsw/outsl */
15805 intel_operand_size (z_mode, sizeflag);
15807 case 0xa5: /* movsw/movsl/movsq */
15808 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15809 case 0xad: /* lodsw/lodsl/lodsq */
15810 intel_operand_size (v_mode, sizeflag);
15813 intel_operand_size (b_mode, sizeflag);
15816 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15817 default segment register DS is printed. */
15818 if (!active_seg_prefix)
15819 active_seg_prefix = PREFIX_DS;
15821 ptr_reg (code, sizeflag);
15825 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15833 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15835 all_prefixes[last_lock_prefix] = 0;
15836 used_prefixes |= PREFIX_LOCK;
15841 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15842 oappend_maybe_intel (scratchbuf);
15846 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15855 sprintf (scratchbuf, "db%d", modrm.reg + add);
15857 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15858 oappend (scratchbuf);
15862 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15864 sprintf (scratchbuf, "%%tr%d", modrm.reg);
15865 oappend_maybe_intel (scratchbuf);
15869 OP_R (int bytemode, int sizeflag)
15871 /* Skip mod/rm byte. */
15874 OP_E_register (bytemode, sizeflag);
15878 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15880 int reg = modrm.reg;
15881 const char **names;
15883 used_prefixes |= (prefixes & PREFIX_DATA);
15884 if (prefixes & PREFIX_DATA)
15893 oappend (names[reg]);
15897 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15899 int reg = modrm.reg;
15900 const char **names;
15912 && bytemode != xmm_mode
15913 && bytemode != xmmq_mode
15914 && bytemode != evex_half_bcst_xmmq_mode
15915 && bytemode != ymm_mode
15916 && bytemode != scalar_mode)
15918 switch (vex.length)
15925 || (bytemode != vex_vsib_q_w_dq_mode
15926 && bytemode != vex_vsib_q_w_d_mode))
15938 else if (bytemode == xmmq_mode
15939 || bytemode == evex_half_bcst_xmmq_mode)
15941 switch (vex.length)
15954 else if (bytemode == ymm_mode)
15958 oappend (names[reg]);
15962 OP_EM (int bytemode, int sizeflag)
15965 const char **names;
15967 if (modrm.mod != 3)
15970 && (bytemode == v_mode || bytemode == v_swap_mode))
15972 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15973 used_prefixes |= (prefixes & PREFIX_DATA);
15975 OP_E (bytemode, sizeflag);
15979 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15982 /* Skip mod/rm byte. */
15985 used_prefixes |= (prefixes & PREFIX_DATA);
15987 if (prefixes & PREFIX_DATA)
15996 oappend (names[reg]);
15999 /* cvt* are the only instructions in sse2 which have
16000 both SSE and MMX operands and also have 0x66 prefix
16001 in their opcode. 0x66 was originally used to differentiate
16002 between SSE and MMX instruction(operands). So we have to handle the
16003 cvt* separately using OP_EMC and OP_MXC */
16005 OP_EMC (int bytemode, int sizeflag)
16007 if (modrm.mod != 3)
16009 if (intel_syntax && bytemode == v_mode)
16011 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16012 used_prefixes |= (prefixes & PREFIX_DATA);
16014 OP_E (bytemode, sizeflag);
16018 /* Skip mod/rm byte. */
16021 used_prefixes |= (prefixes & PREFIX_DATA);
16022 oappend (names_mm[modrm.rm]);
16026 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16028 used_prefixes |= (prefixes & PREFIX_DATA);
16029 oappend (names_mm[modrm.reg]);
16033 OP_EX (int bytemode, int sizeflag)
16036 const char **names;
16038 /* Skip mod/rm byte. */
16042 if (modrm.mod != 3)
16044 OP_E_memory (bytemode, sizeflag);
16059 if ((sizeflag & SUFFIX_ALWAYS)
16060 && (bytemode == x_swap_mode
16061 || bytemode == d_swap_mode
16062 || bytemode == dqw_swap_mode
16063 || bytemode == d_scalar_swap_mode
16064 || bytemode == q_swap_mode
16065 || bytemode == q_scalar_swap_mode))
16069 && bytemode != xmm_mode
16070 && bytemode != xmmdw_mode
16071 && bytemode != xmmqd_mode
16072 && bytemode != xmm_mb_mode
16073 && bytemode != xmm_mw_mode
16074 && bytemode != xmm_md_mode
16075 && bytemode != xmm_mq_mode
16076 && bytemode != xmm_mdq_mode
16077 && bytemode != xmmq_mode
16078 && bytemode != evex_half_bcst_xmmq_mode
16079 && bytemode != ymm_mode
16080 && bytemode != d_scalar_mode
16081 && bytemode != d_scalar_swap_mode
16082 && bytemode != q_scalar_mode
16083 && bytemode != q_scalar_swap_mode
16084 && bytemode != vex_scalar_w_dq_mode)
16086 switch (vex.length)
16101 else if (bytemode == xmmq_mode
16102 || bytemode == evex_half_bcst_xmmq_mode)
16104 switch (vex.length)
16117 else if (bytemode == ymm_mode)
16121 oappend (names[reg]);
16125 OP_MS (int bytemode, int sizeflag)
16127 if (modrm.mod == 3)
16128 OP_EM (bytemode, sizeflag);
16134 OP_XS (int bytemode, int sizeflag)
16136 if (modrm.mod == 3)
16137 OP_EX (bytemode, sizeflag);
16143 OP_M (int bytemode, int sizeflag)
16145 if (modrm.mod == 3)
16146 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16149 OP_E (bytemode, sizeflag);
16153 OP_0f07 (int bytemode, int sizeflag)
16155 if (modrm.mod != 3 || modrm.rm != 0)
16158 OP_E (bytemode, sizeflag);
16161 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16162 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16165 NOP_Fixup1 (int bytemode, int sizeflag)
16167 if ((prefixes & PREFIX_DATA) != 0
16170 && address_mode == mode_64bit))
16171 OP_REG (bytemode, sizeflag);
16173 strcpy (obuf, "nop");
16177 NOP_Fixup2 (int bytemode, int sizeflag)
16179 if ((prefixes & PREFIX_DATA) != 0
16182 && address_mode == mode_64bit))
16183 OP_IMREG (bytemode, sizeflag);
16186 static const char *const Suffix3DNow[] = {
16187 /* 00 */ NULL, NULL, NULL, NULL,
16188 /* 04 */ NULL, NULL, NULL, NULL,
16189 /* 08 */ NULL, NULL, NULL, NULL,
16190 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
16191 /* 10 */ NULL, NULL, NULL, NULL,
16192 /* 14 */ NULL, NULL, NULL, NULL,
16193 /* 18 */ NULL, NULL, NULL, NULL,
16194 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
16195 /* 20 */ NULL, NULL, NULL, NULL,
16196 /* 24 */ NULL, NULL, NULL, NULL,
16197 /* 28 */ NULL, NULL, NULL, NULL,
16198 /* 2C */ NULL, NULL, NULL, NULL,
16199 /* 30 */ NULL, NULL, NULL, NULL,
16200 /* 34 */ NULL, NULL, NULL, NULL,
16201 /* 38 */ NULL, NULL, NULL, NULL,
16202 /* 3C */ NULL, NULL, NULL, NULL,
16203 /* 40 */ NULL, NULL, NULL, NULL,
16204 /* 44 */ NULL, NULL, NULL, NULL,
16205 /* 48 */ NULL, NULL, NULL, NULL,
16206 /* 4C */ NULL, NULL, NULL, NULL,
16207 /* 50 */ NULL, NULL, NULL, NULL,
16208 /* 54 */ NULL, NULL, NULL, NULL,
16209 /* 58 */ NULL, NULL, NULL, NULL,
16210 /* 5C */ NULL, NULL, NULL, NULL,
16211 /* 60 */ NULL, NULL, NULL, NULL,
16212 /* 64 */ NULL, NULL, NULL, NULL,
16213 /* 68 */ NULL, NULL, NULL, NULL,
16214 /* 6C */ NULL, NULL, NULL, NULL,
16215 /* 70 */ NULL, NULL, NULL, NULL,
16216 /* 74 */ NULL, NULL, NULL, NULL,
16217 /* 78 */ NULL, NULL, NULL, NULL,
16218 /* 7C */ NULL, NULL, NULL, NULL,
16219 /* 80 */ NULL, NULL, NULL, NULL,
16220 /* 84 */ NULL, NULL, NULL, NULL,
16221 /* 88 */ NULL, NULL, "pfnacc", NULL,
16222 /* 8C */ NULL, NULL, "pfpnacc", NULL,
16223 /* 90 */ "pfcmpge", NULL, NULL, NULL,
16224 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
16225 /* 98 */ NULL, NULL, "pfsub", NULL,
16226 /* 9C */ NULL, NULL, "pfadd", NULL,
16227 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
16228 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
16229 /* A8 */ NULL, NULL, "pfsubr", NULL,
16230 /* AC */ NULL, NULL, "pfacc", NULL,
16231 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
16232 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
16233 /* B8 */ NULL, NULL, NULL, "pswapd",
16234 /* BC */ NULL, NULL, NULL, "pavgusb",
16235 /* C0 */ NULL, NULL, NULL, NULL,
16236 /* C4 */ NULL, NULL, NULL, NULL,
16237 /* C8 */ NULL, NULL, NULL, NULL,
16238 /* CC */ NULL, NULL, NULL, NULL,
16239 /* D0 */ NULL, NULL, NULL, NULL,
16240 /* D4 */ NULL, NULL, NULL, NULL,
16241 /* D8 */ NULL, NULL, NULL, NULL,
16242 /* DC */ NULL, NULL, NULL, NULL,
16243 /* E0 */ NULL, NULL, NULL, NULL,
16244 /* E4 */ NULL, NULL, NULL, NULL,
16245 /* E8 */ NULL, NULL, NULL, NULL,
16246 /* EC */ NULL, NULL, NULL, NULL,
16247 /* F0 */ NULL, NULL, NULL, NULL,
16248 /* F4 */ NULL, NULL, NULL, NULL,
16249 /* F8 */ NULL, NULL, NULL, NULL,
16250 /* FC */ NULL, NULL, NULL, NULL,
16254 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16256 const char *mnemonic;
16258 FETCH_DATA (the_info, codep + 1);
16259 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16260 place where an 8-bit immediate would normally go. ie. the last
16261 byte of the instruction. */
16262 obufp = mnemonicendp;
16263 mnemonic = Suffix3DNow[*codep++ & 0xff];
16265 oappend (mnemonic);
16268 /* Since a variable sized modrm/sib chunk is between the start
16269 of the opcode (0x0f0f) and the opcode suffix, we need to do
16270 all the modrm processing first, and don't know until now that
16271 we have a bad opcode. This necessitates some cleaning up. */
16272 op_out[0][0] = '\0';
16273 op_out[1][0] = '\0';
16276 mnemonicendp = obufp;
16279 static struct op simd_cmp_op[] =
16281 { STRING_COMMA_LEN ("eq") },
16282 { STRING_COMMA_LEN ("lt") },
16283 { STRING_COMMA_LEN ("le") },
16284 { STRING_COMMA_LEN ("unord") },
16285 { STRING_COMMA_LEN ("neq") },
16286 { STRING_COMMA_LEN ("nlt") },
16287 { STRING_COMMA_LEN ("nle") },
16288 { STRING_COMMA_LEN ("ord") }
16292 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16294 unsigned int cmp_type;
16296 FETCH_DATA (the_info, codep + 1);
16297 cmp_type = *codep++ & 0xff;
16298 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16301 char *p = mnemonicendp - 2;
16305 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16306 mnemonicendp += simd_cmp_op[cmp_type].len;
16310 /* We have a reserved extension byte. Output it directly. */
16311 scratchbuf[0] = '$';
16312 print_operand_value (scratchbuf + 1, 1, cmp_type);
16313 oappend_maybe_intel (scratchbuf);
16314 scratchbuf[0] = '\0';
16319 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16320 int sizeflag ATTRIBUTE_UNUSED)
16322 /* mwait %eax,%ecx */
16325 const char **names = (address_mode == mode_64bit
16326 ? names64 : names32);
16327 strcpy (op_out[0], names[0]);
16328 strcpy (op_out[1], names[1]);
16329 two_source_ops = 1;
16331 /* Skip mod/rm byte. */
16337 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16338 int sizeflag ATTRIBUTE_UNUSED)
16340 /* monitor %eax,%ecx,%edx" */
16343 const char **op1_names;
16344 const char **names = (address_mode == mode_64bit
16345 ? names64 : names32);
16347 if (!(prefixes & PREFIX_ADDR))
16348 op1_names = (address_mode == mode_16bit
16349 ? names16 : names);
16352 /* Remove "addr16/addr32". */
16353 all_prefixes[last_addr_prefix] = 0;
16354 op1_names = (address_mode != mode_32bit
16355 ? names32 : names16);
16356 used_prefixes |= PREFIX_ADDR;
16358 strcpy (op_out[0], op1_names[0]);
16359 strcpy (op_out[1], names[1]);
16360 strcpy (op_out[2], names[2]);
16361 two_source_ops = 1;
16363 /* Skip mod/rm byte. */
16371 /* Throw away prefixes and 1st. opcode byte. */
16372 codep = insn_codep + 1;
16377 REP_Fixup (int bytemode, int sizeflag)
16379 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16381 if (prefixes & PREFIX_REPZ)
16382 all_prefixes[last_repz_prefix] = REP_PREFIX;
16389 OP_IMREG (bytemode, sizeflag);
16392 OP_ESreg (bytemode, sizeflag);
16395 OP_DSreg (bytemode, sizeflag);
16403 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16407 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16409 if (prefixes & PREFIX_REPNZ)
16410 all_prefixes[last_repnz_prefix] = BND_PREFIX;
16413 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16414 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16418 HLE_Fixup1 (int bytemode, int sizeflag)
16421 && (prefixes & PREFIX_LOCK) != 0)
16423 if (prefixes & PREFIX_REPZ)
16424 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16425 if (prefixes & PREFIX_REPNZ)
16426 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16429 OP_E (bytemode, sizeflag);
16432 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16433 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16437 HLE_Fixup2 (int bytemode, int sizeflag)
16439 if (modrm.mod != 3)
16441 if (prefixes & PREFIX_REPZ)
16442 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16443 if (prefixes & PREFIX_REPNZ)
16444 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16447 OP_E (bytemode, sizeflag);
16450 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16451 "xrelease" for memory operand. No check for LOCK prefix. */
16454 HLE_Fixup3 (int bytemode, int sizeflag)
16457 && last_repz_prefix > last_repnz_prefix
16458 && (prefixes & PREFIX_REPZ) != 0)
16459 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16461 OP_E (bytemode, sizeflag);
16465 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16470 /* Change cmpxchg8b to cmpxchg16b. */
16471 char *p = mnemonicendp - 2;
16472 mnemonicendp = stpcpy (p, "16b");
16475 else if ((prefixes & PREFIX_LOCK) != 0)
16477 if (prefixes & PREFIX_REPZ)
16478 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16479 if (prefixes & PREFIX_REPNZ)
16480 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16483 OP_M (bytemode, sizeflag);
16487 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16489 const char **names;
16493 switch (vex.length)
16507 oappend (names[reg]);
16511 CRC32_Fixup (int bytemode, int sizeflag)
16513 /* Add proper suffix to "crc32". */
16514 char *p = mnemonicendp;
16533 if (sizeflag & DFLAG)
16537 used_prefixes |= (prefixes & PREFIX_DATA);
16541 oappend (INTERNAL_DISASSEMBLER_ERROR);
16548 if (modrm.mod == 3)
16552 /* Skip mod/rm byte. */
16557 add = (rex & REX_B) ? 8 : 0;
16558 if (bytemode == b_mode)
16562 oappend (names8rex[modrm.rm + add]);
16564 oappend (names8[modrm.rm + add]);
16570 oappend (names64[modrm.rm + add]);
16571 else if ((prefixes & PREFIX_DATA))
16572 oappend (names16[modrm.rm + add]);
16574 oappend (names32[modrm.rm + add]);
16578 OP_E (bytemode, sizeflag);
16582 FXSAVE_Fixup (int bytemode, int sizeflag)
16584 /* Add proper suffix to "fxsave" and "fxrstor". */
16588 char *p = mnemonicendp;
16594 OP_M (bytemode, sizeflag);
16597 /* Display the destination register operand for instructions with
16601 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16604 const char **names;
16612 reg = vex.register_specifier;
16619 if (bytemode == vex_scalar_mode)
16621 oappend (names_xmm[reg]);
16625 switch (vex.length)
16632 case vex_vsib_q_w_dq_mode:
16633 case vex_vsib_q_w_d_mode:
16644 names = names_mask;
16658 case vex_vsib_q_w_dq_mode:
16659 case vex_vsib_q_w_d_mode:
16660 names = vex.w ? names_ymm : names_xmm;
16664 names = names_mask;
16678 oappend (names[reg]);
16681 /* Get the VEX immediate byte without moving codep. */
16683 static unsigned char
16684 get_vex_imm8 (int sizeflag, int opnum)
16686 int bytes_before_imm = 0;
16688 if (modrm.mod != 3)
16690 /* There are SIB/displacement bytes. */
16691 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16693 /* 32/64 bit address mode */
16694 int base = modrm.rm;
16696 /* Check SIB byte. */
16699 FETCH_DATA (the_info, codep + 1);
16701 /* When decoding the third source, don't increase
16702 bytes_before_imm as this has already been incremented
16703 by one in OP_E_memory while decoding the second
16706 bytes_before_imm++;
16709 /* Don't increase bytes_before_imm when decoding the third source,
16710 it has already been incremented by OP_E_memory while decoding
16711 the second source operand. */
16717 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16718 SIB == 5, there is a 4 byte displacement. */
16720 /* No displacement. */
16723 /* 4 byte displacement. */
16724 bytes_before_imm += 4;
16727 /* 1 byte displacement. */
16728 bytes_before_imm++;
16735 /* 16 bit address mode */
16736 /* Don't increase bytes_before_imm when decoding the third source,
16737 it has already been incremented by OP_E_memory while decoding
16738 the second source operand. */
16744 /* When modrm.rm == 6, there is a 2 byte displacement. */
16746 /* No displacement. */
16749 /* 2 byte displacement. */
16750 bytes_before_imm += 2;
16753 /* 1 byte displacement: when decoding the third source,
16754 don't increase bytes_before_imm as this has already
16755 been incremented by one in OP_E_memory while decoding
16756 the second source operand. */
16758 bytes_before_imm++;
16766 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16767 return codep [bytes_before_imm];
16771 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16773 const char **names;
16775 if (reg == -1 && modrm.mod != 3)
16777 OP_E_memory (bytemode, sizeflag);
16789 else if (reg > 7 && address_mode != mode_64bit)
16793 switch (vex.length)
16804 oappend (names[reg]);
16808 OP_EX_VexImmW (int bytemode, int sizeflag)
16811 static unsigned char vex_imm8;
16813 if (vex_w_done == 0)
16817 /* Skip mod/rm byte. */
16821 vex_imm8 = get_vex_imm8 (sizeflag, 0);
16824 reg = vex_imm8 >> 4;
16826 OP_EX_VexReg (bytemode, sizeflag, reg);
16828 else if (vex_w_done == 1)
16833 reg = vex_imm8 >> 4;
16835 OP_EX_VexReg (bytemode, sizeflag, reg);
16839 /* Output the imm8 directly. */
16840 scratchbuf[0] = '$';
16841 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16842 oappend_maybe_intel (scratchbuf);
16843 scratchbuf[0] = '\0';
16849 OP_Vex_2src (int bytemode, int sizeflag)
16851 if (modrm.mod == 3)
16853 int reg = modrm.rm;
16857 oappend (names_xmm[reg]);
16862 && (bytemode == v_mode || bytemode == v_swap_mode))
16864 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16865 used_prefixes |= (prefixes & PREFIX_DATA);
16867 OP_E (bytemode, sizeflag);
16872 OP_Vex_2src_1 (int bytemode, int sizeflag)
16874 if (modrm.mod == 3)
16876 /* Skip mod/rm byte. */
16882 oappend (names_xmm[vex.register_specifier]);
16884 OP_Vex_2src (bytemode, sizeflag);
16888 OP_Vex_2src_2 (int bytemode, int sizeflag)
16891 OP_Vex_2src (bytemode, sizeflag);
16893 oappend (names_xmm[vex.register_specifier]);
16897 OP_EX_VexW (int bytemode, int sizeflag)
16905 /* Skip mod/rm byte. */
16910 reg = get_vex_imm8 (sizeflag, 0) >> 4;
16915 reg = get_vex_imm8 (sizeflag, 1) >> 4;
16918 OP_EX_VexReg (bytemode, sizeflag, reg);
16922 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16923 int sizeflag ATTRIBUTE_UNUSED)
16925 /* Skip the immediate byte and check for invalid bits. */
16926 FETCH_DATA (the_info, codep + 1);
16927 if (*codep++ & 0xf)
16932 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16935 const char **names;
16937 FETCH_DATA (the_info, codep + 1);
16940 if (bytemode != x_mode)
16947 if (reg > 7 && address_mode != mode_64bit)
16950 switch (vex.length)
16961 oappend (names[reg]);
16965 OP_XMM_VexW (int bytemode, int sizeflag)
16967 /* Turn off the REX.W bit since it is used for swapping operands
16970 OP_XMM (bytemode, sizeflag);
16974 OP_EX_Vex (int bytemode, int sizeflag)
16976 if (modrm.mod != 3)
16978 if (vex.register_specifier != 0)
16982 OP_EX (bytemode, sizeflag);
16986 OP_XMM_Vex (int bytemode, int sizeflag)
16988 if (modrm.mod != 3)
16990 if (vex.register_specifier != 0)
16994 OP_XMM (bytemode, sizeflag);
16998 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17000 switch (vex.length)
17003 mnemonicendp = stpcpy (obuf, "vzeroupper");
17006 mnemonicendp = stpcpy (obuf, "vzeroall");
17013 static struct op vex_cmp_op[] =
17015 { STRING_COMMA_LEN ("eq") },
17016 { STRING_COMMA_LEN ("lt") },
17017 { STRING_COMMA_LEN ("le") },
17018 { STRING_COMMA_LEN ("unord") },
17019 { STRING_COMMA_LEN ("neq") },
17020 { STRING_COMMA_LEN ("nlt") },
17021 { STRING_COMMA_LEN ("nle") },
17022 { STRING_COMMA_LEN ("ord") },
17023 { STRING_COMMA_LEN ("eq_uq") },
17024 { STRING_COMMA_LEN ("nge") },
17025 { STRING_COMMA_LEN ("ngt") },
17026 { STRING_COMMA_LEN ("false") },
17027 { STRING_COMMA_LEN ("neq_oq") },
17028 { STRING_COMMA_LEN ("ge") },
17029 { STRING_COMMA_LEN ("gt") },
17030 { STRING_COMMA_LEN ("true") },
17031 { STRING_COMMA_LEN ("eq_os") },
17032 { STRING_COMMA_LEN ("lt_oq") },
17033 { STRING_COMMA_LEN ("le_oq") },
17034 { STRING_COMMA_LEN ("unord_s") },
17035 { STRING_COMMA_LEN ("neq_us") },
17036 { STRING_COMMA_LEN ("nlt_uq") },
17037 { STRING_COMMA_LEN ("nle_uq") },
17038 { STRING_COMMA_LEN ("ord_s") },
17039 { STRING_COMMA_LEN ("eq_us") },
17040 { STRING_COMMA_LEN ("nge_uq") },
17041 { STRING_COMMA_LEN ("ngt_uq") },
17042 { STRING_COMMA_LEN ("false_os") },
17043 { STRING_COMMA_LEN ("neq_os") },
17044 { STRING_COMMA_LEN ("ge_oq") },
17045 { STRING_COMMA_LEN ("gt_oq") },
17046 { STRING_COMMA_LEN ("true_us") },
17050 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17052 unsigned int cmp_type;
17054 FETCH_DATA (the_info, codep + 1);
17055 cmp_type = *codep++ & 0xff;
17056 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17059 char *p = mnemonicendp - 2;
17063 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17064 mnemonicendp += vex_cmp_op[cmp_type].len;
17068 /* We have a reserved extension byte. Output it directly. */
17069 scratchbuf[0] = '$';
17070 print_operand_value (scratchbuf + 1, 1, cmp_type);
17071 oappend_maybe_intel (scratchbuf);
17072 scratchbuf[0] = '\0';
17077 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17078 int sizeflag ATTRIBUTE_UNUSED)
17080 unsigned int cmp_type;
17085 FETCH_DATA (the_info, codep + 1);
17086 cmp_type = *codep++ & 0xff;
17087 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17088 If it's the case, print suffix, otherwise - print the immediate. */
17089 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17094 char *p = mnemonicendp - 2;
17096 /* vpcmp* can have both one- and two-lettered suffix. */
17110 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17111 mnemonicendp += simd_cmp_op[cmp_type].len;
17115 /* We have a reserved extension byte. Output it directly. */
17116 scratchbuf[0] = '$';
17117 print_operand_value (scratchbuf + 1, 1, cmp_type);
17118 oappend_maybe_intel (scratchbuf);
17119 scratchbuf[0] = '\0';
17123 static const struct op pclmul_op[] =
17125 { STRING_COMMA_LEN ("lql") },
17126 { STRING_COMMA_LEN ("hql") },
17127 { STRING_COMMA_LEN ("lqh") },
17128 { STRING_COMMA_LEN ("hqh") }
17132 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17133 int sizeflag ATTRIBUTE_UNUSED)
17135 unsigned int pclmul_type;
17137 FETCH_DATA (the_info, codep + 1);
17138 pclmul_type = *codep++ & 0xff;
17139 switch (pclmul_type)
17150 if (pclmul_type < ARRAY_SIZE (pclmul_op))
17153 char *p = mnemonicendp - 3;
17158 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17159 mnemonicendp += pclmul_op[pclmul_type].len;
17163 /* We have a reserved extension byte. Output it directly. */
17164 scratchbuf[0] = '$';
17165 print_operand_value (scratchbuf + 1, 1, pclmul_type);
17166 oappend_maybe_intel (scratchbuf);
17167 scratchbuf[0] = '\0';
17172 MOVBE_Fixup (int bytemode, int sizeflag)
17174 /* Add proper suffix to "movbe". */
17175 char *p = mnemonicendp;
17184 if (sizeflag & SUFFIX_ALWAYS)
17190 if (sizeflag & DFLAG)
17194 used_prefixes |= (prefixes & PREFIX_DATA);
17199 oappend (INTERNAL_DISASSEMBLER_ERROR);
17206 OP_M (bytemode, sizeflag);
17210 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17213 const char **names;
17215 /* Skip mod/rm byte. */
17229 oappend (names[reg]);
17233 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17235 const char **names;
17242 oappend (names[vex.register_specifier]);
17246 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17249 || (bytemode != mask_mode && bytemode != mask_bd_mode))
17253 if ((rex & REX_R) != 0 || !vex.r)
17259 oappend (names_mask [modrm.reg]);
17263 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17266 || (bytemode != evex_rounding_mode
17267 && bytemode != evex_sae_mode))
17269 if (modrm.mod == 3 && vex.b)
17272 case evex_rounding_mode:
17273 oappend (names_rounding[vex.ll]);
17275 case evex_sae_mode: