1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
30 /* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
40 #include "opcode/i386.h"
41 #include "libiberty.h"
45 static int fetch_data (struct disassemble_info *, bfd_byte *);
46 static void ckprefix (void);
47 static const char *prefix_name (int, int);
48 static int print_insn (bfd_vma, disassemble_info *);
49 static void dofloat (int);
50 static void OP_ST (int, int);
51 static void OP_STi (int, int);
52 static int putop (const char *, int);
53 static void oappend (const char *);
54 static void append_seg (void);
55 static void OP_indirE (int, int);
56 static void print_operand_value (char *, int, bfd_vma);
57 static void OP_E_register (int, int);
58 static void OP_E_memory (int, int);
59 static void OP_E_extended (int, int);
60 static void print_displacement (char *, bfd_vma);
61 static void OP_E (int, int);
62 static void OP_G (int, int);
63 static bfd_vma get64 (void);
64 static bfd_signed_vma get32 (void);
65 static bfd_signed_vma get32s (void);
66 static int get16 (void);
67 static void set_op (bfd_vma, int);
68 static void OP_Skip_MODRM (int, int);
69 static void OP_REG (int, int);
70 static void OP_IMREG (int, int);
71 static void OP_I (int, int);
72 static void OP_I64 (int, int);
73 static void OP_sI (int, int);
74 static void OP_J (int, int);
75 static void OP_SEG (int, int);
76 static void OP_DIR (int, int);
77 static void OP_OFF (int, int);
78 static void OP_OFF64 (int, int);
79 static void ptr_reg (int, int);
80 static void OP_ESreg (int, int);
81 static void OP_DSreg (int, int);
82 static void OP_C (int, int);
83 static void OP_D (int, int);
84 static void OP_T (int, int);
85 static void OP_R (int, int);
86 static void OP_MMX (int, int);
87 static void OP_XMM (int, int);
88 static void OP_EM (int, int);
89 static void OP_EX (int, int);
90 static void OP_EMC (int,int);
91 static void OP_MXC (int,int);
92 static void OP_MS (int, int);
93 static void OP_XS (int, int);
94 static void OP_M (int, int);
95 static void OP_VEX (int, int);
96 static void OP_VEX_FMA (int, int);
97 static void OP_EX_Vex (int, int);
98 static void OP_EX_VexW (int, int);
99 static void OP_XMM_Vex (int, int);
100 static void OP_XMM_VexW (int, int);
101 static void OP_REG_VexI4 (int, int);
102 static void PCLMUL_Fixup (int, int);
103 static void VEXI4_Fixup (int, int);
104 static void VZERO_Fixup (int, int);
105 static void VCMP_Fixup (int, int);
106 static void OP_0f07 (int, int);
107 static void OP_Monitor (int, int);
108 static void OP_Mwait (int, int);
109 static void NOP_Fixup1 (int, int);
110 static void NOP_Fixup2 (int, int);
111 static void OP_3DNowSuffix (int, int);
112 static void CMP_Fixup (int, int);
113 static void BadOp (void);
114 static void REP_Fixup (int, int);
115 static void CMPXCHG8B_Fixup (int, int);
116 static void XMM_Fixup (int, int);
117 static void CRC32_Fixup (int, int);
119 static void MOVBE_Fixup (int, int);
122 /* Points to first byte not fetched. */
123 bfd_byte *max_fetched;
124 bfd_byte the_buffer[MAX_MNEM_SIZE];
137 enum address_mode address_mode;
139 /* Flags for the prefixes for the current instruction. See below. */
142 /* REX prefix the current instruction. See below. */
144 /* Bits of REX we've already used. */
146 /* Original REX prefix. */
147 static int rex_original;
148 /* REX bits in original REX prefix ignored. It may not be the same
149 as rex_original since some bits may not be ignored. */
150 static int rex_ignored;
151 /* Mark parts used in the REX prefix. When we are testing for
152 empty prefix (for 8bit register REX extension), just mask it
153 out. Otherwise test for REX bit is excuse for existence of REX
154 only in case value is nonzero. */
155 #define USED_REX(value) \
160 rex_used |= (value) | REX_OPCODE; \
163 rex_used |= REX_OPCODE; \
166 /* Flags for prefixes which we somehow handled when printing the
167 current instruction. */
168 static int used_prefixes;
170 /* Flags stored in PREFIXES. */
171 #define PREFIX_REPZ 1
172 #define PREFIX_REPNZ 2
173 #define PREFIX_LOCK 4
175 #define PREFIX_SS 0x10
176 #define PREFIX_DS 0x20
177 #define PREFIX_ES 0x40
178 #define PREFIX_FS 0x80
179 #define PREFIX_GS 0x100
180 #define PREFIX_DATA 0x200
181 #define PREFIX_ADDR 0x400
182 #define PREFIX_FWAIT 0x800
184 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
185 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
187 #define FETCH_DATA(info, addr) \
188 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
189 ? 1 : fetch_data ((info), (addr)))
192 fetch_data (struct disassemble_info *info, bfd_byte *addr)
195 struct dis_private *priv = (struct dis_private *) info->private_data;
196 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
198 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
199 status = (*info->read_memory_func) (start,
201 addr - priv->max_fetched,
207 /* If we did manage to read at least one byte, then
208 print_insn_i386 will do something sensible. Otherwise, print
209 an error. We do that here because this is where we know
211 if (priv->max_fetched == priv->the_buffer)
212 (*info->memory_error_func) (status, start, info);
213 longjmp (priv->bailout, 1);
216 priv->max_fetched = addr;
220 #define XX { NULL, 0 }
222 #define Eb { OP_E, b_mode }
223 #define EbS { OP_E, b_swap_mode }
224 #define Ev { OP_E, v_mode }
225 #define EvS { OP_E, v_swap_mode }
226 #define Ed { OP_E, d_mode }
227 #define Edq { OP_E, dq_mode }
228 #define Edqw { OP_E, dqw_mode }
229 #define Edqb { OP_E, dqb_mode }
230 #define Edqd { OP_E, dqd_mode }
231 #define Eq { OP_E, q_mode }
232 #define indirEv { OP_indirE, stack_v_mode }
233 #define indirEp { OP_indirE, f_mode }
234 #define stackEv { OP_E, stack_v_mode }
235 #define Em { OP_E, m_mode }
236 #define Ew { OP_E, w_mode }
237 #define M { OP_M, 0 } /* lea, lgdt, etc. */
238 #define Ma { OP_M, a_mode }
239 #define Mb { OP_M, b_mode }
240 #define Md { OP_M, d_mode }
241 #define Mo { OP_M, o_mode }
242 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
243 #define Mq { OP_M, q_mode }
244 #define Mx { OP_M, x_mode }
245 #define Mxmm { OP_M, xmm_mode }
246 #define Gb { OP_G, b_mode }
247 #define Gv { OP_G, v_mode }
248 #define Gd { OP_G, d_mode }
249 #define Gdq { OP_G, dq_mode }
250 #define Gm { OP_G, m_mode }
251 #define Gw { OP_G, w_mode }
252 #define Rd { OP_R, d_mode }
253 #define Rm { OP_R, m_mode }
254 #define Ib { OP_I, b_mode }
255 #define sIb { OP_sI, b_mode } /* sign extened byte */
256 #define Iv { OP_I, v_mode }
257 #define Iq { OP_I, q_mode }
258 #define Iv64 { OP_I64, v_mode }
259 #define Iw { OP_I, w_mode }
260 #define I1 { OP_I, const_1_mode }
261 #define Jb { OP_J, b_mode }
262 #define Jv { OP_J, v_mode }
263 #define Cm { OP_C, m_mode }
264 #define Dm { OP_D, m_mode }
265 #define Td { OP_T, d_mode }
266 #define Skip_MODRM { OP_Skip_MODRM, 0 }
268 #define RMeAX { OP_REG, eAX_reg }
269 #define RMeBX { OP_REG, eBX_reg }
270 #define RMeCX { OP_REG, eCX_reg }
271 #define RMeDX { OP_REG, eDX_reg }
272 #define RMeSP { OP_REG, eSP_reg }
273 #define RMeBP { OP_REG, eBP_reg }
274 #define RMeSI { OP_REG, eSI_reg }
275 #define RMeDI { OP_REG, eDI_reg }
276 #define RMrAX { OP_REG, rAX_reg }
277 #define RMrBX { OP_REG, rBX_reg }
278 #define RMrCX { OP_REG, rCX_reg }
279 #define RMrDX { OP_REG, rDX_reg }
280 #define RMrSP { OP_REG, rSP_reg }
281 #define RMrBP { OP_REG, rBP_reg }
282 #define RMrSI { OP_REG, rSI_reg }
283 #define RMrDI { OP_REG, rDI_reg }
284 #define RMAL { OP_REG, al_reg }
285 #define RMAL { OP_REG, al_reg }
286 #define RMCL { OP_REG, cl_reg }
287 #define RMDL { OP_REG, dl_reg }
288 #define RMBL { OP_REG, bl_reg }
289 #define RMAH { OP_REG, ah_reg }
290 #define RMCH { OP_REG, ch_reg }
291 #define RMDH { OP_REG, dh_reg }
292 #define RMBH { OP_REG, bh_reg }
293 #define RMAX { OP_REG, ax_reg }
294 #define RMDX { OP_REG, dx_reg }
296 #define eAX { OP_IMREG, eAX_reg }
297 #define eBX { OP_IMREG, eBX_reg }
298 #define eCX { OP_IMREG, eCX_reg }
299 #define eDX { OP_IMREG, eDX_reg }
300 #define eSP { OP_IMREG, eSP_reg }
301 #define eBP { OP_IMREG, eBP_reg }
302 #define eSI { OP_IMREG, eSI_reg }
303 #define eDI { OP_IMREG, eDI_reg }
304 #define AL { OP_IMREG, al_reg }
305 #define CL { OP_IMREG, cl_reg }
306 #define DL { OP_IMREG, dl_reg }
307 #define BL { OP_IMREG, bl_reg }
308 #define AH { OP_IMREG, ah_reg }
309 #define CH { OP_IMREG, ch_reg }
310 #define DH { OP_IMREG, dh_reg }
311 #define BH { OP_IMREG, bh_reg }
312 #define AX { OP_IMREG, ax_reg }
313 #define DX { OP_IMREG, dx_reg }
314 #define zAX { OP_IMREG, z_mode_ax_reg }
315 #define indirDX { OP_IMREG, indir_dx_reg }
317 #define Sw { OP_SEG, w_mode }
318 #define Sv { OP_SEG, v_mode }
319 #define Ap { OP_DIR, 0 }
320 #define Ob { OP_OFF64, b_mode }
321 #define Ov { OP_OFF64, v_mode }
322 #define Xb { OP_DSreg, eSI_reg }
323 #define Xv { OP_DSreg, eSI_reg }
324 #define Xz { OP_DSreg, eSI_reg }
325 #define Yb { OP_ESreg, eDI_reg }
326 #define Yv { OP_ESreg, eDI_reg }
327 #define DSBX { OP_DSreg, eBX_reg }
329 #define es { OP_REG, es_reg }
330 #define ss { OP_REG, ss_reg }
331 #define cs { OP_REG, cs_reg }
332 #define ds { OP_REG, ds_reg }
333 #define fs { OP_REG, fs_reg }
334 #define gs { OP_REG, gs_reg }
336 #define MX { OP_MMX, 0 }
337 #define XM { OP_XMM, 0 }
338 #define XMM { OP_XMM, xmm_mode }
339 #define EM { OP_EM, v_mode }
340 #define EMS { OP_EM, v_swap_mode }
341 #define EMd { OP_EM, d_mode }
342 #define EMx { OP_EM, x_mode }
343 #define EXw { OP_EX, w_mode }
344 #define EXd { OP_EX, d_mode }
345 #define EXdS { OP_EX, d_swap_mode }
346 #define EXq { OP_EX, q_mode }
347 #define EXqS { OP_EX, q_swap_mode }
348 #define EXx { OP_EX, x_mode }
349 #define EXxS { OP_EX, x_swap_mode }
350 #define EXxmm { OP_EX, xmm_mode }
351 #define EXxmmq { OP_EX, xmmq_mode }
352 #define EXymmq { OP_EX, ymmq_mode }
353 #define EXVexWdq { OP_EX, vex_w_dq_mode }
354 #define MS { OP_MS, v_mode }
355 #define XS { OP_XS, v_mode }
356 #define EMCq { OP_EMC, q_mode }
357 #define MXC { OP_MXC, 0 }
358 #define OPSUF { OP_3DNowSuffix, 0 }
359 #define CMP { CMP_Fixup, 0 }
360 #define XMM0 { XMM_Fixup, 0 }
362 #define Vex { OP_VEX, vex_mode }
363 #define Vex128 { OP_VEX, vex128_mode }
364 #define Vex256 { OP_VEX, vex256_mode }
365 #define VexI4 { VEXI4_Fixup, 0}
366 #define VexFMA { OP_VEX_FMA, vex_mode }
367 #define Vex128FMA { OP_VEX_FMA, vex128_mode }
368 #define EXdVex { OP_EX_Vex, d_mode }
369 #define EXdVexS { OP_EX_Vex, d_swap_mode }
370 #define EXqVex { OP_EX_Vex, q_mode }
371 #define EXqVexS { OP_EX_Vex, q_swap_mode }
372 #define EXVexW { OP_EX_VexW, x_mode }
373 #define EXdVexW { OP_EX_VexW, d_mode }
374 #define EXqVexW { OP_EX_VexW, q_mode }
375 #define XMVex { OP_XMM_Vex, 0 }
376 #define XMVexW { OP_XMM_VexW, 0 }
377 #define XMVexI4 { OP_REG_VexI4, x_mode }
378 #define PCLMUL { PCLMUL_Fixup, 0 }
379 #define VZERO { VZERO_Fixup, 0 }
380 #define VCMP { VCMP_Fixup, 0 }
382 /* Used handle "rep" prefix for string instructions. */
383 #define Xbr { REP_Fixup, eSI_reg }
384 #define Xvr { REP_Fixup, eSI_reg }
385 #define Ybr { REP_Fixup, eDI_reg }
386 #define Yvr { REP_Fixup, eDI_reg }
387 #define Yzr { REP_Fixup, eDI_reg }
388 #define indirDXr { REP_Fixup, indir_dx_reg }
389 #define ALr { REP_Fixup, al_reg }
390 #define eAXr { REP_Fixup, eAX_reg }
392 #define cond_jump_flag { NULL, cond_jump_mode }
393 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
395 /* bits in sizeflag */
396 #define SUFFIX_ALWAYS 4
404 /* byte operand with operand swapped */
405 b_swap_mode = b_mode + 1,
406 /* operand size depends on prefixes */
407 v_mode = b_swap_mode + 1,
408 /* operand size depends on prefixes with operand swapped */
409 v_swap_mode = v_mode + 1,
411 w_mode = v_swap_mode + 1,
412 /* double word operand */
414 /* double word operand with operand swapped */
415 d_swap_mode = d_mode + 1,
416 /* quad word operand */
417 q_mode = d_swap_mode + 1,
418 /* quad word operand with operand swapped */
419 q_swap_mode = q_mode + 1,
420 /* ten-byte operand */
421 t_mode = q_swap_mode + 1,
422 /* 16-byte XMM or 32-byte YMM operand */
424 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
425 x_swap_mode = x_mode + 1,
426 /* 16-byte XMM operand */
427 xmm_mode = x_swap_mode + 1,
428 /* 16-byte XMM or quad word operand */
429 xmmq_mode = xmm_mode + 1,
430 /* 32-byte YMM or quad word operand */
431 ymmq_mode = xmmq_mode + 1,
432 /* d_mode in 32bit, q_mode in 64bit mode. */
433 m_mode = ymmq_mode + 1,
434 /* pair of v_mode operands */
436 cond_jump_mode = a_mode + 1,
437 loop_jcxz_mode = cond_jump_mode + 1,
438 /* operand size depends on REX prefixes. */
439 dq_mode = loop_jcxz_mode + 1,
440 /* registers like dq_mode, memory like w_mode. */
441 dqw_mode = dq_mode + 1,
442 /* 4- or 6-byte pointer operand */
443 f_mode = dqw_mode + 1,
444 const_1_mode = f_mode + 1,
445 /* v_mode for stack-related opcodes. */
446 stack_v_mode = const_1_mode + 1,
447 /* non-quad operand size depends on prefixes */
448 z_mode = stack_v_mode + 1,
449 /* 16-byte operand */
451 /* registers like dq_mode, memory like b_mode. */
452 dqb_mode = o_mode + 1,
453 /* registers like dq_mode, memory like d_mode. */
454 dqd_mode = dqb_mode + 1,
455 /* normal vex mode */
456 vex_mode = dqd_mode + 1,
457 /* 128bit vex mode */
458 vex128_mode = vex_mode + 1,
459 /* 256bit vex mode */
460 vex256_mode = vex128_mode + 1,
461 /* operand size depends on the VEX.W bit. */
462 vex_w_dq_mode = vex256_mode + 1,
464 es_reg = vex_w_dq_mode + 1,
471 eAX_reg = gs_reg + 1,
472 eCX_reg = eAX_reg + 1,
473 eDX_reg = eCX_reg + 1,
474 eBX_reg = eDX_reg + 1,
475 eSP_reg = eBX_reg + 1,
476 eBP_reg = eSP_reg + 1,
477 eSI_reg = eBP_reg + 1,
478 eDI_reg = eSI_reg + 1,
480 al_reg = eDI_reg + 1,
498 rAX_reg = di_reg + 1,
499 rCX_reg = rAX_reg + 1,
500 rDX_reg = rCX_reg + 1,
501 rBX_reg = rDX_reg + 1,
502 rSP_reg = rBX_reg + 1,
503 rBP_reg = rSP_reg + 1,
504 rSI_reg = rBP_reg + 1,
505 rDI_reg = rSI_reg + 1,
507 z_mode_ax_reg = rDI_reg + 1,
508 indir_dx_reg = z_mode_ax_reg + 1
514 USE_REG_TABLE = FLOATCODE + 1,
515 USE_MOD_TABLE = USE_REG_TABLE + 1,
516 USE_RM_TABLE = USE_MOD_TABLE + 1,
517 USE_PREFIX_TABLE = USE_RM_TABLE + 1,
518 USE_X86_64_TABLE = USE_PREFIX_TABLE + 1,
519 USE_3BYTE_TABLE = USE_X86_64_TABLE + 1,
520 USE_VEX_C4_TABLE = USE_3BYTE_TABLE + 1,
521 USE_VEX_C5_TABLE = USE_VEX_C4_TABLE + 1,
522 USE_VEX_LEN_TABLE = USE_VEX_C5_TABLE + 1
525 #define FLOAT NULL, { { NULL, FLOATCODE } }
527 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
528 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
529 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
530 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
531 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
532 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
533 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
534 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
535 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
536 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
556 REG_0F00 = REG_FF + 1,
557 REG_0F01 = REG_0F00 + 1,
558 REG_0F0D = REG_0F01 + 1,
559 REG_0F18 = REG_0F0D + 1,
560 REG_0F71 = REG_0F18 + 1,
561 REG_0F72 = REG_0F71 + 1,
562 REG_0F73 = REG_0F72 + 1,
563 REG_0FA6 = REG_0F73 + 1,
564 REG_0FA7 = REG_0FA6 + 1,
565 REG_0FAE = REG_0FA7 + 1,
566 REG_0FBA = REG_0FAE + 1,
567 REG_0FC7 = REG_0FBA + 1,
568 REG_VEX_71 = REG_0FC7 + 1,
569 REG_VEX_72 = REG_VEX_71 + 1,
570 REG_VEX_73 = REG_VEX_72 + 1,
571 REG_VEX_AE = REG_VEX_73 + 1
577 MOD_0F01_REG_0 = MOD_8D + 1,
578 MOD_0F01_REG_1 = MOD_0F01_REG_0 + 1,
579 MOD_0F01_REG_2 = MOD_0F01_REG_1 + 1,
580 MOD_0F01_REG_3 = MOD_0F01_REG_2 + 1,
581 MOD_0F01_REG_7 = MOD_0F01_REG_3 + 1,
582 MOD_0F12_PREFIX_0 = MOD_0F01_REG_7 + 1,
583 MOD_0F13 = MOD_0F12_PREFIX_0 + 1,
584 MOD_0F16_PREFIX_0 = MOD_0F13 + 1,
585 MOD_0F17 = MOD_0F16_PREFIX_0 + 1,
586 MOD_0F18_REG_0 = MOD_0F17 + 1,
587 MOD_0F18_REG_1 = MOD_0F18_REG_0 + 1,
588 MOD_0F18_REG_2 = MOD_0F18_REG_1 + 1,
589 MOD_0F18_REG_3 = MOD_0F18_REG_2 + 1,
590 MOD_0F20 = MOD_0F18_REG_3 + 1,
591 MOD_0F21 = MOD_0F20 + 1,
592 MOD_0F22 = MOD_0F21 + 1,
593 MOD_0F23 = MOD_0F22 + 1,
594 MOD_0F24 = MOD_0F23 + 1,
595 MOD_0F26 = MOD_0F24 + 1,
596 MOD_0F2B_PREFIX_0 = MOD_0F26 + 1,
597 MOD_0F2B_PREFIX_1 = MOD_0F2B_PREFIX_0 + 1,
598 MOD_0F2B_PREFIX_2 = MOD_0F2B_PREFIX_1 + 1,
599 MOD_0F2B_PREFIX_3 = MOD_0F2B_PREFIX_2 + 1,
600 MOD_0F51 = MOD_0F2B_PREFIX_3 + 1,
601 MOD_0F71_REG_2 = MOD_0F51 + 1,
602 MOD_0F71_REG_4 = MOD_0F71_REG_2 + 1,
603 MOD_0F71_REG_6 = MOD_0F71_REG_4 + 1,
604 MOD_0F72_REG_2 = MOD_0F71_REG_6 + 1,
605 MOD_0F72_REG_4 = MOD_0F72_REG_2 + 1,
606 MOD_0F72_REG_6 = MOD_0F72_REG_4 + 1,
607 MOD_0F73_REG_2 = MOD_0F72_REG_6 + 1,
608 MOD_0F73_REG_3 = MOD_0F73_REG_2 + 1,
609 MOD_0F73_REG_6 = MOD_0F73_REG_3 + 1,
610 MOD_0F73_REG_7 = MOD_0F73_REG_6 + 1,
611 MOD_0FAE_REG_0 = MOD_0F73_REG_7 + 1,
612 MOD_0FAE_REG_1 = MOD_0FAE_REG_0 + 1,
613 MOD_0FAE_REG_2 = MOD_0FAE_REG_1 + 1,
614 MOD_0FAE_REG_3 = MOD_0FAE_REG_2 + 1,
615 MOD_0FAE_REG_4 = MOD_0FAE_REG_3 + 1,
616 MOD_0FAE_REG_5 = MOD_0FAE_REG_4 + 1,
617 MOD_0FAE_REG_6 = MOD_0FAE_REG_5 + 1,
618 MOD_0FAE_REG_7 = MOD_0FAE_REG_6 + 1,
619 MOD_0FB2 = MOD_0FAE_REG_7 + 1,
620 MOD_0FB4 = MOD_0FB2 + 1,
621 MOD_0FB5 = MOD_0FB4 + 1,
622 MOD_0FC7_REG_6 = MOD_0FB5 + 1,
623 MOD_0FC7_REG_7 = MOD_0FC7_REG_6 + 1,
624 MOD_0FD7 = MOD_0FC7_REG_7 + 1,
625 MOD_0FE7_PREFIX_2 = MOD_0FD7 + 1,
626 MOD_0FF0_PREFIX_3 = MOD_0FE7_PREFIX_2 + 1,
627 MOD_0F382A_PREFIX_2 = MOD_0FF0_PREFIX_3 + 1,
628 MOD_62_32BIT = MOD_0F382A_PREFIX_2 + 1,
629 MOD_C4_32BIT = MOD_62_32BIT + 1,
630 MOD_C5_32BIT = MOD_C4_32BIT + 1,
631 MOD_VEX_12_PREFIX_0 = MOD_C5_32BIT + 1,
632 MOD_VEX_13 = MOD_VEX_12_PREFIX_0 + 1,
633 MOD_VEX_16_PREFIX_0 = MOD_VEX_13 + 1,
634 MOD_VEX_17 = MOD_VEX_16_PREFIX_0 + 1,
635 MOD_VEX_2B = MOD_VEX_17 + 1,
636 MOD_VEX_51 = MOD_VEX_2B + 1,
637 MOD_VEX_71_REG_2 = MOD_VEX_51 + 1,
638 MOD_VEX_71_REG_4 = MOD_VEX_71_REG_2 + 1,
639 MOD_VEX_71_REG_6 = MOD_VEX_71_REG_4 + 1,
640 MOD_VEX_72_REG_2 = MOD_VEX_71_REG_6 + 1,
641 MOD_VEX_72_REG_4 = MOD_VEX_72_REG_2 + 1,
642 MOD_VEX_72_REG_6 = MOD_VEX_72_REG_4 + 1,
643 MOD_VEX_73_REG_2 = MOD_VEX_72_REG_6 + 1,
644 MOD_VEX_73_REG_3 = MOD_VEX_73_REG_2 + 1,
645 MOD_VEX_73_REG_6 = MOD_VEX_73_REG_3 + 1,
646 MOD_VEX_73_REG_7 = MOD_VEX_73_REG_6 + 1,
647 MOD_VEX_AE_REG_2 = MOD_VEX_73_REG_7 + 1,
648 MOD_VEX_AE_REG_3 = MOD_VEX_AE_REG_2 + 1,
649 MOD_VEX_D7_PREFIX_2 = MOD_VEX_AE_REG_3 + 1,
650 MOD_VEX_E7_PREFIX_2 = MOD_VEX_D7_PREFIX_2 + 1,
651 MOD_VEX_F0_PREFIX_3 = MOD_VEX_E7_PREFIX_2 + 1,
652 MOD_VEX_3818_PREFIX_2 = MOD_VEX_F0_PREFIX_3 + 1,
653 MOD_VEX_3819_PREFIX_2 = MOD_VEX_3818_PREFIX_2 + 1,
654 MOD_VEX_381A_PREFIX_2 = MOD_VEX_3819_PREFIX_2 + 1,
655 MOD_VEX_382A_PREFIX_2 = MOD_VEX_381A_PREFIX_2 + 1,
656 MOD_VEX_382C_PREFIX_2 = MOD_VEX_382A_PREFIX_2 + 1,
657 MOD_VEX_382D_PREFIX_2 = MOD_VEX_382C_PREFIX_2 + 1,
658 MOD_VEX_382E_PREFIX_2 = MOD_VEX_382D_PREFIX_2 + 1,
659 MOD_VEX_382F_PREFIX_2 = MOD_VEX_382E_PREFIX_2 + 1
665 RM_0F01_REG_1 = RM_0F01_REG_0 + 1,
666 RM_0F01_REG_2 = RM_0F01_REG_1 + 1,
667 RM_0F01_REG_3 = RM_0F01_REG_2 + 1,
668 RM_0F01_REG_7 = RM_0F01_REG_3 + 1,
669 RM_0FAE_REG_5 = RM_0F01_REG_7 + 1,
670 RM_0FAE_REG_6 = RM_0FAE_REG_5 + 1,
671 RM_0FAE_REG_7 = RM_0FAE_REG_6 + 1
677 PREFIX_0F10 = PREFIX_90 + 1,
678 PREFIX_0F11 = PREFIX_0F10 + 1,
679 PREFIX_0F12 = PREFIX_0F11 + 1,
680 PREFIX_0F16 = PREFIX_0F12 + 1,
681 PREFIX_0F2A = PREFIX_0F16 + 1,
682 PREFIX_0F2B = PREFIX_0F2A + 1,
683 PREFIX_0F2C = PREFIX_0F2B + 1,
684 PREFIX_0F2D = PREFIX_0F2C + 1,
685 PREFIX_0F2E = PREFIX_0F2D + 1,
686 PREFIX_0F2F = PREFIX_0F2E + 1,
687 PREFIX_0F51 = PREFIX_0F2F + 1,
688 PREFIX_0F52 = PREFIX_0F51 + 1,
689 PREFIX_0F53 = PREFIX_0F52 + 1,
690 PREFIX_0F58 = PREFIX_0F53 + 1,
691 PREFIX_0F59 = PREFIX_0F58 + 1,
692 PREFIX_0F5A = PREFIX_0F59 + 1,
693 PREFIX_0F5B = PREFIX_0F5A + 1,
694 PREFIX_0F5C = PREFIX_0F5B + 1,
695 PREFIX_0F5D = PREFIX_0F5C + 1,
696 PREFIX_0F5E = PREFIX_0F5D + 1,
697 PREFIX_0F5F = PREFIX_0F5E + 1,
698 PREFIX_0F60 = PREFIX_0F5F + 1,
699 PREFIX_0F61 = PREFIX_0F60 + 1,
700 PREFIX_0F62 = PREFIX_0F61 + 1,
701 PREFIX_0F6C = PREFIX_0F62 + 1,
702 PREFIX_0F6D = PREFIX_0F6C + 1,
703 PREFIX_0F6F = PREFIX_0F6D + 1,
704 PREFIX_0F70 = PREFIX_0F6F + 1,
705 PREFIX_0F73_REG_3 = PREFIX_0F70 + 1,
706 PREFIX_0F73_REG_7 = PREFIX_0F73_REG_3 + 1,
707 PREFIX_0F78 = PREFIX_0F73_REG_7 + 1,
708 PREFIX_0F79 = PREFIX_0F78 + 1,
709 PREFIX_0F7C = PREFIX_0F79 + 1,
710 PREFIX_0F7D = PREFIX_0F7C + 1,
711 PREFIX_0F7E = PREFIX_0F7D + 1,
712 PREFIX_0F7F = PREFIX_0F7E + 1,
713 PREFIX_0FB8 = PREFIX_0F7F + 1,
714 PREFIX_0FBD = PREFIX_0FB8 + 1,
715 PREFIX_0FC2 = PREFIX_0FBD + 1,
716 PREFIX_0FC3 = PREFIX_0FC2 + 1,
717 PREFIX_0FC7_REG_6 = PREFIX_0FC3 + 1,
718 PREFIX_0FD0 = PREFIX_0FC7_REG_6 + 1,
719 PREFIX_0FD6 = PREFIX_0FD0 + 1,
720 PREFIX_0FE6 = PREFIX_0FD6 + 1,
721 PREFIX_0FE7 = PREFIX_0FE6 + 1,
722 PREFIX_0FF0 = PREFIX_0FE7 + 1,
723 PREFIX_0FF7 = PREFIX_0FF0 + 1,
724 PREFIX_0F3810 = PREFIX_0FF7 + 1,
725 PREFIX_0F3814 = PREFIX_0F3810 + 1,
726 PREFIX_0F3815 = PREFIX_0F3814 + 1,
727 PREFIX_0F3817 = PREFIX_0F3815 + 1,
728 PREFIX_0F3820 = PREFIX_0F3817 + 1,
729 PREFIX_0F3821 = PREFIX_0F3820 + 1,
730 PREFIX_0F3822 = PREFIX_0F3821 + 1,
731 PREFIX_0F3823 = PREFIX_0F3822 + 1,
732 PREFIX_0F3824 = PREFIX_0F3823 + 1,
733 PREFIX_0F3825 = PREFIX_0F3824 + 1,
734 PREFIX_0F3828 = PREFIX_0F3825 + 1,
735 PREFIX_0F3829 = PREFIX_0F3828 + 1,
736 PREFIX_0F382A = PREFIX_0F3829 + 1,
737 PREFIX_0F382B = PREFIX_0F382A + 1,
738 PREFIX_0F3830 = PREFIX_0F382B + 1,
739 PREFIX_0F3831 = PREFIX_0F3830 + 1,
740 PREFIX_0F3832 = PREFIX_0F3831 + 1,
741 PREFIX_0F3833 = PREFIX_0F3832 + 1,
742 PREFIX_0F3834 = PREFIX_0F3833 + 1,
743 PREFIX_0F3835 = PREFIX_0F3834 + 1,
744 PREFIX_0F3837 = PREFIX_0F3835 + 1,
745 PREFIX_0F3838 = PREFIX_0F3837 + 1,
746 PREFIX_0F3839 = PREFIX_0F3838 + 1,
747 PREFIX_0F383A = PREFIX_0F3839 + 1,
748 PREFIX_0F383B = PREFIX_0F383A + 1,
749 PREFIX_0F383C = PREFIX_0F383B + 1,
750 PREFIX_0F383D = PREFIX_0F383C + 1,
751 PREFIX_0F383E = PREFIX_0F383D + 1,
752 PREFIX_0F383F = PREFIX_0F383E + 1,
753 PREFIX_0F3840 = PREFIX_0F383F + 1,
754 PREFIX_0F3841 = PREFIX_0F3840 + 1,
755 PREFIX_0F3880 = PREFIX_0F3841 + 1,
756 PREFIX_0F3881 = PREFIX_0F3880 + 1,
757 PREFIX_0F38DB = PREFIX_0F3881 + 1,
758 PREFIX_0F38DC = PREFIX_0F38DB + 1,
759 PREFIX_0F38DD = PREFIX_0F38DC + 1,
760 PREFIX_0F38DE = PREFIX_0F38DD + 1,
761 PREFIX_0F38DF = PREFIX_0F38DE + 1,
762 PREFIX_0F38F0 = PREFIX_0F38DF + 1,
763 PREFIX_0F38F1 = PREFIX_0F38F0 + 1,
764 PREFIX_0F3A08 = PREFIX_0F38F1 + 1,
765 PREFIX_0F3A09 = PREFIX_0F3A08 + 1,
766 PREFIX_0F3A0A = PREFIX_0F3A09 + 1,
767 PREFIX_0F3A0B = PREFIX_0F3A0A + 1,
768 PREFIX_0F3A0C = PREFIX_0F3A0B + 1,
769 PREFIX_0F3A0D = PREFIX_0F3A0C + 1,
770 PREFIX_0F3A0E = PREFIX_0F3A0D + 1,
771 PREFIX_0F3A14 = PREFIX_0F3A0E + 1,
772 PREFIX_0F3A15 = PREFIX_0F3A14 + 1,
773 PREFIX_0F3A16 = PREFIX_0F3A15 + 1,
774 PREFIX_0F3A17 = PREFIX_0F3A16 + 1,
775 PREFIX_0F3A20 = PREFIX_0F3A17 + 1,
776 PREFIX_0F3A21 = PREFIX_0F3A20 + 1,
777 PREFIX_0F3A22 = PREFIX_0F3A21 + 1,
778 PREFIX_0F3A40 = PREFIX_0F3A22 + 1,
779 PREFIX_0F3A41 = PREFIX_0F3A40 + 1,
780 PREFIX_0F3A42 = PREFIX_0F3A41 + 1,
781 PREFIX_0F3A44 = PREFIX_0F3A42 + 1,
782 PREFIX_0F3A60 = PREFIX_0F3A44 + 1,
783 PREFIX_0F3A61 = PREFIX_0F3A60 + 1,
784 PREFIX_0F3A62 = PREFIX_0F3A61 + 1,
785 PREFIX_0F3A63 = PREFIX_0F3A62 + 1,
786 PREFIX_0F3ADF = PREFIX_0F3A63 + 1,
787 PREFIX_VEX_10 = PREFIX_0F3ADF + 1,
788 PREFIX_VEX_11 = PREFIX_VEX_10 + 1,
789 PREFIX_VEX_12 = PREFIX_VEX_11 + 1,
790 PREFIX_VEX_16 = PREFIX_VEX_12 + 1,
791 PREFIX_VEX_2A = PREFIX_VEX_16 + 1,
792 PREFIX_VEX_2C = PREFIX_VEX_2A + 1,
793 PREFIX_VEX_2D = PREFIX_VEX_2C + 1,
794 PREFIX_VEX_2E = PREFIX_VEX_2D + 1,
795 PREFIX_VEX_2F = PREFIX_VEX_2E + 1,
796 PREFIX_VEX_51 = PREFIX_VEX_2F + 1,
797 PREFIX_VEX_52 = PREFIX_VEX_51 + 1,
798 PREFIX_VEX_53 = PREFIX_VEX_52 + 1,
799 PREFIX_VEX_58 = PREFIX_VEX_53 + 1,
800 PREFIX_VEX_59 = PREFIX_VEX_58 + 1,
801 PREFIX_VEX_5A = PREFIX_VEX_59 + 1,
802 PREFIX_VEX_5B = PREFIX_VEX_5A + 1,
803 PREFIX_VEX_5C = PREFIX_VEX_5B + 1,
804 PREFIX_VEX_5D = PREFIX_VEX_5C + 1,
805 PREFIX_VEX_5E = PREFIX_VEX_5D + 1,
806 PREFIX_VEX_5F = PREFIX_VEX_5E + 1,
807 PREFIX_VEX_60 = PREFIX_VEX_5F + 1,
808 PREFIX_VEX_61 = PREFIX_VEX_60 + 1,
809 PREFIX_VEX_62 = PREFIX_VEX_61 + 1,
810 PREFIX_VEX_63 = PREFIX_VEX_62 + 1,
811 PREFIX_VEX_64 = PREFIX_VEX_63 + 1,
812 PREFIX_VEX_65 = PREFIX_VEX_64 + 1,
813 PREFIX_VEX_66 = PREFIX_VEX_65 + 1,
814 PREFIX_VEX_67 = PREFIX_VEX_66 + 1,
815 PREFIX_VEX_68 = PREFIX_VEX_67 + 1,
816 PREFIX_VEX_69 = PREFIX_VEX_68 + 1,
817 PREFIX_VEX_6A = PREFIX_VEX_69 + 1,
818 PREFIX_VEX_6B = PREFIX_VEX_6A + 1,
819 PREFIX_VEX_6C = PREFIX_VEX_6B + 1,
820 PREFIX_VEX_6D = PREFIX_VEX_6C + 1,
821 PREFIX_VEX_6E = PREFIX_VEX_6D + 1,
822 PREFIX_VEX_6F = PREFIX_VEX_6E + 1,
823 PREFIX_VEX_70 = PREFIX_VEX_6F + 1,
824 PREFIX_VEX_71_REG_2 = PREFIX_VEX_70 + 1,
825 PREFIX_VEX_71_REG_4 = PREFIX_VEX_71_REG_2 + 1,
826 PREFIX_VEX_71_REG_6 = PREFIX_VEX_71_REG_4 + 1,
827 PREFIX_VEX_72_REG_2 = PREFIX_VEX_71_REG_6 + 1,
828 PREFIX_VEX_72_REG_4 = PREFIX_VEX_72_REG_2 + 1,
829 PREFIX_VEX_72_REG_6 = PREFIX_VEX_72_REG_4 + 1,
830 PREFIX_VEX_73_REG_2 = PREFIX_VEX_72_REG_6 + 1,
831 PREFIX_VEX_73_REG_3 = PREFIX_VEX_73_REG_2 + 1,
832 PREFIX_VEX_73_REG_6 = PREFIX_VEX_73_REG_3 + 1,
833 PREFIX_VEX_73_REG_7 = PREFIX_VEX_73_REG_6 + 1,
834 PREFIX_VEX_74 = PREFIX_VEX_73_REG_7 + 1,
835 PREFIX_VEX_75 = PREFIX_VEX_74 + 1,
836 PREFIX_VEX_76 = PREFIX_VEX_75 + 1,
837 PREFIX_VEX_77 = PREFIX_VEX_76 + 1,
838 PREFIX_VEX_7C = PREFIX_VEX_77 + 1,
839 PREFIX_VEX_7D = PREFIX_VEX_7C + 1,
840 PREFIX_VEX_7E = PREFIX_VEX_7D + 1,
841 PREFIX_VEX_7F = PREFIX_VEX_7E + 1,
842 PREFIX_VEX_C2 = PREFIX_VEX_7F + 1,
843 PREFIX_VEX_C4 = PREFIX_VEX_C2 + 1,
844 PREFIX_VEX_C5 = PREFIX_VEX_C4 + 1,
845 PREFIX_VEX_D0 = PREFIX_VEX_C5 + 1,
846 PREFIX_VEX_D1 = PREFIX_VEX_D0 + 1,
847 PREFIX_VEX_D2 = PREFIX_VEX_D1 + 1,
848 PREFIX_VEX_D3 = PREFIX_VEX_D2 + 1,
849 PREFIX_VEX_D4 = PREFIX_VEX_D3 + 1,
850 PREFIX_VEX_D5 = PREFIX_VEX_D4 + 1,
851 PREFIX_VEX_D6 = PREFIX_VEX_D5 + 1,
852 PREFIX_VEX_D7 = PREFIX_VEX_D6 + 1,
853 PREFIX_VEX_D8 = PREFIX_VEX_D7 + 1,
854 PREFIX_VEX_D9 = PREFIX_VEX_D8 + 1,
855 PREFIX_VEX_DA = PREFIX_VEX_D9 + 1,
856 PREFIX_VEX_DB = PREFIX_VEX_DA + 1,
857 PREFIX_VEX_DC = PREFIX_VEX_DB + 1,
858 PREFIX_VEX_DD = PREFIX_VEX_DC + 1,
859 PREFIX_VEX_DE = PREFIX_VEX_DD + 1,
860 PREFIX_VEX_DF = PREFIX_VEX_DE + 1,
861 PREFIX_VEX_E0 = PREFIX_VEX_DF + 1,
862 PREFIX_VEX_E1 = PREFIX_VEX_E0 + 1,
863 PREFIX_VEX_E2 = PREFIX_VEX_E1 + 1,
864 PREFIX_VEX_E3 = PREFIX_VEX_E2 + 1,
865 PREFIX_VEX_E4 = PREFIX_VEX_E3 + 1,
866 PREFIX_VEX_E5 = PREFIX_VEX_E4 + 1,
867 PREFIX_VEX_E6 = PREFIX_VEX_E5 + 1,
868 PREFIX_VEX_E7 = PREFIX_VEX_E6 + 1,
869 PREFIX_VEX_E8 = PREFIX_VEX_E7 + 1,
870 PREFIX_VEX_E9 = PREFIX_VEX_E8 + 1,
871 PREFIX_VEX_EA = PREFIX_VEX_E9 + 1,
872 PREFIX_VEX_EB = PREFIX_VEX_EA + 1,
873 PREFIX_VEX_EC = PREFIX_VEX_EB + 1,
874 PREFIX_VEX_ED = PREFIX_VEX_EC + 1,
875 PREFIX_VEX_EE = PREFIX_VEX_ED + 1,
876 PREFIX_VEX_EF = PREFIX_VEX_EE + 1,
877 PREFIX_VEX_F0 = PREFIX_VEX_EF + 1,
878 PREFIX_VEX_F1 = PREFIX_VEX_F0 + 1,
879 PREFIX_VEX_F2 = PREFIX_VEX_F1 + 1,
880 PREFIX_VEX_F3 = PREFIX_VEX_F2 + 1,
881 PREFIX_VEX_F4 = PREFIX_VEX_F3 + 1,
882 PREFIX_VEX_F5 = PREFIX_VEX_F4 + 1,
883 PREFIX_VEX_F6 = PREFIX_VEX_F5 + 1,
884 PREFIX_VEX_F7 = PREFIX_VEX_F6 + 1,
885 PREFIX_VEX_F8 = PREFIX_VEX_F7 + 1,
886 PREFIX_VEX_F9 = PREFIX_VEX_F8 + 1,
887 PREFIX_VEX_FA = PREFIX_VEX_F9 + 1,
888 PREFIX_VEX_FB = PREFIX_VEX_FA + 1,
889 PREFIX_VEX_FC = PREFIX_VEX_FB + 1,
890 PREFIX_VEX_FD = PREFIX_VEX_FC + 1,
891 PREFIX_VEX_FE = PREFIX_VEX_FD + 1,
892 PREFIX_VEX_3800 = PREFIX_VEX_FE + 1,
893 PREFIX_VEX_3801 = PREFIX_VEX_3800 + 1,
894 PREFIX_VEX_3802 = PREFIX_VEX_3801 + 1,
895 PREFIX_VEX_3803 = PREFIX_VEX_3802 + 1,
896 PREFIX_VEX_3804 = PREFIX_VEX_3803 + 1,
897 PREFIX_VEX_3805 = PREFIX_VEX_3804 + 1,
898 PREFIX_VEX_3806 = PREFIX_VEX_3805 + 1,
899 PREFIX_VEX_3807 = PREFIX_VEX_3806 + 1,
900 PREFIX_VEX_3808 = PREFIX_VEX_3807 + 1,
901 PREFIX_VEX_3809 = PREFIX_VEX_3808 + 1,
902 PREFIX_VEX_380A = PREFIX_VEX_3809 + 1,
903 PREFIX_VEX_380B = PREFIX_VEX_380A + 1,
904 PREFIX_VEX_380C = PREFIX_VEX_380B + 1,
905 PREFIX_VEX_380D = PREFIX_VEX_380C + 1,
906 PREFIX_VEX_380E = PREFIX_VEX_380D + 1,
907 PREFIX_VEX_380F = PREFIX_VEX_380E + 1,
908 PREFIX_VEX_3817 = PREFIX_VEX_380F + 1,
909 PREFIX_VEX_3818 = PREFIX_VEX_3817 + 1,
910 PREFIX_VEX_3819 = PREFIX_VEX_3818 + 1,
911 PREFIX_VEX_381A = PREFIX_VEX_3819 + 1,
912 PREFIX_VEX_381C = PREFIX_VEX_381A + 1,
913 PREFIX_VEX_381D = PREFIX_VEX_381C + 1,
914 PREFIX_VEX_381E = PREFIX_VEX_381D + 1,
915 PREFIX_VEX_3820 = PREFIX_VEX_381E + 1,
916 PREFIX_VEX_3821 = PREFIX_VEX_3820 + 1,
917 PREFIX_VEX_3822 = PREFIX_VEX_3821 + 1,
918 PREFIX_VEX_3823 = PREFIX_VEX_3822 + 1,
919 PREFIX_VEX_3824 = PREFIX_VEX_3823 + 1,
920 PREFIX_VEX_3825 = PREFIX_VEX_3824 + 1,
921 PREFIX_VEX_3828 = PREFIX_VEX_3825 + 1,
922 PREFIX_VEX_3829 = PREFIX_VEX_3828 + 1,
923 PREFIX_VEX_382A = PREFIX_VEX_3829 + 1,
924 PREFIX_VEX_382B = PREFIX_VEX_382A + 1,
925 PREFIX_VEX_382C = PREFIX_VEX_382B + 1,
926 PREFIX_VEX_382D = PREFIX_VEX_382C + 1,
927 PREFIX_VEX_382E = PREFIX_VEX_382D + 1,
928 PREFIX_VEX_382F = PREFIX_VEX_382E + 1,
929 PREFIX_VEX_3830 = PREFIX_VEX_382F + 1,
930 PREFIX_VEX_3831 = PREFIX_VEX_3830 + 1,
931 PREFIX_VEX_3832 = PREFIX_VEX_3831 + 1,
932 PREFIX_VEX_3833 = PREFIX_VEX_3832 + 1,
933 PREFIX_VEX_3834 = PREFIX_VEX_3833 + 1,
934 PREFIX_VEX_3835 = PREFIX_VEX_3834 + 1,
935 PREFIX_VEX_3837 = PREFIX_VEX_3835 + 1,
936 PREFIX_VEX_3838 = PREFIX_VEX_3837 + 1,
937 PREFIX_VEX_3839 = PREFIX_VEX_3838 + 1,
938 PREFIX_VEX_383A = PREFIX_VEX_3839 + 1,
939 PREFIX_VEX_383B = PREFIX_VEX_383A + 1,
940 PREFIX_VEX_383C = PREFIX_VEX_383B + 1,
941 PREFIX_VEX_383D = PREFIX_VEX_383C + 1,
942 PREFIX_VEX_383E = PREFIX_VEX_383D + 1,
943 PREFIX_VEX_383F = PREFIX_VEX_383E + 1,
944 PREFIX_VEX_3840 = PREFIX_VEX_383F + 1,
945 PREFIX_VEX_3841 = PREFIX_VEX_3840 + 1,
946 PREFIX_VEX_3896 = PREFIX_VEX_3841 + 1,
947 PREFIX_VEX_3897 = PREFIX_VEX_3896 + 1,
948 PREFIX_VEX_3898 = PREFIX_VEX_3897 + 1,
949 PREFIX_VEX_3899 = PREFIX_VEX_3898 + 1,
950 PREFIX_VEX_389A = PREFIX_VEX_3899 + 1,
951 PREFIX_VEX_389B = PREFIX_VEX_389A + 1,
952 PREFIX_VEX_389C = PREFIX_VEX_389B + 1,
953 PREFIX_VEX_389D = PREFIX_VEX_389C + 1,
954 PREFIX_VEX_389E = PREFIX_VEX_389D + 1,
955 PREFIX_VEX_389F = PREFIX_VEX_389E + 1,
956 PREFIX_VEX_38A6 = PREFIX_VEX_389F + 1,
957 PREFIX_VEX_38A7 = PREFIX_VEX_38A6 + 1,
958 PREFIX_VEX_38A8 = PREFIX_VEX_38A7 + 1,
959 PREFIX_VEX_38A9 = PREFIX_VEX_38A8 + 1,
960 PREFIX_VEX_38AA = PREFIX_VEX_38A9 + 1,
961 PREFIX_VEX_38AB = PREFIX_VEX_38AA + 1,
962 PREFIX_VEX_38AC = PREFIX_VEX_38AB + 1,
963 PREFIX_VEX_38AD = PREFIX_VEX_38AC + 1,
964 PREFIX_VEX_38AE = PREFIX_VEX_38AD + 1,
965 PREFIX_VEX_38AF = PREFIX_VEX_38AE + 1,
966 PREFIX_VEX_38B6 = PREFIX_VEX_38AF + 1,
967 PREFIX_VEX_38B7 = PREFIX_VEX_38B6 + 1,
968 PREFIX_VEX_38B8 = PREFIX_VEX_38B7 + 1,
969 PREFIX_VEX_38B9 = PREFIX_VEX_38B8 + 1,
970 PREFIX_VEX_38BA = PREFIX_VEX_38B9 + 1,
971 PREFIX_VEX_38BB = PREFIX_VEX_38BA + 1,
972 PREFIX_VEX_38BC = PREFIX_VEX_38BB + 1,
973 PREFIX_VEX_38BD = PREFIX_VEX_38BC + 1,
974 PREFIX_VEX_38BE = PREFIX_VEX_38BD + 1,
975 PREFIX_VEX_38BF = PREFIX_VEX_38BE + 1,
976 PREFIX_VEX_38DB = PREFIX_VEX_38BF + 1,
977 PREFIX_VEX_38DC = PREFIX_VEX_38DB + 1,
978 PREFIX_VEX_38DD = PREFIX_VEX_38DC + 1,
979 PREFIX_VEX_38DE = PREFIX_VEX_38DD + 1,
980 PREFIX_VEX_38DF = PREFIX_VEX_38DE + 1,
981 PREFIX_VEX_3A04 = PREFIX_VEX_38DF + 1,
982 PREFIX_VEX_3A05 = PREFIX_VEX_3A04 + 1,
983 PREFIX_VEX_3A06 = PREFIX_VEX_3A05 + 1,
984 PREFIX_VEX_3A08 = PREFIX_VEX_3A06 + 1,
985 PREFIX_VEX_3A09 = PREFIX_VEX_3A08 + 1,
986 PREFIX_VEX_3A0A = PREFIX_VEX_3A09 + 1,
987 PREFIX_VEX_3A0B = PREFIX_VEX_3A0A + 1,
988 PREFIX_VEX_3A0C = PREFIX_VEX_3A0B + 1,
989 PREFIX_VEX_3A0D = PREFIX_VEX_3A0C + 1,
990 PREFIX_VEX_3A0E = PREFIX_VEX_3A0D + 1,
991 PREFIX_VEX_3A0F = PREFIX_VEX_3A0E + 1,
992 PREFIX_VEX_3A14 = PREFIX_VEX_3A0F + 1,
993 PREFIX_VEX_3A15 = PREFIX_VEX_3A14 + 1,
994 PREFIX_VEX_3A16 = PREFIX_VEX_3A15 + 1,
995 PREFIX_VEX_3A17 = PREFIX_VEX_3A16 + 1,
996 PREFIX_VEX_3A18 = PREFIX_VEX_3A17 + 1,
997 PREFIX_VEX_3A19 = PREFIX_VEX_3A18 + 1,
998 PREFIX_VEX_3A20 = PREFIX_VEX_3A19 + 1,
999 PREFIX_VEX_3A21 = PREFIX_VEX_3A20 + 1,
1000 PREFIX_VEX_3A22 = PREFIX_VEX_3A21 + 1,
1001 PREFIX_VEX_3A40 = PREFIX_VEX_3A22 + 1,
1002 PREFIX_VEX_3A41 = PREFIX_VEX_3A40 + 1,
1003 PREFIX_VEX_3A42 = PREFIX_VEX_3A41 + 1,
1004 PREFIX_VEX_3A44 = PREFIX_VEX_3A42 + 1,
1005 PREFIX_VEX_3A4A = PREFIX_VEX_3A44 + 1,
1006 PREFIX_VEX_3A4B = PREFIX_VEX_3A4A + 1,
1007 PREFIX_VEX_3A4C = PREFIX_VEX_3A4B + 1,
1008 PREFIX_VEX_3A5C = PREFIX_VEX_3A4C + 1,
1009 PREFIX_VEX_3A5D = PREFIX_VEX_3A5C + 1,
1010 PREFIX_VEX_3A5E = PREFIX_VEX_3A5D + 1,
1011 PREFIX_VEX_3A5F = PREFIX_VEX_3A5E + 1,
1012 PREFIX_VEX_3A60 = PREFIX_VEX_3A5F + 1,
1013 PREFIX_VEX_3A61 = PREFIX_VEX_3A60 + 1,
1014 PREFIX_VEX_3A62 = PREFIX_VEX_3A61 + 1,
1015 PREFIX_VEX_3A63 = PREFIX_VEX_3A62 + 1,
1016 PREFIX_VEX_3A68 = PREFIX_VEX_3A63 + 1,
1017 PREFIX_VEX_3A69 = PREFIX_VEX_3A68 + 1,
1018 PREFIX_VEX_3A6A = PREFIX_VEX_3A69 + 1,
1019 PREFIX_VEX_3A6B = PREFIX_VEX_3A6A + 1,
1020 PREFIX_VEX_3A6C = PREFIX_VEX_3A6B + 1,
1021 PREFIX_VEX_3A6D = PREFIX_VEX_3A6C + 1,
1022 PREFIX_VEX_3A6E = PREFIX_VEX_3A6D + 1,
1023 PREFIX_VEX_3A6F = PREFIX_VEX_3A6E + 1,
1024 PREFIX_VEX_3A78 = PREFIX_VEX_3A6F + 1,
1025 PREFIX_VEX_3A79 = PREFIX_VEX_3A78 + 1,
1026 PREFIX_VEX_3A7A = PREFIX_VEX_3A79 + 1,
1027 PREFIX_VEX_3A7B = PREFIX_VEX_3A7A + 1,
1028 PREFIX_VEX_3A7C = PREFIX_VEX_3A7B + 1,
1029 PREFIX_VEX_3A7D = PREFIX_VEX_3A7C + 1,
1030 PREFIX_VEX_3A7E = PREFIX_VEX_3A7D + 1,
1031 PREFIX_VEX_3A7F = PREFIX_VEX_3A7E + 1,
1032 PREFIX_VEX_3ADF = PREFIX_VEX_3A7F + 1
1038 X86_64_07 = X86_64_06 + 1,
1039 X86_64_0D = X86_64_07 + 1,
1040 X86_64_16 = X86_64_0D + 1,
1041 X86_64_17 = X86_64_16 + 1,
1042 X86_64_1E = X86_64_17 + 1,
1043 X86_64_1F = X86_64_1E + 1,
1044 X86_64_27 = X86_64_1F + 1,
1045 X86_64_2F = X86_64_27 + 1,
1046 X86_64_37 = X86_64_2F + 1,
1047 X86_64_3F = X86_64_37 + 1,
1048 X86_64_60 = X86_64_3F + 1,
1049 X86_64_61 = X86_64_60 + 1,
1050 X86_64_62 = X86_64_61 + 1,
1051 X86_64_63 = X86_64_62 + 1,
1052 X86_64_6D = X86_64_63 + 1,
1053 X86_64_6F = X86_64_6D + 1,
1054 X86_64_9A = X86_64_6F + 1,
1055 X86_64_C4 = X86_64_9A + 1,
1056 X86_64_C5 = X86_64_C4 + 1,
1057 X86_64_CE = X86_64_C5 + 1,
1058 X86_64_D4 = X86_64_CE + 1,
1059 X86_64_D5 = X86_64_D4 + 1,
1060 X86_64_EA = X86_64_D5 + 1,
1061 X86_64_0F01_REG_0 = X86_64_EA + 1,
1062 X86_64_0F01_REG_1 = X86_64_0F01_REG_0 + 1,
1063 X86_64_0F01_REG_2 = X86_64_0F01_REG_1 + 1,
1064 X86_64_0F01_REG_3 = X86_64_0F01_REG_2 + 1
1069 THREE_BYTE_0F38 = 0,
1070 THREE_BYTE_0F3A = THREE_BYTE_0F38 + 1,
1071 THREE_BYTE_0F7A = THREE_BYTE_0F3A + 1
1077 VEX_0F38 = VEX_0F + 1,
1078 VEX_0F3A = VEX_0F38 + 1
1084 VEX_LEN_10_P_3 = VEX_LEN_10_P_1 + 1,
1085 VEX_LEN_11_P_1 = VEX_LEN_10_P_3 + 1,
1086 VEX_LEN_11_P_3 = VEX_LEN_11_P_1 + 1,
1087 VEX_LEN_12_P_0_M_0 = VEX_LEN_11_P_3 + 1,
1088 VEX_LEN_12_P_0_M_1 = VEX_LEN_12_P_0_M_0 + 1,
1089 VEX_LEN_12_P_2 = VEX_LEN_12_P_0_M_1 + 1,
1090 VEX_LEN_13_M_0 = VEX_LEN_12_P_2 + 1,
1091 VEX_LEN_16_P_0_M_0 = VEX_LEN_13_M_0 + 1,
1092 VEX_LEN_16_P_0_M_1 = VEX_LEN_16_P_0_M_0 + 1,
1093 VEX_LEN_16_P_2 = VEX_LEN_16_P_0_M_1 + 1,
1094 VEX_LEN_17_M_0 = VEX_LEN_16_P_2 + 1,
1095 VEX_LEN_2A_P_1 = VEX_LEN_17_M_0 + 1,
1096 VEX_LEN_2A_P_3 = VEX_LEN_2A_P_1 + 1,
1097 VEX_LEN_2C_P_1 = VEX_LEN_2A_P_3 + 1,
1098 VEX_LEN_2C_P_3 = VEX_LEN_2C_P_1 + 1,
1099 VEX_LEN_2D_P_1 = VEX_LEN_2C_P_3 + 1,
1100 VEX_LEN_2D_P_3 = VEX_LEN_2D_P_1 + 1,
1101 VEX_LEN_2E_P_0 = VEX_LEN_2D_P_3 + 1,
1102 VEX_LEN_2E_P_2 = VEX_LEN_2E_P_0 + 1,
1103 VEX_LEN_2F_P_0 = VEX_LEN_2E_P_2 + 1,
1104 VEX_LEN_2F_P_2 = VEX_LEN_2F_P_0 + 1,
1105 VEX_LEN_51_P_1 = VEX_LEN_2F_P_2 + 1,
1106 VEX_LEN_51_P_3 = VEX_LEN_51_P_1 + 1,
1107 VEX_LEN_52_P_1 = VEX_LEN_51_P_3 + 1,
1108 VEX_LEN_53_P_1 = VEX_LEN_52_P_1 + 1,
1109 VEX_LEN_58_P_1 = VEX_LEN_53_P_1 + 1,
1110 VEX_LEN_58_P_3 = VEX_LEN_58_P_1 + 1,
1111 VEX_LEN_59_P_1 = VEX_LEN_58_P_3 + 1,
1112 VEX_LEN_59_P_3 = VEX_LEN_59_P_1 + 1,
1113 VEX_LEN_5A_P_1 = VEX_LEN_59_P_3 + 1,
1114 VEX_LEN_5A_P_3 = VEX_LEN_5A_P_1 + 1,
1115 VEX_LEN_5C_P_1 = VEX_LEN_5A_P_3 + 1,
1116 VEX_LEN_5C_P_3 = VEX_LEN_5C_P_1 + 1,
1117 VEX_LEN_5D_P_1 = VEX_LEN_5C_P_3 + 1,
1118 VEX_LEN_5D_P_3 = VEX_LEN_5D_P_1 + 1,
1119 VEX_LEN_5E_P_1 = VEX_LEN_5D_P_3 + 1,
1120 VEX_LEN_5E_P_3 = VEX_LEN_5E_P_1 + 1,
1121 VEX_LEN_5F_P_1 = VEX_LEN_5E_P_3 + 1,
1122 VEX_LEN_5F_P_3 = VEX_LEN_5F_P_1 + 1,
1123 VEX_LEN_60_P_2 = VEX_LEN_5F_P_3 + 1,
1124 VEX_LEN_61_P_2 = VEX_LEN_60_P_2 + 1,
1125 VEX_LEN_62_P_2 = VEX_LEN_61_P_2 + 1,
1126 VEX_LEN_63_P_2 = VEX_LEN_62_P_2 + 1,
1127 VEX_LEN_64_P_2 = VEX_LEN_63_P_2 + 1,
1128 VEX_LEN_65_P_2 = VEX_LEN_64_P_2 + 1,
1129 VEX_LEN_66_P_2 = VEX_LEN_65_P_2 + 1,
1130 VEX_LEN_67_P_2 = VEX_LEN_66_P_2 + 1,
1131 VEX_LEN_68_P_2 = VEX_LEN_67_P_2 + 1,
1132 VEX_LEN_69_P_2 = VEX_LEN_68_P_2 + 1,
1133 VEX_LEN_6A_P_2 = VEX_LEN_69_P_2 + 1,
1134 VEX_LEN_6B_P_2 = VEX_LEN_6A_P_2 + 1,
1135 VEX_LEN_6C_P_2 = VEX_LEN_6B_P_2 + 1,
1136 VEX_LEN_6D_P_2 = VEX_LEN_6C_P_2 + 1,
1137 VEX_LEN_6E_P_2 = VEX_LEN_6D_P_2 + 1,
1138 VEX_LEN_70_P_1 = VEX_LEN_6E_P_2 + 1,
1139 VEX_LEN_70_P_2 = VEX_LEN_70_P_1 + 1,
1140 VEX_LEN_70_P_3 = VEX_LEN_70_P_2 + 1,
1141 VEX_LEN_71_R_2_P_2 = VEX_LEN_70_P_3 + 1,
1142 VEX_LEN_71_R_4_P_2 = VEX_LEN_71_R_2_P_2 + 1,
1143 VEX_LEN_71_R_6_P_2 = VEX_LEN_71_R_4_P_2 + 1,
1144 VEX_LEN_72_R_2_P_2 = VEX_LEN_71_R_6_P_2 + 1,
1145 VEX_LEN_72_R_4_P_2 = VEX_LEN_72_R_2_P_2 + 1,
1146 VEX_LEN_72_R_6_P_2 = VEX_LEN_72_R_4_P_2 + 1,
1147 VEX_LEN_73_R_2_P_2 = VEX_LEN_72_R_6_P_2 + 1,
1148 VEX_LEN_73_R_3_P_2 = VEX_LEN_73_R_2_P_2 + 1,
1149 VEX_LEN_73_R_6_P_2 = VEX_LEN_73_R_3_P_2 + 1,
1150 VEX_LEN_73_R_7_P_2 = VEX_LEN_73_R_6_P_2 + 1,
1151 VEX_LEN_74_P_2 = VEX_LEN_73_R_7_P_2 + 1,
1152 VEX_LEN_75_P_2 = VEX_LEN_74_P_2 + 1,
1153 VEX_LEN_76_P_2 = VEX_LEN_75_P_2 + 1,
1154 VEX_LEN_7E_P_1 = VEX_LEN_76_P_2 + 1,
1155 VEX_LEN_7E_P_2 = VEX_LEN_7E_P_1 + 1,
1156 VEX_LEN_AE_R_2_M_0 = VEX_LEN_7E_P_2 + 1,
1157 VEX_LEN_AE_R_3_M_0 = VEX_LEN_AE_R_2_M_0 + 1,
1158 VEX_LEN_C2_P_1 = VEX_LEN_AE_R_3_M_0 + 1,
1159 VEX_LEN_C2_P_3 = VEX_LEN_C2_P_1 + 1,
1160 VEX_LEN_C4_P_2 = VEX_LEN_C2_P_3 + 1,
1161 VEX_LEN_C5_P_2 = VEX_LEN_C4_P_2 + 1,
1162 VEX_LEN_D1_P_2 = VEX_LEN_C5_P_2 + 1,
1163 VEX_LEN_D2_P_2 = VEX_LEN_D1_P_2 + 1,
1164 VEX_LEN_D3_P_2 = VEX_LEN_D2_P_2 + 1,
1165 VEX_LEN_D4_P_2 = VEX_LEN_D3_P_2 + 1,
1166 VEX_LEN_D5_P_2 = VEX_LEN_D4_P_2 + 1,
1167 VEX_LEN_D6_P_2 = VEX_LEN_D5_P_2 + 1,
1168 VEX_LEN_D7_P_2_M_1 = VEX_LEN_D6_P_2 + 1,
1169 VEX_LEN_D8_P_2 = VEX_LEN_D7_P_2_M_1 + 1,
1170 VEX_LEN_D9_P_2 = VEX_LEN_D8_P_2 + 1,
1171 VEX_LEN_DA_P_2 = VEX_LEN_D9_P_2 + 1,
1172 VEX_LEN_DB_P_2 = VEX_LEN_DA_P_2 + 1,
1173 VEX_LEN_DC_P_2 = VEX_LEN_DB_P_2 + 1,
1174 VEX_LEN_DD_P_2 = VEX_LEN_DC_P_2 + 1,
1175 VEX_LEN_DE_P_2 = VEX_LEN_DD_P_2 + 1,
1176 VEX_LEN_DF_P_2 = VEX_LEN_DE_P_2 + 1,
1177 VEX_LEN_E0_P_2 = VEX_LEN_DF_P_2 + 1,
1178 VEX_LEN_E1_P_2 = VEX_LEN_E0_P_2 + 1,
1179 VEX_LEN_E2_P_2 = VEX_LEN_E1_P_2 + 1,
1180 VEX_LEN_E3_P_2 = VEX_LEN_E2_P_2 + 1,
1181 VEX_LEN_E4_P_2 = VEX_LEN_E3_P_2 + 1,
1182 VEX_LEN_E5_P_2 = VEX_LEN_E4_P_2 + 1,
1183 VEX_LEN_E8_P_2 = VEX_LEN_E5_P_2 + 1,
1184 VEX_LEN_E9_P_2 = VEX_LEN_E8_P_2 + 1,
1185 VEX_LEN_EA_P_2 = VEX_LEN_E9_P_2 + 1,
1186 VEX_LEN_EB_P_2 = VEX_LEN_EA_P_2 + 1,
1187 VEX_LEN_EC_P_2 = VEX_LEN_EB_P_2 + 1,
1188 VEX_LEN_ED_P_2 = VEX_LEN_EC_P_2 + 1,
1189 VEX_LEN_EE_P_2 = VEX_LEN_ED_P_2 + 1,
1190 VEX_LEN_EF_P_2 = VEX_LEN_EE_P_2 + 1,
1191 VEX_LEN_F1_P_2 = VEX_LEN_EF_P_2 + 1,
1192 VEX_LEN_F2_P_2 = VEX_LEN_F1_P_2 + 1,
1193 VEX_LEN_F3_P_2 = VEX_LEN_F2_P_2 + 1,
1194 VEX_LEN_F4_P_2 = VEX_LEN_F3_P_2 + 1,
1195 VEX_LEN_F5_P_2 = VEX_LEN_F4_P_2 + 1,
1196 VEX_LEN_F6_P_2 = VEX_LEN_F5_P_2 + 1,
1197 VEX_LEN_F7_P_2 = VEX_LEN_F6_P_2 + 1,
1198 VEX_LEN_F8_P_2 = VEX_LEN_F7_P_2 + 1,
1199 VEX_LEN_F9_P_2 = VEX_LEN_F8_P_2 + 1,
1200 VEX_LEN_FA_P_2 = VEX_LEN_F9_P_2 + 1,
1201 VEX_LEN_FB_P_2 = VEX_LEN_FA_P_2 + 1,
1202 VEX_LEN_FC_P_2 = VEX_LEN_FB_P_2 + 1,
1203 VEX_LEN_FD_P_2 = VEX_LEN_FC_P_2 + 1,
1204 VEX_LEN_FE_P_2 = VEX_LEN_FD_P_2 + 1,
1205 VEX_LEN_3800_P_2 = VEX_LEN_FE_P_2 + 1,
1206 VEX_LEN_3801_P_2 = VEX_LEN_3800_P_2 + 1,
1207 VEX_LEN_3802_P_2 = VEX_LEN_3801_P_2 + 1,
1208 VEX_LEN_3803_P_2 = VEX_LEN_3802_P_2 + 1,
1209 VEX_LEN_3804_P_2 = VEX_LEN_3803_P_2 + 1,
1210 VEX_LEN_3805_P_2 = VEX_LEN_3804_P_2 + 1,
1211 VEX_LEN_3806_P_2 = VEX_LEN_3805_P_2 + 1,
1212 VEX_LEN_3807_P_2 = VEX_LEN_3806_P_2 + 1,
1213 VEX_LEN_3808_P_2 = VEX_LEN_3807_P_2 + 1,
1214 VEX_LEN_3809_P_2 = VEX_LEN_3808_P_2 + 1,
1215 VEX_LEN_380A_P_2 = VEX_LEN_3809_P_2 + 1,
1216 VEX_LEN_380B_P_2 = VEX_LEN_380A_P_2 + 1,
1217 VEX_LEN_3819_P_2_M_0 = VEX_LEN_380B_P_2 + 1,
1218 VEX_LEN_381A_P_2_M_0 = VEX_LEN_3819_P_2_M_0 + 1,
1219 VEX_LEN_381C_P_2 = VEX_LEN_381A_P_2_M_0 + 1,
1220 VEX_LEN_381D_P_2 = VEX_LEN_381C_P_2 + 1,
1221 VEX_LEN_381E_P_2 = VEX_LEN_381D_P_2 + 1,
1222 VEX_LEN_3820_P_2 = VEX_LEN_381E_P_2 + 1,
1223 VEX_LEN_3821_P_2 = VEX_LEN_3820_P_2 + 1,
1224 VEX_LEN_3822_P_2 = VEX_LEN_3821_P_2 + 1,
1225 VEX_LEN_3823_P_2 = VEX_LEN_3822_P_2 + 1,
1226 VEX_LEN_3824_P_2 = VEX_LEN_3823_P_2 + 1,
1227 VEX_LEN_3825_P_2 = VEX_LEN_3824_P_2 + 1,
1228 VEX_LEN_3828_P_2 = VEX_LEN_3825_P_2 + 1,
1229 VEX_LEN_3829_P_2 = VEX_LEN_3828_P_2 + 1,
1230 VEX_LEN_382A_P_2_M_0 = VEX_LEN_3829_P_2 + 1,
1231 VEX_LEN_382B_P_2 = VEX_LEN_382A_P_2_M_0 + 1,
1232 VEX_LEN_3830_P_2 = VEX_LEN_382B_P_2 + 1,
1233 VEX_LEN_3831_P_2 = VEX_LEN_3830_P_2 + 1,
1234 VEX_LEN_3832_P_2 = VEX_LEN_3831_P_2 + 1,
1235 VEX_LEN_3833_P_2 = VEX_LEN_3832_P_2 + 1,
1236 VEX_LEN_3834_P_2 = VEX_LEN_3833_P_2 + 1,
1237 VEX_LEN_3835_P_2 = VEX_LEN_3834_P_2 + 1,
1238 VEX_LEN_3837_P_2 = VEX_LEN_3835_P_2 + 1,
1239 VEX_LEN_3838_P_2 = VEX_LEN_3837_P_2 + 1,
1240 VEX_LEN_3839_P_2 = VEX_LEN_3838_P_2 + 1,
1241 VEX_LEN_383A_P_2 = VEX_LEN_3839_P_2 + 1,
1242 VEX_LEN_383B_P_2 = VEX_LEN_383A_P_2 + 1,
1243 VEX_LEN_383C_P_2 = VEX_LEN_383B_P_2 + 1,
1244 VEX_LEN_383D_P_2 = VEX_LEN_383C_P_2 + 1,
1245 VEX_LEN_383E_P_2 = VEX_LEN_383D_P_2 + 1,
1246 VEX_LEN_383F_P_2 = VEX_LEN_383E_P_2 + 1,
1247 VEX_LEN_3840_P_2 = VEX_LEN_383F_P_2 + 1,
1248 VEX_LEN_3841_P_2 = VEX_LEN_3840_P_2 + 1,
1249 VEX_LEN_38DB_P_2 = VEX_LEN_3841_P_2 + 1,
1250 VEX_LEN_38DC_P_2 = VEX_LEN_38DB_P_2 + 1,
1251 VEX_LEN_38DD_P_2 = VEX_LEN_38DC_P_2 + 1,
1252 VEX_LEN_38DE_P_2 = VEX_LEN_38DD_P_2 + 1,
1253 VEX_LEN_38DF_P_2 = VEX_LEN_38DE_P_2 + 1,
1254 VEX_LEN_3A06_P_2 = VEX_LEN_38DF_P_2 + 1,
1255 VEX_LEN_3A0A_P_2 = VEX_LEN_3A06_P_2 + 1,
1256 VEX_LEN_3A0B_P_2 = VEX_LEN_3A0A_P_2 + 1,
1257 VEX_LEN_3A0E_P_2 = VEX_LEN_3A0B_P_2 + 1,
1258 VEX_LEN_3A0F_P_2 = VEX_LEN_3A0E_P_2 + 1,
1259 VEX_LEN_3A14_P_2 = VEX_LEN_3A0F_P_2 + 1,
1260 VEX_LEN_3A15_P_2 = VEX_LEN_3A14_P_2 + 1,
1261 VEX_LEN_3A16_P_2 = VEX_LEN_3A15_P_2 + 1,
1262 VEX_LEN_3A17_P_2 = VEX_LEN_3A16_P_2 + 1,
1263 VEX_LEN_3A18_P_2 = VEX_LEN_3A17_P_2 + 1,
1264 VEX_LEN_3A19_P_2 = VEX_LEN_3A18_P_2 + 1,
1265 VEX_LEN_3A20_P_2 = VEX_LEN_3A19_P_2 + 1,
1266 VEX_LEN_3A21_P_2 = VEX_LEN_3A20_P_2 + 1,
1267 VEX_LEN_3A22_P_2 = VEX_LEN_3A21_P_2 + 1,
1268 VEX_LEN_3A41_P_2 = VEX_LEN_3A22_P_2 + 1,
1269 VEX_LEN_3A42_P_2 = VEX_LEN_3A41_P_2 + 1,
1270 VEX_LEN_3A44_P_2 = VEX_LEN_3A42_P_2 + 1,
1271 VEX_LEN_3A4C_P_2 = VEX_LEN_3A44_P_2 + 1,
1272 VEX_LEN_3A60_P_2 = VEX_LEN_3A4C_P_2 + 1,
1273 VEX_LEN_3A61_P_2 = VEX_LEN_3A60_P_2 + 1,
1274 VEX_LEN_3A62_P_2 = VEX_LEN_3A61_P_2 + 1,
1275 VEX_LEN_3A63_P_2 = VEX_LEN_3A62_P_2 + 1,
1276 VEX_LEN_3A6A_P_2 = VEX_LEN_3A63_P_2 + 1,
1277 VEX_LEN_3A6B_P_2 = VEX_LEN_3A6A_P_2 + 1,
1278 VEX_LEN_3A6E_P_2 = VEX_LEN_3A6B_P_2 + 1,
1279 VEX_LEN_3A6F_P_2 = VEX_LEN_3A6E_P_2 + 1,
1280 VEX_LEN_3A7A_P_2 = VEX_LEN_3A6F_P_2 + 1,
1281 VEX_LEN_3A7B_P_2 = VEX_LEN_3A7A_P_2 + 1,
1282 VEX_LEN_3A7E_P_2 = VEX_LEN_3A7B_P_2 + 1,
1283 VEX_LEN_3A7F_P_2 = VEX_LEN_3A7E_P_2 + 1,
1284 VEX_LEN_3ADF_P_2 = VEX_LEN_3A7F_P_2 + 1
1287 typedef void (*op_rtn) (int bytemode, int sizeflag);
1298 /* Upper case letters in the instruction names here are macros.
1299 'A' => print 'b' if no register operands or suffix_always is true
1300 'B' => print 'b' if suffix_always is true
1301 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1303 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1304 suffix_always is true
1305 'E' => print 'e' if 32-bit form of jcxz
1306 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1307 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1308 'H' => print ",pt" or ",pn" branch hint
1309 'I' => honor following macro letter even in Intel mode (implemented only
1310 for some of the macro letters)
1312 'K' => print 'd' or 'q' if rex prefix is present.
1313 'L' => print 'l' if suffix_always is true
1314 'M' => print 'r' if intel_mnemonic is false.
1315 'N' => print 'n' if instruction has no wait "prefix"
1316 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1317 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1318 or suffix_always is true. print 'q' if rex prefix is present.
1319 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1321 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1322 'S' => print 'w', 'l' or 'q' if suffix_always is true
1323 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1324 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1325 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1326 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1327 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1328 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1329 suffix_always is true.
1330 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1331 '!' => change condition from true to false or from false to true.
1332 '%' => add 1 upper case letter to the macro.
1334 2 upper case letter macros:
1335 "XY" => print 'x' or 'y' if no register operands or suffix_always
1337 'XW' => print 's', 'd' depending on the VEX.W bit (for FMA)
1338 'LQ' => print 'l' ('d' in Intel mode) or 'q' for memory operand
1339 or suffix_always is true
1341 Many of the above letters print nothing in Intel mode. See "putop"
1344 Braces '{' and '}', and vertical bars '|', indicate alternative
1345 mnemonic strings for AT&T and Intel. */
1347 static const struct dis386 dis386[] = {
1349 { "addB", { Eb, Gb } },
1350 { "addS", { Ev, Gv } },
1351 { "addB", { Gb, EbS } },
1352 { "addS", { Gv, EvS } },
1353 { "addB", { AL, Ib } },
1354 { "addS", { eAX, Iv } },
1355 { X86_64_TABLE (X86_64_06) },
1356 { X86_64_TABLE (X86_64_07) },
1358 { "orB", { Eb, Gb } },
1359 { "orS", { Ev, Gv } },
1360 { "orB", { Gb, EbS } },
1361 { "orS", { Gv, EvS } },
1362 { "orB", { AL, Ib } },
1363 { "orS", { eAX, Iv } },
1364 { X86_64_TABLE (X86_64_0D) },
1365 { "(bad)", { XX } }, /* 0x0f extended opcode escape */
1367 { "adcB", { Eb, Gb } },
1368 { "adcS", { Ev, Gv } },
1369 { "adcB", { Gb, EbS } },
1370 { "adcS", { Gv, EvS } },
1371 { "adcB", { AL, Ib } },
1372 { "adcS", { eAX, Iv } },
1373 { X86_64_TABLE (X86_64_16) },
1374 { X86_64_TABLE (X86_64_17) },
1376 { "sbbB", { Eb, Gb } },
1377 { "sbbS", { Ev, Gv } },
1378 { "sbbB", { Gb, EbS } },
1379 { "sbbS", { Gv, EvS } },
1380 { "sbbB", { AL, Ib } },
1381 { "sbbS", { eAX, Iv } },
1382 { X86_64_TABLE (X86_64_1E) },
1383 { X86_64_TABLE (X86_64_1F) },
1385 { "andB", { Eb, Gb } },
1386 { "andS", { Ev, Gv } },
1387 { "andB", { Gb, EbS } },
1388 { "andS", { Gv, EvS } },
1389 { "andB", { AL, Ib } },
1390 { "andS", { eAX, Iv } },
1391 { "(bad)", { XX } }, /* SEG ES prefix */
1392 { X86_64_TABLE (X86_64_27) },
1394 { "subB", { Eb, Gb } },
1395 { "subS", { Ev, Gv } },
1396 { "subB", { Gb, EbS } },
1397 { "subS", { Gv, EvS } },
1398 { "subB", { AL, Ib } },
1399 { "subS", { eAX, Iv } },
1400 { "(bad)", { XX } }, /* SEG CS prefix */
1401 { X86_64_TABLE (X86_64_2F) },
1403 { "xorB", { Eb, Gb } },
1404 { "xorS", { Ev, Gv } },
1405 { "xorB", { Gb, EbS } },
1406 { "xorS", { Gv, EvS } },
1407 { "xorB", { AL, Ib } },
1408 { "xorS", { eAX, Iv } },
1409 { "(bad)", { XX } }, /* SEG SS prefix */
1410 { X86_64_TABLE (X86_64_37) },
1412 { "cmpB", { Eb, Gb } },
1413 { "cmpS", { Ev, Gv } },
1414 { "cmpB", { Gb, EbS } },
1415 { "cmpS", { Gv, EvS } },
1416 { "cmpB", { AL, Ib } },
1417 { "cmpS", { eAX, Iv } },
1418 { "(bad)", { XX } }, /* SEG DS prefix */
1419 { X86_64_TABLE (X86_64_3F) },
1421 { "inc{S|}", { RMeAX } },
1422 { "inc{S|}", { RMeCX } },
1423 { "inc{S|}", { RMeDX } },
1424 { "inc{S|}", { RMeBX } },
1425 { "inc{S|}", { RMeSP } },
1426 { "inc{S|}", { RMeBP } },
1427 { "inc{S|}", { RMeSI } },
1428 { "inc{S|}", { RMeDI } },
1430 { "dec{S|}", { RMeAX } },
1431 { "dec{S|}", { RMeCX } },
1432 { "dec{S|}", { RMeDX } },
1433 { "dec{S|}", { RMeBX } },
1434 { "dec{S|}", { RMeSP } },
1435 { "dec{S|}", { RMeBP } },
1436 { "dec{S|}", { RMeSI } },
1437 { "dec{S|}", { RMeDI } },
1439 { "pushV", { RMrAX } },
1440 { "pushV", { RMrCX } },
1441 { "pushV", { RMrDX } },
1442 { "pushV", { RMrBX } },
1443 { "pushV", { RMrSP } },
1444 { "pushV", { RMrBP } },
1445 { "pushV", { RMrSI } },
1446 { "pushV", { RMrDI } },
1448 { "popV", { RMrAX } },
1449 { "popV", { RMrCX } },
1450 { "popV", { RMrDX } },
1451 { "popV", { RMrBX } },
1452 { "popV", { RMrSP } },
1453 { "popV", { RMrBP } },
1454 { "popV", { RMrSI } },
1455 { "popV", { RMrDI } },
1457 { X86_64_TABLE (X86_64_60) },
1458 { X86_64_TABLE (X86_64_61) },
1459 { X86_64_TABLE (X86_64_62) },
1460 { X86_64_TABLE (X86_64_63) },
1461 { "(bad)", { XX } }, /* seg fs */
1462 { "(bad)", { XX } }, /* seg gs */
1463 { "(bad)", { XX } }, /* op size prefix */
1464 { "(bad)", { XX } }, /* adr size prefix */
1466 { "pushT", { Iq } },
1467 { "imulS", { Gv, Ev, Iv } },
1468 { "pushT", { sIb } },
1469 { "imulS", { Gv, Ev, sIb } },
1470 { "ins{b|}", { Ybr, indirDX } },
1471 { X86_64_TABLE (X86_64_6D) },
1472 { "outs{b|}", { indirDXr, Xb } },
1473 { X86_64_TABLE (X86_64_6F) },
1475 { "joH", { Jb, XX, cond_jump_flag } },
1476 { "jnoH", { Jb, XX, cond_jump_flag } },
1477 { "jbH", { Jb, XX, cond_jump_flag } },
1478 { "jaeH", { Jb, XX, cond_jump_flag } },
1479 { "jeH", { Jb, XX, cond_jump_flag } },
1480 { "jneH", { Jb, XX, cond_jump_flag } },
1481 { "jbeH", { Jb, XX, cond_jump_flag } },
1482 { "jaH", { Jb, XX, cond_jump_flag } },
1484 { "jsH", { Jb, XX, cond_jump_flag } },
1485 { "jnsH", { Jb, XX, cond_jump_flag } },
1486 { "jpH", { Jb, XX, cond_jump_flag } },
1487 { "jnpH", { Jb, XX, cond_jump_flag } },
1488 { "jlH", { Jb, XX, cond_jump_flag } },
1489 { "jgeH", { Jb, XX, cond_jump_flag } },
1490 { "jleH", { Jb, XX, cond_jump_flag } },
1491 { "jgH", { Jb, XX, cond_jump_flag } },
1493 { REG_TABLE (REG_80) },
1494 { REG_TABLE (REG_81) },
1495 { "(bad)", { XX } },
1496 { REG_TABLE (REG_82) },
1497 { "testB", { Eb, Gb } },
1498 { "testS", { Ev, Gv } },
1499 { "xchgB", { Eb, Gb } },
1500 { "xchgS", { Ev, Gv } },
1502 { "movB", { Eb, Gb } },
1503 { "movS", { Ev, Gv } },
1504 { "movB", { Gb, EbS } },
1505 { "movS", { Gv, EvS } },
1506 { "movD", { Sv, Sw } },
1507 { MOD_TABLE (MOD_8D) },
1508 { "movD", { Sw, Sv } },
1509 { REG_TABLE (REG_8F) },
1511 { PREFIX_TABLE (PREFIX_90) },
1512 { "xchgS", { RMeCX, eAX } },
1513 { "xchgS", { RMeDX, eAX } },
1514 { "xchgS", { RMeBX, eAX } },
1515 { "xchgS", { RMeSP, eAX } },
1516 { "xchgS", { RMeBP, eAX } },
1517 { "xchgS", { RMeSI, eAX } },
1518 { "xchgS", { RMeDI, eAX } },
1520 { "cW{t|}R", { XX } },
1521 { "cR{t|}O", { XX } },
1522 { X86_64_TABLE (X86_64_9A) },
1523 { "(bad)", { XX } }, /* fwait */
1524 { "pushfT", { XX } },
1525 { "popfT", { XX } },
1529 { "movB", { AL, Ob } },
1530 { "movS", { eAX, Ov } },
1531 { "movB", { Ob, AL } },
1532 { "movS", { Ov, eAX } },
1533 { "movs{b|}", { Ybr, Xb } },
1534 { "movs{R|}", { Yvr, Xv } },
1535 { "cmps{b|}", { Xb, Yb } },
1536 { "cmps{R|}", { Xv, Yv } },
1538 { "testB", { AL, Ib } },
1539 { "testS", { eAX, Iv } },
1540 { "stosB", { Ybr, AL } },
1541 { "stosS", { Yvr, eAX } },
1542 { "lodsB", { ALr, Xb } },
1543 { "lodsS", { eAXr, Xv } },
1544 { "scasB", { AL, Yb } },
1545 { "scasS", { eAX, Yv } },
1547 { "movB", { RMAL, Ib } },
1548 { "movB", { RMCL, Ib } },
1549 { "movB", { RMDL, Ib } },
1550 { "movB", { RMBL, Ib } },
1551 { "movB", { RMAH, Ib } },
1552 { "movB", { RMCH, Ib } },
1553 { "movB", { RMDH, Ib } },
1554 { "movB", { RMBH, Ib } },
1556 { "movS", { RMeAX, Iv64 } },
1557 { "movS", { RMeCX, Iv64 } },
1558 { "movS", { RMeDX, Iv64 } },
1559 { "movS", { RMeBX, Iv64 } },
1560 { "movS", { RMeSP, Iv64 } },
1561 { "movS", { RMeBP, Iv64 } },
1562 { "movS", { RMeSI, Iv64 } },
1563 { "movS", { RMeDI, Iv64 } },
1565 { REG_TABLE (REG_C0) },
1566 { REG_TABLE (REG_C1) },
1569 { X86_64_TABLE (X86_64_C4) },
1570 { X86_64_TABLE (X86_64_C5) },
1571 { REG_TABLE (REG_C6) },
1572 { REG_TABLE (REG_C7) },
1574 { "enterT", { Iw, Ib } },
1575 { "leaveT", { XX } },
1576 { "Jret{|f}P", { Iw } },
1577 { "Jret{|f}P", { XX } },
1580 { X86_64_TABLE (X86_64_CE) },
1581 { "iretP", { XX } },
1583 { REG_TABLE (REG_D0) },
1584 { REG_TABLE (REG_D1) },
1585 { REG_TABLE (REG_D2) },
1586 { REG_TABLE (REG_D3) },
1587 { X86_64_TABLE (X86_64_D4) },
1588 { X86_64_TABLE (X86_64_D5) },
1589 { "(bad)", { XX } },
1590 { "xlat", { DSBX } },
1601 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
1602 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
1603 { "loopFH", { Jb, XX, loop_jcxz_flag } },
1604 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
1605 { "inB", { AL, Ib } },
1606 { "inG", { zAX, Ib } },
1607 { "outB", { Ib, AL } },
1608 { "outG", { Ib, zAX } },
1610 { "callT", { Jv } },
1612 { X86_64_TABLE (X86_64_EA) },
1614 { "inB", { AL, indirDX } },
1615 { "inG", { zAX, indirDX } },
1616 { "outB", { indirDX, AL } },
1617 { "outG", { indirDX, zAX } },
1619 { "(bad)", { XX } }, /* lock prefix */
1620 { "icebp", { XX } },
1621 { "(bad)", { XX } }, /* repne */
1622 { "(bad)", { XX } }, /* repz */
1625 { REG_TABLE (REG_F6) },
1626 { REG_TABLE (REG_F7) },
1634 { REG_TABLE (REG_FE) },
1635 { REG_TABLE (REG_FF) },
1638 static const struct dis386 dis386_twobyte[] = {
1640 { REG_TABLE (REG_0F00 ) },
1641 { REG_TABLE (REG_0F01 ) },
1642 { "larS", { Gv, Ew } },
1643 { "lslS", { Gv, Ew } },
1644 { "(bad)", { XX } },
1645 { "syscall", { XX } },
1647 { "sysretP", { XX } },
1650 { "wbinvd", { XX } },
1651 { "(bad)", { XX } },
1653 { "(bad)", { XX } },
1654 { REG_TABLE (REG_0F0D) },
1655 { "femms", { XX } },
1656 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
1658 { PREFIX_TABLE (PREFIX_0F10) },
1659 { PREFIX_TABLE (PREFIX_0F11) },
1660 { PREFIX_TABLE (PREFIX_0F12) },
1661 { MOD_TABLE (MOD_0F13) },
1662 { "unpcklpX", { XM, EXx } },
1663 { "unpckhpX", { XM, EXx } },
1664 { PREFIX_TABLE (PREFIX_0F16) },
1665 { MOD_TABLE (MOD_0F17) },
1667 { REG_TABLE (REG_0F18) },
1676 { MOD_TABLE (MOD_0F20) },
1677 { MOD_TABLE (MOD_0F21) },
1678 { MOD_TABLE (MOD_0F22) },
1679 { MOD_TABLE (MOD_0F23) },
1680 { MOD_TABLE (MOD_0F24) },
1681 { "(bad)", { XX } },
1682 { MOD_TABLE (MOD_0F26) },
1683 { "(bad)", { XX } },
1685 { "movapX", { XM, EXx } },
1686 { "movapX", { EXxS, XM } },
1687 { PREFIX_TABLE (PREFIX_0F2A) },
1688 { PREFIX_TABLE (PREFIX_0F2B) },
1689 { PREFIX_TABLE (PREFIX_0F2C) },
1690 { PREFIX_TABLE (PREFIX_0F2D) },
1691 { PREFIX_TABLE (PREFIX_0F2E) },
1692 { PREFIX_TABLE (PREFIX_0F2F) },
1694 { "wrmsr", { XX } },
1695 { "rdtsc", { XX } },
1696 { "rdmsr", { XX } },
1697 { "rdpmc", { XX } },
1698 { "sysenter", { XX } },
1699 { "sysexit", { XX } },
1700 { "(bad)", { XX } },
1701 { "getsec", { XX } },
1703 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
1704 { "(bad)", { XX } },
1705 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
1706 { "(bad)", { XX } },
1707 { "(bad)", { XX } },
1708 { "(bad)", { XX } },
1709 { "(bad)", { XX } },
1710 { "(bad)", { XX } },
1712 { "cmovoS", { Gv, Ev } },
1713 { "cmovnoS", { Gv, Ev } },
1714 { "cmovbS", { Gv, Ev } },
1715 { "cmovaeS", { Gv, Ev } },
1716 { "cmoveS", { Gv, Ev } },
1717 { "cmovneS", { Gv, Ev } },
1718 { "cmovbeS", { Gv, Ev } },
1719 { "cmovaS", { Gv, Ev } },
1721 { "cmovsS", { Gv, Ev } },
1722 { "cmovnsS", { Gv, Ev } },
1723 { "cmovpS", { Gv, Ev } },
1724 { "cmovnpS", { Gv, Ev } },
1725 { "cmovlS", { Gv, Ev } },
1726 { "cmovgeS", { Gv, Ev } },
1727 { "cmovleS", { Gv, Ev } },
1728 { "cmovgS", { Gv, Ev } },
1730 { MOD_TABLE (MOD_0F51) },
1731 { PREFIX_TABLE (PREFIX_0F51) },
1732 { PREFIX_TABLE (PREFIX_0F52) },
1733 { PREFIX_TABLE (PREFIX_0F53) },
1734 { "andpX", { XM, EXx } },
1735 { "andnpX", { XM, EXx } },
1736 { "orpX", { XM, EXx } },
1737 { "xorpX", { XM, EXx } },
1739 { PREFIX_TABLE (PREFIX_0F58) },
1740 { PREFIX_TABLE (PREFIX_0F59) },
1741 { PREFIX_TABLE (PREFIX_0F5A) },
1742 { PREFIX_TABLE (PREFIX_0F5B) },
1743 { PREFIX_TABLE (PREFIX_0F5C) },
1744 { PREFIX_TABLE (PREFIX_0F5D) },
1745 { PREFIX_TABLE (PREFIX_0F5E) },
1746 { PREFIX_TABLE (PREFIX_0F5F) },
1748 { PREFIX_TABLE (PREFIX_0F60) },
1749 { PREFIX_TABLE (PREFIX_0F61) },
1750 { PREFIX_TABLE (PREFIX_0F62) },
1751 { "packsswb", { MX, EM } },
1752 { "pcmpgtb", { MX, EM } },
1753 { "pcmpgtw", { MX, EM } },
1754 { "pcmpgtd", { MX, EM } },
1755 { "packuswb", { MX, EM } },
1757 { "punpckhbw", { MX, EM } },
1758 { "punpckhwd", { MX, EM } },
1759 { "punpckhdq", { MX, EM } },
1760 { "packssdw", { MX, EM } },
1761 { PREFIX_TABLE (PREFIX_0F6C) },
1762 { PREFIX_TABLE (PREFIX_0F6D) },
1763 { "movK", { MX, Edq } },
1764 { PREFIX_TABLE (PREFIX_0F6F) },
1766 { PREFIX_TABLE (PREFIX_0F70) },
1767 { REG_TABLE (REG_0F71) },
1768 { REG_TABLE (REG_0F72) },
1769 { REG_TABLE (REG_0F73) },
1770 { "pcmpeqb", { MX, EM } },
1771 { "pcmpeqw", { MX, EM } },
1772 { "pcmpeqd", { MX, EM } },
1775 { PREFIX_TABLE (PREFIX_0F78) },
1776 { PREFIX_TABLE (PREFIX_0F79) },
1777 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
1778 { "(bad)", { XX } },
1779 { PREFIX_TABLE (PREFIX_0F7C) },
1780 { PREFIX_TABLE (PREFIX_0F7D) },
1781 { PREFIX_TABLE (PREFIX_0F7E) },
1782 { PREFIX_TABLE (PREFIX_0F7F) },
1784 { "joH", { Jv, XX, cond_jump_flag } },
1785 { "jnoH", { Jv, XX, cond_jump_flag } },
1786 { "jbH", { Jv, XX, cond_jump_flag } },
1787 { "jaeH", { Jv, XX, cond_jump_flag } },
1788 { "jeH", { Jv, XX, cond_jump_flag } },
1789 { "jneH", { Jv, XX, cond_jump_flag } },
1790 { "jbeH", { Jv, XX, cond_jump_flag } },
1791 { "jaH", { Jv, XX, cond_jump_flag } },
1793 { "jsH", { Jv, XX, cond_jump_flag } },
1794 { "jnsH", { Jv, XX, cond_jump_flag } },
1795 { "jpH", { Jv, XX, cond_jump_flag } },
1796 { "jnpH", { Jv, XX, cond_jump_flag } },
1797 { "jlH", { Jv, XX, cond_jump_flag } },
1798 { "jgeH", { Jv, XX, cond_jump_flag } },
1799 { "jleH", { Jv, XX, cond_jump_flag } },
1800 { "jgH", { Jv, XX, cond_jump_flag } },
1803 { "setno", { Eb } },
1805 { "setae", { Eb } },
1807 { "setne", { Eb } },
1808 { "setbe", { Eb } },
1812 { "setns", { Eb } },
1814 { "setnp", { Eb } },
1816 { "setge", { Eb } },
1817 { "setle", { Eb } },
1820 { "pushT", { fs } },
1822 { "cpuid", { XX } },
1823 { "btS", { Ev, Gv } },
1824 { "shldS", { Ev, Gv, Ib } },
1825 { "shldS", { Ev, Gv, CL } },
1826 { REG_TABLE (REG_0FA6) },
1827 { REG_TABLE (REG_0FA7) },
1829 { "pushT", { gs } },
1832 { "btsS", { Ev, Gv } },
1833 { "shrdS", { Ev, Gv, Ib } },
1834 { "shrdS", { Ev, Gv, CL } },
1835 { REG_TABLE (REG_0FAE) },
1836 { "imulS", { Gv, Ev } },
1838 { "cmpxchgB", { Eb, Gb } },
1839 { "cmpxchgS", { Ev, Gv } },
1840 { MOD_TABLE (MOD_0FB2) },
1841 { "btrS", { Ev, Gv } },
1842 { MOD_TABLE (MOD_0FB4) },
1843 { MOD_TABLE (MOD_0FB5) },
1844 { "movz{bR|x}", { Gv, Eb } },
1845 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
1847 { PREFIX_TABLE (PREFIX_0FB8) },
1849 { REG_TABLE (REG_0FBA) },
1850 { "btcS", { Ev, Gv } },
1851 { "bsfS", { Gv, Ev } },
1852 { PREFIX_TABLE (PREFIX_0FBD) },
1853 { "movs{bR|x}", { Gv, Eb } },
1854 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
1856 { "xaddB", { Eb, Gb } },
1857 { "xaddS", { Ev, Gv } },
1858 { PREFIX_TABLE (PREFIX_0FC2) },
1859 { PREFIX_TABLE (PREFIX_0FC3) },
1860 { "pinsrw", { MX, Edqw, Ib } },
1861 { "pextrw", { Gdq, MS, Ib } },
1862 { "shufpX", { XM, EXx, Ib } },
1863 { REG_TABLE (REG_0FC7) },
1865 { "bswap", { RMeAX } },
1866 { "bswap", { RMeCX } },
1867 { "bswap", { RMeDX } },
1868 { "bswap", { RMeBX } },
1869 { "bswap", { RMeSP } },
1870 { "bswap", { RMeBP } },
1871 { "bswap", { RMeSI } },
1872 { "bswap", { RMeDI } },
1874 { PREFIX_TABLE (PREFIX_0FD0) },
1875 { "psrlw", { MX, EM } },
1876 { "psrld", { MX, EM } },
1877 { "psrlq", { MX, EM } },
1878 { "paddq", { MX, EM } },
1879 { "pmullw", { MX, EM } },
1880 { PREFIX_TABLE (PREFIX_0FD6) },
1881 { MOD_TABLE (MOD_0FD7) },
1883 { "psubusb", { MX, EM } },
1884 { "psubusw", { MX, EM } },
1885 { "pminub", { MX, EM } },
1886 { "pand", { MX, EM } },
1887 { "paddusb", { MX, EM } },
1888 { "paddusw", { MX, EM } },
1889 { "pmaxub", { MX, EM } },
1890 { "pandn", { MX, EM } },
1892 { "pavgb", { MX, EM } },
1893 { "psraw", { MX, EM } },
1894 { "psrad", { MX, EM } },
1895 { "pavgw", { MX, EM } },
1896 { "pmulhuw", { MX, EM } },
1897 { "pmulhw", { MX, EM } },
1898 { PREFIX_TABLE (PREFIX_0FE6) },
1899 { PREFIX_TABLE (PREFIX_0FE7) },
1901 { "psubsb", { MX, EM } },
1902 { "psubsw", { MX, EM } },
1903 { "pminsw", { MX, EM } },
1904 { "por", { MX, EM } },
1905 { "paddsb", { MX, EM } },
1906 { "paddsw", { MX, EM } },
1907 { "pmaxsw", { MX, EM } },
1908 { "pxor", { MX, EM } },
1910 { PREFIX_TABLE (PREFIX_0FF0) },
1911 { "psllw", { MX, EM } },
1912 { "pslld", { MX, EM } },
1913 { "psllq", { MX, EM } },
1914 { "pmuludq", { MX, EM } },
1915 { "pmaddwd", { MX, EM } },
1916 { "psadbw", { MX, EM } },
1917 { PREFIX_TABLE (PREFIX_0FF7) },
1919 { "psubb", { MX, EM } },
1920 { "psubw", { MX, EM } },
1921 { "psubd", { MX, EM } },
1922 { "psubq", { MX, EM } },
1923 { "paddb", { MX, EM } },
1924 { "paddw", { MX, EM } },
1925 { "paddd", { MX, EM } },
1926 { "(bad)", { XX } },
1929 static const unsigned char onebyte_has_modrm[256] = {
1930 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1931 /* ------------------------------- */
1932 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1933 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1934 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1935 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1936 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1937 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1938 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1939 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1940 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1941 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1942 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1943 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1944 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1945 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1946 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1947 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1948 /* ------------------------------- */
1949 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1952 static const unsigned char twobyte_has_modrm[256] = {
1953 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1954 /* ------------------------------- */
1955 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1956 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1957 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1958 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1959 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1960 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1961 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1962 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1963 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1964 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1965 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1966 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1967 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1968 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1969 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1970 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1971 /* ------------------------------- */
1972 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1975 static char obuf[100];
1977 static char *mnemonicendp;
1978 static char scratchbuf[100];
1979 static unsigned char *start_codep;
1980 static unsigned char *insn_codep;
1981 static unsigned char *codep;
1982 static const char *lock_prefix;
1983 static const char *data_prefix;
1984 static const char *addr_prefix;
1985 static const char *repz_prefix;
1986 static const char *repnz_prefix;
1987 static disassemble_info *the_info;
1995 static unsigned char need_modrm;
1998 int register_specifier;
2004 static unsigned char need_vex;
2005 static unsigned char need_vex_reg;
2006 static unsigned char vex_w_done;
2014 /* If we are accessing mod/rm/reg without need_modrm set, then the
2015 values are stale. Hitting this abort likely indicates that you
2016 need to update onebyte_has_modrm or twobyte_has_modrm. */
2017 #define MODRM_CHECK if (!need_modrm) abort ()
2019 static const char **names64;
2020 static const char **names32;
2021 static const char **names16;
2022 static const char **names8;
2023 static const char **names8rex;
2024 static const char **names_seg;
2025 static const char *index64;
2026 static const char *index32;
2027 static const char **index16;
2029 static const char *intel_names64[] = {
2030 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2031 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2033 static const char *intel_names32[] = {
2034 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2035 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2037 static const char *intel_names16[] = {
2038 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2039 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2041 static const char *intel_names8[] = {
2042 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2044 static const char *intel_names8rex[] = {
2045 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2046 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2048 static const char *intel_names_seg[] = {
2049 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2051 static const char *intel_index64 = "riz";
2052 static const char *intel_index32 = "eiz";
2053 static const char *intel_index16[] = {
2054 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2057 static const char *att_names64[] = {
2058 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2059 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2061 static const char *att_names32[] = {
2062 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2063 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2065 static const char *att_names16[] = {
2066 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2067 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2069 static const char *att_names8[] = {
2070 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2072 static const char *att_names8rex[] = {
2073 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2074 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2076 static const char *att_names_seg[] = {
2077 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2079 static const char *att_index64 = "%riz";
2080 static const char *att_index32 = "%eiz";
2081 static const char *att_index16[] = {
2082 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2085 static const struct dis386 reg_table[][8] = {
2088 { "addA", { Eb, Ib } },
2089 { "orA", { Eb, Ib } },
2090 { "adcA", { Eb, Ib } },
2091 { "sbbA", { Eb, Ib } },
2092 { "andA", { Eb, Ib } },
2093 { "subA", { Eb, Ib } },
2094 { "xorA", { Eb, Ib } },
2095 { "cmpA", { Eb, Ib } },
2099 { "addQ", { Ev, Iv } },
2100 { "orQ", { Ev, Iv } },
2101 { "adcQ", { Ev, Iv } },
2102 { "sbbQ", { Ev, Iv } },
2103 { "andQ", { Ev, Iv } },
2104 { "subQ", { Ev, Iv } },
2105 { "xorQ", { Ev, Iv } },
2106 { "cmpQ", { Ev, Iv } },
2110 { "addQ", { Ev, sIb } },
2111 { "orQ", { Ev, sIb } },
2112 { "adcQ", { Ev, sIb } },
2113 { "sbbQ", { Ev, sIb } },
2114 { "andQ", { Ev, sIb } },
2115 { "subQ", { Ev, sIb } },
2116 { "xorQ", { Ev, sIb } },
2117 { "cmpQ", { Ev, sIb } },
2121 { "popU", { stackEv } },
2122 { "(bad)", { XX } },
2123 { "(bad)", { XX } },
2124 { "(bad)", { XX } },
2125 { "(bad)", { XX } },
2126 { "(bad)", { XX } },
2127 { "(bad)", { XX } },
2128 { "(bad)", { XX } },
2132 { "rolA", { Eb, Ib } },
2133 { "rorA", { Eb, Ib } },
2134 { "rclA", { Eb, Ib } },
2135 { "rcrA", { Eb, Ib } },
2136 { "shlA", { Eb, Ib } },
2137 { "shrA", { Eb, Ib } },
2138 { "(bad)", { XX } },
2139 { "sarA", { Eb, Ib } },
2143 { "rolQ", { Ev, Ib } },
2144 { "rorQ", { Ev, Ib } },
2145 { "rclQ", { Ev, Ib } },
2146 { "rcrQ", { Ev, Ib } },
2147 { "shlQ", { Ev, Ib } },
2148 { "shrQ", { Ev, Ib } },
2149 { "(bad)", { XX } },
2150 { "sarQ", { Ev, Ib } },
2154 { "movA", { Eb, Ib } },
2155 { "(bad)", { XX } },
2156 { "(bad)", { XX } },
2157 { "(bad)", { XX } },
2158 { "(bad)", { XX } },
2159 { "(bad)", { XX } },
2160 { "(bad)", { XX } },
2161 { "(bad)", { XX } },
2165 { "movQ", { Ev, Iv } },
2166 { "(bad)", { XX } },
2167 { "(bad)", { XX } },
2168 { "(bad)", { XX } },
2169 { "(bad)", { XX } },
2170 { "(bad)", { XX } },
2171 { "(bad)", { XX } },
2172 { "(bad)", { XX } },
2176 { "rolA", { Eb, I1 } },
2177 { "rorA", { Eb, I1 } },
2178 { "rclA", { Eb, I1 } },
2179 { "rcrA", { Eb, I1 } },
2180 { "shlA", { Eb, I1 } },
2181 { "shrA", { Eb, I1 } },
2182 { "(bad)", { XX } },
2183 { "sarA", { Eb, I1 } },
2187 { "rolQ", { Ev, I1 } },
2188 { "rorQ", { Ev, I1 } },
2189 { "rclQ", { Ev, I1 } },
2190 { "rcrQ", { Ev, I1 } },
2191 { "shlQ", { Ev, I1 } },
2192 { "shrQ", { Ev, I1 } },
2193 { "(bad)", { XX } },
2194 { "sarQ", { Ev, I1 } },
2198 { "rolA", { Eb, CL } },
2199 { "rorA", { Eb, CL } },
2200 { "rclA", { Eb, CL } },
2201 { "rcrA", { Eb, CL } },
2202 { "shlA", { Eb, CL } },
2203 { "shrA", { Eb, CL } },
2204 { "(bad)", { XX } },
2205 { "sarA", { Eb, CL } },
2209 { "rolQ", { Ev, CL } },
2210 { "rorQ", { Ev, CL } },
2211 { "rclQ", { Ev, CL } },
2212 { "rcrQ", { Ev, CL } },
2213 { "shlQ", { Ev, CL } },
2214 { "shrQ", { Ev, CL } },
2215 { "(bad)", { XX } },
2216 { "sarQ", { Ev, CL } },
2220 { "testA", { Eb, Ib } },
2221 { "(bad)", { XX } },
2224 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
2225 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
2226 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
2227 { "idivA", { Eb } }, /* and idiv for consistency. */
2231 { "testQ", { Ev, Iv } },
2232 { "(bad)", { XX } },
2235 { "mulQ", { Ev } }, /* Don't print the implicit register. */
2236 { "imulQ", { Ev } },
2238 { "idivQ", { Ev } },
2244 { "(bad)", { XX } },
2245 { "(bad)", { XX } },
2246 { "(bad)", { XX } },
2247 { "(bad)", { XX } },
2248 { "(bad)", { XX } },
2249 { "(bad)", { XX } },
2255 { "callT", { indirEv } },
2256 { "JcallT", { indirEp } },
2257 { "jmpT", { indirEv } },
2258 { "JjmpT", { indirEp } },
2259 { "pushU", { stackEv } },
2260 { "(bad)", { XX } },
2264 { "sldtD", { Sv } },
2270 { "(bad)", { XX } },
2271 { "(bad)", { XX } },
2275 { MOD_TABLE (MOD_0F01_REG_0) },
2276 { MOD_TABLE (MOD_0F01_REG_1) },
2277 { MOD_TABLE (MOD_0F01_REG_2) },
2278 { MOD_TABLE (MOD_0F01_REG_3) },
2279 { "smswD", { Sv } },
2280 { "(bad)", { XX } },
2282 { MOD_TABLE (MOD_0F01_REG_7) },
2286 { "prefetch", { Eb } },
2287 { "prefetchw", { Eb } },
2288 { "(bad)", { XX } },
2289 { "(bad)", { XX } },
2290 { "(bad)", { XX } },
2291 { "(bad)", { XX } },
2292 { "(bad)", { XX } },
2293 { "(bad)", { XX } },
2297 { MOD_TABLE (MOD_0F18_REG_0) },
2298 { MOD_TABLE (MOD_0F18_REG_1) },
2299 { MOD_TABLE (MOD_0F18_REG_2) },
2300 { MOD_TABLE (MOD_0F18_REG_3) },
2301 { "(bad)", { XX } },
2302 { "(bad)", { XX } },
2303 { "(bad)", { XX } },
2304 { "(bad)", { XX } },
2308 { "(bad)", { XX } },
2309 { "(bad)", { XX } },
2310 { MOD_TABLE (MOD_0F71_REG_2) },
2311 { "(bad)", { XX } },
2312 { MOD_TABLE (MOD_0F71_REG_4) },
2313 { "(bad)", { XX } },
2314 { MOD_TABLE (MOD_0F71_REG_6) },
2315 { "(bad)", { XX } },
2319 { "(bad)", { XX } },
2320 { "(bad)", { XX } },
2321 { MOD_TABLE (MOD_0F72_REG_2) },
2322 { "(bad)", { XX } },
2323 { MOD_TABLE (MOD_0F72_REG_4) },
2324 { "(bad)", { XX } },
2325 { MOD_TABLE (MOD_0F72_REG_6) },
2326 { "(bad)", { XX } },
2330 { "(bad)", { XX } },
2331 { "(bad)", { XX } },
2332 { MOD_TABLE (MOD_0F73_REG_2) },
2333 { MOD_TABLE (MOD_0F73_REG_3) },
2334 { "(bad)", { XX } },
2335 { "(bad)", { XX } },
2336 { MOD_TABLE (MOD_0F73_REG_6) },
2337 { MOD_TABLE (MOD_0F73_REG_7) },
2341 { "montmul", { { OP_0f07, 0 } } },
2342 { "xsha1", { { OP_0f07, 0 } } },
2343 { "xsha256", { { OP_0f07, 0 } } },
2344 { "(bad)", { { OP_0f07, 0 } } },
2345 { "(bad)", { { OP_0f07, 0 } } },
2346 { "(bad)", { { OP_0f07, 0 } } },
2347 { "(bad)", { { OP_0f07, 0 } } },
2348 { "(bad)", { { OP_0f07, 0 } } },
2352 { "xstore-rng", { { OP_0f07, 0 } } },
2353 { "xcrypt-ecb", { { OP_0f07, 0 } } },
2354 { "xcrypt-cbc", { { OP_0f07, 0 } } },
2355 { "xcrypt-ctr", { { OP_0f07, 0 } } },
2356 { "xcrypt-cfb", { { OP_0f07, 0 } } },
2357 { "xcrypt-ofb", { { OP_0f07, 0 } } },
2358 { "(bad)", { { OP_0f07, 0 } } },
2359 { "(bad)", { { OP_0f07, 0 } } },
2363 { MOD_TABLE (MOD_0FAE_REG_0) },
2364 { MOD_TABLE (MOD_0FAE_REG_1) },
2365 { MOD_TABLE (MOD_0FAE_REG_2) },
2366 { MOD_TABLE (MOD_0FAE_REG_3) },
2367 { MOD_TABLE (MOD_0FAE_REG_4) },
2368 { MOD_TABLE (MOD_0FAE_REG_5) },
2369 { MOD_TABLE (MOD_0FAE_REG_6) },
2370 { MOD_TABLE (MOD_0FAE_REG_7) },
2374 { "(bad)", { XX } },
2375 { "(bad)", { XX } },
2376 { "(bad)", { XX } },
2377 { "(bad)", { XX } },
2378 { "btQ", { Ev, Ib } },
2379 { "btsQ", { Ev, Ib } },
2380 { "btrQ", { Ev, Ib } },
2381 { "btcQ", { Ev, Ib } },
2385 { "(bad)", { XX } },
2386 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2387 { "(bad)", { XX } },
2388 { "(bad)", { XX } },
2389 { "(bad)", { XX } },
2390 { "(bad)", { XX } },
2391 { MOD_TABLE (MOD_0FC7_REG_6) },
2392 { MOD_TABLE (MOD_0FC7_REG_7) },
2396 { "(bad)", { XX } },
2397 { "(bad)", { XX } },
2398 { MOD_TABLE (MOD_VEX_71_REG_2) },
2399 { "(bad)", { XX } },
2400 { MOD_TABLE (MOD_VEX_71_REG_4) },
2401 { "(bad)", { XX } },
2402 { MOD_TABLE (MOD_VEX_71_REG_6) },
2403 { "(bad)", { XX } },
2407 { "(bad)", { XX } },
2408 { "(bad)", { XX } },
2409 { MOD_TABLE (MOD_VEX_72_REG_2) },
2410 { "(bad)", { XX } },
2411 { MOD_TABLE (MOD_VEX_72_REG_4) },
2412 { "(bad)", { XX } },
2413 { MOD_TABLE (MOD_VEX_72_REG_6) },
2414 { "(bad)", { XX } },
2418 { "(bad)", { XX } },
2419 { "(bad)", { XX } },
2420 { MOD_TABLE (MOD_VEX_73_REG_2) },
2421 { MOD_TABLE (MOD_VEX_73_REG_3) },
2422 { "(bad)", { XX } },
2423 { "(bad)", { XX } },
2424 { MOD_TABLE (MOD_VEX_73_REG_6) },
2425 { MOD_TABLE (MOD_VEX_73_REG_7) },
2429 { "(bad)", { XX } },
2430 { "(bad)", { XX } },
2431 { MOD_TABLE (MOD_VEX_AE_REG_2) },
2432 { MOD_TABLE (MOD_VEX_AE_REG_3) },
2433 { "(bad)", { XX } },
2434 { "(bad)", { XX } },
2435 { "(bad)", { XX } },
2436 { "(bad)", { XX } },
2440 static const struct dis386 prefix_table[][4] = {
2443 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2444 { "pause", { XX } },
2445 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2446 { "(bad)", { XX } },
2451 { "movups", { XM, EXx } },
2452 { "movss", { XM, EXd } },
2453 { "movupd", { XM, EXx } },
2454 { "movsd", { XM, EXq } },
2459 { "movups", { EXxS, XM } },
2460 { "movss", { EXdS, XM } },
2461 { "movupd", { EXxS, XM } },
2462 { "movsd", { EXqS, XM } },
2467 { MOD_TABLE (MOD_0F12_PREFIX_0) },
2468 { "movsldup", { XM, EXx } },
2469 { "movlpd", { XM, EXq } },
2470 { "movddup", { XM, EXq } },
2475 { MOD_TABLE (MOD_0F16_PREFIX_0) },
2476 { "movshdup", { XM, EXx } },
2477 { "movhpd", { XM, EXq } },
2478 { "(bad)", { XX } },
2483 { "cvtpi2ps", { XM, EMCq } },
2484 { "cvtsi2ss%LQ", { XM, Ev } },
2485 { "cvtpi2pd", { XM, EMCq } },
2486 { "cvtsi2sd%LQ", { XM, Ev } },
2491 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2492 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2493 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2494 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2499 { "cvttps2pi", { MXC, EXq } },
2500 { "cvttss2siY", { Gv, EXd } },
2501 { "cvttpd2pi", { MXC, EXx } },
2502 { "cvttsd2siY", { Gv, EXq } },
2507 { "cvtps2pi", { MXC, EXq } },
2508 { "cvtss2siY", { Gv, EXd } },
2509 { "cvtpd2pi", { MXC, EXx } },
2510 { "cvtsd2siY", { Gv, EXq } },
2515 { "ucomiss",{ XM, EXd } },
2516 { "(bad)", { XX } },
2517 { "ucomisd",{ XM, EXq } },
2518 { "(bad)", { XX } },
2523 { "comiss", { XM, EXd } },
2524 { "(bad)", { XX } },
2525 { "comisd", { XM, EXq } },
2526 { "(bad)", { XX } },
2531 { "sqrtps", { XM, EXx } },
2532 { "sqrtss", { XM, EXd } },
2533 { "sqrtpd", { XM, EXx } },
2534 { "sqrtsd", { XM, EXq } },
2539 { "rsqrtps",{ XM, EXx } },
2540 { "rsqrtss",{ XM, EXd } },
2541 { "(bad)", { XX } },
2542 { "(bad)", { XX } },
2547 { "rcpps", { XM, EXx } },
2548 { "rcpss", { XM, EXd } },
2549 { "(bad)", { XX } },
2550 { "(bad)", { XX } },
2555 { "addps", { XM, EXx } },
2556 { "addss", { XM, EXd } },
2557 { "addpd", { XM, EXx } },
2558 { "addsd", { XM, EXq } },
2563 { "mulps", { XM, EXx } },
2564 { "mulss", { XM, EXd } },
2565 { "mulpd", { XM, EXx } },
2566 { "mulsd", { XM, EXq } },
2571 { "cvtps2pd", { XM, EXq } },
2572 { "cvtss2sd", { XM, EXd } },
2573 { "cvtpd2ps", { XM, EXx } },
2574 { "cvtsd2ss", { XM, EXq } },
2579 { "cvtdq2ps", { XM, EXx } },
2580 { "cvttps2dq", { XM, EXx } },
2581 { "cvtps2dq", { XM, EXx } },
2582 { "(bad)", { XX } },
2587 { "subps", { XM, EXx } },
2588 { "subss", { XM, EXd } },
2589 { "subpd", { XM, EXx } },
2590 { "subsd", { XM, EXq } },
2595 { "minps", { XM, EXx } },
2596 { "minss", { XM, EXd } },
2597 { "minpd", { XM, EXx } },
2598 { "minsd", { XM, EXq } },
2603 { "divps", { XM, EXx } },
2604 { "divss", { XM, EXd } },
2605 { "divpd", { XM, EXx } },
2606 { "divsd", { XM, EXq } },
2611 { "maxps", { XM, EXx } },
2612 { "maxss", { XM, EXd } },
2613 { "maxpd", { XM, EXx } },
2614 { "maxsd", { XM, EXq } },
2619 { "punpcklbw",{ MX, EMd } },
2620 { "(bad)", { XX } },
2621 { "punpcklbw",{ MX, EMx } },
2622 { "(bad)", { XX } },
2627 { "punpcklwd",{ MX, EMd } },
2628 { "(bad)", { XX } },
2629 { "punpcklwd",{ MX, EMx } },
2630 { "(bad)", { XX } },
2635 { "punpckldq",{ MX, EMd } },
2636 { "(bad)", { XX } },
2637 { "punpckldq",{ MX, EMx } },
2638 { "(bad)", { XX } },
2643 { "(bad)", { XX } },
2644 { "(bad)", { XX } },
2645 { "punpcklqdq", { XM, EXx } },
2646 { "(bad)", { XX } },
2651 { "(bad)", { XX } },
2652 { "(bad)", { XX } },
2653 { "punpckhqdq", { XM, EXx } },
2654 { "(bad)", { XX } },
2659 { "movq", { MX, EM } },
2660 { "movdqu", { XM, EXx } },
2661 { "movdqa", { XM, EXx } },
2662 { "(bad)", { XX } },
2667 { "pshufw", { MX, EM, Ib } },
2668 { "pshufhw",{ XM, EXx, Ib } },
2669 { "pshufd", { XM, EXx, Ib } },
2670 { "pshuflw",{ XM, EXx, Ib } },
2673 /* PREFIX_0F73_REG_3 */
2675 { "(bad)", { XX } },
2676 { "(bad)", { XX } },
2677 { "psrldq", { XS, Ib } },
2678 { "(bad)", { XX } },
2681 /* PREFIX_0F73_REG_7 */
2683 { "(bad)", { XX } },
2684 { "(bad)", { XX } },
2685 { "pslldq", { XS, Ib } },
2686 { "(bad)", { XX } },
2691 {"vmread", { Em, Gm } },
2693 {"extrq", { XS, Ib, Ib } },
2694 {"insertq", { XM, XS, Ib, Ib } },
2699 {"vmwrite", { Gm, Em } },
2701 {"extrq", { XM, XS } },
2702 {"insertq", { XM, XS } },
2707 { "(bad)", { XX } },
2708 { "(bad)", { XX } },
2709 { "haddpd", { XM, EXx } },
2710 { "haddps", { XM, EXx } },
2715 { "(bad)", { XX } },
2716 { "(bad)", { XX } },
2717 { "hsubpd", { XM, EXx } },
2718 { "hsubps", { XM, EXx } },
2723 { "movK", { Edq, MX } },
2724 { "movq", { XM, EXq } },
2725 { "movK", { Edq, XM } },
2726 { "(bad)", { XX } },
2731 { "movq", { EMS, MX } },
2732 { "movdqu", { EXxS, XM } },
2733 { "movdqa", { EXxS, XM } },
2734 { "(bad)", { XX } },
2739 { "(bad)", { XX } },
2740 { "popcntS", { Gv, Ev } },
2741 { "(bad)", { XX } },
2742 { "(bad)", { XX } },
2747 { "bsrS", { Gv, Ev } },
2748 { "lzcntS", { Gv, Ev } },
2749 { "bsrS", { Gv, Ev } },
2750 { "(bad)", { XX } },
2755 { "cmpps", { XM, EXx, CMP } },
2756 { "cmpss", { XM, EXd, CMP } },
2757 { "cmppd", { XM, EXx, CMP } },
2758 { "cmpsd", { XM, EXq, CMP } },
2763 { "movntiS", { Ma, Gv } },
2764 { "(bad)", { XX } },
2765 { "(bad)", { XX } },
2766 { "(bad)", { XX } },
2769 /* PREFIX_0FC7_REG_6 */
2771 { "vmptrld",{ Mq } },
2772 { "vmxon", { Mq } },
2773 { "vmclear",{ Mq } },
2774 { "(bad)", { XX } },
2779 { "(bad)", { XX } },
2780 { "(bad)", { XX } },
2781 { "addsubpd", { XM, EXx } },
2782 { "addsubps", { XM, EXx } },
2787 { "(bad)", { XX } },
2788 { "movq2dq",{ XM, MS } },
2789 { "movq", { EXqS, XM } },
2790 { "movdq2q",{ MX, XS } },
2795 { "(bad)", { XX } },
2796 { "cvtdq2pd", { XM, EXq } },
2797 { "cvttpd2dq", { XM, EXx } },
2798 { "cvtpd2dq", { XM, EXx } },
2803 { "movntq", { Mq, MX } },
2804 { "(bad)", { XX } },
2805 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
2806 { "(bad)", { XX } },
2811 { "(bad)", { XX } },
2812 { "(bad)", { XX } },
2813 { "(bad)", { XX } },
2814 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
2819 { "maskmovq", { MX, MS } },
2820 { "(bad)", { XX } },
2821 { "maskmovdqu", { XM, XS } },
2822 { "(bad)", { XX } },
2827 { "(bad)", { XX } },
2828 { "(bad)", { XX } },
2829 { "pblendvb", { XM, EXx, XMM0 } },
2830 { "(bad)", { XX } },
2835 { "(bad)", { XX } },
2836 { "(bad)", { XX } },
2837 { "blendvps", { XM, EXx, XMM0 } },
2838 { "(bad)", { XX } },
2843 { "(bad)", { XX } },
2844 { "(bad)", { XX } },
2845 { "blendvpd", { XM, EXx, XMM0 } },
2846 { "(bad)", { XX } },
2851 { "(bad)", { XX } },
2852 { "(bad)", { XX } },
2853 { "ptest", { XM, EXx } },
2854 { "(bad)", { XX } },
2859 { "(bad)", { XX } },
2860 { "(bad)", { XX } },
2861 { "pmovsxbw", { XM, EXq } },
2862 { "(bad)", { XX } },
2867 { "(bad)", { XX } },
2868 { "(bad)", { XX } },
2869 { "pmovsxbd", { XM, EXd } },
2870 { "(bad)", { XX } },
2875 { "(bad)", { XX } },
2876 { "(bad)", { XX } },
2877 { "pmovsxbq", { XM, EXw } },
2878 { "(bad)", { XX } },
2883 { "(bad)", { XX } },
2884 { "(bad)", { XX } },
2885 { "pmovsxwd", { XM, EXq } },
2886 { "(bad)", { XX } },
2891 { "(bad)", { XX } },
2892 { "(bad)", { XX } },
2893 { "pmovsxwq", { XM, EXd } },
2894 { "(bad)", { XX } },
2899 { "(bad)", { XX } },
2900 { "(bad)", { XX } },
2901 { "pmovsxdq", { XM, EXq } },
2902 { "(bad)", { XX } },
2907 { "(bad)", { XX } },
2908 { "(bad)", { XX } },
2909 { "pmuldq", { XM, EXx } },
2910 { "(bad)", { XX } },
2915 { "(bad)", { XX } },
2916 { "(bad)", { XX } },
2917 { "pcmpeqq", { XM, EXx } },
2918 { "(bad)", { XX } },
2923 { "(bad)", { XX } },
2924 { "(bad)", { XX } },
2925 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
2926 { "(bad)", { XX } },
2931 { "(bad)", { XX } },
2932 { "(bad)", { XX } },
2933 { "packusdw", { XM, EXx } },
2934 { "(bad)", { XX } },
2939 { "(bad)", { XX } },
2940 { "(bad)", { XX } },
2941 { "pmovzxbw", { XM, EXq } },
2942 { "(bad)", { XX } },
2947 { "(bad)", { XX } },
2948 { "(bad)", { XX } },
2949 { "pmovzxbd", { XM, EXd } },
2950 { "(bad)", { XX } },
2955 { "(bad)", { XX } },
2956 { "(bad)", { XX } },
2957 { "pmovzxbq", { XM, EXw } },
2958 { "(bad)", { XX } },
2963 { "(bad)", { XX } },
2964 { "(bad)", { XX } },
2965 { "pmovzxwd", { XM, EXq } },
2966 { "(bad)", { XX } },
2971 { "(bad)", { XX } },
2972 { "(bad)", { XX } },
2973 { "pmovzxwq", { XM, EXd } },
2974 { "(bad)", { XX } },
2979 { "(bad)", { XX } },
2980 { "(bad)", { XX } },
2981 { "pmovzxdq", { XM, EXq } },
2982 { "(bad)", { XX } },
2987 { "(bad)", { XX } },
2988 { "(bad)", { XX } },
2989 { "pcmpgtq", { XM, EXx } },
2990 { "(bad)", { XX } },
2995 { "(bad)", { XX } },
2996 { "(bad)", { XX } },
2997 { "pminsb", { XM, EXx } },
2998 { "(bad)", { XX } },
3003 { "(bad)", { XX } },
3004 { "(bad)", { XX } },
3005 { "pminsd", { XM, EXx } },
3006 { "(bad)", { XX } },
3011 { "(bad)", { XX } },
3012 { "(bad)", { XX } },
3013 { "pminuw", { XM, EXx } },
3014 { "(bad)", { XX } },
3019 { "(bad)", { XX } },
3020 { "(bad)", { XX } },
3021 { "pminud", { XM, EXx } },
3022 { "(bad)", { XX } },
3027 { "(bad)", { XX } },
3028 { "(bad)", { XX } },
3029 { "pmaxsb", { XM, EXx } },
3030 { "(bad)", { XX } },
3035 { "(bad)", { XX } },
3036 { "(bad)", { XX } },
3037 { "pmaxsd", { XM, EXx } },
3038 { "(bad)", { XX } },
3043 { "(bad)", { XX } },
3044 { "(bad)", { XX } },
3045 { "pmaxuw", { XM, EXx } },
3046 { "(bad)", { XX } },
3051 { "(bad)", { XX } },
3052 { "(bad)", { XX } },
3053 { "pmaxud", { XM, EXx } },
3054 { "(bad)", { XX } },
3059 { "(bad)", { XX } },
3060 { "(bad)", { XX } },
3061 { "pmulld", { XM, EXx } },
3062 { "(bad)", { XX } },
3067 { "(bad)", { XX } },
3068 { "(bad)", { XX } },
3069 { "phminposuw", { XM, EXx } },
3070 { "(bad)", { XX } },
3075 { "(bad)", { XX } },
3076 { "(bad)", { XX } },
3077 { "invept", { Gm, Mo } },
3078 { "(bad)", { XX } },
3083 { "(bad)", { XX } },
3084 { "(bad)", { XX } },
3085 { "invvpid", { Gm, Mo } },
3086 { "(bad)", { XX } },
3091 { "(bad)", { XX } },
3092 { "(bad)", { XX } },
3093 { "aesimc", { XM, EXx } },
3094 { "(bad)", { XX } },
3099 { "(bad)", { XX } },
3100 { "(bad)", { XX } },
3101 { "aesenc", { XM, EXx } },
3102 { "(bad)", { XX } },
3107 { "(bad)", { XX } },
3108 { "(bad)", { XX } },
3109 { "aesenclast", { XM, EXx } },
3110 { "(bad)", { XX } },
3115 { "(bad)", { XX } },
3116 { "(bad)", { XX } },
3117 { "aesdec", { XM, EXx } },
3118 { "(bad)", { XX } },
3123 { "(bad)", { XX } },
3124 { "(bad)", { XX } },
3125 { "aesdeclast", { XM, EXx } },
3126 { "(bad)", { XX } },
3131 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3132 { "(bad)", { XX } },
3133 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3134 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
3139 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3140 { "(bad)", { XX } },
3141 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3142 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
3147 { "(bad)", { XX } },
3148 { "(bad)", { XX } },
3149 { "roundps", { XM, EXx, Ib } },
3150 { "(bad)", { XX } },
3155 { "(bad)", { XX } },
3156 { "(bad)", { XX } },
3157 { "roundpd", { XM, EXx, Ib } },
3158 { "(bad)", { XX } },
3163 { "(bad)", { XX } },
3164 { "(bad)", { XX } },
3165 { "roundss", { XM, EXd, Ib } },
3166 { "(bad)", { XX } },
3171 { "(bad)", { XX } },
3172 { "(bad)", { XX } },
3173 { "roundsd", { XM, EXq, Ib } },
3174 { "(bad)", { XX } },
3179 { "(bad)", { XX } },
3180 { "(bad)", { XX } },
3181 { "blendps", { XM, EXx, Ib } },
3182 { "(bad)", { XX } },
3187 { "(bad)", { XX } },
3188 { "(bad)", { XX } },
3189 { "blendpd", { XM, EXx, Ib } },
3190 { "(bad)", { XX } },
3195 { "(bad)", { XX } },
3196 { "(bad)", { XX } },
3197 { "pblendw", { XM, EXx, Ib } },
3198 { "(bad)", { XX } },
3203 { "(bad)", { XX } },
3204 { "(bad)", { XX } },
3205 { "pextrb", { Edqb, XM, Ib } },
3206 { "(bad)", { XX } },
3211 { "(bad)", { XX } },
3212 { "(bad)", { XX } },
3213 { "pextrw", { Edqw, XM, Ib } },
3214 { "(bad)", { XX } },
3219 { "(bad)", { XX } },
3220 { "(bad)", { XX } },
3221 { "pextrK", { Edq, XM, Ib } },
3222 { "(bad)", { XX } },
3227 { "(bad)", { XX } },
3228 { "(bad)", { XX } },
3229 { "extractps", { Edqd, XM, Ib } },
3230 { "(bad)", { XX } },
3235 { "(bad)", { XX } },
3236 { "(bad)", { XX } },
3237 { "pinsrb", { XM, Edqb, Ib } },
3238 { "(bad)", { XX } },
3243 { "(bad)", { XX } },
3244 { "(bad)", { XX } },
3245 { "insertps", { XM, EXd, Ib } },
3246 { "(bad)", { XX } },
3251 { "(bad)", { XX } },
3252 { "(bad)", { XX } },
3253 { "pinsrK", { XM, Edq, Ib } },
3254 { "(bad)", { XX } },
3259 { "(bad)", { XX } },
3260 { "(bad)", { XX } },
3261 { "dpps", { XM, EXx, Ib } },
3262 { "(bad)", { XX } },
3267 { "(bad)", { XX } },
3268 { "(bad)", { XX } },
3269 { "dppd", { XM, EXx, Ib } },
3270 { "(bad)", { XX } },
3275 { "(bad)", { XX } },
3276 { "(bad)", { XX } },
3277 { "mpsadbw", { XM, EXx, Ib } },
3278 { "(bad)", { XX } },
3283 { "(bad)", { XX } },
3284 { "(bad)", { XX } },
3285 { "pclmulqdq", { XM, EXx, PCLMUL } },
3286 { "(bad)", { XX } },
3291 { "(bad)", { XX } },
3292 { "(bad)", { XX } },
3293 { "pcmpestrm", { XM, EXx, Ib } },
3294 { "(bad)", { XX } },
3299 { "(bad)", { XX } },
3300 { "(bad)", { XX } },
3301 { "pcmpestri", { XM, EXx, Ib } },
3302 { "(bad)", { XX } },
3307 { "(bad)", { XX } },
3308 { "(bad)", { XX } },
3309 { "pcmpistrm", { XM, EXx, Ib } },
3310 { "(bad)", { XX } },
3315 { "(bad)", { XX } },
3316 { "(bad)", { XX } },
3317 { "pcmpistri", { XM, EXx, Ib } },
3318 { "(bad)", { XX } },
3323 { "(bad)", { XX } },
3324 { "(bad)", { XX } },
3325 { "aeskeygenassist", { XM, EXx, Ib } },
3326 { "(bad)", { XX } },
3331 { "vmovups", { XM, EXx } },
3332 { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3333 { "vmovupd", { XM, EXx } },
3334 { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3339 { "vmovups", { EXxS, XM } },
3340 { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3341 { "vmovupd", { EXxS, XM } },
3342 { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3347 { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3348 { "vmovsldup", { XM, EXx } },
3349 { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3350 { "vmovddup", { XM, EXymmq } },
3355 { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3356 { "vmovshdup", { XM, EXx } },
3357 { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3358 { "(bad)", { XX } },
3363 { "(bad)", { XX } },
3364 { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3365 { "(bad)", { XX } },
3366 { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3371 { "(bad)", { XX } },
3372 { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3373 { "(bad)", { XX } },
3374 { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3379 { "(bad)", { XX } },
3380 { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3381 { "(bad)", { XX } },
3382 { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3387 { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3388 { "(bad)", { XX } },
3389 { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3390 { "(bad)", { XX } },
3395 { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3396 { "(bad)", { XX } },
3397 { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3398 { "(bad)", { XX } },
3403 { "vsqrtps", { XM, EXx } },
3404 { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3405 { "vsqrtpd", { XM, EXx } },
3406 { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3411 { "vrsqrtps", { XM, EXx } },
3412 { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3413 { "(bad)", { XX } },
3414 { "(bad)", { XX } },
3419 { "vrcpps", { XM, EXx } },
3420 { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3421 { "(bad)", { XX } },
3422 { "(bad)", { XX } },
3427 { "vaddps", { XM, Vex, EXx } },
3428 { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3429 { "vaddpd", { XM, Vex, EXx } },
3430 { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3435 { "vmulps", { XM, Vex, EXx } },
3436 { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3437 { "vmulpd", { XM, Vex, EXx } },
3438 { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3443 { "vcvtps2pd", { XM, EXxmmq } },
3444 { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3445 { "vcvtpd2ps%XY", { XMM, EXx } },
3446 { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3451 { "vcvtdq2ps", { XM, EXx } },
3452 { "vcvttps2dq", { XM, EXx } },
3453 { "vcvtps2dq", { XM, EXx } },
3454 { "(bad)", { XX } },
3459 { "vsubps", { XM, Vex, EXx } },
3460 { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3461 { "vsubpd", { XM, Vex, EXx } },
3462 { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3467 { "vminps", { XM, Vex, EXx } },
3468 { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3469 { "vminpd", { XM, Vex, EXx } },
3470 { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3475 { "vdivps", { XM, Vex, EXx } },
3476 { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3477 { "vdivpd", { XM, Vex, EXx } },
3478 { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3483 { "vmaxps", { XM, Vex, EXx } },
3484 { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3485 { "vmaxpd", { XM, Vex, EXx } },
3486 { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3491 { "(bad)", { XX } },
3492 { "(bad)", { XX } },
3493 { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3494 { "(bad)", { XX } },
3499 { "(bad)", { XX } },
3500 { "(bad)", { XX } },
3501 { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3502 { "(bad)", { XX } },
3507 { "(bad)", { XX } },
3508 { "(bad)", { XX } },
3509 { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3510 { "(bad)", { XX } },
3515 { "(bad)", { XX } },
3516 { "(bad)", { XX } },
3517 { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3518 { "(bad)", { XX } },
3523 { "(bad)", { XX } },
3524 { "(bad)", { XX } },
3525 { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3526 { "(bad)", { XX } },
3531 { "(bad)", { XX } },
3532 { "(bad)", { XX } },
3533 { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3534 { "(bad)", { XX } },
3539 { "(bad)", { XX } },
3540 { "(bad)", { XX } },
3541 { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3542 { "(bad)", { XX } },
3547 { "(bad)", { XX } },
3548 { "(bad)", { XX } },
3549 { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3550 { "(bad)", { XX } },
3555 { "(bad)", { XX } },
3556 { "(bad)", { XX } },
3557 { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3558 { "(bad)", { XX } },
3563 { "(bad)", { XX } },
3564 { "(bad)", { XX } },
3565 { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3566 { "(bad)", { XX } },
3571 { "(bad)", { XX } },
3572 { "(bad)", { XX } },
3573 { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3574 { "(bad)", { XX } },
3579 { "(bad)", { XX } },
3580 { "(bad)", { XX } },
3581 { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3582 { "(bad)", { XX } },
3587 { "(bad)", { XX } },
3588 { "(bad)", { XX } },
3589 { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3590 { "(bad)", { XX } },
3595 { "(bad)", { XX } },
3596 { "(bad)", { XX } },
3597 { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3598 { "(bad)", { XX } },
3603 { "(bad)", { XX } },
3604 { "(bad)", { XX } },
3605 { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3606 { "(bad)", { XX } },
3611 { "(bad)", { XX } },
3612 { "vmovdqu", { XM, EXx } },
3613 { "vmovdqa", { XM, EXx } },
3614 { "(bad)", { XX } },
3619 { "(bad)", { XX } },
3620 { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3621 { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3622 { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3625 /* PREFIX_VEX_71_REG_2 */
3627 { "(bad)", { XX } },
3628 { "(bad)", { XX } },
3629 { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3630 { "(bad)", { XX } },
3633 /* PREFIX_VEX_71_REG_4 */
3635 { "(bad)", { XX } },
3636 { "(bad)", { XX } },
3637 { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3638 { "(bad)", { XX } },
3641 /* PREFIX_VEX_71_REG_6 */
3643 { "(bad)", { XX } },
3644 { "(bad)", { XX } },
3645 { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3646 { "(bad)", { XX } },
3649 /* PREFIX_VEX_72_REG_2 */
3651 { "(bad)", { XX } },
3652 { "(bad)", { XX } },
3653 { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3654 { "(bad)", { XX } },
3657 /* PREFIX_VEX_72_REG_4 */
3659 { "(bad)", { XX } },
3660 { "(bad)", { XX } },
3661 { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3662 { "(bad)", { XX } },
3665 /* PREFIX_VEX_72_REG_6 */
3667 { "(bad)", { XX } },
3668 { "(bad)", { XX } },
3669 { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3670 { "(bad)", { XX } },
3673 /* PREFIX_VEX_73_REG_2 */
3675 { "(bad)", { XX } },
3676 { "(bad)", { XX } },
3677 { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3678 { "(bad)", { XX } },
3681 /* PREFIX_VEX_73_REG_3 */
3683 { "(bad)", { XX } },
3684 { "(bad)", { XX } },
3685 { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3686 { "(bad)", { XX } },
3689 /* PREFIX_VEX_73_REG_6 */
3691 { "(bad)", { XX } },
3692 { "(bad)", { XX } },
3693 { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3694 { "(bad)", { XX } },
3697 /* PREFIX_VEX_73_REG_7 */
3699 { "(bad)", { XX } },
3700 { "(bad)", { XX } },
3701 { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3702 { "(bad)", { XX } },
3707 { "(bad)", { XX } },
3708 { "(bad)", { XX } },
3709 { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3710 { "(bad)", { XX } },
3715 { "(bad)", { XX } },
3716 { "(bad)", { XX } },
3717 { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3718 { "(bad)", { XX } },
3723 { "(bad)", { XX } },
3724 { "(bad)", { XX } },
3725 { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3726 { "(bad)", { XX } },
3732 { "(bad)", { XX } },
3733 { "(bad)", { XX } },
3734 { "(bad)", { XX } },
3739 { "(bad)", { XX } },
3740 { "(bad)", { XX } },
3741 { "vhaddpd", { XM, Vex, EXx } },
3742 { "vhaddps", { XM, Vex, EXx } },
3747 { "(bad)", { XX } },
3748 { "(bad)", { XX } },
3749 { "vhsubpd", { XM, Vex, EXx } },
3750 { "vhsubps", { XM, Vex, EXx } },
3755 { "(bad)", { XX } },
3756 { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3757 { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3758 { "(bad)", { XX } },
3763 { "(bad)", { XX } },
3764 { "vmovdqu", { EXxS, XM } },
3765 { "vmovdqa", { EXxS, XM } },
3766 { "(bad)", { XX } },
3771 { "vcmpps", { XM, Vex, EXx, VCMP } },
3772 { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3773 { "vcmppd", { XM, Vex, EXx, VCMP } },
3774 { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3779 { "(bad)", { XX } },
3780 { "(bad)", { XX } },
3781 { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3782 { "(bad)", { XX } },
3787 { "(bad)", { XX } },
3788 { "(bad)", { XX } },
3789 { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3790 { "(bad)", { XX } },
3795 { "(bad)", { XX } },
3796 { "(bad)", { XX } },
3797 { "vaddsubpd", { XM, Vex, EXx } },
3798 { "vaddsubps", { XM, Vex, EXx } },
3803 { "(bad)", { XX } },
3804 { "(bad)", { XX } },
3805 { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3806 { "(bad)", { XX } },
3811 { "(bad)", { XX } },
3812 { "(bad)", { XX } },
3813 { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3814 { "(bad)", { XX } },
3819 { "(bad)", { XX } },
3820 { "(bad)", { XX } },
3821 { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3822 { "(bad)", { XX } },
3827 { "(bad)", { XX } },
3828 { "(bad)", { XX } },
3829 { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3830 { "(bad)", { XX } },
3835 { "(bad)", { XX } },
3836 { "(bad)", { XX } },
3837 { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
3838 { "(bad)", { XX } },
3843 { "(bad)", { XX } },
3844 { "(bad)", { XX } },
3845 { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
3846 { "(bad)", { XX } },
3851 { "(bad)", { XX } },
3852 { "(bad)", { XX } },
3853 { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
3854 { "(bad)", { XX } },
3859 { "(bad)", { XX } },
3860 { "(bad)", { XX } },
3861 { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
3862 { "(bad)", { XX } },
3867 { "(bad)", { XX } },
3868 { "(bad)", { XX } },
3869 { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
3870 { "(bad)", { XX } },
3875 { "(bad)", { XX } },
3876 { "(bad)", { XX } },
3877 { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
3878 { "(bad)", { XX } },
3883 { "(bad)", { XX } },
3884 { "(bad)", { XX } },
3885 { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
3886 { "(bad)", { XX } },
3891 { "(bad)", { XX } },
3892 { "(bad)", { XX } },
3893 { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
3894 { "(bad)", { XX } },
3899 { "(bad)", { XX } },
3900 { "(bad)", { XX } },
3901 { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
3902 { "(bad)", { XX } },
3907 { "(bad)", { XX } },
3908 { "(bad)", { XX } },
3909 { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
3910 { "(bad)", { XX } },
3915 { "(bad)", { XX } },
3916 { "(bad)", { XX } },
3917 { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
3918 { "(bad)", { XX } },
3923 { "(bad)", { XX } },
3924 { "(bad)", { XX } },
3925 { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
3926 { "(bad)", { XX } },
3931 { "(bad)", { XX } },
3932 { "(bad)", { XX } },
3933 { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
3934 { "(bad)", { XX } },
3939 { "(bad)", { XX } },
3940 { "(bad)", { XX } },
3941 { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
3942 { "(bad)", { XX } },
3947 { "(bad)", { XX } },
3948 { "(bad)", { XX } },
3949 { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
3950 { "(bad)", { XX } },
3955 { "(bad)", { XX } },
3956 { "(bad)", { XX } },
3957 { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
3958 { "(bad)", { XX } },
3963 { "(bad)", { XX } },
3964 { "(bad)", { XX } },
3965 { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
3966 { "(bad)", { XX } },
3971 { "(bad)", { XX } },
3972 { "vcvtdq2pd", { XM, EXxmmq } },
3973 { "vcvttpd2dq%XY", { XMM, EXx } },
3974 { "vcvtpd2dq%XY", { XMM, EXx } },
3979 { "(bad)", { XX } },
3980 { "(bad)", { XX } },
3981 { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
3982 { "(bad)", { XX } },
3987 { "(bad)", { XX } },
3988 { "(bad)", { XX } },
3989 { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
3990 { "(bad)", { XX } },
3995 { "(bad)", { XX } },
3996 { "(bad)", { XX } },
3997 { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
3998 { "(bad)", { XX } },
4003 { "(bad)", { XX } },
4004 { "(bad)", { XX } },
4005 { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
4006 { "(bad)", { XX } },
4011 { "(bad)", { XX } },
4012 { "(bad)", { XX } },
4013 { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
4014 { "(bad)", { XX } },
4019 { "(bad)", { XX } },
4020 { "(bad)", { XX } },
4021 { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
4022 { "(bad)", { XX } },
4027 { "(bad)", { XX } },
4028 { "(bad)", { XX } },
4029 { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
4030 { "(bad)", { XX } },
4035 { "(bad)", { XX } },
4036 { "(bad)", { XX } },
4037 { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4038 { "(bad)", { XX } },
4043 { "(bad)", { XX } },
4044 { "(bad)", { XX } },
4045 { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4046 { "(bad)", { XX } },
4051 { "(bad)", { XX } },
4052 { "(bad)", { XX } },
4053 { "(bad)", { XX } },
4054 { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4059 { "(bad)", { XX } },
4060 { "(bad)", { XX } },
4061 { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4062 { "(bad)", { XX } },
4067 { "(bad)", { XX } },
4068 { "(bad)", { XX } },
4069 { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4070 { "(bad)", { XX } },
4075 { "(bad)", { XX } },
4076 { "(bad)", { XX } },
4077 { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4078 { "(bad)", { XX } },
4083 { "(bad)", { XX } },
4084 { "(bad)", { XX } },
4085 { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4086 { "(bad)", { XX } },
4091 { "(bad)", { XX } },
4092 { "(bad)", { XX } },
4093 { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4094 { "(bad)", { XX } },
4099 { "(bad)", { XX } },
4100 { "(bad)", { XX } },
4101 { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4102 { "(bad)", { XX } },
4107 { "(bad)", { XX } },
4108 { "(bad)", { XX } },
4109 { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4110 { "(bad)", { XX } },
4115 { "(bad)", { XX } },
4116 { "(bad)", { XX } },
4117 { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4118 { "(bad)", { XX } },
4123 { "(bad)", { XX } },
4124 { "(bad)", { XX } },
4125 { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4126 { "(bad)", { XX } },
4131 { "(bad)", { XX } },
4132 { "(bad)", { XX } },
4133 { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4134 { "(bad)", { XX } },
4139 { "(bad)", { XX } },
4140 { "(bad)", { XX } },
4141 { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4142 { "(bad)", { XX } },
4147 { "(bad)", { XX } },
4148 { "(bad)", { XX } },
4149 { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4150 { "(bad)", { XX } },
4155 { "(bad)", { XX } },
4156 { "(bad)", { XX } },
4157 { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4158 { "(bad)", { XX } },
4163 { "(bad)", { XX } },
4164 { "(bad)", { XX } },
4165 { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4166 { "(bad)", { XX } },
4169 /* PREFIX_VEX_3800 */
4171 { "(bad)", { XX } },
4172 { "(bad)", { XX } },
4173 { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4174 { "(bad)", { XX } },
4177 /* PREFIX_VEX_3801 */
4179 { "(bad)", { XX } },
4180 { "(bad)", { XX } },
4181 { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4182 { "(bad)", { XX } },
4185 /* PREFIX_VEX_3802 */
4187 { "(bad)", { XX } },
4188 { "(bad)", { XX } },
4189 { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4190 { "(bad)", { XX } },
4193 /* PREFIX_VEX_3803 */
4195 { "(bad)", { XX } },
4196 { "(bad)", { XX } },
4197 { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4198 { "(bad)", { XX } },
4201 /* PREFIX_VEX_3804 */
4203 { "(bad)", { XX } },
4204 { "(bad)", { XX } },
4205 { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4206 { "(bad)", { XX } },
4209 /* PREFIX_VEX_3805 */
4211 { "(bad)", { XX } },
4212 { "(bad)", { XX } },
4213 { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4214 { "(bad)", { XX } },
4217 /* PREFIX_VEX_3806 */
4219 { "(bad)", { XX } },
4220 { "(bad)", { XX } },
4221 { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4222 { "(bad)", { XX } },
4225 /* PREFIX_VEX_3807 */
4227 { "(bad)", { XX } },
4228 { "(bad)", { XX } },
4229 { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4230 { "(bad)", { XX } },
4233 /* PREFIX_VEX_3808 */
4235 { "(bad)", { XX } },
4236 { "(bad)", { XX } },
4237 { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4238 { "(bad)", { XX } },
4241 /* PREFIX_VEX_3809 */
4243 { "(bad)", { XX } },
4244 { "(bad)", { XX } },
4245 { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4246 { "(bad)", { XX } },
4249 /* PREFIX_VEX_380A */
4251 { "(bad)", { XX } },
4252 { "(bad)", { XX } },
4253 { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4254 { "(bad)", { XX } },
4257 /* PREFIX_VEX_380B */
4259 { "(bad)", { XX } },
4260 { "(bad)", { XX } },
4261 { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4262 { "(bad)", { XX } },
4265 /* PREFIX_VEX_380C */
4267 { "(bad)", { XX } },
4268 { "(bad)", { XX } },
4269 { "vpermilps", { XM, Vex, EXx } },
4270 { "(bad)", { XX } },
4273 /* PREFIX_VEX_380D */
4275 { "(bad)", { XX } },
4276 { "(bad)", { XX } },
4277 { "vpermilpd", { XM, Vex, EXx } },
4278 { "(bad)", { XX } },
4281 /* PREFIX_VEX_380E */
4283 { "(bad)", { XX } },
4284 { "(bad)", { XX } },
4285 { "vtestps", { XM, EXx } },
4286 { "(bad)", { XX } },
4289 /* PREFIX_VEX_380F */
4291 { "(bad)", { XX } },
4292 { "(bad)", { XX } },
4293 { "vtestpd", { XM, EXx } },
4294 { "(bad)", { XX } },
4297 /* PREFIX_VEX_3817 */
4299 { "(bad)", { XX } },
4300 { "(bad)", { XX } },
4301 { "vptest", { XM, EXx } },
4302 { "(bad)", { XX } },
4305 /* PREFIX_VEX_3818 */
4307 { "(bad)", { XX } },
4308 { "(bad)", { XX } },
4309 { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4310 { "(bad)", { XX } },
4313 /* PREFIX_VEX_3819 */
4315 { "(bad)", { XX } },
4316 { "(bad)", { XX } },
4317 { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4318 { "(bad)", { XX } },
4321 /* PREFIX_VEX_381A */
4323 { "(bad)", { XX } },
4324 { "(bad)", { XX } },
4325 { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4326 { "(bad)", { XX } },
4329 /* PREFIX_VEX_381C */
4331 { "(bad)", { XX } },
4332 { "(bad)", { XX } },
4333 { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4334 { "(bad)", { XX } },
4337 /* PREFIX_VEX_381D */
4339 { "(bad)", { XX } },
4340 { "(bad)", { XX } },
4341 { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4342 { "(bad)", { XX } },
4345 /* PREFIX_VEX_381E */
4347 { "(bad)", { XX } },
4348 { "(bad)", { XX } },
4349 { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4350 { "(bad)", { XX } },
4353 /* PREFIX_VEX_3820 */
4355 { "(bad)", { XX } },
4356 { "(bad)", { XX } },
4357 { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4358 { "(bad)", { XX } },
4361 /* PREFIX_VEX_3821 */
4363 { "(bad)", { XX } },
4364 { "(bad)", { XX } },
4365 { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4366 { "(bad)", { XX } },
4369 /* PREFIX_VEX_3822 */
4371 { "(bad)", { XX } },
4372 { "(bad)", { XX } },
4373 { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4374 { "(bad)", { XX } },
4377 /* PREFIX_VEX_3823 */
4379 { "(bad)", { XX } },
4380 { "(bad)", { XX } },
4381 { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4382 { "(bad)", { XX } },
4385 /* PREFIX_VEX_3824 */
4387 { "(bad)", { XX } },
4388 { "(bad)", { XX } },
4389 { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4390 { "(bad)", { XX } },
4393 /* PREFIX_VEX_3825 */
4395 { "(bad)", { XX } },
4396 { "(bad)", { XX } },
4397 { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4398 { "(bad)", { XX } },
4401 /* PREFIX_VEX_3828 */
4403 { "(bad)", { XX } },
4404 { "(bad)", { XX } },
4405 { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4406 { "(bad)", { XX } },
4409 /* PREFIX_VEX_3829 */
4411 { "(bad)", { XX } },
4412 { "(bad)", { XX } },
4413 { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4414 { "(bad)", { XX } },
4417 /* PREFIX_VEX_382A */
4419 { "(bad)", { XX } },
4420 { "(bad)", { XX } },
4421 { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4422 { "(bad)", { XX } },
4425 /* PREFIX_VEX_382B */
4427 { "(bad)", { XX } },
4428 { "(bad)", { XX } },
4429 { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4430 { "(bad)", { XX } },
4433 /* PREFIX_VEX_382C */
4435 { "(bad)", { XX } },
4436 { "(bad)", { XX } },
4437 { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4438 { "(bad)", { XX } },
4441 /* PREFIX_VEX_382D */
4443 { "(bad)", { XX } },
4444 { "(bad)", { XX } },
4445 { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4446 { "(bad)", { XX } },
4449 /* PREFIX_VEX_382E */
4451 { "(bad)", { XX } },
4452 { "(bad)", { XX } },
4453 { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4454 { "(bad)", { XX } },
4457 /* PREFIX_VEX_382F */
4459 { "(bad)", { XX } },
4460 { "(bad)", { XX } },
4461 { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4462 { "(bad)", { XX } },
4465 /* PREFIX_VEX_3830 */
4467 { "(bad)", { XX } },
4468 { "(bad)", { XX } },
4469 { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4470 { "(bad)", { XX } },
4473 /* PREFIX_VEX_3831 */
4475 { "(bad)", { XX } },
4476 { "(bad)", { XX } },
4477 { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4478 { "(bad)", { XX } },
4481 /* PREFIX_VEX_3832 */
4483 { "(bad)", { XX } },
4484 { "(bad)", { XX } },
4485 { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4486 { "(bad)", { XX } },
4489 /* PREFIX_VEX_3833 */
4491 { "(bad)", { XX } },
4492 { "(bad)", { XX } },
4493 { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4494 { "(bad)", { XX } },
4497 /* PREFIX_VEX_3834 */
4499 { "(bad)", { XX } },
4500 { "(bad)", { XX } },
4501 { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4502 { "(bad)", { XX } },
4505 /* PREFIX_VEX_3835 */
4507 { "(bad)", { XX } },
4508 { "(bad)", { XX } },
4509 { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4510 { "(bad)", { XX } },
4513 /* PREFIX_VEX_3837 */
4515 { "(bad)", { XX } },
4516 { "(bad)", { XX } },
4517 { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4518 { "(bad)", { XX } },
4521 /* PREFIX_VEX_3838 */
4523 { "(bad)", { XX } },
4524 { "(bad)", { XX } },
4525 { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4526 { "(bad)", { XX } },
4529 /* PREFIX_VEX_3839 */
4531 { "(bad)", { XX } },
4532 { "(bad)", { XX } },
4533 { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4534 { "(bad)", { XX } },
4537 /* PREFIX_VEX_383A */
4539 { "(bad)", { XX } },
4540 { "(bad)", { XX } },
4541 { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4542 { "(bad)", { XX } },
4545 /* PREFIX_VEX_383B */
4547 { "(bad)", { XX } },
4548 { "(bad)", { XX } },
4549 { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4550 { "(bad)", { XX } },
4553 /* PREFIX_VEX_383C */
4555 { "(bad)", { XX } },
4556 { "(bad)", { XX } },
4557 { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4558 { "(bad)", { XX } },
4561 /* PREFIX_VEX_383D */
4563 { "(bad)", { XX } },
4564 { "(bad)", { XX } },
4565 { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4566 { "(bad)", { XX } },
4569 /* PREFIX_VEX_383E */
4571 { "(bad)", { XX } },
4572 { "(bad)", { XX } },
4573 { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4574 { "(bad)", { XX } },
4577 /* PREFIX_VEX_383F */
4579 { "(bad)", { XX } },
4580 { "(bad)", { XX } },
4581 { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4582 { "(bad)", { XX } },
4585 /* PREFIX_VEX_3840 */
4587 { "(bad)", { XX } },
4588 { "(bad)", { XX } },
4589 { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4590 { "(bad)", { XX } },
4593 /* PREFIX_VEX_3841 */
4595 { "(bad)", { XX } },
4596 { "(bad)", { XX } },
4597 { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4598 { "(bad)", { XX } },
4601 /* PREFIX_VEX_3896 */
4603 { "(bad)", { XX } },
4604 { "(bad)", { XX } },
4605 { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4606 { "(bad)", { XX } },
4609 /* PREFIX_VEX_3897 */
4611 { "(bad)", { XX } },
4612 { "(bad)", { XX } },
4613 { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4614 { "(bad)", { XX } },
4617 /* PREFIX_VEX_3898 */
4619 { "(bad)", { XX } },
4620 { "(bad)", { XX } },
4621 { "vfmadd132p%XW", { XM, Vex, EXx } },
4622 { "(bad)", { XX } },
4625 /* PREFIX_VEX_3899 */
4627 { "(bad)", { XX } },
4628 { "(bad)", { XX } },
4629 { "vfmadd132s%XW", { XM, Vex, EXVexWdq } },
4630 { "(bad)", { XX } },
4633 /* PREFIX_VEX_389A */
4635 { "(bad)", { XX } },
4636 { "(bad)", { XX } },
4637 { "vfmsub132p%XW", { XM, Vex, EXx } },
4638 { "(bad)", { XX } },
4641 /* PREFIX_VEX_389B */
4643 { "(bad)", { XX } },
4644 { "(bad)", { XX } },
4645 { "vfmsub132s%XW", { XM, Vex, EXVexWdq } },
4646 { "(bad)", { XX } },
4649 /* PREFIX_VEX_389C */
4651 { "(bad)", { XX } },
4652 { "(bad)", { XX } },
4653 { "vfnmadd132p%XW", { XM, Vex, EXx } },
4654 { "(bad)", { XX } },
4657 /* PREFIX_VEX_389D */
4659 { "(bad)", { XX } },
4660 { "(bad)", { XX } },
4661 { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } },
4662 { "(bad)", { XX } },
4665 /* PREFIX_VEX_389E */
4667 { "(bad)", { XX } },
4668 { "(bad)", { XX } },
4669 { "vfnmsub132p%XW", { XM, Vex, EXx } },
4670 { "(bad)", { XX } },
4673 /* PREFIX_VEX_389F */
4675 { "(bad)", { XX } },
4676 { "(bad)", { XX } },
4677 { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } },
4678 { "(bad)", { XX } },
4681 /* PREFIX_VEX_38A6 */
4683 { "(bad)", { XX } },
4684 { "(bad)", { XX } },
4685 { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4686 { "(bad)", { XX } },
4689 /* PREFIX_VEX_38A7 */
4691 { "(bad)", { XX } },
4692 { "(bad)", { XX } },
4693 { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4694 { "(bad)", { XX } },
4697 /* PREFIX_VEX_38A8 */
4699 { "(bad)", { XX } },
4700 { "(bad)", { XX } },
4701 { "vfmadd213p%XW", { XM, Vex, EXx } },
4702 { "(bad)", { XX } },
4705 /* PREFIX_VEX_38A9 */
4707 { "(bad)", { XX } },
4708 { "(bad)", { XX } },
4709 { "vfmadd213s%XW", { XM, Vex, EXVexWdq } },
4710 { "(bad)", { XX } },
4713 /* PREFIX_VEX_38AA */
4715 { "(bad)", { XX } },
4716 { "(bad)", { XX } },
4717 { "vfmsub213p%XW", { XM, Vex, EXx } },
4718 { "(bad)", { XX } },
4721 /* PREFIX_VEX_38AB */
4723 { "(bad)", { XX } },
4724 { "(bad)", { XX } },
4725 { "vfmsub213s%XW", { XM, Vex, EXVexWdq } },
4726 { "(bad)", { XX } },
4729 /* PREFIX_VEX_38AC */
4731 { "(bad)", { XX } },
4732 { "(bad)", { XX } },
4733 { "vfnmadd213p%XW", { XM, Vex, EXx } },
4734 { "(bad)", { XX } },
4737 /* PREFIX_VEX_38AD */
4739 { "(bad)", { XX } },
4740 { "(bad)", { XX } },
4741 { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } },
4742 { "(bad)", { XX } },
4745 /* PREFIX_VEX_38AE */
4747 { "(bad)", { XX } },
4748 { "(bad)", { XX } },
4749 { "vfnmsub213p%XW", { XM, Vex, EXx } },
4750 { "(bad)", { XX } },
4753 /* PREFIX_VEX_38AF */
4755 { "(bad)", { XX } },
4756 { "(bad)", { XX } },
4757 { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } },
4758 { "(bad)", { XX } },
4761 /* PREFIX_VEX_38B6 */
4763 { "(bad)", { XX } },
4764 { "(bad)", { XX } },
4765 { "vfmaddsub231p%XW", { XM, Vex, EXx } },
4766 { "(bad)", { XX } },
4769 /* PREFIX_VEX_38B7 */
4771 { "(bad)", { XX } },
4772 { "(bad)", { XX } },
4773 { "vfmsubadd231p%XW", { XM, Vex, EXx } },
4774 { "(bad)", { XX } },
4777 /* PREFIX_VEX_38B8 */
4779 { "(bad)", { XX } },
4780 { "(bad)", { XX } },
4781 { "vfmadd231p%XW", { XM, Vex, EXx } },
4782 { "(bad)", { XX } },
4785 /* PREFIX_VEX_38B9 */
4787 { "(bad)", { XX } },
4788 { "(bad)", { XX } },
4789 { "vfmadd231s%XW", { XM, Vex, EXVexWdq } },
4790 { "(bad)", { XX } },
4793 /* PREFIX_VEX_38BA */
4795 { "(bad)", { XX } },
4796 { "(bad)", { XX } },
4797 { "vfmsub231p%XW", { XM, Vex, EXx } },
4798 { "(bad)", { XX } },
4801 /* PREFIX_VEX_38BB */
4803 { "(bad)", { XX } },
4804 { "(bad)", { XX } },
4805 { "vfmsub231s%XW", { XM, Vex, EXVexWdq } },
4806 { "(bad)", { XX } },
4809 /* PREFIX_VEX_38BC */
4811 { "(bad)", { XX } },
4812 { "(bad)", { XX } },
4813 { "vfnmadd231p%XW", { XM, Vex, EXx } },
4814 { "(bad)", { XX } },
4817 /* PREFIX_VEX_38BD */
4819 { "(bad)", { XX } },
4820 { "(bad)", { XX } },
4821 { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } },
4822 { "(bad)", { XX } },
4825 /* PREFIX_VEX_38BE */
4827 { "(bad)", { XX } },
4828 { "(bad)", { XX } },
4829 { "vfnmsub231p%XW", { XM, Vex, EXx } },
4830 { "(bad)", { XX } },
4833 /* PREFIX_VEX_38BF */
4835 { "(bad)", { XX } },
4836 { "(bad)", { XX } },
4837 { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } },
4838 { "(bad)", { XX } },
4841 /* PREFIX_VEX_38DB */
4843 { "(bad)", { XX } },
4844 { "(bad)", { XX } },
4845 { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
4846 { "(bad)", { XX } },
4849 /* PREFIX_VEX_38DC */
4851 { "(bad)", { XX } },
4852 { "(bad)", { XX } },
4853 { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
4854 { "(bad)", { XX } },
4857 /* PREFIX_VEX_38DD */
4859 { "(bad)", { XX } },
4860 { "(bad)", { XX } },
4861 { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
4862 { "(bad)", { XX } },
4865 /* PREFIX_VEX_38DE */
4867 { "(bad)", { XX } },
4868 { "(bad)", { XX } },
4869 { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
4870 { "(bad)", { XX } },
4873 /* PREFIX_VEX_38DF */
4875 { "(bad)", { XX } },
4876 { "(bad)", { XX } },
4877 { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
4878 { "(bad)", { XX } },
4881 /* PREFIX_VEX_3A04 */
4883 { "(bad)", { XX } },
4884 { "(bad)", { XX } },
4885 { "vpermilps", { XM, EXx, Ib } },
4886 { "(bad)", { XX } },
4889 /* PREFIX_VEX_3A05 */
4891 { "(bad)", { XX } },
4892 { "(bad)", { XX } },
4893 { "vpermilpd", { XM, EXx, Ib } },
4894 { "(bad)", { XX } },
4897 /* PREFIX_VEX_3A06 */
4899 { "(bad)", { XX } },
4900 { "(bad)", { XX } },
4901 { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4902 { "(bad)", { XX } },
4905 /* PREFIX_VEX_3A08 */
4907 { "(bad)", { XX } },
4908 { "(bad)", { XX } },
4909 { "vroundps", { XM, EXx, Ib } },
4910 { "(bad)", { XX } },
4913 /* PREFIX_VEX_3A09 */
4915 { "(bad)", { XX } },
4916 { "(bad)", { XX } },
4917 { "vroundpd", { XM, EXx, Ib } },
4918 { "(bad)", { XX } },
4921 /* PREFIX_VEX_3A0A */
4923 { "(bad)", { XX } },
4924 { "(bad)", { XX } },
4925 { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4926 { "(bad)", { XX } },
4929 /* PREFIX_VEX_3A0B */
4931 { "(bad)", { XX } },
4932 { "(bad)", { XX } },
4933 { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4934 { "(bad)", { XX } },
4937 /* PREFIX_VEX_3A0C */
4939 { "(bad)", { XX } },
4940 { "(bad)", { XX } },
4941 { "vblendps", { XM, Vex, EXx, Ib } },
4942 { "(bad)", { XX } },
4945 /* PREFIX_VEX_3A0D */
4947 { "(bad)", { XX } },
4948 { "(bad)", { XX } },
4949 { "vblendpd", { XM, Vex, EXx, Ib } },
4950 { "(bad)", { XX } },
4953 /* PREFIX_VEX_3A0E */
4955 { "(bad)", { XX } },
4956 { "(bad)", { XX } },
4957 { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4958 { "(bad)", { XX } },
4961 /* PREFIX_VEX_3A0F */
4963 { "(bad)", { XX } },
4964 { "(bad)", { XX } },
4965 { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
4966 { "(bad)", { XX } },
4969 /* PREFIX_VEX_3A14 */
4971 { "(bad)", { XX } },
4972 { "(bad)", { XX } },
4973 { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
4974 { "(bad)", { XX } },
4977 /* PREFIX_VEX_3A15 */
4979 { "(bad)", { XX } },
4980 { "(bad)", { XX } },
4981 { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
4982 { "(bad)", { XX } },
4985 /* PREFIX_VEX_3A16 */
4987 { "(bad)", { XX } },
4988 { "(bad)", { XX } },
4989 { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
4990 { "(bad)", { XX } },
4993 /* PREFIX_VEX_3A17 */
4995 { "(bad)", { XX } },
4996 { "(bad)", { XX } },
4997 { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
4998 { "(bad)", { XX } },
5001 /* PREFIX_VEX_3A18 */
5003 { "(bad)", { XX } },
5004 { "(bad)", { XX } },
5005 { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
5006 { "(bad)", { XX } },
5009 /* PREFIX_VEX_3A19 */
5011 { "(bad)", { XX } },
5012 { "(bad)", { XX } },
5013 { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
5014 { "(bad)", { XX } },
5017 /* PREFIX_VEX_3A20 */
5019 { "(bad)", { XX } },
5020 { "(bad)", { XX } },
5021 { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
5022 { "(bad)", { XX } },
5025 /* PREFIX_VEX_3A21 */
5027 { "(bad)", { XX } },
5028 { "(bad)", { XX } },
5029 { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
5030 { "(bad)", { XX } },
5033 /* PREFIX_VEX_3A22 */
5035 { "(bad)", { XX } },
5036 { "(bad)", { XX } },
5037 { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5038 { "(bad)", { XX } },
5041 /* PREFIX_VEX_3A40 */
5043 { "(bad)", { XX } },
5044 { "(bad)", { XX } },
5045 { "vdpps", { XM, Vex, EXx, Ib } },
5046 { "(bad)", { XX } },
5049 /* PREFIX_VEX_3A41 */
5051 { "(bad)", { XX } },
5052 { "(bad)", { XX } },
5053 { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
5054 { "(bad)", { XX } },
5057 /* PREFIX_VEX_3A42 */
5059 { "(bad)", { XX } },
5060 { "(bad)", { XX } },
5061 { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
5062 { "(bad)", { XX } },
5065 /* PREFIX_VEX_3A44 */
5067 { "(bad)", { XX } },
5068 { "(bad)", { XX } },
5069 { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },
5070 { "(bad)", { XX } },
5073 /* PREFIX_VEX_3A4A */
5075 { "(bad)", { XX } },
5076 { "(bad)", { XX } },
5077 { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
5078 { "(bad)", { XX } },
5081 /* PREFIX_VEX_3A4B */
5083 { "(bad)", { XX } },
5084 { "(bad)", { XX } },
5085 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
5086 { "(bad)", { XX } },
5089 /* PREFIX_VEX_3A4C */
5091 { "(bad)", { XX } },
5092 { "(bad)", { XX } },
5093 { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
5094 { "(bad)", { XX } },
5097 /* PREFIX_VEX_3A5C */
5099 { "(bad)", { XX } },
5100 { "(bad)", { XX } },
5101 { "vfmaddsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5102 { "(bad)", { XX } },
5105 /* PREFIX_VEX_3A5D */
5107 { "(bad)", { XX } },
5108 { "(bad)", { XX } },
5109 { "vfmaddsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5110 { "(bad)", { XX } },
5113 /* PREFIX_VEX_3A5E */
5115 { "(bad)", { XX } },
5116 { "(bad)", { XX } },
5117 { "vfmsubaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5118 { "(bad)", { XX } },
5121 /* PREFIX_VEX_3A5F */
5123 { "(bad)", { XX } },
5124 { "(bad)", { XX } },
5125 { "vfmsubaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5126 { "(bad)", { XX } },
5129 /* PREFIX_VEX_3A60 */
5131 { "(bad)", { XX } },
5132 { "(bad)", { XX } },
5133 { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
5134 { "(bad)", { XX } },
5137 /* PREFIX_VEX_3A61 */
5139 { "(bad)", { XX } },
5140 { "(bad)", { XX } },
5141 { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
5142 { "(bad)", { XX } },
5145 /* PREFIX_VEX_3A62 */
5147 { "(bad)", { XX } },
5148 { "(bad)", { XX } },
5149 { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
5150 { "(bad)", { XX } },
5153 /* PREFIX_VEX_3A63 */
5155 { "(bad)", { XX } },
5156 { "(bad)", { XX } },
5157 { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
5158 { "(bad)", { XX } },
5161 /* PREFIX_VEX_3A68 */
5163 { "(bad)", { XX } },
5164 { "(bad)", { XX } },
5165 { "vfmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5166 { "(bad)", { XX } },
5169 /* PREFIX_VEX_3A69 */
5171 { "(bad)", { XX } },
5172 { "(bad)", { XX } },
5173 { "vfmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5174 { "(bad)", { XX } },
5177 /* PREFIX_VEX_3A6A */
5179 { "(bad)", { XX } },
5180 { "(bad)", { XX } },
5181 { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
5182 { "(bad)", { XX } },
5185 /* PREFIX_VEX_3A6B */
5187 { "(bad)", { XX } },
5188 { "(bad)", { XX } },
5189 { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
5190 { "(bad)", { XX } },
5193 /* PREFIX_VEX_3A6C */
5195 { "(bad)", { XX } },
5196 { "(bad)", { XX } },
5197 { "vfmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5198 { "(bad)", { XX } },
5201 /* PREFIX_VEX_3A6D */
5203 { "(bad)", { XX } },
5204 { "(bad)", { XX } },
5205 { "vfmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5206 { "(bad)", { XX } },
5209 /* PREFIX_VEX_3A6E */
5211 { "(bad)", { XX } },
5212 { "(bad)", { XX } },
5213 { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
5214 { "(bad)", { XX } },
5217 /* PREFIX_VEX_3A6F */
5219 { "(bad)", { XX } },
5220 { "(bad)", { XX } },
5221 { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
5222 { "(bad)", { XX } },
5225 /* PREFIX_VEX_3A78 */
5227 { "(bad)", { XX } },
5228 { "(bad)", { XX } },
5229 { "vfnmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5230 { "(bad)", { XX } },
5233 /* PREFIX_VEX_3A79 */
5235 { "(bad)", { XX } },
5236 { "(bad)", { XX } },
5237 { "vfnmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5238 { "(bad)", { XX } },
5241 /* PREFIX_VEX_3A7A */
5243 { "(bad)", { XX } },
5244 { "(bad)", { XX } },
5245 { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
5246 { "(bad)", { XX } },
5249 /* PREFIX_VEX_3A7B */
5251 { "(bad)", { XX } },
5252 { "(bad)", { XX } },
5253 { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
5254 { "(bad)", { XX } },
5257 /* PREFIX_VEX_3A7C */
5259 { "(bad)", { XX } },
5260 { "(bad)", { XX } },
5261 { "vfnmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5262 { "(bad)", { XX } },
5265 /* PREFIX_VEX_3A7D */
5267 { "(bad)", { XX } },
5268 { "(bad)", { XX } },
5269 { "vfnmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5270 { "(bad)", { XX } },
5273 /* PREFIX_VEX_3A7E */
5275 { "(bad)", { XX } },
5276 { "(bad)", { XX } },
5277 { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5278 { "(bad)", { XX } },
5281 /* PREFIX_VEX_3A7F */
5283 { "(bad)", { XX } },
5284 { "(bad)", { XX } },
5285 { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5286 { "(bad)", { XX } },
5289 /* PREFIX_VEX_3ADF */
5291 { "(bad)", { XX } },
5292 { "(bad)", { XX } },
5293 { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5294 { "(bad)", { XX } },
5298 static const struct dis386 x86_64_table[][2] = {
5301 { "push{T|}", { es } },
5302 { "(bad)", { XX } },
5307 { "pop{T|}", { es } },
5308 { "(bad)", { XX } },
5313 { "push{T|}", { cs } },
5314 { "(bad)", { XX } },
5319 { "push{T|}", { ss } },
5320 { "(bad)", { XX } },
5325 { "pop{T|}", { ss } },
5326 { "(bad)", { XX } },
5331 { "push{T|}", { ds } },
5332 { "(bad)", { XX } },
5337 { "pop{T|}", { ds } },
5338 { "(bad)", { XX } },
5344 { "(bad)", { XX } },
5350 { "(bad)", { XX } },
5356 { "(bad)", { XX } },
5362 { "(bad)", { XX } },
5367 { "pusha{P|}", { XX } },
5368 { "(bad)", { XX } },
5373 { "popa{P|}", { XX } },
5374 { "(bad)", { XX } },
5379 { MOD_TABLE (MOD_62_32BIT) },
5380 { "(bad)", { XX } },
5385 { "arpl", { Ew, Gw } },
5386 { "movs{lq|xd}", { Gv, Ed } },
5391 { "ins{R|}", { Yzr, indirDX } },
5392 { "ins{G|}", { Yzr, indirDX } },
5397 { "outs{R|}", { indirDXr, Xz } },
5398 { "outs{G|}", { indirDXr, Xz } },
5403 { "Jcall{T|}", { Ap } },
5404 { "(bad)", { XX } },
5409 { MOD_TABLE (MOD_C4_32BIT) },
5410 { VEX_C4_TABLE (VEX_0F) },
5415 { MOD_TABLE (MOD_C5_32BIT) },
5416 { VEX_C5_TABLE (VEX_0F) },
5422 { "(bad)", { XX } },
5428 { "(bad)", { XX } },
5434 { "(bad)", { XX } },
5439 { "Jjmp{T|}", { Ap } },
5440 { "(bad)", { XX } },
5443 /* X86_64_0F01_REG_0 */
5445 { "sgdt{Q|IQ}", { M } },
5449 /* X86_64_0F01_REG_1 */
5451 { "sidt{Q|IQ}", { M } },
5455 /* X86_64_0F01_REG_2 */
5457 { "lgdt{Q|Q}", { M } },
5461 /* X86_64_0F01_REG_3 */
5463 { "lidt{Q|Q}", { M } },
5468 static const struct dis386 three_byte_table[][256] = {
5470 /* THREE_BYTE_0F38 */
5473 { "pshufb", { MX, EM } },
5474 { "phaddw", { MX, EM } },
5475 { "phaddd", { MX, EM } },
5476 { "phaddsw", { MX, EM } },
5477 { "pmaddubsw", { MX, EM } },
5478 { "phsubw", { MX, EM } },
5479 { "phsubd", { MX, EM } },
5480 { "phsubsw", { MX, EM } },
5482 { "psignb", { MX, EM } },
5483 { "psignw", { MX, EM } },
5484 { "psignd", { MX, EM } },
5485 { "pmulhrsw", { MX, EM } },
5486 { "(bad)", { XX } },
5487 { "(bad)", { XX } },
5488 { "(bad)", { XX } },
5489 { "(bad)", { XX } },
5491 { PREFIX_TABLE (PREFIX_0F3810) },
5492 { "(bad)", { XX } },
5493 { "(bad)", { XX } },
5494 { "(bad)", { XX } },
5495 { PREFIX_TABLE (PREFIX_0F3814) },
5496 { PREFIX_TABLE (PREFIX_0F3815) },
5497 { "(bad)", { XX } },
5498 { PREFIX_TABLE (PREFIX_0F3817) },
5500 { "(bad)", { XX } },
5501 { "(bad)", { XX } },
5502 { "(bad)", { XX } },
5503 { "(bad)", { XX } },
5504 { "pabsb", { MX, EM } },
5505 { "pabsw", { MX, EM } },
5506 { "pabsd", { MX, EM } },
5507 { "(bad)", { XX } },
5509 { PREFIX_TABLE (PREFIX_0F3820) },
5510 { PREFIX_TABLE (PREFIX_0F3821) },
5511 { PREFIX_TABLE (PREFIX_0F3822) },
5512 { PREFIX_TABLE (PREFIX_0F3823) },
5513 { PREFIX_TABLE (PREFIX_0F3824) },
5514 { PREFIX_TABLE (PREFIX_0F3825) },
5515 { "(bad)", { XX } },
5516 { "(bad)", { XX } },
5518 { PREFIX_TABLE (PREFIX_0F3828) },
5519 { PREFIX_TABLE (PREFIX_0F3829) },
5520 { PREFIX_TABLE (PREFIX_0F382A) },
5521 { PREFIX_TABLE (PREFIX_0F382B) },
5522 { "(bad)", { XX } },
5523 { "(bad)", { XX } },
5524 { "(bad)", { XX } },
5525 { "(bad)", { XX } },
5527 { PREFIX_TABLE (PREFIX_0F3830) },
5528 { PREFIX_TABLE (PREFIX_0F3831) },
5529 { PREFIX_TABLE (PREFIX_0F3832) },
5530 { PREFIX_TABLE (PREFIX_0F3833) },
5531 { PREFIX_TABLE (PREFIX_0F3834) },
5532 { PREFIX_TABLE (PREFIX_0F3835) },
5533 { "(bad)", { XX } },
5534 { PREFIX_TABLE (PREFIX_0F3837) },
5536 { PREFIX_TABLE (PREFIX_0F3838) },
5537 { PREFIX_TABLE (PREFIX_0F3839) },
5538 { PREFIX_TABLE (PREFIX_0F383A) },
5539 { PREFIX_TABLE (PREFIX_0F383B) },
5540 { PREFIX_TABLE (PREFIX_0F383C) },
5541 { PREFIX_TABLE (PREFIX_0F383D) },
5542 { PREFIX_TABLE (PREFIX_0F383E) },
5543 { PREFIX_TABLE (PREFIX_0F383F) },
5545 { PREFIX_TABLE (PREFIX_0F3840) },
5546 { PREFIX_TABLE (PREFIX_0F3841) },
5547 { "(bad)", { XX } },
5548 { "(bad)", { XX } },
5549 { "(bad)", { XX } },
5550 { "(bad)", { XX } },
5551 { "(bad)", { XX } },
5552 { "(bad)", { XX } },
5554 { "(bad)", { XX } },
5555 { "(bad)", { XX } },
5556 { "(bad)", { XX } },
5557 { "(bad)", { XX } },
5558 { "(bad)", { XX } },
5559 { "(bad)", { XX } },
5560 { "(bad)", { XX } },
5561 { "(bad)", { XX } },
5563 { "(bad)", { XX } },
5564 { "(bad)", { XX } },
5565 { "(bad)", { XX } },
5566 { "(bad)", { XX } },
5567 { "(bad)", { XX } },
5568 { "(bad)", { XX } },
5569 { "(bad)", { XX } },
5570 { "(bad)", { XX } },
5572 { "(bad)", { XX } },
5573 { "(bad)", { XX } },
5574 { "(bad)", { XX } },
5575 { "(bad)", { XX } },
5576 { "(bad)", { XX } },
5577 { "(bad)", { XX } },
5578 { "(bad)", { XX } },
5579 { "(bad)", { XX } },
5581 { "(bad)", { XX } },
5582 { "(bad)", { XX } },
5583 { "(bad)", { XX } },
5584 { "(bad)", { XX } },
5585 { "(bad)", { XX } },
5586 { "(bad)", { XX } },
5587 { "(bad)", { XX } },
5588 { "(bad)", { XX } },
5590 { "(bad)", { XX } },
5591 { "(bad)", { XX } },
5592 { "(bad)", { XX } },
5593 { "(bad)", { XX } },
5594 { "(bad)", { XX } },
5595 { "(bad)", { XX } },
5596 { "(bad)", { XX } },
5597 { "(bad)", { XX } },
5599 { "(bad)", { XX } },
5600 { "(bad)", { XX } },
5601 { "(bad)", { XX } },
5602 { "(bad)", { XX } },
5603 { "(bad)", { XX } },
5604 { "(bad)", { XX } },
5605 { "(bad)", { XX } },
5606 { "(bad)", { XX } },
5608 { "(bad)", { XX } },
5609 { "(bad)", { XX } },
5610 { "(bad)", { XX } },
5611 { "(bad)", { XX } },
5612 { "(bad)", { XX } },
5613 { "(bad)", { XX } },
5614 { "(bad)", { XX } },
5615 { "(bad)", { XX } },
5617 { PREFIX_TABLE (PREFIX_0F3880) },
5618 { PREFIX_TABLE (PREFIX_0F3881) },
5619 { "(bad)", { XX } },
5620 { "(bad)", { XX } },
5621 { "(bad)", { XX } },
5622 { "(bad)", { XX } },
5623 { "(bad)", { XX } },
5624 { "(bad)", { XX } },
5626 { "(bad)", { XX } },
5627 { "(bad)", { XX } },
5628 { "(bad)", { XX } },
5629 { "(bad)", { XX } },
5630 { "(bad)", { XX } },
5631 { "(bad)", { XX } },
5632 { "(bad)", { XX } },
5633 { "(bad)", { XX } },
5635 { "(bad)", { XX } },
5636 { "(bad)", { XX } },
5637 { "(bad)", { XX } },
5638 { "(bad)", { XX } },
5639 { "(bad)", { XX } },
5640 { "(bad)", { XX } },
5641 { "(bad)", { XX } },
5642 { "(bad)", { XX } },
5644 { "(bad)", { XX } },
5645 { "(bad)", { XX } },
5646 { "(bad)", { XX } },
5647 { "(bad)", { XX } },
5648 { "(bad)", { XX } },
5649 { "(bad)", { XX } },
5650 { "(bad)", { XX } },
5651 { "(bad)", { XX } },
5653 { "(bad)", { XX } },
5654 { "(bad)", { XX } },
5655 { "(bad)", { XX } },
5656 { "(bad)", { XX } },
5657 { "(bad)", { XX } },
5658 { "(bad)", { XX } },
5659 { "(bad)", { XX } },
5660 { "(bad)", { XX } },
5662 { "(bad)", { XX } },
5663 { "(bad)", { XX } },
5664 { "(bad)", { XX } },
5665 { "(bad)", { XX } },
5666 { "(bad)", { XX } },
5667 { "(bad)", { XX } },
5668 { "(bad)", { XX } },
5669 { "(bad)", { XX } },
5671 { "(bad)", { XX } },
5672 { "(bad)", { XX } },
5673 { "(bad)", { XX } },
5674 { "(bad)", { XX } },
5675 { "(bad)", { XX } },
5676 { "(bad)", { XX } },
5677 { "(bad)", { XX } },
5678 { "(bad)", { XX } },
5680 { "(bad)", { XX } },
5681 { "(bad)", { XX } },
5682 { "(bad)", { XX } },
5683 { "(bad)", { XX } },
5684 { "(bad)", { XX } },
5685 { "(bad)", { XX } },
5686 { "(bad)", { XX } },
5687 { "(bad)", { XX } },
5689 { "(bad)", { XX } },
5690 { "(bad)", { XX } },
5691 { "(bad)", { XX } },
5692 { "(bad)", { XX } },
5693 { "(bad)", { XX } },
5694 { "(bad)", { XX } },
5695 { "(bad)", { XX } },
5696 { "(bad)", { XX } },
5698 { "(bad)", { XX } },
5699 { "(bad)", { XX } },
5700 { "(bad)", { XX } },
5701 { "(bad)", { XX } },
5702 { "(bad)", { XX } },
5703 { "(bad)", { XX } },
5704 { "(bad)", { XX } },
5705 { "(bad)", { XX } },
5707 { "(bad)", { XX } },
5708 { "(bad)", { XX } },
5709 { "(bad)", { XX } },
5710 { "(bad)", { XX } },
5711 { "(bad)", { XX } },
5712 { "(bad)", { XX } },
5713 { "(bad)", { XX } },
5714 { "(bad)", { XX } },
5716 { "(bad)", { XX } },
5717 { "(bad)", { XX } },
5718 { "(bad)", { XX } },
5719 { PREFIX_TABLE (PREFIX_0F38DB) },
5720 { PREFIX_TABLE (PREFIX_0F38DC) },
5721 { PREFIX_TABLE (PREFIX_0F38DD) },
5722 { PREFIX_TABLE (PREFIX_0F38DE) },
5723 { PREFIX_TABLE (PREFIX_0F38DF) },
5725 { "(bad)", { XX } },
5726 { "(bad)", { XX } },
5727 { "(bad)", { XX } },
5728 { "(bad)", { XX } },
5729 { "(bad)", { XX } },
5730 { "(bad)", { XX } },
5731 { "(bad)", { XX } },
5732 { "(bad)", { XX } },
5734 { "(bad)", { XX } },
5735 { "(bad)", { XX } },
5736 { "(bad)", { XX } },
5737 { "(bad)", { XX } },
5738 { "(bad)", { XX } },
5739 { "(bad)", { XX } },
5740 { "(bad)", { XX } },
5741 { "(bad)", { XX } },
5743 { PREFIX_TABLE (PREFIX_0F38F0) },
5744 { PREFIX_TABLE (PREFIX_0F38F1) },
5745 { "(bad)", { XX } },
5746 { "(bad)", { XX } },
5747 { "(bad)", { XX } },
5748 { "(bad)", { XX } },
5749 { "(bad)", { XX } },
5750 { "(bad)", { XX } },
5752 { "(bad)", { XX } },
5753 { "(bad)", { XX } },
5754 { "(bad)", { XX } },
5755 { "(bad)", { XX } },
5756 { "(bad)", { XX } },
5757 { "(bad)", { XX } },
5758 { "(bad)", { XX } },
5759 { "(bad)", { XX } },
5761 /* THREE_BYTE_0F3A */
5764 { "(bad)", { XX } },
5765 { "(bad)", { XX } },
5766 { "(bad)", { XX } },
5767 { "(bad)", { XX } },
5768 { "(bad)", { XX } },
5769 { "(bad)", { XX } },
5770 { "(bad)", { XX } },
5771 { "(bad)", { XX } },
5773 { PREFIX_TABLE (PREFIX_0F3A08) },
5774 { PREFIX_TABLE (PREFIX_0F3A09) },
5775 { PREFIX_TABLE (PREFIX_0F3A0A) },
5776 { PREFIX_TABLE (PREFIX_0F3A0B) },
5777 { PREFIX_TABLE (PREFIX_0F3A0C) },
5778 { PREFIX_TABLE (PREFIX_0F3A0D) },
5779 { PREFIX_TABLE (PREFIX_0F3A0E) },
5780 { "palignr", { MX, EM, Ib } },
5782 { "(bad)", { XX } },
5783 { "(bad)", { XX } },
5784 { "(bad)", { XX } },
5785 { "(bad)", { XX } },
5786 { PREFIX_TABLE (PREFIX_0F3A14) },
5787 { PREFIX_TABLE (PREFIX_0F3A15) },
5788 { PREFIX_TABLE (PREFIX_0F3A16) },
5789 { PREFIX_TABLE (PREFIX_0F3A17) },
5791 { "(bad)", { XX } },
5792 { "(bad)", { XX } },
5793 { "(bad)", { XX } },
5794 { "(bad)", { XX } },
5795 { "(bad)", { XX } },
5796 { "(bad)", { XX } },
5797 { "(bad)", { XX } },
5798 { "(bad)", { XX } },
5800 { PREFIX_TABLE (PREFIX_0F3A20) },
5801 { PREFIX_TABLE (PREFIX_0F3A21) },
5802 { PREFIX_TABLE (PREFIX_0F3A22) },
5803 { "(bad)", { XX } },
5804 { "(bad)", { XX } },
5805 { "(bad)", { XX } },
5806 { "(bad)", { XX } },
5807 { "(bad)", { XX } },
5809 { "(bad)", { XX } },
5810 { "(bad)", { XX } },
5811 { "(bad)", { XX } },
5812 { "(bad)", { XX } },
5813 { "(bad)", { XX } },
5814 { "(bad)", { XX } },
5815 { "(bad)", { XX } },
5816 { "(bad)", { XX } },
5818 { "(bad)", { XX } },
5819 { "(bad)", { XX } },
5820 { "(bad)", { XX } },
5821 { "(bad)", { XX } },
5822 { "(bad)", { XX } },
5823 { "(bad)", { XX } },
5824 { "(bad)", { XX } },
5825 { "(bad)", { XX } },
5827 { "(bad)", { XX } },
5828 { "(bad)", { XX } },
5829 { "(bad)", { XX } },
5830 { "(bad)", { XX } },
5831 { "(bad)", { XX } },
5832 { "(bad)", { XX } },
5833 { "(bad)", { XX } },
5834 { "(bad)", { XX } },
5836 { PREFIX_TABLE (PREFIX_0F3A40) },
5837 { PREFIX_TABLE (PREFIX_0F3A41) },
5838 { PREFIX_TABLE (PREFIX_0F3A42) },
5839 { "(bad)", { XX } },
5840 { PREFIX_TABLE (PREFIX_0F3A44) },
5841 { "(bad)", { XX } },
5842 { "(bad)", { XX } },
5843 { "(bad)", { XX } },
5845 { "(bad)", { XX } },
5846 { "(bad)", { XX } },
5847 { "(bad)", { XX } },
5848 { "(bad)", { XX } },
5849 { "(bad)", { XX } },
5850 { "(bad)", { XX } },
5851 { "(bad)", { XX } },
5852 { "(bad)", { XX } },
5854 { "(bad)", { XX } },
5855 { "(bad)", { XX } },
5856 { "(bad)", { XX } },
5857 { "(bad)", { XX } },
5858 { "(bad)", { XX } },
5859 { "(bad)", { XX } },
5860 { "(bad)", { XX } },
5861 { "(bad)", { XX } },
5863 { "(bad)", { XX } },
5864 { "(bad)", { XX } },
5865 { "(bad)", { XX } },
5866 { "(bad)", { XX } },
5867 { "(bad)", { XX } },
5868 { "(bad)", { XX } },
5869 { "(bad)", { XX } },
5870 { "(bad)", { XX } },
5872 { PREFIX_TABLE (PREFIX_0F3A60) },
5873 { PREFIX_TABLE (PREFIX_0F3A61) },
5874 { PREFIX_TABLE (PREFIX_0F3A62) },
5875 { PREFIX_TABLE (PREFIX_0F3A63) },
5876 { "(bad)", { XX } },
5877 { "(bad)", { XX } },
5878 { "(bad)", { XX } },
5879 { "(bad)", { XX } },
5881 { "(bad)", { XX } },
5882 { "(bad)", { XX } },
5883 { "(bad)", { XX } },
5884 { "(bad)", { XX } },
5885 { "(bad)", { XX } },
5886 { "(bad)", { XX } },
5887 { "(bad)", { XX } },
5888 { "(bad)", { XX } },
5890 { "(bad)", { XX } },
5891 { "(bad)", { XX } },
5892 { "(bad)", { XX } },
5893 { "(bad)", { XX } },
5894 { "(bad)", { XX } },
5895 { "(bad)", { XX } },
5896 { "(bad)", { XX } },
5897 { "(bad)", { XX } },
5899 { "(bad)", { XX } },
5900 { "(bad)", { XX } },
5901 { "(bad)", { XX } },
5902 { "(bad)", { XX } },
5903 { "(bad)", { XX } },
5904 { "(bad)", { XX } },
5905 { "(bad)", { XX } },
5906 { "(bad)", { XX } },
5908 { "(bad)", { XX } },
5909 { "(bad)", { XX } },
5910 { "(bad)", { XX } },
5911 { "(bad)", { XX } },
5912 { "(bad)", { XX } },
5913 { "(bad)", { XX } },
5914 { "(bad)", { XX } },
5915 { "(bad)", { XX } },
5917 { "(bad)", { XX } },
5918 { "(bad)", { XX } },
5919 { "(bad)", { XX } },
5920 { "(bad)", { XX } },
5921 { "(bad)", { XX } },
5922 { "(bad)", { XX } },
5923 { "(bad)", { XX } },
5924 { "(bad)", { XX } },
5926 { "(bad)", { XX } },
5927 { "(bad)", { XX } },
5928 { "(bad)", { XX } },
5929 { "(bad)", { XX } },
5930 { "(bad)", { XX } },
5931 { "(bad)", { XX } },
5932 { "(bad)", { XX } },
5933 { "(bad)", { XX } },
5935 { "(bad)", { XX } },
5936 { "(bad)", { XX } },
5937 { "(bad)", { XX } },
5938 { "(bad)", { XX } },
5939 { "(bad)", { XX } },
5940 { "(bad)", { XX } },
5941 { "(bad)", { XX } },
5942 { "(bad)", { XX } },
5944 { "(bad)", { XX } },
5945 { "(bad)", { XX } },
5946 { "(bad)", { XX } },
5947 { "(bad)", { XX } },
5948 { "(bad)", { XX } },
5949 { "(bad)", { XX } },
5950 { "(bad)", { XX } },
5951 { "(bad)", { XX } },
5953 { "(bad)", { XX } },
5954 { "(bad)", { XX } },
5955 { "(bad)", { XX } },
5956 { "(bad)", { XX } },
5957 { "(bad)", { XX } },
5958 { "(bad)", { XX } },
5959 { "(bad)", { XX } },
5960 { "(bad)", { XX } },
5962 { "(bad)", { XX } },
5963 { "(bad)", { XX } },
5964 { "(bad)", { XX } },
5965 { "(bad)", { XX } },
5966 { "(bad)", { XX } },
5967 { "(bad)", { XX } },
5968 { "(bad)", { XX } },
5969 { "(bad)", { XX } },
5971 { "(bad)", { XX } },
5972 { "(bad)", { XX } },
5973 { "(bad)", { XX } },
5974 { "(bad)", { XX } },
5975 { "(bad)", { XX } },
5976 { "(bad)", { XX } },
5977 { "(bad)", { XX } },
5978 { "(bad)", { XX } },
5980 { "(bad)", { XX } },
5981 { "(bad)", { XX } },
5982 { "(bad)", { XX } },
5983 { "(bad)", { XX } },
5984 { "(bad)", { XX } },
5985 { "(bad)", { XX } },
5986 { "(bad)", { XX } },
5987 { "(bad)", { XX } },
5989 { "(bad)", { XX } },
5990 { "(bad)", { XX } },
5991 { "(bad)", { XX } },
5992 { "(bad)", { XX } },
5993 { "(bad)", { XX } },
5994 { "(bad)", { XX } },
5995 { "(bad)", { XX } },
5996 { "(bad)", { XX } },
5998 { "(bad)", { XX } },
5999 { "(bad)", { XX } },
6000 { "(bad)", { XX } },
6001 { "(bad)", { XX } },
6002 { "(bad)", { XX } },
6003 { "(bad)", { XX } },
6004 { "(bad)", { XX } },
6005 { "(bad)", { XX } },
6007 { "(bad)", { XX } },
6008 { "(bad)", { XX } },
6009 { "(bad)", { XX } },
6010 { "(bad)", { XX } },
6011 { "(bad)", { XX } },
6012 { "(bad)", { XX } },
6013 { "(bad)", { XX } },
6014 { PREFIX_TABLE (PREFIX_0F3ADF) },
6016 { "(bad)", { XX } },
6017 { "(bad)", { XX } },
6018 { "(bad)", { XX } },
6019 { "(bad)", { XX } },
6020 { "(bad)", { XX } },
6021 { "(bad)", { XX } },
6022 { "(bad)", { XX } },
6023 { "(bad)", { XX } },
6025 { "(bad)", { XX } },
6026 { "(bad)", { XX } },
6027 { "(bad)", { XX } },
6028 { "(bad)", { XX } },
6029 { "(bad)", { XX } },
6030 { "(bad)", { XX } },
6031 { "(bad)", { XX } },
6032 { "(bad)", { XX } },
6034 { "(bad)", { XX } },
6035 { "(bad)", { XX } },
6036 { "(bad)", { XX } },
6037 { "(bad)", { XX } },
6038 { "(bad)", { XX } },
6039 { "(bad)", { XX } },
6040 { "(bad)", { XX } },
6041 { "(bad)", { XX } },
6043 { "(bad)", { XX } },
6044 { "(bad)", { XX } },
6045 { "(bad)", { XX } },
6046 { "(bad)", { XX } },
6047 { "(bad)", { XX } },
6048 { "(bad)", { XX } },
6049 { "(bad)", { XX } },
6050 { "(bad)", { XX } },
6053 /* THREE_BYTE_0F7A */
6056 { "(bad)", { XX } },
6057 { "(bad)", { XX } },
6058 { "(bad)", { XX } },
6059 { "(bad)", { XX } },
6060 { "(bad)", { XX } },
6061 { "(bad)", { XX } },
6062 { "(bad)", { XX } },
6063 { "(bad)", { XX } },
6065 { "(bad)", { XX } },
6066 { "(bad)", { XX } },
6067 { "(bad)", { XX } },
6068 { "(bad)", { XX } },
6069 { "(bad)", { XX } },
6070 { "(bad)", { XX } },
6071 { "(bad)", { XX } },
6072 { "(bad)", { XX } },
6074 { "(bad)", { XX } },
6075 { "(bad)", { XX } },
6076 { "(bad)", { XX } },
6077 { "(bad)", { XX } },
6078 { "(bad)", { XX } },
6079 { "(bad)", { XX } },
6080 { "(bad)", { XX } },
6081 { "(bad)", { XX } },
6083 { "(bad)", { XX } },
6084 { "(bad)", { XX } },
6085 { "(bad)", { XX } },
6086 { "(bad)", { XX } },
6087 { "(bad)", { XX } },
6088 { "(bad)", { XX } },
6089 { "(bad)", { XX } },
6090 { "(bad)", { XX } },
6092 { "ptest", { XX } },
6093 { "(bad)", { XX } },
6094 { "(bad)", { XX } },
6095 { "(bad)", { XX } },
6096 { "(bad)", { XX } },
6097 { "(bad)", { XX } },
6098 { "(bad)", { XX } },
6099 { "(bad)", { XX } },
6101 { "(bad)", { XX } },
6102 { "(bad)", { XX } },
6103 { "(bad)", { XX } },
6104 { "(bad)", { XX } },
6105 { "(bad)", { XX } },
6106 { "(bad)", { XX } },
6107 { "(bad)", { XX } },
6108 { "(bad)", { XX } },
6110 { "(bad)", { XX } },
6111 { "(bad)", { XX } },
6112 { "(bad)", { XX } },
6113 { "(bad)", { XX } },
6114 { "(bad)", { XX } },
6115 { "(bad)", { XX } },
6116 { "(bad)", { XX } },
6117 { "(bad)", { XX } },
6119 { "(bad)", { XX } },
6120 { "(bad)", { XX } },
6121 { "(bad)", { XX } },
6122 { "(bad)", { XX } },
6123 { "(bad)", { XX } },
6124 { "(bad)", { XX } },
6125 { "(bad)", { XX } },
6126 { "(bad)", { XX } },
6128 { "(bad)", { XX } },
6129 { "phaddbw", { XM, EXq } },
6130 { "phaddbd", { XM, EXq } },
6131 { "phaddbq", { XM, EXq } },
6132 { "(bad)", { XX } },
6133 { "(bad)", { XX } },
6134 { "phaddwd", { XM, EXq } },
6135 { "phaddwq", { XM, EXq } },
6137 { "(bad)", { XX } },
6138 { "(bad)", { XX } },
6139 { "(bad)", { XX } },
6140 { "phadddq", { XM, EXq } },
6141 { "(bad)", { XX } },
6142 { "(bad)", { XX } },
6143 { "(bad)", { XX } },
6144 { "(bad)", { XX } },
6146 { "(bad)", { XX } },
6147 { "phaddubw", { XM, EXq } },
6148 { "phaddubd", { XM, EXq } },
6149 { "phaddubq", { XM, EXq } },
6150 { "(bad)", { XX } },
6151 { "(bad)", { XX } },
6152 { "phadduwd", { XM, EXq } },
6153 { "phadduwq", { XM, EXq } },
6155 { "(bad)", { XX } },
6156 { "(bad)", { XX } },
6157 { "(bad)", { XX } },
6158 { "phaddudq", { XM, EXq } },
6159 { "(bad)", { XX } },
6160 { "(bad)", { XX } },
6161 { "(bad)", { XX } },
6162 { "(bad)", { XX } },
6164 { "(bad)", { XX } },
6165 { "phsubbw", { XM, EXq } },
6166 { "phsubbd", { XM, EXq } },
6167 { "phsubbq", { XM, EXq } },
6168 { "(bad)", { XX } },
6169 { "(bad)", { XX } },
6170 { "(bad)", { XX } },
6171 { "(bad)", { XX } },
6173 { "(bad)", { XX } },
6174 { "(bad)", { XX } },
6175 { "(bad)", { XX } },
6176 { "(bad)", { XX } },
6177 { "(bad)", { XX } },
6178 { "(bad)", { XX } },
6179 { "(bad)", { XX } },
6180 { "(bad)", { XX } },
6182 { "(bad)", { XX } },
6183 { "(bad)", { XX } },
6184 { "(bad)", { XX } },
6185 { "(bad)", { XX } },
6186 { "(bad)", { XX } },
6187 { "(bad)", { XX } },
6188 { "(bad)", { XX } },
6189 { "(bad)", { XX } },
6191 { "(bad)", { XX } },
6192 { "(bad)", { XX } },
6193 { "(bad)", { XX } },
6194 { "(bad)", { XX } },
6195 { "(bad)", { XX } },
6196 { "(bad)", { XX } },
6197 { "(bad)", { XX } },
6198 { "(bad)", { XX } },
6200 { "(bad)", { XX } },
6201 { "(bad)", { XX } },
6202 { "(bad)", { XX } },
6203 { "(bad)", { XX } },
6204 { "(bad)", { XX } },
6205 { "(bad)", { XX } },
6206 { "(bad)", { XX } },
6207 { "(bad)", { XX } },
6209 { "(bad)", { XX } },
6210 { "(bad)", { XX } },
6211 { "(bad)", { XX } },
6212 { "(bad)", { XX } },
6213 { "(bad)", { XX } },
6214 { "(bad)", { XX } },
6215 { "(bad)", { XX } },
6216 { "(bad)", { XX } },
6218 { "(bad)", { XX } },
6219 { "(bad)", { XX } },
6220 { "(bad)", { XX } },
6221 { "(bad)", { XX } },
6222 { "(bad)", { XX } },
6223 { "(bad)", { XX } },
6224 { "(bad)", { XX } },
6225 { "(bad)", { XX } },
6227 { "(bad)", { XX } },
6228 { "(bad)", { XX } },
6229 { "(bad)", { XX } },
6230 { "(bad)", { XX } },
6231 { "(bad)", { XX } },
6232 { "(bad)", { XX } },
6233 { "(bad)", { XX } },
6234 { "(bad)", { XX } },
6236 { "(bad)", { XX } },
6237 { "(bad)", { XX } },
6238 { "(bad)", { XX } },
6239 { "(bad)", { XX } },
6240 { "(bad)", { XX } },
6241 { "(bad)", { XX } },
6242 { "(bad)", { XX } },
6243 { "(bad)", { XX } },
6245 { "(bad)", { XX } },
6246 { "(bad)", { XX } },
6247 { "(bad)", { XX } },
6248 { "(bad)", { XX } },
6249 { "(bad)", { XX } },
6250 { "(bad)", { XX } },
6251 { "(bad)", { XX } },
6252 { "(bad)", { XX } },
6254 { "(bad)", { XX } },
6255 { "(bad)", { XX } },
6256 { "(bad)", { XX } },
6257 { "(bad)", { XX } },
6258 { "(bad)", { XX } },
6259 { "(bad)", { XX } },
6260 { "(bad)", { XX } },
6261 { "(bad)", { XX } },
6263 { "(bad)", { XX } },
6264 { "(bad)", { XX } },
6265 { "(bad)", { XX } },
6266 { "(bad)", { XX } },
6267 { "(bad)", { XX } },
6268 { "(bad)", { XX } },
6269 { "(bad)", { XX } },
6270 { "(bad)", { XX } },
6272 { "(bad)", { XX } },
6273 { "(bad)", { XX } },
6274 { "(bad)", { XX } },
6275 { "(bad)", { XX } },
6276 { "(bad)", { XX } },
6277 { "(bad)", { XX } },
6278 { "(bad)", { XX } },
6279 { "(bad)", { XX } },
6281 { "(bad)", { XX } },
6282 { "(bad)", { XX } },
6283 { "(bad)", { XX } },
6284 { "(bad)", { XX } },
6285 { "(bad)", { XX } },
6286 { "(bad)", { XX } },
6287 { "(bad)", { XX } },
6288 { "(bad)", { XX } },
6290 { "(bad)", { XX } },
6291 { "(bad)", { XX } },
6292 { "(bad)", { XX } },
6293 { "(bad)", { XX } },
6294 { "(bad)", { XX } },
6295 { "(bad)", { XX } },
6296 { "(bad)", { XX } },
6297 { "(bad)", { XX } },
6299 { "(bad)", { XX } },
6300 { "(bad)", { XX } },
6301 { "(bad)", { XX } },
6302 { "(bad)", { XX } },
6303 { "(bad)", { XX } },
6304 { "(bad)", { XX } },
6305 { "(bad)", { XX } },
6306 { "(bad)", { XX } },
6308 { "(bad)", { XX } },
6309 { "(bad)", { XX } },
6310 { "(bad)", { XX } },
6311 { "(bad)", { XX } },
6312 { "(bad)", { XX } },
6313 { "(bad)", { XX } },
6314 { "(bad)", { XX } },
6315 { "(bad)", { XX } },
6317 { "(bad)", { XX } },
6318 { "(bad)", { XX } },
6319 { "(bad)", { XX } },
6320 { "(bad)", { XX } },
6321 { "(bad)", { XX } },
6322 { "(bad)", { XX } },
6323 { "(bad)", { XX } },
6324 { "(bad)", { XX } },
6326 { "(bad)", { XX } },
6327 { "(bad)", { XX } },
6328 { "(bad)", { XX } },
6329 { "(bad)", { XX } },
6330 { "(bad)", { XX } },
6331 { "(bad)", { XX } },
6332 { "(bad)", { XX } },
6333 { "(bad)", { XX } },
6335 { "(bad)", { XX } },
6336 { "(bad)", { XX } },
6337 { "(bad)", { XX } },
6338 { "(bad)", { XX } },
6339 { "(bad)", { XX } },
6340 { "(bad)", { XX } },
6341 { "(bad)", { XX } },
6342 { "(bad)", { XX } },
6347 static const struct dis386 vex_table[][256] = {
6351 { "(bad)", { XX } },
6352 { "(bad)", { XX } },
6353 { "(bad)", { XX } },
6354 { "(bad)", { XX } },
6355 { "(bad)", { XX } },
6356 { "(bad)", { XX } },
6357 { "(bad)", { XX } },
6358 { "(bad)", { XX } },
6360 { "(bad)", { XX } },
6361 { "(bad)", { XX } },
6362 { "(bad)", { XX } },
6363 { "(bad)", { XX } },
6364 { "(bad)", { XX } },
6365 { "(bad)", { XX } },
6366 { "(bad)", { XX } },
6367 { "(bad)", { XX } },
6369 { PREFIX_TABLE (PREFIX_VEX_10) },
6370 { PREFIX_TABLE (PREFIX_VEX_11) },
6371 { PREFIX_TABLE (PREFIX_VEX_12) },
6372 { MOD_TABLE (MOD_VEX_13) },
6373 { "vunpcklpX", { XM, Vex, EXx } },
6374 { "vunpckhpX", { XM, Vex, EXx } },
6375 { PREFIX_TABLE (PREFIX_VEX_16) },
6376 { MOD_TABLE (MOD_VEX_17) },
6378 { "(bad)", { XX } },
6379 { "(bad)", { XX } },
6380 { "(bad)", { XX } },
6381 { "(bad)", { XX } },
6382 { "(bad)", { XX } },
6383 { "(bad)", { XX } },
6384 { "(bad)", { XX } },
6385 { "(bad)", { XX } },
6387 { "(bad)", { XX } },
6388 { "(bad)", { XX } },
6389 { "(bad)", { XX } },
6390 { "(bad)", { XX } },
6391 { "(bad)", { XX } },
6392 { "(bad)", { XX } },
6393 { "(bad)", { XX } },
6394 { "(bad)", { XX } },
6396 { "vmovapX", { XM, EXx } },
6397 { "vmovapX", { EXxS, XM } },
6398 { PREFIX_TABLE (PREFIX_VEX_2A) },
6399 { MOD_TABLE (MOD_VEX_2B) },
6400 { PREFIX_TABLE (PREFIX_VEX_2C) },
6401 { PREFIX_TABLE (PREFIX_VEX_2D) },
6402 { PREFIX_TABLE (PREFIX_VEX_2E) },
6403 { PREFIX_TABLE (PREFIX_VEX_2F) },
6405 { "(bad)", { XX } },
6406 { "(bad)", { XX } },
6407 { "(bad)", { XX } },
6408 { "(bad)", { XX } },
6409 { "(bad)", { XX } },
6410 { "(bad)", { XX } },
6411 { "(bad)", { XX } },
6412 { "(bad)", { XX } },
6414 { "(bad)", { XX } },
6415 { "(bad)", { XX } },
6416 { "(bad)", { XX } },
6417 { "(bad)", { XX } },
6418 { "(bad)", { XX } },
6419 { "(bad)", { XX } },
6420 { "(bad)", { XX } },
6421 { "(bad)", { XX } },
6423 { "(bad)", { XX } },
6424 { "(bad)", { XX } },
6425 { "(bad)", { XX } },
6426 { "(bad)", { XX } },
6427 { "(bad)", { XX } },
6428 { "(bad)", { XX } },
6429 { "(bad)", { XX } },
6430 { "(bad)", { XX } },
6432 { "(bad)", { XX } },
6433 { "(bad)", { XX } },
6434 { "(bad)", { XX } },
6435 { "(bad)", { XX } },
6436 { "(bad)", { XX } },
6437 { "(bad)", { XX } },
6438 { "(bad)", { XX } },
6439 { "(bad)", { XX } },
6441 { MOD_TABLE (MOD_VEX_51) },
6442 { PREFIX_TABLE (PREFIX_VEX_51) },
6443 { PREFIX_TABLE (PREFIX_VEX_52) },
6444 { PREFIX_TABLE (PREFIX_VEX_53) },
6445 { "vandpX", { XM, Vex, EXx } },
6446 { "vandnpX", { XM, Vex, EXx } },
6447 { "vorpX", { XM, Vex, EXx } },
6448 { "vxorpX", { XM, Vex, EXx } },
6450 { PREFIX_TABLE (PREFIX_VEX_58) },
6451 { PREFIX_TABLE (PREFIX_VEX_59) },
6452 { PREFIX_TABLE (PREFIX_VEX_5A) },
6453 { PREFIX_TABLE (PREFIX_VEX_5B) },
6454 { PREFIX_TABLE (PREFIX_VEX_5C) },
6455 { PREFIX_TABLE (PREFIX_VEX_5D) },
6456 { PREFIX_TABLE (PREFIX_VEX_5E) },
6457 { PREFIX_TABLE (PREFIX_VEX_5F) },
6459 { PREFIX_TABLE (PREFIX_VEX_60) },
6460 { PREFIX_TABLE (PREFIX_VEX_61) },
6461 { PREFIX_TABLE (PREFIX_VEX_62) },
6462 { PREFIX_TABLE (PREFIX_VEX_63) },
6463 { PREFIX_TABLE (PREFIX_VEX_64) },
6464 { PREFIX_TABLE (PREFIX_VEX_65) },
6465 { PREFIX_TABLE (PREFIX_VEX_66) },
6466 { PREFIX_TABLE (PREFIX_VEX_67) },
6468 { PREFIX_TABLE (PREFIX_VEX_68) },
6469 { PREFIX_TABLE (PREFIX_VEX_69) },
6470 { PREFIX_TABLE (PREFIX_VEX_6A) },
6471 { PREFIX_TABLE (PREFIX_VEX_6B) },
6472 { PREFIX_TABLE (PREFIX_VEX_6C) },
6473 { PREFIX_TABLE (PREFIX_VEX_6D) },
6474 { PREFIX_TABLE (PREFIX_VEX_6E) },
6475 { PREFIX_TABLE (PREFIX_VEX_6F) },
6477 { PREFIX_TABLE (PREFIX_VEX_70) },
6478 { REG_TABLE (REG_VEX_71) },
6479 { REG_TABLE (REG_VEX_72) },
6480 { REG_TABLE (REG_VEX_73) },
6481 { PREFIX_TABLE (PREFIX_VEX_74) },
6482 { PREFIX_TABLE (PREFIX_VEX_75) },
6483 { PREFIX_TABLE (PREFIX_VEX_76) },
6484 { PREFIX_TABLE (PREFIX_VEX_77) },
6486 { "(bad)", { XX } },
6487 { "(bad)", { XX } },
6488 { "(bad)", { XX } },
6489 { "(bad)", { XX } },
6490 { PREFIX_TABLE (PREFIX_VEX_7C) },
6491 { PREFIX_TABLE (PREFIX_VEX_7D) },
6492 { PREFIX_TABLE (PREFIX_VEX_7E) },
6493 { PREFIX_TABLE (PREFIX_VEX_7F) },
6495 { "(bad)", { XX } },
6496 { "(bad)", { XX } },
6497 { "(bad)", { XX } },
6498 { "(bad)", { XX } },
6499 { "(bad)", { XX } },
6500 { "(bad)", { XX } },
6501 { "(bad)", { XX } },
6502 { "(bad)", { XX } },
6504 { "(bad)", { XX } },
6505 { "(bad)", { XX } },
6506 { "(bad)", { XX } },
6507 { "(bad)", { XX } },
6508 { "(bad)", { XX } },
6509 { "(bad)", { XX } },
6510 { "(bad)", { XX } },
6511 { "(bad)", { XX } },
6513 { "(bad)", { XX } },
6514 { "(bad)", { XX } },
6515 { "(bad)", { XX } },
6516 { "(bad)", { XX } },
6517 { "(bad)", { XX } },
6518 { "(bad)", { XX } },
6519 { "(bad)", { XX } },
6520 { "(bad)", { XX } },
6522 { "(bad)", { XX } },
6523 { "(bad)", { XX } },
6524 { "(bad)", { XX } },
6525 { "(bad)", { XX } },
6526 { "(bad)", { XX } },
6527 { "(bad)", { XX } },
6528 { "(bad)", { XX } },
6529 { "(bad)", { XX } },
6531 { "(bad)", { XX } },
6532 { "(bad)", { XX } },
6533 { "(bad)", { XX } },
6534 { "(bad)", { XX } },
6535 { "(bad)", { XX } },
6536 { "(bad)", { XX } },
6537 { "(bad)", { XX } },
6538 { "(bad)", { XX } },
6540 { "(bad)", { XX } },
6541 { "(bad)", { XX } },
6542 { "(bad)", { XX } },
6543 { "(bad)", { XX } },
6544 { "(bad)", { XX } },
6545 { "(bad)", { XX } },
6546 { REG_TABLE (REG_VEX_AE) },
6547 { "(bad)", { XX } },
6549 { "(bad)", { XX } },
6550 { "(bad)", { XX } },
6551 { "(bad)", { XX } },
6552 { "(bad)", { XX } },
6553 { "(bad)", { XX } },
6554 { "(bad)", { XX } },
6555 { "(bad)", { XX } },
6556 { "(bad)", { XX } },
6558 { "(bad)", { XX } },
6559 { "(bad)", { XX } },
6560 { "(bad)", { XX } },
6561 { "(bad)", { XX } },
6562 { "(bad)", { XX } },
6563 { "(bad)", { XX } },
6564 { "(bad)", { XX } },
6565 { "(bad)", { XX } },
6567 { "(bad)", { XX } },
6568 { "(bad)", { XX } },
6569 { PREFIX_TABLE (PREFIX_VEX_C2) },
6570 { "(bad)", { XX } },
6571 { PREFIX_TABLE (PREFIX_VEX_C4) },
6572 { PREFIX_TABLE (PREFIX_VEX_C5) },
6573 { "vshufpX", { XM, Vex, EXx, Ib } },
6574 { "(bad)", { XX } },
6576 { "(bad)", { XX } },
6577 { "(bad)", { XX } },
6578 { "(bad)", { XX } },
6579 { "(bad)", { XX } },
6580 { "(bad)", { XX } },
6581 { "(bad)", { XX } },
6582 { "(bad)", { XX } },
6583 { "(bad)", { XX } },
6585 { PREFIX_TABLE (PREFIX_VEX_D0) },
6586 { PREFIX_TABLE (PREFIX_VEX_D1) },
6587 { PREFIX_TABLE (PREFIX_VEX_D2) },
6588 { PREFIX_TABLE (PREFIX_VEX_D3) },
6589 { PREFIX_TABLE (PREFIX_VEX_D4) },
6590 { PREFIX_TABLE (PREFIX_VEX_D5) },
6591 { PREFIX_TABLE (PREFIX_VEX_D6) },
6592 { PREFIX_TABLE (PREFIX_VEX_D7) },
6594 { PREFIX_TABLE (PREFIX_VEX_D8) },
6595 { PREFIX_TABLE (PREFIX_VEX_D9) },
6596 { PREFIX_TABLE (PREFIX_VEX_DA) },
6597 { PREFIX_TABLE (PREFIX_VEX_DB) },
6598 { PREFIX_TABLE (PREFIX_VEX_DC) },
6599 { PREFIX_TABLE (PREFIX_VEX_DD) },
6600 { PREFIX_TABLE (PREFIX_VEX_DE) },
6601 { PREFIX_TABLE (PREFIX_VEX_DF) },
6603 { PREFIX_TABLE (PREFIX_VEX_E0) },
6604 { PREFIX_TABLE (PREFIX_VEX_E1) },
6605 { PREFIX_TABLE (PREFIX_VEX_E2) },
6606 { PREFIX_TABLE (PREFIX_VEX_E3) },
6607 { PREFIX_TABLE (PREFIX_VEX_E4) },
6608 { PREFIX_TABLE (PREFIX_VEX_E5) },
6609 { PREFIX_TABLE (PREFIX_VEX_E6) },
6610 { PREFIX_TABLE (PREFIX_VEX_E7) },
6612 { PREFIX_TABLE (PREFIX_VEX_E8) },
6613 { PREFIX_TABLE (PREFIX_VEX_E9) },
6614 { PREFIX_TABLE (PREFIX_VEX_EA) },
6615 { PREFIX_TABLE (PREFIX_VEX_EB) },
6616 { PREFIX_TABLE (PREFIX_VEX_EC) },
6617 { PREFIX_TABLE (PREFIX_VEX_ED) },
6618 { PREFIX_TABLE (PREFIX_VEX_EE) },
6619 { PREFIX_TABLE (PREFIX_VEX_EF) },
6621 { PREFIX_TABLE (PREFIX_VEX_F0) },
6622 { PREFIX_TABLE (PREFIX_VEX_F1) },
6623 { PREFIX_TABLE (PREFIX_VEX_F2) },
6624 { PREFIX_TABLE (PREFIX_VEX_F3) },
6625 { PREFIX_TABLE (PREFIX_VEX_F4) },
6626 { PREFIX_TABLE (PREFIX_VEX_F5) },
6627 { PREFIX_TABLE (PREFIX_VEX_F6) },
6628 { PREFIX_TABLE (PREFIX_VEX_F7) },
6630 { PREFIX_TABLE (PREFIX_VEX_F8) },
6631 { PREFIX_TABLE (PREFIX_VEX_F9) },
6632 { PREFIX_TABLE (PREFIX_VEX_FA) },
6633 { PREFIX_TABLE (PREFIX_VEX_FB) },
6634 { PREFIX_TABLE (PREFIX_VEX_FC) },
6635 { PREFIX_TABLE (PREFIX_VEX_FD) },
6636 { PREFIX_TABLE (PREFIX_VEX_FE) },
6637 { "(bad)", { XX } },
6642 { PREFIX_TABLE (PREFIX_VEX_3800) },
6643 { PREFIX_TABLE (PREFIX_VEX_3801) },
6644 { PREFIX_TABLE (PREFIX_VEX_3802) },
6645 { PREFIX_TABLE (PREFIX_VEX_3803) },
6646 { PREFIX_TABLE (PREFIX_VEX_3804) },
6647 { PREFIX_TABLE (PREFIX_VEX_3805) },
6648 { PREFIX_TABLE (PREFIX_VEX_3806) },
6649 { PREFIX_TABLE (PREFIX_VEX_3807) },
6651 { PREFIX_TABLE (PREFIX_VEX_3808) },
6652 { PREFIX_TABLE (PREFIX_VEX_3809) },
6653 { PREFIX_TABLE (PREFIX_VEX_380A) },
6654 { PREFIX_TABLE (PREFIX_VEX_380B) },
6655 { PREFIX_TABLE (PREFIX_VEX_380C) },
6656 { PREFIX_TABLE (PREFIX_VEX_380D) },
6657 { PREFIX_TABLE (PREFIX_VEX_380E) },
6658 { PREFIX_TABLE (PREFIX_VEX_380F) },
6660 { "(bad)", { XX } },
6661 { "(bad)", { XX } },
6662 { "(bad)", { XX } },
6663 { "(bad)", { XX } },
6664 { "(bad)", { XX } },
6665 { "(bad)", { XX } },
6666 { "(bad)", { XX } },
6667 { PREFIX_TABLE (PREFIX_VEX_3817) },
6669 { PREFIX_TABLE (PREFIX_VEX_3818) },
6670 { PREFIX_TABLE (PREFIX_VEX_3819) },
6671 { PREFIX_TABLE (PREFIX_VEX_381A) },
6672 { "(bad)", { XX } },
6673 { PREFIX_TABLE (PREFIX_VEX_381C) },
6674 { PREFIX_TABLE (PREFIX_VEX_381D) },
6675 { PREFIX_TABLE (PREFIX_VEX_381E) },
6676 { "(bad)", { XX } },
6678 { PREFIX_TABLE (PREFIX_VEX_3820) },
6679 { PREFIX_TABLE (PREFIX_VEX_3821) },
6680 { PREFIX_TABLE (PREFIX_VEX_3822) },
6681 { PREFIX_TABLE (PREFIX_VEX_3823) },
6682 { PREFIX_TABLE (PREFIX_VEX_3824) },
6683 { PREFIX_TABLE (PREFIX_VEX_3825) },
6684 { "(bad)", { XX } },
6685 { "(bad)", { XX } },
6687 { PREFIX_TABLE (PREFIX_VEX_3828) },
6688 { PREFIX_TABLE (PREFIX_VEX_3829) },
6689 { PREFIX_TABLE (PREFIX_VEX_382A) },
6690 { PREFIX_TABLE (PREFIX_VEX_382B) },
6691 { PREFIX_TABLE (PREFIX_VEX_382C) },
6692 { PREFIX_TABLE (PREFIX_VEX_382D) },
6693 { PREFIX_TABLE (PREFIX_VEX_382E) },
6694 { PREFIX_TABLE (PREFIX_VEX_382F) },
6696 { PREFIX_TABLE (PREFIX_VEX_3830) },
6697 { PREFIX_TABLE (PREFIX_VEX_3831) },
6698 { PREFIX_TABLE (PREFIX_VEX_3832) },
6699 { PREFIX_TABLE (PREFIX_VEX_3833) },
6700 { PREFIX_TABLE (PREFIX_VEX_3834) },
6701 { PREFIX_TABLE (PREFIX_VEX_3835) },
6702 { "(bad)", { XX } },
6703 { PREFIX_TABLE (PREFIX_VEX_3837) },
6705 { PREFIX_TABLE (PREFIX_VEX_3838) },
6706 { PREFIX_TABLE (PREFIX_VEX_3839) },
6707 { PREFIX_TABLE (PREFIX_VEX_383A) },
6708 { PREFIX_TABLE (PREFIX_VEX_383B) },
6709 { PREFIX_TABLE (PREFIX_VEX_383C) },
6710 { PREFIX_TABLE (PREFIX_VEX_383D) },
6711 { PREFIX_TABLE (PREFIX_VEX_383E) },
6712 { PREFIX_TABLE (PREFIX_VEX_383F) },
6714 { PREFIX_TABLE (PREFIX_VEX_3840) },
6715 { PREFIX_TABLE (PREFIX_VEX_3841) },
6716 { "(bad)", { XX } },
6717 { "(bad)", { XX } },
6718 { "(bad)", { XX } },
6719 { "(bad)", { XX } },
6720 { "(bad)", { XX } },
6721 { "(bad)", { XX } },
6723 { "(bad)", { XX } },
6724 { "(bad)", { XX } },
6725 { "(bad)", { XX } },
6726 { "(bad)", { XX } },
6727 { "(bad)", { XX } },
6728 { "(bad)", { XX } },
6729 { "(bad)", { XX } },
6730 { "(bad)", { XX } },
6732 { "(bad)", { XX } },
6733 { "(bad)", { XX } },
6734 { "(bad)", { XX } },
6735 { "(bad)", { XX } },
6736 { "(bad)", { XX } },
6737 { "(bad)", { XX } },
6738 { "(bad)", { XX } },
6739 { "(bad)", { XX } },
6741 { "(bad)", { XX } },
6742 { "(bad)", { XX } },
6743 { "(bad)", { XX } },
6744 { "(bad)", { XX } },
6745 { "(bad)", { XX } },
6746 { "(bad)", { XX } },
6747 { "(bad)", { XX } },
6748 { "(bad)", { XX } },
6750 { "(bad)", { XX } },
6751 { "(bad)", { XX } },
6752 { "(bad)", { XX } },
6753 { "(bad)", { XX } },
6754 { "(bad)", { XX } },
6755 { "(bad)", { XX } },
6756 { "(bad)", { XX } },
6757 { "(bad)", { XX } },
6759 { "(bad)", { XX } },
6760 { "(bad)", { XX } },
6761 { "(bad)", { XX } },
6762 { "(bad)", { XX } },
6763 { "(bad)", { XX } },
6764 { "(bad)", { XX } },
6765 { "(bad)", { XX } },
6766 { "(bad)", { XX } },
6768 { "(bad)", { XX } },
6769 { "(bad)", { XX } },
6770 { "(bad)", { XX } },
6771 { "(bad)", { XX } },
6772 { "(bad)", { XX } },
6773 { "(bad)", { XX } },
6774 { "(bad)", { XX } },
6775 { "(bad)", { XX } },
6777 { "(bad)", { XX } },
6778 { "(bad)", { XX } },
6779 { "(bad)", { XX } },
6780 { "(bad)", { XX } },
6781 { "(bad)", { XX } },
6782 { "(bad)", { XX } },
6783 { "(bad)", { XX } },
6784 { "(bad)", { XX } },
6786 { "(bad)", { XX } },
6787 { "(bad)", { XX } },
6788 { "(bad)", { XX } },
6789 { "(bad)", { XX } },
6790 { "(bad)", { XX } },
6791 { "(bad)", { XX } },
6792 { "(bad)", { XX } },
6793 { "(bad)", { XX } },
6795 { "(bad)", { XX } },
6796 { "(bad)", { XX } },
6797 { "(bad)", { XX } },
6798 { "(bad)", { XX } },
6799 { "(bad)", { XX } },
6800 { "(bad)", { XX } },
6801 { "(bad)", { XX } },
6802 { "(bad)", { XX } },
6804 { "(bad)", { XX } },
6805 { "(bad)", { XX } },
6806 { "(bad)", { XX } },
6807 { "(bad)", { XX } },
6808 { "(bad)", { XX } },
6809 { "(bad)", { XX } },
6810 { PREFIX_TABLE (PREFIX_VEX_3896) },
6811 { PREFIX_TABLE (PREFIX_VEX_3897) },
6813 { PREFIX_TABLE (PREFIX_VEX_3898) },
6814 { PREFIX_TABLE (PREFIX_VEX_3899) },
6815 { PREFIX_TABLE (PREFIX_VEX_389A) },
6816 { PREFIX_TABLE (PREFIX_VEX_389B) },
6817 { PREFIX_TABLE (PREFIX_VEX_389C) },
6818 { PREFIX_TABLE (PREFIX_VEX_389D) },
6819 { PREFIX_TABLE (PREFIX_VEX_389E) },
6820 { PREFIX_TABLE (PREFIX_VEX_389F) },
6822 { "(bad)", { XX } },
6823 { "(bad)", { XX } },
6824 { "(bad)", { XX } },
6825 { "(bad)", { XX } },
6826 { "(bad)", { XX } },
6827 { "(bad)", { XX } },
6828 { PREFIX_TABLE (PREFIX_VEX_38A6) },
6829 { PREFIX_TABLE (PREFIX_VEX_38A7) },
6831 { PREFIX_TABLE (PREFIX_VEX_38A8) },
6832 { PREFIX_TABLE (PREFIX_VEX_38A9) },
6833 { PREFIX_TABLE (PREFIX_VEX_38AA) },
6834 { PREFIX_TABLE (PREFIX_VEX_38AB) },
6835 { PREFIX_TABLE (PREFIX_VEX_38AC) },
6836 { PREFIX_TABLE (PREFIX_VEX_38AD) },
6837 { PREFIX_TABLE (PREFIX_VEX_38AE) },
6838 { PREFIX_TABLE (PREFIX_VEX_38AF) },
6840 { "(bad)", { XX } },
6841 { "(bad)", { XX } },
6842 { "(bad)", { XX } },
6843 { "(bad)", { XX } },
6844 { "(bad)", { XX } },
6845 { "(bad)", { XX } },
6846 { PREFIX_TABLE (PREFIX_VEX_38B6) },
6847 { PREFIX_TABLE (PREFIX_VEX_38B7) },
6849 { PREFIX_TABLE (PREFIX_VEX_38B8) },
6850 { PREFIX_TABLE (PREFIX_VEX_38B9) },
6851 { PREFIX_TABLE (PREFIX_VEX_38BA) },
6852 { PREFIX_TABLE (PREFIX_VEX_38BB) },
6853 { PREFIX_TABLE (PREFIX_VEX_38BC) },
6854 { PREFIX_TABLE (PREFIX_VEX_38BD) },
6855 { PREFIX_TABLE (PREFIX_VEX_38BE) },
6856 { PREFIX_TABLE (PREFIX_VEX_38BF) },
6858 { "(bad)", { XX } },
6859 { "(bad)", { XX } },
6860 { "(bad)", { XX } },
6861 { "(bad)", { XX } },
6862 { "(bad)", { XX } },
6863 { "(bad)", { XX } },
6864 { "(bad)", { XX } },
6865 { "(bad)", { XX } },
6867 { "(bad)", { XX } },
6868 { "(bad)", { XX } },
6869 { "(bad)", { XX } },
6870 { "(bad)", { XX } },
6871 { "(bad)", { XX } },
6872 { "(bad)", { XX } },
6873 { "(bad)", { XX } },
6874 { "(bad)", { XX } },
6876 { "(bad)", { XX } },
6877 { "(bad)", { XX } },
6878 { "(bad)", { XX } },
6879 { "(bad)", { XX } },
6880 { "(bad)", { XX } },
6881 { "(bad)", { XX } },
6882 { "(bad)", { XX } },
6883 { "(bad)", { XX } },
6885 { "(bad)", { XX } },
6886 { "(bad)", { XX } },
6887 { "(bad)", { XX } },
6888 { PREFIX_TABLE (PREFIX_VEX_38DB) },
6889 { PREFIX_TABLE (PREFIX_VEX_38DC) },
6890 { PREFIX_TABLE (PREFIX_VEX_38DD) },
6891 { PREFIX_TABLE (PREFIX_VEX_38DE) },
6892 { PREFIX_TABLE (PREFIX_VEX_38DF) },
6894 { "(bad)", { XX } },
6895 { "(bad)", { XX } },
6896 { "(bad)", { XX } },
6897 { "(bad)", { XX } },
6898 { "(bad)", { XX } },
6899 { "(bad)", { XX } },
6900 { "(bad)", { XX } },
6901 { "(bad)", { XX } },
6903 { "(bad)", { XX } },
6904 { "(bad)", { XX } },
6905 { "(bad)", { XX } },
6906 { "(bad)", { XX } },
6907 { "(bad)", { XX } },
6908 { "(bad)", { XX } },
6909 { "(bad)", { XX } },
6910 { "(bad)", { XX } },
6912 { "(bad)", { XX } },
6913 { "(bad)", { XX } },
6914 { "(bad)", { XX } },
6915 { "(bad)", { XX } },
6916 { "(bad)", { XX } },
6917 { "(bad)", { XX } },
6918 { "(bad)", { XX } },
6919 { "(bad)", { XX } },
6921 { "(bad)", { XX } },
6922 { "(bad)", { XX } },
6923 { "(bad)", { XX } },
6924 { "(bad)", { XX } },
6925 { "(bad)", { XX } },
6926 { "(bad)", { XX } },
6927 { "(bad)", { XX } },
6928 { "(bad)", { XX } },
6933 { "(bad)", { XX } },
6934 { "(bad)", { XX } },
6935 { "(bad)", { XX } },
6936 { "(bad)", { XX } },
6937 { PREFIX_TABLE (PREFIX_VEX_3A04) },
6938 { PREFIX_TABLE (PREFIX_VEX_3A05) },
6939 { PREFIX_TABLE (PREFIX_VEX_3A06) },
6940 { "(bad)", { XX } },
6942 { PREFIX_TABLE (PREFIX_VEX_3A08) },
6943 { PREFIX_TABLE (PREFIX_VEX_3A09) },
6944 { PREFIX_TABLE (PREFIX_VEX_3A0A) },
6945 { PREFIX_TABLE (PREFIX_VEX_3A0B) },
6946 { PREFIX_TABLE (PREFIX_VEX_3A0C) },
6947 { PREFIX_TABLE (PREFIX_VEX_3A0D) },
6948 { PREFIX_TABLE (PREFIX_VEX_3A0E) },
6949 { PREFIX_TABLE (PREFIX_VEX_3A0F) },
6951 { "(bad)", { XX } },
6952 { "(bad)", { XX } },
6953 { "(bad)", { XX } },
6954 { "(bad)", { XX } },
6955 { PREFIX_TABLE (PREFIX_VEX_3A14) },
6956 { PREFIX_TABLE (PREFIX_VEX_3A15) },
6957 { PREFIX_TABLE (PREFIX_VEX_3A16) },
6958 { PREFIX_TABLE (PREFIX_VEX_3A17) },
6960 { PREFIX_TABLE (PREFIX_VEX_3A18) },
6961 { PREFIX_TABLE (PREFIX_VEX_3A19) },
6962 { "(bad)", { XX } },
6963 { "(bad)", { XX } },
6964 { "(bad)", { XX } },
6965 { "(bad)", { XX } },
6966 { "(bad)", { XX } },
6967 { "(bad)", { XX } },
6969 { PREFIX_TABLE (PREFIX_VEX_3A20) },
6970 { PREFIX_TABLE (PREFIX_VEX_3A21) },
6971 { PREFIX_TABLE (PREFIX_VEX_3A22) },
6972 { "(bad)", { XX } },
6973 { "(bad)", { XX } },
6974 { "(bad)", { XX } },
6975 { "(bad)", { XX } },
6976 { "(bad)", { XX } },
6978 { "(bad)", { XX } },
6979 { "(bad)", { XX } },
6980 { "(bad)", { XX } },
6981 { "(bad)", { XX } },
6982 { "(bad)", { XX } },
6983 { "(bad)", { XX } },
6984 { "(bad)", { XX } },
6985 { "(bad)", { XX } },
6987 { "(bad)", { XX } },
6988 { "(bad)", { XX } },
6989 { "(bad)", { XX } },
6990 { "(bad)", { XX } },
6991 { "(bad)", { XX } },
6992 { "(bad)", { XX } },
6993 { "(bad)", { XX } },
6994 { "(bad)", { XX } },
6996 { "(bad)", { XX } },
6997 { "(bad)", { XX } },
6998 { "(bad)", { XX } },
6999 { "(bad)", { XX } },
7000 { "(bad)", { XX } },
7001 { "(bad)", { XX } },
7002 { "(bad)", { XX } },
7003 { "(bad)", { XX } },
7005 { PREFIX_TABLE (PREFIX_VEX_3A40) },
7006 { PREFIX_TABLE (PREFIX_VEX_3A41) },
7007 { PREFIX_TABLE (PREFIX_VEX_3A42) },
7008 { "(bad)", { XX } },
7009 { PREFIX_TABLE (PREFIX_VEX_3A44) },
7010 { "(bad)", { XX } },
7011 { "(bad)", { XX } },
7012 { "(bad)", { XX } },
7014 { "(bad)", { XX } },
7015 { "(bad)", { XX } },
7016 { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7017 { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7018 { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7019 { "(bad)", { XX } },
7020 { "(bad)", { XX } },
7021 { "(bad)", { XX } },
7023 { "(bad)", { XX } },
7024 { "(bad)", { XX } },
7025 { "(bad)", { XX } },
7026 { "(bad)", { XX } },
7027 { "(bad)", { XX } },
7028 { "(bad)", { XX } },
7029 { "(bad)", { XX } },
7030 { "(bad)", { XX } },
7032 { "(bad)", { XX } },
7033 { "(bad)", { XX } },
7034 { "(bad)", { XX } },
7035 { "(bad)", { XX } },
7036 { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7037 { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7038 { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7039 { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7041 { PREFIX_TABLE (PREFIX_VEX_3A60) },
7042 { PREFIX_TABLE (PREFIX_VEX_3A61) },
7043 { PREFIX_TABLE (PREFIX_VEX_3A62) },
7044 { PREFIX_TABLE (PREFIX_VEX_3A63) },
7045 { "(bad)", { XX } },
7046 { "(bad)", { XX } },
7047 { "(bad)", { XX } },
7048 { "(bad)", { XX } },
7050 { PREFIX_TABLE (PREFIX_VEX_3A68) },
7051 { PREFIX_TABLE (PREFIX_VEX_3A69) },
7052 { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7053 { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7054 { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7055 { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7056 { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7057 { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7059 { "(bad)", { XX } },
7060 { "(bad)", { XX } },
7061 { "(bad)", { XX } },
7062 { "(bad)", { XX } },
7063 { "(bad)", { XX } },
7064 { "(bad)", { XX } },
7065 { "(bad)", { XX } },
7066 { "(bad)", { XX } },
7068 { PREFIX_TABLE (PREFIX_VEX_3A78) },
7069 { PREFIX_TABLE (PREFIX_VEX_3A79) },
7070 { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7071 { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7072 { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7073 { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7074 { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7075 { PREFIX_TABLE (PREFIX_VEX_3A7F) },
7077 { "(bad)", { XX } },
7078 { "(bad)", { XX } },
7079 { "(bad)", { XX } },
7080 { "(bad)", { XX } },
7081 { "(bad)", { XX } },
7082 { "(bad)", { XX } },
7083 { "(bad)", { XX } },
7084 { "(bad)", { XX } },
7086 { "(bad)", { XX } },
7087 { "(bad)", { XX } },
7088 { "(bad)", { XX } },
7089 { "(bad)", { XX } },
7090 { "(bad)", { XX } },
7091 { "(bad)", { XX } },
7092 { "(bad)", { XX } },
7093 { "(bad)", { XX } },
7095 { "(bad)", { XX } },
7096 { "(bad)", { XX } },
7097 { "(bad)", { XX } },
7098 { "(bad)", { XX } },
7099 { "(bad)", { XX } },
7100 { "(bad)", { XX } },
7101 { "(bad)", { XX } },
7102 { "(bad)", { XX } },
7104 { "(bad)", { XX } },
7105 { "(bad)", { XX } },
7106 { "(bad)", { XX } },
7107 { "(bad)", { XX } },
7108 { "(bad)", { XX } },
7109 { "(bad)", { XX } },
7110 { "(bad)", { XX } },
7111 { "(bad)", { XX } },
7113 { "(bad)", { XX } },
7114 { "(bad)", { XX } },
7115 { "(bad)", { XX } },
7116 { "(bad)", { XX } },
7117 { "(bad)", { XX } },
7118 { "(bad)", { XX } },
7119 { "(bad)", { XX } },
7120 { "(bad)", { XX } },
7122 { "(bad)", { XX } },
7123 { "(bad)", { XX } },
7124 { "(bad)", { XX } },
7125 { "(bad)", { XX } },
7126 { "(bad)", { XX } },
7127 { "(bad)", { XX } },
7128 { "(bad)", { XX } },
7129 { "(bad)", { XX } },
7131 { "(bad)", { XX } },
7132 { "(bad)", { XX } },
7133 { "(bad)", { XX } },
7134 { "(bad)", { XX } },
7135 { "(bad)", { XX } },
7136 { "(bad)", { XX } },
7137 { "(bad)", { XX } },
7138 { "(bad)", { XX } },
7140 { "(bad)", { XX } },
7141 { "(bad)", { XX } },
7142 { "(bad)", { XX } },
7143 { "(bad)", { XX } },
7144 { "(bad)", { XX } },
7145 { "(bad)", { XX } },
7146 { "(bad)", { XX } },
7147 { "(bad)", { XX } },
7149 { "(bad)", { XX } },
7150 { "(bad)", { XX } },
7151 { "(bad)", { XX } },
7152 { "(bad)", { XX } },
7153 { "(bad)", { XX } },
7154 { "(bad)", { XX } },
7155 { "(bad)", { XX } },
7156 { "(bad)", { XX } },
7158 { "(bad)", { XX } },
7159 { "(bad)", { XX } },
7160 { "(bad)", { XX } },
7161 { "(bad)", { XX } },
7162 { "(bad)", { XX } },
7163 { "(bad)", { XX } },
7164 { "(bad)", { XX } },
7165 { "(bad)", { XX } },
7167 { "(bad)", { XX } },
7168 { "(bad)", { XX } },
7169 { "(bad)", { XX } },
7170 { "(bad)", { XX } },
7171 { "(bad)", { XX } },
7172 { "(bad)", { XX } },
7173 { "(bad)", { XX } },
7174 { "(bad)", { XX } },
7176 { "(bad)", { XX } },
7177 { "(bad)", { XX } },
7178 { "(bad)", { XX } },
7179 { "(bad)", { XX } },
7180 { "(bad)", { XX } },
7181 { "(bad)", { XX } },
7182 { "(bad)", { XX } },
7183 { PREFIX_TABLE (PREFIX_VEX_3ADF) },
7185 { "(bad)", { XX } },
7186 { "(bad)", { XX } },
7187 { "(bad)", { XX } },
7188 { "(bad)", { XX } },
7189 { "(bad)", { XX } },
7190 { "(bad)", { XX } },
7191 { "(bad)", { XX } },
7192 { "(bad)", { XX } },
7194 { "(bad)", { XX } },
7195 { "(bad)", { XX } },
7196 { "(bad)", { XX } },
7197 { "(bad)", { XX } },
7198 { "(bad)", { XX } },
7199 { "(bad)", { XX } },
7200 { "(bad)", { XX } },
7201 { "(bad)", { XX } },
7203 { "(bad)", { XX } },
7204 { "(bad)", { XX } },
7205 { "(bad)", { XX } },
7206 { "(bad)", { XX } },
7207 { "(bad)", { XX } },
7208 { "(bad)", { XX } },
7209 { "(bad)", { XX } },
7210 { "(bad)", { XX } },
7212 { "(bad)", { XX } },
7213 { "(bad)", { XX } },
7214 { "(bad)", { XX } },
7215 { "(bad)", { XX } },
7216 { "(bad)", { XX } },
7217 { "(bad)", { XX } },
7218 { "(bad)", { XX } },
7219 { "(bad)", { XX } },
7223 static const struct dis386 vex_len_table[][2] = {
7224 /* VEX_LEN_10_P_1 */
7226 { "vmovss", { XMVex, Vex128, EXd } },
7227 { "(bad)", { XX } },
7230 /* VEX_LEN_10_P_3 */
7232 { "vmovsd", { XMVex, Vex128, EXq } },
7233 { "(bad)", { XX } },
7236 /* VEX_LEN_11_P_1 */
7238 { "vmovss", { EXdVexS, Vex128, XM } },
7239 { "(bad)", { XX } },
7242 /* VEX_LEN_11_P_3 */
7244 { "vmovsd", { EXqVexS, Vex128, XM } },
7245 { "(bad)", { XX } },
7248 /* VEX_LEN_12_P_0_M_0 */
7250 { "vmovlps", { XM, Vex128, EXq } },
7251 { "(bad)", { XX } },
7254 /* VEX_LEN_12_P_0_M_1 */
7256 { "vmovhlps", { XM, Vex128, EXq } },
7257 { "(bad)", { XX } },
7260 /* VEX_LEN_12_P_2 */
7262 { "vmovlpd", { XM, Vex128, EXq } },
7263 { "(bad)", { XX } },
7266 /* VEX_LEN_13_M_0 */
7268 { "vmovlpX", { EXq, XM } },
7269 { "(bad)", { XX } },
7272 /* VEX_LEN_16_P_0_M_0 */
7274 { "vmovhps", { XM, Vex128, EXq } },
7275 { "(bad)", { XX } },
7278 /* VEX_LEN_16_P_0_M_1 */
7280 { "vmovlhps", { XM, Vex128, EXq } },
7281 { "(bad)", { XX } },
7284 /* VEX_LEN_16_P_2 */
7286 { "vmovhpd", { XM, Vex128, EXq } },
7287 { "(bad)", { XX } },
7290 /* VEX_LEN_17_M_0 */
7292 { "vmovhpX", { EXq, XM } },
7293 { "(bad)", { XX } },
7296 /* VEX_LEN_2A_P_1 */
7298 { "vcvtsi2ss%LQ", { XM, Vex128, Ev } },
7299 { "(bad)", { XX } },
7302 /* VEX_LEN_2A_P_3 */
7304 { "vcvtsi2sd%LQ", { XM, Vex128, Ev } },
7305 { "(bad)", { XX } },
7308 /* VEX_LEN_2C_P_1 */
7310 { "vcvttss2siY", { Gv, EXd } },
7311 { "(bad)", { XX } },
7314 /* VEX_LEN_2C_P_3 */
7316 { "vcvttsd2siY", { Gv, EXq } },
7317 { "(bad)", { XX } },
7320 /* VEX_LEN_2D_P_1 */
7322 { "vcvtss2siY", { Gv, EXd } },
7323 { "(bad)", { XX } },
7326 /* VEX_LEN_2D_P_3 */
7328 { "vcvtsd2siY", { Gv, EXq } },
7329 { "(bad)", { XX } },
7332 /* VEX_LEN_2E_P_0 */
7334 { "vucomiss", { XM, EXd } },
7335 { "(bad)", { XX } },
7338 /* VEX_LEN_2E_P_2 */
7340 { "vucomisd", { XM, EXq } },
7341 { "(bad)", { XX } },
7344 /* VEX_LEN_2F_P_0 */
7346 { "vcomiss", { XM, EXd } },
7347 { "(bad)", { XX } },
7350 /* VEX_LEN_2F_P_2 */
7352 { "vcomisd", { XM, EXq } },
7353 { "(bad)", { XX } },
7356 /* VEX_LEN_51_P_1 */
7358 { "vsqrtss", { XM, Vex128, EXd } },
7359 { "(bad)", { XX } },
7362 /* VEX_LEN_51_P_3 */
7364 { "vsqrtsd", { XM, Vex128, EXq } },
7365 { "(bad)", { XX } },
7368 /* VEX_LEN_52_P_1 */
7370 { "vrsqrtss", { XM, Vex128, EXd } },
7371 { "(bad)", { XX } },
7374 /* VEX_LEN_53_P_1 */
7376 { "vrcpss", { XM, Vex128, EXd } },
7377 { "(bad)", { XX } },
7380 /* VEX_LEN_58_P_1 */
7382 { "vaddss", { XM, Vex128, EXd } },
7383 { "(bad)", { XX } },
7386 /* VEX_LEN_58_P_3 */
7388 { "vaddsd", { XM, Vex128, EXq } },
7389 { "(bad)", { XX } },
7392 /* VEX_LEN_59_P_1 */
7394 { "vmulss", { XM, Vex128, EXd } },
7395 { "(bad)", { XX } },
7398 /* VEX_LEN_59_P_3 */
7400 { "vmulsd", { XM, Vex128, EXq } },
7401 { "(bad)", { XX } },
7404 /* VEX_LEN_5A_P_1 */
7406 { "vcvtss2sd", { XM, Vex128, EXd } },
7407 { "(bad)", { XX } },
7410 /* VEX_LEN_5A_P_3 */
7412 { "vcvtsd2ss", { XM, Vex128, EXq } },
7413 { "(bad)", { XX } },
7416 /* VEX_LEN_5C_P_1 */
7418 { "vsubss", { XM, Vex128, EXd } },
7419 { "(bad)", { XX } },
7422 /* VEX_LEN_5C_P_3 */
7424 { "vsubsd", { XM, Vex128, EXq } },
7425 { "(bad)", { XX } },
7428 /* VEX_LEN_5D_P_1 */
7430 { "vminss", { XM, Vex128, EXd } },
7431 { "(bad)", { XX } },
7434 /* VEX_LEN_5D_P_3 */
7436 { "vminsd", { XM, Vex128, EXq } },
7437 { "(bad)", { XX } },
7440 /* VEX_LEN_5E_P_1 */
7442 { "vdivss", { XM, Vex128, EXd } },
7443 { "(bad)", { XX } },
7446 /* VEX_LEN_5E_P_3 */
7448 { "vdivsd", { XM, Vex128, EXq } },
7449 { "(bad)", { XX } },
7452 /* VEX_LEN_5F_P_1 */
7454 { "vmaxss", { XM, Vex128, EXd } },
7455 { "(bad)", { XX } },
7458 /* VEX_LEN_5F_P_3 */
7460 { "vmaxsd", { XM, Vex128, EXq } },
7461 { "(bad)", { XX } },
7464 /* VEX_LEN_60_P_2 */
7466 { "vpunpcklbw", { XM, Vex128, EXx } },
7467 { "(bad)", { XX } },
7470 /* VEX_LEN_61_P_2 */
7472 { "vpunpcklwd", { XM, Vex128, EXx } },
7473 { "(bad)", { XX } },
7476 /* VEX_LEN_62_P_2 */
7478 { "vpunpckldq", { XM, Vex128, EXx } },
7479 { "(bad)", { XX } },
7482 /* VEX_LEN_63_P_2 */
7484 { "vpacksswb", { XM, Vex128, EXx } },
7485 { "(bad)", { XX } },
7488 /* VEX_LEN_64_P_2 */
7490 { "vpcmpgtb", { XM, Vex128, EXx } },
7491 { "(bad)", { XX } },
7494 /* VEX_LEN_65_P_2 */
7496 { "vpcmpgtw", { XM, Vex128, EXx } },
7497 { "(bad)", { XX } },
7500 /* VEX_LEN_66_P_2 */
7502 { "vpcmpgtd", { XM, Vex128, EXx } },
7503 { "(bad)", { XX } },
7506 /* VEX_LEN_67_P_2 */
7508 { "vpackuswb", { XM, Vex128, EXx } },
7509 { "(bad)", { XX } },
7512 /* VEX_LEN_68_P_2 */
7514 { "vpunpckhbw", { XM, Vex128, EXx } },
7515 { "(bad)", { XX } },
7518 /* VEX_LEN_69_P_2 */
7520 { "vpunpckhwd", { XM, Vex128, EXx } },
7521 { "(bad)", { XX } },
7524 /* VEX_LEN_6A_P_2 */
7526 { "vpunpckhdq", { XM, Vex128, EXx } },
7527 { "(bad)", { XX } },
7530 /* VEX_LEN_6B_P_2 */
7532 { "vpackssdw", { XM, Vex128, EXx } },
7533 { "(bad)", { XX } },
7536 /* VEX_LEN_6C_P_2 */
7538 { "vpunpcklqdq", { XM, Vex128, EXx } },
7539 { "(bad)", { XX } },
7542 /* VEX_LEN_6D_P_2 */
7544 { "vpunpckhqdq", { XM, Vex128, EXx } },
7545 { "(bad)", { XX } },
7548 /* VEX_LEN_6E_P_2 */
7550 { "vmovK", { XM, Edq } },
7551 { "(bad)", { XX } },
7554 /* VEX_LEN_70_P_1 */
7556 { "vpshufhw", { XM, EXx, Ib } },
7557 { "(bad)", { XX } },
7560 /* VEX_LEN_70_P_2 */
7562 { "vpshufd", { XM, EXx, Ib } },
7563 { "(bad)", { XX } },
7566 /* VEX_LEN_70_P_3 */
7568 { "vpshuflw", { XM, EXx, Ib } },
7569 { "(bad)", { XX } },
7572 /* VEX_LEN_71_R_2_P_2 */
7574 { "vpsrlw", { Vex128, XS, Ib } },
7575 { "(bad)", { XX } },
7578 /* VEX_LEN_71_R_4_P_2 */
7580 { "vpsraw", { Vex128, XS, Ib } },
7581 { "(bad)", { XX } },
7584 /* VEX_LEN_71_R_6_P_2 */
7586 { "vpsllw", { Vex128, XS, Ib } },
7587 { "(bad)", { XX } },
7590 /* VEX_LEN_72_R_2_P_2 */
7592 { "vpsrld", { Vex128, XS, Ib } },
7593 { "(bad)", { XX } },
7596 /* VEX_LEN_72_R_4_P_2 */
7598 { "vpsrad", { Vex128, XS, Ib } },
7599 { "(bad)", { XX } },
7602 /* VEX_LEN_72_R_6_P_2 */
7604 { "vpslld", { Vex128, XS, Ib } },
7605 { "(bad)", { XX } },
7608 /* VEX_LEN_73_R_2_P_2 */
7610 { "vpsrlq", { Vex128, XS, Ib } },
7611 { "(bad)", { XX } },
7614 /* VEX_LEN_73_R_3_P_2 */
7616 { "vpsrldq", { Vex128, XS, Ib } },
7617 { "(bad)", { XX } },
7620 /* VEX_LEN_73_R_6_P_2 */
7622 { "vpsllq", { Vex128, XS, Ib } },
7623 { "(bad)", { XX } },
7626 /* VEX_LEN_73_R_7_P_2 */
7628 { "vpslldq", { Vex128, XS, Ib } },
7629 { "(bad)", { XX } },
7632 /* VEX_LEN_74_P_2 */
7634 { "vpcmpeqb", { XM, Vex128, EXx } },
7635 { "(bad)", { XX } },
7638 /* VEX_LEN_75_P_2 */
7640 { "vpcmpeqw", { XM, Vex128, EXx } },
7641 { "(bad)", { XX } },
7644 /* VEX_LEN_76_P_2 */
7646 { "vpcmpeqd", { XM, Vex128, EXx } },
7647 { "(bad)", { XX } },
7650 /* VEX_LEN_7E_P_1 */
7652 { "vmovq", { XM, EXq } },
7653 { "(bad)", { XX } },
7656 /* VEX_LEN_7E_P_2 */
7658 { "vmovK", { Edq, XM } },
7659 { "(bad)", { XX } },
7662 /* VEX_LEN_AE_R_2_M_0 */
7664 { "vldmxcsr", { Md } },
7665 { "(bad)", { XX } },
7668 /* VEX_LEN_AE_R_3_M_0 */
7670 { "vstmxcsr", { Md } },
7671 { "(bad)", { XX } },
7674 /* VEX_LEN_C2_P_1 */
7676 { "vcmpss", { XM, Vex128, EXd, VCMP } },
7677 { "(bad)", { XX } },
7680 /* VEX_LEN_C2_P_3 */
7682 { "vcmpsd", { XM, Vex128, EXq, VCMP } },
7683 { "(bad)", { XX } },
7686 /* VEX_LEN_C4_P_2 */
7688 { "vpinsrw", { XM, Vex128, Edqw, Ib } },
7689 { "(bad)", { XX } },
7692 /* VEX_LEN_C5_P_2 */
7694 { "vpextrw", { Gdq, XS, Ib } },
7695 { "(bad)", { XX } },
7698 /* VEX_LEN_D1_P_2 */
7700 { "vpsrlw", { XM, Vex128, EXx } },
7701 { "(bad)", { XX } },
7704 /* VEX_LEN_D2_P_2 */
7706 { "vpsrld", { XM, Vex128, EXx } },
7707 { "(bad)", { XX } },
7710 /* VEX_LEN_D3_P_2 */
7712 { "vpsrlq", { XM, Vex128, EXx } },
7713 { "(bad)", { XX } },
7716 /* VEX_LEN_D4_P_2 */
7718 { "vpaddq", { XM, Vex128, EXx } },
7719 { "(bad)", { XX } },
7722 /* VEX_LEN_D5_P_2 */
7724 { "vpmullw", { XM, Vex128, EXx } },
7725 { "(bad)", { XX } },
7728 /* VEX_LEN_D6_P_2 */
7730 { "vmovq", { EXqS, XM } },
7731 { "(bad)", { XX } },
7734 /* VEX_LEN_D7_P_2_M_1 */
7736 { "vpmovmskb", { Gdq, XS } },
7737 { "(bad)", { XX } },
7740 /* VEX_LEN_D8_P_2 */
7742 { "vpsubusb", { XM, Vex128, EXx } },
7743 { "(bad)", { XX } },
7746 /* VEX_LEN_D9_P_2 */
7748 { "vpsubusw", { XM, Vex128, EXx } },
7749 { "(bad)", { XX } },
7752 /* VEX_LEN_DA_P_2 */
7754 { "vpminub", { XM, Vex128, EXx } },
7755 { "(bad)", { XX } },
7758 /* VEX_LEN_DB_P_2 */
7760 { "vpand", { XM, Vex128, EXx } },
7761 { "(bad)", { XX } },
7764 /* VEX_LEN_DC_P_2 */
7766 { "vpaddusb", { XM, Vex128, EXx } },
7767 { "(bad)", { XX } },
7770 /* VEX_LEN_DD_P_2 */
7772 { "vpaddusw", { XM, Vex128, EXx } },
7773 { "(bad)", { XX } },
7776 /* VEX_LEN_DE_P_2 */
7778 { "vpmaxub", { XM, Vex128, EXx } },
7779 { "(bad)", { XX } },
7782 /* VEX_LEN_DF_P_2 */
7784 { "vpandn", { XM, Vex128, EXx } },
7785 { "(bad)", { XX } },
7788 /* VEX_LEN_E0_P_2 */
7790 { "vpavgb", { XM, Vex128, EXx } },
7791 { "(bad)", { XX } },
7794 /* VEX_LEN_E1_P_2 */
7796 { "vpsraw", { XM, Vex128, EXx } },
7797 { "(bad)", { XX } },
7800 /* VEX_LEN_E2_P_2 */
7802 { "vpsrad", { XM, Vex128, EXx } },
7803 { "(bad)", { XX } },
7806 /* VEX_LEN_E3_P_2 */
7808 { "vpavgw", { XM, Vex128, EXx } },
7809 { "(bad)", { XX } },
7812 /* VEX_LEN_E4_P_2 */
7814 { "vpmulhuw", { XM, Vex128, EXx } },
7815 { "(bad)", { XX } },
7818 /* VEX_LEN_E5_P_2 */
7820 { "vpmulhw", { XM, Vex128, EXx } },
7821 { "(bad)", { XX } },
7824 /* VEX_LEN_E8_P_2 */
7826 { "vpsubsb", { XM, Vex128, EXx } },
7827 { "(bad)", { XX } },
7830 /* VEX_LEN_E9_P_2 */
7832 { "vpsubsw", { XM, Vex128, EXx } },
7833 { "(bad)", { XX } },
7836 /* VEX_LEN_EA_P_2 */
7838 { "vpminsw", { XM, Vex128, EXx } },
7839 { "(bad)", { XX } },
7842 /* VEX_LEN_EB_P_2 */
7844 { "vpor", { XM, Vex128, EXx } },
7845 { "(bad)", { XX } },
7848 /* VEX_LEN_EC_P_2 */
7850 { "vpaddsb", { XM, Vex128, EXx } },
7851 { "(bad)", { XX } },
7854 /* VEX_LEN_ED_P_2 */
7856 { "vpaddsw", { XM, Vex128, EXx } },
7857 { "(bad)", { XX } },
7860 /* VEX_LEN_EE_P_2 */
7862 { "vpmaxsw", { XM, Vex128, EXx } },
7863 { "(bad)", { XX } },
7866 /* VEX_LEN_EF_P_2 */
7868 { "vpxor", { XM, Vex128, EXx } },
7869 { "(bad)", { XX } },
7872 /* VEX_LEN_F1_P_2 */
7874 { "vpsllw", { XM, Vex128, EXx } },
7875 { "(bad)", { XX } },
7878 /* VEX_LEN_F2_P_2 */
7880 { "vpslld", { XM, Vex128, EXx } },
7881 { "(bad)", { XX } },
7884 /* VEX_LEN_F3_P_2 */
7886 { "vpsllq", { XM, Vex128, EXx } },
7887 { "(bad)", { XX } },
7890 /* VEX_LEN_F4_P_2 */
7892 { "vpmuludq", { XM, Vex128, EXx } },
7893 { "(bad)", { XX } },
7896 /* VEX_LEN_F5_P_2 */
7898 { "vpmaddwd", { XM, Vex128, EXx } },
7899 { "(bad)", { XX } },
7902 /* VEX_LEN_F6_P_2 */
7904 { "vpsadbw", { XM, Vex128, EXx } },
7905 { "(bad)", { XX } },
7908 /* VEX_LEN_F7_P_2 */
7910 { "vmaskmovdqu", { XM, XS } },
7911 { "(bad)", { XX } },
7914 /* VEX_LEN_F8_P_2 */
7916 { "vpsubb", { XM, Vex128, EXx } },
7917 { "(bad)", { XX } },
7920 /* VEX_LEN_F9_P_2 */
7922 { "vpsubw", { XM, Vex128, EXx } },
7923 { "(bad)", { XX } },
7926 /* VEX_LEN_FA_P_2 */
7928 { "vpsubd", { XM, Vex128, EXx } },
7929 { "(bad)", { XX } },
7932 /* VEX_LEN_FB_P_2 */
7934 { "vpsubq", { XM, Vex128, EXx } },
7935 { "(bad)", { XX } },
7938 /* VEX_LEN_FC_P_2 */
7940 { "vpaddb", { XM, Vex128, EXx } },
7941 { "(bad)", { XX } },
7944 /* VEX_LEN_FD_P_2 */
7946 { "vpaddw", { XM, Vex128, EXx } },
7947 { "(bad)", { XX } },
7950 /* VEX_LEN_FE_P_2 */
7952 { "vpaddd", { XM, Vex128, EXx } },
7953 { "(bad)", { XX } },
7956 /* VEX_LEN_3800_P_2 */
7958 { "vpshufb", { XM, Vex128, EXx } },
7959 { "(bad)", { XX } },
7962 /* VEX_LEN_3801_P_2 */
7964 { "vphaddw", { XM, Vex128, EXx } },
7965 { "(bad)", { XX } },
7968 /* VEX_LEN_3802_P_2 */
7970 { "vphaddd", { XM, Vex128, EXx } },
7971 { "(bad)", { XX } },
7974 /* VEX_LEN_3803_P_2 */
7976 { "vphaddsw", { XM, Vex128, EXx } },
7977 { "(bad)", { XX } },
7980 /* VEX_LEN_3804_P_2 */
7982 { "vpmaddubsw", { XM, Vex128, EXx } },
7983 { "(bad)", { XX } },
7986 /* VEX_LEN_3805_P_2 */
7988 { "vphsubw", { XM, Vex128, EXx } },
7989 { "(bad)", { XX } },
7992 /* VEX_LEN_3806_P_2 */
7994 { "vphsubd", { XM, Vex128, EXx } },
7995 { "(bad)", { XX } },
7998 /* VEX_LEN_3807_P_2 */
8000 { "vphsubsw", { XM, Vex128, EXx } },
8001 { "(bad)", { XX } },
8004 /* VEX_LEN_3808_P_2 */
8006 { "vpsignb", { XM, Vex128, EXx } },
8007 { "(bad)", { XX } },
8010 /* VEX_LEN_3809_P_2 */
8012 { "vpsignw", { XM, Vex128, EXx } },
8013 { "(bad)", { XX } },
8016 /* VEX_LEN_380A_P_2 */
8018 { "vpsignd", { XM, Vex128, EXx } },
8019 { "(bad)", { XX } },
8022 /* VEX_LEN_380B_P_2 */
8024 { "vpmulhrsw", { XM, Vex128, EXx } },
8025 { "(bad)", { XX } },
8028 /* VEX_LEN_3819_P_2_M_0 */
8030 { "(bad)", { XX } },
8031 { "vbroadcastsd", { XM, Mq } },
8034 /* VEX_LEN_381A_P_2_M_0 */
8036 { "(bad)", { XX } },
8037 { "vbroadcastf128", { XM, Mxmm } },
8040 /* VEX_LEN_381C_P_2 */
8042 { "vpabsb", { XM, EXx } },
8043 { "(bad)", { XX } },
8046 /* VEX_LEN_381D_P_2 */
8048 { "vpabsw", { XM, EXx } },
8049 { "(bad)", { XX } },
8052 /* VEX_LEN_381E_P_2 */
8054 { "vpabsd", { XM, EXx } },
8055 { "(bad)", { XX } },
8058 /* VEX_LEN_3820_P_2 */
8060 { "vpmovsxbw", { XM, EXq } },
8061 { "(bad)", { XX } },
8064 /* VEX_LEN_3821_P_2 */
8066 { "vpmovsxbd", { XM, EXd } },
8067 { "(bad)", { XX } },
8070 /* VEX_LEN_3822_P_2 */
8072 { "vpmovsxbq", { XM, EXw } },
8073 { "(bad)", { XX } },
8076 /* VEX_LEN_3823_P_2 */
8078 { "vpmovsxwd", { XM, EXq } },
8079 { "(bad)", { XX } },
8082 /* VEX_LEN_3824_P_2 */
8084 { "vpmovsxwq", { XM, EXd } },
8085 { "(bad)", { XX } },
8088 /* VEX_LEN_3825_P_2 */
8090 { "vpmovsxdq", { XM, EXq } },
8091 { "(bad)", { XX } },
8094 /* VEX_LEN_3828_P_2 */
8096 { "vpmuldq", { XM, Vex128, EXx } },
8097 { "(bad)", { XX } },
8100 /* VEX_LEN_3829_P_2 */
8102 { "vpcmpeqq", { XM, Vex128, EXx } },
8103 { "(bad)", { XX } },
8106 /* VEX_LEN_382A_P_2_M_0 */
8108 { "vmovntdqa", { XM, Mx } },
8109 { "(bad)", { XX } },
8112 /* VEX_LEN_382B_P_2 */
8114 { "vpackusdw", { XM, Vex128, EXx } },
8115 { "(bad)", { XX } },
8118 /* VEX_LEN_3830_P_2 */
8120 { "vpmovzxbw", { XM, EXq } },
8121 { "(bad)", { XX } },
8124 /* VEX_LEN_3831_P_2 */
8126 { "vpmovzxbd", { XM, EXd } },
8127 { "(bad)", { XX } },
8130 /* VEX_LEN_3832_P_2 */
8132 { "vpmovzxbq", { XM, EXw } },
8133 { "(bad)", { XX } },
8136 /* VEX_LEN_3833_P_2 */
8138 { "vpmovzxwd", { XM, EXq } },
8139 { "(bad)", { XX } },
8142 /* VEX_LEN_3834_P_2 */
8144 { "vpmovzxwq", { XM, EXd } },
8145 { "(bad)", { XX } },
8148 /* VEX_LEN_3835_P_2 */
8150 { "vpmovzxdq", { XM, EXq } },
8151 { "(bad)", { XX } },
8154 /* VEX_LEN_3837_P_2 */
8156 { "vpcmpgtq", { XM, Vex128, EXx } },
8157 { "(bad)", { XX } },
8160 /* VEX_LEN_3838_P_2 */
8162 { "vpminsb", { XM, Vex128, EXx } },
8163 { "(bad)", { XX } },
8166 /* VEX_LEN_3839_P_2 */
8168 { "vpminsd", { XM, Vex128, EXx } },
8169 { "(bad)", { XX } },
8172 /* VEX_LEN_383A_P_2 */
8174 { "vpminuw", { XM, Vex128, EXx } },
8175 { "(bad)", { XX } },
8178 /* VEX_LEN_383B_P_2 */
8180 { "vpminud", { XM, Vex128, EXx } },
8181 { "(bad)", { XX } },
8184 /* VEX_LEN_383C_P_2 */
8186 { "vpmaxsb", { XM, Vex128, EXx } },
8187 { "(bad)", { XX } },
8190 /* VEX_LEN_383D_P_2 */
8192 { "vpmaxsd", { XM, Vex128, EXx } },
8193 { "(bad)", { XX } },
8196 /* VEX_LEN_383E_P_2 */
8198 { "vpmaxuw", { XM, Vex128, EXx } },
8199 { "(bad)", { XX } },
8202 /* VEX_LEN_383F_P_2 */
8204 { "vpmaxud", { XM, Vex128, EXx } },
8205 { "(bad)", { XX } },
8208 /* VEX_LEN_3840_P_2 */
8210 { "vpmulld", { XM, Vex128, EXx } },
8211 { "(bad)", { XX } },
8214 /* VEX_LEN_3841_P_2 */
8216 { "vphminposuw", { XM, EXx } },
8217 { "(bad)", { XX } },
8220 /* VEX_LEN_38DB_P_2 */
8222 { "vaesimc", { XM, EXx } },
8223 { "(bad)", { XX } },
8226 /* VEX_LEN_38DC_P_2 */
8228 { "vaesenc", { XM, Vex128, EXx } },
8229 { "(bad)", { XX } },
8232 /* VEX_LEN_38DD_P_2 */
8234 { "vaesenclast", { XM, Vex128, EXx } },
8235 { "(bad)", { XX } },
8238 /* VEX_LEN_38DE_P_2 */
8240 { "vaesdec", { XM, Vex128, EXx } },
8241 { "(bad)", { XX } },
8244 /* VEX_LEN_38DF_P_2 */
8246 { "vaesdeclast", { XM, Vex128, EXx } },
8247 { "(bad)", { XX } },
8250 /* VEX_LEN_3A06_P_2 */
8252 { "(bad)", { XX } },
8253 { "vperm2f128", { XM, Vex256, EXx, Ib } },
8256 /* VEX_LEN_3A0A_P_2 */
8258 { "vroundss", { XM, Vex128, EXd, Ib } },
8259 { "(bad)", { XX } },
8262 /* VEX_LEN_3A0B_P_2 */
8264 { "vroundsd", { XM, Vex128, EXq, Ib } },
8265 { "(bad)", { XX } },
8268 /* VEX_LEN_3A0E_P_2 */
8270 { "vpblendw", { XM, Vex128, EXx, Ib } },
8271 { "(bad)", { XX } },
8274 /* VEX_LEN_3A0F_P_2 */
8276 { "vpalignr", { XM, Vex128, EXx, Ib } },
8277 { "(bad)", { XX } },
8280 /* VEX_LEN_3A14_P_2 */
8282 { "vpextrb", { Edqb, XM, Ib } },
8283 { "(bad)", { XX } },
8286 /* VEX_LEN_3A15_P_2 */
8288 { "vpextrw", { Edqw, XM, Ib } },
8289 { "(bad)", { XX } },
8292 /* VEX_LEN_3A16_P_2 */
8294 { "vpextrK", { Edq, XM, Ib } },
8295 { "(bad)", { XX } },
8298 /* VEX_LEN_3A17_P_2 */
8300 { "vextractps", { Edqd, XM, Ib } },
8301 { "(bad)", { XX } },
8304 /* VEX_LEN_3A18_P_2 */
8306 { "(bad)", { XX } },
8307 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },
8310 /* VEX_LEN_3A19_P_2 */
8312 { "(bad)", { XX } },
8313 { "vextractf128", { EXxmm, XM, Ib } },
8316 /* VEX_LEN_3A20_P_2 */
8318 { "vpinsrb", { XM, Vex128, Edqb, Ib } },
8319 { "(bad)", { XX } },
8322 /* VEX_LEN_3A21_P_2 */
8324 { "vinsertps", { XM, Vex128, EXd, Ib } },
8325 { "(bad)", { XX } },
8328 /* VEX_LEN_3A22_P_2 */
8330 { "vpinsrK", { XM, Vex128, Edq, Ib } },
8331 { "(bad)", { XX } },
8334 /* VEX_LEN_3A41_P_2 */
8336 { "vdppd", { XM, Vex128, EXx, Ib } },
8337 { "(bad)", { XX } },
8340 /* VEX_LEN_3A42_P_2 */
8342 { "vmpsadbw", { XM, Vex128, EXx, Ib } },
8343 { "(bad)", { XX } },
8346 /* VEX_LEN_3A44_P_2 */
8348 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } },
8349 { "(bad)", { XX } },
8352 /* VEX_LEN_3A4C_P_2 */
8354 { "vpblendvb", { XM, Vex128, EXx, XMVexI4 } },
8355 { "(bad)", { XX } },
8358 /* VEX_LEN_3A60_P_2 */
8360 { "vpcmpestrm", { XM, EXx, Ib } },
8361 { "(bad)", { XX } },
8364 /* VEX_LEN_3A61_P_2 */
8366 { "vpcmpestri", { XM, EXx, Ib } },
8367 { "(bad)", { XX } },
8370 /* VEX_LEN_3A62_P_2 */
8372 { "vpcmpistrm", { XM, EXx, Ib } },
8373 { "(bad)", { XX } },
8376 /* VEX_LEN_3A63_P_2 */
8378 { "vpcmpistri", { XM, EXx, Ib } },
8379 { "(bad)", { XX } },
8382 /* VEX_LEN_3A6A_P_2 */
8384 { "vfmaddss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
8385 { "(bad)", { XX } },
8388 /* VEX_LEN_3A6B_P_2 */
8390 { "vfmaddsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
8391 { "(bad)", { XX } },
8394 /* VEX_LEN_3A6E_P_2 */
8396 { "vfmsubss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
8397 { "(bad)", { XX } },
8400 /* VEX_LEN_3A6F_P_2 */
8402 { "vfmsubsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
8403 { "(bad)", { XX } },
8406 /* VEX_LEN_3A7A_P_2 */
8408 { "vfnmaddss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
8409 { "(bad)", { XX } },
8412 /* VEX_LEN_3A7B_P_2 */
8414 { "vfnmaddsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
8415 { "(bad)", { XX } },
8418 /* VEX_LEN_3A7E_P_2 */
8420 { "vfnmsubss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
8421 { "(bad)", { XX } },
8424 /* VEX_LEN_3A7F_P_2 */
8426 { "vfnmsubsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
8427 { "(bad)", { XX } },
8430 /* VEX_LEN_3ADF_P_2 */
8432 { "vaeskeygenassist", { XM, EXx, Ib } },
8433 { "(bad)", { XX } },
8437 static const struct dis386 mod_table[][2] = {
8440 { "leaS", { Gv, M } },
8441 { "(bad)", { XX } },
8444 /* MOD_0F01_REG_0 */
8445 { X86_64_TABLE (X86_64_0F01_REG_0) },
8446 { RM_TABLE (RM_0F01_REG_0) },
8449 /* MOD_0F01_REG_1 */
8450 { X86_64_TABLE (X86_64_0F01_REG_1) },
8451 { RM_TABLE (RM_0F01_REG_1) },
8454 /* MOD_0F01_REG_2 */
8455 { X86_64_TABLE (X86_64_0F01_REG_2) },
8456 { RM_TABLE (RM_0F01_REG_2) },
8459 /* MOD_0F01_REG_3 */
8460 { X86_64_TABLE (X86_64_0F01_REG_3) },
8461 { RM_TABLE (RM_0F01_REG_3) },
8464 /* MOD_0F01_REG_7 */
8465 { "invlpg", { Mb } },
8466 { RM_TABLE (RM_0F01_REG_7) },
8469 /* MOD_0F12_PREFIX_0 */
8470 { "movlps", { XM, EXq } },
8471 { "movhlps", { XM, EXq } },
8475 { "movlpX", { EXq, XM } },
8476 { "(bad)", { XX } },
8479 /* MOD_0F16_PREFIX_0 */
8480 { "movhps", { XM, EXq } },
8481 { "movlhps", { XM, EXq } },
8485 { "movhpX", { EXq, XM } },
8486 { "(bad)", { XX } },
8489 /* MOD_0F18_REG_0 */
8490 { "prefetchnta", { Mb } },
8491 { "(bad)", { XX } },
8494 /* MOD_0F18_REG_1 */
8495 { "prefetcht0", { Mb } },
8496 { "(bad)", { XX } },
8499 /* MOD_0F18_REG_2 */
8500 { "prefetcht1", { Mb } },
8501 { "(bad)", { XX } },
8504 /* MOD_0F18_REG_3 */
8505 { "prefetcht2", { Mb } },
8506 { "(bad)", { XX } },
8510 { "(bad)", { XX } },
8511 { "movZ", { Rm, Cm } },
8515 { "(bad)", { XX } },
8516 { "movZ", { Rm, Dm } },
8520 { "(bad)", { XX } },
8521 { "movZ", { Cm, Rm } },
8525 { "(bad)", { XX } },
8526 { "movZ", { Dm, Rm } },
8530 { "(bad)", { XX } },
8531 { "movL", { Rd, Td } },
8535 { "(bad)", { XX } },
8536 { "movL", { Td, Rd } },
8539 /* MOD_0F2B_PREFIX_0 */
8540 {"movntps", { Mx, XM } },
8541 { "(bad)", { XX } },
8544 /* MOD_0F2B_PREFIX_1 */
8545 {"movntss", { Md, XM } },
8546 { "(bad)", { XX } },
8549 /* MOD_0F2B_PREFIX_2 */
8550 {"movntpd", { Mx, XM } },
8551 { "(bad)", { XX } },
8554 /* MOD_0F2B_PREFIX_3 */
8555 {"movntsd", { Mq, XM } },
8556 { "(bad)", { XX } },
8560 { "(bad)", { XX } },
8561 { "movmskpX", { Gdq, XS } },
8564 /* MOD_0F71_REG_2 */
8565 { "(bad)", { XX } },
8566 { "psrlw", { MS, Ib } },
8569 /* MOD_0F71_REG_4 */
8570 { "(bad)", { XX } },
8571 { "psraw", { MS, Ib } },
8574 /* MOD_0F71_REG_6 */
8575 { "(bad)", { XX } },
8576 { "psllw", { MS, Ib } },
8579 /* MOD_0F72_REG_2 */
8580 { "(bad)", { XX } },
8581 { "psrld", { MS, Ib } },
8584 /* MOD_0F72_REG_4 */
8585 { "(bad)", { XX } },
8586 { "psrad", { MS, Ib } },
8589 /* MOD_0F72_REG_6 */
8590 { "(bad)", { XX } },
8591 { "pslld", { MS, Ib } },
8594 /* MOD_0F73_REG_2 */
8595 { "(bad)", { XX } },
8596 { "psrlq", { MS, Ib } },
8599 /* MOD_0F73_REG_3 */
8600 { "(bad)", { XX } },
8601 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
8604 /* MOD_0F73_REG_6 */
8605 { "(bad)", { XX } },
8606 { "psllq", { MS, Ib } },
8609 /* MOD_0F73_REG_7 */
8610 { "(bad)", { XX } },
8611 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
8614 /* MOD_0FAE_REG_0 */
8615 { "fxsave", { M } },
8616 { "(bad)", { XX } },
8619 /* MOD_0FAE_REG_1 */
8620 { "fxrstor", { M } },
8621 { "(bad)", { XX } },
8624 /* MOD_0FAE_REG_2 */
8625 { "ldmxcsr", { Md } },
8626 { "(bad)", { XX } },
8629 /* MOD_0FAE_REG_3 */
8630 { "stmxcsr", { Md } },
8631 { "(bad)", { XX } },
8634 /* MOD_0FAE_REG_4 */
8636 { "(bad)", { XX } },
8639 /* MOD_0FAE_REG_5 */
8640 { "xrstor", { M } },
8641 { RM_TABLE (RM_0FAE_REG_5) },
8644 /* MOD_0FAE_REG_6 */
8645 { "xsaveopt", { M } },
8646 { RM_TABLE (RM_0FAE_REG_6) },
8649 /* MOD_0FAE_REG_7 */
8650 { "clflush", { Mb } },
8651 { RM_TABLE (RM_0FAE_REG_7) },
8655 { "lssS", { Gv, Mp } },
8656 { "(bad)", { XX } },
8660 { "lfsS", { Gv, Mp } },
8661 { "(bad)", { XX } },
8665 { "lgsS", { Gv, Mp } },
8666 { "(bad)", { XX } },
8669 /* MOD_0FC7_REG_6 */
8670 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
8671 { "(bad)", { XX } },
8674 /* MOD_0FC7_REG_7 */
8675 { "vmptrst", { Mq } },
8676 { "(bad)", { XX } },
8680 { "(bad)", { XX } },
8681 { "pmovmskb", { Gdq, MS } },
8684 /* MOD_0FE7_PREFIX_2 */
8685 { "movntdq", { Mx, XM } },
8686 { "(bad)", { XX } },
8689 /* MOD_0FF0_PREFIX_3 */
8690 { "lddqu", { XM, M } },
8691 { "(bad)", { XX } },
8694 /* MOD_0F382A_PREFIX_2 */
8695 { "movntdqa", { XM, Mx } },
8696 { "(bad)", { XX } },
8700 { "bound{S|}", { Gv, Ma } },
8701 { "(bad)", { XX } },
8705 { "lesS", { Gv, Mp } },
8706 { VEX_C4_TABLE (VEX_0F) },
8710 { "ldsS", { Gv, Mp } },
8711 { VEX_C5_TABLE (VEX_0F) },
8714 /* MOD_VEX_12_PREFIX_0 */
8715 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
8716 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
8720 { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
8721 { "(bad)", { XX } },
8724 /* MOD_VEX_16_PREFIX_0 */
8725 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
8726 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
8730 { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
8731 { "(bad)", { XX } },
8735 { "vmovntpX", { Mx, XM } },
8736 { "(bad)", { XX } },
8740 { "(bad)", { XX } },
8741 { "vmovmskpX", { Gdq, XS } },
8744 /* MOD_VEX_71_REG_2 */
8745 { "(bad)", { XX } },
8746 { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
8749 /* MOD_VEX_71_REG_4 */
8750 { "(bad)", { XX } },
8751 { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
8754 /* MOD_VEX_71_REG_6 */
8755 { "(bad)", { XX } },
8756 { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
8759 /* MOD_VEX_72_REG_2 */
8760 { "(bad)", { XX } },
8761 { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
8764 /* MOD_VEX_72_REG_4 */
8765 { "(bad)", { XX } },
8766 { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
8769 /* MOD_VEX_72_REG_6 */
8770 { "(bad)", { XX } },
8771 { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
8774 /* MOD_VEX_73_REG_2 */
8775 { "(bad)", { XX } },
8776 { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
8779 /* MOD_VEX_73_REG_3 */
8780 { "(bad)", { XX } },
8781 { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
8784 /* MOD_VEX_73_REG_6 */
8785 { "(bad)", { XX } },
8786 { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
8789 /* MOD_VEX_73_REG_7 */
8790 { "(bad)", { XX } },
8791 { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
8794 /* MOD_VEX_AE_REG_2 */
8795 { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
8796 { "(bad)", { XX } },
8799 /* MOD_VEX_AE_REG_3 */
8800 { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
8801 { "(bad)", { XX } },
8804 /* MOD_VEX_D7_PREFIX_2 */
8805 { "(bad)", { XX } },
8806 { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
8809 /* MOD_VEX_E7_PREFIX_2 */
8810 { "vmovntdq", { Mx, XM } },
8811 { "(bad)", { XX } },
8814 /* MOD_VEX_F0_PREFIX_3 */
8815 { "vlddqu", { XM, M } },
8816 { "(bad)", { XX } },
8819 /* MOD_VEX_3818_PREFIX_2 */
8820 { "vbroadcastss", { XM, Md } },
8821 { "(bad)", { XX } },
8824 /* MOD_VEX_3819_PREFIX_2 */
8825 { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
8826 { "(bad)", { XX } },
8829 /* MOD_VEX_381A_PREFIX_2 */
8830 { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
8831 { "(bad)", { XX } },
8834 /* MOD_VEX_382A_PREFIX_2 */
8835 { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
8836 { "(bad)", { XX } },
8839 /* MOD_VEX_382C_PREFIX_2 */
8840 { "vmaskmovps", { XM, Vex, Mx } },
8841 { "(bad)", { XX } },
8844 /* MOD_VEX_382D_PREFIX_2 */
8845 { "vmaskmovpd", { XM, Vex, Mx } },
8846 { "(bad)", { XX } },
8849 /* MOD_VEX_382E_PREFIX_2 */
8850 { "vmaskmovps", { Mx, Vex, XM } },
8851 { "(bad)", { XX } },
8854 /* MOD_VEX_382F_PREFIX_2 */
8855 { "vmaskmovpd", { Mx, Vex, XM } },
8856 { "(bad)", { XX } },
8860 static const struct dis386 rm_table[][8] = {
8863 { "(bad)", { XX } },
8864 { "vmcall", { Skip_MODRM } },
8865 { "vmlaunch", { Skip_MODRM } },
8866 { "vmresume", { Skip_MODRM } },
8867 { "vmxoff", { Skip_MODRM } },
8868 { "(bad)", { XX } },
8869 { "(bad)", { XX } },
8870 { "(bad)", { XX } },
8874 { "monitor", { { OP_Monitor, 0 } } },
8875 { "mwait", { { OP_Mwait, 0 } } },
8876 { "(bad)", { XX } },
8877 { "(bad)", { XX } },
8878 { "(bad)", { XX } },
8879 { "(bad)", { XX } },
8880 { "(bad)", { XX } },
8881 { "(bad)", { XX } },
8885 { "xgetbv", { Skip_MODRM } },
8886 { "xsetbv", { Skip_MODRM } },
8887 { "(bad)", { XX } },
8888 { "(bad)", { XX } },
8889 { "(bad)", { XX } },
8890 { "(bad)", { XX } },
8891 { "(bad)", { XX } },
8892 { "(bad)", { XX } },
8896 { "vmrun", { Skip_MODRM } },
8897 { "vmmcall", { Skip_MODRM } },
8898 { "vmload", { Skip_MODRM } },
8899 { "vmsave", { Skip_MODRM } },
8900 { "stgi", { Skip_MODRM } },
8901 { "clgi", { Skip_MODRM } },
8902 { "skinit", { Skip_MODRM } },
8903 { "invlpga", { Skip_MODRM } },
8907 { "swapgs", { Skip_MODRM } },
8908 { "rdtscp", { Skip_MODRM } },
8909 { "(bad)", { XX } },
8910 { "(bad)", { XX } },
8911 { "(bad)", { XX } },
8912 { "(bad)", { XX } },
8913 { "(bad)", { XX } },
8914 { "(bad)", { XX } },
8918 { "lfence", { Skip_MODRM } },
8919 { "(bad)", { XX } },
8920 { "(bad)", { XX } },
8921 { "(bad)", { XX } },
8922 { "(bad)", { XX } },
8923 { "(bad)", { XX } },
8924 { "(bad)", { XX } },
8925 { "(bad)", { XX } },
8929 { "mfence", { Skip_MODRM } },
8930 { "(bad)", { XX } },
8931 { "(bad)", { XX } },
8932 { "(bad)", { XX } },
8933 { "(bad)", { XX } },
8934 { "(bad)", { XX } },
8935 { "(bad)", { XX } },
8936 { "(bad)", { XX } },
8940 { "sfence", { Skip_MODRM } },
8941 { "(bad)", { XX } },
8942 { "(bad)", { XX } },
8943 { "(bad)", { XX } },
8944 { "(bad)", { XX } },
8945 { "(bad)", { XX } },
8946 { "(bad)", { XX } },
8947 { "(bad)", { XX } },
8951 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8965 FETCH_DATA (the_info, codep + 1);
8969 /* REX prefixes family. */
8986 if (address_mode == mode_64bit)
8992 prefixes |= PREFIX_REPZ;
8995 prefixes |= PREFIX_REPNZ;
8998 prefixes |= PREFIX_LOCK;
9001 prefixes |= PREFIX_CS;
9004 prefixes |= PREFIX_SS;
9007 prefixes |= PREFIX_DS;
9010 prefixes |= PREFIX_ES;
9013 prefixes |= PREFIX_FS;
9016 prefixes |= PREFIX_GS;
9019 prefixes |= PREFIX_DATA;
9022 prefixes |= PREFIX_ADDR;
9025 /* fwait is really an instruction. If there are prefixes
9026 before the fwait, they belong to the fwait, *not* to the
9027 following instruction. */
9028 if (prefixes || rex)
9030 prefixes |= PREFIX_FWAIT;
9034 prefixes = PREFIX_FWAIT;
9039 /* Rex is ignored when followed by another prefix. */
9051 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9055 prefix_name (int pref, int sizeflag)
9057 static const char *rexes [16] =
9062 "rex.XB", /* 0x43 */
9064 "rex.RB", /* 0x45 */
9065 "rex.RX", /* 0x46 */
9066 "rex.RXB", /* 0x47 */
9068 "rex.WB", /* 0x49 */
9069 "rex.WX", /* 0x4a */
9070 "rex.WXB", /* 0x4b */
9071 "rex.WR", /* 0x4c */
9072 "rex.WRB", /* 0x4d */
9073 "rex.WRX", /* 0x4e */
9074 "rex.WRXB", /* 0x4f */
9079 /* REX prefixes family. */
9096 return rexes [pref - 0x40];
9116 return (sizeflag & DFLAG) ? "data16" : "data32";
9118 if (address_mode == mode_64bit)
9119 return (sizeflag & AFLAG) ? "addr32" : "addr64";
9121 return (sizeflag & AFLAG) ? "addr16" : "addr32";
9129 static char op_out[MAX_OPERANDS][100];
9130 static int op_ad, op_index[MAX_OPERANDS];
9131 static int two_source_ops;
9132 static bfd_vma op_address[MAX_OPERANDS];
9133 static bfd_vma op_riprel[MAX_OPERANDS];
9134 static bfd_vma start_pc;
9137 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9138 * (see topic "Redundant prefixes" in the "Differences from 8086"
9139 * section of the "Virtual 8086 Mode" chapter.)
9140 * 'pc' should be the address of this instruction, it will
9141 * be used to print the target address if this is a relative jump or call
9142 * The function returns the length of this instruction in bytes.
9145 static char intel_syntax;
9146 static char intel_mnemonic = !SYSV386_COMPAT;
9147 static char open_char;
9148 static char close_char;
9149 static char separator_char;
9150 static char scale_char;
9152 /* Here for backwards compatibility. When gdb stops using
9153 print_insn_i386_att and print_insn_i386_intel these functions can
9154 disappear, and print_insn_i386 be merged into print_insn. */
9156 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9160 return print_insn (pc, info);
9164 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9168 return print_insn (pc, info);
9172 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9176 return print_insn (pc, info);
9180 print_i386_disassembler_options (FILE *stream)
9182 fprintf (stream, _("\n\
9183 The following i386/x86-64 specific disassembler options are supported for use\n\
9184 with the -M switch (multiple options should be separated by commas):\n"));
9186 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
9187 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
9188 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
9189 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
9190 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
9191 fprintf (stream, _(" att-mnemonic\n"
9192 " Display instruction in AT&T mnemonic\n"));
9193 fprintf (stream, _(" intel-mnemonic\n"
9194 " Display instruction in Intel mnemonic\n"));
9195 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
9196 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
9197 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
9198 fprintf (stream, _(" data32 Assume 32bit data size\n"));
9199 fprintf (stream, _(" data16 Assume 16bit data size\n"));
9200 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
9203 /* Get a pointer to struct dis386 with a valid name. */
9205 static const struct dis386 *
9206 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9208 int index, vex_table_index;
9210 if (dp->name != NULL)
9213 switch (dp->op[0].bytemode)
9216 dp = ®_table[dp->op[1].bytemode][modrm.reg];
9220 index = modrm.mod == 0x3 ? 1 : 0;
9221 dp = &mod_table[dp->op[1].bytemode][index];
9225 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9228 case USE_PREFIX_TABLE:
9231 /* The prefix in VEX is implicit. */
9237 case REPE_PREFIX_OPCODE:
9240 case DATA_PREFIX_OPCODE:
9243 case REPNE_PREFIX_OPCODE:
9254 used_prefixes |= (prefixes & PREFIX_REPZ);
9255 if (prefixes & PREFIX_REPZ)
9262 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
9264 used_prefixes |= (prefixes & PREFIX_REPNZ);
9265 if (prefixes & PREFIX_REPNZ)
9268 repnz_prefix = NULL;
9272 used_prefixes |= (prefixes & PREFIX_DATA);
9273 if (prefixes & PREFIX_DATA)
9281 dp = &prefix_table[dp->op[1].bytemode][index];
9284 case USE_X86_64_TABLE:
9285 index = address_mode == mode_64bit ? 1 : 0;
9286 dp = &x86_64_table[dp->op[1].bytemode][index];
9289 case USE_3BYTE_TABLE:
9290 FETCH_DATA (info, codep + 2);
9292 dp = &three_byte_table[dp->op[1].bytemode][index];
9293 modrm.mod = (*codep >> 6) & 3;
9294 modrm.reg = (*codep >> 3) & 7;
9295 modrm.rm = *codep & 7;
9298 case USE_VEX_LEN_TABLE:
9315 dp = &vex_len_table[dp->op[1].bytemode][index];
9318 case USE_VEX_C4_TABLE:
9319 FETCH_DATA (info, codep + 3);
9320 /* All bits in the REX prefix are ignored. */
9322 rex = ~(*codep >> 5) & 0x7;
9323 switch ((*codep & 0x1f))
9328 vex_table_index = 0;
9331 vex_table_index = 1;
9334 vex_table_index = 2;
9338 vex.w = *codep & 0x80;
9339 if (vex.w && address_mode == mode_64bit)
9342 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9343 if (address_mode != mode_64bit
9344 && vex.register_specifier > 0x7)
9347 vex.length = (*codep & 0x4) ? 256 : 128;
9348 switch ((*codep & 0x3))
9354 vex.prefix = DATA_PREFIX_OPCODE;
9357 vex.prefix = REPE_PREFIX_OPCODE;
9360 vex.prefix = REPNE_PREFIX_OPCODE;
9367 dp = &vex_table[vex_table_index][index];
9368 /* There is no MODRM byte for VEX [82|77]. */
9369 if (index != 0x77 && index != 0x82)
9371 FETCH_DATA (info, codep + 1);
9372 modrm.mod = (*codep >> 6) & 3;
9373 modrm.reg = (*codep >> 3) & 7;
9374 modrm.rm = *codep & 7;
9378 case USE_VEX_C5_TABLE:
9379 FETCH_DATA (info, codep + 2);
9380 /* All bits in the REX prefix are ignored. */
9382 rex = (*codep & 0x80) ? 0 : REX_R;
9384 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9385 if (address_mode != mode_64bit
9386 && vex.register_specifier > 0x7)
9389 vex.length = (*codep & 0x4) ? 256 : 128;
9390 switch ((*codep & 0x3))
9396 vex.prefix = DATA_PREFIX_OPCODE;
9399 vex.prefix = REPE_PREFIX_OPCODE;
9402 vex.prefix = REPNE_PREFIX_OPCODE;
9409 dp = &vex_table[dp->op[1].bytemode][index];
9410 /* There is no MODRM byte for VEX [82|77]. */
9411 if (index != 0x77 && index != 0x82)
9413 FETCH_DATA (info, codep + 1);
9414 modrm.mod = (*codep >> 6) & 3;
9415 modrm.reg = (*codep >> 3) & 7;
9416 modrm.rm = *codep & 7;
9424 if (dp->name != NULL)
9427 return get_valid_dis386 (dp, info);
9431 print_insn (bfd_vma pc, disassemble_info *info)
9433 const struct dis386 *dp;
9435 char *op_txt[MAX_OPERANDS];
9439 struct dis_private priv;
9441 char prefix_obuf[32];
9444 if (info->mach == bfd_mach_x86_64_intel_syntax
9445 || info->mach == bfd_mach_x86_64
9446 || info->mach == bfd_mach_l1om
9447 || info->mach == bfd_mach_l1om_intel_syntax)
9448 address_mode = mode_64bit;
9450 address_mode = mode_32bit;
9452 if (intel_syntax == (char) -1)
9453 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
9454 || info->mach == bfd_mach_x86_64_intel_syntax
9455 || info->mach == bfd_mach_l1om_intel_syntax);
9457 if (info->mach == bfd_mach_i386_i386
9458 || info->mach == bfd_mach_x86_64
9459 || info->mach == bfd_mach_l1om
9460 || info->mach == bfd_mach_i386_i386_intel_syntax
9461 || info->mach == bfd_mach_x86_64_intel_syntax
9462 || info->mach == bfd_mach_l1om_intel_syntax)
9463 priv.orig_sizeflag = AFLAG | DFLAG;
9464 else if (info->mach == bfd_mach_i386_i8086)
9465 priv.orig_sizeflag = 0;
9469 for (p = info->disassembler_options; p != NULL; )
9471 if (CONST_STRNEQ (p, "x86-64"))
9473 address_mode = mode_64bit;
9474 priv.orig_sizeflag = AFLAG | DFLAG;
9476 else if (CONST_STRNEQ (p, "i386"))
9478 address_mode = mode_32bit;
9479 priv.orig_sizeflag = AFLAG | DFLAG;
9481 else if (CONST_STRNEQ (p, "i8086"))
9483 address_mode = mode_16bit;
9484 priv.orig_sizeflag = 0;
9486 else if (CONST_STRNEQ (p, "intel"))
9489 if (CONST_STRNEQ (p + 5, "-mnemonic"))
9492 else if (CONST_STRNEQ (p, "att"))
9495 if (CONST_STRNEQ (p + 3, "-mnemonic"))
9498 else if (CONST_STRNEQ (p, "addr"))
9500 if (address_mode == mode_64bit)
9502 if (p[4] == '3' && p[5] == '2')
9503 priv.orig_sizeflag &= ~AFLAG;
9504 else if (p[4] == '6' && p[5] == '4')
9505 priv.orig_sizeflag |= AFLAG;
9509 if (p[4] == '1' && p[5] == '6')
9510 priv.orig_sizeflag &= ~AFLAG;
9511 else if (p[4] == '3' && p[5] == '2')
9512 priv.orig_sizeflag |= AFLAG;
9515 else if (CONST_STRNEQ (p, "data"))
9517 if (p[4] == '1' && p[5] == '6')
9518 priv.orig_sizeflag &= ~DFLAG;
9519 else if (p[4] == '3' && p[5] == '2')
9520 priv.orig_sizeflag |= DFLAG;
9522 else if (CONST_STRNEQ (p, "suffix"))
9523 priv.orig_sizeflag |= SUFFIX_ALWAYS;
9525 p = strchr (p, ',');
9532 names64 = intel_names64;
9533 names32 = intel_names32;
9534 names16 = intel_names16;
9535 names8 = intel_names8;
9536 names8rex = intel_names8rex;
9537 names_seg = intel_names_seg;
9538 index64 = intel_index64;
9539 index32 = intel_index32;
9540 index16 = intel_index16;
9543 separator_char = '+';
9548 names64 = att_names64;
9549 names32 = att_names32;
9550 names16 = att_names16;
9551 names8 = att_names8;
9552 names8rex = att_names8rex;
9553 names_seg = att_names_seg;
9554 index64 = att_index64;
9555 index32 = att_index32;
9556 index16 = att_index16;
9559 separator_char = ',';
9563 /* The output looks better if we put 7 bytes on a line, since that
9564 puts most long word instructions on a single line. Use 8 bytes
9566 if (info->mach == bfd_mach_l1om
9567 || info->mach == bfd_mach_l1om_intel_syntax)
9568 info->bytes_per_line = 8;
9570 info->bytes_per_line = 7;
9572 info->private_data = &priv;
9573 priv.max_fetched = priv.the_buffer;
9574 priv.insn_start = pc;
9577 for (i = 0; i < MAX_OPERANDS; ++i)
9585 start_codep = priv.the_buffer;
9586 codep = priv.the_buffer;
9588 if (setjmp (priv.bailout) != 0)
9592 /* Getting here means we tried for data but didn't get it. That
9593 means we have an incomplete instruction of some sort. Just
9594 print the first byte as a prefix or a .byte pseudo-op. */
9595 if (codep > priv.the_buffer)
9597 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9599 (*info->fprintf_func) (info->stream, "%s", name);
9602 /* Just print the first byte as a .byte instruction. */
9603 (*info->fprintf_func) (info->stream, ".byte 0x%x",
9604 (unsigned int) priv.the_buffer[0]);
9617 sizeflag = priv.orig_sizeflag;
9619 FETCH_DATA (info, codep + 1);
9620 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
9622 if (((prefixes & PREFIX_FWAIT)
9623 && ((*codep < 0xd8) || (*codep > 0xdf)))
9624 || (rex && rex_used))
9628 /* fwait not followed by floating point instruction, or rex followed
9629 by other prefixes. Print the first prefix. */
9630 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9632 name = INTERNAL_DISASSEMBLER_ERROR;
9633 (*info->fprintf_func) (info->stream, "%s", name);
9641 unsigned char threebyte;
9642 FETCH_DATA (info, codep + 2);
9643 threebyte = *++codep;
9644 dp = &dis386_twobyte[threebyte];
9645 need_modrm = twobyte_has_modrm[*codep];
9650 dp = &dis386[*codep];
9651 need_modrm = onebyte_has_modrm[*codep];
9655 if ((prefixes & PREFIX_REPZ))
9657 repz_prefix = "repz ";
9658 used_prefixes |= PREFIX_REPZ;
9663 if ((prefixes & PREFIX_REPNZ))
9665 repnz_prefix = "repnz ";
9666 used_prefixes |= PREFIX_REPNZ;
9669 repnz_prefix = NULL;
9671 if ((prefixes & PREFIX_LOCK))
9673 lock_prefix = "lock ";
9674 used_prefixes |= PREFIX_LOCK;
9680 if (prefixes & PREFIX_ADDR)
9683 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
9685 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
9686 addr_prefix = "addr32 ";
9688 addr_prefix = "addr16 ";
9689 used_prefixes |= PREFIX_ADDR;
9694 if ((prefixes & PREFIX_DATA))
9697 if (dp->op[2].bytemode == cond_jump_mode
9698 && dp->op[0].bytemode == v_mode
9701 if (sizeflag & DFLAG)
9702 data_prefix = "data32 ";
9704 data_prefix = "data16 ";
9705 used_prefixes |= PREFIX_DATA;
9711 FETCH_DATA (info, codep + 1);
9712 modrm.mod = (*codep >> 6) & 3;
9713 modrm.reg = (*codep >> 3) & 7;
9714 modrm.rm = *codep & 7;
9721 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9727 dp = get_valid_dis386 (dp, info);
9728 if (dp != NULL && putop (dp->name, sizeflag) == 0)
9730 for (i = 0; i < MAX_OPERANDS; ++i)
9733 op_ad = MAX_OPERANDS - 1 - i;
9735 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
9740 /* See if any prefixes were not used. If so, print the first one
9741 separately. If we don't do this, we'll wind up printing an
9742 instruction stream which does not precisely correspond to the
9743 bytes we are disassembling. */
9744 if ((prefixes & ~used_prefixes) != 0)
9748 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9750 name = INTERNAL_DISASSEMBLER_ERROR;
9751 (*info->fprintf_func) (info->stream, "%s", name);
9754 if ((rex_original & ~rex_used) || rex_ignored)
9757 name = prefix_name (rex_original, priv.orig_sizeflag);
9759 name = INTERNAL_DISASSEMBLER_ERROR;
9760 (*info->fprintf_func) (info->stream, "%s ", name);
9764 prefix_obufp = prefix_obuf;
9766 prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
9768 prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
9770 prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
9772 prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
9774 prefix_obufp = stpcpy (prefix_obufp, data_prefix);
9776 if (prefix_obuf[0] != 0)
9777 (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
9779 obufp = mnemonicendp;
9780 for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
9783 (*info->fprintf_func) (info->stream, "%s", obuf);
9785 /* The enter and bound instructions are printed with operands in the same
9786 order as the intel book; everything else is printed in reverse order. */
9787 if (intel_syntax || two_source_ops)
9791 for (i = 0; i < MAX_OPERANDS; ++i)
9792 op_txt[i] = op_out[i];
9794 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9796 op_ad = op_index[i];
9797 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
9798 op_index[MAX_OPERANDS - 1 - i] = op_ad;
9799 riprel = op_riprel[i];
9800 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
9801 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9806 for (i = 0; i < MAX_OPERANDS; ++i)
9807 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
9811 for (i = 0; i < MAX_OPERANDS; ++i)
9815 (*info->fprintf_func) (info->stream, ",");
9816 if (op_index[i] != -1 && !op_riprel[i])
9817 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
9819 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
9823 for (i = 0; i < MAX_OPERANDS; i++)
9824 if (op_index[i] != -1 && op_riprel[i])
9826 (*info->fprintf_func) (info->stream, " # ");
9827 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
9828 + op_address[op_index[i]]), info);
9831 return codep - priv.the_buffer;
9834 static const char *float_mem[] = {
9909 static const unsigned char float_mem_mode[] = {
9984 #define ST { OP_ST, 0 }
9985 #define STi { OP_STi, 0 }
9987 #define FGRPd9_2 NULL, { { NULL, 0 } }
9988 #define FGRPd9_4 NULL, { { NULL, 1 } }
9989 #define FGRPd9_5 NULL, { { NULL, 2 } }
9990 #define FGRPd9_6 NULL, { { NULL, 3 } }
9991 #define FGRPd9_7 NULL, { { NULL, 4 } }
9992 #define FGRPda_5 NULL, { { NULL, 5 } }
9993 #define FGRPdb_4 NULL, { { NULL, 6 } }
9994 #define FGRPde_3 NULL, { { NULL, 7 } }
9995 #define FGRPdf_4 NULL, { { NULL, 8 } }
9997 static const struct dis386 float_reg[][8] = {
10000 { "fadd", { ST, STi } },
10001 { "fmul", { ST, STi } },
10002 { "fcom", { STi } },
10003 { "fcomp", { STi } },
10004 { "fsub", { ST, STi } },
10005 { "fsubr", { ST, STi } },
10006 { "fdiv", { ST, STi } },
10007 { "fdivr", { ST, STi } },
10011 { "fld", { STi } },
10012 { "fxch", { STi } },
10014 { "(bad)", { XX } },
10022 { "fcmovb", { ST, STi } },
10023 { "fcmove", { ST, STi } },
10024 { "fcmovbe",{ ST, STi } },
10025 { "fcmovu", { ST, STi } },
10026 { "(bad)", { XX } },
10028 { "(bad)", { XX } },
10029 { "(bad)", { XX } },
10033 { "fcmovnb",{ ST, STi } },
10034 { "fcmovne",{ ST, STi } },
10035 { "fcmovnbe",{ ST, STi } },
10036 { "fcmovnu",{ ST, STi } },
10038 { "fucomi", { ST, STi } },
10039 { "fcomi", { ST, STi } },
10040 { "(bad)", { XX } },
10044 { "fadd", { STi, ST } },
10045 { "fmul", { STi, ST } },
10046 { "(bad)", { XX } },
10047 { "(bad)", { XX } },
10048 { "fsub!M", { STi, ST } },
10049 { "fsubM", { STi, ST } },
10050 { "fdiv!M", { STi, ST } },
10051 { "fdivM", { STi, ST } },
10055 { "ffree", { STi } },
10056 { "(bad)", { XX } },
10057 { "fst", { STi } },
10058 { "fstp", { STi } },
10059 { "fucom", { STi } },
10060 { "fucomp", { STi } },
10061 { "(bad)", { XX } },
10062 { "(bad)", { XX } },
10066 { "faddp", { STi, ST } },
10067 { "fmulp", { STi, ST } },
10068 { "(bad)", { XX } },
10070 { "fsub!Mp", { STi, ST } },
10071 { "fsubMp", { STi, ST } },
10072 { "fdiv!Mp", { STi, ST } },
10073 { "fdivMp", { STi, ST } },
10077 { "ffreep", { STi } },
10078 { "(bad)", { XX } },
10079 { "(bad)", { XX } },
10080 { "(bad)", { XX } },
10082 { "fucomip", { ST, STi } },
10083 { "fcomip", { ST, STi } },
10084 { "(bad)", { XX } },
10088 static char *fgrps[][8] = {
10091 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10096 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10101 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10106 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10111 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10116 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10121 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10122 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10127 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10132 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10137 swap_operand (void)
10139 mnemonicendp[0] = '.';
10140 mnemonicendp[1] = 's';
10145 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10146 int sizeflag ATTRIBUTE_UNUSED)
10148 /* Skip mod/rm byte. */
10154 dofloat (int sizeflag)
10156 const struct dis386 *dp;
10157 unsigned char floatop;
10159 floatop = codep[-1];
10161 if (modrm.mod != 3)
10163 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10165 putop (float_mem[fp_indx], sizeflag);
10168 OP_E (float_mem_mode[fp_indx], sizeflag);
10171 /* Skip mod/rm byte. */
10175 dp = &float_reg[floatop - 0xd8][modrm.reg];
10176 if (dp->name == NULL)
10178 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10180 /* Instruction fnstsw is only one with strange arg. */
10181 if (floatop == 0xdf && codep[-1] == 0xe0)
10182 strcpy (op_out[0], names16[0]);
10186 putop (dp->name, sizeflag);
10191 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10196 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10201 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10203 oappend ("%st" + intel_syntax);
10207 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10209 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10210 oappend (scratchbuf + intel_syntax);
10213 /* Capital letters in template are macros. */
10215 putop (const char *in_template, int sizeflag)
10220 unsigned int l = 0, len = 1;
10223 #define SAVE_LAST(c) \
10224 if (l < len && l < sizeof (last)) \
10229 for (p = in_template; *p; p++)
10246 while (*++p != '|')
10247 if (*p == '}' || *p == '\0')
10250 /* Fall through. */
10255 while (*++p != '}')
10266 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10272 if (sizeflag & SUFFIX_ALWAYS)
10276 if (intel_syntax && !alt)
10278 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10280 if (sizeflag & DFLAG)
10281 *obufp++ = intel_syntax ? 'd' : 'l';
10283 *obufp++ = intel_syntax ? 'w' : 's';
10284 used_prefixes |= (prefixes & PREFIX_DATA);
10288 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10291 if (modrm.mod == 3)
10295 else if (sizeflag & DFLAG)
10296 *obufp++ = intel_syntax ? 'd' : 'l';
10299 used_prefixes |= (prefixes & PREFIX_DATA);
10304 case 'E': /* For jcxz/jecxz */
10305 if (address_mode == mode_64bit)
10307 if (sizeflag & AFLAG)
10313 if (sizeflag & AFLAG)
10315 used_prefixes |= (prefixes & PREFIX_ADDR);
10320 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10322 if (sizeflag & AFLAG)
10323 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10325 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10326 used_prefixes |= (prefixes & PREFIX_ADDR);
10330 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10332 if ((rex & REX_W) || (sizeflag & DFLAG))
10336 if (!(rex & REX_W))
10337 used_prefixes |= (prefixes & PREFIX_DATA);
10342 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10343 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10345 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10348 if (prefixes & PREFIX_DS)
10369 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
10374 /* Fall through. */
10377 if (l != 0 || len != 1)
10385 if (sizeflag & SUFFIX_ALWAYS)
10389 if (intel_mnemonic != cond)
10393 if ((prefixes & PREFIX_FWAIT) == 0)
10396 used_prefixes |= PREFIX_FWAIT;
10402 else if (intel_syntax && (sizeflag & DFLAG))
10406 if (!(rex & REX_W))
10407 used_prefixes |= (prefixes & PREFIX_DATA);
10412 if (address_mode == mode_64bit && (sizeflag & DFLAG))
10417 /* Fall through. */
10421 if ((prefixes & PREFIX_DATA)
10423 || (sizeflag & SUFFIX_ALWAYS))
10430 if (sizeflag & DFLAG)
10435 used_prefixes |= (prefixes & PREFIX_DATA);
10441 if (address_mode == mode_64bit && (sizeflag & DFLAG))
10443 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10447 /* Fall through. */
10450 if (l == 0 && len == 1)
10453 if (intel_syntax && !alt)
10456 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10462 if (sizeflag & DFLAG)
10463 *obufp++ = intel_syntax ? 'd' : 'l';
10467 used_prefixes |= (prefixes & PREFIX_DATA);
10472 if (l != 1 || len != 2 || last[0] != 'L')
10478 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
10493 else if (sizeflag & DFLAG)
10502 if (intel_syntax && !p[1]
10503 && ((rex & REX_W) || (sizeflag & DFLAG)))
10505 if (!(rex & REX_W))
10506 used_prefixes |= (prefixes & PREFIX_DATA);
10511 if (address_mode == mode_64bit && (sizeflag & DFLAG))
10513 if (sizeflag & SUFFIX_ALWAYS)
10517 /* Fall through. */
10521 if (sizeflag & SUFFIX_ALWAYS)
10527 if (sizeflag & DFLAG)
10531 used_prefixes |= (prefixes & PREFIX_DATA);
10536 if (l != 0 || len != 1)
10541 if (need_vex && vex.prefix)
10543 if (vex.prefix == DATA_PREFIX_OPCODE)
10548 else if (prefixes & PREFIX_DATA)
10552 used_prefixes |= (prefixes & PREFIX_DATA);
10555 if (l == 0 && len == 1)
10557 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10568 if (l != 1 || len != 2 || last[0] != 'X')
10576 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
10578 switch (vex.length)
10592 if (l == 0 && len == 1)
10594 /* operand size flag for cwtl, cbtw */
10603 else if (sizeflag & DFLAG)
10607 if (!(rex & REX_W))
10608 used_prefixes |= (prefixes & PREFIX_DATA);
10612 if (l != 1 || len != 2 || last[0] != 'X')
10619 *obufp++ = vex.w ? 'd': 's';
10626 mnemonicendp = obufp;
10631 oappend (const char *s)
10633 obufp = stpcpy (obufp, s);
10639 if (prefixes & PREFIX_CS)
10641 used_prefixes |= PREFIX_CS;
10642 oappend ("%cs:" + intel_syntax);
10644 if (prefixes & PREFIX_DS)
10646 used_prefixes |= PREFIX_DS;
10647 oappend ("%ds:" + intel_syntax);
10649 if (prefixes & PREFIX_SS)
10651 used_prefixes |= PREFIX_SS;
10652 oappend ("%ss:" + intel_syntax);
10654 if (prefixes & PREFIX_ES)
10656 used_prefixes |= PREFIX_ES;
10657 oappend ("%es:" + intel_syntax);
10659 if (prefixes & PREFIX_FS)
10661 used_prefixes |= PREFIX_FS;
10662 oappend ("%fs:" + intel_syntax);
10664 if (prefixes & PREFIX_GS)
10666 used_prefixes |= PREFIX_GS;
10667 oappend ("%gs:" + intel_syntax);
10672 OP_indirE (int bytemode, int sizeflag)
10676 OP_E (bytemode, sizeflag);
10680 print_operand_value (char *buf, int hex, bfd_vma disp)
10682 if (address_mode == mode_64bit)
10690 sprintf_vma (tmp, disp);
10691 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
10692 strcpy (buf + 2, tmp + i);
10696 bfd_signed_vma v = disp;
10703 /* Check for possible overflow on 0x8000000000000000. */
10706 strcpy (buf, "9223372036854775808");
10720 tmp[28 - i] = (v % 10) + '0';
10724 strcpy (buf, tmp + 29 - i);
10730 sprintf (buf, "0x%x", (unsigned int) disp);
10732 sprintf (buf, "%d", (int) disp);
10736 /* Put DISP in BUF as signed hex number. */
10739 print_displacement (char *buf, bfd_vma disp)
10741 bfd_signed_vma val = disp;
10750 /* Check for possible overflow. */
10753 switch (address_mode)
10756 strcpy (buf + j, "0x8000000000000000");
10759 strcpy (buf + j, "0x80000000");
10762 strcpy (buf + j, "0x8000");
10772 sprintf_vma (tmp, (bfd_vma) val);
10773 for (i = 0; tmp[i] == '0'; i++)
10775 if (tmp[i] == '\0')
10777 strcpy (buf + j, tmp + i);
10781 intel_operand_size (int bytemode, int sizeflag)
10788 oappend ("BYTE PTR ");
10792 oappend ("WORD PTR ");
10795 if (address_mode == mode_64bit && (sizeflag & DFLAG))
10797 oappend ("QWORD PTR ");
10798 used_prefixes |= (prefixes & PREFIX_DATA);
10807 oappend ("QWORD PTR ");
10808 else if ((sizeflag & DFLAG) || bytemode == dq_mode)
10809 oappend ("DWORD PTR ");
10811 oappend ("WORD PTR ");
10812 used_prefixes |= (prefixes & PREFIX_DATA);
10815 if ((rex & REX_W) || (sizeflag & DFLAG))
10817 oappend ("WORD PTR ");
10818 if (!(rex & REX_W))
10819 used_prefixes |= (prefixes & PREFIX_DATA);
10822 if (sizeflag & DFLAG)
10823 oappend ("QWORD PTR ");
10825 oappend ("DWORD PTR ");
10826 used_prefixes |= (prefixes & PREFIX_DATA);
10831 oappend ("DWORD PTR ");
10835 oappend ("QWORD PTR ");
10838 if (address_mode == mode_64bit)
10839 oappend ("QWORD PTR ");
10841 oappend ("DWORD PTR ");
10844 if (sizeflag & DFLAG)
10845 oappend ("FWORD PTR ");
10847 oappend ("DWORD PTR ");
10848 used_prefixes |= (prefixes & PREFIX_DATA);
10851 oappend ("TBYTE PTR ");
10857 switch (vex.length)
10860 oappend ("XMMWORD PTR ");
10863 oappend ("YMMWORD PTR ");
10870 oappend ("XMMWORD PTR ");
10873 oappend ("XMMWORD PTR ");
10879 switch (vex.length)
10882 oappend ("QWORD PTR ");
10885 oappend ("XMMWORD PTR ");
10895 switch (vex.length)
10898 oappend ("QWORD PTR ");
10901 oappend ("YMMWORD PTR ");
10908 oappend ("OWORD PTR ");
10910 case vex_w_dq_mode:
10915 oappend ("QWORD PTR ");
10917 oappend ("DWORD PTR ");
10925 OP_E_register (int bytemode, int sizeflag)
10927 int reg = modrm.rm;
10928 const char **names;
10934 if ((sizeflag & SUFFIX_ALWAYS)
10935 && (bytemode == b_swap_mode || bytemode == v_swap_mode))
10958 names = address_mode == mode_64bit ? names64 : names32;
10961 if (address_mode == mode_64bit && (sizeflag & DFLAG))
10964 used_prefixes |= (prefixes & PREFIX_DATA);
10978 else if ((sizeflag & DFLAG)
10979 || (bytemode != v_mode
10980 && bytemode != v_swap_mode))
10984 used_prefixes |= (prefixes & PREFIX_DATA);
10989 oappend (INTERNAL_DISASSEMBLER_ERROR);
10992 oappend (names[reg]);
10996 OP_E_memory (int bytemode, int sizeflag)
10999 int add = (rex & REX_B) ? 8 : 0;
11004 intel_operand_size (bytemode, sizeflag);
11007 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11009 /* 32/64 bit address mode */
11027 FETCH_DATA (the_info, codep + 1);
11028 index = (*codep >> 3) & 7;
11029 scale = (*codep >> 6) & 3;
11034 haveindex = index != 4;
11037 rbase = base + add;
11045 if (address_mode == mode_64bit && !havesib)
11051 FETCH_DATA (the_info, codep + 1);
11053 if ((disp & 0x80) != 0)
11061 /* In 32bit mode, we need index register to tell [offset] from
11062 [eiz*1 + offset]. */
11063 needindex = (havesib
11066 && address_mode == mode_32bit);
11067 havedisp = (havebase
11069 || (havesib && (haveindex || scale != 0)));
11072 if (modrm.mod != 0 || base == 5)
11074 if (havedisp || riprel)
11075 print_displacement (scratchbuf, disp);
11077 print_operand_value (scratchbuf, 1, disp);
11078 oappend (scratchbuf);
11082 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
11086 if (havebase || haveindex || riprel)
11087 used_prefixes |= PREFIX_ADDR;
11089 if (havedisp || (intel_syntax && riprel))
11091 *obufp++ = open_char;
11092 if (intel_syntax && riprel)
11095 oappend (sizeflag & AFLAG ? "rip" : "eip");
11099 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
11100 ? names64[rbase] : names32[rbase]);
11103 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11104 print index to tell base + index from base. */
11108 || (havebase && base != ESP_REG_NUM))
11110 if (!intel_syntax || havebase)
11112 *obufp++ = separator_char;
11116 oappend (address_mode == mode_64bit
11117 && (sizeflag & AFLAG)
11118 ? names64[index] : names32[index]);
11120 oappend (address_mode == mode_64bit
11121 && (sizeflag & AFLAG)
11122 ? index64 : index32);
11124 *obufp++ = scale_char;
11126 sprintf (scratchbuf, "%d", 1 << scale);
11127 oappend (scratchbuf);
11131 && (disp || modrm.mod != 0 || base == 5))
11133 if (!havedisp || (bfd_signed_vma) disp >= 0)
11138 else if (modrm.mod != 1 && disp != -disp)
11142 disp = - (bfd_signed_vma) disp;
11146 print_displacement (scratchbuf, disp);
11148 print_operand_value (scratchbuf, 1, disp);
11149 oappend (scratchbuf);
11152 *obufp++ = close_char;
11155 else if (intel_syntax)
11157 if (modrm.mod != 0 || base == 5)
11159 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11160 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11164 oappend (names_seg[ds_reg - es_reg]);
11167 print_operand_value (scratchbuf, 1, disp);
11168 oappend (scratchbuf);
11173 { /* 16 bit address mode */
11180 if ((disp & 0x8000) != 0)
11185 FETCH_DATA (the_info, codep + 1);
11187 if ((disp & 0x80) != 0)
11192 if ((disp & 0x8000) != 0)
11198 if (modrm.mod != 0 || modrm.rm == 6)
11200 print_displacement (scratchbuf, disp);
11201 oappend (scratchbuf);
11204 if (modrm.mod != 0 || modrm.rm != 6)
11206 *obufp++ = open_char;
11208 oappend (index16[modrm.rm]);
11210 && (disp || modrm.mod != 0 || modrm.rm == 6))
11212 if ((bfd_signed_vma) disp >= 0)
11217 else if (modrm.mod != 1)
11221 disp = - (bfd_signed_vma) disp;
11224 print_displacement (scratchbuf, disp);
11225 oappend (scratchbuf);
11228 *obufp++ = close_char;
11231 else if (intel_syntax)
11233 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11234 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11238 oappend (names_seg[ds_reg - es_reg]);
11241 print_operand_value (scratchbuf, 1, disp & 0xffff);
11242 oappend (scratchbuf);
11248 OP_E_extended (int bytemode, int sizeflag)
11250 /* Skip mod/rm byte. */
11254 if (modrm.mod == 3)
11255 OP_E_register (bytemode, sizeflag);
11257 OP_E_memory (bytemode, sizeflag);
11261 OP_E (int bytemode, int sizeflag)
11263 OP_E_extended (bytemode, sizeflag);
11268 OP_G (int bytemode, int sizeflag)
11279 oappend (names8rex[modrm.reg + add]);
11281 oappend (names8[modrm.reg + add]);
11284 oappend (names16[modrm.reg + add]);
11287 oappend (names32[modrm.reg + add]);
11290 oappend (names64[modrm.reg + add]);
11299 oappend (names64[modrm.reg + add]);
11300 else if ((sizeflag & DFLAG) || bytemode != v_mode)
11301 oappend (names32[modrm.reg + add]);
11303 oappend (names16[modrm.reg + add]);
11304 used_prefixes |= (prefixes & PREFIX_DATA);
11307 if (address_mode == mode_64bit)
11308 oappend (names64[modrm.reg + add]);
11310 oappend (names32[modrm.reg + add]);
11313 oappend (INTERNAL_DISASSEMBLER_ERROR);
11326 FETCH_DATA (the_info, codep + 8);
11327 a = *codep++ & 0xff;
11328 a |= (*codep++ & 0xff) << 8;
11329 a |= (*codep++ & 0xff) << 16;
11330 a |= (*codep++ & 0xff) << 24;
11331 b = *codep++ & 0xff;
11332 b |= (*codep++ & 0xff) << 8;
11333 b |= (*codep++ & 0xff) << 16;
11334 b |= (*codep++ & 0xff) << 24;
11335 x = a + ((bfd_vma) b << 32);
11343 static bfd_signed_vma
11346 bfd_signed_vma x = 0;
11348 FETCH_DATA (the_info, codep + 4);
11349 x = *codep++ & (bfd_signed_vma) 0xff;
11350 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11351 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11352 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11356 static bfd_signed_vma
11359 bfd_signed_vma x = 0;
11361 FETCH_DATA (the_info, codep + 4);
11362 x = *codep++ & (bfd_signed_vma) 0xff;
11363 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11364 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11365 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11367 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
11377 FETCH_DATA (the_info, codep + 2);
11378 x = *codep++ & 0xff;
11379 x |= (*codep++ & 0xff) << 8;
11384 set_op (bfd_vma op, int riprel)
11386 op_index[op_ad] = op_ad;
11387 if (address_mode == mode_64bit)
11389 op_address[op_ad] = op;
11390 op_riprel[op_ad] = riprel;
11394 /* Mask to get a 32-bit address. */
11395 op_address[op_ad] = op & 0xffffffff;
11396 op_riprel[op_ad] = riprel & 0xffffffff;
11401 OP_REG (int code, int sizeflag)
11413 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
11414 case sp_reg: case bp_reg: case si_reg: case di_reg:
11415 s = names16[code - ax_reg + add];
11417 case es_reg: case ss_reg: case cs_reg:
11418 case ds_reg: case fs_reg: case gs_reg:
11419 s = names_seg[code - es_reg + add];
11421 case al_reg: case ah_reg: case cl_reg: case ch_reg:
11422 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
11425 s = names8rex[code - al_reg + add];
11427 s = names8[code - al_reg];
11429 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
11430 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
11431 if (address_mode == mode_64bit && (sizeflag & DFLAG))
11433 s = names64[code - rAX_reg + add];
11436 code += eAX_reg - rAX_reg;
11437 /* Fall through. */
11438 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
11439 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
11442 s = names64[code - eAX_reg + add];
11443 else if (sizeflag & DFLAG)
11444 s = names32[code - eAX_reg + add];
11446 s = names16[code - eAX_reg + add];
11447 used_prefixes |= (prefixes & PREFIX_DATA);
11450 s = INTERNAL_DISASSEMBLER_ERROR;
11457 OP_IMREG (int code, int sizeflag)
11469 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
11470 case sp_reg: case bp_reg: case si_reg: case di_reg:
11471 s = names16[code - ax_reg];
11473 case es_reg: case ss_reg: case cs_reg:
11474 case ds_reg: case fs_reg: case gs_reg:
11475 s = names_seg[code - es_reg];
11477 case al_reg: case ah_reg: case cl_reg: case ch_reg:
11478 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
11481 s = names8rex[code - al_reg];
11483 s = names8[code - al_reg];
11485 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
11486 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
11489 s = names64[code - eAX_reg];
11490 else if (sizeflag & DFLAG)
11491 s = names32[code - eAX_reg];
11493 s = names16[code - eAX_reg];
11494 used_prefixes |= (prefixes & PREFIX_DATA);
11496 case z_mode_ax_reg:
11497 if ((rex & REX_W) || (sizeflag & DFLAG))
11501 if (!(rex & REX_W))
11502 used_prefixes |= (prefixes & PREFIX_DATA);
11505 s = INTERNAL_DISASSEMBLER_ERROR;
11512 OP_I (int bytemode, int sizeflag)
11515 bfd_signed_vma mask = -1;
11520 FETCH_DATA (the_info, codep + 1);
11525 if (address_mode == mode_64bit)
11530 /* Fall through. */
11535 else if (sizeflag & DFLAG)
11545 used_prefixes |= (prefixes & PREFIX_DATA);
11556 oappend (INTERNAL_DISASSEMBLER_ERROR);
11561 scratchbuf[0] = '$';
11562 print_operand_value (scratchbuf + 1, 1, op);
11563 oappend (scratchbuf + intel_syntax);
11564 scratchbuf[0] = '\0';
11568 OP_I64 (int bytemode, int sizeflag)
11571 bfd_signed_vma mask = -1;
11573 if (address_mode != mode_64bit)
11575 OP_I (bytemode, sizeflag);
11582 FETCH_DATA (the_info, codep + 1);
11590 else if (sizeflag & DFLAG)
11600 used_prefixes |= (prefixes & PREFIX_DATA);
11607 oappend (INTERNAL_DISASSEMBLER_ERROR);
11612 scratchbuf[0] = '$';
11613 print_operand_value (scratchbuf + 1, 1, op);
11614 oappend (scratchbuf + intel_syntax);
11615 scratchbuf[0] = '\0';
11619 OP_sI (int bytemode, int sizeflag)
11622 bfd_signed_vma mask = -1;
11627 FETCH_DATA (the_info, codep + 1);
11629 if ((op & 0x80) != 0)
11637 else if (sizeflag & DFLAG)
11646 if ((op & 0x8000) != 0)
11649 used_prefixes |= (prefixes & PREFIX_DATA);
11654 if ((op & 0x8000) != 0)
11658 oappend (INTERNAL_DISASSEMBLER_ERROR);
11662 scratchbuf[0] = '$';
11663 print_operand_value (scratchbuf + 1, 1, op);
11664 oappend (scratchbuf + intel_syntax);
11668 OP_J (int bytemode, int sizeflag)
11672 bfd_vma segment = 0;
11677 FETCH_DATA (the_info, codep + 1);
11679 if ((disp & 0x80) != 0)
11683 if ((sizeflag & DFLAG) || (rex & REX_W))
11688 if ((disp & 0x8000) != 0)
11690 /* In 16bit mode, address is wrapped around at 64k within
11691 the same segment. Otherwise, a data16 prefix on a jump
11692 instruction means that the pc is masked to 16 bits after
11693 the displacement is added! */
11695 if ((prefixes & PREFIX_DATA) == 0)
11696 segment = ((start_pc + codep - start_codep)
11697 & ~((bfd_vma) 0xffff));
11699 used_prefixes |= (prefixes & PREFIX_DATA);
11702 oappend (INTERNAL_DISASSEMBLER_ERROR);
11705 disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
11707 print_operand_value (scratchbuf, 1, disp);
11708 oappend (scratchbuf);
11712 OP_SEG (int bytemode, int sizeflag)
11714 if (bytemode == w_mode)
11715 oappend (names_seg[modrm.reg]);
11717 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
11721 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
11725 if (sizeflag & DFLAG)
11735 used_prefixes |= (prefixes & PREFIX_DATA);
11737 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
11739 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
11740 oappend (scratchbuf);
11744 OP_OFF (int bytemode, int sizeflag)
11748 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
11749 intel_operand_size (bytemode, sizeflag);
11752 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11759 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11760 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
11762 oappend (names_seg[ds_reg - es_reg]);
11766 print_operand_value (scratchbuf, 1, off);
11767 oappend (scratchbuf);
11771 OP_OFF64 (int bytemode, int sizeflag)
11775 if (address_mode != mode_64bit
11776 || (prefixes & PREFIX_ADDR))
11778 OP_OFF (bytemode, sizeflag);
11782 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
11783 intel_operand_size (bytemode, sizeflag);
11790 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11791 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
11793 oappend (names_seg[ds_reg - es_reg]);
11797 print_operand_value (scratchbuf, 1, off);
11798 oappend (scratchbuf);
11802 ptr_reg (int code, int sizeflag)
11806 *obufp++ = open_char;
11807 used_prefixes |= (prefixes & PREFIX_ADDR);
11808 if (address_mode == mode_64bit)
11810 if (!(sizeflag & AFLAG))
11811 s = names32[code - eAX_reg];
11813 s = names64[code - eAX_reg];
11815 else if (sizeflag & AFLAG)
11816 s = names32[code - eAX_reg];
11818 s = names16[code - eAX_reg];
11820 *obufp++ = close_char;
11825 OP_ESreg (int code, int sizeflag)
11831 case 0x6d: /* insw/insl */
11832 intel_operand_size (z_mode, sizeflag);
11834 case 0xa5: /* movsw/movsl/movsq */
11835 case 0xa7: /* cmpsw/cmpsl/cmpsq */
11836 case 0xab: /* stosw/stosl */
11837 case 0xaf: /* scasw/scasl */
11838 intel_operand_size (v_mode, sizeflag);
11841 intel_operand_size (b_mode, sizeflag);
11844 oappend ("%es:" + intel_syntax);
11845 ptr_reg (code, sizeflag);
11849 OP_DSreg (int code, int sizeflag)
11855 case 0x6f: /* outsw/outsl */
11856 intel_operand_size (z_mode, sizeflag);
11858 case 0xa5: /* movsw/movsl/movsq */
11859 case 0xa7: /* cmpsw/cmpsl/cmpsq */
11860 case 0xad: /* lodsw/lodsl/lodsq */
11861 intel_operand_size (v_mode, sizeflag);
11864 intel_operand_size (b_mode, sizeflag);
11873 | PREFIX_GS)) == 0)
11874 prefixes |= PREFIX_DS;
11876 ptr_reg (code, sizeflag);
11880 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11888 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
11890 lock_prefix = NULL;
11891 used_prefixes |= PREFIX_LOCK;
11896 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
11897 oappend (scratchbuf + intel_syntax);
11901 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11910 sprintf (scratchbuf, "db%d", modrm.reg + add);
11912 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
11913 oappend (scratchbuf);
11917 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11919 sprintf (scratchbuf, "%%tr%d", modrm.reg);
11920 oappend (scratchbuf + intel_syntax);
11924 OP_R (int bytemode, int sizeflag)
11926 if (modrm.mod == 3)
11927 OP_E (bytemode, sizeflag);
11933 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11935 used_prefixes |= (prefixes & PREFIX_DATA);
11936 if (prefixes & PREFIX_DATA)
11944 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
11947 sprintf (scratchbuf, "%%mm%d", modrm.reg);
11948 oappend (scratchbuf + intel_syntax);
11952 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
11960 if (need_vex && bytemode != xmm_mode)
11962 switch (vex.length)
11965 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
11968 sprintf (scratchbuf, "%%ymm%d", modrm.reg + add);
11975 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
11976 oappend (scratchbuf + intel_syntax);
11980 OP_EM (int bytemode, int sizeflag)
11982 if (modrm.mod != 3)
11985 && (bytemode == v_mode || bytemode == v_swap_mode))
11987 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
11988 used_prefixes |= (prefixes & PREFIX_DATA);
11990 OP_E (bytemode, sizeflag);
11994 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
11997 /* Skip mod/rm byte. */
12000 used_prefixes |= (prefixes & PREFIX_DATA);
12001 if (prefixes & PREFIX_DATA)
12010 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12013 sprintf (scratchbuf, "%%mm%d", modrm.rm);
12014 oappend (scratchbuf + intel_syntax);
12017 /* cvt* are the only instructions in sse2 which have
12018 both SSE and MMX operands and also have 0x66 prefix
12019 in their opcode. 0x66 was originally used to differentiate
12020 between SSE and MMX instruction(operands). So we have to handle the
12021 cvt* separately using OP_EMC and OP_MXC */
12023 OP_EMC (int bytemode, int sizeflag)
12025 if (modrm.mod != 3)
12027 if (intel_syntax && bytemode == v_mode)
12029 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12030 used_prefixes |= (prefixes & PREFIX_DATA);
12032 OP_E (bytemode, sizeflag);
12036 /* Skip mod/rm byte. */
12039 used_prefixes |= (prefixes & PREFIX_DATA);
12040 sprintf (scratchbuf, "%%mm%d", modrm.rm);
12041 oappend (scratchbuf + intel_syntax);
12045 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12047 used_prefixes |= (prefixes & PREFIX_DATA);
12048 sprintf (scratchbuf, "%%mm%d", modrm.reg);
12049 oappend (scratchbuf + intel_syntax);
12053 OP_EX (int bytemode, int sizeflag)
12057 /* Skip mod/rm byte. */
12061 if (modrm.mod != 3)
12063 OP_E_memory (bytemode, sizeflag);
12073 if ((sizeflag & SUFFIX_ALWAYS)
12074 && (bytemode == x_swap_mode
12075 || bytemode == d_swap_mode
12076 || bytemode == q_swap_mode))
12080 && bytemode != xmm_mode
12081 && bytemode != xmmq_mode)
12083 switch (vex.length)
12086 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12089 sprintf (scratchbuf, "%%ymm%d", modrm.rm + add);
12096 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12097 oappend (scratchbuf + intel_syntax);
12101 OP_MS (int bytemode, int sizeflag)
12103 if (modrm.mod == 3)
12104 OP_EM (bytemode, sizeflag);
12110 OP_XS (int bytemode, int sizeflag)
12112 if (modrm.mod == 3)
12113 OP_EX (bytemode, sizeflag);
12119 OP_M (int bytemode, int sizeflag)
12121 if (modrm.mod == 3)
12122 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12125 OP_E (bytemode, sizeflag);
12129 OP_0f07 (int bytemode, int sizeflag)
12131 if (modrm.mod != 3 || modrm.rm != 0)
12134 OP_E (bytemode, sizeflag);
12137 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12138 32bit mode and "xchg %rax,%rax" in 64bit mode. */
12141 NOP_Fixup1 (int bytemode, int sizeflag)
12143 if ((prefixes & PREFIX_DATA) != 0
12146 && address_mode == mode_64bit))
12147 OP_REG (bytemode, sizeflag);
12149 strcpy (obuf, "nop");
12153 NOP_Fixup2 (int bytemode, int sizeflag)
12155 if ((prefixes & PREFIX_DATA) != 0
12158 && address_mode == mode_64bit))
12159 OP_IMREG (bytemode, sizeflag);
12162 static const char *const Suffix3DNow[] = {
12163 /* 00 */ NULL, NULL, NULL, NULL,
12164 /* 04 */ NULL, NULL, NULL, NULL,
12165 /* 08 */ NULL, NULL, NULL, NULL,
12166 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
12167 /* 10 */ NULL, NULL, NULL, NULL,
12168 /* 14 */ NULL, NULL, NULL, NULL,
12169 /* 18 */ NULL, NULL, NULL, NULL,
12170 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
12171 /* 20 */ NULL, NULL, NULL, NULL,
12172 /* 24 */ NULL, NULL, NULL, NULL,
12173 /* 28 */ NULL, NULL, NULL, NULL,
12174 /* 2C */ NULL, NULL, NULL, NULL,
12175 /* 30 */ NULL, NULL, NULL, NULL,
12176 /* 34 */ NULL, NULL, NULL, NULL,
12177 /* 38 */ NULL, NULL, NULL, NULL,
12178 /* 3C */ NULL, NULL, NULL, NULL,
12179 /* 40 */ NULL, NULL, NULL, NULL,
12180 /* 44 */ NULL, NULL, NULL, NULL,
12181 /* 48 */ NULL, NULL, NULL, NULL,
12182 /* 4C */ NULL, NULL, NULL, NULL,
12183 /* 50 */ NULL, NULL, NULL, NULL,
12184 /* 54 */ NULL, NULL, NULL, NULL,
12185 /* 58 */ NULL, NULL, NULL, NULL,
12186 /* 5C */ NULL, NULL, NULL, NULL,
12187 /* 60 */ NULL, NULL, NULL, NULL,
12188 /* 64 */ NULL, NULL, NULL, NULL,
12189 /* 68 */ NULL, NULL, NULL, NULL,
12190 /* 6C */ NULL, NULL, NULL, NULL,
12191 /* 70 */ NULL, NULL, NULL, NULL,
12192 /* 74 */ NULL, NULL, NULL, NULL,
12193 /* 78 */ NULL, NULL, NULL, NULL,
12194 /* 7C */ NULL, NULL, NULL, NULL,
12195 /* 80 */ NULL, NULL, NULL, NULL,
12196 /* 84 */ NULL, NULL, NULL, NULL,
12197 /* 88 */ NULL, NULL, "pfnacc", NULL,
12198 /* 8C */ NULL, NULL, "pfpnacc", NULL,
12199 /* 90 */ "pfcmpge", NULL, NULL, NULL,
12200 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
12201 /* 98 */ NULL, NULL, "pfsub", NULL,
12202 /* 9C */ NULL, NULL, "pfadd", NULL,
12203 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
12204 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
12205 /* A8 */ NULL, NULL, "pfsubr", NULL,
12206 /* AC */ NULL, NULL, "pfacc", NULL,
12207 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
12208 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
12209 /* B8 */ NULL, NULL, NULL, "pswapd",
12210 /* BC */ NULL, NULL, NULL, "pavgusb",
12211 /* C0 */ NULL, NULL, NULL, NULL,
12212 /* C4 */ NULL, NULL, NULL, NULL,
12213 /* C8 */ NULL, NULL, NULL, NULL,
12214 /* CC */ NULL, NULL, NULL, NULL,
12215 /* D0 */ NULL, NULL, NULL, NULL,
12216 /* D4 */ NULL, NULL, NULL, NULL,
12217 /* D8 */ NULL, NULL, NULL, NULL,
12218 /* DC */ NULL, NULL, NULL, NULL,
12219 /* E0 */ NULL, NULL, NULL, NULL,
12220 /* E4 */ NULL, NULL, NULL, NULL,
12221 /* E8 */ NULL, NULL, NULL, NULL,
12222 /* EC */ NULL, NULL, NULL, NULL,
12223 /* F0 */ NULL, NULL, NULL, NULL,
12224 /* F4 */ NULL, NULL, NULL, NULL,
12225 /* F8 */ NULL, NULL, NULL, NULL,
12226 /* FC */ NULL, NULL, NULL, NULL,
12230 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12232 const char *mnemonic;
12234 FETCH_DATA (the_info, codep + 1);
12235 /* AMD 3DNow! instructions are specified by an opcode suffix in the
12236 place where an 8-bit immediate would normally go. ie. the last
12237 byte of the instruction. */
12238 obufp = mnemonicendp;
12239 mnemonic = Suffix3DNow[*codep++ & 0xff];
12241 oappend (mnemonic);
12244 /* Since a variable sized modrm/sib chunk is between the start
12245 of the opcode (0x0f0f) and the opcode suffix, we need to do
12246 all the modrm processing first, and don't know until now that
12247 we have a bad opcode. This necessitates some cleaning up. */
12248 op_out[0][0] = '\0';
12249 op_out[1][0] = '\0';
12252 mnemonicendp = obufp;
12255 static struct op simd_cmp_op[] =
12257 { STRING_COMMA_LEN ("eq") },
12258 { STRING_COMMA_LEN ("lt") },
12259 { STRING_COMMA_LEN ("le") },
12260 { STRING_COMMA_LEN ("unord") },
12261 { STRING_COMMA_LEN ("neq") },
12262 { STRING_COMMA_LEN ("nlt") },
12263 { STRING_COMMA_LEN ("nle") },
12264 { STRING_COMMA_LEN ("ord") }
12268 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12270 unsigned int cmp_type;
12272 FETCH_DATA (the_info, codep + 1);
12273 cmp_type = *codep++ & 0xff;
12274 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
12277 char *p = mnemonicendp - 2;
12281 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
12282 mnemonicendp += simd_cmp_op[cmp_type].len;
12286 /* We have a reserved extension byte. Output it directly. */
12287 scratchbuf[0] = '$';
12288 print_operand_value (scratchbuf + 1, 1, cmp_type);
12289 oappend (scratchbuf + intel_syntax);
12290 scratchbuf[0] = '\0';
12295 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
12296 int sizeflag ATTRIBUTE_UNUSED)
12298 /* mwait %eax,%ecx */
12301 const char **names = (address_mode == mode_64bit
12302 ? names64 : names32);
12303 strcpy (op_out[0], names[0]);
12304 strcpy (op_out[1], names[1]);
12305 two_source_ops = 1;
12307 /* Skip mod/rm byte. */
12313 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
12314 int sizeflag ATTRIBUTE_UNUSED)
12316 /* monitor %eax,%ecx,%edx" */
12319 const char **op1_names;
12320 const char **names = (address_mode == mode_64bit
12321 ? names64 : names32);
12323 if (!(prefixes & PREFIX_ADDR))
12324 op1_names = (address_mode == mode_16bit
12325 ? names16 : names);
12328 /* Remove "addr16/addr32". */
12329 addr_prefix = NULL;
12330 op1_names = (address_mode != mode_32bit
12331 ? names32 : names16);
12332 used_prefixes |= PREFIX_ADDR;
12334 strcpy (op_out[0], op1_names[0]);
12335 strcpy (op_out[1], names[1]);
12336 strcpy (op_out[2], names[2]);
12337 two_source_ops = 1;
12339 /* Skip mod/rm byte. */
12347 /* Throw away prefixes and 1st. opcode byte. */
12348 codep = insn_codep + 1;
12353 REP_Fixup (int bytemode, int sizeflag)
12355 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
12357 if (prefixes & PREFIX_REPZ)
12358 repz_prefix = "rep ";
12365 OP_IMREG (bytemode, sizeflag);
12368 OP_ESreg (bytemode, sizeflag);
12371 OP_DSreg (bytemode, sizeflag);
12380 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
12385 /* Change cmpxchg8b to cmpxchg16b. */
12386 char *p = mnemonicendp - 2;
12387 mnemonicendp = stpcpy (p, "16b");
12390 OP_M (bytemode, sizeflag);
12394 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
12398 switch (vex.length)
12401 sprintf (scratchbuf, "%%xmm%d", reg);
12404 sprintf (scratchbuf, "%%ymm%d", reg);
12411 sprintf (scratchbuf, "%%xmm%d", reg);
12412 oappend (scratchbuf + intel_syntax);
12416 CRC32_Fixup (int bytemode, int sizeflag)
12418 /* Add proper suffix to "crc32". */
12419 char *p = mnemonicendp;
12436 else if (sizeflag & DFLAG)
12440 used_prefixes |= (prefixes & PREFIX_DATA);
12443 oappend (INTERNAL_DISASSEMBLER_ERROR);
12450 if (modrm.mod == 3)
12454 /* Skip mod/rm byte. */
12459 add = (rex & REX_B) ? 8 : 0;
12460 if (bytemode == b_mode)
12464 oappend (names8rex[modrm.rm + add]);
12466 oappend (names8[modrm.rm + add]);
12472 oappend (names64[modrm.rm + add]);
12473 else if ((prefixes & PREFIX_DATA))
12474 oappend (names16[modrm.rm + add]);
12476 oappend (names32[modrm.rm + add]);
12480 OP_E (bytemode, sizeflag);
12483 /* Display the destination register operand for instructions with
12487 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12495 switch (vex.length)
12508 sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
12521 sprintf (scratchbuf, "%%ymm%d", vex.register_specifier);
12527 oappend (scratchbuf + intel_syntax);
12530 /* Get the VEX immediate byte without moving codep. */
12532 static unsigned char
12533 get_vex_imm8 (int sizeflag)
12535 int bytes_before_imm = 0;
12537 /* Skip mod/rm byte. */
12541 if (modrm.mod != 3)
12543 /* There are SIB/displacement bytes. */
12544 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12546 /* 32/64 bit address mode */
12547 int base = modrm.rm;
12549 /* Check SIB byte. */
12552 FETCH_DATA (the_info, codep + 1);
12554 bytes_before_imm++;
12560 /* When modrm.rm == 5 or modrm.rm == 4 and base in
12561 SIB == 5, there is a 4 byte displacement. */
12563 /* No displacement. */
12566 /* 4 byte displacement. */
12567 bytes_before_imm += 4;
12570 /* 1 byte displacement. */
12571 bytes_before_imm++;
12576 { /* 16 bit address mode */
12580 /* When modrm.rm == 6, there is a 2 byte displacement. */
12582 /* No displacement. */
12585 /* 2 byte displacement. */
12586 bytes_before_imm += 2;
12589 /* 1 byte displacement. */
12590 bytes_before_imm++;
12596 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
12597 return codep [bytes_before_imm];
12601 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
12603 if (reg == -1 && modrm.mod != 3)
12605 OP_E_memory (bytemode, sizeflag);
12617 else if (reg > 7 && address_mode != mode_64bit)
12621 switch (vex.length)
12624 sprintf (scratchbuf, "%%xmm%d", reg);
12627 sprintf (scratchbuf, "%%ymm%d", reg);
12632 oappend (scratchbuf + intel_syntax);
12636 OP_EX_VexW (int bytemode, int sizeflag)
12644 reg = vex.register_specifier;
12649 reg = vex.register_specifier;
12652 OP_EX_VexReg (bytemode, sizeflag, reg);
12656 OP_VEX_FMA (int bytemode, int sizeflag)
12658 int reg = get_vex_imm8 (sizeflag) >> 4;
12660 if (reg > 7 && address_mode != mode_64bit)
12663 switch (vex.length)
12676 sprintf (scratchbuf, "%%xmm%d", reg);
12688 sprintf (scratchbuf, "%%ymm%d", reg);
12693 oappend (scratchbuf + intel_syntax);
12697 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
12698 int sizeflag ATTRIBUTE_UNUSED)
12700 /* Skip the immediate byte and check for invalid bits. */
12701 FETCH_DATA (the_info, codep + 1);
12702 if (*codep++ & 0xf)
12707 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12710 FETCH_DATA (the_info, codep + 1);
12713 if (bytemode != x_mode)
12720 if (reg > 7 && address_mode != mode_64bit)
12723 switch (vex.length)
12726 sprintf (scratchbuf, "%%xmm%d", reg);
12729 sprintf (scratchbuf, "%%ymm%d", reg);
12734 oappend (scratchbuf + intel_syntax);
12738 OP_XMM_VexW (int bytemode, int sizeflag)
12740 /* Turn off the REX.W bit since it is used for swapping operands
12743 OP_XMM (bytemode, sizeflag);
12747 OP_EX_Vex (int bytemode, int sizeflag)
12749 if (modrm.mod != 3)
12751 if (vex.register_specifier != 0)
12755 OP_EX (bytemode, sizeflag);
12759 OP_XMM_Vex (int bytemode, int sizeflag)
12761 if (modrm.mod != 3)
12763 if (vex.register_specifier != 0)
12767 OP_XMM (bytemode, sizeflag);
12771 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12773 switch (vex.length)
12776 mnemonicendp = stpcpy (obuf, "vzeroupper");
12779 mnemonicendp = stpcpy (obuf, "vzeroall");
12786 static struct op vex_cmp_op[] =
12788 { STRING_COMMA_LEN ("eq") },
12789 { STRING_COMMA_LEN ("lt") },
12790 { STRING_COMMA_LEN ("le") },
12791 { STRING_COMMA_LEN ("unord") },
12792 { STRING_COMMA_LEN ("neq") },
12793 { STRING_COMMA_LEN ("nlt") },
12794 { STRING_COMMA_LEN ("nle") },
12795 { STRING_COMMA_LEN ("ord") },
12796 { STRING_COMMA_LEN ("eq_uq") },
12797 { STRING_COMMA_LEN ("nge") },
12798 { STRING_COMMA_LEN ("ngt") },
12799 { STRING_COMMA_LEN ("false") },
12800 { STRING_COMMA_LEN ("neq_oq") },
12801 { STRING_COMMA_LEN ("ge") },
12802 { STRING_COMMA_LEN ("gt") },
12803 { STRING_COMMA_LEN ("true") },
12804 { STRING_COMMA_LEN ("eq_os") },
12805 { STRING_COMMA_LEN ("lt_oq") },
12806 { STRING_COMMA_LEN ("le_oq") },
12807 { STRING_COMMA_LEN ("unord_s") },
12808 { STRING_COMMA_LEN ("neq_us") },
12809 { STRING_COMMA_LEN ("nlt_uq") },
12810 { STRING_COMMA_LEN ("nle_uq") },
12811 { STRING_COMMA_LEN ("ord_s") },
12812 { STRING_COMMA_LEN ("eq_us") },
12813 { STRING_COMMA_LEN ("nge_uq") },
12814 { STRING_COMMA_LEN ("ngt_uq") },
12815 { STRING_COMMA_LEN ("false_os") },
12816 { STRING_COMMA_LEN ("neq_os") },
12817 { STRING_COMMA_LEN ("ge_oq") },
12818 { STRING_COMMA_LEN ("gt_oq") },
12819 { STRING_COMMA_LEN ("true_us") },
12823 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12825 unsigned int cmp_type;
12827 FETCH_DATA (the_info, codep + 1);
12828 cmp_type = *codep++ & 0xff;
12829 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
12832 char *p = mnemonicendp - 2;
12836 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
12837 mnemonicendp += vex_cmp_op[cmp_type].len;
12841 /* We have a reserved extension byte. Output it directly. */
12842 scratchbuf[0] = '$';
12843 print_operand_value (scratchbuf + 1, 1, cmp_type);
12844 oappend (scratchbuf + intel_syntax);
12845 scratchbuf[0] = '\0';
12849 static const struct op pclmul_op[] =
12851 { STRING_COMMA_LEN ("lql") },
12852 { STRING_COMMA_LEN ("hql") },
12853 { STRING_COMMA_LEN ("lqh") },
12854 { STRING_COMMA_LEN ("hqh") }
12858 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
12859 int sizeflag ATTRIBUTE_UNUSED)
12861 unsigned int pclmul_type;
12863 FETCH_DATA (the_info, codep + 1);
12864 pclmul_type = *codep++ & 0xff;
12865 switch (pclmul_type)
12876 if (pclmul_type < ARRAY_SIZE (pclmul_op))
12879 char *p = mnemonicendp - 3;
12884 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
12885 mnemonicendp += pclmul_op[pclmul_type].len;
12889 /* We have a reserved extension byte. Output it directly. */
12890 scratchbuf[0] = '$';
12891 print_operand_value (scratchbuf + 1, 1, pclmul_type);
12892 oappend (scratchbuf + intel_syntax);
12893 scratchbuf[0] = '\0';
12898 MOVBE_Fixup (int bytemode, int sizeflag)
12900 /* Add proper suffix to "movbe". */
12901 char *p = mnemonicendp;
12910 if (sizeflag & SUFFIX_ALWAYS)
12914 else if (sizeflag & DFLAG)
12919 used_prefixes |= (prefixes & PREFIX_DATA);
12922 oappend (INTERNAL_DISASSEMBLER_ERROR);
12929 OP_M (bytemode, sizeflag);