1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2015 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma, disassemble_info *);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma get64 (void);
58 static bfd_signed_vma get32 (void);
59 static bfd_signed_vma get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void HLE_Fixup1 (int, int);
113 static void HLE_Fixup2 (int, int);
114 static void HLE_Fixup3 (int, int);
115 static void CMPXCHG8B_Fixup (int, int);
116 static void XMM_Fixup (int, int);
117 static void CRC32_Fixup (int, int);
118 static void FXSAVE_Fixup (int, int);
119 static void OP_LWPCB_E (int, int);
120 static void OP_LWP_E (int, int);
121 static void OP_Vex_2src_1 (int, int);
122 static void OP_Vex_2src_2 (int, int);
124 static void MOVBE_Fixup (int, int);
126 static void OP_Mask (int, int);
129 /* Points to first byte not fetched. */
130 bfd_byte *max_fetched;
131 bfd_byte the_buffer[MAX_MNEM_SIZE];
134 OPCODES_SIGJMP_BUF bailout;
144 enum address_mode address_mode;
146 /* Flags for the prefixes for the current instruction. See below. */
149 /* REX prefix the current instruction. See below. */
151 /* Bits of REX we've already used. */
153 /* REX bits in original REX prefix ignored. */
154 static int rex_ignored;
155 /* Mark parts used in the REX prefix. When we are testing for
156 empty prefix (for 8bit register REX extension), just mask it
157 out. Otherwise test for REX bit is excuse for existence of REX
158 only in case value is nonzero. */
159 #define USED_REX(value) \
164 rex_used |= (value) | REX_OPCODE; \
167 rex_used |= REX_OPCODE; \
170 /* Flags for prefixes which we somehow handled when printing the
171 current instruction. */
172 static int used_prefixes;
174 /* Flags stored in PREFIXES. */
175 #define PREFIX_REPZ 1
176 #define PREFIX_REPNZ 2
177 #define PREFIX_LOCK 4
179 #define PREFIX_SS 0x10
180 #define PREFIX_DS 0x20
181 #define PREFIX_ES 0x40
182 #define PREFIX_FS 0x80
183 #define PREFIX_GS 0x100
184 #define PREFIX_DATA 0x200
185 #define PREFIX_ADDR 0x400
186 #define PREFIX_FWAIT 0x800
188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
189 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
191 #define FETCH_DATA(info, addr) \
192 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
193 ? 1 : fetch_data ((info), (addr)))
196 fetch_data (struct disassemble_info *info, bfd_byte *addr)
199 struct dis_private *priv = (struct dis_private *) info->private_data;
200 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
202 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
203 status = (*info->read_memory_func) (start,
205 addr - priv->max_fetched,
211 /* If we did manage to read at least one byte, then
212 print_insn_i386 will do something sensible. Otherwise, print
213 an error. We do that here because this is where we know
215 if (priv->max_fetched == priv->the_buffer)
216 (*info->memory_error_func) (status, start, info);
217 OPCODES_SIGLONGJMP (priv->bailout, 1);
220 priv->max_fetched = addr;
224 /* Possible values for prefix requirement. */
225 #define PREFIX_UD_SHIFT 8
226 #define PREFIX_UD_REPZ (PREFIX_REPZ << PREFIX_UD_SHIFT)
227 #define PREFIX_UD_REPNZ (PREFIX_REPNZ << PREFIX_UD_SHIFT)
228 #define PREFIX_UD_DATA (PREFIX_DATA << PREFIX_UD_SHIFT)
229 #define PREFIX_UD_ADDR (PREFIX_ADDR << PREFIX_UD_SHIFT)
230 #define PREFIX_UD_LOCK (PREFIX_LOCK << PREFIX_UD_SHIFT)
231 #define PREFIX_IGNORED_SHIFT 16
232 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
233 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
234 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
235 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
236 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
238 /* Opcode prefixes. */
239 #define PREFIX_OPCODE (PREFIX_REPZ \
243 /* Prefixes ignored. */
244 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
245 | PREFIX_IGNORED_REPNZ \
246 | PREFIX_IGNORED_DATA)
248 #define XX { NULL, 0 }
249 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
251 #define Eb { OP_E, b_mode }
252 #define Ebnd { OP_E, bnd_mode }
253 #define EbS { OP_E, b_swap_mode }
254 #define Ev { OP_E, v_mode }
255 #define Ev_bnd { OP_E, v_bnd_mode }
256 #define EvS { OP_E, v_swap_mode }
257 #define Ed { OP_E, d_mode }
258 #define Edq { OP_E, dq_mode }
259 #define Edqw { OP_E, dqw_mode }
260 #define EdqwS { OP_E, dqw_swap_mode }
261 #define Edqb { OP_E, dqb_mode }
262 #define Edb { OP_E, db_mode }
263 #define Edw { OP_E, dw_mode }
264 #define Edqd { OP_E, dqd_mode }
265 #define Eq { OP_E, q_mode }
266 #define indirEv { OP_indirE, stack_v_mode }
267 #define indirEp { OP_indirE, f_mode }
268 #define stackEv { OP_E, stack_v_mode }
269 #define Em { OP_E, m_mode }
270 #define Ew { OP_E, w_mode }
271 #define M { OP_M, 0 } /* lea, lgdt, etc. */
272 #define Ma { OP_M, a_mode }
273 #define Mb { OP_M, b_mode }
274 #define Md { OP_M, d_mode }
275 #define Mo { OP_M, o_mode }
276 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
277 #define Mq { OP_M, q_mode }
278 #define Mx { OP_M, x_mode }
279 #define Mxmm { OP_M, xmm_mode }
280 #define Gb { OP_G, b_mode }
281 #define Gbnd { OP_G, bnd_mode }
282 #define Gv { OP_G, v_mode }
283 #define Gd { OP_G, d_mode }
284 #define Gdq { OP_G, dq_mode }
285 #define Gm { OP_G, m_mode }
286 #define Gw { OP_G, w_mode }
287 #define Rd { OP_R, d_mode }
288 #define Rdq { OP_R, dq_mode }
289 #define Rm { OP_R, m_mode }
290 #define Ib { OP_I, b_mode }
291 #define sIb { OP_sI, b_mode } /* sign extened byte */
292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
293 #define Iv { OP_I, v_mode }
294 #define sIv { OP_sI, v_mode }
295 #define Iq { OP_I, q_mode }
296 #define Iv64 { OP_I64, v_mode }
297 #define Iw { OP_I, w_mode }
298 #define I1 { OP_I, const_1_mode }
299 #define Jb { OP_J, b_mode }
300 #define Jv { OP_J, v_mode }
301 #define Cm { OP_C, m_mode }
302 #define Dm { OP_D, m_mode }
303 #define Td { OP_T, d_mode }
304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
306 #define RMeAX { OP_REG, eAX_reg }
307 #define RMeBX { OP_REG, eBX_reg }
308 #define RMeCX { OP_REG, eCX_reg }
309 #define RMeDX { OP_REG, eDX_reg }
310 #define RMeSP { OP_REG, eSP_reg }
311 #define RMeBP { OP_REG, eBP_reg }
312 #define RMeSI { OP_REG, eSI_reg }
313 #define RMeDI { OP_REG, eDI_reg }
314 #define RMrAX { OP_REG, rAX_reg }
315 #define RMrBX { OP_REG, rBX_reg }
316 #define RMrCX { OP_REG, rCX_reg }
317 #define RMrDX { OP_REG, rDX_reg }
318 #define RMrSP { OP_REG, rSP_reg }
319 #define RMrBP { OP_REG, rBP_reg }
320 #define RMrSI { OP_REG, rSI_reg }
321 #define RMrDI { OP_REG, rDI_reg }
322 #define RMAL { OP_REG, al_reg }
323 #define RMCL { OP_REG, cl_reg }
324 #define RMDL { OP_REG, dl_reg }
325 #define RMBL { OP_REG, bl_reg }
326 #define RMAH { OP_REG, ah_reg }
327 #define RMCH { OP_REG, ch_reg }
328 #define RMDH { OP_REG, dh_reg }
329 #define RMBH { OP_REG, bh_reg }
330 #define RMAX { OP_REG, ax_reg }
331 #define RMDX { OP_REG, dx_reg }
333 #define eAX { OP_IMREG, eAX_reg }
334 #define eBX { OP_IMREG, eBX_reg }
335 #define eCX { OP_IMREG, eCX_reg }
336 #define eDX { OP_IMREG, eDX_reg }
337 #define eSP { OP_IMREG, eSP_reg }
338 #define eBP { OP_IMREG, eBP_reg }
339 #define eSI { OP_IMREG, eSI_reg }
340 #define eDI { OP_IMREG, eDI_reg }
341 #define AL { OP_IMREG, al_reg }
342 #define CL { OP_IMREG, cl_reg }
343 #define DL { OP_IMREG, dl_reg }
344 #define BL { OP_IMREG, bl_reg }
345 #define AH { OP_IMREG, ah_reg }
346 #define CH { OP_IMREG, ch_reg }
347 #define DH { OP_IMREG, dh_reg }
348 #define BH { OP_IMREG, bh_reg }
349 #define AX { OP_IMREG, ax_reg }
350 #define DX { OP_IMREG, dx_reg }
351 #define zAX { OP_IMREG, z_mode_ax_reg }
352 #define indirDX { OP_IMREG, indir_dx_reg }
354 #define Sw { OP_SEG, w_mode }
355 #define Sv { OP_SEG, v_mode }
356 #define Ap { OP_DIR, 0 }
357 #define Ob { OP_OFF64, b_mode }
358 #define Ov { OP_OFF64, v_mode }
359 #define Xb { OP_DSreg, eSI_reg }
360 #define Xv { OP_DSreg, eSI_reg }
361 #define Xz { OP_DSreg, eSI_reg }
362 #define Yb { OP_ESreg, eDI_reg }
363 #define Yv { OP_ESreg, eDI_reg }
364 #define DSBX { OP_DSreg, eBX_reg }
366 #define es { OP_REG, es_reg }
367 #define ss { OP_REG, ss_reg }
368 #define cs { OP_REG, cs_reg }
369 #define ds { OP_REG, ds_reg }
370 #define fs { OP_REG, fs_reg }
371 #define gs { OP_REG, gs_reg }
373 #define MX { OP_MMX, 0 }
374 #define XM { OP_XMM, 0 }
375 #define XMScalar { OP_XMM, scalar_mode }
376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
377 #define XMM { OP_XMM, xmm_mode }
378 #define XMxmmq { OP_XMM, xmmq_mode }
379 #define EM { OP_EM, v_mode }
380 #define EMS { OP_EM, v_swap_mode }
381 #define EMd { OP_EM, d_mode }
382 #define EMx { OP_EM, x_mode }
383 #define EXw { OP_EX, w_mode }
384 #define EXd { OP_EX, d_mode }
385 #define EXdScalar { OP_EX, d_scalar_mode }
386 #define EXdS { OP_EX, d_swap_mode }
387 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
388 #define EXq { OP_EX, q_mode }
389 #define EXqScalar { OP_EX, q_scalar_mode }
390 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
391 #define EXqS { OP_EX, q_swap_mode }
392 #define EXx { OP_EX, x_mode }
393 #define EXxS { OP_EX, x_swap_mode }
394 #define EXxmm { OP_EX, xmm_mode }
395 #define EXymm { OP_EX, ymm_mode }
396 #define EXxmmq { OP_EX, xmmq_mode }
397 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
398 #define EXxmm_mb { OP_EX, xmm_mb_mode }
399 #define EXxmm_mw { OP_EX, xmm_mw_mode }
400 #define EXxmm_md { OP_EX, xmm_md_mode }
401 #define EXxmm_mq { OP_EX, xmm_mq_mode }
402 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
403 #define EXxmmdw { OP_EX, xmmdw_mode }
404 #define EXxmmqd { OP_EX, xmmqd_mode }
405 #define EXymmq { OP_EX, ymmq_mode }
406 #define EXVexWdq { OP_EX, vex_w_dq_mode }
407 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
408 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
409 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
410 #define MS { OP_MS, v_mode }
411 #define XS { OP_XS, v_mode }
412 #define EMCq { OP_EMC, q_mode }
413 #define MXC { OP_MXC, 0 }
414 #define OPSUF { OP_3DNowSuffix, 0 }
415 #define CMP { CMP_Fixup, 0 }
416 #define XMM0 { XMM_Fixup, 0 }
417 #define FXSAVE { FXSAVE_Fixup, 0 }
418 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
419 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
421 #define Vex { OP_VEX, vex_mode }
422 #define VexScalar { OP_VEX, vex_scalar_mode }
423 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
424 #define Vex128 { OP_VEX, vex128_mode }
425 #define Vex256 { OP_VEX, vex256_mode }
426 #define VexGdq { OP_VEX, dq_mode }
427 #define VexI4 { VEXI4_Fixup, 0}
428 #define EXdVex { OP_EX_Vex, d_mode }
429 #define EXdVexS { OP_EX_Vex, d_swap_mode }
430 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
431 #define EXqVex { OP_EX_Vex, q_mode }
432 #define EXqVexS { OP_EX_Vex, q_swap_mode }
433 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
434 #define EXVexW { OP_EX_VexW, x_mode }
435 #define EXdVexW { OP_EX_VexW, d_mode }
436 #define EXqVexW { OP_EX_VexW, q_mode }
437 #define EXVexImmW { OP_EX_VexImmW, x_mode }
438 #define XMVex { OP_XMM_Vex, 0 }
439 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
440 #define XMVexW { OP_XMM_VexW, 0 }
441 #define XMVexI4 { OP_REG_VexI4, x_mode }
442 #define PCLMUL { PCLMUL_Fixup, 0 }
443 #define VZERO { VZERO_Fixup, 0 }
444 #define VCMP { VCMP_Fixup, 0 }
445 #define VPCMP { VPCMP_Fixup, 0 }
447 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
448 #define EXxEVexS { OP_Rounding, evex_sae_mode }
450 #define XMask { OP_Mask, mask_mode }
451 #define MaskG { OP_G, mask_mode }
452 #define MaskE { OP_E, mask_mode }
453 #define MaskBDE { OP_E, mask_bd_mode }
454 #define MaskR { OP_R, mask_mode }
455 #define MaskVex { OP_VEX, mask_mode }
457 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
458 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
459 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
460 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
462 /* Used handle "rep" prefix for string instructions. */
463 #define Xbr { REP_Fixup, eSI_reg }
464 #define Xvr { REP_Fixup, eSI_reg }
465 #define Ybr { REP_Fixup, eDI_reg }
466 #define Yvr { REP_Fixup, eDI_reg }
467 #define Yzr { REP_Fixup, eDI_reg }
468 #define indirDXr { REP_Fixup, indir_dx_reg }
469 #define ALr { REP_Fixup, al_reg }
470 #define eAXr { REP_Fixup, eAX_reg }
472 /* Used handle HLE prefix for lockable instructions. */
473 #define Ebh1 { HLE_Fixup1, b_mode }
474 #define Evh1 { HLE_Fixup1, v_mode }
475 #define Ebh2 { HLE_Fixup2, b_mode }
476 #define Evh2 { HLE_Fixup2, v_mode }
477 #define Ebh3 { HLE_Fixup3, b_mode }
478 #define Evh3 { HLE_Fixup3, v_mode }
480 #define BND { BND_Fixup, 0 }
482 #define cond_jump_flag { NULL, cond_jump_mode }
483 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
485 /* bits in sizeflag */
486 #define SUFFIX_ALWAYS 4
494 /* byte operand with operand swapped */
496 /* byte operand, sign extend like 'T' suffix */
498 /* operand size depends on prefixes */
500 /* operand size depends on prefixes with operand swapped */
504 /* double word operand */
506 /* double word operand with operand swapped */
508 /* quad word operand */
510 /* quad word operand with operand swapped */
512 /* ten-byte operand */
514 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
515 broadcast enabled. */
517 /* Similar to x_mode, but with different EVEX mem shifts. */
519 /* Similar to x_mode, but with disabled broadcast. */
521 /* Similar to x_mode, but with operands swapped and disabled broadcast
524 /* 16-byte XMM operand */
526 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
527 memory operand (depending on vector length). Broadcast isn't
530 /* Same as xmmq_mode, but broadcast is allowed. */
531 evex_half_bcst_xmmq_mode,
532 /* XMM register or byte memory operand */
534 /* XMM register or word memory operand */
536 /* XMM register or double word memory operand */
538 /* XMM register or quad word memory operand */
540 /* XMM register or double/quad word memory operand, depending on
543 /* 16-byte XMM, word, double word or quad word operand. */
545 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
547 /* 32-byte YMM operand */
549 /* quad word, ymmword or zmmword memory operand. */
551 /* 32-byte YMM or 16-byte word operand */
553 /* d_mode in 32bit, q_mode in 64bit mode. */
555 /* pair of v_mode operands */
560 /* operand size depends on REX prefixes. */
562 /* registers like dq_mode, memory like w_mode. */
566 /* 4- or 6-byte pointer operand */
569 /* v_mode for stack-related opcodes. */
571 /* non-quad operand size depends on prefixes */
573 /* 16-byte operand */
575 /* registers like dq_mode, memory like b_mode. */
577 /* registers like d_mode, memory like b_mode. */
579 /* registers like d_mode, memory like w_mode. */
581 /* registers like dq_mode, memory like d_mode. */
583 /* normal vex mode */
585 /* 128bit vex mode */
587 /* 256bit vex mode */
589 /* operand size depends on the VEX.W bit. */
592 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
593 vex_vsib_d_w_dq_mode,
594 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
596 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
597 vex_vsib_q_w_dq_mode,
598 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
601 /* scalar, ignore vector length. */
603 /* like d_mode, ignore vector length. */
605 /* like d_swap_mode, ignore vector length. */
607 /* like q_mode, ignore vector length. */
609 /* like q_swap_mode, ignore vector length. */
611 /* like vex_mode, ignore vector length. */
613 /* like vex_w_dq_mode, ignore vector length. */
614 vex_scalar_w_dq_mode,
616 /* Static rounding. */
618 /* Supress all exceptions. */
621 /* Mask register operand. */
623 /* Mask register operand. */
690 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
692 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
693 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
694 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
695 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
696 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
697 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
698 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
699 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
700 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
701 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
702 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
703 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
704 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
705 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
706 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
822 MOD_VEX_0F12_PREFIX_0,
824 MOD_VEX_0F16_PREFIX_0,
840 MOD_VEX_0FD7_PREFIX_2,
841 MOD_VEX_0FE7_PREFIX_2,
842 MOD_VEX_0FF0_PREFIX_3,
843 MOD_VEX_0F381A_PREFIX_2,
844 MOD_VEX_0F382A_PREFIX_2,
845 MOD_VEX_0F382C_PREFIX_2,
846 MOD_VEX_0F382D_PREFIX_2,
847 MOD_VEX_0F382E_PREFIX_2,
848 MOD_VEX_0F382F_PREFIX_2,
849 MOD_VEX_0F385A_PREFIX_2,
850 MOD_VEX_0F388C_PREFIX_2,
851 MOD_VEX_0F388E_PREFIX_2,
853 MOD_EVEX_0F10_PREFIX_1,
854 MOD_EVEX_0F10_PREFIX_3,
855 MOD_EVEX_0F11_PREFIX_1,
856 MOD_EVEX_0F11_PREFIX_3,
857 MOD_EVEX_0F12_PREFIX_0,
858 MOD_EVEX_0F16_PREFIX_0,
859 MOD_EVEX_0F38C6_REG_1,
860 MOD_EVEX_0F38C6_REG_2,
861 MOD_EVEX_0F38C6_REG_5,
862 MOD_EVEX_0F38C6_REG_6,
863 MOD_EVEX_0F38C7_REG_1,
864 MOD_EVEX_0F38C7_REG_2,
865 MOD_EVEX_0F38C7_REG_5,
866 MOD_EVEX_0F38C7_REG_6
930 PREFIX_RM_0_0FAE_REG_7,
1060 PREFIX_VEX_0F71_REG_2,
1061 PREFIX_VEX_0F71_REG_4,
1062 PREFIX_VEX_0F71_REG_6,
1063 PREFIX_VEX_0F72_REG_2,
1064 PREFIX_VEX_0F72_REG_4,
1065 PREFIX_VEX_0F72_REG_6,
1066 PREFIX_VEX_0F73_REG_2,
1067 PREFIX_VEX_0F73_REG_3,
1068 PREFIX_VEX_0F73_REG_6,
1069 PREFIX_VEX_0F73_REG_7,
1241 PREFIX_VEX_0F38F3_REG_1,
1242 PREFIX_VEX_0F38F3_REG_2,
1243 PREFIX_VEX_0F38F3_REG_3,
1360 PREFIX_EVEX_0F71_REG_2,
1361 PREFIX_EVEX_0F71_REG_4,
1362 PREFIX_EVEX_0F71_REG_6,
1363 PREFIX_EVEX_0F72_REG_0,
1364 PREFIX_EVEX_0F72_REG_1,
1365 PREFIX_EVEX_0F72_REG_2,
1366 PREFIX_EVEX_0F72_REG_4,
1367 PREFIX_EVEX_0F72_REG_6,
1368 PREFIX_EVEX_0F73_REG_2,
1369 PREFIX_EVEX_0F73_REG_3,
1370 PREFIX_EVEX_0F73_REG_6,
1371 PREFIX_EVEX_0F73_REG_7,
1554 PREFIX_EVEX_0F38C6_REG_1,
1555 PREFIX_EVEX_0F38C6_REG_2,
1556 PREFIX_EVEX_0F38C6_REG_5,
1557 PREFIX_EVEX_0F38C6_REG_6,
1558 PREFIX_EVEX_0F38C7_REG_1,
1559 PREFIX_EVEX_0F38C7_REG_2,
1560 PREFIX_EVEX_0F38C7_REG_5,
1561 PREFIX_EVEX_0F38C7_REG_6,
1648 THREE_BYTE_0F38 = 0,
1676 VEX_LEN_0F10_P_1 = 0,
1680 VEX_LEN_0F12_P_0_M_0,
1681 VEX_LEN_0F12_P_0_M_1,
1684 VEX_LEN_0F16_P_0_M_0,
1685 VEX_LEN_0F16_P_0_M_1,
1749 VEX_LEN_0FAE_R_2_M_0,
1750 VEX_LEN_0FAE_R_3_M_0,
1759 VEX_LEN_0F381A_P_2_M_0,
1762 VEX_LEN_0F385A_P_2_M_0,
1769 VEX_LEN_0F38F3_R_1_P_0,
1770 VEX_LEN_0F38F3_R_2_P_0,
1771 VEX_LEN_0F38F3_R_3_P_0,
1817 VEX_LEN_0FXOP_08_CC,
1818 VEX_LEN_0FXOP_08_CD,
1819 VEX_LEN_0FXOP_08_CE,
1820 VEX_LEN_0FXOP_08_CF,
1821 VEX_LEN_0FXOP_08_EC,
1822 VEX_LEN_0FXOP_08_ED,
1823 VEX_LEN_0FXOP_08_EE,
1824 VEX_LEN_0FXOP_08_EF,
1825 VEX_LEN_0FXOP_09_80,
1859 VEX_W_0F41_P_0_LEN_1,
1860 VEX_W_0F41_P_2_LEN_1,
1861 VEX_W_0F42_P_0_LEN_1,
1862 VEX_W_0F42_P_2_LEN_1,
1863 VEX_W_0F44_P_0_LEN_0,
1864 VEX_W_0F44_P_2_LEN_0,
1865 VEX_W_0F45_P_0_LEN_1,
1866 VEX_W_0F45_P_2_LEN_1,
1867 VEX_W_0F46_P_0_LEN_1,
1868 VEX_W_0F46_P_2_LEN_1,
1869 VEX_W_0F47_P_0_LEN_1,
1870 VEX_W_0F47_P_2_LEN_1,
1871 VEX_W_0F4A_P_0_LEN_1,
1872 VEX_W_0F4A_P_2_LEN_1,
1873 VEX_W_0F4B_P_0_LEN_1,
1874 VEX_W_0F4B_P_2_LEN_1,
1954 VEX_W_0F90_P_0_LEN_0,
1955 VEX_W_0F90_P_2_LEN_0,
1956 VEX_W_0F91_P_0_LEN_0,
1957 VEX_W_0F91_P_2_LEN_0,
1958 VEX_W_0F92_P_0_LEN_0,
1959 VEX_W_0F92_P_2_LEN_0,
1960 VEX_W_0F92_P_3_LEN_0,
1961 VEX_W_0F93_P_0_LEN_0,
1962 VEX_W_0F93_P_2_LEN_0,
1963 VEX_W_0F93_P_3_LEN_0,
1964 VEX_W_0F98_P_0_LEN_0,
1965 VEX_W_0F98_P_2_LEN_0,
1966 VEX_W_0F99_P_0_LEN_0,
1967 VEX_W_0F99_P_2_LEN_0,
2046 VEX_W_0F381A_P_2_M_0,
2058 VEX_W_0F382A_P_2_M_0,
2060 VEX_W_0F382C_P_2_M_0,
2061 VEX_W_0F382D_P_2_M_0,
2062 VEX_W_0F382E_P_2_M_0,
2063 VEX_W_0F382F_P_2_M_0,
2085 VEX_W_0F385A_P_2_M_0,
2113 VEX_W_0F3A30_P_2_LEN_0,
2114 VEX_W_0F3A31_P_2_LEN_0,
2115 VEX_W_0F3A32_P_2_LEN_0,
2116 VEX_W_0F3A33_P_2_LEN_0,
2136 EVEX_W_0F10_P_1_M_0,
2137 EVEX_W_0F10_P_1_M_1,
2139 EVEX_W_0F10_P_3_M_0,
2140 EVEX_W_0F10_P_3_M_1,
2142 EVEX_W_0F11_P_1_M_0,
2143 EVEX_W_0F11_P_1_M_1,
2145 EVEX_W_0F11_P_3_M_0,
2146 EVEX_W_0F11_P_3_M_1,
2147 EVEX_W_0F12_P_0_M_0,
2148 EVEX_W_0F12_P_0_M_1,
2158 EVEX_W_0F16_P_0_M_0,
2159 EVEX_W_0F16_P_0_M_1,
2230 EVEX_W_0F72_R_2_P_2,
2231 EVEX_W_0F72_R_6_P_2,
2232 EVEX_W_0F73_R_2_P_2,
2233 EVEX_W_0F73_R_6_P_2,
2333 EVEX_W_0F38C7_R_1_P_2,
2334 EVEX_W_0F38C7_R_2_P_2,
2335 EVEX_W_0F38C7_R_5_P_2,
2336 EVEX_W_0F38C7_R_6_P_2,
2371 typedef void (*op_rtn) (int bytemode, int sizeflag);
2380 unsigned int prefix_requirement;
2383 /* Upper case letters in the instruction names here are macros.
2384 'A' => print 'b' if no register operands or suffix_always is true
2385 'B' => print 'b' if suffix_always is true
2386 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2388 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2389 suffix_always is true
2390 'E' => print 'e' if 32-bit form of jcxz
2391 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2392 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2393 'H' => print ",pt" or ",pn" branch hint
2394 'I' => honor following macro letter even in Intel mode (implemented only
2395 for some of the macro letters)
2397 'K' => print 'd' or 'q' if rex prefix is present.
2398 'L' => print 'l' if suffix_always is true
2399 'M' => print 'r' if intel_mnemonic is false.
2400 'N' => print 'n' if instruction has no wait "prefix"
2401 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2402 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2403 or suffix_always is true. print 'q' if rex prefix is present.
2404 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2406 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2407 'S' => print 'w', 'l' or 'q' if suffix_always is true
2408 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2409 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2410 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2411 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2412 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2413 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2414 suffix_always is true.
2415 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2416 '!' => change condition from true to false or from false to true.
2417 '%' => add 1 upper case letter to the macro.
2419 2 upper case letter macros:
2420 "XY" => print 'x' or 'y' if no register operands or suffix_always
2422 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2423 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2424 or suffix_always is true
2425 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2426 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2427 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2428 "LW" => print 'd', 'q' depending on the VEX.W bit
2429 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2430 an operand size prefix, or suffix_always is true. print
2431 'q' if rex prefix is present.
2433 Many of the above letters print nothing in Intel mode. See "putop"
2436 Braces '{' and '}', and vertical bars '|', indicate alternative
2437 mnemonic strings for AT&T and Intel. */
2439 static const struct dis386 dis386[] = {
2441 { "addB", { Ebh1, Gb }, 0 },
2442 { "addS", { Evh1, Gv }, 0 },
2443 { "addB", { Gb, EbS }, 0 },
2444 { "addS", { Gv, EvS }, 0 },
2445 { "addB", { AL, Ib }, 0 },
2446 { "addS", { eAX, Iv }, 0 },
2447 { X86_64_TABLE (X86_64_06) },
2448 { X86_64_TABLE (X86_64_07) },
2450 { "orB", { Ebh1, Gb }, 0 },
2451 { "orS", { Evh1, Gv }, 0 },
2452 { "orB", { Gb, EbS }, 0 },
2453 { "orS", { Gv, EvS }, 0 },
2454 { "orB", { AL, Ib }, 0 },
2455 { "orS", { eAX, Iv }, 0 },
2456 { X86_64_TABLE (X86_64_0D) },
2457 { Bad_Opcode }, /* 0x0f extended opcode escape */
2459 { "adcB", { Ebh1, Gb }, 0 },
2460 { "adcS", { Evh1, Gv }, 0 },
2461 { "adcB", { Gb, EbS }, 0 },
2462 { "adcS", { Gv, EvS }, 0 },
2463 { "adcB", { AL, Ib }, 0 },
2464 { "adcS", { eAX, Iv }, 0 },
2465 { X86_64_TABLE (X86_64_16) },
2466 { X86_64_TABLE (X86_64_17) },
2468 { "sbbB", { Ebh1, Gb }, 0 },
2469 { "sbbS", { Evh1, Gv }, 0 },
2470 { "sbbB", { Gb, EbS }, 0 },
2471 { "sbbS", { Gv, EvS }, 0 },
2472 { "sbbB", { AL, Ib }, 0 },
2473 { "sbbS", { eAX, Iv }, 0 },
2474 { X86_64_TABLE (X86_64_1E) },
2475 { X86_64_TABLE (X86_64_1F) },
2477 { "andB", { Ebh1, Gb }, 0 },
2478 { "andS", { Evh1, Gv }, 0 },
2479 { "andB", { Gb, EbS }, 0 },
2480 { "andS", { Gv, EvS }, 0 },
2481 { "andB", { AL, Ib }, 0 },
2482 { "andS", { eAX, Iv }, 0 },
2483 { Bad_Opcode }, /* SEG ES prefix */
2484 { X86_64_TABLE (X86_64_27) },
2486 { "subB", { Ebh1, Gb }, 0 },
2487 { "subS", { Evh1, Gv }, 0 },
2488 { "subB", { Gb, EbS }, 0 },
2489 { "subS", { Gv, EvS }, 0 },
2490 { "subB", { AL, Ib }, 0 },
2491 { "subS", { eAX, Iv }, 0 },
2492 { Bad_Opcode }, /* SEG CS prefix */
2493 { X86_64_TABLE (X86_64_2F) },
2495 { "xorB", { Ebh1, Gb }, 0 },
2496 { "xorS", { Evh1, Gv }, 0 },
2497 { "xorB", { Gb, EbS }, 0 },
2498 { "xorS", { Gv, EvS }, 0 },
2499 { "xorB", { AL, Ib }, 0 },
2500 { "xorS", { eAX, Iv }, 0 },
2501 { Bad_Opcode }, /* SEG SS prefix */
2502 { X86_64_TABLE (X86_64_37) },
2504 { "cmpB", { Eb, Gb }, 0 },
2505 { "cmpS", { Ev, Gv }, 0 },
2506 { "cmpB", { Gb, EbS }, 0 },
2507 { "cmpS", { Gv, EvS }, 0 },
2508 { "cmpB", { AL, Ib }, 0 },
2509 { "cmpS", { eAX, Iv }, 0 },
2510 { Bad_Opcode }, /* SEG DS prefix */
2511 { X86_64_TABLE (X86_64_3F) },
2513 { "inc{S|}", { RMeAX }, 0 },
2514 { "inc{S|}", { RMeCX }, 0 },
2515 { "inc{S|}", { RMeDX }, 0 },
2516 { "inc{S|}", { RMeBX }, 0 },
2517 { "inc{S|}", { RMeSP }, 0 },
2518 { "inc{S|}", { RMeBP }, 0 },
2519 { "inc{S|}", { RMeSI }, 0 },
2520 { "inc{S|}", { RMeDI }, 0 },
2522 { "dec{S|}", { RMeAX }, 0 },
2523 { "dec{S|}", { RMeCX }, 0 },
2524 { "dec{S|}", { RMeDX }, 0 },
2525 { "dec{S|}", { RMeBX }, 0 },
2526 { "dec{S|}", { RMeSP }, 0 },
2527 { "dec{S|}", { RMeBP }, 0 },
2528 { "dec{S|}", { RMeSI }, 0 },
2529 { "dec{S|}", { RMeDI }, 0 },
2531 { "pushV", { RMrAX }, 0 },
2532 { "pushV", { RMrCX }, 0 },
2533 { "pushV", { RMrDX }, 0 },
2534 { "pushV", { RMrBX }, 0 },
2535 { "pushV", { RMrSP }, 0 },
2536 { "pushV", { RMrBP }, 0 },
2537 { "pushV", { RMrSI }, 0 },
2538 { "pushV", { RMrDI }, 0 },
2540 { "popV", { RMrAX }, 0 },
2541 { "popV", { RMrCX }, 0 },
2542 { "popV", { RMrDX }, 0 },
2543 { "popV", { RMrBX }, 0 },
2544 { "popV", { RMrSP }, 0 },
2545 { "popV", { RMrBP }, 0 },
2546 { "popV", { RMrSI }, 0 },
2547 { "popV", { RMrDI }, 0 },
2549 { X86_64_TABLE (X86_64_60) },
2550 { X86_64_TABLE (X86_64_61) },
2551 { X86_64_TABLE (X86_64_62) },
2552 { X86_64_TABLE (X86_64_63) },
2553 { Bad_Opcode }, /* seg fs */
2554 { Bad_Opcode }, /* seg gs */
2555 { Bad_Opcode }, /* op size prefix */
2556 { Bad_Opcode }, /* adr size prefix */
2558 { "pushT", { sIv }, 0 },
2559 { "imulS", { Gv, Ev, Iv }, 0 },
2560 { "pushT", { sIbT }, 0 },
2561 { "imulS", { Gv, Ev, sIb }, 0 },
2562 { "ins{b|}", { Ybr, indirDX }, 0 },
2563 { X86_64_TABLE (X86_64_6D) },
2564 { "outs{b|}", { indirDXr, Xb }, 0 },
2565 { X86_64_TABLE (X86_64_6F) },
2567 { "joH", { Jb, BND, cond_jump_flag }, 0 },
2568 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
2569 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
2570 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
2571 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
2572 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
2573 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
2574 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
2576 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
2577 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
2578 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
2579 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
2580 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
2581 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
2582 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
2583 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
2585 { REG_TABLE (REG_80) },
2586 { REG_TABLE (REG_81) },
2588 { REG_TABLE (REG_82) },
2589 { "testB", { Eb, Gb }, 0 },
2590 { "testS", { Ev, Gv }, 0 },
2591 { "xchgB", { Ebh2, Gb }, 0 },
2592 { "xchgS", { Evh2, Gv }, 0 },
2594 { "movB", { Ebh3, Gb }, 0 },
2595 { "movS", { Evh3, Gv }, 0 },
2596 { "movB", { Gb, EbS }, 0 },
2597 { "movS", { Gv, EvS }, 0 },
2598 { "movD", { Sv, Sw }, 0 },
2599 { MOD_TABLE (MOD_8D) },
2600 { "movD", { Sw, Sv }, 0 },
2601 { REG_TABLE (REG_8F) },
2603 { PREFIX_TABLE (PREFIX_90) },
2604 { "xchgS", { RMeCX, eAX }, 0 },
2605 { "xchgS", { RMeDX, eAX }, 0 },
2606 { "xchgS", { RMeBX, eAX }, 0 },
2607 { "xchgS", { RMeSP, eAX }, 0 },
2608 { "xchgS", { RMeBP, eAX }, 0 },
2609 { "xchgS", { RMeSI, eAX }, 0 },
2610 { "xchgS", { RMeDI, eAX }, 0 },
2612 { "cW{t|}R", { XX }, 0 },
2613 { "cR{t|}O", { XX }, 0 },
2614 { X86_64_TABLE (X86_64_9A) },
2615 { Bad_Opcode }, /* fwait */
2616 { "pushfT", { XX }, 0 },
2617 { "popfT", { XX }, 0 },
2618 { "sahf", { XX }, 0 },
2619 { "lahf", { XX }, 0 },
2621 { "mov%LB", { AL, Ob }, 0 },
2622 { "mov%LS", { eAX, Ov }, 0 },
2623 { "mov%LB", { Ob, AL }, 0 },
2624 { "mov%LS", { Ov, eAX }, 0 },
2625 { "movs{b|}", { Ybr, Xb }, 0 },
2626 { "movs{R|}", { Yvr, Xv }, 0 },
2627 { "cmps{b|}", { Xb, Yb }, 0 },
2628 { "cmps{R|}", { Xv, Yv }, 0 },
2630 { "testB", { AL, Ib }, 0 },
2631 { "testS", { eAX, Iv }, 0 },
2632 { "stosB", { Ybr, AL }, 0 },
2633 { "stosS", { Yvr, eAX }, 0 },
2634 { "lodsB", { ALr, Xb }, 0 },
2635 { "lodsS", { eAXr, Xv }, 0 },
2636 { "scasB", { AL, Yb }, 0 },
2637 { "scasS", { eAX, Yv }, 0 },
2639 { "movB", { RMAL, Ib }, 0 },
2640 { "movB", { RMCL, Ib }, 0 },
2641 { "movB", { RMDL, Ib }, 0 },
2642 { "movB", { RMBL, Ib }, 0 },
2643 { "movB", { RMAH, Ib }, 0 },
2644 { "movB", { RMCH, Ib }, 0 },
2645 { "movB", { RMDH, Ib }, 0 },
2646 { "movB", { RMBH, Ib }, 0 },
2648 { "mov%LV", { RMeAX, Iv64 }, 0 },
2649 { "mov%LV", { RMeCX, Iv64 }, 0 },
2650 { "mov%LV", { RMeDX, Iv64 }, 0 },
2651 { "mov%LV", { RMeBX, Iv64 }, 0 },
2652 { "mov%LV", { RMeSP, Iv64 }, 0 },
2653 { "mov%LV", { RMeBP, Iv64 }, 0 },
2654 { "mov%LV", { RMeSI, Iv64 }, 0 },
2655 { "mov%LV", { RMeDI, Iv64 }, 0 },
2657 { REG_TABLE (REG_C0) },
2658 { REG_TABLE (REG_C1) },
2659 { "retT", { Iw, BND }, 0 },
2660 { "retT", { BND }, 0 },
2661 { X86_64_TABLE (X86_64_C4) },
2662 { X86_64_TABLE (X86_64_C5) },
2663 { REG_TABLE (REG_C6) },
2664 { REG_TABLE (REG_C7) },
2666 { "enterT", { Iw, Ib }, 0 },
2667 { "leaveT", { XX }, 0 },
2668 { "Jret{|f}P", { Iw }, 0 },
2669 { "Jret{|f}P", { XX }, 0 },
2670 { "int3", { XX }, 0 },
2671 { "int", { Ib }, 0 },
2672 { X86_64_TABLE (X86_64_CE) },
2673 { "iret%LP", { XX }, 0 },
2675 { REG_TABLE (REG_D0) },
2676 { REG_TABLE (REG_D1) },
2677 { REG_TABLE (REG_D2) },
2678 { REG_TABLE (REG_D3) },
2679 { X86_64_TABLE (X86_64_D4) },
2680 { X86_64_TABLE (X86_64_D5) },
2682 { "xlat", { DSBX }, 0 },
2693 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2694 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2695 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2696 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2697 { "inB", { AL, Ib }, 0 },
2698 { "inG", { zAX, Ib }, 0 },
2699 { "outB", { Ib, AL }, 0 },
2700 { "outG", { Ib, zAX }, 0 },
2702 { "callT", { Jv, BND }, 0 },
2703 { "jmpT", { Jv, BND }, 0 },
2704 { X86_64_TABLE (X86_64_EA) },
2705 { "jmp", { Jb, BND }, 0 },
2706 { "inB", { AL, indirDX }, 0 },
2707 { "inG", { zAX, indirDX }, 0 },
2708 { "outB", { indirDX, AL }, 0 },
2709 { "outG", { indirDX, zAX }, 0 },
2711 { Bad_Opcode }, /* lock prefix */
2712 { "icebp", { XX }, 0 },
2713 { Bad_Opcode }, /* repne */
2714 { Bad_Opcode }, /* repz */
2715 { "hlt", { XX }, 0 },
2716 { "cmc", { XX }, 0 },
2717 { REG_TABLE (REG_F6) },
2718 { REG_TABLE (REG_F7) },
2720 { "clc", { XX }, 0 },
2721 { "stc", { XX }, 0 },
2722 { "cli", { XX }, 0 },
2723 { "sti", { XX }, 0 },
2724 { "cld", { XX }, 0 },
2725 { "std", { XX }, 0 },
2726 { REG_TABLE (REG_FE) },
2727 { REG_TABLE (REG_FF) },
2730 static const struct dis386 dis386_twobyte[] = {
2732 { REG_TABLE (REG_0F00 ) },
2733 { REG_TABLE (REG_0F01 ) },
2734 { "larS", { Gv, Ew }, 0 },
2735 { "lslS", { Gv, Ew }, 0 },
2737 { "syscall", { XX }, 0 },
2738 { "clts", { XX }, 0 },
2739 { "sysret%LP", { XX }, 0 },
2741 { "invd", { XX }, 0 },
2742 { "wbinvd", { XX }, 0 },
2744 { "ud2", { XX }, 0 },
2746 { REG_TABLE (REG_0F0D) },
2747 { "femms", { XX }, 0 },
2748 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2750 { PREFIX_TABLE (PREFIX_0F10) },
2751 { PREFIX_TABLE (PREFIX_0F11) },
2752 { PREFIX_TABLE (PREFIX_0F12) },
2753 { MOD_TABLE (MOD_0F13) },
2754 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2755 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2756 { PREFIX_TABLE (PREFIX_0F16) },
2757 { MOD_TABLE (MOD_0F17) },
2759 { REG_TABLE (REG_0F18) },
2760 { "nopQ", { Ev }, 0 },
2761 { PREFIX_TABLE (PREFIX_0F1A) },
2762 { PREFIX_TABLE (PREFIX_0F1B) },
2763 { "nopQ", { Ev }, 0 },
2764 { "nopQ", { Ev }, 0 },
2765 { "nopQ", { Ev }, 0 },
2766 { "nopQ", { Ev }, 0 },
2768 { "movZ", { Rm, Cm }, 0 },
2769 { "movZ", { Rm, Dm }, 0 },
2770 { "movZ", { Cm, Rm }, 0 },
2771 { "movZ", { Dm, Rm }, 0 },
2772 { MOD_TABLE (MOD_0F24) },
2774 { MOD_TABLE (MOD_0F26) },
2777 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2778 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2779 { PREFIX_TABLE (PREFIX_0F2A) },
2780 { PREFIX_TABLE (PREFIX_0F2B) },
2781 { PREFIX_TABLE (PREFIX_0F2C) },
2782 { PREFIX_TABLE (PREFIX_0F2D) },
2783 { PREFIX_TABLE (PREFIX_0F2E) },
2784 { PREFIX_TABLE (PREFIX_0F2F) },
2786 { "wrmsr", { XX }, 0 },
2787 { "rdtsc", { XX }, 0 },
2788 { "rdmsr", { XX }, 0 },
2789 { "rdpmc", { XX }, 0 },
2790 { "sysenter", { XX }, 0 },
2791 { "sysexit", { XX }, 0 },
2793 { "getsec", { XX }, 0 },
2795 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2797 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2804 { "cmovoS", { Gv, Ev }, 0 },
2805 { "cmovnoS", { Gv, Ev }, 0 },
2806 { "cmovbS", { Gv, Ev }, 0 },
2807 { "cmovaeS", { Gv, Ev }, 0 },
2808 { "cmoveS", { Gv, Ev }, 0 },
2809 { "cmovneS", { Gv, Ev }, 0 },
2810 { "cmovbeS", { Gv, Ev }, 0 },
2811 { "cmovaS", { Gv, Ev }, 0 },
2813 { "cmovsS", { Gv, Ev }, 0 },
2814 { "cmovnsS", { Gv, Ev }, 0 },
2815 { "cmovpS", { Gv, Ev }, 0 },
2816 { "cmovnpS", { Gv, Ev }, 0 },
2817 { "cmovlS", { Gv, Ev }, 0 },
2818 { "cmovgeS", { Gv, Ev }, 0 },
2819 { "cmovleS", { Gv, Ev }, 0 },
2820 { "cmovgS", { Gv, Ev }, 0 },
2822 { MOD_TABLE (MOD_0F51) },
2823 { PREFIX_TABLE (PREFIX_0F51) },
2824 { PREFIX_TABLE (PREFIX_0F52) },
2825 { PREFIX_TABLE (PREFIX_0F53) },
2826 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2827 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2828 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2829 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2831 { PREFIX_TABLE (PREFIX_0F58) },
2832 { PREFIX_TABLE (PREFIX_0F59) },
2833 { PREFIX_TABLE (PREFIX_0F5A) },
2834 { PREFIX_TABLE (PREFIX_0F5B) },
2835 { PREFIX_TABLE (PREFIX_0F5C) },
2836 { PREFIX_TABLE (PREFIX_0F5D) },
2837 { PREFIX_TABLE (PREFIX_0F5E) },
2838 { PREFIX_TABLE (PREFIX_0F5F) },
2840 { PREFIX_TABLE (PREFIX_0F60) },
2841 { PREFIX_TABLE (PREFIX_0F61) },
2842 { PREFIX_TABLE (PREFIX_0F62) },
2843 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2844 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2845 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2846 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2847 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2849 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2850 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2851 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2852 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2853 { PREFIX_TABLE (PREFIX_0F6C) },
2854 { PREFIX_TABLE (PREFIX_0F6D) },
2855 { "movK", { MX, Edq }, PREFIX_OPCODE },
2856 { PREFIX_TABLE (PREFIX_0F6F) },
2858 { PREFIX_TABLE (PREFIX_0F70) },
2859 { REG_TABLE (REG_0F71) },
2860 { REG_TABLE (REG_0F72) },
2861 { REG_TABLE (REG_0F73) },
2862 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2863 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2864 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2865 { "emms", { XX }, PREFIX_OPCODE },
2867 { PREFIX_TABLE (PREFIX_0F78) },
2868 { PREFIX_TABLE (PREFIX_0F79) },
2869 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2871 { PREFIX_TABLE (PREFIX_0F7C) },
2872 { PREFIX_TABLE (PREFIX_0F7D) },
2873 { PREFIX_TABLE (PREFIX_0F7E) },
2874 { PREFIX_TABLE (PREFIX_0F7F) },
2876 { "joH", { Jv, BND, cond_jump_flag }, 0 },
2877 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
2878 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
2879 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
2880 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
2881 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
2882 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
2883 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
2885 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
2886 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
2887 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
2888 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
2889 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
2890 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
2891 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
2892 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
2894 { "seto", { Eb }, 0 },
2895 { "setno", { Eb }, 0 },
2896 { "setb", { Eb }, 0 },
2897 { "setae", { Eb }, 0 },
2898 { "sete", { Eb }, 0 },
2899 { "setne", { Eb }, 0 },
2900 { "setbe", { Eb }, 0 },
2901 { "seta", { Eb }, 0 },
2903 { "sets", { Eb }, 0 },
2904 { "setns", { Eb }, 0 },
2905 { "setp", { Eb }, 0 },
2906 { "setnp", { Eb }, 0 },
2907 { "setl", { Eb }, 0 },
2908 { "setge", { Eb }, 0 },
2909 { "setle", { Eb }, 0 },
2910 { "setg", { Eb }, 0 },
2912 { "pushT", { fs }, 0 },
2913 { "popT", { fs }, 0 },
2914 { "cpuid", { XX }, 0 },
2915 { "btS", { Ev, Gv }, 0 },
2916 { "shldS", { Ev, Gv, Ib }, 0 },
2917 { "shldS", { Ev, Gv, CL }, 0 },
2918 { REG_TABLE (REG_0FA6) },
2919 { REG_TABLE (REG_0FA7) },
2921 { "pushT", { gs }, 0 },
2922 { "popT", { gs }, 0 },
2923 { "rsm", { XX }, 0 },
2924 { "btsS", { Evh1, Gv }, 0 },
2925 { "shrdS", { Ev, Gv, Ib }, 0 },
2926 { "shrdS", { Ev, Gv, CL }, 0 },
2927 { REG_TABLE (REG_0FAE) },
2928 { "imulS", { Gv, Ev }, 0 },
2930 { "cmpxchgB", { Ebh1, Gb }, 0 },
2931 { "cmpxchgS", { Evh1, Gv }, 0 },
2932 { MOD_TABLE (MOD_0FB2) },
2933 { "btrS", { Evh1, Gv }, 0 },
2934 { MOD_TABLE (MOD_0FB4) },
2935 { MOD_TABLE (MOD_0FB5) },
2936 { "movz{bR|x}", { Gv, Eb }, 0 },
2937 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2939 { PREFIX_TABLE (PREFIX_0FB8) },
2940 { "ud1", { XX }, 0 },
2941 { REG_TABLE (REG_0FBA) },
2942 { "btcS", { Evh1, Gv }, 0 },
2943 { PREFIX_TABLE (PREFIX_0FBC) },
2944 { PREFIX_TABLE (PREFIX_0FBD) },
2945 { "movs{bR|x}", { Gv, Eb }, 0 },
2946 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2948 { "xaddB", { Ebh1, Gb }, 0 },
2949 { "xaddS", { Evh1, Gv }, 0 },
2950 { PREFIX_TABLE (PREFIX_0FC2) },
2951 { PREFIX_TABLE (PREFIX_0FC3) },
2952 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
2953 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
2954 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
2955 { REG_TABLE (REG_0FC7) },
2957 { "bswap", { RMeAX }, 0 },
2958 { "bswap", { RMeCX }, 0 },
2959 { "bswap", { RMeDX }, 0 },
2960 { "bswap", { RMeBX }, 0 },
2961 { "bswap", { RMeSP }, 0 },
2962 { "bswap", { RMeBP }, 0 },
2963 { "bswap", { RMeSI }, 0 },
2964 { "bswap", { RMeDI }, 0 },
2966 { PREFIX_TABLE (PREFIX_0FD0) },
2967 { "psrlw", { MX, EM }, PREFIX_OPCODE },
2968 { "psrld", { MX, EM }, PREFIX_OPCODE },
2969 { "psrlq", { MX, EM }, PREFIX_OPCODE },
2970 { "paddq", { MX, EM }, PREFIX_OPCODE },
2971 { "pmullw", { MX, EM }, PREFIX_OPCODE },
2972 { PREFIX_TABLE (PREFIX_0FD6) },
2973 { MOD_TABLE (MOD_0FD7) },
2975 { "psubusb", { MX, EM }, PREFIX_OPCODE },
2976 { "psubusw", { MX, EM }, PREFIX_OPCODE },
2977 { "pminub", { MX, EM }, PREFIX_OPCODE },
2978 { "pand", { MX, EM }, PREFIX_OPCODE },
2979 { "paddusb", { MX, EM }, PREFIX_OPCODE },
2980 { "paddusw", { MX, EM }, PREFIX_OPCODE },
2981 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
2982 { "pandn", { MX, EM }, PREFIX_OPCODE },
2984 { "pavgb", { MX, EM }, PREFIX_OPCODE },
2985 { "psraw", { MX, EM }, PREFIX_OPCODE },
2986 { "psrad", { MX, EM }, PREFIX_OPCODE },
2987 { "pavgw", { MX, EM }, PREFIX_OPCODE },
2988 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
2989 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
2990 { PREFIX_TABLE (PREFIX_0FE6) },
2991 { PREFIX_TABLE (PREFIX_0FE7) },
2993 { "psubsb", { MX, EM }, PREFIX_OPCODE },
2994 { "psubsw", { MX, EM }, PREFIX_OPCODE },
2995 { "pminsw", { MX, EM }, PREFIX_OPCODE },
2996 { "por", { MX, EM }, PREFIX_OPCODE },
2997 { "paddsb", { MX, EM }, PREFIX_OPCODE },
2998 { "paddsw", { MX, EM }, PREFIX_OPCODE },
2999 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
3000 { "pxor", { MX, EM }, PREFIX_OPCODE },
3002 { PREFIX_TABLE (PREFIX_0FF0) },
3003 { "psllw", { MX, EM }, PREFIX_OPCODE },
3004 { "pslld", { MX, EM }, PREFIX_OPCODE },
3005 { "psllq", { MX, EM }, PREFIX_OPCODE },
3006 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
3007 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
3008 { "psadbw", { MX, EM }, PREFIX_OPCODE },
3009 { PREFIX_TABLE (PREFIX_0FF7) },
3011 { "psubb", { MX, EM }, PREFIX_OPCODE },
3012 { "psubw", { MX, EM }, PREFIX_OPCODE },
3013 { "psubd", { MX, EM }, PREFIX_OPCODE },
3014 { "psubq", { MX, EM }, PREFIX_OPCODE },
3015 { "paddb", { MX, EM }, PREFIX_OPCODE },
3016 { "paddw", { MX, EM }, PREFIX_OPCODE },
3017 { "paddd", { MX, EM }, PREFIX_OPCODE },
3021 static const unsigned char onebyte_has_modrm[256] = {
3022 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3023 /* ------------------------------- */
3024 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3025 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3026 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3027 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3028 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3029 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3030 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3031 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3032 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3033 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3034 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3035 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3036 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3037 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3038 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3039 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3040 /* ------------------------------- */
3041 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3044 static const unsigned char twobyte_has_modrm[256] = {
3045 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3046 /* ------------------------------- */
3047 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3048 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3049 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3050 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3051 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3052 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3053 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3054 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3055 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3056 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3057 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3058 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3059 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3060 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3061 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3062 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3063 /* ------------------------------- */
3064 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3067 static char obuf[100];
3069 static char *mnemonicendp;
3070 static char scratchbuf[100];
3071 static unsigned char *start_codep;
3072 static unsigned char *insn_codep;
3073 static unsigned char *codep;
3074 static unsigned char *end_codep;
3075 static int last_lock_prefix;
3076 static int last_repz_prefix;
3077 static int last_repnz_prefix;
3078 static int last_data_prefix;
3079 static int last_addr_prefix;
3080 static int last_rex_prefix;
3081 static int last_seg_prefix;
3082 static int fwait_prefix;
3083 /* The PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is mandatory. */
3084 static int prefix_requirement;
3085 /* The active segment register prefix. */
3086 static int active_seg_prefix;
3087 #define MAX_CODE_LENGTH 15
3088 /* We can up to 14 prefixes since the maximum instruction length is
3090 static int all_prefixes[MAX_CODE_LENGTH - 1];
3091 static disassemble_info *the_info;
3099 static unsigned char need_modrm;
3109 int register_specifier;
3116 int mask_register_specifier;
3122 static unsigned char need_vex;
3123 static unsigned char need_vex_reg;
3124 static unsigned char vex_w_done;
3132 /* If we are accessing mod/rm/reg without need_modrm set, then the
3133 values are stale. Hitting this abort likely indicates that you
3134 need to update onebyte_has_modrm or twobyte_has_modrm. */
3135 #define MODRM_CHECK if (!need_modrm) abort ()
3137 static const char **names64;
3138 static const char **names32;
3139 static const char **names16;
3140 static const char **names8;
3141 static const char **names8rex;
3142 static const char **names_seg;
3143 static const char *index64;
3144 static const char *index32;
3145 static const char **index16;
3146 static const char **names_bnd;
3148 static const char *intel_names64[] = {
3149 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3150 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3152 static const char *intel_names32[] = {
3153 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3154 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3156 static const char *intel_names16[] = {
3157 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3158 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3160 static const char *intel_names8[] = {
3161 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3163 static const char *intel_names8rex[] = {
3164 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3165 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3167 static const char *intel_names_seg[] = {
3168 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3170 static const char *intel_index64 = "riz";
3171 static const char *intel_index32 = "eiz";
3172 static const char *intel_index16[] = {
3173 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3176 static const char *att_names64[] = {
3177 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3178 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3180 static const char *att_names32[] = {
3181 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3182 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3184 static const char *att_names16[] = {
3185 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3186 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3188 static const char *att_names8[] = {
3189 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3191 static const char *att_names8rex[] = {
3192 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3193 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3195 static const char *att_names_seg[] = {
3196 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3198 static const char *att_index64 = "%riz";
3199 static const char *att_index32 = "%eiz";
3200 static const char *att_index16[] = {
3201 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3204 static const char **names_mm;
3205 static const char *intel_names_mm[] = {
3206 "mm0", "mm1", "mm2", "mm3",
3207 "mm4", "mm5", "mm6", "mm7"
3209 static const char *att_names_mm[] = {
3210 "%mm0", "%mm1", "%mm2", "%mm3",
3211 "%mm4", "%mm5", "%mm6", "%mm7"
3214 static const char *intel_names_bnd[] = {
3215 "bnd0", "bnd1", "bnd2", "bnd3"
3218 static const char *att_names_bnd[] = {
3219 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3222 static const char **names_xmm;
3223 static const char *intel_names_xmm[] = {
3224 "xmm0", "xmm1", "xmm2", "xmm3",
3225 "xmm4", "xmm5", "xmm6", "xmm7",
3226 "xmm8", "xmm9", "xmm10", "xmm11",
3227 "xmm12", "xmm13", "xmm14", "xmm15",
3228 "xmm16", "xmm17", "xmm18", "xmm19",
3229 "xmm20", "xmm21", "xmm22", "xmm23",
3230 "xmm24", "xmm25", "xmm26", "xmm27",
3231 "xmm28", "xmm29", "xmm30", "xmm31"
3233 static const char *att_names_xmm[] = {
3234 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3235 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3236 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3237 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3238 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3239 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3240 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3241 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3244 static const char **names_ymm;
3245 static const char *intel_names_ymm[] = {
3246 "ymm0", "ymm1", "ymm2", "ymm3",
3247 "ymm4", "ymm5", "ymm6", "ymm7",
3248 "ymm8", "ymm9", "ymm10", "ymm11",
3249 "ymm12", "ymm13", "ymm14", "ymm15",
3250 "ymm16", "ymm17", "ymm18", "ymm19",
3251 "ymm20", "ymm21", "ymm22", "ymm23",
3252 "ymm24", "ymm25", "ymm26", "ymm27",
3253 "ymm28", "ymm29", "ymm30", "ymm31"
3255 static const char *att_names_ymm[] = {
3256 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3257 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3258 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3259 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3260 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3261 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3262 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3263 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3266 static const char **names_zmm;
3267 static const char *intel_names_zmm[] = {
3268 "zmm0", "zmm1", "zmm2", "zmm3",
3269 "zmm4", "zmm5", "zmm6", "zmm7",
3270 "zmm8", "zmm9", "zmm10", "zmm11",
3271 "zmm12", "zmm13", "zmm14", "zmm15",
3272 "zmm16", "zmm17", "zmm18", "zmm19",
3273 "zmm20", "zmm21", "zmm22", "zmm23",
3274 "zmm24", "zmm25", "zmm26", "zmm27",
3275 "zmm28", "zmm29", "zmm30", "zmm31"
3277 static const char *att_names_zmm[] = {
3278 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3279 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3280 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3281 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3282 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3283 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3284 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3285 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3288 static const char **names_mask;
3289 static const char *intel_names_mask[] = {
3290 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3292 static const char *att_names_mask[] = {
3293 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3296 static const char *names_rounding[] =
3304 static const struct dis386 reg_table[][8] = {
3307 { "addA", { Ebh1, Ib }, 0 },
3308 { "orA", { Ebh1, Ib }, 0 },
3309 { "adcA", { Ebh1, Ib }, 0 },
3310 { "sbbA", { Ebh1, Ib }, 0 },
3311 { "andA", { Ebh1, Ib }, 0 },
3312 { "subA", { Ebh1, Ib }, 0 },
3313 { "xorA", { Ebh1, Ib }, 0 },
3314 { "cmpA", { Eb, Ib }, 0 },
3318 { "addQ", { Evh1, Iv }, 0 },
3319 { "orQ", { Evh1, Iv }, 0 },
3320 { "adcQ", { Evh1, Iv }, 0 },
3321 { "sbbQ", { Evh1, Iv }, 0 },
3322 { "andQ", { Evh1, Iv }, 0 },
3323 { "subQ", { Evh1, Iv }, 0 },
3324 { "xorQ", { Evh1, Iv }, 0 },
3325 { "cmpQ", { Ev, Iv }, 0 },
3329 { "addQ", { Evh1, sIb }, 0 },
3330 { "orQ", { Evh1, sIb }, 0 },
3331 { "adcQ", { Evh1, sIb }, 0 },
3332 { "sbbQ", { Evh1, sIb }, 0 },
3333 { "andQ", { Evh1, sIb }, 0 },
3334 { "subQ", { Evh1, sIb }, 0 },
3335 { "xorQ", { Evh1, sIb }, 0 },
3336 { "cmpQ", { Ev, sIb }, 0 },
3340 { "popU", { stackEv }, 0 },
3341 { XOP_8F_TABLE (XOP_09) },
3345 { XOP_8F_TABLE (XOP_09) },
3349 { "rolA", { Eb, Ib }, 0 },
3350 { "rorA", { Eb, Ib }, 0 },
3351 { "rclA", { Eb, Ib }, 0 },
3352 { "rcrA", { Eb, Ib }, 0 },
3353 { "shlA", { Eb, Ib }, 0 },
3354 { "shrA", { Eb, Ib }, 0 },
3356 { "sarA", { Eb, Ib }, 0 },
3360 { "rolQ", { Ev, Ib }, 0 },
3361 { "rorQ", { Ev, Ib }, 0 },
3362 { "rclQ", { Ev, Ib }, 0 },
3363 { "rcrQ", { Ev, Ib }, 0 },
3364 { "shlQ", { Ev, Ib }, 0 },
3365 { "shrQ", { Ev, Ib }, 0 },
3367 { "sarQ", { Ev, Ib }, 0 },
3371 { "movA", { Ebh3, Ib }, 0 },
3378 { MOD_TABLE (MOD_C6_REG_7) },
3382 { "movQ", { Evh3, Iv }, 0 },
3389 { MOD_TABLE (MOD_C7_REG_7) },
3393 { "rolA", { Eb, I1 }, 0 },
3394 { "rorA", { Eb, I1 }, 0 },
3395 { "rclA", { Eb, I1 }, 0 },
3396 { "rcrA", { Eb, I1 }, 0 },
3397 { "shlA", { Eb, I1 }, 0 },
3398 { "shrA", { Eb, I1 }, 0 },
3400 { "sarA", { Eb, I1 }, 0 },
3404 { "rolQ", { Ev, I1 }, 0 },
3405 { "rorQ", { Ev, I1 }, 0 },
3406 { "rclQ", { Ev, I1 }, 0 },
3407 { "rcrQ", { Ev, I1 }, 0 },
3408 { "shlQ", { Ev, I1 }, 0 },
3409 { "shrQ", { Ev, I1 }, 0 },
3411 { "sarQ", { Ev, I1 }, 0 },
3415 { "rolA", { Eb, CL }, 0 },
3416 { "rorA", { Eb, CL }, 0 },
3417 { "rclA", { Eb, CL }, 0 },
3418 { "rcrA", { Eb, CL }, 0 },
3419 { "shlA", { Eb, CL }, 0 },
3420 { "shrA", { Eb, CL }, 0 },
3422 { "sarA", { Eb, CL }, 0 },
3426 { "rolQ", { Ev, CL }, 0 },
3427 { "rorQ", { Ev, CL }, 0 },
3428 { "rclQ", { Ev, CL }, 0 },
3429 { "rcrQ", { Ev, CL }, 0 },
3430 { "shlQ", { Ev, CL }, 0 },
3431 { "shrQ", { Ev, CL }, 0 },
3433 { "sarQ", { Ev, CL }, 0 },
3437 { "testA", { Eb, Ib }, 0 },
3439 { "notA", { Ebh1 }, 0 },
3440 { "negA", { Ebh1 }, 0 },
3441 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
3442 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
3443 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
3444 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
3448 { "testQ", { Ev, Iv }, 0 },
3450 { "notQ", { Evh1 }, 0 },
3451 { "negQ", { Evh1 }, 0 },
3452 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
3453 { "imulQ", { Ev }, 0 },
3454 { "divQ", { Ev }, 0 },
3455 { "idivQ", { Ev }, 0 },
3459 { "incA", { Ebh1 }, 0 },
3460 { "decA", { Ebh1 }, 0 },
3464 { "incQ", { Evh1 }, 0 },
3465 { "decQ", { Evh1 }, 0 },
3466 { "call{T|}", { indirEv, BND }, 0 },
3467 { MOD_TABLE (MOD_FF_REG_3) },
3468 { "jmp{T|}", { indirEv, BND }, 0 },
3469 { MOD_TABLE (MOD_FF_REG_5) },
3470 { "pushU", { stackEv }, 0 },
3475 { "sldtD", { Sv }, 0 },
3476 { "strD", { Sv }, 0 },
3477 { "lldt", { Ew }, 0 },
3478 { "ltr", { Ew }, 0 },
3479 { "verr", { Ew }, 0 },
3480 { "verw", { Ew }, 0 },
3486 { MOD_TABLE (MOD_0F01_REG_0) },
3487 { MOD_TABLE (MOD_0F01_REG_1) },
3488 { MOD_TABLE (MOD_0F01_REG_2) },
3489 { MOD_TABLE (MOD_0F01_REG_3) },
3490 { "smswD", { Sv }, 0 },
3492 { "lmsw", { Ew }, 0 },
3493 { MOD_TABLE (MOD_0F01_REG_7) },
3497 { "prefetch", { Mb }, 0 },
3498 { "prefetchw", { Mb }, 0 },
3499 { "prefetchwt1", { Mb }, 0 },
3500 { "prefetch", { Mb }, 0 },
3501 { "prefetch", { Mb }, 0 },
3502 { "prefetch", { Mb }, 0 },
3503 { "prefetch", { Mb }, 0 },
3504 { "prefetch", { Mb }, 0 },
3508 { MOD_TABLE (MOD_0F18_REG_0) },
3509 { MOD_TABLE (MOD_0F18_REG_1) },
3510 { MOD_TABLE (MOD_0F18_REG_2) },
3511 { MOD_TABLE (MOD_0F18_REG_3) },
3512 { MOD_TABLE (MOD_0F18_REG_4) },
3513 { MOD_TABLE (MOD_0F18_REG_5) },
3514 { MOD_TABLE (MOD_0F18_REG_6) },
3515 { MOD_TABLE (MOD_0F18_REG_7) },
3521 { MOD_TABLE (MOD_0F71_REG_2) },
3523 { MOD_TABLE (MOD_0F71_REG_4) },
3525 { MOD_TABLE (MOD_0F71_REG_6) },
3531 { MOD_TABLE (MOD_0F72_REG_2) },
3533 { MOD_TABLE (MOD_0F72_REG_4) },
3535 { MOD_TABLE (MOD_0F72_REG_6) },
3541 { MOD_TABLE (MOD_0F73_REG_2) },
3542 { MOD_TABLE (MOD_0F73_REG_3) },
3545 { MOD_TABLE (MOD_0F73_REG_6) },
3546 { MOD_TABLE (MOD_0F73_REG_7) },
3550 { "montmul", { { OP_0f07, 0 } }, 0 },
3551 { "xsha1", { { OP_0f07, 0 } }, 0 },
3552 { "xsha256", { { OP_0f07, 0 } }, 0 },
3556 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
3557 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
3558 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
3559 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
3560 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
3561 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
3565 { MOD_TABLE (MOD_0FAE_REG_0) },
3566 { MOD_TABLE (MOD_0FAE_REG_1) },
3567 { MOD_TABLE (MOD_0FAE_REG_2) },
3568 { MOD_TABLE (MOD_0FAE_REG_3) },
3569 { MOD_TABLE (MOD_0FAE_REG_4) },
3570 { MOD_TABLE (MOD_0FAE_REG_5) },
3571 { MOD_TABLE (MOD_0FAE_REG_6) },
3572 { MOD_TABLE (MOD_0FAE_REG_7) },
3580 { "btQ", { Ev, Ib }, 0 },
3581 { "btsQ", { Evh1, Ib }, 0 },
3582 { "btrQ", { Evh1, Ib }, 0 },
3583 { "btcQ", { Evh1, Ib }, 0 },
3588 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3590 { MOD_TABLE (MOD_0FC7_REG_3) },
3591 { MOD_TABLE (MOD_0FC7_REG_4) },
3592 { MOD_TABLE (MOD_0FC7_REG_5) },
3593 { MOD_TABLE (MOD_0FC7_REG_6) },
3594 { MOD_TABLE (MOD_0FC7_REG_7) },
3600 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3602 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3604 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3610 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3612 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3614 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3620 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3621 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3624 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3625 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3631 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3632 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3634 /* REG_VEX_0F38F3 */
3637 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3638 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3639 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3643 { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3644 { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3648 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3649 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3651 /* REG_XOP_TBM_01 */
3654 { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3655 { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3656 { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 },
3657 { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3658 { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 },
3659 { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 },
3660 { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3662 /* REG_XOP_TBM_02 */
3665 { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3670 { "blci", { { OP_LWP_E, 0 }, Ev }, 0 },
3672 #define NEED_REG_TABLE
3673 #include "i386-dis-evex.h"
3674 #undef NEED_REG_TABLE
3677 static const struct dis386 prefix_table[][4] = {
3680 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3681 { "pause", { XX }, 0 },
3682 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3683 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3688 { "movups", { XM, EXx }, PREFIX_OPCODE },
3689 { "movss", { XM, EXd }, PREFIX_OPCODE },
3690 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3691 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3696 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3697 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3698 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3699 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3704 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3705 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3706 { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3707 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3712 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3713 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3714 { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3719 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3720 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3721 { "bndmov", { Gbnd, Ebnd }, 0 },
3722 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3727 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3728 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3729 { "bndmov", { Ebnd, Gbnd }, 0 },
3730 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3735 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3736 { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3737 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3738 { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3743 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3744 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3745 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3746 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3751 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3752 { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3753 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3754 { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3759 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3760 { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3761 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3762 { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3767 { "ucomiss",{ XM, EXd }, 0 },
3769 { "ucomisd",{ XM, EXq }, 0 },
3774 { "comiss", { XM, EXd }, 0 },
3776 { "comisd", { XM, EXq }, 0 },
3781 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3782 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3783 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3784 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3789 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3790 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3795 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3796 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3801 { "addps", { XM, EXx }, PREFIX_OPCODE },
3802 { "addss", { XM, EXd }, PREFIX_OPCODE },
3803 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3804 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3809 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3810 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3811 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3812 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3817 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3818 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3819 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3820 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3825 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3826 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3827 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3832 { "subps", { XM, EXx }, PREFIX_OPCODE },
3833 { "subss", { XM, EXd }, PREFIX_OPCODE },
3834 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3835 { "subsd", { XM, EXq }, PREFIX_OPCODE },
3840 { "minps", { XM, EXx }, PREFIX_OPCODE },
3841 { "minss", { XM, EXd }, PREFIX_OPCODE },
3842 { "minpd", { XM, EXx }, PREFIX_OPCODE },
3843 { "minsd", { XM, EXq }, PREFIX_OPCODE },
3848 { "divps", { XM, EXx }, PREFIX_OPCODE },
3849 { "divss", { XM, EXd }, PREFIX_OPCODE },
3850 { "divpd", { XM, EXx }, PREFIX_OPCODE },
3851 { "divsd", { XM, EXq }, PREFIX_OPCODE },
3856 { "maxps", { XM, EXx }, PREFIX_OPCODE },
3857 { "maxss", { XM, EXd }, PREFIX_OPCODE },
3858 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
3859 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
3864 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3866 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3871 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3873 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3878 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3880 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3887 { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3894 { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3899 { "movq", { MX, EM }, PREFIX_OPCODE },
3900 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3901 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3906 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3907 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3908 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3909 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3912 /* PREFIX_0F73_REG_3 */
3916 { "psrldq", { XS, Ib }, 0 },
3919 /* PREFIX_0F73_REG_7 */
3923 { "pslldq", { XS, Ib }, 0 },
3928 {"vmread", { Em, Gm }, 0 },
3930 {"extrq", { XS, Ib, Ib }, 0 },
3931 {"insertq", { XM, XS, Ib, Ib }, 0 },
3936 {"vmwrite", { Gm, Em }, 0 },
3938 {"extrq", { XM, XS }, 0 },
3939 {"insertq", { XM, XS }, 0 },
3946 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3947 { "haddps", { XM, EXx }, PREFIX_OPCODE },
3954 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3955 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3960 { "movK", { Edq, MX }, PREFIX_OPCODE },
3961 { "movq", { XM, EXq }, PREFIX_OPCODE },
3962 { "movK", { Edq, XM }, PREFIX_OPCODE },
3967 { "movq", { EMS, MX }, PREFIX_OPCODE },
3968 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3969 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3972 /* PREFIX_0FAE_REG_0 */
3975 { "rdfsbase", { Ev }, 0 },
3978 /* PREFIX_0FAE_REG_1 */
3981 { "rdgsbase", { Ev }, 0 },
3984 /* PREFIX_0FAE_REG_2 */
3987 { "wrfsbase", { Ev }, 0 },
3990 /* PREFIX_0FAE_REG_3 */
3993 { "wrgsbase", { Ev }, 0 },
3996 /* PREFIX_0FAE_REG_6 */
3998 { "xsaveopt", { FXSAVE }, 0 },
4000 { "clwb", { Mb }, 0 },
4003 /* PREFIX_0FAE_REG_7 */
4005 { "clflush", { Mb }, 0 },
4007 { "clflushopt", { Mb }, 0 },
4010 /* PREFIX_RM_0_0FAE_REG_7 */
4012 { "sfence", { Skip_MODRM }, 0 },
4014 { "pcommit", { Skip_MODRM }, 0 },
4020 { "popcntS", { Gv, Ev }, 0 },
4025 { "bsfS", { Gv, Ev }, 0 },
4026 { "tzcntS", { Gv, Ev }, 0 },
4027 { "bsfS", { Gv, Ev }, 0 },
4032 { "bsrS", { Gv, Ev }, 0 },
4033 { "lzcntS", { Gv, Ev }, 0 },
4034 { "bsrS", { Gv, Ev }, 0 },
4039 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
4040 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
4041 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
4042 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
4047 { "movntiS", { Ma, Gv }, PREFIX_OPCODE },
4050 /* PREFIX_0FC7_REG_6 */
4052 { "vmptrld",{ Mq }, 0 },
4053 { "vmxon", { Mq }, 0 },
4054 { "vmclear",{ Mq }, 0 },
4061 { "addsubpd", { XM, EXx }, 0 },
4062 { "addsubps", { XM, EXx }, 0 },
4068 { "movq2dq",{ XM, MS }, 0 },
4069 { "movq", { EXqS, XM }, 0 },
4070 { "movdq2q",{ MX, XS }, 0 },
4076 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4077 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4078 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4083 { "movntq", { Mq, MX }, PREFIX_OPCODE },
4085 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4093 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4098 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4100 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4107 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4114 { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4121 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4128 { "ptest", { XM, EXx }, PREFIX_OPCODE },
4135 { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4142 { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4149 { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4156 { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4163 { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4170 { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4177 { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4184 { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4191 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4198 { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4205 { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4212 { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4219 { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4226 { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4233 { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4240 { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4247 { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4254 { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4261 { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4268 { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4275 { "pminud", { XM, EXx }, PREFIX_OPCODE },
4282 { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4289 { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4296 { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4303 { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4310 { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4317 { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4324 { "invept", { Gm, Mo }, PREFIX_OPCODE },
4331 { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4338 { "invpcid", { Gm, M }, PREFIX_OPCODE },
4343 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4348 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4353 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4358 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4363 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4368 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4375 { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4382 { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4389 { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4396 { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4403 { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4408 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4410 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4411 { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4416 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4418 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4419 { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4425 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
4426 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
4434 { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4441 { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4448 { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4455 { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4462 { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4469 { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4476 { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4483 { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4490 { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4497 { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4504 { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4511 { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4518 { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4525 { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4532 { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE },
4539 { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE },
4546 { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4553 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4560 { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4567 { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE },
4574 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4581 { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4586 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4593 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4596 /* PREFIX_VEX_0F10 */
4598 { VEX_W_TABLE (VEX_W_0F10_P_0) },
4599 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4600 { VEX_W_TABLE (VEX_W_0F10_P_2) },
4601 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4604 /* PREFIX_VEX_0F11 */
4606 { VEX_W_TABLE (VEX_W_0F11_P_0) },
4607 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4608 { VEX_W_TABLE (VEX_W_0F11_P_2) },
4609 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4612 /* PREFIX_VEX_0F12 */
4614 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4615 { VEX_W_TABLE (VEX_W_0F12_P_1) },
4616 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4617 { VEX_W_TABLE (VEX_W_0F12_P_3) },
4620 /* PREFIX_VEX_0F16 */
4622 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4623 { VEX_W_TABLE (VEX_W_0F16_P_1) },
4624 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4627 /* PREFIX_VEX_0F2A */
4630 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4632 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4635 /* PREFIX_VEX_0F2C */
4638 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4640 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4643 /* PREFIX_VEX_0F2D */
4646 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4648 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4651 /* PREFIX_VEX_0F2E */
4653 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4655 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4658 /* PREFIX_VEX_0F2F */
4660 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4662 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4665 /* PREFIX_VEX_0F41 */
4667 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4669 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4672 /* PREFIX_VEX_0F42 */
4674 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4676 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4679 /* PREFIX_VEX_0F44 */
4681 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4683 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4686 /* PREFIX_VEX_0F45 */
4688 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4690 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4693 /* PREFIX_VEX_0F46 */
4695 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4697 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4700 /* PREFIX_VEX_0F47 */
4702 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4704 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4707 /* PREFIX_VEX_0F4A */
4709 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4711 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4714 /* PREFIX_VEX_0F4B */
4716 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4718 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4721 /* PREFIX_VEX_0F51 */
4723 { VEX_W_TABLE (VEX_W_0F51_P_0) },
4724 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4725 { VEX_W_TABLE (VEX_W_0F51_P_2) },
4726 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4729 /* PREFIX_VEX_0F52 */
4731 { VEX_W_TABLE (VEX_W_0F52_P_0) },
4732 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4735 /* PREFIX_VEX_0F53 */
4737 { VEX_W_TABLE (VEX_W_0F53_P_0) },
4738 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4741 /* PREFIX_VEX_0F58 */
4743 { VEX_W_TABLE (VEX_W_0F58_P_0) },
4744 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4745 { VEX_W_TABLE (VEX_W_0F58_P_2) },
4746 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4749 /* PREFIX_VEX_0F59 */
4751 { VEX_W_TABLE (VEX_W_0F59_P_0) },
4752 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4753 { VEX_W_TABLE (VEX_W_0F59_P_2) },
4754 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4757 /* PREFIX_VEX_0F5A */
4759 { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4760 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4761 { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4762 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4765 /* PREFIX_VEX_0F5B */
4767 { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4768 { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4769 { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4772 /* PREFIX_VEX_0F5C */
4774 { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4775 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4776 { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4777 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4780 /* PREFIX_VEX_0F5D */
4782 { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4783 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4784 { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4785 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4788 /* PREFIX_VEX_0F5E */
4790 { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4791 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4792 { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4793 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4796 /* PREFIX_VEX_0F5F */
4798 { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4799 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4800 { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4801 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4804 /* PREFIX_VEX_0F60 */
4808 { VEX_W_TABLE (VEX_W_0F60_P_2) },
4811 /* PREFIX_VEX_0F61 */
4815 { VEX_W_TABLE (VEX_W_0F61_P_2) },
4818 /* PREFIX_VEX_0F62 */
4822 { VEX_W_TABLE (VEX_W_0F62_P_2) },
4825 /* PREFIX_VEX_0F63 */
4829 { VEX_W_TABLE (VEX_W_0F63_P_2) },
4832 /* PREFIX_VEX_0F64 */
4836 { VEX_W_TABLE (VEX_W_0F64_P_2) },
4839 /* PREFIX_VEX_0F65 */
4843 { VEX_W_TABLE (VEX_W_0F65_P_2) },
4846 /* PREFIX_VEX_0F66 */
4850 { VEX_W_TABLE (VEX_W_0F66_P_2) },
4853 /* PREFIX_VEX_0F67 */
4857 { VEX_W_TABLE (VEX_W_0F67_P_2) },
4860 /* PREFIX_VEX_0F68 */
4864 { VEX_W_TABLE (VEX_W_0F68_P_2) },
4867 /* PREFIX_VEX_0F69 */
4871 { VEX_W_TABLE (VEX_W_0F69_P_2) },
4874 /* PREFIX_VEX_0F6A */
4878 { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4881 /* PREFIX_VEX_0F6B */
4885 { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4888 /* PREFIX_VEX_0F6C */
4892 { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4895 /* PREFIX_VEX_0F6D */
4899 { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4902 /* PREFIX_VEX_0F6E */
4906 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4909 /* PREFIX_VEX_0F6F */
4912 { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4913 { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4916 /* PREFIX_VEX_0F70 */
4919 { VEX_W_TABLE (VEX_W_0F70_P_1) },
4920 { VEX_W_TABLE (VEX_W_0F70_P_2) },
4921 { VEX_W_TABLE (VEX_W_0F70_P_3) },
4924 /* PREFIX_VEX_0F71_REG_2 */
4928 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4931 /* PREFIX_VEX_0F71_REG_4 */
4935 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4938 /* PREFIX_VEX_0F71_REG_6 */
4942 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4945 /* PREFIX_VEX_0F72_REG_2 */
4949 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4952 /* PREFIX_VEX_0F72_REG_4 */
4956 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4959 /* PREFIX_VEX_0F72_REG_6 */
4963 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4966 /* PREFIX_VEX_0F73_REG_2 */
4970 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4973 /* PREFIX_VEX_0F73_REG_3 */
4977 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4980 /* PREFIX_VEX_0F73_REG_6 */
4984 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4987 /* PREFIX_VEX_0F73_REG_7 */
4991 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4994 /* PREFIX_VEX_0F74 */
4998 { VEX_W_TABLE (VEX_W_0F74_P_2) },
5001 /* PREFIX_VEX_0F75 */
5005 { VEX_W_TABLE (VEX_W_0F75_P_2) },
5008 /* PREFIX_VEX_0F76 */
5012 { VEX_W_TABLE (VEX_W_0F76_P_2) },
5015 /* PREFIX_VEX_0F77 */
5017 { VEX_W_TABLE (VEX_W_0F77_P_0) },
5020 /* PREFIX_VEX_0F7C */
5024 { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5025 { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5028 /* PREFIX_VEX_0F7D */
5032 { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5033 { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5036 /* PREFIX_VEX_0F7E */
5039 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5040 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5043 /* PREFIX_VEX_0F7F */
5046 { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5047 { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5050 /* PREFIX_VEX_0F90 */
5052 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5054 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5057 /* PREFIX_VEX_0F91 */
5059 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5061 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5064 /* PREFIX_VEX_0F92 */
5066 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5068 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5069 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5072 /* PREFIX_VEX_0F93 */
5074 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5076 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5077 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5080 /* PREFIX_VEX_0F98 */
5082 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5084 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5087 /* PREFIX_VEX_0F99 */
5089 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5091 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5094 /* PREFIX_VEX_0FC2 */
5096 { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5097 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5098 { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5099 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5102 /* PREFIX_VEX_0FC4 */
5106 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5109 /* PREFIX_VEX_0FC5 */
5113 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5116 /* PREFIX_VEX_0FD0 */
5120 { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5121 { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5124 /* PREFIX_VEX_0FD1 */
5128 { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5131 /* PREFIX_VEX_0FD2 */
5135 { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5138 /* PREFIX_VEX_0FD3 */
5142 { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5145 /* PREFIX_VEX_0FD4 */
5149 { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5152 /* PREFIX_VEX_0FD5 */
5156 { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5159 /* PREFIX_VEX_0FD6 */
5163 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5166 /* PREFIX_VEX_0FD7 */
5170 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5173 /* PREFIX_VEX_0FD8 */
5177 { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5180 /* PREFIX_VEX_0FD9 */
5184 { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5187 /* PREFIX_VEX_0FDA */
5191 { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5194 /* PREFIX_VEX_0FDB */
5198 { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5201 /* PREFIX_VEX_0FDC */
5205 { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5208 /* PREFIX_VEX_0FDD */
5212 { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5215 /* PREFIX_VEX_0FDE */
5219 { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5222 /* PREFIX_VEX_0FDF */
5226 { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5229 /* PREFIX_VEX_0FE0 */
5233 { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5236 /* PREFIX_VEX_0FE1 */
5240 { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5243 /* PREFIX_VEX_0FE2 */
5247 { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5250 /* PREFIX_VEX_0FE3 */
5254 { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5257 /* PREFIX_VEX_0FE4 */
5261 { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5264 /* PREFIX_VEX_0FE5 */
5268 { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5271 /* PREFIX_VEX_0FE6 */
5274 { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5275 { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5276 { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5279 /* PREFIX_VEX_0FE7 */
5283 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5286 /* PREFIX_VEX_0FE8 */
5290 { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5293 /* PREFIX_VEX_0FE9 */
5297 { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5300 /* PREFIX_VEX_0FEA */
5304 { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5307 /* PREFIX_VEX_0FEB */
5311 { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5314 /* PREFIX_VEX_0FEC */
5318 { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5321 /* PREFIX_VEX_0FED */
5325 { VEX_W_TABLE (VEX_W_0FED_P_2) },
5328 /* PREFIX_VEX_0FEE */
5332 { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5335 /* PREFIX_VEX_0FEF */
5339 { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5342 /* PREFIX_VEX_0FF0 */
5347 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5350 /* PREFIX_VEX_0FF1 */
5354 { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5357 /* PREFIX_VEX_0FF2 */
5361 { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5364 /* PREFIX_VEX_0FF3 */
5368 { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5371 /* PREFIX_VEX_0FF4 */
5375 { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5378 /* PREFIX_VEX_0FF5 */
5382 { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5385 /* PREFIX_VEX_0FF6 */
5389 { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5392 /* PREFIX_VEX_0FF7 */
5396 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5399 /* PREFIX_VEX_0FF8 */
5403 { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5406 /* PREFIX_VEX_0FF9 */
5410 { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5413 /* PREFIX_VEX_0FFA */
5417 { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5420 /* PREFIX_VEX_0FFB */
5424 { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5427 /* PREFIX_VEX_0FFC */
5431 { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5434 /* PREFIX_VEX_0FFD */
5438 { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5441 /* PREFIX_VEX_0FFE */
5445 { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5448 /* PREFIX_VEX_0F3800 */
5452 { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5455 /* PREFIX_VEX_0F3801 */
5459 { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5462 /* PREFIX_VEX_0F3802 */
5466 { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5469 /* PREFIX_VEX_0F3803 */
5473 { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5476 /* PREFIX_VEX_0F3804 */
5480 { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5483 /* PREFIX_VEX_0F3805 */
5487 { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5490 /* PREFIX_VEX_0F3806 */
5494 { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5497 /* PREFIX_VEX_0F3807 */
5501 { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5504 /* PREFIX_VEX_0F3808 */
5508 { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5511 /* PREFIX_VEX_0F3809 */
5515 { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5518 /* PREFIX_VEX_0F380A */
5522 { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5525 /* PREFIX_VEX_0F380B */
5529 { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5532 /* PREFIX_VEX_0F380C */
5536 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5539 /* PREFIX_VEX_0F380D */
5543 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5546 /* PREFIX_VEX_0F380E */
5550 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5553 /* PREFIX_VEX_0F380F */
5557 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5560 /* PREFIX_VEX_0F3813 */
5564 { "vcvtph2ps", { XM, EXxmmq }, 0 },
5567 /* PREFIX_VEX_0F3816 */
5571 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5574 /* PREFIX_VEX_0F3817 */
5578 { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5581 /* PREFIX_VEX_0F3818 */
5585 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5588 /* PREFIX_VEX_0F3819 */
5592 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5595 /* PREFIX_VEX_0F381A */
5599 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5602 /* PREFIX_VEX_0F381C */
5606 { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5609 /* PREFIX_VEX_0F381D */
5613 { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5616 /* PREFIX_VEX_0F381E */
5620 { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5623 /* PREFIX_VEX_0F3820 */
5627 { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5630 /* PREFIX_VEX_0F3821 */
5634 { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5637 /* PREFIX_VEX_0F3822 */
5641 { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5644 /* PREFIX_VEX_0F3823 */
5648 { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5651 /* PREFIX_VEX_0F3824 */
5655 { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5658 /* PREFIX_VEX_0F3825 */
5662 { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5665 /* PREFIX_VEX_0F3828 */
5669 { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5672 /* PREFIX_VEX_0F3829 */
5676 { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5679 /* PREFIX_VEX_0F382A */
5683 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5686 /* PREFIX_VEX_0F382B */
5690 { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5693 /* PREFIX_VEX_0F382C */
5697 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5700 /* PREFIX_VEX_0F382D */
5704 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5707 /* PREFIX_VEX_0F382E */
5711 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5714 /* PREFIX_VEX_0F382F */
5718 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5721 /* PREFIX_VEX_0F3830 */
5725 { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5728 /* PREFIX_VEX_0F3831 */
5732 { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5735 /* PREFIX_VEX_0F3832 */
5739 { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5742 /* PREFIX_VEX_0F3833 */
5746 { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5749 /* PREFIX_VEX_0F3834 */
5753 { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5756 /* PREFIX_VEX_0F3835 */
5760 { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5763 /* PREFIX_VEX_0F3836 */
5767 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5770 /* PREFIX_VEX_0F3837 */
5774 { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5777 /* PREFIX_VEX_0F3838 */
5781 { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5784 /* PREFIX_VEX_0F3839 */
5788 { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5791 /* PREFIX_VEX_0F383A */
5795 { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5798 /* PREFIX_VEX_0F383B */
5802 { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5805 /* PREFIX_VEX_0F383C */
5809 { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5812 /* PREFIX_VEX_0F383D */
5816 { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5819 /* PREFIX_VEX_0F383E */
5823 { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5826 /* PREFIX_VEX_0F383F */
5830 { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5833 /* PREFIX_VEX_0F3840 */
5837 { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5840 /* PREFIX_VEX_0F3841 */
5844 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5847 /* PREFIX_VEX_0F3845 */
5851 { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5854 /* PREFIX_VEX_0F3846 */
5858 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5861 /* PREFIX_VEX_0F3847 */
5865 { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5868 /* PREFIX_VEX_0F3858 */
5872 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5875 /* PREFIX_VEX_0F3859 */
5879 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5882 /* PREFIX_VEX_0F385A */
5886 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5889 /* PREFIX_VEX_0F3878 */
5893 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5896 /* PREFIX_VEX_0F3879 */
5900 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5903 /* PREFIX_VEX_0F388C */
5907 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5910 /* PREFIX_VEX_0F388E */
5914 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5917 /* PREFIX_VEX_0F3890 */
5921 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5924 /* PREFIX_VEX_0F3891 */
5928 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5931 /* PREFIX_VEX_0F3892 */
5935 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5938 /* PREFIX_VEX_0F3893 */
5942 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5945 /* PREFIX_VEX_0F3896 */
5949 { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
5952 /* PREFIX_VEX_0F3897 */
5956 { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
5959 /* PREFIX_VEX_0F3898 */
5963 { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
5966 /* PREFIX_VEX_0F3899 */
5970 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5973 /* PREFIX_VEX_0F389A */
5977 { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
5980 /* PREFIX_VEX_0F389B */
5984 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5987 /* PREFIX_VEX_0F389C */
5991 { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
5994 /* PREFIX_VEX_0F389D */
5998 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6001 /* PREFIX_VEX_0F389E */
6005 { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6008 /* PREFIX_VEX_0F389F */
6012 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6015 /* PREFIX_VEX_0F38A6 */
6019 { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6023 /* PREFIX_VEX_0F38A7 */
6027 { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6030 /* PREFIX_VEX_0F38A8 */
6034 { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6037 /* PREFIX_VEX_0F38A9 */
6041 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6044 /* PREFIX_VEX_0F38AA */
6048 { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6051 /* PREFIX_VEX_0F38AB */
6055 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6058 /* PREFIX_VEX_0F38AC */
6062 { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6065 /* PREFIX_VEX_0F38AD */
6069 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6072 /* PREFIX_VEX_0F38AE */
6076 { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6079 /* PREFIX_VEX_0F38AF */
6083 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6086 /* PREFIX_VEX_0F38B6 */
6090 { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6093 /* PREFIX_VEX_0F38B7 */
6097 { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6100 /* PREFIX_VEX_0F38B8 */
6104 { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6107 /* PREFIX_VEX_0F38B9 */
6111 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6114 /* PREFIX_VEX_0F38BA */
6118 { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6121 /* PREFIX_VEX_0F38BB */
6125 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6128 /* PREFIX_VEX_0F38BC */
6132 { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6135 /* PREFIX_VEX_0F38BD */
6139 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6142 /* PREFIX_VEX_0F38BE */
6146 { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6149 /* PREFIX_VEX_0F38BF */
6153 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6156 /* PREFIX_VEX_0F38DB */
6160 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6163 /* PREFIX_VEX_0F38DC */
6167 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6170 /* PREFIX_VEX_0F38DD */
6174 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6177 /* PREFIX_VEX_0F38DE */
6181 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6184 /* PREFIX_VEX_0F38DF */
6188 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6191 /* PREFIX_VEX_0F38F2 */
6193 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6196 /* PREFIX_VEX_0F38F3_REG_1 */
6198 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6201 /* PREFIX_VEX_0F38F3_REG_2 */
6203 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6206 /* PREFIX_VEX_0F38F3_REG_3 */
6208 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6211 /* PREFIX_VEX_0F38F5 */
6213 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6214 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6216 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6219 /* PREFIX_VEX_0F38F6 */
6224 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6227 /* PREFIX_VEX_0F38F7 */
6229 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6230 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6231 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6232 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6235 /* PREFIX_VEX_0F3A00 */
6239 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6242 /* PREFIX_VEX_0F3A01 */
6246 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6249 /* PREFIX_VEX_0F3A02 */
6253 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6256 /* PREFIX_VEX_0F3A04 */
6260 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6263 /* PREFIX_VEX_0F3A05 */
6267 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6270 /* PREFIX_VEX_0F3A06 */
6274 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6277 /* PREFIX_VEX_0F3A08 */
6281 { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6284 /* PREFIX_VEX_0F3A09 */
6288 { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6291 /* PREFIX_VEX_0F3A0A */
6295 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6298 /* PREFIX_VEX_0F3A0B */
6302 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6305 /* PREFIX_VEX_0F3A0C */
6309 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6312 /* PREFIX_VEX_0F3A0D */
6316 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6319 /* PREFIX_VEX_0F3A0E */
6323 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6326 /* PREFIX_VEX_0F3A0F */
6330 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6333 /* PREFIX_VEX_0F3A14 */
6337 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6340 /* PREFIX_VEX_0F3A15 */
6344 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6347 /* PREFIX_VEX_0F3A16 */
6351 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6354 /* PREFIX_VEX_0F3A17 */
6358 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6361 /* PREFIX_VEX_0F3A18 */
6365 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6368 /* PREFIX_VEX_0F3A19 */
6372 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6375 /* PREFIX_VEX_0F3A1D */
6379 { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6382 /* PREFIX_VEX_0F3A20 */
6386 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6389 /* PREFIX_VEX_0F3A21 */
6393 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6396 /* PREFIX_VEX_0F3A22 */
6400 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6403 /* PREFIX_VEX_0F3A30 */
6407 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6410 /* PREFIX_VEX_0F3A31 */
6414 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6417 /* PREFIX_VEX_0F3A32 */
6421 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6424 /* PREFIX_VEX_0F3A33 */
6428 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6431 /* PREFIX_VEX_0F3A38 */
6435 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6438 /* PREFIX_VEX_0F3A39 */
6442 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6445 /* PREFIX_VEX_0F3A40 */
6449 { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6452 /* PREFIX_VEX_0F3A41 */
6456 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6459 /* PREFIX_VEX_0F3A42 */
6463 { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6466 /* PREFIX_VEX_0F3A44 */
6470 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6473 /* PREFIX_VEX_0F3A46 */
6477 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6480 /* PREFIX_VEX_0F3A48 */
6484 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6487 /* PREFIX_VEX_0F3A49 */
6491 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6494 /* PREFIX_VEX_0F3A4A */
6498 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6501 /* PREFIX_VEX_0F3A4B */
6505 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6508 /* PREFIX_VEX_0F3A4C */
6512 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6515 /* PREFIX_VEX_0F3A5C */
6519 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6522 /* PREFIX_VEX_0F3A5D */
6526 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6529 /* PREFIX_VEX_0F3A5E */
6533 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6536 /* PREFIX_VEX_0F3A5F */
6540 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6543 /* PREFIX_VEX_0F3A60 */
6547 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6551 /* PREFIX_VEX_0F3A61 */
6555 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6558 /* PREFIX_VEX_0F3A62 */
6562 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6565 /* PREFIX_VEX_0F3A63 */
6569 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6572 /* PREFIX_VEX_0F3A68 */
6576 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6579 /* PREFIX_VEX_0F3A69 */
6583 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6586 /* PREFIX_VEX_0F3A6A */
6590 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6593 /* PREFIX_VEX_0F3A6B */
6597 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6600 /* PREFIX_VEX_0F3A6C */
6604 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6607 /* PREFIX_VEX_0F3A6D */
6611 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6614 /* PREFIX_VEX_0F3A6E */
6618 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6621 /* PREFIX_VEX_0F3A6F */
6625 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6628 /* PREFIX_VEX_0F3A78 */
6632 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6635 /* PREFIX_VEX_0F3A79 */
6639 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6642 /* PREFIX_VEX_0F3A7A */
6646 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6649 /* PREFIX_VEX_0F3A7B */
6653 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6656 /* PREFIX_VEX_0F3A7C */
6660 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6664 /* PREFIX_VEX_0F3A7D */
6668 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6671 /* PREFIX_VEX_0F3A7E */
6675 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6678 /* PREFIX_VEX_0F3A7F */
6682 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6685 /* PREFIX_VEX_0F3ADF */
6689 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6692 /* PREFIX_VEX_0F3AF0 */
6697 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6700 #define NEED_PREFIX_TABLE
6701 #include "i386-dis-evex.h"
6702 #undef NEED_PREFIX_TABLE
6705 static const struct dis386 x86_64_table[][2] = {
6708 { "pushP", { es }, 0 },
6713 { "popP", { es }, 0 },
6718 { "pushP", { cs }, 0 },
6723 { "pushP", { ss }, 0 },
6728 { "popP", { ss }, 0 },
6733 { "pushP", { ds }, 0 },
6738 { "popP", { ds }, 0 },
6743 { "daa", { XX }, 0 },
6748 { "das", { XX }, 0 },
6753 { "aaa", { XX }, 0 },
6758 { "aas", { XX }, 0 },
6763 { "pushaP", { XX }, 0 },
6768 { "popaP", { XX }, 0 },
6773 { MOD_TABLE (MOD_62_32BIT) },
6774 { EVEX_TABLE (EVEX_0F) },
6779 { "arpl", { Ew, Gw }, 0 },
6780 { "movs{lq|xd}", { Gv, Ed }, 0 },
6785 { "ins{R|}", { Yzr, indirDX }, 0 },
6786 { "ins{G|}", { Yzr, indirDX }, 0 },
6791 { "outs{R|}", { indirDXr, Xz }, 0 },
6792 { "outs{G|}", { indirDXr, Xz }, 0 },
6797 { "Jcall{T|}", { Ap }, 0 },
6802 { MOD_TABLE (MOD_C4_32BIT) },
6803 { VEX_C4_TABLE (VEX_0F) },
6808 { MOD_TABLE (MOD_C5_32BIT) },
6809 { VEX_C5_TABLE (VEX_0F) },
6814 { "into", { XX }, 0 },
6819 { "aam", { Ib }, 0 },
6824 { "aad", { Ib }, 0 },
6829 { "Jjmp{T|}", { Ap }, 0 },
6832 /* X86_64_0F01_REG_0 */
6834 { "sgdt{Q|IQ}", { M }, 0 },
6835 { "sgdt", { M }, 0 },
6838 /* X86_64_0F01_REG_1 */
6840 { "sidt{Q|IQ}", { M }, 0 },
6841 { "sidt", { M }, 0 },
6844 /* X86_64_0F01_REG_2 */
6846 { "lgdt{Q|Q}", { M }, 0 },
6847 { "lgdt", { M }, 0 },
6850 /* X86_64_0F01_REG_3 */
6852 { "lidt{Q|Q}", { M }, 0 },
6853 { "lidt", { M }, 0 },
6857 static const struct dis386 three_byte_table[][256] = {
6859 /* THREE_BYTE_0F38 */
6862 { "pshufb", { MX, EM }, PREFIX_OPCODE },
6863 { "phaddw", { MX, EM }, PREFIX_OPCODE },
6864 { "phaddd", { MX, EM }, PREFIX_OPCODE },
6865 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
6866 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
6867 { "phsubw", { MX, EM }, PREFIX_OPCODE },
6868 { "phsubd", { MX, EM }, PREFIX_OPCODE },
6869 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
6871 { "psignb", { MX, EM }, PREFIX_OPCODE },
6872 { "psignw", { MX, EM }, PREFIX_OPCODE },
6873 { "psignd", { MX, EM }, PREFIX_OPCODE },
6874 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
6880 { PREFIX_TABLE (PREFIX_0F3810) },
6884 { PREFIX_TABLE (PREFIX_0F3814) },
6885 { PREFIX_TABLE (PREFIX_0F3815) },
6887 { PREFIX_TABLE (PREFIX_0F3817) },
6893 { "pabsb", { MX, EM }, PREFIX_OPCODE },
6894 { "pabsw", { MX, EM }, PREFIX_OPCODE },
6895 { "pabsd", { MX, EM }, PREFIX_OPCODE },
6898 { PREFIX_TABLE (PREFIX_0F3820) },
6899 { PREFIX_TABLE (PREFIX_0F3821) },
6900 { PREFIX_TABLE (PREFIX_0F3822) },
6901 { PREFIX_TABLE (PREFIX_0F3823) },
6902 { PREFIX_TABLE (PREFIX_0F3824) },
6903 { PREFIX_TABLE (PREFIX_0F3825) },
6907 { PREFIX_TABLE (PREFIX_0F3828) },
6908 { PREFIX_TABLE (PREFIX_0F3829) },
6909 { PREFIX_TABLE (PREFIX_0F382A) },
6910 { PREFIX_TABLE (PREFIX_0F382B) },
6916 { PREFIX_TABLE (PREFIX_0F3830) },
6917 { PREFIX_TABLE (PREFIX_0F3831) },
6918 { PREFIX_TABLE (PREFIX_0F3832) },
6919 { PREFIX_TABLE (PREFIX_0F3833) },
6920 { PREFIX_TABLE (PREFIX_0F3834) },
6921 { PREFIX_TABLE (PREFIX_0F3835) },
6923 { PREFIX_TABLE (PREFIX_0F3837) },
6925 { PREFIX_TABLE (PREFIX_0F3838) },
6926 { PREFIX_TABLE (PREFIX_0F3839) },
6927 { PREFIX_TABLE (PREFIX_0F383A) },
6928 { PREFIX_TABLE (PREFIX_0F383B) },
6929 { PREFIX_TABLE (PREFIX_0F383C) },
6930 { PREFIX_TABLE (PREFIX_0F383D) },
6931 { PREFIX_TABLE (PREFIX_0F383E) },
6932 { PREFIX_TABLE (PREFIX_0F383F) },
6934 { PREFIX_TABLE (PREFIX_0F3840) },
6935 { PREFIX_TABLE (PREFIX_0F3841) },
7006 { PREFIX_TABLE (PREFIX_0F3880) },
7007 { PREFIX_TABLE (PREFIX_0F3881) },
7008 { PREFIX_TABLE (PREFIX_0F3882) },
7087 { PREFIX_TABLE (PREFIX_0F38C8) },
7088 { PREFIX_TABLE (PREFIX_0F38C9) },
7089 { PREFIX_TABLE (PREFIX_0F38CA) },
7090 { PREFIX_TABLE (PREFIX_0F38CB) },
7091 { PREFIX_TABLE (PREFIX_0F38CC) },
7092 { PREFIX_TABLE (PREFIX_0F38CD) },
7108 { PREFIX_TABLE (PREFIX_0F38DB) },
7109 { PREFIX_TABLE (PREFIX_0F38DC) },
7110 { PREFIX_TABLE (PREFIX_0F38DD) },
7111 { PREFIX_TABLE (PREFIX_0F38DE) },
7112 { PREFIX_TABLE (PREFIX_0F38DF) },
7132 { PREFIX_TABLE (PREFIX_0F38F0) },
7133 { PREFIX_TABLE (PREFIX_0F38F1) },
7138 { PREFIX_TABLE (PREFIX_0F38F6) },
7150 /* THREE_BYTE_0F3A */
7162 { PREFIX_TABLE (PREFIX_0F3A08) },
7163 { PREFIX_TABLE (PREFIX_0F3A09) },
7164 { PREFIX_TABLE (PREFIX_0F3A0A) },
7165 { PREFIX_TABLE (PREFIX_0F3A0B) },
7166 { PREFIX_TABLE (PREFIX_0F3A0C) },
7167 { PREFIX_TABLE (PREFIX_0F3A0D) },
7168 { PREFIX_TABLE (PREFIX_0F3A0E) },
7169 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
7175 { PREFIX_TABLE (PREFIX_0F3A14) },
7176 { PREFIX_TABLE (PREFIX_0F3A15) },
7177 { PREFIX_TABLE (PREFIX_0F3A16) },
7178 { PREFIX_TABLE (PREFIX_0F3A17) },
7189 { PREFIX_TABLE (PREFIX_0F3A20) },
7190 { PREFIX_TABLE (PREFIX_0F3A21) },
7191 { PREFIX_TABLE (PREFIX_0F3A22) },
7225 { PREFIX_TABLE (PREFIX_0F3A40) },
7226 { PREFIX_TABLE (PREFIX_0F3A41) },
7227 { PREFIX_TABLE (PREFIX_0F3A42) },
7229 { PREFIX_TABLE (PREFIX_0F3A44) },
7261 { PREFIX_TABLE (PREFIX_0F3A60) },
7262 { PREFIX_TABLE (PREFIX_0F3A61) },
7263 { PREFIX_TABLE (PREFIX_0F3A62) },
7264 { PREFIX_TABLE (PREFIX_0F3A63) },
7382 { PREFIX_TABLE (PREFIX_0F3ACC) },
7403 { PREFIX_TABLE (PREFIX_0F3ADF) },
7442 /* THREE_BYTE_0F7A */
7481 { "ptest", { XX }, PREFIX_OPCODE },
7518 { "phaddbw", { XM, EXq }, PREFIX_OPCODE },
7519 { "phaddbd", { XM, EXq }, PREFIX_OPCODE },
7520 { "phaddbq", { XM, EXq }, PREFIX_OPCODE },
7523 { "phaddwd", { XM, EXq }, PREFIX_OPCODE },
7524 { "phaddwq", { XM, EXq }, PREFIX_OPCODE },
7529 { "phadddq", { XM, EXq }, PREFIX_OPCODE },
7536 { "phaddubw", { XM, EXq }, PREFIX_OPCODE },
7537 { "phaddubd", { XM, EXq }, PREFIX_OPCODE },
7538 { "phaddubq", { XM, EXq }, PREFIX_OPCODE },
7541 { "phadduwd", { XM, EXq }, PREFIX_OPCODE },
7542 { "phadduwq", { XM, EXq }, PREFIX_OPCODE },
7547 { "phaddudq", { XM, EXq }, PREFIX_OPCODE },
7554 { "phsubbw", { XM, EXq }, PREFIX_OPCODE },
7555 { "phsubbd", { XM, EXq }, PREFIX_OPCODE },
7556 { "phsubbq", { XM, EXq }, PREFIX_OPCODE },
7735 static const struct dis386 xop_table[][256] = {
7888 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7889 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7890 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7898 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7899 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7906 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7907 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7908 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7916 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7917 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7921 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7922 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7925 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7943 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7955 { "vprotb", { XM, Vex_2src_1, Ib }, 0 },
7956 { "vprotw", { XM, Vex_2src_1, Ib }, 0 },
7957 { "vprotd", { XM, Vex_2src_1, Ib }, 0 },
7958 { "vprotq", { XM, Vex_2src_1, Ib }, 0 },
7968 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7969 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7970 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7971 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
8004 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8005 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8006 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8007 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8031 { REG_TABLE (REG_XOP_TBM_01) },
8032 { REG_TABLE (REG_XOP_TBM_02) },
8050 { REG_TABLE (REG_XOP_LWPCB) },
8174 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8175 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8176 { "vfrczss", { XM, EXd }, 0 },
8177 { "vfrczsd", { XM, EXq }, 0 },
8192 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8193 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8194 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8195 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8196 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8197 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8198 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8199 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8201 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8202 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8203 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8204 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8247 { "vphaddbw", { XM, EXxmm }, 0 },
8248 { "vphaddbd", { XM, EXxmm }, 0 },
8249 { "vphaddbq", { XM, EXxmm }, 0 },
8252 { "vphaddwd", { XM, EXxmm }, 0 },
8253 { "vphaddwq", { XM, EXxmm }, 0 },
8258 { "vphadddq", { XM, EXxmm }, 0 },
8265 { "vphaddubw", { XM, EXxmm }, 0 },
8266 { "vphaddubd", { XM, EXxmm }, 0 },
8267 { "vphaddubq", { XM, EXxmm }, 0 },
8270 { "vphadduwd", { XM, EXxmm }, 0 },
8271 { "vphadduwq", { XM, EXxmm }, 0 },
8276 { "vphaddudq", { XM, EXxmm }, 0 },
8283 { "vphsubbw", { XM, EXxmm }, 0 },
8284 { "vphsubwd", { XM, EXxmm }, 0 },
8285 { "vphsubdq", { XM, EXxmm }, 0 },
8339 { "bextr", { Gv, Ev, Iq }, 0 },
8341 { REG_TABLE (REG_XOP_LWP) },
8611 static const struct dis386 vex_table[][256] = {
8633 { PREFIX_TABLE (PREFIX_VEX_0F10) },
8634 { PREFIX_TABLE (PREFIX_VEX_0F11) },
8635 { PREFIX_TABLE (PREFIX_VEX_0F12) },
8636 { MOD_TABLE (MOD_VEX_0F13) },
8637 { VEX_W_TABLE (VEX_W_0F14) },
8638 { VEX_W_TABLE (VEX_W_0F15) },
8639 { PREFIX_TABLE (PREFIX_VEX_0F16) },
8640 { MOD_TABLE (MOD_VEX_0F17) },
8660 { VEX_W_TABLE (VEX_W_0F28) },
8661 { VEX_W_TABLE (VEX_W_0F29) },
8662 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8663 { MOD_TABLE (MOD_VEX_0F2B) },
8664 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8665 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8666 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8667 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8688 { PREFIX_TABLE (PREFIX_VEX_0F41) },
8689 { PREFIX_TABLE (PREFIX_VEX_0F42) },
8691 { PREFIX_TABLE (PREFIX_VEX_0F44) },
8692 { PREFIX_TABLE (PREFIX_VEX_0F45) },
8693 { PREFIX_TABLE (PREFIX_VEX_0F46) },
8694 { PREFIX_TABLE (PREFIX_VEX_0F47) },
8698 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8699 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8705 { MOD_TABLE (MOD_VEX_0F50) },
8706 { PREFIX_TABLE (PREFIX_VEX_0F51) },
8707 { PREFIX_TABLE (PREFIX_VEX_0F52) },
8708 { PREFIX_TABLE (PREFIX_VEX_0F53) },
8709 { "vandpX", { XM, Vex, EXx }, 0 },
8710 { "vandnpX", { XM, Vex, EXx }, 0 },
8711 { "vorpX", { XM, Vex, EXx }, 0 },
8712 { "vxorpX", { XM, Vex, EXx }, 0 },
8714 { PREFIX_TABLE (PREFIX_VEX_0F58) },
8715 { PREFIX_TABLE (PREFIX_VEX_0F59) },
8716 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8717 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8718 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8719 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8720 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8721 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8723 { PREFIX_TABLE (PREFIX_VEX_0F60) },
8724 { PREFIX_TABLE (PREFIX_VEX_0F61) },
8725 { PREFIX_TABLE (PREFIX_VEX_0F62) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F63) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F64) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F65) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F66) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F67) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F68) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F69) },
8734 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8735 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8736 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8741 { PREFIX_TABLE (PREFIX_VEX_0F70) },
8742 { REG_TABLE (REG_VEX_0F71) },
8743 { REG_TABLE (REG_VEX_0F72) },
8744 { REG_TABLE (REG_VEX_0F73) },
8745 { PREFIX_TABLE (PREFIX_VEX_0F74) },
8746 { PREFIX_TABLE (PREFIX_VEX_0F75) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F76) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F77) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F90) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F91) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F92) },
8780 { PREFIX_TABLE (PREFIX_VEX_0F93) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F98) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F99) },
8810 { REG_TABLE (REG_VEX_0FAE) },
8833 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8835 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8836 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8837 { "vshufpX", { XM, Vex, EXx, Ib }, 0 },
8849 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8850 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8851 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8852 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8853 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8854 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8855 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8856 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8858 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8859 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8860 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8861 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8862 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8863 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8864 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8865 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8867 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8868 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8869 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8870 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8871 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8872 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8873 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8874 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8876 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8877 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8878 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8879 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8880 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8881 { PREFIX_TABLE (PREFIX_VEX_0FED) },
8882 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8883 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8885 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8886 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8887 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8888 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8889 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8890 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8891 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8892 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8894 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8895 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8896 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8897 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8898 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8899 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8900 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8907 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8909 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8927 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8954 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8956 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8957 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8960 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8961 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8962 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8963 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8964 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8965 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8966 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8967 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8969 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8972 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8973 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8974 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8975 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8976 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8978 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8979 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8983 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8984 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8985 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
9005 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9006 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9063 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9065 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9068 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9077 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9078 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9079 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9080 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9081 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9082 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9083 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9084 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9096 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9098 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9099 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9101 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9102 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9110 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9111 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9113 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9114 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9115 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9116 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9117 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9118 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9119 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9120 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9152 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9153 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9154 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9155 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9156 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9178 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9179 { REG_TABLE (REG_VEX_0F38F3) },
9181 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9182 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9183 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9197 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9198 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9199 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9201 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9202 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9203 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9206 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9207 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9208 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9209 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9210 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9211 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9212 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9213 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9219 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9220 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9221 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9222 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9224 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9225 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9229 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9233 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9234 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9235 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9251 { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9252 { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9253 { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9254 { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9260 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9261 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9269 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9270 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9271 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9273 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9275 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9278 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9279 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9280 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9281 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9282 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9300 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9301 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9302 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9303 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9305 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9306 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9307 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9308 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9314 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9315 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9316 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9317 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9318 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9319 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9320 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9321 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9332 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9333 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9334 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9335 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9336 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9337 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9338 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9339 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9447 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9467 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9487 #define NEED_OPCODE_TABLE
9488 #include "i386-dis-evex.h"
9489 #undef NEED_OPCODE_TABLE
9490 static const struct dis386 vex_len_table[][2] = {
9491 /* VEX_LEN_0F10_P_1 */
9493 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9494 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9497 /* VEX_LEN_0F10_P_3 */
9499 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9500 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9503 /* VEX_LEN_0F11_P_1 */
9505 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9506 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9509 /* VEX_LEN_0F11_P_3 */
9511 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9512 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9515 /* VEX_LEN_0F12_P_0_M_0 */
9517 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9520 /* VEX_LEN_0F12_P_0_M_1 */
9522 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9525 /* VEX_LEN_0F12_P_2 */
9527 { VEX_W_TABLE (VEX_W_0F12_P_2) },
9530 /* VEX_LEN_0F13_M_0 */
9532 { VEX_W_TABLE (VEX_W_0F13_M_0) },
9535 /* VEX_LEN_0F16_P_0_M_0 */
9537 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9540 /* VEX_LEN_0F16_P_0_M_1 */
9542 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9545 /* VEX_LEN_0F16_P_2 */
9547 { VEX_W_TABLE (VEX_W_0F16_P_2) },
9550 /* VEX_LEN_0F17_M_0 */
9552 { VEX_W_TABLE (VEX_W_0F17_M_0) },
9555 /* VEX_LEN_0F2A_P_1 */
9557 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9558 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9561 /* VEX_LEN_0F2A_P_3 */
9563 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9564 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9567 /* VEX_LEN_0F2C_P_1 */
9569 { "vcvttss2siY", { Gv, EXdScalar }, 0 },
9570 { "vcvttss2siY", { Gv, EXdScalar }, 0 },
9573 /* VEX_LEN_0F2C_P_3 */
9575 { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
9576 { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
9579 /* VEX_LEN_0F2D_P_1 */
9581 { "vcvtss2siY", { Gv, EXdScalar }, 0 },
9582 { "vcvtss2siY", { Gv, EXdScalar }, 0 },
9585 /* VEX_LEN_0F2D_P_3 */
9587 { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
9588 { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
9591 /* VEX_LEN_0F2E_P_0 */
9593 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9594 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9597 /* VEX_LEN_0F2E_P_2 */
9599 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9600 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9603 /* VEX_LEN_0F2F_P_0 */
9605 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9606 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9609 /* VEX_LEN_0F2F_P_2 */
9611 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9612 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9615 /* VEX_LEN_0F41_P_0 */
9618 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9620 /* VEX_LEN_0F41_P_2 */
9623 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9625 /* VEX_LEN_0F42_P_0 */
9628 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9630 /* VEX_LEN_0F42_P_2 */
9633 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9635 /* VEX_LEN_0F44_P_0 */
9637 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9639 /* VEX_LEN_0F44_P_2 */
9641 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9643 /* VEX_LEN_0F45_P_0 */
9646 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9648 /* VEX_LEN_0F45_P_2 */
9651 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9653 /* VEX_LEN_0F46_P_0 */
9656 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9658 /* VEX_LEN_0F46_P_2 */
9661 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9663 /* VEX_LEN_0F47_P_0 */
9666 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9668 /* VEX_LEN_0F47_P_2 */
9671 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9673 /* VEX_LEN_0F4A_P_0 */
9676 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9678 /* VEX_LEN_0F4A_P_2 */
9681 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9683 /* VEX_LEN_0F4B_P_0 */
9686 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9688 /* VEX_LEN_0F4B_P_2 */
9691 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9694 /* VEX_LEN_0F51_P_1 */
9696 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9697 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9700 /* VEX_LEN_0F51_P_3 */
9702 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9703 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9706 /* VEX_LEN_0F52_P_1 */
9708 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9709 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9712 /* VEX_LEN_0F53_P_1 */
9714 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9715 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9718 /* VEX_LEN_0F58_P_1 */
9720 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9721 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9724 /* VEX_LEN_0F58_P_3 */
9726 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9727 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9730 /* VEX_LEN_0F59_P_1 */
9732 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9733 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9736 /* VEX_LEN_0F59_P_3 */
9738 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9739 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9742 /* VEX_LEN_0F5A_P_1 */
9744 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9745 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9748 /* VEX_LEN_0F5A_P_3 */
9750 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9751 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9754 /* VEX_LEN_0F5C_P_1 */
9756 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9757 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9760 /* VEX_LEN_0F5C_P_3 */
9762 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9763 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9766 /* VEX_LEN_0F5D_P_1 */
9768 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9769 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9772 /* VEX_LEN_0F5D_P_3 */
9774 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9775 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9778 /* VEX_LEN_0F5E_P_1 */
9780 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9781 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9784 /* VEX_LEN_0F5E_P_3 */
9786 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9787 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9790 /* VEX_LEN_0F5F_P_1 */
9792 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9793 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9796 /* VEX_LEN_0F5F_P_3 */
9798 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9799 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9802 /* VEX_LEN_0F6E_P_2 */
9804 { "vmovK", { XMScalar, Edq }, 0 },
9805 { "vmovK", { XMScalar, Edq }, 0 },
9808 /* VEX_LEN_0F7E_P_1 */
9810 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9811 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9814 /* VEX_LEN_0F7E_P_2 */
9816 { "vmovK", { Edq, XMScalar }, 0 },
9817 { "vmovK", { Edq, XMScalar }, 0 },
9820 /* VEX_LEN_0F90_P_0 */
9822 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9825 /* VEX_LEN_0F90_P_2 */
9827 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9830 /* VEX_LEN_0F91_P_0 */
9832 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9835 /* VEX_LEN_0F91_P_2 */
9837 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9840 /* VEX_LEN_0F92_P_0 */
9842 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9845 /* VEX_LEN_0F92_P_2 */
9847 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9850 /* VEX_LEN_0F92_P_3 */
9852 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9855 /* VEX_LEN_0F93_P_0 */
9857 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9860 /* VEX_LEN_0F93_P_2 */
9862 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9865 /* VEX_LEN_0F93_P_3 */
9867 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9870 /* VEX_LEN_0F98_P_0 */
9872 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9875 /* VEX_LEN_0F98_P_2 */
9877 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9880 /* VEX_LEN_0F99_P_0 */
9882 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9885 /* VEX_LEN_0F99_P_2 */
9887 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9890 /* VEX_LEN_0FAE_R_2_M_0 */
9892 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9895 /* VEX_LEN_0FAE_R_3_M_0 */
9897 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9900 /* VEX_LEN_0FC2_P_1 */
9902 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9903 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9906 /* VEX_LEN_0FC2_P_3 */
9908 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9909 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9912 /* VEX_LEN_0FC4_P_2 */
9914 { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9917 /* VEX_LEN_0FC5_P_2 */
9919 { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9922 /* VEX_LEN_0FD6_P_2 */
9924 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9925 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9928 /* VEX_LEN_0FF7_P_2 */
9930 { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9933 /* VEX_LEN_0F3816_P_2 */
9936 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9939 /* VEX_LEN_0F3819_P_2 */
9942 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9945 /* VEX_LEN_0F381A_P_2_M_0 */
9948 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9951 /* VEX_LEN_0F3836_P_2 */
9954 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9957 /* VEX_LEN_0F3841_P_2 */
9959 { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9962 /* VEX_LEN_0F385A_P_2_M_0 */
9965 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9968 /* VEX_LEN_0F38DB_P_2 */
9970 { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9973 /* VEX_LEN_0F38DC_P_2 */
9975 { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9978 /* VEX_LEN_0F38DD_P_2 */
9980 { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9983 /* VEX_LEN_0F38DE_P_2 */
9985 { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9988 /* VEX_LEN_0F38DF_P_2 */
9990 { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9993 /* VEX_LEN_0F38F2_P_0 */
9995 { "andnS", { Gdq, VexGdq, Edq }, 0 },
9998 /* VEX_LEN_0F38F3_R_1_P_0 */
10000 { "blsrS", { VexGdq, Edq }, 0 },
10003 /* VEX_LEN_0F38F3_R_2_P_0 */
10005 { "blsmskS", { VexGdq, Edq }, 0 },
10008 /* VEX_LEN_0F38F3_R_3_P_0 */
10010 { "blsiS", { VexGdq, Edq }, 0 },
10013 /* VEX_LEN_0F38F5_P_0 */
10015 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
10018 /* VEX_LEN_0F38F5_P_1 */
10020 { "pextS", { Gdq, VexGdq, Edq }, 0 },
10023 /* VEX_LEN_0F38F5_P_3 */
10025 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
10028 /* VEX_LEN_0F38F6_P_3 */
10030 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
10033 /* VEX_LEN_0F38F7_P_0 */
10035 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
10038 /* VEX_LEN_0F38F7_P_1 */
10040 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
10043 /* VEX_LEN_0F38F7_P_2 */
10045 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
10048 /* VEX_LEN_0F38F7_P_3 */
10050 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
10053 /* VEX_LEN_0F3A00_P_2 */
10056 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10059 /* VEX_LEN_0F3A01_P_2 */
10062 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10065 /* VEX_LEN_0F3A06_P_2 */
10068 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10071 /* VEX_LEN_0F3A0A_P_2 */
10073 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10074 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10077 /* VEX_LEN_0F3A0B_P_2 */
10079 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10080 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10083 /* VEX_LEN_0F3A14_P_2 */
10085 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10088 /* VEX_LEN_0F3A15_P_2 */
10090 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10093 /* VEX_LEN_0F3A16_P_2 */
10095 { "vpextrK", { Edq, XM, Ib }, 0 },
10098 /* VEX_LEN_0F3A17_P_2 */
10100 { "vextractps", { Edqd, XM, Ib }, 0 },
10103 /* VEX_LEN_0F3A18_P_2 */
10106 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10109 /* VEX_LEN_0F3A19_P_2 */
10112 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10115 /* VEX_LEN_0F3A20_P_2 */
10117 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10120 /* VEX_LEN_0F3A21_P_2 */
10122 { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10125 /* VEX_LEN_0F3A22_P_2 */
10127 { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 },
10130 /* VEX_LEN_0F3A30_P_2 */
10132 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10135 /* VEX_LEN_0F3A31_P_2 */
10137 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10140 /* VEX_LEN_0F3A32_P_2 */
10142 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10145 /* VEX_LEN_0F3A33_P_2 */
10147 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10150 /* VEX_LEN_0F3A38_P_2 */
10153 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10156 /* VEX_LEN_0F3A39_P_2 */
10159 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10162 /* VEX_LEN_0F3A41_P_2 */
10164 { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10167 /* VEX_LEN_0F3A44_P_2 */
10169 { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10172 /* VEX_LEN_0F3A46_P_2 */
10175 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10178 /* VEX_LEN_0F3A60_P_2 */
10180 { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10183 /* VEX_LEN_0F3A61_P_2 */
10185 { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10188 /* VEX_LEN_0F3A62_P_2 */
10190 { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10193 /* VEX_LEN_0F3A63_P_2 */
10195 { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10198 /* VEX_LEN_0F3A6A_P_2 */
10200 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10203 /* VEX_LEN_0F3A6B_P_2 */
10205 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10208 /* VEX_LEN_0F3A6E_P_2 */
10210 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10213 /* VEX_LEN_0F3A6F_P_2 */
10215 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10218 /* VEX_LEN_0F3A7A_P_2 */
10220 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10223 /* VEX_LEN_0F3A7B_P_2 */
10225 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10228 /* VEX_LEN_0F3A7E_P_2 */
10230 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10233 /* VEX_LEN_0F3A7F_P_2 */
10235 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10238 /* VEX_LEN_0F3ADF_P_2 */
10240 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10243 /* VEX_LEN_0F3AF0_P_3 */
10245 { "rorxS", { Gdq, Edq, Ib }, 0 },
10248 /* VEX_LEN_0FXOP_08_CC */
10250 { "vpcomb", { XM, Vex128, EXx, Ib }, 0 },
10253 /* VEX_LEN_0FXOP_08_CD */
10255 { "vpcomw", { XM, Vex128, EXx, Ib }, 0 },
10258 /* VEX_LEN_0FXOP_08_CE */
10260 { "vpcomd", { XM, Vex128, EXx, Ib }, 0 },
10263 /* VEX_LEN_0FXOP_08_CF */
10265 { "vpcomq", { XM, Vex128, EXx, Ib }, 0 },
10268 /* VEX_LEN_0FXOP_08_EC */
10270 { "vpcomub", { XM, Vex128, EXx, Ib }, 0 },
10273 /* VEX_LEN_0FXOP_08_ED */
10275 { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 },
10278 /* VEX_LEN_0FXOP_08_EE */
10280 { "vpcomud", { XM, Vex128, EXx, Ib }, 0 },
10283 /* VEX_LEN_0FXOP_08_EF */
10285 { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 },
10288 /* VEX_LEN_0FXOP_09_80 */
10290 { "vfrczps", { XM, EXxmm }, 0 },
10291 { "vfrczps", { XM, EXymmq }, 0 },
10294 /* VEX_LEN_0FXOP_09_81 */
10296 { "vfrczpd", { XM, EXxmm }, 0 },
10297 { "vfrczpd", { XM, EXymmq }, 0 },
10301 static const struct dis386 vex_w_table[][2] = {
10303 /* VEX_W_0F10_P_0 */
10304 { "vmovups", { XM, EXx }, 0 },
10307 /* VEX_W_0F10_P_1 */
10308 { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
10311 /* VEX_W_0F10_P_2 */
10312 { "vmovupd", { XM, EXx }, 0 },
10315 /* VEX_W_0F10_P_3 */
10316 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
10319 /* VEX_W_0F11_P_0 */
10320 { "vmovups", { EXxS, XM }, 0 },
10323 /* VEX_W_0F11_P_1 */
10324 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10327 /* VEX_W_0F11_P_2 */
10328 { "vmovupd", { EXxS, XM }, 0 },
10331 /* VEX_W_0F11_P_3 */
10332 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10335 /* VEX_W_0F12_P_0_M_0 */
10336 { "vmovlps", { XM, Vex128, EXq }, 0 },
10339 /* VEX_W_0F12_P_0_M_1 */
10340 { "vmovhlps", { XM, Vex128, EXq }, 0 },
10343 /* VEX_W_0F12_P_1 */
10344 { "vmovsldup", { XM, EXx }, 0 },
10347 /* VEX_W_0F12_P_2 */
10348 { "vmovlpd", { XM, Vex128, EXq }, 0 },
10351 /* VEX_W_0F12_P_3 */
10352 { "vmovddup", { XM, EXymmq }, 0 },
10355 /* VEX_W_0F13_M_0 */
10356 { "vmovlpX", { EXq, XM }, 0 },
10360 { "vunpcklpX", { XM, Vex, EXx }, 0 },
10364 { "vunpckhpX", { XM, Vex, EXx }, 0 },
10367 /* VEX_W_0F16_P_0_M_0 */
10368 { "vmovhps", { XM, Vex128, EXq }, 0 },
10371 /* VEX_W_0F16_P_0_M_1 */
10372 { "vmovlhps", { XM, Vex128, EXq }, 0 },
10375 /* VEX_W_0F16_P_1 */
10376 { "vmovshdup", { XM, EXx }, 0 },
10379 /* VEX_W_0F16_P_2 */
10380 { "vmovhpd", { XM, Vex128, EXq }, 0 },
10383 /* VEX_W_0F17_M_0 */
10384 { "vmovhpX", { EXq, XM }, 0 },
10388 { "vmovapX", { XM, EXx }, 0 },
10392 { "vmovapX", { EXxS, XM }, 0 },
10395 /* VEX_W_0F2B_M_0 */
10396 { "vmovntpX", { Mx, XM }, 0 },
10399 /* VEX_W_0F2E_P_0 */
10400 { "vucomiss", { XMScalar, EXdScalar }, 0 },
10403 /* VEX_W_0F2E_P_2 */
10404 { "vucomisd", { XMScalar, EXqScalar }, 0 },
10407 /* VEX_W_0F2F_P_0 */
10408 { "vcomiss", { XMScalar, EXdScalar }, 0 },
10411 /* VEX_W_0F2F_P_2 */
10412 { "vcomisd", { XMScalar, EXqScalar }, 0 },
10415 /* VEX_W_0F41_P_0_LEN_1 */
10416 { "kandw", { MaskG, MaskVex, MaskR }, 0 },
10417 { "kandq", { MaskG, MaskVex, MaskR }, 0 },
10420 /* VEX_W_0F41_P_2_LEN_1 */
10421 { "kandb", { MaskG, MaskVex, MaskR }, 0 },
10422 { "kandd", { MaskG, MaskVex, MaskR }, 0 },
10425 /* VEX_W_0F42_P_0_LEN_1 */
10426 { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
10427 { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
10430 /* VEX_W_0F42_P_2_LEN_1 */
10431 { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
10432 { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
10435 /* VEX_W_0F44_P_0_LEN_0 */
10436 { "knotw", { MaskG, MaskR }, 0 },
10437 { "knotq", { MaskG, MaskR }, 0 },
10440 /* VEX_W_0F44_P_2_LEN_0 */
10441 { "knotb", { MaskG, MaskR }, 0 },
10442 { "knotd", { MaskG, MaskR }, 0 },
10445 /* VEX_W_0F45_P_0_LEN_1 */
10446 { "korw", { MaskG, MaskVex, MaskR }, 0 },
10447 { "korq", { MaskG, MaskVex, MaskR }, 0 },
10450 /* VEX_W_0F45_P_2_LEN_1 */
10451 { "korb", { MaskG, MaskVex, MaskR }, 0 },
10452 { "kord", { MaskG, MaskVex, MaskR }, 0 },
10455 /* VEX_W_0F46_P_0_LEN_1 */
10456 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
10457 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
10460 /* VEX_W_0F46_P_2_LEN_1 */
10461 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
10462 { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
10465 /* VEX_W_0F47_P_0_LEN_1 */
10466 { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
10467 { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
10470 /* VEX_W_0F47_P_2_LEN_1 */
10471 { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
10472 { "kxord", { MaskG, MaskVex, MaskR }, 0 },
10475 /* VEX_W_0F4A_P_0_LEN_1 */
10476 { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
10477 { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
10480 /* VEX_W_0F4A_P_2_LEN_1 */
10481 { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
10482 { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
10485 /* VEX_W_0F4B_P_0_LEN_1 */
10486 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
10487 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
10490 /* VEX_W_0F4B_P_2_LEN_1 */
10491 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
10494 /* VEX_W_0F50_M_0 */
10495 { "vmovmskpX", { Gdq, XS }, 0 },
10498 /* VEX_W_0F51_P_0 */
10499 { "vsqrtps", { XM, EXx }, 0 },
10502 /* VEX_W_0F51_P_1 */
10503 { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10506 /* VEX_W_0F51_P_2 */
10507 { "vsqrtpd", { XM, EXx }, 0 },
10510 /* VEX_W_0F51_P_3 */
10511 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10514 /* VEX_W_0F52_P_0 */
10515 { "vrsqrtps", { XM, EXx }, 0 },
10518 /* VEX_W_0F52_P_1 */
10519 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10522 /* VEX_W_0F53_P_0 */
10523 { "vrcpps", { XM, EXx }, 0 },
10526 /* VEX_W_0F53_P_1 */
10527 { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
10530 /* VEX_W_0F58_P_0 */
10531 { "vaddps", { XM, Vex, EXx }, 0 },
10534 /* VEX_W_0F58_P_1 */
10535 { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
10538 /* VEX_W_0F58_P_2 */
10539 { "vaddpd", { XM, Vex, EXx }, 0 },
10542 /* VEX_W_0F58_P_3 */
10543 { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10546 /* VEX_W_0F59_P_0 */
10547 { "vmulps", { XM, Vex, EXx }, 0 },
10550 /* VEX_W_0F59_P_1 */
10551 { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
10554 /* VEX_W_0F59_P_2 */
10555 { "vmulpd", { XM, Vex, EXx }, 0 },
10558 /* VEX_W_0F59_P_3 */
10559 { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10562 /* VEX_W_0F5A_P_0 */
10563 { "vcvtps2pd", { XM, EXxmmq }, 0 },
10566 /* VEX_W_0F5A_P_1 */
10567 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
10570 /* VEX_W_0F5A_P_3 */
10571 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
10574 /* VEX_W_0F5B_P_0 */
10575 { "vcvtdq2ps", { XM, EXx }, 0 },
10578 /* VEX_W_0F5B_P_1 */
10579 { "vcvttps2dq", { XM, EXx }, 0 },
10582 /* VEX_W_0F5B_P_2 */
10583 { "vcvtps2dq", { XM, EXx }, 0 },
10586 /* VEX_W_0F5C_P_0 */
10587 { "vsubps", { XM, Vex, EXx }, 0 },
10590 /* VEX_W_0F5C_P_1 */
10591 { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
10594 /* VEX_W_0F5C_P_2 */
10595 { "vsubpd", { XM, Vex, EXx }, 0 },
10598 /* VEX_W_0F5C_P_3 */
10599 { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10602 /* VEX_W_0F5D_P_0 */
10603 { "vminps", { XM, Vex, EXx }, 0 },
10606 /* VEX_W_0F5D_P_1 */
10607 { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
10610 /* VEX_W_0F5D_P_2 */
10611 { "vminpd", { XM, Vex, EXx }, 0 },
10614 /* VEX_W_0F5D_P_3 */
10615 { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10618 /* VEX_W_0F5E_P_0 */
10619 { "vdivps", { XM, Vex, EXx }, 0 },
10622 /* VEX_W_0F5E_P_1 */
10623 { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
10626 /* VEX_W_0F5E_P_2 */
10627 { "vdivpd", { XM, Vex, EXx }, 0 },
10630 /* VEX_W_0F5E_P_3 */
10631 { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10634 /* VEX_W_0F5F_P_0 */
10635 { "vmaxps", { XM, Vex, EXx }, 0 },
10638 /* VEX_W_0F5F_P_1 */
10639 { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
10642 /* VEX_W_0F5F_P_2 */
10643 { "vmaxpd", { XM, Vex, EXx }, 0 },
10646 /* VEX_W_0F5F_P_3 */
10647 { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10650 /* VEX_W_0F60_P_2 */
10651 { "vpunpcklbw", { XM, Vex, EXx }, 0 },
10654 /* VEX_W_0F61_P_2 */
10655 { "vpunpcklwd", { XM, Vex, EXx }, 0 },
10658 /* VEX_W_0F62_P_2 */
10659 { "vpunpckldq", { XM, Vex, EXx }, 0 },
10662 /* VEX_W_0F63_P_2 */
10663 { "vpacksswb", { XM, Vex, EXx }, 0 },
10666 /* VEX_W_0F64_P_2 */
10667 { "vpcmpgtb", { XM, Vex, EXx }, 0 },
10670 /* VEX_W_0F65_P_2 */
10671 { "vpcmpgtw", { XM, Vex, EXx }, 0 },
10674 /* VEX_W_0F66_P_2 */
10675 { "vpcmpgtd", { XM, Vex, EXx }, 0 },
10678 /* VEX_W_0F67_P_2 */
10679 { "vpackuswb", { XM, Vex, EXx }, 0 },
10682 /* VEX_W_0F68_P_2 */
10683 { "vpunpckhbw", { XM, Vex, EXx }, 0 },
10686 /* VEX_W_0F69_P_2 */
10687 { "vpunpckhwd", { XM, Vex, EXx }, 0 },
10690 /* VEX_W_0F6A_P_2 */
10691 { "vpunpckhdq", { XM, Vex, EXx }, 0 },
10694 /* VEX_W_0F6B_P_2 */
10695 { "vpackssdw", { XM, Vex, EXx }, 0 },
10698 /* VEX_W_0F6C_P_2 */
10699 { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
10702 /* VEX_W_0F6D_P_2 */
10703 { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
10706 /* VEX_W_0F6F_P_1 */
10707 { "vmovdqu", { XM, EXx }, 0 },
10710 /* VEX_W_0F6F_P_2 */
10711 { "vmovdqa", { XM, EXx }, 0 },
10714 /* VEX_W_0F70_P_1 */
10715 { "vpshufhw", { XM, EXx, Ib }, 0 },
10718 /* VEX_W_0F70_P_2 */
10719 { "vpshufd", { XM, EXx, Ib }, 0 },
10722 /* VEX_W_0F70_P_3 */
10723 { "vpshuflw", { XM, EXx, Ib }, 0 },
10726 /* VEX_W_0F71_R_2_P_2 */
10727 { "vpsrlw", { Vex, XS, Ib }, 0 },
10730 /* VEX_W_0F71_R_4_P_2 */
10731 { "vpsraw", { Vex, XS, Ib }, 0 },
10734 /* VEX_W_0F71_R_6_P_2 */
10735 { "vpsllw", { Vex, XS, Ib }, 0 },
10738 /* VEX_W_0F72_R_2_P_2 */
10739 { "vpsrld", { Vex, XS, Ib }, 0 },
10742 /* VEX_W_0F72_R_4_P_2 */
10743 { "vpsrad", { Vex, XS, Ib }, 0 },
10746 /* VEX_W_0F72_R_6_P_2 */
10747 { "vpslld", { Vex, XS, Ib }, 0 },
10750 /* VEX_W_0F73_R_2_P_2 */
10751 { "vpsrlq", { Vex, XS, Ib }, 0 },
10754 /* VEX_W_0F73_R_3_P_2 */
10755 { "vpsrldq", { Vex, XS, Ib }, 0 },
10758 /* VEX_W_0F73_R_6_P_2 */
10759 { "vpsllq", { Vex, XS, Ib }, 0 },
10762 /* VEX_W_0F73_R_7_P_2 */
10763 { "vpslldq", { Vex, XS, Ib }, 0 },
10766 /* VEX_W_0F74_P_2 */
10767 { "vpcmpeqb", { XM, Vex, EXx }, 0 },
10770 /* VEX_W_0F75_P_2 */
10771 { "vpcmpeqw", { XM, Vex, EXx }, 0 },
10774 /* VEX_W_0F76_P_2 */
10775 { "vpcmpeqd", { XM, Vex, EXx }, 0 },
10778 /* VEX_W_0F77_P_0 */
10779 { "", { VZERO }, 0 },
10782 /* VEX_W_0F7C_P_2 */
10783 { "vhaddpd", { XM, Vex, EXx }, 0 },
10786 /* VEX_W_0F7C_P_3 */
10787 { "vhaddps", { XM, Vex, EXx }, 0 },
10790 /* VEX_W_0F7D_P_2 */
10791 { "vhsubpd", { XM, Vex, EXx }, 0 },
10794 /* VEX_W_0F7D_P_3 */
10795 { "vhsubps", { XM, Vex, EXx }, 0 },
10798 /* VEX_W_0F7E_P_1 */
10799 { "vmovq", { XMScalar, EXqScalar }, 0 },
10802 /* VEX_W_0F7F_P_1 */
10803 { "vmovdqu", { EXxS, XM }, 0 },
10806 /* VEX_W_0F7F_P_2 */
10807 { "vmovdqa", { EXxS, XM }, 0 },
10810 /* VEX_W_0F90_P_0_LEN_0 */
10811 { "kmovw", { MaskG, MaskE }, 0 },
10812 { "kmovq", { MaskG, MaskE }, 0 },
10815 /* VEX_W_0F90_P_2_LEN_0 */
10816 { "kmovb", { MaskG, MaskBDE }, 0 },
10817 { "kmovd", { MaskG, MaskBDE }, 0 },
10820 /* VEX_W_0F91_P_0_LEN_0 */
10821 { "kmovw", { Ew, MaskG }, 0 },
10822 { "kmovq", { Eq, MaskG }, 0 },
10825 /* VEX_W_0F91_P_2_LEN_0 */
10826 { "kmovb", { Eb, MaskG }, 0 },
10827 { "kmovd", { Ed, MaskG }, 0 },
10830 /* VEX_W_0F92_P_0_LEN_0 */
10831 { "kmovw", { MaskG, Rdq }, 0 },
10834 /* VEX_W_0F92_P_2_LEN_0 */
10835 { "kmovb", { MaskG, Rdq }, 0 },
10838 /* VEX_W_0F92_P_3_LEN_0 */
10839 { "kmovd", { MaskG, Rdq }, 0 },
10840 { "kmovq", { MaskG, Rdq }, 0 },
10843 /* VEX_W_0F93_P_0_LEN_0 */
10844 { "kmovw", { Gdq, MaskR }, 0 },
10847 /* VEX_W_0F93_P_2_LEN_0 */
10848 { "kmovb", { Gdq, MaskR }, 0 },
10851 /* VEX_W_0F93_P_3_LEN_0 */
10852 { "kmovd", { Gdq, MaskR }, 0 },
10853 { "kmovq", { Gdq, MaskR }, 0 },
10856 /* VEX_W_0F98_P_0_LEN_0 */
10857 { "kortestw", { MaskG, MaskR }, 0 },
10858 { "kortestq", { MaskG, MaskR }, 0 },
10861 /* VEX_W_0F98_P_2_LEN_0 */
10862 { "kortestb", { MaskG, MaskR }, 0 },
10863 { "kortestd", { MaskG, MaskR }, 0 },
10866 /* VEX_W_0F99_P_0_LEN_0 */
10867 { "ktestw", { MaskG, MaskR }, 0 },
10868 { "ktestq", { MaskG, MaskR }, 0 },
10871 /* VEX_W_0F99_P_2_LEN_0 */
10872 { "ktestb", { MaskG, MaskR }, 0 },
10873 { "ktestd", { MaskG, MaskR }, 0 },
10876 /* VEX_W_0FAE_R_2_M_0 */
10877 { "vldmxcsr", { Md }, 0 },
10880 /* VEX_W_0FAE_R_3_M_0 */
10881 { "vstmxcsr", { Md }, 0 },
10884 /* VEX_W_0FC2_P_0 */
10885 { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
10888 /* VEX_W_0FC2_P_1 */
10889 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10892 /* VEX_W_0FC2_P_2 */
10893 { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
10896 /* VEX_W_0FC2_P_3 */
10897 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10900 /* VEX_W_0FC4_P_2 */
10901 { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
10904 /* VEX_W_0FC5_P_2 */
10905 { "vpextrw", { Gdq, XS, Ib }, 0 },
10908 /* VEX_W_0FD0_P_2 */
10909 { "vaddsubpd", { XM, Vex, EXx }, 0 },
10912 /* VEX_W_0FD0_P_3 */
10913 { "vaddsubps", { XM, Vex, EXx }, 0 },
10916 /* VEX_W_0FD1_P_2 */
10917 { "vpsrlw", { XM, Vex, EXxmm }, 0 },
10920 /* VEX_W_0FD2_P_2 */
10921 { "vpsrld", { XM, Vex, EXxmm }, 0 },
10924 /* VEX_W_0FD3_P_2 */
10925 { "vpsrlq", { XM, Vex, EXxmm }, 0 },
10928 /* VEX_W_0FD4_P_2 */
10929 { "vpaddq", { XM, Vex, EXx }, 0 },
10932 /* VEX_W_0FD5_P_2 */
10933 { "vpmullw", { XM, Vex, EXx }, 0 },
10936 /* VEX_W_0FD6_P_2 */
10937 { "vmovq", { EXqScalarS, XMScalar }, 0 },
10940 /* VEX_W_0FD7_P_2_M_1 */
10941 { "vpmovmskb", { Gdq, XS }, 0 },
10944 /* VEX_W_0FD8_P_2 */
10945 { "vpsubusb", { XM, Vex, EXx }, 0 },
10948 /* VEX_W_0FD9_P_2 */
10949 { "vpsubusw", { XM, Vex, EXx }, 0 },
10952 /* VEX_W_0FDA_P_2 */
10953 { "vpminub", { XM, Vex, EXx }, 0 },
10956 /* VEX_W_0FDB_P_2 */
10957 { "vpand", { XM, Vex, EXx }, 0 },
10960 /* VEX_W_0FDC_P_2 */
10961 { "vpaddusb", { XM, Vex, EXx }, 0 },
10964 /* VEX_W_0FDD_P_2 */
10965 { "vpaddusw", { XM, Vex, EXx }, 0 },
10968 /* VEX_W_0FDE_P_2 */
10969 { "vpmaxub", { XM, Vex, EXx }, 0 },
10972 /* VEX_W_0FDF_P_2 */
10973 { "vpandn", { XM, Vex, EXx }, 0 },
10976 /* VEX_W_0FE0_P_2 */
10977 { "vpavgb", { XM, Vex, EXx }, 0 },
10980 /* VEX_W_0FE1_P_2 */
10981 { "vpsraw", { XM, Vex, EXxmm }, 0 },
10984 /* VEX_W_0FE2_P_2 */
10985 { "vpsrad", { XM, Vex, EXxmm }, 0 },
10988 /* VEX_W_0FE3_P_2 */
10989 { "vpavgw", { XM, Vex, EXx }, 0 },
10992 /* VEX_W_0FE4_P_2 */
10993 { "vpmulhuw", { XM, Vex, EXx }, 0 },
10996 /* VEX_W_0FE5_P_2 */
10997 { "vpmulhw", { XM, Vex, EXx }, 0 },
11000 /* VEX_W_0FE6_P_1 */
11001 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
11004 /* VEX_W_0FE6_P_2 */
11005 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
11008 /* VEX_W_0FE6_P_3 */
11009 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
11012 /* VEX_W_0FE7_P_2_M_0 */
11013 { "vmovntdq", { Mx, XM }, 0 },
11016 /* VEX_W_0FE8_P_2 */
11017 { "vpsubsb", { XM, Vex, EXx }, 0 },
11020 /* VEX_W_0FE9_P_2 */
11021 { "vpsubsw", { XM, Vex, EXx }, 0 },
11024 /* VEX_W_0FEA_P_2 */
11025 { "vpminsw", { XM, Vex, EXx }, 0 },
11028 /* VEX_W_0FEB_P_2 */
11029 { "vpor", { XM, Vex, EXx }, 0 },
11032 /* VEX_W_0FEC_P_2 */
11033 { "vpaddsb", { XM, Vex, EXx }, 0 },
11036 /* VEX_W_0FED_P_2 */
11037 { "vpaddsw", { XM, Vex, EXx }, 0 },
11040 /* VEX_W_0FEE_P_2 */
11041 { "vpmaxsw", { XM, Vex, EXx }, 0 },
11044 /* VEX_W_0FEF_P_2 */
11045 { "vpxor", { XM, Vex, EXx }, 0 },
11048 /* VEX_W_0FF0_P_3_M_0 */
11049 { "vlddqu", { XM, M }, 0 },
11052 /* VEX_W_0FF1_P_2 */
11053 { "vpsllw", { XM, Vex, EXxmm }, 0 },
11056 /* VEX_W_0FF2_P_2 */
11057 { "vpslld", { XM, Vex, EXxmm }, 0 },
11060 /* VEX_W_0FF3_P_2 */
11061 { "vpsllq", { XM, Vex, EXxmm }, 0 },
11064 /* VEX_W_0FF4_P_2 */
11065 { "vpmuludq", { XM, Vex, EXx }, 0 },
11068 /* VEX_W_0FF5_P_2 */
11069 { "vpmaddwd", { XM, Vex, EXx }, 0 },
11072 /* VEX_W_0FF6_P_2 */
11073 { "vpsadbw", { XM, Vex, EXx }, 0 },
11076 /* VEX_W_0FF7_P_2 */
11077 { "vmaskmovdqu", { XM, XS }, 0 },
11080 /* VEX_W_0FF8_P_2 */
11081 { "vpsubb", { XM, Vex, EXx }, 0 },
11084 /* VEX_W_0FF9_P_2 */
11085 { "vpsubw", { XM, Vex, EXx }, 0 },
11088 /* VEX_W_0FFA_P_2 */
11089 { "vpsubd", { XM, Vex, EXx }, 0 },
11092 /* VEX_W_0FFB_P_2 */
11093 { "vpsubq", { XM, Vex, EXx }, 0 },
11096 /* VEX_W_0FFC_P_2 */
11097 { "vpaddb", { XM, Vex, EXx }, 0 },
11100 /* VEX_W_0FFD_P_2 */
11101 { "vpaddw", { XM, Vex, EXx }, 0 },
11104 /* VEX_W_0FFE_P_2 */
11105 { "vpaddd", { XM, Vex, EXx }, 0 },
11108 /* VEX_W_0F3800_P_2 */
11109 { "vpshufb", { XM, Vex, EXx }, 0 },
11112 /* VEX_W_0F3801_P_2 */
11113 { "vphaddw", { XM, Vex, EXx }, 0 },
11116 /* VEX_W_0F3802_P_2 */
11117 { "vphaddd", { XM, Vex, EXx }, 0 },
11120 /* VEX_W_0F3803_P_2 */
11121 { "vphaddsw", { XM, Vex, EXx }, 0 },
11124 /* VEX_W_0F3804_P_2 */
11125 { "vpmaddubsw", { XM, Vex, EXx }, 0 },
11128 /* VEX_W_0F3805_P_2 */
11129 { "vphsubw", { XM, Vex, EXx }, 0 },
11132 /* VEX_W_0F3806_P_2 */
11133 { "vphsubd", { XM, Vex, EXx }, 0 },
11136 /* VEX_W_0F3807_P_2 */
11137 { "vphsubsw", { XM, Vex, EXx }, 0 },
11140 /* VEX_W_0F3808_P_2 */
11141 { "vpsignb", { XM, Vex, EXx }, 0 },
11144 /* VEX_W_0F3809_P_2 */
11145 { "vpsignw", { XM, Vex, EXx }, 0 },
11148 /* VEX_W_0F380A_P_2 */
11149 { "vpsignd", { XM, Vex, EXx }, 0 },
11152 /* VEX_W_0F380B_P_2 */
11153 { "vpmulhrsw", { XM, Vex, EXx }, 0 },
11156 /* VEX_W_0F380C_P_2 */
11157 { "vpermilps", { XM, Vex, EXx }, 0 },
11160 /* VEX_W_0F380D_P_2 */
11161 { "vpermilpd", { XM, Vex, EXx }, 0 },
11164 /* VEX_W_0F380E_P_2 */
11165 { "vtestps", { XM, EXx }, 0 },
11168 /* VEX_W_0F380F_P_2 */
11169 { "vtestpd", { XM, EXx }, 0 },
11172 /* VEX_W_0F3816_P_2 */
11173 { "vpermps", { XM, Vex, EXx }, 0 },
11176 /* VEX_W_0F3817_P_2 */
11177 { "vptest", { XM, EXx }, 0 },
11180 /* VEX_W_0F3818_P_2 */
11181 { "vbroadcastss", { XM, EXxmm_md }, 0 },
11184 /* VEX_W_0F3819_P_2 */
11185 { "vbroadcastsd", { XM, EXxmm_mq }, 0 },
11188 /* VEX_W_0F381A_P_2_M_0 */
11189 { "vbroadcastf128", { XM, Mxmm }, 0 },
11192 /* VEX_W_0F381C_P_2 */
11193 { "vpabsb", { XM, EXx }, 0 },
11196 /* VEX_W_0F381D_P_2 */
11197 { "vpabsw", { XM, EXx }, 0 },
11200 /* VEX_W_0F381E_P_2 */
11201 { "vpabsd", { XM, EXx }, 0 },
11204 /* VEX_W_0F3820_P_2 */
11205 { "vpmovsxbw", { XM, EXxmmq }, 0 },
11208 /* VEX_W_0F3821_P_2 */
11209 { "vpmovsxbd", { XM, EXxmmqd }, 0 },
11212 /* VEX_W_0F3822_P_2 */
11213 { "vpmovsxbq", { XM, EXxmmdw }, 0 },
11216 /* VEX_W_0F3823_P_2 */
11217 { "vpmovsxwd", { XM, EXxmmq }, 0 },
11220 /* VEX_W_0F3824_P_2 */
11221 { "vpmovsxwq", { XM, EXxmmqd }, 0 },
11224 /* VEX_W_0F3825_P_2 */
11225 { "vpmovsxdq", { XM, EXxmmq }, 0 },
11228 /* VEX_W_0F3828_P_2 */
11229 { "vpmuldq", { XM, Vex, EXx }, 0 },
11232 /* VEX_W_0F3829_P_2 */
11233 { "vpcmpeqq", { XM, Vex, EXx }, 0 },
11236 /* VEX_W_0F382A_P_2_M_0 */
11237 { "vmovntdqa", { XM, Mx }, 0 },
11240 /* VEX_W_0F382B_P_2 */
11241 { "vpackusdw", { XM, Vex, EXx }, 0 },
11244 /* VEX_W_0F382C_P_2_M_0 */
11245 { "vmaskmovps", { XM, Vex, Mx }, 0 },
11248 /* VEX_W_0F382D_P_2_M_0 */
11249 { "vmaskmovpd", { XM, Vex, Mx }, 0 },
11252 /* VEX_W_0F382E_P_2_M_0 */
11253 { "vmaskmovps", { Mx, Vex, XM }, 0 },
11256 /* VEX_W_0F382F_P_2_M_0 */
11257 { "vmaskmovpd", { Mx, Vex, XM }, 0 },
11260 /* VEX_W_0F3830_P_2 */
11261 { "vpmovzxbw", { XM, EXxmmq }, 0 },
11264 /* VEX_W_0F3831_P_2 */
11265 { "vpmovzxbd", { XM, EXxmmqd }, 0 },
11268 /* VEX_W_0F3832_P_2 */
11269 { "vpmovzxbq", { XM, EXxmmdw }, 0 },
11272 /* VEX_W_0F3833_P_2 */
11273 { "vpmovzxwd", { XM, EXxmmq }, 0 },
11276 /* VEX_W_0F3834_P_2 */
11277 { "vpmovzxwq", { XM, EXxmmqd }, 0 },
11280 /* VEX_W_0F3835_P_2 */
11281 { "vpmovzxdq", { XM, EXxmmq }, 0 },
11284 /* VEX_W_0F3836_P_2 */
11285 { "vpermd", { XM, Vex, EXx }, 0 },
11288 /* VEX_W_0F3837_P_2 */
11289 { "vpcmpgtq", { XM, Vex, EXx }, 0 },
11292 /* VEX_W_0F3838_P_2 */
11293 { "vpminsb", { XM, Vex, EXx }, 0 },
11296 /* VEX_W_0F3839_P_2 */
11297 { "vpminsd", { XM, Vex, EXx }, 0 },
11300 /* VEX_W_0F383A_P_2 */
11301 { "vpminuw", { XM, Vex, EXx }, 0 },
11304 /* VEX_W_0F383B_P_2 */
11305 { "vpminud", { XM, Vex, EXx }, 0 },
11308 /* VEX_W_0F383C_P_2 */
11309 { "vpmaxsb", { XM, Vex, EXx }, 0 },
11312 /* VEX_W_0F383D_P_2 */
11313 { "vpmaxsd", { XM, Vex, EXx }, 0 },
11316 /* VEX_W_0F383E_P_2 */
11317 { "vpmaxuw", { XM, Vex, EXx }, 0 },
11320 /* VEX_W_0F383F_P_2 */
11321 { "vpmaxud", { XM, Vex, EXx }, 0 },
11324 /* VEX_W_0F3840_P_2 */
11325 { "vpmulld", { XM, Vex, EXx }, 0 },
11328 /* VEX_W_0F3841_P_2 */
11329 { "vphminposuw", { XM, EXx }, 0 },
11332 /* VEX_W_0F3846_P_2 */
11333 { "vpsravd", { XM, Vex, EXx }, 0 },
11336 /* VEX_W_0F3858_P_2 */
11337 { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11340 /* VEX_W_0F3859_P_2 */
11341 { "vpbroadcastq", { XM, EXxmm_mq }, 0 },
11344 /* VEX_W_0F385A_P_2_M_0 */
11345 { "vbroadcasti128", { XM, Mxmm }, 0 },
11348 /* VEX_W_0F3878_P_2 */
11349 { "vpbroadcastb", { XM, EXxmm_mb }, 0 },
11352 /* VEX_W_0F3879_P_2 */
11353 { "vpbroadcastw", { XM, EXxmm_mw }, 0 },
11356 /* VEX_W_0F38DB_P_2 */
11357 { "vaesimc", { XM, EXx }, 0 },
11360 /* VEX_W_0F38DC_P_2 */
11361 { "vaesenc", { XM, Vex128, EXx }, 0 },
11364 /* VEX_W_0F38DD_P_2 */
11365 { "vaesenclast", { XM, Vex128, EXx }, 0 },
11368 /* VEX_W_0F38DE_P_2 */
11369 { "vaesdec", { XM, Vex128, EXx }, 0 },
11372 /* VEX_W_0F38DF_P_2 */
11373 { "vaesdeclast", { XM, Vex128, EXx }, 0 },
11376 /* VEX_W_0F3A00_P_2 */
11378 { "vpermq", { XM, EXx, Ib }, 0 },
11381 /* VEX_W_0F3A01_P_2 */
11383 { "vpermpd", { XM, EXx, Ib }, 0 },
11386 /* VEX_W_0F3A02_P_2 */
11387 { "vpblendd", { XM, Vex, EXx, Ib }, 0 },
11390 /* VEX_W_0F3A04_P_2 */
11391 { "vpermilps", { XM, EXx, Ib }, 0 },
11394 /* VEX_W_0F3A05_P_2 */
11395 { "vpermilpd", { XM, EXx, Ib }, 0 },
11398 /* VEX_W_0F3A06_P_2 */
11399 { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 },
11402 /* VEX_W_0F3A08_P_2 */
11403 { "vroundps", { XM, EXx, Ib }, 0 },
11406 /* VEX_W_0F3A09_P_2 */
11407 { "vroundpd", { XM, EXx, Ib }, 0 },
11410 /* VEX_W_0F3A0A_P_2 */
11411 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11414 /* VEX_W_0F3A0B_P_2 */
11415 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11418 /* VEX_W_0F3A0C_P_2 */
11419 { "vblendps", { XM, Vex, EXx, Ib }, 0 },
11422 /* VEX_W_0F3A0D_P_2 */
11423 { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
11426 /* VEX_W_0F3A0E_P_2 */
11427 { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
11430 /* VEX_W_0F3A0F_P_2 */
11431 { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
11434 /* VEX_W_0F3A14_P_2 */
11435 { "vpextrb", { Edqb, XM, Ib }, 0 },
11438 /* VEX_W_0F3A15_P_2 */
11439 { "vpextrw", { Edqw, XM, Ib }, 0 },
11442 /* VEX_W_0F3A18_P_2 */
11443 { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 },
11446 /* VEX_W_0F3A19_P_2 */
11447 { "vextractf128", { EXxmm, XM, Ib }, 0 },
11450 /* VEX_W_0F3A20_P_2 */
11451 { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
11454 /* VEX_W_0F3A21_P_2 */
11455 { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
11458 /* VEX_W_0F3A30_P_2_LEN_0 */
11459 { "kshiftrb", { MaskG, MaskR, Ib }, 0 },
11460 { "kshiftrw", { MaskG, MaskR, Ib }, 0 },
11463 /* VEX_W_0F3A31_P_2_LEN_0 */
11464 { "kshiftrd", { MaskG, MaskR, Ib }, 0 },
11465 { "kshiftrq", { MaskG, MaskR, Ib }, 0 },
11468 /* VEX_W_0F3A32_P_2_LEN_0 */
11469 { "kshiftlb", { MaskG, MaskR, Ib }, 0 },
11470 { "kshiftlw", { MaskG, MaskR, Ib }, 0 },
11473 /* VEX_W_0F3A33_P_2_LEN_0 */
11474 { "kshiftld", { MaskG, MaskR, Ib }, 0 },
11475 { "kshiftlq", { MaskG, MaskR, Ib }, 0 },
11478 /* VEX_W_0F3A38_P_2 */
11479 { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 },
11482 /* VEX_W_0F3A39_P_2 */
11483 { "vextracti128", { EXxmm, XM, Ib }, 0 },
11486 /* VEX_W_0F3A40_P_2 */
11487 { "vdpps", { XM, Vex, EXx, Ib }, 0 },
11490 /* VEX_W_0F3A41_P_2 */
11491 { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
11494 /* VEX_W_0F3A42_P_2 */
11495 { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
11498 /* VEX_W_0F3A44_P_2 */
11499 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL }, 0 },
11502 /* VEX_W_0F3A46_P_2 */
11503 { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
11506 /* VEX_W_0F3A48_P_2 */
11507 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11508 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11511 /* VEX_W_0F3A49_P_2 */
11512 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11513 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11516 /* VEX_W_0F3A4A_P_2 */
11517 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 },
11520 /* VEX_W_0F3A4B_P_2 */
11521 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 },
11524 /* VEX_W_0F3A4C_P_2 */
11525 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
11528 /* VEX_W_0F3A60_P_2 */
11529 { "vpcmpestrm", { XM, EXx, Ib }, 0 },
11532 /* VEX_W_0F3A61_P_2 */
11533 { "vpcmpestri", { XM, EXx, Ib }, 0 },
11536 /* VEX_W_0F3A62_P_2 */
11537 { "vpcmpistrm", { XM, EXx, Ib }, 0 },
11540 /* VEX_W_0F3A63_P_2 */
11541 { "vpcmpistri", { XM, EXx, Ib }, 0 },
11544 /* VEX_W_0F3ADF_P_2 */
11545 { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11547 #define NEED_VEX_W_TABLE
11548 #include "i386-dis-evex.h"
11549 #undef NEED_VEX_W_TABLE
11552 static const struct dis386 mod_table[][2] = {
11555 { "leaS", { Gv, M }, 0 },
11560 { RM_TABLE (RM_C6_REG_7) },
11565 { RM_TABLE (RM_C7_REG_7) },
11569 { "Jcall{T|}", { indirEp }, 0 },
11573 { "Jjmp{T|}", { indirEp }, 0 },
11576 /* MOD_0F01_REG_0 */
11577 { X86_64_TABLE (X86_64_0F01_REG_0) },
11578 { RM_TABLE (RM_0F01_REG_0) },
11581 /* MOD_0F01_REG_1 */
11582 { X86_64_TABLE (X86_64_0F01_REG_1) },
11583 { RM_TABLE (RM_0F01_REG_1) },
11586 /* MOD_0F01_REG_2 */
11587 { X86_64_TABLE (X86_64_0F01_REG_2) },
11588 { RM_TABLE (RM_0F01_REG_2) },
11591 /* MOD_0F01_REG_3 */
11592 { X86_64_TABLE (X86_64_0F01_REG_3) },
11593 { RM_TABLE (RM_0F01_REG_3) },
11596 /* MOD_0F01_REG_7 */
11597 { "invlpg", { Mb }, 0 },
11598 { RM_TABLE (RM_0F01_REG_7) },
11601 /* MOD_0F12_PREFIX_0 */
11602 { "movlps", { XM, EXq }, PREFIX_OPCODE },
11603 { "movhlps", { XM, EXq }, PREFIX_OPCODE },
11607 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
11610 /* MOD_0F16_PREFIX_0 */
11611 { "movhps", { XM, EXq }, 0 },
11612 { "movlhps", { XM, EXq }, 0 },
11616 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
11619 /* MOD_0F18_REG_0 */
11620 { "prefetchnta", { Mb }, 0 },
11623 /* MOD_0F18_REG_1 */
11624 { "prefetcht0", { Mb }, 0 },
11627 /* MOD_0F18_REG_2 */
11628 { "prefetcht1", { Mb }, 0 },
11631 /* MOD_0F18_REG_3 */
11632 { "prefetcht2", { Mb }, 0 },
11635 /* MOD_0F18_REG_4 */
11636 { "nop/reserved", { Mb }, 0 },
11639 /* MOD_0F18_REG_5 */
11640 { "nop/reserved", { Mb }, 0 },
11643 /* MOD_0F18_REG_6 */
11644 { "nop/reserved", { Mb }, 0 },
11647 /* MOD_0F18_REG_7 */
11648 { "nop/reserved", { Mb }, 0 },
11651 /* MOD_0F1A_PREFIX_0 */
11652 { "bndldx", { Gbnd, Ev_bnd }, 0 },
11653 { "nopQ", { Ev }, 0 },
11656 /* MOD_0F1B_PREFIX_0 */
11657 { "bndstx", { Ev_bnd, Gbnd }, 0 },
11658 { "nopQ", { Ev }, 0 },
11661 /* MOD_0F1B_PREFIX_1 */
11662 { "bndmk", { Gbnd, Ev_bnd }, 0 },
11663 { "nopQ", { Ev }, 0 },
11668 { "movL", { Rd, Td }, 0 },
11673 { "movL", { Td, Rd }, 0 },
11676 /* MOD_0F2B_PREFIX_0 */
11677 {"movntps", { Mx, XM }, PREFIX_OPCODE },
11680 /* MOD_0F2B_PREFIX_1 */
11681 {"movntss", { Md, XM }, PREFIX_OPCODE },
11684 /* MOD_0F2B_PREFIX_2 */
11685 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
11688 /* MOD_0F2B_PREFIX_3 */
11689 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
11694 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
11697 /* MOD_0F71_REG_2 */
11699 { "psrlw", { MS, Ib }, 0 },
11702 /* MOD_0F71_REG_4 */
11704 { "psraw", { MS, Ib }, 0 },
11707 /* MOD_0F71_REG_6 */
11709 { "psllw", { MS, Ib }, 0 },
11712 /* MOD_0F72_REG_2 */
11714 { "psrld", { MS, Ib }, 0 },
11717 /* MOD_0F72_REG_4 */
11719 { "psrad", { MS, Ib }, 0 },
11722 /* MOD_0F72_REG_6 */
11724 { "pslld", { MS, Ib }, 0 },
11727 /* MOD_0F73_REG_2 */
11729 { "psrlq", { MS, Ib }, 0 },
11732 /* MOD_0F73_REG_3 */
11734 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11737 /* MOD_0F73_REG_6 */
11739 { "psllq", { MS, Ib }, 0 },
11742 /* MOD_0F73_REG_7 */
11744 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11747 /* MOD_0FAE_REG_0 */
11748 { "fxsave", { FXSAVE }, 0 },
11749 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11752 /* MOD_0FAE_REG_1 */
11753 { "fxrstor", { FXSAVE }, 0 },
11754 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11757 /* MOD_0FAE_REG_2 */
11758 { "ldmxcsr", { Md }, 0 },
11759 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11762 /* MOD_0FAE_REG_3 */
11763 { "stmxcsr", { Md }, 0 },
11764 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11767 /* MOD_0FAE_REG_4 */
11768 { "xsave", { FXSAVE }, 0 },
11771 /* MOD_0FAE_REG_5 */
11772 { "xrstor", { FXSAVE }, 0 },
11773 { RM_TABLE (RM_0FAE_REG_5) },
11776 /* MOD_0FAE_REG_6 */
11777 { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11778 { RM_TABLE (RM_0FAE_REG_6) },
11781 /* MOD_0FAE_REG_7 */
11782 { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11783 { RM_TABLE (RM_0FAE_REG_7) },
11787 { "lssS", { Gv, Mp }, 0 },
11791 { "lfsS", { Gv, Mp }, 0 },
11795 { "lgsS", { Gv, Mp }, 0 },
11798 /* MOD_0FC7_REG_3 */
11799 { "xrstors", { FXSAVE }, 0 },
11802 /* MOD_0FC7_REG_4 */
11803 { "xsavec", { FXSAVE }, 0 },
11806 /* MOD_0FC7_REG_5 */
11807 { "xsaves", { FXSAVE }, 0 },
11810 /* MOD_0FC7_REG_6 */
11811 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
11812 { "rdrand", { Ev }, 0 },
11815 /* MOD_0FC7_REG_7 */
11816 { "vmptrst", { Mq }, 0 },
11817 { "rdseed", { Ev }, 0 },
11822 { "pmovmskb", { Gdq, MS }, 0 },
11825 /* MOD_0FE7_PREFIX_2 */
11826 { "movntdq", { Mx, XM }, 0 },
11829 /* MOD_0FF0_PREFIX_3 */
11830 { "lddqu", { XM, M }, 0 },
11833 /* MOD_0F382A_PREFIX_2 */
11834 { "movntdqa", { XM, Mx }, 0 },
11838 { "bound{S|}", { Gv, Ma }, 0 },
11839 { EVEX_TABLE (EVEX_0F) },
11843 { "lesS", { Gv, Mp }, 0 },
11844 { VEX_C4_TABLE (VEX_0F) },
11848 { "ldsS", { Gv, Mp }, 0 },
11849 { VEX_C5_TABLE (VEX_0F) },
11852 /* MOD_VEX_0F12_PREFIX_0 */
11853 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11854 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11858 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11861 /* MOD_VEX_0F16_PREFIX_0 */
11862 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11863 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11867 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11871 { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11876 { VEX_W_TABLE (VEX_W_0F50_M_0) },
11879 /* MOD_VEX_0F71_REG_2 */
11881 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11884 /* MOD_VEX_0F71_REG_4 */
11886 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11889 /* MOD_VEX_0F71_REG_6 */
11891 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11894 /* MOD_VEX_0F72_REG_2 */
11896 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11899 /* MOD_VEX_0F72_REG_4 */
11901 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11904 /* MOD_VEX_0F72_REG_6 */
11906 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11909 /* MOD_VEX_0F73_REG_2 */
11911 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11914 /* MOD_VEX_0F73_REG_3 */
11916 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11919 /* MOD_VEX_0F73_REG_6 */
11921 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11924 /* MOD_VEX_0F73_REG_7 */
11926 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11929 /* MOD_VEX_0FAE_REG_2 */
11930 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11933 /* MOD_VEX_0FAE_REG_3 */
11934 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11937 /* MOD_VEX_0FD7_PREFIX_2 */
11939 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11942 /* MOD_VEX_0FE7_PREFIX_2 */
11943 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11946 /* MOD_VEX_0FF0_PREFIX_3 */
11947 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11950 /* MOD_VEX_0F381A_PREFIX_2 */
11951 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11954 /* MOD_VEX_0F382A_PREFIX_2 */
11955 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11958 /* MOD_VEX_0F382C_PREFIX_2 */
11959 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11962 /* MOD_VEX_0F382D_PREFIX_2 */
11963 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11966 /* MOD_VEX_0F382E_PREFIX_2 */
11967 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11970 /* MOD_VEX_0F382F_PREFIX_2 */
11971 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11974 /* MOD_VEX_0F385A_PREFIX_2 */
11975 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11978 /* MOD_VEX_0F388C_PREFIX_2 */
11979 { "vpmaskmov%LW", { XM, Vex, Mx }, 0 },
11982 /* MOD_VEX_0F388E_PREFIX_2 */
11983 { "vpmaskmov%LW", { Mx, Vex, XM }, 0 },
11985 #define NEED_MOD_TABLE
11986 #include "i386-dis-evex.h"
11987 #undef NEED_MOD_TABLE
11990 static const struct dis386 rm_table[][8] = {
11993 { "xabort", { Skip_MODRM, Ib }, 0 },
11997 { "xbeginT", { Skip_MODRM, Jv }, 0 },
12000 /* RM_0F01_REG_0 */
12002 { "vmcall", { Skip_MODRM }, 0 },
12003 { "vmlaunch", { Skip_MODRM }, 0 },
12004 { "vmresume", { Skip_MODRM }, 0 },
12005 { "vmxoff", { Skip_MODRM }, 0 },
12008 /* RM_0F01_REG_1 */
12009 { "monitor", { { OP_Monitor, 0 } }, 0 },
12010 { "mwait", { { OP_Mwait, 0 } }, 0 },
12011 { "clac", { Skip_MODRM }, 0 },
12012 { "stac", { Skip_MODRM }, 0 },
12016 { "encls", { Skip_MODRM }, 0 },
12019 /* RM_0F01_REG_2 */
12020 { "xgetbv", { Skip_MODRM }, 0 },
12021 { "xsetbv", { Skip_MODRM }, 0 },
12024 { "vmfunc", { Skip_MODRM }, 0 },
12025 { "xend", { Skip_MODRM }, 0 },
12026 { "xtest", { Skip_MODRM }, 0 },
12027 { "enclu", { Skip_MODRM }, 0 },
12030 /* RM_0F01_REG_3 */
12031 { "vmrun", { Skip_MODRM }, 0 },
12032 { "vmmcall", { Skip_MODRM }, 0 },
12033 { "vmload", { Skip_MODRM }, 0 },
12034 { "vmsave", { Skip_MODRM }, 0 },
12035 { "stgi", { Skip_MODRM }, 0 },
12036 { "clgi", { Skip_MODRM }, 0 },
12037 { "skinit", { Skip_MODRM }, 0 },
12038 { "invlpga", { Skip_MODRM }, 0 },
12041 /* RM_0F01_REG_7 */
12042 { "swapgs", { Skip_MODRM }, 0 },
12043 { "rdtscp", { Skip_MODRM }, 0 },
12046 { "clzero", { Skip_MODRM }, 0 },
12049 /* RM_0FAE_REG_5 */
12050 { "lfence", { Skip_MODRM }, 0 },
12053 /* RM_0FAE_REG_6 */
12054 { "mfence", { Skip_MODRM }, 0 },
12057 /* RM_0FAE_REG_7 */
12058 { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) },
12062 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12064 /* We use the high bit to indicate different name for the same
12066 #define REP_PREFIX (0xf3 | 0x100)
12067 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12068 #define XRELEASE_PREFIX (0xf3 | 0x400)
12069 #define BND_PREFIX (0xf2 | 0x400)
12074 int newrex, i, length;
12080 last_lock_prefix = -1;
12081 last_repz_prefix = -1;
12082 last_repnz_prefix = -1;
12083 last_data_prefix = -1;
12084 last_addr_prefix = -1;
12085 last_rex_prefix = -1;
12086 last_seg_prefix = -1;
12088 active_seg_prefix = 0;
12089 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12090 all_prefixes[i] = 0;
12093 /* The maximum instruction length is 15bytes. */
12094 while (length < MAX_CODE_LENGTH - 1)
12096 FETCH_DATA (the_info, codep + 1);
12100 /* REX prefixes family. */
12117 if (address_mode == mode_64bit)
12121 last_rex_prefix = i;
12124 prefixes |= PREFIX_REPZ;
12125 last_repz_prefix = i;
12128 prefixes |= PREFIX_REPNZ;
12129 last_repnz_prefix = i;
12132 prefixes |= PREFIX_LOCK;
12133 last_lock_prefix = i;
12136 prefixes |= PREFIX_CS;
12137 last_seg_prefix = i;
12138 active_seg_prefix = PREFIX_CS;
12141 prefixes |= PREFIX_SS;
12142 last_seg_prefix = i;
12143 active_seg_prefix = PREFIX_SS;
12146 prefixes |= PREFIX_DS;
12147 last_seg_prefix = i;
12148 active_seg_prefix = PREFIX_DS;
12151 prefixes |= PREFIX_ES;
12152 last_seg_prefix = i;
12153 active_seg_prefix = PREFIX_ES;
12156 prefixes |= PREFIX_FS;
12157 last_seg_prefix = i;
12158 active_seg_prefix = PREFIX_FS;
12161 prefixes |= PREFIX_GS;
12162 last_seg_prefix = i;
12163 active_seg_prefix = PREFIX_GS;
12166 prefixes |= PREFIX_DATA;
12167 last_data_prefix = i;
12170 prefixes |= PREFIX_ADDR;
12171 last_addr_prefix = i;
12174 /* fwait is really an instruction. If there are prefixes
12175 before the fwait, they belong to the fwait, *not* to the
12176 following instruction. */
12178 if (prefixes || rex)
12180 prefixes |= PREFIX_FWAIT;
12182 /* This ensures that the previous REX prefixes are noticed
12183 as unused prefixes, as in the return case below. */
12187 prefixes = PREFIX_FWAIT;
12192 /* Rex is ignored when followed by another prefix. */
12198 if (*codep != FWAIT_OPCODE)
12199 all_prefixes[i++] = *codep;
12207 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12210 static const char *
12211 prefix_name (int pref, int sizeflag)
12213 static const char *rexes [16] =
12216 "rex.B", /* 0x41 */
12217 "rex.X", /* 0x42 */
12218 "rex.XB", /* 0x43 */
12219 "rex.R", /* 0x44 */
12220 "rex.RB", /* 0x45 */
12221 "rex.RX", /* 0x46 */
12222 "rex.RXB", /* 0x47 */
12223 "rex.W", /* 0x48 */
12224 "rex.WB", /* 0x49 */
12225 "rex.WX", /* 0x4a */
12226 "rex.WXB", /* 0x4b */
12227 "rex.WR", /* 0x4c */
12228 "rex.WRB", /* 0x4d */
12229 "rex.WRX", /* 0x4e */
12230 "rex.WRXB", /* 0x4f */
12235 /* REX prefixes family. */
12252 return rexes [pref - 0x40];
12272 return (sizeflag & DFLAG) ? "data16" : "data32";
12274 if (address_mode == mode_64bit)
12275 return (sizeflag & AFLAG) ? "addr32" : "addr64";
12277 return (sizeflag & AFLAG) ? "addr16" : "addr32";
12282 case XACQUIRE_PREFIX:
12284 case XRELEASE_PREFIX:
12293 static char op_out[MAX_OPERANDS][100];
12294 static int op_ad, op_index[MAX_OPERANDS];
12295 static int two_source_ops;
12296 static bfd_vma op_address[MAX_OPERANDS];
12297 static bfd_vma op_riprel[MAX_OPERANDS];
12298 static bfd_vma start_pc;
12301 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12302 * (see topic "Redundant prefixes" in the "Differences from 8086"
12303 * section of the "Virtual 8086 Mode" chapter.)
12304 * 'pc' should be the address of this instruction, it will
12305 * be used to print the target address if this is a relative jump or call
12306 * The function returns the length of this instruction in bytes.
12309 static char intel_syntax;
12310 static char intel_mnemonic = !SYSV386_COMPAT;
12311 static char open_char;
12312 static char close_char;
12313 static char separator_char;
12314 static char scale_char;
12316 /* Here for backwards compatibility. When gdb stops using
12317 print_insn_i386_att and print_insn_i386_intel these functions can
12318 disappear, and print_insn_i386 be merged into print_insn. */
12320 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12324 return print_insn (pc, info);
12328 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12332 return print_insn (pc, info);
12336 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12340 return print_insn (pc, info);
12344 print_i386_disassembler_options (FILE *stream)
12346 fprintf (stream, _("\n\
12347 The following i386/x86-64 specific disassembler options are supported for use\n\
12348 with the -M switch (multiple options should be separated by commas):\n"));
12350 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
12351 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
12352 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
12353 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
12354 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
12355 fprintf (stream, _(" att-mnemonic\n"
12356 " Display instruction in AT&T mnemonic\n"));
12357 fprintf (stream, _(" intel-mnemonic\n"
12358 " Display instruction in Intel mnemonic\n"));
12359 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
12360 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
12361 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
12362 fprintf (stream, _(" data32 Assume 32bit data size\n"));
12363 fprintf (stream, _(" data16 Assume 16bit data size\n"));
12364 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12368 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12370 /* Get a pointer to struct dis386 with a valid name. */
12372 static const struct dis386 *
12373 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12375 int vindex, vex_table_index;
12377 if (dp->name != NULL)
12380 switch (dp->op[0].bytemode)
12382 case USE_REG_TABLE:
12383 dp = ®_table[dp->op[1].bytemode][modrm.reg];
12386 case USE_MOD_TABLE:
12387 vindex = modrm.mod == 0x3 ? 1 : 0;
12388 dp = &mod_table[dp->op[1].bytemode][vindex];
12392 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12395 case USE_PREFIX_TABLE:
12398 /* The prefix in VEX is implicit. */
12399 switch (vex.prefix)
12404 case REPE_PREFIX_OPCODE:
12407 case DATA_PREFIX_OPCODE:
12410 case REPNE_PREFIX_OPCODE:
12420 int last_prefix = -1;
12423 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12424 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12426 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12428 if (last_repz_prefix > last_repnz_prefix)
12431 prefix = PREFIX_REPZ;
12432 last_prefix = last_repz_prefix;
12437 prefix = PREFIX_REPNZ;
12438 last_prefix = last_repnz_prefix;
12441 /* Check if prefix should be ignored. */
12442 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12443 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12448 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12451 prefix = PREFIX_DATA;
12452 last_prefix = last_data_prefix;
12457 used_prefixes |= prefix;
12458 all_prefixes[last_prefix] = 0;
12461 dp = &prefix_table[dp->op[1].bytemode][vindex];
12464 case USE_X86_64_TABLE:
12465 vindex = address_mode == mode_64bit ? 1 : 0;
12466 dp = &x86_64_table[dp->op[1].bytemode][vindex];
12469 case USE_3BYTE_TABLE:
12470 FETCH_DATA (info, codep + 2);
12472 dp = &three_byte_table[dp->op[1].bytemode][vindex];
12474 modrm.mod = (*codep >> 6) & 3;
12475 modrm.reg = (*codep >> 3) & 7;
12476 modrm.rm = *codep & 7;
12479 case USE_VEX_LEN_TABLE:
12483 switch (vex.length)
12496 dp = &vex_len_table[dp->op[1].bytemode][vindex];
12499 case USE_XOP_8F_TABLE:
12500 FETCH_DATA (info, codep + 3);
12501 /* All bits in the REX prefix are ignored. */
12503 rex = ~(*codep >> 5) & 0x7;
12505 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12506 switch ((*codep & 0x1f))
12512 vex_table_index = XOP_08;
12515 vex_table_index = XOP_09;
12518 vex_table_index = XOP_0A;
12522 vex.w = *codep & 0x80;
12523 if (vex.w && address_mode == mode_64bit)
12526 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12527 if (address_mode != mode_64bit
12528 && vex.register_specifier > 0x7)
12534 vex.length = (*codep & 0x4) ? 256 : 128;
12535 switch ((*codep & 0x3))
12541 vex.prefix = DATA_PREFIX_OPCODE;
12544 vex.prefix = REPE_PREFIX_OPCODE;
12547 vex.prefix = REPNE_PREFIX_OPCODE;
12554 dp = &xop_table[vex_table_index][vindex];
12557 FETCH_DATA (info, codep + 1);
12558 modrm.mod = (*codep >> 6) & 3;
12559 modrm.reg = (*codep >> 3) & 7;
12560 modrm.rm = *codep & 7;
12563 case USE_VEX_C4_TABLE:
12565 FETCH_DATA (info, codep + 3);
12566 /* All bits in the REX prefix are ignored. */
12568 rex = ~(*codep >> 5) & 0x7;
12569 switch ((*codep & 0x1f))
12575 vex_table_index = VEX_0F;
12578 vex_table_index = VEX_0F38;
12581 vex_table_index = VEX_0F3A;
12585 vex.w = *codep & 0x80;
12586 if (vex.w && address_mode == mode_64bit)
12589 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12590 if (address_mode != mode_64bit
12591 && vex.register_specifier > 0x7)
12597 vex.length = (*codep & 0x4) ? 256 : 128;
12598 switch ((*codep & 0x3))
12604 vex.prefix = DATA_PREFIX_OPCODE;
12607 vex.prefix = REPE_PREFIX_OPCODE;
12610 vex.prefix = REPNE_PREFIX_OPCODE;
12617 dp = &vex_table[vex_table_index][vindex];
12619 /* There is no MODRM byte for VEX [82|77]. */
12620 if (vindex != 0x77 && vindex != 0x82)
12622 FETCH_DATA (info, codep + 1);
12623 modrm.mod = (*codep >> 6) & 3;
12624 modrm.reg = (*codep >> 3) & 7;
12625 modrm.rm = *codep & 7;
12629 case USE_VEX_C5_TABLE:
12631 FETCH_DATA (info, codep + 2);
12632 /* All bits in the REX prefix are ignored. */
12634 rex = (*codep & 0x80) ? 0 : REX_R;
12636 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12637 if (address_mode != mode_64bit
12638 && vex.register_specifier > 0x7)
12646 vex.length = (*codep & 0x4) ? 256 : 128;
12647 switch ((*codep & 0x3))
12653 vex.prefix = DATA_PREFIX_OPCODE;
12656 vex.prefix = REPE_PREFIX_OPCODE;
12659 vex.prefix = REPNE_PREFIX_OPCODE;
12666 dp = &vex_table[dp->op[1].bytemode][vindex];
12668 /* There is no MODRM byte for VEX [82|77]. */
12669 if (vindex != 0x77 && vindex != 0x82)
12671 FETCH_DATA (info, codep + 1);
12672 modrm.mod = (*codep >> 6) & 3;
12673 modrm.reg = (*codep >> 3) & 7;
12674 modrm.rm = *codep & 7;
12678 case USE_VEX_W_TABLE:
12682 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12685 case USE_EVEX_TABLE:
12686 two_source_ops = 0;
12689 FETCH_DATA (info, codep + 4);
12690 /* All bits in the REX prefix are ignored. */
12692 /* The first byte after 0x62. */
12693 rex = ~(*codep >> 5) & 0x7;
12694 vex.r = *codep & 0x10;
12695 switch ((*codep & 0xf))
12698 return &bad_opcode;
12700 vex_table_index = EVEX_0F;
12703 vex_table_index = EVEX_0F38;
12706 vex_table_index = EVEX_0F3A;
12710 /* The second byte after 0x62. */
12712 vex.w = *codep & 0x80;
12713 if (vex.w && address_mode == mode_64bit)
12716 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12717 if (address_mode != mode_64bit)
12719 /* In 16/32-bit mode silently ignore following bits. */
12723 vex.register_specifier &= 0x7;
12727 if (!(*codep & 0x4))
12728 return &bad_opcode;
12730 switch ((*codep & 0x3))
12736 vex.prefix = DATA_PREFIX_OPCODE;
12739 vex.prefix = REPE_PREFIX_OPCODE;
12742 vex.prefix = REPNE_PREFIX_OPCODE;
12746 /* The third byte after 0x62. */
12749 /* Remember the static rounding bits. */
12750 vex.ll = (*codep >> 5) & 3;
12751 vex.b = (*codep & 0x10) != 0;
12753 vex.v = *codep & 0x8;
12754 vex.mask_register_specifier = *codep & 0x7;
12755 vex.zeroing = *codep & 0x80;
12761 dp = &evex_table[vex_table_index][vindex];
12763 FETCH_DATA (info, codep + 1);
12764 modrm.mod = (*codep >> 6) & 3;
12765 modrm.reg = (*codep >> 3) & 7;
12766 modrm.rm = *codep & 7;
12768 /* Set vector length. */
12769 if (modrm.mod == 3 && vex.b)
12785 return &bad_opcode;
12798 if (dp->name != NULL)
12801 return get_valid_dis386 (dp, info);
12805 get_sib (disassemble_info *info, int sizeflag)
12807 /* If modrm.mod == 3, operand must be register. */
12809 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12813 FETCH_DATA (info, codep + 2);
12814 sib.index = (codep [1] >> 3) & 7;
12815 sib.scale = (codep [1] >> 6) & 3;
12816 sib.base = codep [1] & 7;
12821 print_insn (bfd_vma pc, disassemble_info *info)
12823 const struct dis386 *dp;
12825 char *op_txt[MAX_OPERANDS];
12827 int sizeflag, orig_sizeflag;
12829 struct dis_private priv;
12832 priv.orig_sizeflag = AFLAG | DFLAG;
12833 if ((info->mach & bfd_mach_i386_i386) != 0)
12834 address_mode = mode_32bit;
12835 else if (info->mach == bfd_mach_i386_i8086)
12837 address_mode = mode_16bit;
12838 priv.orig_sizeflag = 0;
12841 address_mode = mode_64bit;
12843 if (intel_syntax == (char) -1)
12844 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12846 for (p = info->disassembler_options; p != NULL; )
12848 if (CONST_STRNEQ (p, "x86-64"))
12850 address_mode = mode_64bit;
12851 priv.orig_sizeflag = AFLAG | DFLAG;
12853 else if (CONST_STRNEQ (p, "i386"))
12855 address_mode = mode_32bit;
12856 priv.orig_sizeflag = AFLAG | DFLAG;
12858 else if (CONST_STRNEQ (p, "i8086"))
12860 address_mode = mode_16bit;
12861 priv.orig_sizeflag = 0;
12863 else if (CONST_STRNEQ (p, "intel"))
12866 if (CONST_STRNEQ (p + 5, "-mnemonic"))
12867 intel_mnemonic = 1;
12869 else if (CONST_STRNEQ (p, "att"))
12872 if (CONST_STRNEQ (p + 3, "-mnemonic"))
12873 intel_mnemonic = 0;
12875 else if (CONST_STRNEQ (p, "addr"))
12877 if (address_mode == mode_64bit)
12879 if (p[4] == '3' && p[5] == '2')
12880 priv.orig_sizeflag &= ~AFLAG;
12881 else if (p[4] == '6' && p[5] == '4')
12882 priv.orig_sizeflag |= AFLAG;
12886 if (p[4] == '1' && p[5] == '6')
12887 priv.orig_sizeflag &= ~AFLAG;
12888 else if (p[4] == '3' && p[5] == '2')
12889 priv.orig_sizeflag |= AFLAG;
12892 else if (CONST_STRNEQ (p, "data"))
12894 if (p[4] == '1' && p[5] == '6')
12895 priv.orig_sizeflag &= ~DFLAG;
12896 else if (p[4] == '3' && p[5] == '2')
12897 priv.orig_sizeflag |= DFLAG;
12899 else if (CONST_STRNEQ (p, "suffix"))
12900 priv.orig_sizeflag |= SUFFIX_ALWAYS;
12902 p = strchr (p, ',');
12909 names64 = intel_names64;
12910 names32 = intel_names32;
12911 names16 = intel_names16;
12912 names8 = intel_names8;
12913 names8rex = intel_names8rex;
12914 names_seg = intel_names_seg;
12915 names_mm = intel_names_mm;
12916 names_bnd = intel_names_bnd;
12917 names_xmm = intel_names_xmm;
12918 names_ymm = intel_names_ymm;
12919 names_zmm = intel_names_zmm;
12920 index64 = intel_index64;
12921 index32 = intel_index32;
12922 names_mask = intel_names_mask;
12923 index16 = intel_index16;
12926 separator_char = '+';
12931 names64 = att_names64;
12932 names32 = att_names32;
12933 names16 = att_names16;
12934 names8 = att_names8;
12935 names8rex = att_names8rex;
12936 names_seg = att_names_seg;
12937 names_mm = att_names_mm;
12938 names_bnd = att_names_bnd;
12939 names_xmm = att_names_xmm;
12940 names_ymm = att_names_ymm;
12941 names_zmm = att_names_zmm;
12942 index64 = att_index64;
12943 index32 = att_index32;
12944 names_mask = att_names_mask;
12945 index16 = att_index16;
12948 separator_char = ',';
12952 /* The output looks better if we put 7 bytes on a line, since that
12953 puts most long word instructions on a single line. Use 8 bytes
12955 if ((info->mach & bfd_mach_l1om) != 0)
12956 info->bytes_per_line = 8;
12958 info->bytes_per_line = 7;
12960 info->private_data = &priv;
12961 priv.max_fetched = priv.the_buffer;
12962 priv.insn_start = pc;
12965 for (i = 0; i < MAX_OPERANDS; ++i)
12973 start_codep = priv.the_buffer;
12974 codep = priv.the_buffer;
12976 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12980 /* Getting here means we tried for data but didn't get it. That
12981 means we have an incomplete instruction of some sort. Just
12982 print the first byte as a prefix or a .byte pseudo-op. */
12983 if (codep > priv.the_buffer)
12985 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12987 (*info->fprintf_func) (info->stream, "%s", name);
12990 /* Just print the first byte as a .byte instruction. */
12991 (*info->fprintf_func) (info->stream, ".byte 0x%x",
12992 (unsigned int) priv.the_buffer[0]);
13002 sizeflag = priv.orig_sizeflag;
13004 if (!ckprefix () || rex_used)
13006 /* Too many prefixes or unused REX prefixes. */
13008 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13010 (*info->fprintf_func) (info->stream, "%s%s",
13012 prefix_name (all_prefixes[i], sizeflag));
13016 insn_codep = codep;
13018 FETCH_DATA (info, codep + 1);
13019 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13021 if (((prefixes & PREFIX_FWAIT)
13022 && ((*codep < 0xd8) || (*codep > 0xdf))))
13024 /* Handle prefixes before fwait. */
13025 for (i = 0; i < fwait_prefix && all_prefixes[i];
13027 (*info->fprintf_func) (info->stream, "%s ",
13028 prefix_name (all_prefixes[i], sizeflag));
13029 (*info->fprintf_func) (info->stream, "fwait");
13033 if (*codep == 0x0f)
13035 unsigned char threebyte;
13036 FETCH_DATA (info, codep + 2);
13037 threebyte = *++codep;
13038 dp = &dis386_twobyte[threebyte];
13039 need_modrm = twobyte_has_modrm[*codep];
13040 prefix_requirement = dp->prefix_requirement;
13045 dp = &dis386[*codep];
13046 need_modrm = onebyte_has_modrm[*codep];
13047 prefix_requirement = 0;
13051 /* Save sizeflag for printing the extra prefixes later before updating
13052 it for mnemonic and operand processing. The prefix names depend
13053 only on the address mode. */
13054 orig_sizeflag = sizeflag;
13055 if (prefixes & PREFIX_ADDR)
13057 if ((prefixes & PREFIX_DATA))
13063 FETCH_DATA (info, codep + 1);
13064 modrm.mod = (*codep >> 6) & 3;
13065 modrm.reg = (*codep >> 3) & 7;
13066 modrm.rm = *codep & 7;
13074 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13076 get_sib (info, sizeflag);
13077 dofloat (sizeflag);
13081 dp = get_valid_dis386 (dp, info);
13082 if (dp != NULL && putop (dp->name, sizeflag) == 0)
13084 get_sib (info, sizeflag);
13085 for (i = 0; i < MAX_OPERANDS; ++i)
13088 op_ad = MAX_OPERANDS - 1 - i;
13090 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13091 /* For EVEX instruction after the last operand masking
13092 should be printed. */
13093 if (i == 0 && vex.evex)
13095 /* Don't print {%k0}. */
13096 if (vex.mask_register_specifier)
13099 oappend (names_mask[vex.mask_register_specifier]);
13109 /* Check if the REX prefix is used. */
13110 if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13111 all_prefixes[last_rex_prefix] = 0;
13113 /* Check if the SEG prefix is used. */
13114 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13115 | PREFIX_FS | PREFIX_GS)) != 0
13116 && (used_prefixes & active_seg_prefix) != 0)
13117 all_prefixes[last_seg_prefix] = 0;
13119 /* Check if the ADDR prefix is used. */
13120 if ((prefixes & PREFIX_ADDR) != 0
13121 && (used_prefixes & PREFIX_ADDR) != 0)
13122 all_prefixes[last_addr_prefix] = 0;
13124 /* Check if the DATA prefix is used. */
13125 if ((prefixes & PREFIX_DATA) != 0
13126 && (used_prefixes & PREFIX_DATA) != 0)
13127 all_prefixes[last_data_prefix] = 0;
13129 /* Print the extra prefixes. */
13131 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13132 if (all_prefixes[i])
13135 name = prefix_name (all_prefixes[i], orig_sizeflag);
13138 prefix_length += strlen (name) + 1;
13139 (*info->fprintf_func) (info->stream, "%s ", name);
13142 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13143 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13144 used by putop and MMX/SSE operand and may be overriden by the
13145 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13147 if (prefix_requirement == PREFIX_OPCODE
13148 && dp != &bad_opcode
13150 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13152 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13154 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13156 && (used_prefixes & PREFIX_DATA) == 0))))
13158 (*info->fprintf_func) (info->stream, "(bad)");
13159 return end_codep - priv.the_buffer;
13162 /* Check maximum code length. */
13163 if ((codep - start_codep) > MAX_CODE_LENGTH)
13165 (*info->fprintf_func) (info->stream, "(bad)");
13166 return MAX_CODE_LENGTH;
13169 obufp = mnemonicendp;
13170 for (i = strlen (obuf) + prefix_length; i < 6; i++)
13173 (*info->fprintf_func) (info->stream, "%s", obuf);
13175 /* The enter and bound instructions are printed with operands in the same
13176 order as the intel book; everything else is printed in reverse order. */
13177 if (intel_syntax || two_source_ops)
13181 for (i = 0; i < MAX_OPERANDS; ++i)
13182 op_txt[i] = op_out[i];
13184 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13186 op_ad = op_index[i];
13187 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13188 op_index[MAX_OPERANDS - 1 - i] = op_ad;
13189 riprel = op_riprel[i];
13190 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13191 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13196 for (i = 0; i < MAX_OPERANDS; ++i)
13197 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13201 for (i = 0; i < MAX_OPERANDS; ++i)
13205 (*info->fprintf_func) (info->stream, ",");
13206 if (op_index[i] != -1 && !op_riprel[i])
13207 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13209 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13213 for (i = 0; i < MAX_OPERANDS; i++)
13214 if (op_index[i] != -1 && op_riprel[i])
13216 (*info->fprintf_func) (info->stream, " # ");
13217 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
13218 + op_address[op_index[i]]), info);
13221 return codep - priv.the_buffer;
13224 static const char *float_mem[] = {
13299 static const unsigned char float_mem_mode[] = {
13374 #define ST { OP_ST, 0 }
13375 #define STi { OP_STi, 0 }
13377 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13378 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13379 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13380 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13381 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13382 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13383 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13384 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13385 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13387 static const struct dis386 float_reg[][8] = {
13390 { "fadd", { ST, STi }, 0 },
13391 { "fmul", { ST, STi }, 0 },
13392 { "fcom", { STi }, 0 },
13393 { "fcomp", { STi }, 0 },
13394 { "fsub", { ST, STi }, 0 },
13395 { "fsubr", { ST, STi }, 0 },
13396 { "fdiv", { ST, STi }, 0 },
13397 { "fdivr", { ST, STi }, 0 },
13401 { "fld", { STi }, 0 },
13402 { "fxch", { STi }, 0 },
13412 { "fcmovb", { ST, STi }, 0 },
13413 { "fcmove", { ST, STi }, 0 },
13414 { "fcmovbe",{ ST, STi }, 0 },
13415 { "fcmovu", { ST, STi }, 0 },
13423 { "fcmovnb",{ ST, STi }, 0 },
13424 { "fcmovne",{ ST, STi }, 0 },
13425 { "fcmovnbe",{ ST, STi }, 0 },
13426 { "fcmovnu",{ ST, STi }, 0 },
13428 { "fucomi", { ST, STi }, 0 },
13429 { "fcomi", { ST, STi }, 0 },
13434 { "fadd", { STi, ST }, 0 },
13435 { "fmul", { STi, ST }, 0 },
13438 { "fsub!M", { STi, ST }, 0 },
13439 { "fsubM", { STi, ST }, 0 },
13440 { "fdiv!M", { STi, ST }, 0 },
13441 { "fdivM", { STi, ST }, 0 },
13445 { "ffree", { STi }, 0 },
13447 { "fst", { STi }, 0 },
13448 { "fstp", { STi }, 0 },
13449 { "fucom", { STi }, 0 },
13450 { "fucomp", { STi }, 0 },
13456 { "faddp", { STi, ST }, 0 },
13457 { "fmulp", { STi, ST }, 0 },
13460 { "fsub!Mp", { STi, ST }, 0 },
13461 { "fsubMp", { STi, ST }, 0 },
13462 { "fdiv!Mp", { STi, ST }, 0 },
13463 { "fdivMp", { STi, ST }, 0 },
13467 { "ffreep", { STi }, 0 },
13472 { "fucomip", { ST, STi }, 0 },
13473 { "fcomip", { ST, STi }, 0 },
13478 static char *fgrps[][8] = {
13481 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13486 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13491 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13496 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13501 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13506 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13511 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13512 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13517 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13522 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13527 swap_operand (void)
13529 mnemonicendp[0] = '.';
13530 mnemonicendp[1] = 's';
13535 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13536 int sizeflag ATTRIBUTE_UNUSED)
13538 /* Skip mod/rm byte. */
13544 dofloat (int sizeflag)
13546 const struct dis386 *dp;
13547 unsigned char floatop;
13549 floatop = codep[-1];
13551 if (modrm.mod != 3)
13553 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13555 putop (float_mem[fp_indx], sizeflag);
13558 OP_E (float_mem_mode[fp_indx], sizeflag);
13561 /* Skip mod/rm byte. */
13565 dp = &float_reg[floatop - 0xd8][modrm.reg];
13566 if (dp->name == NULL)
13568 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13570 /* Instruction fnstsw is only one with strange arg. */
13571 if (floatop == 0xdf && codep[-1] == 0xe0)
13572 strcpy (op_out[0], names16[0]);
13576 putop (dp->name, sizeflag);
13581 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13586 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13590 /* Like oappend (below), but S is a string starting with '%'.
13591 In Intel syntax, the '%' is elided. */
13593 oappend_maybe_intel (const char *s)
13595 oappend (s + intel_syntax);
13599 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13601 oappend_maybe_intel ("%st");
13605 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13607 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13608 oappend_maybe_intel (scratchbuf);
13611 /* Capital letters in template are macros. */
13613 putop (const char *in_template, int sizeflag)
13618 unsigned int l = 0, len = 1;
13621 #define SAVE_LAST(c) \
13622 if (l < len && l < sizeof (last)) \
13627 for (p = in_template; *p; p++)
13644 while (*++p != '|')
13645 if (*p == '}' || *p == '\0')
13648 /* Fall through. */
13653 while (*++p != '}')
13664 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13668 if (l == 0 && len == 1)
13673 if (sizeflag & SUFFIX_ALWAYS)
13686 if (address_mode == mode_64bit
13687 && !(prefixes & PREFIX_ADDR))
13698 if (intel_syntax && !alt)
13700 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13702 if (sizeflag & DFLAG)
13703 *obufp++ = intel_syntax ? 'd' : 'l';
13705 *obufp++ = intel_syntax ? 'w' : 's';
13706 used_prefixes |= (prefixes & PREFIX_DATA);
13710 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13713 if (modrm.mod == 3)
13719 if (sizeflag & DFLAG)
13720 *obufp++ = intel_syntax ? 'd' : 'l';
13723 used_prefixes |= (prefixes & PREFIX_DATA);
13729 case 'E': /* For jcxz/jecxz */
13730 if (address_mode == mode_64bit)
13732 if (sizeflag & AFLAG)
13738 if (sizeflag & AFLAG)
13740 used_prefixes |= (prefixes & PREFIX_ADDR);
13745 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13747 if (sizeflag & AFLAG)
13748 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13750 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13751 used_prefixes |= (prefixes & PREFIX_ADDR);
13755 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13757 if ((rex & REX_W) || (sizeflag & DFLAG))
13761 if (!(rex & REX_W))
13762 used_prefixes |= (prefixes & PREFIX_DATA);
13767 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13768 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13770 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13773 if (prefixes & PREFIX_DS)
13794 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13799 /* Fall through. */
13802 if (l != 0 || len != 1)
13810 if (sizeflag & SUFFIX_ALWAYS)
13814 if (intel_mnemonic != cond)
13818 if ((prefixes & PREFIX_FWAIT) == 0)
13821 used_prefixes |= PREFIX_FWAIT;
13827 else if (intel_syntax && (sizeflag & DFLAG))
13831 if (!(rex & REX_W))
13832 used_prefixes |= (prefixes & PREFIX_DATA);
13836 && address_mode == mode_64bit
13837 && ((sizeflag & DFLAG) || (rex & REX_W)))
13842 /* Fall through. */
13845 if (l == 0 && len == 1)
13850 if ((rex & REX_W) == 0
13851 && (prefixes & PREFIX_DATA))
13853 if ((sizeflag & DFLAG) == 0)
13855 used_prefixes |= (prefixes & PREFIX_DATA);
13859 if ((prefixes & PREFIX_DATA)
13861 || (sizeflag & SUFFIX_ALWAYS))
13868 if (sizeflag & DFLAG)
13872 used_prefixes |= (prefixes & PREFIX_DATA);
13878 if (l != 1 || len != 2 || last[0] != 'L')
13884 if ((prefixes & PREFIX_DATA)
13886 || (sizeflag & SUFFIX_ALWAYS))
13893 if (sizeflag & DFLAG)
13894 *obufp++ = intel_syntax ? 'd' : 'l';
13897 used_prefixes |= (prefixes & PREFIX_DATA);
13905 if (address_mode == mode_64bit
13906 && ((sizeflag & DFLAG) || (rex & REX_W)))
13908 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13912 /* Fall through. */
13915 if (l == 0 && len == 1)
13918 if (intel_syntax && !alt)
13921 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13927 if (sizeflag & DFLAG)
13928 *obufp++ = intel_syntax ? 'd' : 'l';
13931 used_prefixes |= (prefixes & PREFIX_DATA);
13937 if (l != 1 || len != 2 || last[0] != 'L')
13943 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13958 else if (sizeflag & DFLAG)
13967 if (intel_syntax && !p[1]
13968 && ((rex & REX_W) || (sizeflag & DFLAG)))
13970 if (!(rex & REX_W))
13971 used_prefixes |= (prefixes & PREFIX_DATA);
13974 if (l == 0 && len == 1)
13978 if (address_mode == mode_64bit
13979 && ((sizeflag & DFLAG) || (rex & REX_W)))
13981 if (sizeflag & SUFFIX_ALWAYS)
14003 /* Fall through. */
14006 if (l == 0 && len == 1)
14011 if (sizeflag & SUFFIX_ALWAYS)
14017 if (sizeflag & DFLAG)
14021 used_prefixes |= (prefixes & PREFIX_DATA);
14035 if (address_mode == mode_64bit
14036 && !(prefixes & PREFIX_ADDR))
14047 if (l != 0 || len != 1)
14052 if (need_vex && vex.prefix)
14054 if (vex.prefix == DATA_PREFIX_OPCODE)
14061 if (prefixes & PREFIX_DATA)
14065 used_prefixes |= (prefixes & PREFIX_DATA);
14069 if (l == 0 && len == 1)
14071 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14082 if (l != 1 || len != 2 || last[0] != 'X')
14090 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14092 switch (vex.length)
14106 if (l == 0 && len == 1)
14108 /* operand size flag for cwtl, cbtw */
14117 else if (sizeflag & DFLAG)
14121 if (!(rex & REX_W))
14122 used_prefixes |= (prefixes & PREFIX_DATA);
14129 && last[0] != 'L'))
14136 if (last[0] == 'X')
14137 *obufp++ = vex.w ? 'd': 's';
14139 *obufp++ = vex.w ? 'q': 'd';
14146 mnemonicendp = obufp;
14151 oappend (const char *s)
14153 obufp = stpcpy (obufp, s);
14159 /* Only print the active segment register. */
14160 if (!active_seg_prefix)
14163 used_prefixes |= active_seg_prefix;
14164 switch (active_seg_prefix)
14167 oappend_maybe_intel ("%cs:");
14170 oappend_maybe_intel ("%ds:");
14173 oappend_maybe_intel ("%ss:");
14176 oappend_maybe_intel ("%es:");
14179 oappend_maybe_intel ("%fs:");
14182 oappend_maybe_intel ("%gs:");
14190 OP_indirE (int bytemode, int sizeflag)
14194 OP_E (bytemode, sizeflag);
14198 print_operand_value (char *buf, int hex, bfd_vma disp)
14200 if (address_mode == mode_64bit)
14208 sprintf_vma (tmp, disp);
14209 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14210 strcpy (buf + 2, tmp + i);
14214 bfd_signed_vma v = disp;
14221 /* Check for possible overflow on 0x8000000000000000. */
14224 strcpy (buf, "9223372036854775808");
14238 tmp[28 - i] = (v % 10) + '0';
14242 strcpy (buf, tmp + 29 - i);
14248 sprintf (buf, "0x%x", (unsigned int) disp);
14250 sprintf (buf, "%d", (int) disp);
14254 /* Put DISP in BUF as signed hex number. */
14257 print_displacement (char *buf, bfd_vma disp)
14259 bfd_signed_vma val = disp;
14268 /* Check for possible overflow. */
14271 switch (address_mode)
14274 strcpy (buf + j, "0x8000000000000000");
14277 strcpy (buf + j, "0x80000000");
14280 strcpy (buf + j, "0x8000");
14290 sprintf_vma (tmp, (bfd_vma) val);
14291 for (i = 0; tmp[i] == '0'; i++)
14293 if (tmp[i] == '\0')
14295 strcpy (buf + j, tmp + i);
14299 intel_operand_size (int bytemode, int sizeflag)
14303 && (bytemode == x_mode
14304 || bytemode == evex_half_bcst_xmmq_mode))
14307 oappend ("QWORD PTR ");
14309 oappend ("DWORD PTR ");
14318 oappend ("BYTE PTR ");
14323 case dqw_swap_mode:
14324 oappend ("WORD PTR ");
14327 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14329 oappend ("QWORD PTR ");
14338 oappend ("QWORD PTR ");
14341 if ((sizeflag & DFLAG) || bytemode == dq_mode)
14342 oappend ("DWORD PTR ");
14344 oappend ("WORD PTR ");
14345 used_prefixes |= (prefixes & PREFIX_DATA);
14349 if ((rex & REX_W) || (sizeflag & DFLAG))
14351 oappend ("WORD PTR ");
14352 if (!(rex & REX_W))
14353 used_prefixes |= (prefixes & PREFIX_DATA);
14356 if (sizeflag & DFLAG)
14357 oappend ("QWORD PTR ");
14359 oappend ("DWORD PTR ");
14360 used_prefixes |= (prefixes & PREFIX_DATA);
14363 case d_scalar_mode:
14364 case d_scalar_swap_mode:
14367 oappend ("DWORD PTR ");
14370 case q_scalar_mode:
14371 case q_scalar_swap_mode:
14373 oappend ("QWORD PTR ");
14376 if (address_mode == mode_64bit)
14377 oappend ("QWORD PTR ");
14379 oappend ("DWORD PTR ");
14382 if (sizeflag & DFLAG)
14383 oappend ("FWORD PTR ");
14385 oappend ("DWORD PTR ");
14386 used_prefixes |= (prefixes & PREFIX_DATA);
14389 oappend ("TBYTE PTR ");
14393 case evex_x_gscat_mode:
14394 case evex_x_nobcst_mode:
14397 switch (vex.length)
14400 oappend ("XMMWORD PTR ");
14403 oappend ("YMMWORD PTR ");
14406 oappend ("ZMMWORD PTR ");
14413 oappend ("XMMWORD PTR ");
14416 oappend ("XMMWORD PTR ");
14419 oappend ("YMMWORD PTR ");
14422 case evex_half_bcst_xmmq_mode:
14426 switch (vex.length)
14429 oappend ("QWORD PTR ");
14432 oappend ("XMMWORD PTR ");
14435 oappend ("YMMWORD PTR ");
14445 switch (vex.length)
14450 oappend ("BYTE PTR ");
14460 switch (vex.length)
14465 oappend ("WORD PTR ");
14475 switch (vex.length)
14480 oappend ("DWORD PTR ");
14490 switch (vex.length)
14495 oappend ("QWORD PTR ");
14505 switch (vex.length)
14508 oappend ("WORD PTR ");
14511 oappend ("DWORD PTR ");
14514 oappend ("QWORD PTR ");
14524 switch (vex.length)
14527 oappend ("DWORD PTR ");
14530 oappend ("QWORD PTR ");
14533 oappend ("XMMWORD PTR ");
14543 switch (vex.length)
14546 oappend ("QWORD PTR ");
14549 oappend ("YMMWORD PTR ");
14552 oappend ("ZMMWORD PTR ");
14562 switch (vex.length)
14566 oappend ("XMMWORD PTR ");
14573 oappend ("OWORD PTR ");
14576 case vex_w_dq_mode:
14577 case vex_scalar_w_dq_mode:
14582 oappend ("QWORD PTR ");
14584 oappend ("DWORD PTR ");
14586 case vex_vsib_d_w_dq_mode:
14587 case vex_vsib_q_w_dq_mode:
14594 oappend ("QWORD PTR ");
14596 oappend ("DWORD PTR ");
14600 switch (vex.length)
14603 oappend ("XMMWORD PTR ");
14606 oappend ("YMMWORD PTR ");
14609 oappend ("ZMMWORD PTR ");
14616 case vex_vsib_q_w_d_mode:
14617 case vex_vsib_d_w_d_mode:
14618 if (!need_vex || !vex.evex)
14621 switch (vex.length)
14624 oappend ("QWORD PTR ");
14627 oappend ("XMMWORD PTR ");
14630 oappend ("YMMWORD PTR ");
14638 if (!need_vex || vex.length != 128)
14641 oappend ("DWORD PTR ");
14643 oappend ("BYTE PTR ");
14649 oappend ("QWORD PTR ");
14651 oappend ("WORD PTR ");
14660 OP_E_register (int bytemode, int sizeflag)
14662 int reg = modrm.rm;
14663 const char **names;
14669 if ((sizeflag & SUFFIX_ALWAYS)
14670 && (bytemode == b_swap_mode
14671 || bytemode == v_swap_mode
14672 || bytemode == dqw_swap_mode))
14698 names = address_mode == mode_64bit ? names64 : names32;
14704 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14717 case dqw_swap_mode:
14723 if ((sizeflag & DFLAG)
14724 || (bytemode != v_mode
14725 && bytemode != v_swap_mode))
14729 used_prefixes |= (prefixes & PREFIX_DATA);
14734 names = names_mask;
14739 oappend (INTERNAL_DISASSEMBLER_ERROR);
14742 oappend (names[reg]);
14746 OP_E_memory (int bytemode, int sizeflag)
14749 int add = (rex & REX_B) ? 8 : 0;
14755 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
14757 && bytemode != x_mode
14758 && bytemode != xmmq_mode
14759 && bytemode != evex_half_bcst_xmmq_mode)
14768 case dqw_swap_mode:
14775 case vex_vsib_d_w_dq_mode:
14776 case vex_vsib_d_w_d_mode:
14777 case vex_vsib_q_w_dq_mode:
14778 case vex_vsib_q_w_d_mode:
14779 case evex_x_gscat_mode:
14781 shift = vex.w ? 3 : 2;
14784 case evex_half_bcst_xmmq_mode:
14788 shift = vex.w ? 3 : 2;
14791 /* Fall through if vex.b == 0. */
14795 case evex_x_nobcst_mode:
14797 switch (vex.length)
14820 case q_scalar_mode:
14822 case q_scalar_swap_mode:
14828 case d_scalar_mode:
14830 case d_scalar_swap_mode:
14842 /* Make necessary corrections to shift for modes that need it.
14843 For these modes we currently have shift 4, 5 or 6 depending on
14844 vex.length (it corresponds to xmmword, ymmword or zmmword
14845 operand). We might want to make it 3, 4 or 5 (e.g. for
14846 xmmq_mode). In case of broadcast enabled the corrections
14847 aren't needed, as element size is always 32 or 64 bits. */
14849 && (bytemode == xmmq_mode
14850 || bytemode == evex_half_bcst_xmmq_mode))
14852 else if (bytemode == xmmqd_mode)
14854 else if (bytemode == xmmdw_mode)
14856 else if (bytemode == ymmq_mode && vex.length == 128)
14864 intel_operand_size (bytemode, sizeflag);
14867 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14869 /* 32/64 bit address mode */
14878 int addr32flag = !((sizeflag & AFLAG)
14879 || bytemode == v_bnd_mode
14880 || bytemode == bnd_mode);
14881 const char **indexes64 = names64;
14882 const char **indexes32 = names32;
14892 vindex = sib.index;
14898 case vex_vsib_d_w_dq_mode:
14899 case vex_vsib_d_w_d_mode:
14900 case vex_vsib_q_w_dq_mode:
14901 case vex_vsib_q_w_d_mode:
14911 switch (vex.length)
14914 indexes64 = indexes32 = names_xmm;
14918 || bytemode == vex_vsib_q_w_dq_mode
14919 || bytemode == vex_vsib_q_w_d_mode)
14920 indexes64 = indexes32 = names_ymm;
14922 indexes64 = indexes32 = names_xmm;
14926 || bytemode == vex_vsib_q_w_dq_mode
14927 || bytemode == vex_vsib_q_w_d_mode)
14928 indexes64 = indexes32 = names_zmm;
14930 indexes64 = indexes32 = names_ymm;
14937 haveindex = vindex != 4;
14944 rbase = base + add;
14952 if (address_mode == mode_64bit && !havesib)
14958 FETCH_DATA (the_info, codep + 1);
14960 if ((disp & 0x80) != 0)
14962 if (vex.evex && shift > 0)
14970 /* In 32bit mode, we need index register to tell [offset] from
14971 [eiz*1 + offset]. */
14972 needindex = (havesib
14975 && address_mode == mode_32bit);
14976 havedisp = (havebase
14978 || (havesib && (haveindex || scale != 0)));
14981 if (modrm.mod != 0 || base == 5)
14983 if (havedisp || riprel)
14984 print_displacement (scratchbuf, disp);
14986 print_operand_value (scratchbuf, 1, disp);
14987 oappend (scratchbuf);
14991 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
14995 if ((havebase || haveindex || riprel)
14996 && (bytemode != v_bnd_mode)
14997 && (bytemode != bnd_mode))
14998 used_prefixes |= PREFIX_ADDR;
15000 if (havedisp || (intel_syntax && riprel))
15002 *obufp++ = open_char;
15003 if (intel_syntax && riprel)
15006 oappend (sizeflag & AFLAG ? "rip" : "eip");
15010 oappend (address_mode == mode_64bit && !addr32flag
15011 ? names64[rbase] : names32[rbase]);
15014 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15015 print index to tell base + index from base. */
15019 || (havebase && base != ESP_REG_NUM))
15021 if (!intel_syntax || havebase)
15023 *obufp++ = separator_char;
15027 oappend (address_mode == mode_64bit && !addr32flag
15028 ? indexes64[vindex] : indexes32[vindex]);
15030 oappend (address_mode == mode_64bit && !addr32flag
15031 ? index64 : index32);
15033 *obufp++ = scale_char;
15035 sprintf (scratchbuf, "%d", 1 << scale);
15036 oappend (scratchbuf);
15040 && (disp || modrm.mod != 0 || base == 5))
15042 if (!havedisp || (bfd_signed_vma) disp >= 0)
15047 else if (modrm.mod != 1 && disp != -disp)
15051 disp = - (bfd_signed_vma) disp;
15055 print_displacement (scratchbuf, disp);
15057 print_operand_value (scratchbuf, 1, disp);
15058 oappend (scratchbuf);
15061 *obufp++ = close_char;
15064 else if (intel_syntax)
15066 if (modrm.mod != 0 || base == 5)
15068 if (!active_seg_prefix)
15070 oappend (names_seg[ds_reg - es_reg]);
15073 print_operand_value (scratchbuf, 1, disp);
15074 oappend (scratchbuf);
15080 /* 16 bit address mode */
15081 used_prefixes |= prefixes & PREFIX_ADDR;
15088 if ((disp & 0x8000) != 0)
15093 FETCH_DATA (the_info, codep + 1);
15095 if ((disp & 0x80) != 0)
15100 if ((disp & 0x8000) != 0)
15106 if (modrm.mod != 0 || modrm.rm == 6)
15108 print_displacement (scratchbuf, disp);
15109 oappend (scratchbuf);
15112 if (modrm.mod != 0 || modrm.rm != 6)
15114 *obufp++ = open_char;
15116 oappend (index16[modrm.rm]);
15118 && (disp || modrm.mod != 0 || modrm.rm == 6))
15120 if ((bfd_signed_vma) disp >= 0)
15125 else if (modrm.mod != 1)
15129 disp = - (bfd_signed_vma) disp;
15132 print_displacement (scratchbuf, disp);
15133 oappend (scratchbuf);
15136 *obufp++ = close_char;
15139 else if (intel_syntax)
15141 if (!active_seg_prefix)
15143 oappend (names_seg[ds_reg - es_reg]);
15146 print_operand_value (scratchbuf, 1, disp & 0xffff);
15147 oappend (scratchbuf);
15150 if (vex.evex && vex.b
15151 && (bytemode == x_mode
15152 || bytemode == xmmq_mode
15153 || bytemode == evex_half_bcst_xmmq_mode))
15156 || bytemode == xmmq_mode
15157 || bytemode == evex_half_bcst_xmmq_mode)
15159 switch (vex.length)
15162 oappend ("{1to2}");
15165 oappend ("{1to4}");
15168 oappend ("{1to8}");
15176 switch (vex.length)
15179 oappend ("{1to4}");
15182 oappend ("{1to8}");
15185 oappend ("{1to16}");
15195 OP_E (int bytemode, int sizeflag)
15197 /* Skip mod/rm byte. */
15201 if (modrm.mod == 3)
15202 OP_E_register (bytemode, sizeflag);
15204 OP_E_memory (bytemode, sizeflag);
15208 OP_G (int bytemode, int sizeflag)
15219 oappend (names8rex[modrm.reg + add]);
15221 oappend (names8[modrm.reg + add]);
15224 oappend (names16[modrm.reg + add]);
15229 oappend (names32[modrm.reg + add]);
15232 oappend (names64[modrm.reg + add]);
15235 oappend (names_bnd[modrm.reg]);
15242 case dqw_swap_mode:
15245 oappend (names64[modrm.reg + add]);
15248 if ((sizeflag & DFLAG) || bytemode != v_mode)
15249 oappend (names32[modrm.reg + add]);
15251 oappend (names16[modrm.reg + add]);
15252 used_prefixes |= (prefixes & PREFIX_DATA);
15256 if (address_mode == mode_64bit)
15257 oappend (names64[modrm.reg + add]);
15259 oappend (names32[modrm.reg + add]);
15263 oappend (names_mask[modrm.reg + add]);
15266 oappend (INTERNAL_DISASSEMBLER_ERROR);
15279 FETCH_DATA (the_info, codep + 8);
15280 a = *codep++ & 0xff;
15281 a |= (*codep++ & 0xff) << 8;
15282 a |= (*codep++ & 0xff) << 16;
15283 a |= (*codep++ & 0xff) << 24;
15284 b = *codep++ & 0xff;
15285 b |= (*codep++ & 0xff) << 8;
15286 b |= (*codep++ & 0xff) << 16;
15287 b |= (*codep++ & 0xff) << 24;
15288 x = a + ((bfd_vma) b << 32);
15296 static bfd_signed_vma
15299 bfd_signed_vma x = 0;
15301 FETCH_DATA (the_info, codep + 4);
15302 x = *codep++ & (bfd_signed_vma) 0xff;
15303 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15304 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15305 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15309 static bfd_signed_vma
15312 bfd_signed_vma x = 0;
15314 FETCH_DATA (the_info, codep + 4);
15315 x = *codep++ & (bfd_signed_vma) 0xff;
15316 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15317 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15318 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15320 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15330 FETCH_DATA (the_info, codep + 2);
15331 x = *codep++ & 0xff;
15332 x |= (*codep++ & 0xff) << 8;
15337 set_op (bfd_vma op, int riprel)
15339 op_index[op_ad] = op_ad;
15340 if (address_mode == mode_64bit)
15342 op_address[op_ad] = op;
15343 op_riprel[op_ad] = riprel;
15347 /* Mask to get a 32-bit address. */
15348 op_address[op_ad] = op & 0xffffffff;
15349 op_riprel[op_ad] = riprel & 0xffffffff;
15354 OP_REG (int code, int sizeflag)
15361 case es_reg: case ss_reg: case cs_reg:
15362 case ds_reg: case fs_reg: case gs_reg:
15363 oappend (names_seg[code - es_reg]);
15375 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15376 case sp_reg: case bp_reg: case si_reg: case di_reg:
15377 s = names16[code - ax_reg + add];
15379 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15380 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15383 s = names8rex[code - al_reg + add];
15385 s = names8[code - al_reg];
15387 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15388 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15389 if (address_mode == mode_64bit
15390 && ((sizeflag & DFLAG) || (rex & REX_W)))
15392 s = names64[code - rAX_reg + add];
15395 code += eAX_reg - rAX_reg;
15396 /* Fall through. */
15397 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15398 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15401 s = names64[code - eAX_reg + add];
15404 if (sizeflag & DFLAG)
15405 s = names32[code - eAX_reg + add];
15407 s = names16[code - eAX_reg + add];
15408 used_prefixes |= (prefixes & PREFIX_DATA);
15412 s = INTERNAL_DISASSEMBLER_ERROR;
15419 OP_IMREG (int code, int sizeflag)
15431 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15432 case sp_reg: case bp_reg: case si_reg: case di_reg:
15433 s = names16[code - ax_reg];
15435 case es_reg: case ss_reg: case cs_reg:
15436 case ds_reg: case fs_reg: case gs_reg:
15437 s = names_seg[code - es_reg];
15439 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15440 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15443 s = names8rex[code - al_reg];
15445 s = names8[code - al_reg];
15447 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15448 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15451 s = names64[code - eAX_reg];
15454 if (sizeflag & DFLAG)
15455 s = names32[code - eAX_reg];
15457 s = names16[code - eAX_reg];
15458 used_prefixes |= (prefixes & PREFIX_DATA);
15461 case z_mode_ax_reg:
15462 if ((rex & REX_W) || (sizeflag & DFLAG))
15466 if (!(rex & REX_W))
15467 used_prefixes |= (prefixes & PREFIX_DATA);
15470 s = INTERNAL_DISASSEMBLER_ERROR;
15477 OP_I (int bytemode, int sizeflag)
15480 bfd_signed_vma mask = -1;
15485 FETCH_DATA (the_info, codep + 1);
15490 if (address_mode == mode_64bit)
15495 /* Fall through. */
15502 if (sizeflag & DFLAG)
15512 used_prefixes |= (prefixes & PREFIX_DATA);
15524 oappend (INTERNAL_DISASSEMBLER_ERROR);
15529 scratchbuf[0] = '$';
15530 print_operand_value (scratchbuf + 1, 1, op);
15531 oappend_maybe_intel (scratchbuf);
15532 scratchbuf[0] = '\0';
15536 OP_I64 (int bytemode, int sizeflag)
15539 bfd_signed_vma mask = -1;
15541 if (address_mode != mode_64bit)
15543 OP_I (bytemode, sizeflag);
15550 FETCH_DATA (the_info, codep + 1);
15560 if (sizeflag & DFLAG)
15570 used_prefixes |= (prefixes & PREFIX_DATA);
15578 oappend (INTERNAL_DISASSEMBLER_ERROR);
15583 scratchbuf[0] = '$';
15584 print_operand_value (scratchbuf + 1, 1, op);
15585 oappend_maybe_intel (scratchbuf);
15586 scratchbuf[0] = '\0';
15590 OP_sI (int bytemode, int sizeflag)
15598 FETCH_DATA (the_info, codep + 1);
15600 if ((op & 0x80) != 0)
15602 if (bytemode == b_T_mode)
15604 if (address_mode != mode_64bit
15605 || !((sizeflag & DFLAG) || (rex & REX_W)))
15607 /* The operand-size prefix is overridden by a REX prefix. */
15608 if ((sizeflag & DFLAG) || (rex & REX_W))
15616 if (!(rex & REX_W))
15618 if (sizeflag & DFLAG)
15626 /* The operand-size prefix is overridden by a REX prefix. */
15627 if ((sizeflag & DFLAG) || (rex & REX_W))
15633 oappend (INTERNAL_DISASSEMBLER_ERROR);
15637 scratchbuf[0] = '$';
15638 print_operand_value (scratchbuf + 1, 1, op);
15639 oappend_maybe_intel (scratchbuf);
15643 OP_J (int bytemode, int sizeflag)
15647 bfd_vma segment = 0;
15652 FETCH_DATA (the_info, codep + 1);
15654 if ((disp & 0x80) != 0)
15659 if ((sizeflag & DFLAG) || (rex & REX_W))
15664 if ((disp & 0x8000) != 0)
15666 /* In 16bit mode, address is wrapped around at 64k within
15667 the same segment. Otherwise, a data16 prefix on a jump
15668 instruction means that the pc is masked to 16 bits after
15669 the displacement is added! */
15671 if ((prefixes & PREFIX_DATA) == 0)
15672 segment = ((start_pc + codep - start_codep)
15673 & ~((bfd_vma) 0xffff));
15675 if (!(rex & REX_W))
15676 used_prefixes |= (prefixes & PREFIX_DATA);
15679 oappend (INTERNAL_DISASSEMBLER_ERROR);
15682 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15684 print_operand_value (scratchbuf, 1, disp);
15685 oappend (scratchbuf);
15689 OP_SEG (int bytemode, int sizeflag)
15691 if (bytemode == w_mode)
15692 oappend (names_seg[modrm.reg]);
15694 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15698 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15702 if (sizeflag & DFLAG)
15712 used_prefixes |= (prefixes & PREFIX_DATA);
15714 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15716 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15717 oappend (scratchbuf);
15721 OP_OFF (int bytemode, int sizeflag)
15725 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15726 intel_operand_size (bytemode, sizeflag);
15729 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15736 if (!active_seg_prefix)
15738 oappend (names_seg[ds_reg - es_reg]);
15742 print_operand_value (scratchbuf, 1, off);
15743 oappend (scratchbuf);
15747 OP_OFF64 (int bytemode, int sizeflag)
15751 if (address_mode != mode_64bit
15752 || (prefixes & PREFIX_ADDR))
15754 OP_OFF (bytemode, sizeflag);
15758 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15759 intel_operand_size (bytemode, sizeflag);
15766 if (!active_seg_prefix)
15768 oappend (names_seg[ds_reg - es_reg]);
15772 print_operand_value (scratchbuf, 1, off);
15773 oappend (scratchbuf);
15777 ptr_reg (int code, int sizeflag)
15781 *obufp++ = open_char;
15782 used_prefixes |= (prefixes & PREFIX_ADDR);
15783 if (address_mode == mode_64bit)
15785 if (!(sizeflag & AFLAG))
15786 s = names32[code - eAX_reg];
15788 s = names64[code - eAX_reg];
15790 else if (sizeflag & AFLAG)
15791 s = names32[code - eAX_reg];
15793 s = names16[code - eAX_reg];
15795 *obufp++ = close_char;
15800 OP_ESreg (int code, int sizeflag)
15806 case 0x6d: /* insw/insl */
15807 intel_operand_size (z_mode, sizeflag);
15809 case 0xa5: /* movsw/movsl/movsq */
15810 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15811 case 0xab: /* stosw/stosl */
15812 case 0xaf: /* scasw/scasl */
15813 intel_operand_size (v_mode, sizeflag);
15816 intel_operand_size (b_mode, sizeflag);
15819 oappend_maybe_intel ("%es:");
15820 ptr_reg (code, sizeflag);
15824 OP_DSreg (int code, int sizeflag)
15830 case 0x6f: /* outsw/outsl */
15831 intel_operand_size (z_mode, sizeflag);
15833 case 0xa5: /* movsw/movsl/movsq */
15834 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15835 case 0xad: /* lodsw/lodsl/lodsq */
15836 intel_operand_size (v_mode, sizeflag);
15839 intel_operand_size (b_mode, sizeflag);
15842 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15843 default segment register DS is printed. */
15844 if (!active_seg_prefix)
15845 active_seg_prefix = PREFIX_DS;
15847 ptr_reg (code, sizeflag);
15851 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15859 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15861 all_prefixes[last_lock_prefix] = 0;
15862 used_prefixes |= PREFIX_LOCK;
15867 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15868 oappend_maybe_intel (scratchbuf);
15872 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15881 sprintf (scratchbuf, "db%d", modrm.reg + add);
15883 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15884 oappend (scratchbuf);
15888 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15890 sprintf (scratchbuf, "%%tr%d", modrm.reg);
15891 oappend_maybe_intel (scratchbuf);
15895 OP_R (int bytemode, int sizeflag)
15897 /* Skip mod/rm byte. */
15900 OP_E_register (bytemode, sizeflag);
15904 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15906 int reg = modrm.reg;
15907 const char **names;
15909 used_prefixes |= (prefixes & PREFIX_DATA);
15910 if (prefixes & PREFIX_DATA)
15919 oappend (names[reg]);
15923 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15925 int reg = modrm.reg;
15926 const char **names;
15938 && bytemode != xmm_mode
15939 && bytemode != xmmq_mode
15940 && bytemode != evex_half_bcst_xmmq_mode
15941 && bytemode != ymm_mode
15942 && bytemode != scalar_mode)
15944 switch (vex.length)
15951 || (bytemode != vex_vsib_q_w_dq_mode
15952 && bytemode != vex_vsib_q_w_d_mode))
15964 else if (bytemode == xmmq_mode
15965 || bytemode == evex_half_bcst_xmmq_mode)
15967 switch (vex.length)
15980 else if (bytemode == ymm_mode)
15984 oappend (names[reg]);
15988 OP_EM (int bytemode, int sizeflag)
15991 const char **names;
15993 if (modrm.mod != 3)
15996 && (bytemode == v_mode || bytemode == v_swap_mode))
15998 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15999 used_prefixes |= (prefixes & PREFIX_DATA);
16001 OP_E (bytemode, sizeflag);
16005 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16008 /* Skip mod/rm byte. */
16011 used_prefixes |= (prefixes & PREFIX_DATA);
16013 if (prefixes & PREFIX_DATA)
16022 oappend (names[reg]);
16025 /* cvt* are the only instructions in sse2 which have
16026 both SSE and MMX operands and also have 0x66 prefix
16027 in their opcode. 0x66 was originally used to differentiate
16028 between SSE and MMX instruction(operands). So we have to handle the
16029 cvt* separately using OP_EMC and OP_MXC */
16031 OP_EMC (int bytemode, int sizeflag)
16033 if (modrm.mod != 3)
16035 if (intel_syntax && bytemode == v_mode)
16037 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16038 used_prefixes |= (prefixes & PREFIX_DATA);
16040 OP_E (bytemode, sizeflag);
16044 /* Skip mod/rm byte. */
16047 used_prefixes |= (prefixes & PREFIX_DATA);
16048 oappend (names_mm[modrm.rm]);
16052 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16054 used_prefixes |= (prefixes & PREFIX_DATA);
16055 oappend (names_mm[modrm.reg]);
16059 OP_EX (int bytemode, int sizeflag)
16062 const char **names;
16064 /* Skip mod/rm byte. */
16068 if (modrm.mod != 3)
16070 OP_E_memory (bytemode, sizeflag);
16085 if ((sizeflag & SUFFIX_ALWAYS)
16086 && (bytemode == x_swap_mode
16087 || bytemode == d_swap_mode
16088 || bytemode == dqw_swap_mode
16089 || bytemode == d_scalar_swap_mode
16090 || bytemode == q_swap_mode
16091 || bytemode == q_scalar_swap_mode))
16095 && bytemode != xmm_mode
16096 && bytemode != xmmdw_mode
16097 && bytemode != xmmqd_mode
16098 && bytemode != xmm_mb_mode
16099 && bytemode != xmm_mw_mode
16100 && bytemode != xmm_md_mode
16101 && bytemode != xmm_mq_mode
16102 && bytemode != xmm_mdq_mode
16103 && bytemode != xmmq_mode
16104 && bytemode != evex_half_bcst_xmmq_mode
16105 && bytemode != ymm_mode
16106 && bytemode != d_scalar_mode
16107 && bytemode != d_scalar_swap_mode
16108 && bytemode != q_scalar_mode
16109 && bytemode != q_scalar_swap_mode
16110 && bytemode != vex_scalar_w_dq_mode)
16112 switch (vex.length)
16127 else if (bytemode == xmmq_mode
16128 || bytemode == evex_half_bcst_xmmq_mode)
16130 switch (vex.length)
16143 else if (bytemode == ymm_mode)
16147 oappend (names[reg]);
16151 OP_MS (int bytemode, int sizeflag)
16153 if (modrm.mod == 3)
16154 OP_EM (bytemode, sizeflag);
16160 OP_XS (int bytemode, int sizeflag)
16162 if (modrm.mod == 3)
16163 OP_EX (bytemode, sizeflag);
16169 OP_M (int bytemode, int sizeflag)
16171 if (modrm.mod == 3)
16172 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16175 OP_E (bytemode, sizeflag);
16179 OP_0f07 (int bytemode, int sizeflag)
16181 if (modrm.mod != 3 || modrm.rm != 0)
16184 OP_E (bytemode, sizeflag);
16187 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16188 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16191 NOP_Fixup1 (int bytemode, int sizeflag)
16193 if ((prefixes & PREFIX_DATA) != 0
16196 && address_mode == mode_64bit))
16197 OP_REG (bytemode, sizeflag);
16199 strcpy (obuf, "nop");
16203 NOP_Fixup2 (int bytemode, int sizeflag)
16205 if ((prefixes & PREFIX_DATA) != 0
16208 && address_mode == mode_64bit))
16209 OP_IMREG (bytemode, sizeflag);
16212 static const char *const Suffix3DNow[] = {
16213 /* 00 */ NULL, NULL, NULL, NULL,
16214 /* 04 */ NULL, NULL, NULL, NULL,
16215 /* 08 */ NULL, NULL, NULL, NULL,
16216 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
16217 /* 10 */ NULL, NULL, NULL, NULL,
16218 /* 14 */ NULL, NULL, NULL, NULL,
16219 /* 18 */ NULL, NULL, NULL, NULL,
16220 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
16221 /* 20 */ NULL, NULL, NULL, NULL,
16222 /* 24 */ NULL, NULL, NULL, NULL,
16223 /* 28 */ NULL, NULL, NULL, NULL,
16224 /* 2C */ NULL, NULL, NULL, NULL,
16225 /* 30 */ NULL, NULL, NULL, NULL,
16226 /* 34 */ NULL, NULL, NULL, NULL,
16227 /* 38 */ NULL, NULL, NULL, NULL,
16228 /* 3C */ NULL, NULL, NULL, NULL,
16229 /* 40 */ NULL, NULL, NULL, NULL,
16230 /* 44 */ NULL, NULL, NULL, NULL,
16231 /* 48 */ NULL, NULL, NULL, NULL,
16232 /* 4C */ NULL, NULL, NULL, NULL,
16233 /* 50 */ NULL, NULL, NULL, NULL,
16234 /* 54 */ NULL, NULL, NULL, NULL,
16235 /* 58 */ NULL, NULL, NULL, NULL,
16236 /* 5C */ NULL, NULL, NULL, NULL,
16237 /* 60 */ NULL, NULL, NULL, NULL,
16238 /* 64 */ NULL, NULL, NULL, NULL,
16239 /* 68 */ NULL, NULL, NULL, NULL,
16240 /* 6C */ NULL, NULL, NULL, NULL,
16241 /* 70 */ NULL, NULL, NULL, NULL,
16242 /* 74 */ NULL, NULL, NULL, NULL,
16243 /* 78 */ NULL, NULL, NULL, NULL,
16244 /* 7C */ NULL, NULL, NULL, NULL,
16245 /* 80 */ NULL, NULL, NULL, NULL,
16246 /* 84 */ NULL, NULL, NULL, NULL,
16247 /* 88 */ NULL, NULL, "pfnacc", NULL,
16248 /* 8C */ NULL, NULL, "pfpnacc", NULL,
16249 /* 90 */ "pfcmpge", NULL, NULL, NULL,
16250 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
16251 /* 98 */ NULL, NULL, "pfsub", NULL,
16252 /* 9C */ NULL, NULL, "pfadd", NULL,
16253 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
16254 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
16255 /* A8 */ NULL, NULL, "pfsubr", NULL,
16256 /* AC */ NULL, NULL, "pfacc", NULL,
16257 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
16258 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
16259 /* B8 */ NULL, NULL, NULL, "pswapd",
16260 /* BC */ NULL, NULL, NULL, "pavgusb",
16261 /* C0 */ NULL, NULL, NULL, NULL,
16262 /* C4 */ NULL, NULL, NULL, NULL,
16263 /* C8 */ NULL, NULL, NULL, NULL,
16264 /* CC */ NULL, NULL, NULL, NULL,
16265 /* D0 */ NULL, NULL, NULL, NULL,
16266 /* D4 */ NULL, NULL, NULL, NULL,
16267 /* D8 */ NULL, NULL, NULL, NULL,
16268 /* DC */ NULL, NULL, NULL, NULL,
16269 /* E0 */ NULL, NULL, NULL, NULL,
16270 /* E4 */ NULL, NULL, NULL, NULL,
16271 /* E8 */ NULL, NULL, NULL, NULL,
16272 /* EC */ NULL, NULL, NULL, NULL,
16273 /* F0 */ NULL, NULL, NULL, NULL,
16274 /* F4 */ NULL, NULL, NULL, NULL,
16275 /* F8 */ NULL, NULL, NULL, NULL,
16276 /* FC */ NULL, NULL, NULL, NULL,
16280 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16282 const char *mnemonic;
16284 FETCH_DATA (the_info, codep + 1);
16285 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16286 place where an 8-bit immediate would normally go. ie. the last
16287 byte of the instruction. */
16288 obufp = mnemonicendp;
16289 mnemonic = Suffix3DNow[*codep++ & 0xff];
16291 oappend (mnemonic);
16294 /* Since a variable sized modrm/sib chunk is between the start
16295 of the opcode (0x0f0f) and the opcode suffix, we need to do
16296 all the modrm processing first, and don't know until now that
16297 we have a bad opcode. This necessitates some cleaning up. */
16298 op_out[0][0] = '\0';
16299 op_out[1][0] = '\0';
16302 mnemonicendp = obufp;
16305 static struct op simd_cmp_op[] =
16307 { STRING_COMMA_LEN ("eq") },
16308 { STRING_COMMA_LEN ("lt") },
16309 { STRING_COMMA_LEN ("le") },
16310 { STRING_COMMA_LEN ("unord") },
16311 { STRING_COMMA_LEN ("neq") },
16312 { STRING_COMMA_LEN ("nlt") },
16313 { STRING_COMMA_LEN ("nle") },
16314 { STRING_COMMA_LEN ("ord") }
16318 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16320 unsigned int cmp_type;
16322 FETCH_DATA (the_info, codep + 1);
16323 cmp_type = *codep++ & 0xff;
16324 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16327 char *p = mnemonicendp - 2;
16331 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16332 mnemonicendp += simd_cmp_op[cmp_type].len;
16336 /* We have a reserved extension byte. Output it directly. */
16337 scratchbuf[0] = '$';
16338 print_operand_value (scratchbuf + 1, 1, cmp_type);
16339 oappend_maybe_intel (scratchbuf);
16340 scratchbuf[0] = '\0';
16345 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16346 int sizeflag ATTRIBUTE_UNUSED)
16348 /* mwait %eax,%ecx */
16351 const char **names = (address_mode == mode_64bit
16352 ? names64 : names32);
16353 strcpy (op_out[0], names[0]);
16354 strcpy (op_out[1], names[1]);
16355 two_source_ops = 1;
16357 /* Skip mod/rm byte. */
16363 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16364 int sizeflag ATTRIBUTE_UNUSED)
16366 /* monitor %eax,%ecx,%edx" */
16369 const char **op1_names;
16370 const char **names = (address_mode == mode_64bit
16371 ? names64 : names32);
16373 if (!(prefixes & PREFIX_ADDR))
16374 op1_names = (address_mode == mode_16bit
16375 ? names16 : names);
16378 /* Remove "addr16/addr32". */
16379 all_prefixes[last_addr_prefix] = 0;
16380 op1_names = (address_mode != mode_32bit
16381 ? names32 : names16);
16382 used_prefixes |= PREFIX_ADDR;
16384 strcpy (op_out[0], op1_names[0]);
16385 strcpy (op_out[1], names[1]);
16386 strcpy (op_out[2], names[2]);
16387 two_source_ops = 1;
16389 /* Skip mod/rm byte. */
16397 /* Throw away prefixes and 1st. opcode byte. */
16398 codep = insn_codep + 1;
16403 REP_Fixup (int bytemode, int sizeflag)
16405 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16407 if (prefixes & PREFIX_REPZ)
16408 all_prefixes[last_repz_prefix] = REP_PREFIX;
16415 OP_IMREG (bytemode, sizeflag);
16418 OP_ESreg (bytemode, sizeflag);
16421 OP_DSreg (bytemode, sizeflag);
16429 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16433 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16435 if (prefixes & PREFIX_REPNZ)
16436 all_prefixes[last_repnz_prefix] = BND_PREFIX;
16439 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16440 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16444 HLE_Fixup1 (int bytemode, int sizeflag)
16447 && (prefixes & PREFIX_LOCK) != 0)
16449 if (prefixes & PREFIX_REPZ)
16450 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16451 if (prefixes & PREFIX_REPNZ)
16452 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16455 OP_E (bytemode, sizeflag);
16458 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16459 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16463 HLE_Fixup2 (int bytemode, int sizeflag)
16465 if (modrm.mod != 3)
16467 if (prefixes & PREFIX_REPZ)
16468 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16469 if (prefixes & PREFIX_REPNZ)
16470 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16473 OP_E (bytemode, sizeflag);
16476 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16477 "xrelease" for memory operand. No check for LOCK prefix. */
16480 HLE_Fixup3 (int bytemode, int sizeflag)
16483 && last_repz_prefix > last_repnz_prefix
16484 && (prefixes & PREFIX_REPZ) != 0)
16485 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16487 OP_E (bytemode, sizeflag);
16491 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16496 /* Change cmpxchg8b to cmpxchg16b. */
16497 char *p = mnemonicendp - 2;
16498 mnemonicendp = stpcpy (p, "16b");
16501 else if ((prefixes & PREFIX_LOCK) != 0)
16503 if (prefixes & PREFIX_REPZ)
16504 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16505 if (prefixes & PREFIX_REPNZ)
16506 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16509 OP_M (bytemode, sizeflag);
16513 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16515 const char **names;
16519 switch (vex.length)
16533 oappend (names[reg]);
16537 CRC32_Fixup (int bytemode, int sizeflag)
16539 /* Add proper suffix to "crc32". */
16540 char *p = mnemonicendp;
16559 if (sizeflag & DFLAG)
16563 used_prefixes |= (prefixes & PREFIX_DATA);
16567 oappend (INTERNAL_DISASSEMBLER_ERROR);
16574 if (modrm.mod == 3)
16578 /* Skip mod/rm byte. */
16583 add = (rex & REX_B) ? 8 : 0;
16584 if (bytemode == b_mode)
16588 oappend (names8rex[modrm.rm + add]);
16590 oappend (names8[modrm.rm + add]);
16596 oappend (names64[modrm.rm + add]);
16597 else if ((prefixes & PREFIX_DATA))
16598 oappend (names16[modrm.rm + add]);
16600 oappend (names32[modrm.rm + add]);
16604 OP_E (bytemode, sizeflag);
16608 FXSAVE_Fixup (int bytemode, int sizeflag)
16610 /* Add proper suffix to "fxsave" and "fxrstor". */
16614 char *p = mnemonicendp;
16620 OP_M (bytemode, sizeflag);
16623 /* Display the destination register operand for instructions with
16627 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16630 const char **names;
16638 reg = vex.register_specifier;
16645 if (bytemode == vex_scalar_mode)
16647 oappend (names_xmm[reg]);
16651 switch (vex.length)
16658 case vex_vsib_q_w_dq_mode:
16659 case vex_vsib_q_w_d_mode:
16670 names = names_mask;
16684 case vex_vsib_q_w_dq_mode:
16685 case vex_vsib_q_w_d_mode:
16686 names = vex.w ? names_ymm : names_xmm;
16690 names = names_mask;
16704 oappend (names[reg]);
16707 /* Get the VEX immediate byte without moving codep. */
16709 static unsigned char
16710 get_vex_imm8 (int sizeflag, int opnum)
16712 int bytes_before_imm = 0;
16714 if (modrm.mod != 3)
16716 /* There are SIB/displacement bytes. */
16717 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16719 /* 32/64 bit address mode */
16720 int base = modrm.rm;
16722 /* Check SIB byte. */
16725 FETCH_DATA (the_info, codep + 1);
16727 /* When decoding the third source, don't increase
16728 bytes_before_imm as this has already been incremented
16729 by one in OP_E_memory while decoding the second
16732 bytes_before_imm++;
16735 /* Don't increase bytes_before_imm when decoding the third source,
16736 it has already been incremented by OP_E_memory while decoding
16737 the second source operand. */
16743 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16744 SIB == 5, there is a 4 byte displacement. */
16746 /* No displacement. */
16749 /* 4 byte displacement. */
16750 bytes_before_imm += 4;
16753 /* 1 byte displacement. */
16754 bytes_before_imm++;
16761 /* 16 bit address mode */
16762 /* Don't increase bytes_before_imm when decoding the third source,
16763 it has already been incremented by OP_E_memory while decoding
16764 the second source operand. */
16770 /* When modrm.rm == 6, there is a 2 byte displacement. */
16772 /* No displacement. */
16775 /* 2 byte displacement. */
16776 bytes_before_imm += 2;
16779 /* 1 byte displacement: when decoding the third source,
16780 don't increase bytes_before_imm as this has already
16781 been incremented by one in OP_E_memory while decoding
16782 the second source operand. */
16784 bytes_before_imm++;
16792 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16793 return codep [bytes_before_imm];
16797 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16799 const char **names;
16801 if (reg == -1 && modrm.mod != 3)
16803 OP_E_memory (bytemode, sizeflag);
16815 else if (reg > 7 && address_mode != mode_64bit)
16819 switch (vex.length)
16830 oappend (names[reg]);
16834 OP_EX_VexImmW (int bytemode, int sizeflag)
16837 static unsigned char vex_imm8;
16839 if (vex_w_done == 0)
16843 /* Skip mod/rm byte. */
16847 vex_imm8 = get_vex_imm8 (sizeflag, 0);
16850 reg = vex_imm8 >> 4;
16852 OP_EX_VexReg (bytemode, sizeflag, reg);
16854 else if (vex_w_done == 1)
16859 reg = vex_imm8 >> 4;
16861 OP_EX_VexReg (bytemode, sizeflag, reg);
16865 /* Output the imm8 directly. */
16866 scratchbuf[0] = '$';
16867 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16868 oappend_maybe_intel (scratchbuf);
16869 scratchbuf[0] = '\0';
16875 OP_Vex_2src (int bytemode, int sizeflag)
16877 if (modrm.mod == 3)
16879 int reg = modrm.rm;
16883 oappend (names_xmm[reg]);
16888 && (bytemode == v_mode || bytemode == v_swap_mode))
16890 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16891 used_prefixes |= (prefixes & PREFIX_DATA);
16893 OP_E (bytemode, sizeflag);
16898 OP_Vex_2src_1 (int bytemode, int sizeflag)
16900 if (modrm.mod == 3)
16902 /* Skip mod/rm byte. */
16908 oappend (names_xmm[vex.register_specifier]);
16910 OP_Vex_2src (bytemode, sizeflag);
16914 OP_Vex_2src_2 (int bytemode, int sizeflag)
16917 OP_Vex_2src (bytemode, sizeflag);
16919 oappend (names_xmm[vex.register_specifier]);
16923 OP_EX_VexW (int bytemode, int sizeflag)
16931 /* Skip mod/rm byte. */
16936 reg = get_vex_imm8 (sizeflag, 0) >> 4;
16941 reg = get_vex_imm8 (sizeflag, 1) >> 4;
16944 OP_EX_VexReg (bytemode, sizeflag, reg);
16948 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16949 int sizeflag ATTRIBUTE_UNUSED)
16951 /* Skip the immediate byte and check for invalid bits. */
16952 FETCH_DATA (the_info, codep + 1);
16953 if (*codep++ & 0xf)
16958 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16961 const char **names;
16963 FETCH_DATA (the_info, codep + 1);
16966 if (bytemode != x_mode)
16973 if (reg > 7 && address_mode != mode_64bit)
16976 switch (vex.length)
16987 oappend (names[reg]);
16991 OP_XMM_VexW (int bytemode, int sizeflag)
16993 /* Turn off the REX.W bit since it is used for swapping operands
16996 OP_XMM (bytemode, sizeflag);
17000 OP_EX_Vex (int bytemode, int sizeflag)
17002 if (modrm.mod != 3)
17004 if (vex.register_specifier != 0)
17008 OP_EX (bytemode, sizeflag);
17012 OP_XMM_Vex (int bytemode, int sizeflag)
17014 if (modrm.mod != 3)
17016 if (vex.register_specifier != 0)
17020 OP_XMM (bytemode, sizeflag);
17024 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17026 switch (vex.length)
17029 mnemonicendp = stpcpy (obuf, "vzeroupper");
17032 mnemonicendp = stpcpy (obuf, "vzeroall");
17039 static struct op vex_cmp_op[] =
17041 { STRING_COMMA_LEN ("eq") },
17042 { STRING_COMMA_LEN ("lt") },
17043 { STRING_COMMA_LEN ("le") },
17044 { STRING_COMMA_LEN ("unord") },
17045 { STRING_COMMA_LEN ("neq") },
17046 { STRING_COMMA_LEN ("nlt") },
17047 { STRING_COMMA_LEN ("nle") },
17048 { STRING_COMMA_LEN ("ord") },
17049 { STRING_COMMA_LEN ("eq_uq") },
17050 { STRING_COMMA_LEN ("nge") },
17051 { STRING_COMMA_LEN ("ngt") },
17052 { STRING_COMMA_LEN ("false") },
17053 { STRING_COMMA_LEN ("neq_oq") },
17054 { STRING_COMMA_LEN ("ge") },
17055 { STRING_COMMA_LEN ("gt") },
17056 { STRING_COMMA_LEN ("true") },
17057 { STRING_COMMA_LEN ("eq_os") },
17058 { STRING_COMMA_LEN ("lt_oq") },
17059 { STRING_COMMA_LEN ("le_oq") },
17060 { STRING_COMMA_LEN ("unord_s") },
17061 { STRING_COMMA_LEN ("neq_us") },
17062 { STRING_COMMA_LEN ("nlt_uq") },
17063 { STRING_COMMA_LEN ("nle_uq") },
17064 { STRING_COMMA_LEN ("ord_s") },
17065 { STRING_COMMA_LEN ("eq_us") },
17066 { STRING_COMMA_LEN ("nge_uq") },
17067 { STRING_COMMA_LEN ("ngt_uq") },
17068 { STRING_COMMA_LEN ("false_os") },
17069 { STRING_COMMA_LEN ("neq_os") },
17070 { STRING_COMMA_LEN ("ge_oq") },
17071 { STRING_COMMA_LEN ("gt_oq") },
17072 { STRING_COMMA_LEN ("true_us") },
17076 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17078 unsigned int cmp_type;
17080 FETCH_DATA (the_info, codep + 1);
17081 cmp_type = *codep++ & 0xff;
17082 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17085 char *p = mnemonicendp - 2;
17089 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17090 mnemonicendp += vex_cmp_op[cmp_type].len;
17094 /* We have a reserved extension byte. Output it directly. */
17095 scratchbuf[0] = '$';
17096 print_operand_value (scratchbuf + 1, 1, cmp_type);
17097 oappend_maybe_intel (scratchbuf);
17098 scratchbuf[0] = '\0';
17103 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17104 int sizeflag ATTRIBUTE_UNUSED)
17106 unsigned int cmp_type;
17111 FETCH_DATA (the_info, codep + 1);
17112 cmp_type = *codep++ & 0xff;
17113 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17114 If it's the case, print suffix, otherwise - print the immediate. */
17115 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17120 char *p = mnemonicendp - 2;
17122 /* vpcmp* can have both one- and two-lettered suffix. */
17136 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17137 mnemonicendp += simd_cmp_op[cmp_type].len;
17141 /* We have a reserved extension byte. Output it directly. */
17142 scratchbuf[0] = '$';
17143 print_operand_value (scratchbuf + 1, 1, cmp_type);
17144 oappend_maybe_intel (scratchbuf);
17145 scratchbuf[0] = '\0';
17149 static const struct op pclmul_op[] =
17151 { STRING_COMMA_LEN ("lql") },
17152 { STRING_COMMA_LEN ("hql") },
17153 { STRING_COMMA_LEN ("lqh") },
17154 { STRING_COMMA_LEN ("hqh") }
17158 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17159 int sizeflag ATTRIBUTE_UNUSED)
17161 unsigned int pclmul_type;
17163 FETCH_DATA (the_info, codep + 1);
17164 pclmul_type = *codep++ & 0xff;
17165 switch (pclmul_type)
17176 if (pclmul_type < ARRAY_SIZE (pclmul_op))
17179 char *p = mnemonicendp - 3;
17184 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17185 mnemonicendp += pclmul_op[pclmul_type].len;
17189 /* We have a reserved extension byte. Output it directly. */
17190 scratchbuf[0] = '$';
17191 print_operand_value (scratchbuf + 1, 1, pclmul_type);
17192 oappend_maybe_intel (scratchbuf);
17193 scratchbuf[0] = '\0';
17198 MOVBE_Fixup (int bytemode, int sizeflag)
17200 /* Add proper suffix to "movbe". */
17201 char *p = mnemonicendp;
17210 if (sizeflag & SUFFIX_ALWAYS)
17216 if (sizeflag & DFLAG)
17220 used_prefixes |= (prefixes & PREFIX_DATA);
17225 oappend (INTERNAL_DISASSEMBLER_ERROR);
17232 OP_M (bytemode, sizeflag);
17236 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17239 const char **names;
17241 /* Skip mod/rm byte. */
17255 oappend (names[reg]);
17259 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17261 const char **names;
17268 oappend (names[vex.register_specifier]);
17272 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17275 || (bytemode != mask_mode && bytemode != mask_bd_mode))
17279 if ((rex & REX_R) != 0 || !vex.r)
17285 oappend (names_mask [modrm.reg]);
17289 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17292 || (bytemode != evex_rounding_mode
17293 && bytemode != evex_sae_mode))
17295 if (modrm.mod == 3 && vex.b)
17298 case evex_rounding_mode:
17299 oappend (names_rounding[vex.ll]);
17301 case evex_sae_mode: