1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2018 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma, disassemble_info *);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma get64 (void);
58 static bfd_signed_vma get32 (void);
59 static bfd_signed_vma get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VZERO_Fixup (int, int);
99 static void VCMP_Fixup (int, int);
100 static void VPCMP_Fixup (int, int);
101 static void VPCOM_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void OP_Mwaitx (int, int);
106 static void NOP_Fixup1 (int, int);
107 static void NOP_Fixup2 (int, int);
108 static void OP_3DNowSuffix (int, int);
109 static void CMP_Fixup (int, int);
110 static void BadOp (void);
111 static void REP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void NOTRACK_Fixup (int, int);
114 static void HLE_Fixup1 (int, int);
115 static void HLE_Fixup2 (int, int);
116 static void HLE_Fixup3 (int, int);
117 static void CMPXCHG8B_Fixup (int, int);
118 static void XMM_Fixup (int, int);
119 static void CRC32_Fixup (int, int);
120 static void FXSAVE_Fixup (int, int);
121 static void PCMPESTR_Fixup (int, int);
122 static void OP_LWPCB_E (int, int);
123 static void OP_LWP_E (int, int);
124 static void OP_Vex_2src_1 (int, int);
125 static void OP_Vex_2src_2 (int, int);
127 static void MOVBE_Fixup (int, int);
129 static void OP_Mask (int, int);
132 /* Points to first byte not fetched. */
133 bfd_byte *max_fetched;
134 bfd_byte the_buffer[MAX_MNEM_SIZE];
137 OPCODES_SIGJMP_BUF bailout;
147 enum address_mode address_mode;
149 /* Flags for the prefixes for the current instruction. See below. */
152 /* REX prefix the current instruction. See below. */
154 /* Bits of REX we've already used. */
156 /* REX bits in original REX prefix ignored. */
157 static int rex_ignored;
158 /* Mark parts used in the REX prefix. When we are testing for
159 empty prefix (for 8bit register REX extension), just mask it
160 out. Otherwise test for REX bit is excuse for existence of REX
161 only in case value is nonzero. */
162 #define USED_REX(value) \
167 rex_used |= (value) | REX_OPCODE; \
170 rex_used |= REX_OPCODE; \
173 /* Flags for prefixes which we somehow handled when printing the
174 current instruction. */
175 static int used_prefixes;
177 /* Flags stored in PREFIXES. */
178 #define PREFIX_REPZ 1
179 #define PREFIX_REPNZ 2
180 #define PREFIX_LOCK 4
182 #define PREFIX_SS 0x10
183 #define PREFIX_DS 0x20
184 #define PREFIX_ES 0x40
185 #define PREFIX_FS 0x80
186 #define PREFIX_GS 0x100
187 #define PREFIX_DATA 0x200
188 #define PREFIX_ADDR 0x400
189 #define PREFIX_FWAIT 0x800
191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
192 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
194 #define FETCH_DATA(info, addr) \
195 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
196 ? 1 : fetch_data ((info), (addr)))
199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
202 struct dis_private *priv = (struct dis_private *) info->private_data;
203 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
205 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
206 status = (*info->read_memory_func) (start,
208 addr - priv->max_fetched,
214 /* If we did manage to read at least one byte, then
215 print_insn_i386 will do something sensible. Otherwise, print
216 an error. We do that here because this is where we know
218 if (priv->max_fetched == priv->the_buffer)
219 (*info->memory_error_func) (status, start, info);
220 OPCODES_SIGLONGJMP (priv->bailout, 1);
223 priv->max_fetched = addr;
227 /* Possible values for prefix requirement. */
228 #define PREFIX_IGNORED_SHIFT 16
229 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
233 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
235 /* Opcode prefixes. */
236 #define PREFIX_OPCODE (PREFIX_REPZ \
240 /* Prefixes ignored. */
241 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
242 | PREFIX_IGNORED_REPNZ \
243 | PREFIX_IGNORED_DATA)
245 #define XX { NULL, 0 }
246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
248 #define Eb { OP_E, b_mode }
249 #define Ebnd { OP_E, bnd_mode }
250 #define EbS { OP_E, b_swap_mode }
251 #define EbndS { OP_E, bnd_swap_mode }
252 #define Ev { OP_E, v_mode }
253 #define Eva { OP_E, va_mode }
254 #define Ev_bnd { OP_E, v_bnd_mode }
255 #define EvS { OP_E, v_swap_mode }
256 #define Ed { OP_E, d_mode }
257 #define Edq { OP_E, dq_mode }
258 #define Edqw { OP_E, dqw_mode }
259 #define Edqb { OP_E, dqb_mode }
260 #define Edb { OP_E, db_mode }
261 #define Edw { OP_E, dw_mode }
262 #define Edqd { OP_E, dqd_mode }
263 #define Edqa { OP_E, dqa_mode }
264 #define Eq { OP_E, q_mode }
265 #define indirEv { OP_indirE, indir_v_mode }
266 #define indirEp { OP_indirE, f_mode }
267 #define stackEv { OP_E, stack_v_mode }
268 #define Em { OP_E, m_mode }
269 #define Ew { OP_E, w_mode }
270 #define M { OP_M, 0 } /* lea, lgdt, etc. */
271 #define Ma { OP_M, a_mode }
272 #define Mb { OP_M, b_mode }
273 #define Md { OP_M, d_mode }
274 #define Mo { OP_M, o_mode }
275 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
276 #define Mq { OP_M, q_mode }
277 #define Mv_bnd { OP_M, v_bndmk_mode }
278 #define Mx { OP_M, x_mode }
279 #define Mxmm { OP_M, xmm_mode }
280 #define Gb { OP_G, b_mode }
281 #define Gbnd { OP_G, bnd_mode }
282 #define Gv { OP_G, v_mode }
283 #define Gd { OP_G, d_mode }
284 #define Gdq { OP_G, dq_mode }
285 #define Gm { OP_G, m_mode }
286 #define Gva { OP_G, va_mode }
287 #define Gw { OP_G, w_mode }
288 #define Rd { OP_R, d_mode }
289 #define Rdq { OP_R, dq_mode }
290 #define Rm { OP_R, m_mode }
291 #define Ib { OP_I, b_mode }
292 #define sIb { OP_sI, b_mode } /* sign extened byte */
293 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
294 #define Iv { OP_I, v_mode }
295 #define sIv { OP_sI, v_mode }
296 #define Iq { OP_I, q_mode }
297 #define Iv64 { OP_I64, v_mode }
298 #define Iw { OP_I, w_mode }
299 #define I1 { OP_I, const_1_mode }
300 #define Jb { OP_J, b_mode }
301 #define Jv { OP_J, v_mode }
302 #define Cm { OP_C, m_mode }
303 #define Dm { OP_D, m_mode }
304 #define Td { OP_T, d_mode }
305 #define Skip_MODRM { OP_Skip_MODRM, 0 }
307 #define RMeAX { OP_REG, eAX_reg }
308 #define RMeBX { OP_REG, eBX_reg }
309 #define RMeCX { OP_REG, eCX_reg }
310 #define RMeDX { OP_REG, eDX_reg }
311 #define RMeSP { OP_REG, eSP_reg }
312 #define RMeBP { OP_REG, eBP_reg }
313 #define RMeSI { OP_REG, eSI_reg }
314 #define RMeDI { OP_REG, eDI_reg }
315 #define RMrAX { OP_REG, rAX_reg }
316 #define RMrBX { OP_REG, rBX_reg }
317 #define RMrCX { OP_REG, rCX_reg }
318 #define RMrDX { OP_REG, rDX_reg }
319 #define RMrSP { OP_REG, rSP_reg }
320 #define RMrBP { OP_REG, rBP_reg }
321 #define RMrSI { OP_REG, rSI_reg }
322 #define RMrDI { OP_REG, rDI_reg }
323 #define RMAL { OP_REG, al_reg }
324 #define RMCL { OP_REG, cl_reg }
325 #define RMDL { OP_REG, dl_reg }
326 #define RMBL { OP_REG, bl_reg }
327 #define RMAH { OP_REG, ah_reg }
328 #define RMCH { OP_REG, ch_reg }
329 #define RMDH { OP_REG, dh_reg }
330 #define RMBH { OP_REG, bh_reg }
331 #define RMAX { OP_REG, ax_reg }
332 #define RMDX { OP_REG, dx_reg }
334 #define eAX { OP_IMREG, eAX_reg }
335 #define eBX { OP_IMREG, eBX_reg }
336 #define eCX { OP_IMREG, eCX_reg }
337 #define eDX { OP_IMREG, eDX_reg }
338 #define eSP { OP_IMREG, eSP_reg }
339 #define eBP { OP_IMREG, eBP_reg }
340 #define eSI { OP_IMREG, eSI_reg }
341 #define eDI { OP_IMREG, eDI_reg }
342 #define AL { OP_IMREG, al_reg }
343 #define CL { OP_IMREG, cl_reg }
344 #define DL { OP_IMREG, dl_reg }
345 #define BL { OP_IMREG, bl_reg }
346 #define AH { OP_IMREG, ah_reg }
347 #define CH { OP_IMREG, ch_reg }
348 #define DH { OP_IMREG, dh_reg }
349 #define BH { OP_IMREG, bh_reg }
350 #define AX { OP_IMREG, ax_reg }
351 #define DX { OP_IMREG, dx_reg }
352 #define zAX { OP_IMREG, z_mode_ax_reg }
353 #define indirDX { OP_IMREG, indir_dx_reg }
355 #define Sw { OP_SEG, w_mode }
356 #define Sv { OP_SEG, v_mode }
357 #define Ap { OP_DIR, 0 }
358 #define Ob { OP_OFF64, b_mode }
359 #define Ov { OP_OFF64, v_mode }
360 #define Xb { OP_DSreg, eSI_reg }
361 #define Xv { OP_DSreg, eSI_reg }
362 #define Xz { OP_DSreg, eSI_reg }
363 #define Yb { OP_ESreg, eDI_reg }
364 #define Yv { OP_ESreg, eDI_reg }
365 #define DSBX { OP_DSreg, eBX_reg }
367 #define es { OP_REG, es_reg }
368 #define ss { OP_REG, ss_reg }
369 #define cs { OP_REG, cs_reg }
370 #define ds { OP_REG, ds_reg }
371 #define fs { OP_REG, fs_reg }
372 #define gs { OP_REG, gs_reg }
374 #define MX { OP_MMX, 0 }
375 #define XM { OP_XMM, 0 }
376 #define XMScalar { OP_XMM, scalar_mode }
377 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
378 #define XMM { OP_XMM, xmm_mode }
379 #define XMxmmq { OP_XMM, xmmq_mode }
380 #define EM { OP_EM, v_mode }
381 #define EMS { OP_EM, v_swap_mode }
382 #define EMd { OP_EM, d_mode }
383 #define EMx { OP_EM, x_mode }
384 #define EXbScalar { OP_EX, b_scalar_mode }
385 #define EXw { OP_EX, w_mode }
386 #define EXwScalar { OP_EX, w_scalar_mode }
387 #define EXd { OP_EX, d_mode }
388 #define EXdScalar { OP_EX, d_scalar_mode }
389 #define EXdS { OP_EX, d_swap_mode }
390 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
391 #define EXq { OP_EX, q_mode }
392 #define EXqScalar { OP_EX, q_scalar_mode }
393 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
394 #define EXqS { OP_EX, q_swap_mode }
395 #define EXx { OP_EX, x_mode }
396 #define EXxS { OP_EX, x_swap_mode }
397 #define EXxmm { OP_EX, xmm_mode }
398 #define EXymm { OP_EX, ymm_mode }
399 #define EXxmmq { OP_EX, xmmq_mode }
400 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
401 #define EXxmm_mb { OP_EX, xmm_mb_mode }
402 #define EXxmm_mw { OP_EX, xmm_mw_mode }
403 #define EXxmm_md { OP_EX, xmm_md_mode }
404 #define EXxmm_mq { OP_EX, xmm_mq_mode }
405 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
406 #define EXxmmdw { OP_EX, xmmdw_mode }
407 #define EXxmmqd { OP_EX, xmmqd_mode }
408 #define EXymmq { OP_EX, ymmq_mode }
409 #define EXVexWdq { OP_EX, vex_w_dq_mode }
410 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
411 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
412 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
413 #define MS { OP_MS, v_mode }
414 #define XS { OP_XS, v_mode }
415 #define EMCq { OP_EMC, q_mode }
416 #define MXC { OP_MXC, 0 }
417 #define OPSUF { OP_3DNowSuffix, 0 }
418 #define CMP { CMP_Fixup, 0 }
419 #define XMM0 { XMM_Fixup, 0 }
420 #define FXSAVE { FXSAVE_Fixup, 0 }
421 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
422 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
424 #define Vex { OP_VEX, vex_mode }
425 #define VexScalar { OP_VEX, vex_scalar_mode }
426 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
427 #define Vex128 { OP_VEX, vex128_mode }
428 #define Vex256 { OP_VEX, vex256_mode }
429 #define VexGdq { OP_VEX, dq_mode }
430 #define EXdVex { OP_EX_Vex, d_mode }
431 #define EXdVexS { OP_EX_Vex, d_swap_mode }
432 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
433 #define EXqVex { OP_EX_Vex, q_mode }
434 #define EXqVexS { OP_EX_Vex, q_swap_mode }
435 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
436 #define EXVexW { OP_EX_VexW, x_mode }
437 #define EXdVexW { OP_EX_VexW, d_mode }
438 #define EXqVexW { OP_EX_VexW, q_mode }
439 #define EXVexImmW { OP_EX_VexImmW, x_mode }
440 #define XMVex { OP_XMM_Vex, 0 }
441 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
442 #define XMVexW { OP_XMM_VexW, 0 }
443 #define XMVexI4 { OP_REG_VexI4, x_mode }
444 #define PCLMUL { PCLMUL_Fixup, 0 }
445 #define VZERO { VZERO_Fixup, 0 }
446 #define VCMP { VCMP_Fixup, 0 }
447 #define VPCMP { VPCMP_Fixup, 0 }
448 #define VPCOM { VPCOM_Fixup, 0 }
450 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
451 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
452 #define EXxEVexS { OP_Rounding, evex_sae_mode }
454 #define XMask { OP_Mask, mask_mode }
455 #define MaskG { OP_G, mask_mode }
456 #define MaskE { OP_E, mask_mode }
457 #define MaskBDE { OP_E, mask_bd_mode }
458 #define MaskR { OP_R, mask_mode }
459 #define MaskVex { OP_VEX, mask_mode }
461 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
462 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
463 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
464 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
466 /* Used handle "rep" prefix for string instructions. */
467 #define Xbr { REP_Fixup, eSI_reg }
468 #define Xvr { REP_Fixup, eSI_reg }
469 #define Ybr { REP_Fixup, eDI_reg }
470 #define Yvr { REP_Fixup, eDI_reg }
471 #define Yzr { REP_Fixup, eDI_reg }
472 #define indirDXr { REP_Fixup, indir_dx_reg }
473 #define ALr { REP_Fixup, al_reg }
474 #define eAXr { REP_Fixup, eAX_reg }
476 /* Used handle HLE prefix for lockable instructions. */
477 #define Ebh1 { HLE_Fixup1, b_mode }
478 #define Evh1 { HLE_Fixup1, v_mode }
479 #define Ebh2 { HLE_Fixup2, b_mode }
480 #define Evh2 { HLE_Fixup2, v_mode }
481 #define Ebh3 { HLE_Fixup3, b_mode }
482 #define Evh3 { HLE_Fixup3, v_mode }
484 #define BND { BND_Fixup, 0 }
485 #define NOTRACK { NOTRACK_Fixup, 0 }
487 #define cond_jump_flag { NULL, cond_jump_mode }
488 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
490 /* bits in sizeflag */
491 #define SUFFIX_ALWAYS 4
499 /* byte operand with operand swapped */
501 /* byte operand, sign extend like 'T' suffix */
503 /* operand size depends on prefixes */
505 /* operand size depends on prefixes with operand swapped */
507 /* operand size depends on address prefix */
511 /* double word operand */
513 /* double word operand with operand swapped */
515 /* quad word operand */
517 /* quad word operand with operand swapped */
519 /* ten-byte operand */
521 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
522 broadcast enabled. */
524 /* Similar to x_mode, but with different EVEX mem shifts. */
526 /* Similar to x_mode, but with disabled broadcast. */
528 /* Similar to x_mode, but with operands swapped and disabled broadcast
531 /* 16-byte XMM operand */
533 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
534 memory operand (depending on vector length). Broadcast isn't
537 /* Same as xmmq_mode, but broadcast is allowed. */
538 evex_half_bcst_xmmq_mode,
539 /* XMM register or byte memory operand */
541 /* XMM register or word memory operand */
543 /* XMM register or double word memory operand */
545 /* XMM register or quad word memory operand */
547 /* XMM register or double/quad word memory operand, depending on
550 /* 16-byte XMM, word, double word or quad word operand. */
552 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
554 /* 32-byte YMM operand */
556 /* quad word, ymmword or zmmword memory operand. */
558 /* 32-byte YMM or 16-byte word operand */
560 /* d_mode in 32bit, q_mode in 64bit mode. */
562 /* pair of v_mode operands */
567 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
569 /* operand size depends on REX prefixes. */
571 /* registers like dq_mode, memory like w_mode. */
575 /* bounds operand with operand swapped */
577 /* 4- or 6-byte pointer operand */
580 /* v_mode for indirect branch opcodes. */
582 /* v_mode for stack-related opcodes. */
584 /* non-quad operand size depends on prefixes */
586 /* 16-byte operand */
588 /* registers like dq_mode, memory like b_mode. */
590 /* registers like d_mode, memory like b_mode. */
592 /* registers like d_mode, memory like w_mode. */
594 /* registers like dq_mode, memory like d_mode. */
596 /* operand size depends on the W bit as well as address mode. */
598 /* normal vex mode */
600 /* 128bit vex mode */
602 /* 256bit vex mode */
604 /* operand size depends on the VEX.W bit. */
607 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
608 vex_vsib_d_w_dq_mode,
609 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
611 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
612 vex_vsib_q_w_dq_mode,
613 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
616 /* scalar, ignore vector length. */
618 /* like b_mode, ignore vector length. */
620 /* like w_mode, ignore vector length. */
622 /* like d_mode, ignore vector length. */
624 /* like d_swap_mode, ignore vector length. */
626 /* like q_mode, ignore vector length. */
628 /* like q_swap_mode, ignore vector length. */
630 /* like vex_mode, ignore vector length. */
632 /* like vex_w_dq_mode, ignore vector length. */
633 vex_scalar_w_dq_mode,
635 /* Static rounding. */
637 /* Static rounding, 64-bit mode only. */
638 evex_rounding_64_mode,
639 /* Supress all exceptions. */
642 /* Mask register operand. */
644 /* Mask register operand. */
711 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
713 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
714 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
715 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
716 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
717 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
718 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
719 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
720 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
721 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
722 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
723 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
724 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
725 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
726 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
727 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
853 MOD_VEX_0F12_PREFIX_0,
855 MOD_VEX_0F16_PREFIX_0,
858 MOD_VEX_W_0_0F41_P_0_LEN_1,
859 MOD_VEX_W_1_0F41_P_0_LEN_1,
860 MOD_VEX_W_0_0F41_P_2_LEN_1,
861 MOD_VEX_W_1_0F41_P_2_LEN_1,
862 MOD_VEX_W_0_0F42_P_0_LEN_1,
863 MOD_VEX_W_1_0F42_P_0_LEN_1,
864 MOD_VEX_W_0_0F42_P_2_LEN_1,
865 MOD_VEX_W_1_0F42_P_2_LEN_1,
866 MOD_VEX_W_0_0F44_P_0_LEN_1,
867 MOD_VEX_W_1_0F44_P_0_LEN_1,
868 MOD_VEX_W_0_0F44_P_2_LEN_1,
869 MOD_VEX_W_1_0F44_P_2_LEN_1,
870 MOD_VEX_W_0_0F45_P_0_LEN_1,
871 MOD_VEX_W_1_0F45_P_0_LEN_1,
872 MOD_VEX_W_0_0F45_P_2_LEN_1,
873 MOD_VEX_W_1_0F45_P_2_LEN_1,
874 MOD_VEX_W_0_0F46_P_0_LEN_1,
875 MOD_VEX_W_1_0F46_P_0_LEN_1,
876 MOD_VEX_W_0_0F46_P_2_LEN_1,
877 MOD_VEX_W_1_0F46_P_2_LEN_1,
878 MOD_VEX_W_0_0F47_P_0_LEN_1,
879 MOD_VEX_W_1_0F47_P_0_LEN_1,
880 MOD_VEX_W_0_0F47_P_2_LEN_1,
881 MOD_VEX_W_1_0F47_P_2_LEN_1,
882 MOD_VEX_W_0_0F4A_P_0_LEN_1,
883 MOD_VEX_W_1_0F4A_P_0_LEN_1,
884 MOD_VEX_W_0_0F4A_P_2_LEN_1,
885 MOD_VEX_W_1_0F4A_P_2_LEN_1,
886 MOD_VEX_W_0_0F4B_P_0_LEN_1,
887 MOD_VEX_W_1_0F4B_P_0_LEN_1,
888 MOD_VEX_W_0_0F4B_P_2_LEN_1,
900 MOD_VEX_W_0_0F91_P_0_LEN_0,
901 MOD_VEX_W_1_0F91_P_0_LEN_0,
902 MOD_VEX_W_0_0F91_P_2_LEN_0,
903 MOD_VEX_W_1_0F91_P_2_LEN_0,
904 MOD_VEX_W_0_0F92_P_0_LEN_0,
905 MOD_VEX_W_0_0F92_P_2_LEN_0,
906 MOD_VEX_W_0_0F92_P_3_LEN_0,
907 MOD_VEX_W_1_0F92_P_3_LEN_0,
908 MOD_VEX_W_0_0F93_P_0_LEN_0,
909 MOD_VEX_W_0_0F93_P_2_LEN_0,
910 MOD_VEX_W_0_0F93_P_3_LEN_0,
911 MOD_VEX_W_1_0F93_P_3_LEN_0,
912 MOD_VEX_W_0_0F98_P_0_LEN_0,
913 MOD_VEX_W_1_0F98_P_0_LEN_0,
914 MOD_VEX_W_0_0F98_P_2_LEN_0,
915 MOD_VEX_W_1_0F98_P_2_LEN_0,
916 MOD_VEX_W_0_0F99_P_0_LEN_0,
917 MOD_VEX_W_1_0F99_P_0_LEN_0,
918 MOD_VEX_W_0_0F99_P_2_LEN_0,
919 MOD_VEX_W_1_0F99_P_2_LEN_0,
922 MOD_VEX_0FD7_PREFIX_2,
923 MOD_VEX_0FE7_PREFIX_2,
924 MOD_VEX_0FF0_PREFIX_3,
925 MOD_VEX_0F381A_PREFIX_2,
926 MOD_VEX_0F382A_PREFIX_2,
927 MOD_VEX_0F382C_PREFIX_2,
928 MOD_VEX_0F382D_PREFIX_2,
929 MOD_VEX_0F382E_PREFIX_2,
930 MOD_VEX_0F382F_PREFIX_2,
931 MOD_VEX_0F385A_PREFIX_2,
932 MOD_VEX_0F388C_PREFIX_2,
933 MOD_VEX_0F388E_PREFIX_2,
934 MOD_VEX_W_0_0F3A30_P_2_LEN_0,
935 MOD_VEX_W_1_0F3A30_P_2_LEN_0,
936 MOD_VEX_W_0_0F3A31_P_2_LEN_0,
937 MOD_VEX_W_1_0F3A31_P_2_LEN_0,
938 MOD_VEX_W_0_0F3A32_P_2_LEN_0,
939 MOD_VEX_W_1_0F3A32_P_2_LEN_0,
940 MOD_VEX_W_0_0F3A33_P_2_LEN_0,
941 MOD_VEX_W_1_0F3A33_P_2_LEN_0,
943 MOD_EVEX_0F10_PREFIX_1,
944 MOD_EVEX_0F10_PREFIX_3,
945 MOD_EVEX_0F11_PREFIX_1,
946 MOD_EVEX_0F11_PREFIX_3,
947 MOD_EVEX_0F12_PREFIX_0,
948 MOD_EVEX_0F16_PREFIX_0,
949 MOD_EVEX_0F38C6_REG_1,
950 MOD_EVEX_0F38C6_REG_2,
951 MOD_EVEX_0F38C6_REG_5,
952 MOD_EVEX_0F38C6_REG_6,
953 MOD_EVEX_0F38C7_REG_1,
954 MOD_EVEX_0F38C7_REG_2,
955 MOD_EVEX_0F38C7_REG_5,
956 MOD_EVEX_0F38C7_REG_6
977 PREFIX_MOD_0_0F01_REG_5,
978 PREFIX_MOD_3_0F01_REG_5_RM_0,
979 PREFIX_MOD_3_0F01_REG_5_RM_2,
1025 PREFIX_MOD_0_0FAE_REG_4,
1026 PREFIX_MOD_3_0FAE_REG_4,
1027 PREFIX_MOD_0_0FAE_REG_5,
1028 PREFIX_MOD_3_0FAE_REG_5,
1029 PREFIX_MOD_0_0FAE_REG_6,
1030 PREFIX_MOD_1_0FAE_REG_6,
1037 PREFIX_MOD_0_0FC7_REG_6,
1038 PREFIX_MOD_3_0FC7_REG_6,
1039 PREFIX_MOD_3_0FC7_REG_7,
1169 PREFIX_VEX_0F71_REG_2,
1170 PREFIX_VEX_0F71_REG_4,
1171 PREFIX_VEX_0F71_REG_6,
1172 PREFIX_VEX_0F72_REG_2,
1173 PREFIX_VEX_0F72_REG_4,
1174 PREFIX_VEX_0F72_REG_6,
1175 PREFIX_VEX_0F73_REG_2,
1176 PREFIX_VEX_0F73_REG_3,
1177 PREFIX_VEX_0F73_REG_6,
1178 PREFIX_VEX_0F73_REG_7,
1351 PREFIX_VEX_0F38F3_REG_1,
1352 PREFIX_VEX_0F38F3_REG_2,
1353 PREFIX_VEX_0F38F3_REG_3,
1472 PREFIX_EVEX_0F71_REG_2,
1473 PREFIX_EVEX_0F71_REG_4,
1474 PREFIX_EVEX_0F71_REG_6,
1475 PREFIX_EVEX_0F72_REG_0,
1476 PREFIX_EVEX_0F72_REG_1,
1477 PREFIX_EVEX_0F72_REG_2,
1478 PREFIX_EVEX_0F72_REG_4,
1479 PREFIX_EVEX_0F72_REG_6,
1480 PREFIX_EVEX_0F73_REG_2,
1481 PREFIX_EVEX_0F73_REG_3,
1482 PREFIX_EVEX_0F73_REG_6,
1483 PREFIX_EVEX_0F73_REG_7,
1679 PREFIX_EVEX_0F38C6_REG_1,
1680 PREFIX_EVEX_0F38C6_REG_2,
1681 PREFIX_EVEX_0F38C6_REG_5,
1682 PREFIX_EVEX_0F38C6_REG_6,
1683 PREFIX_EVEX_0F38C7_REG_1,
1684 PREFIX_EVEX_0F38C7_REG_2,
1685 PREFIX_EVEX_0F38C7_REG_5,
1686 PREFIX_EVEX_0F38C7_REG_6,
1788 THREE_BYTE_0F38 = 0,
1815 VEX_LEN_0F10_P_1 = 0,
1819 VEX_LEN_0F12_P_0_M_0,
1820 VEX_LEN_0F12_P_0_M_1,
1823 VEX_LEN_0F16_P_0_M_0,
1824 VEX_LEN_0F16_P_0_M_1,
1888 VEX_LEN_0FAE_R_2_M_0,
1889 VEX_LEN_0FAE_R_3_M_0,
1898 VEX_LEN_0F381A_P_2_M_0,
1901 VEX_LEN_0F385A_P_2_M_0,
1904 VEX_LEN_0F38F3_R_1_P_0,
1905 VEX_LEN_0F38F3_R_2_P_0,
1906 VEX_LEN_0F38F3_R_3_P_0,
1951 VEX_LEN_0FXOP_08_CC,
1952 VEX_LEN_0FXOP_08_CD,
1953 VEX_LEN_0FXOP_08_CE,
1954 VEX_LEN_0FXOP_08_CF,
1955 VEX_LEN_0FXOP_08_EC,
1956 VEX_LEN_0FXOP_08_ED,
1957 VEX_LEN_0FXOP_08_EE,
1958 VEX_LEN_0FXOP_08_EF,
1959 VEX_LEN_0FXOP_09_80,
1993 VEX_W_0F41_P_0_LEN_1,
1994 VEX_W_0F41_P_2_LEN_1,
1995 VEX_W_0F42_P_0_LEN_1,
1996 VEX_W_0F42_P_2_LEN_1,
1997 VEX_W_0F44_P_0_LEN_0,
1998 VEX_W_0F44_P_2_LEN_0,
1999 VEX_W_0F45_P_0_LEN_1,
2000 VEX_W_0F45_P_2_LEN_1,
2001 VEX_W_0F46_P_0_LEN_1,
2002 VEX_W_0F46_P_2_LEN_1,
2003 VEX_W_0F47_P_0_LEN_1,
2004 VEX_W_0F47_P_2_LEN_1,
2005 VEX_W_0F4A_P_0_LEN_1,
2006 VEX_W_0F4A_P_2_LEN_1,
2007 VEX_W_0F4B_P_0_LEN_1,
2008 VEX_W_0F4B_P_2_LEN_1,
2088 VEX_W_0F90_P_0_LEN_0,
2089 VEX_W_0F90_P_2_LEN_0,
2090 VEX_W_0F91_P_0_LEN_0,
2091 VEX_W_0F91_P_2_LEN_0,
2092 VEX_W_0F92_P_0_LEN_0,
2093 VEX_W_0F92_P_2_LEN_0,
2094 VEX_W_0F92_P_3_LEN_0,
2095 VEX_W_0F93_P_0_LEN_0,
2096 VEX_W_0F93_P_2_LEN_0,
2097 VEX_W_0F93_P_3_LEN_0,
2098 VEX_W_0F98_P_0_LEN_0,
2099 VEX_W_0F98_P_2_LEN_0,
2100 VEX_W_0F99_P_0_LEN_0,
2101 VEX_W_0F99_P_2_LEN_0,
2180 VEX_W_0F381A_P_2_M_0,
2192 VEX_W_0F382A_P_2_M_0,
2194 VEX_W_0F382C_P_2_M_0,
2195 VEX_W_0F382D_P_2_M_0,
2196 VEX_W_0F382E_P_2_M_0,
2197 VEX_W_0F382F_P_2_M_0,
2219 VEX_W_0F385A_P_2_M_0,
2244 VEX_W_0F3A30_P_2_LEN_0,
2245 VEX_W_0F3A31_P_2_LEN_0,
2246 VEX_W_0F3A32_P_2_LEN_0,
2247 VEX_W_0F3A33_P_2_LEN_0,
2266 EVEX_W_0F10_P_1_M_0,
2267 EVEX_W_0F10_P_1_M_1,
2269 EVEX_W_0F10_P_3_M_0,
2270 EVEX_W_0F10_P_3_M_1,
2272 EVEX_W_0F11_P_1_M_0,
2273 EVEX_W_0F11_P_1_M_1,
2275 EVEX_W_0F11_P_3_M_0,
2276 EVEX_W_0F11_P_3_M_1,
2277 EVEX_W_0F12_P_0_M_0,
2278 EVEX_W_0F12_P_0_M_1,
2288 EVEX_W_0F16_P_0_M_0,
2289 EVEX_W_0F16_P_0_M_1,
2360 EVEX_W_0F72_R_2_P_2,
2361 EVEX_W_0F72_R_6_P_2,
2362 EVEX_W_0F73_R_2_P_2,
2363 EVEX_W_0F73_R_6_P_2,
2471 EVEX_W_0F38C7_R_1_P_2,
2472 EVEX_W_0F38C7_R_2_P_2,
2473 EVEX_W_0F38C7_R_5_P_2,
2474 EVEX_W_0F38C7_R_6_P_2,
2515 typedef void (*op_rtn) (int bytemode, int sizeflag);
2524 unsigned int prefix_requirement;
2527 /* Upper case letters in the instruction names here are macros.
2528 'A' => print 'b' if no register operands or suffix_always is true
2529 'B' => print 'b' if suffix_always is true
2530 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2532 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2533 suffix_always is true
2534 'E' => print 'e' if 32-bit form of jcxz
2535 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2536 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2537 'H' => print ",pt" or ",pn" branch hint
2538 'I' => honor following macro letter even in Intel mode (implemented only
2539 for some of the macro letters)
2541 'K' => print 'd' or 'q' if rex prefix is present.
2542 'L' => print 'l' if suffix_always is true
2543 'M' => print 'r' if intel_mnemonic is false.
2544 'N' => print 'n' if instruction has no wait "prefix"
2545 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2546 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2547 or suffix_always is true. print 'q' if rex prefix is present.
2548 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2550 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2551 'S' => print 'w', 'l' or 'q' if suffix_always is true
2552 'T' => print 'q' in 64bit mode if instruction has no operand size
2553 prefix and behave as 'P' otherwise
2554 'U' => print 'q' in 64bit mode if instruction has no operand size
2555 prefix and behave as 'Q' otherwise
2556 'V' => print 'q' in 64bit mode if instruction has no operand size
2557 prefix and behave as 'S' otherwise
2558 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2559 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2561 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2562 '!' => change condition from true to false or from false to true.
2563 '%' => add 1 upper case letter to the macro.
2564 '^' => print 'w' or 'l' depending on operand size prefix or
2565 suffix_always is true (lcall/ljmp).
2566 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2567 on operand size prefix.
2568 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2569 has no operand size prefix for AMD64 ISA, behave as 'P'
2572 2 upper case letter macros:
2573 "XY" => print 'x' or 'y' if suffix_always is true or no register
2574 operands and no broadcast.
2575 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2576 register operands and no broadcast.
2577 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2578 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2579 or suffix_always is true
2580 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2581 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2582 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2583 "LW" => print 'd', 'q' depending on the VEX.W bit
2584 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2585 an operand size prefix, or suffix_always is true. print
2586 'q' if rex prefix is present.
2588 Many of the above letters print nothing in Intel mode. See "putop"
2591 Braces '{' and '}', and vertical bars '|', indicate alternative
2592 mnemonic strings for AT&T and Intel. */
2594 static const struct dis386 dis386[] = {
2596 { "addB", { Ebh1, Gb }, 0 },
2597 { "addS", { Evh1, Gv }, 0 },
2598 { "addB", { Gb, EbS }, 0 },
2599 { "addS", { Gv, EvS }, 0 },
2600 { "addB", { AL, Ib }, 0 },
2601 { "addS", { eAX, Iv }, 0 },
2602 { X86_64_TABLE (X86_64_06) },
2603 { X86_64_TABLE (X86_64_07) },
2605 { "orB", { Ebh1, Gb }, 0 },
2606 { "orS", { Evh1, Gv }, 0 },
2607 { "orB", { Gb, EbS }, 0 },
2608 { "orS", { Gv, EvS }, 0 },
2609 { "orB", { AL, Ib }, 0 },
2610 { "orS", { eAX, Iv }, 0 },
2611 { X86_64_TABLE (X86_64_0D) },
2612 { Bad_Opcode }, /* 0x0f extended opcode escape */
2614 { "adcB", { Ebh1, Gb }, 0 },
2615 { "adcS", { Evh1, Gv }, 0 },
2616 { "adcB", { Gb, EbS }, 0 },
2617 { "adcS", { Gv, EvS }, 0 },
2618 { "adcB", { AL, Ib }, 0 },
2619 { "adcS", { eAX, Iv }, 0 },
2620 { X86_64_TABLE (X86_64_16) },
2621 { X86_64_TABLE (X86_64_17) },
2623 { "sbbB", { Ebh1, Gb }, 0 },
2624 { "sbbS", { Evh1, Gv }, 0 },
2625 { "sbbB", { Gb, EbS }, 0 },
2626 { "sbbS", { Gv, EvS }, 0 },
2627 { "sbbB", { AL, Ib }, 0 },
2628 { "sbbS", { eAX, Iv }, 0 },
2629 { X86_64_TABLE (X86_64_1E) },
2630 { X86_64_TABLE (X86_64_1F) },
2632 { "andB", { Ebh1, Gb }, 0 },
2633 { "andS", { Evh1, Gv }, 0 },
2634 { "andB", { Gb, EbS }, 0 },
2635 { "andS", { Gv, EvS }, 0 },
2636 { "andB", { AL, Ib }, 0 },
2637 { "andS", { eAX, Iv }, 0 },
2638 { Bad_Opcode }, /* SEG ES prefix */
2639 { X86_64_TABLE (X86_64_27) },
2641 { "subB", { Ebh1, Gb }, 0 },
2642 { "subS", { Evh1, Gv }, 0 },
2643 { "subB", { Gb, EbS }, 0 },
2644 { "subS", { Gv, EvS }, 0 },
2645 { "subB", { AL, Ib }, 0 },
2646 { "subS", { eAX, Iv }, 0 },
2647 { Bad_Opcode }, /* SEG CS prefix */
2648 { X86_64_TABLE (X86_64_2F) },
2650 { "xorB", { Ebh1, Gb }, 0 },
2651 { "xorS", { Evh1, Gv }, 0 },
2652 { "xorB", { Gb, EbS }, 0 },
2653 { "xorS", { Gv, EvS }, 0 },
2654 { "xorB", { AL, Ib }, 0 },
2655 { "xorS", { eAX, Iv }, 0 },
2656 { Bad_Opcode }, /* SEG SS prefix */
2657 { X86_64_TABLE (X86_64_37) },
2659 { "cmpB", { Eb, Gb }, 0 },
2660 { "cmpS", { Ev, Gv }, 0 },
2661 { "cmpB", { Gb, EbS }, 0 },
2662 { "cmpS", { Gv, EvS }, 0 },
2663 { "cmpB", { AL, Ib }, 0 },
2664 { "cmpS", { eAX, Iv }, 0 },
2665 { Bad_Opcode }, /* SEG DS prefix */
2666 { X86_64_TABLE (X86_64_3F) },
2668 { "inc{S|}", { RMeAX }, 0 },
2669 { "inc{S|}", { RMeCX }, 0 },
2670 { "inc{S|}", { RMeDX }, 0 },
2671 { "inc{S|}", { RMeBX }, 0 },
2672 { "inc{S|}", { RMeSP }, 0 },
2673 { "inc{S|}", { RMeBP }, 0 },
2674 { "inc{S|}", { RMeSI }, 0 },
2675 { "inc{S|}", { RMeDI }, 0 },
2677 { "dec{S|}", { RMeAX }, 0 },
2678 { "dec{S|}", { RMeCX }, 0 },
2679 { "dec{S|}", { RMeDX }, 0 },
2680 { "dec{S|}", { RMeBX }, 0 },
2681 { "dec{S|}", { RMeSP }, 0 },
2682 { "dec{S|}", { RMeBP }, 0 },
2683 { "dec{S|}", { RMeSI }, 0 },
2684 { "dec{S|}", { RMeDI }, 0 },
2686 { "pushV", { RMrAX }, 0 },
2687 { "pushV", { RMrCX }, 0 },
2688 { "pushV", { RMrDX }, 0 },
2689 { "pushV", { RMrBX }, 0 },
2690 { "pushV", { RMrSP }, 0 },
2691 { "pushV", { RMrBP }, 0 },
2692 { "pushV", { RMrSI }, 0 },
2693 { "pushV", { RMrDI }, 0 },
2695 { "popV", { RMrAX }, 0 },
2696 { "popV", { RMrCX }, 0 },
2697 { "popV", { RMrDX }, 0 },
2698 { "popV", { RMrBX }, 0 },
2699 { "popV", { RMrSP }, 0 },
2700 { "popV", { RMrBP }, 0 },
2701 { "popV", { RMrSI }, 0 },
2702 { "popV", { RMrDI }, 0 },
2704 { X86_64_TABLE (X86_64_60) },
2705 { X86_64_TABLE (X86_64_61) },
2706 { X86_64_TABLE (X86_64_62) },
2707 { X86_64_TABLE (X86_64_63) },
2708 { Bad_Opcode }, /* seg fs */
2709 { Bad_Opcode }, /* seg gs */
2710 { Bad_Opcode }, /* op size prefix */
2711 { Bad_Opcode }, /* adr size prefix */
2713 { "pushT", { sIv }, 0 },
2714 { "imulS", { Gv, Ev, Iv }, 0 },
2715 { "pushT", { sIbT }, 0 },
2716 { "imulS", { Gv, Ev, sIb }, 0 },
2717 { "ins{b|}", { Ybr, indirDX }, 0 },
2718 { X86_64_TABLE (X86_64_6D) },
2719 { "outs{b|}", { indirDXr, Xb }, 0 },
2720 { X86_64_TABLE (X86_64_6F) },
2722 { "joH", { Jb, BND, cond_jump_flag }, 0 },
2723 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
2724 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
2725 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
2726 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
2727 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
2728 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
2729 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
2731 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
2732 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
2733 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
2734 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
2735 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
2736 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
2737 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
2738 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
2740 { REG_TABLE (REG_80) },
2741 { REG_TABLE (REG_81) },
2742 { X86_64_TABLE (X86_64_82) },
2743 { REG_TABLE (REG_83) },
2744 { "testB", { Eb, Gb }, 0 },
2745 { "testS", { Ev, Gv }, 0 },
2746 { "xchgB", { Ebh2, Gb }, 0 },
2747 { "xchgS", { Evh2, Gv }, 0 },
2749 { "movB", { Ebh3, Gb }, 0 },
2750 { "movS", { Evh3, Gv }, 0 },
2751 { "movB", { Gb, EbS }, 0 },
2752 { "movS", { Gv, EvS }, 0 },
2753 { "movD", { Sv, Sw }, 0 },
2754 { MOD_TABLE (MOD_8D) },
2755 { "movD", { Sw, Sv }, 0 },
2756 { REG_TABLE (REG_8F) },
2758 { PREFIX_TABLE (PREFIX_90) },
2759 { "xchgS", { RMeCX, eAX }, 0 },
2760 { "xchgS", { RMeDX, eAX }, 0 },
2761 { "xchgS", { RMeBX, eAX }, 0 },
2762 { "xchgS", { RMeSP, eAX }, 0 },
2763 { "xchgS", { RMeBP, eAX }, 0 },
2764 { "xchgS", { RMeSI, eAX }, 0 },
2765 { "xchgS", { RMeDI, eAX }, 0 },
2767 { "cW{t|}R", { XX }, 0 },
2768 { "cR{t|}O", { XX }, 0 },
2769 { X86_64_TABLE (X86_64_9A) },
2770 { Bad_Opcode }, /* fwait */
2771 { "pushfT", { XX }, 0 },
2772 { "popfT", { XX }, 0 },
2773 { "sahf", { XX }, 0 },
2774 { "lahf", { XX }, 0 },
2776 { "mov%LB", { AL, Ob }, 0 },
2777 { "mov%LS", { eAX, Ov }, 0 },
2778 { "mov%LB", { Ob, AL }, 0 },
2779 { "mov%LS", { Ov, eAX }, 0 },
2780 { "movs{b|}", { Ybr, Xb }, 0 },
2781 { "movs{R|}", { Yvr, Xv }, 0 },
2782 { "cmps{b|}", { Xb, Yb }, 0 },
2783 { "cmps{R|}", { Xv, Yv }, 0 },
2785 { "testB", { AL, Ib }, 0 },
2786 { "testS", { eAX, Iv }, 0 },
2787 { "stosB", { Ybr, AL }, 0 },
2788 { "stosS", { Yvr, eAX }, 0 },
2789 { "lodsB", { ALr, Xb }, 0 },
2790 { "lodsS", { eAXr, Xv }, 0 },
2791 { "scasB", { AL, Yb }, 0 },
2792 { "scasS", { eAX, Yv }, 0 },
2794 { "movB", { RMAL, Ib }, 0 },
2795 { "movB", { RMCL, Ib }, 0 },
2796 { "movB", { RMDL, Ib }, 0 },
2797 { "movB", { RMBL, Ib }, 0 },
2798 { "movB", { RMAH, Ib }, 0 },
2799 { "movB", { RMCH, Ib }, 0 },
2800 { "movB", { RMDH, Ib }, 0 },
2801 { "movB", { RMBH, Ib }, 0 },
2803 { "mov%LV", { RMeAX, Iv64 }, 0 },
2804 { "mov%LV", { RMeCX, Iv64 }, 0 },
2805 { "mov%LV", { RMeDX, Iv64 }, 0 },
2806 { "mov%LV", { RMeBX, Iv64 }, 0 },
2807 { "mov%LV", { RMeSP, Iv64 }, 0 },
2808 { "mov%LV", { RMeBP, Iv64 }, 0 },
2809 { "mov%LV", { RMeSI, Iv64 }, 0 },
2810 { "mov%LV", { RMeDI, Iv64 }, 0 },
2812 { REG_TABLE (REG_C0) },
2813 { REG_TABLE (REG_C1) },
2814 { "retT", { Iw, BND }, 0 },
2815 { "retT", { BND }, 0 },
2816 { X86_64_TABLE (X86_64_C4) },
2817 { X86_64_TABLE (X86_64_C5) },
2818 { REG_TABLE (REG_C6) },
2819 { REG_TABLE (REG_C7) },
2821 { "enterT", { Iw, Ib }, 0 },
2822 { "leaveT", { XX }, 0 },
2823 { "Jret{|f}P", { Iw }, 0 },
2824 { "Jret{|f}P", { XX }, 0 },
2825 { "int3", { XX }, 0 },
2826 { "int", { Ib }, 0 },
2827 { X86_64_TABLE (X86_64_CE) },
2828 { "iret%LP", { XX }, 0 },
2830 { REG_TABLE (REG_D0) },
2831 { REG_TABLE (REG_D1) },
2832 { REG_TABLE (REG_D2) },
2833 { REG_TABLE (REG_D3) },
2834 { X86_64_TABLE (X86_64_D4) },
2835 { X86_64_TABLE (X86_64_D5) },
2837 { "xlat", { DSBX }, 0 },
2848 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2849 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2850 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2851 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2852 { "inB", { AL, Ib }, 0 },
2853 { "inG", { zAX, Ib }, 0 },
2854 { "outB", { Ib, AL }, 0 },
2855 { "outG", { Ib, zAX }, 0 },
2857 { X86_64_TABLE (X86_64_E8) },
2858 { X86_64_TABLE (X86_64_E9) },
2859 { X86_64_TABLE (X86_64_EA) },
2860 { "jmp", { Jb, BND }, 0 },
2861 { "inB", { AL, indirDX }, 0 },
2862 { "inG", { zAX, indirDX }, 0 },
2863 { "outB", { indirDX, AL }, 0 },
2864 { "outG", { indirDX, zAX }, 0 },
2866 { Bad_Opcode }, /* lock prefix */
2867 { "icebp", { XX }, 0 },
2868 { Bad_Opcode }, /* repne */
2869 { Bad_Opcode }, /* repz */
2870 { "hlt", { XX }, 0 },
2871 { "cmc", { XX }, 0 },
2872 { REG_TABLE (REG_F6) },
2873 { REG_TABLE (REG_F7) },
2875 { "clc", { XX }, 0 },
2876 { "stc", { XX }, 0 },
2877 { "cli", { XX }, 0 },
2878 { "sti", { XX }, 0 },
2879 { "cld", { XX }, 0 },
2880 { "std", { XX }, 0 },
2881 { REG_TABLE (REG_FE) },
2882 { REG_TABLE (REG_FF) },
2885 static const struct dis386 dis386_twobyte[] = {
2887 { REG_TABLE (REG_0F00 ) },
2888 { REG_TABLE (REG_0F01 ) },
2889 { "larS", { Gv, Ew }, 0 },
2890 { "lslS", { Gv, Ew }, 0 },
2892 { "syscall", { XX }, 0 },
2893 { "clts", { XX }, 0 },
2894 { "sysret%LP", { XX }, 0 },
2896 { "invd", { XX }, 0 },
2897 { PREFIX_TABLE (PREFIX_0F09) },
2899 { "ud2", { XX }, 0 },
2901 { REG_TABLE (REG_0F0D) },
2902 { "femms", { XX }, 0 },
2903 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2905 { PREFIX_TABLE (PREFIX_0F10) },
2906 { PREFIX_TABLE (PREFIX_0F11) },
2907 { PREFIX_TABLE (PREFIX_0F12) },
2908 { MOD_TABLE (MOD_0F13) },
2909 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2910 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2911 { PREFIX_TABLE (PREFIX_0F16) },
2912 { MOD_TABLE (MOD_0F17) },
2914 { REG_TABLE (REG_0F18) },
2915 { "nopQ", { Ev }, 0 },
2916 { PREFIX_TABLE (PREFIX_0F1A) },
2917 { PREFIX_TABLE (PREFIX_0F1B) },
2918 { PREFIX_TABLE (PREFIX_0F1C) },
2919 { "nopQ", { Ev }, 0 },
2920 { PREFIX_TABLE (PREFIX_0F1E) },
2921 { "nopQ", { Ev }, 0 },
2923 { "movZ", { Rm, Cm }, 0 },
2924 { "movZ", { Rm, Dm }, 0 },
2925 { "movZ", { Cm, Rm }, 0 },
2926 { "movZ", { Dm, Rm }, 0 },
2927 { MOD_TABLE (MOD_0F24) },
2929 { MOD_TABLE (MOD_0F26) },
2932 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2933 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2934 { PREFIX_TABLE (PREFIX_0F2A) },
2935 { PREFIX_TABLE (PREFIX_0F2B) },
2936 { PREFIX_TABLE (PREFIX_0F2C) },
2937 { PREFIX_TABLE (PREFIX_0F2D) },
2938 { PREFIX_TABLE (PREFIX_0F2E) },
2939 { PREFIX_TABLE (PREFIX_0F2F) },
2941 { "wrmsr", { XX }, 0 },
2942 { "rdtsc", { XX }, 0 },
2943 { "rdmsr", { XX }, 0 },
2944 { "rdpmc", { XX }, 0 },
2945 { "sysenter", { XX }, 0 },
2946 { "sysexit", { XX }, 0 },
2948 { "getsec", { XX }, 0 },
2950 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2952 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2959 { "cmovoS", { Gv, Ev }, 0 },
2960 { "cmovnoS", { Gv, Ev }, 0 },
2961 { "cmovbS", { Gv, Ev }, 0 },
2962 { "cmovaeS", { Gv, Ev }, 0 },
2963 { "cmoveS", { Gv, Ev }, 0 },
2964 { "cmovneS", { Gv, Ev }, 0 },
2965 { "cmovbeS", { Gv, Ev }, 0 },
2966 { "cmovaS", { Gv, Ev }, 0 },
2968 { "cmovsS", { Gv, Ev }, 0 },
2969 { "cmovnsS", { Gv, Ev }, 0 },
2970 { "cmovpS", { Gv, Ev }, 0 },
2971 { "cmovnpS", { Gv, Ev }, 0 },
2972 { "cmovlS", { Gv, Ev }, 0 },
2973 { "cmovgeS", { Gv, Ev }, 0 },
2974 { "cmovleS", { Gv, Ev }, 0 },
2975 { "cmovgS", { Gv, Ev }, 0 },
2977 { MOD_TABLE (MOD_0F51) },
2978 { PREFIX_TABLE (PREFIX_0F51) },
2979 { PREFIX_TABLE (PREFIX_0F52) },
2980 { PREFIX_TABLE (PREFIX_0F53) },
2981 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2982 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2983 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2984 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2986 { PREFIX_TABLE (PREFIX_0F58) },
2987 { PREFIX_TABLE (PREFIX_0F59) },
2988 { PREFIX_TABLE (PREFIX_0F5A) },
2989 { PREFIX_TABLE (PREFIX_0F5B) },
2990 { PREFIX_TABLE (PREFIX_0F5C) },
2991 { PREFIX_TABLE (PREFIX_0F5D) },
2992 { PREFIX_TABLE (PREFIX_0F5E) },
2993 { PREFIX_TABLE (PREFIX_0F5F) },
2995 { PREFIX_TABLE (PREFIX_0F60) },
2996 { PREFIX_TABLE (PREFIX_0F61) },
2997 { PREFIX_TABLE (PREFIX_0F62) },
2998 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2999 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
3000 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
3001 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
3002 { "packuswb", { MX, EM }, PREFIX_OPCODE },
3004 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
3005 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
3006 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
3007 { "packssdw", { MX, EM }, PREFIX_OPCODE },
3008 { PREFIX_TABLE (PREFIX_0F6C) },
3009 { PREFIX_TABLE (PREFIX_0F6D) },
3010 { "movK", { MX, Edq }, PREFIX_OPCODE },
3011 { PREFIX_TABLE (PREFIX_0F6F) },
3013 { PREFIX_TABLE (PREFIX_0F70) },
3014 { REG_TABLE (REG_0F71) },
3015 { REG_TABLE (REG_0F72) },
3016 { REG_TABLE (REG_0F73) },
3017 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
3018 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
3019 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
3020 { "emms", { XX }, PREFIX_OPCODE },
3022 { PREFIX_TABLE (PREFIX_0F78) },
3023 { PREFIX_TABLE (PREFIX_0F79) },
3026 { PREFIX_TABLE (PREFIX_0F7C) },
3027 { PREFIX_TABLE (PREFIX_0F7D) },
3028 { PREFIX_TABLE (PREFIX_0F7E) },
3029 { PREFIX_TABLE (PREFIX_0F7F) },
3031 { "joH", { Jv, BND, cond_jump_flag }, 0 },
3032 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
3033 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
3034 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
3035 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
3036 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
3037 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
3038 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
3040 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
3041 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
3042 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
3043 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
3044 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
3045 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
3046 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
3047 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
3049 { "seto", { Eb }, 0 },
3050 { "setno", { Eb }, 0 },
3051 { "setb", { Eb }, 0 },
3052 { "setae", { Eb }, 0 },
3053 { "sete", { Eb }, 0 },
3054 { "setne", { Eb }, 0 },
3055 { "setbe", { Eb }, 0 },
3056 { "seta", { Eb }, 0 },
3058 { "sets", { Eb }, 0 },
3059 { "setns", { Eb }, 0 },
3060 { "setp", { Eb }, 0 },
3061 { "setnp", { Eb }, 0 },
3062 { "setl", { Eb }, 0 },
3063 { "setge", { Eb }, 0 },
3064 { "setle", { Eb }, 0 },
3065 { "setg", { Eb }, 0 },
3067 { "pushT", { fs }, 0 },
3068 { "popT", { fs }, 0 },
3069 { "cpuid", { XX }, 0 },
3070 { "btS", { Ev, Gv }, 0 },
3071 { "shldS", { Ev, Gv, Ib }, 0 },
3072 { "shldS", { Ev, Gv, CL }, 0 },
3073 { REG_TABLE (REG_0FA6) },
3074 { REG_TABLE (REG_0FA7) },
3076 { "pushT", { gs }, 0 },
3077 { "popT", { gs }, 0 },
3078 { "rsm", { XX }, 0 },
3079 { "btsS", { Evh1, Gv }, 0 },
3080 { "shrdS", { Ev, Gv, Ib }, 0 },
3081 { "shrdS", { Ev, Gv, CL }, 0 },
3082 { REG_TABLE (REG_0FAE) },
3083 { "imulS", { Gv, Ev }, 0 },
3085 { "cmpxchgB", { Ebh1, Gb }, 0 },
3086 { "cmpxchgS", { Evh1, Gv }, 0 },
3087 { MOD_TABLE (MOD_0FB2) },
3088 { "btrS", { Evh1, Gv }, 0 },
3089 { MOD_TABLE (MOD_0FB4) },
3090 { MOD_TABLE (MOD_0FB5) },
3091 { "movz{bR|x}", { Gv, Eb }, 0 },
3092 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3094 { PREFIX_TABLE (PREFIX_0FB8) },
3095 { "ud1S", { Gv, Ev }, 0 },
3096 { REG_TABLE (REG_0FBA) },
3097 { "btcS", { Evh1, Gv }, 0 },
3098 { PREFIX_TABLE (PREFIX_0FBC) },
3099 { PREFIX_TABLE (PREFIX_0FBD) },
3100 { "movs{bR|x}", { Gv, Eb }, 0 },
3101 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3103 { "xaddB", { Ebh1, Gb }, 0 },
3104 { "xaddS", { Evh1, Gv }, 0 },
3105 { PREFIX_TABLE (PREFIX_0FC2) },
3106 { MOD_TABLE (MOD_0FC3) },
3107 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
3108 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
3109 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
3110 { REG_TABLE (REG_0FC7) },
3112 { "bswap", { RMeAX }, 0 },
3113 { "bswap", { RMeCX }, 0 },
3114 { "bswap", { RMeDX }, 0 },
3115 { "bswap", { RMeBX }, 0 },
3116 { "bswap", { RMeSP }, 0 },
3117 { "bswap", { RMeBP }, 0 },
3118 { "bswap", { RMeSI }, 0 },
3119 { "bswap", { RMeDI }, 0 },
3121 { PREFIX_TABLE (PREFIX_0FD0) },
3122 { "psrlw", { MX, EM }, PREFIX_OPCODE },
3123 { "psrld", { MX, EM }, PREFIX_OPCODE },
3124 { "psrlq", { MX, EM }, PREFIX_OPCODE },
3125 { "paddq", { MX, EM }, PREFIX_OPCODE },
3126 { "pmullw", { MX, EM }, PREFIX_OPCODE },
3127 { PREFIX_TABLE (PREFIX_0FD6) },
3128 { MOD_TABLE (MOD_0FD7) },
3130 { "psubusb", { MX, EM }, PREFIX_OPCODE },
3131 { "psubusw", { MX, EM }, PREFIX_OPCODE },
3132 { "pminub", { MX, EM }, PREFIX_OPCODE },
3133 { "pand", { MX, EM }, PREFIX_OPCODE },
3134 { "paddusb", { MX, EM }, PREFIX_OPCODE },
3135 { "paddusw", { MX, EM }, PREFIX_OPCODE },
3136 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
3137 { "pandn", { MX, EM }, PREFIX_OPCODE },
3139 { "pavgb", { MX, EM }, PREFIX_OPCODE },
3140 { "psraw", { MX, EM }, PREFIX_OPCODE },
3141 { "psrad", { MX, EM }, PREFIX_OPCODE },
3142 { "pavgw", { MX, EM }, PREFIX_OPCODE },
3143 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
3144 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
3145 { PREFIX_TABLE (PREFIX_0FE6) },
3146 { PREFIX_TABLE (PREFIX_0FE7) },
3148 { "psubsb", { MX, EM }, PREFIX_OPCODE },
3149 { "psubsw", { MX, EM }, PREFIX_OPCODE },
3150 { "pminsw", { MX, EM }, PREFIX_OPCODE },
3151 { "por", { MX, EM }, PREFIX_OPCODE },
3152 { "paddsb", { MX, EM }, PREFIX_OPCODE },
3153 { "paddsw", { MX, EM }, PREFIX_OPCODE },
3154 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
3155 { "pxor", { MX, EM }, PREFIX_OPCODE },
3157 { PREFIX_TABLE (PREFIX_0FF0) },
3158 { "psllw", { MX, EM }, PREFIX_OPCODE },
3159 { "pslld", { MX, EM }, PREFIX_OPCODE },
3160 { "psllq", { MX, EM }, PREFIX_OPCODE },
3161 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
3162 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
3163 { "psadbw", { MX, EM }, PREFIX_OPCODE },
3164 { PREFIX_TABLE (PREFIX_0FF7) },
3166 { "psubb", { MX, EM }, PREFIX_OPCODE },
3167 { "psubw", { MX, EM }, PREFIX_OPCODE },
3168 { "psubd", { MX, EM }, PREFIX_OPCODE },
3169 { "psubq", { MX, EM }, PREFIX_OPCODE },
3170 { "paddb", { MX, EM }, PREFIX_OPCODE },
3171 { "paddw", { MX, EM }, PREFIX_OPCODE },
3172 { "paddd", { MX, EM }, PREFIX_OPCODE },
3173 { "ud0S", { Gv, Ev }, 0 },
3176 static const unsigned char onebyte_has_modrm[256] = {
3177 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3178 /* ------------------------------- */
3179 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3180 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3181 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3182 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3183 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3184 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3185 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3186 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3187 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3188 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3189 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3190 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3191 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3192 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3193 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3194 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3195 /* ------------------------------- */
3196 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3199 static const unsigned char twobyte_has_modrm[256] = {
3200 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3201 /* ------------------------------- */
3202 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3203 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3204 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3205 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3206 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3207 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3208 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3209 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3210 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3211 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3212 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3213 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
3214 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3215 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3216 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3217 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
3218 /* ------------------------------- */
3219 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3222 static char obuf[100];
3224 static char *mnemonicendp;
3225 static char scratchbuf[100];
3226 static unsigned char *start_codep;
3227 static unsigned char *insn_codep;
3228 static unsigned char *codep;
3229 static unsigned char *end_codep;
3230 static int last_lock_prefix;
3231 static int last_repz_prefix;
3232 static int last_repnz_prefix;
3233 static int last_data_prefix;
3234 static int last_addr_prefix;
3235 static int last_rex_prefix;
3236 static int last_seg_prefix;
3237 static int fwait_prefix;
3238 /* The active segment register prefix. */
3239 static int active_seg_prefix;
3240 #define MAX_CODE_LENGTH 15
3241 /* We can up to 14 prefixes since the maximum instruction length is
3243 static int all_prefixes[MAX_CODE_LENGTH - 1];
3244 static disassemble_info *the_info;
3252 static unsigned char need_modrm;
3262 int register_specifier;
3269 int mask_register_specifier;
3275 static unsigned char need_vex;
3276 static unsigned char need_vex_reg;
3277 static unsigned char vex_w_done;
3285 /* If we are accessing mod/rm/reg without need_modrm set, then the
3286 values are stale. Hitting this abort likely indicates that you
3287 need to update onebyte_has_modrm or twobyte_has_modrm. */
3288 #define MODRM_CHECK if (!need_modrm) abort ()
3290 static const char **names64;
3291 static const char **names32;
3292 static const char **names16;
3293 static const char **names8;
3294 static const char **names8rex;
3295 static const char **names_seg;
3296 static const char *index64;
3297 static const char *index32;
3298 static const char **index16;
3299 static const char **names_bnd;
3301 static const char *intel_names64[] = {
3302 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3303 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3305 static const char *intel_names32[] = {
3306 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3307 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3309 static const char *intel_names16[] = {
3310 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3311 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3313 static const char *intel_names8[] = {
3314 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3316 static const char *intel_names8rex[] = {
3317 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3318 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3320 static const char *intel_names_seg[] = {
3321 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3323 static const char *intel_index64 = "riz";
3324 static const char *intel_index32 = "eiz";
3325 static const char *intel_index16[] = {
3326 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3329 static const char *att_names64[] = {
3330 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3331 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3333 static const char *att_names32[] = {
3334 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3335 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3337 static const char *att_names16[] = {
3338 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3339 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3341 static const char *att_names8[] = {
3342 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3344 static const char *att_names8rex[] = {
3345 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3346 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3348 static const char *att_names_seg[] = {
3349 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3351 static const char *att_index64 = "%riz";
3352 static const char *att_index32 = "%eiz";
3353 static const char *att_index16[] = {
3354 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3357 static const char **names_mm;
3358 static const char *intel_names_mm[] = {
3359 "mm0", "mm1", "mm2", "mm3",
3360 "mm4", "mm5", "mm6", "mm7"
3362 static const char *att_names_mm[] = {
3363 "%mm0", "%mm1", "%mm2", "%mm3",
3364 "%mm4", "%mm5", "%mm6", "%mm7"
3367 static const char *intel_names_bnd[] = {
3368 "bnd0", "bnd1", "bnd2", "bnd3"
3371 static const char *att_names_bnd[] = {
3372 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3375 static const char **names_xmm;
3376 static const char *intel_names_xmm[] = {
3377 "xmm0", "xmm1", "xmm2", "xmm3",
3378 "xmm4", "xmm5", "xmm6", "xmm7",
3379 "xmm8", "xmm9", "xmm10", "xmm11",
3380 "xmm12", "xmm13", "xmm14", "xmm15",
3381 "xmm16", "xmm17", "xmm18", "xmm19",
3382 "xmm20", "xmm21", "xmm22", "xmm23",
3383 "xmm24", "xmm25", "xmm26", "xmm27",
3384 "xmm28", "xmm29", "xmm30", "xmm31"
3386 static const char *att_names_xmm[] = {
3387 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3388 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3389 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3390 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3391 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3392 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3393 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3394 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3397 static const char **names_ymm;
3398 static const char *intel_names_ymm[] = {
3399 "ymm0", "ymm1", "ymm2", "ymm3",
3400 "ymm4", "ymm5", "ymm6", "ymm7",
3401 "ymm8", "ymm9", "ymm10", "ymm11",
3402 "ymm12", "ymm13", "ymm14", "ymm15",
3403 "ymm16", "ymm17", "ymm18", "ymm19",
3404 "ymm20", "ymm21", "ymm22", "ymm23",
3405 "ymm24", "ymm25", "ymm26", "ymm27",
3406 "ymm28", "ymm29", "ymm30", "ymm31"
3408 static const char *att_names_ymm[] = {
3409 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3410 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3411 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3412 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3413 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3414 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3415 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3416 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3419 static const char **names_zmm;
3420 static const char *intel_names_zmm[] = {
3421 "zmm0", "zmm1", "zmm2", "zmm3",
3422 "zmm4", "zmm5", "zmm6", "zmm7",
3423 "zmm8", "zmm9", "zmm10", "zmm11",
3424 "zmm12", "zmm13", "zmm14", "zmm15",
3425 "zmm16", "zmm17", "zmm18", "zmm19",
3426 "zmm20", "zmm21", "zmm22", "zmm23",
3427 "zmm24", "zmm25", "zmm26", "zmm27",
3428 "zmm28", "zmm29", "zmm30", "zmm31"
3430 static const char *att_names_zmm[] = {
3431 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3432 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3433 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3434 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3435 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3436 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3437 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3438 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3441 static const char **names_mask;
3442 static const char *intel_names_mask[] = {
3443 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3445 static const char *att_names_mask[] = {
3446 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3449 static const char *names_rounding[] =
3457 static const struct dis386 reg_table[][8] = {
3460 { "addA", { Ebh1, Ib }, 0 },
3461 { "orA", { Ebh1, Ib }, 0 },
3462 { "adcA", { Ebh1, Ib }, 0 },
3463 { "sbbA", { Ebh1, Ib }, 0 },
3464 { "andA", { Ebh1, Ib }, 0 },
3465 { "subA", { Ebh1, Ib }, 0 },
3466 { "xorA", { Ebh1, Ib }, 0 },
3467 { "cmpA", { Eb, Ib }, 0 },
3471 { "addQ", { Evh1, Iv }, 0 },
3472 { "orQ", { Evh1, Iv }, 0 },
3473 { "adcQ", { Evh1, Iv }, 0 },
3474 { "sbbQ", { Evh1, Iv }, 0 },
3475 { "andQ", { Evh1, Iv }, 0 },
3476 { "subQ", { Evh1, Iv }, 0 },
3477 { "xorQ", { Evh1, Iv }, 0 },
3478 { "cmpQ", { Ev, Iv }, 0 },
3482 { "addQ", { Evh1, sIb }, 0 },
3483 { "orQ", { Evh1, sIb }, 0 },
3484 { "adcQ", { Evh1, sIb }, 0 },
3485 { "sbbQ", { Evh1, sIb }, 0 },
3486 { "andQ", { Evh1, sIb }, 0 },
3487 { "subQ", { Evh1, sIb }, 0 },
3488 { "xorQ", { Evh1, sIb }, 0 },
3489 { "cmpQ", { Ev, sIb }, 0 },
3493 { "popU", { stackEv }, 0 },
3494 { XOP_8F_TABLE (XOP_09) },
3498 { XOP_8F_TABLE (XOP_09) },
3502 { "rolA", { Eb, Ib }, 0 },
3503 { "rorA", { Eb, Ib }, 0 },
3504 { "rclA", { Eb, Ib }, 0 },
3505 { "rcrA", { Eb, Ib }, 0 },
3506 { "shlA", { Eb, Ib }, 0 },
3507 { "shrA", { Eb, Ib }, 0 },
3508 { "shlA", { Eb, Ib }, 0 },
3509 { "sarA", { Eb, Ib }, 0 },
3513 { "rolQ", { Ev, Ib }, 0 },
3514 { "rorQ", { Ev, Ib }, 0 },
3515 { "rclQ", { Ev, Ib }, 0 },
3516 { "rcrQ", { Ev, Ib }, 0 },
3517 { "shlQ", { Ev, Ib }, 0 },
3518 { "shrQ", { Ev, Ib }, 0 },
3519 { "shlQ", { Ev, Ib }, 0 },
3520 { "sarQ", { Ev, Ib }, 0 },
3524 { "movA", { Ebh3, Ib }, 0 },
3531 { MOD_TABLE (MOD_C6_REG_7) },
3535 { "movQ", { Evh3, Iv }, 0 },
3542 { MOD_TABLE (MOD_C7_REG_7) },
3546 { "rolA", { Eb, I1 }, 0 },
3547 { "rorA", { Eb, I1 }, 0 },
3548 { "rclA", { Eb, I1 }, 0 },
3549 { "rcrA", { Eb, I1 }, 0 },
3550 { "shlA", { Eb, I1 }, 0 },
3551 { "shrA", { Eb, I1 }, 0 },
3552 { "shlA", { Eb, I1 }, 0 },
3553 { "sarA", { Eb, I1 }, 0 },
3557 { "rolQ", { Ev, I1 }, 0 },
3558 { "rorQ", { Ev, I1 }, 0 },
3559 { "rclQ", { Ev, I1 }, 0 },
3560 { "rcrQ", { Ev, I1 }, 0 },
3561 { "shlQ", { Ev, I1 }, 0 },
3562 { "shrQ", { Ev, I1 }, 0 },
3563 { "shlQ", { Ev, I1 }, 0 },
3564 { "sarQ", { Ev, I1 }, 0 },
3568 { "rolA", { Eb, CL }, 0 },
3569 { "rorA", { Eb, CL }, 0 },
3570 { "rclA", { Eb, CL }, 0 },
3571 { "rcrA", { Eb, CL }, 0 },
3572 { "shlA", { Eb, CL }, 0 },
3573 { "shrA", { Eb, CL }, 0 },
3574 { "shlA", { Eb, CL }, 0 },
3575 { "sarA", { Eb, CL }, 0 },
3579 { "rolQ", { Ev, CL }, 0 },
3580 { "rorQ", { Ev, CL }, 0 },
3581 { "rclQ", { Ev, CL }, 0 },
3582 { "rcrQ", { Ev, CL }, 0 },
3583 { "shlQ", { Ev, CL }, 0 },
3584 { "shrQ", { Ev, CL }, 0 },
3585 { "shlQ", { Ev, CL }, 0 },
3586 { "sarQ", { Ev, CL }, 0 },
3590 { "testA", { Eb, Ib }, 0 },
3591 { "testA", { Eb, Ib }, 0 },
3592 { "notA", { Ebh1 }, 0 },
3593 { "negA", { Ebh1 }, 0 },
3594 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
3595 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
3596 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
3597 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
3601 { "testQ", { Ev, Iv }, 0 },
3602 { "testQ", { Ev, Iv }, 0 },
3603 { "notQ", { Evh1 }, 0 },
3604 { "negQ", { Evh1 }, 0 },
3605 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
3606 { "imulQ", { Ev }, 0 },
3607 { "divQ", { Ev }, 0 },
3608 { "idivQ", { Ev }, 0 },
3612 { "incA", { Ebh1 }, 0 },
3613 { "decA", { Ebh1 }, 0 },
3617 { "incQ", { Evh1 }, 0 },
3618 { "decQ", { Evh1 }, 0 },
3619 { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3620 { MOD_TABLE (MOD_FF_REG_3) },
3621 { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3622 { MOD_TABLE (MOD_FF_REG_5) },
3623 { "pushU", { stackEv }, 0 },
3628 { "sldtD", { Sv }, 0 },
3629 { "strD", { Sv }, 0 },
3630 { "lldt", { Ew }, 0 },
3631 { "ltr", { Ew }, 0 },
3632 { "verr", { Ew }, 0 },
3633 { "verw", { Ew }, 0 },
3639 { MOD_TABLE (MOD_0F01_REG_0) },
3640 { MOD_TABLE (MOD_0F01_REG_1) },
3641 { MOD_TABLE (MOD_0F01_REG_2) },
3642 { MOD_TABLE (MOD_0F01_REG_3) },
3643 { "smswD", { Sv }, 0 },
3644 { MOD_TABLE (MOD_0F01_REG_5) },
3645 { "lmsw", { Ew }, 0 },
3646 { MOD_TABLE (MOD_0F01_REG_7) },
3650 { "prefetch", { Mb }, 0 },
3651 { "prefetchw", { Mb }, 0 },
3652 { "prefetchwt1", { Mb }, 0 },
3653 { "prefetch", { Mb }, 0 },
3654 { "prefetch", { Mb }, 0 },
3655 { "prefetch", { Mb }, 0 },
3656 { "prefetch", { Mb }, 0 },
3657 { "prefetch", { Mb }, 0 },
3661 { MOD_TABLE (MOD_0F18_REG_0) },
3662 { MOD_TABLE (MOD_0F18_REG_1) },
3663 { MOD_TABLE (MOD_0F18_REG_2) },
3664 { MOD_TABLE (MOD_0F18_REG_3) },
3665 { MOD_TABLE (MOD_0F18_REG_4) },
3666 { MOD_TABLE (MOD_0F18_REG_5) },
3667 { MOD_TABLE (MOD_0F18_REG_6) },
3668 { MOD_TABLE (MOD_0F18_REG_7) },
3670 /* REG_0F1C_MOD_0 */
3672 { "cldemote", { Mb }, 0 },
3673 { "nopQ", { Ev }, 0 },
3674 { "nopQ", { Ev }, 0 },
3675 { "nopQ", { Ev }, 0 },
3676 { "nopQ", { Ev }, 0 },
3677 { "nopQ", { Ev }, 0 },
3678 { "nopQ", { Ev }, 0 },
3679 { "nopQ", { Ev }, 0 },
3681 /* REG_0F1E_MOD_3 */
3683 { "nopQ", { Ev }, 0 },
3684 { "rdsspK", { Rdq }, PREFIX_OPCODE },
3685 { "nopQ", { Ev }, 0 },
3686 { "nopQ", { Ev }, 0 },
3687 { "nopQ", { Ev }, 0 },
3688 { "nopQ", { Ev }, 0 },
3689 { "nopQ", { Ev }, 0 },
3690 { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3696 { MOD_TABLE (MOD_0F71_REG_2) },
3698 { MOD_TABLE (MOD_0F71_REG_4) },
3700 { MOD_TABLE (MOD_0F71_REG_6) },
3706 { MOD_TABLE (MOD_0F72_REG_2) },
3708 { MOD_TABLE (MOD_0F72_REG_4) },
3710 { MOD_TABLE (MOD_0F72_REG_6) },
3716 { MOD_TABLE (MOD_0F73_REG_2) },
3717 { MOD_TABLE (MOD_0F73_REG_3) },
3720 { MOD_TABLE (MOD_0F73_REG_6) },
3721 { MOD_TABLE (MOD_0F73_REG_7) },
3725 { "montmul", { { OP_0f07, 0 } }, 0 },
3726 { "xsha1", { { OP_0f07, 0 } }, 0 },
3727 { "xsha256", { { OP_0f07, 0 } }, 0 },
3731 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
3732 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
3733 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
3734 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
3735 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
3736 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
3740 { MOD_TABLE (MOD_0FAE_REG_0) },
3741 { MOD_TABLE (MOD_0FAE_REG_1) },
3742 { MOD_TABLE (MOD_0FAE_REG_2) },
3743 { MOD_TABLE (MOD_0FAE_REG_3) },
3744 { MOD_TABLE (MOD_0FAE_REG_4) },
3745 { MOD_TABLE (MOD_0FAE_REG_5) },
3746 { MOD_TABLE (MOD_0FAE_REG_6) },
3747 { MOD_TABLE (MOD_0FAE_REG_7) },
3755 { "btQ", { Ev, Ib }, 0 },
3756 { "btsQ", { Evh1, Ib }, 0 },
3757 { "btrQ", { Evh1, Ib }, 0 },
3758 { "btcQ", { Evh1, Ib }, 0 },
3763 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3765 { MOD_TABLE (MOD_0FC7_REG_3) },
3766 { MOD_TABLE (MOD_0FC7_REG_4) },
3767 { MOD_TABLE (MOD_0FC7_REG_5) },
3768 { MOD_TABLE (MOD_0FC7_REG_6) },
3769 { MOD_TABLE (MOD_0FC7_REG_7) },
3775 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3777 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3779 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3785 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3787 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3789 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3795 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3796 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3799 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3800 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3806 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3807 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3809 /* REG_VEX_0F38F3 */
3812 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3813 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3814 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3818 { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3819 { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3823 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3824 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3826 /* REG_XOP_TBM_01 */
3829 { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3830 { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3831 { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 },
3832 { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3833 { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 },
3834 { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 },
3835 { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3837 /* REG_XOP_TBM_02 */
3840 { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3845 { "blci", { { OP_LWP_E, 0 }, Ev }, 0 },
3847 #define NEED_REG_TABLE
3848 #include "i386-dis-evex.h"
3849 #undef NEED_REG_TABLE
3852 static const struct dis386 prefix_table[][4] = {
3855 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3856 { "pause", { XX }, 0 },
3857 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3858 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3861 /* PREFIX_MOD_0_0F01_REG_5 */
3864 { "rstorssp", { Mq }, PREFIX_OPCODE },
3867 /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3870 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3873 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3876 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3881 { "wbinvd", { XX }, 0 },
3882 { "wbnoinvd", { XX }, 0 },
3887 { "movups", { XM, EXx }, PREFIX_OPCODE },
3888 { "movss", { XM, EXd }, PREFIX_OPCODE },
3889 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3890 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3895 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3896 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3897 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3898 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3903 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3904 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3905 { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3906 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3911 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3912 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3913 { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3918 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3919 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3920 { "bndmov", { Gbnd, Ebnd }, 0 },
3921 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3926 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3927 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3928 { "bndmov", { EbndS, Gbnd }, 0 },
3929 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3934 { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3935 { "nopQ", { Ev }, PREFIX_OPCODE },
3936 { "nopQ", { Ev }, PREFIX_OPCODE },
3937 { "nopQ", { Ev }, PREFIX_OPCODE },
3942 { "nopQ", { Ev }, PREFIX_OPCODE },
3943 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3944 { "nopQ", { Ev }, PREFIX_OPCODE },
3945 { "nopQ", { Ev }, PREFIX_OPCODE },
3950 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3951 { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3952 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3953 { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3958 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3959 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3960 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3961 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3966 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3967 { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE },
3968 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3969 { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE },
3974 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3975 { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE },
3976 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3977 { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE },
3982 { "ucomiss",{ XM, EXd }, 0 },
3984 { "ucomisd",{ XM, EXq }, 0 },
3989 { "comiss", { XM, EXd }, 0 },
3991 { "comisd", { XM, EXq }, 0 },
3996 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3997 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3998 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3999 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
4004 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
4005 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
4010 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
4011 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
4016 { "addps", { XM, EXx }, PREFIX_OPCODE },
4017 { "addss", { XM, EXd }, PREFIX_OPCODE },
4018 { "addpd", { XM, EXx }, PREFIX_OPCODE },
4019 { "addsd", { XM, EXq }, PREFIX_OPCODE },
4024 { "mulps", { XM, EXx }, PREFIX_OPCODE },
4025 { "mulss", { XM, EXd }, PREFIX_OPCODE },
4026 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
4027 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
4032 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
4033 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
4034 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
4035 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
4040 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
4041 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
4042 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
4047 { "subps", { XM, EXx }, PREFIX_OPCODE },
4048 { "subss", { XM, EXd }, PREFIX_OPCODE },
4049 { "subpd", { XM, EXx }, PREFIX_OPCODE },
4050 { "subsd", { XM, EXq }, PREFIX_OPCODE },
4055 { "minps", { XM, EXx }, PREFIX_OPCODE },
4056 { "minss", { XM, EXd }, PREFIX_OPCODE },
4057 { "minpd", { XM, EXx }, PREFIX_OPCODE },
4058 { "minsd", { XM, EXq }, PREFIX_OPCODE },
4063 { "divps", { XM, EXx }, PREFIX_OPCODE },
4064 { "divss", { XM, EXd }, PREFIX_OPCODE },
4065 { "divpd", { XM, EXx }, PREFIX_OPCODE },
4066 { "divsd", { XM, EXq }, PREFIX_OPCODE },
4071 { "maxps", { XM, EXx }, PREFIX_OPCODE },
4072 { "maxss", { XM, EXd }, PREFIX_OPCODE },
4073 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
4074 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
4079 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
4081 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
4086 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
4088 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
4093 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
4095 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
4102 { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
4109 { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
4114 { "movq", { MX, EM }, PREFIX_OPCODE },
4115 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
4116 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4121 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4122 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4123 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4124 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4127 /* PREFIX_0F73_REG_3 */
4131 { "psrldq", { XS, Ib }, 0 },
4134 /* PREFIX_0F73_REG_7 */
4138 { "pslldq", { XS, Ib }, 0 },
4143 {"vmread", { Em, Gm }, 0 },
4145 {"extrq", { XS, Ib, Ib }, 0 },
4146 {"insertq", { XM, XS, Ib, Ib }, 0 },
4151 {"vmwrite", { Gm, Em }, 0 },
4153 {"extrq", { XM, XS }, 0 },
4154 {"insertq", { XM, XS }, 0 },
4161 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4162 { "haddps", { XM, EXx }, PREFIX_OPCODE },
4169 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4170 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4175 { "movK", { Edq, MX }, PREFIX_OPCODE },
4176 { "movq", { XM, EXq }, PREFIX_OPCODE },
4177 { "movK", { Edq, XM }, PREFIX_OPCODE },
4182 { "movq", { EMS, MX }, PREFIX_OPCODE },
4183 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4184 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4187 /* PREFIX_0FAE_REG_0 */
4190 { "rdfsbase", { Ev }, 0 },
4193 /* PREFIX_0FAE_REG_1 */
4196 { "rdgsbase", { Ev }, 0 },
4199 /* PREFIX_0FAE_REG_2 */
4202 { "wrfsbase", { Ev }, 0 },
4205 /* PREFIX_0FAE_REG_3 */
4208 { "wrgsbase", { Ev }, 0 },
4211 /* PREFIX_MOD_0_0FAE_REG_4 */
4213 { "xsave", { FXSAVE }, 0 },
4214 { "ptwrite%LQ", { Edq }, 0 },
4217 /* PREFIX_MOD_3_0FAE_REG_4 */
4220 { "ptwrite%LQ", { Edq }, 0 },
4223 /* PREFIX_MOD_0_0FAE_REG_5 */
4225 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
4228 /* PREFIX_MOD_3_0FAE_REG_5 */
4230 { "lfence", { Skip_MODRM }, 0 },
4231 { "incsspK", { Rdq }, PREFIX_OPCODE },
4234 /* PREFIX_MOD_0_0FAE_REG_6 */
4236 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
4237 { "clrssbsy", { Mq }, PREFIX_OPCODE },
4238 { "clwb", { Mb }, PREFIX_OPCODE },
4241 /* PREFIX_MOD_1_0FAE_REG_6 */
4243 { RM_TABLE (RM_0FAE_REG_6) },
4244 { "umonitor", { Eva }, PREFIX_OPCODE },
4245 { "tpause", { Edq }, PREFIX_OPCODE },
4246 { "umwait", { Edq }, PREFIX_OPCODE },
4249 /* PREFIX_0FAE_REG_7 */
4251 { "clflush", { Mb }, 0 },
4253 { "clflushopt", { Mb }, 0 },
4259 { "popcntS", { Gv, Ev }, 0 },
4264 { "bsfS", { Gv, Ev }, 0 },
4265 { "tzcntS", { Gv, Ev }, 0 },
4266 { "bsfS", { Gv, Ev }, 0 },
4271 { "bsrS", { Gv, Ev }, 0 },
4272 { "lzcntS", { Gv, Ev }, 0 },
4273 { "bsrS", { Gv, Ev }, 0 },
4278 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
4279 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
4280 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
4281 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
4284 /* PREFIX_MOD_0_0FC3 */
4286 { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4289 /* PREFIX_MOD_0_0FC7_REG_6 */
4291 { "vmptrld",{ Mq }, 0 },
4292 { "vmxon", { Mq }, 0 },
4293 { "vmclear",{ Mq }, 0 },
4296 /* PREFIX_MOD_3_0FC7_REG_6 */
4298 { "rdrand", { Ev }, 0 },
4300 { "rdrand", { Ev }, 0 }
4303 /* PREFIX_MOD_3_0FC7_REG_7 */
4305 { "rdseed", { Ev }, 0 },
4306 { "rdpid", { Em }, 0 },
4307 { "rdseed", { Ev }, 0 },
4314 { "addsubpd", { XM, EXx }, 0 },
4315 { "addsubps", { XM, EXx }, 0 },
4321 { "movq2dq",{ XM, MS }, 0 },
4322 { "movq", { EXqS, XM }, 0 },
4323 { "movdq2q",{ MX, XS }, 0 },
4329 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4330 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4331 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4336 { "movntq", { Mq, MX }, PREFIX_OPCODE },
4338 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4346 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4351 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4353 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4360 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4367 { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4374 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4381 { "ptest", { XM, EXx }, PREFIX_OPCODE },
4388 { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4395 { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4402 { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4409 { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4416 { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4423 { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4430 { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4437 { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4444 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4451 { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4458 { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4465 { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4472 { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4479 { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4486 { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4493 { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4500 { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4507 { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4514 { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4521 { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4528 { "pminud", { XM, EXx }, PREFIX_OPCODE },
4535 { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4542 { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4549 { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4556 { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4563 { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4570 { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4577 { "invept", { Gm, Mo }, PREFIX_OPCODE },
4584 { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4591 { "invpcid", { Gm, M }, PREFIX_OPCODE },
4596 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4601 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4606 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4611 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4616 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4621 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4628 { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4635 { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4642 { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4649 { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4656 { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4663 { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4668 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4670 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4671 { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4676 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4678 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4679 { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4686 { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4691 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4692 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
4693 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
4701 { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4706 { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4713 { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4720 { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4727 { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4734 { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4741 { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4748 { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4755 { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4762 { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4769 { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4776 { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4783 { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4790 { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4797 { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4804 { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4811 { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE },
4818 { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE },
4825 { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4832 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4839 { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4846 { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4853 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4860 { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4865 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4872 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4879 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4886 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4889 /* PREFIX_VEX_0F10 */
4891 { VEX_W_TABLE (VEX_W_0F10_P_0) },
4892 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4893 { VEX_W_TABLE (VEX_W_0F10_P_2) },
4894 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4897 /* PREFIX_VEX_0F11 */
4899 { VEX_W_TABLE (VEX_W_0F11_P_0) },
4900 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4901 { VEX_W_TABLE (VEX_W_0F11_P_2) },
4902 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4905 /* PREFIX_VEX_0F12 */
4907 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4908 { VEX_W_TABLE (VEX_W_0F12_P_1) },
4909 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4910 { VEX_W_TABLE (VEX_W_0F12_P_3) },
4913 /* PREFIX_VEX_0F16 */
4915 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4916 { VEX_W_TABLE (VEX_W_0F16_P_1) },
4917 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4920 /* PREFIX_VEX_0F2A */
4923 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4925 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4928 /* PREFIX_VEX_0F2C */
4931 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4933 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4936 /* PREFIX_VEX_0F2D */
4939 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4941 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4944 /* PREFIX_VEX_0F2E */
4946 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4948 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4951 /* PREFIX_VEX_0F2F */
4953 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4955 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4958 /* PREFIX_VEX_0F41 */
4960 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4962 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4965 /* PREFIX_VEX_0F42 */
4967 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4969 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4972 /* PREFIX_VEX_0F44 */
4974 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4976 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4979 /* PREFIX_VEX_0F45 */
4981 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4983 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4986 /* PREFIX_VEX_0F46 */
4988 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4990 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4993 /* PREFIX_VEX_0F47 */
4995 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4997 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
5000 /* PREFIX_VEX_0F4A */
5002 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
5004 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
5007 /* PREFIX_VEX_0F4B */
5009 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
5011 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
5014 /* PREFIX_VEX_0F51 */
5016 { VEX_W_TABLE (VEX_W_0F51_P_0) },
5017 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
5018 { VEX_W_TABLE (VEX_W_0F51_P_2) },
5019 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
5022 /* PREFIX_VEX_0F52 */
5024 { VEX_W_TABLE (VEX_W_0F52_P_0) },
5025 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
5028 /* PREFIX_VEX_0F53 */
5030 { VEX_W_TABLE (VEX_W_0F53_P_0) },
5031 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
5034 /* PREFIX_VEX_0F58 */
5036 { VEX_W_TABLE (VEX_W_0F58_P_0) },
5037 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
5038 { VEX_W_TABLE (VEX_W_0F58_P_2) },
5039 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
5042 /* PREFIX_VEX_0F59 */
5044 { VEX_W_TABLE (VEX_W_0F59_P_0) },
5045 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
5046 { VEX_W_TABLE (VEX_W_0F59_P_2) },
5047 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
5050 /* PREFIX_VEX_0F5A */
5052 { VEX_W_TABLE (VEX_W_0F5A_P_0) },
5053 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
5054 { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
5055 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
5058 /* PREFIX_VEX_0F5B */
5060 { VEX_W_TABLE (VEX_W_0F5B_P_0) },
5061 { VEX_W_TABLE (VEX_W_0F5B_P_1) },
5062 { VEX_W_TABLE (VEX_W_0F5B_P_2) },
5065 /* PREFIX_VEX_0F5C */
5067 { VEX_W_TABLE (VEX_W_0F5C_P_0) },
5068 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
5069 { VEX_W_TABLE (VEX_W_0F5C_P_2) },
5070 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
5073 /* PREFIX_VEX_0F5D */
5075 { VEX_W_TABLE (VEX_W_0F5D_P_0) },
5076 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
5077 { VEX_W_TABLE (VEX_W_0F5D_P_2) },
5078 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
5081 /* PREFIX_VEX_0F5E */
5083 { VEX_W_TABLE (VEX_W_0F5E_P_0) },
5084 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
5085 { VEX_W_TABLE (VEX_W_0F5E_P_2) },
5086 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
5089 /* PREFIX_VEX_0F5F */
5091 { VEX_W_TABLE (VEX_W_0F5F_P_0) },
5092 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
5093 { VEX_W_TABLE (VEX_W_0F5F_P_2) },
5094 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
5097 /* PREFIX_VEX_0F60 */
5101 { VEX_W_TABLE (VEX_W_0F60_P_2) },
5104 /* PREFIX_VEX_0F61 */
5108 { VEX_W_TABLE (VEX_W_0F61_P_2) },
5111 /* PREFIX_VEX_0F62 */
5115 { VEX_W_TABLE (VEX_W_0F62_P_2) },
5118 /* PREFIX_VEX_0F63 */
5122 { VEX_W_TABLE (VEX_W_0F63_P_2) },
5125 /* PREFIX_VEX_0F64 */
5129 { VEX_W_TABLE (VEX_W_0F64_P_2) },
5132 /* PREFIX_VEX_0F65 */
5136 { VEX_W_TABLE (VEX_W_0F65_P_2) },
5139 /* PREFIX_VEX_0F66 */
5143 { VEX_W_TABLE (VEX_W_0F66_P_2) },
5146 /* PREFIX_VEX_0F67 */
5150 { VEX_W_TABLE (VEX_W_0F67_P_2) },
5153 /* PREFIX_VEX_0F68 */
5157 { VEX_W_TABLE (VEX_W_0F68_P_2) },
5160 /* PREFIX_VEX_0F69 */
5164 { VEX_W_TABLE (VEX_W_0F69_P_2) },
5167 /* PREFIX_VEX_0F6A */
5171 { VEX_W_TABLE (VEX_W_0F6A_P_2) },
5174 /* PREFIX_VEX_0F6B */
5178 { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5181 /* PREFIX_VEX_0F6C */
5185 { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5188 /* PREFIX_VEX_0F6D */
5192 { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5195 /* PREFIX_VEX_0F6E */
5199 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5202 /* PREFIX_VEX_0F6F */
5205 { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5206 { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5209 /* PREFIX_VEX_0F70 */
5212 { VEX_W_TABLE (VEX_W_0F70_P_1) },
5213 { VEX_W_TABLE (VEX_W_0F70_P_2) },
5214 { VEX_W_TABLE (VEX_W_0F70_P_3) },
5217 /* PREFIX_VEX_0F71_REG_2 */
5221 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5224 /* PREFIX_VEX_0F71_REG_4 */
5228 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5231 /* PREFIX_VEX_0F71_REG_6 */
5235 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5238 /* PREFIX_VEX_0F72_REG_2 */
5242 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5245 /* PREFIX_VEX_0F72_REG_4 */
5249 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5252 /* PREFIX_VEX_0F72_REG_6 */
5256 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5259 /* PREFIX_VEX_0F73_REG_2 */
5263 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5266 /* PREFIX_VEX_0F73_REG_3 */
5270 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5273 /* PREFIX_VEX_0F73_REG_6 */
5277 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5280 /* PREFIX_VEX_0F73_REG_7 */
5284 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5287 /* PREFIX_VEX_0F74 */
5291 { VEX_W_TABLE (VEX_W_0F74_P_2) },
5294 /* PREFIX_VEX_0F75 */
5298 { VEX_W_TABLE (VEX_W_0F75_P_2) },
5301 /* PREFIX_VEX_0F76 */
5305 { VEX_W_TABLE (VEX_W_0F76_P_2) },
5308 /* PREFIX_VEX_0F77 */
5310 { VEX_W_TABLE (VEX_W_0F77_P_0) },
5313 /* PREFIX_VEX_0F7C */
5317 { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5318 { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5321 /* PREFIX_VEX_0F7D */
5325 { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5326 { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5329 /* PREFIX_VEX_0F7E */
5332 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5333 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5336 /* PREFIX_VEX_0F7F */
5339 { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5340 { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5343 /* PREFIX_VEX_0F90 */
5345 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5347 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5350 /* PREFIX_VEX_0F91 */
5352 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5354 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5357 /* PREFIX_VEX_0F92 */
5359 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5361 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5362 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5365 /* PREFIX_VEX_0F93 */
5367 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5369 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5370 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5373 /* PREFIX_VEX_0F98 */
5375 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5377 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5380 /* PREFIX_VEX_0F99 */
5382 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5384 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5387 /* PREFIX_VEX_0FC2 */
5389 { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5390 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5391 { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5392 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5395 /* PREFIX_VEX_0FC4 */
5399 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5402 /* PREFIX_VEX_0FC5 */
5406 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5409 /* PREFIX_VEX_0FD0 */
5413 { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5414 { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5417 /* PREFIX_VEX_0FD1 */
5421 { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5424 /* PREFIX_VEX_0FD2 */
5428 { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5431 /* PREFIX_VEX_0FD3 */
5435 { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5438 /* PREFIX_VEX_0FD4 */
5442 { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5445 /* PREFIX_VEX_0FD5 */
5449 { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5452 /* PREFIX_VEX_0FD6 */
5456 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5459 /* PREFIX_VEX_0FD7 */
5463 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5466 /* PREFIX_VEX_0FD8 */
5470 { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5473 /* PREFIX_VEX_0FD9 */
5477 { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5480 /* PREFIX_VEX_0FDA */
5484 { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5487 /* PREFIX_VEX_0FDB */
5491 { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5494 /* PREFIX_VEX_0FDC */
5498 { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5501 /* PREFIX_VEX_0FDD */
5505 { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5508 /* PREFIX_VEX_0FDE */
5512 { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5515 /* PREFIX_VEX_0FDF */
5519 { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5522 /* PREFIX_VEX_0FE0 */
5526 { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5529 /* PREFIX_VEX_0FE1 */
5533 { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5536 /* PREFIX_VEX_0FE2 */
5540 { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5543 /* PREFIX_VEX_0FE3 */
5547 { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5550 /* PREFIX_VEX_0FE4 */
5554 { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5557 /* PREFIX_VEX_0FE5 */
5561 { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5564 /* PREFIX_VEX_0FE6 */
5567 { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5568 { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5569 { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5572 /* PREFIX_VEX_0FE7 */
5576 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5579 /* PREFIX_VEX_0FE8 */
5583 { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5586 /* PREFIX_VEX_0FE9 */
5590 { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5593 /* PREFIX_VEX_0FEA */
5597 { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5600 /* PREFIX_VEX_0FEB */
5604 { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5607 /* PREFIX_VEX_0FEC */
5611 { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5614 /* PREFIX_VEX_0FED */
5618 { VEX_W_TABLE (VEX_W_0FED_P_2) },
5621 /* PREFIX_VEX_0FEE */
5625 { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5628 /* PREFIX_VEX_0FEF */
5632 { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5635 /* PREFIX_VEX_0FF0 */
5640 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5643 /* PREFIX_VEX_0FF1 */
5647 { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5650 /* PREFIX_VEX_0FF2 */
5654 { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5657 /* PREFIX_VEX_0FF3 */
5661 { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5664 /* PREFIX_VEX_0FF4 */
5668 { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5671 /* PREFIX_VEX_0FF5 */
5675 { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5678 /* PREFIX_VEX_0FF6 */
5682 { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5685 /* PREFIX_VEX_0FF7 */
5689 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5692 /* PREFIX_VEX_0FF8 */
5696 { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5699 /* PREFIX_VEX_0FF9 */
5703 { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5706 /* PREFIX_VEX_0FFA */
5710 { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5713 /* PREFIX_VEX_0FFB */
5717 { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5720 /* PREFIX_VEX_0FFC */
5724 { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5727 /* PREFIX_VEX_0FFD */
5731 { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5734 /* PREFIX_VEX_0FFE */
5738 { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5741 /* PREFIX_VEX_0F3800 */
5745 { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5748 /* PREFIX_VEX_0F3801 */
5752 { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5755 /* PREFIX_VEX_0F3802 */
5759 { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5762 /* PREFIX_VEX_0F3803 */
5766 { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5769 /* PREFIX_VEX_0F3804 */
5773 { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5776 /* PREFIX_VEX_0F3805 */
5780 { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5783 /* PREFIX_VEX_0F3806 */
5787 { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5790 /* PREFIX_VEX_0F3807 */
5794 { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5797 /* PREFIX_VEX_0F3808 */
5801 { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5804 /* PREFIX_VEX_0F3809 */
5808 { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5811 /* PREFIX_VEX_0F380A */
5815 { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5818 /* PREFIX_VEX_0F380B */
5822 { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5825 /* PREFIX_VEX_0F380C */
5829 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5832 /* PREFIX_VEX_0F380D */
5836 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5839 /* PREFIX_VEX_0F380E */
5843 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5846 /* PREFIX_VEX_0F380F */
5850 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5853 /* PREFIX_VEX_0F3813 */
5857 { "vcvtph2ps", { XM, EXxmmq }, 0 },
5860 /* PREFIX_VEX_0F3816 */
5864 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5867 /* PREFIX_VEX_0F3817 */
5871 { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5874 /* PREFIX_VEX_0F3818 */
5878 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5881 /* PREFIX_VEX_0F3819 */
5885 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5888 /* PREFIX_VEX_0F381A */
5892 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5895 /* PREFIX_VEX_0F381C */
5899 { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5902 /* PREFIX_VEX_0F381D */
5906 { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5909 /* PREFIX_VEX_0F381E */
5913 { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5916 /* PREFIX_VEX_0F3820 */
5920 { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5923 /* PREFIX_VEX_0F3821 */
5927 { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5930 /* PREFIX_VEX_0F3822 */
5934 { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5937 /* PREFIX_VEX_0F3823 */
5941 { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5944 /* PREFIX_VEX_0F3824 */
5948 { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5951 /* PREFIX_VEX_0F3825 */
5955 { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5958 /* PREFIX_VEX_0F3828 */
5962 { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5965 /* PREFIX_VEX_0F3829 */
5969 { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5972 /* PREFIX_VEX_0F382A */
5976 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5979 /* PREFIX_VEX_0F382B */
5983 { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5986 /* PREFIX_VEX_0F382C */
5990 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5993 /* PREFIX_VEX_0F382D */
5997 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
6000 /* PREFIX_VEX_0F382E */
6004 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
6007 /* PREFIX_VEX_0F382F */
6011 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
6014 /* PREFIX_VEX_0F3830 */
6018 { VEX_W_TABLE (VEX_W_0F3830_P_2) },
6021 /* PREFIX_VEX_0F3831 */
6025 { VEX_W_TABLE (VEX_W_0F3831_P_2) },
6028 /* PREFIX_VEX_0F3832 */
6032 { VEX_W_TABLE (VEX_W_0F3832_P_2) },
6035 /* PREFIX_VEX_0F3833 */
6039 { VEX_W_TABLE (VEX_W_0F3833_P_2) },
6042 /* PREFIX_VEX_0F3834 */
6046 { VEX_W_TABLE (VEX_W_0F3834_P_2) },
6049 /* PREFIX_VEX_0F3835 */
6053 { VEX_W_TABLE (VEX_W_0F3835_P_2) },
6056 /* PREFIX_VEX_0F3836 */
6060 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
6063 /* PREFIX_VEX_0F3837 */
6067 { VEX_W_TABLE (VEX_W_0F3837_P_2) },
6070 /* PREFIX_VEX_0F3838 */
6074 { VEX_W_TABLE (VEX_W_0F3838_P_2) },
6077 /* PREFIX_VEX_0F3839 */
6081 { VEX_W_TABLE (VEX_W_0F3839_P_2) },
6084 /* PREFIX_VEX_0F383A */
6088 { VEX_W_TABLE (VEX_W_0F383A_P_2) },
6091 /* PREFIX_VEX_0F383B */
6095 { VEX_W_TABLE (VEX_W_0F383B_P_2) },
6098 /* PREFIX_VEX_0F383C */
6102 { VEX_W_TABLE (VEX_W_0F383C_P_2) },
6105 /* PREFIX_VEX_0F383D */
6109 { VEX_W_TABLE (VEX_W_0F383D_P_2) },
6112 /* PREFIX_VEX_0F383E */
6116 { VEX_W_TABLE (VEX_W_0F383E_P_2) },
6119 /* PREFIX_VEX_0F383F */
6123 { VEX_W_TABLE (VEX_W_0F383F_P_2) },
6126 /* PREFIX_VEX_0F3840 */
6130 { VEX_W_TABLE (VEX_W_0F3840_P_2) },
6133 /* PREFIX_VEX_0F3841 */
6137 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
6140 /* PREFIX_VEX_0F3845 */
6144 { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
6147 /* PREFIX_VEX_0F3846 */
6151 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
6154 /* PREFIX_VEX_0F3847 */
6158 { "vpsllv%LW", { XM, Vex, EXx }, 0 },
6161 /* PREFIX_VEX_0F3858 */
6165 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
6168 /* PREFIX_VEX_0F3859 */
6172 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
6175 /* PREFIX_VEX_0F385A */
6179 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6182 /* PREFIX_VEX_0F3878 */
6186 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6189 /* PREFIX_VEX_0F3879 */
6193 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6196 /* PREFIX_VEX_0F388C */
6200 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6203 /* PREFIX_VEX_0F388E */
6207 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6210 /* PREFIX_VEX_0F3890 */
6214 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6217 /* PREFIX_VEX_0F3891 */
6221 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6224 /* PREFIX_VEX_0F3892 */
6228 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6231 /* PREFIX_VEX_0F3893 */
6235 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6238 /* PREFIX_VEX_0F3896 */
6242 { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6245 /* PREFIX_VEX_0F3897 */
6249 { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6252 /* PREFIX_VEX_0F3898 */
6256 { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6259 /* PREFIX_VEX_0F3899 */
6263 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6266 /* PREFIX_VEX_0F389A */
6270 { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6273 /* PREFIX_VEX_0F389B */
6277 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6280 /* PREFIX_VEX_0F389C */
6284 { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6287 /* PREFIX_VEX_0F389D */
6291 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6294 /* PREFIX_VEX_0F389E */
6298 { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6301 /* PREFIX_VEX_0F389F */
6305 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6308 /* PREFIX_VEX_0F38A6 */
6312 { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6316 /* PREFIX_VEX_0F38A7 */
6320 { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6323 /* PREFIX_VEX_0F38A8 */
6327 { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6330 /* PREFIX_VEX_0F38A9 */
6334 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6337 /* PREFIX_VEX_0F38AA */
6341 { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6344 /* PREFIX_VEX_0F38AB */
6348 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6351 /* PREFIX_VEX_0F38AC */
6355 { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6358 /* PREFIX_VEX_0F38AD */
6362 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6365 /* PREFIX_VEX_0F38AE */
6369 { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6372 /* PREFIX_VEX_0F38AF */
6376 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6379 /* PREFIX_VEX_0F38B6 */
6383 { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6386 /* PREFIX_VEX_0F38B7 */
6390 { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6393 /* PREFIX_VEX_0F38B8 */
6397 { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6400 /* PREFIX_VEX_0F38B9 */
6404 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6407 /* PREFIX_VEX_0F38BA */
6411 { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6414 /* PREFIX_VEX_0F38BB */
6418 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6421 /* PREFIX_VEX_0F38BC */
6425 { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6428 /* PREFIX_VEX_0F38BD */
6432 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6435 /* PREFIX_VEX_0F38BE */
6439 { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6442 /* PREFIX_VEX_0F38BF */
6446 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6449 /* PREFIX_VEX_0F38CF */
6453 { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6456 /* PREFIX_VEX_0F38DB */
6460 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6463 /* PREFIX_VEX_0F38DC */
6467 { "vaesenc", { XM, Vex, EXx }, 0 },
6470 /* PREFIX_VEX_0F38DD */
6474 { "vaesenclast", { XM, Vex, EXx }, 0 },
6477 /* PREFIX_VEX_0F38DE */
6481 { "vaesdec", { XM, Vex, EXx }, 0 },
6484 /* PREFIX_VEX_0F38DF */
6488 { "vaesdeclast", { XM, Vex, EXx }, 0 },
6491 /* PREFIX_VEX_0F38F2 */
6493 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6496 /* PREFIX_VEX_0F38F3_REG_1 */
6498 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6501 /* PREFIX_VEX_0F38F3_REG_2 */
6503 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6506 /* PREFIX_VEX_0F38F3_REG_3 */
6508 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6511 /* PREFIX_VEX_0F38F5 */
6513 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6514 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6516 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6519 /* PREFIX_VEX_0F38F6 */
6524 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6527 /* PREFIX_VEX_0F38F7 */
6529 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6530 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6531 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6532 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6535 /* PREFIX_VEX_0F3A00 */
6539 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6542 /* PREFIX_VEX_0F3A01 */
6546 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6549 /* PREFIX_VEX_0F3A02 */
6553 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6556 /* PREFIX_VEX_0F3A04 */
6560 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6563 /* PREFIX_VEX_0F3A05 */
6567 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6570 /* PREFIX_VEX_0F3A06 */
6574 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6577 /* PREFIX_VEX_0F3A08 */
6581 { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6584 /* PREFIX_VEX_0F3A09 */
6588 { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6591 /* PREFIX_VEX_0F3A0A */
6595 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6598 /* PREFIX_VEX_0F3A0B */
6602 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6605 /* PREFIX_VEX_0F3A0C */
6609 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6612 /* PREFIX_VEX_0F3A0D */
6616 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6619 /* PREFIX_VEX_0F3A0E */
6623 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6626 /* PREFIX_VEX_0F3A0F */
6630 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6633 /* PREFIX_VEX_0F3A14 */
6637 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6640 /* PREFIX_VEX_0F3A15 */
6644 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6647 /* PREFIX_VEX_0F3A16 */
6651 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6654 /* PREFIX_VEX_0F3A17 */
6658 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6661 /* PREFIX_VEX_0F3A18 */
6665 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6668 /* PREFIX_VEX_0F3A19 */
6672 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6675 /* PREFIX_VEX_0F3A1D */
6679 { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6682 /* PREFIX_VEX_0F3A20 */
6686 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6689 /* PREFIX_VEX_0F3A21 */
6693 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6696 /* PREFIX_VEX_0F3A22 */
6700 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6703 /* PREFIX_VEX_0F3A30 */
6707 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6710 /* PREFIX_VEX_0F3A31 */
6714 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6717 /* PREFIX_VEX_0F3A32 */
6721 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6724 /* PREFIX_VEX_0F3A33 */
6728 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6731 /* PREFIX_VEX_0F3A38 */
6735 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6738 /* PREFIX_VEX_0F3A39 */
6742 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6745 /* PREFIX_VEX_0F3A40 */
6749 { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6752 /* PREFIX_VEX_0F3A41 */
6756 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6759 /* PREFIX_VEX_0F3A42 */
6763 { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6766 /* PREFIX_VEX_0F3A44 */
6770 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 },
6773 /* PREFIX_VEX_0F3A46 */
6777 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6780 /* PREFIX_VEX_0F3A48 */
6784 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6787 /* PREFIX_VEX_0F3A49 */
6791 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6794 /* PREFIX_VEX_0F3A4A */
6798 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6801 /* PREFIX_VEX_0F3A4B */
6805 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6808 /* PREFIX_VEX_0F3A4C */
6812 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6815 /* PREFIX_VEX_0F3A5C */
6819 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6822 /* PREFIX_VEX_0F3A5D */
6826 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6829 /* PREFIX_VEX_0F3A5E */
6833 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6836 /* PREFIX_VEX_0F3A5F */
6840 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6843 /* PREFIX_VEX_0F3A60 */
6847 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6851 /* PREFIX_VEX_0F3A61 */
6855 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6858 /* PREFIX_VEX_0F3A62 */
6862 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6865 /* PREFIX_VEX_0F3A63 */
6869 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6872 /* PREFIX_VEX_0F3A68 */
6876 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6879 /* PREFIX_VEX_0F3A69 */
6883 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6886 /* PREFIX_VEX_0F3A6A */
6890 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6893 /* PREFIX_VEX_0F3A6B */
6897 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6900 /* PREFIX_VEX_0F3A6C */
6904 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6907 /* PREFIX_VEX_0F3A6D */
6911 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6914 /* PREFIX_VEX_0F3A6E */
6918 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6921 /* PREFIX_VEX_0F3A6F */
6925 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6928 /* PREFIX_VEX_0F3A78 */
6932 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6935 /* PREFIX_VEX_0F3A79 */
6939 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6942 /* PREFIX_VEX_0F3A7A */
6946 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6949 /* PREFIX_VEX_0F3A7B */
6953 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6956 /* PREFIX_VEX_0F3A7C */
6960 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6964 /* PREFIX_VEX_0F3A7D */
6968 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6971 /* PREFIX_VEX_0F3A7E */
6975 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6978 /* PREFIX_VEX_0F3A7F */
6982 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6985 /* PREFIX_VEX_0F3ACE */
6989 { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6992 /* PREFIX_VEX_0F3ACF */
6996 { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6999 /* PREFIX_VEX_0F3ADF */
7003 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
7006 /* PREFIX_VEX_0F3AF0 */
7011 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
7014 #define NEED_PREFIX_TABLE
7015 #include "i386-dis-evex.h"
7016 #undef NEED_PREFIX_TABLE
7019 static const struct dis386 x86_64_table[][2] = {
7022 { "pushP", { es }, 0 },
7027 { "popP", { es }, 0 },
7032 { "pushP", { cs }, 0 },
7037 { "pushP", { ss }, 0 },
7042 { "popP", { ss }, 0 },
7047 { "pushP", { ds }, 0 },
7052 { "popP", { ds }, 0 },
7057 { "daa", { XX }, 0 },
7062 { "das", { XX }, 0 },
7067 { "aaa", { XX }, 0 },
7072 { "aas", { XX }, 0 },
7077 { "pushaP", { XX }, 0 },
7082 { "popaP", { XX }, 0 },
7087 { MOD_TABLE (MOD_62_32BIT) },
7088 { EVEX_TABLE (EVEX_0F) },
7093 { "arpl", { Ew, Gw }, 0 },
7094 { "movs{lq|xd}", { Gv, Ed }, 0 },
7099 { "ins{R|}", { Yzr, indirDX }, 0 },
7100 { "ins{G|}", { Yzr, indirDX }, 0 },
7105 { "outs{R|}", { indirDXr, Xz }, 0 },
7106 { "outs{G|}", { indirDXr, Xz }, 0 },
7111 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
7112 { REG_TABLE (REG_80) },
7117 { "Jcall{T|}", { Ap }, 0 },
7122 { MOD_TABLE (MOD_C4_32BIT) },
7123 { VEX_C4_TABLE (VEX_0F) },
7128 { MOD_TABLE (MOD_C5_32BIT) },
7129 { VEX_C5_TABLE (VEX_0F) },
7134 { "into", { XX }, 0 },
7139 { "aam", { Ib }, 0 },
7144 { "aad", { Ib }, 0 },
7149 { "callP", { Jv, BND }, 0 },
7150 { "call@", { Jv, BND }, 0 }
7155 { "jmpP", { Jv, BND }, 0 },
7156 { "jmp@", { Jv, BND }, 0 }
7161 { "Jjmp{T|}", { Ap }, 0 },
7164 /* X86_64_0F01_REG_0 */
7166 { "sgdt{Q|IQ}", { M }, 0 },
7167 { "sgdt", { M }, 0 },
7170 /* X86_64_0F01_REG_1 */
7172 { "sidt{Q|IQ}", { M }, 0 },
7173 { "sidt", { M }, 0 },
7176 /* X86_64_0F01_REG_2 */
7178 { "lgdt{Q|Q}", { M }, 0 },
7179 { "lgdt", { M }, 0 },
7182 /* X86_64_0F01_REG_3 */
7184 { "lidt{Q|Q}", { M }, 0 },
7185 { "lidt", { M }, 0 },
7189 static const struct dis386 three_byte_table[][256] = {
7191 /* THREE_BYTE_0F38 */
7194 { "pshufb", { MX, EM }, PREFIX_OPCODE },
7195 { "phaddw", { MX, EM }, PREFIX_OPCODE },
7196 { "phaddd", { MX, EM }, PREFIX_OPCODE },
7197 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
7198 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
7199 { "phsubw", { MX, EM }, PREFIX_OPCODE },
7200 { "phsubd", { MX, EM }, PREFIX_OPCODE },
7201 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
7203 { "psignb", { MX, EM }, PREFIX_OPCODE },
7204 { "psignw", { MX, EM }, PREFIX_OPCODE },
7205 { "psignd", { MX, EM }, PREFIX_OPCODE },
7206 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
7212 { PREFIX_TABLE (PREFIX_0F3810) },
7216 { PREFIX_TABLE (PREFIX_0F3814) },
7217 { PREFIX_TABLE (PREFIX_0F3815) },
7219 { PREFIX_TABLE (PREFIX_0F3817) },
7225 { "pabsb", { MX, EM }, PREFIX_OPCODE },
7226 { "pabsw", { MX, EM }, PREFIX_OPCODE },
7227 { "pabsd", { MX, EM }, PREFIX_OPCODE },
7230 { PREFIX_TABLE (PREFIX_0F3820) },
7231 { PREFIX_TABLE (PREFIX_0F3821) },
7232 { PREFIX_TABLE (PREFIX_0F3822) },
7233 { PREFIX_TABLE (PREFIX_0F3823) },
7234 { PREFIX_TABLE (PREFIX_0F3824) },
7235 { PREFIX_TABLE (PREFIX_0F3825) },
7239 { PREFIX_TABLE (PREFIX_0F3828) },
7240 { PREFIX_TABLE (PREFIX_0F3829) },
7241 { PREFIX_TABLE (PREFIX_0F382A) },
7242 { PREFIX_TABLE (PREFIX_0F382B) },
7248 { PREFIX_TABLE (PREFIX_0F3830) },
7249 { PREFIX_TABLE (PREFIX_0F3831) },
7250 { PREFIX_TABLE (PREFIX_0F3832) },
7251 { PREFIX_TABLE (PREFIX_0F3833) },
7252 { PREFIX_TABLE (PREFIX_0F3834) },
7253 { PREFIX_TABLE (PREFIX_0F3835) },
7255 { PREFIX_TABLE (PREFIX_0F3837) },
7257 { PREFIX_TABLE (PREFIX_0F3838) },
7258 { PREFIX_TABLE (PREFIX_0F3839) },
7259 { PREFIX_TABLE (PREFIX_0F383A) },
7260 { PREFIX_TABLE (PREFIX_0F383B) },
7261 { PREFIX_TABLE (PREFIX_0F383C) },
7262 { PREFIX_TABLE (PREFIX_0F383D) },
7263 { PREFIX_TABLE (PREFIX_0F383E) },
7264 { PREFIX_TABLE (PREFIX_0F383F) },
7266 { PREFIX_TABLE (PREFIX_0F3840) },
7267 { PREFIX_TABLE (PREFIX_0F3841) },
7338 { PREFIX_TABLE (PREFIX_0F3880) },
7339 { PREFIX_TABLE (PREFIX_0F3881) },
7340 { PREFIX_TABLE (PREFIX_0F3882) },
7419 { PREFIX_TABLE (PREFIX_0F38C8) },
7420 { PREFIX_TABLE (PREFIX_0F38C9) },
7421 { PREFIX_TABLE (PREFIX_0F38CA) },
7422 { PREFIX_TABLE (PREFIX_0F38CB) },
7423 { PREFIX_TABLE (PREFIX_0F38CC) },
7424 { PREFIX_TABLE (PREFIX_0F38CD) },
7426 { PREFIX_TABLE (PREFIX_0F38CF) },
7440 { PREFIX_TABLE (PREFIX_0F38DB) },
7441 { PREFIX_TABLE (PREFIX_0F38DC) },
7442 { PREFIX_TABLE (PREFIX_0F38DD) },
7443 { PREFIX_TABLE (PREFIX_0F38DE) },
7444 { PREFIX_TABLE (PREFIX_0F38DF) },
7464 { PREFIX_TABLE (PREFIX_0F38F0) },
7465 { PREFIX_TABLE (PREFIX_0F38F1) },
7469 { PREFIX_TABLE (PREFIX_0F38F5) },
7470 { PREFIX_TABLE (PREFIX_0F38F6) },
7473 { PREFIX_TABLE (PREFIX_0F38F8) },
7474 { PREFIX_TABLE (PREFIX_0F38F9) },
7482 /* THREE_BYTE_0F3A */
7494 { PREFIX_TABLE (PREFIX_0F3A08) },
7495 { PREFIX_TABLE (PREFIX_0F3A09) },
7496 { PREFIX_TABLE (PREFIX_0F3A0A) },
7497 { PREFIX_TABLE (PREFIX_0F3A0B) },
7498 { PREFIX_TABLE (PREFIX_0F3A0C) },
7499 { PREFIX_TABLE (PREFIX_0F3A0D) },
7500 { PREFIX_TABLE (PREFIX_0F3A0E) },
7501 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
7507 { PREFIX_TABLE (PREFIX_0F3A14) },
7508 { PREFIX_TABLE (PREFIX_0F3A15) },
7509 { PREFIX_TABLE (PREFIX_0F3A16) },
7510 { PREFIX_TABLE (PREFIX_0F3A17) },
7521 { PREFIX_TABLE (PREFIX_0F3A20) },
7522 { PREFIX_TABLE (PREFIX_0F3A21) },
7523 { PREFIX_TABLE (PREFIX_0F3A22) },
7557 { PREFIX_TABLE (PREFIX_0F3A40) },
7558 { PREFIX_TABLE (PREFIX_0F3A41) },
7559 { PREFIX_TABLE (PREFIX_0F3A42) },
7561 { PREFIX_TABLE (PREFIX_0F3A44) },
7593 { PREFIX_TABLE (PREFIX_0F3A60) },
7594 { PREFIX_TABLE (PREFIX_0F3A61) },
7595 { PREFIX_TABLE (PREFIX_0F3A62) },
7596 { PREFIX_TABLE (PREFIX_0F3A63) },
7714 { PREFIX_TABLE (PREFIX_0F3ACC) },
7716 { PREFIX_TABLE (PREFIX_0F3ACE) },
7717 { PREFIX_TABLE (PREFIX_0F3ACF) },
7735 { PREFIX_TABLE (PREFIX_0F3ADF) },
7775 static const struct dis386 xop_table[][256] = {
7928 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7929 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7930 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7938 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7939 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7946 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7947 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7948 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7956 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7957 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7961 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7962 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7965 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7983 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7995 { "vprotb", { XM, Vex_2src_1, Ib }, 0 },
7996 { "vprotw", { XM, Vex_2src_1, Ib }, 0 },
7997 { "vprotd", { XM, Vex_2src_1, Ib }, 0 },
7998 { "vprotq", { XM, Vex_2src_1, Ib }, 0 },
8008 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
8009 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
8010 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
8011 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
8044 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8045 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8046 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8047 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8071 { REG_TABLE (REG_XOP_TBM_01) },
8072 { REG_TABLE (REG_XOP_TBM_02) },
8090 { REG_TABLE (REG_XOP_LWPCB) },
8214 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8215 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8216 { "vfrczss", { XM, EXd }, 0 },
8217 { "vfrczsd", { XM, EXq }, 0 },
8232 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8233 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8234 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8235 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8236 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8237 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8238 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8239 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8241 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8242 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8243 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8244 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8287 { "vphaddbw", { XM, EXxmm }, 0 },
8288 { "vphaddbd", { XM, EXxmm }, 0 },
8289 { "vphaddbq", { XM, EXxmm }, 0 },
8292 { "vphaddwd", { XM, EXxmm }, 0 },
8293 { "vphaddwq", { XM, EXxmm }, 0 },
8298 { "vphadddq", { XM, EXxmm }, 0 },
8305 { "vphaddubw", { XM, EXxmm }, 0 },
8306 { "vphaddubd", { XM, EXxmm }, 0 },
8307 { "vphaddubq", { XM, EXxmm }, 0 },
8310 { "vphadduwd", { XM, EXxmm }, 0 },
8311 { "vphadduwq", { XM, EXxmm }, 0 },
8316 { "vphaddudq", { XM, EXxmm }, 0 },
8323 { "vphsubbw", { XM, EXxmm }, 0 },
8324 { "vphsubwd", { XM, EXxmm }, 0 },
8325 { "vphsubdq", { XM, EXxmm }, 0 },
8379 { "bextr", { Gv, Ev, Iq }, 0 },
8381 { REG_TABLE (REG_XOP_LWP) },
8651 static const struct dis386 vex_table[][256] = {
8673 { PREFIX_TABLE (PREFIX_VEX_0F10) },
8674 { PREFIX_TABLE (PREFIX_VEX_0F11) },
8675 { PREFIX_TABLE (PREFIX_VEX_0F12) },
8676 { MOD_TABLE (MOD_VEX_0F13) },
8677 { VEX_W_TABLE (VEX_W_0F14) },
8678 { VEX_W_TABLE (VEX_W_0F15) },
8679 { PREFIX_TABLE (PREFIX_VEX_0F16) },
8680 { MOD_TABLE (MOD_VEX_0F17) },
8700 { VEX_W_TABLE (VEX_W_0F28) },
8701 { VEX_W_TABLE (VEX_W_0F29) },
8702 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8703 { MOD_TABLE (MOD_VEX_0F2B) },
8704 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8705 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8706 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8707 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F41) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F42) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F44) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F45) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F46) },
8734 { PREFIX_TABLE (PREFIX_VEX_0F47) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8745 { MOD_TABLE (MOD_VEX_0F50) },
8746 { PREFIX_TABLE (PREFIX_VEX_0F51) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F52) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F53) },
8749 { "vandpX", { XM, Vex, EXx }, 0 },
8750 { "vandnpX", { XM, Vex, EXx }, 0 },
8751 { "vorpX", { XM, Vex, EXx }, 0 },
8752 { "vxorpX", { XM, Vex, EXx }, 0 },
8754 { PREFIX_TABLE (PREFIX_VEX_0F58) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F59) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F60) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F61) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F62) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F63) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F64) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F65) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F66) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F67) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F68) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F69) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8781 { PREFIX_TABLE (PREFIX_VEX_0F70) },
8782 { REG_TABLE (REG_VEX_0F71) },
8783 { REG_TABLE (REG_VEX_0F72) },
8784 { REG_TABLE (REG_VEX_0F73) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F74) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F75) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F76) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F77) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8795 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8797 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8817 { PREFIX_TABLE (PREFIX_VEX_0F90) },
8818 { PREFIX_TABLE (PREFIX_VEX_0F91) },
8819 { PREFIX_TABLE (PREFIX_VEX_0F92) },
8820 { PREFIX_TABLE (PREFIX_VEX_0F93) },
8826 { PREFIX_TABLE (PREFIX_VEX_0F98) },
8827 { PREFIX_TABLE (PREFIX_VEX_0F99) },
8850 { REG_TABLE (REG_VEX_0FAE) },
8873 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8875 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8876 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8877 { "vshufpX", { XM, Vex, EXx, Ib }, 0 },
8889 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8890 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8891 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8892 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8893 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8894 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8895 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8896 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8898 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8899 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8900 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8901 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8902 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8903 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8904 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8905 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8907 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8908 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8909 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8910 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8911 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8912 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8913 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8914 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8916 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8917 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8918 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8919 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8920 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8921 { PREFIX_TABLE (PREFIX_VEX_0FED) },
8922 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8923 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8925 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8926 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8927 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8928 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8929 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8930 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8931 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8932 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8934 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8935 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8936 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8937 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8938 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8939 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8940 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8956 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8957 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8959 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8960 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8961 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8962 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8967 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8973 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8974 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8975 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8977 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8978 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8979 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8982 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8983 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8984 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8985 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8986 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8987 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8991 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8992 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8993 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8994 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8995 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8996 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8997 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
9001 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
9002 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
9004 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
9005 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
9006 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
9009 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
9010 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
9011 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
9012 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
9013 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
9014 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
9015 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
9024 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9046 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9047 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9081 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9082 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9103 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9105 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9108 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9109 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9110 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9111 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9114 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9115 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9117 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9118 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9119 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9120 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9121 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9122 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9123 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9124 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9132 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9135 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9136 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9137 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9138 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9139 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9140 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9141 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9142 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9150 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9151 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9153 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9154 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9155 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9156 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9157 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9158 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9159 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9160 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9178 { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
9192 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9193 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9194 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9195 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9196 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9218 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9219 { REG_TABLE (REG_VEX_0F38F3) },
9221 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9222 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9223 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9237 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9238 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9239 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9241 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9242 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9243 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9246 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9247 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9248 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9249 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9250 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9251 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9252 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9253 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9259 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9260 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9261 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9262 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9264 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9265 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9269 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9273 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9274 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9275 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9291 { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9292 { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9293 { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9294 { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9300 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9301 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9309 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9310 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9311 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9313 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9315 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9318 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9319 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9320 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9321 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9322 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9340 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9341 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9342 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9343 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9345 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9346 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9347 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9348 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9354 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9355 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9356 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9357 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9358 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9359 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9360 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9361 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9372 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9373 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9374 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9375 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9376 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9377 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9378 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9379 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9468 { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9469 { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9487 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9507 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9527 #define NEED_OPCODE_TABLE
9528 #include "i386-dis-evex.h"
9529 #undef NEED_OPCODE_TABLE
9530 static const struct dis386 vex_len_table[][2] = {
9531 /* VEX_LEN_0F10_P_1 */
9533 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9534 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9537 /* VEX_LEN_0F10_P_3 */
9539 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9540 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9543 /* VEX_LEN_0F11_P_1 */
9545 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9546 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9549 /* VEX_LEN_0F11_P_3 */
9551 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9552 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9555 /* VEX_LEN_0F12_P_0_M_0 */
9557 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9560 /* VEX_LEN_0F12_P_0_M_1 */
9562 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9565 /* VEX_LEN_0F12_P_2 */
9567 { VEX_W_TABLE (VEX_W_0F12_P_2) },
9570 /* VEX_LEN_0F13_M_0 */
9572 { VEX_W_TABLE (VEX_W_0F13_M_0) },
9575 /* VEX_LEN_0F16_P_0_M_0 */
9577 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9580 /* VEX_LEN_0F16_P_0_M_1 */
9582 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9585 /* VEX_LEN_0F16_P_2 */
9587 { VEX_W_TABLE (VEX_W_0F16_P_2) },
9590 /* VEX_LEN_0F17_M_0 */
9592 { VEX_W_TABLE (VEX_W_0F17_M_0) },
9595 /* VEX_LEN_0F2A_P_1 */
9597 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9598 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9601 /* VEX_LEN_0F2A_P_3 */
9603 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9604 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9607 /* VEX_LEN_0F2C_P_1 */
9609 { "vcvttss2si", { Gv, EXdScalar }, 0 },
9610 { "vcvttss2si", { Gv, EXdScalar }, 0 },
9613 /* VEX_LEN_0F2C_P_3 */
9615 { "vcvttsd2si", { Gv, EXqScalar }, 0 },
9616 { "vcvttsd2si", { Gv, EXqScalar }, 0 },
9619 /* VEX_LEN_0F2D_P_1 */
9621 { "vcvtss2si", { Gv, EXdScalar }, 0 },
9622 { "vcvtss2si", { Gv, EXdScalar }, 0 },
9625 /* VEX_LEN_0F2D_P_3 */
9627 { "vcvtsd2si", { Gv, EXqScalar }, 0 },
9628 { "vcvtsd2si", { Gv, EXqScalar }, 0 },
9631 /* VEX_LEN_0F2E_P_0 */
9633 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9634 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9637 /* VEX_LEN_0F2E_P_2 */
9639 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9640 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9643 /* VEX_LEN_0F2F_P_0 */
9645 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9646 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9649 /* VEX_LEN_0F2F_P_2 */
9651 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9652 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9655 /* VEX_LEN_0F41_P_0 */
9658 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9660 /* VEX_LEN_0F41_P_2 */
9663 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9665 /* VEX_LEN_0F42_P_0 */
9668 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9670 /* VEX_LEN_0F42_P_2 */
9673 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9675 /* VEX_LEN_0F44_P_0 */
9677 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9679 /* VEX_LEN_0F44_P_2 */
9681 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9683 /* VEX_LEN_0F45_P_0 */
9686 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9688 /* VEX_LEN_0F45_P_2 */
9691 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9693 /* VEX_LEN_0F46_P_0 */
9696 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9698 /* VEX_LEN_0F46_P_2 */
9701 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9703 /* VEX_LEN_0F47_P_0 */
9706 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9708 /* VEX_LEN_0F47_P_2 */
9711 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9713 /* VEX_LEN_0F4A_P_0 */
9716 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9718 /* VEX_LEN_0F4A_P_2 */
9721 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9723 /* VEX_LEN_0F4B_P_0 */
9726 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9728 /* VEX_LEN_0F4B_P_2 */
9731 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9734 /* VEX_LEN_0F51_P_1 */
9736 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9737 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9740 /* VEX_LEN_0F51_P_3 */
9742 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9743 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9746 /* VEX_LEN_0F52_P_1 */
9748 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9749 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9752 /* VEX_LEN_0F53_P_1 */
9754 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9755 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9758 /* VEX_LEN_0F58_P_1 */
9760 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9761 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9764 /* VEX_LEN_0F58_P_3 */
9766 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9767 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9770 /* VEX_LEN_0F59_P_1 */
9772 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9773 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9776 /* VEX_LEN_0F59_P_3 */
9778 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9779 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9782 /* VEX_LEN_0F5A_P_1 */
9784 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9785 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9788 /* VEX_LEN_0F5A_P_3 */
9790 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9791 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9794 /* VEX_LEN_0F5C_P_1 */
9796 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9797 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9800 /* VEX_LEN_0F5C_P_3 */
9802 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9803 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9806 /* VEX_LEN_0F5D_P_1 */
9808 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9809 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9812 /* VEX_LEN_0F5D_P_3 */
9814 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9815 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9818 /* VEX_LEN_0F5E_P_1 */
9820 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9821 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9824 /* VEX_LEN_0F5E_P_3 */
9826 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9827 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9830 /* VEX_LEN_0F5F_P_1 */
9832 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9833 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9836 /* VEX_LEN_0F5F_P_3 */
9838 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9839 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9842 /* VEX_LEN_0F6E_P_2 */
9844 { "vmovK", { XMScalar, Edq }, 0 },
9845 { "vmovK", { XMScalar, Edq }, 0 },
9848 /* VEX_LEN_0F7E_P_1 */
9850 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9853 /* VEX_LEN_0F7E_P_2 */
9855 { "vmovK", { Edq, XMScalar }, 0 },
9856 { "vmovK", { Edq, XMScalar }, 0 },
9859 /* VEX_LEN_0F90_P_0 */
9861 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9864 /* VEX_LEN_0F90_P_2 */
9866 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9869 /* VEX_LEN_0F91_P_0 */
9871 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9874 /* VEX_LEN_0F91_P_2 */
9876 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9879 /* VEX_LEN_0F92_P_0 */
9881 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9884 /* VEX_LEN_0F92_P_2 */
9886 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9889 /* VEX_LEN_0F92_P_3 */
9891 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9894 /* VEX_LEN_0F93_P_0 */
9896 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9899 /* VEX_LEN_0F93_P_2 */
9901 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9904 /* VEX_LEN_0F93_P_3 */
9906 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9909 /* VEX_LEN_0F98_P_0 */
9911 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9914 /* VEX_LEN_0F98_P_2 */
9916 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9919 /* VEX_LEN_0F99_P_0 */
9921 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9924 /* VEX_LEN_0F99_P_2 */
9926 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9929 /* VEX_LEN_0FAE_R_2_M_0 */
9931 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9934 /* VEX_LEN_0FAE_R_3_M_0 */
9936 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9939 /* VEX_LEN_0FC2_P_1 */
9941 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9942 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9945 /* VEX_LEN_0FC2_P_3 */
9947 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9948 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9951 /* VEX_LEN_0FC4_P_2 */
9953 { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9956 /* VEX_LEN_0FC5_P_2 */
9958 { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9961 /* VEX_LEN_0FD6_P_2 */
9963 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9966 /* VEX_LEN_0FF7_P_2 */
9968 { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9971 /* VEX_LEN_0F3816_P_2 */
9974 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9977 /* VEX_LEN_0F3819_P_2 */
9980 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9983 /* VEX_LEN_0F381A_P_2_M_0 */
9986 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9989 /* VEX_LEN_0F3836_P_2 */
9992 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9995 /* VEX_LEN_0F3841_P_2 */
9997 { VEX_W_TABLE (VEX_W_0F3841_P_2) },
10000 /* VEX_LEN_0F385A_P_2_M_0 */
10003 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
10006 /* VEX_LEN_0F38DB_P_2 */
10008 { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
10011 /* VEX_LEN_0F38F2_P_0 */
10013 { "andnS", { Gdq, VexGdq, Edq }, 0 },
10016 /* VEX_LEN_0F38F3_R_1_P_0 */
10018 { "blsrS", { VexGdq, Edq }, 0 },
10021 /* VEX_LEN_0F38F3_R_2_P_0 */
10023 { "blsmskS", { VexGdq, Edq }, 0 },
10026 /* VEX_LEN_0F38F3_R_3_P_0 */
10028 { "blsiS", { VexGdq, Edq }, 0 },
10031 /* VEX_LEN_0F38F5_P_0 */
10033 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
10036 /* VEX_LEN_0F38F5_P_1 */
10038 { "pextS", { Gdq, VexGdq, Edq }, 0 },
10041 /* VEX_LEN_0F38F5_P_3 */
10043 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
10046 /* VEX_LEN_0F38F6_P_3 */
10048 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
10051 /* VEX_LEN_0F38F7_P_0 */
10053 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
10056 /* VEX_LEN_0F38F7_P_1 */
10058 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
10061 /* VEX_LEN_0F38F7_P_2 */
10063 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
10066 /* VEX_LEN_0F38F7_P_3 */
10068 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
10071 /* VEX_LEN_0F3A00_P_2 */
10074 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10077 /* VEX_LEN_0F3A01_P_2 */
10080 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10083 /* VEX_LEN_0F3A06_P_2 */
10086 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10089 /* VEX_LEN_0F3A0A_P_2 */
10091 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10092 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10095 /* VEX_LEN_0F3A0B_P_2 */
10097 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10098 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10101 /* VEX_LEN_0F3A14_P_2 */
10103 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10106 /* VEX_LEN_0F3A15_P_2 */
10108 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10111 /* VEX_LEN_0F3A16_P_2 */
10113 { "vpextrK", { Edq, XM, Ib }, 0 },
10116 /* VEX_LEN_0F3A17_P_2 */
10118 { "vextractps", { Edqd, XM, Ib }, 0 },
10121 /* VEX_LEN_0F3A18_P_2 */
10124 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10127 /* VEX_LEN_0F3A19_P_2 */
10130 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10133 /* VEX_LEN_0F3A20_P_2 */
10135 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10138 /* VEX_LEN_0F3A21_P_2 */
10140 { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10143 /* VEX_LEN_0F3A22_P_2 */
10145 { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 },
10148 /* VEX_LEN_0F3A30_P_2 */
10150 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10153 /* VEX_LEN_0F3A31_P_2 */
10155 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10158 /* VEX_LEN_0F3A32_P_2 */
10160 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10163 /* VEX_LEN_0F3A33_P_2 */
10165 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10168 /* VEX_LEN_0F3A38_P_2 */
10171 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10174 /* VEX_LEN_0F3A39_P_2 */
10177 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10180 /* VEX_LEN_0F3A41_P_2 */
10182 { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10185 /* VEX_LEN_0F3A46_P_2 */
10188 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10191 /* VEX_LEN_0F3A60_P_2 */
10193 { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10196 /* VEX_LEN_0F3A61_P_2 */
10198 { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10201 /* VEX_LEN_0F3A62_P_2 */
10203 { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10206 /* VEX_LEN_0F3A63_P_2 */
10208 { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10211 /* VEX_LEN_0F3A6A_P_2 */
10213 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10216 /* VEX_LEN_0F3A6B_P_2 */
10218 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10221 /* VEX_LEN_0F3A6E_P_2 */
10223 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10226 /* VEX_LEN_0F3A6F_P_2 */
10228 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10231 /* VEX_LEN_0F3A7A_P_2 */
10233 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10236 /* VEX_LEN_0F3A7B_P_2 */
10238 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10241 /* VEX_LEN_0F3A7E_P_2 */
10243 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10246 /* VEX_LEN_0F3A7F_P_2 */
10248 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10251 /* VEX_LEN_0F3ADF_P_2 */
10253 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10256 /* VEX_LEN_0F3AF0_P_3 */
10258 { "rorxS", { Gdq, Edq, Ib }, 0 },
10261 /* VEX_LEN_0FXOP_08_CC */
10263 { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 },
10266 /* VEX_LEN_0FXOP_08_CD */
10268 { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 },
10271 /* VEX_LEN_0FXOP_08_CE */
10273 { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 },
10276 /* VEX_LEN_0FXOP_08_CF */
10278 { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 },
10281 /* VEX_LEN_0FXOP_08_EC */
10283 { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 },
10286 /* VEX_LEN_0FXOP_08_ED */
10288 { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 },
10291 /* VEX_LEN_0FXOP_08_EE */
10293 { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 },
10296 /* VEX_LEN_0FXOP_08_EF */
10298 { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 },
10301 /* VEX_LEN_0FXOP_09_80 */
10303 { "vfrczps", { XM, EXxmm }, 0 },
10304 { "vfrczps", { XM, EXymmq }, 0 },
10307 /* VEX_LEN_0FXOP_09_81 */
10309 { "vfrczpd", { XM, EXxmm }, 0 },
10310 { "vfrczpd", { XM, EXymmq }, 0 },
10314 static const struct dis386 vex_w_table[][2] = {
10316 /* VEX_W_0F10_P_0 */
10317 { "vmovups", { XM, EXx }, 0 },
10320 /* VEX_W_0F10_P_1 */
10321 { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
10324 /* VEX_W_0F10_P_2 */
10325 { "vmovupd", { XM, EXx }, 0 },
10328 /* VEX_W_0F10_P_3 */
10329 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
10332 /* VEX_W_0F11_P_0 */
10333 { "vmovups", { EXxS, XM }, 0 },
10336 /* VEX_W_0F11_P_1 */
10337 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10340 /* VEX_W_0F11_P_2 */
10341 { "vmovupd", { EXxS, XM }, 0 },
10344 /* VEX_W_0F11_P_3 */
10345 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10348 /* VEX_W_0F12_P_0_M_0 */
10349 { "vmovlps", { XM, Vex128, EXq }, 0 },
10352 /* VEX_W_0F12_P_0_M_1 */
10353 { "vmovhlps", { XM, Vex128, EXq }, 0 },
10356 /* VEX_W_0F12_P_1 */
10357 { "vmovsldup", { XM, EXx }, 0 },
10360 /* VEX_W_0F12_P_2 */
10361 { "vmovlpd", { XM, Vex128, EXq }, 0 },
10364 /* VEX_W_0F12_P_3 */
10365 { "vmovddup", { XM, EXymmq }, 0 },
10368 /* VEX_W_0F13_M_0 */
10369 { "vmovlpX", { EXq, XM }, 0 },
10373 { "vunpcklpX", { XM, Vex, EXx }, 0 },
10377 { "vunpckhpX", { XM, Vex, EXx }, 0 },
10380 /* VEX_W_0F16_P_0_M_0 */
10381 { "vmovhps", { XM, Vex128, EXq }, 0 },
10384 /* VEX_W_0F16_P_0_M_1 */
10385 { "vmovlhps", { XM, Vex128, EXq }, 0 },
10388 /* VEX_W_0F16_P_1 */
10389 { "vmovshdup", { XM, EXx }, 0 },
10392 /* VEX_W_0F16_P_2 */
10393 { "vmovhpd", { XM, Vex128, EXq }, 0 },
10396 /* VEX_W_0F17_M_0 */
10397 { "vmovhpX", { EXq, XM }, 0 },
10401 { "vmovapX", { XM, EXx }, 0 },
10405 { "vmovapX", { EXxS, XM }, 0 },
10408 /* VEX_W_0F2B_M_0 */
10409 { "vmovntpX", { Mx, XM }, 0 },
10412 /* VEX_W_0F2E_P_0 */
10413 { "vucomiss", { XMScalar, EXdScalar }, 0 },
10416 /* VEX_W_0F2E_P_2 */
10417 { "vucomisd", { XMScalar, EXqScalar }, 0 },
10420 /* VEX_W_0F2F_P_0 */
10421 { "vcomiss", { XMScalar, EXdScalar }, 0 },
10424 /* VEX_W_0F2F_P_2 */
10425 { "vcomisd", { XMScalar, EXqScalar }, 0 },
10428 /* VEX_W_0F41_P_0_LEN_1 */
10429 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10430 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10433 /* VEX_W_0F41_P_2_LEN_1 */
10434 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10435 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10438 /* VEX_W_0F42_P_0_LEN_1 */
10439 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10440 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10443 /* VEX_W_0F42_P_2_LEN_1 */
10444 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10445 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10448 /* VEX_W_0F44_P_0_LEN_0 */
10449 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10450 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10453 /* VEX_W_0F44_P_2_LEN_0 */
10454 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10455 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10458 /* VEX_W_0F45_P_0_LEN_1 */
10459 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10460 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10463 /* VEX_W_0F45_P_2_LEN_1 */
10464 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10465 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10468 /* VEX_W_0F46_P_0_LEN_1 */
10469 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10470 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10473 /* VEX_W_0F46_P_2_LEN_1 */
10474 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10475 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10478 /* VEX_W_0F47_P_0_LEN_1 */
10479 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10480 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10483 /* VEX_W_0F47_P_2_LEN_1 */
10484 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10485 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10488 /* VEX_W_0F4A_P_0_LEN_1 */
10489 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10490 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10493 /* VEX_W_0F4A_P_2_LEN_1 */
10494 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10495 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10498 /* VEX_W_0F4B_P_0_LEN_1 */
10499 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10500 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10503 /* VEX_W_0F4B_P_2_LEN_1 */
10504 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10507 /* VEX_W_0F50_M_0 */
10508 { "vmovmskpX", { Gdq, XS }, 0 },
10511 /* VEX_W_0F51_P_0 */
10512 { "vsqrtps", { XM, EXx }, 0 },
10515 /* VEX_W_0F51_P_1 */
10516 { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10519 /* VEX_W_0F51_P_2 */
10520 { "vsqrtpd", { XM, EXx }, 0 },
10523 /* VEX_W_0F51_P_3 */
10524 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10527 /* VEX_W_0F52_P_0 */
10528 { "vrsqrtps", { XM, EXx }, 0 },
10531 /* VEX_W_0F52_P_1 */
10532 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10535 /* VEX_W_0F53_P_0 */
10536 { "vrcpps", { XM, EXx }, 0 },
10539 /* VEX_W_0F53_P_1 */
10540 { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
10543 /* VEX_W_0F58_P_0 */
10544 { "vaddps", { XM, Vex, EXx }, 0 },
10547 /* VEX_W_0F58_P_1 */
10548 { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
10551 /* VEX_W_0F58_P_2 */
10552 { "vaddpd", { XM, Vex, EXx }, 0 },
10555 /* VEX_W_0F58_P_3 */
10556 { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10559 /* VEX_W_0F59_P_0 */
10560 { "vmulps", { XM, Vex, EXx }, 0 },
10563 /* VEX_W_0F59_P_1 */
10564 { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
10567 /* VEX_W_0F59_P_2 */
10568 { "vmulpd", { XM, Vex, EXx }, 0 },
10571 /* VEX_W_0F59_P_3 */
10572 { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10575 /* VEX_W_0F5A_P_0 */
10576 { "vcvtps2pd", { XM, EXxmmq }, 0 },
10579 /* VEX_W_0F5A_P_1 */
10580 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
10583 /* VEX_W_0F5A_P_3 */
10584 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
10587 /* VEX_W_0F5B_P_0 */
10588 { "vcvtdq2ps", { XM, EXx }, 0 },
10591 /* VEX_W_0F5B_P_1 */
10592 { "vcvttps2dq", { XM, EXx }, 0 },
10595 /* VEX_W_0F5B_P_2 */
10596 { "vcvtps2dq", { XM, EXx }, 0 },
10599 /* VEX_W_0F5C_P_0 */
10600 { "vsubps", { XM, Vex, EXx }, 0 },
10603 /* VEX_W_0F5C_P_1 */
10604 { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
10607 /* VEX_W_0F5C_P_2 */
10608 { "vsubpd", { XM, Vex, EXx }, 0 },
10611 /* VEX_W_0F5C_P_3 */
10612 { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10615 /* VEX_W_0F5D_P_0 */
10616 { "vminps", { XM, Vex, EXx }, 0 },
10619 /* VEX_W_0F5D_P_1 */
10620 { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
10623 /* VEX_W_0F5D_P_2 */
10624 { "vminpd", { XM, Vex, EXx }, 0 },
10627 /* VEX_W_0F5D_P_3 */
10628 { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10631 /* VEX_W_0F5E_P_0 */
10632 { "vdivps", { XM, Vex, EXx }, 0 },
10635 /* VEX_W_0F5E_P_1 */
10636 { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
10639 /* VEX_W_0F5E_P_2 */
10640 { "vdivpd", { XM, Vex, EXx }, 0 },
10643 /* VEX_W_0F5E_P_3 */
10644 { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10647 /* VEX_W_0F5F_P_0 */
10648 { "vmaxps", { XM, Vex, EXx }, 0 },
10651 /* VEX_W_0F5F_P_1 */
10652 { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
10655 /* VEX_W_0F5F_P_2 */
10656 { "vmaxpd", { XM, Vex, EXx }, 0 },
10659 /* VEX_W_0F5F_P_3 */
10660 { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10663 /* VEX_W_0F60_P_2 */
10664 { "vpunpcklbw", { XM, Vex, EXx }, 0 },
10667 /* VEX_W_0F61_P_2 */
10668 { "vpunpcklwd", { XM, Vex, EXx }, 0 },
10671 /* VEX_W_0F62_P_2 */
10672 { "vpunpckldq", { XM, Vex, EXx }, 0 },
10675 /* VEX_W_0F63_P_2 */
10676 { "vpacksswb", { XM, Vex, EXx }, 0 },
10679 /* VEX_W_0F64_P_2 */
10680 { "vpcmpgtb", { XM, Vex, EXx }, 0 },
10683 /* VEX_W_0F65_P_2 */
10684 { "vpcmpgtw", { XM, Vex, EXx }, 0 },
10687 /* VEX_W_0F66_P_2 */
10688 { "vpcmpgtd", { XM, Vex, EXx }, 0 },
10691 /* VEX_W_0F67_P_2 */
10692 { "vpackuswb", { XM, Vex, EXx }, 0 },
10695 /* VEX_W_0F68_P_2 */
10696 { "vpunpckhbw", { XM, Vex, EXx }, 0 },
10699 /* VEX_W_0F69_P_2 */
10700 { "vpunpckhwd", { XM, Vex, EXx }, 0 },
10703 /* VEX_W_0F6A_P_2 */
10704 { "vpunpckhdq", { XM, Vex, EXx }, 0 },
10707 /* VEX_W_0F6B_P_2 */
10708 { "vpackssdw", { XM, Vex, EXx }, 0 },
10711 /* VEX_W_0F6C_P_2 */
10712 { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
10715 /* VEX_W_0F6D_P_2 */
10716 { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
10719 /* VEX_W_0F6F_P_1 */
10720 { "vmovdqu", { XM, EXx }, 0 },
10723 /* VEX_W_0F6F_P_2 */
10724 { "vmovdqa", { XM, EXx }, 0 },
10727 /* VEX_W_0F70_P_1 */
10728 { "vpshufhw", { XM, EXx, Ib }, 0 },
10731 /* VEX_W_0F70_P_2 */
10732 { "vpshufd", { XM, EXx, Ib }, 0 },
10735 /* VEX_W_0F70_P_3 */
10736 { "vpshuflw", { XM, EXx, Ib }, 0 },
10739 /* VEX_W_0F71_R_2_P_2 */
10740 { "vpsrlw", { Vex, XS, Ib }, 0 },
10743 /* VEX_W_0F71_R_4_P_2 */
10744 { "vpsraw", { Vex, XS, Ib }, 0 },
10747 /* VEX_W_0F71_R_6_P_2 */
10748 { "vpsllw", { Vex, XS, Ib }, 0 },
10751 /* VEX_W_0F72_R_2_P_2 */
10752 { "vpsrld", { Vex, XS, Ib }, 0 },
10755 /* VEX_W_0F72_R_4_P_2 */
10756 { "vpsrad", { Vex, XS, Ib }, 0 },
10759 /* VEX_W_0F72_R_6_P_2 */
10760 { "vpslld", { Vex, XS, Ib }, 0 },
10763 /* VEX_W_0F73_R_2_P_2 */
10764 { "vpsrlq", { Vex, XS, Ib }, 0 },
10767 /* VEX_W_0F73_R_3_P_2 */
10768 { "vpsrldq", { Vex, XS, Ib }, 0 },
10771 /* VEX_W_0F73_R_6_P_2 */
10772 { "vpsllq", { Vex, XS, Ib }, 0 },
10775 /* VEX_W_0F73_R_7_P_2 */
10776 { "vpslldq", { Vex, XS, Ib }, 0 },
10779 /* VEX_W_0F74_P_2 */
10780 { "vpcmpeqb", { XM, Vex, EXx }, 0 },
10783 /* VEX_W_0F75_P_2 */
10784 { "vpcmpeqw", { XM, Vex, EXx }, 0 },
10787 /* VEX_W_0F76_P_2 */
10788 { "vpcmpeqd", { XM, Vex, EXx }, 0 },
10791 /* VEX_W_0F77_P_0 */
10792 { "", { VZERO }, 0 },
10795 /* VEX_W_0F7C_P_2 */
10796 { "vhaddpd", { XM, Vex, EXx }, 0 },
10799 /* VEX_W_0F7C_P_3 */
10800 { "vhaddps", { XM, Vex, EXx }, 0 },
10803 /* VEX_W_0F7D_P_2 */
10804 { "vhsubpd", { XM, Vex, EXx }, 0 },
10807 /* VEX_W_0F7D_P_3 */
10808 { "vhsubps", { XM, Vex, EXx }, 0 },
10811 /* VEX_W_0F7E_P_1 */
10812 { "vmovq", { XMScalar, EXqScalar }, 0 },
10815 /* VEX_W_0F7F_P_1 */
10816 { "vmovdqu", { EXxS, XM }, 0 },
10819 /* VEX_W_0F7F_P_2 */
10820 { "vmovdqa", { EXxS, XM }, 0 },
10823 /* VEX_W_0F90_P_0_LEN_0 */
10824 { "kmovw", { MaskG, MaskE }, 0 },
10825 { "kmovq", { MaskG, MaskE }, 0 },
10828 /* VEX_W_0F90_P_2_LEN_0 */
10829 { "kmovb", { MaskG, MaskBDE }, 0 },
10830 { "kmovd", { MaskG, MaskBDE }, 0 },
10833 /* VEX_W_0F91_P_0_LEN_0 */
10834 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10835 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10838 /* VEX_W_0F91_P_2_LEN_0 */
10839 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10840 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10843 /* VEX_W_0F92_P_0_LEN_0 */
10844 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10847 /* VEX_W_0F92_P_2_LEN_0 */
10848 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10851 /* VEX_W_0F92_P_3_LEN_0 */
10852 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10853 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10856 /* VEX_W_0F93_P_0_LEN_0 */
10857 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10860 /* VEX_W_0F93_P_2_LEN_0 */
10861 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10864 /* VEX_W_0F93_P_3_LEN_0 */
10865 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10866 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10869 /* VEX_W_0F98_P_0_LEN_0 */
10870 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10871 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10874 /* VEX_W_0F98_P_2_LEN_0 */
10875 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10876 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10879 /* VEX_W_0F99_P_0_LEN_0 */
10880 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10881 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10884 /* VEX_W_0F99_P_2_LEN_0 */
10885 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10886 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10889 /* VEX_W_0FAE_R_2_M_0 */
10890 { "vldmxcsr", { Md }, 0 },
10893 /* VEX_W_0FAE_R_3_M_0 */
10894 { "vstmxcsr", { Md }, 0 },
10897 /* VEX_W_0FC2_P_0 */
10898 { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
10901 /* VEX_W_0FC2_P_1 */
10902 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10905 /* VEX_W_0FC2_P_2 */
10906 { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
10909 /* VEX_W_0FC2_P_3 */
10910 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10913 /* VEX_W_0FC4_P_2 */
10914 { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
10917 /* VEX_W_0FC5_P_2 */
10918 { "vpextrw", { Gdq, XS, Ib }, 0 },
10921 /* VEX_W_0FD0_P_2 */
10922 { "vaddsubpd", { XM, Vex, EXx }, 0 },
10925 /* VEX_W_0FD0_P_3 */
10926 { "vaddsubps", { XM, Vex, EXx }, 0 },
10929 /* VEX_W_0FD1_P_2 */
10930 { "vpsrlw", { XM, Vex, EXxmm }, 0 },
10933 /* VEX_W_0FD2_P_2 */
10934 { "vpsrld", { XM, Vex, EXxmm }, 0 },
10937 /* VEX_W_0FD3_P_2 */
10938 { "vpsrlq", { XM, Vex, EXxmm }, 0 },
10941 /* VEX_W_0FD4_P_2 */
10942 { "vpaddq", { XM, Vex, EXx }, 0 },
10945 /* VEX_W_0FD5_P_2 */
10946 { "vpmullw", { XM, Vex, EXx }, 0 },
10949 /* VEX_W_0FD6_P_2 */
10950 { "vmovq", { EXqScalarS, XMScalar }, 0 },
10953 /* VEX_W_0FD7_P_2_M_1 */
10954 { "vpmovmskb", { Gdq, XS }, 0 },
10957 /* VEX_W_0FD8_P_2 */
10958 { "vpsubusb", { XM, Vex, EXx }, 0 },
10961 /* VEX_W_0FD9_P_2 */
10962 { "vpsubusw", { XM, Vex, EXx }, 0 },
10965 /* VEX_W_0FDA_P_2 */
10966 { "vpminub", { XM, Vex, EXx }, 0 },
10969 /* VEX_W_0FDB_P_2 */
10970 { "vpand", { XM, Vex, EXx }, 0 },
10973 /* VEX_W_0FDC_P_2 */
10974 { "vpaddusb", { XM, Vex, EXx }, 0 },
10977 /* VEX_W_0FDD_P_2 */
10978 { "vpaddusw", { XM, Vex, EXx }, 0 },
10981 /* VEX_W_0FDE_P_2 */
10982 { "vpmaxub", { XM, Vex, EXx }, 0 },
10985 /* VEX_W_0FDF_P_2 */
10986 { "vpandn", { XM, Vex, EXx }, 0 },
10989 /* VEX_W_0FE0_P_2 */
10990 { "vpavgb", { XM, Vex, EXx }, 0 },
10993 /* VEX_W_0FE1_P_2 */
10994 { "vpsraw", { XM, Vex, EXxmm }, 0 },
10997 /* VEX_W_0FE2_P_2 */
10998 { "vpsrad", { XM, Vex, EXxmm }, 0 },
11001 /* VEX_W_0FE3_P_2 */
11002 { "vpavgw", { XM, Vex, EXx }, 0 },
11005 /* VEX_W_0FE4_P_2 */
11006 { "vpmulhuw", { XM, Vex, EXx }, 0 },
11009 /* VEX_W_0FE5_P_2 */
11010 { "vpmulhw", { XM, Vex, EXx }, 0 },
11013 /* VEX_W_0FE6_P_1 */
11014 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
11017 /* VEX_W_0FE6_P_2 */
11018 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
11021 /* VEX_W_0FE6_P_3 */
11022 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
11025 /* VEX_W_0FE7_P_2_M_0 */
11026 { "vmovntdq", { Mx, XM }, 0 },
11029 /* VEX_W_0FE8_P_2 */
11030 { "vpsubsb", { XM, Vex, EXx }, 0 },
11033 /* VEX_W_0FE9_P_2 */
11034 { "vpsubsw", { XM, Vex, EXx }, 0 },
11037 /* VEX_W_0FEA_P_2 */
11038 { "vpminsw", { XM, Vex, EXx }, 0 },
11041 /* VEX_W_0FEB_P_2 */
11042 { "vpor", { XM, Vex, EXx }, 0 },
11045 /* VEX_W_0FEC_P_2 */
11046 { "vpaddsb", { XM, Vex, EXx }, 0 },
11049 /* VEX_W_0FED_P_2 */
11050 { "vpaddsw", { XM, Vex, EXx }, 0 },
11053 /* VEX_W_0FEE_P_2 */
11054 { "vpmaxsw", { XM, Vex, EXx }, 0 },
11057 /* VEX_W_0FEF_P_2 */
11058 { "vpxor", { XM, Vex, EXx }, 0 },
11061 /* VEX_W_0FF0_P_3_M_0 */
11062 { "vlddqu", { XM, M }, 0 },
11065 /* VEX_W_0FF1_P_2 */
11066 { "vpsllw", { XM, Vex, EXxmm }, 0 },
11069 /* VEX_W_0FF2_P_2 */
11070 { "vpslld", { XM, Vex, EXxmm }, 0 },
11073 /* VEX_W_0FF3_P_2 */
11074 { "vpsllq", { XM, Vex, EXxmm }, 0 },
11077 /* VEX_W_0FF4_P_2 */
11078 { "vpmuludq", { XM, Vex, EXx }, 0 },
11081 /* VEX_W_0FF5_P_2 */
11082 { "vpmaddwd", { XM, Vex, EXx }, 0 },
11085 /* VEX_W_0FF6_P_2 */
11086 { "vpsadbw", { XM, Vex, EXx }, 0 },
11089 /* VEX_W_0FF7_P_2 */
11090 { "vmaskmovdqu", { XM, XS }, 0 },
11093 /* VEX_W_0FF8_P_2 */
11094 { "vpsubb", { XM, Vex, EXx }, 0 },
11097 /* VEX_W_0FF9_P_2 */
11098 { "vpsubw", { XM, Vex, EXx }, 0 },
11101 /* VEX_W_0FFA_P_2 */
11102 { "vpsubd", { XM, Vex, EXx }, 0 },
11105 /* VEX_W_0FFB_P_2 */
11106 { "vpsubq", { XM, Vex, EXx }, 0 },
11109 /* VEX_W_0FFC_P_2 */
11110 { "vpaddb", { XM, Vex, EXx }, 0 },
11113 /* VEX_W_0FFD_P_2 */
11114 { "vpaddw", { XM, Vex, EXx }, 0 },
11117 /* VEX_W_0FFE_P_2 */
11118 { "vpaddd", { XM, Vex, EXx }, 0 },
11121 /* VEX_W_0F3800_P_2 */
11122 { "vpshufb", { XM, Vex, EXx }, 0 },
11125 /* VEX_W_0F3801_P_2 */
11126 { "vphaddw", { XM, Vex, EXx }, 0 },
11129 /* VEX_W_0F3802_P_2 */
11130 { "vphaddd", { XM, Vex, EXx }, 0 },
11133 /* VEX_W_0F3803_P_2 */
11134 { "vphaddsw", { XM, Vex, EXx }, 0 },
11137 /* VEX_W_0F3804_P_2 */
11138 { "vpmaddubsw", { XM, Vex, EXx }, 0 },
11141 /* VEX_W_0F3805_P_2 */
11142 { "vphsubw", { XM, Vex, EXx }, 0 },
11145 /* VEX_W_0F3806_P_2 */
11146 { "vphsubd", { XM, Vex, EXx }, 0 },
11149 /* VEX_W_0F3807_P_2 */
11150 { "vphsubsw", { XM, Vex, EXx }, 0 },
11153 /* VEX_W_0F3808_P_2 */
11154 { "vpsignb", { XM, Vex, EXx }, 0 },
11157 /* VEX_W_0F3809_P_2 */
11158 { "vpsignw", { XM, Vex, EXx }, 0 },
11161 /* VEX_W_0F380A_P_2 */
11162 { "vpsignd", { XM, Vex, EXx }, 0 },
11165 /* VEX_W_0F380B_P_2 */
11166 { "vpmulhrsw", { XM, Vex, EXx }, 0 },
11169 /* VEX_W_0F380C_P_2 */
11170 { "vpermilps", { XM, Vex, EXx }, 0 },
11173 /* VEX_W_0F380D_P_2 */
11174 { "vpermilpd", { XM, Vex, EXx }, 0 },
11177 /* VEX_W_0F380E_P_2 */
11178 { "vtestps", { XM, EXx }, 0 },
11181 /* VEX_W_0F380F_P_2 */
11182 { "vtestpd", { XM, EXx }, 0 },
11185 /* VEX_W_0F3816_P_2 */
11186 { "vpermps", { XM, Vex, EXx }, 0 },
11189 /* VEX_W_0F3817_P_2 */
11190 { "vptest", { XM, EXx }, 0 },
11193 /* VEX_W_0F3818_P_2 */
11194 { "vbroadcastss", { XM, EXxmm_md }, 0 },
11197 /* VEX_W_0F3819_P_2 */
11198 { "vbroadcastsd", { XM, EXxmm_mq }, 0 },
11201 /* VEX_W_0F381A_P_2_M_0 */
11202 { "vbroadcastf128", { XM, Mxmm }, 0 },
11205 /* VEX_W_0F381C_P_2 */
11206 { "vpabsb", { XM, EXx }, 0 },
11209 /* VEX_W_0F381D_P_2 */
11210 { "vpabsw", { XM, EXx }, 0 },
11213 /* VEX_W_0F381E_P_2 */
11214 { "vpabsd", { XM, EXx }, 0 },
11217 /* VEX_W_0F3820_P_2 */
11218 { "vpmovsxbw", { XM, EXxmmq }, 0 },
11221 /* VEX_W_0F3821_P_2 */
11222 { "vpmovsxbd", { XM, EXxmmqd }, 0 },
11225 /* VEX_W_0F3822_P_2 */
11226 { "vpmovsxbq", { XM, EXxmmdw }, 0 },
11229 /* VEX_W_0F3823_P_2 */
11230 { "vpmovsxwd", { XM, EXxmmq }, 0 },
11233 /* VEX_W_0F3824_P_2 */
11234 { "vpmovsxwq", { XM, EXxmmqd }, 0 },
11237 /* VEX_W_0F3825_P_2 */
11238 { "vpmovsxdq", { XM, EXxmmq }, 0 },
11241 /* VEX_W_0F3828_P_2 */
11242 { "vpmuldq", { XM, Vex, EXx }, 0 },
11245 /* VEX_W_0F3829_P_2 */
11246 { "vpcmpeqq", { XM, Vex, EXx }, 0 },
11249 /* VEX_W_0F382A_P_2_M_0 */
11250 { "vmovntdqa", { XM, Mx }, 0 },
11253 /* VEX_W_0F382B_P_2 */
11254 { "vpackusdw", { XM, Vex, EXx }, 0 },
11257 /* VEX_W_0F382C_P_2_M_0 */
11258 { "vmaskmovps", { XM, Vex, Mx }, 0 },
11261 /* VEX_W_0F382D_P_2_M_0 */
11262 { "vmaskmovpd", { XM, Vex, Mx }, 0 },
11265 /* VEX_W_0F382E_P_2_M_0 */
11266 { "vmaskmovps", { Mx, Vex, XM }, 0 },
11269 /* VEX_W_0F382F_P_2_M_0 */
11270 { "vmaskmovpd", { Mx, Vex, XM }, 0 },
11273 /* VEX_W_0F3830_P_2 */
11274 { "vpmovzxbw", { XM, EXxmmq }, 0 },
11277 /* VEX_W_0F3831_P_2 */
11278 { "vpmovzxbd", { XM, EXxmmqd }, 0 },
11281 /* VEX_W_0F3832_P_2 */
11282 { "vpmovzxbq", { XM, EXxmmdw }, 0 },
11285 /* VEX_W_0F3833_P_2 */
11286 { "vpmovzxwd", { XM, EXxmmq }, 0 },
11289 /* VEX_W_0F3834_P_2 */
11290 { "vpmovzxwq", { XM, EXxmmqd }, 0 },
11293 /* VEX_W_0F3835_P_2 */
11294 { "vpmovzxdq", { XM, EXxmmq }, 0 },
11297 /* VEX_W_0F3836_P_2 */
11298 { "vpermd", { XM, Vex, EXx }, 0 },
11301 /* VEX_W_0F3837_P_2 */
11302 { "vpcmpgtq", { XM, Vex, EXx }, 0 },
11305 /* VEX_W_0F3838_P_2 */
11306 { "vpminsb", { XM, Vex, EXx }, 0 },
11309 /* VEX_W_0F3839_P_2 */
11310 { "vpminsd", { XM, Vex, EXx }, 0 },
11313 /* VEX_W_0F383A_P_2 */
11314 { "vpminuw", { XM, Vex, EXx }, 0 },
11317 /* VEX_W_0F383B_P_2 */
11318 { "vpminud", { XM, Vex, EXx }, 0 },
11321 /* VEX_W_0F383C_P_2 */
11322 { "vpmaxsb", { XM, Vex, EXx }, 0 },
11325 /* VEX_W_0F383D_P_2 */
11326 { "vpmaxsd", { XM, Vex, EXx }, 0 },
11329 /* VEX_W_0F383E_P_2 */
11330 { "vpmaxuw", { XM, Vex, EXx }, 0 },
11333 /* VEX_W_0F383F_P_2 */
11334 { "vpmaxud", { XM, Vex, EXx }, 0 },
11337 /* VEX_W_0F3840_P_2 */
11338 { "vpmulld", { XM, Vex, EXx }, 0 },
11341 /* VEX_W_0F3841_P_2 */
11342 { "vphminposuw", { XM, EXx }, 0 },
11345 /* VEX_W_0F3846_P_2 */
11346 { "vpsravd", { XM, Vex, EXx }, 0 },
11349 /* VEX_W_0F3858_P_2 */
11350 { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11353 /* VEX_W_0F3859_P_2 */
11354 { "vpbroadcastq", { XM, EXxmm_mq }, 0 },
11357 /* VEX_W_0F385A_P_2_M_0 */
11358 { "vbroadcasti128", { XM, Mxmm }, 0 },
11361 /* VEX_W_0F3878_P_2 */
11362 { "vpbroadcastb", { XM, EXxmm_mb }, 0 },
11365 /* VEX_W_0F3879_P_2 */
11366 { "vpbroadcastw", { XM, EXxmm_mw }, 0 },
11369 /* VEX_W_0F38CF_P_2 */
11370 { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
11373 /* VEX_W_0F38DB_P_2 */
11374 { "vaesimc", { XM, EXx }, 0 },
11377 /* VEX_W_0F3A00_P_2 */
11379 { "vpermq", { XM, EXx, Ib }, 0 },
11382 /* VEX_W_0F3A01_P_2 */
11384 { "vpermpd", { XM, EXx, Ib }, 0 },
11387 /* VEX_W_0F3A02_P_2 */
11388 { "vpblendd", { XM, Vex, EXx, Ib }, 0 },
11391 /* VEX_W_0F3A04_P_2 */
11392 { "vpermilps", { XM, EXx, Ib }, 0 },
11395 /* VEX_W_0F3A05_P_2 */
11396 { "vpermilpd", { XM, EXx, Ib }, 0 },
11399 /* VEX_W_0F3A06_P_2 */
11400 { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 },
11403 /* VEX_W_0F3A08_P_2 */
11404 { "vroundps", { XM, EXx, Ib }, 0 },
11407 /* VEX_W_0F3A09_P_2 */
11408 { "vroundpd", { XM, EXx, Ib }, 0 },
11411 /* VEX_W_0F3A0A_P_2 */
11412 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11415 /* VEX_W_0F3A0B_P_2 */
11416 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11419 /* VEX_W_0F3A0C_P_2 */
11420 { "vblendps", { XM, Vex, EXx, Ib }, 0 },
11423 /* VEX_W_0F3A0D_P_2 */
11424 { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
11427 /* VEX_W_0F3A0E_P_2 */
11428 { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
11431 /* VEX_W_0F3A0F_P_2 */
11432 { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
11435 /* VEX_W_0F3A14_P_2 */
11436 { "vpextrb", { Edqb, XM, Ib }, 0 },
11439 /* VEX_W_0F3A15_P_2 */
11440 { "vpextrw", { Edqw, XM, Ib }, 0 },
11443 /* VEX_W_0F3A18_P_2 */
11444 { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 },
11447 /* VEX_W_0F3A19_P_2 */
11448 { "vextractf128", { EXxmm, XM, Ib }, 0 },
11451 /* VEX_W_0F3A20_P_2 */
11452 { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
11455 /* VEX_W_0F3A21_P_2 */
11456 { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
11459 /* VEX_W_0F3A30_P_2_LEN_0 */
11460 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11461 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11464 /* VEX_W_0F3A31_P_2_LEN_0 */
11465 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11466 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11469 /* VEX_W_0F3A32_P_2_LEN_0 */
11470 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11471 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11474 /* VEX_W_0F3A33_P_2_LEN_0 */
11475 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11476 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11479 /* VEX_W_0F3A38_P_2 */
11480 { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 },
11483 /* VEX_W_0F3A39_P_2 */
11484 { "vextracti128", { EXxmm, XM, Ib }, 0 },
11487 /* VEX_W_0F3A40_P_2 */
11488 { "vdpps", { XM, Vex, EXx, Ib }, 0 },
11491 /* VEX_W_0F3A41_P_2 */
11492 { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
11495 /* VEX_W_0F3A42_P_2 */
11496 { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
11499 /* VEX_W_0F3A46_P_2 */
11500 { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
11503 /* VEX_W_0F3A48_P_2 */
11504 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11505 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11508 /* VEX_W_0F3A49_P_2 */
11509 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11510 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11513 /* VEX_W_0F3A4A_P_2 */
11514 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 },
11517 /* VEX_W_0F3A4B_P_2 */
11518 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 },
11521 /* VEX_W_0F3A4C_P_2 */
11522 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
11525 /* VEX_W_0F3A62_P_2 */
11526 { "vpcmpistrm", { XM, EXx, Ib }, 0 },
11529 /* VEX_W_0F3A63_P_2 */
11530 { "vpcmpistri", { XM, EXx, Ib }, 0 },
11533 /* VEX_W_0F3ACE_P_2 */
11535 { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
11538 /* VEX_W_0F3ACF_P_2 */
11540 { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 },
11543 /* VEX_W_0F3ADF_P_2 */
11544 { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11546 #define NEED_VEX_W_TABLE
11547 #include "i386-dis-evex.h"
11548 #undef NEED_VEX_W_TABLE
11551 static const struct dis386 mod_table[][2] = {
11554 { "leaS", { Gv, M }, 0 },
11559 { RM_TABLE (RM_C6_REG_7) },
11564 { RM_TABLE (RM_C7_REG_7) },
11568 { "Jcall^", { indirEp }, 0 },
11572 { "Jjmp^", { indirEp }, 0 },
11575 /* MOD_0F01_REG_0 */
11576 { X86_64_TABLE (X86_64_0F01_REG_0) },
11577 { RM_TABLE (RM_0F01_REG_0) },
11580 /* MOD_0F01_REG_1 */
11581 { X86_64_TABLE (X86_64_0F01_REG_1) },
11582 { RM_TABLE (RM_0F01_REG_1) },
11585 /* MOD_0F01_REG_2 */
11586 { X86_64_TABLE (X86_64_0F01_REG_2) },
11587 { RM_TABLE (RM_0F01_REG_2) },
11590 /* MOD_0F01_REG_3 */
11591 { X86_64_TABLE (X86_64_0F01_REG_3) },
11592 { RM_TABLE (RM_0F01_REG_3) },
11595 /* MOD_0F01_REG_5 */
11596 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
11597 { RM_TABLE (RM_0F01_REG_5) },
11600 /* MOD_0F01_REG_7 */
11601 { "invlpg", { Mb }, 0 },
11602 { RM_TABLE (RM_0F01_REG_7) },
11605 /* MOD_0F12_PREFIX_0 */
11606 { "movlps", { XM, EXq }, PREFIX_OPCODE },
11607 { "movhlps", { XM, EXq }, PREFIX_OPCODE },
11611 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
11614 /* MOD_0F16_PREFIX_0 */
11615 { "movhps", { XM, EXq }, 0 },
11616 { "movlhps", { XM, EXq }, 0 },
11620 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
11623 /* MOD_0F18_REG_0 */
11624 { "prefetchnta", { Mb }, 0 },
11627 /* MOD_0F18_REG_1 */
11628 { "prefetcht0", { Mb }, 0 },
11631 /* MOD_0F18_REG_2 */
11632 { "prefetcht1", { Mb }, 0 },
11635 /* MOD_0F18_REG_3 */
11636 { "prefetcht2", { Mb }, 0 },
11639 /* MOD_0F18_REG_4 */
11640 { "nop/reserved", { Mb }, 0 },
11643 /* MOD_0F18_REG_5 */
11644 { "nop/reserved", { Mb }, 0 },
11647 /* MOD_0F18_REG_6 */
11648 { "nop/reserved", { Mb }, 0 },
11651 /* MOD_0F18_REG_7 */
11652 { "nop/reserved", { Mb }, 0 },
11655 /* MOD_0F1A_PREFIX_0 */
11656 { "bndldx", { Gbnd, Mv_bnd }, 0 },
11657 { "nopQ", { Ev }, 0 },
11660 /* MOD_0F1B_PREFIX_0 */
11661 { "bndstx", { Mv_bnd, Gbnd }, 0 },
11662 { "nopQ", { Ev }, 0 },
11665 /* MOD_0F1B_PREFIX_1 */
11666 { "bndmk", { Gbnd, Mv_bnd }, 0 },
11667 { "nopQ", { Ev }, 0 },
11670 /* MOD_0F1C_PREFIX_0 */
11671 { REG_TABLE (REG_0F1C_MOD_0) },
11672 { "nopQ", { Ev }, 0 },
11675 /* MOD_0F1E_PREFIX_1 */
11676 { "nopQ", { Ev }, 0 },
11677 { REG_TABLE (REG_0F1E_MOD_3) },
11682 { "movL", { Rd, Td }, 0 },
11687 { "movL", { Td, Rd }, 0 },
11690 /* MOD_0F2B_PREFIX_0 */
11691 {"movntps", { Mx, XM }, PREFIX_OPCODE },
11694 /* MOD_0F2B_PREFIX_1 */
11695 {"movntss", { Md, XM }, PREFIX_OPCODE },
11698 /* MOD_0F2B_PREFIX_2 */
11699 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
11702 /* MOD_0F2B_PREFIX_3 */
11703 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
11708 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
11711 /* MOD_0F71_REG_2 */
11713 { "psrlw", { MS, Ib }, 0 },
11716 /* MOD_0F71_REG_4 */
11718 { "psraw", { MS, Ib }, 0 },
11721 /* MOD_0F71_REG_6 */
11723 { "psllw", { MS, Ib }, 0 },
11726 /* MOD_0F72_REG_2 */
11728 { "psrld", { MS, Ib }, 0 },
11731 /* MOD_0F72_REG_4 */
11733 { "psrad", { MS, Ib }, 0 },
11736 /* MOD_0F72_REG_6 */
11738 { "pslld", { MS, Ib }, 0 },
11741 /* MOD_0F73_REG_2 */
11743 { "psrlq", { MS, Ib }, 0 },
11746 /* MOD_0F73_REG_3 */
11748 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11751 /* MOD_0F73_REG_6 */
11753 { "psllq", { MS, Ib }, 0 },
11756 /* MOD_0F73_REG_7 */
11758 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11761 /* MOD_0FAE_REG_0 */
11762 { "fxsave", { FXSAVE }, 0 },
11763 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11766 /* MOD_0FAE_REG_1 */
11767 { "fxrstor", { FXSAVE }, 0 },
11768 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11771 /* MOD_0FAE_REG_2 */
11772 { "ldmxcsr", { Md }, 0 },
11773 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11776 /* MOD_0FAE_REG_3 */
11777 { "stmxcsr", { Md }, 0 },
11778 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11781 /* MOD_0FAE_REG_4 */
11782 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11783 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11786 /* MOD_0FAE_REG_5 */
11787 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
11788 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
11791 /* MOD_0FAE_REG_6 */
11792 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
11793 { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
11796 /* MOD_0FAE_REG_7 */
11797 { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11798 { RM_TABLE (RM_0FAE_REG_7) },
11802 { "lssS", { Gv, Mp }, 0 },
11806 { "lfsS", { Gv, Mp }, 0 },
11810 { "lgsS", { Gv, Mp }, 0 },
11814 { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11817 /* MOD_0FC7_REG_3 */
11818 { "xrstors", { FXSAVE }, 0 },
11821 /* MOD_0FC7_REG_4 */
11822 { "xsavec", { FXSAVE }, 0 },
11825 /* MOD_0FC7_REG_5 */
11826 { "xsaves", { FXSAVE }, 0 },
11829 /* MOD_0FC7_REG_6 */
11830 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11831 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11834 /* MOD_0FC7_REG_7 */
11835 { "vmptrst", { Mq }, 0 },
11836 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11841 { "pmovmskb", { Gdq, MS }, 0 },
11844 /* MOD_0FE7_PREFIX_2 */
11845 { "movntdq", { Mx, XM }, 0 },
11848 /* MOD_0FF0_PREFIX_3 */
11849 { "lddqu", { XM, M }, 0 },
11852 /* MOD_0F382A_PREFIX_2 */
11853 { "movntdqa", { XM, Mx }, 0 },
11856 /* MOD_0F38F5_PREFIX_2 */
11857 { "wrussK", { M, Gdq }, PREFIX_OPCODE },
11860 /* MOD_0F38F6_PREFIX_0 */
11861 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
11864 /* MOD_0F38F8_PREFIX_2 */
11865 { "movdir64b", { Gva, M }, PREFIX_OPCODE },
11868 /* MOD_0F38F9_PREFIX_0 */
11869 { "movdiri", { Em, Gv }, PREFIX_OPCODE },
11873 { "bound{S|}", { Gv, Ma }, 0 },
11874 { EVEX_TABLE (EVEX_0F) },
11878 { "lesS", { Gv, Mp }, 0 },
11879 { VEX_C4_TABLE (VEX_0F) },
11883 { "ldsS", { Gv, Mp }, 0 },
11884 { VEX_C5_TABLE (VEX_0F) },
11887 /* MOD_VEX_0F12_PREFIX_0 */
11888 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11889 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11893 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11896 /* MOD_VEX_0F16_PREFIX_0 */
11897 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11898 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11902 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11906 { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11909 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11911 { "kandw", { MaskG, MaskVex, MaskR }, 0 },
11914 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11916 { "kandq", { MaskG, MaskVex, MaskR }, 0 },
11919 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11921 { "kandb", { MaskG, MaskVex, MaskR }, 0 },
11924 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11926 { "kandd", { MaskG, MaskVex, MaskR }, 0 },
11929 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11931 { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
11934 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11936 { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
11939 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11941 { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
11944 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11946 { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
11949 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11951 { "knotw", { MaskG, MaskR }, 0 },
11954 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11956 { "knotq", { MaskG, MaskR }, 0 },
11959 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11961 { "knotb", { MaskG, MaskR }, 0 },
11964 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11966 { "knotd", { MaskG, MaskR }, 0 },
11969 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11971 { "korw", { MaskG, MaskVex, MaskR }, 0 },
11974 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11976 { "korq", { MaskG, MaskVex, MaskR }, 0 },
11979 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11981 { "korb", { MaskG, MaskVex, MaskR }, 0 },
11984 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11986 { "kord", { MaskG, MaskVex, MaskR }, 0 },
11989 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11991 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
11994 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11996 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
11999 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
12001 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
12004 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
12006 { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
12009 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
12011 { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
12014 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
12016 { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
12019 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
12021 { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
12024 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
12026 { "kxord", { MaskG, MaskVex, MaskR }, 0 },
12029 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
12031 { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
12034 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
12036 { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
12039 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
12041 { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
12044 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
12046 { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
12049 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
12051 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
12054 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
12056 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
12059 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
12061 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
12066 { VEX_W_TABLE (VEX_W_0F50_M_0) },
12069 /* MOD_VEX_0F71_REG_2 */
12071 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
12074 /* MOD_VEX_0F71_REG_4 */
12076 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
12079 /* MOD_VEX_0F71_REG_6 */
12081 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
12084 /* MOD_VEX_0F72_REG_2 */
12086 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12089 /* MOD_VEX_0F72_REG_4 */
12091 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12094 /* MOD_VEX_0F72_REG_6 */
12096 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12099 /* MOD_VEX_0F73_REG_2 */
12101 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12104 /* MOD_VEX_0F73_REG_3 */
12106 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12109 /* MOD_VEX_0F73_REG_6 */
12111 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12114 /* MOD_VEX_0F73_REG_7 */
12116 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12119 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12120 { "kmovw", { Ew, MaskG }, 0 },
12124 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12125 { "kmovq", { Eq, MaskG }, 0 },
12129 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12130 { "kmovb", { Eb, MaskG }, 0 },
12134 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12135 { "kmovd", { Ed, MaskG }, 0 },
12139 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12141 { "kmovw", { MaskG, Rdq }, 0 },
12144 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12146 { "kmovb", { MaskG, Rdq }, 0 },
12149 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12151 { "kmovd", { MaskG, Rdq }, 0 },
12154 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12156 { "kmovq", { MaskG, Rdq }, 0 },
12159 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12161 { "kmovw", { Gdq, MaskR }, 0 },
12164 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12166 { "kmovb", { Gdq, MaskR }, 0 },
12169 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12171 { "kmovd", { Gdq, MaskR }, 0 },
12174 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12176 { "kmovq", { Gdq, MaskR }, 0 },
12179 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12181 { "kortestw", { MaskG, MaskR }, 0 },
12184 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12186 { "kortestq", { MaskG, MaskR }, 0 },
12189 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12191 { "kortestb", { MaskG, MaskR }, 0 },
12194 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12196 { "kortestd", { MaskG, MaskR }, 0 },
12199 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12201 { "ktestw", { MaskG, MaskR }, 0 },
12204 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12206 { "ktestq", { MaskG, MaskR }, 0 },
12209 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12211 { "ktestb", { MaskG, MaskR }, 0 },
12214 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12216 { "ktestd", { MaskG, MaskR }, 0 },
12219 /* MOD_VEX_0FAE_REG_2 */
12220 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12223 /* MOD_VEX_0FAE_REG_3 */
12224 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12227 /* MOD_VEX_0FD7_PREFIX_2 */
12229 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12232 /* MOD_VEX_0FE7_PREFIX_2 */
12233 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12236 /* MOD_VEX_0FF0_PREFIX_3 */
12237 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12240 /* MOD_VEX_0F381A_PREFIX_2 */
12241 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12244 /* MOD_VEX_0F382A_PREFIX_2 */
12245 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12248 /* MOD_VEX_0F382C_PREFIX_2 */
12249 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12252 /* MOD_VEX_0F382D_PREFIX_2 */
12253 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12256 /* MOD_VEX_0F382E_PREFIX_2 */
12257 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12260 /* MOD_VEX_0F382F_PREFIX_2 */
12261 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12264 /* MOD_VEX_0F385A_PREFIX_2 */
12265 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12268 /* MOD_VEX_0F388C_PREFIX_2 */
12269 { "vpmaskmov%LW", { XM, Vex, Mx }, 0 },
12272 /* MOD_VEX_0F388E_PREFIX_2 */
12273 { "vpmaskmov%LW", { Mx, Vex, XM }, 0 },
12276 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12278 { "kshiftrb", { MaskG, MaskR, Ib }, 0 },
12281 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12283 { "kshiftrw", { MaskG, MaskR, Ib }, 0 },
12286 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12288 { "kshiftrd", { MaskG, MaskR, Ib }, 0 },
12291 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12293 { "kshiftrq", { MaskG, MaskR, Ib }, 0 },
12296 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12298 { "kshiftlb", { MaskG, MaskR, Ib }, 0 },
12301 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12303 { "kshiftlw", { MaskG, MaskR, Ib }, 0 },
12306 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12308 { "kshiftld", { MaskG, MaskR, Ib }, 0 },
12311 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12313 { "kshiftlq", { MaskG, MaskR, Ib }, 0 },
12315 #define NEED_MOD_TABLE
12316 #include "i386-dis-evex.h"
12317 #undef NEED_MOD_TABLE
12320 static const struct dis386 rm_table[][8] = {
12323 { "xabort", { Skip_MODRM, Ib }, 0 },
12327 { "xbeginT", { Skip_MODRM, Jv }, 0 },
12330 /* RM_0F01_REG_0 */
12332 { "vmcall", { Skip_MODRM }, 0 },
12333 { "vmlaunch", { Skip_MODRM }, 0 },
12334 { "vmresume", { Skip_MODRM }, 0 },
12335 { "vmxoff", { Skip_MODRM }, 0 },
12336 { "pconfig", { Skip_MODRM }, 0 },
12339 /* RM_0F01_REG_1 */
12340 { "monitor", { { OP_Monitor, 0 } }, 0 },
12341 { "mwait", { { OP_Mwait, 0 } }, 0 },
12342 { "clac", { Skip_MODRM }, 0 },
12343 { "stac", { Skip_MODRM }, 0 },
12347 { "encls", { Skip_MODRM }, 0 },
12350 /* RM_0F01_REG_2 */
12351 { "xgetbv", { Skip_MODRM }, 0 },
12352 { "xsetbv", { Skip_MODRM }, 0 },
12355 { "vmfunc", { Skip_MODRM }, 0 },
12356 { "xend", { Skip_MODRM }, 0 },
12357 { "xtest", { Skip_MODRM }, 0 },
12358 { "enclu", { Skip_MODRM }, 0 },
12361 /* RM_0F01_REG_3 */
12362 { "vmrun", { Skip_MODRM }, 0 },
12363 { "vmmcall", { Skip_MODRM }, 0 },
12364 { "vmload", { Skip_MODRM }, 0 },
12365 { "vmsave", { Skip_MODRM }, 0 },
12366 { "stgi", { Skip_MODRM }, 0 },
12367 { "clgi", { Skip_MODRM }, 0 },
12368 { "skinit", { Skip_MODRM }, 0 },
12369 { "invlpga", { Skip_MODRM }, 0 },
12372 /* RM_0F01_REG_5 */
12373 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
12375 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
12379 { "rdpkru", { Skip_MODRM }, 0 },
12380 { "wrpkru", { Skip_MODRM }, 0 },
12383 /* RM_0F01_REG_7 */
12384 { "swapgs", { Skip_MODRM }, 0 },
12385 { "rdtscp", { Skip_MODRM }, 0 },
12386 { "monitorx", { { OP_Monitor, 0 } }, 0 },
12387 { "mwaitx", { { OP_Mwaitx, 0 } }, 0 },
12388 { "clzero", { Skip_MODRM }, 0 },
12391 /* RM_0F1E_MOD_3_REG_7 */
12392 { "nopQ", { Ev }, 0 },
12393 { "nopQ", { Ev }, 0 },
12394 { "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
12395 { "endbr32", { Skip_MODRM }, PREFIX_OPCODE },
12396 { "nopQ", { Ev }, 0 },
12397 { "nopQ", { Ev }, 0 },
12398 { "nopQ", { Ev }, 0 },
12399 { "nopQ", { Ev }, 0 },
12402 /* RM_0FAE_REG_6 */
12403 { "mfence", { Skip_MODRM }, 0 },
12406 /* RM_0FAE_REG_7 */
12407 { "sfence", { Skip_MODRM }, 0 },
12412 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12414 /* We use the high bit to indicate different name for the same
12416 #define REP_PREFIX (0xf3 | 0x100)
12417 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12418 #define XRELEASE_PREFIX (0xf3 | 0x400)
12419 #define BND_PREFIX (0xf2 | 0x400)
12420 #define NOTRACK_PREFIX (0x3e | 0x100)
12425 int newrex, i, length;
12431 last_lock_prefix = -1;
12432 last_repz_prefix = -1;
12433 last_repnz_prefix = -1;
12434 last_data_prefix = -1;
12435 last_addr_prefix = -1;
12436 last_rex_prefix = -1;
12437 last_seg_prefix = -1;
12439 active_seg_prefix = 0;
12440 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12441 all_prefixes[i] = 0;
12444 /* The maximum instruction length is 15bytes. */
12445 while (length < MAX_CODE_LENGTH - 1)
12447 FETCH_DATA (the_info, codep + 1);
12451 /* REX prefixes family. */
12468 if (address_mode == mode_64bit)
12472 last_rex_prefix = i;
12475 prefixes |= PREFIX_REPZ;
12476 last_repz_prefix = i;
12479 prefixes |= PREFIX_REPNZ;
12480 last_repnz_prefix = i;
12483 prefixes |= PREFIX_LOCK;
12484 last_lock_prefix = i;
12487 prefixes |= PREFIX_CS;
12488 last_seg_prefix = i;
12489 active_seg_prefix = PREFIX_CS;
12492 prefixes |= PREFIX_SS;
12493 last_seg_prefix = i;
12494 active_seg_prefix = PREFIX_SS;
12497 prefixes |= PREFIX_DS;
12498 last_seg_prefix = i;
12499 active_seg_prefix = PREFIX_DS;
12502 prefixes |= PREFIX_ES;
12503 last_seg_prefix = i;
12504 active_seg_prefix = PREFIX_ES;
12507 prefixes |= PREFIX_FS;
12508 last_seg_prefix = i;
12509 active_seg_prefix = PREFIX_FS;
12512 prefixes |= PREFIX_GS;
12513 last_seg_prefix = i;
12514 active_seg_prefix = PREFIX_GS;
12517 prefixes |= PREFIX_DATA;
12518 last_data_prefix = i;
12521 prefixes |= PREFIX_ADDR;
12522 last_addr_prefix = i;
12525 /* fwait is really an instruction. If there are prefixes
12526 before the fwait, they belong to the fwait, *not* to the
12527 following instruction. */
12529 if (prefixes || rex)
12531 prefixes |= PREFIX_FWAIT;
12533 /* This ensures that the previous REX prefixes are noticed
12534 as unused prefixes, as in the return case below. */
12538 prefixes = PREFIX_FWAIT;
12543 /* Rex is ignored when followed by another prefix. */
12549 if (*codep != FWAIT_OPCODE)
12550 all_prefixes[i++] = *codep;
12558 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12561 static const char *
12562 prefix_name (int pref, int sizeflag)
12564 static const char *rexes [16] =
12567 "rex.B", /* 0x41 */
12568 "rex.X", /* 0x42 */
12569 "rex.XB", /* 0x43 */
12570 "rex.R", /* 0x44 */
12571 "rex.RB", /* 0x45 */
12572 "rex.RX", /* 0x46 */
12573 "rex.RXB", /* 0x47 */
12574 "rex.W", /* 0x48 */
12575 "rex.WB", /* 0x49 */
12576 "rex.WX", /* 0x4a */
12577 "rex.WXB", /* 0x4b */
12578 "rex.WR", /* 0x4c */
12579 "rex.WRB", /* 0x4d */
12580 "rex.WRX", /* 0x4e */
12581 "rex.WRXB", /* 0x4f */
12586 /* REX prefixes family. */
12603 return rexes [pref - 0x40];
12623 return (sizeflag & DFLAG) ? "data16" : "data32";
12625 if (address_mode == mode_64bit)
12626 return (sizeflag & AFLAG) ? "addr32" : "addr64";
12628 return (sizeflag & AFLAG) ? "addr16" : "addr32";
12633 case XACQUIRE_PREFIX:
12635 case XRELEASE_PREFIX:
12639 case NOTRACK_PREFIX:
12646 static char op_out[MAX_OPERANDS][100];
12647 static int op_ad, op_index[MAX_OPERANDS];
12648 static int two_source_ops;
12649 static bfd_vma op_address[MAX_OPERANDS];
12650 static bfd_vma op_riprel[MAX_OPERANDS];
12651 static bfd_vma start_pc;
12654 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12655 * (see topic "Redundant prefixes" in the "Differences from 8086"
12656 * section of the "Virtual 8086 Mode" chapter.)
12657 * 'pc' should be the address of this instruction, it will
12658 * be used to print the target address if this is a relative jump or call
12659 * The function returns the length of this instruction in bytes.
12662 static char intel_syntax;
12663 static char intel_mnemonic = !SYSV386_COMPAT;
12664 static char open_char;
12665 static char close_char;
12666 static char separator_char;
12667 static char scale_char;
12675 static enum x86_64_isa isa64;
12677 /* Here for backwards compatibility. When gdb stops using
12678 print_insn_i386_att and print_insn_i386_intel these functions can
12679 disappear, and print_insn_i386 be merged into print_insn. */
12681 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12685 return print_insn (pc, info);
12689 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12693 return print_insn (pc, info);
12697 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12701 return print_insn (pc, info);
12705 print_i386_disassembler_options (FILE *stream)
12707 fprintf (stream, _("\n\
12708 The following i386/x86-64 specific disassembler options are supported for use\n\
12709 with the -M switch (multiple options should be separated by commas):\n"));
12711 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
12712 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
12713 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
12714 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
12715 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
12716 fprintf (stream, _(" att-mnemonic\n"
12717 " Display instruction in AT&T mnemonic\n"));
12718 fprintf (stream, _(" intel-mnemonic\n"
12719 " Display instruction in Intel mnemonic\n"));
12720 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
12721 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
12722 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
12723 fprintf (stream, _(" data32 Assume 32bit data size\n"));
12724 fprintf (stream, _(" data16 Assume 16bit data size\n"));
12725 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12726 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
12727 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
12731 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12733 /* Get a pointer to struct dis386 with a valid name. */
12735 static const struct dis386 *
12736 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12738 int vindex, vex_table_index;
12740 if (dp->name != NULL)
12743 switch (dp->op[0].bytemode)
12745 case USE_REG_TABLE:
12746 dp = ®_table[dp->op[1].bytemode][modrm.reg];
12749 case USE_MOD_TABLE:
12750 vindex = modrm.mod == 0x3 ? 1 : 0;
12751 dp = &mod_table[dp->op[1].bytemode][vindex];
12755 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12758 case USE_PREFIX_TABLE:
12761 /* The prefix in VEX is implicit. */
12762 switch (vex.prefix)
12767 case REPE_PREFIX_OPCODE:
12770 case DATA_PREFIX_OPCODE:
12773 case REPNE_PREFIX_OPCODE:
12783 int last_prefix = -1;
12786 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12787 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12789 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12791 if (last_repz_prefix > last_repnz_prefix)
12794 prefix = PREFIX_REPZ;
12795 last_prefix = last_repz_prefix;
12800 prefix = PREFIX_REPNZ;
12801 last_prefix = last_repnz_prefix;
12804 /* Check if prefix should be ignored. */
12805 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12806 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12811 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12814 prefix = PREFIX_DATA;
12815 last_prefix = last_data_prefix;
12820 used_prefixes |= prefix;
12821 all_prefixes[last_prefix] = 0;
12824 dp = &prefix_table[dp->op[1].bytemode][vindex];
12827 case USE_X86_64_TABLE:
12828 vindex = address_mode == mode_64bit ? 1 : 0;
12829 dp = &x86_64_table[dp->op[1].bytemode][vindex];
12832 case USE_3BYTE_TABLE:
12833 FETCH_DATA (info, codep + 2);
12835 dp = &three_byte_table[dp->op[1].bytemode][vindex];
12837 modrm.mod = (*codep >> 6) & 3;
12838 modrm.reg = (*codep >> 3) & 7;
12839 modrm.rm = *codep & 7;
12842 case USE_VEX_LEN_TABLE:
12846 switch (vex.length)
12859 dp = &vex_len_table[dp->op[1].bytemode][vindex];
12862 case USE_XOP_8F_TABLE:
12863 FETCH_DATA (info, codep + 3);
12864 /* All bits in the REX prefix are ignored. */
12866 rex = ~(*codep >> 5) & 0x7;
12868 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12869 switch ((*codep & 0x1f))
12875 vex_table_index = XOP_08;
12878 vex_table_index = XOP_09;
12881 vex_table_index = XOP_0A;
12885 vex.w = *codep & 0x80;
12886 if (vex.w && address_mode == mode_64bit)
12889 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12890 if (address_mode != mode_64bit)
12892 /* In 16/32-bit mode REX_B is silently ignored. */
12896 vex.length = (*codep & 0x4) ? 256 : 128;
12897 switch ((*codep & 0x3))
12902 vex.prefix = DATA_PREFIX_OPCODE;
12905 vex.prefix = REPE_PREFIX_OPCODE;
12908 vex.prefix = REPNE_PREFIX_OPCODE;
12915 dp = &xop_table[vex_table_index][vindex];
12918 FETCH_DATA (info, codep + 1);
12919 modrm.mod = (*codep >> 6) & 3;
12920 modrm.reg = (*codep >> 3) & 7;
12921 modrm.rm = *codep & 7;
12924 case USE_VEX_C4_TABLE:
12926 FETCH_DATA (info, codep + 3);
12927 /* All bits in the REX prefix are ignored. */
12929 rex = ~(*codep >> 5) & 0x7;
12930 switch ((*codep & 0x1f))
12936 vex_table_index = VEX_0F;
12939 vex_table_index = VEX_0F38;
12942 vex_table_index = VEX_0F3A;
12946 vex.w = *codep & 0x80;
12947 if (address_mode == mode_64bit)
12954 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12955 is ignored, other REX bits are 0 and the highest bit in
12956 VEX.vvvv is also ignored (but we mustn't clear it here). */
12959 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12960 vex.length = (*codep & 0x4) ? 256 : 128;
12961 switch ((*codep & 0x3))
12966 vex.prefix = DATA_PREFIX_OPCODE;
12969 vex.prefix = REPE_PREFIX_OPCODE;
12972 vex.prefix = REPNE_PREFIX_OPCODE;
12979 dp = &vex_table[vex_table_index][vindex];
12981 /* There is no MODRM byte for VEX0F 77. */
12982 if (vex_table_index != VEX_0F || vindex != 0x77)
12984 FETCH_DATA (info, codep + 1);
12985 modrm.mod = (*codep >> 6) & 3;
12986 modrm.reg = (*codep >> 3) & 7;
12987 modrm.rm = *codep & 7;
12991 case USE_VEX_C5_TABLE:
12993 FETCH_DATA (info, codep + 2);
12994 /* All bits in the REX prefix are ignored. */
12996 rex = (*codep & 0x80) ? 0 : REX_R;
12998 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
13000 vex.register_specifier = (~(*codep >> 3)) & 0xf;
13001 vex.length = (*codep & 0x4) ? 256 : 128;
13002 switch ((*codep & 0x3))
13007 vex.prefix = DATA_PREFIX_OPCODE;
13010 vex.prefix = REPE_PREFIX_OPCODE;
13013 vex.prefix = REPNE_PREFIX_OPCODE;
13020 dp = &vex_table[dp->op[1].bytemode][vindex];
13022 /* There is no MODRM byte for VEX 77. */
13023 if (vindex != 0x77)
13025 FETCH_DATA (info, codep + 1);
13026 modrm.mod = (*codep >> 6) & 3;
13027 modrm.reg = (*codep >> 3) & 7;
13028 modrm.rm = *codep & 7;
13032 case USE_VEX_W_TABLE:
13036 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
13039 case USE_EVEX_TABLE:
13040 two_source_ops = 0;
13043 FETCH_DATA (info, codep + 4);
13044 /* All bits in the REX prefix are ignored. */
13046 /* The first byte after 0x62. */
13047 rex = ~(*codep >> 5) & 0x7;
13048 vex.r = *codep & 0x10;
13049 switch ((*codep & 0xf))
13052 return &bad_opcode;
13054 vex_table_index = EVEX_0F;
13057 vex_table_index = EVEX_0F38;
13060 vex_table_index = EVEX_0F3A;
13064 /* The second byte after 0x62. */
13066 vex.w = *codep & 0x80;
13067 if (vex.w && address_mode == mode_64bit)
13070 vex.register_specifier = (~(*codep >> 3)) & 0xf;
13073 if (!(*codep & 0x4))
13074 return &bad_opcode;
13076 switch ((*codep & 0x3))
13081 vex.prefix = DATA_PREFIX_OPCODE;
13084 vex.prefix = REPE_PREFIX_OPCODE;
13087 vex.prefix = REPNE_PREFIX_OPCODE;
13091 /* The third byte after 0x62. */
13094 /* Remember the static rounding bits. */
13095 vex.ll = (*codep >> 5) & 3;
13096 vex.b = (*codep & 0x10) != 0;
13098 vex.v = *codep & 0x8;
13099 vex.mask_register_specifier = *codep & 0x7;
13100 vex.zeroing = *codep & 0x80;
13102 if (address_mode != mode_64bit)
13104 /* In 16/32-bit mode silently ignore following bits. */
13114 dp = &evex_table[vex_table_index][vindex];
13116 FETCH_DATA (info, codep + 1);
13117 modrm.mod = (*codep >> 6) & 3;
13118 modrm.reg = (*codep >> 3) & 7;
13119 modrm.rm = *codep & 7;
13121 /* Set vector length. */
13122 if (modrm.mod == 3 && vex.b)
13138 return &bad_opcode;
13151 if (dp->name != NULL)
13154 return get_valid_dis386 (dp, info);
13158 get_sib (disassemble_info *info, int sizeflag)
13160 /* If modrm.mod == 3, operand must be register. */
13162 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13166 FETCH_DATA (info, codep + 2);
13167 sib.index = (codep [1] >> 3) & 7;
13168 sib.scale = (codep [1] >> 6) & 3;
13169 sib.base = codep [1] & 7;
13174 print_insn (bfd_vma pc, disassemble_info *info)
13176 const struct dis386 *dp;
13178 char *op_txt[MAX_OPERANDS];
13180 int sizeflag, orig_sizeflag;
13182 struct dis_private priv;
13185 priv.orig_sizeflag = AFLAG | DFLAG;
13186 if ((info->mach & bfd_mach_i386_i386) != 0)
13187 address_mode = mode_32bit;
13188 else if (info->mach == bfd_mach_i386_i8086)
13190 address_mode = mode_16bit;
13191 priv.orig_sizeflag = 0;
13194 address_mode = mode_64bit;
13196 if (intel_syntax == (char) -1)
13197 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13199 for (p = info->disassembler_options; p != NULL; )
13201 if (CONST_STRNEQ (p, "amd64"))
13203 else if (CONST_STRNEQ (p, "intel64"))
13205 else if (CONST_STRNEQ (p, "x86-64"))
13207 address_mode = mode_64bit;
13208 priv.orig_sizeflag = AFLAG | DFLAG;
13210 else if (CONST_STRNEQ (p, "i386"))
13212 address_mode = mode_32bit;
13213 priv.orig_sizeflag = AFLAG | DFLAG;
13215 else if (CONST_STRNEQ (p, "i8086"))
13217 address_mode = mode_16bit;
13218 priv.orig_sizeflag = 0;
13220 else if (CONST_STRNEQ (p, "intel"))
13223 if (CONST_STRNEQ (p + 5, "-mnemonic"))
13224 intel_mnemonic = 1;
13226 else if (CONST_STRNEQ (p, "att"))
13229 if (CONST_STRNEQ (p + 3, "-mnemonic"))
13230 intel_mnemonic = 0;
13232 else if (CONST_STRNEQ (p, "addr"))
13234 if (address_mode == mode_64bit)
13236 if (p[4] == '3' && p[5] == '2')
13237 priv.orig_sizeflag &= ~AFLAG;
13238 else if (p[4] == '6' && p[5] == '4')
13239 priv.orig_sizeflag |= AFLAG;
13243 if (p[4] == '1' && p[5] == '6')
13244 priv.orig_sizeflag &= ~AFLAG;
13245 else if (p[4] == '3' && p[5] == '2')
13246 priv.orig_sizeflag |= AFLAG;
13249 else if (CONST_STRNEQ (p, "data"))
13251 if (p[4] == '1' && p[5] == '6')
13252 priv.orig_sizeflag &= ~DFLAG;
13253 else if (p[4] == '3' && p[5] == '2')
13254 priv.orig_sizeflag |= DFLAG;
13256 else if (CONST_STRNEQ (p, "suffix"))
13257 priv.orig_sizeflag |= SUFFIX_ALWAYS;
13259 p = strchr (p, ',');
13264 if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13266 (*info->fprintf_func) (info->stream,
13267 _("64-bit address is disabled"));
13273 names64 = intel_names64;
13274 names32 = intel_names32;
13275 names16 = intel_names16;
13276 names8 = intel_names8;
13277 names8rex = intel_names8rex;
13278 names_seg = intel_names_seg;
13279 names_mm = intel_names_mm;
13280 names_bnd = intel_names_bnd;
13281 names_xmm = intel_names_xmm;
13282 names_ymm = intel_names_ymm;
13283 names_zmm = intel_names_zmm;
13284 index64 = intel_index64;
13285 index32 = intel_index32;
13286 names_mask = intel_names_mask;
13287 index16 = intel_index16;
13290 separator_char = '+';
13295 names64 = att_names64;
13296 names32 = att_names32;
13297 names16 = att_names16;
13298 names8 = att_names8;
13299 names8rex = att_names8rex;
13300 names_seg = att_names_seg;
13301 names_mm = att_names_mm;
13302 names_bnd = att_names_bnd;
13303 names_xmm = att_names_xmm;
13304 names_ymm = att_names_ymm;
13305 names_zmm = att_names_zmm;
13306 index64 = att_index64;
13307 index32 = att_index32;
13308 names_mask = att_names_mask;
13309 index16 = att_index16;
13312 separator_char = ',';
13316 /* The output looks better if we put 7 bytes on a line, since that
13317 puts most long word instructions on a single line. Use 8 bytes
13319 if ((info->mach & bfd_mach_l1om) != 0)
13320 info->bytes_per_line = 8;
13322 info->bytes_per_line = 7;
13324 info->private_data = &priv;
13325 priv.max_fetched = priv.the_buffer;
13326 priv.insn_start = pc;
13329 for (i = 0; i < MAX_OPERANDS; ++i)
13337 start_codep = priv.the_buffer;
13338 codep = priv.the_buffer;
13340 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13344 /* Getting here means we tried for data but didn't get it. That
13345 means we have an incomplete instruction of some sort. Just
13346 print the first byte as a prefix or a .byte pseudo-op. */
13347 if (codep > priv.the_buffer)
13349 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13351 (*info->fprintf_func) (info->stream, "%s", name);
13354 /* Just print the first byte as a .byte instruction. */
13355 (*info->fprintf_func) (info->stream, ".byte 0x%x",
13356 (unsigned int) priv.the_buffer[0]);
13366 sizeflag = priv.orig_sizeflag;
13368 if (!ckprefix () || rex_used)
13370 /* Too many prefixes or unused REX prefixes. */
13372 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13374 (*info->fprintf_func) (info->stream, "%s%s",
13376 prefix_name (all_prefixes[i], sizeflag));
13380 insn_codep = codep;
13382 FETCH_DATA (info, codep + 1);
13383 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13385 if (((prefixes & PREFIX_FWAIT)
13386 && ((*codep < 0xd8) || (*codep > 0xdf))))
13388 /* Handle prefixes before fwait. */
13389 for (i = 0; i < fwait_prefix && all_prefixes[i];
13391 (*info->fprintf_func) (info->stream, "%s ",
13392 prefix_name (all_prefixes[i], sizeflag));
13393 (*info->fprintf_func) (info->stream, "fwait");
13397 if (*codep == 0x0f)
13399 unsigned char threebyte;
13402 FETCH_DATA (info, codep + 1);
13403 threebyte = *codep;
13404 dp = &dis386_twobyte[threebyte];
13405 need_modrm = twobyte_has_modrm[*codep];
13410 dp = &dis386[*codep];
13411 need_modrm = onebyte_has_modrm[*codep];
13415 /* Save sizeflag for printing the extra prefixes later before updating
13416 it for mnemonic and operand processing. The prefix names depend
13417 only on the address mode. */
13418 orig_sizeflag = sizeflag;
13419 if (prefixes & PREFIX_ADDR)
13421 if ((prefixes & PREFIX_DATA))
13427 FETCH_DATA (info, codep + 1);
13428 modrm.mod = (*codep >> 6) & 3;
13429 modrm.reg = (*codep >> 3) & 7;
13430 modrm.rm = *codep & 7;
13436 memset (&vex, 0, sizeof (vex));
13438 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13440 get_sib (info, sizeflag);
13441 dofloat (sizeflag);
13445 dp = get_valid_dis386 (dp, info);
13446 if (dp != NULL && putop (dp->name, sizeflag) == 0)
13448 get_sib (info, sizeflag);
13449 for (i = 0; i < MAX_OPERANDS; ++i)
13452 op_ad = MAX_OPERANDS - 1 - i;
13454 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13455 /* For EVEX instruction after the last operand masking
13456 should be printed. */
13457 if (i == 0 && vex.evex)
13459 /* Don't print {%k0}. */
13460 if (vex.mask_register_specifier)
13463 oappend (names_mask[vex.mask_register_specifier]);
13473 /* Check if the REX prefix is used. */
13474 if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13475 all_prefixes[last_rex_prefix] = 0;
13477 /* Check if the SEG prefix is used. */
13478 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13479 | PREFIX_FS | PREFIX_GS)) != 0
13480 && (used_prefixes & active_seg_prefix) != 0)
13481 all_prefixes[last_seg_prefix] = 0;
13483 /* Check if the ADDR prefix is used. */
13484 if ((prefixes & PREFIX_ADDR) != 0
13485 && (used_prefixes & PREFIX_ADDR) != 0)
13486 all_prefixes[last_addr_prefix] = 0;
13488 /* Check if the DATA prefix is used. */
13489 if ((prefixes & PREFIX_DATA) != 0
13490 && (used_prefixes & PREFIX_DATA) != 0)
13491 all_prefixes[last_data_prefix] = 0;
13493 /* Print the extra prefixes. */
13495 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13496 if (all_prefixes[i])
13499 name = prefix_name (all_prefixes[i], orig_sizeflag);
13502 prefix_length += strlen (name) + 1;
13503 (*info->fprintf_func) (info->stream, "%s ", name);
13506 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13507 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13508 used by putop and MMX/SSE operand and may be overriden by the
13509 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13511 if (dp->prefix_requirement == PREFIX_OPCODE
13512 && dp != &bad_opcode
13514 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13516 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13518 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13520 && (used_prefixes & PREFIX_DATA) == 0))))
13522 (*info->fprintf_func) (info->stream, "(bad)");
13523 return end_codep - priv.the_buffer;
13526 /* Check maximum code length. */
13527 if ((codep - start_codep) > MAX_CODE_LENGTH)
13529 (*info->fprintf_func) (info->stream, "(bad)");
13530 return MAX_CODE_LENGTH;
13533 obufp = mnemonicendp;
13534 for (i = strlen (obuf) + prefix_length; i < 6; i++)
13537 (*info->fprintf_func) (info->stream, "%s", obuf);
13539 /* The enter and bound instructions are printed with operands in the same
13540 order as the intel book; everything else is printed in reverse order. */
13541 if (intel_syntax || two_source_ops)
13545 for (i = 0; i < MAX_OPERANDS; ++i)
13546 op_txt[i] = op_out[i];
13548 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13549 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13551 op_txt[2] = op_out[3];
13552 op_txt[3] = op_out[2];
13555 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13557 op_ad = op_index[i];
13558 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13559 op_index[MAX_OPERANDS - 1 - i] = op_ad;
13560 riprel = op_riprel[i];
13561 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13562 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13567 for (i = 0; i < MAX_OPERANDS; ++i)
13568 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13572 for (i = 0; i < MAX_OPERANDS; ++i)
13576 (*info->fprintf_func) (info->stream, ",");
13577 if (op_index[i] != -1 && !op_riprel[i])
13578 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13580 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13584 for (i = 0; i < MAX_OPERANDS; i++)
13585 if (op_index[i] != -1 && op_riprel[i])
13587 (*info->fprintf_func) (info->stream, " # ");
13588 (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13589 + op_address[op_index[i]]), info);
13592 return codep - priv.the_buffer;
13595 static const char *float_mem[] = {
13670 static const unsigned char float_mem_mode[] = {
13745 #define ST { OP_ST, 0 }
13746 #define STi { OP_STi, 0 }
13748 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13749 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13750 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13751 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13752 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13753 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13754 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13755 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13756 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13758 static const struct dis386 float_reg[][8] = {
13761 { "fadd", { ST, STi }, 0 },
13762 { "fmul", { ST, STi }, 0 },
13763 { "fcom", { STi }, 0 },
13764 { "fcomp", { STi }, 0 },
13765 { "fsub", { ST, STi }, 0 },
13766 { "fsubr", { ST, STi }, 0 },
13767 { "fdiv", { ST, STi }, 0 },
13768 { "fdivr", { ST, STi }, 0 },
13772 { "fld", { STi }, 0 },
13773 { "fxch", { STi }, 0 },
13783 { "fcmovb", { ST, STi }, 0 },
13784 { "fcmove", { ST, STi }, 0 },
13785 { "fcmovbe",{ ST, STi }, 0 },
13786 { "fcmovu", { ST, STi }, 0 },
13794 { "fcmovnb",{ ST, STi }, 0 },
13795 { "fcmovne",{ ST, STi }, 0 },
13796 { "fcmovnbe",{ ST, STi }, 0 },
13797 { "fcmovnu",{ ST, STi }, 0 },
13799 { "fucomi", { ST, STi }, 0 },
13800 { "fcomi", { ST, STi }, 0 },
13805 { "fadd", { STi, ST }, 0 },
13806 { "fmul", { STi, ST }, 0 },
13809 { "fsub{!M|r}", { STi, ST }, 0 },
13810 { "fsub{M|}", { STi, ST }, 0 },
13811 { "fdiv{!M|r}", { STi, ST }, 0 },
13812 { "fdiv{M|}", { STi, ST }, 0 },
13816 { "ffree", { STi }, 0 },
13818 { "fst", { STi }, 0 },
13819 { "fstp", { STi }, 0 },
13820 { "fucom", { STi }, 0 },
13821 { "fucomp", { STi }, 0 },
13827 { "faddp", { STi, ST }, 0 },
13828 { "fmulp", { STi, ST }, 0 },
13831 { "fsub{!M|r}p", { STi, ST }, 0 },
13832 { "fsub{M|}p", { STi, ST }, 0 },
13833 { "fdiv{!M|r}p", { STi, ST }, 0 },
13834 { "fdiv{M|}p", { STi, ST }, 0 },
13838 { "ffreep", { STi }, 0 },
13843 { "fucomip", { ST, STi }, 0 },
13844 { "fcomip", { ST, STi }, 0 },
13849 static char *fgrps[][8] = {
13852 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13857 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13862 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13867 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13872 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13877 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13882 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13887 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13888 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13893 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13898 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13903 swap_operand (void)
13905 mnemonicendp[0] = '.';
13906 mnemonicendp[1] = 's';
13911 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13912 int sizeflag ATTRIBUTE_UNUSED)
13914 /* Skip mod/rm byte. */
13920 dofloat (int sizeflag)
13922 const struct dis386 *dp;
13923 unsigned char floatop;
13925 floatop = codep[-1];
13927 if (modrm.mod != 3)
13929 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13931 putop (float_mem[fp_indx], sizeflag);
13934 OP_E (float_mem_mode[fp_indx], sizeflag);
13937 /* Skip mod/rm byte. */
13941 dp = &float_reg[floatop - 0xd8][modrm.reg];
13942 if (dp->name == NULL)
13944 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13946 /* Instruction fnstsw is only one with strange arg. */
13947 if (floatop == 0xdf && codep[-1] == 0xe0)
13948 strcpy (op_out[0], names16[0]);
13952 putop (dp->name, sizeflag);
13957 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13962 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13966 /* Like oappend (below), but S is a string starting with '%'.
13967 In Intel syntax, the '%' is elided. */
13969 oappend_maybe_intel (const char *s)
13971 oappend (s + intel_syntax);
13975 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13977 oappend_maybe_intel ("%st");
13981 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13983 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13984 oappend_maybe_intel (scratchbuf);
13987 /* Capital letters in template are macros. */
13989 putop (const char *in_template, int sizeflag)
13994 unsigned int l = 0, len = 1;
13997 #define SAVE_LAST(c) \
13998 if (l < len && l < sizeof (last)) \
14003 for (p = in_template; *p; p++)
14019 while (*++p != '|')
14020 if (*p == '}' || *p == '\0')
14023 /* Fall through. */
14028 while (*++p != '}')
14039 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14043 if (l == 0 && len == 1)
14048 if (sizeflag & SUFFIX_ALWAYS)
14061 if (address_mode == mode_64bit
14062 && !(prefixes & PREFIX_ADDR))
14073 if (intel_syntax && !alt)
14075 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14077 if (sizeflag & DFLAG)
14078 *obufp++ = intel_syntax ? 'd' : 'l';
14080 *obufp++ = intel_syntax ? 'w' : 's';
14081 used_prefixes |= (prefixes & PREFIX_DATA);
14085 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14088 if (modrm.mod == 3)
14094 if (sizeflag & DFLAG)
14095 *obufp++ = intel_syntax ? 'd' : 'l';
14098 used_prefixes |= (prefixes & PREFIX_DATA);
14104 case 'E': /* For jcxz/jecxz */
14105 if (address_mode == mode_64bit)
14107 if (sizeflag & AFLAG)
14113 if (sizeflag & AFLAG)
14115 used_prefixes |= (prefixes & PREFIX_ADDR);
14120 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14122 if (sizeflag & AFLAG)
14123 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14125 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14126 used_prefixes |= (prefixes & PREFIX_ADDR);
14130 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14132 if ((rex & REX_W) || (sizeflag & DFLAG))
14136 if (!(rex & REX_W))
14137 used_prefixes |= (prefixes & PREFIX_DATA);
14142 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14143 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14145 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14148 if (prefixes & PREFIX_DS)
14167 if (l != 0 || len != 1)
14169 if (l != 1 || len != 2 || last[0] != 'X')
14174 if (!need_vex || !vex.evex)
14177 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14179 switch (vex.length)
14197 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14202 /* Fall through. */
14205 if (l != 0 || len != 1)
14213 if (sizeflag & SUFFIX_ALWAYS)
14217 if (intel_mnemonic != cond)
14221 if ((prefixes & PREFIX_FWAIT) == 0)
14224 used_prefixes |= PREFIX_FWAIT;
14230 else if (intel_syntax && (sizeflag & DFLAG))
14234 if (!(rex & REX_W))
14235 used_prefixes |= (prefixes & PREFIX_DATA);
14239 && address_mode == mode_64bit
14240 && isa64 == intel64)
14245 /* Fall through. */
14248 && address_mode == mode_64bit
14249 && ((sizeflag & DFLAG) || (rex & REX_W)))
14254 /* Fall through. */
14257 if (l == 0 && len == 1)
14262 if ((rex & REX_W) == 0
14263 && (prefixes & PREFIX_DATA))
14265 if ((sizeflag & DFLAG) == 0)
14267 used_prefixes |= (prefixes & PREFIX_DATA);
14271 if ((prefixes & PREFIX_DATA)
14273 || (sizeflag & SUFFIX_ALWAYS))
14280 if (sizeflag & DFLAG)
14284 used_prefixes |= (prefixes & PREFIX_DATA);
14290 if (l != 1 || len != 2 || last[0] != 'L')
14296 if ((prefixes & PREFIX_DATA)
14298 || (sizeflag & SUFFIX_ALWAYS))
14305 if (sizeflag & DFLAG)
14306 *obufp++ = intel_syntax ? 'd' : 'l';
14309 used_prefixes |= (prefixes & PREFIX_DATA);
14317 if (address_mode == mode_64bit
14318 && ((sizeflag & DFLAG) || (rex & REX_W)))
14320 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14324 /* Fall through. */
14327 if (l == 0 && len == 1)
14330 if (intel_syntax && !alt)
14333 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14339 if (sizeflag & DFLAG)
14340 *obufp++ = intel_syntax ? 'd' : 'l';
14343 used_prefixes |= (prefixes & PREFIX_DATA);
14349 if (l != 1 || len != 2 || last[0] != 'L')
14355 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14370 else if (sizeflag & DFLAG)
14379 if (intel_syntax && !p[1]
14380 && ((rex & REX_W) || (sizeflag & DFLAG)))
14382 if (!(rex & REX_W))
14383 used_prefixes |= (prefixes & PREFIX_DATA);
14386 if (l == 0 && len == 1)
14390 if (address_mode == mode_64bit
14391 && ((sizeflag & DFLAG) || (rex & REX_W)))
14393 if (sizeflag & SUFFIX_ALWAYS)
14415 /* Fall through. */
14418 if (l == 0 && len == 1)
14423 if (sizeflag & SUFFIX_ALWAYS)
14429 if (sizeflag & DFLAG)
14433 used_prefixes |= (prefixes & PREFIX_DATA);
14447 if (address_mode == mode_64bit
14448 && !(prefixes & PREFIX_ADDR))
14459 if (l != 0 || len != 1)
14464 if (need_vex && vex.prefix)
14466 if (vex.prefix == DATA_PREFIX_OPCODE)
14473 if (prefixes & PREFIX_DATA)
14477 used_prefixes |= (prefixes & PREFIX_DATA);
14481 if (l == 0 && len == 1)
14485 if (l != 1 || len != 2 || last[0] != 'X')
14493 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14495 switch (vex.length)
14511 if (l == 0 && len == 1)
14513 /* operand size flag for cwtl, cbtw */
14522 else if (sizeflag & DFLAG)
14526 if (!(rex & REX_W))
14527 used_prefixes |= (prefixes & PREFIX_DATA);
14534 && last[0] != 'L'))
14541 if (last[0] == 'X')
14542 *obufp++ = vex.w ? 'd': 's';
14544 *obufp++ = vex.w ? 'q': 'd';
14550 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14552 if (sizeflag & DFLAG)
14556 used_prefixes |= (prefixes & PREFIX_DATA);
14562 if (address_mode == mode_64bit
14563 && (isa64 == intel64
14564 || ((sizeflag & DFLAG) || (rex & REX_W))))
14566 else if ((prefixes & PREFIX_DATA))
14568 if (!(sizeflag & DFLAG))
14570 used_prefixes |= (prefixes & PREFIX_DATA);
14577 mnemonicendp = obufp;
14582 oappend (const char *s)
14584 obufp = stpcpy (obufp, s);
14590 /* Only print the active segment register. */
14591 if (!active_seg_prefix)
14594 used_prefixes |= active_seg_prefix;
14595 switch (active_seg_prefix)
14598 oappend_maybe_intel ("%cs:");
14601 oappend_maybe_intel ("%ds:");
14604 oappend_maybe_intel ("%ss:");
14607 oappend_maybe_intel ("%es:");
14610 oappend_maybe_intel ("%fs:");
14613 oappend_maybe_intel ("%gs:");
14621 OP_indirE (int bytemode, int sizeflag)
14625 OP_E (bytemode, sizeflag);
14629 print_operand_value (char *buf, int hex, bfd_vma disp)
14631 if (address_mode == mode_64bit)
14639 sprintf_vma (tmp, disp);
14640 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14641 strcpy (buf + 2, tmp + i);
14645 bfd_signed_vma v = disp;
14652 /* Check for possible overflow on 0x8000000000000000. */
14655 strcpy (buf, "9223372036854775808");
14669 tmp[28 - i] = (v % 10) + '0';
14673 strcpy (buf, tmp + 29 - i);
14679 sprintf (buf, "0x%x", (unsigned int) disp);
14681 sprintf (buf, "%d", (int) disp);
14685 /* Put DISP in BUF as signed hex number. */
14688 print_displacement (char *buf, bfd_vma disp)
14690 bfd_signed_vma val = disp;
14699 /* Check for possible overflow. */
14702 switch (address_mode)
14705 strcpy (buf + j, "0x8000000000000000");
14708 strcpy (buf + j, "0x80000000");
14711 strcpy (buf + j, "0x8000");
14721 sprintf_vma (tmp, (bfd_vma) val);
14722 for (i = 0; tmp[i] == '0'; i++)
14724 if (tmp[i] == '\0')
14726 strcpy (buf + j, tmp + i);
14730 intel_operand_size (int bytemode, int sizeflag)
14734 && (bytemode == x_mode
14735 || bytemode == evex_half_bcst_xmmq_mode))
14738 oappend ("QWORD PTR ");
14740 oappend ("DWORD PTR ");
14749 oappend ("BYTE PTR ");
14754 oappend ("WORD PTR ");
14757 if (address_mode == mode_64bit && isa64 == intel64)
14759 oappend ("QWORD PTR ");
14762 /* Fall through. */
14764 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14766 oappend ("QWORD PTR ");
14769 /* Fall through. */
14775 oappend ("QWORD PTR ");
14778 if ((sizeflag & DFLAG) || bytemode == dq_mode)
14779 oappend ("DWORD PTR ");
14781 oappend ("WORD PTR ");
14782 used_prefixes |= (prefixes & PREFIX_DATA);
14786 if ((rex & REX_W) || (sizeflag & DFLAG))
14788 oappend ("WORD PTR ");
14789 if (!(rex & REX_W))
14790 used_prefixes |= (prefixes & PREFIX_DATA);
14793 if (sizeflag & DFLAG)
14794 oappend ("QWORD PTR ");
14796 oappend ("DWORD PTR ");
14797 used_prefixes |= (prefixes & PREFIX_DATA);
14800 case d_scalar_mode:
14801 case d_scalar_swap_mode:
14804 oappend ("DWORD PTR ");
14807 case q_scalar_mode:
14808 case q_scalar_swap_mode:
14810 oappend ("QWORD PTR ");
14814 if (address_mode == mode_64bit)
14815 oappend ("QWORD PTR ");
14817 oappend ("DWORD PTR ");
14820 if (sizeflag & DFLAG)
14821 oappend ("FWORD PTR ");
14823 oappend ("DWORD PTR ");
14824 used_prefixes |= (prefixes & PREFIX_DATA);
14827 oappend ("TBYTE PTR ");
14831 case evex_x_gscat_mode:
14832 case evex_x_nobcst_mode:
14833 case b_scalar_mode:
14834 case w_scalar_mode:
14837 switch (vex.length)
14840 oappend ("XMMWORD PTR ");
14843 oappend ("YMMWORD PTR ");
14846 oappend ("ZMMWORD PTR ");
14853 oappend ("XMMWORD PTR ");
14856 oappend ("XMMWORD PTR ");
14859 oappend ("YMMWORD PTR ");
14862 case evex_half_bcst_xmmq_mode:
14866 switch (vex.length)
14869 oappend ("QWORD PTR ");
14872 oappend ("XMMWORD PTR ");
14875 oappend ("YMMWORD PTR ");
14885 switch (vex.length)
14890 oappend ("BYTE PTR ");
14900 switch (vex.length)
14905 oappend ("WORD PTR ");
14915 switch (vex.length)
14920 oappend ("DWORD PTR ");
14930 switch (vex.length)
14935 oappend ("QWORD PTR ");
14945 switch (vex.length)
14948 oappend ("WORD PTR ");
14951 oappend ("DWORD PTR ");
14954 oappend ("QWORD PTR ");
14964 switch (vex.length)
14967 oappend ("DWORD PTR ");
14970 oappend ("QWORD PTR ");
14973 oappend ("XMMWORD PTR ");
14983 switch (vex.length)
14986 oappend ("QWORD PTR ");
14989 oappend ("YMMWORD PTR ");
14992 oappend ("ZMMWORD PTR ");
15002 switch (vex.length)
15006 oappend ("XMMWORD PTR ");
15013 oappend ("OWORD PTR ");
15016 case vex_w_dq_mode:
15017 case vex_scalar_w_dq_mode:
15022 oappend ("QWORD PTR ");
15024 oappend ("DWORD PTR ");
15026 case vex_vsib_d_w_dq_mode:
15027 case vex_vsib_q_w_dq_mode:
15034 oappend ("QWORD PTR ");
15036 oappend ("DWORD PTR ");
15040 switch (vex.length)
15043 oappend ("XMMWORD PTR ");
15046 oappend ("YMMWORD PTR ");
15049 oappend ("ZMMWORD PTR ");
15056 case vex_vsib_q_w_d_mode:
15057 case vex_vsib_d_w_d_mode:
15058 if (!need_vex || !vex.evex)
15061 switch (vex.length)
15064 oappend ("QWORD PTR ");
15067 oappend ("XMMWORD PTR ");
15070 oappend ("YMMWORD PTR ");
15078 if (!need_vex || vex.length != 128)
15081 oappend ("DWORD PTR ");
15083 oappend ("BYTE PTR ");
15089 oappend ("QWORD PTR ");
15091 oappend ("WORD PTR ");
15101 OP_E_register (int bytemode, int sizeflag)
15103 int reg = modrm.rm;
15104 const char **names;
15110 if ((sizeflag & SUFFIX_ALWAYS)
15111 && (bytemode == b_swap_mode
15112 || bytemode == bnd_swap_mode
15113 || bytemode == v_swap_mode))
15139 names = address_mode == mode_64bit ? names64 : names32;
15142 case bnd_swap_mode:
15151 if (address_mode == mode_64bit && isa64 == intel64)
15156 /* Fall through. */
15158 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15164 /* Fall through. */
15177 if ((sizeflag & DFLAG)
15178 || (bytemode != v_mode
15179 && bytemode != v_swap_mode))
15183 used_prefixes |= (prefixes & PREFIX_DATA);
15187 names = (address_mode == mode_64bit
15188 ? names64 : names32);
15189 if (!(prefixes & PREFIX_ADDR))
15190 names = (address_mode == mode_16bit
15191 ? names16 : names);
15194 /* Remove "addr16/addr32". */
15195 all_prefixes[last_addr_prefix] = 0;
15196 names = (address_mode != mode_32bit
15197 ? names32 : names16);
15198 used_prefixes |= PREFIX_ADDR;
15208 names = names_mask;
15213 oappend (INTERNAL_DISASSEMBLER_ERROR);
15216 oappend (names[reg]);
15220 OP_E_memory (int bytemode, int sizeflag)
15223 int add = (rex & REX_B) ? 8 : 0;
15229 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
15231 && bytemode != x_mode
15232 && bytemode != xmmq_mode
15233 && bytemode != evex_half_bcst_xmmq_mode)
15248 case vex_vsib_d_w_dq_mode:
15249 case vex_vsib_d_w_d_mode:
15250 case vex_vsib_q_w_dq_mode:
15251 case vex_vsib_q_w_d_mode:
15252 case evex_x_gscat_mode:
15254 shift = vex.w ? 3 : 2;
15257 case evex_half_bcst_xmmq_mode:
15261 shift = vex.w ? 3 : 2;
15264 /* Fall through. */
15268 case evex_x_nobcst_mode:
15270 switch (vex.length)
15293 case q_scalar_mode:
15295 case q_scalar_swap_mode:
15301 case d_scalar_mode:
15303 case d_scalar_swap_mode:
15306 case w_scalar_mode:
15310 case b_scalar_mode:
15315 shift = address_mode == mode_64bit ? 3 : 2;
15320 /* Make necessary corrections to shift for modes that need it.
15321 For these modes we currently have shift 4, 5 or 6 depending on
15322 vex.length (it corresponds to xmmword, ymmword or zmmword
15323 operand). We might want to make it 3, 4 or 5 (e.g. for
15324 xmmq_mode). In case of broadcast enabled the corrections
15325 aren't needed, as element size is always 32 or 64 bits. */
15327 && (bytemode == xmmq_mode
15328 || bytemode == evex_half_bcst_xmmq_mode))
15330 else if (bytemode == xmmqd_mode)
15332 else if (bytemode == xmmdw_mode)
15334 else if (bytemode == ymmq_mode && vex.length == 128)
15342 intel_operand_size (bytemode, sizeflag);
15345 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15347 /* 32/64 bit address mode */
15357 int addr32flag = !((sizeflag & AFLAG)
15358 || bytemode == v_bnd_mode
15359 || bytemode == v_bndmk_mode
15360 || bytemode == bnd_mode
15361 || bytemode == bnd_swap_mode);
15362 const char **indexes64 = names64;
15363 const char **indexes32 = names32;
15373 vindex = sib.index;
15379 case vex_vsib_d_w_dq_mode:
15380 case vex_vsib_d_w_d_mode:
15381 case vex_vsib_q_w_dq_mode:
15382 case vex_vsib_q_w_d_mode:
15392 switch (vex.length)
15395 indexes64 = indexes32 = names_xmm;
15399 || bytemode == vex_vsib_q_w_dq_mode
15400 || bytemode == vex_vsib_q_w_d_mode)
15401 indexes64 = indexes32 = names_ymm;
15403 indexes64 = indexes32 = names_xmm;
15407 || bytemode == vex_vsib_q_w_dq_mode
15408 || bytemode == vex_vsib_q_w_d_mode)
15409 indexes64 = indexes32 = names_zmm;
15411 indexes64 = indexes32 = names_ymm;
15418 haveindex = vindex != 4;
15425 rbase = base + add;
15433 if (address_mode == mode_64bit && !havesib)
15436 if (riprel && bytemode == v_bndmk_mode)
15444 FETCH_DATA (the_info, codep + 1);
15446 if ((disp & 0x80) != 0)
15448 if (vex.evex && shift > 0)
15461 && address_mode != mode_16bit)
15463 if (address_mode == mode_64bit)
15465 /* Display eiz instead of addr32. */
15466 needindex = addr32flag;
15471 /* In 32-bit mode, we need index register to tell [offset]
15472 from [eiz*1 + offset]. */
15477 havedisp = (havebase
15479 || (havesib && (haveindex || scale != 0)));
15482 if (modrm.mod != 0 || base == 5)
15484 if (havedisp || riprel)
15485 print_displacement (scratchbuf, disp);
15487 print_operand_value (scratchbuf, 1, disp);
15488 oappend (scratchbuf);
15492 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15496 if ((havebase || haveindex || needaddr32 || riprel)
15497 && (bytemode != v_bnd_mode)
15498 && (bytemode != v_bndmk_mode)
15499 && (bytemode != bnd_mode)
15500 && (bytemode != bnd_swap_mode))
15501 used_prefixes |= PREFIX_ADDR;
15503 if (havedisp || (intel_syntax && riprel))
15505 *obufp++ = open_char;
15506 if (intel_syntax && riprel)
15509 oappend (!addr32flag ? "rip" : "eip");
15513 oappend (address_mode == mode_64bit && !addr32flag
15514 ? names64[rbase] : names32[rbase]);
15517 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15518 print index to tell base + index from base. */
15522 || (havebase && base != ESP_REG_NUM))
15524 if (!intel_syntax || havebase)
15526 *obufp++ = separator_char;
15530 oappend (address_mode == mode_64bit && !addr32flag
15531 ? indexes64[vindex] : indexes32[vindex]);
15533 oappend (address_mode == mode_64bit && !addr32flag
15534 ? index64 : index32);
15536 *obufp++ = scale_char;
15538 sprintf (scratchbuf, "%d", 1 << scale);
15539 oappend (scratchbuf);
15543 && (disp || modrm.mod != 0 || base == 5))
15545 if (!havedisp || (bfd_signed_vma) disp >= 0)
15550 else if (modrm.mod != 1 && disp != -disp)
15554 disp = - (bfd_signed_vma) disp;
15558 print_displacement (scratchbuf, disp);
15560 print_operand_value (scratchbuf, 1, disp);
15561 oappend (scratchbuf);
15564 *obufp++ = close_char;
15567 else if (intel_syntax)
15569 if (modrm.mod != 0 || base == 5)
15571 if (!active_seg_prefix)
15573 oappend (names_seg[ds_reg - es_reg]);
15576 print_operand_value (scratchbuf, 1, disp);
15577 oappend (scratchbuf);
15583 /* 16 bit address mode */
15584 used_prefixes |= prefixes & PREFIX_ADDR;
15591 if ((disp & 0x8000) != 0)
15596 FETCH_DATA (the_info, codep + 1);
15598 if ((disp & 0x80) != 0)
15600 if (vex.evex && shift > 0)
15605 if ((disp & 0x8000) != 0)
15611 if (modrm.mod != 0 || modrm.rm == 6)
15613 print_displacement (scratchbuf, disp);
15614 oappend (scratchbuf);
15617 if (modrm.mod != 0 || modrm.rm != 6)
15619 *obufp++ = open_char;
15621 oappend (index16[modrm.rm]);
15623 && (disp || modrm.mod != 0 || modrm.rm == 6))
15625 if ((bfd_signed_vma) disp >= 0)
15630 else if (modrm.mod != 1)
15634 disp = - (bfd_signed_vma) disp;
15637 print_displacement (scratchbuf, disp);
15638 oappend (scratchbuf);
15641 *obufp++ = close_char;
15644 else if (intel_syntax)
15646 if (!active_seg_prefix)
15648 oappend (names_seg[ds_reg - es_reg]);
15651 print_operand_value (scratchbuf, 1, disp & 0xffff);
15652 oappend (scratchbuf);
15655 if (vex.evex && vex.b
15656 && (bytemode == x_mode
15657 || bytemode == xmmq_mode
15658 || bytemode == evex_half_bcst_xmmq_mode))
15661 || bytemode == xmmq_mode
15662 || bytemode == evex_half_bcst_xmmq_mode)
15664 switch (vex.length)
15667 oappend ("{1to2}");
15670 oappend ("{1to4}");
15673 oappend ("{1to8}");
15681 switch (vex.length)
15684 oappend ("{1to4}");
15687 oappend ("{1to8}");
15690 oappend ("{1to16}");
15700 OP_E (int bytemode, int sizeflag)
15702 /* Skip mod/rm byte. */
15706 if (modrm.mod == 3)
15707 OP_E_register (bytemode, sizeflag);
15709 OP_E_memory (bytemode, sizeflag);
15713 OP_G (int bytemode, int sizeflag)
15716 const char **names;
15725 oappend (names8rex[modrm.reg + add]);
15727 oappend (names8[modrm.reg + add]);
15730 oappend (names16[modrm.reg + add]);
15735 oappend (names32[modrm.reg + add]);
15738 oappend (names64[modrm.reg + add]);
15741 if (modrm.reg > 0x3)
15746 oappend (names_bnd[modrm.reg]);
15755 oappend (names64[modrm.reg + add]);
15758 if ((sizeflag & DFLAG) || bytemode != v_mode)
15759 oappend (names32[modrm.reg + add]);
15761 oappend (names16[modrm.reg + add]);
15762 used_prefixes |= (prefixes & PREFIX_DATA);
15766 names = (address_mode == mode_64bit
15767 ? names64 : names32);
15768 if (!(prefixes & PREFIX_ADDR))
15770 if (address_mode == mode_16bit)
15775 /* Remove "addr16/addr32". */
15776 all_prefixes[last_addr_prefix] = 0;
15777 names = (address_mode != mode_32bit
15778 ? names32 : names16);
15779 used_prefixes |= PREFIX_ADDR;
15781 oappend (names[modrm.reg + add]);
15784 if (address_mode == mode_64bit)
15785 oappend (names64[modrm.reg + add]);
15787 oappend (names32[modrm.reg + add]);
15791 if ((modrm.reg + add) > 0x7)
15796 oappend (names_mask[modrm.reg + add]);
15799 oappend (INTERNAL_DISASSEMBLER_ERROR);
15812 FETCH_DATA (the_info, codep + 8);
15813 a = *codep++ & 0xff;
15814 a |= (*codep++ & 0xff) << 8;
15815 a |= (*codep++ & 0xff) << 16;
15816 a |= (*codep++ & 0xffu) << 24;
15817 b = *codep++ & 0xff;
15818 b |= (*codep++ & 0xff) << 8;
15819 b |= (*codep++ & 0xff) << 16;
15820 b |= (*codep++ & 0xffu) << 24;
15821 x = a + ((bfd_vma) b << 32);
15829 static bfd_signed_vma
15832 bfd_signed_vma x = 0;
15834 FETCH_DATA (the_info, codep + 4);
15835 x = *codep++ & (bfd_signed_vma) 0xff;
15836 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15837 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15838 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15842 static bfd_signed_vma
15845 bfd_signed_vma x = 0;
15847 FETCH_DATA (the_info, codep + 4);
15848 x = *codep++ & (bfd_signed_vma) 0xff;
15849 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15850 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15851 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15853 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15863 FETCH_DATA (the_info, codep + 2);
15864 x = *codep++ & 0xff;
15865 x |= (*codep++ & 0xff) << 8;
15870 set_op (bfd_vma op, int riprel)
15872 op_index[op_ad] = op_ad;
15873 if (address_mode == mode_64bit)
15875 op_address[op_ad] = op;
15876 op_riprel[op_ad] = riprel;
15880 /* Mask to get a 32-bit address. */
15881 op_address[op_ad] = op & 0xffffffff;
15882 op_riprel[op_ad] = riprel & 0xffffffff;
15887 OP_REG (int code, int sizeflag)
15894 case es_reg: case ss_reg: case cs_reg:
15895 case ds_reg: case fs_reg: case gs_reg:
15896 oappend (names_seg[code - es_reg]);
15908 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15909 case sp_reg: case bp_reg: case si_reg: case di_reg:
15910 s = names16[code - ax_reg + add];
15912 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15913 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15916 s = names8rex[code - al_reg + add];
15918 s = names8[code - al_reg];
15920 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15921 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15922 if (address_mode == mode_64bit
15923 && ((sizeflag & DFLAG) || (rex & REX_W)))
15925 s = names64[code - rAX_reg + add];
15928 code += eAX_reg - rAX_reg;
15929 /* Fall through. */
15930 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15931 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15934 s = names64[code - eAX_reg + add];
15937 if (sizeflag & DFLAG)
15938 s = names32[code - eAX_reg + add];
15940 s = names16[code - eAX_reg + add];
15941 used_prefixes |= (prefixes & PREFIX_DATA);
15945 s = INTERNAL_DISASSEMBLER_ERROR;
15952 OP_IMREG (int code, int sizeflag)
15964 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15965 case sp_reg: case bp_reg: case si_reg: case di_reg:
15966 s = names16[code - ax_reg];
15968 case es_reg: case ss_reg: case cs_reg:
15969 case ds_reg: case fs_reg: case gs_reg:
15970 s = names_seg[code - es_reg];
15972 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15973 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15976 s = names8rex[code - al_reg];
15978 s = names8[code - al_reg];
15980 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15981 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15984 s = names64[code - eAX_reg];
15987 if (sizeflag & DFLAG)
15988 s = names32[code - eAX_reg];
15990 s = names16[code - eAX_reg];
15991 used_prefixes |= (prefixes & PREFIX_DATA);
15994 case z_mode_ax_reg:
15995 if ((rex & REX_W) || (sizeflag & DFLAG))
15999 if (!(rex & REX_W))
16000 used_prefixes |= (prefixes & PREFIX_DATA);
16003 s = INTERNAL_DISASSEMBLER_ERROR;
16010 OP_I (int bytemode, int sizeflag)
16013 bfd_signed_vma mask = -1;
16018 FETCH_DATA (the_info, codep + 1);
16023 if (address_mode == mode_64bit)
16028 /* Fall through. */
16035 if (sizeflag & DFLAG)
16045 used_prefixes |= (prefixes & PREFIX_DATA);
16057 oappend (INTERNAL_DISASSEMBLER_ERROR);
16062 scratchbuf[0] = '$';
16063 print_operand_value (scratchbuf + 1, 1, op);
16064 oappend_maybe_intel (scratchbuf);
16065 scratchbuf[0] = '\0';
16069 OP_I64 (int bytemode, int sizeflag)
16072 bfd_signed_vma mask = -1;
16074 if (address_mode != mode_64bit)
16076 OP_I (bytemode, sizeflag);
16083 FETCH_DATA (the_info, codep + 1);
16093 if (sizeflag & DFLAG)
16103 used_prefixes |= (prefixes & PREFIX_DATA);
16111 oappend (INTERNAL_DISASSEMBLER_ERROR);
16116 scratchbuf[0] = '$';
16117 print_operand_value (scratchbuf + 1, 1, op);
16118 oappend_maybe_intel (scratchbuf);
16119 scratchbuf[0] = '\0';
16123 OP_sI (int bytemode, int sizeflag)
16131 FETCH_DATA (the_info, codep + 1);
16133 if ((op & 0x80) != 0)
16135 if (bytemode == b_T_mode)
16137 if (address_mode != mode_64bit
16138 || !((sizeflag & DFLAG) || (rex & REX_W)))
16140 /* The operand-size prefix is overridden by a REX prefix. */
16141 if ((sizeflag & DFLAG) || (rex & REX_W))
16149 if (!(rex & REX_W))
16151 if (sizeflag & DFLAG)
16159 /* The operand-size prefix is overridden by a REX prefix. */
16160 if ((sizeflag & DFLAG) || (rex & REX_W))
16166 oappend (INTERNAL_DISASSEMBLER_ERROR);
16170 scratchbuf[0] = '$';
16171 print_operand_value (scratchbuf + 1, 1, op);
16172 oappend_maybe_intel (scratchbuf);
16176 OP_J (int bytemode, int sizeflag)
16180 bfd_vma segment = 0;
16185 FETCH_DATA (the_info, codep + 1);
16187 if ((disp & 0x80) != 0)
16191 if (isa64 == amd64)
16193 if ((sizeflag & DFLAG)
16194 || (address_mode == mode_64bit
16195 && (isa64 != amd64 || (rex & REX_W))))
16200 if ((disp & 0x8000) != 0)
16202 /* In 16bit mode, address is wrapped around at 64k within
16203 the same segment. Otherwise, a data16 prefix on a jump
16204 instruction means that the pc is masked to 16 bits after
16205 the displacement is added! */
16207 if ((prefixes & PREFIX_DATA) == 0)
16208 segment = ((start_pc + (codep - start_codep))
16209 & ~((bfd_vma) 0xffff));
16211 if (address_mode != mode_64bit
16212 || (isa64 == amd64 && !(rex & REX_W)))
16213 used_prefixes |= (prefixes & PREFIX_DATA);
16216 oappend (INTERNAL_DISASSEMBLER_ERROR);
16219 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16221 print_operand_value (scratchbuf, 1, disp);
16222 oappend (scratchbuf);
16226 OP_SEG (int bytemode, int sizeflag)
16228 if (bytemode == w_mode)
16229 oappend (names_seg[modrm.reg]);
16231 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16235 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16239 if (sizeflag & DFLAG)
16249 used_prefixes |= (prefixes & PREFIX_DATA);
16251 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16253 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16254 oappend (scratchbuf);
16258 OP_OFF (int bytemode, int sizeflag)
16262 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16263 intel_operand_size (bytemode, sizeflag);
16266 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16273 if (!active_seg_prefix)
16275 oappend (names_seg[ds_reg - es_reg]);
16279 print_operand_value (scratchbuf, 1, off);
16280 oappend (scratchbuf);
16284 OP_OFF64 (int bytemode, int sizeflag)
16288 if (address_mode != mode_64bit
16289 || (prefixes & PREFIX_ADDR))
16291 OP_OFF (bytemode, sizeflag);
16295 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16296 intel_operand_size (bytemode, sizeflag);
16303 if (!active_seg_prefix)
16305 oappend (names_seg[ds_reg - es_reg]);
16309 print_operand_value (scratchbuf, 1, off);
16310 oappend (scratchbuf);
16314 ptr_reg (int code, int sizeflag)
16318 *obufp++ = open_char;
16319 used_prefixes |= (prefixes & PREFIX_ADDR);
16320 if (address_mode == mode_64bit)
16322 if (!(sizeflag & AFLAG))
16323 s = names32[code - eAX_reg];
16325 s = names64[code - eAX_reg];
16327 else if (sizeflag & AFLAG)
16328 s = names32[code - eAX_reg];
16330 s = names16[code - eAX_reg];
16332 *obufp++ = close_char;
16337 OP_ESreg (int code, int sizeflag)
16343 case 0x6d: /* insw/insl */
16344 intel_operand_size (z_mode, sizeflag);
16346 case 0xa5: /* movsw/movsl/movsq */
16347 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16348 case 0xab: /* stosw/stosl */
16349 case 0xaf: /* scasw/scasl */
16350 intel_operand_size (v_mode, sizeflag);
16353 intel_operand_size (b_mode, sizeflag);
16356 oappend_maybe_intel ("%es:");
16357 ptr_reg (code, sizeflag);
16361 OP_DSreg (int code, int sizeflag)
16367 case 0x6f: /* outsw/outsl */
16368 intel_operand_size (z_mode, sizeflag);
16370 case 0xa5: /* movsw/movsl/movsq */
16371 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16372 case 0xad: /* lodsw/lodsl/lodsq */
16373 intel_operand_size (v_mode, sizeflag);
16376 intel_operand_size (b_mode, sizeflag);
16379 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16380 default segment register DS is printed. */
16381 if (!active_seg_prefix)
16382 active_seg_prefix = PREFIX_DS;
16384 ptr_reg (code, sizeflag);
16388 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16396 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16398 all_prefixes[last_lock_prefix] = 0;
16399 used_prefixes |= PREFIX_LOCK;
16404 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16405 oappend_maybe_intel (scratchbuf);
16409 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16418 sprintf (scratchbuf, "db%d", modrm.reg + add);
16420 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16421 oappend (scratchbuf);
16425 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16427 sprintf (scratchbuf, "%%tr%d", modrm.reg);
16428 oappend_maybe_intel (scratchbuf);
16432 OP_R (int bytemode, int sizeflag)
16434 /* Skip mod/rm byte. */
16437 OP_E_register (bytemode, sizeflag);
16441 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16443 int reg = modrm.reg;
16444 const char **names;
16446 used_prefixes |= (prefixes & PREFIX_DATA);
16447 if (prefixes & PREFIX_DATA)
16456 oappend (names[reg]);
16460 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16462 int reg = modrm.reg;
16463 const char **names;
16475 && bytemode != xmm_mode
16476 && bytemode != xmmq_mode
16477 && bytemode != evex_half_bcst_xmmq_mode
16478 && bytemode != ymm_mode
16479 && bytemode != scalar_mode)
16481 switch (vex.length)
16488 || (bytemode != vex_vsib_q_w_dq_mode
16489 && bytemode != vex_vsib_q_w_d_mode))
16501 else if (bytemode == xmmq_mode
16502 || bytemode == evex_half_bcst_xmmq_mode)
16504 switch (vex.length)
16517 else if (bytemode == ymm_mode)
16521 oappend (names[reg]);
16525 OP_EM (int bytemode, int sizeflag)
16528 const char **names;
16530 if (modrm.mod != 3)
16533 && (bytemode == v_mode || bytemode == v_swap_mode))
16535 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16536 used_prefixes |= (prefixes & PREFIX_DATA);
16538 OP_E (bytemode, sizeflag);
16542 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16545 /* Skip mod/rm byte. */
16548 used_prefixes |= (prefixes & PREFIX_DATA);
16550 if (prefixes & PREFIX_DATA)
16559 oappend (names[reg]);
16562 /* cvt* are the only instructions in sse2 which have
16563 both SSE and MMX operands and also have 0x66 prefix
16564 in their opcode. 0x66 was originally used to differentiate
16565 between SSE and MMX instruction(operands). So we have to handle the
16566 cvt* separately using OP_EMC and OP_MXC */
16568 OP_EMC (int bytemode, int sizeflag)
16570 if (modrm.mod != 3)
16572 if (intel_syntax && bytemode == v_mode)
16574 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16575 used_prefixes |= (prefixes & PREFIX_DATA);
16577 OP_E (bytemode, sizeflag);
16581 /* Skip mod/rm byte. */
16584 used_prefixes |= (prefixes & PREFIX_DATA);
16585 oappend (names_mm[modrm.rm]);
16589 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16591 used_prefixes |= (prefixes & PREFIX_DATA);
16592 oappend (names_mm[modrm.reg]);
16596 OP_EX (int bytemode, int sizeflag)
16599 const char **names;
16601 /* Skip mod/rm byte. */
16605 if (modrm.mod != 3)
16607 OP_E_memory (bytemode, sizeflag);
16622 if ((sizeflag & SUFFIX_ALWAYS)
16623 && (bytemode == x_swap_mode
16624 || bytemode == d_swap_mode
16625 || bytemode == d_scalar_swap_mode
16626 || bytemode == q_swap_mode
16627 || bytemode == q_scalar_swap_mode))
16631 && bytemode != xmm_mode
16632 && bytemode != xmmdw_mode
16633 && bytemode != xmmqd_mode
16634 && bytemode != xmm_mb_mode
16635 && bytemode != xmm_mw_mode
16636 && bytemode != xmm_md_mode
16637 && bytemode != xmm_mq_mode
16638 && bytemode != xmm_mdq_mode
16639 && bytemode != xmmq_mode
16640 && bytemode != evex_half_bcst_xmmq_mode
16641 && bytemode != ymm_mode
16642 && bytemode != d_scalar_mode
16643 && bytemode != d_scalar_swap_mode
16644 && bytemode != q_scalar_mode
16645 && bytemode != q_scalar_swap_mode
16646 && bytemode != vex_scalar_w_dq_mode)
16648 switch (vex.length)
16663 else if (bytemode == xmmq_mode
16664 || bytemode == evex_half_bcst_xmmq_mode)
16666 switch (vex.length)
16679 else if (bytemode == ymm_mode)
16683 oappend (names[reg]);
16687 OP_MS (int bytemode, int sizeflag)
16689 if (modrm.mod == 3)
16690 OP_EM (bytemode, sizeflag);
16696 OP_XS (int bytemode, int sizeflag)
16698 if (modrm.mod == 3)
16699 OP_EX (bytemode, sizeflag);
16705 OP_M (int bytemode, int sizeflag)
16707 if (modrm.mod == 3)
16708 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16711 OP_E (bytemode, sizeflag);
16715 OP_0f07 (int bytemode, int sizeflag)
16717 if (modrm.mod != 3 || modrm.rm != 0)
16720 OP_E (bytemode, sizeflag);
16723 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16724 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16727 NOP_Fixup1 (int bytemode, int sizeflag)
16729 if ((prefixes & PREFIX_DATA) != 0
16732 && address_mode == mode_64bit))
16733 OP_REG (bytemode, sizeflag);
16735 strcpy (obuf, "nop");
16739 NOP_Fixup2 (int bytemode, int sizeflag)
16741 if ((prefixes & PREFIX_DATA) != 0
16744 && address_mode == mode_64bit))
16745 OP_IMREG (bytemode, sizeflag);
16748 static const char *const Suffix3DNow[] = {
16749 /* 00 */ NULL, NULL, NULL, NULL,
16750 /* 04 */ NULL, NULL, NULL, NULL,
16751 /* 08 */ NULL, NULL, NULL, NULL,
16752 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
16753 /* 10 */ NULL, NULL, NULL, NULL,
16754 /* 14 */ NULL, NULL, NULL, NULL,
16755 /* 18 */ NULL, NULL, NULL, NULL,
16756 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
16757 /* 20 */ NULL, NULL, NULL, NULL,
16758 /* 24 */ NULL, NULL, NULL, NULL,
16759 /* 28 */ NULL, NULL, NULL, NULL,
16760 /* 2C */ NULL, NULL, NULL, NULL,
16761 /* 30 */ NULL, NULL, NULL, NULL,
16762 /* 34 */ NULL, NULL, NULL, NULL,
16763 /* 38 */ NULL, NULL, NULL, NULL,
16764 /* 3C */ NULL, NULL, NULL, NULL,
16765 /* 40 */ NULL, NULL, NULL, NULL,
16766 /* 44 */ NULL, NULL, NULL, NULL,
16767 /* 48 */ NULL, NULL, NULL, NULL,
16768 /* 4C */ NULL, NULL, NULL, NULL,
16769 /* 50 */ NULL, NULL, NULL, NULL,
16770 /* 54 */ NULL, NULL, NULL, NULL,
16771 /* 58 */ NULL, NULL, NULL, NULL,
16772 /* 5C */ NULL, NULL, NULL, NULL,
16773 /* 60 */ NULL, NULL, NULL, NULL,
16774 /* 64 */ NULL, NULL, NULL, NULL,
16775 /* 68 */ NULL, NULL, NULL, NULL,
16776 /* 6C */ NULL, NULL, NULL, NULL,
16777 /* 70 */ NULL, NULL, NULL, NULL,
16778 /* 74 */ NULL, NULL, NULL, NULL,
16779 /* 78 */ NULL, NULL, NULL, NULL,
16780 /* 7C */ NULL, NULL, NULL, NULL,
16781 /* 80 */ NULL, NULL, NULL, NULL,
16782 /* 84 */ NULL, NULL, NULL, NULL,
16783 /* 88 */ NULL, NULL, "pfnacc", NULL,
16784 /* 8C */ NULL, NULL, "pfpnacc", NULL,
16785 /* 90 */ "pfcmpge", NULL, NULL, NULL,
16786 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
16787 /* 98 */ NULL, NULL, "pfsub", NULL,
16788 /* 9C */ NULL, NULL, "pfadd", NULL,
16789 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
16790 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
16791 /* A8 */ NULL, NULL, "pfsubr", NULL,
16792 /* AC */ NULL, NULL, "pfacc", NULL,
16793 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
16794 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
16795 /* B8 */ NULL, NULL, NULL, "pswapd",
16796 /* BC */ NULL, NULL, NULL, "pavgusb",
16797 /* C0 */ NULL, NULL, NULL, NULL,
16798 /* C4 */ NULL, NULL, NULL, NULL,
16799 /* C8 */ NULL, NULL, NULL, NULL,
16800 /* CC */ NULL, NULL, NULL, NULL,
16801 /* D0 */ NULL, NULL, NULL, NULL,
16802 /* D4 */ NULL, NULL, NULL, NULL,
16803 /* D8 */ NULL, NULL, NULL, NULL,
16804 /* DC */ NULL, NULL, NULL, NULL,
16805 /* E0 */ NULL, NULL, NULL, NULL,
16806 /* E4 */ NULL, NULL, NULL, NULL,
16807 /* E8 */ NULL, NULL, NULL, NULL,
16808 /* EC */ NULL, NULL, NULL, NULL,
16809 /* F0 */ NULL, NULL, NULL, NULL,
16810 /* F4 */ NULL, NULL, NULL, NULL,
16811 /* F8 */ NULL, NULL, NULL, NULL,
16812 /* FC */ NULL, NULL, NULL, NULL,
16816 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16818 const char *mnemonic;
16820 FETCH_DATA (the_info, codep + 1);
16821 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16822 place where an 8-bit immediate would normally go. ie. the last
16823 byte of the instruction. */
16824 obufp = mnemonicendp;
16825 mnemonic = Suffix3DNow[*codep++ & 0xff];
16827 oappend (mnemonic);
16830 /* Since a variable sized modrm/sib chunk is between the start
16831 of the opcode (0x0f0f) and the opcode suffix, we need to do
16832 all the modrm processing first, and don't know until now that
16833 we have a bad opcode. This necessitates some cleaning up. */
16834 op_out[0][0] = '\0';
16835 op_out[1][0] = '\0';
16838 mnemonicendp = obufp;
16841 static struct op simd_cmp_op[] =
16843 { STRING_COMMA_LEN ("eq") },
16844 { STRING_COMMA_LEN ("lt") },
16845 { STRING_COMMA_LEN ("le") },
16846 { STRING_COMMA_LEN ("unord") },
16847 { STRING_COMMA_LEN ("neq") },
16848 { STRING_COMMA_LEN ("nlt") },
16849 { STRING_COMMA_LEN ("nle") },
16850 { STRING_COMMA_LEN ("ord") }
16854 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16856 unsigned int cmp_type;
16858 FETCH_DATA (the_info, codep + 1);
16859 cmp_type = *codep++ & 0xff;
16860 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16863 char *p = mnemonicendp - 2;
16867 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16868 mnemonicendp += simd_cmp_op[cmp_type].len;
16872 /* We have a reserved extension byte. Output it directly. */
16873 scratchbuf[0] = '$';
16874 print_operand_value (scratchbuf + 1, 1, cmp_type);
16875 oappend_maybe_intel (scratchbuf);
16876 scratchbuf[0] = '\0';
16881 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16882 int sizeflag ATTRIBUTE_UNUSED)
16884 /* mwaitx %eax,%ecx,%ebx */
16887 const char **names = (address_mode == mode_64bit
16888 ? names64 : names32);
16889 strcpy (op_out[0], names[0]);
16890 strcpy (op_out[1], names[1]);
16891 strcpy (op_out[2], names[3]);
16892 two_source_ops = 1;
16894 /* Skip mod/rm byte. */
16900 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16901 int sizeflag ATTRIBUTE_UNUSED)
16903 /* mwait %eax,%ecx */
16906 const char **names = (address_mode == mode_64bit
16907 ? names64 : names32);
16908 strcpy (op_out[0], names[0]);
16909 strcpy (op_out[1], names[1]);
16910 two_source_ops = 1;
16912 /* Skip mod/rm byte. */
16918 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16919 int sizeflag ATTRIBUTE_UNUSED)
16921 /* monitor %eax,%ecx,%edx" */
16924 const char **op1_names;
16925 const char **names = (address_mode == mode_64bit
16926 ? names64 : names32);
16928 if (!(prefixes & PREFIX_ADDR))
16929 op1_names = (address_mode == mode_16bit
16930 ? names16 : names);
16933 /* Remove "addr16/addr32". */
16934 all_prefixes[last_addr_prefix] = 0;
16935 op1_names = (address_mode != mode_32bit
16936 ? names32 : names16);
16937 used_prefixes |= PREFIX_ADDR;
16939 strcpy (op_out[0], op1_names[0]);
16940 strcpy (op_out[1], names[1]);
16941 strcpy (op_out[2], names[2]);
16942 two_source_ops = 1;
16944 /* Skip mod/rm byte. */
16952 /* Throw away prefixes and 1st. opcode byte. */
16953 codep = insn_codep + 1;
16958 REP_Fixup (int bytemode, int sizeflag)
16960 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16962 if (prefixes & PREFIX_REPZ)
16963 all_prefixes[last_repz_prefix] = REP_PREFIX;
16970 OP_IMREG (bytemode, sizeflag);
16973 OP_ESreg (bytemode, sizeflag);
16976 OP_DSreg (bytemode, sizeflag);
16984 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16988 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16990 if (prefixes & PREFIX_REPNZ)
16991 all_prefixes[last_repnz_prefix] = BND_PREFIX;
16994 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16998 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16999 int sizeflag ATTRIBUTE_UNUSED)
17001 if (active_seg_prefix == PREFIX_DS
17002 && (address_mode != mode_64bit || last_data_prefix < 0))
17004 /* NOTRACK prefix is only valid on indirect branch instructions.
17005 NB: DATA prefix is unsupported for Intel64. */
17006 active_seg_prefix = 0;
17007 all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
17011 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
17012 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
17016 HLE_Fixup1 (int bytemode, int sizeflag)
17019 && (prefixes & PREFIX_LOCK) != 0)
17021 if (prefixes & PREFIX_REPZ)
17022 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17023 if (prefixes & PREFIX_REPNZ)
17024 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17027 OP_E (bytemode, sizeflag);
17030 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
17031 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
17035 HLE_Fixup2 (int bytemode, int sizeflag)
17037 if (modrm.mod != 3)
17039 if (prefixes & PREFIX_REPZ)
17040 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17041 if (prefixes & PREFIX_REPNZ)
17042 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17045 OP_E (bytemode, sizeflag);
17048 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
17049 "xrelease" for memory operand. No check for LOCK prefix. */
17052 HLE_Fixup3 (int bytemode, int sizeflag)
17055 && last_repz_prefix > last_repnz_prefix
17056 && (prefixes & PREFIX_REPZ) != 0)
17057 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17059 OP_E (bytemode, sizeflag);
17063 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
17068 /* Change cmpxchg8b to cmpxchg16b. */
17069 char *p = mnemonicendp - 2;
17070 mnemonicendp = stpcpy (p, "16b");
17073 else if ((prefixes & PREFIX_LOCK) != 0)
17075 if (prefixes & PREFIX_REPZ)
17076 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17077 if (prefixes & PREFIX_REPNZ)
17078 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17081 OP_M (bytemode, sizeflag);
17085 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
17087 const char **names;
17091 switch (vex.length)
17105 oappend (names[reg]);
17109 CRC32_Fixup (int bytemode, int sizeflag)
17111 /* Add proper suffix to "crc32". */
17112 char *p = mnemonicendp;
17131 if (sizeflag & DFLAG)
17135 used_prefixes |= (prefixes & PREFIX_DATA);
17139 oappend (INTERNAL_DISASSEMBLER_ERROR);
17146 if (modrm.mod == 3)
17150 /* Skip mod/rm byte. */
17155 add = (rex & REX_B) ? 8 : 0;
17156 if (bytemode == b_mode)
17160 oappend (names8rex[modrm.rm + add]);
17162 oappend (names8[modrm.rm + add]);
17168 oappend (names64[modrm.rm + add]);
17169 else if ((prefixes & PREFIX_DATA))
17170 oappend (names16[modrm.rm + add]);
17172 oappend (names32[modrm.rm + add]);
17176 OP_E (bytemode, sizeflag);
17180 FXSAVE_Fixup (int bytemode, int sizeflag)
17182 /* Add proper suffix to "fxsave" and "fxrstor". */
17186 char *p = mnemonicendp;
17192 OP_M (bytemode, sizeflag);
17196 PCMPESTR_Fixup (int bytemode, int sizeflag)
17198 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
17201 char *p = mnemonicendp;
17206 else if (sizeflag & SUFFIX_ALWAYS)
17213 OP_EX (bytemode, sizeflag);
17216 /* Display the destination register operand for instructions with
17220 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17223 const char **names;
17231 reg = vex.register_specifier;
17232 if (address_mode != mode_64bit)
17234 else if (vex.evex && !vex.v)
17237 if (bytemode == vex_scalar_mode)
17239 oappend (names_xmm[reg]);
17243 switch (vex.length)
17250 case vex_vsib_q_w_dq_mode:
17251 case vex_vsib_q_w_d_mode:
17267 names = names_mask;
17281 case vex_vsib_q_w_dq_mode:
17282 case vex_vsib_q_w_d_mode:
17283 names = vex.w ? names_ymm : names_xmm;
17292 names = names_mask;
17295 /* See PR binutils/20893 for a reproducer. */
17307 oappend (names[reg]);
17310 /* Get the VEX immediate byte without moving codep. */
17312 static unsigned char
17313 get_vex_imm8 (int sizeflag, int opnum)
17315 int bytes_before_imm = 0;
17317 if (modrm.mod != 3)
17319 /* There are SIB/displacement bytes. */
17320 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17322 /* 32/64 bit address mode */
17323 int base = modrm.rm;
17325 /* Check SIB byte. */
17328 FETCH_DATA (the_info, codep + 1);
17330 /* When decoding the third source, don't increase
17331 bytes_before_imm as this has already been incremented
17332 by one in OP_E_memory while decoding the second
17335 bytes_before_imm++;
17338 /* Don't increase bytes_before_imm when decoding the third source,
17339 it has already been incremented by OP_E_memory while decoding
17340 the second source operand. */
17346 /* When modrm.rm == 5 or modrm.rm == 4 and base in
17347 SIB == 5, there is a 4 byte displacement. */
17349 /* No displacement. */
17351 /* Fall through. */
17353 /* 4 byte displacement. */
17354 bytes_before_imm += 4;
17357 /* 1 byte displacement. */
17358 bytes_before_imm++;
17365 /* 16 bit address mode */
17366 /* Don't increase bytes_before_imm when decoding the third source,
17367 it has already been incremented by OP_E_memory while decoding
17368 the second source operand. */
17374 /* When modrm.rm == 6, there is a 2 byte displacement. */
17376 /* No displacement. */
17378 /* Fall through. */
17380 /* 2 byte displacement. */
17381 bytes_before_imm += 2;
17384 /* 1 byte displacement: when decoding the third source,
17385 don't increase bytes_before_imm as this has already
17386 been incremented by one in OP_E_memory while decoding
17387 the second source operand. */
17389 bytes_before_imm++;
17397 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17398 return codep [bytes_before_imm];
17402 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17404 const char **names;
17406 if (reg == -1 && modrm.mod != 3)
17408 OP_E_memory (bytemode, sizeflag);
17420 if (address_mode != mode_64bit)
17424 switch (vex.length)
17435 oappend (names[reg]);
17439 OP_EX_VexImmW (int bytemode, int sizeflag)
17442 static unsigned char vex_imm8;
17444 if (vex_w_done == 0)
17448 /* Skip mod/rm byte. */
17452 vex_imm8 = get_vex_imm8 (sizeflag, 0);
17455 reg = vex_imm8 >> 4;
17457 OP_EX_VexReg (bytemode, sizeflag, reg);
17459 else if (vex_w_done == 1)
17464 reg = vex_imm8 >> 4;
17466 OP_EX_VexReg (bytemode, sizeflag, reg);
17470 /* Output the imm8 directly. */
17471 scratchbuf[0] = '$';
17472 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17473 oappend_maybe_intel (scratchbuf);
17474 scratchbuf[0] = '\0';
17480 OP_Vex_2src (int bytemode, int sizeflag)
17482 if (modrm.mod == 3)
17484 int reg = modrm.rm;
17488 oappend (names_xmm[reg]);
17493 && (bytemode == v_mode || bytemode == v_swap_mode))
17495 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17496 used_prefixes |= (prefixes & PREFIX_DATA);
17498 OP_E (bytemode, sizeflag);
17503 OP_Vex_2src_1 (int bytemode, int sizeflag)
17505 if (modrm.mod == 3)
17507 /* Skip mod/rm byte. */
17514 unsigned int reg = vex.register_specifier;
17516 if (address_mode != mode_64bit)
17518 oappend (names_xmm[reg]);
17521 OP_Vex_2src (bytemode, sizeflag);
17525 OP_Vex_2src_2 (int bytemode, int sizeflag)
17528 OP_Vex_2src (bytemode, sizeflag);
17531 unsigned int reg = vex.register_specifier;
17533 if (address_mode != mode_64bit)
17535 oappend (names_xmm[reg]);
17540 OP_EX_VexW (int bytemode, int sizeflag)
17546 /* Skip mod/rm byte. */
17551 reg = get_vex_imm8 (sizeflag, 0) >> 4;
17556 reg = get_vex_imm8 (sizeflag, 1) >> 4;
17559 OP_EX_VexReg (bytemode, sizeflag, reg);
17567 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17570 const char **names;
17572 FETCH_DATA (the_info, codep + 1);
17575 if (bytemode != x_mode)
17579 if (address_mode != mode_64bit)
17582 switch (vex.length)
17593 oappend (names[reg]);
17597 OP_XMM_VexW (int bytemode, int sizeflag)
17599 /* Turn off the REX.W bit since it is used for swapping operands
17602 OP_XMM (bytemode, sizeflag);
17606 OP_EX_Vex (int bytemode, int sizeflag)
17608 if (modrm.mod != 3)
17610 if (vex.register_specifier != 0)
17614 OP_EX (bytemode, sizeflag);
17618 OP_XMM_Vex (int bytemode, int sizeflag)
17620 if (modrm.mod != 3)
17622 if (vex.register_specifier != 0)
17626 OP_XMM (bytemode, sizeflag);
17630 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17632 switch (vex.length)
17635 mnemonicendp = stpcpy (obuf, "vzeroupper");
17638 mnemonicendp = stpcpy (obuf, "vzeroall");
17645 static struct op vex_cmp_op[] =
17647 { STRING_COMMA_LEN ("eq") },
17648 { STRING_COMMA_LEN ("lt") },
17649 { STRING_COMMA_LEN ("le") },
17650 { STRING_COMMA_LEN ("unord") },
17651 { STRING_COMMA_LEN ("neq") },
17652 { STRING_COMMA_LEN ("nlt") },
17653 { STRING_COMMA_LEN ("nle") },
17654 { STRING_COMMA_LEN ("ord") },
17655 { STRING_COMMA_LEN ("eq_uq") },
17656 { STRING_COMMA_LEN ("nge") },
17657 { STRING_COMMA_LEN ("ngt") },
17658 { STRING_COMMA_LEN ("false") },
17659 { STRING_COMMA_LEN ("neq_oq") },
17660 { STRING_COMMA_LEN ("ge") },
17661 { STRING_COMMA_LEN ("gt") },
17662 { STRING_COMMA_LEN ("true") },
17663 { STRING_COMMA_LEN ("eq_os") },
17664 { STRING_COMMA_LEN ("lt_oq") },
17665 { STRING_COMMA_LEN ("le_oq") },
17666 { STRING_COMMA_LEN ("unord_s") },
17667 { STRING_COMMA_LEN ("neq_us") },
17668 { STRING_COMMA_LEN ("nlt_uq") },
17669 { STRING_COMMA_LEN ("nle_uq") },
17670 { STRING_COMMA_LEN ("ord_s") },
17671 { STRING_COMMA_LEN ("eq_us") },
17672 { STRING_COMMA_LEN ("nge_uq") },
17673 { STRING_COMMA_LEN ("ngt_uq") },
17674 { STRING_COMMA_LEN ("false_os") },
17675 { STRING_COMMA_LEN ("neq_os") },
17676 { STRING_COMMA_LEN ("ge_oq") },
17677 { STRING_COMMA_LEN ("gt_oq") },
17678 { STRING_COMMA_LEN ("true_us") },
17682 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17684 unsigned int cmp_type;
17686 FETCH_DATA (the_info, codep + 1);
17687 cmp_type = *codep++ & 0xff;
17688 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17691 char *p = mnemonicendp - 2;
17695 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17696 mnemonicendp += vex_cmp_op[cmp_type].len;
17700 /* We have a reserved extension byte. Output it directly. */
17701 scratchbuf[0] = '$';
17702 print_operand_value (scratchbuf + 1, 1, cmp_type);
17703 oappend_maybe_intel (scratchbuf);
17704 scratchbuf[0] = '\0';
17709 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17710 int sizeflag ATTRIBUTE_UNUSED)
17712 unsigned int cmp_type;
17717 FETCH_DATA (the_info, codep + 1);
17718 cmp_type = *codep++ & 0xff;
17719 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17720 If it's the case, print suffix, otherwise - print the immediate. */
17721 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17726 char *p = mnemonicendp - 2;
17728 /* vpcmp* can have both one- and two-lettered suffix. */
17742 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17743 mnemonicendp += simd_cmp_op[cmp_type].len;
17747 /* We have a reserved extension byte. Output it directly. */
17748 scratchbuf[0] = '$';
17749 print_operand_value (scratchbuf + 1, 1, cmp_type);
17750 oappend_maybe_intel (scratchbuf);
17751 scratchbuf[0] = '\0';
17755 static const struct op xop_cmp_op[] =
17757 { STRING_COMMA_LEN ("lt") },
17758 { STRING_COMMA_LEN ("le") },
17759 { STRING_COMMA_LEN ("gt") },
17760 { STRING_COMMA_LEN ("ge") },
17761 { STRING_COMMA_LEN ("eq") },
17762 { STRING_COMMA_LEN ("neq") },
17763 { STRING_COMMA_LEN ("false") },
17764 { STRING_COMMA_LEN ("true") }
17768 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
17769 int sizeflag ATTRIBUTE_UNUSED)
17771 unsigned int cmp_type;
17773 FETCH_DATA (the_info, codep + 1);
17774 cmp_type = *codep++ & 0xff;
17775 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
17778 char *p = mnemonicendp - 2;
17780 /* vpcom* can have both one- and two-lettered suffix. */
17794 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
17795 mnemonicendp += xop_cmp_op[cmp_type].len;
17799 /* We have a reserved extension byte. Output it directly. */
17800 scratchbuf[0] = '$';
17801 print_operand_value (scratchbuf + 1, 1, cmp_type);
17802 oappend_maybe_intel (scratchbuf);
17803 scratchbuf[0] = '\0';
17807 static const struct op pclmul_op[] =
17809 { STRING_COMMA_LEN ("lql") },
17810 { STRING_COMMA_LEN ("hql") },
17811 { STRING_COMMA_LEN ("lqh") },
17812 { STRING_COMMA_LEN ("hqh") }
17816 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17817 int sizeflag ATTRIBUTE_UNUSED)
17819 unsigned int pclmul_type;
17821 FETCH_DATA (the_info, codep + 1);
17822 pclmul_type = *codep++ & 0xff;
17823 switch (pclmul_type)
17834 if (pclmul_type < ARRAY_SIZE (pclmul_op))
17837 char *p = mnemonicendp - 3;
17842 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17843 mnemonicendp += pclmul_op[pclmul_type].len;
17847 /* We have a reserved extension byte. Output it directly. */
17848 scratchbuf[0] = '$';
17849 print_operand_value (scratchbuf + 1, 1, pclmul_type);
17850 oappend_maybe_intel (scratchbuf);
17851 scratchbuf[0] = '\0';
17856 MOVBE_Fixup (int bytemode, int sizeflag)
17858 /* Add proper suffix to "movbe". */
17859 char *p = mnemonicendp;
17868 if (sizeflag & SUFFIX_ALWAYS)
17874 if (sizeflag & DFLAG)
17878 used_prefixes |= (prefixes & PREFIX_DATA);
17883 oappend (INTERNAL_DISASSEMBLER_ERROR);
17890 OP_M (bytemode, sizeflag);
17894 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17897 const char **names;
17899 /* Skip mod/rm byte. */
17913 oappend (names[reg]);
17917 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17919 const char **names;
17920 unsigned int reg = vex.register_specifier;
17927 if (address_mode != mode_64bit)
17929 oappend (names[reg]);
17933 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17936 || (bytemode != mask_mode && bytemode != mask_bd_mode))
17940 if ((rex & REX_R) != 0 || !vex.r)
17946 oappend (names_mask [modrm.reg]);
17950 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17953 || (bytemode != evex_rounding_mode
17954 && bytemode != evex_rounding_64_mode
17955 && bytemode != evex_sae_mode))
17957 if (modrm.mod == 3 && vex.b)
17960 case evex_rounding_64_mode:
17961 if (address_mode != mode_64bit)
17966 /* Fall through. */
17967 case evex_rounding_mode:
17968 oappend (names_rounding[vex.ll]);
17970 case evex_sae_mode: