1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma, disassemble_info *);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma get64 (void);
58 static bfd_signed_vma get32 (void);
59 static bfd_signed_vma get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void HLE_Fixup1 (int, int);
113 static void HLE_Fixup2 (int, int);
114 static void HLE_Fixup3 (int, int);
115 static void CMPXCHG8B_Fixup (int, int);
116 static void XMM_Fixup (int, int);
117 static void CRC32_Fixup (int, int);
118 static void FXSAVE_Fixup (int, int);
119 static void OP_LWPCB_E (int, int);
120 static void OP_LWP_E (int, int);
121 static void OP_Vex_2src_1 (int, int);
122 static void OP_Vex_2src_2 (int, int);
124 static void MOVBE_Fixup (int, int);
126 static void OP_Mask (int, int);
129 /* Points to first byte not fetched. */
130 bfd_byte *max_fetched;
131 bfd_byte the_buffer[MAX_MNEM_SIZE];
134 OPCODES_SIGJMP_BUF bailout;
144 enum address_mode address_mode;
146 /* Flags for the prefixes for the current instruction. See below. */
149 /* REX prefix the current instruction. See below. */
151 /* Bits of REX we've already used. */
153 /* REX bits in original REX prefix ignored. */
154 static int rex_ignored;
155 /* Mark parts used in the REX prefix. When we are testing for
156 empty prefix (for 8bit register REX extension), just mask it
157 out. Otherwise test for REX bit is excuse for existence of REX
158 only in case value is nonzero. */
159 #define USED_REX(value) \
164 rex_used |= (value) | REX_OPCODE; \
167 rex_used |= REX_OPCODE; \
170 /* Flags for prefixes which we somehow handled when printing the
171 current instruction. */
172 static int used_prefixes;
174 /* Flags stored in PREFIXES. */
175 #define PREFIX_REPZ 1
176 #define PREFIX_REPNZ 2
177 #define PREFIX_LOCK 4
179 #define PREFIX_SS 0x10
180 #define PREFIX_DS 0x20
181 #define PREFIX_ES 0x40
182 #define PREFIX_FS 0x80
183 #define PREFIX_GS 0x100
184 #define PREFIX_DATA 0x200
185 #define PREFIX_ADDR 0x400
186 #define PREFIX_FWAIT 0x800
188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
189 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
191 #define FETCH_DATA(info, addr) \
192 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
193 ? 1 : fetch_data ((info), (addr)))
196 fetch_data (struct disassemble_info *info, bfd_byte *addr)
199 struct dis_private *priv = (struct dis_private *) info->private_data;
200 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
202 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
203 status = (*info->read_memory_func) (start,
205 addr - priv->max_fetched,
211 /* If we did manage to read at least one byte, then
212 print_insn_i386 will do something sensible. Otherwise, print
213 an error. We do that here because this is where we know
215 if (priv->max_fetched == priv->the_buffer)
216 (*info->memory_error_func) (status, start, info);
217 OPCODES_SIGLONGJMP (priv->bailout, 1);
220 priv->max_fetched = addr;
224 #define XX { NULL, 0 }
225 #define Bad_Opcode NULL, { { NULL, 0 } }
227 #define Eb { OP_E, b_mode }
228 #define Ebnd { OP_E, bnd_mode }
229 #define EbS { OP_E, b_swap_mode }
230 #define Ev { OP_E, v_mode }
231 #define Ev_bnd { OP_E, v_bnd_mode }
232 #define EvS { OP_E, v_swap_mode }
233 #define Ed { OP_E, d_mode }
234 #define Edq { OP_E, dq_mode }
235 #define Edqw { OP_E, dqw_mode }
236 #define Edqb { OP_E, dqb_mode }
237 #define Edqd { OP_E, dqd_mode }
238 #define Eq { OP_E, q_mode }
239 #define indirEv { OP_indirE, stack_v_mode }
240 #define indirEp { OP_indirE, f_mode }
241 #define stackEv { OP_E, stack_v_mode }
242 #define Em { OP_E, m_mode }
243 #define Ew { OP_E, w_mode }
244 #define M { OP_M, 0 } /* lea, lgdt, etc. */
245 #define Ma { OP_M, a_mode }
246 #define Mb { OP_M, b_mode }
247 #define Md { OP_M, d_mode }
248 #define Mo { OP_M, o_mode }
249 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
250 #define Mq { OP_M, q_mode }
251 #define Mx { OP_M, x_mode }
252 #define Mxmm { OP_M, xmm_mode }
253 #define Gb { OP_G, b_mode }
254 #define Gbnd { OP_G, bnd_mode }
255 #define Gv { OP_G, v_mode }
256 #define Gd { OP_G, d_mode }
257 #define Gdq { OP_G, dq_mode }
258 #define Gm { OP_G, m_mode }
259 #define Gw { OP_G, w_mode }
260 #define Rd { OP_R, d_mode }
261 #define Rdq { OP_R, dq_mode }
262 #define Rm { OP_R, m_mode }
263 #define Ib { OP_I, b_mode }
264 #define sIb { OP_sI, b_mode } /* sign extened byte */
265 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
266 #define Iv { OP_I, v_mode }
267 #define sIv { OP_sI, v_mode }
268 #define Iq { OP_I, q_mode }
269 #define Iv64 { OP_I64, v_mode }
270 #define Iw { OP_I, w_mode }
271 #define I1 { OP_I, const_1_mode }
272 #define Jb { OP_J, b_mode }
273 #define Jv { OP_J, v_mode }
274 #define Cm { OP_C, m_mode }
275 #define Dm { OP_D, m_mode }
276 #define Td { OP_T, d_mode }
277 #define Skip_MODRM { OP_Skip_MODRM, 0 }
279 #define RMeAX { OP_REG, eAX_reg }
280 #define RMeBX { OP_REG, eBX_reg }
281 #define RMeCX { OP_REG, eCX_reg }
282 #define RMeDX { OP_REG, eDX_reg }
283 #define RMeSP { OP_REG, eSP_reg }
284 #define RMeBP { OP_REG, eBP_reg }
285 #define RMeSI { OP_REG, eSI_reg }
286 #define RMeDI { OP_REG, eDI_reg }
287 #define RMrAX { OP_REG, rAX_reg }
288 #define RMrBX { OP_REG, rBX_reg }
289 #define RMrCX { OP_REG, rCX_reg }
290 #define RMrDX { OP_REG, rDX_reg }
291 #define RMrSP { OP_REG, rSP_reg }
292 #define RMrBP { OP_REG, rBP_reg }
293 #define RMrSI { OP_REG, rSI_reg }
294 #define RMrDI { OP_REG, rDI_reg }
295 #define RMAL { OP_REG, al_reg }
296 #define RMCL { OP_REG, cl_reg }
297 #define RMDL { OP_REG, dl_reg }
298 #define RMBL { OP_REG, bl_reg }
299 #define RMAH { OP_REG, ah_reg }
300 #define RMCH { OP_REG, ch_reg }
301 #define RMDH { OP_REG, dh_reg }
302 #define RMBH { OP_REG, bh_reg }
303 #define RMAX { OP_REG, ax_reg }
304 #define RMDX { OP_REG, dx_reg }
306 #define eAX { OP_IMREG, eAX_reg }
307 #define eBX { OP_IMREG, eBX_reg }
308 #define eCX { OP_IMREG, eCX_reg }
309 #define eDX { OP_IMREG, eDX_reg }
310 #define eSP { OP_IMREG, eSP_reg }
311 #define eBP { OP_IMREG, eBP_reg }
312 #define eSI { OP_IMREG, eSI_reg }
313 #define eDI { OP_IMREG, eDI_reg }
314 #define AL { OP_IMREG, al_reg }
315 #define CL { OP_IMREG, cl_reg }
316 #define DL { OP_IMREG, dl_reg }
317 #define BL { OP_IMREG, bl_reg }
318 #define AH { OP_IMREG, ah_reg }
319 #define CH { OP_IMREG, ch_reg }
320 #define DH { OP_IMREG, dh_reg }
321 #define BH { OP_IMREG, bh_reg }
322 #define AX { OP_IMREG, ax_reg }
323 #define DX { OP_IMREG, dx_reg }
324 #define zAX { OP_IMREG, z_mode_ax_reg }
325 #define indirDX { OP_IMREG, indir_dx_reg }
327 #define Sw { OP_SEG, w_mode }
328 #define Sv { OP_SEG, v_mode }
329 #define Ap { OP_DIR, 0 }
330 #define Ob { OP_OFF64, b_mode }
331 #define Ov { OP_OFF64, v_mode }
332 #define Xb { OP_DSreg, eSI_reg }
333 #define Xv { OP_DSreg, eSI_reg }
334 #define Xz { OP_DSreg, eSI_reg }
335 #define Yb { OP_ESreg, eDI_reg }
336 #define Yv { OP_ESreg, eDI_reg }
337 #define DSBX { OP_DSreg, eBX_reg }
339 #define es { OP_REG, es_reg }
340 #define ss { OP_REG, ss_reg }
341 #define cs { OP_REG, cs_reg }
342 #define ds { OP_REG, ds_reg }
343 #define fs { OP_REG, fs_reg }
344 #define gs { OP_REG, gs_reg }
346 #define MX { OP_MMX, 0 }
347 #define XM { OP_XMM, 0 }
348 #define XMScalar { OP_XMM, scalar_mode }
349 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
350 #define XMM { OP_XMM, xmm_mode }
351 #define XMxmmq { OP_XMM, xmmq_mode }
352 #define EM { OP_EM, v_mode }
353 #define EMS { OP_EM, v_swap_mode }
354 #define EMd { OP_EM, d_mode }
355 #define EMx { OP_EM, x_mode }
356 #define EXw { OP_EX, w_mode }
357 #define EXd { OP_EX, d_mode }
358 #define EXdScalar { OP_EX, d_scalar_mode }
359 #define EXdS { OP_EX, d_swap_mode }
360 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
361 #define EXq { OP_EX, q_mode }
362 #define EXqScalar { OP_EX, q_scalar_mode }
363 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
364 #define EXqS { OP_EX, q_swap_mode }
365 #define EXx { OP_EX, x_mode }
366 #define EXxS { OP_EX, x_swap_mode }
367 #define EXxmm { OP_EX, xmm_mode }
368 #define EXymm { OP_EX, ymm_mode }
369 #define EXxmmq { OP_EX, xmmq_mode }
370 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
371 #define EXxmm_mb { OP_EX, xmm_mb_mode }
372 #define EXxmm_mw { OP_EX, xmm_mw_mode }
373 #define EXxmm_md { OP_EX, xmm_md_mode }
374 #define EXxmm_mq { OP_EX, xmm_mq_mode }
375 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
376 #define EXxmmdw { OP_EX, xmmdw_mode }
377 #define EXxmmqd { OP_EX, xmmqd_mode }
378 #define EXymmq { OP_EX, ymmq_mode }
379 #define EXVexWdq { OP_EX, vex_w_dq_mode }
380 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
381 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
382 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
383 #define MS { OP_MS, v_mode }
384 #define XS { OP_XS, v_mode }
385 #define EMCq { OP_EMC, q_mode }
386 #define MXC { OP_MXC, 0 }
387 #define OPSUF { OP_3DNowSuffix, 0 }
388 #define CMP { CMP_Fixup, 0 }
389 #define XMM0 { XMM_Fixup, 0 }
390 #define FXSAVE { FXSAVE_Fixup, 0 }
391 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
392 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
394 #define Vex { OP_VEX, vex_mode }
395 #define VexScalar { OP_VEX, vex_scalar_mode }
396 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
397 #define Vex128 { OP_VEX, vex128_mode }
398 #define Vex256 { OP_VEX, vex256_mode }
399 #define VexGdq { OP_VEX, dq_mode }
400 #define VexI4 { VEXI4_Fixup, 0}
401 #define EXdVex { OP_EX_Vex, d_mode }
402 #define EXdVexS { OP_EX_Vex, d_swap_mode }
403 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
404 #define EXqVex { OP_EX_Vex, q_mode }
405 #define EXqVexS { OP_EX_Vex, q_swap_mode }
406 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
407 #define EXVexW { OP_EX_VexW, x_mode }
408 #define EXdVexW { OP_EX_VexW, d_mode }
409 #define EXqVexW { OP_EX_VexW, q_mode }
410 #define EXVexImmW { OP_EX_VexImmW, x_mode }
411 #define XMVex { OP_XMM_Vex, 0 }
412 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
413 #define XMVexW { OP_XMM_VexW, 0 }
414 #define XMVexI4 { OP_REG_VexI4, x_mode }
415 #define PCLMUL { PCLMUL_Fixup, 0 }
416 #define VZERO { VZERO_Fixup, 0 }
417 #define VCMP { VCMP_Fixup, 0 }
418 #define VPCMP { VPCMP_Fixup, 0 }
420 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
421 #define EXxEVexS { OP_Rounding, evex_sae_mode }
423 #define XMask { OP_Mask, mask_mode }
424 #define MaskG { OP_G, mask_mode }
425 #define MaskE { OP_E, mask_mode }
426 #define MaskR { OP_R, mask_mode }
427 #define MaskVex { OP_VEX, mask_mode }
429 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
430 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
431 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
432 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
434 /* Used handle "rep" prefix for string instructions. */
435 #define Xbr { REP_Fixup, eSI_reg }
436 #define Xvr { REP_Fixup, eSI_reg }
437 #define Ybr { REP_Fixup, eDI_reg }
438 #define Yvr { REP_Fixup, eDI_reg }
439 #define Yzr { REP_Fixup, eDI_reg }
440 #define indirDXr { REP_Fixup, indir_dx_reg }
441 #define ALr { REP_Fixup, al_reg }
442 #define eAXr { REP_Fixup, eAX_reg }
444 /* Used handle HLE prefix for lockable instructions. */
445 #define Ebh1 { HLE_Fixup1, b_mode }
446 #define Evh1 { HLE_Fixup1, v_mode }
447 #define Ebh2 { HLE_Fixup2, b_mode }
448 #define Evh2 { HLE_Fixup2, v_mode }
449 #define Ebh3 { HLE_Fixup3, b_mode }
450 #define Evh3 { HLE_Fixup3, v_mode }
452 #define BND { BND_Fixup, 0 }
454 #define cond_jump_flag { NULL, cond_jump_mode }
455 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
457 /* bits in sizeflag */
458 #define SUFFIX_ALWAYS 4
466 /* byte operand with operand swapped */
468 /* byte operand, sign extend like 'T' suffix */
470 /* operand size depends on prefixes */
472 /* operand size depends on prefixes with operand swapped */
476 /* double word operand */
478 /* double word operand with operand swapped */
480 /* quad word operand */
482 /* quad word operand with operand swapped */
484 /* ten-byte operand */
486 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
487 broadcast enabled. */
489 /* Similar to x_mode, but with different EVEX mem shifts. */
491 /* Similar to x_mode, but with disabled broadcast. */
493 /* Similar to x_mode, but with operands swapped and disabled broadcast
496 /* 16-byte XMM operand */
498 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
499 memory operand (depending on vector length). Broadcast isn't
502 /* Same as xmmq_mode, but broadcast is allowed. */
503 evex_half_bcst_xmmq_mode,
504 /* XMM register or byte memory operand */
506 /* XMM register or word memory operand */
508 /* XMM register or double word memory operand */
510 /* XMM register or quad word memory operand */
512 /* XMM register or double/quad word memory operand, depending on
515 /* 16-byte XMM, word, double word or quad word operand. */
517 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
519 /* 32-byte YMM operand */
521 /* quad word, ymmword or zmmword memory operand. */
523 /* 32-byte YMM or 16-byte word operand */
525 /* d_mode in 32bit, q_mode in 64bit mode. */
527 /* pair of v_mode operands */
532 /* operand size depends on REX prefixes. */
534 /* registers like dq_mode, memory like w_mode. */
537 /* 4- or 6-byte pointer operand */
540 /* v_mode for stack-related opcodes. */
542 /* non-quad operand size depends on prefixes */
544 /* 16-byte operand */
546 /* registers like dq_mode, memory like b_mode. */
548 /* registers like dq_mode, memory like d_mode. */
550 /* normal vex mode */
552 /* 128bit vex mode */
554 /* 256bit vex mode */
556 /* operand size depends on the VEX.W bit. */
559 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
560 vex_vsib_d_w_dq_mode,
561 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
563 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
564 vex_vsib_q_w_dq_mode,
565 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
568 /* scalar, ignore vector length. */
570 /* like d_mode, ignore vector length. */
572 /* like d_swap_mode, ignore vector length. */
574 /* like q_mode, ignore vector length. */
576 /* like q_swap_mode, ignore vector length. */
578 /* like vex_mode, ignore vector length. */
580 /* like vex_w_dq_mode, ignore vector length. */
581 vex_scalar_w_dq_mode,
583 /* Static rounding. */
585 /* Supress all exceptions. */
588 /* Mask register operand. */
655 #define FLOAT NULL, { { NULL, FLOATCODE } }
657 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
658 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
659 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
660 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
661 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
662 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
663 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
664 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
665 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
666 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
667 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
668 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
669 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
788 MOD_VEX_0F12_PREFIX_0,
790 MOD_VEX_0F16_PREFIX_0,
806 MOD_VEX_0FD7_PREFIX_2,
807 MOD_VEX_0FE7_PREFIX_2,
808 MOD_VEX_0FF0_PREFIX_3,
809 MOD_VEX_0F381A_PREFIX_2,
810 MOD_VEX_0F382A_PREFIX_2,
811 MOD_VEX_0F382C_PREFIX_2,
812 MOD_VEX_0F382D_PREFIX_2,
813 MOD_VEX_0F382E_PREFIX_2,
814 MOD_VEX_0F382F_PREFIX_2,
815 MOD_VEX_0F385A_PREFIX_2,
816 MOD_VEX_0F388C_PREFIX_2,
817 MOD_VEX_0F388E_PREFIX_2,
819 MOD_EVEX_0F10_PREFIX_1,
820 MOD_EVEX_0F10_PREFIX_3,
821 MOD_EVEX_0F11_PREFIX_1,
822 MOD_EVEX_0F11_PREFIX_3,
823 MOD_EVEX_0F12_PREFIX_0,
824 MOD_EVEX_0F16_PREFIX_0,
825 MOD_EVEX_0F38C6_REG_1,
826 MOD_EVEX_0F38C6_REG_2,
827 MOD_EVEX_0F38C6_REG_5,
828 MOD_EVEX_0F38C6_REG_6,
829 MOD_EVEX_0F38C7_REG_1,
830 MOD_EVEX_0F38C7_REG_2,
831 MOD_EVEX_0F38C7_REG_5,
832 MOD_EVEX_0F38C7_REG_6
1023 PREFIX_VEX_0F71_REG_2,
1024 PREFIX_VEX_0F71_REG_4,
1025 PREFIX_VEX_0F71_REG_6,
1026 PREFIX_VEX_0F72_REG_2,
1027 PREFIX_VEX_0F72_REG_4,
1028 PREFIX_VEX_0F72_REG_6,
1029 PREFIX_VEX_0F73_REG_2,
1030 PREFIX_VEX_0F73_REG_3,
1031 PREFIX_VEX_0F73_REG_6,
1032 PREFIX_VEX_0F73_REG_7,
1203 PREFIX_VEX_0F38F3_REG_1,
1204 PREFIX_VEX_0F38F3_REG_2,
1205 PREFIX_VEX_0F38F3_REG_3,
1307 PREFIX_EVEX_0F72_REG_0,
1308 PREFIX_EVEX_0F72_REG_1,
1309 PREFIX_EVEX_0F72_REG_2,
1310 PREFIX_EVEX_0F72_REG_4,
1311 PREFIX_EVEX_0F72_REG_6,
1312 PREFIX_EVEX_0F73_REG_2,
1313 PREFIX_EVEX_0F73_REG_6,
1442 PREFIX_EVEX_0F38C6_REG_1,
1443 PREFIX_EVEX_0F38C6_REG_2,
1444 PREFIX_EVEX_0F38C6_REG_5,
1445 PREFIX_EVEX_0F38C6_REG_6,
1446 PREFIX_EVEX_0F38C7_REG_1,
1447 PREFIX_EVEX_0F38C7_REG_2,
1448 PREFIX_EVEX_0F38C7_REG_5,
1449 PREFIX_EVEX_0F38C7_REG_6,
1521 THREE_BYTE_0F38 = 0,
1549 VEX_LEN_0F10_P_1 = 0,
1553 VEX_LEN_0F12_P_0_M_0,
1554 VEX_LEN_0F12_P_0_M_1,
1557 VEX_LEN_0F16_P_0_M_0,
1558 VEX_LEN_0F16_P_0_M_1,
1604 VEX_LEN_0FAE_R_2_M_0,
1605 VEX_LEN_0FAE_R_3_M_0,
1614 VEX_LEN_0F381A_P_2_M_0,
1617 VEX_LEN_0F385A_P_2_M_0,
1624 VEX_LEN_0F38F3_R_1_P_0,
1625 VEX_LEN_0F38F3_R_2_P_0,
1626 VEX_LEN_0F38F3_R_3_P_0,
1670 VEX_LEN_0FXOP_08_CC,
1671 VEX_LEN_0FXOP_08_CD,
1672 VEX_LEN_0FXOP_08_CE,
1673 VEX_LEN_0FXOP_08_CF,
1674 VEX_LEN_0FXOP_08_EC,
1675 VEX_LEN_0FXOP_08_ED,
1676 VEX_LEN_0FXOP_08_EE,
1677 VEX_LEN_0FXOP_08_EF,
1678 VEX_LEN_0FXOP_09_80,
1712 VEX_W_0F41_P_0_LEN_1,
1713 VEX_W_0F42_P_0_LEN_1,
1714 VEX_W_0F44_P_0_LEN_0,
1715 VEX_W_0F45_P_0_LEN_1,
1716 VEX_W_0F46_P_0_LEN_1,
1717 VEX_W_0F47_P_0_LEN_1,
1718 VEX_W_0F4B_P_2_LEN_1,
1798 VEX_W_0F90_P_0_LEN_0,
1799 VEX_W_0F91_P_0_LEN_0,
1800 VEX_W_0F92_P_0_LEN_0,
1801 VEX_W_0F93_P_0_LEN_0,
1802 VEX_W_0F98_P_0_LEN_0,
1881 VEX_W_0F381A_P_2_M_0,
1893 VEX_W_0F382A_P_2_M_0,
1895 VEX_W_0F382C_P_2_M_0,
1896 VEX_W_0F382D_P_2_M_0,
1897 VEX_W_0F382E_P_2_M_0,
1898 VEX_W_0F382F_P_2_M_0,
1920 VEX_W_0F385A_P_2_M_0,
1948 VEX_W_0F3A30_P_2_LEN_0,
1949 VEX_W_0F3A32_P_2_LEN_0,
1969 EVEX_W_0F10_P_1_M_0,
1970 EVEX_W_0F10_P_1_M_1,
1972 EVEX_W_0F10_P_3_M_0,
1973 EVEX_W_0F10_P_3_M_1,
1975 EVEX_W_0F11_P_1_M_0,
1976 EVEX_W_0F11_P_1_M_1,
1978 EVEX_W_0F11_P_3_M_0,
1979 EVEX_W_0F11_P_3_M_1,
1980 EVEX_W_0F12_P_0_M_0,
1981 EVEX_W_0F12_P_0_M_1,
1991 EVEX_W_0F16_P_0_M_0,
1992 EVEX_W_0F16_P_0_M_1,
2053 EVEX_W_0F72_R_2_P_2,
2054 EVEX_W_0F72_R_6_P_2,
2055 EVEX_W_0F73_R_2_P_2,
2056 EVEX_W_0F73_R_6_P_2,
2129 EVEX_W_0F38C7_R_1_P_2,
2130 EVEX_W_0F38C7_R_2_P_2,
2131 EVEX_W_0F38C7_R_5_P_2,
2132 EVEX_W_0F38C7_R_6_P_2,
2156 typedef void (*op_rtn) (int bytemode, int sizeflag);
2167 /* Upper case letters in the instruction names here are macros.
2168 'A' => print 'b' if no register operands or suffix_always is true
2169 'B' => print 'b' if suffix_always is true
2170 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2172 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2173 suffix_always is true
2174 'E' => print 'e' if 32-bit form of jcxz
2175 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2176 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2177 'H' => print ",pt" or ",pn" branch hint
2178 'I' => honor following macro letter even in Intel mode (implemented only
2179 for some of the macro letters)
2181 'K' => print 'd' or 'q' if rex prefix is present.
2182 'L' => print 'l' if suffix_always is true
2183 'M' => print 'r' if intel_mnemonic is false.
2184 'N' => print 'n' if instruction has no wait "prefix"
2185 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2186 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2187 or suffix_always is true. print 'q' if rex prefix is present.
2188 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2190 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2191 'S' => print 'w', 'l' or 'q' if suffix_always is true
2192 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2193 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2194 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2195 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2196 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2197 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2198 suffix_always is true.
2199 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2200 '!' => change condition from true to false or from false to true.
2201 '%' => add 1 upper case letter to the macro.
2203 2 upper case letter macros:
2204 "XY" => print 'x' or 'y' if no register operands or suffix_always
2206 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2207 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2208 or suffix_always is true
2209 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2210 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2211 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2212 "LW" => print 'd', 'q' depending on the VEX.W bit
2214 Many of the above letters print nothing in Intel mode. See "putop"
2217 Braces '{' and '}', and vertical bars '|', indicate alternative
2218 mnemonic strings for AT&T and Intel. */
2220 static const struct dis386 dis386[] = {
2222 { "addB", { Ebh1, Gb } },
2223 { "addS", { Evh1, Gv } },
2224 { "addB", { Gb, EbS } },
2225 { "addS", { Gv, EvS } },
2226 { "addB", { AL, Ib } },
2227 { "addS", { eAX, Iv } },
2228 { X86_64_TABLE (X86_64_06) },
2229 { X86_64_TABLE (X86_64_07) },
2231 { "orB", { Ebh1, Gb } },
2232 { "orS", { Evh1, Gv } },
2233 { "orB", { Gb, EbS } },
2234 { "orS", { Gv, EvS } },
2235 { "orB", { AL, Ib } },
2236 { "orS", { eAX, Iv } },
2237 { X86_64_TABLE (X86_64_0D) },
2238 { Bad_Opcode }, /* 0x0f extended opcode escape */
2240 { "adcB", { Ebh1, Gb } },
2241 { "adcS", { Evh1, Gv } },
2242 { "adcB", { Gb, EbS } },
2243 { "adcS", { Gv, EvS } },
2244 { "adcB", { AL, Ib } },
2245 { "adcS", { eAX, Iv } },
2246 { X86_64_TABLE (X86_64_16) },
2247 { X86_64_TABLE (X86_64_17) },
2249 { "sbbB", { Ebh1, Gb } },
2250 { "sbbS", { Evh1, Gv } },
2251 { "sbbB", { Gb, EbS } },
2252 { "sbbS", { Gv, EvS } },
2253 { "sbbB", { AL, Ib } },
2254 { "sbbS", { eAX, Iv } },
2255 { X86_64_TABLE (X86_64_1E) },
2256 { X86_64_TABLE (X86_64_1F) },
2258 { "andB", { Ebh1, Gb } },
2259 { "andS", { Evh1, Gv } },
2260 { "andB", { Gb, EbS } },
2261 { "andS", { Gv, EvS } },
2262 { "andB", { AL, Ib } },
2263 { "andS", { eAX, Iv } },
2264 { Bad_Opcode }, /* SEG ES prefix */
2265 { X86_64_TABLE (X86_64_27) },
2267 { "subB", { Ebh1, Gb } },
2268 { "subS", { Evh1, Gv } },
2269 { "subB", { Gb, EbS } },
2270 { "subS", { Gv, EvS } },
2271 { "subB", { AL, Ib } },
2272 { "subS", { eAX, Iv } },
2273 { Bad_Opcode }, /* SEG CS prefix */
2274 { X86_64_TABLE (X86_64_2F) },
2276 { "xorB", { Ebh1, Gb } },
2277 { "xorS", { Evh1, Gv } },
2278 { "xorB", { Gb, EbS } },
2279 { "xorS", { Gv, EvS } },
2280 { "xorB", { AL, Ib } },
2281 { "xorS", { eAX, Iv } },
2282 { Bad_Opcode }, /* SEG SS prefix */
2283 { X86_64_TABLE (X86_64_37) },
2285 { "cmpB", { Eb, Gb } },
2286 { "cmpS", { Ev, Gv } },
2287 { "cmpB", { Gb, EbS } },
2288 { "cmpS", { Gv, EvS } },
2289 { "cmpB", { AL, Ib } },
2290 { "cmpS", { eAX, Iv } },
2291 { Bad_Opcode }, /* SEG DS prefix */
2292 { X86_64_TABLE (X86_64_3F) },
2294 { "inc{S|}", { RMeAX } },
2295 { "inc{S|}", { RMeCX } },
2296 { "inc{S|}", { RMeDX } },
2297 { "inc{S|}", { RMeBX } },
2298 { "inc{S|}", { RMeSP } },
2299 { "inc{S|}", { RMeBP } },
2300 { "inc{S|}", { RMeSI } },
2301 { "inc{S|}", { RMeDI } },
2303 { "dec{S|}", { RMeAX } },
2304 { "dec{S|}", { RMeCX } },
2305 { "dec{S|}", { RMeDX } },
2306 { "dec{S|}", { RMeBX } },
2307 { "dec{S|}", { RMeSP } },
2308 { "dec{S|}", { RMeBP } },
2309 { "dec{S|}", { RMeSI } },
2310 { "dec{S|}", { RMeDI } },
2312 { "pushV", { RMrAX } },
2313 { "pushV", { RMrCX } },
2314 { "pushV", { RMrDX } },
2315 { "pushV", { RMrBX } },
2316 { "pushV", { RMrSP } },
2317 { "pushV", { RMrBP } },
2318 { "pushV", { RMrSI } },
2319 { "pushV", { RMrDI } },
2321 { "popV", { RMrAX } },
2322 { "popV", { RMrCX } },
2323 { "popV", { RMrDX } },
2324 { "popV", { RMrBX } },
2325 { "popV", { RMrSP } },
2326 { "popV", { RMrBP } },
2327 { "popV", { RMrSI } },
2328 { "popV", { RMrDI } },
2330 { X86_64_TABLE (X86_64_60) },
2331 { X86_64_TABLE (X86_64_61) },
2332 { X86_64_TABLE (X86_64_62) },
2333 { X86_64_TABLE (X86_64_63) },
2334 { Bad_Opcode }, /* seg fs */
2335 { Bad_Opcode }, /* seg gs */
2336 { Bad_Opcode }, /* op size prefix */
2337 { Bad_Opcode }, /* adr size prefix */
2339 { "pushT", { sIv } },
2340 { "imulS", { Gv, Ev, Iv } },
2341 { "pushT", { sIbT } },
2342 { "imulS", { Gv, Ev, sIb } },
2343 { "ins{b|}", { Ybr, indirDX } },
2344 { X86_64_TABLE (X86_64_6D) },
2345 { "outs{b|}", { indirDXr, Xb } },
2346 { X86_64_TABLE (X86_64_6F) },
2348 { "joH", { Jb, BND, cond_jump_flag } },
2349 { "jnoH", { Jb, BND, cond_jump_flag } },
2350 { "jbH", { Jb, BND, cond_jump_flag } },
2351 { "jaeH", { Jb, BND, cond_jump_flag } },
2352 { "jeH", { Jb, BND, cond_jump_flag } },
2353 { "jneH", { Jb, BND, cond_jump_flag } },
2354 { "jbeH", { Jb, BND, cond_jump_flag } },
2355 { "jaH", { Jb, BND, cond_jump_flag } },
2357 { "jsH", { Jb, BND, cond_jump_flag } },
2358 { "jnsH", { Jb, BND, cond_jump_flag } },
2359 { "jpH", { Jb, BND, cond_jump_flag } },
2360 { "jnpH", { Jb, BND, cond_jump_flag } },
2361 { "jlH", { Jb, BND, cond_jump_flag } },
2362 { "jgeH", { Jb, BND, cond_jump_flag } },
2363 { "jleH", { Jb, BND, cond_jump_flag } },
2364 { "jgH", { Jb, BND, cond_jump_flag } },
2366 { REG_TABLE (REG_80) },
2367 { REG_TABLE (REG_81) },
2369 { REG_TABLE (REG_82) },
2370 { "testB", { Eb, Gb } },
2371 { "testS", { Ev, Gv } },
2372 { "xchgB", { Ebh2, Gb } },
2373 { "xchgS", { Evh2, Gv } },
2375 { "movB", { Ebh3, Gb } },
2376 { "movS", { Evh3, Gv } },
2377 { "movB", { Gb, EbS } },
2378 { "movS", { Gv, EvS } },
2379 { "movD", { Sv, Sw } },
2380 { MOD_TABLE (MOD_8D) },
2381 { "movD", { Sw, Sv } },
2382 { REG_TABLE (REG_8F) },
2384 { PREFIX_TABLE (PREFIX_90) },
2385 { "xchgS", { RMeCX, eAX } },
2386 { "xchgS", { RMeDX, eAX } },
2387 { "xchgS", { RMeBX, eAX } },
2388 { "xchgS", { RMeSP, eAX } },
2389 { "xchgS", { RMeBP, eAX } },
2390 { "xchgS", { RMeSI, eAX } },
2391 { "xchgS", { RMeDI, eAX } },
2393 { "cW{t|}R", { XX } },
2394 { "cR{t|}O", { XX } },
2395 { X86_64_TABLE (X86_64_9A) },
2396 { Bad_Opcode }, /* fwait */
2397 { "pushfT", { XX } },
2398 { "popfT", { XX } },
2402 { "mov%LB", { AL, Ob } },
2403 { "mov%LS", { eAX, Ov } },
2404 { "mov%LB", { Ob, AL } },
2405 { "mov%LS", { Ov, eAX } },
2406 { "movs{b|}", { Ybr, Xb } },
2407 { "movs{R|}", { Yvr, Xv } },
2408 { "cmps{b|}", { Xb, Yb } },
2409 { "cmps{R|}", { Xv, Yv } },
2411 { "testB", { AL, Ib } },
2412 { "testS", { eAX, Iv } },
2413 { "stosB", { Ybr, AL } },
2414 { "stosS", { Yvr, eAX } },
2415 { "lodsB", { ALr, Xb } },
2416 { "lodsS", { eAXr, Xv } },
2417 { "scasB", { AL, Yb } },
2418 { "scasS", { eAX, Yv } },
2420 { "movB", { RMAL, Ib } },
2421 { "movB", { RMCL, Ib } },
2422 { "movB", { RMDL, Ib } },
2423 { "movB", { RMBL, Ib } },
2424 { "movB", { RMAH, Ib } },
2425 { "movB", { RMCH, Ib } },
2426 { "movB", { RMDH, Ib } },
2427 { "movB", { RMBH, Ib } },
2429 { "mov%LV", { RMeAX, Iv64 } },
2430 { "mov%LV", { RMeCX, Iv64 } },
2431 { "mov%LV", { RMeDX, Iv64 } },
2432 { "mov%LV", { RMeBX, Iv64 } },
2433 { "mov%LV", { RMeSP, Iv64 } },
2434 { "mov%LV", { RMeBP, Iv64 } },
2435 { "mov%LV", { RMeSI, Iv64 } },
2436 { "mov%LV", { RMeDI, Iv64 } },
2438 { REG_TABLE (REG_C0) },
2439 { REG_TABLE (REG_C1) },
2440 { "retT", { Iw, BND } },
2441 { "retT", { BND } },
2442 { X86_64_TABLE (X86_64_C4) },
2443 { X86_64_TABLE (X86_64_C5) },
2444 { REG_TABLE (REG_C6) },
2445 { REG_TABLE (REG_C7) },
2447 { "enterT", { Iw, Ib } },
2448 { "leaveT", { XX } },
2449 { "Jret{|f}P", { Iw } },
2450 { "Jret{|f}P", { XX } },
2453 { X86_64_TABLE (X86_64_CE) },
2454 { "iretP", { XX } },
2456 { REG_TABLE (REG_D0) },
2457 { REG_TABLE (REG_D1) },
2458 { REG_TABLE (REG_D2) },
2459 { REG_TABLE (REG_D3) },
2460 { X86_64_TABLE (X86_64_D4) },
2461 { X86_64_TABLE (X86_64_D5) },
2463 { "xlat", { DSBX } },
2474 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
2475 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
2476 { "loopFH", { Jb, XX, loop_jcxz_flag } },
2477 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
2478 { "inB", { AL, Ib } },
2479 { "inG", { zAX, Ib } },
2480 { "outB", { Ib, AL } },
2481 { "outG", { Ib, zAX } },
2483 { "callT", { Jv, BND } },
2484 { "jmpT", { Jv, BND } },
2485 { X86_64_TABLE (X86_64_EA) },
2486 { "jmp", { Jb, BND } },
2487 { "inB", { AL, indirDX } },
2488 { "inG", { zAX, indirDX } },
2489 { "outB", { indirDX, AL } },
2490 { "outG", { indirDX, zAX } },
2492 { Bad_Opcode }, /* lock prefix */
2493 { "icebp", { XX } },
2494 { Bad_Opcode }, /* repne */
2495 { Bad_Opcode }, /* repz */
2498 { REG_TABLE (REG_F6) },
2499 { REG_TABLE (REG_F7) },
2507 { REG_TABLE (REG_FE) },
2508 { REG_TABLE (REG_FF) },
2511 static const struct dis386 dis386_twobyte[] = {
2513 { REG_TABLE (REG_0F00 ) },
2514 { REG_TABLE (REG_0F01 ) },
2515 { "larS", { Gv, Ew } },
2516 { "lslS", { Gv, Ew } },
2518 { "syscall", { XX } },
2520 { "sysretP", { XX } },
2523 { "wbinvd", { XX } },
2527 { REG_TABLE (REG_0F0D) },
2528 { "femms", { XX } },
2529 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
2531 { PREFIX_TABLE (PREFIX_0F10) },
2532 { PREFIX_TABLE (PREFIX_0F11) },
2533 { PREFIX_TABLE (PREFIX_0F12) },
2534 { MOD_TABLE (MOD_0F13) },
2535 { "unpcklpX", { XM, EXx } },
2536 { "unpckhpX", { XM, EXx } },
2537 { PREFIX_TABLE (PREFIX_0F16) },
2538 { MOD_TABLE (MOD_0F17) },
2540 { REG_TABLE (REG_0F18) },
2542 { PREFIX_TABLE (PREFIX_0F1A) },
2543 { PREFIX_TABLE (PREFIX_0F1B) },
2549 { MOD_TABLE (MOD_0F20) },
2550 { MOD_TABLE (MOD_0F21) },
2551 { MOD_TABLE (MOD_0F22) },
2552 { MOD_TABLE (MOD_0F23) },
2553 { MOD_TABLE (MOD_0F24) },
2555 { MOD_TABLE (MOD_0F26) },
2558 { "movapX", { XM, EXx } },
2559 { "movapX", { EXxS, XM } },
2560 { PREFIX_TABLE (PREFIX_0F2A) },
2561 { PREFIX_TABLE (PREFIX_0F2B) },
2562 { PREFIX_TABLE (PREFIX_0F2C) },
2563 { PREFIX_TABLE (PREFIX_0F2D) },
2564 { PREFIX_TABLE (PREFIX_0F2E) },
2565 { PREFIX_TABLE (PREFIX_0F2F) },
2567 { "wrmsr", { XX } },
2568 { "rdtsc", { XX } },
2569 { "rdmsr", { XX } },
2570 { "rdpmc", { XX } },
2571 { "sysenter", { XX } },
2572 { "sysexit", { XX } },
2574 { "getsec", { XX } },
2576 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2578 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2585 { "cmovoS", { Gv, Ev } },
2586 { "cmovnoS", { Gv, Ev } },
2587 { "cmovbS", { Gv, Ev } },
2588 { "cmovaeS", { Gv, Ev } },
2589 { "cmoveS", { Gv, Ev } },
2590 { "cmovneS", { Gv, Ev } },
2591 { "cmovbeS", { Gv, Ev } },
2592 { "cmovaS", { Gv, Ev } },
2594 { "cmovsS", { Gv, Ev } },
2595 { "cmovnsS", { Gv, Ev } },
2596 { "cmovpS", { Gv, Ev } },
2597 { "cmovnpS", { Gv, Ev } },
2598 { "cmovlS", { Gv, Ev } },
2599 { "cmovgeS", { Gv, Ev } },
2600 { "cmovleS", { Gv, Ev } },
2601 { "cmovgS", { Gv, Ev } },
2603 { MOD_TABLE (MOD_0F51) },
2604 { PREFIX_TABLE (PREFIX_0F51) },
2605 { PREFIX_TABLE (PREFIX_0F52) },
2606 { PREFIX_TABLE (PREFIX_0F53) },
2607 { "andpX", { XM, EXx } },
2608 { "andnpX", { XM, EXx } },
2609 { "orpX", { XM, EXx } },
2610 { "xorpX", { XM, EXx } },
2612 { PREFIX_TABLE (PREFIX_0F58) },
2613 { PREFIX_TABLE (PREFIX_0F59) },
2614 { PREFIX_TABLE (PREFIX_0F5A) },
2615 { PREFIX_TABLE (PREFIX_0F5B) },
2616 { PREFIX_TABLE (PREFIX_0F5C) },
2617 { PREFIX_TABLE (PREFIX_0F5D) },
2618 { PREFIX_TABLE (PREFIX_0F5E) },
2619 { PREFIX_TABLE (PREFIX_0F5F) },
2621 { PREFIX_TABLE (PREFIX_0F60) },
2622 { PREFIX_TABLE (PREFIX_0F61) },
2623 { PREFIX_TABLE (PREFIX_0F62) },
2624 { "packsswb", { MX, EM } },
2625 { "pcmpgtb", { MX, EM } },
2626 { "pcmpgtw", { MX, EM } },
2627 { "pcmpgtd", { MX, EM } },
2628 { "packuswb", { MX, EM } },
2630 { "punpckhbw", { MX, EM } },
2631 { "punpckhwd", { MX, EM } },
2632 { "punpckhdq", { MX, EM } },
2633 { "packssdw", { MX, EM } },
2634 { PREFIX_TABLE (PREFIX_0F6C) },
2635 { PREFIX_TABLE (PREFIX_0F6D) },
2636 { "movK", { MX, Edq } },
2637 { PREFIX_TABLE (PREFIX_0F6F) },
2639 { PREFIX_TABLE (PREFIX_0F70) },
2640 { REG_TABLE (REG_0F71) },
2641 { REG_TABLE (REG_0F72) },
2642 { REG_TABLE (REG_0F73) },
2643 { "pcmpeqb", { MX, EM } },
2644 { "pcmpeqw", { MX, EM } },
2645 { "pcmpeqd", { MX, EM } },
2648 { PREFIX_TABLE (PREFIX_0F78) },
2649 { PREFIX_TABLE (PREFIX_0F79) },
2650 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2652 { PREFIX_TABLE (PREFIX_0F7C) },
2653 { PREFIX_TABLE (PREFIX_0F7D) },
2654 { PREFIX_TABLE (PREFIX_0F7E) },
2655 { PREFIX_TABLE (PREFIX_0F7F) },
2657 { "joH", { Jv, BND, cond_jump_flag } },
2658 { "jnoH", { Jv, BND, cond_jump_flag } },
2659 { "jbH", { Jv, BND, cond_jump_flag } },
2660 { "jaeH", { Jv, BND, cond_jump_flag } },
2661 { "jeH", { Jv, BND, cond_jump_flag } },
2662 { "jneH", { Jv, BND, cond_jump_flag } },
2663 { "jbeH", { Jv, BND, cond_jump_flag } },
2664 { "jaH", { Jv, BND, cond_jump_flag } },
2666 { "jsH", { Jv, BND, cond_jump_flag } },
2667 { "jnsH", { Jv, BND, cond_jump_flag } },
2668 { "jpH", { Jv, BND, cond_jump_flag } },
2669 { "jnpH", { Jv, BND, cond_jump_flag } },
2670 { "jlH", { Jv, BND, cond_jump_flag } },
2671 { "jgeH", { Jv, BND, cond_jump_flag } },
2672 { "jleH", { Jv, BND, cond_jump_flag } },
2673 { "jgH", { Jv, BND, cond_jump_flag } },
2676 { "setno", { Eb } },
2678 { "setae", { Eb } },
2680 { "setne", { Eb } },
2681 { "setbe", { Eb } },
2685 { "setns", { Eb } },
2687 { "setnp", { Eb } },
2689 { "setge", { Eb } },
2690 { "setle", { Eb } },
2693 { "pushT", { fs } },
2695 { "cpuid", { XX } },
2696 { "btS", { Ev, Gv } },
2697 { "shldS", { Ev, Gv, Ib } },
2698 { "shldS", { Ev, Gv, CL } },
2699 { REG_TABLE (REG_0FA6) },
2700 { REG_TABLE (REG_0FA7) },
2702 { "pushT", { gs } },
2705 { "btsS", { Evh1, Gv } },
2706 { "shrdS", { Ev, Gv, Ib } },
2707 { "shrdS", { Ev, Gv, CL } },
2708 { REG_TABLE (REG_0FAE) },
2709 { "imulS", { Gv, Ev } },
2711 { "cmpxchgB", { Ebh1, Gb } },
2712 { "cmpxchgS", { Evh1, Gv } },
2713 { MOD_TABLE (MOD_0FB2) },
2714 { "btrS", { Evh1, Gv } },
2715 { MOD_TABLE (MOD_0FB4) },
2716 { MOD_TABLE (MOD_0FB5) },
2717 { "movz{bR|x}", { Gv, Eb } },
2718 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
2720 { PREFIX_TABLE (PREFIX_0FB8) },
2722 { REG_TABLE (REG_0FBA) },
2723 { "btcS", { Evh1, Gv } },
2724 { PREFIX_TABLE (PREFIX_0FBC) },
2725 { PREFIX_TABLE (PREFIX_0FBD) },
2726 { "movs{bR|x}", { Gv, Eb } },
2727 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
2729 { "xaddB", { Ebh1, Gb } },
2730 { "xaddS", { Evh1, Gv } },
2731 { PREFIX_TABLE (PREFIX_0FC2) },
2732 { PREFIX_TABLE (PREFIX_0FC3) },
2733 { "pinsrw", { MX, Edqw, Ib } },
2734 { "pextrw", { Gdq, MS, Ib } },
2735 { "shufpX", { XM, EXx, Ib } },
2736 { REG_TABLE (REG_0FC7) },
2738 { "bswap", { RMeAX } },
2739 { "bswap", { RMeCX } },
2740 { "bswap", { RMeDX } },
2741 { "bswap", { RMeBX } },
2742 { "bswap", { RMeSP } },
2743 { "bswap", { RMeBP } },
2744 { "bswap", { RMeSI } },
2745 { "bswap", { RMeDI } },
2747 { PREFIX_TABLE (PREFIX_0FD0) },
2748 { "psrlw", { MX, EM } },
2749 { "psrld", { MX, EM } },
2750 { "psrlq", { MX, EM } },
2751 { "paddq", { MX, EM } },
2752 { "pmullw", { MX, EM } },
2753 { PREFIX_TABLE (PREFIX_0FD6) },
2754 { MOD_TABLE (MOD_0FD7) },
2756 { "psubusb", { MX, EM } },
2757 { "psubusw", { MX, EM } },
2758 { "pminub", { MX, EM } },
2759 { "pand", { MX, EM } },
2760 { "paddusb", { MX, EM } },
2761 { "paddusw", { MX, EM } },
2762 { "pmaxub", { MX, EM } },
2763 { "pandn", { MX, EM } },
2765 { "pavgb", { MX, EM } },
2766 { "psraw", { MX, EM } },
2767 { "psrad", { MX, EM } },
2768 { "pavgw", { MX, EM } },
2769 { "pmulhuw", { MX, EM } },
2770 { "pmulhw", { MX, EM } },
2771 { PREFIX_TABLE (PREFIX_0FE6) },
2772 { PREFIX_TABLE (PREFIX_0FE7) },
2774 { "psubsb", { MX, EM } },
2775 { "psubsw", { MX, EM } },
2776 { "pminsw", { MX, EM } },
2777 { "por", { MX, EM } },
2778 { "paddsb", { MX, EM } },
2779 { "paddsw", { MX, EM } },
2780 { "pmaxsw", { MX, EM } },
2781 { "pxor", { MX, EM } },
2783 { PREFIX_TABLE (PREFIX_0FF0) },
2784 { "psllw", { MX, EM } },
2785 { "pslld", { MX, EM } },
2786 { "psllq", { MX, EM } },
2787 { "pmuludq", { MX, EM } },
2788 { "pmaddwd", { MX, EM } },
2789 { "psadbw", { MX, EM } },
2790 { PREFIX_TABLE (PREFIX_0FF7) },
2792 { "psubb", { MX, EM } },
2793 { "psubw", { MX, EM } },
2794 { "psubd", { MX, EM } },
2795 { "psubq", { MX, EM } },
2796 { "paddb", { MX, EM } },
2797 { "paddw", { MX, EM } },
2798 { "paddd", { MX, EM } },
2802 static const unsigned char onebyte_has_modrm[256] = {
2803 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2804 /* ------------------------------- */
2805 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2806 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2807 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2808 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2809 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2810 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2811 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2812 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2813 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2814 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2815 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2816 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2817 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2818 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2819 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2820 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2821 /* ------------------------------- */
2822 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2825 static const unsigned char twobyte_has_modrm[256] = {
2826 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2827 /* ------------------------------- */
2828 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2829 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2830 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2831 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2832 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2833 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2834 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2835 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2836 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2837 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2838 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2839 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2840 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2841 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2842 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2843 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
2844 /* ------------------------------- */
2845 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2848 static const unsigned char twobyte_has_mandatory_prefix[256] = {
2849 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2850 /* ------------------------------- */
2851 /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
2852 /* 10 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 1f */
2853 /* 20 */ 0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0, /* 2f */
2854 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2855 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
2856 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2857 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2858 /* 70 */ 1,0,0,0,1,1,1,1,0,0,1,1,1,1,1,1, /* 7f */
2859 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2860 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
2861 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
2862 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
2863 /* c0 */ 0,0,1,1,1,1,1,0,0,0,0,0,0,0,0,0, /* cf */
2864 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2865 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2866 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
2867 /* ------------------------------- */
2868 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2871 static char obuf[100];
2873 static char *mnemonicendp;
2874 static char scratchbuf[100];
2875 static unsigned char *start_codep;
2876 static unsigned char *insn_codep;
2877 static unsigned char *codep;
2878 static unsigned char *end_codep;
2879 static int last_lock_prefix;
2880 static int last_repz_prefix;
2881 static int last_repnz_prefix;
2882 static int last_data_prefix;
2883 static int last_addr_prefix;
2884 static int last_rex_prefix;
2885 static int last_seg_prefix;
2886 /* The PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is mandatory. */
2887 static int mandatory_prefix;
2888 /* The active segment register prefix. */
2889 static int active_seg_prefix;
2890 #define MAX_CODE_LENGTH 15
2891 /* We can up to 14 prefixes since the maximum instruction length is
2893 static int all_prefixes[MAX_CODE_LENGTH - 1];
2894 static disassemble_info *the_info;
2902 static unsigned char need_modrm;
2912 int register_specifier;
2919 int mask_register_specifier;
2925 static unsigned char need_vex;
2926 static unsigned char need_vex_reg;
2927 static unsigned char vex_w_done;
2935 /* If we are accessing mod/rm/reg without need_modrm set, then the
2936 values are stale. Hitting this abort likely indicates that you
2937 need to update onebyte_has_modrm or twobyte_has_modrm. */
2938 #define MODRM_CHECK if (!need_modrm) abort ()
2940 static const char **names64;
2941 static const char **names32;
2942 static const char **names16;
2943 static const char **names8;
2944 static const char **names8rex;
2945 static const char **names_seg;
2946 static const char *index64;
2947 static const char *index32;
2948 static const char **index16;
2949 static const char **names_bnd;
2951 static const char *intel_names64[] = {
2952 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2953 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2955 static const char *intel_names32[] = {
2956 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2957 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2959 static const char *intel_names16[] = {
2960 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2961 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2963 static const char *intel_names8[] = {
2964 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2966 static const char *intel_names8rex[] = {
2967 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2968 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2970 static const char *intel_names_seg[] = {
2971 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2973 static const char *intel_index64 = "riz";
2974 static const char *intel_index32 = "eiz";
2975 static const char *intel_index16[] = {
2976 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2979 static const char *att_names64[] = {
2980 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2981 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2983 static const char *att_names32[] = {
2984 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2985 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2987 static const char *att_names16[] = {
2988 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2989 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2991 static const char *att_names8[] = {
2992 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2994 static const char *att_names8rex[] = {
2995 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2996 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2998 static const char *att_names_seg[] = {
2999 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3001 static const char *att_index64 = "%riz";
3002 static const char *att_index32 = "%eiz";
3003 static const char *att_index16[] = {
3004 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3007 static const char **names_mm;
3008 static const char *intel_names_mm[] = {
3009 "mm0", "mm1", "mm2", "mm3",
3010 "mm4", "mm5", "mm6", "mm7"
3012 static const char *att_names_mm[] = {
3013 "%mm0", "%mm1", "%mm2", "%mm3",
3014 "%mm4", "%mm5", "%mm6", "%mm7"
3017 static const char *intel_names_bnd[] = {
3018 "bnd0", "bnd1", "bnd2", "bnd3"
3021 static const char *att_names_bnd[] = {
3022 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3025 static const char **names_xmm;
3026 static const char *intel_names_xmm[] = {
3027 "xmm0", "xmm1", "xmm2", "xmm3",
3028 "xmm4", "xmm5", "xmm6", "xmm7",
3029 "xmm8", "xmm9", "xmm10", "xmm11",
3030 "xmm12", "xmm13", "xmm14", "xmm15",
3031 "xmm16", "xmm17", "xmm18", "xmm19",
3032 "xmm20", "xmm21", "xmm22", "xmm23",
3033 "xmm24", "xmm25", "xmm26", "xmm27",
3034 "xmm28", "xmm29", "xmm30", "xmm31"
3036 static const char *att_names_xmm[] = {
3037 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3038 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3039 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3040 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3041 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3042 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3043 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3044 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3047 static const char **names_ymm;
3048 static const char *intel_names_ymm[] = {
3049 "ymm0", "ymm1", "ymm2", "ymm3",
3050 "ymm4", "ymm5", "ymm6", "ymm7",
3051 "ymm8", "ymm9", "ymm10", "ymm11",
3052 "ymm12", "ymm13", "ymm14", "ymm15",
3053 "ymm16", "ymm17", "ymm18", "ymm19",
3054 "ymm20", "ymm21", "ymm22", "ymm23",
3055 "ymm24", "ymm25", "ymm26", "ymm27",
3056 "ymm28", "ymm29", "ymm30", "ymm31"
3058 static const char *att_names_ymm[] = {
3059 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3060 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3061 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3062 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3063 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3064 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3065 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3066 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3069 static const char **names_zmm;
3070 static const char *intel_names_zmm[] = {
3071 "zmm0", "zmm1", "zmm2", "zmm3",
3072 "zmm4", "zmm5", "zmm6", "zmm7",
3073 "zmm8", "zmm9", "zmm10", "zmm11",
3074 "zmm12", "zmm13", "zmm14", "zmm15",
3075 "zmm16", "zmm17", "zmm18", "zmm19",
3076 "zmm20", "zmm21", "zmm22", "zmm23",
3077 "zmm24", "zmm25", "zmm26", "zmm27",
3078 "zmm28", "zmm29", "zmm30", "zmm31"
3080 static const char *att_names_zmm[] = {
3081 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3082 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3083 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3084 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3085 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3086 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3087 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3088 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3091 static const char **names_mask;
3092 static const char *intel_names_mask[] = {
3093 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3095 static const char *att_names_mask[] = {
3096 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3099 static const char *names_rounding[] =
3107 static const struct dis386 reg_table[][8] = {
3110 { "addA", { Ebh1, Ib } },
3111 { "orA", { Ebh1, Ib } },
3112 { "adcA", { Ebh1, Ib } },
3113 { "sbbA", { Ebh1, Ib } },
3114 { "andA", { Ebh1, Ib } },
3115 { "subA", { Ebh1, Ib } },
3116 { "xorA", { Ebh1, Ib } },
3117 { "cmpA", { Eb, Ib } },
3121 { "addQ", { Evh1, Iv } },
3122 { "orQ", { Evh1, Iv } },
3123 { "adcQ", { Evh1, Iv } },
3124 { "sbbQ", { Evh1, Iv } },
3125 { "andQ", { Evh1, Iv } },
3126 { "subQ", { Evh1, Iv } },
3127 { "xorQ", { Evh1, Iv } },
3128 { "cmpQ", { Ev, Iv } },
3132 { "addQ", { Evh1, sIb } },
3133 { "orQ", { Evh1, sIb } },
3134 { "adcQ", { Evh1, sIb } },
3135 { "sbbQ", { Evh1, sIb } },
3136 { "andQ", { Evh1, sIb } },
3137 { "subQ", { Evh1, sIb } },
3138 { "xorQ", { Evh1, sIb } },
3139 { "cmpQ", { Ev, sIb } },
3143 { "popU", { stackEv } },
3144 { XOP_8F_TABLE (XOP_09) },
3148 { XOP_8F_TABLE (XOP_09) },
3152 { "rolA", { Eb, Ib } },
3153 { "rorA", { Eb, Ib } },
3154 { "rclA", { Eb, Ib } },
3155 { "rcrA", { Eb, Ib } },
3156 { "shlA", { Eb, Ib } },
3157 { "shrA", { Eb, Ib } },
3159 { "sarA", { Eb, Ib } },
3163 { "rolQ", { Ev, Ib } },
3164 { "rorQ", { Ev, Ib } },
3165 { "rclQ", { Ev, Ib } },
3166 { "rcrQ", { Ev, Ib } },
3167 { "shlQ", { Ev, Ib } },
3168 { "shrQ", { Ev, Ib } },
3170 { "sarQ", { Ev, Ib } },
3174 { "movA", { Ebh3, Ib } },
3181 { MOD_TABLE (MOD_C6_REG_7) },
3185 { "movQ", { Evh3, Iv } },
3192 { MOD_TABLE (MOD_C7_REG_7) },
3196 { "rolA", { Eb, I1 } },
3197 { "rorA", { Eb, I1 } },
3198 { "rclA", { Eb, I1 } },
3199 { "rcrA", { Eb, I1 } },
3200 { "shlA", { Eb, I1 } },
3201 { "shrA", { Eb, I1 } },
3203 { "sarA", { Eb, I1 } },
3207 { "rolQ", { Ev, I1 } },
3208 { "rorQ", { Ev, I1 } },
3209 { "rclQ", { Ev, I1 } },
3210 { "rcrQ", { Ev, I1 } },
3211 { "shlQ", { Ev, I1 } },
3212 { "shrQ", { Ev, I1 } },
3214 { "sarQ", { Ev, I1 } },
3218 { "rolA", { Eb, CL } },
3219 { "rorA", { Eb, CL } },
3220 { "rclA", { Eb, CL } },
3221 { "rcrA", { Eb, CL } },
3222 { "shlA", { Eb, CL } },
3223 { "shrA", { Eb, CL } },
3225 { "sarA", { Eb, CL } },
3229 { "rolQ", { Ev, CL } },
3230 { "rorQ", { Ev, CL } },
3231 { "rclQ", { Ev, CL } },
3232 { "rcrQ", { Ev, CL } },
3233 { "shlQ", { Ev, CL } },
3234 { "shrQ", { Ev, CL } },
3236 { "sarQ", { Ev, CL } },
3240 { "testA", { Eb, Ib } },
3242 { "notA", { Ebh1 } },
3243 { "negA", { Ebh1 } },
3244 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
3245 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
3246 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
3247 { "idivA", { Eb } }, /* and idiv for consistency. */
3251 { "testQ", { Ev, Iv } },
3253 { "notQ", { Evh1 } },
3254 { "negQ", { Evh1 } },
3255 { "mulQ", { Ev } }, /* Don't print the implicit register. */
3256 { "imulQ", { Ev } },
3258 { "idivQ", { Ev } },
3262 { "incA", { Ebh1 } },
3263 { "decA", { Ebh1 } },
3267 { "incQ", { Evh1 } },
3268 { "decQ", { Evh1 } },
3269 { "call{T|}", { indirEv, BND } },
3270 { MOD_TABLE (MOD_FF_REG_3) },
3271 { "jmp{T|}", { indirEv, BND } },
3272 { MOD_TABLE (MOD_FF_REG_5) },
3273 { "pushU", { stackEv } },
3278 { "sldtD", { Sv } },
3289 { MOD_TABLE (MOD_0F01_REG_0) },
3290 { MOD_TABLE (MOD_0F01_REG_1) },
3291 { MOD_TABLE (MOD_0F01_REG_2) },
3292 { MOD_TABLE (MOD_0F01_REG_3) },
3293 { "smswD", { Sv } },
3296 { MOD_TABLE (MOD_0F01_REG_7) },
3300 { "prefetch", { Mb } },
3301 { "prefetchw", { Mb } },
3302 { "prefetchwt1", { Mb } },
3303 { "prefetch", { Mb } },
3304 { "prefetch", { Mb } },
3305 { "prefetch", { Mb } },
3306 { "prefetch", { Mb } },
3307 { "prefetch", { Mb } },
3311 { MOD_TABLE (MOD_0F18_REG_0) },
3312 { MOD_TABLE (MOD_0F18_REG_1) },
3313 { MOD_TABLE (MOD_0F18_REG_2) },
3314 { MOD_TABLE (MOD_0F18_REG_3) },
3315 { MOD_TABLE (MOD_0F18_REG_4) },
3316 { MOD_TABLE (MOD_0F18_REG_5) },
3317 { MOD_TABLE (MOD_0F18_REG_6) },
3318 { MOD_TABLE (MOD_0F18_REG_7) },
3324 { MOD_TABLE (MOD_0F71_REG_2) },
3326 { MOD_TABLE (MOD_0F71_REG_4) },
3328 { MOD_TABLE (MOD_0F71_REG_6) },
3334 { MOD_TABLE (MOD_0F72_REG_2) },
3336 { MOD_TABLE (MOD_0F72_REG_4) },
3338 { MOD_TABLE (MOD_0F72_REG_6) },
3344 { MOD_TABLE (MOD_0F73_REG_2) },
3345 { MOD_TABLE (MOD_0F73_REG_3) },
3348 { MOD_TABLE (MOD_0F73_REG_6) },
3349 { MOD_TABLE (MOD_0F73_REG_7) },
3353 { "montmul", { { OP_0f07, 0 } } },
3354 { "xsha1", { { OP_0f07, 0 } } },
3355 { "xsha256", { { OP_0f07, 0 } } },
3359 { "xstore-rng", { { OP_0f07, 0 } } },
3360 { "xcrypt-ecb", { { OP_0f07, 0 } } },
3361 { "xcrypt-cbc", { { OP_0f07, 0 } } },
3362 { "xcrypt-ctr", { { OP_0f07, 0 } } },
3363 { "xcrypt-cfb", { { OP_0f07, 0 } } },
3364 { "xcrypt-ofb", { { OP_0f07, 0 } } },
3368 { MOD_TABLE (MOD_0FAE_REG_0) },
3369 { MOD_TABLE (MOD_0FAE_REG_1) },
3370 { MOD_TABLE (MOD_0FAE_REG_2) },
3371 { MOD_TABLE (MOD_0FAE_REG_3) },
3372 { MOD_TABLE (MOD_0FAE_REG_4) },
3373 { MOD_TABLE (MOD_0FAE_REG_5) },
3374 { MOD_TABLE (MOD_0FAE_REG_6) },
3375 { MOD_TABLE (MOD_0FAE_REG_7) },
3383 { "btQ", { Ev, Ib } },
3384 { "btsQ", { Evh1, Ib } },
3385 { "btrQ", { Evh1, Ib } },
3386 { "btcQ", { Evh1, Ib } },
3391 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
3393 { MOD_TABLE (MOD_0FC7_REG_3) },
3394 { MOD_TABLE (MOD_0FC7_REG_4) },
3395 { MOD_TABLE (MOD_0FC7_REG_5) },
3396 { MOD_TABLE (MOD_0FC7_REG_6) },
3397 { MOD_TABLE (MOD_0FC7_REG_7) },
3403 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3405 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3407 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3413 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3415 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3417 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3423 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3424 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3427 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3428 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3434 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3435 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3437 /* REG_VEX_0F38F3 */
3440 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3441 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3442 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3446 { "llwpcb", { { OP_LWPCB_E, 0 } } },
3447 { "slwpcb", { { OP_LWPCB_E, 0 } } },
3451 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
3452 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
3454 /* REG_XOP_TBM_01 */
3457 { "blcfill", { { OP_LWP_E, 0 }, Ev } },
3458 { "blsfill", { { OP_LWP_E, 0 }, Ev } },
3459 { "blcs", { { OP_LWP_E, 0 }, Ev } },
3460 { "tzmsk", { { OP_LWP_E, 0 }, Ev } },
3461 { "blcic", { { OP_LWP_E, 0 }, Ev } },
3462 { "blsic", { { OP_LWP_E, 0 }, Ev } },
3463 { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
3465 /* REG_XOP_TBM_02 */
3468 { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
3473 { "blci", { { OP_LWP_E, 0 }, Ev } },
3475 #define NEED_REG_TABLE
3476 #include "i386-dis-evex.h"
3477 #undef NEED_REG_TABLE
3480 static const struct dis386 prefix_table[][4] = {
3483 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3484 { "pause", { XX } },
3485 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3490 { "movups", { XM, EXx } },
3491 { "movss", { XM, EXd } },
3492 { "movupd", { XM, EXx } },
3493 { "movsd", { XM, EXq } },
3498 { "movups", { EXxS, XM } },
3499 { "movss", { EXdS, XM } },
3500 { "movupd", { EXxS, XM } },
3501 { "movsd", { EXqS, XM } },
3506 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3507 { "movsldup", { XM, EXx } },
3508 { "movlpd", { XM, EXq } },
3509 { "movddup", { XM, EXq } },
3514 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3515 { "movshdup", { XM, EXx } },
3516 { "movhpd", { XM, EXq } },
3521 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3522 { "bndcl", { Gbnd, Ev_bnd } },
3523 { "bndmov", { Gbnd, Ebnd } },
3524 { "bndcu", { Gbnd, Ev_bnd } },
3529 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3530 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3531 { "bndmov", { Ebnd, Gbnd } },
3532 { "bndcn", { Gbnd, Ev_bnd } },
3537 { "cvtpi2ps", { XM, EMCq } },
3538 { "cvtsi2ss%LQ", { XM, Ev } },
3539 { "cvtpi2pd", { XM, EMCq } },
3540 { "cvtsi2sd%LQ", { XM, Ev } },
3545 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3546 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3547 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3548 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3553 { "cvttps2pi", { MXC, EXq } },
3554 { "cvttss2siY", { Gv, EXd } },
3555 { "cvttpd2pi", { MXC, EXx } },
3556 { "cvttsd2siY", { Gv, EXq } },
3561 { "cvtps2pi", { MXC, EXq } },
3562 { "cvtss2siY", { Gv, EXd } },
3563 { "cvtpd2pi", { MXC, EXx } },
3564 { "cvtsd2siY", { Gv, EXq } },
3569 { "ucomiss",{ XM, EXd } },
3571 { "ucomisd",{ XM, EXq } },
3576 { "comiss", { XM, EXd } },
3578 { "comisd", { XM, EXq } },
3583 { "sqrtps", { XM, EXx } },
3584 { "sqrtss", { XM, EXd } },
3585 { "sqrtpd", { XM, EXx } },
3586 { "sqrtsd", { XM, EXq } },
3591 { "rsqrtps",{ XM, EXx } },
3592 { "rsqrtss",{ XM, EXd } },
3597 { "rcpps", { XM, EXx } },
3598 { "rcpss", { XM, EXd } },
3603 { "addps", { XM, EXx } },
3604 { "addss", { XM, EXd } },
3605 { "addpd", { XM, EXx } },
3606 { "addsd", { XM, EXq } },
3611 { "mulps", { XM, EXx } },
3612 { "mulss", { XM, EXd } },
3613 { "mulpd", { XM, EXx } },
3614 { "mulsd", { XM, EXq } },
3619 { "cvtps2pd", { XM, EXq } },
3620 { "cvtss2sd", { XM, EXd } },
3621 { "cvtpd2ps", { XM, EXx } },
3622 { "cvtsd2ss", { XM, EXq } },
3627 { "cvtdq2ps", { XM, EXx } },
3628 { "cvttps2dq", { XM, EXx } },
3629 { "cvtps2dq", { XM, EXx } },
3634 { "subps", { XM, EXx } },
3635 { "subss", { XM, EXd } },
3636 { "subpd", { XM, EXx } },
3637 { "subsd", { XM, EXq } },
3642 { "minps", { XM, EXx } },
3643 { "minss", { XM, EXd } },
3644 { "minpd", { XM, EXx } },
3645 { "minsd", { XM, EXq } },
3650 { "divps", { XM, EXx } },
3651 { "divss", { XM, EXd } },
3652 { "divpd", { XM, EXx } },
3653 { "divsd", { XM, EXq } },
3658 { "maxps", { XM, EXx } },
3659 { "maxss", { XM, EXd } },
3660 { "maxpd", { XM, EXx } },
3661 { "maxsd", { XM, EXq } },
3666 { "punpcklbw",{ MX, EMd } },
3668 { "punpcklbw",{ MX, EMx } },
3673 { "punpcklwd",{ MX, EMd } },
3675 { "punpcklwd",{ MX, EMx } },
3680 { "punpckldq",{ MX, EMd } },
3682 { "punpckldq",{ MX, EMx } },
3689 { "punpcklqdq", { XM, EXx } },
3696 { "punpckhqdq", { XM, EXx } },
3701 { "movq", { MX, EM } },
3702 { "movdqu", { XM, EXx } },
3703 { "movdqa", { XM, EXx } },
3708 { "pshufw", { MX, EM, Ib } },
3709 { "pshufhw",{ XM, EXx, Ib } },
3710 { "pshufd", { XM, EXx, Ib } },
3711 { "pshuflw",{ XM, EXx, Ib } },
3714 /* PREFIX_0F73_REG_3 */
3718 { "psrldq", { XS, Ib } },
3721 /* PREFIX_0F73_REG_7 */
3725 { "pslldq", { XS, Ib } },
3730 {"vmread", { Em, Gm } },
3732 {"extrq", { XS, Ib, Ib } },
3733 {"insertq", { XM, XS, Ib, Ib } },
3738 {"vmwrite", { Gm, Em } },
3740 {"extrq", { XM, XS } },
3741 {"insertq", { XM, XS } },
3748 { "haddpd", { XM, EXx } },
3749 { "haddps", { XM, EXx } },
3756 { "hsubpd", { XM, EXx } },
3757 { "hsubps", { XM, EXx } },
3762 { "movK", { Edq, MX } },
3763 { "movq", { XM, EXq } },
3764 { "movK", { Edq, XM } },
3769 { "movq", { EMS, MX } },
3770 { "movdqu", { EXxS, XM } },
3771 { "movdqa", { EXxS, XM } },
3774 /* PREFIX_0FAE_REG_0 */
3777 { "rdfsbase", { Ev } },
3780 /* PREFIX_0FAE_REG_1 */
3783 { "rdgsbase", { Ev } },
3786 /* PREFIX_0FAE_REG_2 */
3789 { "wrfsbase", { Ev } },
3792 /* PREFIX_0FAE_REG_3 */
3795 { "wrgsbase", { Ev } },
3798 /* PREFIX_0FAE_REG_7 */
3800 { "clflush", { Mb } },
3802 { "clflushopt", { Mb } },
3808 { "popcntS", { Gv, Ev } },
3813 { "bsfS", { Gv, Ev } },
3814 { "tzcntS", { Gv, Ev } },
3815 { "bsfS", { Gv, Ev } },
3820 { "bsrS", { Gv, Ev } },
3821 { "lzcntS", { Gv, Ev } },
3822 { "bsrS", { Gv, Ev } },
3827 { "cmpps", { XM, EXx, CMP } },
3828 { "cmpss", { XM, EXd, CMP } },
3829 { "cmppd", { XM, EXx, CMP } },
3830 { "cmpsd", { XM, EXq, CMP } },
3835 { "movntiS", { Ma, Gv } },
3838 /* PREFIX_0FC7_REG_6 */
3840 { "vmptrld",{ Mq } },
3841 { "vmxon", { Mq } },
3842 { "vmclear",{ Mq } },
3849 { "addsubpd", { XM, EXx } },
3850 { "addsubps", { XM, EXx } },
3856 { "movq2dq",{ XM, MS } },
3857 { "movq", { EXqS, XM } },
3858 { "movdq2q",{ MX, XS } },
3864 { "cvtdq2pd", { XM, EXq } },
3865 { "cvttpd2dq", { XM, EXx } },
3866 { "cvtpd2dq", { XM, EXx } },
3871 { "movntq", { Mq, MX } },
3873 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3881 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3886 { "maskmovq", { MX, MS } },
3888 { "maskmovdqu", { XM, XS } },
3895 { "pblendvb", { XM, EXx, XMM0 } },
3902 { "blendvps", { XM, EXx, XMM0 } },
3909 { "blendvpd", { XM, EXx, XMM0 } },
3916 { "ptest", { XM, EXx } },
3923 { "pmovsxbw", { XM, EXq } },
3930 { "pmovsxbd", { XM, EXd } },
3937 { "pmovsxbq", { XM, EXw } },
3944 { "pmovsxwd", { XM, EXq } },
3951 { "pmovsxwq", { XM, EXd } },
3958 { "pmovsxdq", { XM, EXq } },
3965 { "pmuldq", { XM, EXx } },
3972 { "pcmpeqq", { XM, EXx } },
3979 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3986 { "packusdw", { XM, EXx } },
3993 { "pmovzxbw", { XM, EXq } },
4000 { "pmovzxbd", { XM, EXd } },
4007 { "pmovzxbq", { XM, EXw } },
4014 { "pmovzxwd", { XM, EXq } },
4021 { "pmovzxwq", { XM, EXd } },
4028 { "pmovzxdq", { XM, EXq } },
4035 { "pcmpgtq", { XM, EXx } },
4042 { "pminsb", { XM, EXx } },
4049 { "pminsd", { XM, EXx } },
4056 { "pminuw", { XM, EXx } },
4063 { "pminud", { XM, EXx } },
4070 { "pmaxsb", { XM, EXx } },
4077 { "pmaxsd", { XM, EXx } },
4084 { "pmaxuw", { XM, EXx } },
4091 { "pmaxud", { XM, EXx } },
4098 { "pmulld", { XM, EXx } },
4105 { "phminposuw", { XM, EXx } },
4112 { "invept", { Gm, Mo } },
4119 { "invvpid", { Gm, Mo } },
4126 { "invpcid", { Gm, M } },
4131 { "sha1nexte", { XM, EXxmm } },
4136 { "sha1msg1", { XM, EXxmm } },
4141 { "sha1msg2", { XM, EXxmm } },
4146 { "sha256rnds2", { XM, EXxmm, XMM0 } },
4151 { "sha256msg1", { XM, EXxmm } },
4156 { "sha256msg2", { XM, EXxmm } },
4163 { "aesimc", { XM, EXx } },
4170 { "aesenc", { XM, EXx } },
4177 { "aesenclast", { XM, EXx } },
4184 { "aesdec", { XM, EXx } },
4191 { "aesdeclast", { XM, EXx } },
4196 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4198 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4199 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
4204 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4206 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4207 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
4213 { "adoxS", { Gdq, Edq} },
4214 { "adcxS", { Gdq, Edq} },
4222 { "roundps", { XM, EXx, Ib } },
4229 { "roundpd", { XM, EXx, Ib } },
4236 { "roundss", { XM, EXd, Ib } },
4243 { "roundsd", { XM, EXq, Ib } },
4250 { "blendps", { XM, EXx, Ib } },
4257 { "blendpd", { XM, EXx, Ib } },
4264 { "pblendw", { XM, EXx, Ib } },
4271 { "pextrb", { Edqb, XM, Ib } },
4278 { "pextrw", { Edqw, XM, Ib } },
4285 { "pextrK", { Edq, XM, Ib } },
4292 { "extractps", { Edqd, XM, Ib } },
4299 { "pinsrb", { XM, Edqb, Ib } },
4306 { "insertps", { XM, EXd, Ib } },
4313 { "pinsrK", { XM, Edq, Ib } },
4320 { "dpps", { XM, EXx, Ib } },
4327 { "dppd", { XM, EXx, Ib } },
4334 { "mpsadbw", { XM, EXx, Ib } },
4341 { "pclmulqdq", { XM, EXx, PCLMUL } },
4348 { "pcmpestrm", { XM, EXx, Ib } },
4355 { "pcmpestri", { XM, EXx, Ib } },
4362 { "pcmpistrm", { XM, EXx, Ib } },
4369 { "pcmpistri", { XM, EXx, Ib } },
4374 { "sha1rnds4", { XM, EXxmm, Ib } },
4381 { "aeskeygenassist", { XM, EXx, Ib } },
4384 /* PREFIX_VEX_0F10 */
4386 { VEX_W_TABLE (VEX_W_0F10_P_0) },
4387 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4388 { VEX_W_TABLE (VEX_W_0F10_P_2) },
4389 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4392 /* PREFIX_VEX_0F11 */
4394 { VEX_W_TABLE (VEX_W_0F11_P_0) },
4395 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4396 { VEX_W_TABLE (VEX_W_0F11_P_2) },
4397 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4400 /* PREFIX_VEX_0F12 */
4402 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4403 { VEX_W_TABLE (VEX_W_0F12_P_1) },
4404 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4405 { VEX_W_TABLE (VEX_W_0F12_P_3) },
4408 /* PREFIX_VEX_0F16 */
4410 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4411 { VEX_W_TABLE (VEX_W_0F16_P_1) },
4412 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4415 /* PREFIX_VEX_0F2A */
4418 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4420 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4423 /* PREFIX_VEX_0F2C */
4426 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4428 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4431 /* PREFIX_VEX_0F2D */
4434 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4436 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4439 /* PREFIX_VEX_0F2E */
4441 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4443 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4446 /* PREFIX_VEX_0F2F */
4448 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4450 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4453 /* PREFIX_VEX_0F41 */
4455 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4458 /* PREFIX_VEX_0F42 */
4460 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4463 /* PREFIX_VEX_0F44 */
4465 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4468 /* PREFIX_VEX_0F45 */
4470 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4473 /* PREFIX_VEX_0F46 */
4475 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4478 /* PREFIX_VEX_0F47 */
4480 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4483 /* PREFIX_VEX_0F4B */
4487 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4490 /* PREFIX_VEX_0F51 */
4492 { VEX_W_TABLE (VEX_W_0F51_P_0) },
4493 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4494 { VEX_W_TABLE (VEX_W_0F51_P_2) },
4495 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4498 /* PREFIX_VEX_0F52 */
4500 { VEX_W_TABLE (VEX_W_0F52_P_0) },
4501 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4504 /* PREFIX_VEX_0F53 */
4506 { VEX_W_TABLE (VEX_W_0F53_P_0) },
4507 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4510 /* PREFIX_VEX_0F58 */
4512 { VEX_W_TABLE (VEX_W_0F58_P_0) },
4513 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4514 { VEX_W_TABLE (VEX_W_0F58_P_2) },
4515 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4518 /* PREFIX_VEX_0F59 */
4520 { VEX_W_TABLE (VEX_W_0F59_P_0) },
4521 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4522 { VEX_W_TABLE (VEX_W_0F59_P_2) },
4523 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4526 /* PREFIX_VEX_0F5A */
4528 { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4529 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4530 { "vcvtpd2ps%XY", { XMM, EXx } },
4531 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4534 /* PREFIX_VEX_0F5B */
4536 { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4537 { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4538 { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4541 /* PREFIX_VEX_0F5C */
4543 { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4544 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4545 { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4546 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4549 /* PREFIX_VEX_0F5D */
4551 { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4552 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4553 { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4554 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4557 /* PREFIX_VEX_0F5E */
4559 { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4560 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4561 { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4562 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4565 /* PREFIX_VEX_0F5F */
4567 { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4568 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4569 { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4570 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4573 /* PREFIX_VEX_0F60 */
4577 { VEX_W_TABLE (VEX_W_0F60_P_2) },
4580 /* PREFIX_VEX_0F61 */
4584 { VEX_W_TABLE (VEX_W_0F61_P_2) },
4587 /* PREFIX_VEX_0F62 */
4591 { VEX_W_TABLE (VEX_W_0F62_P_2) },
4594 /* PREFIX_VEX_0F63 */
4598 { VEX_W_TABLE (VEX_W_0F63_P_2) },
4601 /* PREFIX_VEX_0F64 */
4605 { VEX_W_TABLE (VEX_W_0F64_P_2) },
4608 /* PREFIX_VEX_0F65 */
4612 { VEX_W_TABLE (VEX_W_0F65_P_2) },
4615 /* PREFIX_VEX_0F66 */
4619 { VEX_W_TABLE (VEX_W_0F66_P_2) },
4622 /* PREFIX_VEX_0F67 */
4626 { VEX_W_TABLE (VEX_W_0F67_P_2) },
4629 /* PREFIX_VEX_0F68 */
4633 { VEX_W_TABLE (VEX_W_0F68_P_2) },
4636 /* PREFIX_VEX_0F69 */
4640 { VEX_W_TABLE (VEX_W_0F69_P_2) },
4643 /* PREFIX_VEX_0F6A */
4647 { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4650 /* PREFIX_VEX_0F6B */
4654 { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4657 /* PREFIX_VEX_0F6C */
4661 { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4664 /* PREFIX_VEX_0F6D */
4668 { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4671 /* PREFIX_VEX_0F6E */
4675 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4678 /* PREFIX_VEX_0F6F */
4681 { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4682 { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4685 /* PREFIX_VEX_0F70 */
4688 { VEX_W_TABLE (VEX_W_0F70_P_1) },
4689 { VEX_W_TABLE (VEX_W_0F70_P_2) },
4690 { VEX_W_TABLE (VEX_W_0F70_P_3) },
4693 /* PREFIX_VEX_0F71_REG_2 */
4697 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4700 /* PREFIX_VEX_0F71_REG_4 */
4704 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4707 /* PREFIX_VEX_0F71_REG_6 */
4711 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4714 /* PREFIX_VEX_0F72_REG_2 */
4718 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4721 /* PREFIX_VEX_0F72_REG_4 */
4725 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4728 /* PREFIX_VEX_0F72_REG_6 */
4732 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4735 /* PREFIX_VEX_0F73_REG_2 */
4739 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4742 /* PREFIX_VEX_0F73_REG_3 */
4746 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4749 /* PREFIX_VEX_0F73_REG_6 */
4753 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4756 /* PREFIX_VEX_0F73_REG_7 */
4760 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4763 /* PREFIX_VEX_0F74 */
4767 { VEX_W_TABLE (VEX_W_0F74_P_2) },
4770 /* PREFIX_VEX_0F75 */
4774 { VEX_W_TABLE (VEX_W_0F75_P_2) },
4777 /* PREFIX_VEX_0F76 */
4781 { VEX_W_TABLE (VEX_W_0F76_P_2) },
4784 /* PREFIX_VEX_0F77 */
4786 { VEX_W_TABLE (VEX_W_0F77_P_0) },
4789 /* PREFIX_VEX_0F7C */
4793 { VEX_W_TABLE (VEX_W_0F7C_P_2) },
4794 { VEX_W_TABLE (VEX_W_0F7C_P_3) },
4797 /* PREFIX_VEX_0F7D */
4801 { VEX_W_TABLE (VEX_W_0F7D_P_2) },
4802 { VEX_W_TABLE (VEX_W_0F7D_P_3) },
4805 /* PREFIX_VEX_0F7E */
4808 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4809 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4812 /* PREFIX_VEX_0F7F */
4815 { VEX_W_TABLE (VEX_W_0F7F_P_1) },
4816 { VEX_W_TABLE (VEX_W_0F7F_P_2) },
4819 /* PREFIX_VEX_0F90 */
4821 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
4824 /* PREFIX_VEX_0F91 */
4826 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
4829 /* PREFIX_VEX_0F92 */
4831 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
4834 /* PREFIX_VEX_0F93 */
4836 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
4839 /* PREFIX_VEX_0F98 */
4841 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
4844 /* PREFIX_VEX_0FC2 */
4846 { VEX_W_TABLE (VEX_W_0FC2_P_0) },
4847 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
4848 { VEX_W_TABLE (VEX_W_0FC2_P_2) },
4849 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
4852 /* PREFIX_VEX_0FC4 */
4856 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
4859 /* PREFIX_VEX_0FC5 */
4863 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
4866 /* PREFIX_VEX_0FD0 */
4870 { VEX_W_TABLE (VEX_W_0FD0_P_2) },
4871 { VEX_W_TABLE (VEX_W_0FD0_P_3) },
4874 /* PREFIX_VEX_0FD1 */
4878 { VEX_W_TABLE (VEX_W_0FD1_P_2) },
4881 /* PREFIX_VEX_0FD2 */
4885 { VEX_W_TABLE (VEX_W_0FD2_P_2) },
4888 /* PREFIX_VEX_0FD3 */
4892 { VEX_W_TABLE (VEX_W_0FD3_P_2) },
4895 /* PREFIX_VEX_0FD4 */
4899 { VEX_W_TABLE (VEX_W_0FD4_P_2) },
4902 /* PREFIX_VEX_0FD5 */
4906 { VEX_W_TABLE (VEX_W_0FD5_P_2) },
4909 /* PREFIX_VEX_0FD6 */
4913 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
4916 /* PREFIX_VEX_0FD7 */
4920 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
4923 /* PREFIX_VEX_0FD8 */
4927 { VEX_W_TABLE (VEX_W_0FD8_P_2) },
4930 /* PREFIX_VEX_0FD9 */
4934 { VEX_W_TABLE (VEX_W_0FD9_P_2) },
4937 /* PREFIX_VEX_0FDA */
4941 { VEX_W_TABLE (VEX_W_0FDA_P_2) },
4944 /* PREFIX_VEX_0FDB */
4948 { VEX_W_TABLE (VEX_W_0FDB_P_2) },
4951 /* PREFIX_VEX_0FDC */
4955 { VEX_W_TABLE (VEX_W_0FDC_P_2) },
4958 /* PREFIX_VEX_0FDD */
4962 { VEX_W_TABLE (VEX_W_0FDD_P_2) },
4965 /* PREFIX_VEX_0FDE */
4969 { VEX_W_TABLE (VEX_W_0FDE_P_2) },
4972 /* PREFIX_VEX_0FDF */
4976 { VEX_W_TABLE (VEX_W_0FDF_P_2) },
4979 /* PREFIX_VEX_0FE0 */
4983 { VEX_W_TABLE (VEX_W_0FE0_P_2) },
4986 /* PREFIX_VEX_0FE1 */
4990 { VEX_W_TABLE (VEX_W_0FE1_P_2) },
4993 /* PREFIX_VEX_0FE2 */
4997 { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5000 /* PREFIX_VEX_0FE3 */
5004 { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5007 /* PREFIX_VEX_0FE4 */
5011 { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5014 /* PREFIX_VEX_0FE5 */
5018 { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5021 /* PREFIX_VEX_0FE6 */
5024 { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5025 { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5026 { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5029 /* PREFIX_VEX_0FE7 */
5033 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5036 /* PREFIX_VEX_0FE8 */
5040 { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5043 /* PREFIX_VEX_0FE9 */
5047 { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5050 /* PREFIX_VEX_0FEA */
5054 { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5057 /* PREFIX_VEX_0FEB */
5061 { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5064 /* PREFIX_VEX_0FEC */
5068 { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5071 /* PREFIX_VEX_0FED */
5075 { VEX_W_TABLE (VEX_W_0FED_P_2) },
5078 /* PREFIX_VEX_0FEE */
5082 { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5085 /* PREFIX_VEX_0FEF */
5089 { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5092 /* PREFIX_VEX_0FF0 */
5097 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5100 /* PREFIX_VEX_0FF1 */
5104 { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5107 /* PREFIX_VEX_0FF2 */
5111 { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5114 /* PREFIX_VEX_0FF3 */
5118 { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5121 /* PREFIX_VEX_0FF4 */
5125 { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5128 /* PREFIX_VEX_0FF5 */
5132 { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5135 /* PREFIX_VEX_0FF6 */
5139 { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5142 /* PREFIX_VEX_0FF7 */
5146 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5149 /* PREFIX_VEX_0FF8 */
5153 { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5156 /* PREFIX_VEX_0FF9 */
5160 { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5163 /* PREFIX_VEX_0FFA */
5167 { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5170 /* PREFIX_VEX_0FFB */
5174 { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5177 /* PREFIX_VEX_0FFC */
5181 { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5184 /* PREFIX_VEX_0FFD */
5188 { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5191 /* PREFIX_VEX_0FFE */
5195 { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5198 /* PREFIX_VEX_0F3800 */
5202 { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5205 /* PREFIX_VEX_0F3801 */
5209 { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5212 /* PREFIX_VEX_0F3802 */
5216 { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5219 /* PREFIX_VEX_0F3803 */
5223 { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5226 /* PREFIX_VEX_0F3804 */
5230 { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5233 /* PREFIX_VEX_0F3805 */
5237 { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5240 /* PREFIX_VEX_0F3806 */
5244 { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5247 /* PREFIX_VEX_0F3807 */
5251 { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5254 /* PREFIX_VEX_0F3808 */
5258 { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5261 /* PREFIX_VEX_0F3809 */
5265 { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5268 /* PREFIX_VEX_0F380A */
5272 { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5275 /* PREFIX_VEX_0F380B */
5279 { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5282 /* PREFIX_VEX_0F380C */
5286 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5289 /* PREFIX_VEX_0F380D */
5293 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5296 /* PREFIX_VEX_0F380E */
5300 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5303 /* PREFIX_VEX_0F380F */
5307 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5310 /* PREFIX_VEX_0F3813 */
5314 { "vcvtph2ps", { XM, EXxmmq } },
5317 /* PREFIX_VEX_0F3816 */
5321 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5324 /* PREFIX_VEX_0F3817 */
5328 { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5331 /* PREFIX_VEX_0F3818 */
5335 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5338 /* PREFIX_VEX_0F3819 */
5342 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5345 /* PREFIX_VEX_0F381A */
5349 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5352 /* PREFIX_VEX_0F381C */
5356 { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5359 /* PREFIX_VEX_0F381D */
5363 { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5366 /* PREFIX_VEX_0F381E */
5370 { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5373 /* PREFIX_VEX_0F3820 */
5377 { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5380 /* PREFIX_VEX_0F3821 */
5384 { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5387 /* PREFIX_VEX_0F3822 */
5391 { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5394 /* PREFIX_VEX_0F3823 */
5398 { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5401 /* PREFIX_VEX_0F3824 */
5405 { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5408 /* PREFIX_VEX_0F3825 */
5412 { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5415 /* PREFIX_VEX_0F3828 */
5419 { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5422 /* PREFIX_VEX_0F3829 */
5426 { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5429 /* PREFIX_VEX_0F382A */
5433 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5436 /* PREFIX_VEX_0F382B */
5440 { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5443 /* PREFIX_VEX_0F382C */
5447 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5450 /* PREFIX_VEX_0F382D */
5454 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5457 /* PREFIX_VEX_0F382E */
5461 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5464 /* PREFIX_VEX_0F382F */
5468 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5471 /* PREFIX_VEX_0F3830 */
5475 { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5478 /* PREFIX_VEX_0F3831 */
5482 { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5485 /* PREFIX_VEX_0F3832 */
5489 { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5492 /* PREFIX_VEX_0F3833 */
5496 { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5499 /* PREFIX_VEX_0F3834 */
5503 { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5506 /* PREFIX_VEX_0F3835 */
5510 { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5513 /* PREFIX_VEX_0F3836 */
5517 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5520 /* PREFIX_VEX_0F3837 */
5524 { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5527 /* PREFIX_VEX_0F3838 */
5531 { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5534 /* PREFIX_VEX_0F3839 */
5538 { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5541 /* PREFIX_VEX_0F383A */
5545 { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5548 /* PREFIX_VEX_0F383B */
5552 { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5555 /* PREFIX_VEX_0F383C */
5559 { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5562 /* PREFIX_VEX_0F383D */
5566 { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5569 /* PREFIX_VEX_0F383E */
5573 { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5576 /* PREFIX_VEX_0F383F */
5580 { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5583 /* PREFIX_VEX_0F3840 */
5587 { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5590 /* PREFIX_VEX_0F3841 */
5594 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5597 /* PREFIX_VEX_0F3845 */
5601 { "vpsrlv%LW", { XM, Vex, EXx } },
5604 /* PREFIX_VEX_0F3846 */
5608 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5611 /* PREFIX_VEX_0F3847 */
5615 { "vpsllv%LW", { XM, Vex, EXx } },
5618 /* PREFIX_VEX_0F3858 */
5622 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5625 /* PREFIX_VEX_0F3859 */
5629 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5632 /* PREFIX_VEX_0F385A */
5636 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5639 /* PREFIX_VEX_0F3878 */
5643 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5646 /* PREFIX_VEX_0F3879 */
5650 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5653 /* PREFIX_VEX_0F388C */
5657 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5660 /* PREFIX_VEX_0F388E */
5664 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5667 /* PREFIX_VEX_0F3890 */
5671 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
5674 /* PREFIX_VEX_0F3891 */
5678 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5681 /* PREFIX_VEX_0F3892 */
5685 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
5688 /* PREFIX_VEX_0F3893 */
5692 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5695 /* PREFIX_VEX_0F3896 */
5699 { "vfmaddsub132p%XW", { XM, Vex, EXx } },
5702 /* PREFIX_VEX_0F3897 */
5706 { "vfmsubadd132p%XW", { XM, Vex, EXx } },
5709 /* PREFIX_VEX_0F3898 */
5713 { "vfmadd132p%XW", { XM, Vex, EXx } },
5716 /* PREFIX_VEX_0F3899 */
5720 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5723 /* PREFIX_VEX_0F389A */
5727 { "vfmsub132p%XW", { XM, Vex, EXx } },
5730 /* PREFIX_VEX_0F389B */
5734 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5737 /* PREFIX_VEX_0F389C */
5741 { "vfnmadd132p%XW", { XM, Vex, EXx } },
5744 /* PREFIX_VEX_0F389D */
5748 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5751 /* PREFIX_VEX_0F389E */
5755 { "vfnmsub132p%XW", { XM, Vex, EXx } },
5758 /* PREFIX_VEX_0F389F */
5762 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5765 /* PREFIX_VEX_0F38A6 */
5769 { "vfmaddsub213p%XW", { XM, Vex, EXx } },
5773 /* PREFIX_VEX_0F38A7 */
5777 { "vfmsubadd213p%XW", { XM, Vex, EXx } },
5780 /* PREFIX_VEX_0F38A8 */
5784 { "vfmadd213p%XW", { XM, Vex, EXx } },
5787 /* PREFIX_VEX_0F38A9 */
5791 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5794 /* PREFIX_VEX_0F38AA */
5798 { "vfmsub213p%XW", { XM, Vex, EXx } },
5801 /* PREFIX_VEX_0F38AB */
5805 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5808 /* PREFIX_VEX_0F38AC */
5812 { "vfnmadd213p%XW", { XM, Vex, EXx } },
5815 /* PREFIX_VEX_0F38AD */
5819 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5822 /* PREFIX_VEX_0F38AE */
5826 { "vfnmsub213p%XW", { XM, Vex, EXx } },
5829 /* PREFIX_VEX_0F38AF */
5833 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5836 /* PREFIX_VEX_0F38B6 */
5840 { "vfmaddsub231p%XW", { XM, Vex, EXx } },
5843 /* PREFIX_VEX_0F38B7 */
5847 { "vfmsubadd231p%XW", { XM, Vex, EXx } },
5850 /* PREFIX_VEX_0F38B8 */
5854 { "vfmadd231p%XW", { XM, Vex, EXx } },
5857 /* PREFIX_VEX_0F38B9 */
5861 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5864 /* PREFIX_VEX_0F38BA */
5868 { "vfmsub231p%XW", { XM, Vex, EXx } },
5871 /* PREFIX_VEX_0F38BB */
5875 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5878 /* PREFIX_VEX_0F38BC */
5882 { "vfnmadd231p%XW", { XM, Vex, EXx } },
5885 /* PREFIX_VEX_0F38BD */
5889 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5892 /* PREFIX_VEX_0F38BE */
5896 { "vfnmsub231p%XW", { XM, Vex, EXx } },
5899 /* PREFIX_VEX_0F38BF */
5903 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5906 /* PREFIX_VEX_0F38DB */
5910 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
5913 /* PREFIX_VEX_0F38DC */
5917 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
5920 /* PREFIX_VEX_0F38DD */
5924 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
5927 /* PREFIX_VEX_0F38DE */
5931 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
5934 /* PREFIX_VEX_0F38DF */
5938 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
5941 /* PREFIX_VEX_0F38F2 */
5943 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
5946 /* PREFIX_VEX_0F38F3_REG_1 */
5948 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
5951 /* PREFIX_VEX_0F38F3_REG_2 */
5953 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
5956 /* PREFIX_VEX_0F38F3_REG_3 */
5958 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
5961 /* PREFIX_VEX_0F38F5 */
5963 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
5964 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
5966 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
5969 /* PREFIX_VEX_0F38F6 */
5974 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
5977 /* PREFIX_VEX_0F38F7 */
5979 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
5980 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
5981 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
5982 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
5985 /* PREFIX_VEX_0F3A00 */
5989 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
5992 /* PREFIX_VEX_0F3A01 */
5996 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
5999 /* PREFIX_VEX_0F3A02 */
6003 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6006 /* PREFIX_VEX_0F3A04 */
6010 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6013 /* PREFIX_VEX_0F3A05 */
6017 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6020 /* PREFIX_VEX_0F3A06 */
6024 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6027 /* PREFIX_VEX_0F3A08 */
6031 { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6034 /* PREFIX_VEX_0F3A09 */
6038 { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6041 /* PREFIX_VEX_0F3A0A */
6045 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6048 /* PREFIX_VEX_0F3A0B */
6052 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6055 /* PREFIX_VEX_0F3A0C */
6059 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6062 /* PREFIX_VEX_0F3A0D */
6066 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6069 /* PREFIX_VEX_0F3A0E */
6073 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6076 /* PREFIX_VEX_0F3A0F */
6080 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6083 /* PREFIX_VEX_0F3A14 */
6087 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6090 /* PREFIX_VEX_0F3A15 */
6094 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6097 /* PREFIX_VEX_0F3A16 */
6101 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6104 /* PREFIX_VEX_0F3A17 */
6108 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6111 /* PREFIX_VEX_0F3A18 */
6115 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6118 /* PREFIX_VEX_0F3A19 */
6122 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6125 /* PREFIX_VEX_0F3A1D */
6129 { "vcvtps2ph", { EXxmmq, XM, Ib } },
6132 /* PREFIX_VEX_0F3A20 */
6136 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6139 /* PREFIX_VEX_0F3A21 */
6143 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6146 /* PREFIX_VEX_0F3A22 */
6150 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6153 /* PREFIX_VEX_0F3A30 */
6157 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6160 /* PREFIX_VEX_0F3A32 */
6164 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6167 /* PREFIX_VEX_0F3A38 */
6171 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6174 /* PREFIX_VEX_0F3A39 */
6178 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6181 /* PREFIX_VEX_0F3A40 */
6185 { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6188 /* PREFIX_VEX_0F3A41 */
6192 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6195 /* PREFIX_VEX_0F3A42 */
6199 { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6202 /* PREFIX_VEX_0F3A44 */
6206 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6209 /* PREFIX_VEX_0F3A46 */
6213 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6216 /* PREFIX_VEX_0F3A48 */
6220 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6223 /* PREFIX_VEX_0F3A49 */
6227 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6230 /* PREFIX_VEX_0F3A4A */
6234 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6237 /* PREFIX_VEX_0F3A4B */
6241 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6244 /* PREFIX_VEX_0F3A4C */
6248 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6251 /* PREFIX_VEX_0F3A5C */
6255 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6258 /* PREFIX_VEX_0F3A5D */
6262 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6265 /* PREFIX_VEX_0F3A5E */
6269 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6272 /* PREFIX_VEX_0F3A5F */
6276 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6279 /* PREFIX_VEX_0F3A60 */
6283 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6287 /* PREFIX_VEX_0F3A61 */
6291 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6294 /* PREFIX_VEX_0F3A62 */
6298 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6301 /* PREFIX_VEX_0F3A63 */
6305 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6308 /* PREFIX_VEX_0F3A68 */
6312 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6315 /* PREFIX_VEX_0F3A69 */
6319 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6322 /* PREFIX_VEX_0F3A6A */
6326 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6329 /* PREFIX_VEX_0F3A6B */
6333 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6336 /* PREFIX_VEX_0F3A6C */
6340 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6343 /* PREFIX_VEX_0F3A6D */
6347 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6350 /* PREFIX_VEX_0F3A6E */
6354 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6357 /* PREFIX_VEX_0F3A6F */
6361 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6364 /* PREFIX_VEX_0F3A78 */
6368 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6371 /* PREFIX_VEX_0F3A79 */
6375 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6378 /* PREFIX_VEX_0F3A7A */
6382 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6385 /* PREFIX_VEX_0F3A7B */
6389 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6392 /* PREFIX_VEX_0F3A7C */
6396 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6400 /* PREFIX_VEX_0F3A7D */
6404 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6407 /* PREFIX_VEX_0F3A7E */
6411 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6414 /* PREFIX_VEX_0F3A7F */
6418 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6421 /* PREFIX_VEX_0F3ADF */
6425 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6428 /* PREFIX_VEX_0F3AF0 */
6433 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6436 #define NEED_PREFIX_TABLE
6437 #include "i386-dis-evex.h"
6438 #undef NEED_PREFIX_TABLE
6441 static const struct dis386 x86_64_table[][2] = {
6444 { "pushP", { es } },
6454 { "pushP", { cs } },
6459 { "pushP", { ss } },
6469 { "pushP", { ds } },
6499 { "pushaP", { XX } },
6504 { "popaP", { XX } },
6509 { MOD_TABLE (MOD_62_32BIT) },
6510 { EVEX_TABLE (EVEX_0F) },
6515 { "arpl", { Ew, Gw } },
6516 { "movs{lq|xd}", { Gv, Ed } },
6521 { "ins{R|}", { Yzr, indirDX } },
6522 { "ins{G|}", { Yzr, indirDX } },
6527 { "outs{R|}", { indirDXr, Xz } },
6528 { "outs{G|}", { indirDXr, Xz } },
6533 { "Jcall{T|}", { Ap } },
6538 { MOD_TABLE (MOD_C4_32BIT) },
6539 { VEX_C4_TABLE (VEX_0F) },
6544 { MOD_TABLE (MOD_C5_32BIT) },
6545 { VEX_C5_TABLE (VEX_0F) },
6565 { "Jjmp{T|}", { Ap } },
6568 /* X86_64_0F01_REG_0 */
6570 { "sgdt{Q|IQ}", { M } },
6574 /* X86_64_0F01_REG_1 */
6576 { "sidt{Q|IQ}", { M } },
6580 /* X86_64_0F01_REG_2 */
6582 { "lgdt{Q|Q}", { M } },
6586 /* X86_64_0F01_REG_3 */
6588 { "lidt{Q|Q}", { M } },
6593 static const struct dis386 three_byte_table[][256] = {
6595 /* THREE_BYTE_0F38 */
6598 { "pshufb", { MX, EM } },
6599 { "phaddw", { MX, EM } },
6600 { "phaddd", { MX, EM } },
6601 { "phaddsw", { MX, EM } },
6602 { "pmaddubsw", { MX, EM } },
6603 { "phsubw", { MX, EM } },
6604 { "phsubd", { MX, EM } },
6605 { "phsubsw", { MX, EM } },
6607 { "psignb", { MX, EM } },
6608 { "psignw", { MX, EM } },
6609 { "psignd", { MX, EM } },
6610 { "pmulhrsw", { MX, EM } },
6616 { PREFIX_TABLE (PREFIX_0F3810) },
6620 { PREFIX_TABLE (PREFIX_0F3814) },
6621 { PREFIX_TABLE (PREFIX_0F3815) },
6623 { PREFIX_TABLE (PREFIX_0F3817) },
6629 { "pabsb", { MX, EM } },
6630 { "pabsw", { MX, EM } },
6631 { "pabsd", { MX, EM } },
6634 { PREFIX_TABLE (PREFIX_0F3820) },
6635 { PREFIX_TABLE (PREFIX_0F3821) },
6636 { PREFIX_TABLE (PREFIX_0F3822) },
6637 { PREFIX_TABLE (PREFIX_0F3823) },
6638 { PREFIX_TABLE (PREFIX_0F3824) },
6639 { PREFIX_TABLE (PREFIX_0F3825) },
6643 { PREFIX_TABLE (PREFIX_0F3828) },
6644 { PREFIX_TABLE (PREFIX_0F3829) },
6645 { PREFIX_TABLE (PREFIX_0F382A) },
6646 { PREFIX_TABLE (PREFIX_0F382B) },
6652 { PREFIX_TABLE (PREFIX_0F3830) },
6653 { PREFIX_TABLE (PREFIX_0F3831) },
6654 { PREFIX_TABLE (PREFIX_0F3832) },
6655 { PREFIX_TABLE (PREFIX_0F3833) },
6656 { PREFIX_TABLE (PREFIX_0F3834) },
6657 { PREFIX_TABLE (PREFIX_0F3835) },
6659 { PREFIX_TABLE (PREFIX_0F3837) },
6661 { PREFIX_TABLE (PREFIX_0F3838) },
6662 { PREFIX_TABLE (PREFIX_0F3839) },
6663 { PREFIX_TABLE (PREFIX_0F383A) },
6664 { PREFIX_TABLE (PREFIX_0F383B) },
6665 { PREFIX_TABLE (PREFIX_0F383C) },
6666 { PREFIX_TABLE (PREFIX_0F383D) },
6667 { PREFIX_TABLE (PREFIX_0F383E) },
6668 { PREFIX_TABLE (PREFIX_0F383F) },
6670 { PREFIX_TABLE (PREFIX_0F3840) },
6671 { PREFIX_TABLE (PREFIX_0F3841) },
6742 { PREFIX_TABLE (PREFIX_0F3880) },
6743 { PREFIX_TABLE (PREFIX_0F3881) },
6744 { PREFIX_TABLE (PREFIX_0F3882) },
6823 { PREFIX_TABLE (PREFIX_0F38C8) },
6824 { PREFIX_TABLE (PREFIX_0F38C9) },
6825 { PREFIX_TABLE (PREFIX_0F38CA) },
6826 { PREFIX_TABLE (PREFIX_0F38CB) },
6827 { PREFIX_TABLE (PREFIX_0F38CC) },
6828 { PREFIX_TABLE (PREFIX_0F38CD) },
6844 { PREFIX_TABLE (PREFIX_0F38DB) },
6845 { PREFIX_TABLE (PREFIX_0F38DC) },
6846 { PREFIX_TABLE (PREFIX_0F38DD) },
6847 { PREFIX_TABLE (PREFIX_0F38DE) },
6848 { PREFIX_TABLE (PREFIX_0F38DF) },
6868 { PREFIX_TABLE (PREFIX_0F38F0) },
6869 { PREFIX_TABLE (PREFIX_0F38F1) },
6874 { PREFIX_TABLE (PREFIX_0F38F6) },
6886 /* THREE_BYTE_0F3A */
6898 { PREFIX_TABLE (PREFIX_0F3A08) },
6899 { PREFIX_TABLE (PREFIX_0F3A09) },
6900 { PREFIX_TABLE (PREFIX_0F3A0A) },
6901 { PREFIX_TABLE (PREFIX_0F3A0B) },
6902 { PREFIX_TABLE (PREFIX_0F3A0C) },
6903 { PREFIX_TABLE (PREFIX_0F3A0D) },
6904 { PREFIX_TABLE (PREFIX_0F3A0E) },
6905 { "palignr", { MX, EM, Ib } },
6911 { PREFIX_TABLE (PREFIX_0F3A14) },
6912 { PREFIX_TABLE (PREFIX_0F3A15) },
6913 { PREFIX_TABLE (PREFIX_0F3A16) },
6914 { PREFIX_TABLE (PREFIX_0F3A17) },
6925 { PREFIX_TABLE (PREFIX_0F3A20) },
6926 { PREFIX_TABLE (PREFIX_0F3A21) },
6927 { PREFIX_TABLE (PREFIX_0F3A22) },
6961 { PREFIX_TABLE (PREFIX_0F3A40) },
6962 { PREFIX_TABLE (PREFIX_0F3A41) },
6963 { PREFIX_TABLE (PREFIX_0F3A42) },
6965 { PREFIX_TABLE (PREFIX_0F3A44) },
6997 { PREFIX_TABLE (PREFIX_0F3A60) },
6998 { PREFIX_TABLE (PREFIX_0F3A61) },
6999 { PREFIX_TABLE (PREFIX_0F3A62) },
7000 { PREFIX_TABLE (PREFIX_0F3A63) },
7118 { PREFIX_TABLE (PREFIX_0F3ACC) },
7139 { PREFIX_TABLE (PREFIX_0F3ADF) },
7178 /* THREE_BYTE_0F7A */
7217 { "ptest", { XX } },
7254 { "phaddbw", { XM, EXq } },
7255 { "phaddbd", { XM, EXq } },
7256 { "phaddbq", { XM, EXq } },
7259 { "phaddwd", { XM, EXq } },
7260 { "phaddwq", { XM, EXq } },
7265 { "phadddq", { XM, EXq } },
7272 { "phaddubw", { XM, EXq } },
7273 { "phaddubd", { XM, EXq } },
7274 { "phaddubq", { XM, EXq } },
7277 { "phadduwd", { XM, EXq } },
7278 { "phadduwq", { XM, EXq } },
7283 { "phaddudq", { XM, EXq } },
7290 { "phsubbw", { XM, EXq } },
7291 { "phsubbd", { XM, EXq } },
7292 { "phsubbq", { XM, EXq } },
7471 static const struct dis386 xop_table[][256] = {
7624 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7625 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7626 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7634 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7635 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7642 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7643 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7644 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7652 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7653 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7657 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7658 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7661 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7679 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7691 { "vprotb", { XM, Vex_2src_1, Ib } },
7692 { "vprotw", { XM, Vex_2src_1, Ib } },
7693 { "vprotd", { XM, Vex_2src_1, Ib } },
7694 { "vprotq", { XM, Vex_2src_1, Ib } },
7704 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7705 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7706 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7707 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7740 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7741 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7742 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7743 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7767 { REG_TABLE (REG_XOP_TBM_01) },
7768 { REG_TABLE (REG_XOP_TBM_02) },
7786 { REG_TABLE (REG_XOP_LWPCB) },
7910 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7911 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7912 { "vfrczss", { XM, EXd } },
7913 { "vfrczsd", { XM, EXq } },
7928 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } },
7929 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } },
7930 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } },
7931 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } },
7932 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } },
7933 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } },
7934 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } },
7935 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } },
7937 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } },
7938 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } },
7939 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } },
7940 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } },
7983 { "vphaddbw", { XM, EXxmm } },
7984 { "vphaddbd", { XM, EXxmm } },
7985 { "vphaddbq", { XM, EXxmm } },
7988 { "vphaddwd", { XM, EXxmm } },
7989 { "vphaddwq", { XM, EXxmm } },
7994 { "vphadddq", { XM, EXxmm } },
8001 { "vphaddubw", { XM, EXxmm } },
8002 { "vphaddubd", { XM, EXxmm } },
8003 { "vphaddubq", { XM, EXxmm } },
8006 { "vphadduwd", { XM, EXxmm } },
8007 { "vphadduwq", { XM, EXxmm } },
8012 { "vphaddudq", { XM, EXxmm } },
8019 { "vphsubbw", { XM, EXxmm } },
8020 { "vphsubwd", { XM, EXxmm } },
8021 { "vphsubdq", { XM, EXxmm } },
8075 { "bextr", { Gv, Ev, Iq } },
8077 { REG_TABLE (REG_XOP_LWP) },
8347 static const struct dis386 vex_table[][256] = {
8369 { PREFIX_TABLE (PREFIX_VEX_0F10) },
8370 { PREFIX_TABLE (PREFIX_VEX_0F11) },
8371 { PREFIX_TABLE (PREFIX_VEX_0F12) },
8372 { MOD_TABLE (MOD_VEX_0F13) },
8373 { VEX_W_TABLE (VEX_W_0F14) },
8374 { VEX_W_TABLE (VEX_W_0F15) },
8375 { PREFIX_TABLE (PREFIX_VEX_0F16) },
8376 { MOD_TABLE (MOD_VEX_0F17) },
8396 { VEX_W_TABLE (VEX_W_0F28) },
8397 { VEX_W_TABLE (VEX_W_0F29) },
8398 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8399 { MOD_TABLE (MOD_VEX_0F2B) },
8400 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8401 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8402 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8403 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8424 { PREFIX_TABLE (PREFIX_VEX_0F41) },
8425 { PREFIX_TABLE (PREFIX_VEX_0F42) },
8427 { PREFIX_TABLE (PREFIX_VEX_0F44) },
8428 { PREFIX_TABLE (PREFIX_VEX_0F45) },
8429 { PREFIX_TABLE (PREFIX_VEX_0F46) },
8430 { PREFIX_TABLE (PREFIX_VEX_0F47) },
8435 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8441 { MOD_TABLE (MOD_VEX_0F50) },
8442 { PREFIX_TABLE (PREFIX_VEX_0F51) },
8443 { PREFIX_TABLE (PREFIX_VEX_0F52) },
8444 { PREFIX_TABLE (PREFIX_VEX_0F53) },
8445 { "vandpX", { XM, Vex, EXx } },
8446 { "vandnpX", { XM, Vex, EXx } },
8447 { "vorpX", { XM, Vex, EXx } },
8448 { "vxorpX", { XM, Vex, EXx } },
8450 { PREFIX_TABLE (PREFIX_VEX_0F58) },
8451 { PREFIX_TABLE (PREFIX_VEX_0F59) },
8452 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8453 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8454 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8455 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8456 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8457 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8459 { PREFIX_TABLE (PREFIX_VEX_0F60) },
8460 { PREFIX_TABLE (PREFIX_VEX_0F61) },
8461 { PREFIX_TABLE (PREFIX_VEX_0F62) },
8462 { PREFIX_TABLE (PREFIX_VEX_0F63) },
8463 { PREFIX_TABLE (PREFIX_VEX_0F64) },
8464 { PREFIX_TABLE (PREFIX_VEX_0F65) },
8465 { PREFIX_TABLE (PREFIX_VEX_0F66) },
8466 { PREFIX_TABLE (PREFIX_VEX_0F67) },
8468 { PREFIX_TABLE (PREFIX_VEX_0F68) },
8469 { PREFIX_TABLE (PREFIX_VEX_0F69) },
8470 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8471 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8472 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8473 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8474 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8475 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8477 { PREFIX_TABLE (PREFIX_VEX_0F70) },
8478 { REG_TABLE (REG_VEX_0F71) },
8479 { REG_TABLE (REG_VEX_0F72) },
8480 { REG_TABLE (REG_VEX_0F73) },
8481 { PREFIX_TABLE (PREFIX_VEX_0F74) },
8482 { PREFIX_TABLE (PREFIX_VEX_0F75) },
8483 { PREFIX_TABLE (PREFIX_VEX_0F76) },
8484 { PREFIX_TABLE (PREFIX_VEX_0F77) },
8490 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8491 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8492 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8493 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8513 { PREFIX_TABLE (PREFIX_VEX_0F90) },
8514 { PREFIX_TABLE (PREFIX_VEX_0F91) },
8515 { PREFIX_TABLE (PREFIX_VEX_0F92) },
8516 { PREFIX_TABLE (PREFIX_VEX_0F93) },
8522 { PREFIX_TABLE (PREFIX_VEX_0F98) },
8546 { REG_TABLE (REG_VEX_0FAE) },
8569 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8571 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8572 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8573 { "vshufpX", { XM, Vex, EXx, Ib } },
8585 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8586 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8587 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8588 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8589 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8590 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8591 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8592 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8594 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8595 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8596 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8597 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8598 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8599 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8600 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8601 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8603 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8604 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8605 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8606 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8607 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8608 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8609 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8610 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8612 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8613 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8614 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8615 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8616 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8617 { PREFIX_TABLE (PREFIX_VEX_0FED) },
8618 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8619 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8621 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8622 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8623 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8624 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8625 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8626 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8627 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8628 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8630 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8631 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8632 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8633 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8634 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8635 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8636 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8642 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8643 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8644 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8645 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8646 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8647 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8648 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8649 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8651 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8652 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8653 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8654 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8655 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8656 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8657 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8658 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8663 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8666 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8667 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8669 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8670 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8671 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8673 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8674 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8675 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8678 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8679 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8680 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8681 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8682 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8683 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8687 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8688 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8689 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8690 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8691 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8692 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8693 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8694 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8696 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8697 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8698 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8699 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8700 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8701 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8702 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8703 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8705 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8706 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8707 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8708 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8709 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8710 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8711 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8712 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8714 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8715 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8719 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8720 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8721 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8741 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8742 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8743 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8799 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8804 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8806 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8807 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8810 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8811 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8813 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8814 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8815 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8816 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8817 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8818 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8819 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8820 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8828 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8829 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8831 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8832 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8833 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8834 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8835 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8836 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8837 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8838 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8846 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8847 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8849 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8850 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8851 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8852 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8853 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8854 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8855 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8856 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8915 { REG_TABLE (REG_VEX_0F38F3) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8956 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8957 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8960 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8961 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8965 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8969 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8987 { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
8989 { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
8996 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8997 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9005 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9006 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9009 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9011 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9014 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9015 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9017 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9036 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9037 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9038 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9050 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9051 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9052 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9053 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9054 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9055 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9056 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9057 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9068 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9183 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9203 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9223 #define NEED_OPCODE_TABLE
9224 #include "i386-dis-evex.h"
9225 #undef NEED_OPCODE_TABLE
9226 static const struct dis386 vex_len_table[][2] = {
9227 /* VEX_LEN_0F10_P_1 */
9229 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9230 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9233 /* VEX_LEN_0F10_P_3 */
9235 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9236 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9239 /* VEX_LEN_0F11_P_1 */
9241 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9242 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9245 /* VEX_LEN_0F11_P_3 */
9247 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9248 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9251 /* VEX_LEN_0F12_P_0_M_0 */
9253 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9256 /* VEX_LEN_0F12_P_0_M_1 */
9258 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9261 /* VEX_LEN_0F12_P_2 */
9263 { VEX_W_TABLE (VEX_W_0F12_P_2) },
9266 /* VEX_LEN_0F13_M_0 */
9268 { VEX_W_TABLE (VEX_W_0F13_M_0) },
9271 /* VEX_LEN_0F16_P_0_M_0 */
9273 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9276 /* VEX_LEN_0F16_P_0_M_1 */
9278 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9281 /* VEX_LEN_0F16_P_2 */
9283 { VEX_W_TABLE (VEX_W_0F16_P_2) },
9286 /* VEX_LEN_0F17_M_0 */
9288 { VEX_W_TABLE (VEX_W_0F17_M_0) },
9291 /* VEX_LEN_0F2A_P_1 */
9293 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
9294 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
9297 /* VEX_LEN_0F2A_P_3 */
9299 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
9300 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
9303 /* VEX_LEN_0F2C_P_1 */
9305 { "vcvttss2siY", { Gv, EXdScalar } },
9306 { "vcvttss2siY", { Gv, EXdScalar } },
9309 /* VEX_LEN_0F2C_P_3 */
9311 { "vcvttsd2siY", { Gv, EXqScalar } },
9312 { "vcvttsd2siY", { Gv, EXqScalar } },
9315 /* VEX_LEN_0F2D_P_1 */
9317 { "vcvtss2siY", { Gv, EXdScalar } },
9318 { "vcvtss2siY", { Gv, EXdScalar } },
9321 /* VEX_LEN_0F2D_P_3 */
9323 { "vcvtsd2siY", { Gv, EXqScalar } },
9324 { "vcvtsd2siY", { Gv, EXqScalar } },
9327 /* VEX_LEN_0F2E_P_0 */
9329 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9330 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9333 /* VEX_LEN_0F2E_P_2 */
9335 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9336 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9339 /* VEX_LEN_0F2F_P_0 */
9341 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9342 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9345 /* VEX_LEN_0F2F_P_2 */
9347 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9348 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9351 /* VEX_LEN_0F41_P_0 */
9354 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9356 /* VEX_LEN_0F42_P_0 */
9359 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9361 /* VEX_LEN_0F44_P_0 */
9363 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9365 /* VEX_LEN_0F45_P_0 */
9368 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9370 /* VEX_LEN_0F46_P_0 */
9373 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9375 /* VEX_LEN_0F47_P_0 */
9378 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9380 /* VEX_LEN_0F4B_P_2 */
9383 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9386 /* VEX_LEN_0F51_P_1 */
9388 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9389 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9392 /* VEX_LEN_0F51_P_3 */
9394 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9395 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9398 /* VEX_LEN_0F52_P_1 */
9400 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9401 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9404 /* VEX_LEN_0F53_P_1 */
9406 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9407 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9410 /* VEX_LEN_0F58_P_1 */
9412 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9413 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9416 /* VEX_LEN_0F58_P_3 */
9418 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9419 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9422 /* VEX_LEN_0F59_P_1 */
9424 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9425 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9428 /* VEX_LEN_0F59_P_3 */
9430 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9431 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9434 /* VEX_LEN_0F5A_P_1 */
9436 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9437 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9440 /* VEX_LEN_0F5A_P_3 */
9442 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9443 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9446 /* VEX_LEN_0F5C_P_1 */
9448 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9449 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9452 /* VEX_LEN_0F5C_P_3 */
9454 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9455 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9458 /* VEX_LEN_0F5D_P_1 */
9460 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9461 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9464 /* VEX_LEN_0F5D_P_3 */
9466 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9467 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9470 /* VEX_LEN_0F5E_P_1 */
9472 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9473 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9476 /* VEX_LEN_0F5E_P_3 */
9478 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9479 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9482 /* VEX_LEN_0F5F_P_1 */
9484 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9485 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9488 /* VEX_LEN_0F5F_P_3 */
9490 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9491 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9494 /* VEX_LEN_0F6E_P_2 */
9496 { "vmovK", { XMScalar, Edq } },
9497 { "vmovK", { XMScalar, Edq } },
9500 /* VEX_LEN_0F7E_P_1 */
9502 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9503 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9506 /* VEX_LEN_0F7E_P_2 */
9508 { "vmovK", { Edq, XMScalar } },
9509 { "vmovK", { Edq, XMScalar } },
9512 /* VEX_LEN_0F90_P_0 */
9514 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9517 /* VEX_LEN_0F91_P_0 */
9519 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9522 /* VEX_LEN_0F92_P_0 */
9524 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9527 /* VEX_LEN_0F93_P_0 */
9529 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9532 /* VEX_LEN_0F98_P_0 */
9534 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9537 /* VEX_LEN_0FAE_R_2_M_0 */
9539 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9542 /* VEX_LEN_0FAE_R_3_M_0 */
9544 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9547 /* VEX_LEN_0FC2_P_1 */
9549 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9550 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9553 /* VEX_LEN_0FC2_P_3 */
9555 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9556 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9559 /* VEX_LEN_0FC4_P_2 */
9561 { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9564 /* VEX_LEN_0FC5_P_2 */
9566 { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9569 /* VEX_LEN_0FD6_P_2 */
9571 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9572 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9575 /* VEX_LEN_0FF7_P_2 */
9577 { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9580 /* VEX_LEN_0F3816_P_2 */
9583 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9586 /* VEX_LEN_0F3819_P_2 */
9589 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9592 /* VEX_LEN_0F381A_P_2_M_0 */
9595 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9598 /* VEX_LEN_0F3836_P_2 */
9601 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9604 /* VEX_LEN_0F3841_P_2 */
9606 { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9609 /* VEX_LEN_0F385A_P_2_M_0 */
9612 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9615 /* VEX_LEN_0F38DB_P_2 */
9617 { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9620 /* VEX_LEN_0F38DC_P_2 */
9622 { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9625 /* VEX_LEN_0F38DD_P_2 */
9627 { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9630 /* VEX_LEN_0F38DE_P_2 */
9632 { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9635 /* VEX_LEN_0F38DF_P_2 */
9637 { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9640 /* VEX_LEN_0F38F2_P_0 */
9642 { "andnS", { Gdq, VexGdq, Edq } },
9645 /* VEX_LEN_0F38F3_R_1_P_0 */
9647 { "blsrS", { VexGdq, Edq } },
9650 /* VEX_LEN_0F38F3_R_2_P_0 */
9652 { "blsmskS", { VexGdq, Edq } },
9655 /* VEX_LEN_0F38F3_R_3_P_0 */
9657 { "blsiS", { VexGdq, Edq } },
9660 /* VEX_LEN_0F38F5_P_0 */
9662 { "bzhiS", { Gdq, Edq, VexGdq } },
9665 /* VEX_LEN_0F38F5_P_1 */
9667 { "pextS", { Gdq, VexGdq, Edq } },
9670 /* VEX_LEN_0F38F5_P_3 */
9672 { "pdepS", { Gdq, VexGdq, Edq } },
9675 /* VEX_LEN_0F38F6_P_3 */
9677 { "mulxS", { Gdq, VexGdq, Edq } },
9680 /* VEX_LEN_0F38F7_P_0 */
9682 { "bextrS", { Gdq, Edq, VexGdq } },
9685 /* VEX_LEN_0F38F7_P_1 */
9687 { "sarxS", { Gdq, Edq, VexGdq } },
9690 /* VEX_LEN_0F38F7_P_2 */
9692 { "shlxS", { Gdq, Edq, VexGdq } },
9695 /* VEX_LEN_0F38F7_P_3 */
9697 { "shrxS", { Gdq, Edq, VexGdq } },
9700 /* VEX_LEN_0F3A00_P_2 */
9703 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9706 /* VEX_LEN_0F3A01_P_2 */
9709 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9712 /* VEX_LEN_0F3A06_P_2 */
9715 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9718 /* VEX_LEN_0F3A0A_P_2 */
9720 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9721 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9724 /* VEX_LEN_0F3A0B_P_2 */
9726 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9727 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9730 /* VEX_LEN_0F3A14_P_2 */
9732 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9735 /* VEX_LEN_0F3A15_P_2 */
9737 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9740 /* VEX_LEN_0F3A16_P_2 */
9742 { "vpextrK", { Edq, XM, Ib } },
9745 /* VEX_LEN_0F3A17_P_2 */
9747 { "vextractps", { Edqd, XM, Ib } },
9750 /* VEX_LEN_0F3A18_P_2 */
9753 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9756 /* VEX_LEN_0F3A19_P_2 */
9759 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9762 /* VEX_LEN_0F3A20_P_2 */
9764 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
9767 /* VEX_LEN_0F3A21_P_2 */
9769 { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
9772 /* VEX_LEN_0F3A22_P_2 */
9774 { "vpinsrK", { XM, Vex128, Edq, Ib } },
9777 /* VEX_LEN_0F3A30_P_2 */
9779 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9782 /* VEX_LEN_0F3A32_P_2 */
9784 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9787 /* VEX_LEN_0F3A38_P_2 */
9790 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9793 /* VEX_LEN_0F3A39_P_2 */
9796 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9799 /* VEX_LEN_0F3A41_P_2 */
9801 { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
9804 /* VEX_LEN_0F3A44_P_2 */
9806 { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
9809 /* VEX_LEN_0F3A46_P_2 */
9812 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9815 /* VEX_LEN_0F3A60_P_2 */
9817 { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
9820 /* VEX_LEN_0F3A61_P_2 */
9822 { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
9825 /* VEX_LEN_0F3A62_P_2 */
9827 { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
9830 /* VEX_LEN_0F3A63_P_2 */
9832 { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
9835 /* VEX_LEN_0F3A6A_P_2 */
9837 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9840 /* VEX_LEN_0F3A6B_P_2 */
9842 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9845 /* VEX_LEN_0F3A6E_P_2 */
9847 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9850 /* VEX_LEN_0F3A6F_P_2 */
9852 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9855 /* VEX_LEN_0F3A7A_P_2 */
9857 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9860 /* VEX_LEN_0F3A7B_P_2 */
9862 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9865 /* VEX_LEN_0F3A7E_P_2 */
9867 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9870 /* VEX_LEN_0F3A7F_P_2 */
9872 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9875 /* VEX_LEN_0F3ADF_P_2 */
9877 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
9880 /* VEX_LEN_0F3AF0_P_3 */
9882 { "rorxS", { Gdq, Edq, Ib } },
9885 /* VEX_LEN_0FXOP_08_CC */
9887 { "vpcomb", { XM, Vex128, EXx, Ib } },
9890 /* VEX_LEN_0FXOP_08_CD */
9892 { "vpcomw", { XM, Vex128, EXx, Ib } },
9895 /* VEX_LEN_0FXOP_08_CE */
9897 { "vpcomd", { XM, Vex128, EXx, Ib } },
9900 /* VEX_LEN_0FXOP_08_CF */
9902 { "vpcomq", { XM, Vex128, EXx, Ib } },
9905 /* VEX_LEN_0FXOP_08_EC */
9907 { "vpcomub", { XM, Vex128, EXx, Ib } },
9910 /* VEX_LEN_0FXOP_08_ED */
9912 { "vpcomuw", { XM, Vex128, EXx, Ib } },
9915 /* VEX_LEN_0FXOP_08_EE */
9917 { "vpcomud", { XM, Vex128, EXx, Ib } },
9920 /* VEX_LEN_0FXOP_08_EF */
9922 { "vpcomuq", { XM, Vex128, EXx, Ib } },
9925 /* VEX_LEN_0FXOP_09_80 */
9927 { "vfrczps", { XM, EXxmm } },
9928 { "vfrczps", { XM, EXymmq } },
9931 /* VEX_LEN_0FXOP_09_81 */
9933 { "vfrczpd", { XM, EXxmm } },
9934 { "vfrczpd", { XM, EXymmq } },
9938 static const struct dis386 vex_w_table[][2] = {
9940 /* VEX_W_0F10_P_0 */
9941 { "vmovups", { XM, EXx } },
9944 /* VEX_W_0F10_P_1 */
9945 { "vmovss", { XMVexScalar, VexScalar, EXdScalar } },
9948 /* VEX_W_0F10_P_2 */
9949 { "vmovupd", { XM, EXx } },
9952 /* VEX_W_0F10_P_3 */
9953 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } },
9956 /* VEX_W_0F11_P_0 */
9957 { "vmovups", { EXxS, XM } },
9960 /* VEX_W_0F11_P_1 */
9961 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } },
9964 /* VEX_W_0F11_P_2 */
9965 { "vmovupd", { EXxS, XM } },
9968 /* VEX_W_0F11_P_3 */
9969 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } },
9972 /* VEX_W_0F12_P_0_M_0 */
9973 { "vmovlps", { XM, Vex128, EXq } },
9976 /* VEX_W_0F12_P_0_M_1 */
9977 { "vmovhlps", { XM, Vex128, EXq } },
9980 /* VEX_W_0F12_P_1 */
9981 { "vmovsldup", { XM, EXx } },
9984 /* VEX_W_0F12_P_2 */
9985 { "vmovlpd", { XM, Vex128, EXq } },
9988 /* VEX_W_0F12_P_3 */
9989 { "vmovddup", { XM, EXymmq } },
9992 /* VEX_W_0F13_M_0 */
9993 { "vmovlpX", { EXq, XM } },
9997 { "vunpcklpX", { XM, Vex, EXx } },
10001 { "vunpckhpX", { XM, Vex, EXx } },
10004 /* VEX_W_0F16_P_0_M_0 */
10005 { "vmovhps", { XM, Vex128, EXq } },
10008 /* VEX_W_0F16_P_0_M_1 */
10009 { "vmovlhps", { XM, Vex128, EXq } },
10012 /* VEX_W_0F16_P_1 */
10013 { "vmovshdup", { XM, EXx } },
10016 /* VEX_W_0F16_P_2 */
10017 { "vmovhpd", { XM, Vex128, EXq } },
10020 /* VEX_W_0F17_M_0 */
10021 { "vmovhpX", { EXq, XM } },
10025 { "vmovapX", { XM, EXx } },
10029 { "vmovapX", { EXxS, XM } },
10032 /* VEX_W_0F2B_M_0 */
10033 { "vmovntpX", { Mx, XM } },
10036 /* VEX_W_0F2E_P_0 */
10037 { "vucomiss", { XMScalar, EXdScalar } },
10040 /* VEX_W_0F2E_P_2 */
10041 { "vucomisd", { XMScalar, EXqScalar } },
10044 /* VEX_W_0F2F_P_0 */
10045 { "vcomiss", { XMScalar, EXdScalar } },
10048 /* VEX_W_0F2F_P_2 */
10049 { "vcomisd", { XMScalar, EXqScalar } },
10052 /* VEX_W_0F41_P_0_LEN_1 */
10053 { "kandw", { MaskG, MaskVex, MaskR } },
10056 /* VEX_W_0F42_P_0_LEN_1 */
10057 { "kandnw", { MaskG, MaskVex, MaskR } },
10060 /* VEX_W_0F44_P_0_LEN_0 */
10061 { "knotw", { MaskG, MaskR } },
10064 /* VEX_W_0F45_P_0_LEN_1 */
10065 { "korw", { MaskG, MaskVex, MaskR } },
10068 /* VEX_W_0F46_P_0_LEN_1 */
10069 { "kxnorw", { MaskG, MaskVex, MaskR } },
10072 /* VEX_W_0F47_P_0_LEN_1 */
10073 { "kxorw", { MaskG, MaskVex, MaskR } },
10076 /* VEX_W_0F4B_P_2_LEN_1 */
10077 { "kunpckbw", { MaskG, MaskVex, MaskR } },
10080 /* VEX_W_0F50_M_0 */
10081 { "vmovmskpX", { Gdq, XS } },
10084 /* VEX_W_0F51_P_0 */
10085 { "vsqrtps", { XM, EXx } },
10088 /* VEX_W_0F51_P_1 */
10089 { "vsqrtss", { XMScalar, VexScalar, EXdScalar } },
10092 /* VEX_W_0F51_P_2 */
10093 { "vsqrtpd", { XM, EXx } },
10096 /* VEX_W_0F51_P_3 */
10097 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar } },
10100 /* VEX_W_0F52_P_0 */
10101 { "vrsqrtps", { XM, EXx } },
10104 /* VEX_W_0F52_P_1 */
10105 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar } },
10108 /* VEX_W_0F53_P_0 */
10109 { "vrcpps", { XM, EXx } },
10112 /* VEX_W_0F53_P_1 */
10113 { "vrcpss", { XMScalar, VexScalar, EXdScalar } },
10116 /* VEX_W_0F58_P_0 */
10117 { "vaddps", { XM, Vex, EXx } },
10120 /* VEX_W_0F58_P_1 */
10121 { "vaddss", { XMScalar, VexScalar, EXdScalar } },
10124 /* VEX_W_0F58_P_2 */
10125 { "vaddpd", { XM, Vex, EXx } },
10128 /* VEX_W_0F58_P_3 */
10129 { "vaddsd", { XMScalar, VexScalar, EXqScalar } },
10132 /* VEX_W_0F59_P_0 */
10133 { "vmulps", { XM, Vex, EXx } },
10136 /* VEX_W_0F59_P_1 */
10137 { "vmulss", { XMScalar, VexScalar, EXdScalar } },
10140 /* VEX_W_0F59_P_2 */
10141 { "vmulpd", { XM, Vex, EXx } },
10144 /* VEX_W_0F59_P_3 */
10145 { "vmulsd", { XMScalar, VexScalar, EXqScalar } },
10148 /* VEX_W_0F5A_P_0 */
10149 { "vcvtps2pd", { XM, EXxmmq } },
10152 /* VEX_W_0F5A_P_1 */
10153 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar } },
10156 /* VEX_W_0F5A_P_3 */
10157 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar } },
10160 /* VEX_W_0F5B_P_0 */
10161 { "vcvtdq2ps", { XM, EXx } },
10164 /* VEX_W_0F5B_P_1 */
10165 { "vcvttps2dq", { XM, EXx } },
10168 /* VEX_W_0F5B_P_2 */
10169 { "vcvtps2dq", { XM, EXx } },
10172 /* VEX_W_0F5C_P_0 */
10173 { "vsubps", { XM, Vex, EXx } },
10176 /* VEX_W_0F5C_P_1 */
10177 { "vsubss", { XMScalar, VexScalar, EXdScalar } },
10180 /* VEX_W_0F5C_P_2 */
10181 { "vsubpd", { XM, Vex, EXx } },
10184 /* VEX_W_0F5C_P_3 */
10185 { "vsubsd", { XMScalar, VexScalar, EXqScalar } },
10188 /* VEX_W_0F5D_P_0 */
10189 { "vminps", { XM, Vex, EXx } },
10192 /* VEX_W_0F5D_P_1 */
10193 { "vminss", { XMScalar, VexScalar, EXdScalar } },
10196 /* VEX_W_0F5D_P_2 */
10197 { "vminpd", { XM, Vex, EXx } },
10200 /* VEX_W_0F5D_P_3 */
10201 { "vminsd", { XMScalar, VexScalar, EXqScalar } },
10204 /* VEX_W_0F5E_P_0 */
10205 { "vdivps", { XM, Vex, EXx } },
10208 /* VEX_W_0F5E_P_1 */
10209 { "vdivss", { XMScalar, VexScalar, EXdScalar } },
10212 /* VEX_W_0F5E_P_2 */
10213 { "vdivpd", { XM, Vex, EXx } },
10216 /* VEX_W_0F5E_P_3 */
10217 { "vdivsd", { XMScalar, VexScalar, EXqScalar } },
10220 /* VEX_W_0F5F_P_0 */
10221 { "vmaxps", { XM, Vex, EXx } },
10224 /* VEX_W_0F5F_P_1 */
10225 { "vmaxss", { XMScalar, VexScalar, EXdScalar } },
10228 /* VEX_W_0F5F_P_2 */
10229 { "vmaxpd", { XM, Vex, EXx } },
10232 /* VEX_W_0F5F_P_3 */
10233 { "vmaxsd", { XMScalar, VexScalar, EXqScalar } },
10236 /* VEX_W_0F60_P_2 */
10237 { "vpunpcklbw", { XM, Vex, EXx } },
10240 /* VEX_W_0F61_P_2 */
10241 { "vpunpcklwd", { XM, Vex, EXx } },
10244 /* VEX_W_0F62_P_2 */
10245 { "vpunpckldq", { XM, Vex, EXx } },
10248 /* VEX_W_0F63_P_2 */
10249 { "vpacksswb", { XM, Vex, EXx } },
10252 /* VEX_W_0F64_P_2 */
10253 { "vpcmpgtb", { XM, Vex, EXx } },
10256 /* VEX_W_0F65_P_2 */
10257 { "vpcmpgtw", { XM, Vex, EXx } },
10260 /* VEX_W_0F66_P_2 */
10261 { "vpcmpgtd", { XM, Vex, EXx } },
10264 /* VEX_W_0F67_P_2 */
10265 { "vpackuswb", { XM, Vex, EXx } },
10268 /* VEX_W_0F68_P_2 */
10269 { "vpunpckhbw", { XM, Vex, EXx } },
10272 /* VEX_W_0F69_P_2 */
10273 { "vpunpckhwd", { XM, Vex, EXx } },
10276 /* VEX_W_0F6A_P_2 */
10277 { "vpunpckhdq", { XM, Vex, EXx } },
10280 /* VEX_W_0F6B_P_2 */
10281 { "vpackssdw", { XM, Vex, EXx } },
10284 /* VEX_W_0F6C_P_2 */
10285 { "vpunpcklqdq", { XM, Vex, EXx } },
10288 /* VEX_W_0F6D_P_2 */
10289 { "vpunpckhqdq", { XM, Vex, EXx } },
10292 /* VEX_W_0F6F_P_1 */
10293 { "vmovdqu", { XM, EXx } },
10296 /* VEX_W_0F6F_P_2 */
10297 { "vmovdqa", { XM, EXx } },
10300 /* VEX_W_0F70_P_1 */
10301 { "vpshufhw", { XM, EXx, Ib } },
10304 /* VEX_W_0F70_P_2 */
10305 { "vpshufd", { XM, EXx, Ib } },
10308 /* VEX_W_0F70_P_3 */
10309 { "vpshuflw", { XM, EXx, Ib } },
10312 /* VEX_W_0F71_R_2_P_2 */
10313 { "vpsrlw", { Vex, XS, Ib } },
10316 /* VEX_W_0F71_R_4_P_2 */
10317 { "vpsraw", { Vex, XS, Ib } },
10320 /* VEX_W_0F71_R_6_P_2 */
10321 { "vpsllw", { Vex, XS, Ib } },
10324 /* VEX_W_0F72_R_2_P_2 */
10325 { "vpsrld", { Vex, XS, Ib } },
10328 /* VEX_W_0F72_R_4_P_2 */
10329 { "vpsrad", { Vex, XS, Ib } },
10332 /* VEX_W_0F72_R_6_P_2 */
10333 { "vpslld", { Vex, XS, Ib } },
10336 /* VEX_W_0F73_R_2_P_2 */
10337 { "vpsrlq", { Vex, XS, Ib } },
10340 /* VEX_W_0F73_R_3_P_2 */
10341 { "vpsrldq", { Vex, XS, Ib } },
10344 /* VEX_W_0F73_R_6_P_2 */
10345 { "vpsllq", { Vex, XS, Ib } },
10348 /* VEX_W_0F73_R_7_P_2 */
10349 { "vpslldq", { Vex, XS, Ib } },
10352 /* VEX_W_0F74_P_2 */
10353 { "vpcmpeqb", { XM, Vex, EXx } },
10356 /* VEX_W_0F75_P_2 */
10357 { "vpcmpeqw", { XM, Vex, EXx } },
10360 /* VEX_W_0F76_P_2 */
10361 { "vpcmpeqd", { XM, Vex, EXx } },
10364 /* VEX_W_0F77_P_0 */
10368 /* VEX_W_0F7C_P_2 */
10369 { "vhaddpd", { XM, Vex, EXx } },
10372 /* VEX_W_0F7C_P_3 */
10373 { "vhaddps", { XM, Vex, EXx } },
10376 /* VEX_W_0F7D_P_2 */
10377 { "vhsubpd", { XM, Vex, EXx } },
10380 /* VEX_W_0F7D_P_3 */
10381 { "vhsubps", { XM, Vex, EXx } },
10384 /* VEX_W_0F7E_P_1 */
10385 { "vmovq", { XMScalar, EXqScalar } },
10388 /* VEX_W_0F7F_P_1 */
10389 { "vmovdqu", { EXxS, XM } },
10392 /* VEX_W_0F7F_P_2 */
10393 { "vmovdqa", { EXxS, XM } },
10396 /* VEX_W_0F90_P_0_LEN_0 */
10397 { "kmovw", { MaskG, MaskE } },
10400 /* VEX_W_0F91_P_0_LEN_0 */
10401 { "kmovw", { Ew, MaskG } },
10404 /* VEX_W_0F92_P_0_LEN_0 */
10405 { "kmovw", { MaskG, Rdq } },
10408 /* VEX_W_0F93_P_0_LEN_0 */
10409 { "kmovw", { Gdq, MaskR } },
10412 /* VEX_W_0F98_P_0_LEN_0 */
10413 { "kortestw", { MaskG, MaskR } },
10416 /* VEX_W_0FAE_R_2_M_0 */
10417 { "vldmxcsr", { Md } },
10420 /* VEX_W_0FAE_R_3_M_0 */
10421 { "vstmxcsr", { Md } },
10424 /* VEX_W_0FC2_P_0 */
10425 { "vcmpps", { XM, Vex, EXx, VCMP } },
10428 /* VEX_W_0FC2_P_1 */
10429 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP } },
10432 /* VEX_W_0FC2_P_2 */
10433 { "vcmppd", { XM, Vex, EXx, VCMP } },
10436 /* VEX_W_0FC2_P_3 */
10437 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP } },
10440 /* VEX_W_0FC4_P_2 */
10441 { "vpinsrw", { XM, Vex128, Edqw, Ib } },
10444 /* VEX_W_0FC5_P_2 */
10445 { "vpextrw", { Gdq, XS, Ib } },
10448 /* VEX_W_0FD0_P_2 */
10449 { "vaddsubpd", { XM, Vex, EXx } },
10452 /* VEX_W_0FD0_P_3 */
10453 { "vaddsubps", { XM, Vex, EXx } },
10456 /* VEX_W_0FD1_P_2 */
10457 { "vpsrlw", { XM, Vex, EXxmm } },
10460 /* VEX_W_0FD2_P_2 */
10461 { "vpsrld", { XM, Vex, EXxmm } },
10464 /* VEX_W_0FD3_P_2 */
10465 { "vpsrlq", { XM, Vex, EXxmm } },
10468 /* VEX_W_0FD4_P_2 */
10469 { "vpaddq", { XM, Vex, EXx } },
10472 /* VEX_W_0FD5_P_2 */
10473 { "vpmullw", { XM, Vex, EXx } },
10476 /* VEX_W_0FD6_P_2 */
10477 { "vmovq", { EXqScalarS, XMScalar } },
10480 /* VEX_W_0FD7_P_2_M_1 */
10481 { "vpmovmskb", { Gdq, XS } },
10484 /* VEX_W_0FD8_P_2 */
10485 { "vpsubusb", { XM, Vex, EXx } },
10488 /* VEX_W_0FD9_P_2 */
10489 { "vpsubusw", { XM, Vex, EXx } },
10492 /* VEX_W_0FDA_P_2 */
10493 { "vpminub", { XM, Vex, EXx } },
10496 /* VEX_W_0FDB_P_2 */
10497 { "vpand", { XM, Vex, EXx } },
10500 /* VEX_W_0FDC_P_2 */
10501 { "vpaddusb", { XM, Vex, EXx } },
10504 /* VEX_W_0FDD_P_2 */
10505 { "vpaddusw", { XM, Vex, EXx } },
10508 /* VEX_W_0FDE_P_2 */
10509 { "vpmaxub", { XM, Vex, EXx } },
10512 /* VEX_W_0FDF_P_2 */
10513 { "vpandn", { XM, Vex, EXx } },
10516 /* VEX_W_0FE0_P_2 */
10517 { "vpavgb", { XM, Vex, EXx } },
10520 /* VEX_W_0FE1_P_2 */
10521 { "vpsraw", { XM, Vex, EXxmm } },
10524 /* VEX_W_0FE2_P_2 */
10525 { "vpsrad", { XM, Vex, EXxmm } },
10528 /* VEX_W_0FE3_P_2 */
10529 { "vpavgw", { XM, Vex, EXx } },
10532 /* VEX_W_0FE4_P_2 */
10533 { "vpmulhuw", { XM, Vex, EXx } },
10536 /* VEX_W_0FE5_P_2 */
10537 { "vpmulhw", { XM, Vex, EXx } },
10540 /* VEX_W_0FE6_P_1 */
10541 { "vcvtdq2pd", { XM, EXxmmq } },
10544 /* VEX_W_0FE6_P_2 */
10545 { "vcvttpd2dq%XY", { XMM, EXx } },
10548 /* VEX_W_0FE6_P_3 */
10549 { "vcvtpd2dq%XY", { XMM, EXx } },
10552 /* VEX_W_0FE7_P_2_M_0 */
10553 { "vmovntdq", { Mx, XM } },
10556 /* VEX_W_0FE8_P_2 */
10557 { "vpsubsb", { XM, Vex, EXx } },
10560 /* VEX_W_0FE9_P_2 */
10561 { "vpsubsw", { XM, Vex, EXx } },
10564 /* VEX_W_0FEA_P_2 */
10565 { "vpminsw", { XM, Vex, EXx } },
10568 /* VEX_W_0FEB_P_2 */
10569 { "vpor", { XM, Vex, EXx } },
10572 /* VEX_W_0FEC_P_2 */
10573 { "vpaddsb", { XM, Vex, EXx } },
10576 /* VEX_W_0FED_P_2 */
10577 { "vpaddsw", { XM, Vex, EXx } },
10580 /* VEX_W_0FEE_P_2 */
10581 { "vpmaxsw", { XM, Vex, EXx } },
10584 /* VEX_W_0FEF_P_2 */
10585 { "vpxor", { XM, Vex, EXx } },
10588 /* VEX_W_0FF0_P_3_M_0 */
10589 { "vlddqu", { XM, M } },
10592 /* VEX_W_0FF1_P_2 */
10593 { "vpsllw", { XM, Vex, EXxmm } },
10596 /* VEX_W_0FF2_P_2 */
10597 { "vpslld", { XM, Vex, EXxmm } },
10600 /* VEX_W_0FF3_P_2 */
10601 { "vpsllq", { XM, Vex, EXxmm } },
10604 /* VEX_W_0FF4_P_2 */
10605 { "vpmuludq", { XM, Vex, EXx } },
10608 /* VEX_W_0FF5_P_2 */
10609 { "vpmaddwd", { XM, Vex, EXx } },
10612 /* VEX_W_0FF6_P_2 */
10613 { "vpsadbw", { XM, Vex, EXx } },
10616 /* VEX_W_0FF7_P_2 */
10617 { "vmaskmovdqu", { XM, XS } },
10620 /* VEX_W_0FF8_P_2 */
10621 { "vpsubb", { XM, Vex, EXx } },
10624 /* VEX_W_0FF9_P_2 */
10625 { "vpsubw", { XM, Vex, EXx } },
10628 /* VEX_W_0FFA_P_2 */
10629 { "vpsubd", { XM, Vex, EXx } },
10632 /* VEX_W_0FFB_P_2 */
10633 { "vpsubq", { XM, Vex, EXx } },
10636 /* VEX_W_0FFC_P_2 */
10637 { "vpaddb", { XM, Vex, EXx } },
10640 /* VEX_W_0FFD_P_2 */
10641 { "vpaddw", { XM, Vex, EXx } },
10644 /* VEX_W_0FFE_P_2 */
10645 { "vpaddd", { XM, Vex, EXx } },
10648 /* VEX_W_0F3800_P_2 */
10649 { "vpshufb", { XM, Vex, EXx } },
10652 /* VEX_W_0F3801_P_2 */
10653 { "vphaddw", { XM, Vex, EXx } },
10656 /* VEX_W_0F3802_P_2 */
10657 { "vphaddd", { XM, Vex, EXx } },
10660 /* VEX_W_0F3803_P_2 */
10661 { "vphaddsw", { XM, Vex, EXx } },
10664 /* VEX_W_0F3804_P_2 */
10665 { "vpmaddubsw", { XM, Vex, EXx } },
10668 /* VEX_W_0F3805_P_2 */
10669 { "vphsubw", { XM, Vex, EXx } },
10672 /* VEX_W_0F3806_P_2 */
10673 { "vphsubd", { XM, Vex, EXx } },
10676 /* VEX_W_0F3807_P_2 */
10677 { "vphsubsw", { XM, Vex, EXx } },
10680 /* VEX_W_0F3808_P_2 */
10681 { "vpsignb", { XM, Vex, EXx } },
10684 /* VEX_W_0F3809_P_2 */
10685 { "vpsignw", { XM, Vex, EXx } },
10688 /* VEX_W_0F380A_P_2 */
10689 { "vpsignd", { XM, Vex, EXx } },
10692 /* VEX_W_0F380B_P_2 */
10693 { "vpmulhrsw", { XM, Vex, EXx } },
10696 /* VEX_W_0F380C_P_2 */
10697 { "vpermilps", { XM, Vex, EXx } },
10700 /* VEX_W_0F380D_P_2 */
10701 { "vpermilpd", { XM, Vex, EXx } },
10704 /* VEX_W_0F380E_P_2 */
10705 { "vtestps", { XM, EXx } },
10708 /* VEX_W_0F380F_P_2 */
10709 { "vtestpd", { XM, EXx } },
10712 /* VEX_W_0F3816_P_2 */
10713 { "vpermps", { XM, Vex, EXx } },
10716 /* VEX_W_0F3817_P_2 */
10717 { "vptest", { XM, EXx } },
10720 /* VEX_W_0F3818_P_2 */
10721 { "vbroadcastss", { XM, EXxmm_md } },
10724 /* VEX_W_0F3819_P_2 */
10725 { "vbroadcastsd", { XM, EXxmm_mq } },
10728 /* VEX_W_0F381A_P_2_M_0 */
10729 { "vbroadcastf128", { XM, Mxmm } },
10732 /* VEX_W_0F381C_P_2 */
10733 { "vpabsb", { XM, EXx } },
10736 /* VEX_W_0F381D_P_2 */
10737 { "vpabsw", { XM, EXx } },
10740 /* VEX_W_0F381E_P_2 */
10741 { "vpabsd", { XM, EXx } },
10744 /* VEX_W_0F3820_P_2 */
10745 { "vpmovsxbw", { XM, EXxmmq } },
10748 /* VEX_W_0F3821_P_2 */
10749 { "vpmovsxbd", { XM, EXxmmqd } },
10752 /* VEX_W_0F3822_P_2 */
10753 { "vpmovsxbq", { XM, EXxmmdw } },
10756 /* VEX_W_0F3823_P_2 */
10757 { "vpmovsxwd", { XM, EXxmmq } },
10760 /* VEX_W_0F3824_P_2 */
10761 { "vpmovsxwq", { XM, EXxmmqd } },
10764 /* VEX_W_0F3825_P_2 */
10765 { "vpmovsxdq", { XM, EXxmmq } },
10768 /* VEX_W_0F3828_P_2 */
10769 { "vpmuldq", { XM, Vex, EXx } },
10772 /* VEX_W_0F3829_P_2 */
10773 { "vpcmpeqq", { XM, Vex, EXx } },
10776 /* VEX_W_0F382A_P_2_M_0 */
10777 { "vmovntdqa", { XM, Mx } },
10780 /* VEX_W_0F382B_P_2 */
10781 { "vpackusdw", { XM, Vex, EXx } },
10784 /* VEX_W_0F382C_P_2_M_0 */
10785 { "vmaskmovps", { XM, Vex, Mx } },
10788 /* VEX_W_0F382D_P_2_M_0 */
10789 { "vmaskmovpd", { XM, Vex, Mx } },
10792 /* VEX_W_0F382E_P_2_M_0 */
10793 { "vmaskmovps", { Mx, Vex, XM } },
10796 /* VEX_W_0F382F_P_2_M_0 */
10797 { "vmaskmovpd", { Mx, Vex, XM } },
10800 /* VEX_W_0F3830_P_2 */
10801 { "vpmovzxbw", { XM, EXxmmq } },
10804 /* VEX_W_0F3831_P_2 */
10805 { "vpmovzxbd", { XM, EXxmmqd } },
10808 /* VEX_W_0F3832_P_2 */
10809 { "vpmovzxbq", { XM, EXxmmdw } },
10812 /* VEX_W_0F3833_P_2 */
10813 { "vpmovzxwd", { XM, EXxmmq } },
10816 /* VEX_W_0F3834_P_2 */
10817 { "vpmovzxwq", { XM, EXxmmqd } },
10820 /* VEX_W_0F3835_P_2 */
10821 { "vpmovzxdq", { XM, EXxmmq } },
10824 /* VEX_W_0F3836_P_2 */
10825 { "vpermd", { XM, Vex, EXx } },
10828 /* VEX_W_0F3837_P_2 */
10829 { "vpcmpgtq", { XM, Vex, EXx } },
10832 /* VEX_W_0F3838_P_2 */
10833 { "vpminsb", { XM, Vex, EXx } },
10836 /* VEX_W_0F3839_P_2 */
10837 { "vpminsd", { XM, Vex, EXx } },
10840 /* VEX_W_0F383A_P_2 */
10841 { "vpminuw", { XM, Vex, EXx } },
10844 /* VEX_W_0F383B_P_2 */
10845 { "vpminud", { XM, Vex, EXx } },
10848 /* VEX_W_0F383C_P_2 */
10849 { "vpmaxsb", { XM, Vex, EXx } },
10852 /* VEX_W_0F383D_P_2 */
10853 { "vpmaxsd", { XM, Vex, EXx } },
10856 /* VEX_W_0F383E_P_2 */
10857 { "vpmaxuw", { XM, Vex, EXx } },
10860 /* VEX_W_0F383F_P_2 */
10861 { "vpmaxud", { XM, Vex, EXx } },
10864 /* VEX_W_0F3840_P_2 */
10865 { "vpmulld", { XM, Vex, EXx } },
10868 /* VEX_W_0F3841_P_2 */
10869 { "vphminposuw", { XM, EXx } },
10872 /* VEX_W_0F3846_P_2 */
10873 { "vpsravd", { XM, Vex, EXx } },
10876 /* VEX_W_0F3858_P_2 */
10877 { "vpbroadcastd", { XM, EXxmm_md } },
10880 /* VEX_W_0F3859_P_2 */
10881 { "vpbroadcastq", { XM, EXxmm_mq } },
10884 /* VEX_W_0F385A_P_2_M_0 */
10885 { "vbroadcasti128", { XM, Mxmm } },
10888 /* VEX_W_0F3878_P_2 */
10889 { "vpbroadcastb", { XM, EXxmm_mb } },
10892 /* VEX_W_0F3879_P_2 */
10893 { "vpbroadcastw", { XM, EXxmm_mw } },
10896 /* VEX_W_0F38DB_P_2 */
10897 { "vaesimc", { XM, EXx } },
10900 /* VEX_W_0F38DC_P_2 */
10901 { "vaesenc", { XM, Vex128, EXx } },
10904 /* VEX_W_0F38DD_P_2 */
10905 { "vaesenclast", { XM, Vex128, EXx } },
10908 /* VEX_W_0F38DE_P_2 */
10909 { "vaesdec", { XM, Vex128, EXx } },
10912 /* VEX_W_0F38DF_P_2 */
10913 { "vaesdeclast", { XM, Vex128, EXx } },
10916 /* VEX_W_0F3A00_P_2 */
10918 { "vpermq", { XM, EXx, Ib } },
10921 /* VEX_W_0F3A01_P_2 */
10923 { "vpermpd", { XM, EXx, Ib } },
10926 /* VEX_W_0F3A02_P_2 */
10927 { "vpblendd", { XM, Vex, EXx, Ib } },
10930 /* VEX_W_0F3A04_P_2 */
10931 { "vpermilps", { XM, EXx, Ib } },
10934 /* VEX_W_0F3A05_P_2 */
10935 { "vpermilpd", { XM, EXx, Ib } },
10938 /* VEX_W_0F3A06_P_2 */
10939 { "vperm2f128", { XM, Vex256, EXx, Ib } },
10942 /* VEX_W_0F3A08_P_2 */
10943 { "vroundps", { XM, EXx, Ib } },
10946 /* VEX_W_0F3A09_P_2 */
10947 { "vroundpd", { XM, EXx, Ib } },
10950 /* VEX_W_0F3A0A_P_2 */
10951 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib } },
10954 /* VEX_W_0F3A0B_P_2 */
10955 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib } },
10958 /* VEX_W_0F3A0C_P_2 */
10959 { "vblendps", { XM, Vex, EXx, Ib } },
10962 /* VEX_W_0F3A0D_P_2 */
10963 { "vblendpd", { XM, Vex, EXx, Ib } },
10966 /* VEX_W_0F3A0E_P_2 */
10967 { "vpblendw", { XM, Vex, EXx, Ib } },
10970 /* VEX_W_0F3A0F_P_2 */
10971 { "vpalignr", { XM, Vex, EXx, Ib } },
10974 /* VEX_W_0F3A14_P_2 */
10975 { "vpextrb", { Edqb, XM, Ib } },
10978 /* VEX_W_0F3A15_P_2 */
10979 { "vpextrw", { Edqw, XM, Ib } },
10982 /* VEX_W_0F3A18_P_2 */
10983 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },
10986 /* VEX_W_0F3A19_P_2 */
10987 { "vextractf128", { EXxmm, XM, Ib } },
10990 /* VEX_W_0F3A20_P_2 */
10991 { "vpinsrb", { XM, Vex128, Edqb, Ib } },
10994 /* VEX_W_0F3A21_P_2 */
10995 { "vinsertps", { XM, Vex128, EXd, Ib } },
10998 /* VEX_W_0F3A30_P_2 */
11000 { "kshiftrw", { MaskG, MaskR, Ib } },
11003 /* VEX_W_0F3A32_P_2 */
11005 { "kshiftlw", { MaskG, MaskR, Ib } },
11008 /* VEX_W_0F3A38_P_2 */
11009 { "vinserti128", { XM, Vex256, EXxmm, Ib } },
11012 /* VEX_W_0F3A39_P_2 */
11013 { "vextracti128", { EXxmm, XM, Ib } },
11016 /* VEX_W_0F3A40_P_2 */
11017 { "vdpps", { XM, Vex, EXx, Ib } },
11020 /* VEX_W_0F3A41_P_2 */
11021 { "vdppd", { XM, Vex128, EXx, Ib } },
11024 /* VEX_W_0F3A42_P_2 */
11025 { "vmpsadbw", { XM, Vex, EXx, Ib } },
11028 /* VEX_W_0F3A44_P_2 */
11029 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } },
11032 /* VEX_W_0F3A46_P_2 */
11033 { "vperm2i128", { XM, Vex256, EXx, Ib } },
11036 /* VEX_W_0F3A48_P_2 */
11037 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11038 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11041 /* VEX_W_0F3A49_P_2 */
11042 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11043 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11046 /* VEX_W_0F3A4A_P_2 */
11047 { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
11050 /* VEX_W_0F3A4B_P_2 */
11051 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
11054 /* VEX_W_0F3A4C_P_2 */
11055 { "vpblendvb", { XM, Vex, EXx, XMVexI4 } },
11058 /* VEX_W_0F3A60_P_2 */
11059 { "vpcmpestrm", { XM, EXx, Ib } },
11062 /* VEX_W_0F3A61_P_2 */
11063 { "vpcmpestri", { XM, EXx, Ib } },
11066 /* VEX_W_0F3A62_P_2 */
11067 { "vpcmpistrm", { XM, EXx, Ib } },
11070 /* VEX_W_0F3A63_P_2 */
11071 { "vpcmpistri", { XM, EXx, Ib } },
11074 /* VEX_W_0F3ADF_P_2 */
11075 { "vaeskeygenassist", { XM, EXx, Ib } },
11077 #define NEED_VEX_W_TABLE
11078 #include "i386-dis-evex.h"
11079 #undef NEED_VEX_W_TABLE
11082 static const struct dis386 mod_table[][2] = {
11085 { "leaS", { Gv, M } },
11090 { RM_TABLE (RM_C6_REG_7) },
11095 { RM_TABLE (RM_C7_REG_7) },
11099 { "Jcall{T|}", { indirEp } },
11103 { "Jjmp{T|}", { indirEp } },
11106 /* MOD_0F01_REG_0 */
11107 { X86_64_TABLE (X86_64_0F01_REG_0) },
11108 { RM_TABLE (RM_0F01_REG_0) },
11111 /* MOD_0F01_REG_1 */
11112 { X86_64_TABLE (X86_64_0F01_REG_1) },
11113 { RM_TABLE (RM_0F01_REG_1) },
11116 /* MOD_0F01_REG_2 */
11117 { X86_64_TABLE (X86_64_0F01_REG_2) },
11118 { RM_TABLE (RM_0F01_REG_2) },
11121 /* MOD_0F01_REG_3 */
11122 { X86_64_TABLE (X86_64_0F01_REG_3) },
11123 { RM_TABLE (RM_0F01_REG_3) },
11126 /* MOD_0F01_REG_7 */
11127 { "invlpg", { Mb } },
11128 { RM_TABLE (RM_0F01_REG_7) },
11131 /* MOD_0F12_PREFIX_0 */
11132 { "movlps", { XM, EXq } },
11133 { "movhlps", { XM, EXq } },
11137 { "movlpX", { EXq, XM } },
11140 /* MOD_0F16_PREFIX_0 */
11141 { "movhps", { XM, EXq } },
11142 { "movlhps", { XM, EXq } },
11146 { "movhpX", { EXq, XM } },
11149 /* MOD_0F18_REG_0 */
11150 { "prefetchnta", { Mb } },
11153 /* MOD_0F18_REG_1 */
11154 { "prefetcht0", { Mb } },
11157 /* MOD_0F18_REG_2 */
11158 { "prefetcht1", { Mb } },
11161 /* MOD_0F18_REG_3 */
11162 { "prefetcht2", { Mb } },
11165 /* MOD_0F18_REG_4 */
11166 { "nop/reserved", { Mb } },
11169 /* MOD_0F18_REG_5 */
11170 { "nop/reserved", { Mb } },
11173 /* MOD_0F18_REG_6 */
11174 { "nop/reserved", { Mb } },
11177 /* MOD_0F18_REG_7 */
11178 { "nop/reserved", { Mb } },
11181 /* MOD_0F1A_PREFIX_0 */
11182 { "bndldx", { Gbnd, Ev_bnd } },
11183 { "nopQ", { Ev } },
11186 /* MOD_0F1B_PREFIX_0 */
11187 { "bndstx", { Ev_bnd, Gbnd } },
11188 { "nopQ", { Ev } },
11191 /* MOD_0F1B_PREFIX_1 */
11192 { "bndmk", { Gbnd, Ev_bnd } },
11193 { "nopQ", { Ev } },
11198 { "movZ", { Rm, Cm } },
11203 { "movZ", { Rm, Dm } },
11208 { "movZ", { Cm, Rm } },
11213 { "movZ", { Dm, Rm } },
11218 { "movL", { Rd, Td } },
11223 { "movL", { Td, Rd } },
11226 /* MOD_0F2B_PREFIX_0 */
11227 {"movntps", { Mx, XM } },
11230 /* MOD_0F2B_PREFIX_1 */
11231 {"movntss", { Md, XM } },
11234 /* MOD_0F2B_PREFIX_2 */
11235 {"movntpd", { Mx, XM } },
11238 /* MOD_0F2B_PREFIX_3 */
11239 {"movntsd", { Mq, XM } },
11244 { "movmskpX", { Gdq, XS } },
11247 /* MOD_0F71_REG_2 */
11249 { "psrlw", { MS, Ib } },
11252 /* MOD_0F71_REG_4 */
11254 { "psraw", { MS, Ib } },
11257 /* MOD_0F71_REG_6 */
11259 { "psllw", { MS, Ib } },
11262 /* MOD_0F72_REG_2 */
11264 { "psrld", { MS, Ib } },
11267 /* MOD_0F72_REG_4 */
11269 { "psrad", { MS, Ib } },
11272 /* MOD_0F72_REG_6 */
11274 { "pslld", { MS, Ib } },
11277 /* MOD_0F73_REG_2 */
11279 { "psrlq", { MS, Ib } },
11282 /* MOD_0F73_REG_3 */
11284 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11287 /* MOD_0F73_REG_6 */
11289 { "psllq", { MS, Ib } },
11292 /* MOD_0F73_REG_7 */
11294 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11297 /* MOD_0FAE_REG_0 */
11298 { "fxsave", { FXSAVE } },
11299 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11302 /* MOD_0FAE_REG_1 */
11303 { "fxrstor", { FXSAVE } },
11304 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11307 /* MOD_0FAE_REG_2 */
11308 { "ldmxcsr", { Md } },
11309 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11312 /* MOD_0FAE_REG_3 */
11313 { "stmxcsr", { Md } },
11314 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11317 /* MOD_0FAE_REG_4 */
11318 { "xsave", { FXSAVE } },
11321 /* MOD_0FAE_REG_5 */
11322 { "xrstor", { FXSAVE } },
11323 { RM_TABLE (RM_0FAE_REG_5) },
11326 /* MOD_0FAE_REG_6 */
11327 { "xsaveopt", { FXSAVE } },
11328 { RM_TABLE (RM_0FAE_REG_6) },
11331 /* MOD_0FAE_REG_7 */
11332 { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11333 { RM_TABLE (RM_0FAE_REG_7) },
11337 { "lssS", { Gv, Mp } },
11341 { "lfsS", { Gv, Mp } },
11345 { "lgsS", { Gv, Mp } },
11348 /* MOD_0FC7_REG_3 */
11349 { "xrstors", { FXSAVE } },
11352 /* MOD_0FC7_REG_4 */
11353 { "xsavec", { FXSAVE } },
11356 /* MOD_0FC7_REG_5 */
11357 { "xsaves", { FXSAVE } },
11360 /* MOD_0FC7_REG_6 */
11361 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
11362 { "rdrand", { Ev } },
11365 /* MOD_0FC7_REG_7 */
11366 { "vmptrst", { Mq } },
11367 { "rdseed", { Ev } },
11372 { "pmovmskb", { Gdq, MS } },
11375 /* MOD_0FE7_PREFIX_2 */
11376 { "movntdq", { Mx, XM } },
11379 /* MOD_0FF0_PREFIX_3 */
11380 { "lddqu", { XM, M } },
11383 /* MOD_0F382A_PREFIX_2 */
11384 { "movntdqa", { XM, Mx } },
11388 { "bound{S|}", { Gv, Ma } },
11389 { EVEX_TABLE (EVEX_0F) },
11393 { "lesS", { Gv, Mp } },
11394 { VEX_C4_TABLE (VEX_0F) },
11398 { "ldsS", { Gv, Mp } },
11399 { VEX_C5_TABLE (VEX_0F) },
11402 /* MOD_VEX_0F12_PREFIX_0 */
11403 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11404 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11408 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11411 /* MOD_VEX_0F16_PREFIX_0 */
11412 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11413 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11417 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11421 { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11426 { VEX_W_TABLE (VEX_W_0F50_M_0) },
11429 /* MOD_VEX_0F71_REG_2 */
11431 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11434 /* MOD_VEX_0F71_REG_4 */
11436 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11439 /* MOD_VEX_0F71_REG_6 */
11441 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11444 /* MOD_VEX_0F72_REG_2 */
11446 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11449 /* MOD_VEX_0F72_REG_4 */
11451 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11454 /* MOD_VEX_0F72_REG_6 */
11456 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11459 /* MOD_VEX_0F73_REG_2 */
11461 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11464 /* MOD_VEX_0F73_REG_3 */
11466 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11469 /* MOD_VEX_0F73_REG_6 */
11471 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11474 /* MOD_VEX_0F73_REG_7 */
11476 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11479 /* MOD_VEX_0FAE_REG_2 */
11480 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11483 /* MOD_VEX_0FAE_REG_3 */
11484 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11487 /* MOD_VEX_0FD7_PREFIX_2 */
11489 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11492 /* MOD_VEX_0FE7_PREFIX_2 */
11493 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11496 /* MOD_VEX_0FF0_PREFIX_3 */
11497 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11500 /* MOD_VEX_0F381A_PREFIX_2 */
11501 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11504 /* MOD_VEX_0F382A_PREFIX_2 */
11505 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11508 /* MOD_VEX_0F382C_PREFIX_2 */
11509 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11512 /* MOD_VEX_0F382D_PREFIX_2 */
11513 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11516 /* MOD_VEX_0F382E_PREFIX_2 */
11517 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11520 /* MOD_VEX_0F382F_PREFIX_2 */
11521 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11524 /* MOD_VEX_0F385A_PREFIX_2 */
11525 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11528 /* MOD_VEX_0F388C_PREFIX_2 */
11529 { "vpmaskmov%LW", { XM, Vex, Mx } },
11532 /* MOD_VEX_0F388E_PREFIX_2 */
11533 { "vpmaskmov%LW", { Mx, Vex, XM } },
11535 #define NEED_MOD_TABLE
11536 #include "i386-dis-evex.h"
11537 #undef NEED_MOD_TABLE
11540 static const struct dis386 rm_table[][8] = {
11543 { "xabort", { Skip_MODRM, Ib } },
11547 { "xbeginT", { Skip_MODRM, Jv } },
11550 /* RM_0F01_REG_0 */
11552 { "vmcall", { Skip_MODRM } },
11553 { "vmlaunch", { Skip_MODRM } },
11554 { "vmresume", { Skip_MODRM } },
11555 { "vmxoff", { Skip_MODRM } },
11558 /* RM_0F01_REG_1 */
11559 { "monitor", { { OP_Monitor, 0 } } },
11560 { "mwait", { { OP_Mwait, 0 } } },
11561 { "clac", { Skip_MODRM } },
11562 { "stac", { Skip_MODRM } },
11566 { "encls", { Skip_MODRM } },
11569 /* RM_0F01_REG_2 */
11570 { "xgetbv", { Skip_MODRM } },
11571 { "xsetbv", { Skip_MODRM } },
11574 { "vmfunc", { Skip_MODRM } },
11575 { "xend", { Skip_MODRM } },
11576 { "xtest", { Skip_MODRM } },
11577 { "enclu", { Skip_MODRM } },
11580 /* RM_0F01_REG_3 */
11581 { "vmrun", { Skip_MODRM } },
11582 { "vmmcall", { Skip_MODRM } },
11583 { "vmload", { Skip_MODRM } },
11584 { "vmsave", { Skip_MODRM } },
11585 { "stgi", { Skip_MODRM } },
11586 { "clgi", { Skip_MODRM } },
11587 { "skinit", { Skip_MODRM } },
11588 { "invlpga", { Skip_MODRM } },
11591 /* RM_0F01_REG_7 */
11592 { "swapgs", { Skip_MODRM } },
11593 { "rdtscp", { Skip_MODRM } },
11596 /* RM_0FAE_REG_5 */
11597 { "lfence", { Skip_MODRM } },
11600 /* RM_0FAE_REG_6 */
11601 { "mfence", { Skip_MODRM } },
11604 /* RM_0FAE_REG_7 */
11605 { "sfence", { Skip_MODRM } },
11609 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11611 /* We use the high bit to indicate different name for the same
11613 #define ADDR16_PREFIX (0x67 | 0x100)
11614 #define ADDR32_PREFIX (0x67 | 0x200)
11615 #define DATA16_PREFIX (0x66 | 0x100)
11616 #define DATA32_PREFIX (0x66 | 0x200)
11617 #define REP_PREFIX (0xf3 | 0x100)
11618 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11619 #define XRELEASE_PREFIX (0xf3 | 0x400)
11620 #define BND_PREFIX (0xf2 | 0x400)
11625 int newrex, i, length;
11631 last_lock_prefix = -1;
11632 last_repz_prefix = -1;
11633 last_repnz_prefix = -1;
11634 last_data_prefix = -1;
11635 last_addr_prefix = -1;
11636 last_rex_prefix = -1;
11637 last_seg_prefix = -1;
11638 active_seg_prefix = 0;
11639 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11640 all_prefixes[i] = 0;
11643 /* The maximum instruction length is 15bytes. */
11644 while (length < MAX_CODE_LENGTH - 1)
11646 FETCH_DATA (the_info, codep + 1);
11650 /* REX prefixes family. */
11667 if (address_mode == mode_64bit)
11671 last_rex_prefix = i;
11674 prefixes |= PREFIX_REPZ;
11675 last_repz_prefix = i;
11678 prefixes |= PREFIX_REPNZ;
11679 last_repnz_prefix = i;
11682 prefixes |= PREFIX_LOCK;
11683 last_lock_prefix = i;
11686 prefixes |= PREFIX_CS;
11687 last_seg_prefix = i;
11688 active_seg_prefix = PREFIX_CS;
11691 prefixes |= PREFIX_SS;
11692 last_seg_prefix = i;
11693 active_seg_prefix = PREFIX_SS;
11696 prefixes |= PREFIX_DS;
11697 last_seg_prefix = i;
11698 active_seg_prefix = PREFIX_DS;
11701 prefixes |= PREFIX_ES;
11702 last_seg_prefix = i;
11703 active_seg_prefix = PREFIX_ES;
11706 prefixes |= PREFIX_FS;
11707 last_seg_prefix = i;
11708 active_seg_prefix = PREFIX_FS;
11711 prefixes |= PREFIX_GS;
11712 last_seg_prefix = i;
11713 active_seg_prefix = PREFIX_GS;
11716 prefixes |= PREFIX_DATA;
11717 last_data_prefix = i;
11720 prefixes |= PREFIX_ADDR;
11721 last_addr_prefix = i;
11724 /* fwait is really an instruction. If there are prefixes
11725 before the fwait, they belong to the fwait, *not* to the
11726 following instruction. */
11727 if (prefixes || rex)
11729 prefixes |= PREFIX_FWAIT;
11731 /* This ensures that the previous REX prefixes are noticed
11732 as unused prefixes, as in the return case below. */
11736 prefixes = PREFIX_FWAIT;
11741 /* Rex is ignored when followed by another prefix. */
11747 if (*codep != FWAIT_OPCODE)
11748 all_prefixes[i++] = *codep;
11756 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11759 static const char *
11760 prefix_name (int pref, int sizeflag)
11762 static const char *rexes [16] =
11765 "rex.B", /* 0x41 */
11766 "rex.X", /* 0x42 */
11767 "rex.XB", /* 0x43 */
11768 "rex.R", /* 0x44 */
11769 "rex.RB", /* 0x45 */
11770 "rex.RX", /* 0x46 */
11771 "rex.RXB", /* 0x47 */
11772 "rex.W", /* 0x48 */
11773 "rex.WB", /* 0x49 */
11774 "rex.WX", /* 0x4a */
11775 "rex.WXB", /* 0x4b */
11776 "rex.WR", /* 0x4c */
11777 "rex.WRB", /* 0x4d */
11778 "rex.WRX", /* 0x4e */
11779 "rex.WRXB", /* 0x4f */
11784 /* REX prefixes family. */
11801 return rexes [pref - 0x40];
11821 return (sizeflag & DFLAG) ? "data16" : "data32";
11823 if (address_mode == mode_64bit)
11824 return (sizeflag & AFLAG) ? "addr32" : "addr64";
11826 return (sizeflag & AFLAG) ? "addr16" : "addr32";
11829 case ADDR16_PREFIX:
11831 case ADDR32_PREFIX:
11833 case DATA16_PREFIX:
11835 case DATA32_PREFIX:
11839 case XACQUIRE_PREFIX:
11841 case XRELEASE_PREFIX:
11850 static char op_out[MAX_OPERANDS][100];
11851 static int op_ad, op_index[MAX_OPERANDS];
11852 static int two_source_ops;
11853 static bfd_vma op_address[MAX_OPERANDS];
11854 static bfd_vma op_riprel[MAX_OPERANDS];
11855 static bfd_vma start_pc;
11858 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11859 * (see topic "Redundant prefixes" in the "Differences from 8086"
11860 * section of the "Virtual 8086 Mode" chapter.)
11861 * 'pc' should be the address of this instruction, it will
11862 * be used to print the target address if this is a relative jump or call
11863 * The function returns the length of this instruction in bytes.
11866 static char intel_syntax;
11867 static char intel_mnemonic = !SYSV386_COMPAT;
11868 static char open_char;
11869 static char close_char;
11870 static char separator_char;
11871 static char scale_char;
11873 /* Here for backwards compatibility. When gdb stops using
11874 print_insn_i386_att and print_insn_i386_intel these functions can
11875 disappear, and print_insn_i386 be merged into print_insn. */
11877 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11881 return print_insn (pc, info);
11885 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11889 return print_insn (pc, info);
11893 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11897 return print_insn (pc, info);
11901 print_i386_disassembler_options (FILE *stream)
11903 fprintf (stream, _("\n\
11904 The following i386/x86-64 specific disassembler options are supported for use\n\
11905 with the -M switch (multiple options should be separated by commas):\n"));
11907 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
11908 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
11909 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
11910 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
11911 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
11912 fprintf (stream, _(" att-mnemonic\n"
11913 " Display instruction in AT&T mnemonic\n"));
11914 fprintf (stream, _(" intel-mnemonic\n"
11915 " Display instruction in Intel mnemonic\n"));
11916 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
11917 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
11918 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
11919 fprintf (stream, _(" data32 Assume 32bit data size\n"));
11920 fprintf (stream, _(" data16 Assume 16bit data size\n"));
11921 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11925 static const struct dis386 bad_opcode = { "(bad)", { XX } };
11927 /* Get a pointer to struct dis386 with a valid name. */
11929 static const struct dis386 *
11930 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11932 int vindex, vex_table_index;
11934 if (dp->name != NULL)
11937 switch (dp->op[0].bytemode)
11939 case USE_REG_TABLE:
11940 dp = ®_table[dp->op[1].bytemode][modrm.reg];
11943 case USE_MOD_TABLE:
11944 vindex = modrm.mod == 0x3 ? 1 : 0;
11945 dp = &mod_table[dp->op[1].bytemode][vindex];
11949 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11952 case USE_PREFIX_TABLE:
11955 /* The prefix in VEX is implicit. */
11956 switch (vex.prefix)
11961 case REPE_PREFIX_OPCODE:
11964 case DATA_PREFIX_OPCODE:
11967 case REPNE_PREFIX_OPCODE:
11977 int last_prefix = -1;
11980 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11981 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11983 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11985 if (last_repz_prefix > last_repnz_prefix)
11988 prefix = PREFIX_REPZ;
11989 last_prefix = last_repz_prefix;
11994 prefix = PREFIX_REPNZ;
11995 last_prefix = last_repnz_prefix;
11998 /* Ignore the invalid index if it isn't mandatory. */
11999 if (!mandatory_prefix
12000 && (prefix_table[dp->op[1].bytemode][vindex].name
12002 && (prefix_table[dp->op[1].bytemode][vindex].op[0].bytemode
12007 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12010 prefix = PREFIX_DATA;
12011 last_prefix = last_data_prefix;
12016 used_prefixes |= prefix;
12017 all_prefixes[last_prefix] = 0;
12020 dp = &prefix_table[dp->op[1].bytemode][vindex];
12023 case USE_X86_64_TABLE:
12024 vindex = address_mode == mode_64bit ? 1 : 0;
12025 dp = &x86_64_table[dp->op[1].bytemode][vindex];
12028 case USE_3BYTE_TABLE:
12029 FETCH_DATA (info, codep + 2);
12031 dp = &three_byte_table[dp->op[1].bytemode][vindex];
12033 modrm.mod = (*codep >> 6) & 3;
12034 modrm.reg = (*codep >> 3) & 7;
12035 modrm.rm = *codep & 7;
12038 case USE_VEX_LEN_TABLE:
12042 switch (vex.length)
12055 dp = &vex_len_table[dp->op[1].bytemode][vindex];
12058 case USE_XOP_8F_TABLE:
12059 FETCH_DATA (info, codep + 3);
12060 /* All bits in the REX prefix are ignored. */
12062 rex = ~(*codep >> 5) & 0x7;
12064 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12065 switch ((*codep & 0x1f))
12071 vex_table_index = XOP_08;
12074 vex_table_index = XOP_09;
12077 vex_table_index = XOP_0A;
12081 vex.w = *codep & 0x80;
12082 if (vex.w && address_mode == mode_64bit)
12085 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12086 if (address_mode != mode_64bit
12087 && vex.register_specifier > 0x7)
12093 vex.length = (*codep & 0x4) ? 256 : 128;
12094 switch ((*codep & 0x3))
12100 vex.prefix = DATA_PREFIX_OPCODE;
12103 vex.prefix = REPE_PREFIX_OPCODE;
12106 vex.prefix = REPNE_PREFIX_OPCODE;
12113 dp = &xop_table[vex_table_index][vindex];
12116 FETCH_DATA (info, codep + 1);
12117 modrm.mod = (*codep >> 6) & 3;
12118 modrm.reg = (*codep >> 3) & 7;
12119 modrm.rm = *codep & 7;
12122 case USE_VEX_C4_TABLE:
12124 FETCH_DATA (info, codep + 3);
12125 /* All bits in the REX prefix are ignored. */
12127 rex = ~(*codep >> 5) & 0x7;
12128 switch ((*codep & 0x1f))
12134 vex_table_index = VEX_0F;
12137 vex_table_index = VEX_0F38;
12140 vex_table_index = VEX_0F3A;
12144 vex.w = *codep & 0x80;
12145 if (vex.w && address_mode == mode_64bit)
12148 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12149 if (address_mode != mode_64bit
12150 && vex.register_specifier > 0x7)
12156 vex.length = (*codep & 0x4) ? 256 : 128;
12157 switch ((*codep & 0x3))
12163 vex.prefix = DATA_PREFIX_OPCODE;
12166 vex.prefix = REPE_PREFIX_OPCODE;
12169 vex.prefix = REPNE_PREFIX_OPCODE;
12176 dp = &vex_table[vex_table_index][vindex];
12178 /* There is no MODRM byte for VEX [82|77]. */
12179 if (vindex != 0x77 && vindex != 0x82)
12181 FETCH_DATA (info, codep + 1);
12182 modrm.mod = (*codep >> 6) & 3;
12183 modrm.reg = (*codep >> 3) & 7;
12184 modrm.rm = *codep & 7;
12188 case USE_VEX_C5_TABLE:
12190 FETCH_DATA (info, codep + 2);
12191 /* All bits in the REX prefix are ignored. */
12193 rex = (*codep & 0x80) ? 0 : REX_R;
12195 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12196 if (address_mode != mode_64bit
12197 && vex.register_specifier > 0x7)
12205 vex.length = (*codep & 0x4) ? 256 : 128;
12206 switch ((*codep & 0x3))
12212 vex.prefix = DATA_PREFIX_OPCODE;
12215 vex.prefix = REPE_PREFIX_OPCODE;
12218 vex.prefix = REPNE_PREFIX_OPCODE;
12225 dp = &vex_table[dp->op[1].bytemode][vindex];
12227 /* There is no MODRM byte for VEX [82|77]. */
12228 if (vindex != 0x77 && vindex != 0x82)
12230 FETCH_DATA (info, codep + 1);
12231 modrm.mod = (*codep >> 6) & 3;
12232 modrm.reg = (*codep >> 3) & 7;
12233 modrm.rm = *codep & 7;
12237 case USE_VEX_W_TABLE:
12241 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12244 case USE_EVEX_TABLE:
12245 two_source_ops = 0;
12248 FETCH_DATA (info, codep + 4);
12249 /* All bits in the REX prefix are ignored. */
12251 /* The first byte after 0x62. */
12252 rex = ~(*codep >> 5) & 0x7;
12253 vex.r = *codep & 0x10;
12254 switch ((*codep & 0xf))
12257 return &bad_opcode;
12259 vex_table_index = EVEX_0F;
12262 vex_table_index = EVEX_0F38;
12265 vex_table_index = EVEX_0F3A;
12269 /* The second byte after 0x62. */
12271 vex.w = *codep & 0x80;
12272 if (vex.w && address_mode == mode_64bit)
12275 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12276 if (address_mode != mode_64bit)
12278 /* In 16/32-bit mode silently ignore following bits. */
12282 vex.register_specifier &= 0x7;
12286 if (!(*codep & 0x4))
12287 return &bad_opcode;
12289 switch ((*codep & 0x3))
12295 vex.prefix = DATA_PREFIX_OPCODE;
12298 vex.prefix = REPE_PREFIX_OPCODE;
12301 vex.prefix = REPNE_PREFIX_OPCODE;
12305 /* The third byte after 0x62. */
12308 /* Remember the static rounding bits. */
12309 vex.ll = (*codep >> 5) & 3;
12310 vex.b = (*codep & 0x10) != 0;
12312 vex.v = *codep & 0x8;
12313 vex.mask_register_specifier = *codep & 0x7;
12314 vex.zeroing = *codep & 0x80;
12320 dp = &evex_table[vex_table_index][vindex];
12322 FETCH_DATA (info, codep + 1);
12323 modrm.mod = (*codep >> 6) & 3;
12324 modrm.reg = (*codep >> 3) & 7;
12325 modrm.rm = *codep & 7;
12327 /* Set vector length. */
12328 if (modrm.mod == 3 && vex.b)
12344 return &bad_opcode;
12357 if (dp->name != NULL)
12360 return get_valid_dis386 (dp, info);
12364 get_sib (disassemble_info *info, int sizeflag)
12366 /* If modrm.mod == 3, operand must be register. */
12368 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12372 FETCH_DATA (info, codep + 2);
12373 sib.index = (codep [1] >> 3) & 7;
12374 sib.scale = (codep [1] >> 6) & 3;
12375 sib.base = codep [1] & 7;
12380 print_insn (bfd_vma pc, disassemble_info *info)
12382 const struct dis386 *dp;
12384 char *op_txt[MAX_OPERANDS];
12388 struct dis_private priv;
12390 int default_prefixes;
12392 priv.orig_sizeflag = AFLAG | DFLAG;
12393 if ((info->mach & bfd_mach_i386_i386) != 0)
12394 address_mode = mode_32bit;
12395 else if (info->mach == bfd_mach_i386_i8086)
12397 address_mode = mode_16bit;
12398 priv.orig_sizeflag = 0;
12401 address_mode = mode_64bit;
12403 if (intel_syntax == (char) -1)
12404 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12406 for (p = info->disassembler_options; p != NULL; )
12408 if (CONST_STRNEQ (p, "x86-64"))
12410 address_mode = mode_64bit;
12411 priv.orig_sizeflag = AFLAG | DFLAG;
12413 else if (CONST_STRNEQ (p, "i386"))
12415 address_mode = mode_32bit;
12416 priv.orig_sizeflag = AFLAG | DFLAG;
12418 else if (CONST_STRNEQ (p, "i8086"))
12420 address_mode = mode_16bit;
12421 priv.orig_sizeflag = 0;
12423 else if (CONST_STRNEQ (p, "intel"))
12426 if (CONST_STRNEQ (p + 5, "-mnemonic"))
12427 intel_mnemonic = 1;
12429 else if (CONST_STRNEQ (p, "att"))
12432 if (CONST_STRNEQ (p + 3, "-mnemonic"))
12433 intel_mnemonic = 0;
12435 else if (CONST_STRNEQ (p, "addr"))
12437 if (address_mode == mode_64bit)
12439 if (p[4] == '3' && p[5] == '2')
12440 priv.orig_sizeflag &= ~AFLAG;
12441 else if (p[4] == '6' && p[5] == '4')
12442 priv.orig_sizeflag |= AFLAG;
12446 if (p[4] == '1' && p[5] == '6')
12447 priv.orig_sizeflag &= ~AFLAG;
12448 else if (p[4] == '3' && p[5] == '2')
12449 priv.orig_sizeflag |= AFLAG;
12452 else if (CONST_STRNEQ (p, "data"))
12454 if (p[4] == '1' && p[5] == '6')
12455 priv.orig_sizeflag &= ~DFLAG;
12456 else if (p[4] == '3' && p[5] == '2')
12457 priv.orig_sizeflag |= DFLAG;
12459 else if (CONST_STRNEQ (p, "suffix"))
12460 priv.orig_sizeflag |= SUFFIX_ALWAYS;
12462 p = strchr (p, ',');
12469 names64 = intel_names64;
12470 names32 = intel_names32;
12471 names16 = intel_names16;
12472 names8 = intel_names8;
12473 names8rex = intel_names8rex;
12474 names_seg = intel_names_seg;
12475 names_mm = intel_names_mm;
12476 names_bnd = intel_names_bnd;
12477 names_xmm = intel_names_xmm;
12478 names_ymm = intel_names_ymm;
12479 names_zmm = intel_names_zmm;
12480 index64 = intel_index64;
12481 index32 = intel_index32;
12482 names_mask = intel_names_mask;
12483 index16 = intel_index16;
12486 separator_char = '+';
12491 names64 = att_names64;
12492 names32 = att_names32;
12493 names16 = att_names16;
12494 names8 = att_names8;
12495 names8rex = att_names8rex;
12496 names_seg = att_names_seg;
12497 names_mm = att_names_mm;
12498 names_bnd = att_names_bnd;
12499 names_xmm = att_names_xmm;
12500 names_ymm = att_names_ymm;
12501 names_zmm = att_names_zmm;
12502 index64 = att_index64;
12503 index32 = att_index32;
12504 names_mask = att_names_mask;
12505 index16 = att_index16;
12508 separator_char = ',';
12512 /* The output looks better if we put 7 bytes on a line, since that
12513 puts most long word instructions on a single line. Use 8 bytes
12515 if ((info->mach & bfd_mach_l1om) != 0)
12516 info->bytes_per_line = 8;
12518 info->bytes_per_line = 7;
12520 info->private_data = &priv;
12521 priv.max_fetched = priv.the_buffer;
12522 priv.insn_start = pc;
12525 for (i = 0; i < MAX_OPERANDS; ++i)
12533 start_codep = priv.the_buffer;
12534 codep = priv.the_buffer;
12536 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12540 /* Getting here means we tried for data but didn't get it. That
12541 means we have an incomplete instruction of some sort. Just
12542 print the first byte as a prefix or a .byte pseudo-op. */
12543 if (codep > priv.the_buffer)
12545 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12547 (*info->fprintf_func) (info->stream, "%s", name);
12550 /* Just print the first byte as a .byte instruction. */
12551 (*info->fprintf_func) (info->stream, ".byte 0x%x",
12552 (unsigned int) priv.the_buffer[0]);
12562 sizeflag = priv.orig_sizeflag;
12564 if (!ckprefix () || rex_used)
12566 /* Too many prefixes or unused REX prefixes. */
12568 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12570 (*info->fprintf_func) (info->stream, "%s%s",
12572 prefix_name (all_prefixes[i], sizeflag));
12576 insn_codep = codep;
12578 FETCH_DATA (info, codep + 1);
12579 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12581 if (((prefixes & PREFIX_FWAIT)
12582 && ((*codep < 0xd8) || (*codep > 0xdf))))
12584 /* Handle prefixes before fwait. */
12586 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12588 (*info->fprintf_func) (info->stream, "%s ",
12589 prefix_name (all_prefixes[i], sizeflag));
12590 (*info->fprintf_func) (info->stream, "fwait");
12594 if (*codep == 0x0f)
12596 unsigned char threebyte;
12597 FETCH_DATA (info, codep + 2);
12598 threebyte = *++codep;
12599 dp = &dis386_twobyte[threebyte];
12600 need_modrm = twobyte_has_modrm[*codep];
12601 mandatory_prefix = twobyte_has_mandatory_prefix[*codep];
12606 dp = &dis386[*codep];
12607 need_modrm = onebyte_has_modrm[*codep];
12608 mandatory_prefix = 0;
12612 default_prefixes = 0;
12613 if (prefixes & PREFIX_ADDR)
12616 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
12618 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12619 all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
12621 all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
12622 default_prefixes |= PREFIX_ADDR;
12626 if ((prefixes & PREFIX_DATA))
12629 if (dp->op[2].bytemode == cond_jump_mode
12630 && dp->op[0].bytemode == v_mode
12633 if (sizeflag & DFLAG)
12634 all_prefixes[last_data_prefix] = DATA32_PREFIX;
12636 all_prefixes[last_data_prefix] = DATA16_PREFIX;
12637 default_prefixes |= PREFIX_DATA;
12639 else if (rex & REX_W)
12641 /* REX_W will override PREFIX_DATA. */
12642 default_prefixes |= PREFIX_DATA;
12649 FETCH_DATA (info, codep + 1);
12650 modrm.mod = (*codep >> 6) & 3;
12651 modrm.reg = (*codep >> 3) & 7;
12652 modrm.rm = *codep & 7;
12660 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12662 get_sib (info, sizeflag);
12663 dofloat (sizeflag);
12667 dp = get_valid_dis386 (dp, info);
12668 if (dp != NULL && putop (dp->name, sizeflag) == 0)
12670 get_sib (info, sizeflag);
12671 for (i = 0; i < MAX_OPERANDS; ++i)
12674 op_ad = MAX_OPERANDS - 1 - i;
12676 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12677 /* For EVEX instruction after the last operand masking
12678 should be printed. */
12679 if (i == 0 && vex.evex)
12681 /* Don't print {%k0}. */
12682 if (vex.mask_register_specifier)
12685 oappend (names_mask[vex.mask_register_specifier]);
12695 /* Check if the REX prefix is used. */
12696 if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12697 all_prefixes[last_rex_prefix] = 0;
12699 /* Check if the SEG prefix is used. */
12700 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12701 | PREFIX_FS | PREFIX_GS)) != 0
12702 && (used_prefixes & active_seg_prefix) != 0)
12703 all_prefixes[last_seg_prefix] = 0;
12705 /* Check if the ADDR prefix is used. */
12706 if ((prefixes & PREFIX_ADDR) != 0
12707 && (used_prefixes & PREFIX_ADDR) != 0)
12708 all_prefixes[last_addr_prefix] = 0;
12710 /* Check if the DATA prefix is used. Restore the DFLAG bit in
12711 sizeflag if the DATA prefix is unused. */
12712 if ((prefixes & PREFIX_DATA) != 0)
12714 if ((used_prefixes & PREFIX_DATA) != 0)
12715 all_prefixes[last_data_prefix] = 0;
12716 else if ((default_prefixes & PREFIX_DATA) == 0)
12721 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12722 if (all_prefixes[i])
12725 name = prefix_name (all_prefixes[i], sizeflag);
12728 prefix_length += strlen (name) + 1;
12729 (*info->fprintf_func) (info->stream, "%s ", name);
12732 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12733 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12734 used by putop and MMX/SSE operand and may be overriden by the
12735 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12737 if (mandatory_prefix
12738 && dp != &bad_opcode
12740 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12742 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12744 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12746 && (used_prefixes & PREFIX_DATA) == 0))))
12748 (*info->fprintf_func) (info->stream, "(bad)");
12749 return end_codep - priv.the_buffer;
12752 /* Check maximum code length. */
12753 if ((codep - start_codep) > MAX_CODE_LENGTH)
12755 (*info->fprintf_func) (info->stream, "(bad)");
12756 return MAX_CODE_LENGTH;
12759 obufp = mnemonicendp;
12760 for (i = strlen (obuf) + prefix_length; i < 6; i++)
12763 (*info->fprintf_func) (info->stream, "%s", obuf);
12765 /* The enter and bound instructions are printed with operands in the same
12766 order as the intel book; everything else is printed in reverse order. */
12767 if (intel_syntax || two_source_ops)
12771 for (i = 0; i < MAX_OPERANDS; ++i)
12772 op_txt[i] = op_out[i];
12774 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12776 op_ad = op_index[i];
12777 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12778 op_index[MAX_OPERANDS - 1 - i] = op_ad;
12779 riprel = op_riprel[i];
12780 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12781 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12786 for (i = 0; i < MAX_OPERANDS; ++i)
12787 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12791 for (i = 0; i < MAX_OPERANDS; ++i)
12795 (*info->fprintf_func) (info->stream, ",");
12796 if (op_index[i] != -1 && !op_riprel[i])
12797 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12799 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12803 for (i = 0; i < MAX_OPERANDS; i++)
12804 if (op_index[i] != -1 && op_riprel[i])
12806 (*info->fprintf_func) (info->stream, " # ");
12807 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
12808 + op_address[op_index[i]]), info);
12811 return codep - priv.the_buffer;
12814 static const char *float_mem[] = {
12889 static const unsigned char float_mem_mode[] = {
12964 #define ST { OP_ST, 0 }
12965 #define STi { OP_STi, 0 }
12967 #define FGRPd9_2 NULL, { { NULL, 0 } }
12968 #define FGRPd9_4 NULL, { { NULL, 1 } }
12969 #define FGRPd9_5 NULL, { { NULL, 2 } }
12970 #define FGRPd9_6 NULL, { { NULL, 3 } }
12971 #define FGRPd9_7 NULL, { { NULL, 4 } }
12972 #define FGRPda_5 NULL, { { NULL, 5 } }
12973 #define FGRPdb_4 NULL, { { NULL, 6 } }
12974 #define FGRPde_3 NULL, { { NULL, 7 } }
12975 #define FGRPdf_4 NULL, { { NULL, 8 } }
12977 static const struct dis386 float_reg[][8] = {
12980 { "fadd", { ST, STi } },
12981 { "fmul", { ST, STi } },
12982 { "fcom", { STi } },
12983 { "fcomp", { STi } },
12984 { "fsub", { ST, STi } },
12985 { "fsubr", { ST, STi } },
12986 { "fdiv", { ST, STi } },
12987 { "fdivr", { ST, STi } },
12991 { "fld", { STi } },
12992 { "fxch", { STi } },
13002 { "fcmovb", { ST, STi } },
13003 { "fcmove", { ST, STi } },
13004 { "fcmovbe",{ ST, STi } },
13005 { "fcmovu", { ST, STi } },
13013 { "fcmovnb",{ ST, STi } },
13014 { "fcmovne",{ ST, STi } },
13015 { "fcmovnbe",{ ST, STi } },
13016 { "fcmovnu",{ ST, STi } },
13018 { "fucomi", { ST, STi } },
13019 { "fcomi", { ST, STi } },
13024 { "fadd", { STi, ST } },
13025 { "fmul", { STi, ST } },
13028 { "fsub!M", { STi, ST } },
13029 { "fsubM", { STi, ST } },
13030 { "fdiv!M", { STi, ST } },
13031 { "fdivM", { STi, ST } },
13035 { "ffree", { STi } },
13037 { "fst", { STi } },
13038 { "fstp", { STi } },
13039 { "fucom", { STi } },
13040 { "fucomp", { STi } },
13046 { "faddp", { STi, ST } },
13047 { "fmulp", { STi, ST } },
13050 { "fsub!Mp", { STi, ST } },
13051 { "fsubMp", { STi, ST } },
13052 { "fdiv!Mp", { STi, ST } },
13053 { "fdivMp", { STi, ST } },
13057 { "ffreep", { STi } },
13062 { "fucomip", { ST, STi } },
13063 { "fcomip", { ST, STi } },
13068 static char *fgrps[][8] = {
13071 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13076 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13081 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13086 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13091 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13096 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13101 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13102 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13107 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13112 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13117 swap_operand (void)
13119 mnemonicendp[0] = '.';
13120 mnemonicendp[1] = 's';
13125 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13126 int sizeflag ATTRIBUTE_UNUSED)
13128 /* Skip mod/rm byte. */
13134 dofloat (int sizeflag)
13136 const struct dis386 *dp;
13137 unsigned char floatop;
13139 floatop = codep[-1];
13141 if (modrm.mod != 3)
13143 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13145 putop (float_mem[fp_indx], sizeflag);
13148 OP_E (float_mem_mode[fp_indx], sizeflag);
13151 /* Skip mod/rm byte. */
13155 dp = &float_reg[floatop - 0xd8][modrm.reg];
13156 if (dp->name == NULL)
13158 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13160 /* Instruction fnstsw is only one with strange arg. */
13161 if (floatop == 0xdf && codep[-1] == 0xe0)
13162 strcpy (op_out[0], names16[0]);
13166 putop (dp->name, sizeflag);
13171 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13176 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13180 /* Like oappend (below), but S is a string starting with '%'.
13181 In Intel syntax, the '%' is elided. */
13183 oappend_maybe_intel (const char *s)
13185 oappend (s + intel_syntax);
13189 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13191 oappend_maybe_intel ("%st");
13195 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13197 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13198 oappend_maybe_intel (scratchbuf);
13201 /* Capital letters in template are macros. */
13203 putop (const char *in_template, int sizeflag)
13208 unsigned int l = 0, len = 1;
13211 #define SAVE_LAST(c) \
13212 if (l < len && l < sizeof (last)) \
13217 for (p = in_template; *p; p++)
13234 while (*++p != '|')
13235 if (*p == '}' || *p == '\0')
13238 /* Fall through. */
13243 while (*++p != '}')
13254 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13258 if (l == 0 && len == 1)
13263 if (sizeflag & SUFFIX_ALWAYS)
13276 if (address_mode == mode_64bit
13277 && !(prefixes & PREFIX_ADDR))
13288 if (intel_syntax && !alt)
13290 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13292 if (sizeflag & DFLAG)
13293 *obufp++ = intel_syntax ? 'd' : 'l';
13295 *obufp++ = intel_syntax ? 'w' : 's';
13296 used_prefixes |= (prefixes & PREFIX_DATA);
13300 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13303 if (modrm.mod == 3)
13309 if (sizeflag & DFLAG)
13310 *obufp++ = intel_syntax ? 'd' : 'l';
13313 used_prefixes |= (prefixes & PREFIX_DATA);
13319 case 'E': /* For jcxz/jecxz */
13320 if (address_mode == mode_64bit)
13322 if (sizeflag & AFLAG)
13328 if (sizeflag & AFLAG)
13330 used_prefixes |= (prefixes & PREFIX_ADDR);
13335 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13337 if (sizeflag & AFLAG)
13338 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13340 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13341 used_prefixes |= (prefixes & PREFIX_ADDR);
13345 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13347 if ((rex & REX_W) || (sizeflag & DFLAG))
13351 if (!(rex & REX_W))
13352 used_prefixes |= (prefixes & PREFIX_DATA);
13357 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13358 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13360 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13363 if (prefixes & PREFIX_DS)
13384 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13389 /* Fall through. */
13392 if (l != 0 || len != 1)
13400 if (sizeflag & SUFFIX_ALWAYS)
13404 if (intel_mnemonic != cond)
13408 if ((prefixes & PREFIX_FWAIT) == 0)
13411 used_prefixes |= PREFIX_FWAIT;
13417 else if (intel_syntax && (sizeflag & DFLAG))
13421 if (!(rex & REX_W))
13422 used_prefixes |= (prefixes & PREFIX_DATA);
13426 && address_mode == mode_64bit
13427 && ((sizeflag & DFLAG) || (rex & REX_W)))
13432 /* Fall through. */
13436 if ((rex & REX_W) == 0
13437 && (prefixes & PREFIX_DATA))
13439 if ((sizeflag & DFLAG) == 0)
13441 used_prefixes |= (prefixes & PREFIX_DATA);
13445 if ((prefixes & PREFIX_DATA)
13447 || (sizeflag & SUFFIX_ALWAYS))
13454 if (sizeflag & DFLAG)
13458 used_prefixes |= (prefixes & PREFIX_DATA);
13465 if (address_mode == mode_64bit
13466 && ((sizeflag & DFLAG) || (rex & REX_W)))
13468 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13472 /* Fall through. */
13475 if (l == 0 && len == 1)
13478 if (intel_syntax && !alt)
13481 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13487 if (sizeflag & DFLAG)
13488 *obufp++ = intel_syntax ? 'd' : 'l';
13491 used_prefixes |= (prefixes & PREFIX_DATA);
13497 if (l != 1 || len != 2 || last[0] != 'L')
13503 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13518 else if (sizeflag & DFLAG)
13527 if (intel_syntax && !p[1]
13528 && ((rex & REX_W) || (sizeflag & DFLAG)))
13530 if (!(rex & REX_W))
13531 used_prefixes |= (prefixes & PREFIX_DATA);
13534 if (l == 0 && len == 1)
13538 if (address_mode == mode_64bit
13539 && ((sizeflag & DFLAG) || (rex & REX_W)))
13541 if (sizeflag & SUFFIX_ALWAYS)
13563 /* Fall through. */
13566 if (l == 0 && len == 1)
13571 if (sizeflag & SUFFIX_ALWAYS)
13577 if (sizeflag & DFLAG)
13581 used_prefixes |= (prefixes & PREFIX_DATA);
13595 if (address_mode == mode_64bit
13596 && !(prefixes & PREFIX_ADDR))
13607 if (l != 0 || len != 1)
13612 if (need_vex && vex.prefix)
13614 if (vex.prefix == DATA_PREFIX_OPCODE)
13621 if (prefixes & PREFIX_DATA)
13625 used_prefixes |= (prefixes & PREFIX_DATA);
13629 if (l == 0 && len == 1)
13631 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13642 if (l != 1 || len != 2 || last[0] != 'X')
13650 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13652 switch (vex.length)
13666 if (l == 0 && len == 1)
13668 /* operand size flag for cwtl, cbtw */
13677 else if (sizeflag & DFLAG)
13681 if (!(rex & REX_W))
13682 used_prefixes |= (prefixes & PREFIX_DATA);
13689 && last[0] != 'L'))
13696 if (last[0] == 'X')
13697 *obufp++ = vex.w ? 'd': 's';
13699 *obufp++ = vex.w ? 'q': 'd';
13706 mnemonicendp = obufp;
13711 oappend (const char *s)
13713 obufp = stpcpy (obufp, s);
13719 /* Only print the active segment register. */
13720 if (!active_seg_prefix)
13723 used_prefixes |= active_seg_prefix;
13724 switch (active_seg_prefix)
13727 oappend_maybe_intel ("%cs:");
13730 oappend_maybe_intel ("%ds:");
13733 oappend_maybe_intel ("%ss:");
13736 oappend_maybe_intel ("%es:");
13739 oappend_maybe_intel ("%fs:");
13742 oappend_maybe_intel ("%gs:");
13750 OP_indirE (int bytemode, int sizeflag)
13754 OP_E (bytemode, sizeflag);
13758 print_operand_value (char *buf, int hex, bfd_vma disp)
13760 if (address_mode == mode_64bit)
13768 sprintf_vma (tmp, disp);
13769 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13770 strcpy (buf + 2, tmp + i);
13774 bfd_signed_vma v = disp;
13781 /* Check for possible overflow on 0x8000000000000000. */
13784 strcpy (buf, "9223372036854775808");
13798 tmp[28 - i] = (v % 10) + '0';
13802 strcpy (buf, tmp + 29 - i);
13808 sprintf (buf, "0x%x", (unsigned int) disp);
13810 sprintf (buf, "%d", (int) disp);
13814 /* Put DISP in BUF as signed hex number. */
13817 print_displacement (char *buf, bfd_vma disp)
13819 bfd_signed_vma val = disp;
13828 /* Check for possible overflow. */
13831 switch (address_mode)
13834 strcpy (buf + j, "0x8000000000000000");
13837 strcpy (buf + j, "0x80000000");
13840 strcpy (buf + j, "0x8000");
13850 sprintf_vma (tmp, (bfd_vma) val);
13851 for (i = 0; tmp[i] == '0'; i++)
13853 if (tmp[i] == '\0')
13855 strcpy (buf + j, tmp + i);
13859 intel_operand_size (int bytemode, int sizeflag)
13863 && (bytemode == x_mode
13864 || bytemode == evex_half_bcst_xmmq_mode))
13867 oappend ("QWORD PTR ");
13869 oappend ("DWORD PTR ");
13877 oappend ("BYTE PTR ");
13881 oappend ("WORD PTR ");
13884 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13886 oappend ("QWORD PTR ");
13895 oappend ("QWORD PTR ");
13898 if ((sizeflag & DFLAG) || bytemode == dq_mode)
13899 oappend ("DWORD PTR ");
13901 oappend ("WORD PTR ");
13902 used_prefixes |= (prefixes & PREFIX_DATA);
13906 if ((rex & REX_W) || (sizeflag & DFLAG))
13908 oappend ("WORD PTR ");
13909 if (!(rex & REX_W))
13910 used_prefixes |= (prefixes & PREFIX_DATA);
13913 if (sizeflag & DFLAG)
13914 oappend ("QWORD PTR ");
13916 oappend ("DWORD PTR ");
13917 used_prefixes |= (prefixes & PREFIX_DATA);
13920 case d_scalar_mode:
13921 case d_scalar_swap_mode:
13924 oappend ("DWORD PTR ");
13927 case q_scalar_mode:
13928 case q_scalar_swap_mode:
13930 oappend ("QWORD PTR ");
13933 if (address_mode == mode_64bit)
13934 oappend ("QWORD PTR ");
13936 oappend ("DWORD PTR ");
13939 if (sizeflag & DFLAG)
13940 oappend ("FWORD PTR ");
13942 oappend ("DWORD PTR ");
13943 used_prefixes |= (prefixes & PREFIX_DATA);
13946 oappend ("TBYTE PTR ");
13950 case evex_x_gscat_mode:
13951 case evex_x_nobcst_mode:
13954 switch (vex.length)
13957 oappend ("XMMWORD PTR ");
13960 oappend ("YMMWORD PTR ");
13963 oappend ("ZMMWORD PTR ");
13970 oappend ("XMMWORD PTR ");
13973 oappend ("XMMWORD PTR ");
13976 oappend ("YMMWORD PTR ");
13979 case evex_half_bcst_xmmq_mode:
13983 switch (vex.length)
13986 oappend ("QWORD PTR ");
13989 oappend ("XMMWORD PTR ");
13992 oappend ("YMMWORD PTR ");
14002 switch (vex.length)
14007 oappend ("BYTE PTR ");
14017 switch (vex.length)
14022 oappend ("WORD PTR ");
14032 switch (vex.length)
14037 oappend ("DWORD PTR ");
14047 switch (vex.length)
14052 oappend ("QWORD PTR ");
14062 switch (vex.length)
14065 oappend ("WORD PTR ");
14068 oappend ("DWORD PTR ");
14071 oappend ("QWORD PTR ");
14081 switch (vex.length)
14084 oappend ("DWORD PTR ");
14087 oappend ("QWORD PTR ");
14090 oappend ("XMMWORD PTR ");
14100 switch (vex.length)
14103 oappend ("QWORD PTR ");
14106 oappend ("YMMWORD PTR ");
14109 oappend ("ZMMWORD PTR ");
14119 switch (vex.length)
14123 oappend ("XMMWORD PTR ");
14130 oappend ("OWORD PTR ");
14133 case vex_w_dq_mode:
14134 case vex_scalar_w_dq_mode:
14139 oappend ("QWORD PTR ");
14141 oappend ("DWORD PTR ");
14143 case vex_vsib_d_w_dq_mode:
14144 case vex_vsib_q_w_dq_mode:
14151 oappend ("QWORD PTR ");
14153 oappend ("DWORD PTR ");
14157 if (vex.length != 512)
14159 oappend ("ZMMWORD PTR ");
14162 case vex_vsib_q_w_d_mode:
14163 case vex_vsib_d_w_d_mode:
14164 if (!need_vex || !vex.evex || vex.length != 512)
14167 oappend ("YMMWORD PTR ");
14173 /* Currently the only instructions, which allows either mask or
14174 memory operand, are AVX512's KMOVW instructions. They need
14175 Word-sized operand. */
14176 if (vex.w || vex.length != 128)
14178 oappend ("WORD PTR ");
14187 OP_E_register (int bytemode, int sizeflag)
14189 int reg = modrm.rm;
14190 const char **names;
14196 if ((sizeflag & SUFFIX_ALWAYS)
14197 && (bytemode == b_swap_mode || bytemode == v_swap_mode))
14221 names = address_mode == mode_64bit ? names64 : names32;
14227 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14245 if ((sizeflag & DFLAG)
14246 || (bytemode != v_mode
14247 && bytemode != v_swap_mode))
14251 used_prefixes |= (prefixes & PREFIX_DATA);
14255 names = names_mask;
14260 oappend (INTERNAL_DISASSEMBLER_ERROR);
14263 oappend (names[reg]);
14267 OP_E_memory (int bytemode, int sizeflag)
14270 int add = (rex & REX_B) ? 8 : 0;
14276 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
14278 && bytemode != x_mode
14279 && bytemode != evex_half_bcst_xmmq_mode)
14286 case vex_vsib_d_w_dq_mode:
14287 case vex_vsib_d_w_d_mode:
14288 case vex_vsib_q_w_dq_mode:
14289 case vex_vsib_q_w_d_mode:
14290 case evex_x_gscat_mode:
14292 shift = vex.w ? 3 : 2;
14295 case evex_half_bcst_xmmq_mode:
14298 shift = vex.w ? 3 : 2;
14301 /* Fall through if vex.b == 0. */
14306 case evex_x_nobcst_mode:
14308 switch (vex.length)
14331 case q_scalar_mode:
14333 case q_scalar_swap_mode:
14339 case d_scalar_mode:
14341 case d_scalar_swap_mode:
14353 /* Make necessary corrections to shift for modes that need it.
14354 For these modes we currently have shift 4, 5 or 6 depending on
14355 vex.length (it corresponds to xmmword, ymmword or zmmword
14356 operand). We might want to make it 3, 4 or 5 (e.g. for
14357 xmmq_mode). In case of broadcast enabled the corrections
14358 aren't needed, as element size is always 32 or 64 bits. */
14359 if (bytemode == xmmq_mode
14360 || (bytemode == evex_half_bcst_xmmq_mode
14363 else if (bytemode == xmmqd_mode)
14365 else if (bytemode == xmmdw_mode)
14373 intel_operand_size (bytemode, sizeflag);
14376 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14378 /* 32/64 bit address mode */
14387 int addr32flag = !((sizeflag & AFLAG)
14388 || bytemode == v_bnd_mode
14389 || bytemode == bnd_mode);
14390 const char **indexes64 = names64;
14391 const char **indexes32 = names32;
14401 vindex = sib.index;
14407 case vex_vsib_d_w_dq_mode:
14408 case vex_vsib_d_w_d_mode:
14409 case vex_vsib_q_w_dq_mode:
14410 case vex_vsib_q_w_d_mode:
14420 switch (vex.length)
14423 indexes64 = indexes32 = names_xmm;
14427 || bytemode == vex_vsib_q_w_dq_mode
14428 || bytemode == vex_vsib_q_w_d_mode)
14429 indexes64 = indexes32 = names_ymm;
14431 indexes64 = indexes32 = names_xmm;
14435 || bytemode == vex_vsib_q_w_dq_mode
14436 || bytemode == vex_vsib_q_w_d_mode)
14437 indexes64 = indexes32 = names_zmm;
14439 indexes64 = indexes32 = names_ymm;
14446 haveindex = vindex != 4;
14453 rbase = base + add;
14461 if (address_mode == mode_64bit && !havesib)
14467 FETCH_DATA (the_info, codep + 1);
14469 if ((disp & 0x80) != 0)
14471 if (vex.evex && shift > 0)
14479 /* In 32bit mode, we need index register to tell [offset] from
14480 [eiz*1 + offset]. */
14481 needindex = (havesib
14484 && address_mode == mode_32bit);
14485 havedisp = (havebase
14487 || (havesib && (haveindex || scale != 0)));
14490 if (modrm.mod != 0 || base == 5)
14492 if (havedisp || riprel)
14493 print_displacement (scratchbuf, disp);
14495 print_operand_value (scratchbuf, 1, disp);
14496 oappend (scratchbuf);
14500 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
14504 if ((havebase || haveindex || riprel)
14505 && (bytemode != v_bnd_mode)
14506 && (bytemode != bnd_mode))
14507 used_prefixes |= PREFIX_ADDR;
14509 if (havedisp || (intel_syntax && riprel))
14511 *obufp++ = open_char;
14512 if (intel_syntax && riprel)
14515 oappend (sizeflag & AFLAG ? "rip" : "eip");
14519 oappend (address_mode == mode_64bit && !addr32flag
14520 ? names64[rbase] : names32[rbase]);
14523 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14524 print index to tell base + index from base. */
14528 || (havebase && base != ESP_REG_NUM))
14530 if (!intel_syntax || havebase)
14532 *obufp++ = separator_char;
14536 oappend (address_mode == mode_64bit && !addr32flag
14537 ? indexes64[vindex] : indexes32[vindex]);
14539 oappend (address_mode == mode_64bit && !addr32flag
14540 ? index64 : index32);
14542 *obufp++ = scale_char;
14544 sprintf (scratchbuf, "%d", 1 << scale);
14545 oappend (scratchbuf);
14549 && (disp || modrm.mod != 0 || base == 5))
14551 if (!havedisp || (bfd_signed_vma) disp >= 0)
14556 else if (modrm.mod != 1 && disp != -disp)
14560 disp = - (bfd_signed_vma) disp;
14564 print_displacement (scratchbuf, disp);
14566 print_operand_value (scratchbuf, 1, disp);
14567 oappend (scratchbuf);
14570 *obufp++ = close_char;
14573 else if (intel_syntax)
14575 if (modrm.mod != 0 || base == 5)
14577 if (!active_seg_prefix)
14579 oappend (names_seg[ds_reg - es_reg]);
14582 print_operand_value (scratchbuf, 1, disp);
14583 oappend (scratchbuf);
14589 /* 16 bit address mode */
14590 used_prefixes |= prefixes & PREFIX_ADDR;
14597 if ((disp & 0x8000) != 0)
14602 FETCH_DATA (the_info, codep + 1);
14604 if ((disp & 0x80) != 0)
14609 if ((disp & 0x8000) != 0)
14615 if (modrm.mod != 0 || modrm.rm == 6)
14617 print_displacement (scratchbuf, disp);
14618 oappend (scratchbuf);
14621 if (modrm.mod != 0 || modrm.rm != 6)
14623 *obufp++ = open_char;
14625 oappend (index16[modrm.rm]);
14627 && (disp || modrm.mod != 0 || modrm.rm == 6))
14629 if ((bfd_signed_vma) disp >= 0)
14634 else if (modrm.mod != 1)
14638 disp = - (bfd_signed_vma) disp;
14641 print_displacement (scratchbuf, disp);
14642 oappend (scratchbuf);
14645 *obufp++ = close_char;
14648 else if (intel_syntax)
14650 if (!active_seg_prefix)
14652 oappend (names_seg[ds_reg - es_reg]);
14655 print_operand_value (scratchbuf, 1, disp & 0xffff);
14656 oappend (scratchbuf);
14659 if (vex.evex && vex.b
14660 && (bytemode == x_mode
14661 || bytemode == evex_half_bcst_xmmq_mode))
14663 if (vex.w || bytemode == evex_half_bcst_xmmq_mode)
14664 oappend ("{1to8}");
14666 oappend ("{1to16}");
14671 OP_E (int bytemode, int sizeflag)
14673 /* Skip mod/rm byte. */
14677 if (modrm.mod == 3)
14678 OP_E_register (bytemode, sizeflag);
14680 OP_E_memory (bytemode, sizeflag);
14684 OP_G (int bytemode, int sizeflag)
14695 oappend (names8rex[modrm.reg + add]);
14697 oappend (names8[modrm.reg + add]);
14700 oappend (names16[modrm.reg + add]);
14703 oappend (names32[modrm.reg + add]);
14706 oappend (names64[modrm.reg + add]);
14709 oappend (names_bnd[modrm.reg]);
14718 oappend (names64[modrm.reg + add]);
14721 if ((sizeflag & DFLAG) || bytemode != v_mode)
14722 oappend (names32[modrm.reg + add]);
14724 oappend (names16[modrm.reg + add]);
14725 used_prefixes |= (prefixes & PREFIX_DATA);
14729 if (address_mode == mode_64bit)
14730 oappend (names64[modrm.reg + add]);
14732 oappend (names32[modrm.reg + add]);
14735 oappend (names_mask[modrm.reg + add]);
14738 oappend (INTERNAL_DISASSEMBLER_ERROR);
14751 FETCH_DATA (the_info, codep + 8);
14752 a = *codep++ & 0xff;
14753 a |= (*codep++ & 0xff) << 8;
14754 a |= (*codep++ & 0xff) << 16;
14755 a |= (*codep++ & 0xff) << 24;
14756 b = *codep++ & 0xff;
14757 b |= (*codep++ & 0xff) << 8;
14758 b |= (*codep++ & 0xff) << 16;
14759 b |= (*codep++ & 0xff) << 24;
14760 x = a + ((bfd_vma) b << 32);
14768 static bfd_signed_vma
14771 bfd_signed_vma x = 0;
14773 FETCH_DATA (the_info, codep + 4);
14774 x = *codep++ & (bfd_signed_vma) 0xff;
14775 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14776 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14777 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14781 static bfd_signed_vma
14784 bfd_signed_vma x = 0;
14786 FETCH_DATA (the_info, codep + 4);
14787 x = *codep++ & (bfd_signed_vma) 0xff;
14788 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14789 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14790 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14792 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14802 FETCH_DATA (the_info, codep + 2);
14803 x = *codep++ & 0xff;
14804 x |= (*codep++ & 0xff) << 8;
14809 set_op (bfd_vma op, int riprel)
14811 op_index[op_ad] = op_ad;
14812 if (address_mode == mode_64bit)
14814 op_address[op_ad] = op;
14815 op_riprel[op_ad] = riprel;
14819 /* Mask to get a 32-bit address. */
14820 op_address[op_ad] = op & 0xffffffff;
14821 op_riprel[op_ad] = riprel & 0xffffffff;
14826 OP_REG (int code, int sizeflag)
14833 case es_reg: case ss_reg: case cs_reg:
14834 case ds_reg: case fs_reg: case gs_reg:
14835 oappend (names_seg[code - es_reg]);
14847 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14848 case sp_reg: case bp_reg: case si_reg: case di_reg:
14849 s = names16[code - ax_reg + add];
14851 case al_reg: case ah_reg: case cl_reg: case ch_reg:
14852 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14855 s = names8rex[code - al_reg + add];
14857 s = names8[code - al_reg];
14859 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14860 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14861 if (address_mode == mode_64bit
14862 && ((sizeflag & DFLAG) || (rex & REX_W)))
14864 s = names64[code - rAX_reg + add];
14867 code += eAX_reg - rAX_reg;
14868 /* Fall through. */
14869 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14870 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14873 s = names64[code - eAX_reg + add];
14876 if (sizeflag & DFLAG)
14877 s = names32[code - eAX_reg + add];
14879 s = names16[code - eAX_reg + add];
14880 used_prefixes |= (prefixes & PREFIX_DATA);
14884 s = INTERNAL_DISASSEMBLER_ERROR;
14891 OP_IMREG (int code, int sizeflag)
14903 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14904 case sp_reg: case bp_reg: case si_reg: case di_reg:
14905 s = names16[code - ax_reg];
14907 case es_reg: case ss_reg: case cs_reg:
14908 case ds_reg: case fs_reg: case gs_reg:
14909 s = names_seg[code - es_reg];
14911 case al_reg: case ah_reg: case cl_reg: case ch_reg:
14912 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14915 s = names8rex[code - al_reg];
14917 s = names8[code - al_reg];
14919 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14920 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14923 s = names64[code - eAX_reg];
14926 if (sizeflag & DFLAG)
14927 s = names32[code - eAX_reg];
14929 s = names16[code - eAX_reg];
14930 used_prefixes |= (prefixes & PREFIX_DATA);
14933 case z_mode_ax_reg:
14934 if ((rex & REX_W) || (sizeflag & DFLAG))
14938 if (!(rex & REX_W))
14939 used_prefixes |= (prefixes & PREFIX_DATA);
14942 s = INTERNAL_DISASSEMBLER_ERROR;
14949 OP_I (int bytemode, int sizeflag)
14952 bfd_signed_vma mask = -1;
14957 FETCH_DATA (the_info, codep + 1);
14962 if (address_mode == mode_64bit)
14967 /* Fall through. */
14974 if (sizeflag & DFLAG)
14984 used_prefixes |= (prefixes & PREFIX_DATA);
14996 oappend (INTERNAL_DISASSEMBLER_ERROR);
15001 scratchbuf[0] = '$';
15002 print_operand_value (scratchbuf + 1, 1, op);
15003 oappend_maybe_intel (scratchbuf);
15004 scratchbuf[0] = '\0';
15008 OP_I64 (int bytemode, int sizeflag)
15011 bfd_signed_vma mask = -1;
15013 if (address_mode != mode_64bit)
15015 OP_I (bytemode, sizeflag);
15022 FETCH_DATA (the_info, codep + 1);
15032 if (sizeflag & DFLAG)
15042 used_prefixes |= (prefixes & PREFIX_DATA);
15050 oappend (INTERNAL_DISASSEMBLER_ERROR);
15055 scratchbuf[0] = '$';
15056 print_operand_value (scratchbuf + 1, 1, op);
15057 oappend_maybe_intel (scratchbuf);
15058 scratchbuf[0] = '\0';
15062 OP_sI (int bytemode, int sizeflag)
15070 FETCH_DATA (the_info, codep + 1);
15072 if ((op & 0x80) != 0)
15074 if (bytemode == b_T_mode)
15076 if (address_mode != mode_64bit
15077 || !((sizeflag & DFLAG) || (rex & REX_W)))
15079 /* The operand-size prefix is overridden by a REX prefix. */
15080 if ((sizeflag & DFLAG) || (rex & REX_W))
15088 if (!(rex & REX_W))
15090 if (sizeflag & DFLAG)
15098 /* The operand-size prefix is overridden by a REX prefix. */
15099 if ((sizeflag & DFLAG) || (rex & REX_W))
15105 oappend (INTERNAL_DISASSEMBLER_ERROR);
15109 scratchbuf[0] = '$';
15110 print_operand_value (scratchbuf + 1, 1, op);
15111 oappend_maybe_intel (scratchbuf);
15115 OP_J (int bytemode, int sizeflag)
15119 bfd_vma segment = 0;
15124 FETCH_DATA (the_info, codep + 1);
15126 if ((disp & 0x80) != 0)
15131 if ((sizeflag & DFLAG) || (rex & REX_W))
15136 if ((disp & 0x8000) != 0)
15138 /* In 16bit mode, address is wrapped around at 64k within
15139 the same segment. Otherwise, a data16 prefix on a jump
15140 instruction means that the pc is masked to 16 bits after
15141 the displacement is added! */
15143 if ((prefixes & PREFIX_DATA) == 0)
15144 segment = ((start_pc + codep - start_codep)
15145 & ~((bfd_vma) 0xffff));
15147 if (!(rex & REX_W))
15148 used_prefixes |= (prefixes & PREFIX_DATA);
15151 oappend (INTERNAL_DISASSEMBLER_ERROR);
15154 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15156 print_operand_value (scratchbuf, 1, disp);
15157 oappend (scratchbuf);
15161 OP_SEG (int bytemode, int sizeflag)
15163 if (bytemode == w_mode)
15164 oappend (names_seg[modrm.reg]);
15166 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15170 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15174 if (sizeflag & DFLAG)
15184 used_prefixes |= (prefixes & PREFIX_DATA);
15186 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15188 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15189 oappend (scratchbuf);
15193 OP_OFF (int bytemode, int sizeflag)
15197 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15198 intel_operand_size (bytemode, sizeflag);
15201 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15208 if (!active_seg_prefix)
15210 oappend (names_seg[ds_reg - es_reg]);
15214 print_operand_value (scratchbuf, 1, off);
15215 oappend (scratchbuf);
15219 OP_OFF64 (int bytemode, int sizeflag)
15223 if (address_mode != mode_64bit
15224 || (prefixes & PREFIX_ADDR))
15226 OP_OFF (bytemode, sizeflag);
15230 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15231 intel_operand_size (bytemode, sizeflag);
15238 if (!active_seg_prefix)
15240 oappend (names_seg[ds_reg - es_reg]);
15244 print_operand_value (scratchbuf, 1, off);
15245 oappend (scratchbuf);
15249 ptr_reg (int code, int sizeflag)
15253 *obufp++ = open_char;
15254 used_prefixes |= (prefixes & PREFIX_ADDR);
15255 if (address_mode == mode_64bit)
15257 if (!(sizeflag & AFLAG))
15258 s = names32[code - eAX_reg];
15260 s = names64[code - eAX_reg];
15262 else if (sizeflag & AFLAG)
15263 s = names32[code - eAX_reg];
15265 s = names16[code - eAX_reg];
15267 *obufp++ = close_char;
15272 OP_ESreg (int code, int sizeflag)
15278 case 0x6d: /* insw/insl */
15279 intel_operand_size (z_mode, sizeflag);
15281 case 0xa5: /* movsw/movsl/movsq */
15282 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15283 case 0xab: /* stosw/stosl */
15284 case 0xaf: /* scasw/scasl */
15285 intel_operand_size (v_mode, sizeflag);
15288 intel_operand_size (b_mode, sizeflag);
15291 oappend_maybe_intel ("%es:");
15292 ptr_reg (code, sizeflag);
15296 OP_DSreg (int code, int sizeflag)
15302 case 0x6f: /* outsw/outsl */
15303 intel_operand_size (z_mode, sizeflag);
15305 case 0xa5: /* movsw/movsl/movsq */
15306 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15307 case 0xad: /* lodsw/lodsl/lodsq */
15308 intel_operand_size (v_mode, sizeflag);
15311 intel_operand_size (b_mode, sizeflag);
15314 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15315 default segment register DS is printed. */
15316 if (!active_seg_prefix)
15317 active_seg_prefix = PREFIX_DS;
15319 ptr_reg (code, sizeflag);
15323 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15331 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15333 all_prefixes[last_lock_prefix] = 0;
15334 used_prefixes |= PREFIX_LOCK;
15339 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15340 oappend_maybe_intel (scratchbuf);
15344 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15353 sprintf (scratchbuf, "db%d", modrm.reg + add);
15355 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15356 oappend (scratchbuf);
15360 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15362 sprintf (scratchbuf, "%%tr%d", modrm.reg);
15363 oappend_maybe_intel (scratchbuf);
15367 OP_R (int bytemode, int sizeflag)
15369 if (modrm.mod == 3)
15370 OP_E (bytemode, sizeflag);
15376 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15378 int reg = modrm.reg;
15379 const char **names;
15381 used_prefixes |= (prefixes & PREFIX_DATA);
15382 if (prefixes & PREFIX_DATA)
15391 oappend (names[reg]);
15395 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15397 int reg = modrm.reg;
15398 const char **names;
15410 && bytemode != xmm_mode
15411 && bytemode != xmmq_mode
15412 && bytemode != evex_half_bcst_xmmq_mode
15413 && bytemode != ymm_mode
15414 && bytemode != scalar_mode)
15416 switch (vex.length)
15423 || (bytemode != vex_vsib_q_w_dq_mode
15424 && bytemode != vex_vsib_q_w_d_mode))
15436 else if (bytemode == xmmq_mode
15437 || bytemode == evex_half_bcst_xmmq_mode)
15439 switch (vex.length)
15452 else if (bytemode == ymm_mode)
15456 oappend (names[reg]);
15460 OP_EM (int bytemode, int sizeflag)
15463 const char **names;
15465 if (modrm.mod != 3)
15468 && (bytemode == v_mode || bytemode == v_swap_mode))
15470 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15471 used_prefixes |= (prefixes & PREFIX_DATA);
15473 OP_E (bytemode, sizeflag);
15477 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15480 /* Skip mod/rm byte. */
15483 used_prefixes |= (prefixes & PREFIX_DATA);
15485 if (prefixes & PREFIX_DATA)
15494 oappend (names[reg]);
15497 /* cvt* are the only instructions in sse2 which have
15498 both SSE and MMX operands and also have 0x66 prefix
15499 in their opcode. 0x66 was originally used to differentiate
15500 between SSE and MMX instruction(operands). So we have to handle the
15501 cvt* separately using OP_EMC and OP_MXC */
15503 OP_EMC (int bytemode, int sizeflag)
15505 if (modrm.mod != 3)
15507 if (intel_syntax && bytemode == v_mode)
15509 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15510 used_prefixes |= (prefixes & PREFIX_DATA);
15512 OP_E (bytemode, sizeflag);
15516 /* Skip mod/rm byte. */
15519 used_prefixes |= (prefixes & PREFIX_DATA);
15520 oappend (names_mm[modrm.rm]);
15524 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15526 used_prefixes |= (prefixes & PREFIX_DATA);
15527 oappend (names_mm[modrm.reg]);
15531 OP_EX (int bytemode, int sizeflag)
15534 const char **names;
15536 /* Skip mod/rm byte. */
15540 if (modrm.mod != 3)
15542 OP_E_memory (bytemode, sizeflag);
15557 if ((sizeflag & SUFFIX_ALWAYS)
15558 && (bytemode == x_swap_mode
15559 || bytemode == d_swap_mode
15560 || bytemode == d_scalar_swap_mode
15561 || bytemode == q_swap_mode
15562 || bytemode == q_scalar_swap_mode))
15566 && bytemode != xmm_mode
15567 && bytemode != xmmdw_mode
15568 && bytemode != xmmqd_mode
15569 && bytemode != xmm_mb_mode
15570 && bytemode != xmm_mw_mode
15571 && bytemode != xmm_md_mode
15572 && bytemode != xmm_mq_mode
15573 && bytemode != xmm_mdq_mode
15574 && bytemode != xmmq_mode
15575 && bytemode != evex_half_bcst_xmmq_mode
15576 && bytemode != ymm_mode
15577 && bytemode != d_scalar_mode
15578 && bytemode != d_scalar_swap_mode
15579 && bytemode != q_scalar_mode
15580 && bytemode != q_scalar_swap_mode
15581 && bytemode != vex_scalar_w_dq_mode)
15583 switch (vex.length)
15598 else if (bytemode == xmmq_mode
15599 || bytemode == evex_half_bcst_xmmq_mode)
15601 switch (vex.length)
15614 else if (bytemode == ymm_mode)
15618 oappend (names[reg]);
15622 OP_MS (int bytemode, int sizeflag)
15624 if (modrm.mod == 3)
15625 OP_EM (bytemode, sizeflag);
15631 OP_XS (int bytemode, int sizeflag)
15633 if (modrm.mod == 3)
15634 OP_EX (bytemode, sizeflag);
15640 OP_M (int bytemode, int sizeflag)
15642 if (modrm.mod == 3)
15643 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15646 OP_E (bytemode, sizeflag);
15650 OP_0f07 (int bytemode, int sizeflag)
15652 if (modrm.mod != 3 || modrm.rm != 0)
15655 OP_E (bytemode, sizeflag);
15658 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15659 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15662 NOP_Fixup1 (int bytemode, int sizeflag)
15664 if ((prefixes & PREFIX_DATA) != 0
15667 && address_mode == mode_64bit))
15668 OP_REG (bytemode, sizeflag);
15670 strcpy (obuf, "nop");
15674 NOP_Fixup2 (int bytemode, int sizeflag)
15676 if ((prefixes & PREFIX_DATA) != 0
15679 && address_mode == mode_64bit))
15680 OP_IMREG (bytemode, sizeflag);
15683 static const char *const Suffix3DNow[] = {
15684 /* 00 */ NULL, NULL, NULL, NULL,
15685 /* 04 */ NULL, NULL, NULL, NULL,
15686 /* 08 */ NULL, NULL, NULL, NULL,
15687 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
15688 /* 10 */ NULL, NULL, NULL, NULL,
15689 /* 14 */ NULL, NULL, NULL, NULL,
15690 /* 18 */ NULL, NULL, NULL, NULL,
15691 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
15692 /* 20 */ NULL, NULL, NULL, NULL,
15693 /* 24 */ NULL, NULL, NULL, NULL,
15694 /* 28 */ NULL, NULL, NULL, NULL,
15695 /* 2C */ NULL, NULL, NULL, NULL,
15696 /* 30 */ NULL, NULL, NULL, NULL,
15697 /* 34 */ NULL, NULL, NULL, NULL,
15698 /* 38 */ NULL, NULL, NULL, NULL,
15699 /* 3C */ NULL, NULL, NULL, NULL,
15700 /* 40 */ NULL, NULL, NULL, NULL,
15701 /* 44 */ NULL, NULL, NULL, NULL,
15702 /* 48 */ NULL, NULL, NULL, NULL,
15703 /* 4C */ NULL, NULL, NULL, NULL,
15704 /* 50 */ NULL, NULL, NULL, NULL,
15705 /* 54 */ NULL, NULL, NULL, NULL,
15706 /* 58 */ NULL, NULL, NULL, NULL,
15707 /* 5C */ NULL, NULL, NULL, NULL,
15708 /* 60 */ NULL, NULL, NULL, NULL,
15709 /* 64 */ NULL, NULL, NULL, NULL,
15710 /* 68 */ NULL, NULL, NULL, NULL,
15711 /* 6C */ NULL, NULL, NULL, NULL,
15712 /* 70 */ NULL, NULL, NULL, NULL,
15713 /* 74 */ NULL, NULL, NULL, NULL,
15714 /* 78 */ NULL, NULL, NULL, NULL,
15715 /* 7C */ NULL, NULL, NULL, NULL,
15716 /* 80 */ NULL, NULL, NULL, NULL,
15717 /* 84 */ NULL, NULL, NULL, NULL,
15718 /* 88 */ NULL, NULL, "pfnacc", NULL,
15719 /* 8C */ NULL, NULL, "pfpnacc", NULL,
15720 /* 90 */ "pfcmpge", NULL, NULL, NULL,
15721 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
15722 /* 98 */ NULL, NULL, "pfsub", NULL,
15723 /* 9C */ NULL, NULL, "pfadd", NULL,
15724 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
15725 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
15726 /* A8 */ NULL, NULL, "pfsubr", NULL,
15727 /* AC */ NULL, NULL, "pfacc", NULL,
15728 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
15729 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
15730 /* B8 */ NULL, NULL, NULL, "pswapd",
15731 /* BC */ NULL, NULL, NULL, "pavgusb",
15732 /* C0 */ NULL, NULL, NULL, NULL,
15733 /* C4 */ NULL, NULL, NULL, NULL,
15734 /* C8 */ NULL, NULL, NULL, NULL,
15735 /* CC */ NULL, NULL, NULL, NULL,
15736 /* D0 */ NULL, NULL, NULL, NULL,
15737 /* D4 */ NULL, NULL, NULL, NULL,
15738 /* D8 */ NULL, NULL, NULL, NULL,
15739 /* DC */ NULL, NULL, NULL, NULL,
15740 /* E0 */ NULL, NULL, NULL, NULL,
15741 /* E4 */ NULL, NULL, NULL, NULL,
15742 /* E8 */ NULL, NULL, NULL, NULL,
15743 /* EC */ NULL, NULL, NULL, NULL,
15744 /* F0 */ NULL, NULL, NULL, NULL,
15745 /* F4 */ NULL, NULL, NULL, NULL,
15746 /* F8 */ NULL, NULL, NULL, NULL,
15747 /* FC */ NULL, NULL, NULL, NULL,
15751 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15753 const char *mnemonic;
15755 FETCH_DATA (the_info, codep + 1);
15756 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15757 place where an 8-bit immediate would normally go. ie. the last
15758 byte of the instruction. */
15759 obufp = mnemonicendp;
15760 mnemonic = Suffix3DNow[*codep++ & 0xff];
15762 oappend (mnemonic);
15765 /* Since a variable sized modrm/sib chunk is between the start
15766 of the opcode (0x0f0f) and the opcode suffix, we need to do
15767 all the modrm processing first, and don't know until now that
15768 we have a bad opcode. This necessitates some cleaning up. */
15769 op_out[0][0] = '\0';
15770 op_out[1][0] = '\0';
15773 mnemonicendp = obufp;
15776 static struct op simd_cmp_op[] =
15778 { STRING_COMMA_LEN ("eq") },
15779 { STRING_COMMA_LEN ("lt") },
15780 { STRING_COMMA_LEN ("le") },
15781 { STRING_COMMA_LEN ("unord") },
15782 { STRING_COMMA_LEN ("neq") },
15783 { STRING_COMMA_LEN ("nlt") },
15784 { STRING_COMMA_LEN ("nle") },
15785 { STRING_COMMA_LEN ("ord") }
15789 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15791 unsigned int cmp_type;
15793 FETCH_DATA (the_info, codep + 1);
15794 cmp_type = *codep++ & 0xff;
15795 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15798 char *p = mnemonicendp - 2;
15802 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15803 mnemonicendp += simd_cmp_op[cmp_type].len;
15807 /* We have a reserved extension byte. Output it directly. */
15808 scratchbuf[0] = '$';
15809 print_operand_value (scratchbuf + 1, 1, cmp_type);
15810 oappend_maybe_intel (scratchbuf);
15811 scratchbuf[0] = '\0';
15816 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15817 int sizeflag ATTRIBUTE_UNUSED)
15819 /* mwait %eax,%ecx */
15822 const char **names = (address_mode == mode_64bit
15823 ? names64 : names32);
15824 strcpy (op_out[0], names[0]);
15825 strcpy (op_out[1], names[1]);
15826 two_source_ops = 1;
15828 /* Skip mod/rm byte. */
15834 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15835 int sizeflag ATTRIBUTE_UNUSED)
15837 /* monitor %eax,%ecx,%edx" */
15840 const char **op1_names;
15841 const char **names = (address_mode == mode_64bit
15842 ? names64 : names32);
15844 if (!(prefixes & PREFIX_ADDR))
15845 op1_names = (address_mode == mode_16bit
15846 ? names16 : names);
15849 /* Remove "addr16/addr32". */
15850 all_prefixes[last_addr_prefix] = 0;
15851 op1_names = (address_mode != mode_32bit
15852 ? names32 : names16);
15853 used_prefixes |= PREFIX_ADDR;
15855 strcpy (op_out[0], op1_names[0]);
15856 strcpy (op_out[1], names[1]);
15857 strcpy (op_out[2], names[2]);
15858 two_source_ops = 1;
15860 /* Skip mod/rm byte. */
15868 /* Throw away prefixes and 1st. opcode byte. */
15869 codep = insn_codep + 1;
15874 REP_Fixup (int bytemode, int sizeflag)
15876 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15878 if (prefixes & PREFIX_REPZ)
15879 all_prefixes[last_repz_prefix] = REP_PREFIX;
15886 OP_IMREG (bytemode, sizeflag);
15889 OP_ESreg (bytemode, sizeflag);
15892 OP_DSreg (bytemode, sizeflag);
15900 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15904 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15906 if (prefixes & PREFIX_REPNZ)
15907 all_prefixes[last_repnz_prefix] = BND_PREFIX;
15910 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15911 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15915 HLE_Fixup1 (int bytemode, int sizeflag)
15918 && (prefixes & PREFIX_LOCK) != 0)
15920 if (prefixes & PREFIX_REPZ)
15921 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15922 if (prefixes & PREFIX_REPNZ)
15923 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15926 OP_E (bytemode, sizeflag);
15929 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15930 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15934 HLE_Fixup2 (int bytemode, int sizeflag)
15936 if (modrm.mod != 3)
15938 if (prefixes & PREFIX_REPZ)
15939 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15940 if (prefixes & PREFIX_REPNZ)
15941 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15944 OP_E (bytemode, sizeflag);
15947 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15948 "xrelease" for memory operand. No check for LOCK prefix. */
15951 HLE_Fixup3 (int bytemode, int sizeflag)
15954 && last_repz_prefix > last_repnz_prefix
15955 && (prefixes & PREFIX_REPZ) != 0)
15956 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15958 OP_E (bytemode, sizeflag);
15962 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15967 /* Change cmpxchg8b to cmpxchg16b. */
15968 char *p = mnemonicendp - 2;
15969 mnemonicendp = stpcpy (p, "16b");
15972 else if ((prefixes & PREFIX_LOCK) != 0)
15974 if (prefixes & PREFIX_REPZ)
15975 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15976 if (prefixes & PREFIX_REPNZ)
15977 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15980 OP_M (bytemode, sizeflag);
15984 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15986 const char **names;
15990 switch (vex.length)
16004 oappend (names[reg]);
16008 CRC32_Fixup (int bytemode, int sizeflag)
16010 /* Add proper suffix to "crc32". */
16011 char *p = mnemonicendp;
16030 if (sizeflag & DFLAG)
16034 used_prefixes |= (prefixes & PREFIX_DATA);
16038 oappend (INTERNAL_DISASSEMBLER_ERROR);
16045 if (modrm.mod == 3)
16049 /* Skip mod/rm byte. */
16054 add = (rex & REX_B) ? 8 : 0;
16055 if (bytemode == b_mode)
16059 oappend (names8rex[modrm.rm + add]);
16061 oappend (names8[modrm.rm + add]);
16067 oappend (names64[modrm.rm + add]);
16068 else if ((prefixes & PREFIX_DATA))
16069 oappend (names16[modrm.rm + add]);
16071 oappend (names32[modrm.rm + add]);
16075 OP_E (bytemode, sizeflag);
16079 FXSAVE_Fixup (int bytemode, int sizeflag)
16081 /* Add proper suffix to "fxsave" and "fxrstor". */
16085 char *p = mnemonicendp;
16091 OP_M (bytemode, sizeflag);
16094 /* Display the destination register operand for instructions with
16098 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16101 const char **names;
16109 reg = vex.register_specifier;
16116 if (bytemode == vex_scalar_mode)
16118 oappend (names_xmm[reg]);
16122 switch (vex.length)
16129 case vex_vsib_q_w_dq_mode:
16130 case vex_vsib_q_w_d_mode:
16140 names = names_mask;
16154 case vex_vsib_q_w_dq_mode:
16155 case vex_vsib_q_w_d_mode:
16156 names = vex.w ? names_ymm : names_xmm;
16159 names = names_mask;
16173 oappend (names[reg]);
16176 /* Get the VEX immediate byte without moving codep. */
16178 static unsigned char
16179 get_vex_imm8 (int sizeflag, int opnum)
16181 int bytes_before_imm = 0;
16183 if (modrm.mod != 3)
16185 /* There are SIB/displacement bytes. */
16186 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16188 /* 32/64 bit address mode */
16189 int base = modrm.rm;
16191 /* Check SIB byte. */
16194 FETCH_DATA (the_info, codep + 1);
16196 /* When decoding the third source, don't increase
16197 bytes_before_imm as this has already been incremented
16198 by one in OP_E_memory while decoding the second
16201 bytes_before_imm++;
16204 /* Don't increase bytes_before_imm when decoding the third source,
16205 it has already been incremented by OP_E_memory while decoding
16206 the second source operand. */
16212 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16213 SIB == 5, there is a 4 byte displacement. */
16215 /* No displacement. */
16218 /* 4 byte displacement. */
16219 bytes_before_imm += 4;
16222 /* 1 byte displacement. */
16223 bytes_before_imm++;
16230 /* 16 bit address mode */
16231 /* Don't increase bytes_before_imm when decoding the third source,
16232 it has already been incremented by OP_E_memory while decoding
16233 the second source operand. */
16239 /* When modrm.rm == 6, there is a 2 byte displacement. */
16241 /* No displacement. */
16244 /* 2 byte displacement. */
16245 bytes_before_imm += 2;
16248 /* 1 byte displacement: when decoding the third source,
16249 don't increase bytes_before_imm as this has already
16250 been incremented by one in OP_E_memory while decoding
16251 the second source operand. */
16253 bytes_before_imm++;
16261 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16262 return codep [bytes_before_imm];
16266 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16268 const char **names;
16270 if (reg == -1 && modrm.mod != 3)
16272 OP_E_memory (bytemode, sizeflag);
16284 else if (reg > 7 && address_mode != mode_64bit)
16288 switch (vex.length)
16299 oappend (names[reg]);
16303 OP_EX_VexImmW (int bytemode, int sizeflag)
16306 static unsigned char vex_imm8;
16308 if (vex_w_done == 0)
16312 /* Skip mod/rm byte. */
16316 vex_imm8 = get_vex_imm8 (sizeflag, 0);
16319 reg = vex_imm8 >> 4;
16321 OP_EX_VexReg (bytemode, sizeflag, reg);
16323 else if (vex_w_done == 1)
16328 reg = vex_imm8 >> 4;
16330 OP_EX_VexReg (bytemode, sizeflag, reg);
16334 /* Output the imm8 directly. */
16335 scratchbuf[0] = '$';
16336 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16337 oappend_maybe_intel (scratchbuf);
16338 scratchbuf[0] = '\0';
16344 OP_Vex_2src (int bytemode, int sizeflag)
16346 if (modrm.mod == 3)
16348 int reg = modrm.rm;
16352 oappend (names_xmm[reg]);
16357 && (bytemode == v_mode || bytemode == v_swap_mode))
16359 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16360 used_prefixes |= (prefixes & PREFIX_DATA);
16362 OP_E (bytemode, sizeflag);
16367 OP_Vex_2src_1 (int bytemode, int sizeflag)
16369 if (modrm.mod == 3)
16371 /* Skip mod/rm byte. */
16377 oappend (names_xmm[vex.register_specifier]);
16379 OP_Vex_2src (bytemode, sizeflag);
16383 OP_Vex_2src_2 (int bytemode, int sizeflag)
16386 OP_Vex_2src (bytemode, sizeflag);
16388 oappend (names_xmm[vex.register_specifier]);
16392 OP_EX_VexW (int bytemode, int sizeflag)
16400 /* Skip mod/rm byte. */
16405 reg = get_vex_imm8 (sizeflag, 0) >> 4;
16410 reg = get_vex_imm8 (sizeflag, 1) >> 4;
16413 OP_EX_VexReg (bytemode, sizeflag, reg);
16417 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16418 int sizeflag ATTRIBUTE_UNUSED)
16420 /* Skip the immediate byte and check for invalid bits. */
16421 FETCH_DATA (the_info, codep + 1);
16422 if (*codep++ & 0xf)
16427 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16430 const char **names;
16432 FETCH_DATA (the_info, codep + 1);
16435 if (bytemode != x_mode)
16442 if (reg > 7 && address_mode != mode_64bit)
16445 switch (vex.length)
16456 oappend (names[reg]);
16460 OP_XMM_VexW (int bytemode, int sizeflag)
16462 /* Turn off the REX.W bit since it is used for swapping operands
16465 OP_XMM (bytemode, sizeflag);
16469 OP_EX_Vex (int bytemode, int sizeflag)
16471 if (modrm.mod != 3)
16473 if (vex.register_specifier != 0)
16477 OP_EX (bytemode, sizeflag);
16481 OP_XMM_Vex (int bytemode, int sizeflag)
16483 if (modrm.mod != 3)
16485 if (vex.register_specifier != 0)
16489 OP_XMM (bytemode, sizeflag);
16493 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16495 switch (vex.length)
16498 mnemonicendp = stpcpy (obuf, "vzeroupper");
16501 mnemonicendp = stpcpy (obuf, "vzeroall");
16508 static struct op vex_cmp_op[] =
16510 { STRING_COMMA_LEN ("eq") },
16511 { STRING_COMMA_LEN ("lt") },
16512 { STRING_COMMA_LEN ("le") },
16513 { STRING_COMMA_LEN ("unord") },
16514 { STRING_COMMA_LEN ("neq") },
16515 { STRING_COMMA_LEN ("nlt") },
16516 { STRING_COMMA_LEN ("nle") },
16517 { STRING_COMMA_LEN ("ord") },
16518 { STRING_COMMA_LEN ("eq_uq") },
16519 { STRING_COMMA_LEN ("nge") },
16520 { STRING_COMMA_LEN ("ngt") },
16521 { STRING_COMMA_LEN ("false") },
16522 { STRING_COMMA_LEN ("neq_oq") },
16523 { STRING_COMMA_LEN ("ge") },
16524 { STRING_COMMA_LEN ("gt") },
16525 { STRING_COMMA_LEN ("true") },
16526 { STRING_COMMA_LEN ("eq_os") },
16527 { STRING_COMMA_LEN ("lt_oq") },
16528 { STRING_COMMA_LEN ("le_oq") },
16529 { STRING_COMMA_LEN ("unord_s") },
16530 { STRING_COMMA_LEN ("neq_us") },
16531 { STRING_COMMA_LEN ("nlt_uq") },
16532 { STRING_COMMA_LEN ("nle_uq") },
16533 { STRING_COMMA_LEN ("ord_s") },
16534 { STRING_COMMA_LEN ("eq_us") },
16535 { STRING_COMMA_LEN ("nge_uq") },
16536 { STRING_COMMA_LEN ("ngt_uq") },
16537 { STRING_COMMA_LEN ("false_os") },
16538 { STRING_COMMA_LEN ("neq_os") },
16539 { STRING_COMMA_LEN ("ge_oq") },
16540 { STRING_COMMA_LEN ("gt_oq") },
16541 { STRING_COMMA_LEN ("true_us") },
16545 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16547 unsigned int cmp_type;
16549 FETCH_DATA (the_info, codep + 1);
16550 cmp_type = *codep++ & 0xff;
16551 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16554 char *p = mnemonicendp - 2;
16558 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16559 mnemonicendp += vex_cmp_op[cmp_type].len;
16563 /* We have a reserved extension byte. Output it directly. */
16564 scratchbuf[0] = '$';
16565 print_operand_value (scratchbuf + 1, 1, cmp_type);
16566 oappend_maybe_intel (scratchbuf);
16567 scratchbuf[0] = '\0';
16572 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16573 int sizeflag ATTRIBUTE_UNUSED)
16575 unsigned int cmp_type;
16580 FETCH_DATA (the_info, codep + 1);
16581 cmp_type = *codep++ & 0xff;
16582 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16583 If it's the case, print suffix, otherwise - print the immediate. */
16584 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16589 char *p = mnemonicendp - 2;
16591 /* vpcmp* can have both one- and two-lettered suffix. */
16605 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16606 mnemonicendp += simd_cmp_op[cmp_type].len;
16610 /* We have a reserved extension byte. Output it directly. */
16611 scratchbuf[0] = '$';
16612 print_operand_value (scratchbuf + 1, 1, cmp_type);
16613 oappend_maybe_intel (scratchbuf);
16614 scratchbuf[0] = '\0';
16618 static const struct op pclmul_op[] =
16620 { STRING_COMMA_LEN ("lql") },
16621 { STRING_COMMA_LEN ("hql") },
16622 { STRING_COMMA_LEN ("lqh") },
16623 { STRING_COMMA_LEN ("hqh") }
16627 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16628 int sizeflag ATTRIBUTE_UNUSED)
16630 unsigned int pclmul_type;
16632 FETCH_DATA (the_info, codep + 1);
16633 pclmul_type = *codep++ & 0xff;
16634 switch (pclmul_type)
16645 if (pclmul_type < ARRAY_SIZE (pclmul_op))
16648 char *p = mnemonicendp - 3;
16653 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16654 mnemonicendp += pclmul_op[pclmul_type].len;
16658 /* We have a reserved extension byte. Output it directly. */
16659 scratchbuf[0] = '$';
16660 print_operand_value (scratchbuf + 1, 1, pclmul_type);
16661 oappend_maybe_intel (scratchbuf);
16662 scratchbuf[0] = '\0';
16667 MOVBE_Fixup (int bytemode, int sizeflag)
16669 /* Add proper suffix to "movbe". */
16670 char *p = mnemonicendp;
16679 if (sizeflag & SUFFIX_ALWAYS)
16685 if (sizeflag & DFLAG)
16689 used_prefixes |= (prefixes & PREFIX_DATA);
16694 oappend (INTERNAL_DISASSEMBLER_ERROR);
16701 OP_M (bytemode, sizeflag);
16705 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16708 const char **names;
16710 /* Skip mod/rm byte. */
16724 oappend (names[reg]);
16728 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16730 const char **names;
16737 oappend (names[vex.register_specifier]);
16741 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16744 || bytemode != mask_mode)
16748 if ((rex & REX_R) != 0 || !vex.r)
16754 oappend (names_mask [modrm.reg]);
16758 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16761 || (bytemode != evex_rounding_mode
16762 && bytemode != evex_sae_mode))
16764 if (modrm.mod == 3 && vex.b)
16767 case evex_rounding_mode:
16768 oappend (names_rounding[vex.ll]);
16770 case evex_sae_mode: