1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma, disassemble_info *);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma get64 (void);
58 static bfd_signed_vma get32 (void);
59 static bfd_signed_vma get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void HLE_Fixup1 (int, int);
113 static void HLE_Fixup2 (int, int);
114 static void HLE_Fixup3 (int, int);
115 static void CMPXCHG8B_Fixup (int, int);
116 static void XMM_Fixup (int, int);
117 static void CRC32_Fixup (int, int);
118 static void FXSAVE_Fixup (int, int);
119 static void OP_LWPCB_E (int, int);
120 static void OP_LWP_E (int, int);
121 static void OP_Vex_2src_1 (int, int);
122 static void OP_Vex_2src_2 (int, int);
124 static void MOVBE_Fixup (int, int);
126 static void OP_Mask (int, int);
129 /* Points to first byte not fetched. */
130 bfd_byte *max_fetched;
131 bfd_byte the_buffer[MAX_MNEM_SIZE];
134 OPCODES_SIGJMP_BUF bailout;
144 enum address_mode address_mode;
146 /* Flags for the prefixes for the current instruction. See below. */
149 /* REX prefix the current instruction. See below. */
151 /* Bits of REX we've already used. */
153 /* REX bits in original REX prefix ignored. */
154 static int rex_ignored;
155 /* Mark parts used in the REX prefix. When we are testing for
156 empty prefix (for 8bit register REX extension), just mask it
157 out. Otherwise test for REX bit is excuse for existence of REX
158 only in case value is nonzero. */
159 #define USED_REX(value) \
164 rex_used |= (value) | REX_OPCODE; \
167 rex_used |= REX_OPCODE; \
170 /* Flags for prefixes which we somehow handled when printing the
171 current instruction. */
172 static int used_prefixes;
174 /* Flags stored in PREFIXES. */
175 #define PREFIX_REPZ 1
176 #define PREFIX_REPNZ 2
177 #define PREFIX_LOCK 4
179 #define PREFIX_SS 0x10
180 #define PREFIX_DS 0x20
181 #define PREFIX_ES 0x40
182 #define PREFIX_FS 0x80
183 #define PREFIX_GS 0x100
184 #define PREFIX_DATA 0x200
185 #define PREFIX_ADDR 0x400
186 #define PREFIX_FWAIT 0x800
188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
189 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
191 #define FETCH_DATA(info, addr) \
192 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
193 ? 1 : fetch_data ((info), (addr)))
196 fetch_data (struct disassemble_info *info, bfd_byte *addr)
199 struct dis_private *priv = (struct dis_private *) info->private_data;
200 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
202 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
203 status = (*info->read_memory_func) (start,
205 addr - priv->max_fetched,
211 /* If we did manage to read at least one byte, then
212 print_insn_i386 will do something sensible. Otherwise, print
213 an error. We do that here because this is where we know
215 if (priv->max_fetched == priv->the_buffer)
216 (*info->memory_error_func) (status, start, info);
217 OPCODES_SIGLONGJMP (priv->bailout, 1);
220 priv->max_fetched = addr;
224 #define XX { NULL, 0 }
225 #define Bad_Opcode NULL, { { NULL, 0 } }
227 #define Eb { OP_E, b_mode }
228 #define Ebnd { OP_E, bnd_mode }
229 #define EbS { OP_E, b_swap_mode }
230 #define Ev { OP_E, v_mode }
231 #define Ev_bnd { OP_E, v_bnd_mode }
232 #define EvS { OP_E, v_swap_mode }
233 #define Ed { OP_E, d_mode }
234 #define Edq { OP_E, dq_mode }
235 #define Edqw { OP_E, dqw_mode }
236 #define EdqwS { OP_E, dqw_swap_mode }
237 #define Edqb { OP_E, dqb_mode }
238 #define Edb { OP_E, db_mode }
239 #define Edw { OP_E, dw_mode }
240 #define Edqd { OP_E, dqd_mode }
241 #define Eq { OP_E, q_mode }
242 #define indirEv { OP_indirE, stack_v_mode }
243 #define indirEp { OP_indirE, f_mode }
244 #define stackEv { OP_E, stack_v_mode }
245 #define Em { OP_E, m_mode }
246 #define Ew { OP_E, w_mode }
247 #define M { OP_M, 0 } /* lea, lgdt, etc. */
248 #define Ma { OP_M, a_mode }
249 #define Mb { OP_M, b_mode }
250 #define Md { OP_M, d_mode }
251 #define Mo { OP_M, o_mode }
252 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
253 #define Mq { OP_M, q_mode }
254 #define Mx { OP_M, x_mode }
255 #define Mxmm { OP_M, xmm_mode }
256 #define Gb { OP_G, b_mode }
257 #define Gbnd { OP_G, bnd_mode }
258 #define Gv { OP_G, v_mode }
259 #define Gd { OP_G, d_mode }
260 #define Gdq { OP_G, dq_mode }
261 #define Gm { OP_G, m_mode }
262 #define Gw { OP_G, w_mode }
263 #define Rd { OP_R, d_mode }
264 #define Rdq { OP_R, dq_mode }
265 #define Rm { OP_R, m_mode }
266 #define Ib { OP_I, b_mode }
267 #define sIb { OP_sI, b_mode } /* sign extened byte */
268 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
269 #define Iv { OP_I, v_mode }
270 #define sIv { OP_sI, v_mode }
271 #define Iq { OP_I, q_mode }
272 #define Iv64 { OP_I64, v_mode }
273 #define Iw { OP_I, w_mode }
274 #define I1 { OP_I, const_1_mode }
275 #define Jb { OP_J, b_mode }
276 #define Jv { OP_J, v_mode }
277 #define Cm { OP_C, m_mode }
278 #define Dm { OP_D, m_mode }
279 #define Td { OP_T, d_mode }
280 #define Skip_MODRM { OP_Skip_MODRM, 0 }
282 #define RMeAX { OP_REG, eAX_reg }
283 #define RMeBX { OP_REG, eBX_reg }
284 #define RMeCX { OP_REG, eCX_reg }
285 #define RMeDX { OP_REG, eDX_reg }
286 #define RMeSP { OP_REG, eSP_reg }
287 #define RMeBP { OP_REG, eBP_reg }
288 #define RMeSI { OP_REG, eSI_reg }
289 #define RMeDI { OP_REG, eDI_reg }
290 #define RMrAX { OP_REG, rAX_reg }
291 #define RMrBX { OP_REG, rBX_reg }
292 #define RMrCX { OP_REG, rCX_reg }
293 #define RMrDX { OP_REG, rDX_reg }
294 #define RMrSP { OP_REG, rSP_reg }
295 #define RMrBP { OP_REG, rBP_reg }
296 #define RMrSI { OP_REG, rSI_reg }
297 #define RMrDI { OP_REG, rDI_reg }
298 #define RMAL { OP_REG, al_reg }
299 #define RMCL { OP_REG, cl_reg }
300 #define RMDL { OP_REG, dl_reg }
301 #define RMBL { OP_REG, bl_reg }
302 #define RMAH { OP_REG, ah_reg }
303 #define RMCH { OP_REG, ch_reg }
304 #define RMDH { OP_REG, dh_reg }
305 #define RMBH { OP_REG, bh_reg }
306 #define RMAX { OP_REG, ax_reg }
307 #define RMDX { OP_REG, dx_reg }
309 #define eAX { OP_IMREG, eAX_reg }
310 #define eBX { OP_IMREG, eBX_reg }
311 #define eCX { OP_IMREG, eCX_reg }
312 #define eDX { OP_IMREG, eDX_reg }
313 #define eSP { OP_IMREG, eSP_reg }
314 #define eBP { OP_IMREG, eBP_reg }
315 #define eSI { OP_IMREG, eSI_reg }
316 #define eDI { OP_IMREG, eDI_reg }
317 #define AL { OP_IMREG, al_reg }
318 #define CL { OP_IMREG, cl_reg }
319 #define DL { OP_IMREG, dl_reg }
320 #define BL { OP_IMREG, bl_reg }
321 #define AH { OP_IMREG, ah_reg }
322 #define CH { OP_IMREG, ch_reg }
323 #define DH { OP_IMREG, dh_reg }
324 #define BH { OP_IMREG, bh_reg }
325 #define AX { OP_IMREG, ax_reg }
326 #define DX { OP_IMREG, dx_reg }
327 #define zAX { OP_IMREG, z_mode_ax_reg }
328 #define indirDX { OP_IMREG, indir_dx_reg }
330 #define Sw { OP_SEG, w_mode }
331 #define Sv { OP_SEG, v_mode }
332 #define Ap { OP_DIR, 0 }
333 #define Ob { OP_OFF64, b_mode }
334 #define Ov { OP_OFF64, v_mode }
335 #define Xb { OP_DSreg, eSI_reg }
336 #define Xv { OP_DSreg, eSI_reg }
337 #define Xz { OP_DSreg, eSI_reg }
338 #define Yb { OP_ESreg, eDI_reg }
339 #define Yv { OP_ESreg, eDI_reg }
340 #define DSBX { OP_DSreg, eBX_reg }
342 #define es { OP_REG, es_reg }
343 #define ss { OP_REG, ss_reg }
344 #define cs { OP_REG, cs_reg }
345 #define ds { OP_REG, ds_reg }
346 #define fs { OP_REG, fs_reg }
347 #define gs { OP_REG, gs_reg }
349 #define MX { OP_MMX, 0 }
350 #define XM { OP_XMM, 0 }
351 #define XMScalar { OP_XMM, scalar_mode }
352 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
353 #define XMM { OP_XMM, xmm_mode }
354 #define XMxmmq { OP_XMM, xmmq_mode }
355 #define EM { OP_EM, v_mode }
356 #define EMS { OP_EM, v_swap_mode }
357 #define EMd { OP_EM, d_mode }
358 #define EMx { OP_EM, x_mode }
359 #define EXw { OP_EX, w_mode }
360 #define EXd { OP_EX, d_mode }
361 #define EXdScalar { OP_EX, d_scalar_mode }
362 #define EXdS { OP_EX, d_swap_mode }
363 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
364 #define EXq { OP_EX, q_mode }
365 #define EXqScalar { OP_EX, q_scalar_mode }
366 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
367 #define EXqS { OP_EX, q_swap_mode }
368 #define EXx { OP_EX, x_mode }
369 #define EXxS { OP_EX, x_swap_mode }
370 #define EXxmm { OP_EX, xmm_mode }
371 #define EXymm { OP_EX, ymm_mode }
372 #define EXxmmq { OP_EX, xmmq_mode }
373 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
374 #define EXxmm_mb { OP_EX, xmm_mb_mode }
375 #define EXxmm_mw { OP_EX, xmm_mw_mode }
376 #define EXxmm_md { OP_EX, xmm_md_mode }
377 #define EXxmm_mq { OP_EX, xmm_mq_mode }
378 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
379 #define EXxmmdw { OP_EX, xmmdw_mode }
380 #define EXxmmqd { OP_EX, xmmqd_mode }
381 #define EXymmq { OP_EX, ymmq_mode }
382 #define EXVexWdq { OP_EX, vex_w_dq_mode }
383 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
384 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
385 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
386 #define MS { OP_MS, v_mode }
387 #define XS { OP_XS, v_mode }
388 #define EMCq { OP_EMC, q_mode }
389 #define MXC { OP_MXC, 0 }
390 #define OPSUF { OP_3DNowSuffix, 0 }
391 #define CMP { CMP_Fixup, 0 }
392 #define XMM0 { XMM_Fixup, 0 }
393 #define FXSAVE { FXSAVE_Fixup, 0 }
394 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
395 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
397 #define Vex { OP_VEX, vex_mode }
398 #define VexScalar { OP_VEX, vex_scalar_mode }
399 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
400 #define Vex128 { OP_VEX, vex128_mode }
401 #define Vex256 { OP_VEX, vex256_mode }
402 #define VexGdq { OP_VEX, dq_mode }
403 #define VexI4 { VEXI4_Fixup, 0}
404 #define EXdVex { OP_EX_Vex, d_mode }
405 #define EXdVexS { OP_EX_Vex, d_swap_mode }
406 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
407 #define EXqVex { OP_EX_Vex, q_mode }
408 #define EXqVexS { OP_EX_Vex, q_swap_mode }
409 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
410 #define EXVexW { OP_EX_VexW, x_mode }
411 #define EXdVexW { OP_EX_VexW, d_mode }
412 #define EXqVexW { OP_EX_VexW, q_mode }
413 #define EXVexImmW { OP_EX_VexImmW, x_mode }
414 #define XMVex { OP_XMM_Vex, 0 }
415 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
416 #define XMVexW { OP_XMM_VexW, 0 }
417 #define XMVexI4 { OP_REG_VexI4, x_mode }
418 #define PCLMUL { PCLMUL_Fixup, 0 }
419 #define VZERO { VZERO_Fixup, 0 }
420 #define VCMP { VCMP_Fixup, 0 }
421 #define VPCMP { VPCMP_Fixup, 0 }
423 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
424 #define EXxEVexS { OP_Rounding, evex_sae_mode }
426 #define XMask { OP_Mask, mask_mode }
427 #define MaskG { OP_G, mask_mode }
428 #define MaskE { OP_E, mask_mode }
429 #define MaskBDE { OP_E, mask_bd_mode }
430 #define MaskR { OP_R, mask_mode }
431 #define MaskVex { OP_VEX, mask_mode }
433 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
434 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
435 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
436 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
438 /* Used handle "rep" prefix for string instructions. */
439 #define Xbr { REP_Fixup, eSI_reg }
440 #define Xvr { REP_Fixup, eSI_reg }
441 #define Ybr { REP_Fixup, eDI_reg }
442 #define Yvr { REP_Fixup, eDI_reg }
443 #define Yzr { REP_Fixup, eDI_reg }
444 #define indirDXr { REP_Fixup, indir_dx_reg }
445 #define ALr { REP_Fixup, al_reg }
446 #define eAXr { REP_Fixup, eAX_reg }
448 /* Used handle HLE prefix for lockable instructions. */
449 #define Ebh1 { HLE_Fixup1, b_mode }
450 #define Evh1 { HLE_Fixup1, v_mode }
451 #define Ebh2 { HLE_Fixup2, b_mode }
452 #define Evh2 { HLE_Fixup2, v_mode }
453 #define Ebh3 { HLE_Fixup3, b_mode }
454 #define Evh3 { HLE_Fixup3, v_mode }
456 #define BND { BND_Fixup, 0 }
458 #define cond_jump_flag { NULL, cond_jump_mode }
459 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
461 /* bits in sizeflag */
462 #define SUFFIX_ALWAYS 4
470 /* byte operand with operand swapped */
472 /* byte operand, sign extend like 'T' suffix */
474 /* operand size depends on prefixes */
476 /* operand size depends on prefixes with operand swapped */
480 /* double word operand */
482 /* double word operand with operand swapped */
484 /* quad word operand */
486 /* quad word operand with operand swapped */
488 /* ten-byte operand */
490 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
491 broadcast enabled. */
493 /* Similar to x_mode, but with different EVEX mem shifts. */
495 /* Similar to x_mode, but with disabled broadcast. */
497 /* Similar to x_mode, but with operands swapped and disabled broadcast
500 /* 16-byte XMM operand */
502 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
503 memory operand (depending on vector length). Broadcast isn't
506 /* Same as xmmq_mode, but broadcast is allowed. */
507 evex_half_bcst_xmmq_mode,
508 /* XMM register or byte memory operand */
510 /* XMM register or word memory operand */
512 /* XMM register or double word memory operand */
514 /* XMM register or quad word memory operand */
516 /* XMM register or double/quad word memory operand, depending on
519 /* 16-byte XMM, word, double word or quad word operand. */
521 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
523 /* 32-byte YMM operand */
525 /* quad word, ymmword or zmmword memory operand. */
527 /* 32-byte YMM or 16-byte word operand */
529 /* d_mode in 32bit, q_mode in 64bit mode. */
531 /* pair of v_mode operands */
536 /* operand size depends on REX prefixes. */
538 /* registers like dq_mode, memory like w_mode. */
542 /* 4- or 6-byte pointer operand */
545 /* v_mode for stack-related opcodes. */
547 /* non-quad operand size depends on prefixes */
549 /* 16-byte operand */
551 /* registers like dq_mode, memory like b_mode. */
553 /* registers like d_mode, memory like b_mode. */
555 /* registers like d_mode, memory like w_mode. */
557 /* registers like dq_mode, memory like d_mode. */
559 /* normal vex mode */
561 /* 128bit vex mode */
563 /* 256bit vex mode */
565 /* operand size depends on the VEX.W bit. */
568 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
569 vex_vsib_d_w_dq_mode,
570 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
572 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
573 vex_vsib_q_w_dq_mode,
574 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
577 /* scalar, ignore vector length. */
579 /* like d_mode, ignore vector length. */
581 /* like d_swap_mode, ignore vector length. */
583 /* like q_mode, ignore vector length. */
585 /* like q_swap_mode, ignore vector length. */
587 /* like vex_mode, ignore vector length. */
589 /* like vex_w_dq_mode, ignore vector length. */
590 vex_scalar_w_dq_mode,
592 /* Static rounding. */
594 /* Supress all exceptions. */
597 /* Mask register operand. */
599 /* Mask register operand. */
666 #define FLOAT NULL, { { NULL, FLOATCODE } }
668 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
669 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
670 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
671 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
672 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
673 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
674 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
675 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
676 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
677 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
678 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
679 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
680 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
796 MOD_VEX_0F12_PREFIX_0,
798 MOD_VEX_0F16_PREFIX_0,
814 MOD_VEX_0FD7_PREFIX_2,
815 MOD_VEX_0FE7_PREFIX_2,
816 MOD_VEX_0FF0_PREFIX_3,
817 MOD_VEX_0F381A_PREFIX_2,
818 MOD_VEX_0F382A_PREFIX_2,
819 MOD_VEX_0F382C_PREFIX_2,
820 MOD_VEX_0F382D_PREFIX_2,
821 MOD_VEX_0F382E_PREFIX_2,
822 MOD_VEX_0F382F_PREFIX_2,
823 MOD_VEX_0F385A_PREFIX_2,
824 MOD_VEX_0F388C_PREFIX_2,
825 MOD_VEX_0F388E_PREFIX_2,
827 MOD_EVEX_0F10_PREFIX_1,
828 MOD_EVEX_0F10_PREFIX_3,
829 MOD_EVEX_0F11_PREFIX_1,
830 MOD_EVEX_0F11_PREFIX_3,
831 MOD_EVEX_0F12_PREFIX_0,
832 MOD_EVEX_0F16_PREFIX_0,
833 MOD_EVEX_0F38C6_REG_1,
834 MOD_EVEX_0F38C6_REG_2,
835 MOD_EVEX_0F38C6_REG_5,
836 MOD_EVEX_0F38C6_REG_6,
837 MOD_EVEX_0F38C7_REG_1,
838 MOD_EVEX_0F38C7_REG_2,
839 MOD_EVEX_0F38C7_REG_5,
840 MOD_EVEX_0F38C7_REG_6
904 PREFIX_RM_0_0FAE_REG_7,
1034 PREFIX_VEX_0F71_REG_2,
1035 PREFIX_VEX_0F71_REG_4,
1036 PREFIX_VEX_0F71_REG_6,
1037 PREFIX_VEX_0F72_REG_2,
1038 PREFIX_VEX_0F72_REG_4,
1039 PREFIX_VEX_0F72_REG_6,
1040 PREFIX_VEX_0F73_REG_2,
1041 PREFIX_VEX_0F73_REG_3,
1042 PREFIX_VEX_0F73_REG_6,
1043 PREFIX_VEX_0F73_REG_7,
1215 PREFIX_VEX_0F38F3_REG_1,
1216 PREFIX_VEX_0F38F3_REG_2,
1217 PREFIX_VEX_0F38F3_REG_3,
1334 PREFIX_EVEX_0F71_REG_2,
1335 PREFIX_EVEX_0F71_REG_4,
1336 PREFIX_EVEX_0F71_REG_6,
1337 PREFIX_EVEX_0F72_REG_0,
1338 PREFIX_EVEX_0F72_REG_1,
1339 PREFIX_EVEX_0F72_REG_2,
1340 PREFIX_EVEX_0F72_REG_4,
1341 PREFIX_EVEX_0F72_REG_6,
1342 PREFIX_EVEX_0F73_REG_2,
1343 PREFIX_EVEX_0F73_REG_3,
1344 PREFIX_EVEX_0F73_REG_6,
1345 PREFIX_EVEX_0F73_REG_7,
1525 PREFIX_EVEX_0F38C6_REG_1,
1526 PREFIX_EVEX_0F38C6_REG_2,
1527 PREFIX_EVEX_0F38C6_REG_5,
1528 PREFIX_EVEX_0F38C6_REG_6,
1529 PREFIX_EVEX_0F38C7_REG_1,
1530 PREFIX_EVEX_0F38C7_REG_2,
1531 PREFIX_EVEX_0F38C7_REG_5,
1532 PREFIX_EVEX_0F38C7_REG_6,
1619 THREE_BYTE_0F38 = 0,
1647 VEX_LEN_0F10_P_1 = 0,
1651 VEX_LEN_0F12_P_0_M_0,
1652 VEX_LEN_0F12_P_0_M_1,
1655 VEX_LEN_0F16_P_0_M_0,
1656 VEX_LEN_0F16_P_0_M_1,
1720 VEX_LEN_0FAE_R_2_M_0,
1721 VEX_LEN_0FAE_R_3_M_0,
1730 VEX_LEN_0F381A_P_2_M_0,
1733 VEX_LEN_0F385A_P_2_M_0,
1740 VEX_LEN_0F38F3_R_1_P_0,
1741 VEX_LEN_0F38F3_R_2_P_0,
1742 VEX_LEN_0F38F3_R_3_P_0,
1788 VEX_LEN_0FXOP_08_CC,
1789 VEX_LEN_0FXOP_08_CD,
1790 VEX_LEN_0FXOP_08_CE,
1791 VEX_LEN_0FXOP_08_CF,
1792 VEX_LEN_0FXOP_08_EC,
1793 VEX_LEN_0FXOP_08_ED,
1794 VEX_LEN_0FXOP_08_EE,
1795 VEX_LEN_0FXOP_08_EF,
1796 VEX_LEN_0FXOP_09_80,
1830 VEX_W_0F41_P_0_LEN_1,
1831 VEX_W_0F41_P_2_LEN_1,
1832 VEX_W_0F42_P_0_LEN_1,
1833 VEX_W_0F42_P_2_LEN_1,
1834 VEX_W_0F44_P_0_LEN_0,
1835 VEX_W_0F44_P_2_LEN_0,
1836 VEX_W_0F45_P_0_LEN_1,
1837 VEX_W_0F45_P_2_LEN_1,
1838 VEX_W_0F46_P_0_LEN_1,
1839 VEX_W_0F46_P_2_LEN_1,
1840 VEX_W_0F47_P_0_LEN_1,
1841 VEX_W_0F47_P_2_LEN_1,
1842 VEX_W_0F4A_P_0_LEN_1,
1843 VEX_W_0F4A_P_2_LEN_1,
1844 VEX_W_0F4B_P_0_LEN_1,
1845 VEX_W_0F4B_P_2_LEN_1,
1925 VEX_W_0F90_P_0_LEN_0,
1926 VEX_W_0F90_P_2_LEN_0,
1927 VEX_W_0F91_P_0_LEN_0,
1928 VEX_W_0F91_P_2_LEN_0,
1929 VEX_W_0F92_P_0_LEN_0,
1930 VEX_W_0F92_P_2_LEN_0,
1931 VEX_W_0F92_P_3_LEN_0,
1932 VEX_W_0F93_P_0_LEN_0,
1933 VEX_W_0F93_P_2_LEN_0,
1934 VEX_W_0F93_P_3_LEN_0,
1935 VEX_W_0F98_P_0_LEN_0,
1936 VEX_W_0F98_P_2_LEN_0,
1937 VEX_W_0F99_P_0_LEN_0,
1938 VEX_W_0F99_P_2_LEN_0,
2017 VEX_W_0F381A_P_2_M_0,
2029 VEX_W_0F382A_P_2_M_0,
2031 VEX_W_0F382C_P_2_M_0,
2032 VEX_W_0F382D_P_2_M_0,
2033 VEX_W_0F382E_P_2_M_0,
2034 VEX_W_0F382F_P_2_M_0,
2056 VEX_W_0F385A_P_2_M_0,
2084 VEX_W_0F3A30_P_2_LEN_0,
2085 VEX_W_0F3A31_P_2_LEN_0,
2086 VEX_W_0F3A32_P_2_LEN_0,
2087 VEX_W_0F3A33_P_2_LEN_0,
2107 EVEX_W_0F10_P_1_M_0,
2108 EVEX_W_0F10_P_1_M_1,
2110 EVEX_W_0F10_P_3_M_0,
2111 EVEX_W_0F10_P_3_M_1,
2113 EVEX_W_0F11_P_1_M_0,
2114 EVEX_W_0F11_P_1_M_1,
2116 EVEX_W_0F11_P_3_M_0,
2117 EVEX_W_0F11_P_3_M_1,
2118 EVEX_W_0F12_P_0_M_0,
2119 EVEX_W_0F12_P_0_M_1,
2129 EVEX_W_0F16_P_0_M_0,
2130 EVEX_W_0F16_P_0_M_1,
2201 EVEX_W_0F72_R_2_P_2,
2202 EVEX_W_0F72_R_6_P_2,
2203 EVEX_W_0F73_R_2_P_2,
2204 EVEX_W_0F73_R_6_P_2,
2303 EVEX_W_0F38C7_R_1_P_2,
2304 EVEX_W_0F38C7_R_2_P_2,
2305 EVEX_W_0F38C7_R_5_P_2,
2306 EVEX_W_0F38C7_R_6_P_2,
2341 typedef void (*op_rtn) (int bytemode, int sizeflag);
2352 /* Upper case letters in the instruction names here are macros.
2353 'A' => print 'b' if no register operands or suffix_always is true
2354 'B' => print 'b' if suffix_always is true
2355 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2357 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2358 suffix_always is true
2359 'E' => print 'e' if 32-bit form of jcxz
2360 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2361 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2362 'H' => print ",pt" or ",pn" branch hint
2363 'I' => honor following macro letter even in Intel mode (implemented only
2364 for some of the macro letters)
2366 'K' => print 'd' or 'q' if rex prefix is present.
2367 'L' => print 'l' if suffix_always is true
2368 'M' => print 'r' if intel_mnemonic is false.
2369 'N' => print 'n' if instruction has no wait "prefix"
2370 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2371 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2372 or suffix_always is true. print 'q' if rex prefix is present.
2373 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2375 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2376 'S' => print 'w', 'l' or 'q' if suffix_always is true
2377 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2378 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2379 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2380 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2381 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2382 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2383 suffix_always is true.
2384 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2385 '!' => change condition from true to false or from false to true.
2386 '%' => add 1 upper case letter to the macro.
2388 2 upper case letter macros:
2389 "XY" => print 'x' or 'y' if no register operands or suffix_always
2391 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2392 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2393 or suffix_always is true
2394 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2395 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2396 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2397 "LW" => print 'd', 'q' depending on the VEX.W bit
2398 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2399 an operand size prefix, or suffix_always is true. print
2400 'q' if rex prefix is present.
2402 Many of the above letters print nothing in Intel mode. See "putop"
2405 Braces '{' and '}', and vertical bars '|', indicate alternative
2406 mnemonic strings for AT&T and Intel. */
2408 static const struct dis386 dis386[] = {
2410 { "addB", { Ebh1, Gb } },
2411 { "addS", { Evh1, Gv } },
2412 { "addB", { Gb, EbS } },
2413 { "addS", { Gv, EvS } },
2414 { "addB", { AL, Ib } },
2415 { "addS", { eAX, Iv } },
2416 { X86_64_TABLE (X86_64_06) },
2417 { X86_64_TABLE (X86_64_07) },
2419 { "orB", { Ebh1, Gb } },
2420 { "orS", { Evh1, Gv } },
2421 { "orB", { Gb, EbS } },
2422 { "orS", { Gv, EvS } },
2423 { "orB", { AL, Ib } },
2424 { "orS", { eAX, Iv } },
2425 { X86_64_TABLE (X86_64_0D) },
2426 { Bad_Opcode }, /* 0x0f extended opcode escape */
2428 { "adcB", { Ebh1, Gb } },
2429 { "adcS", { Evh1, Gv } },
2430 { "adcB", { Gb, EbS } },
2431 { "adcS", { Gv, EvS } },
2432 { "adcB", { AL, Ib } },
2433 { "adcS", { eAX, Iv } },
2434 { X86_64_TABLE (X86_64_16) },
2435 { X86_64_TABLE (X86_64_17) },
2437 { "sbbB", { Ebh1, Gb } },
2438 { "sbbS", { Evh1, Gv } },
2439 { "sbbB", { Gb, EbS } },
2440 { "sbbS", { Gv, EvS } },
2441 { "sbbB", { AL, Ib } },
2442 { "sbbS", { eAX, Iv } },
2443 { X86_64_TABLE (X86_64_1E) },
2444 { X86_64_TABLE (X86_64_1F) },
2446 { "andB", { Ebh1, Gb } },
2447 { "andS", { Evh1, Gv } },
2448 { "andB", { Gb, EbS } },
2449 { "andS", { Gv, EvS } },
2450 { "andB", { AL, Ib } },
2451 { "andS", { eAX, Iv } },
2452 { Bad_Opcode }, /* SEG ES prefix */
2453 { X86_64_TABLE (X86_64_27) },
2455 { "subB", { Ebh1, Gb } },
2456 { "subS", { Evh1, Gv } },
2457 { "subB", { Gb, EbS } },
2458 { "subS", { Gv, EvS } },
2459 { "subB", { AL, Ib } },
2460 { "subS", { eAX, Iv } },
2461 { Bad_Opcode }, /* SEG CS prefix */
2462 { X86_64_TABLE (X86_64_2F) },
2464 { "xorB", { Ebh1, Gb } },
2465 { "xorS", { Evh1, Gv } },
2466 { "xorB", { Gb, EbS } },
2467 { "xorS", { Gv, EvS } },
2468 { "xorB", { AL, Ib } },
2469 { "xorS", { eAX, Iv } },
2470 { Bad_Opcode }, /* SEG SS prefix */
2471 { X86_64_TABLE (X86_64_37) },
2473 { "cmpB", { Eb, Gb } },
2474 { "cmpS", { Ev, Gv } },
2475 { "cmpB", { Gb, EbS } },
2476 { "cmpS", { Gv, EvS } },
2477 { "cmpB", { AL, Ib } },
2478 { "cmpS", { eAX, Iv } },
2479 { Bad_Opcode }, /* SEG DS prefix */
2480 { X86_64_TABLE (X86_64_3F) },
2482 { "inc{S|}", { RMeAX } },
2483 { "inc{S|}", { RMeCX } },
2484 { "inc{S|}", { RMeDX } },
2485 { "inc{S|}", { RMeBX } },
2486 { "inc{S|}", { RMeSP } },
2487 { "inc{S|}", { RMeBP } },
2488 { "inc{S|}", { RMeSI } },
2489 { "inc{S|}", { RMeDI } },
2491 { "dec{S|}", { RMeAX } },
2492 { "dec{S|}", { RMeCX } },
2493 { "dec{S|}", { RMeDX } },
2494 { "dec{S|}", { RMeBX } },
2495 { "dec{S|}", { RMeSP } },
2496 { "dec{S|}", { RMeBP } },
2497 { "dec{S|}", { RMeSI } },
2498 { "dec{S|}", { RMeDI } },
2500 { "pushV", { RMrAX } },
2501 { "pushV", { RMrCX } },
2502 { "pushV", { RMrDX } },
2503 { "pushV", { RMrBX } },
2504 { "pushV", { RMrSP } },
2505 { "pushV", { RMrBP } },
2506 { "pushV", { RMrSI } },
2507 { "pushV", { RMrDI } },
2509 { "popV", { RMrAX } },
2510 { "popV", { RMrCX } },
2511 { "popV", { RMrDX } },
2512 { "popV", { RMrBX } },
2513 { "popV", { RMrSP } },
2514 { "popV", { RMrBP } },
2515 { "popV", { RMrSI } },
2516 { "popV", { RMrDI } },
2518 { X86_64_TABLE (X86_64_60) },
2519 { X86_64_TABLE (X86_64_61) },
2520 { X86_64_TABLE (X86_64_62) },
2521 { X86_64_TABLE (X86_64_63) },
2522 { Bad_Opcode }, /* seg fs */
2523 { Bad_Opcode }, /* seg gs */
2524 { Bad_Opcode }, /* op size prefix */
2525 { Bad_Opcode }, /* adr size prefix */
2527 { "pushT", { sIv } },
2528 { "imulS", { Gv, Ev, Iv } },
2529 { "pushT", { sIbT } },
2530 { "imulS", { Gv, Ev, sIb } },
2531 { "ins{b|}", { Ybr, indirDX } },
2532 { X86_64_TABLE (X86_64_6D) },
2533 { "outs{b|}", { indirDXr, Xb } },
2534 { X86_64_TABLE (X86_64_6F) },
2536 { "joH", { Jb, BND, cond_jump_flag } },
2537 { "jnoH", { Jb, BND, cond_jump_flag } },
2538 { "jbH", { Jb, BND, cond_jump_flag } },
2539 { "jaeH", { Jb, BND, cond_jump_flag } },
2540 { "jeH", { Jb, BND, cond_jump_flag } },
2541 { "jneH", { Jb, BND, cond_jump_flag } },
2542 { "jbeH", { Jb, BND, cond_jump_flag } },
2543 { "jaH", { Jb, BND, cond_jump_flag } },
2545 { "jsH", { Jb, BND, cond_jump_flag } },
2546 { "jnsH", { Jb, BND, cond_jump_flag } },
2547 { "jpH", { Jb, BND, cond_jump_flag } },
2548 { "jnpH", { Jb, BND, cond_jump_flag } },
2549 { "jlH", { Jb, BND, cond_jump_flag } },
2550 { "jgeH", { Jb, BND, cond_jump_flag } },
2551 { "jleH", { Jb, BND, cond_jump_flag } },
2552 { "jgH", { Jb, BND, cond_jump_flag } },
2554 { REG_TABLE (REG_80) },
2555 { REG_TABLE (REG_81) },
2557 { REG_TABLE (REG_82) },
2558 { "testB", { Eb, Gb } },
2559 { "testS", { Ev, Gv } },
2560 { "xchgB", { Ebh2, Gb } },
2561 { "xchgS", { Evh2, Gv } },
2563 { "movB", { Ebh3, Gb } },
2564 { "movS", { Evh3, Gv } },
2565 { "movB", { Gb, EbS } },
2566 { "movS", { Gv, EvS } },
2567 { "movD", { Sv, Sw } },
2568 { MOD_TABLE (MOD_8D) },
2569 { "movD", { Sw, Sv } },
2570 { REG_TABLE (REG_8F) },
2572 { PREFIX_TABLE (PREFIX_90) },
2573 { "xchgS", { RMeCX, eAX } },
2574 { "xchgS", { RMeDX, eAX } },
2575 { "xchgS", { RMeBX, eAX } },
2576 { "xchgS", { RMeSP, eAX } },
2577 { "xchgS", { RMeBP, eAX } },
2578 { "xchgS", { RMeSI, eAX } },
2579 { "xchgS", { RMeDI, eAX } },
2581 { "cW{t|}R", { XX } },
2582 { "cR{t|}O", { XX } },
2583 { X86_64_TABLE (X86_64_9A) },
2584 { Bad_Opcode }, /* fwait */
2585 { "pushfT", { XX } },
2586 { "popfT", { XX } },
2590 { "mov%LB", { AL, Ob } },
2591 { "mov%LS", { eAX, Ov } },
2592 { "mov%LB", { Ob, AL } },
2593 { "mov%LS", { Ov, eAX } },
2594 { "movs{b|}", { Ybr, Xb } },
2595 { "movs{R|}", { Yvr, Xv } },
2596 { "cmps{b|}", { Xb, Yb } },
2597 { "cmps{R|}", { Xv, Yv } },
2599 { "testB", { AL, Ib } },
2600 { "testS", { eAX, Iv } },
2601 { "stosB", { Ybr, AL } },
2602 { "stosS", { Yvr, eAX } },
2603 { "lodsB", { ALr, Xb } },
2604 { "lodsS", { eAXr, Xv } },
2605 { "scasB", { AL, Yb } },
2606 { "scasS", { eAX, Yv } },
2608 { "movB", { RMAL, Ib } },
2609 { "movB", { RMCL, Ib } },
2610 { "movB", { RMDL, Ib } },
2611 { "movB", { RMBL, Ib } },
2612 { "movB", { RMAH, Ib } },
2613 { "movB", { RMCH, Ib } },
2614 { "movB", { RMDH, Ib } },
2615 { "movB", { RMBH, Ib } },
2617 { "mov%LV", { RMeAX, Iv64 } },
2618 { "mov%LV", { RMeCX, Iv64 } },
2619 { "mov%LV", { RMeDX, Iv64 } },
2620 { "mov%LV", { RMeBX, Iv64 } },
2621 { "mov%LV", { RMeSP, Iv64 } },
2622 { "mov%LV", { RMeBP, Iv64 } },
2623 { "mov%LV", { RMeSI, Iv64 } },
2624 { "mov%LV", { RMeDI, Iv64 } },
2626 { REG_TABLE (REG_C0) },
2627 { REG_TABLE (REG_C1) },
2628 { "retT", { Iw, BND } },
2629 { "retT", { BND } },
2630 { X86_64_TABLE (X86_64_C4) },
2631 { X86_64_TABLE (X86_64_C5) },
2632 { REG_TABLE (REG_C6) },
2633 { REG_TABLE (REG_C7) },
2635 { "enterT", { Iw, Ib } },
2636 { "leaveT", { XX } },
2637 { "Jret{|f}P", { Iw } },
2638 { "Jret{|f}P", { XX } },
2641 { X86_64_TABLE (X86_64_CE) },
2642 { "iret%LP", { XX } },
2644 { REG_TABLE (REG_D0) },
2645 { REG_TABLE (REG_D1) },
2646 { REG_TABLE (REG_D2) },
2647 { REG_TABLE (REG_D3) },
2648 { X86_64_TABLE (X86_64_D4) },
2649 { X86_64_TABLE (X86_64_D5) },
2651 { "xlat", { DSBX } },
2662 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
2663 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
2664 { "loopFH", { Jb, XX, loop_jcxz_flag } },
2665 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
2666 { "inB", { AL, Ib } },
2667 { "inG", { zAX, Ib } },
2668 { "outB", { Ib, AL } },
2669 { "outG", { Ib, zAX } },
2671 { "callT", { Jv, BND } },
2672 { "jmpT", { Jv, BND } },
2673 { X86_64_TABLE (X86_64_EA) },
2674 { "jmp", { Jb, BND } },
2675 { "inB", { AL, indirDX } },
2676 { "inG", { zAX, indirDX } },
2677 { "outB", { indirDX, AL } },
2678 { "outG", { indirDX, zAX } },
2680 { Bad_Opcode }, /* lock prefix */
2681 { "icebp", { XX } },
2682 { Bad_Opcode }, /* repne */
2683 { Bad_Opcode }, /* repz */
2686 { REG_TABLE (REG_F6) },
2687 { REG_TABLE (REG_F7) },
2695 { REG_TABLE (REG_FE) },
2696 { REG_TABLE (REG_FF) },
2699 static const struct dis386 dis386_twobyte[] = {
2701 { REG_TABLE (REG_0F00 ) },
2702 { REG_TABLE (REG_0F01 ) },
2703 { "larS", { Gv, Ew } },
2704 { "lslS", { Gv, Ew } },
2706 { "syscall", { XX } },
2708 { "sysret%LP", { XX } },
2711 { "wbinvd", { XX } },
2715 { REG_TABLE (REG_0F0D) },
2716 { "femms", { XX } },
2717 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
2719 { PREFIX_TABLE (PREFIX_0F10) },
2720 { PREFIX_TABLE (PREFIX_0F11) },
2721 { PREFIX_TABLE (PREFIX_0F12) },
2722 { MOD_TABLE (MOD_0F13) },
2723 { "unpcklpX", { XM, EXx } },
2724 { "unpckhpX", { XM, EXx } },
2725 { PREFIX_TABLE (PREFIX_0F16) },
2726 { MOD_TABLE (MOD_0F17) },
2728 { REG_TABLE (REG_0F18) },
2730 { PREFIX_TABLE (PREFIX_0F1A) },
2731 { PREFIX_TABLE (PREFIX_0F1B) },
2737 { "movZ", { Rm, Cm } },
2738 { "movZ", { Rm, Dm } },
2739 { "movZ", { Cm, Rm } },
2740 { "movZ", { Dm, Rm } },
2741 { MOD_TABLE (MOD_0F24) },
2743 { MOD_TABLE (MOD_0F26) },
2746 { "movapX", { XM, EXx } },
2747 { "movapX", { EXxS, XM } },
2748 { PREFIX_TABLE (PREFIX_0F2A) },
2749 { PREFIX_TABLE (PREFIX_0F2B) },
2750 { PREFIX_TABLE (PREFIX_0F2C) },
2751 { PREFIX_TABLE (PREFIX_0F2D) },
2752 { PREFIX_TABLE (PREFIX_0F2E) },
2753 { PREFIX_TABLE (PREFIX_0F2F) },
2755 { "wrmsr", { XX } },
2756 { "rdtsc", { XX } },
2757 { "rdmsr", { XX } },
2758 { "rdpmc", { XX } },
2759 { "sysenter", { XX } },
2760 { "sysexit", { XX } },
2762 { "getsec", { XX } },
2764 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2766 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2773 { "cmovoS", { Gv, Ev } },
2774 { "cmovnoS", { Gv, Ev } },
2775 { "cmovbS", { Gv, Ev } },
2776 { "cmovaeS", { Gv, Ev } },
2777 { "cmoveS", { Gv, Ev } },
2778 { "cmovneS", { Gv, Ev } },
2779 { "cmovbeS", { Gv, Ev } },
2780 { "cmovaS", { Gv, Ev } },
2782 { "cmovsS", { Gv, Ev } },
2783 { "cmovnsS", { Gv, Ev } },
2784 { "cmovpS", { Gv, Ev } },
2785 { "cmovnpS", { Gv, Ev } },
2786 { "cmovlS", { Gv, Ev } },
2787 { "cmovgeS", { Gv, Ev } },
2788 { "cmovleS", { Gv, Ev } },
2789 { "cmovgS", { Gv, Ev } },
2791 { MOD_TABLE (MOD_0F51) },
2792 { PREFIX_TABLE (PREFIX_0F51) },
2793 { PREFIX_TABLE (PREFIX_0F52) },
2794 { PREFIX_TABLE (PREFIX_0F53) },
2795 { "andpX", { XM, EXx } },
2796 { "andnpX", { XM, EXx } },
2797 { "orpX", { XM, EXx } },
2798 { "xorpX", { XM, EXx } },
2800 { PREFIX_TABLE (PREFIX_0F58) },
2801 { PREFIX_TABLE (PREFIX_0F59) },
2802 { PREFIX_TABLE (PREFIX_0F5A) },
2803 { PREFIX_TABLE (PREFIX_0F5B) },
2804 { PREFIX_TABLE (PREFIX_0F5C) },
2805 { PREFIX_TABLE (PREFIX_0F5D) },
2806 { PREFIX_TABLE (PREFIX_0F5E) },
2807 { PREFIX_TABLE (PREFIX_0F5F) },
2809 { PREFIX_TABLE (PREFIX_0F60) },
2810 { PREFIX_TABLE (PREFIX_0F61) },
2811 { PREFIX_TABLE (PREFIX_0F62) },
2812 { "packsswb", { MX, EM } },
2813 { "pcmpgtb", { MX, EM } },
2814 { "pcmpgtw", { MX, EM } },
2815 { "pcmpgtd", { MX, EM } },
2816 { "packuswb", { MX, EM } },
2818 { "punpckhbw", { MX, EM } },
2819 { "punpckhwd", { MX, EM } },
2820 { "punpckhdq", { MX, EM } },
2821 { "packssdw", { MX, EM } },
2822 { PREFIX_TABLE (PREFIX_0F6C) },
2823 { PREFIX_TABLE (PREFIX_0F6D) },
2824 { "movK", { MX, Edq } },
2825 { PREFIX_TABLE (PREFIX_0F6F) },
2827 { PREFIX_TABLE (PREFIX_0F70) },
2828 { REG_TABLE (REG_0F71) },
2829 { REG_TABLE (REG_0F72) },
2830 { REG_TABLE (REG_0F73) },
2831 { "pcmpeqb", { MX, EM } },
2832 { "pcmpeqw", { MX, EM } },
2833 { "pcmpeqd", { MX, EM } },
2836 { PREFIX_TABLE (PREFIX_0F78) },
2837 { PREFIX_TABLE (PREFIX_0F79) },
2838 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2840 { PREFIX_TABLE (PREFIX_0F7C) },
2841 { PREFIX_TABLE (PREFIX_0F7D) },
2842 { PREFIX_TABLE (PREFIX_0F7E) },
2843 { PREFIX_TABLE (PREFIX_0F7F) },
2845 { "joH", { Jv, BND, cond_jump_flag } },
2846 { "jnoH", { Jv, BND, cond_jump_flag } },
2847 { "jbH", { Jv, BND, cond_jump_flag } },
2848 { "jaeH", { Jv, BND, cond_jump_flag } },
2849 { "jeH", { Jv, BND, cond_jump_flag } },
2850 { "jneH", { Jv, BND, cond_jump_flag } },
2851 { "jbeH", { Jv, BND, cond_jump_flag } },
2852 { "jaH", { Jv, BND, cond_jump_flag } },
2854 { "jsH", { Jv, BND, cond_jump_flag } },
2855 { "jnsH", { Jv, BND, cond_jump_flag } },
2856 { "jpH", { Jv, BND, cond_jump_flag } },
2857 { "jnpH", { Jv, BND, cond_jump_flag } },
2858 { "jlH", { Jv, BND, cond_jump_flag } },
2859 { "jgeH", { Jv, BND, cond_jump_flag } },
2860 { "jleH", { Jv, BND, cond_jump_flag } },
2861 { "jgH", { Jv, BND, cond_jump_flag } },
2864 { "setno", { Eb } },
2866 { "setae", { Eb } },
2868 { "setne", { Eb } },
2869 { "setbe", { Eb } },
2873 { "setns", { Eb } },
2875 { "setnp", { Eb } },
2877 { "setge", { Eb } },
2878 { "setle", { Eb } },
2881 { "pushT", { fs } },
2883 { "cpuid", { XX } },
2884 { "btS", { Ev, Gv } },
2885 { "shldS", { Ev, Gv, Ib } },
2886 { "shldS", { Ev, Gv, CL } },
2887 { REG_TABLE (REG_0FA6) },
2888 { REG_TABLE (REG_0FA7) },
2890 { "pushT", { gs } },
2893 { "btsS", { Evh1, Gv } },
2894 { "shrdS", { Ev, Gv, Ib } },
2895 { "shrdS", { Ev, Gv, CL } },
2896 { REG_TABLE (REG_0FAE) },
2897 { "imulS", { Gv, Ev } },
2899 { "cmpxchgB", { Ebh1, Gb } },
2900 { "cmpxchgS", { Evh1, Gv } },
2901 { MOD_TABLE (MOD_0FB2) },
2902 { "btrS", { Evh1, Gv } },
2903 { MOD_TABLE (MOD_0FB4) },
2904 { MOD_TABLE (MOD_0FB5) },
2905 { "movz{bR|x}", { Gv, Eb } },
2906 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
2908 { PREFIX_TABLE (PREFIX_0FB8) },
2910 { REG_TABLE (REG_0FBA) },
2911 { "btcS", { Evh1, Gv } },
2912 { PREFIX_TABLE (PREFIX_0FBC) },
2913 { PREFIX_TABLE (PREFIX_0FBD) },
2914 { "movs{bR|x}", { Gv, Eb } },
2915 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
2917 { "xaddB", { Ebh1, Gb } },
2918 { "xaddS", { Evh1, Gv } },
2919 { PREFIX_TABLE (PREFIX_0FC2) },
2920 { PREFIX_TABLE (PREFIX_0FC3) },
2921 { "pinsrw", { MX, Edqw, Ib } },
2922 { "pextrw", { Gdq, MS, Ib } },
2923 { "shufpX", { XM, EXx, Ib } },
2924 { REG_TABLE (REG_0FC7) },
2926 { "bswap", { RMeAX } },
2927 { "bswap", { RMeCX } },
2928 { "bswap", { RMeDX } },
2929 { "bswap", { RMeBX } },
2930 { "bswap", { RMeSP } },
2931 { "bswap", { RMeBP } },
2932 { "bswap", { RMeSI } },
2933 { "bswap", { RMeDI } },
2935 { PREFIX_TABLE (PREFIX_0FD0) },
2936 { "psrlw", { MX, EM } },
2937 { "psrld", { MX, EM } },
2938 { "psrlq", { MX, EM } },
2939 { "paddq", { MX, EM } },
2940 { "pmullw", { MX, EM } },
2941 { PREFIX_TABLE (PREFIX_0FD6) },
2942 { MOD_TABLE (MOD_0FD7) },
2944 { "psubusb", { MX, EM } },
2945 { "psubusw", { MX, EM } },
2946 { "pminub", { MX, EM } },
2947 { "pand", { MX, EM } },
2948 { "paddusb", { MX, EM } },
2949 { "paddusw", { MX, EM } },
2950 { "pmaxub", { MX, EM } },
2951 { "pandn", { MX, EM } },
2953 { "pavgb", { MX, EM } },
2954 { "psraw", { MX, EM } },
2955 { "psrad", { MX, EM } },
2956 { "pavgw", { MX, EM } },
2957 { "pmulhuw", { MX, EM } },
2958 { "pmulhw", { MX, EM } },
2959 { PREFIX_TABLE (PREFIX_0FE6) },
2960 { PREFIX_TABLE (PREFIX_0FE7) },
2962 { "psubsb", { MX, EM } },
2963 { "psubsw", { MX, EM } },
2964 { "pminsw", { MX, EM } },
2965 { "por", { MX, EM } },
2966 { "paddsb", { MX, EM } },
2967 { "paddsw", { MX, EM } },
2968 { "pmaxsw", { MX, EM } },
2969 { "pxor", { MX, EM } },
2971 { PREFIX_TABLE (PREFIX_0FF0) },
2972 { "psllw", { MX, EM } },
2973 { "pslld", { MX, EM } },
2974 { "psllq", { MX, EM } },
2975 { "pmuludq", { MX, EM } },
2976 { "pmaddwd", { MX, EM } },
2977 { "psadbw", { MX, EM } },
2978 { PREFIX_TABLE (PREFIX_0FF7) },
2980 { "psubb", { MX, EM } },
2981 { "psubw", { MX, EM } },
2982 { "psubd", { MX, EM } },
2983 { "psubq", { MX, EM } },
2984 { "paddb", { MX, EM } },
2985 { "paddw", { MX, EM } },
2986 { "paddd", { MX, EM } },
2990 static const unsigned char onebyte_has_modrm[256] = {
2991 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2992 /* ------------------------------- */
2993 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2994 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2995 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2996 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2997 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2998 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2999 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3000 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3001 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3002 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3003 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3004 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3005 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3006 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3007 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3008 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3009 /* ------------------------------- */
3010 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3013 static const unsigned char twobyte_has_modrm[256] = {
3014 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3015 /* ------------------------------- */
3016 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3017 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3018 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3019 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3020 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3021 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3022 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3023 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3024 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3025 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3026 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3027 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3028 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3029 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3030 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3031 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3032 /* ------------------------------- */
3033 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3036 static const unsigned char twobyte_has_mandatory_prefix[256] = {
3037 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3038 /* ------------------------------- */
3039 /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
3040 /* 10 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 1f */
3041 /* 20 */ 0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0, /* 2f */
3042 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3043 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
3044 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3045 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3046 /* 70 */ 1,0,0,0,1,1,1,1,0,0,1,1,1,1,1,1, /* 7f */
3047 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3048 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
3049 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
3050 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
3051 /* c0 */ 0,0,1,1,1,1,1,0,0,0,0,0,0,0,0,0, /* cf */
3052 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3053 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3054 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3055 /* ------------------------------- */
3056 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3059 static char obuf[100];
3061 static char *mnemonicendp;
3062 static char scratchbuf[100];
3063 static unsigned char *start_codep;
3064 static unsigned char *insn_codep;
3065 static unsigned char *codep;
3066 static unsigned char *end_codep;
3067 static int last_lock_prefix;
3068 static int last_repz_prefix;
3069 static int last_repnz_prefix;
3070 static int last_data_prefix;
3071 static int last_addr_prefix;
3072 static int last_rex_prefix;
3073 static int last_seg_prefix;
3074 static int fwait_prefix;
3075 /* The PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is mandatory. */
3076 static int mandatory_prefix;
3077 /* The active segment register prefix. */
3078 static int active_seg_prefix;
3079 #define MAX_CODE_LENGTH 15
3080 /* We can up to 14 prefixes since the maximum instruction length is
3082 static int all_prefixes[MAX_CODE_LENGTH - 1];
3083 static disassemble_info *the_info;
3091 static unsigned char need_modrm;
3101 int register_specifier;
3108 int mask_register_specifier;
3114 static unsigned char need_vex;
3115 static unsigned char need_vex_reg;
3116 static unsigned char vex_w_done;
3124 /* If we are accessing mod/rm/reg without need_modrm set, then the
3125 values are stale. Hitting this abort likely indicates that you
3126 need to update onebyte_has_modrm or twobyte_has_modrm. */
3127 #define MODRM_CHECK if (!need_modrm) abort ()
3129 static const char **names64;
3130 static const char **names32;
3131 static const char **names16;
3132 static const char **names8;
3133 static const char **names8rex;
3134 static const char **names_seg;
3135 static const char *index64;
3136 static const char *index32;
3137 static const char **index16;
3138 static const char **names_bnd;
3140 static const char *intel_names64[] = {
3141 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3142 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3144 static const char *intel_names32[] = {
3145 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3146 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3148 static const char *intel_names16[] = {
3149 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3150 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3152 static const char *intel_names8[] = {
3153 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3155 static const char *intel_names8rex[] = {
3156 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3157 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3159 static const char *intel_names_seg[] = {
3160 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3162 static const char *intel_index64 = "riz";
3163 static const char *intel_index32 = "eiz";
3164 static const char *intel_index16[] = {
3165 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3168 static const char *att_names64[] = {
3169 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3170 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3172 static const char *att_names32[] = {
3173 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3174 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3176 static const char *att_names16[] = {
3177 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3178 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3180 static const char *att_names8[] = {
3181 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3183 static const char *att_names8rex[] = {
3184 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3185 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3187 static const char *att_names_seg[] = {
3188 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3190 static const char *att_index64 = "%riz";
3191 static const char *att_index32 = "%eiz";
3192 static const char *att_index16[] = {
3193 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3196 static const char **names_mm;
3197 static const char *intel_names_mm[] = {
3198 "mm0", "mm1", "mm2", "mm3",
3199 "mm4", "mm5", "mm6", "mm7"
3201 static const char *att_names_mm[] = {
3202 "%mm0", "%mm1", "%mm2", "%mm3",
3203 "%mm4", "%mm5", "%mm6", "%mm7"
3206 static const char *intel_names_bnd[] = {
3207 "bnd0", "bnd1", "bnd2", "bnd3"
3210 static const char *att_names_bnd[] = {
3211 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3214 static const char **names_xmm;
3215 static const char *intel_names_xmm[] = {
3216 "xmm0", "xmm1", "xmm2", "xmm3",
3217 "xmm4", "xmm5", "xmm6", "xmm7",
3218 "xmm8", "xmm9", "xmm10", "xmm11",
3219 "xmm12", "xmm13", "xmm14", "xmm15",
3220 "xmm16", "xmm17", "xmm18", "xmm19",
3221 "xmm20", "xmm21", "xmm22", "xmm23",
3222 "xmm24", "xmm25", "xmm26", "xmm27",
3223 "xmm28", "xmm29", "xmm30", "xmm31"
3225 static const char *att_names_xmm[] = {
3226 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3227 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3228 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3229 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3230 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3231 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3232 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3233 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3236 static const char **names_ymm;
3237 static const char *intel_names_ymm[] = {
3238 "ymm0", "ymm1", "ymm2", "ymm3",
3239 "ymm4", "ymm5", "ymm6", "ymm7",
3240 "ymm8", "ymm9", "ymm10", "ymm11",
3241 "ymm12", "ymm13", "ymm14", "ymm15",
3242 "ymm16", "ymm17", "ymm18", "ymm19",
3243 "ymm20", "ymm21", "ymm22", "ymm23",
3244 "ymm24", "ymm25", "ymm26", "ymm27",
3245 "ymm28", "ymm29", "ymm30", "ymm31"
3247 static const char *att_names_ymm[] = {
3248 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3249 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3250 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3251 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3252 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3253 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3254 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3255 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3258 static const char **names_zmm;
3259 static const char *intel_names_zmm[] = {
3260 "zmm0", "zmm1", "zmm2", "zmm3",
3261 "zmm4", "zmm5", "zmm6", "zmm7",
3262 "zmm8", "zmm9", "zmm10", "zmm11",
3263 "zmm12", "zmm13", "zmm14", "zmm15",
3264 "zmm16", "zmm17", "zmm18", "zmm19",
3265 "zmm20", "zmm21", "zmm22", "zmm23",
3266 "zmm24", "zmm25", "zmm26", "zmm27",
3267 "zmm28", "zmm29", "zmm30", "zmm31"
3269 static const char *att_names_zmm[] = {
3270 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3271 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3272 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3273 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3274 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3275 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3276 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3277 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3280 static const char **names_mask;
3281 static const char *intel_names_mask[] = {
3282 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3284 static const char *att_names_mask[] = {
3285 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3288 static const char *names_rounding[] =
3296 static const struct dis386 reg_table[][8] = {
3299 { "addA", { Ebh1, Ib } },
3300 { "orA", { Ebh1, Ib } },
3301 { "adcA", { Ebh1, Ib } },
3302 { "sbbA", { Ebh1, Ib } },
3303 { "andA", { Ebh1, Ib } },
3304 { "subA", { Ebh1, Ib } },
3305 { "xorA", { Ebh1, Ib } },
3306 { "cmpA", { Eb, Ib } },
3310 { "addQ", { Evh1, Iv } },
3311 { "orQ", { Evh1, Iv } },
3312 { "adcQ", { Evh1, Iv } },
3313 { "sbbQ", { Evh1, Iv } },
3314 { "andQ", { Evh1, Iv } },
3315 { "subQ", { Evh1, Iv } },
3316 { "xorQ", { Evh1, Iv } },
3317 { "cmpQ", { Ev, Iv } },
3321 { "addQ", { Evh1, sIb } },
3322 { "orQ", { Evh1, sIb } },
3323 { "adcQ", { Evh1, sIb } },
3324 { "sbbQ", { Evh1, sIb } },
3325 { "andQ", { Evh1, sIb } },
3326 { "subQ", { Evh1, sIb } },
3327 { "xorQ", { Evh1, sIb } },
3328 { "cmpQ", { Ev, sIb } },
3332 { "popU", { stackEv } },
3333 { XOP_8F_TABLE (XOP_09) },
3337 { XOP_8F_TABLE (XOP_09) },
3341 { "rolA", { Eb, Ib } },
3342 { "rorA", { Eb, Ib } },
3343 { "rclA", { Eb, Ib } },
3344 { "rcrA", { Eb, Ib } },
3345 { "shlA", { Eb, Ib } },
3346 { "shrA", { Eb, Ib } },
3348 { "sarA", { Eb, Ib } },
3352 { "rolQ", { Ev, Ib } },
3353 { "rorQ", { Ev, Ib } },
3354 { "rclQ", { Ev, Ib } },
3355 { "rcrQ", { Ev, Ib } },
3356 { "shlQ", { Ev, Ib } },
3357 { "shrQ", { Ev, Ib } },
3359 { "sarQ", { Ev, Ib } },
3363 { "movA", { Ebh3, Ib } },
3370 { MOD_TABLE (MOD_C6_REG_7) },
3374 { "movQ", { Evh3, Iv } },
3381 { MOD_TABLE (MOD_C7_REG_7) },
3385 { "rolA", { Eb, I1 } },
3386 { "rorA", { Eb, I1 } },
3387 { "rclA", { Eb, I1 } },
3388 { "rcrA", { Eb, I1 } },
3389 { "shlA", { Eb, I1 } },
3390 { "shrA", { Eb, I1 } },
3392 { "sarA", { Eb, I1 } },
3396 { "rolQ", { Ev, I1 } },
3397 { "rorQ", { Ev, I1 } },
3398 { "rclQ", { Ev, I1 } },
3399 { "rcrQ", { Ev, I1 } },
3400 { "shlQ", { Ev, I1 } },
3401 { "shrQ", { Ev, I1 } },
3403 { "sarQ", { Ev, I1 } },
3407 { "rolA", { Eb, CL } },
3408 { "rorA", { Eb, CL } },
3409 { "rclA", { Eb, CL } },
3410 { "rcrA", { Eb, CL } },
3411 { "shlA", { Eb, CL } },
3412 { "shrA", { Eb, CL } },
3414 { "sarA", { Eb, CL } },
3418 { "rolQ", { Ev, CL } },
3419 { "rorQ", { Ev, CL } },
3420 { "rclQ", { Ev, CL } },
3421 { "rcrQ", { Ev, CL } },
3422 { "shlQ", { Ev, CL } },
3423 { "shrQ", { Ev, CL } },
3425 { "sarQ", { Ev, CL } },
3429 { "testA", { Eb, Ib } },
3431 { "notA", { Ebh1 } },
3432 { "negA", { Ebh1 } },
3433 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
3434 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
3435 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
3436 { "idivA", { Eb } }, /* and idiv for consistency. */
3440 { "testQ", { Ev, Iv } },
3442 { "notQ", { Evh1 } },
3443 { "negQ", { Evh1 } },
3444 { "mulQ", { Ev } }, /* Don't print the implicit register. */
3445 { "imulQ", { Ev } },
3447 { "idivQ", { Ev } },
3451 { "incA", { Ebh1 } },
3452 { "decA", { Ebh1 } },
3456 { "incQ", { Evh1 } },
3457 { "decQ", { Evh1 } },
3458 { "call{T|}", { indirEv, BND } },
3459 { MOD_TABLE (MOD_FF_REG_3) },
3460 { "jmp{T|}", { indirEv, BND } },
3461 { MOD_TABLE (MOD_FF_REG_5) },
3462 { "pushU", { stackEv } },
3467 { "sldtD", { Sv } },
3478 { MOD_TABLE (MOD_0F01_REG_0) },
3479 { MOD_TABLE (MOD_0F01_REG_1) },
3480 { MOD_TABLE (MOD_0F01_REG_2) },
3481 { MOD_TABLE (MOD_0F01_REG_3) },
3482 { "smswD", { Sv } },
3485 { MOD_TABLE (MOD_0F01_REG_7) },
3489 { "prefetch", { Mb } },
3490 { "prefetchw", { Mb } },
3491 { "prefetchwt1", { Mb } },
3492 { "prefetch", { Mb } },
3493 { "prefetch", { Mb } },
3494 { "prefetch", { Mb } },
3495 { "prefetch", { Mb } },
3496 { "prefetch", { Mb } },
3500 { MOD_TABLE (MOD_0F18_REG_0) },
3501 { MOD_TABLE (MOD_0F18_REG_1) },
3502 { MOD_TABLE (MOD_0F18_REG_2) },
3503 { MOD_TABLE (MOD_0F18_REG_3) },
3504 { MOD_TABLE (MOD_0F18_REG_4) },
3505 { MOD_TABLE (MOD_0F18_REG_5) },
3506 { MOD_TABLE (MOD_0F18_REG_6) },
3507 { MOD_TABLE (MOD_0F18_REG_7) },
3513 { MOD_TABLE (MOD_0F71_REG_2) },
3515 { MOD_TABLE (MOD_0F71_REG_4) },
3517 { MOD_TABLE (MOD_0F71_REG_6) },
3523 { MOD_TABLE (MOD_0F72_REG_2) },
3525 { MOD_TABLE (MOD_0F72_REG_4) },
3527 { MOD_TABLE (MOD_0F72_REG_6) },
3533 { MOD_TABLE (MOD_0F73_REG_2) },
3534 { MOD_TABLE (MOD_0F73_REG_3) },
3537 { MOD_TABLE (MOD_0F73_REG_6) },
3538 { MOD_TABLE (MOD_0F73_REG_7) },
3542 { "montmul", { { OP_0f07, 0 } } },
3543 { "xsha1", { { OP_0f07, 0 } } },
3544 { "xsha256", { { OP_0f07, 0 } } },
3548 { "xstore-rng", { { OP_0f07, 0 } } },
3549 { "xcrypt-ecb", { { OP_0f07, 0 } } },
3550 { "xcrypt-cbc", { { OP_0f07, 0 } } },
3551 { "xcrypt-ctr", { { OP_0f07, 0 } } },
3552 { "xcrypt-cfb", { { OP_0f07, 0 } } },
3553 { "xcrypt-ofb", { { OP_0f07, 0 } } },
3557 { MOD_TABLE (MOD_0FAE_REG_0) },
3558 { MOD_TABLE (MOD_0FAE_REG_1) },
3559 { MOD_TABLE (MOD_0FAE_REG_2) },
3560 { MOD_TABLE (MOD_0FAE_REG_3) },
3561 { MOD_TABLE (MOD_0FAE_REG_4) },
3562 { MOD_TABLE (MOD_0FAE_REG_5) },
3563 { MOD_TABLE (MOD_0FAE_REG_6) },
3564 { MOD_TABLE (MOD_0FAE_REG_7) },
3572 { "btQ", { Ev, Ib } },
3573 { "btsQ", { Evh1, Ib } },
3574 { "btrQ", { Evh1, Ib } },
3575 { "btcQ", { Evh1, Ib } },
3580 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
3582 { MOD_TABLE (MOD_0FC7_REG_3) },
3583 { MOD_TABLE (MOD_0FC7_REG_4) },
3584 { MOD_TABLE (MOD_0FC7_REG_5) },
3585 { MOD_TABLE (MOD_0FC7_REG_6) },
3586 { MOD_TABLE (MOD_0FC7_REG_7) },
3592 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3594 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3596 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3602 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3604 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3606 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3612 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3613 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3616 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3617 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3623 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3624 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3626 /* REG_VEX_0F38F3 */
3629 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3630 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3631 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3635 { "llwpcb", { { OP_LWPCB_E, 0 } } },
3636 { "slwpcb", { { OP_LWPCB_E, 0 } } },
3640 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
3641 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
3643 /* REG_XOP_TBM_01 */
3646 { "blcfill", { { OP_LWP_E, 0 }, Ev } },
3647 { "blsfill", { { OP_LWP_E, 0 }, Ev } },
3648 { "blcs", { { OP_LWP_E, 0 }, Ev } },
3649 { "tzmsk", { { OP_LWP_E, 0 }, Ev } },
3650 { "blcic", { { OP_LWP_E, 0 }, Ev } },
3651 { "blsic", { { OP_LWP_E, 0 }, Ev } },
3652 { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
3654 /* REG_XOP_TBM_02 */
3657 { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
3662 { "blci", { { OP_LWP_E, 0 }, Ev } },
3664 #define NEED_REG_TABLE
3665 #include "i386-dis-evex.h"
3666 #undef NEED_REG_TABLE
3669 static const struct dis386 prefix_table[][4] = {
3672 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3673 { "pause", { XX } },
3674 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3679 { "movups", { XM, EXx } },
3680 { "movss", { XM, EXd } },
3681 { "movupd", { XM, EXx } },
3682 { "movsd", { XM, EXq } },
3687 { "movups", { EXxS, XM } },
3688 { "movss", { EXdS, XM } },
3689 { "movupd", { EXxS, XM } },
3690 { "movsd", { EXqS, XM } },
3695 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3696 { "movsldup", { XM, EXx } },
3697 { "movlpd", { XM, EXq } },
3698 { "movddup", { XM, EXq } },
3703 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3704 { "movshdup", { XM, EXx } },
3705 { "movhpd", { XM, EXq } },
3710 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3711 { "bndcl", { Gbnd, Ev_bnd } },
3712 { "bndmov", { Gbnd, Ebnd } },
3713 { "bndcu", { Gbnd, Ev_bnd } },
3718 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3719 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3720 { "bndmov", { Ebnd, Gbnd } },
3721 { "bndcn", { Gbnd, Ev_bnd } },
3726 { "cvtpi2ps", { XM, EMCq } },
3727 { "cvtsi2ss%LQ", { XM, Ev } },
3728 { "cvtpi2pd", { XM, EMCq } },
3729 { "cvtsi2sd%LQ", { XM, Ev } },
3734 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3735 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3736 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3737 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3742 { "cvttps2pi", { MXC, EXq } },
3743 { "cvttss2siY", { Gv, EXd } },
3744 { "cvttpd2pi", { MXC, EXx } },
3745 { "cvttsd2siY", { Gv, EXq } },
3750 { "cvtps2pi", { MXC, EXq } },
3751 { "cvtss2siY", { Gv, EXd } },
3752 { "cvtpd2pi", { MXC, EXx } },
3753 { "cvtsd2siY", { Gv, EXq } },
3758 { "ucomiss",{ XM, EXd } },
3760 { "ucomisd",{ XM, EXq } },
3765 { "comiss", { XM, EXd } },
3767 { "comisd", { XM, EXq } },
3772 { "sqrtps", { XM, EXx } },
3773 { "sqrtss", { XM, EXd } },
3774 { "sqrtpd", { XM, EXx } },
3775 { "sqrtsd", { XM, EXq } },
3780 { "rsqrtps",{ XM, EXx } },
3781 { "rsqrtss",{ XM, EXd } },
3786 { "rcpps", { XM, EXx } },
3787 { "rcpss", { XM, EXd } },
3792 { "addps", { XM, EXx } },
3793 { "addss", { XM, EXd } },
3794 { "addpd", { XM, EXx } },
3795 { "addsd", { XM, EXq } },
3800 { "mulps", { XM, EXx } },
3801 { "mulss", { XM, EXd } },
3802 { "mulpd", { XM, EXx } },
3803 { "mulsd", { XM, EXq } },
3808 { "cvtps2pd", { XM, EXq } },
3809 { "cvtss2sd", { XM, EXd } },
3810 { "cvtpd2ps", { XM, EXx } },
3811 { "cvtsd2ss", { XM, EXq } },
3816 { "cvtdq2ps", { XM, EXx } },
3817 { "cvttps2dq", { XM, EXx } },
3818 { "cvtps2dq", { XM, EXx } },
3823 { "subps", { XM, EXx } },
3824 { "subss", { XM, EXd } },
3825 { "subpd", { XM, EXx } },
3826 { "subsd", { XM, EXq } },
3831 { "minps", { XM, EXx } },
3832 { "minss", { XM, EXd } },
3833 { "minpd", { XM, EXx } },
3834 { "minsd", { XM, EXq } },
3839 { "divps", { XM, EXx } },
3840 { "divss", { XM, EXd } },
3841 { "divpd", { XM, EXx } },
3842 { "divsd", { XM, EXq } },
3847 { "maxps", { XM, EXx } },
3848 { "maxss", { XM, EXd } },
3849 { "maxpd", { XM, EXx } },
3850 { "maxsd", { XM, EXq } },
3855 { "punpcklbw",{ MX, EMd } },
3857 { "punpcklbw",{ MX, EMx } },
3862 { "punpcklwd",{ MX, EMd } },
3864 { "punpcklwd",{ MX, EMx } },
3869 { "punpckldq",{ MX, EMd } },
3871 { "punpckldq",{ MX, EMx } },
3878 { "punpcklqdq", { XM, EXx } },
3885 { "punpckhqdq", { XM, EXx } },
3890 { "movq", { MX, EM } },
3891 { "movdqu", { XM, EXx } },
3892 { "movdqa", { XM, EXx } },
3897 { "pshufw", { MX, EM, Ib } },
3898 { "pshufhw",{ XM, EXx, Ib } },
3899 { "pshufd", { XM, EXx, Ib } },
3900 { "pshuflw",{ XM, EXx, Ib } },
3903 /* PREFIX_0F73_REG_3 */
3907 { "psrldq", { XS, Ib } },
3910 /* PREFIX_0F73_REG_7 */
3914 { "pslldq", { XS, Ib } },
3919 {"vmread", { Em, Gm } },
3921 {"extrq", { XS, Ib, Ib } },
3922 {"insertq", { XM, XS, Ib, Ib } },
3927 {"vmwrite", { Gm, Em } },
3929 {"extrq", { XM, XS } },
3930 {"insertq", { XM, XS } },
3937 { "haddpd", { XM, EXx } },
3938 { "haddps", { XM, EXx } },
3945 { "hsubpd", { XM, EXx } },
3946 { "hsubps", { XM, EXx } },
3951 { "movK", { Edq, MX } },
3952 { "movq", { XM, EXq } },
3953 { "movK", { Edq, XM } },
3958 { "movq", { EMS, MX } },
3959 { "movdqu", { EXxS, XM } },
3960 { "movdqa", { EXxS, XM } },
3963 /* PREFIX_0FAE_REG_0 */
3966 { "rdfsbase", { Ev } },
3969 /* PREFIX_0FAE_REG_1 */
3972 { "rdgsbase", { Ev } },
3975 /* PREFIX_0FAE_REG_2 */
3978 { "wrfsbase", { Ev } },
3981 /* PREFIX_0FAE_REG_3 */
3984 { "wrgsbase", { Ev } },
3987 /* PREFIX_0FAE_REG_6 */
3989 { "xsaveopt", { FXSAVE } },
3994 /* PREFIX_0FAE_REG_7 */
3996 { "clflush", { Mb } },
3998 { "clflushopt", { Mb } },
4001 /* PREFIX_RM_0_0FAE_REG_7 */
4003 { "sfence", { Skip_MODRM } },
4005 { "pcommit", { Skip_MODRM } },
4011 { "popcntS", { Gv, Ev } },
4016 { "bsfS", { Gv, Ev } },
4017 { "tzcntS", { Gv, Ev } },
4018 { "bsfS", { Gv, Ev } },
4023 { "bsrS", { Gv, Ev } },
4024 { "lzcntS", { Gv, Ev } },
4025 { "bsrS", { Gv, Ev } },
4030 { "cmpps", { XM, EXx, CMP } },
4031 { "cmpss", { XM, EXd, CMP } },
4032 { "cmppd", { XM, EXx, CMP } },
4033 { "cmpsd", { XM, EXq, CMP } },
4038 { "movntiS", { Ma, Gv } },
4041 /* PREFIX_0FC7_REG_6 */
4043 { "vmptrld",{ Mq } },
4044 { "vmxon", { Mq } },
4045 { "vmclear",{ Mq } },
4052 { "addsubpd", { XM, EXx } },
4053 { "addsubps", { XM, EXx } },
4059 { "movq2dq",{ XM, MS } },
4060 { "movq", { EXqS, XM } },
4061 { "movdq2q",{ MX, XS } },
4067 { "cvtdq2pd", { XM, EXq } },
4068 { "cvttpd2dq", { XM, EXx } },
4069 { "cvtpd2dq", { XM, EXx } },
4074 { "movntq", { Mq, MX } },
4076 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4084 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4089 { "maskmovq", { MX, MS } },
4091 { "maskmovdqu", { XM, XS } },
4098 { "pblendvb", { XM, EXx, XMM0 } },
4105 { "blendvps", { XM, EXx, XMM0 } },
4112 { "blendvpd", { XM, EXx, XMM0 } },
4119 { "ptest", { XM, EXx } },
4126 { "pmovsxbw", { XM, EXq } },
4133 { "pmovsxbd", { XM, EXd } },
4140 { "pmovsxbq", { XM, EXw } },
4147 { "pmovsxwd", { XM, EXq } },
4154 { "pmovsxwq", { XM, EXd } },
4161 { "pmovsxdq", { XM, EXq } },
4168 { "pmuldq", { XM, EXx } },
4175 { "pcmpeqq", { XM, EXx } },
4182 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4189 { "packusdw", { XM, EXx } },
4196 { "pmovzxbw", { XM, EXq } },
4203 { "pmovzxbd", { XM, EXd } },
4210 { "pmovzxbq", { XM, EXw } },
4217 { "pmovzxwd", { XM, EXq } },
4224 { "pmovzxwq", { XM, EXd } },
4231 { "pmovzxdq", { XM, EXq } },
4238 { "pcmpgtq", { XM, EXx } },
4245 { "pminsb", { XM, EXx } },
4252 { "pminsd", { XM, EXx } },
4259 { "pminuw", { XM, EXx } },
4266 { "pminud", { XM, EXx } },
4273 { "pmaxsb", { XM, EXx } },
4280 { "pmaxsd", { XM, EXx } },
4287 { "pmaxuw", { XM, EXx } },
4294 { "pmaxud", { XM, EXx } },
4301 { "pmulld", { XM, EXx } },
4308 { "phminposuw", { XM, EXx } },
4315 { "invept", { Gm, Mo } },
4322 { "invvpid", { Gm, Mo } },
4329 { "invpcid", { Gm, M } },
4334 { "sha1nexte", { XM, EXxmm } },
4339 { "sha1msg1", { XM, EXxmm } },
4344 { "sha1msg2", { XM, EXxmm } },
4349 { "sha256rnds2", { XM, EXxmm, XMM0 } },
4354 { "sha256msg1", { XM, EXxmm } },
4359 { "sha256msg2", { XM, EXxmm } },
4366 { "aesimc", { XM, EXx } },
4373 { "aesenc", { XM, EXx } },
4380 { "aesenclast", { XM, EXx } },
4387 { "aesdec", { XM, EXx } },
4394 { "aesdeclast", { XM, EXx } },
4399 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4401 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4402 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
4407 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4409 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4410 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
4416 { "adoxS", { Gdq, Edq} },
4417 { "adcxS", { Gdq, Edq} },
4425 { "roundps", { XM, EXx, Ib } },
4432 { "roundpd", { XM, EXx, Ib } },
4439 { "roundss", { XM, EXd, Ib } },
4446 { "roundsd", { XM, EXq, Ib } },
4453 { "blendps", { XM, EXx, Ib } },
4460 { "blendpd", { XM, EXx, Ib } },
4467 { "pblendw", { XM, EXx, Ib } },
4474 { "pextrb", { Edqb, XM, Ib } },
4481 { "pextrw", { Edqw, XM, Ib } },
4488 { "pextrK", { Edq, XM, Ib } },
4495 { "extractps", { Edqd, XM, Ib } },
4502 { "pinsrb", { XM, Edqb, Ib } },
4509 { "insertps", { XM, EXd, Ib } },
4516 { "pinsrK", { XM, Edq, Ib } },
4523 { "dpps", { XM, EXx, Ib } },
4530 { "dppd", { XM, EXx, Ib } },
4537 { "mpsadbw", { XM, EXx, Ib } },
4544 { "pclmulqdq", { XM, EXx, PCLMUL } },
4551 { "pcmpestrm", { XM, EXx, Ib } },
4558 { "pcmpestri", { XM, EXx, Ib } },
4565 { "pcmpistrm", { XM, EXx, Ib } },
4572 { "pcmpistri", { XM, EXx, Ib } },
4577 { "sha1rnds4", { XM, EXxmm, Ib } },
4584 { "aeskeygenassist", { XM, EXx, Ib } },
4587 /* PREFIX_VEX_0F10 */
4589 { VEX_W_TABLE (VEX_W_0F10_P_0) },
4590 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4591 { VEX_W_TABLE (VEX_W_0F10_P_2) },
4592 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4595 /* PREFIX_VEX_0F11 */
4597 { VEX_W_TABLE (VEX_W_0F11_P_0) },
4598 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4599 { VEX_W_TABLE (VEX_W_0F11_P_2) },
4600 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4603 /* PREFIX_VEX_0F12 */
4605 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4606 { VEX_W_TABLE (VEX_W_0F12_P_1) },
4607 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4608 { VEX_W_TABLE (VEX_W_0F12_P_3) },
4611 /* PREFIX_VEX_0F16 */
4613 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4614 { VEX_W_TABLE (VEX_W_0F16_P_1) },
4615 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4618 /* PREFIX_VEX_0F2A */
4621 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4623 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4626 /* PREFIX_VEX_0F2C */
4629 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4631 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4634 /* PREFIX_VEX_0F2D */
4637 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4639 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4642 /* PREFIX_VEX_0F2E */
4644 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4646 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4649 /* PREFIX_VEX_0F2F */
4651 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4653 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4656 /* PREFIX_VEX_0F41 */
4658 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4660 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4663 /* PREFIX_VEX_0F42 */
4665 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4667 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4670 /* PREFIX_VEX_0F44 */
4672 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4674 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4677 /* PREFIX_VEX_0F45 */
4679 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4681 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4684 /* PREFIX_VEX_0F46 */
4686 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4688 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4691 /* PREFIX_VEX_0F47 */
4693 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4695 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4698 /* PREFIX_VEX_0F4A */
4700 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4702 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4705 /* PREFIX_VEX_0F4B */
4707 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4709 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4712 /* PREFIX_VEX_0F51 */
4714 { VEX_W_TABLE (VEX_W_0F51_P_0) },
4715 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4716 { VEX_W_TABLE (VEX_W_0F51_P_2) },
4717 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4720 /* PREFIX_VEX_0F52 */
4722 { VEX_W_TABLE (VEX_W_0F52_P_0) },
4723 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4726 /* PREFIX_VEX_0F53 */
4728 { VEX_W_TABLE (VEX_W_0F53_P_0) },
4729 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4732 /* PREFIX_VEX_0F58 */
4734 { VEX_W_TABLE (VEX_W_0F58_P_0) },
4735 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4736 { VEX_W_TABLE (VEX_W_0F58_P_2) },
4737 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4740 /* PREFIX_VEX_0F59 */
4742 { VEX_W_TABLE (VEX_W_0F59_P_0) },
4743 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4744 { VEX_W_TABLE (VEX_W_0F59_P_2) },
4745 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4748 /* PREFIX_VEX_0F5A */
4750 { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4751 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4752 { "vcvtpd2ps%XY", { XMM, EXx } },
4753 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4756 /* PREFIX_VEX_0F5B */
4758 { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4759 { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4760 { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4763 /* PREFIX_VEX_0F5C */
4765 { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4766 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4767 { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4768 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4771 /* PREFIX_VEX_0F5D */
4773 { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4774 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4775 { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4776 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4779 /* PREFIX_VEX_0F5E */
4781 { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4782 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4783 { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4784 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4787 /* PREFIX_VEX_0F5F */
4789 { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4790 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4791 { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4792 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4795 /* PREFIX_VEX_0F60 */
4799 { VEX_W_TABLE (VEX_W_0F60_P_2) },
4802 /* PREFIX_VEX_0F61 */
4806 { VEX_W_TABLE (VEX_W_0F61_P_2) },
4809 /* PREFIX_VEX_0F62 */
4813 { VEX_W_TABLE (VEX_W_0F62_P_2) },
4816 /* PREFIX_VEX_0F63 */
4820 { VEX_W_TABLE (VEX_W_0F63_P_2) },
4823 /* PREFIX_VEX_0F64 */
4827 { VEX_W_TABLE (VEX_W_0F64_P_2) },
4830 /* PREFIX_VEX_0F65 */
4834 { VEX_W_TABLE (VEX_W_0F65_P_2) },
4837 /* PREFIX_VEX_0F66 */
4841 { VEX_W_TABLE (VEX_W_0F66_P_2) },
4844 /* PREFIX_VEX_0F67 */
4848 { VEX_W_TABLE (VEX_W_0F67_P_2) },
4851 /* PREFIX_VEX_0F68 */
4855 { VEX_W_TABLE (VEX_W_0F68_P_2) },
4858 /* PREFIX_VEX_0F69 */
4862 { VEX_W_TABLE (VEX_W_0F69_P_2) },
4865 /* PREFIX_VEX_0F6A */
4869 { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4872 /* PREFIX_VEX_0F6B */
4876 { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4879 /* PREFIX_VEX_0F6C */
4883 { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4886 /* PREFIX_VEX_0F6D */
4890 { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4893 /* PREFIX_VEX_0F6E */
4897 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4900 /* PREFIX_VEX_0F6F */
4903 { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4904 { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4907 /* PREFIX_VEX_0F70 */
4910 { VEX_W_TABLE (VEX_W_0F70_P_1) },
4911 { VEX_W_TABLE (VEX_W_0F70_P_2) },
4912 { VEX_W_TABLE (VEX_W_0F70_P_3) },
4915 /* PREFIX_VEX_0F71_REG_2 */
4919 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4922 /* PREFIX_VEX_0F71_REG_4 */
4926 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4929 /* PREFIX_VEX_0F71_REG_6 */
4933 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4936 /* PREFIX_VEX_0F72_REG_2 */
4940 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4943 /* PREFIX_VEX_0F72_REG_4 */
4947 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4950 /* PREFIX_VEX_0F72_REG_6 */
4954 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4957 /* PREFIX_VEX_0F73_REG_2 */
4961 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4964 /* PREFIX_VEX_0F73_REG_3 */
4968 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4971 /* PREFIX_VEX_0F73_REG_6 */
4975 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4978 /* PREFIX_VEX_0F73_REG_7 */
4982 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4985 /* PREFIX_VEX_0F74 */
4989 { VEX_W_TABLE (VEX_W_0F74_P_2) },
4992 /* PREFIX_VEX_0F75 */
4996 { VEX_W_TABLE (VEX_W_0F75_P_2) },
4999 /* PREFIX_VEX_0F76 */
5003 { VEX_W_TABLE (VEX_W_0F76_P_2) },
5006 /* PREFIX_VEX_0F77 */
5008 { VEX_W_TABLE (VEX_W_0F77_P_0) },
5011 /* PREFIX_VEX_0F7C */
5015 { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5016 { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5019 /* PREFIX_VEX_0F7D */
5023 { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5024 { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5027 /* PREFIX_VEX_0F7E */
5030 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5031 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5034 /* PREFIX_VEX_0F7F */
5037 { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5038 { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5041 /* PREFIX_VEX_0F90 */
5043 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5045 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5048 /* PREFIX_VEX_0F91 */
5050 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5052 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5055 /* PREFIX_VEX_0F92 */
5057 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5059 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5060 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5063 /* PREFIX_VEX_0F93 */
5065 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5067 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5068 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5071 /* PREFIX_VEX_0F98 */
5073 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5075 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5078 /* PREFIX_VEX_0F99 */
5080 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5082 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5085 /* PREFIX_VEX_0FC2 */
5087 { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5088 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5089 { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5090 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5093 /* PREFIX_VEX_0FC4 */
5097 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5100 /* PREFIX_VEX_0FC5 */
5104 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5107 /* PREFIX_VEX_0FD0 */
5111 { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5112 { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5115 /* PREFIX_VEX_0FD1 */
5119 { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5122 /* PREFIX_VEX_0FD2 */
5126 { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5129 /* PREFIX_VEX_0FD3 */
5133 { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5136 /* PREFIX_VEX_0FD4 */
5140 { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5143 /* PREFIX_VEX_0FD5 */
5147 { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5150 /* PREFIX_VEX_0FD6 */
5154 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5157 /* PREFIX_VEX_0FD7 */
5161 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5164 /* PREFIX_VEX_0FD8 */
5168 { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5171 /* PREFIX_VEX_0FD9 */
5175 { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5178 /* PREFIX_VEX_0FDA */
5182 { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5185 /* PREFIX_VEX_0FDB */
5189 { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5192 /* PREFIX_VEX_0FDC */
5196 { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5199 /* PREFIX_VEX_0FDD */
5203 { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5206 /* PREFIX_VEX_0FDE */
5210 { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5213 /* PREFIX_VEX_0FDF */
5217 { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5220 /* PREFIX_VEX_0FE0 */
5224 { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5227 /* PREFIX_VEX_0FE1 */
5231 { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5234 /* PREFIX_VEX_0FE2 */
5238 { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5241 /* PREFIX_VEX_0FE3 */
5245 { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5248 /* PREFIX_VEX_0FE4 */
5252 { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5255 /* PREFIX_VEX_0FE5 */
5259 { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5262 /* PREFIX_VEX_0FE6 */
5265 { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5266 { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5267 { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5270 /* PREFIX_VEX_0FE7 */
5274 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5277 /* PREFIX_VEX_0FE8 */
5281 { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5284 /* PREFIX_VEX_0FE9 */
5288 { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5291 /* PREFIX_VEX_0FEA */
5295 { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5298 /* PREFIX_VEX_0FEB */
5302 { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5305 /* PREFIX_VEX_0FEC */
5309 { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5312 /* PREFIX_VEX_0FED */
5316 { VEX_W_TABLE (VEX_W_0FED_P_2) },
5319 /* PREFIX_VEX_0FEE */
5323 { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5326 /* PREFIX_VEX_0FEF */
5330 { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5333 /* PREFIX_VEX_0FF0 */
5338 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5341 /* PREFIX_VEX_0FF1 */
5345 { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5348 /* PREFIX_VEX_0FF2 */
5352 { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5355 /* PREFIX_VEX_0FF3 */
5359 { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5362 /* PREFIX_VEX_0FF4 */
5366 { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5369 /* PREFIX_VEX_0FF5 */
5373 { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5376 /* PREFIX_VEX_0FF6 */
5380 { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5383 /* PREFIX_VEX_0FF7 */
5387 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5390 /* PREFIX_VEX_0FF8 */
5394 { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5397 /* PREFIX_VEX_0FF9 */
5401 { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5404 /* PREFIX_VEX_0FFA */
5408 { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5411 /* PREFIX_VEX_0FFB */
5415 { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5418 /* PREFIX_VEX_0FFC */
5422 { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5425 /* PREFIX_VEX_0FFD */
5429 { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5432 /* PREFIX_VEX_0FFE */
5436 { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5439 /* PREFIX_VEX_0F3800 */
5443 { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5446 /* PREFIX_VEX_0F3801 */
5450 { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5453 /* PREFIX_VEX_0F3802 */
5457 { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5460 /* PREFIX_VEX_0F3803 */
5464 { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5467 /* PREFIX_VEX_0F3804 */
5471 { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5474 /* PREFIX_VEX_0F3805 */
5478 { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5481 /* PREFIX_VEX_0F3806 */
5485 { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5488 /* PREFIX_VEX_0F3807 */
5492 { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5495 /* PREFIX_VEX_0F3808 */
5499 { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5502 /* PREFIX_VEX_0F3809 */
5506 { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5509 /* PREFIX_VEX_0F380A */
5513 { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5516 /* PREFIX_VEX_0F380B */
5520 { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5523 /* PREFIX_VEX_0F380C */
5527 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5530 /* PREFIX_VEX_0F380D */
5534 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5537 /* PREFIX_VEX_0F380E */
5541 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5544 /* PREFIX_VEX_0F380F */
5548 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5551 /* PREFIX_VEX_0F3813 */
5555 { "vcvtph2ps", { XM, EXxmmq } },
5558 /* PREFIX_VEX_0F3816 */
5562 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5565 /* PREFIX_VEX_0F3817 */
5569 { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5572 /* PREFIX_VEX_0F3818 */
5576 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5579 /* PREFIX_VEX_0F3819 */
5583 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5586 /* PREFIX_VEX_0F381A */
5590 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5593 /* PREFIX_VEX_0F381C */
5597 { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5600 /* PREFIX_VEX_0F381D */
5604 { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5607 /* PREFIX_VEX_0F381E */
5611 { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5614 /* PREFIX_VEX_0F3820 */
5618 { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5621 /* PREFIX_VEX_0F3821 */
5625 { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5628 /* PREFIX_VEX_0F3822 */
5632 { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5635 /* PREFIX_VEX_0F3823 */
5639 { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5642 /* PREFIX_VEX_0F3824 */
5646 { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5649 /* PREFIX_VEX_0F3825 */
5653 { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5656 /* PREFIX_VEX_0F3828 */
5660 { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5663 /* PREFIX_VEX_0F3829 */
5667 { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5670 /* PREFIX_VEX_0F382A */
5674 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5677 /* PREFIX_VEX_0F382B */
5681 { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5684 /* PREFIX_VEX_0F382C */
5688 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5691 /* PREFIX_VEX_0F382D */
5695 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5698 /* PREFIX_VEX_0F382E */
5702 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5705 /* PREFIX_VEX_0F382F */
5709 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5712 /* PREFIX_VEX_0F3830 */
5716 { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5719 /* PREFIX_VEX_0F3831 */
5723 { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5726 /* PREFIX_VEX_0F3832 */
5730 { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5733 /* PREFIX_VEX_0F3833 */
5737 { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5740 /* PREFIX_VEX_0F3834 */
5744 { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5747 /* PREFIX_VEX_0F3835 */
5751 { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5754 /* PREFIX_VEX_0F3836 */
5758 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5761 /* PREFIX_VEX_0F3837 */
5765 { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5768 /* PREFIX_VEX_0F3838 */
5772 { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5775 /* PREFIX_VEX_0F3839 */
5779 { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5782 /* PREFIX_VEX_0F383A */
5786 { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5789 /* PREFIX_VEX_0F383B */
5793 { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5796 /* PREFIX_VEX_0F383C */
5800 { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5803 /* PREFIX_VEX_0F383D */
5807 { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5810 /* PREFIX_VEX_0F383E */
5814 { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5817 /* PREFIX_VEX_0F383F */
5821 { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5824 /* PREFIX_VEX_0F3840 */
5828 { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5831 /* PREFIX_VEX_0F3841 */
5835 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5838 /* PREFIX_VEX_0F3845 */
5842 { "vpsrlv%LW", { XM, Vex, EXx } },
5845 /* PREFIX_VEX_0F3846 */
5849 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5852 /* PREFIX_VEX_0F3847 */
5856 { "vpsllv%LW", { XM, Vex, EXx } },
5859 /* PREFIX_VEX_0F3858 */
5863 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5866 /* PREFIX_VEX_0F3859 */
5870 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5873 /* PREFIX_VEX_0F385A */
5877 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5880 /* PREFIX_VEX_0F3878 */
5884 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5887 /* PREFIX_VEX_0F3879 */
5891 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5894 /* PREFIX_VEX_0F388C */
5898 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5901 /* PREFIX_VEX_0F388E */
5905 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5908 /* PREFIX_VEX_0F3890 */
5912 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
5915 /* PREFIX_VEX_0F3891 */
5919 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5922 /* PREFIX_VEX_0F3892 */
5926 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
5929 /* PREFIX_VEX_0F3893 */
5933 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5936 /* PREFIX_VEX_0F3896 */
5940 { "vfmaddsub132p%XW", { XM, Vex, EXx } },
5943 /* PREFIX_VEX_0F3897 */
5947 { "vfmsubadd132p%XW", { XM, Vex, EXx } },
5950 /* PREFIX_VEX_0F3898 */
5954 { "vfmadd132p%XW", { XM, Vex, EXx } },
5957 /* PREFIX_VEX_0F3899 */
5961 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5964 /* PREFIX_VEX_0F389A */
5968 { "vfmsub132p%XW", { XM, Vex, EXx } },
5971 /* PREFIX_VEX_0F389B */
5975 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5978 /* PREFIX_VEX_0F389C */
5982 { "vfnmadd132p%XW", { XM, Vex, EXx } },
5985 /* PREFIX_VEX_0F389D */
5989 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5992 /* PREFIX_VEX_0F389E */
5996 { "vfnmsub132p%XW", { XM, Vex, EXx } },
5999 /* PREFIX_VEX_0F389F */
6003 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6006 /* PREFIX_VEX_0F38A6 */
6010 { "vfmaddsub213p%XW", { XM, Vex, EXx } },
6014 /* PREFIX_VEX_0F38A7 */
6018 { "vfmsubadd213p%XW", { XM, Vex, EXx } },
6021 /* PREFIX_VEX_0F38A8 */
6025 { "vfmadd213p%XW", { XM, Vex, EXx } },
6028 /* PREFIX_VEX_0F38A9 */
6032 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6035 /* PREFIX_VEX_0F38AA */
6039 { "vfmsub213p%XW", { XM, Vex, EXx } },
6042 /* PREFIX_VEX_0F38AB */
6046 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6049 /* PREFIX_VEX_0F38AC */
6053 { "vfnmadd213p%XW", { XM, Vex, EXx } },
6056 /* PREFIX_VEX_0F38AD */
6060 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6063 /* PREFIX_VEX_0F38AE */
6067 { "vfnmsub213p%XW", { XM, Vex, EXx } },
6070 /* PREFIX_VEX_0F38AF */
6074 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6077 /* PREFIX_VEX_0F38B6 */
6081 { "vfmaddsub231p%XW", { XM, Vex, EXx } },
6084 /* PREFIX_VEX_0F38B7 */
6088 { "vfmsubadd231p%XW", { XM, Vex, EXx } },
6091 /* PREFIX_VEX_0F38B8 */
6095 { "vfmadd231p%XW", { XM, Vex, EXx } },
6098 /* PREFIX_VEX_0F38B9 */
6102 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6105 /* PREFIX_VEX_0F38BA */
6109 { "vfmsub231p%XW", { XM, Vex, EXx } },
6112 /* PREFIX_VEX_0F38BB */
6116 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6119 /* PREFIX_VEX_0F38BC */
6123 { "vfnmadd231p%XW", { XM, Vex, EXx } },
6126 /* PREFIX_VEX_0F38BD */
6130 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6133 /* PREFIX_VEX_0F38BE */
6137 { "vfnmsub231p%XW", { XM, Vex, EXx } },
6140 /* PREFIX_VEX_0F38BF */
6144 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6147 /* PREFIX_VEX_0F38DB */
6151 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6154 /* PREFIX_VEX_0F38DC */
6158 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6161 /* PREFIX_VEX_0F38DD */
6165 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6168 /* PREFIX_VEX_0F38DE */
6172 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6175 /* PREFIX_VEX_0F38DF */
6179 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6182 /* PREFIX_VEX_0F38F2 */
6184 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6187 /* PREFIX_VEX_0F38F3_REG_1 */
6189 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6192 /* PREFIX_VEX_0F38F3_REG_2 */
6194 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6197 /* PREFIX_VEX_0F38F3_REG_3 */
6199 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6202 /* PREFIX_VEX_0F38F5 */
6204 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6205 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6207 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6210 /* PREFIX_VEX_0F38F6 */
6215 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6218 /* PREFIX_VEX_0F38F7 */
6220 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6221 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6222 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6223 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6226 /* PREFIX_VEX_0F3A00 */
6230 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6233 /* PREFIX_VEX_0F3A01 */
6237 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6240 /* PREFIX_VEX_0F3A02 */
6244 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6247 /* PREFIX_VEX_0F3A04 */
6251 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6254 /* PREFIX_VEX_0F3A05 */
6258 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6261 /* PREFIX_VEX_0F3A06 */
6265 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6268 /* PREFIX_VEX_0F3A08 */
6272 { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6275 /* PREFIX_VEX_0F3A09 */
6279 { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6282 /* PREFIX_VEX_0F3A0A */
6286 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6289 /* PREFIX_VEX_0F3A0B */
6293 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6296 /* PREFIX_VEX_0F3A0C */
6300 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6303 /* PREFIX_VEX_0F3A0D */
6307 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6310 /* PREFIX_VEX_0F3A0E */
6314 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6317 /* PREFIX_VEX_0F3A0F */
6321 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6324 /* PREFIX_VEX_0F3A14 */
6328 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6331 /* PREFIX_VEX_0F3A15 */
6335 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6338 /* PREFIX_VEX_0F3A16 */
6342 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6345 /* PREFIX_VEX_0F3A17 */
6349 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6352 /* PREFIX_VEX_0F3A18 */
6356 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6359 /* PREFIX_VEX_0F3A19 */
6363 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6366 /* PREFIX_VEX_0F3A1D */
6370 { "vcvtps2ph", { EXxmmq, XM, Ib } },
6373 /* PREFIX_VEX_0F3A20 */
6377 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6380 /* PREFIX_VEX_0F3A21 */
6384 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6387 /* PREFIX_VEX_0F3A22 */
6391 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6394 /* PREFIX_VEX_0F3A30 */
6398 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6401 /* PREFIX_VEX_0F3A31 */
6405 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6408 /* PREFIX_VEX_0F3A32 */
6412 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6415 /* PREFIX_VEX_0F3A33 */
6419 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6422 /* PREFIX_VEX_0F3A38 */
6426 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6429 /* PREFIX_VEX_0F3A39 */
6433 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6436 /* PREFIX_VEX_0F3A40 */
6440 { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6443 /* PREFIX_VEX_0F3A41 */
6447 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6450 /* PREFIX_VEX_0F3A42 */
6454 { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6457 /* PREFIX_VEX_0F3A44 */
6461 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6464 /* PREFIX_VEX_0F3A46 */
6468 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6471 /* PREFIX_VEX_0F3A48 */
6475 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6478 /* PREFIX_VEX_0F3A49 */
6482 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6485 /* PREFIX_VEX_0F3A4A */
6489 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6492 /* PREFIX_VEX_0F3A4B */
6496 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6499 /* PREFIX_VEX_0F3A4C */
6503 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6506 /* PREFIX_VEX_0F3A5C */
6510 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6513 /* PREFIX_VEX_0F3A5D */
6517 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6520 /* PREFIX_VEX_0F3A5E */
6524 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6527 /* PREFIX_VEX_0F3A5F */
6531 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6534 /* PREFIX_VEX_0F3A60 */
6538 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6542 /* PREFIX_VEX_0F3A61 */
6546 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6549 /* PREFIX_VEX_0F3A62 */
6553 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6556 /* PREFIX_VEX_0F3A63 */
6560 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6563 /* PREFIX_VEX_0F3A68 */
6567 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6570 /* PREFIX_VEX_0F3A69 */
6574 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6577 /* PREFIX_VEX_0F3A6A */
6581 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6584 /* PREFIX_VEX_0F3A6B */
6588 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6591 /* PREFIX_VEX_0F3A6C */
6595 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6598 /* PREFIX_VEX_0F3A6D */
6602 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6605 /* PREFIX_VEX_0F3A6E */
6609 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6612 /* PREFIX_VEX_0F3A6F */
6616 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6619 /* PREFIX_VEX_0F3A78 */
6623 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6626 /* PREFIX_VEX_0F3A79 */
6630 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6633 /* PREFIX_VEX_0F3A7A */
6637 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6640 /* PREFIX_VEX_0F3A7B */
6644 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6647 /* PREFIX_VEX_0F3A7C */
6651 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6655 /* PREFIX_VEX_0F3A7D */
6659 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6662 /* PREFIX_VEX_0F3A7E */
6666 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6669 /* PREFIX_VEX_0F3A7F */
6673 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6676 /* PREFIX_VEX_0F3ADF */
6680 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6683 /* PREFIX_VEX_0F3AF0 */
6688 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6691 #define NEED_PREFIX_TABLE
6692 #include "i386-dis-evex.h"
6693 #undef NEED_PREFIX_TABLE
6696 static const struct dis386 x86_64_table[][2] = {
6699 { "pushP", { es } },
6709 { "pushP", { cs } },
6714 { "pushP", { ss } },
6724 { "pushP", { ds } },
6754 { "pushaP", { XX } },
6759 { "popaP", { XX } },
6764 { MOD_TABLE (MOD_62_32BIT) },
6765 { EVEX_TABLE (EVEX_0F) },
6770 { "arpl", { Ew, Gw } },
6771 { "movs{lq|xd}", { Gv, Ed } },
6776 { "ins{R|}", { Yzr, indirDX } },
6777 { "ins{G|}", { Yzr, indirDX } },
6782 { "outs{R|}", { indirDXr, Xz } },
6783 { "outs{G|}", { indirDXr, Xz } },
6788 { "Jcall{T|}", { Ap } },
6793 { MOD_TABLE (MOD_C4_32BIT) },
6794 { VEX_C4_TABLE (VEX_0F) },
6799 { MOD_TABLE (MOD_C5_32BIT) },
6800 { VEX_C5_TABLE (VEX_0F) },
6820 { "Jjmp{T|}", { Ap } },
6823 /* X86_64_0F01_REG_0 */
6825 { "sgdt{Q|IQ}", { M } },
6829 /* X86_64_0F01_REG_1 */
6831 { "sidt{Q|IQ}", { M } },
6835 /* X86_64_0F01_REG_2 */
6837 { "lgdt{Q|Q}", { M } },
6841 /* X86_64_0F01_REG_3 */
6843 { "lidt{Q|Q}", { M } },
6848 static const struct dis386 three_byte_table[][256] = {
6850 /* THREE_BYTE_0F38 */
6853 { "pshufb", { MX, EM } },
6854 { "phaddw", { MX, EM } },
6855 { "phaddd", { MX, EM } },
6856 { "phaddsw", { MX, EM } },
6857 { "pmaddubsw", { MX, EM } },
6858 { "phsubw", { MX, EM } },
6859 { "phsubd", { MX, EM } },
6860 { "phsubsw", { MX, EM } },
6862 { "psignb", { MX, EM } },
6863 { "psignw", { MX, EM } },
6864 { "psignd", { MX, EM } },
6865 { "pmulhrsw", { MX, EM } },
6871 { PREFIX_TABLE (PREFIX_0F3810) },
6875 { PREFIX_TABLE (PREFIX_0F3814) },
6876 { PREFIX_TABLE (PREFIX_0F3815) },
6878 { PREFIX_TABLE (PREFIX_0F3817) },
6884 { "pabsb", { MX, EM } },
6885 { "pabsw", { MX, EM } },
6886 { "pabsd", { MX, EM } },
6889 { PREFIX_TABLE (PREFIX_0F3820) },
6890 { PREFIX_TABLE (PREFIX_0F3821) },
6891 { PREFIX_TABLE (PREFIX_0F3822) },
6892 { PREFIX_TABLE (PREFIX_0F3823) },
6893 { PREFIX_TABLE (PREFIX_0F3824) },
6894 { PREFIX_TABLE (PREFIX_0F3825) },
6898 { PREFIX_TABLE (PREFIX_0F3828) },
6899 { PREFIX_TABLE (PREFIX_0F3829) },
6900 { PREFIX_TABLE (PREFIX_0F382A) },
6901 { PREFIX_TABLE (PREFIX_0F382B) },
6907 { PREFIX_TABLE (PREFIX_0F3830) },
6908 { PREFIX_TABLE (PREFIX_0F3831) },
6909 { PREFIX_TABLE (PREFIX_0F3832) },
6910 { PREFIX_TABLE (PREFIX_0F3833) },
6911 { PREFIX_TABLE (PREFIX_0F3834) },
6912 { PREFIX_TABLE (PREFIX_0F3835) },
6914 { PREFIX_TABLE (PREFIX_0F3837) },
6916 { PREFIX_TABLE (PREFIX_0F3838) },
6917 { PREFIX_TABLE (PREFIX_0F3839) },
6918 { PREFIX_TABLE (PREFIX_0F383A) },
6919 { PREFIX_TABLE (PREFIX_0F383B) },
6920 { PREFIX_TABLE (PREFIX_0F383C) },
6921 { PREFIX_TABLE (PREFIX_0F383D) },
6922 { PREFIX_TABLE (PREFIX_0F383E) },
6923 { PREFIX_TABLE (PREFIX_0F383F) },
6925 { PREFIX_TABLE (PREFIX_0F3840) },
6926 { PREFIX_TABLE (PREFIX_0F3841) },
6997 { PREFIX_TABLE (PREFIX_0F3880) },
6998 { PREFIX_TABLE (PREFIX_0F3881) },
6999 { PREFIX_TABLE (PREFIX_0F3882) },
7078 { PREFIX_TABLE (PREFIX_0F38C8) },
7079 { PREFIX_TABLE (PREFIX_0F38C9) },
7080 { PREFIX_TABLE (PREFIX_0F38CA) },
7081 { PREFIX_TABLE (PREFIX_0F38CB) },
7082 { PREFIX_TABLE (PREFIX_0F38CC) },
7083 { PREFIX_TABLE (PREFIX_0F38CD) },
7099 { PREFIX_TABLE (PREFIX_0F38DB) },
7100 { PREFIX_TABLE (PREFIX_0F38DC) },
7101 { PREFIX_TABLE (PREFIX_0F38DD) },
7102 { PREFIX_TABLE (PREFIX_0F38DE) },
7103 { PREFIX_TABLE (PREFIX_0F38DF) },
7123 { PREFIX_TABLE (PREFIX_0F38F0) },
7124 { PREFIX_TABLE (PREFIX_0F38F1) },
7129 { PREFIX_TABLE (PREFIX_0F38F6) },
7141 /* THREE_BYTE_0F3A */
7153 { PREFIX_TABLE (PREFIX_0F3A08) },
7154 { PREFIX_TABLE (PREFIX_0F3A09) },
7155 { PREFIX_TABLE (PREFIX_0F3A0A) },
7156 { PREFIX_TABLE (PREFIX_0F3A0B) },
7157 { PREFIX_TABLE (PREFIX_0F3A0C) },
7158 { PREFIX_TABLE (PREFIX_0F3A0D) },
7159 { PREFIX_TABLE (PREFIX_0F3A0E) },
7160 { "palignr", { MX, EM, Ib } },
7166 { PREFIX_TABLE (PREFIX_0F3A14) },
7167 { PREFIX_TABLE (PREFIX_0F3A15) },
7168 { PREFIX_TABLE (PREFIX_0F3A16) },
7169 { PREFIX_TABLE (PREFIX_0F3A17) },
7180 { PREFIX_TABLE (PREFIX_0F3A20) },
7181 { PREFIX_TABLE (PREFIX_0F3A21) },
7182 { PREFIX_TABLE (PREFIX_0F3A22) },
7216 { PREFIX_TABLE (PREFIX_0F3A40) },
7217 { PREFIX_TABLE (PREFIX_0F3A41) },
7218 { PREFIX_TABLE (PREFIX_0F3A42) },
7220 { PREFIX_TABLE (PREFIX_0F3A44) },
7252 { PREFIX_TABLE (PREFIX_0F3A60) },
7253 { PREFIX_TABLE (PREFIX_0F3A61) },
7254 { PREFIX_TABLE (PREFIX_0F3A62) },
7255 { PREFIX_TABLE (PREFIX_0F3A63) },
7373 { PREFIX_TABLE (PREFIX_0F3ACC) },
7394 { PREFIX_TABLE (PREFIX_0F3ADF) },
7433 /* THREE_BYTE_0F7A */
7472 { "ptest", { XX } },
7509 { "phaddbw", { XM, EXq } },
7510 { "phaddbd", { XM, EXq } },
7511 { "phaddbq", { XM, EXq } },
7514 { "phaddwd", { XM, EXq } },
7515 { "phaddwq", { XM, EXq } },
7520 { "phadddq", { XM, EXq } },
7527 { "phaddubw", { XM, EXq } },
7528 { "phaddubd", { XM, EXq } },
7529 { "phaddubq", { XM, EXq } },
7532 { "phadduwd", { XM, EXq } },
7533 { "phadduwq", { XM, EXq } },
7538 { "phaddudq", { XM, EXq } },
7545 { "phsubbw", { XM, EXq } },
7546 { "phsubbd", { XM, EXq } },
7547 { "phsubbq", { XM, EXq } },
7726 static const struct dis386 xop_table[][256] = {
7879 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7880 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7881 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7889 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7890 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7897 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7898 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7899 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7907 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7908 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7912 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7913 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7916 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7934 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7946 { "vprotb", { XM, Vex_2src_1, Ib } },
7947 { "vprotw", { XM, Vex_2src_1, Ib } },
7948 { "vprotd", { XM, Vex_2src_1, Ib } },
7949 { "vprotq", { XM, Vex_2src_1, Ib } },
7959 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7960 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7961 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7962 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7995 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7996 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7997 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7998 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8022 { REG_TABLE (REG_XOP_TBM_01) },
8023 { REG_TABLE (REG_XOP_TBM_02) },
8041 { REG_TABLE (REG_XOP_LWPCB) },
8165 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8166 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8167 { "vfrczss", { XM, EXd } },
8168 { "vfrczsd", { XM, EXq } },
8183 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } },
8184 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } },
8185 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } },
8186 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } },
8187 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } },
8188 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } },
8189 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } },
8190 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } },
8192 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } },
8193 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } },
8194 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } },
8195 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } },
8238 { "vphaddbw", { XM, EXxmm } },
8239 { "vphaddbd", { XM, EXxmm } },
8240 { "vphaddbq", { XM, EXxmm } },
8243 { "vphaddwd", { XM, EXxmm } },
8244 { "vphaddwq", { XM, EXxmm } },
8249 { "vphadddq", { XM, EXxmm } },
8256 { "vphaddubw", { XM, EXxmm } },
8257 { "vphaddubd", { XM, EXxmm } },
8258 { "vphaddubq", { XM, EXxmm } },
8261 { "vphadduwd", { XM, EXxmm } },
8262 { "vphadduwq", { XM, EXxmm } },
8267 { "vphaddudq", { XM, EXxmm } },
8274 { "vphsubbw", { XM, EXxmm } },
8275 { "vphsubwd", { XM, EXxmm } },
8276 { "vphsubdq", { XM, EXxmm } },
8330 { "bextr", { Gv, Ev, Iq } },
8332 { REG_TABLE (REG_XOP_LWP) },
8602 static const struct dis386 vex_table[][256] = {
8624 { PREFIX_TABLE (PREFIX_VEX_0F10) },
8625 { PREFIX_TABLE (PREFIX_VEX_0F11) },
8626 { PREFIX_TABLE (PREFIX_VEX_0F12) },
8627 { MOD_TABLE (MOD_VEX_0F13) },
8628 { VEX_W_TABLE (VEX_W_0F14) },
8629 { VEX_W_TABLE (VEX_W_0F15) },
8630 { PREFIX_TABLE (PREFIX_VEX_0F16) },
8631 { MOD_TABLE (MOD_VEX_0F17) },
8651 { VEX_W_TABLE (VEX_W_0F28) },
8652 { VEX_W_TABLE (VEX_W_0F29) },
8653 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8654 { MOD_TABLE (MOD_VEX_0F2B) },
8655 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8656 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8657 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8658 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8679 { PREFIX_TABLE (PREFIX_VEX_0F41) },
8680 { PREFIX_TABLE (PREFIX_VEX_0F42) },
8682 { PREFIX_TABLE (PREFIX_VEX_0F44) },
8683 { PREFIX_TABLE (PREFIX_VEX_0F45) },
8684 { PREFIX_TABLE (PREFIX_VEX_0F46) },
8685 { PREFIX_TABLE (PREFIX_VEX_0F47) },
8689 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8690 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8696 { MOD_TABLE (MOD_VEX_0F50) },
8697 { PREFIX_TABLE (PREFIX_VEX_0F51) },
8698 { PREFIX_TABLE (PREFIX_VEX_0F52) },
8699 { PREFIX_TABLE (PREFIX_VEX_0F53) },
8700 { "vandpX", { XM, Vex, EXx } },
8701 { "vandnpX", { XM, Vex, EXx } },
8702 { "vorpX", { XM, Vex, EXx } },
8703 { "vxorpX", { XM, Vex, EXx } },
8705 { PREFIX_TABLE (PREFIX_VEX_0F58) },
8706 { PREFIX_TABLE (PREFIX_VEX_0F59) },
8707 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8708 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8709 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8710 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8711 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8712 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8714 { PREFIX_TABLE (PREFIX_VEX_0F60) },
8715 { PREFIX_TABLE (PREFIX_VEX_0F61) },
8716 { PREFIX_TABLE (PREFIX_VEX_0F62) },
8717 { PREFIX_TABLE (PREFIX_VEX_0F63) },
8718 { PREFIX_TABLE (PREFIX_VEX_0F64) },
8719 { PREFIX_TABLE (PREFIX_VEX_0F65) },
8720 { PREFIX_TABLE (PREFIX_VEX_0F66) },
8721 { PREFIX_TABLE (PREFIX_VEX_0F67) },
8723 { PREFIX_TABLE (PREFIX_VEX_0F68) },
8724 { PREFIX_TABLE (PREFIX_VEX_0F69) },
8725 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F70) },
8733 { REG_TABLE (REG_VEX_0F71) },
8734 { REG_TABLE (REG_VEX_0F72) },
8735 { REG_TABLE (REG_VEX_0F73) },
8736 { PREFIX_TABLE (PREFIX_VEX_0F74) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F75) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F76) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F77) },
8745 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8746 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F90) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F91) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F92) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F93) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F98) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F99) },
8801 { REG_TABLE (REG_VEX_0FAE) },
8824 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8826 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8827 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8828 { "vshufpX", { XM, Vex, EXx, Ib } },
8840 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8841 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8842 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8843 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8844 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8845 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8846 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8847 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8849 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8850 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8851 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8852 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8853 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8854 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8855 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8856 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8858 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8859 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8860 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8861 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8862 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8863 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8864 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8865 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8867 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8868 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8869 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8870 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8871 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8872 { PREFIX_TABLE (PREFIX_VEX_0FED) },
8873 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8874 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8876 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8877 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8878 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8879 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8880 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8881 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8882 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8883 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8885 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8886 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8887 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8888 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8889 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8890 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8891 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8907 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8909 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8924 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8925 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8926 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8928 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8929 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8954 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8956 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8957 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8960 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8961 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8962 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8963 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8964 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8965 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8966 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8967 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8969 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8974 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8975 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8976 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8996 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8997 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9032 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9033 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9054 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9056 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9059 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9061 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9062 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9065 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9066 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9068 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9083 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9084 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9086 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9087 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9088 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9101 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9102 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9104 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9105 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9106 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9107 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9108 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9109 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9110 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9111 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9143 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9144 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9145 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9146 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9147 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9169 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9170 { REG_TABLE (REG_VEX_0F38F3) },
9172 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9173 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9174 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9188 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9189 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9190 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9192 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9193 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9194 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9197 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9198 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9199 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9200 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9201 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9202 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9203 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9204 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9210 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9211 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9212 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9213 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9215 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9216 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9220 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9224 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9225 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9226 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9242 { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9243 { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9244 { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9245 { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9251 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9252 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9260 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9261 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9262 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9264 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9266 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9269 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9270 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9271 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9272 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9273 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9291 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9292 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9293 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9294 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9296 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9297 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9298 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9299 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9305 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9306 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9307 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9308 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9309 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9310 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9311 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9312 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9323 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9324 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9325 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9326 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9327 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9328 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9329 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9330 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9438 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9458 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9478 #define NEED_OPCODE_TABLE
9479 #include "i386-dis-evex.h"
9480 #undef NEED_OPCODE_TABLE
9481 static const struct dis386 vex_len_table[][2] = {
9482 /* VEX_LEN_0F10_P_1 */
9484 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9485 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9488 /* VEX_LEN_0F10_P_3 */
9490 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9491 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9494 /* VEX_LEN_0F11_P_1 */
9496 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9497 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9500 /* VEX_LEN_0F11_P_3 */
9502 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9503 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9506 /* VEX_LEN_0F12_P_0_M_0 */
9508 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9511 /* VEX_LEN_0F12_P_0_M_1 */
9513 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9516 /* VEX_LEN_0F12_P_2 */
9518 { VEX_W_TABLE (VEX_W_0F12_P_2) },
9521 /* VEX_LEN_0F13_M_0 */
9523 { VEX_W_TABLE (VEX_W_0F13_M_0) },
9526 /* VEX_LEN_0F16_P_0_M_0 */
9528 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9531 /* VEX_LEN_0F16_P_0_M_1 */
9533 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9536 /* VEX_LEN_0F16_P_2 */
9538 { VEX_W_TABLE (VEX_W_0F16_P_2) },
9541 /* VEX_LEN_0F17_M_0 */
9543 { VEX_W_TABLE (VEX_W_0F17_M_0) },
9546 /* VEX_LEN_0F2A_P_1 */
9548 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
9549 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
9552 /* VEX_LEN_0F2A_P_3 */
9554 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
9555 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
9558 /* VEX_LEN_0F2C_P_1 */
9560 { "vcvttss2siY", { Gv, EXdScalar } },
9561 { "vcvttss2siY", { Gv, EXdScalar } },
9564 /* VEX_LEN_0F2C_P_3 */
9566 { "vcvttsd2siY", { Gv, EXqScalar } },
9567 { "vcvttsd2siY", { Gv, EXqScalar } },
9570 /* VEX_LEN_0F2D_P_1 */
9572 { "vcvtss2siY", { Gv, EXdScalar } },
9573 { "vcvtss2siY", { Gv, EXdScalar } },
9576 /* VEX_LEN_0F2D_P_3 */
9578 { "vcvtsd2siY", { Gv, EXqScalar } },
9579 { "vcvtsd2siY", { Gv, EXqScalar } },
9582 /* VEX_LEN_0F2E_P_0 */
9584 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9585 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9588 /* VEX_LEN_0F2E_P_2 */
9590 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9591 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9594 /* VEX_LEN_0F2F_P_0 */
9596 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9597 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9600 /* VEX_LEN_0F2F_P_2 */
9602 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9603 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9606 /* VEX_LEN_0F41_P_0 */
9609 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9611 /* VEX_LEN_0F41_P_2 */
9614 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9616 /* VEX_LEN_0F42_P_0 */
9619 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9621 /* VEX_LEN_0F42_P_2 */
9624 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9626 /* VEX_LEN_0F44_P_0 */
9628 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9630 /* VEX_LEN_0F44_P_2 */
9632 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9634 /* VEX_LEN_0F45_P_0 */
9637 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9639 /* VEX_LEN_0F45_P_2 */
9642 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9644 /* VEX_LEN_0F46_P_0 */
9647 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9649 /* VEX_LEN_0F46_P_2 */
9652 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9654 /* VEX_LEN_0F47_P_0 */
9657 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9659 /* VEX_LEN_0F47_P_2 */
9662 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9664 /* VEX_LEN_0F4A_P_0 */
9667 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9669 /* VEX_LEN_0F4A_P_2 */
9672 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9674 /* VEX_LEN_0F4B_P_0 */
9677 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9679 /* VEX_LEN_0F4B_P_2 */
9682 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9685 /* VEX_LEN_0F51_P_1 */
9687 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9688 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9691 /* VEX_LEN_0F51_P_3 */
9693 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9694 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9697 /* VEX_LEN_0F52_P_1 */
9699 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9700 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9703 /* VEX_LEN_0F53_P_1 */
9705 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9706 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9709 /* VEX_LEN_0F58_P_1 */
9711 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9712 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9715 /* VEX_LEN_0F58_P_3 */
9717 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9718 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9721 /* VEX_LEN_0F59_P_1 */
9723 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9724 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9727 /* VEX_LEN_0F59_P_3 */
9729 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9730 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9733 /* VEX_LEN_0F5A_P_1 */
9735 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9736 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9739 /* VEX_LEN_0F5A_P_3 */
9741 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9742 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9745 /* VEX_LEN_0F5C_P_1 */
9747 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9748 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9751 /* VEX_LEN_0F5C_P_3 */
9753 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9754 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9757 /* VEX_LEN_0F5D_P_1 */
9759 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9760 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9763 /* VEX_LEN_0F5D_P_3 */
9765 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9766 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9769 /* VEX_LEN_0F5E_P_1 */
9771 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9772 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9775 /* VEX_LEN_0F5E_P_3 */
9777 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9778 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9781 /* VEX_LEN_0F5F_P_1 */
9783 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9784 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9787 /* VEX_LEN_0F5F_P_3 */
9789 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9790 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9793 /* VEX_LEN_0F6E_P_2 */
9795 { "vmovK", { XMScalar, Edq } },
9796 { "vmovK", { XMScalar, Edq } },
9799 /* VEX_LEN_0F7E_P_1 */
9801 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9802 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9805 /* VEX_LEN_0F7E_P_2 */
9807 { "vmovK", { Edq, XMScalar } },
9808 { "vmovK", { Edq, XMScalar } },
9811 /* VEX_LEN_0F90_P_0 */
9813 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9816 /* VEX_LEN_0F90_P_2 */
9818 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9821 /* VEX_LEN_0F91_P_0 */
9823 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9826 /* VEX_LEN_0F91_P_2 */
9828 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9831 /* VEX_LEN_0F92_P_0 */
9833 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9836 /* VEX_LEN_0F92_P_2 */
9838 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9841 /* VEX_LEN_0F92_P_3 */
9843 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9846 /* VEX_LEN_0F93_P_0 */
9848 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9851 /* VEX_LEN_0F93_P_2 */
9853 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9856 /* VEX_LEN_0F93_P_3 */
9858 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9861 /* VEX_LEN_0F98_P_0 */
9863 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9866 /* VEX_LEN_0F98_P_2 */
9868 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9871 /* VEX_LEN_0F99_P_0 */
9873 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9876 /* VEX_LEN_0F99_P_2 */
9878 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9881 /* VEX_LEN_0FAE_R_2_M_0 */
9883 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9886 /* VEX_LEN_0FAE_R_3_M_0 */
9888 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9891 /* VEX_LEN_0FC2_P_1 */
9893 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9894 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9897 /* VEX_LEN_0FC2_P_3 */
9899 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9900 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9903 /* VEX_LEN_0FC4_P_2 */
9905 { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9908 /* VEX_LEN_0FC5_P_2 */
9910 { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9913 /* VEX_LEN_0FD6_P_2 */
9915 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9916 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9919 /* VEX_LEN_0FF7_P_2 */
9921 { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9924 /* VEX_LEN_0F3816_P_2 */
9927 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9930 /* VEX_LEN_0F3819_P_2 */
9933 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9936 /* VEX_LEN_0F381A_P_2_M_0 */
9939 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9942 /* VEX_LEN_0F3836_P_2 */
9945 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9948 /* VEX_LEN_0F3841_P_2 */
9950 { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9953 /* VEX_LEN_0F385A_P_2_M_0 */
9956 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9959 /* VEX_LEN_0F38DB_P_2 */
9961 { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9964 /* VEX_LEN_0F38DC_P_2 */
9966 { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9969 /* VEX_LEN_0F38DD_P_2 */
9971 { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9974 /* VEX_LEN_0F38DE_P_2 */
9976 { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9979 /* VEX_LEN_0F38DF_P_2 */
9981 { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9984 /* VEX_LEN_0F38F2_P_0 */
9986 { "andnS", { Gdq, VexGdq, Edq } },
9989 /* VEX_LEN_0F38F3_R_1_P_0 */
9991 { "blsrS", { VexGdq, Edq } },
9994 /* VEX_LEN_0F38F3_R_2_P_0 */
9996 { "blsmskS", { VexGdq, Edq } },
9999 /* VEX_LEN_0F38F3_R_3_P_0 */
10001 { "blsiS", { VexGdq, Edq } },
10004 /* VEX_LEN_0F38F5_P_0 */
10006 { "bzhiS", { Gdq, Edq, VexGdq } },
10009 /* VEX_LEN_0F38F5_P_1 */
10011 { "pextS", { Gdq, VexGdq, Edq } },
10014 /* VEX_LEN_0F38F5_P_3 */
10016 { "pdepS", { Gdq, VexGdq, Edq } },
10019 /* VEX_LEN_0F38F6_P_3 */
10021 { "mulxS", { Gdq, VexGdq, Edq } },
10024 /* VEX_LEN_0F38F7_P_0 */
10026 { "bextrS", { Gdq, Edq, VexGdq } },
10029 /* VEX_LEN_0F38F7_P_1 */
10031 { "sarxS", { Gdq, Edq, VexGdq } },
10034 /* VEX_LEN_0F38F7_P_2 */
10036 { "shlxS", { Gdq, Edq, VexGdq } },
10039 /* VEX_LEN_0F38F7_P_3 */
10041 { "shrxS", { Gdq, Edq, VexGdq } },
10044 /* VEX_LEN_0F3A00_P_2 */
10047 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10050 /* VEX_LEN_0F3A01_P_2 */
10053 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10056 /* VEX_LEN_0F3A06_P_2 */
10059 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10062 /* VEX_LEN_0F3A0A_P_2 */
10064 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10065 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10068 /* VEX_LEN_0F3A0B_P_2 */
10070 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10071 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10074 /* VEX_LEN_0F3A14_P_2 */
10076 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10079 /* VEX_LEN_0F3A15_P_2 */
10081 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10084 /* VEX_LEN_0F3A16_P_2 */
10086 { "vpextrK", { Edq, XM, Ib } },
10089 /* VEX_LEN_0F3A17_P_2 */
10091 { "vextractps", { Edqd, XM, Ib } },
10094 /* VEX_LEN_0F3A18_P_2 */
10097 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10100 /* VEX_LEN_0F3A19_P_2 */
10103 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10106 /* VEX_LEN_0F3A20_P_2 */
10108 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10111 /* VEX_LEN_0F3A21_P_2 */
10113 { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10116 /* VEX_LEN_0F3A22_P_2 */
10118 { "vpinsrK", { XM, Vex128, Edq, Ib } },
10121 /* VEX_LEN_0F3A30_P_2 */
10123 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10126 /* VEX_LEN_0F3A31_P_2 */
10128 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10131 /* VEX_LEN_0F3A32_P_2 */
10133 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10136 /* VEX_LEN_0F3A33_P_2 */
10138 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10141 /* VEX_LEN_0F3A38_P_2 */
10144 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10147 /* VEX_LEN_0F3A39_P_2 */
10150 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10153 /* VEX_LEN_0F3A41_P_2 */
10155 { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10158 /* VEX_LEN_0F3A44_P_2 */
10160 { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10163 /* VEX_LEN_0F3A46_P_2 */
10166 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10169 /* VEX_LEN_0F3A60_P_2 */
10171 { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10174 /* VEX_LEN_0F3A61_P_2 */
10176 { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10179 /* VEX_LEN_0F3A62_P_2 */
10181 { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10184 /* VEX_LEN_0F3A63_P_2 */
10186 { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10189 /* VEX_LEN_0F3A6A_P_2 */
10191 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10194 /* VEX_LEN_0F3A6B_P_2 */
10196 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10199 /* VEX_LEN_0F3A6E_P_2 */
10201 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10204 /* VEX_LEN_0F3A6F_P_2 */
10206 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10209 /* VEX_LEN_0F3A7A_P_2 */
10211 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10214 /* VEX_LEN_0F3A7B_P_2 */
10216 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10219 /* VEX_LEN_0F3A7E_P_2 */
10221 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10224 /* VEX_LEN_0F3A7F_P_2 */
10226 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10229 /* VEX_LEN_0F3ADF_P_2 */
10231 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10234 /* VEX_LEN_0F3AF0_P_3 */
10236 { "rorxS", { Gdq, Edq, Ib } },
10239 /* VEX_LEN_0FXOP_08_CC */
10241 { "vpcomb", { XM, Vex128, EXx, Ib } },
10244 /* VEX_LEN_0FXOP_08_CD */
10246 { "vpcomw", { XM, Vex128, EXx, Ib } },
10249 /* VEX_LEN_0FXOP_08_CE */
10251 { "vpcomd", { XM, Vex128, EXx, Ib } },
10254 /* VEX_LEN_0FXOP_08_CF */
10256 { "vpcomq", { XM, Vex128, EXx, Ib } },
10259 /* VEX_LEN_0FXOP_08_EC */
10261 { "vpcomub", { XM, Vex128, EXx, Ib } },
10264 /* VEX_LEN_0FXOP_08_ED */
10266 { "vpcomuw", { XM, Vex128, EXx, Ib } },
10269 /* VEX_LEN_0FXOP_08_EE */
10271 { "vpcomud", { XM, Vex128, EXx, Ib } },
10274 /* VEX_LEN_0FXOP_08_EF */
10276 { "vpcomuq", { XM, Vex128, EXx, Ib } },
10279 /* VEX_LEN_0FXOP_09_80 */
10281 { "vfrczps", { XM, EXxmm } },
10282 { "vfrczps", { XM, EXymmq } },
10285 /* VEX_LEN_0FXOP_09_81 */
10287 { "vfrczpd", { XM, EXxmm } },
10288 { "vfrczpd", { XM, EXymmq } },
10292 static const struct dis386 vex_w_table[][2] = {
10294 /* VEX_W_0F10_P_0 */
10295 { "vmovups", { XM, EXx } },
10298 /* VEX_W_0F10_P_1 */
10299 { "vmovss", { XMVexScalar, VexScalar, EXdScalar } },
10302 /* VEX_W_0F10_P_2 */
10303 { "vmovupd", { XM, EXx } },
10306 /* VEX_W_0F10_P_3 */
10307 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } },
10310 /* VEX_W_0F11_P_0 */
10311 { "vmovups", { EXxS, XM } },
10314 /* VEX_W_0F11_P_1 */
10315 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } },
10318 /* VEX_W_0F11_P_2 */
10319 { "vmovupd", { EXxS, XM } },
10322 /* VEX_W_0F11_P_3 */
10323 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } },
10326 /* VEX_W_0F12_P_0_M_0 */
10327 { "vmovlps", { XM, Vex128, EXq } },
10330 /* VEX_W_0F12_P_0_M_1 */
10331 { "vmovhlps", { XM, Vex128, EXq } },
10334 /* VEX_W_0F12_P_1 */
10335 { "vmovsldup", { XM, EXx } },
10338 /* VEX_W_0F12_P_2 */
10339 { "vmovlpd", { XM, Vex128, EXq } },
10342 /* VEX_W_0F12_P_3 */
10343 { "vmovddup", { XM, EXymmq } },
10346 /* VEX_W_0F13_M_0 */
10347 { "vmovlpX", { EXq, XM } },
10351 { "vunpcklpX", { XM, Vex, EXx } },
10355 { "vunpckhpX", { XM, Vex, EXx } },
10358 /* VEX_W_0F16_P_0_M_0 */
10359 { "vmovhps", { XM, Vex128, EXq } },
10362 /* VEX_W_0F16_P_0_M_1 */
10363 { "vmovlhps", { XM, Vex128, EXq } },
10366 /* VEX_W_0F16_P_1 */
10367 { "vmovshdup", { XM, EXx } },
10370 /* VEX_W_0F16_P_2 */
10371 { "vmovhpd", { XM, Vex128, EXq } },
10374 /* VEX_W_0F17_M_0 */
10375 { "vmovhpX", { EXq, XM } },
10379 { "vmovapX", { XM, EXx } },
10383 { "vmovapX", { EXxS, XM } },
10386 /* VEX_W_0F2B_M_0 */
10387 { "vmovntpX", { Mx, XM } },
10390 /* VEX_W_0F2E_P_0 */
10391 { "vucomiss", { XMScalar, EXdScalar } },
10394 /* VEX_W_0F2E_P_2 */
10395 { "vucomisd", { XMScalar, EXqScalar } },
10398 /* VEX_W_0F2F_P_0 */
10399 { "vcomiss", { XMScalar, EXdScalar } },
10402 /* VEX_W_0F2F_P_2 */
10403 { "vcomisd", { XMScalar, EXqScalar } },
10406 /* VEX_W_0F41_P_0_LEN_1 */
10407 { "kandw", { MaskG, MaskVex, MaskR } },
10408 { "kandq", { MaskG, MaskVex, MaskR } },
10411 /* VEX_W_0F41_P_2_LEN_1 */
10412 { "kandb", { MaskG, MaskVex, MaskR } },
10413 { "kandd", { MaskG, MaskVex, MaskR } },
10416 /* VEX_W_0F42_P_0_LEN_1 */
10417 { "kandnw", { MaskG, MaskVex, MaskR } },
10418 { "kandnq", { MaskG, MaskVex, MaskR } },
10421 /* VEX_W_0F42_P_2_LEN_1 */
10422 { "kandnb", { MaskG, MaskVex, MaskR } },
10423 { "kandnd", { MaskG, MaskVex, MaskR } },
10426 /* VEX_W_0F44_P_0_LEN_0 */
10427 { "knotw", { MaskG, MaskR } },
10428 { "knotq", { MaskG, MaskR } },
10431 /* VEX_W_0F44_P_2_LEN_0 */
10432 { "knotb", { MaskG, MaskR } },
10433 { "knotd", { MaskG, MaskR } },
10436 /* VEX_W_0F45_P_0_LEN_1 */
10437 { "korw", { MaskG, MaskVex, MaskR } },
10438 { "korq", { MaskG, MaskVex, MaskR } },
10441 /* VEX_W_0F45_P_2_LEN_1 */
10442 { "korb", { MaskG, MaskVex, MaskR } },
10443 { "kord", { MaskG, MaskVex, MaskR } },
10446 /* VEX_W_0F46_P_0_LEN_1 */
10447 { "kxnorw", { MaskG, MaskVex, MaskR } },
10448 { "kxnorq", { MaskG, MaskVex, MaskR } },
10451 /* VEX_W_0F46_P_2_LEN_1 */
10452 { "kxnorb", { MaskG, MaskVex, MaskR } },
10453 { "kxnord", { MaskG, MaskVex, MaskR } },
10456 /* VEX_W_0F47_P_0_LEN_1 */
10457 { "kxorw", { MaskG, MaskVex, MaskR } },
10458 { "kxorq", { MaskG, MaskVex, MaskR } },
10461 /* VEX_W_0F47_P_2_LEN_1 */
10462 { "kxorb", { MaskG, MaskVex, MaskR } },
10463 { "kxord", { MaskG, MaskVex, MaskR } },
10466 /* VEX_W_0F4A_P_0_LEN_1 */
10467 { "kaddw", { MaskG, MaskVex, MaskR } },
10468 { "kaddq", { MaskG, MaskVex, MaskR } },
10471 /* VEX_W_0F4A_P_2_LEN_1 */
10472 { "kaddb", { MaskG, MaskVex, MaskR } },
10473 { "kaddd", { MaskG, MaskVex, MaskR } },
10476 /* VEX_W_0F4B_P_0_LEN_1 */
10477 { "kunpckwd", { MaskG, MaskVex, MaskR } },
10478 { "kunpckdq", { MaskG, MaskVex, MaskR } },
10481 /* VEX_W_0F4B_P_2_LEN_1 */
10482 { "kunpckbw", { MaskG, MaskVex, MaskR } },
10485 /* VEX_W_0F50_M_0 */
10486 { "vmovmskpX", { Gdq, XS } },
10489 /* VEX_W_0F51_P_0 */
10490 { "vsqrtps", { XM, EXx } },
10493 /* VEX_W_0F51_P_1 */
10494 { "vsqrtss", { XMScalar, VexScalar, EXdScalar } },
10497 /* VEX_W_0F51_P_2 */
10498 { "vsqrtpd", { XM, EXx } },
10501 /* VEX_W_0F51_P_3 */
10502 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar } },
10505 /* VEX_W_0F52_P_0 */
10506 { "vrsqrtps", { XM, EXx } },
10509 /* VEX_W_0F52_P_1 */
10510 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar } },
10513 /* VEX_W_0F53_P_0 */
10514 { "vrcpps", { XM, EXx } },
10517 /* VEX_W_0F53_P_1 */
10518 { "vrcpss", { XMScalar, VexScalar, EXdScalar } },
10521 /* VEX_W_0F58_P_0 */
10522 { "vaddps", { XM, Vex, EXx } },
10525 /* VEX_W_0F58_P_1 */
10526 { "vaddss", { XMScalar, VexScalar, EXdScalar } },
10529 /* VEX_W_0F58_P_2 */
10530 { "vaddpd", { XM, Vex, EXx } },
10533 /* VEX_W_0F58_P_3 */
10534 { "vaddsd", { XMScalar, VexScalar, EXqScalar } },
10537 /* VEX_W_0F59_P_0 */
10538 { "vmulps", { XM, Vex, EXx } },
10541 /* VEX_W_0F59_P_1 */
10542 { "vmulss", { XMScalar, VexScalar, EXdScalar } },
10545 /* VEX_W_0F59_P_2 */
10546 { "vmulpd", { XM, Vex, EXx } },
10549 /* VEX_W_0F59_P_3 */
10550 { "vmulsd", { XMScalar, VexScalar, EXqScalar } },
10553 /* VEX_W_0F5A_P_0 */
10554 { "vcvtps2pd", { XM, EXxmmq } },
10557 /* VEX_W_0F5A_P_1 */
10558 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar } },
10561 /* VEX_W_0F5A_P_3 */
10562 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar } },
10565 /* VEX_W_0F5B_P_0 */
10566 { "vcvtdq2ps", { XM, EXx } },
10569 /* VEX_W_0F5B_P_1 */
10570 { "vcvttps2dq", { XM, EXx } },
10573 /* VEX_W_0F5B_P_2 */
10574 { "vcvtps2dq", { XM, EXx } },
10577 /* VEX_W_0F5C_P_0 */
10578 { "vsubps", { XM, Vex, EXx } },
10581 /* VEX_W_0F5C_P_1 */
10582 { "vsubss", { XMScalar, VexScalar, EXdScalar } },
10585 /* VEX_W_0F5C_P_2 */
10586 { "vsubpd", { XM, Vex, EXx } },
10589 /* VEX_W_0F5C_P_3 */
10590 { "vsubsd", { XMScalar, VexScalar, EXqScalar } },
10593 /* VEX_W_0F5D_P_0 */
10594 { "vminps", { XM, Vex, EXx } },
10597 /* VEX_W_0F5D_P_1 */
10598 { "vminss", { XMScalar, VexScalar, EXdScalar } },
10601 /* VEX_W_0F5D_P_2 */
10602 { "vminpd", { XM, Vex, EXx } },
10605 /* VEX_W_0F5D_P_3 */
10606 { "vminsd", { XMScalar, VexScalar, EXqScalar } },
10609 /* VEX_W_0F5E_P_0 */
10610 { "vdivps", { XM, Vex, EXx } },
10613 /* VEX_W_0F5E_P_1 */
10614 { "vdivss", { XMScalar, VexScalar, EXdScalar } },
10617 /* VEX_W_0F5E_P_2 */
10618 { "vdivpd", { XM, Vex, EXx } },
10621 /* VEX_W_0F5E_P_3 */
10622 { "vdivsd", { XMScalar, VexScalar, EXqScalar } },
10625 /* VEX_W_0F5F_P_0 */
10626 { "vmaxps", { XM, Vex, EXx } },
10629 /* VEX_W_0F5F_P_1 */
10630 { "vmaxss", { XMScalar, VexScalar, EXdScalar } },
10633 /* VEX_W_0F5F_P_2 */
10634 { "vmaxpd", { XM, Vex, EXx } },
10637 /* VEX_W_0F5F_P_3 */
10638 { "vmaxsd", { XMScalar, VexScalar, EXqScalar } },
10641 /* VEX_W_0F60_P_2 */
10642 { "vpunpcklbw", { XM, Vex, EXx } },
10645 /* VEX_W_0F61_P_2 */
10646 { "vpunpcklwd", { XM, Vex, EXx } },
10649 /* VEX_W_0F62_P_2 */
10650 { "vpunpckldq", { XM, Vex, EXx } },
10653 /* VEX_W_0F63_P_2 */
10654 { "vpacksswb", { XM, Vex, EXx } },
10657 /* VEX_W_0F64_P_2 */
10658 { "vpcmpgtb", { XM, Vex, EXx } },
10661 /* VEX_W_0F65_P_2 */
10662 { "vpcmpgtw", { XM, Vex, EXx } },
10665 /* VEX_W_0F66_P_2 */
10666 { "vpcmpgtd", { XM, Vex, EXx } },
10669 /* VEX_W_0F67_P_2 */
10670 { "vpackuswb", { XM, Vex, EXx } },
10673 /* VEX_W_0F68_P_2 */
10674 { "vpunpckhbw", { XM, Vex, EXx } },
10677 /* VEX_W_0F69_P_2 */
10678 { "vpunpckhwd", { XM, Vex, EXx } },
10681 /* VEX_W_0F6A_P_2 */
10682 { "vpunpckhdq", { XM, Vex, EXx } },
10685 /* VEX_W_0F6B_P_2 */
10686 { "vpackssdw", { XM, Vex, EXx } },
10689 /* VEX_W_0F6C_P_2 */
10690 { "vpunpcklqdq", { XM, Vex, EXx } },
10693 /* VEX_W_0F6D_P_2 */
10694 { "vpunpckhqdq", { XM, Vex, EXx } },
10697 /* VEX_W_0F6F_P_1 */
10698 { "vmovdqu", { XM, EXx } },
10701 /* VEX_W_0F6F_P_2 */
10702 { "vmovdqa", { XM, EXx } },
10705 /* VEX_W_0F70_P_1 */
10706 { "vpshufhw", { XM, EXx, Ib } },
10709 /* VEX_W_0F70_P_2 */
10710 { "vpshufd", { XM, EXx, Ib } },
10713 /* VEX_W_0F70_P_3 */
10714 { "vpshuflw", { XM, EXx, Ib } },
10717 /* VEX_W_0F71_R_2_P_2 */
10718 { "vpsrlw", { Vex, XS, Ib } },
10721 /* VEX_W_0F71_R_4_P_2 */
10722 { "vpsraw", { Vex, XS, Ib } },
10725 /* VEX_W_0F71_R_6_P_2 */
10726 { "vpsllw", { Vex, XS, Ib } },
10729 /* VEX_W_0F72_R_2_P_2 */
10730 { "vpsrld", { Vex, XS, Ib } },
10733 /* VEX_W_0F72_R_4_P_2 */
10734 { "vpsrad", { Vex, XS, Ib } },
10737 /* VEX_W_0F72_R_6_P_2 */
10738 { "vpslld", { Vex, XS, Ib } },
10741 /* VEX_W_0F73_R_2_P_2 */
10742 { "vpsrlq", { Vex, XS, Ib } },
10745 /* VEX_W_0F73_R_3_P_2 */
10746 { "vpsrldq", { Vex, XS, Ib } },
10749 /* VEX_W_0F73_R_6_P_2 */
10750 { "vpsllq", { Vex, XS, Ib } },
10753 /* VEX_W_0F73_R_7_P_2 */
10754 { "vpslldq", { Vex, XS, Ib } },
10757 /* VEX_W_0F74_P_2 */
10758 { "vpcmpeqb", { XM, Vex, EXx } },
10761 /* VEX_W_0F75_P_2 */
10762 { "vpcmpeqw", { XM, Vex, EXx } },
10765 /* VEX_W_0F76_P_2 */
10766 { "vpcmpeqd", { XM, Vex, EXx } },
10769 /* VEX_W_0F77_P_0 */
10773 /* VEX_W_0F7C_P_2 */
10774 { "vhaddpd", { XM, Vex, EXx } },
10777 /* VEX_W_0F7C_P_3 */
10778 { "vhaddps", { XM, Vex, EXx } },
10781 /* VEX_W_0F7D_P_2 */
10782 { "vhsubpd", { XM, Vex, EXx } },
10785 /* VEX_W_0F7D_P_3 */
10786 { "vhsubps", { XM, Vex, EXx } },
10789 /* VEX_W_0F7E_P_1 */
10790 { "vmovq", { XMScalar, EXqScalar } },
10793 /* VEX_W_0F7F_P_1 */
10794 { "vmovdqu", { EXxS, XM } },
10797 /* VEX_W_0F7F_P_2 */
10798 { "vmovdqa", { EXxS, XM } },
10801 /* VEX_W_0F90_P_0_LEN_0 */
10802 { "kmovw", { MaskG, MaskE } },
10803 { "kmovq", { MaskG, MaskE } },
10806 /* VEX_W_0F90_P_2_LEN_0 */
10807 { "kmovb", { MaskG, MaskBDE } },
10808 { "kmovd", { MaskG, MaskBDE } },
10811 /* VEX_W_0F91_P_0_LEN_0 */
10812 { "kmovw", { Ew, MaskG } },
10813 { "kmovq", { Eq, MaskG } },
10816 /* VEX_W_0F91_P_2_LEN_0 */
10817 { "kmovb", { Eb, MaskG } },
10818 { "kmovd", { Ed, MaskG } },
10821 /* VEX_W_0F92_P_0_LEN_0 */
10822 { "kmovw", { MaskG, Rdq } },
10825 /* VEX_W_0F92_P_2_LEN_0 */
10826 { "kmovb", { MaskG, Rdq } },
10829 /* VEX_W_0F92_P_3_LEN_0 */
10830 { "kmovd", { MaskG, Rdq } },
10831 { "kmovq", { MaskG, Rdq } },
10834 /* VEX_W_0F93_P_0_LEN_0 */
10835 { "kmovw", { Gdq, MaskR } },
10838 /* VEX_W_0F93_P_2_LEN_0 */
10839 { "kmovb", { Gdq, MaskR } },
10842 /* VEX_W_0F93_P_3_LEN_0 */
10843 { "kmovd", { Gdq, MaskR } },
10844 { "kmovq", { Gdq, MaskR } },
10847 /* VEX_W_0F98_P_0_LEN_0 */
10848 { "kortestw", { MaskG, MaskR } },
10849 { "kortestq", { MaskG, MaskR } },
10852 /* VEX_W_0F98_P_2_LEN_0 */
10853 { "kortestb", { MaskG, MaskR } },
10854 { "kortestd", { MaskG, MaskR } },
10857 /* VEX_W_0F99_P_0_LEN_0 */
10858 { "ktestw", { MaskG, MaskR } },
10859 { "ktestq", { MaskG, MaskR } },
10862 /* VEX_W_0F99_P_2_LEN_0 */
10863 { "ktestb", { MaskG, MaskR } },
10864 { "ktestd", { MaskG, MaskR } },
10867 /* VEX_W_0FAE_R_2_M_0 */
10868 { "vldmxcsr", { Md } },
10871 /* VEX_W_0FAE_R_3_M_0 */
10872 { "vstmxcsr", { Md } },
10875 /* VEX_W_0FC2_P_0 */
10876 { "vcmpps", { XM, Vex, EXx, VCMP } },
10879 /* VEX_W_0FC2_P_1 */
10880 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP } },
10883 /* VEX_W_0FC2_P_2 */
10884 { "vcmppd", { XM, Vex, EXx, VCMP } },
10887 /* VEX_W_0FC2_P_3 */
10888 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP } },
10891 /* VEX_W_0FC4_P_2 */
10892 { "vpinsrw", { XM, Vex128, Edqw, Ib } },
10895 /* VEX_W_0FC5_P_2 */
10896 { "vpextrw", { Gdq, XS, Ib } },
10899 /* VEX_W_0FD0_P_2 */
10900 { "vaddsubpd", { XM, Vex, EXx } },
10903 /* VEX_W_0FD0_P_3 */
10904 { "vaddsubps", { XM, Vex, EXx } },
10907 /* VEX_W_0FD1_P_2 */
10908 { "vpsrlw", { XM, Vex, EXxmm } },
10911 /* VEX_W_0FD2_P_2 */
10912 { "vpsrld", { XM, Vex, EXxmm } },
10915 /* VEX_W_0FD3_P_2 */
10916 { "vpsrlq", { XM, Vex, EXxmm } },
10919 /* VEX_W_0FD4_P_2 */
10920 { "vpaddq", { XM, Vex, EXx } },
10923 /* VEX_W_0FD5_P_2 */
10924 { "vpmullw", { XM, Vex, EXx } },
10927 /* VEX_W_0FD6_P_2 */
10928 { "vmovq", { EXqScalarS, XMScalar } },
10931 /* VEX_W_0FD7_P_2_M_1 */
10932 { "vpmovmskb", { Gdq, XS } },
10935 /* VEX_W_0FD8_P_2 */
10936 { "vpsubusb", { XM, Vex, EXx } },
10939 /* VEX_W_0FD9_P_2 */
10940 { "vpsubusw", { XM, Vex, EXx } },
10943 /* VEX_W_0FDA_P_2 */
10944 { "vpminub", { XM, Vex, EXx } },
10947 /* VEX_W_0FDB_P_2 */
10948 { "vpand", { XM, Vex, EXx } },
10951 /* VEX_W_0FDC_P_2 */
10952 { "vpaddusb", { XM, Vex, EXx } },
10955 /* VEX_W_0FDD_P_2 */
10956 { "vpaddusw", { XM, Vex, EXx } },
10959 /* VEX_W_0FDE_P_2 */
10960 { "vpmaxub", { XM, Vex, EXx } },
10963 /* VEX_W_0FDF_P_2 */
10964 { "vpandn", { XM, Vex, EXx } },
10967 /* VEX_W_0FE0_P_2 */
10968 { "vpavgb", { XM, Vex, EXx } },
10971 /* VEX_W_0FE1_P_2 */
10972 { "vpsraw", { XM, Vex, EXxmm } },
10975 /* VEX_W_0FE2_P_2 */
10976 { "vpsrad", { XM, Vex, EXxmm } },
10979 /* VEX_W_0FE3_P_2 */
10980 { "vpavgw", { XM, Vex, EXx } },
10983 /* VEX_W_0FE4_P_2 */
10984 { "vpmulhuw", { XM, Vex, EXx } },
10987 /* VEX_W_0FE5_P_2 */
10988 { "vpmulhw", { XM, Vex, EXx } },
10991 /* VEX_W_0FE6_P_1 */
10992 { "vcvtdq2pd", { XM, EXxmmq } },
10995 /* VEX_W_0FE6_P_2 */
10996 { "vcvttpd2dq%XY", { XMM, EXx } },
10999 /* VEX_W_0FE6_P_3 */
11000 { "vcvtpd2dq%XY", { XMM, EXx } },
11003 /* VEX_W_0FE7_P_2_M_0 */
11004 { "vmovntdq", { Mx, XM } },
11007 /* VEX_W_0FE8_P_2 */
11008 { "vpsubsb", { XM, Vex, EXx } },
11011 /* VEX_W_0FE9_P_2 */
11012 { "vpsubsw", { XM, Vex, EXx } },
11015 /* VEX_W_0FEA_P_2 */
11016 { "vpminsw", { XM, Vex, EXx } },
11019 /* VEX_W_0FEB_P_2 */
11020 { "vpor", { XM, Vex, EXx } },
11023 /* VEX_W_0FEC_P_2 */
11024 { "vpaddsb", { XM, Vex, EXx } },
11027 /* VEX_W_0FED_P_2 */
11028 { "vpaddsw", { XM, Vex, EXx } },
11031 /* VEX_W_0FEE_P_2 */
11032 { "vpmaxsw", { XM, Vex, EXx } },
11035 /* VEX_W_0FEF_P_2 */
11036 { "vpxor", { XM, Vex, EXx } },
11039 /* VEX_W_0FF0_P_3_M_0 */
11040 { "vlddqu", { XM, M } },
11043 /* VEX_W_0FF1_P_2 */
11044 { "vpsllw", { XM, Vex, EXxmm } },
11047 /* VEX_W_0FF2_P_2 */
11048 { "vpslld", { XM, Vex, EXxmm } },
11051 /* VEX_W_0FF3_P_2 */
11052 { "vpsllq", { XM, Vex, EXxmm } },
11055 /* VEX_W_0FF4_P_2 */
11056 { "vpmuludq", { XM, Vex, EXx } },
11059 /* VEX_W_0FF5_P_2 */
11060 { "vpmaddwd", { XM, Vex, EXx } },
11063 /* VEX_W_0FF6_P_2 */
11064 { "vpsadbw", { XM, Vex, EXx } },
11067 /* VEX_W_0FF7_P_2 */
11068 { "vmaskmovdqu", { XM, XS } },
11071 /* VEX_W_0FF8_P_2 */
11072 { "vpsubb", { XM, Vex, EXx } },
11075 /* VEX_W_0FF9_P_2 */
11076 { "vpsubw", { XM, Vex, EXx } },
11079 /* VEX_W_0FFA_P_2 */
11080 { "vpsubd", { XM, Vex, EXx } },
11083 /* VEX_W_0FFB_P_2 */
11084 { "vpsubq", { XM, Vex, EXx } },
11087 /* VEX_W_0FFC_P_2 */
11088 { "vpaddb", { XM, Vex, EXx } },
11091 /* VEX_W_0FFD_P_2 */
11092 { "vpaddw", { XM, Vex, EXx } },
11095 /* VEX_W_0FFE_P_2 */
11096 { "vpaddd", { XM, Vex, EXx } },
11099 /* VEX_W_0F3800_P_2 */
11100 { "vpshufb", { XM, Vex, EXx } },
11103 /* VEX_W_0F3801_P_2 */
11104 { "vphaddw", { XM, Vex, EXx } },
11107 /* VEX_W_0F3802_P_2 */
11108 { "vphaddd", { XM, Vex, EXx } },
11111 /* VEX_W_0F3803_P_2 */
11112 { "vphaddsw", { XM, Vex, EXx } },
11115 /* VEX_W_0F3804_P_2 */
11116 { "vpmaddubsw", { XM, Vex, EXx } },
11119 /* VEX_W_0F3805_P_2 */
11120 { "vphsubw", { XM, Vex, EXx } },
11123 /* VEX_W_0F3806_P_2 */
11124 { "vphsubd", { XM, Vex, EXx } },
11127 /* VEX_W_0F3807_P_2 */
11128 { "vphsubsw", { XM, Vex, EXx } },
11131 /* VEX_W_0F3808_P_2 */
11132 { "vpsignb", { XM, Vex, EXx } },
11135 /* VEX_W_0F3809_P_2 */
11136 { "vpsignw", { XM, Vex, EXx } },
11139 /* VEX_W_0F380A_P_2 */
11140 { "vpsignd", { XM, Vex, EXx } },
11143 /* VEX_W_0F380B_P_2 */
11144 { "vpmulhrsw", { XM, Vex, EXx } },
11147 /* VEX_W_0F380C_P_2 */
11148 { "vpermilps", { XM, Vex, EXx } },
11151 /* VEX_W_0F380D_P_2 */
11152 { "vpermilpd", { XM, Vex, EXx } },
11155 /* VEX_W_0F380E_P_2 */
11156 { "vtestps", { XM, EXx } },
11159 /* VEX_W_0F380F_P_2 */
11160 { "vtestpd", { XM, EXx } },
11163 /* VEX_W_0F3816_P_2 */
11164 { "vpermps", { XM, Vex, EXx } },
11167 /* VEX_W_0F3817_P_2 */
11168 { "vptest", { XM, EXx } },
11171 /* VEX_W_0F3818_P_2 */
11172 { "vbroadcastss", { XM, EXxmm_md } },
11175 /* VEX_W_0F3819_P_2 */
11176 { "vbroadcastsd", { XM, EXxmm_mq } },
11179 /* VEX_W_0F381A_P_2_M_0 */
11180 { "vbroadcastf128", { XM, Mxmm } },
11183 /* VEX_W_0F381C_P_2 */
11184 { "vpabsb", { XM, EXx } },
11187 /* VEX_W_0F381D_P_2 */
11188 { "vpabsw", { XM, EXx } },
11191 /* VEX_W_0F381E_P_2 */
11192 { "vpabsd", { XM, EXx } },
11195 /* VEX_W_0F3820_P_2 */
11196 { "vpmovsxbw", { XM, EXxmmq } },
11199 /* VEX_W_0F3821_P_2 */
11200 { "vpmovsxbd", { XM, EXxmmqd } },
11203 /* VEX_W_0F3822_P_2 */
11204 { "vpmovsxbq", { XM, EXxmmdw } },
11207 /* VEX_W_0F3823_P_2 */
11208 { "vpmovsxwd", { XM, EXxmmq } },
11211 /* VEX_W_0F3824_P_2 */
11212 { "vpmovsxwq", { XM, EXxmmqd } },
11215 /* VEX_W_0F3825_P_2 */
11216 { "vpmovsxdq", { XM, EXxmmq } },
11219 /* VEX_W_0F3828_P_2 */
11220 { "vpmuldq", { XM, Vex, EXx } },
11223 /* VEX_W_0F3829_P_2 */
11224 { "vpcmpeqq", { XM, Vex, EXx } },
11227 /* VEX_W_0F382A_P_2_M_0 */
11228 { "vmovntdqa", { XM, Mx } },
11231 /* VEX_W_0F382B_P_2 */
11232 { "vpackusdw", { XM, Vex, EXx } },
11235 /* VEX_W_0F382C_P_2_M_0 */
11236 { "vmaskmovps", { XM, Vex, Mx } },
11239 /* VEX_W_0F382D_P_2_M_0 */
11240 { "vmaskmovpd", { XM, Vex, Mx } },
11243 /* VEX_W_0F382E_P_2_M_0 */
11244 { "vmaskmovps", { Mx, Vex, XM } },
11247 /* VEX_W_0F382F_P_2_M_0 */
11248 { "vmaskmovpd", { Mx, Vex, XM } },
11251 /* VEX_W_0F3830_P_2 */
11252 { "vpmovzxbw", { XM, EXxmmq } },
11255 /* VEX_W_0F3831_P_2 */
11256 { "vpmovzxbd", { XM, EXxmmqd } },
11259 /* VEX_W_0F3832_P_2 */
11260 { "vpmovzxbq", { XM, EXxmmdw } },
11263 /* VEX_W_0F3833_P_2 */
11264 { "vpmovzxwd", { XM, EXxmmq } },
11267 /* VEX_W_0F3834_P_2 */
11268 { "vpmovzxwq", { XM, EXxmmqd } },
11271 /* VEX_W_0F3835_P_2 */
11272 { "vpmovzxdq", { XM, EXxmmq } },
11275 /* VEX_W_0F3836_P_2 */
11276 { "vpermd", { XM, Vex, EXx } },
11279 /* VEX_W_0F3837_P_2 */
11280 { "vpcmpgtq", { XM, Vex, EXx } },
11283 /* VEX_W_0F3838_P_2 */
11284 { "vpminsb", { XM, Vex, EXx } },
11287 /* VEX_W_0F3839_P_2 */
11288 { "vpminsd", { XM, Vex, EXx } },
11291 /* VEX_W_0F383A_P_2 */
11292 { "vpminuw", { XM, Vex, EXx } },
11295 /* VEX_W_0F383B_P_2 */
11296 { "vpminud", { XM, Vex, EXx } },
11299 /* VEX_W_0F383C_P_2 */
11300 { "vpmaxsb", { XM, Vex, EXx } },
11303 /* VEX_W_0F383D_P_2 */
11304 { "vpmaxsd", { XM, Vex, EXx } },
11307 /* VEX_W_0F383E_P_2 */
11308 { "vpmaxuw", { XM, Vex, EXx } },
11311 /* VEX_W_0F383F_P_2 */
11312 { "vpmaxud", { XM, Vex, EXx } },
11315 /* VEX_W_0F3840_P_2 */
11316 { "vpmulld", { XM, Vex, EXx } },
11319 /* VEX_W_0F3841_P_2 */
11320 { "vphminposuw", { XM, EXx } },
11323 /* VEX_W_0F3846_P_2 */
11324 { "vpsravd", { XM, Vex, EXx } },
11327 /* VEX_W_0F3858_P_2 */
11328 { "vpbroadcastd", { XM, EXxmm_md } },
11331 /* VEX_W_0F3859_P_2 */
11332 { "vpbroadcastq", { XM, EXxmm_mq } },
11335 /* VEX_W_0F385A_P_2_M_0 */
11336 { "vbroadcasti128", { XM, Mxmm } },
11339 /* VEX_W_0F3878_P_2 */
11340 { "vpbroadcastb", { XM, EXxmm_mb } },
11343 /* VEX_W_0F3879_P_2 */
11344 { "vpbroadcastw", { XM, EXxmm_mw } },
11347 /* VEX_W_0F38DB_P_2 */
11348 { "vaesimc", { XM, EXx } },
11351 /* VEX_W_0F38DC_P_2 */
11352 { "vaesenc", { XM, Vex128, EXx } },
11355 /* VEX_W_0F38DD_P_2 */
11356 { "vaesenclast", { XM, Vex128, EXx } },
11359 /* VEX_W_0F38DE_P_2 */
11360 { "vaesdec", { XM, Vex128, EXx } },
11363 /* VEX_W_0F38DF_P_2 */
11364 { "vaesdeclast", { XM, Vex128, EXx } },
11367 /* VEX_W_0F3A00_P_2 */
11369 { "vpermq", { XM, EXx, Ib } },
11372 /* VEX_W_0F3A01_P_2 */
11374 { "vpermpd", { XM, EXx, Ib } },
11377 /* VEX_W_0F3A02_P_2 */
11378 { "vpblendd", { XM, Vex, EXx, Ib } },
11381 /* VEX_W_0F3A04_P_2 */
11382 { "vpermilps", { XM, EXx, Ib } },
11385 /* VEX_W_0F3A05_P_2 */
11386 { "vpermilpd", { XM, EXx, Ib } },
11389 /* VEX_W_0F3A06_P_2 */
11390 { "vperm2f128", { XM, Vex256, EXx, Ib } },
11393 /* VEX_W_0F3A08_P_2 */
11394 { "vroundps", { XM, EXx, Ib } },
11397 /* VEX_W_0F3A09_P_2 */
11398 { "vroundpd", { XM, EXx, Ib } },
11401 /* VEX_W_0F3A0A_P_2 */
11402 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib } },
11405 /* VEX_W_0F3A0B_P_2 */
11406 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib } },
11409 /* VEX_W_0F3A0C_P_2 */
11410 { "vblendps", { XM, Vex, EXx, Ib } },
11413 /* VEX_W_0F3A0D_P_2 */
11414 { "vblendpd", { XM, Vex, EXx, Ib } },
11417 /* VEX_W_0F3A0E_P_2 */
11418 { "vpblendw", { XM, Vex, EXx, Ib } },
11421 /* VEX_W_0F3A0F_P_2 */
11422 { "vpalignr", { XM, Vex, EXx, Ib } },
11425 /* VEX_W_0F3A14_P_2 */
11426 { "vpextrb", { Edqb, XM, Ib } },
11429 /* VEX_W_0F3A15_P_2 */
11430 { "vpextrw", { Edqw, XM, Ib } },
11433 /* VEX_W_0F3A18_P_2 */
11434 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },
11437 /* VEX_W_0F3A19_P_2 */
11438 { "vextractf128", { EXxmm, XM, Ib } },
11441 /* VEX_W_0F3A20_P_2 */
11442 { "vpinsrb", { XM, Vex128, Edqb, Ib } },
11445 /* VEX_W_0F3A21_P_2 */
11446 { "vinsertps", { XM, Vex128, EXd, Ib } },
11449 /* VEX_W_0F3A30_P_2_LEN_0 */
11450 { "kshiftrb", { MaskG, MaskR, Ib } },
11451 { "kshiftrw", { MaskG, MaskR, Ib } },
11454 /* VEX_W_0F3A31_P_2_LEN_0 */
11455 { "kshiftrd", { MaskG, MaskR, Ib } },
11456 { "kshiftrq", { MaskG, MaskR, Ib } },
11459 /* VEX_W_0F3A32_P_2_LEN_0 */
11460 { "kshiftlb", { MaskG, MaskR, Ib } },
11461 { "kshiftlw", { MaskG, MaskR, Ib } },
11464 /* VEX_W_0F3A33_P_2_LEN_0 */
11465 { "kshiftld", { MaskG, MaskR, Ib } },
11466 { "kshiftlq", { MaskG, MaskR, Ib } },
11469 /* VEX_W_0F3A38_P_2 */
11470 { "vinserti128", { XM, Vex256, EXxmm, Ib } },
11473 /* VEX_W_0F3A39_P_2 */
11474 { "vextracti128", { EXxmm, XM, Ib } },
11477 /* VEX_W_0F3A40_P_2 */
11478 { "vdpps", { XM, Vex, EXx, Ib } },
11481 /* VEX_W_0F3A41_P_2 */
11482 { "vdppd", { XM, Vex128, EXx, Ib } },
11485 /* VEX_W_0F3A42_P_2 */
11486 { "vmpsadbw", { XM, Vex, EXx, Ib } },
11489 /* VEX_W_0F3A44_P_2 */
11490 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } },
11493 /* VEX_W_0F3A46_P_2 */
11494 { "vperm2i128", { XM, Vex256, EXx, Ib } },
11497 /* VEX_W_0F3A48_P_2 */
11498 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11499 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11502 /* VEX_W_0F3A49_P_2 */
11503 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11504 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11507 /* VEX_W_0F3A4A_P_2 */
11508 { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
11511 /* VEX_W_0F3A4B_P_2 */
11512 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
11515 /* VEX_W_0F3A4C_P_2 */
11516 { "vpblendvb", { XM, Vex, EXx, XMVexI4 } },
11519 /* VEX_W_0F3A60_P_2 */
11520 { "vpcmpestrm", { XM, EXx, Ib } },
11523 /* VEX_W_0F3A61_P_2 */
11524 { "vpcmpestri", { XM, EXx, Ib } },
11527 /* VEX_W_0F3A62_P_2 */
11528 { "vpcmpistrm", { XM, EXx, Ib } },
11531 /* VEX_W_0F3A63_P_2 */
11532 { "vpcmpistri", { XM, EXx, Ib } },
11535 /* VEX_W_0F3ADF_P_2 */
11536 { "vaeskeygenassist", { XM, EXx, Ib } },
11538 #define NEED_VEX_W_TABLE
11539 #include "i386-dis-evex.h"
11540 #undef NEED_VEX_W_TABLE
11543 static const struct dis386 mod_table[][2] = {
11546 { "leaS", { Gv, M } },
11551 { RM_TABLE (RM_C6_REG_7) },
11556 { RM_TABLE (RM_C7_REG_7) },
11560 { "Jcall{T|}", { indirEp } },
11564 { "Jjmp{T|}", { indirEp } },
11567 /* MOD_0F01_REG_0 */
11568 { X86_64_TABLE (X86_64_0F01_REG_0) },
11569 { RM_TABLE (RM_0F01_REG_0) },
11572 /* MOD_0F01_REG_1 */
11573 { X86_64_TABLE (X86_64_0F01_REG_1) },
11574 { RM_TABLE (RM_0F01_REG_1) },
11577 /* MOD_0F01_REG_2 */
11578 { X86_64_TABLE (X86_64_0F01_REG_2) },
11579 { RM_TABLE (RM_0F01_REG_2) },
11582 /* MOD_0F01_REG_3 */
11583 { X86_64_TABLE (X86_64_0F01_REG_3) },
11584 { RM_TABLE (RM_0F01_REG_3) },
11587 /* MOD_0F01_REG_7 */
11588 { "invlpg", { Mb } },
11589 { RM_TABLE (RM_0F01_REG_7) },
11592 /* MOD_0F12_PREFIX_0 */
11593 { "movlps", { XM, EXq } },
11594 { "movhlps", { XM, EXq } },
11598 { "movlpX", { EXq, XM } },
11601 /* MOD_0F16_PREFIX_0 */
11602 { "movhps", { XM, EXq } },
11603 { "movlhps", { XM, EXq } },
11607 { "movhpX", { EXq, XM } },
11610 /* MOD_0F18_REG_0 */
11611 { "prefetchnta", { Mb } },
11614 /* MOD_0F18_REG_1 */
11615 { "prefetcht0", { Mb } },
11618 /* MOD_0F18_REG_2 */
11619 { "prefetcht1", { Mb } },
11622 /* MOD_0F18_REG_3 */
11623 { "prefetcht2", { Mb } },
11626 /* MOD_0F18_REG_4 */
11627 { "nop/reserved", { Mb } },
11630 /* MOD_0F18_REG_5 */
11631 { "nop/reserved", { Mb } },
11634 /* MOD_0F18_REG_6 */
11635 { "nop/reserved", { Mb } },
11638 /* MOD_0F18_REG_7 */
11639 { "nop/reserved", { Mb } },
11642 /* MOD_0F1A_PREFIX_0 */
11643 { "bndldx", { Gbnd, Ev_bnd } },
11644 { "nopQ", { Ev } },
11647 /* MOD_0F1B_PREFIX_0 */
11648 { "bndstx", { Ev_bnd, Gbnd } },
11649 { "nopQ", { Ev } },
11652 /* MOD_0F1B_PREFIX_1 */
11653 { "bndmk", { Gbnd, Ev_bnd } },
11654 { "nopQ", { Ev } },
11659 { "movL", { Rd, Td } },
11664 { "movL", { Td, Rd } },
11667 /* MOD_0F2B_PREFIX_0 */
11668 {"movntps", { Mx, XM } },
11671 /* MOD_0F2B_PREFIX_1 */
11672 {"movntss", { Md, XM } },
11675 /* MOD_0F2B_PREFIX_2 */
11676 {"movntpd", { Mx, XM } },
11679 /* MOD_0F2B_PREFIX_3 */
11680 {"movntsd", { Mq, XM } },
11685 { "movmskpX", { Gdq, XS } },
11688 /* MOD_0F71_REG_2 */
11690 { "psrlw", { MS, Ib } },
11693 /* MOD_0F71_REG_4 */
11695 { "psraw", { MS, Ib } },
11698 /* MOD_0F71_REG_6 */
11700 { "psllw", { MS, Ib } },
11703 /* MOD_0F72_REG_2 */
11705 { "psrld", { MS, Ib } },
11708 /* MOD_0F72_REG_4 */
11710 { "psrad", { MS, Ib } },
11713 /* MOD_0F72_REG_6 */
11715 { "pslld", { MS, Ib } },
11718 /* MOD_0F73_REG_2 */
11720 { "psrlq", { MS, Ib } },
11723 /* MOD_0F73_REG_3 */
11725 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11728 /* MOD_0F73_REG_6 */
11730 { "psllq", { MS, Ib } },
11733 /* MOD_0F73_REG_7 */
11735 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11738 /* MOD_0FAE_REG_0 */
11739 { "fxsave", { FXSAVE } },
11740 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11743 /* MOD_0FAE_REG_1 */
11744 { "fxrstor", { FXSAVE } },
11745 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11748 /* MOD_0FAE_REG_2 */
11749 { "ldmxcsr", { Md } },
11750 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11753 /* MOD_0FAE_REG_3 */
11754 { "stmxcsr", { Md } },
11755 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11758 /* MOD_0FAE_REG_4 */
11759 { "xsave", { FXSAVE } },
11762 /* MOD_0FAE_REG_5 */
11763 { "xrstor", { FXSAVE } },
11764 { RM_TABLE (RM_0FAE_REG_5) },
11767 /* MOD_0FAE_REG_6 */
11768 { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11769 { RM_TABLE (RM_0FAE_REG_6) },
11772 /* MOD_0FAE_REG_7 */
11773 { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11774 { RM_TABLE (RM_0FAE_REG_7) },
11778 { "lssS", { Gv, Mp } },
11782 { "lfsS", { Gv, Mp } },
11786 { "lgsS", { Gv, Mp } },
11789 /* MOD_0FC7_REG_3 */
11790 { "xrstors", { FXSAVE } },
11793 /* MOD_0FC7_REG_4 */
11794 { "xsavec", { FXSAVE } },
11797 /* MOD_0FC7_REG_5 */
11798 { "xsaves", { FXSAVE } },
11801 /* MOD_0FC7_REG_6 */
11802 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
11803 { "rdrand", { Ev } },
11806 /* MOD_0FC7_REG_7 */
11807 { "vmptrst", { Mq } },
11808 { "rdseed", { Ev } },
11813 { "pmovmskb", { Gdq, MS } },
11816 /* MOD_0FE7_PREFIX_2 */
11817 { "movntdq", { Mx, XM } },
11820 /* MOD_0FF0_PREFIX_3 */
11821 { "lddqu", { XM, M } },
11824 /* MOD_0F382A_PREFIX_2 */
11825 { "movntdqa", { XM, Mx } },
11829 { "bound{S|}", { Gv, Ma } },
11830 { EVEX_TABLE (EVEX_0F) },
11834 { "lesS", { Gv, Mp } },
11835 { VEX_C4_TABLE (VEX_0F) },
11839 { "ldsS", { Gv, Mp } },
11840 { VEX_C5_TABLE (VEX_0F) },
11843 /* MOD_VEX_0F12_PREFIX_0 */
11844 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11845 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11849 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11852 /* MOD_VEX_0F16_PREFIX_0 */
11853 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11854 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11858 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11862 { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11867 { VEX_W_TABLE (VEX_W_0F50_M_0) },
11870 /* MOD_VEX_0F71_REG_2 */
11872 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11875 /* MOD_VEX_0F71_REG_4 */
11877 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11880 /* MOD_VEX_0F71_REG_6 */
11882 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11885 /* MOD_VEX_0F72_REG_2 */
11887 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11890 /* MOD_VEX_0F72_REG_4 */
11892 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11895 /* MOD_VEX_0F72_REG_6 */
11897 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11900 /* MOD_VEX_0F73_REG_2 */
11902 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11905 /* MOD_VEX_0F73_REG_3 */
11907 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11910 /* MOD_VEX_0F73_REG_6 */
11912 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11915 /* MOD_VEX_0F73_REG_7 */
11917 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11920 /* MOD_VEX_0FAE_REG_2 */
11921 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11924 /* MOD_VEX_0FAE_REG_3 */
11925 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11928 /* MOD_VEX_0FD7_PREFIX_2 */
11930 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11933 /* MOD_VEX_0FE7_PREFIX_2 */
11934 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11937 /* MOD_VEX_0FF0_PREFIX_3 */
11938 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11941 /* MOD_VEX_0F381A_PREFIX_2 */
11942 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11945 /* MOD_VEX_0F382A_PREFIX_2 */
11946 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11949 /* MOD_VEX_0F382C_PREFIX_2 */
11950 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11953 /* MOD_VEX_0F382D_PREFIX_2 */
11954 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11957 /* MOD_VEX_0F382E_PREFIX_2 */
11958 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11961 /* MOD_VEX_0F382F_PREFIX_2 */
11962 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11965 /* MOD_VEX_0F385A_PREFIX_2 */
11966 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11969 /* MOD_VEX_0F388C_PREFIX_2 */
11970 { "vpmaskmov%LW", { XM, Vex, Mx } },
11973 /* MOD_VEX_0F388E_PREFIX_2 */
11974 { "vpmaskmov%LW", { Mx, Vex, XM } },
11976 #define NEED_MOD_TABLE
11977 #include "i386-dis-evex.h"
11978 #undef NEED_MOD_TABLE
11981 static const struct dis386 rm_table[][8] = {
11984 { "xabort", { Skip_MODRM, Ib } },
11988 { "xbeginT", { Skip_MODRM, Jv } },
11991 /* RM_0F01_REG_0 */
11993 { "vmcall", { Skip_MODRM } },
11994 { "vmlaunch", { Skip_MODRM } },
11995 { "vmresume", { Skip_MODRM } },
11996 { "vmxoff", { Skip_MODRM } },
11999 /* RM_0F01_REG_1 */
12000 { "monitor", { { OP_Monitor, 0 } } },
12001 { "mwait", { { OP_Mwait, 0 } } },
12002 { "clac", { Skip_MODRM } },
12003 { "stac", { Skip_MODRM } },
12007 { "encls", { Skip_MODRM } },
12010 /* RM_0F01_REG_2 */
12011 { "xgetbv", { Skip_MODRM } },
12012 { "xsetbv", { Skip_MODRM } },
12015 { "vmfunc", { Skip_MODRM } },
12016 { "xend", { Skip_MODRM } },
12017 { "xtest", { Skip_MODRM } },
12018 { "enclu", { Skip_MODRM } },
12021 /* RM_0F01_REG_3 */
12022 { "vmrun", { Skip_MODRM } },
12023 { "vmmcall", { Skip_MODRM } },
12024 { "vmload", { Skip_MODRM } },
12025 { "vmsave", { Skip_MODRM } },
12026 { "stgi", { Skip_MODRM } },
12027 { "clgi", { Skip_MODRM } },
12028 { "skinit", { Skip_MODRM } },
12029 { "invlpga", { Skip_MODRM } },
12032 /* RM_0F01_REG_7 */
12033 { "swapgs", { Skip_MODRM } },
12034 { "rdtscp", { Skip_MODRM } },
12037 /* RM_0FAE_REG_5 */
12038 { "lfence", { Skip_MODRM } },
12041 /* RM_0FAE_REG_6 */
12042 { "mfence", { Skip_MODRM } },
12045 /* RM_0FAE_REG_7 */
12046 { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) },
12050 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12052 /* We use the high bit to indicate different name for the same
12054 #define REP_PREFIX (0xf3 | 0x100)
12055 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12056 #define XRELEASE_PREFIX (0xf3 | 0x400)
12057 #define BND_PREFIX (0xf2 | 0x400)
12062 int newrex, i, length;
12068 last_lock_prefix = -1;
12069 last_repz_prefix = -1;
12070 last_repnz_prefix = -1;
12071 last_data_prefix = -1;
12072 last_addr_prefix = -1;
12073 last_rex_prefix = -1;
12074 last_seg_prefix = -1;
12076 active_seg_prefix = 0;
12077 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12078 all_prefixes[i] = 0;
12081 /* The maximum instruction length is 15bytes. */
12082 while (length < MAX_CODE_LENGTH - 1)
12084 FETCH_DATA (the_info, codep + 1);
12088 /* REX prefixes family. */
12105 if (address_mode == mode_64bit)
12109 last_rex_prefix = i;
12112 prefixes |= PREFIX_REPZ;
12113 last_repz_prefix = i;
12116 prefixes |= PREFIX_REPNZ;
12117 last_repnz_prefix = i;
12120 prefixes |= PREFIX_LOCK;
12121 last_lock_prefix = i;
12124 prefixes |= PREFIX_CS;
12125 last_seg_prefix = i;
12126 active_seg_prefix = PREFIX_CS;
12129 prefixes |= PREFIX_SS;
12130 last_seg_prefix = i;
12131 active_seg_prefix = PREFIX_SS;
12134 prefixes |= PREFIX_DS;
12135 last_seg_prefix = i;
12136 active_seg_prefix = PREFIX_DS;
12139 prefixes |= PREFIX_ES;
12140 last_seg_prefix = i;
12141 active_seg_prefix = PREFIX_ES;
12144 prefixes |= PREFIX_FS;
12145 last_seg_prefix = i;
12146 active_seg_prefix = PREFIX_FS;
12149 prefixes |= PREFIX_GS;
12150 last_seg_prefix = i;
12151 active_seg_prefix = PREFIX_GS;
12154 prefixes |= PREFIX_DATA;
12155 last_data_prefix = i;
12158 prefixes |= PREFIX_ADDR;
12159 last_addr_prefix = i;
12162 /* fwait is really an instruction. If there are prefixes
12163 before the fwait, they belong to the fwait, *not* to the
12164 following instruction. */
12166 if (prefixes || rex)
12168 prefixes |= PREFIX_FWAIT;
12170 /* This ensures that the previous REX prefixes are noticed
12171 as unused prefixes, as in the return case below. */
12175 prefixes = PREFIX_FWAIT;
12180 /* Rex is ignored when followed by another prefix. */
12186 if (*codep != FWAIT_OPCODE)
12187 all_prefixes[i++] = *codep;
12195 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12198 static const char *
12199 prefix_name (int pref, int sizeflag)
12201 static const char *rexes [16] =
12204 "rex.B", /* 0x41 */
12205 "rex.X", /* 0x42 */
12206 "rex.XB", /* 0x43 */
12207 "rex.R", /* 0x44 */
12208 "rex.RB", /* 0x45 */
12209 "rex.RX", /* 0x46 */
12210 "rex.RXB", /* 0x47 */
12211 "rex.W", /* 0x48 */
12212 "rex.WB", /* 0x49 */
12213 "rex.WX", /* 0x4a */
12214 "rex.WXB", /* 0x4b */
12215 "rex.WR", /* 0x4c */
12216 "rex.WRB", /* 0x4d */
12217 "rex.WRX", /* 0x4e */
12218 "rex.WRXB", /* 0x4f */
12223 /* REX prefixes family. */
12240 return rexes [pref - 0x40];
12260 return (sizeflag & DFLAG) ? "data16" : "data32";
12262 if (address_mode == mode_64bit)
12263 return (sizeflag & AFLAG) ? "addr32" : "addr64";
12265 return (sizeflag & AFLAG) ? "addr16" : "addr32";
12270 case XACQUIRE_PREFIX:
12272 case XRELEASE_PREFIX:
12281 static char op_out[MAX_OPERANDS][100];
12282 static int op_ad, op_index[MAX_OPERANDS];
12283 static int two_source_ops;
12284 static bfd_vma op_address[MAX_OPERANDS];
12285 static bfd_vma op_riprel[MAX_OPERANDS];
12286 static bfd_vma start_pc;
12289 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12290 * (see topic "Redundant prefixes" in the "Differences from 8086"
12291 * section of the "Virtual 8086 Mode" chapter.)
12292 * 'pc' should be the address of this instruction, it will
12293 * be used to print the target address if this is a relative jump or call
12294 * The function returns the length of this instruction in bytes.
12297 static char intel_syntax;
12298 static char intel_mnemonic = !SYSV386_COMPAT;
12299 static char open_char;
12300 static char close_char;
12301 static char separator_char;
12302 static char scale_char;
12304 /* Here for backwards compatibility. When gdb stops using
12305 print_insn_i386_att and print_insn_i386_intel these functions can
12306 disappear, and print_insn_i386 be merged into print_insn. */
12308 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12312 return print_insn (pc, info);
12316 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12320 return print_insn (pc, info);
12324 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12328 return print_insn (pc, info);
12332 print_i386_disassembler_options (FILE *stream)
12334 fprintf (stream, _("\n\
12335 The following i386/x86-64 specific disassembler options are supported for use\n\
12336 with the -M switch (multiple options should be separated by commas):\n"));
12338 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
12339 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
12340 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
12341 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
12342 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
12343 fprintf (stream, _(" att-mnemonic\n"
12344 " Display instruction in AT&T mnemonic\n"));
12345 fprintf (stream, _(" intel-mnemonic\n"
12346 " Display instruction in Intel mnemonic\n"));
12347 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
12348 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
12349 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
12350 fprintf (stream, _(" data32 Assume 32bit data size\n"));
12351 fprintf (stream, _(" data16 Assume 16bit data size\n"));
12352 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12356 static const struct dis386 bad_opcode = { "(bad)", { XX } };
12358 /* Get a pointer to struct dis386 with a valid name. */
12360 static const struct dis386 *
12361 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12363 int vindex, vex_table_index;
12365 if (dp->name != NULL)
12368 switch (dp->op[0].bytemode)
12370 case USE_REG_TABLE:
12371 dp = ®_table[dp->op[1].bytemode][modrm.reg];
12374 case USE_MOD_TABLE:
12375 vindex = modrm.mod == 0x3 ? 1 : 0;
12376 dp = &mod_table[dp->op[1].bytemode][vindex];
12380 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12383 case USE_PREFIX_TABLE:
12386 /* The prefix in VEX is implicit. */
12387 switch (vex.prefix)
12392 case REPE_PREFIX_OPCODE:
12395 case DATA_PREFIX_OPCODE:
12398 case REPNE_PREFIX_OPCODE:
12408 int last_prefix = -1;
12411 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12412 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12414 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12416 if (last_repz_prefix > last_repnz_prefix)
12419 prefix = PREFIX_REPZ;
12420 last_prefix = last_repz_prefix;
12425 prefix = PREFIX_REPNZ;
12426 last_prefix = last_repnz_prefix;
12429 /* Ignore the invalid index if it isn't mandatory. */
12430 if (!mandatory_prefix
12431 && (prefix_table[dp->op[1].bytemode][vindex].name
12433 && (prefix_table[dp->op[1].bytemode][vindex].op[0].bytemode
12438 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12441 prefix = PREFIX_DATA;
12442 last_prefix = last_data_prefix;
12447 used_prefixes |= prefix;
12448 all_prefixes[last_prefix] = 0;
12451 dp = &prefix_table[dp->op[1].bytemode][vindex];
12454 case USE_X86_64_TABLE:
12455 vindex = address_mode == mode_64bit ? 1 : 0;
12456 dp = &x86_64_table[dp->op[1].bytemode][vindex];
12459 case USE_3BYTE_TABLE:
12460 FETCH_DATA (info, codep + 2);
12462 dp = &three_byte_table[dp->op[1].bytemode][vindex];
12464 modrm.mod = (*codep >> 6) & 3;
12465 modrm.reg = (*codep >> 3) & 7;
12466 modrm.rm = *codep & 7;
12469 case USE_VEX_LEN_TABLE:
12473 switch (vex.length)
12486 dp = &vex_len_table[dp->op[1].bytemode][vindex];
12489 case USE_XOP_8F_TABLE:
12490 FETCH_DATA (info, codep + 3);
12491 /* All bits in the REX prefix are ignored. */
12493 rex = ~(*codep >> 5) & 0x7;
12495 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12496 switch ((*codep & 0x1f))
12502 vex_table_index = XOP_08;
12505 vex_table_index = XOP_09;
12508 vex_table_index = XOP_0A;
12512 vex.w = *codep & 0x80;
12513 if (vex.w && address_mode == mode_64bit)
12516 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12517 if (address_mode != mode_64bit
12518 && vex.register_specifier > 0x7)
12524 vex.length = (*codep & 0x4) ? 256 : 128;
12525 switch ((*codep & 0x3))
12531 vex.prefix = DATA_PREFIX_OPCODE;
12534 vex.prefix = REPE_PREFIX_OPCODE;
12537 vex.prefix = REPNE_PREFIX_OPCODE;
12544 dp = &xop_table[vex_table_index][vindex];
12547 FETCH_DATA (info, codep + 1);
12548 modrm.mod = (*codep >> 6) & 3;
12549 modrm.reg = (*codep >> 3) & 7;
12550 modrm.rm = *codep & 7;
12553 case USE_VEX_C4_TABLE:
12555 FETCH_DATA (info, codep + 3);
12556 /* All bits in the REX prefix are ignored. */
12558 rex = ~(*codep >> 5) & 0x7;
12559 switch ((*codep & 0x1f))
12565 vex_table_index = VEX_0F;
12568 vex_table_index = VEX_0F38;
12571 vex_table_index = VEX_0F3A;
12575 vex.w = *codep & 0x80;
12576 if (vex.w && address_mode == mode_64bit)
12579 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12580 if (address_mode != mode_64bit
12581 && vex.register_specifier > 0x7)
12587 vex.length = (*codep & 0x4) ? 256 : 128;
12588 switch ((*codep & 0x3))
12594 vex.prefix = DATA_PREFIX_OPCODE;
12597 vex.prefix = REPE_PREFIX_OPCODE;
12600 vex.prefix = REPNE_PREFIX_OPCODE;
12607 dp = &vex_table[vex_table_index][vindex];
12609 /* There is no MODRM byte for VEX [82|77]. */
12610 if (vindex != 0x77 && vindex != 0x82)
12612 FETCH_DATA (info, codep + 1);
12613 modrm.mod = (*codep >> 6) & 3;
12614 modrm.reg = (*codep >> 3) & 7;
12615 modrm.rm = *codep & 7;
12619 case USE_VEX_C5_TABLE:
12621 FETCH_DATA (info, codep + 2);
12622 /* All bits in the REX prefix are ignored. */
12624 rex = (*codep & 0x80) ? 0 : REX_R;
12626 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12627 if (address_mode != mode_64bit
12628 && vex.register_specifier > 0x7)
12636 vex.length = (*codep & 0x4) ? 256 : 128;
12637 switch ((*codep & 0x3))
12643 vex.prefix = DATA_PREFIX_OPCODE;
12646 vex.prefix = REPE_PREFIX_OPCODE;
12649 vex.prefix = REPNE_PREFIX_OPCODE;
12656 dp = &vex_table[dp->op[1].bytemode][vindex];
12658 /* There is no MODRM byte for VEX [82|77]. */
12659 if (vindex != 0x77 && vindex != 0x82)
12661 FETCH_DATA (info, codep + 1);
12662 modrm.mod = (*codep >> 6) & 3;
12663 modrm.reg = (*codep >> 3) & 7;
12664 modrm.rm = *codep & 7;
12668 case USE_VEX_W_TABLE:
12672 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12675 case USE_EVEX_TABLE:
12676 two_source_ops = 0;
12679 FETCH_DATA (info, codep + 4);
12680 /* All bits in the REX prefix are ignored. */
12682 /* The first byte after 0x62. */
12683 rex = ~(*codep >> 5) & 0x7;
12684 vex.r = *codep & 0x10;
12685 switch ((*codep & 0xf))
12688 return &bad_opcode;
12690 vex_table_index = EVEX_0F;
12693 vex_table_index = EVEX_0F38;
12696 vex_table_index = EVEX_0F3A;
12700 /* The second byte after 0x62. */
12702 vex.w = *codep & 0x80;
12703 if (vex.w && address_mode == mode_64bit)
12706 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12707 if (address_mode != mode_64bit)
12709 /* In 16/32-bit mode silently ignore following bits. */
12713 vex.register_specifier &= 0x7;
12717 if (!(*codep & 0x4))
12718 return &bad_opcode;
12720 switch ((*codep & 0x3))
12726 vex.prefix = DATA_PREFIX_OPCODE;
12729 vex.prefix = REPE_PREFIX_OPCODE;
12732 vex.prefix = REPNE_PREFIX_OPCODE;
12736 /* The third byte after 0x62. */
12739 /* Remember the static rounding bits. */
12740 vex.ll = (*codep >> 5) & 3;
12741 vex.b = (*codep & 0x10) != 0;
12743 vex.v = *codep & 0x8;
12744 vex.mask_register_specifier = *codep & 0x7;
12745 vex.zeroing = *codep & 0x80;
12751 dp = &evex_table[vex_table_index][vindex];
12753 FETCH_DATA (info, codep + 1);
12754 modrm.mod = (*codep >> 6) & 3;
12755 modrm.reg = (*codep >> 3) & 7;
12756 modrm.rm = *codep & 7;
12758 /* Set vector length. */
12759 if (modrm.mod == 3 && vex.b)
12775 return &bad_opcode;
12788 if (dp->name != NULL)
12791 return get_valid_dis386 (dp, info);
12795 get_sib (disassemble_info *info, int sizeflag)
12797 /* If modrm.mod == 3, operand must be register. */
12799 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12803 FETCH_DATA (info, codep + 2);
12804 sib.index = (codep [1] >> 3) & 7;
12805 sib.scale = (codep [1] >> 6) & 3;
12806 sib.base = codep [1] & 7;
12811 print_insn (bfd_vma pc, disassemble_info *info)
12813 const struct dis386 *dp;
12815 char *op_txt[MAX_OPERANDS];
12817 int sizeflag, orig_sizeflag;
12819 struct dis_private priv;
12822 priv.orig_sizeflag = AFLAG | DFLAG;
12823 if ((info->mach & bfd_mach_i386_i386) != 0)
12824 address_mode = mode_32bit;
12825 else if (info->mach == bfd_mach_i386_i8086)
12827 address_mode = mode_16bit;
12828 priv.orig_sizeflag = 0;
12831 address_mode = mode_64bit;
12833 if (intel_syntax == (char) -1)
12834 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12836 for (p = info->disassembler_options; p != NULL; )
12838 if (CONST_STRNEQ (p, "x86-64"))
12840 address_mode = mode_64bit;
12841 priv.orig_sizeflag = AFLAG | DFLAG;
12843 else if (CONST_STRNEQ (p, "i386"))
12845 address_mode = mode_32bit;
12846 priv.orig_sizeflag = AFLAG | DFLAG;
12848 else if (CONST_STRNEQ (p, "i8086"))
12850 address_mode = mode_16bit;
12851 priv.orig_sizeflag = 0;
12853 else if (CONST_STRNEQ (p, "intel"))
12856 if (CONST_STRNEQ (p + 5, "-mnemonic"))
12857 intel_mnemonic = 1;
12859 else if (CONST_STRNEQ (p, "att"))
12862 if (CONST_STRNEQ (p + 3, "-mnemonic"))
12863 intel_mnemonic = 0;
12865 else if (CONST_STRNEQ (p, "addr"))
12867 if (address_mode == mode_64bit)
12869 if (p[4] == '3' && p[5] == '2')
12870 priv.orig_sizeflag &= ~AFLAG;
12871 else if (p[4] == '6' && p[5] == '4')
12872 priv.orig_sizeflag |= AFLAG;
12876 if (p[4] == '1' && p[5] == '6')
12877 priv.orig_sizeflag &= ~AFLAG;
12878 else if (p[4] == '3' && p[5] == '2')
12879 priv.orig_sizeflag |= AFLAG;
12882 else if (CONST_STRNEQ (p, "data"))
12884 if (p[4] == '1' && p[5] == '6')
12885 priv.orig_sizeflag &= ~DFLAG;
12886 else if (p[4] == '3' && p[5] == '2')
12887 priv.orig_sizeflag |= DFLAG;
12889 else if (CONST_STRNEQ (p, "suffix"))
12890 priv.orig_sizeflag |= SUFFIX_ALWAYS;
12892 p = strchr (p, ',');
12899 names64 = intel_names64;
12900 names32 = intel_names32;
12901 names16 = intel_names16;
12902 names8 = intel_names8;
12903 names8rex = intel_names8rex;
12904 names_seg = intel_names_seg;
12905 names_mm = intel_names_mm;
12906 names_bnd = intel_names_bnd;
12907 names_xmm = intel_names_xmm;
12908 names_ymm = intel_names_ymm;
12909 names_zmm = intel_names_zmm;
12910 index64 = intel_index64;
12911 index32 = intel_index32;
12912 names_mask = intel_names_mask;
12913 index16 = intel_index16;
12916 separator_char = '+';
12921 names64 = att_names64;
12922 names32 = att_names32;
12923 names16 = att_names16;
12924 names8 = att_names8;
12925 names8rex = att_names8rex;
12926 names_seg = att_names_seg;
12927 names_mm = att_names_mm;
12928 names_bnd = att_names_bnd;
12929 names_xmm = att_names_xmm;
12930 names_ymm = att_names_ymm;
12931 names_zmm = att_names_zmm;
12932 index64 = att_index64;
12933 index32 = att_index32;
12934 names_mask = att_names_mask;
12935 index16 = att_index16;
12938 separator_char = ',';
12942 /* The output looks better if we put 7 bytes on a line, since that
12943 puts most long word instructions on a single line. Use 8 bytes
12945 if ((info->mach & bfd_mach_l1om) != 0)
12946 info->bytes_per_line = 8;
12948 info->bytes_per_line = 7;
12950 info->private_data = &priv;
12951 priv.max_fetched = priv.the_buffer;
12952 priv.insn_start = pc;
12955 for (i = 0; i < MAX_OPERANDS; ++i)
12963 start_codep = priv.the_buffer;
12964 codep = priv.the_buffer;
12966 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12970 /* Getting here means we tried for data but didn't get it. That
12971 means we have an incomplete instruction of some sort. Just
12972 print the first byte as a prefix or a .byte pseudo-op. */
12973 if (codep > priv.the_buffer)
12975 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12977 (*info->fprintf_func) (info->stream, "%s", name);
12980 /* Just print the first byte as a .byte instruction. */
12981 (*info->fprintf_func) (info->stream, ".byte 0x%x",
12982 (unsigned int) priv.the_buffer[0]);
12992 sizeflag = priv.orig_sizeflag;
12994 if (!ckprefix () || rex_used)
12996 /* Too many prefixes or unused REX prefixes. */
12998 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13000 (*info->fprintf_func) (info->stream, "%s%s",
13002 prefix_name (all_prefixes[i], sizeflag));
13006 insn_codep = codep;
13008 FETCH_DATA (info, codep + 1);
13009 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13011 if (((prefixes & PREFIX_FWAIT)
13012 && ((*codep < 0xd8) || (*codep > 0xdf))))
13014 /* Handle prefixes before fwait. */
13015 for (i = 0; i < fwait_prefix && all_prefixes[i];
13017 (*info->fprintf_func) (info->stream, "%s ",
13018 prefix_name (all_prefixes[i], sizeflag));
13019 (*info->fprintf_func) (info->stream, "fwait");
13023 if (*codep == 0x0f)
13025 unsigned char threebyte;
13026 FETCH_DATA (info, codep + 2);
13027 threebyte = *++codep;
13028 dp = &dis386_twobyte[threebyte];
13029 need_modrm = twobyte_has_modrm[*codep];
13030 mandatory_prefix = twobyte_has_mandatory_prefix[*codep];
13035 dp = &dis386[*codep];
13036 need_modrm = onebyte_has_modrm[*codep];
13037 mandatory_prefix = 0;
13041 /* Save sizeflag for printing the extra prefixes later before updating
13042 it for mnemonic and operand processing. The prefix names depend
13043 only on the address mode. */
13044 orig_sizeflag = sizeflag;
13045 if (prefixes & PREFIX_ADDR)
13047 if ((prefixes & PREFIX_DATA))
13053 FETCH_DATA (info, codep + 1);
13054 modrm.mod = (*codep >> 6) & 3;
13055 modrm.reg = (*codep >> 3) & 7;
13056 modrm.rm = *codep & 7;
13064 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13066 get_sib (info, sizeflag);
13067 dofloat (sizeflag);
13071 dp = get_valid_dis386 (dp, info);
13072 if (dp != NULL && putop (dp->name, sizeflag) == 0)
13074 get_sib (info, sizeflag);
13075 for (i = 0; i < MAX_OPERANDS; ++i)
13078 op_ad = MAX_OPERANDS - 1 - i;
13080 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13081 /* For EVEX instruction after the last operand masking
13082 should be printed. */
13083 if (i == 0 && vex.evex)
13085 /* Don't print {%k0}. */
13086 if (vex.mask_register_specifier)
13089 oappend (names_mask[vex.mask_register_specifier]);
13099 /* Check if the REX prefix is used. */
13100 if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13101 all_prefixes[last_rex_prefix] = 0;
13103 /* Check if the SEG prefix is used. */
13104 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13105 | PREFIX_FS | PREFIX_GS)) != 0
13106 && (used_prefixes & active_seg_prefix) != 0)
13107 all_prefixes[last_seg_prefix] = 0;
13109 /* Check if the ADDR prefix is used. */
13110 if ((prefixes & PREFIX_ADDR) != 0
13111 && (used_prefixes & PREFIX_ADDR) != 0)
13112 all_prefixes[last_addr_prefix] = 0;
13114 /* Check if the DATA prefix is used. */
13115 if ((prefixes & PREFIX_DATA) != 0
13116 && (used_prefixes & PREFIX_DATA) != 0)
13117 all_prefixes[last_data_prefix] = 0;
13119 /* Print the extra prefixes. */
13121 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13122 if (all_prefixes[i])
13125 name = prefix_name (all_prefixes[i], orig_sizeflag);
13128 prefix_length += strlen (name) + 1;
13129 (*info->fprintf_func) (info->stream, "%s ", name);
13132 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13133 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13134 used by putop and MMX/SSE operand and may be overriden by the
13135 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13137 if (mandatory_prefix
13138 && dp != &bad_opcode
13140 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13142 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13144 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13146 && (used_prefixes & PREFIX_DATA) == 0))))
13148 (*info->fprintf_func) (info->stream, "(bad)");
13149 return end_codep - priv.the_buffer;
13152 /* Check maximum code length. */
13153 if ((codep - start_codep) > MAX_CODE_LENGTH)
13155 (*info->fprintf_func) (info->stream, "(bad)");
13156 return MAX_CODE_LENGTH;
13159 obufp = mnemonicendp;
13160 for (i = strlen (obuf) + prefix_length; i < 6; i++)
13163 (*info->fprintf_func) (info->stream, "%s", obuf);
13165 /* The enter and bound instructions are printed with operands in the same
13166 order as the intel book; everything else is printed in reverse order. */
13167 if (intel_syntax || two_source_ops)
13171 for (i = 0; i < MAX_OPERANDS; ++i)
13172 op_txt[i] = op_out[i];
13174 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13176 op_ad = op_index[i];
13177 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13178 op_index[MAX_OPERANDS - 1 - i] = op_ad;
13179 riprel = op_riprel[i];
13180 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13181 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13186 for (i = 0; i < MAX_OPERANDS; ++i)
13187 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13191 for (i = 0; i < MAX_OPERANDS; ++i)
13195 (*info->fprintf_func) (info->stream, ",");
13196 if (op_index[i] != -1 && !op_riprel[i])
13197 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13199 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13203 for (i = 0; i < MAX_OPERANDS; i++)
13204 if (op_index[i] != -1 && op_riprel[i])
13206 (*info->fprintf_func) (info->stream, " # ");
13207 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
13208 + op_address[op_index[i]]), info);
13211 return codep - priv.the_buffer;
13214 static const char *float_mem[] = {
13289 static const unsigned char float_mem_mode[] = {
13364 #define ST { OP_ST, 0 }
13365 #define STi { OP_STi, 0 }
13367 #define FGRPd9_2 NULL, { { NULL, 0 } }
13368 #define FGRPd9_4 NULL, { { NULL, 1 } }
13369 #define FGRPd9_5 NULL, { { NULL, 2 } }
13370 #define FGRPd9_6 NULL, { { NULL, 3 } }
13371 #define FGRPd9_7 NULL, { { NULL, 4 } }
13372 #define FGRPda_5 NULL, { { NULL, 5 } }
13373 #define FGRPdb_4 NULL, { { NULL, 6 } }
13374 #define FGRPde_3 NULL, { { NULL, 7 } }
13375 #define FGRPdf_4 NULL, { { NULL, 8 } }
13377 static const struct dis386 float_reg[][8] = {
13380 { "fadd", { ST, STi } },
13381 { "fmul", { ST, STi } },
13382 { "fcom", { STi } },
13383 { "fcomp", { STi } },
13384 { "fsub", { ST, STi } },
13385 { "fsubr", { ST, STi } },
13386 { "fdiv", { ST, STi } },
13387 { "fdivr", { ST, STi } },
13391 { "fld", { STi } },
13392 { "fxch", { STi } },
13402 { "fcmovb", { ST, STi } },
13403 { "fcmove", { ST, STi } },
13404 { "fcmovbe",{ ST, STi } },
13405 { "fcmovu", { ST, STi } },
13413 { "fcmovnb",{ ST, STi } },
13414 { "fcmovne",{ ST, STi } },
13415 { "fcmovnbe",{ ST, STi } },
13416 { "fcmovnu",{ ST, STi } },
13418 { "fucomi", { ST, STi } },
13419 { "fcomi", { ST, STi } },
13424 { "fadd", { STi, ST } },
13425 { "fmul", { STi, ST } },
13428 { "fsub!M", { STi, ST } },
13429 { "fsubM", { STi, ST } },
13430 { "fdiv!M", { STi, ST } },
13431 { "fdivM", { STi, ST } },
13435 { "ffree", { STi } },
13437 { "fst", { STi } },
13438 { "fstp", { STi } },
13439 { "fucom", { STi } },
13440 { "fucomp", { STi } },
13446 { "faddp", { STi, ST } },
13447 { "fmulp", { STi, ST } },
13450 { "fsub!Mp", { STi, ST } },
13451 { "fsubMp", { STi, ST } },
13452 { "fdiv!Mp", { STi, ST } },
13453 { "fdivMp", { STi, ST } },
13457 { "ffreep", { STi } },
13462 { "fucomip", { ST, STi } },
13463 { "fcomip", { ST, STi } },
13468 static char *fgrps[][8] = {
13471 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13476 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13481 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13486 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13491 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13496 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13501 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13502 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13507 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13512 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13517 swap_operand (void)
13519 mnemonicendp[0] = '.';
13520 mnemonicendp[1] = 's';
13525 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13526 int sizeflag ATTRIBUTE_UNUSED)
13528 /* Skip mod/rm byte. */
13534 dofloat (int sizeflag)
13536 const struct dis386 *dp;
13537 unsigned char floatop;
13539 floatop = codep[-1];
13541 if (modrm.mod != 3)
13543 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13545 putop (float_mem[fp_indx], sizeflag);
13548 OP_E (float_mem_mode[fp_indx], sizeflag);
13551 /* Skip mod/rm byte. */
13555 dp = &float_reg[floatop - 0xd8][modrm.reg];
13556 if (dp->name == NULL)
13558 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13560 /* Instruction fnstsw is only one with strange arg. */
13561 if (floatop == 0xdf && codep[-1] == 0xe0)
13562 strcpy (op_out[0], names16[0]);
13566 putop (dp->name, sizeflag);
13571 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13576 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13580 /* Like oappend (below), but S is a string starting with '%'.
13581 In Intel syntax, the '%' is elided. */
13583 oappend_maybe_intel (const char *s)
13585 oappend (s + intel_syntax);
13589 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13591 oappend_maybe_intel ("%st");
13595 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13597 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13598 oappend_maybe_intel (scratchbuf);
13601 /* Capital letters in template are macros. */
13603 putop (const char *in_template, int sizeflag)
13608 unsigned int l = 0, len = 1;
13611 #define SAVE_LAST(c) \
13612 if (l < len && l < sizeof (last)) \
13617 for (p = in_template; *p; p++)
13634 while (*++p != '|')
13635 if (*p == '}' || *p == '\0')
13638 /* Fall through. */
13643 while (*++p != '}')
13654 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13658 if (l == 0 && len == 1)
13663 if (sizeflag & SUFFIX_ALWAYS)
13676 if (address_mode == mode_64bit
13677 && !(prefixes & PREFIX_ADDR))
13688 if (intel_syntax && !alt)
13690 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13692 if (sizeflag & DFLAG)
13693 *obufp++ = intel_syntax ? 'd' : 'l';
13695 *obufp++ = intel_syntax ? 'w' : 's';
13696 used_prefixes |= (prefixes & PREFIX_DATA);
13700 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13703 if (modrm.mod == 3)
13709 if (sizeflag & DFLAG)
13710 *obufp++ = intel_syntax ? 'd' : 'l';
13713 used_prefixes |= (prefixes & PREFIX_DATA);
13719 case 'E': /* For jcxz/jecxz */
13720 if (address_mode == mode_64bit)
13722 if (sizeflag & AFLAG)
13728 if (sizeflag & AFLAG)
13730 used_prefixes |= (prefixes & PREFIX_ADDR);
13735 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13737 if (sizeflag & AFLAG)
13738 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13740 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13741 used_prefixes |= (prefixes & PREFIX_ADDR);
13745 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13747 if ((rex & REX_W) || (sizeflag & DFLAG))
13751 if (!(rex & REX_W))
13752 used_prefixes |= (prefixes & PREFIX_DATA);
13757 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13758 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13760 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13763 if (prefixes & PREFIX_DS)
13784 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13789 /* Fall through. */
13792 if (l != 0 || len != 1)
13800 if (sizeflag & SUFFIX_ALWAYS)
13804 if (intel_mnemonic != cond)
13808 if ((prefixes & PREFIX_FWAIT) == 0)
13811 used_prefixes |= PREFIX_FWAIT;
13817 else if (intel_syntax && (sizeflag & DFLAG))
13821 if (!(rex & REX_W))
13822 used_prefixes |= (prefixes & PREFIX_DATA);
13826 && address_mode == mode_64bit
13827 && ((sizeflag & DFLAG) || (rex & REX_W)))
13832 /* Fall through. */
13835 if (l == 0 && len == 1)
13840 if ((rex & REX_W) == 0
13841 && (prefixes & PREFIX_DATA))
13843 if ((sizeflag & DFLAG) == 0)
13845 used_prefixes |= (prefixes & PREFIX_DATA);
13849 if ((prefixes & PREFIX_DATA)
13851 || (sizeflag & SUFFIX_ALWAYS))
13858 if (sizeflag & DFLAG)
13862 used_prefixes |= (prefixes & PREFIX_DATA);
13868 if (l != 1 || len != 2 || last[0] != 'L')
13874 if ((prefixes & PREFIX_DATA)
13876 || (sizeflag & SUFFIX_ALWAYS))
13883 if (sizeflag & DFLAG)
13884 *obufp++ = intel_syntax ? 'd' : 'l';
13887 used_prefixes |= (prefixes & PREFIX_DATA);
13895 if (address_mode == mode_64bit
13896 && ((sizeflag & DFLAG) || (rex & REX_W)))
13898 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13902 /* Fall through. */
13905 if (l == 0 && len == 1)
13908 if (intel_syntax && !alt)
13911 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13917 if (sizeflag & DFLAG)
13918 *obufp++ = intel_syntax ? 'd' : 'l';
13921 used_prefixes |= (prefixes & PREFIX_DATA);
13927 if (l != 1 || len != 2 || last[0] != 'L')
13933 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13948 else if (sizeflag & DFLAG)
13957 if (intel_syntax && !p[1]
13958 && ((rex & REX_W) || (sizeflag & DFLAG)))
13960 if (!(rex & REX_W))
13961 used_prefixes |= (prefixes & PREFIX_DATA);
13964 if (l == 0 && len == 1)
13968 if (address_mode == mode_64bit
13969 && ((sizeflag & DFLAG) || (rex & REX_W)))
13971 if (sizeflag & SUFFIX_ALWAYS)
13993 /* Fall through. */
13996 if (l == 0 && len == 1)
14001 if (sizeflag & SUFFIX_ALWAYS)
14007 if (sizeflag & DFLAG)
14011 used_prefixes |= (prefixes & PREFIX_DATA);
14025 if (address_mode == mode_64bit
14026 && !(prefixes & PREFIX_ADDR))
14037 if (l != 0 || len != 1)
14042 if (need_vex && vex.prefix)
14044 if (vex.prefix == DATA_PREFIX_OPCODE)
14051 if (prefixes & PREFIX_DATA)
14055 used_prefixes |= (prefixes & PREFIX_DATA);
14059 if (l == 0 && len == 1)
14061 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14072 if (l != 1 || len != 2 || last[0] != 'X')
14080 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14082 switch (vex.length)
14096 if (l == 0 && len == 1)
14098 /* operand size flag for cwtl, cbtw */
14107 else if (sizeflag & DFLAG)
14111 if (!(rex & REX_W))
14112 used_prefixes |= (prefixes & PREFIX_DATA);
14119 && last[0] != 'L'))
14126 if (last[0] == 'X')
14127 *obufp++ = vex.w ? 'd': 's';
14129 *obufp++ = vex.w ? 'q': 'd';
14136 mnemonicendp = obufp;
14141 oappend (const char *s)
14143 obufp = stpcpy (obufp, s);
14149 /* Only print the active segment register. */
14150 if (!active_seg_prefix)
14153 used_prefixes |= active_seg_prefix;
14154 switch (active_seg_prefix)
14157 oappend_maybe_intel ("%cs:");
14160 oappend_maybe_intel ("%ds:");
14163 oappend_maybe_intel ("%ss:");
14166 oappend_maybe_intel ("%es:");
14169 oappend_maybe_intel ("%fs:");
14172 oappend_maybe_intel ("%gs:");
14180 OP_indirE (int bytemode, int sizeflag)
14184 OP_E (bytemode, sizeflag);
14188 print_operand_value (char *buf, int hex, bfd_vma disp)
14190 if (address_mode == mode_64bit)
14198 sprintf_vma (tmp, disp);
14199 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14200 strcpy (buf + 2, tmp + i);
14204 bfd_signed_vma v = disp;
14211 /* Check for possible overflow on 0x8000000000000000. */
14214 strcpy (buf, "9223372036854775808");
14228 tmp[28 - i] = (v % 10) + '0';
14232 strcpy (buf, tmp + 29 - i);
14238 sprintf (buf, "0x%x", (unsigned int) disp);
14240 sprintf (buf, "%d", (int) disp);
14244 /* Put DISP in BUF as signed hex number. */
14247 print_displacement (char *buf, bfd_vma disp)
14249 bfd_signed_vma val = disp;
14258 /* Check for possible overflow. */
14261 switch (address_mode)
14264 strcpy (buf + j, "0x8000000000000000");
14267 strcpy (buf + j, "0x80000000");
14270 strcpy (buf + j, "0x8000");
14280 sprintf_vma (tmp, (bfd_vma) val);
14281 for (i = 0; tmp[i] == '0'; i++)
14283 if (tmp[i] == '\0')
14285 strcpy (buf + j, tmp + i);
14289 intel_operand_size (int bytemode, int sizeflag)
14293 && (bytemode == x_mode
14294 || bytemode == evex_half_bcst_xmmq_mode))
14297 oappend ("QWORD PTR ");
14299 oappend ("DWORD PTR ");
14308 oappend ("BYTE PTR ");
14313 case dqw_swap_mode:
14314 oappend ("WORD PTR ");
14317 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14319 oappend ("QWORD PTR ");
14328 oappend ("QWORD PTR ");
14331 if ((sizeflag & DFLAG) || bytemode == dq_mode)
14332 oappend ("DWORD PTR ");
14334 oappend ("WORD PTR ");
14335 used_prefixes |= (prefixes & PREFIX_DATA);
14339 if ((rex & REX_W) || (sizeflag & DFLAG))
14341 oappend ("WORD PTR ");
14342 if (!(rex & REX_W))
14343 used_prefixes |= (prefixes & PREFIX_DATA);
14346 if (sizeflag & DFLAG)
14347 oappend ("QWORD PTR ");
14349 oappend ("DWORD PTR ");
14350 used_prefixes |= (prefixes & PREFIX_DATA);
14353 case d_scalar_mode:
14354 case d_scalar_swap_mode:
14357 oappend ("DWORD PTR ");
14360 case q_scalar_mode:
14361 case q_scalar_swap_mode:
14363 oappend ("QWORD PTR ");
14366 if (address_mode == mode_64bit)
14367 oappend ("QWORD PTR ");
14369 oappend ("DWORD PTR ");
14372 if (sizeflag & DFLAG)
14373 oappend ("FWORD PTR ");
14375 oappend ("DWORD PTR ");
14376 used_prefixes |= (prefixes & PREFIX_DATA);
14379 oappend ("TBYTE PTR ");
14383 case evex_x_gscat_mode:
14384 case evex_x_nobcst_mode:
14387 switch (vex.length)
14390 oappend ("XMMWORD PTR ");
14393 oappend ("YMMWORD PTR ");
14396 oappend ("ZMMWORD PTR ");
14403 oappend ("XMMWORD PTR ");
14406 oappend ("XMMWORD PTR ");
14409 oappend ("YMMWORD PTR ");
14412 case evex_half_bcst_xmmq_mode:
14416 switch (vex.length)
14419 oappend ("QWORD PTR ");
14422 oappend ("XMMWORD PTR ");
14425 oappend ("YMMWORD PTR ");
14435 switch (vex.length)
14440 oappend ("BYTE PTR ");
14450 switch (vex.length)
14455 oappend ("WORD PTR ");
14465 switch (vex.length)
14470 oappend ("DWORD PTR ");
14480 switch (vex.length)
14485 oappend ("QWORD PTR ");
14495 switch (vex.length)
14498 oappend ("WORD PTR ");
14501 oappend ("DWORD PTR ");
14504 oappend ("QWORD PTR ");
14514 switch (vex.length)
14517 oappend ("DWORD PTR ");
14520 oappend ("QWORD PTR ");
14523 oappend ("XMMWORD PTR ");
14533 switch (vex.length)
14536 oappend ("QWORD PTR ");
14539 oappend ("YMMWORD PTR ");
14542 oappend ("ZMMWORD PTR ");
14552 switch (vex.length)
14556 oappend ("XMMWORD PTR ");
14563 oappend ("OWORD PTR ");
14566 case vex_w_dq_mode:
14567 case vex_scalar_w_dq_mode:
14572 oappend ("QWORD PTR ");
14574 oappend ("DWORD PTR ");
14576 case vex_vsib_d_w_dq_mode:
14577 case vex_vsib_q_w_dq_mode:
14584 oappend ("QWORD PTR ");
14586 oappend ("DWORD PTR ");
14590 switch (vex.length)
14593 oappend ("XMMWORD PTR ");
14596 oappend ("YMMWORD PTR ");
14599 oappend ("ZMMWORD PTR ");
14606 case vex_vsib_q_w_d_mode:
14607 case vex_vsib_d_w_d_mode:
14608 if (!need_vex || !vex.evex)
14611 switch (vex.length)
14614 oappend ("QWORD PTR ");
14617 oappend ("XMMWORD PTR ");
14620 oappend ("YMMWORD PTR ");
14628 if (!need_vex || vex.length != 128)
14631 oappend ("DWORD PTR ");
14633 oappend ("BYTE PTR ");
14639 oappend ("QWORD PTR ");
14641 oappend ("WORD PTR ");
14650 OP_E_register (int bytemode, int sizeflag)
14652 int reg = modrm.rm;
14653 const char **names;
14659 if ((sizeflag & SUFFIX_ALWAYS)
14660 && (bytemode == b_swap_mode
14661 || bytemode == v_swap_mode
14662 || bytemode == dqw_swap_mode))
14688 names = address_mode == mode_64bit ? names64 : names32;
14694 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14707 case dqw_swap_mode:
14713 if ((sizeflag & DFLAG)
14714 || (bytemode != v_mode
14715 && bytemode != v_swap_mode))
14719 used_prefixes |= (prefixes & PREFIX_DATA);
14724 names = names_mask;
14729 oappend (INTERNAL_DISASSEMBLER_ERROR);
14732 oappend (names[reg]);
14736 OP_E_memory (int bytemode, int sizeflag)
14739 int add = (rex & REX_B) ? 8 : 0;
14745 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
14747 && bytemode != x_mode
14748 && bytemode != xmmq_mode
14749 && bytemode != evex_half_bcst_xmmq_mode)
14758 case dqw_swap_mode:
14765 case vex_vsib_d_w_dq_mode:
14766 case vex_vsib_d_w_d_mode:
14767 case vex_vsib_q_w_dq_mode:
14768 case vex_vsib_q_w_d_mode:
14769 case evex_x_gscat_mode:
14771 shift = vex.w ? 3 : 2;
14774 case evex_half_bcst_xmmq_mode:
14778 shift = vex.w ? 3 : 2;
14781 /* Fall through if vex.b == 0. */
14785 case evex_x_nobcst_mode:
14787 switch (vex.length)
14810 case q_scalar_mode:
14812 case q_scalar_swap_mode:
14818 case d_scalar_mode:
14820 case d_scalar_swap_mode:
14832 /* Make necessary corrections to shift for modes that need it.
14833 For these modes we currently have shift 4, 5 or 6 depending on
14834 vex.length (it corresponds to xmmword, ymmword or zmmword
14835 operand). We might want to make it 3, 4 or 5 (e.g. for
14836 xmmq_mode). In case of broadcast enabled the corrections
14837 aren't needed, as element size is always 32 or 64 bits. */
14839 && (bytemode == xmmq_mode
14840 || bytemode == evex_half_bcst_xmmq_mode))
14842 else if (bytemode == xmmqd_mode)
14844 else if (bytemode == xmmdw_mode)
14846 else if (bytemode == ymmq_mode && vex.length == 128)
14854 intel_operand_size (bytemode, sizeflag);
14857 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14859 /* 32/64 bit address mode */
14868 int addr32flag = !((sizeflag & AFLAG)
14869 || bytemode == v_bnd_mode
14870 || bytemode == bnd_mode);
14871 const char **indexes64 = names64;
14872 const char **indexes32 = names32;
14882 vindex = sib.index;
14888 case vex_vsib_d_w_dq_mode:
14889 case vex_vsib_d_w_d_mode:
14890 case vex_vsib_q_w_dq_mode:
14891 case vex_vsib_q_w_d_mode:
14901 switch (vex.length)
14904 indexes64 = indexes32 = names_xmm;
14908 || bytemode == vex_vsib_q_w_dq_mode
14909 || bytemode == vex_vsib_q_w_d_mode)
14910 indexes64 = indexes32 = names_ymm;
14912 indexes64 = indexes32 = names_xmm;
14916 || bytemode == vex_vsib_q_w_dq_mode
14917 || bytemode == vex_vsib_q_w_d_mode)
14918 indexes64 = indexes32 = names_zmm;
14920 indexes64 = indexes32 = names_ymm;
14927 haveindex = vindex != 4;
14934 rbase = base + add;
14942 if (address_mode == mode_64bit && !havesib)
14948 FETCH_DATA (the_info, codep + 1);
14950 if ((disp & 0x80) != 0)
14952 if (vex.evex && shift > 0)
14960 /* In 32bit mode, we need index register to tell [offset] from
14961 [eiz*1 + offset]. */
14962 needindex = (havesib
14965 && address_mode == mode_32bit);
14966 havedisp = (havebase
14968 || (havesib && (haveindex || scale != 0)));
14971 if (modrm.mod != 0 || base == 5)
14973 if (havedisp || riprel)
14974 print_displacement (scratchbuf, disp);
14976 print_operand_value (scratchbuf, 1, disp);
14977 oappend (scratchbuf);
14981 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
14985 if ((havebase || haveindex || riprel)
14986 && (bytemode != v_bnd_mode)
14987 && (bytemode != bnd_mode))
14988 used_prefixes |= PREFIX_ADDR;
14990 if (havedisp || (intel_syntax && riprel))
14992 *obufp++ = open_char;
14993 if (intel_syntax && riprel)
14996 oappend (sizeflag & AFLAG ? "rip" : "eip");
15000 oappend (address_mode == mode_64bit && !addr32flag
15001 ? names64[rbase] : names32[rbase]);
15004 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15005 print index to tell base + index from base. */
15009 || (havebase && base != ESP_REG_NUM))
15011 if (!intel_syntax || havebase)
15013 *obufp++ = separator_char;
15017 oappend (address_mode == mode_64bit && !addr32flag
15018 ? indexes64[vindex] : indexes32[vindex]);
15020 oappend (address_mode == mode_64bit && !addr32flag
15021 ? index64 : index32);
15023 *obufp++ = scale_char;
15025 sprintf (scratchbuf, "%d", 1 << scale);
15026 oappend (scratchbuf);
15030 && (disp || modrm.mod != 0 || base == 5))
15032 if (!havedisp || (bfd_signed_vma) disp >= 0)
15037 else if (modrm.mod != 1 && disp != -disp)
15041 disp = - (bfd_signed_vma) disp;
15045 print_displacement (scratchbuf, disp);
15047 print_operand_value (scratchbuf, 1, disp);
15048 oappend (scratchbuf);
15051 *obufp++ = close_char;
15054 else if (intel_syntax)
15056 if (modrm.mod != 0 || base == 5)
15058 if (!active_seg_prefix)
15060 oappend (names_seg[ds_reg - es_reg]);
15063 print_operand_value (scratchbuf, 1, disp);
15064 oappend (scratchbuf);
15070 /* 16 bit address mode */
15071 used_prefixes |= prefixes & PREFIX_ADDR;
15078 if ((disp & 0x8000) != 0)
15083 FETCH_DATA (the_info, codep + 1);
15085 if ((disp & 0x80) != 0)
15090 if ((disp & 0x8000) != 0)
15096 if (modrm.mod != 0 || modrm.rm == 6)
15098 print_displacement (scratchbuf, disp);
15099 oappend (scratchbuf);
15102 if (modrm.mod != 0 || modrm.rm != 6)
15104 *obufp++ = open_char;
15106 oappend (index16[modrm.rm]);
15108 && (disp || modrm.mod != 0 || modrm.rm == 6))
15110 if ((bfd_signed_vma) disp >= 0)
15115 else if (modrm.mod != 1)
15119 disp = - (bfd_signed_vma) disp;
15122 print_displacement (scratchbuf, disp);
15123 oappend (scratchbuf);
15126 *obufp++ = close_char;
15129 else if (intel_syntax)
15131 if (!active_seg_prefix)
15133 oappend (names_seg[ds_reg - es_reg]);
15136 print_operand_value (scratchbuf, 1, disp & 0xffff);
15137 oappend (scratchbuf);
15140 if (vex.evex && vex.b
15141 && (bytemode == x_mode
15142 || bytemode == xmmq_mode
15143 || bytemode == evex_half_bcst_xmmq_mode))
15146 || bytemode == xmmq_mode
15147 || bytemode == evex_half_bcst_xmmq_mode)
15149 switch (vex.length)
15152 oappend ("{1to2}");
15155 oappend ("{1to4}");
15158 oappend ("{1to8}");
15166 switch (vex.length)
15169 oappend ("{1to4}");
15172 oappend ("{1to8}");
15175 oappend ("{1to16}");
15185 OP_E (int bytemode, int sizeflag)
15187 /* Skip mod/rm byte. */
15191 if (modrm.mod == 3)
15192 OP_E_register (bytemode, sizeflag);
15194 OP_E_memory (bytemode, sizeflag);
15198 OP_G (int bytemode, int sizeflag)
15209 oappend (names8rex[modrm.reg + add]);
15211 oappend (names8[modrm.reg + add]);
15214 oappend (names16[modrm.reg + add]);
15219 oappend (names32[modrm.reg + add]);
15222 oappend (names64[modrm.reg + add]);
15225 oappend (names_bnd[modrm.reg]);
15232 case dqw_swap_mode:
15235 oappend (names64[modrm.reg + add]);
15238 if ((sizeflag & DFLAG) || bytemode != v_mode)
15239 oappend (names32[modrm.reg + add]);
15241 oappend (names16[modrm.reg + add]);
15242 used_prefixes |= (prefixes & PREFIX_DATA);
15246 if (address_mode == mode_64bit)
15247 oappend (names64[modrm.reg + add]);
15249 oappend (names32[modrm.reg + add]);
15253 oappend (names_mask[modrm.reg + add]);
15256 oappend (INTERNAL_DISASSEMBLER_ERROR);
15269 FETCH_DATA (the_info, codep + 8);
15270 a = *codep++ & 0xff;
15271 a |= (*codep++ & 0xff) << 8;
15272 a |= (*codep++ & 0xff) << 16;
15273 a |= (*codep++ & 0xff) << 24;
15274 b = *codep++ & 0xff;
15275 b |= (*codep++ & 0xff) << 8;
15276 b |= (*codep++ & 0xff) << 16;
15277 b |= (*codep++ & 0xff) << 24;
15278 x = a + ((bfd_vma) b << 32);
15286 static bfd_signed_vma
15289 bfd_signed_vma x = 0;
15291 FETCH_DATA (the_info, codep + 4);
15292 x = *codep++ & (bfd_signed_vma) 0xff;
15293 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15294 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15295 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15299 static bfd_signed_vma
15302 bfd_signed_vma x = 0;
15304 FETCH_DATA (the_info, codep + 4);
15305 x = *codep++ & (bfd_signed_vma) 0xff;
15306 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15307 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15308 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15310 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15320 FETCH_DATA (the_info, codep + 2);
15321 x = *codep++ & 0xff;
15322 x |= (*codep++ & 0xff) << 8;
15327 set_op (bfd_vma op, int riprel)
15329 op_index[op_ad] = op_ad;
15330 if (address_mode == mode_64bit)
15332 op_address[op_ad] = op;
15333 op_riprel[op_ad] = riprel;
15337 /* Mask to get a 32-bit address. */
15338 op_address[op_ad] = op & 0xffffffff;
15339 op_riprel[op_ad] = riprel & 0xffffffff;
15344 OP_REG (int code, int sizeflag)
15351 case es_reg: case ss_reg: case cs_reg:
15352 case ds_reg: case fs_reg: case gs_reg:
15353 oappend (names_seg[code - es_reg]);
15365 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15366 case sp_reg: case bp_reg: case si_reg: case di_reg:
15367 s = names16[code - ax_reg + add];
15369 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15370 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15373 s = names8rex[code - al_reg + add];
15375 s = names8[code - al_reg];
15377 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15378 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15379 if (address_mode == mode_64bit
15380 && ((sizeflag & DFLAG) || (rex & REX_W)))
15382 s = names64[code - rAX_reg + add];
15385 code += eAX_reg - rAX_reg;
15386 /* Fall through. */
15387 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15388 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15391 s = names64[code - eAX_reg + add];
15394 if (sizeflag & DFLAG)
15395 s = names32[code - eAX_reg + add];
15397 s = names16[code - eAX_reg + add];
15398 used_prefixes |= (prefixes & PREFIX_DATA);
15402 s = INTERNAL_DISASSEMBLER_ERROR;
15409 OP_IMREG (int code, int sizeflag)
15421 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15422 case sp_reg: case bp_reg: case si_reg: case di_reg:
15423 s = names16[code - ax_reg];
15425 case es_reg: case ss_reg: case cs_reg:
15426 case ds_reg: case fs_reg: case gs_reg:
15427 s = names_seg[code - es_reg];
15429 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15430 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15433 s = names8rex[code - al_reg];
15435 s = names8[code - al_reg];
15437 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15438 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15441 s = names64[code - eAX_reg];
15444 if (sizeflag & DFLAG)
15445 s = names32[code - eAX_reg];
15447 s = names16[code - eAX_reg];
15448 used_prefixes |= (prefixes & PREFIX_DATA);
15451 case z_mode_ax_reg:
15452 if ((rex & REX_W) || (sizeflag & DFLAG))
15456 if (!(rex & REX_W))
15457 used_prefixes |= (prefixes & PREFIX_DATA);
15460 s = INTERNAL_DISASSEMBLER_ERROR;
15467 OP_I (int bytemode, int sizeflag)
15470 bfd_signed_vma mask = -1;
15475 FETCH_DATA (the_info, codep + 1);
15480 if (address_mode == mode_64bit)
15485 /* Fall through. */
15492 if (sizeflag & DFLAG)
15502 used_prefixes |= (prefixes & PREFIX_DATA);
15514 oappend (INTERNAL_DISASSEMBLER_ERROR);
15519 scratchbuf[0] = '$';
15520 print_operand_value (scratchbuf + 1, 1, op);
15521 oappend_maybe_intel (scratchbuf);
15522 scratchbuf[0] = '\0';
15526 OP_I64 (int bytemode, int sizeflag)
15529 bfd_signed_vma mask = -1;
15531 if (address_mode != mode_64bit)
15533 OP_I (bytemode, sizeflag);
15540 FETCH_DATA (the_info, codep + 1);
15550 if (sizeflag & DFLAG)
15560 used_prefixes |= (prefixes & PREFIX_DATA);
15568 oappend (INTERNAL_DISASSEMBLER_ERROR);
15573 scratchbuf[0] = '$';
15574 print_operand_value (scratchbuf + 1, 1, op);
15575 oappend_maybe_intel (scratchbuf);
15576 scratchbuf[0] = '\0';
15580 OP_sI (int bytemode, int sizeflag)
15588 FETCH_DATA (the_info, codep + 1);
15590 if ((op & 0x80) != 0)
15592 if (bytemode == b_T_mode)
15594 if (address_mode != mode_64bit
15595 || !((sizeflag & DFLAG) || (rex & REX_W)))
15597 /* The operand-size prefix is overridden by a REX prefix. */
15598 if ((sizeflag & DFLAG) || (rex & REX_W))
15606 if (!(rex & REX_W))
15608 if (sizeflag & DFLAG)
15616 /* The operand-size prefix is overridden by a REX prefix. */
15617 if ((sizeflag & DFLAG) || (rex & REX_W))
15623 oappend (INTERNAL_DISASSEMBLER_ERROR);
15627 scratchbuf[0] = '$';
15628 print_operand_value (scratchbuf + 1, 1, op);
15629 oappend_maybe_intel (scratchbuf);
15633 OP_J (int bytemode, int sizeflag)
15637 bfd_vma segment = 0;
15642 FETCH_DATA (the_info, codep + 1);
15644 if ((disp & 0x80) != 0)
15649 if ((sizeflag & DFLAG) || (rex & REX_W))
15654 if ((disp & 0x8000) != 0)
15656 /* In 16bit mode, address is wrapped around at 64k within
15657 the same segment. Otherwise, a data16 prefix on a jump
15658 instruction means that the pc is masked to 16 bits after
15659 the displacement is added! */
15661 if ((prefixes & PREFIX_DATA) == 0)
15662 segment = ((start_pc + codep - start_codep)
15663 & ~((bfd_vma) 0xffff));
15665 if (!(rex & REX_W))
15666 used_prefixes |= (prefixes & PREFIX_DATA);
15669 oappend (INTERNAL_DISASSEMBLER_ERROR);
15672 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15674 print_operand_value (scratchbuf, 1, disp);
15675 oappend (scratchbuf);
15679 OP_SEG (int bytemode, int sizeflag)
15681 if (bytemode == w_mode)
15682 oappend (names_seg[modrm.reg]);
15684 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15688 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15692 if (sizeflag & DFLAG)
15702 used_prefixes |= (prefixes & PREFIX_DATA);
15704 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15706 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15707 oappend (scratchbuf);
15711 OP_OFF (int bytemode, int sizeflag)
15715 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15716 intel_operand_size (bytemode, sizeflag);
15719 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15726 if (!active_seg_prefix)
15728 oappend (names_seg[ds_reg - es_reg]);
15732 print_operand_value (scratchbuf, 1, off);
15733 oappend (scratchbuf);
15737 OP_OFF64 (int bytemode, int sizeflag)
15741 if (address_mode != mode_64bit
15742 || (prefixes & PREFIX_ADDR))
15744 OP_OFF (bytemode, sizeflag);
15748 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15749 intel_operand_size (bytemode, sizeflag);
15756 if (!active_seg_prefix)
15758 oappend (names_seg[ds_reg - es_reg]);
15762 print_operand_value (scratchbuf, 1, off);
15763 oappend (scratchbuf);
15767 ptr_reg (int code, int sizeflag)
15771 *obufp++ = open_char;
15772 used_prefixes |= (prefixes & PREFIX_ADDR);
15773 if (address_mode == mode_64bit)
15775 if (!(sizeflag & AFLAG))
15776 s = names32[code - eAX_reg];
15778 s = names64[code - eAX_reg];
15780 else if (sizeflag & AFLAG)
15781 s = names32[code - eAX_reg];
15783 s = names16[code - eAX_reg];
15785 *obufp++ = close_char;
15790 OP_ESreg (int code, int sizeflag)
15796 case 0x6d: /* insw/insl */
15797 intel_operand_size (z_mode, sizeflag);
15799 case 0xa5: /* movsw/movsl/movsq */
15800 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15801 case 0xab: /* stosw/stosl */
15802 case 0xaf: /* scasw/scasl */
15803 intel_operand_size (v_mode, sizeflag);
15806 intel_operand_size (b_mode, sizeflag);
15809 oappend_maybe_intel ("%es:");
15810 ptr_reg (code, sizeflag);
15814 OP_DSreg (int code, int sizeflag)
15820 case 0x6f: /* outsw/outsl */
15821 intel_operand_size (z_mode, sizeflag);
15823 case 0xa5: /* movsw/movsl/movsq */
15824 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15825 case 0xad: /* lodsw/lodsl/lodsq */
15826 intel_operand_size (v_mode, sizeflag);
15829 intel_operand_size (b_mode, sizeflag);
15832 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15833 default segment register DS is printed. */
15834 if (!active_seg_prefix)
15835 active_seg_prefix = PREFIX_DS;
15837 ptr_reg (code, sizeflag);
15841 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15849 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15851 all_prefixes[last_lock_prefix] = 0;
15852 used_prefixes |= PREFIX_LOCK;
15857 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15858 oappend_maybe_intel (scratchbuf);
15862 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15871 sprintf (scratchbuf, "db%d", modrm.reg + add);
15873 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15874 oappend (scratchbuf);
15878 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15880 sprintf (scratchbuf, "%%tr%d", modrm.reg);
15881 oappend_maybe_intel (scratchbuf);
15885 OP_R (int bytemode, int sizeflag)
15887 /* Skip mod/rm byte. */
15890 OP_E_register (bytemode, sizeflag);
15894 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15896 int reg = modrm.reg;
15897 const char **names;
15899 used_prefixes |= (prefixes & PREFIX_DATA);
15900 if (prefixes & PREFIX_DATA)
15909 oappend (names[reg]);
15913 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15915 int reg = modrm.reg;
15916 const char **names;
15928 && bytemode != xmm_mode
15929 && bytemode != xmmq_mode
15930 && bytemode != evex_half_bcst_xmmq_mode
15931 && bytemode != ymm_mode
15932 && bytemode != scalar_mode)
15934 switch (vex.length)
15941 || (bytemode != vex_vsib_q_w_dq_mode
15942 && bytemode != vex_vsib_q_w_d_mode))
15954 else if (bytemode == xmmq_mode
15955 || bytemode == evex_half_bcst_xmmq_mode)
15957 switch (vex.length)
15970 else if (bytemode == ymm_mode)
15974 oappend (names[reg]);
15978 OP_EM (int bytemode, int sizeflag)
15981 const char **names;
15983 if (modrm.mod != 3)
15986 && (bytemode == v_mode || bytemode == v_swap_mode))
15988 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15989 used_prefixes |= (prefixes & PREFIX_DATA);
15991 OP_E (bytemode, sizeflag);
15995 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15998 /* Skip mod/rm byte. */
16001 used_prefixes |= (prefixes & PREFIX_DATA);
16003 if (prefixes & PREFIX_DATA)
16012 oappend (names[reg]);
16015 /* cvt* are the only instructions in sse2 which have
16016 both SSE and MMX operands and also have 0x66 prefix
16017 in their opcode. 0x66 was originally used to differentiate
16018 between SSE and MMX instruction(operands). So we have to handle the
16019 cvt* separately using OP_EMC and OP_MXC */
16021 OP_EMC (int bytemode, int sizeflag)
16023 if (modrm.mod != 3)
16025 if (intel_syntax && bytemode == v_mode)
16027 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16028 used_prefixes |= (prefixes & PREFIX_DATA);
16030 OP_E (bytemode, sizeflag);
16034 /* Skip mod/rm byte. */
16037 used_prefixes |= (prefixes & PREFIX_DATA);
16038 oappend (names_mm[modrm.rm]);
16042 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16044 used_prefixes |= (prefixes & PREFIX_DATA);
16045 oappend (names_mm[modrm.reg]);
16049 OP_EX (int bytemode, int sizeflag)
16052 const char **names;
16054 /* Skip mod/rm byte. */
16058 if (modrm.mod != 3)
16060 OP_E_memory (bytemode, sizeflag);
16075 if ((sizeflag & SUFFIX_ALWAYS)
16076 && (bytemode == x_swap_mode
16077 || bytemode == d_swap_mode
16078 || bytemode == dqw_swap_mode
16079 || bytemode == d_scalar_swap_mode
16080 || bytemode == q_swap_mode
16081 || bytemode == q_scalar_swap_mode))
16085 && bytemode != xmm_mode
16086 && bytemode != xmmdw_mode
16087 && bytemode != xmmqd_mode
16088 && bytemode != xmm_mb_mode
16089 && bytemode != xmm_mw_mode
16090 && bytemode != xmm_md_mode
16091 && bytemode != xmm_mq_mode
16092 && bytemode != xmm_mdq_mode
16093 && bytemode != xmmq_mode
16094 && bytemode != evex_half_bcst_xmmq_mode
16095 && bytemode != ymm_mode
16096 && bytemode != d_scalar_mode
16097 && bytemode != d_scalar_swap_mode
16098 && bytemode != q_scalar_mode
16099 && bytemode != q_scalar_swap_mode
16100 && bytemode != vex_scalar_w_dq_mode)
16102 switch (vex.length)
16117 else if (bytemode == xmmq_mode
16118 || bytemode == evex_half_bcst_xmmq_mode)
16120 switch (vex.length)
16133 else if (bytemode == ymm_mode)
16137 oappend (names[reg]);
16141 OP_MS (int bytemode, int sizeflag)
16143 if (modrm.mod == 3)
16144 OP_EM (bytemode, sizeflag);
16150 OP_XS (int bytemode, int sizeflag)
16152 if (modrm.mod == 3)
16153 OP_EX (bytemode, sizeflag);
16159 OP_M (int bytemode, int sizeflag)
16161 if (modrm.mod == 3)
16162 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16165 OP_E (bytemode, sizeflag);
16169 OP_0f07 (int bytemode, int sizeflag)
16171 if (modrm.mod != 3 || modrm.rm != 0)
16174 OP_E (bytemode, sizeflag);
16177 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16178 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16181 NOP_Fixup1 (int bytemode, int sizeflag)
16183 if ((prefixes & PREFIX_DATA) != 0
16186 && address_mode == mode_64bit))
16187 OP_REG (bytemode, sizeflag);
16189 strcpy (obuf, "nop");
16193 NOP_Fixup2 (int bytemode, int sizeflag)
16195 if ((prefixes & PREFIX_DATA) != 0
16198 && address_mode == mode_64bit))
16199 OP_IMREG (bytemode, sizeflag);
16202 static const char *const Suffix3DNow[] = {
16203 /* 00 */ NULL, NULL, NULL, NULL,
16204 /* 04 */ NULL, NULL, NULL, NULL,
16205 /* 08 */ NULL, NULL, NULL, NULL,
16206 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
16207 /* 10 */ NULL, NULL, NULL, NULL,
16208 /* 14 */ NULL, NULL, NULL, NULL,
16209 /* 18 */ NULL, NULL, NULL, NULL,
16210 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
16211 /* 20 */ NULL, NULL, NULL, NULL,
16212 /* 24 */ NULL, NULL, NULL, NULL,
16213 /* 28 */ NULL, NULL, NULL, NULL,
16214 /* 2C */ NULL, NULL, NULL, NULL,
16215 /* 30 */ NULL, NULL, NULL, NULL,
16216 /* 34 */ NULL, NULL, NULL, NULL,
16217 /* 38 */ NULL, NULL, NULL, NULL,
16218 /* 3C */ NULL, NULL, NULL, NULL,
16219 /* 40 */ NULL, NULL, NULL, NULL,
16220 /* 44 */ NULL, NULL, NULL, NULL,
16221 /* 48 */ NULL, NULL, NULL, NULL,
16222 /* 4C */ NULL, NULL, NULL, NULL,
16223 /* 50 */ NULL, NULL, NULL, NULL,
16224 /* 54 */ NULL, NULL, NULL, NULL,
16225 /* 58 */ NULL, NULL, NULL, NULL,
16226 /* 5C */ NULL, NULL, NULL, NULL,
16227 /* 60 */ NULL, NULL, NULL, NULL,
16228 /* 64 */ NULL, NULL, NULL, NULL,
16229 /* 68 */ NULL, NULL, NULL, NULL,
16230 /* 6C */ NULL, NULL, NULL, NULL,
16231 /* 70 */ NULL, NULL, NULL, NULL,
16232 /* 74 */ NULL, NULL, NULL, NULL,
16233 /* 78 */ NULL, NULL, NULL, NULL,
16234 /* 7C */ NULL, NULL, NULL, NULL,
16235 /* 80 */ NULL, NULL, NULL, NULL,
16236 /* 84 */ NULL, NULL, NULL, NULL,
16237 /* 88 */ NULL, NULL, "pfnacc", NULL,
16238 /* 8C */ NULL, NULL, "pfpnacc", NULL,
16239 /* 90 */ "pfcmpge", NULL, NULL, NULL,
16240 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
16241 /* 98 */ NULL, NULL, "pfsub", NULL,
16242 /* 9C */ NULL, NULL, "pfadd", NULL,
16243 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
16244 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
16245 /* A8 */ NULL, NULL, "pfsubr", NULL,
16246 /* AC */ NULL, NULL, "pfacc", NULL,
16247 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
16248 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
16249 /* B8 */ NULL, NULL, NULL, "pswapd",
16250 /* BC */ NULL, NULL, NULL, "pavgusb",
16251 /* C0 */ NULL, NULL, NULL, NULL,
16252 /* C4 */ NULL, NULL, NULL, NULL,
16253 /* C8 */ NULL, NULL, NULL, NULL,
16254 /* CC */ NULL, NULL, NULL, NULL,
16255 /* D0 */ NULL, NULL, NULL, NULL,
16256 /* D4 */ NULL, NULL, NULL, NULL,
16257 /* D8 */ NULL, NULL, NULL, NULL,
16258 /* DC */ NULL, NULL, NULL, NULL,
16259 /* E0 */ NULL, NULL, NULL, NULL,
16260 /* E4 */ NULL, NULL, NULL, NULL,
16261 /* E8 */ NULL, NULL, NULL, NULL,
16262 /* EC */ NULL, NULL, NULL, NULL,
16263 /* F0 */ NULL, NULL, NULL, NULL,
16264 /* F4 */ NULL, NULL, NULL, NULL,
16265 /* F8 */ NULL, NULL, NULL, NULL,
16266 /* FC */ NULL, NULL, NULL, NULL,
16270 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16272 const char *mnemonic;
16274 FETCH_DATA (the_info, codep + 1);
16275 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16276 place where an 8-bit immediate would normally go. ie. the last
16277 byte of the instruction. */
16278 obufp = mnemonicendp;
16279 mnemonic = Suffix3DNow[*codep++ & 0xff];
16281 oappend (mnemonic);
16284 /* Since a variable sized modrm/sib chunk is between the start
16285 of the opcode (0x0f0f) and the opcode suffix, we need to do
16286 all the modrm processing first, and don't know until now that
16287 we have a bad opcode. This necessitates some cleaning up. */
16288 op_out[0][0] = '\0';
16289 op_out[1][0] = '\0';
16292 mnemonicendp = obufp;
16295 static struct op simd_cmp_op[] =
16297 { STRING_COMMA_LEN ("eq") },
16298 { STRING_COMMA_LEN ("lt") },
16299 { STRING_COMMA_LEN ("le") },
16300 { STRING_COMMA_LEN ("unord") },
16301 { STRING_COMMA_LEN ("neq") },
16302 { STRING_COMMA_LEN ("nlt") },
16303 { STRING_COMMA_LEN ("nle") },
16304 { STRING_COMMA_LEN ("ord") }
16308 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16310 unsigned int cmp_type;
16312 FETCH_DATA (the_info, codep + 1);
16313 cmp_type = *codep++ & 0xff;
16314 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16317 char *p = mnemonicendp - 2;
16321 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16322 mnemonicendp += simd_cmp_op[cmp_type].len;
16326 /* We have a reserved extension byte. Output it directly. */
16327 scratchbuf[0] = '$';
16328 print_operand_value (scratchbuf + 1, 1, cmp_type);
16329 oappend_maybe_intel (scratchbuf);
16330 scratchbuf[0] = '\0';
16335 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16336 int sizeflag ATTRIBUTE_UNUSED)
16338 /* mwait %eax,%ecx */
16341 const char **names = (address_mode == mode_64bit
16342 ? names64 : names32);
16343 strcpy (op_out[0], names[0]);
16344 strcpy (op_out[1], names[1]);
16345 two_source_ops = 1;
16347 /* Skip mod/rm byte. */
16353 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16354 int sizeflag ATTRIBUTE_UNUSED)
16356 /* monitor %eax,%ecx,%edx" */
16359 const char **op1_names;
16360 const char **names = (address_mode == mode_64bit
16361 ? names64 : names32);
16363 if (!(prefixes & PREFIX_ADDR))
16364 op1_names = (address_mode == mode_16bit
16365 ? names16 : names);
16368 /* Remove "addr16/addr32". */
16369 all_prefixes[last_addr_prefix] = 0;
16370 op1_names = (address_mode != mode_32bit
16371 ? names32 : names16);
16372 used_prefixes |= PREFIX_ADDR;
16374 strcpy (op_out[0], op1_names[0]);
16375 strcpy (op_out[1], names[1]);
16376 strcpy (op_out[2], names[2]);
16377 two_source_ops = 1;
16379 /* Skip mod/rm byte. */
16387 /* Throw away prefixes and 1st. opcode byte. */
16388 codep = insn_codep + 1;
16393 REP_Fixup (int bytemode, int sizeflag)
16395 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16397 if (prefixes & PREFIX_REPZ)
16398 all_prefixes[last_repz_prefix] = REP_PREFIX;
16405 OP_IMREG (bytemode, sizeflag);
16408 OP_ESreg (bytemode, sizeflag);
16411 OP_DSreg (bytemode, sizeflag);
16419 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16423 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16425 if (prefixes & PREFIX_REPNZ)
16426 all_prefixes[last_repnz_prefix] = BND_PREFIX;
16429 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16430 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16434 HLE_Fixup1 (int bytemode, int sizeflag)
16437 && (prefixes & PREFIX_LOCK) != 0)
16439 if (prefixes & PREFIX_REPZ)
16440 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16441 if (prefixes & PREFIX_REPNZ)
16442 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16445 OP_E (bytemode, sizeflag);
16448 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16449 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16453 HLE_Fixup2 (int bytemode, int sizeflag)
16455 if (modrm.mod != 3)
16457 if (prefixes & PREFIX_REPZ)
16458 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16459 if (prefixes & PREFIX_REPNZ)
16460 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16463 OP_E (bytemode, sizeflag);
16466 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16467 "xrelease" for memory operand. No check for LOCK prefix. */
16470 HLE_Fixup3 (int bytemode, int sizeflag)
16473 && last_repz_prefix > last_repnz_prefix
16474 && (prefixes & PREFIX_REPZ) != 0)
16475 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16477 OP_E (bytemode, sizeflag);
16481 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16486 /* Change cmpxchg8b to cmpxchg16b. */
16487 char *p = mnemonicendp - 2;
16488 mnemonicendp = stpcpy (p, "16b");
16491 else if ((prefixes & PREFIX_LOCK) != 0)
16493 if (prefixes & PREFIX_REPZ)
16494 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16495 if (prefixes & PREFIX_REPNZ)
16496 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16499 OP_M (bytemode, sizeflag);
16503 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16505 const char **names;
16509 switch (vex.length)
16523 oappend (names[reg]);
16527 CRC32_Fixup (int bytemode, int sizeflag)
16529 /* Add proper suffix to "crc32". */
16530 char *p = mnemonicendp;
16549 if (sizeflag & DFLAG)
16553 used_prefixes |= (prefixes & PREFIX_DATA);
16557 oappend (INTERNAL_DISASSEMBLER_ERROR);
16564 if (modrm.mod == 3)
16568 /* Skip mod/rm byte. */
16573 add = (rex & REX_B) ? 8 : 0;
16574 if (bytemode == b_mode)
16578 oappend (names8rex[modrm.rm + add]);
16580 oappend (names8[modrm.rm + add]);
16586 oappend (names64[modrm.rm + add]);
16587 else if ((prefixes & PREFIX_DATA))
16588 oappend (names16[modrm.rm + add]);
16590 oappend (names32[modrm.rm + add]);
16594 OP_E (bytemode, sizeflag);
16598 FXSAVE_Fixup (int bytemode, int sizeflag)
16600 /* Add proper suffix to "fxsave" and "fxrstor". */
16604 char *p = mnemonicendp;
16610 OP_M (bytemode, sizeflag);
16613 /* Display the destination register operand for instructions with
16617 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16620 const char **names;
16628 reg = vex.register_specifier;
16635 if (bytemode == vex_scalar_mode)
16637 oappend (names_xmm[reg]);
16641 switch (vex.length)
16648 case vex_vsib_q_w_dq_mode:
16649 case vex_vsib_q_w_d_mode:
16660 names = names_mask;
16674 case vex_vsib_q_w_dq_mode:
16675 case vex_vsib_q_w_d_mode:
16676 names = vex.w ? names_ymm : names_xmm;
16680 names = names_mask;
16694 oappend (names[reg]);
16697 /* Get the VEX immediate byte without moving codep. */
16699 static unsigned char
16700 get_vex_imm8 (int sizeflag, int opnum)
16702 int bytes_before_imm = 0;
16704 if (modrm.mod != 3)
16706 /* There are SIB/displacement bytes. */
16707 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16709 /* 32/64 bit address mode */
16710 int base = modrm.rm;
16712 /* Check SIB byte. */
16715 FETCH_DATA (the_info, codep + 1);
16717 /* When decoding the third source, don't increase
16718 bytes_before_imm as this has already been incremented
16719 by one in OP_E_memory while decoding the second
16722 bytes_before_imm++;
16725 /* Don't increase bytes_before_imm when decoding the third source,
16726 it has already been incremented by OP_E_memory while decoding
16727 the second source operand. */
16733 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16734 SIB == 5, there is a 4 byte displacement. */
16736 /* No displacement. */
16739 /* 4 byte displacement. */
16740 bytes_before_imm += 4;
16743 /* 1 byte displacement. */
16744 bytes_before_imm++;
16751 /* 16 bit address mode */
16752 /* Don't increase bytes_before_imm when decoding the third source,
16753 it has already been incremented by OP_E_memory while decoding
16754 the second source operand. */
16760 /* When modrm.rm == 6, there is a 2 byte displacement. */
16762 /* No displacement. */
16765 /* 2 byte displacement. */
16766 bytes_before_imm += 2;
16769 /* 1 byte displacement: when decoding the third source,
16770 don't increase bytes_before_imm as this has already
16771 been incremented by one in OP_E_memory while decoding
16772 the second source operand. */
16774 bytes_before_imm++;
16782 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16783 return codep [bytes_before_imm];
16787 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16789 const char **names;
16791 if (reg == -1 && modrm.mod != 3)
16793 OP_E_memory (bytemode, sizeflag);
16805 else if (reg > 7 && address_mode != mode_64bit)
16809 switch (vex.length)
16820 oappend (names[reg]);
16824 OP_EX_VexImmW (int bytemode, int sizeflag)
16827 static unsigned char vex_imm8;
16829 if (vex_w_done == 0)
16833 /* Skip mod/rm byte. */
16837 vex_imm8 = get_vex_imm8 (sizeflag, 0);
16840 reg = vex_imm8 >> 4;
16842 OP_EX_VexReg (bytemode, sizeflag, reg);
16844 else if (vex_w_done == 1)
16849 reg = vex_imm8 >> 4;
16851 OP_EX_VexReg (bytemode, sizeflag, reg);
16855 /* Output the imm8 directly. */
16856 scratchbuf[0] = '$';
16857 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16858 oappend_maybe_intel (scratchbuf);
16859 scratchbuf[0] = '\0';
16865 OP_Vex_2src (int bytemode, int sizeflag)
16867 if (modrm.mod == 3)
16869 int reg = modrm.rm;
16873 oappend (names_xmm[reg]);
16878 && (bytemode == v_mode || bytemode == v_swap_mode))
16880 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16881 used_prefixes |= (prefixes & PREFIX_DATA);
16883 OP_E (bytemode, sizeflag);
16888 OP_Vex_2src_1 (int bytemode, int sizeflag)
16890 if (modrm.mod == 3)
16892 /* Skip mod/rm byte. */
16898 oappend (names_xmm[vex.register_specifier]);
16900 OP_Vex_2src (bytemode, sizeflag);
16904 OP_Vex_2src_2 (int bytemode, int sizeflag)
16907 OP_Vex_2src (bytemode, sizeflag);
16909 oappend (names_xmm[vex.register_specifier]);
16913 OP_EX_VexW (int bytemode, int sizeflag)
16921 /* Skip mod/rm byte. */
16926 reg = get_vex_imm8 (sizeflag, 0) >> 4;
16931 reg = get_vex_imm8 (sizeflag, 1) >> 4;
16934 OP_EX_VexReg (bytemode, sizeflag, reg);
16938 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16939 int sizeflag ATTRIBUTE_UNUSED)
16941 /* Skip the immediate byte and check for invalid bits. */
16942 FETCH_DATA (the_info, codep + 1);
16943 if (*codep++ & 0xf)
16948 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16951 const char **names;
16953 FETCH_DATA (the_info, codep + 1);
16956 if (bytemode != x_mode)
16963 if (reg > 7 && address_mode != mode_64bit)
16966 switch (vex.length)
16977 oappend (names[reg]);
16981 OP_XMM_VexW (int bytemode, int sizeflag)
16983 /* Turn off the REX.W bit since it is used for swapping operands
16986 OP_XMM (bytemode, sizeflag);
16990 OP_EX_Vex (int bytemode, int sizeflag)
16992 if (modrm.mod != 3)
16994 if (vex.register_specifier != 0)
16998 OP_EX (bytemode, sizeflag);
17002 OP_XMM_Vex (int bytemode, int sizeflag)
17004 if (modrm.mod != 3)
17006 if (vex.register_specifier != 0)
17010 OP_XMM (bytemode, sizeflag);
17014 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17016 switch (vex.length)
17019 mnemonicendp = stpcpy (obuf, "vzeroupper");
17022 mnemonicendp = stpcpy (obuf, "vzeroall");
17029 static struct op vex_cmp_op[] =
17031 { STRING_COMMA_LEN ("eq") },
17032 { STRING_COMMA_LEN ("lt") },
17033 { STRING_COMMA_LEN ("le") },
17034 { STRING_COMMA_LEN ("unord") },
17035 { STRING_COMMA_LEN ("neq") },
17036 { STRING_COMMA_LEN ("nlt") },
17037 { STRING_COMMA_LEN ("nle") },
17038 { STRING_COMMA_LEN ("ord") },
17039 { STRING_COMMA_LEN ("eq_uq") },
17040 { STRING_COMMA_LEN ("nge") },
17041 { STRING_COMMA_LEN ("ngt") },
17042 { STRING_COMMA_LEN ("false") },
17043 { STRING_COMMA_LEN ("neq_oq") },
17044 { STRING_COMMA_LEN ("ge") },
17045 { STRING_COMMA_LEN ("gt") },
17046 { STRING_COMMA_LEN ("true") },
17047 { STRING_COMMA_LEN ("eq_os") },
17048 { STRING_COMMA_LEN ("lt_oq") },
17049 { STRING_COMMA_LEN ("le_oq") },
17050 { STRING_COMMA_LEN ("unord_s") },
17051 { STRING_COMMA_LEN ("neq_us") },
17052 { STRING_COMMA_LEN ("nlt_uq") },
17053 { STRING_COMMA_LEN ("nle_uq") },
17054 { STRING_COMMA_LEN ("ord_s") },
17055 { STRING_COMMA_LEN ("eq_us") },
17056 { STRING_COMMA_LEN ("nge_uq") },
17057 { STRING_COMMA_LEN ("ngt_uq") },
17058 { STRING_COMMA_LEN ("false_os") },
17059 { STRING_COMMA_LEN ("neq_os") },
17060 { STRING_COMMA_LEN ("ge_oq") },
17061 { STRING_COMMA_LEN ("gt_oq") },
17062 { STRING_COMMA_LEN ("true_us") },
17066 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17068 unsigned int cmp_type;
17070 FETCH_DATA (the_info, codep + 1);
17071 cmp_type = *codep++ & 0xff;
17072 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17075 char *p = mnemonicendp - 2;
17079 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17080 mnemonicendp += vex_cmp_op[cmp_type].len;
17084 /* We have a reserved extension byte. Output it directly. */
17085 scratchbuf[0] = '$';
17086 print_operand_value (scratchbuf + 1, 1, cmp_type);
17087 oappend_maybe_intel (scratchbuf);
17088 scratchbuf[0] = '\0';
17093 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17094 int sizeflag ATTRIBUTE_UNUSED)
17096 unsigned int cmp_type;
17101 FETCH_DATA (the_info, codep + 1);
17102 cmp_type = *codep++ & 0xff;
17103 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17104 If it's the case, print suffix, otherwise - print the immediate. */
17105 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17110 char *p = mnemonicendp - 2;
17112 /* vpcmp* can have both one- and two-lettered suffix. */
17126 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17127 mnemonicendp += simd_cmp_op[cmp_type].len;
17131 /* We have a reserved extension byte. Output it directly. */
17132 scratchbuf[0] = '$';
17133 print_operand_value (scratchbuf + 1, 1, cmp_type);
17134 oappend_maybe_intel (scratchbuf);
17135 scratchbuf[0] = '\0';
17139 static const struct op pclmul_op[] =
17141 { STRING_COMMA_LEN ("lql") },
17142 { STRING_COMMA_LEN ("hql") },
17143 { STRING_COMMA_LEN ("lqh") },
17144 { STRING_COMMA_LEN ("hqh") }
17148 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17149 int sizeflag ATTRIBUTE_UNUSED)
17151 unsigned int pclmul_type;
17153 FETCH_DATA (the_info, codep + 1);
17154 pclmul_type = *codep++ & 0xff;
17155 switch (pclmul_type)
17166 if (pclmul_type < ARRAY_SIZE (pclmul_op))
17169 char *p = mnemonicendp - 3;
17174 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17175 mnemonicendp += pclmul_op[pclmul_type].len;
17179 /* We have a reserved extension byte. Output it directly. */
17180 scratchbuf[0] = '$';
17181 print_operand_value (scratchbuf + 1, 1, pclmul_type);
17182 oappend_maybe_intel (scratchbuf);
17183 scratchbuf[0] = '\0';
17188 MOVBE_Fixup (int bytemode, int sizeflag)
17190 /* Add proper suffix to "movbe". */
17191 char *p = mnemonicendp;
17200 if (sizeflag & SUFFIX_ALWAYS)
17206 if (sizeflag & DFLAG)
17210 used_prefixes |= (prefixes & PREFIX_DATA);
17215 oappend (INTERNAL_DISASSEMBLER_ERROR);
17222 OP_M (bytemode, sizeflag);
17226 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17229 const char **names;
17231 /* Skip mod/rm byte. */
17245 oappend (names[reg]);
17249 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17251 const char **names;
17258 oappend (names[vex.register_specifier]);
17262 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17265 || (bytemode != mask_mode && bytemode != mask_bd_mode))
17269 if ((rex & REX_R) != 0 || !vex.r)
17275 oappend (names_mask [modrm.reg]);
17279 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17282 || (bytemode != evex_rounding_mode
17283 && bytemode != evex_sae_mode))
17285 if (modrm.mod == 3 && vex.b)
17288 case evex_rounding_mode:
17289 oappend (names_rounding[vex.ll]);
17291 case evex_sae_mode: