1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
30 /* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
40 #include "opcode/i386.h"
41 #include "libiberty.h"
45 static int print_insn (bfd_vma, disassemble_info *);
46 static void dofloat (int);
47 static void OP_ST (int, int);
48 static void OP_STi (int, int);
49 static int putop (const char *, int);
50 static void oappend (const char *);
51 static void append_seg (void);
52 static void OP_indirE (int, int);
53 static void print_operand_value (char *, int, bfd_vma);
54 static void OP_E_register (int, int);
55 static void OP_E_memory (int, int);
56 static void print_displacement (char *, bfd_vma);
57 static void OP_E (int, int);
58 static void OP_G (int, int);
59 static bfd_vma get64 (void);
60 static bfd_signed_vma get32 (void);
61 static bfd_signed_vma get32s (void);
62 static int get16 (void);
63 static void set_op (bfd_vma, int);
64 static void OP_Skip_MODRM (int, int);
65 static void OP_REG (int, int);
66 static void OP_IMREG (int, int);
67 static void OP_I (int, int);
68 static void OP_I64 (int, int);
69 static void OP_sI (int, int);
70 static void OP_J (int, int);
71 static void OP_SEG (int, int);
72 static void OP_DIR (int, int);
73 static void OP_OFF (int, int);
74 static void OP_OFF64 (int, int);
75 static void ptr_reg (int, int);
76 static void OP_ESreg (int, int);
77 static void OP_DSreg (int, int);
78 static void OP_C (int, int);
79 static void OP_D (int, int);
80 static void OP_T (int, int);
81 static void OP_R (int, int);
82 static void OP_MMX (int, int);
83 static void OP_XMM (int, int);
84 static void OP_EM (int, int);
85 static void OP_EX (int, int);
86 static void OP_EMC (int,int);
87 static void OP_MXC (int,int);
88 static void OP_MS (int, int);
89 static void OP_XS (int, int);
90 static void OP_M (int, int);
91 static void OP_VEX (int, int);
92 static void OP_EX_Vex (int, int);
93 static void OP_EX_VexW (int, int);
94 static void OP_EX_VexImmW (int, int);
95 static void OP_XMM_Vex (int, int);
96 static void OP_XMM_VexW (int, int);
97 static void OP_REG_VexI4 (int, int);
98 static void PCLMUL_Fixup (int, int);
99 static void VEXI4_Fixup (int, int);
100 static void VZERO_Fixup (int, int);
101 static void VCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void CMPXCHG8B_Fixup (int, int);
112 static void XMM_Fixup (int, int);
113 static void CRC32_Fixup (int, int);
114 static void FXSAVE_Fixup (int, int);
115 static void OP_LWPCB_E (int, int);
116 static void OP_LWP_E (int, int);
117 static void OP_Vex_2src_1 (int, int);
118 static void OP_Vex_2src_2 (int, int);
120 static void MOVBE_Fixup (int, int);
123 /* Points to first byte not fetched. */
124 bfd_byte *max_fetched;
125 bfd_byte the_buffer[MAX_MNEM_SIZE];
138 enum address_mode address_mode;
140 /* Flags for the prefixes for the current instruction. See below. */
143 /* REX prefix the current instruction. See below. */
145 /* Bits of REX we've already used. */
147 /* REX bits in original REX prefix ignored. */
148 static int rex_ignored;
149 /* Mark parts used in the REX prefix. When we are testing for
150 empty prefix (for 8bit register REX extension), just mask it
151 out. Otherwise test for REX bit is excuse for existence of REX
152 only in case value is nonzero. */
153 #define USED_REX(value) \
158 rex_used |= (value) | REX_OPCODE; \
161 rex_used |= REX_OPCODE; \
164 /* Flags for prefixes which we somehow handled when printing the
165 current instruction. */
166 static int used_prefixes;
168 /* Flags stored in PREFIXES. */
169 #define PREFIX_REPZ 1
170 #define PREFIX_REPNZ 2
171 #define PREFIX_LOCK 4
173 #define PREFIX_SS 0x10
174 #define PREFIX_DS 0x20
175 #define PREFIX_ES 0x40
176 #define PREFIX_FS 0x80
177 #define PREFIX_GS 0x100
178 #define PREFIX_DATA 0x200
179 #define PREFIX_ADDR 0x400
180 #define PREFIX_FWAIT 0x800
182 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
183 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
185 #define FETCH_DATA(info, addr) \
186 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
187 ? 1 : fetch_data ((info), (addr)))
190 fetch_data (struct disassemble_info *info, bfd_byte *addr)
193 struct dis_private *priv = (struct dis_private *) info->private_data;
194 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
196 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
197 status = (*info->read_memory_func) (start,
199 addr - priv->max_fetched,
205 /* If we did manage to read at least one byte, then
206 print_insn_i386 will do something sensible. Otherwise, print
207 an error. We do that here because this is where we know
209 if (priv->max_fetched == priv->the_buffer)
210 (*info->memory_error_func) (status, start, info);
211 longjmp (priv->bailout, 1);
214 priv->max_fetched = addr;
218 #define XX { NULL, 0 }
219 #define Bad_Opcode NULL, { { NULL, 0 } }
221 #define Eb { OP_E, b_mode }
222 #define EbS { OP_E, b_swap_mode }
223 #define Ev { OP_E, v_mode }
224 #define EvS { OP_E, v_swap_mode }
225 #define Ed { OP_E, d_mode }
226 #define Edq { OP_E, dq_mode }
227 #define Edqw { OP_E, dqw_mode }
228 #define Edqb { OP_E, dqb_mode }
229 #define Edqd { OP_E, dqd_mode }
230 #define Eq { OP_E, q_mode }
231 #define indirEv { OP_indirE, stack_v_mode }
232 #define indirEp { OP_indirE, f_mode }
233 #define stackEv { OP_E, stack_v_mode }
234 #define Em { OP_E, m_mode }
235 #define Ew { OP_E, w_mode }
236 #define M { OP_M, 0 } /* lea, lgdt, etc. */
237 #define Ma { OP_M, a_mode }
238 #define Mb { OP_M, b_mode }
239 #define Md { OP_M, d_mode }
240 #define Mo { OP_M, o_mode }
241 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
242 #define Mq { OP_M, q_mode }
243 #define Mx { OP_M, x_mode }
244 #define Mxmm { OP_M, xmm_mode }
245 #define Gb { OP_G, b_mode }
246 #define Gv { OP_G, v_mode }
247 #define Gd { OP_G, d_mode }
248 #define Gdq { OP_G, dq_mode }
249 #define Gm { OP_G, m_mode }
250 #define Gw { OP_G, w_mode }
251 #define Rd { OP_R, d_mode }
252 #define Rm { OP_R, m_mode }
253 #define Ib { OP_I, b_mode }
254 #define sIb { OP_sI, b_mode } /* sign extened byte */
255 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
256 #define Iv { OP_I, v_mode }
257 #define sIv { OP_sI, v_mode }
258 #define Iq { OP_I, q_mode }
259 #define Iv64 { OP_I64, v_mode }
260 #define Iw { OP_I, w_mode }
261 #define I1 { OP_I, const_1_mode }
262 #define Jb { OP_J, b_mode }
263 #define Jv { OP_J, v_mode }
264 #define Cm { OP_C, m_mode }
265 #define Dm { OP_D, m_mode }
266 #define Td { OP_T, d_mode }
267 #define Skip_MODRM { OP_Skip_MODRM, 0 }
269 #define RMeAX { OP_REG, eAX_reg }
270 #define RMeBX { OP_REG, eBX_reg }
271 #define RMeCX { OP_REG, eCX_reg }
272 #define RMeDX { OP_REG, eDX_reg }
273 #define RMeSP { OP_REG, eSP_reg }
274 #define RMeBP { OP_REG, eBP_reg }
275 #define RMeSI { OP_REG, eSI_reg }
276 #define RMeDI { OP_REG, eDI_reg }
277 #define RMrAX { OP_REG, rAX_reg }
278 #define RMrBX { OP_REG, rBX_reg }
279 #define RMrCX { OP_REG, rCX_reg }
280 #define RMrDX { OP_REG, rDX_reg }
281 #define RMrSP { OP_REG, rSP_reg }
282 #define RMrBP { OP_REG, rBP_reg }
283 #define RMrSI { OP_REG, rSI_reg }
284 #define RMrDI { OP_REG, rDI_reg }
285 #define RMAL { OP_REG, al_reg }
286 #define RMCL { OP_REG, cl_reg }
287 #define RMDL { OP_REG, dl_reg }
288 #define RMBL { OP_REG, bl_reg }
289 #define RMAH { OP_REG, ah_reg }
290 #define RMCH { OP_REG, ch_reg }
291 #define RMDH { OP_REG, dh_reg }
292 #define RMBH { OP_REG, bh_reg }
293 #define RMAX { OP_REG, ax_reg }
294 #define RMDX { OP_REG, dx_reg }
296 #define eAX { OP_IMREG, eAX_reg }
297 #define eBX { OP_IMREG, eBX_reg }
298 #define eCX { OP_IMREG, eCX_reg }
299 #define eDX { OP_IMREG, eDX_reg }
300 #define eSP { OP_IMREG, eSP_reg }
301 #define eBP { OP_IMREG, eBP_reg }
302 #define eSI { OP_IMREG, eSI_reg }
303 #define eDI { OP_IMREG, eDI_reg }
304 #define AL { OP_IMREG, al_reg }
305 #define CL { OP_IMREG, cl_reg }
306 #define DL { OP_IMREG, dl_reg }
307 #define BL { OP_IMREG, bl_reg }
308 #define AH { OP_IMREG, ah_reg }
309 #define CH { OP_IMREG, ch_reg }
310 #define DH { OP_IMREG, dh_reg }
311 #define BH { OP_IMREG, bh_reg }
312 #define AX { OP_IMREG, ax_reg }
313 #define DX { OP_IMREG, dx_reg }
314 #define zAX { OP_IMREG, z_mode_ax_reg }
315 #define indirDX { OP_IMREG, indir_dx_reg }
317 #define Sw { OP_SEG, w_mode }
318 #define Sv { OP_SEG, v_mode }
319 #define Ap { OP_DIR, 0 }
320 #define Ob { OP_OFF64, b_mode }
321 #define Ov { OP_OFF64, v_mode }
322 #define Xb { OP_DSreg, eSI_reg }
323 #define Xv { OP_DSreg, eSI_reg }
324 #define Xz { OP_DSreg, eSI_reg }
325 #define Yb { OP_ESreg, eDI_reg }
326 #define Yv { OP_ESreg, eDI_reg }
327 #define DSBX { OP_DSreg, eBX_reg }
329 #define es { OP_REG, es_reg }
330 #define ss { OP_REG, ss_reg }
331 #define cs { OP_REG, cs_reg }
332 #define ds { OP_REG, ds_reg }
333 #define fs { OP_REG, fs_reg }
334 #define gs { OP_REG, gs_reg }
336 #define MX { OP_MMX, 0 }
337 #define XM { OP_XMM, 0 }
338 #define XMScalar { OP_XMM, scalar_mode }
339 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
340 #define XMM { OP_XMM, xmm_mode }
341 #define EM { OP_EM, v_mode }
342 #define EMS { OP_EM, v_swap_mode }
343 #define EMd { OP_EM, d_mode }
344 #define EMx { OP_EM, x_mode }
345 #define EXw { OP_EX, w_mode }
346 #define EXd { OP_EX, d_mode }
347 #define EXdScalar { OP_EX, d_scalar_mode }
348 #define EXdS { OP_EX, d_swap_mode }
349 #define EXq { OP_EX, q_mode }
350 #define EXqScalar { OP_EX, q_scalar_mode }
351 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
352 #define EXqS { OP_EX, q_swap_mode }
353 #define EXx { OP_EX, x_mode }
354 #define EXxS { OP_EX, x_swap_mode }
355 #define EXxmm { OP_EX, xmm_mode }
356 #define EXxmmq { OP_EX, xmmq_mode }
357 #define EXxmm_mb { OP_EX, xmm_mb_mode }
358 #define EXxmm_mw { OP_EX, xmm_mw_mode }
359 #define EXxmm_md { OP_EX, xmm_md_mode }
360 #define EXxmm_mq { OP_EX, xmm_mq_mode }
361 #define EXxmmdw { OP_EX, xmmdw_mode }
362 #define EXxmmqd { OP_EX, xmmqd_mode }
363 #define EXymmq { OP_EX, ymmq_mode }
364 #define EXVexWdq { OP_EX, vex_w_dq_mode }
365 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
366 #define MS { OP_MS, v_mode }
367 #define XS { OP_XS, v_mode }
368 #define EMCq { OP_EMC, q_mode }
369 #define MXC { OP_MXC, 0 }
370 #define OPSUF { OP_3DNowSuffix, 0 }
371 #define CMP { CMP_Fixup, 0 }
372 #define XMM0 { XMM_Fixup, 0 }
373 #define FXSAVE { FXSAVE_Fixup, 0 }
374 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
375 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
377 #define Vex { OP_VEX, vex_mode }
378 #define VexScalar { OP_VEX, vex_scalar_mode }
379 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
380 #define Vex128 { OP_VEX, vex128_mode }
381 #define Vex256 { OP_VEX, vex256_mode }
382 #define VexGdq { OP_VEX, dq_mode }
383 #define VexI4 { VEXI4_Fixup, 0}
384 #define EXdVex { OP_EX_Vex, d_mode }
385 #define EXdVexS { OP_EX_Vex, d_swap_mode }
386 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
387 #define EXqVex { OP_EX_Vex, q_mode }
388 #define EXqVexS { OP_EX_Vex, q_swap_mode }
389 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
390 #define EXVexW { OP_EX_VexW, x_mode }
391 #define EXdVexW { OP_EX_VexW, d_mode }
392 #define EXqVexW { OP_EX_VexW, q_mode }
393 #define EXVexImmW { OP_EX_VexImmW, x_mode }
394 #define XMVex { OP_XMM_Vex, 0 }
395 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
396 #define XMVexW { OP_XMM_VexW, 0 }
397 #define XMVexI4 { OP_REG_VexI4, x_mode }
398 #define PCLMUL { PCLMUL_Fixup, 0 }
399 #define VZERO { VZERO_Fixup, 0 }
400 #define VCMP { VCMP_Fixup, 0 }
402 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
403 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
405 /* Used handle "rep" prefix for string instructions. */
406 #define Xbr { REP_Fixup, eSI_reg }
407 #define Xvr { REP_Fixup, eSI_reg }
408 #define Ybr { REP_Fixup, eDI_reg }
409 #define Yvr { REP_Fixup, eDI_reg }
410 #define Yzr { REP_Fixup, eDI_reg }
411 #define indirDXr { REP_Fixup, indir_dx_reg }
412 #define ALr { REP_Fixup, al_reg }
413 #define eAXr { REP_Fixup, eAX_reg }
415 #define cond_jump_flag { NULL, cond_jump_mode }
416 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
418 /* bits in sizeflag */
419 #define SUFFIX_ALWAYS 4
427 /* byte operand with operand swapped */
429 /* byte operand, sign extend like 'T' suffix */
431 /* operand size depends on prefixes */
433 /* operand size depends on prefixes with operand swapped */
437 /* double word operand */
439 /* double word operand with operand swapped */
441 /* quad word operand */
443 /* quad word operand with operand swapped */
445 /* ten-byte operand */
447 /* 16-byte XMM or 32-byte YMM operand */
449 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
451 /* 16-byte XMM operand */
453 /* 16-byte XMM or quad word operand */
455 /* XMM register or byte memory operand */
457 /* XMM register or word memory operand */
459 /* XMM register or double word memory operand */
461 /* XMM register or quad word memory operand */
463 /* 16-byte XMM, word or double word operand */
465 /* 16-byte XMM, double word or quad word operand */
467 /* 32-byte YMM or quad word operand */
469 /* 32-byte YMM or 16-byte word operand */
471 /* d_mode in 32bit, q_mode in 64bit mode. */
473 /* pair of v_mode operands */
477 /* operand size depends on REX prefixes. */
479 /* registers like dq_mode, memory like w_mode. */
481 /* 4- or 6-byte pointer operand */
484 /* v_mode for stack-related opcodes. */
486 /* non-quad operand size depends on prefixes */
488 /* 16-byte operand */
490 /* registers like dq_mode, memory like b_mode. */
492 /* registers like dq_mode, memory like d_mode. */
494 /* normal vex mode */
496 /* 128bit vex mode */
498 /* 256bit vex mode */
500 /* operand size depends on the VEX.W bit. */
503 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
504 vex_vsib_d_w_dq_mode,
505 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
506 vex_vsib_q_w_dq_mode,
508 /* scalar, ignore vector length. */
510 /* like d_mode, ignore vector length. */
512 /* like d_swap_mode, ignore vector length. */
514 /* like q_mode, ignore vector length. */
516 /* like q_swap_mode, ignore vector length. */
518 /* like vex_mode, ignore vector length. */
520 /* like vex_w_dq_mode, ignore vector length. */
521 vex_scalar_w_dq_mode,
586 #define FLOAT NULL, { { NULL, FLOATCODE } }
588 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
589 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
590 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
591 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
592 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
593 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
594 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
595 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
596 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
597 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
598 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
599 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
699 MOD_VEX_0F12_PREFIX_0,
701 MOD_VEX_0F16_PREFIX_0,
717 MOD_VEX_0FD7_PREFIX_2,
718 MOD_VEX_0FE7_PREFIX_2,
719 MOD_VEX_0FF0_PREFIX_3,
720 MOD_VEX_0F381A_PREFIX_2,
721 MOD_VEX_0F382A_PREFIX_2,
722 MOD_VEX_0F382C_PREFIX_2,
723 MOD_VEX_0F382D_PREFIX_2,
724 MOD_VEX_0F382E_PREFIX_2,
725 MOD_VEX_0F382F_PREFIX_2,
726 MOD_VEX_0F385A_PREFIX_2,
727 MOD_VEX_0F388C_PREFIX_2,
728 MOD_VEX_0F388E_PREFIX_2,
899 PREFIX_VEX_0F71_REG_2,
900 PREFIX_VEX_0F71_REG_4,
901 PREFIX_VEX_0F71_REG_6,
902 PREFIX_VEX_0F72_REG_2,
903 PREFIX_VEX_0F72_REG_4,
904 PREFIX_VEX_0F72_REG_6,
905 PREFIX_VEX_0F73_REG_2,
906 PREFIX_VEX_0F73_REG_3,
907 PREFIX_VEX_0F73_REG_6,
908 PREFIX_VEX_0F73_REG_7,
1074 PREFIX_VEX_0F38F3_REG_1,
1075 PREFIX_VEX_0F38F3_REG_2,
1076 PREFIX_VEX_0F38F3_REG_3,
1178 THREE_BYTE_0F38 = 0,
1199 VEX_LEN_0F10_P_1 = 0,
1203 VEX_LEN_0F12_P_0_M_0,
1204 VEX_LEN_0F12_P_0_M_1,
1207 VEX_LEN_0F16_P_0_M_0,
1208 VEX_LEN_0F16_P_0_M_1,
1242 VEX_LEN_0FAE_R_2_M_0,
1243 VEX_LEN_0FAE_R_3_M_0,
1252 VEX_LEN_0F381A_P_2_M_0,
1255 VEX_LEN_0F385A_P_2_M_0,
1262 VEX_LEN_0F38F3_R_1_P_0,
1263 VEX_LEN_0F38F3_R_2_P_0,
1264 VEX_LEN_0F38F3_R_3_P_0,
1306 VEX_LEN_0FXOP_09_80,
1497 VEX_W_0F381A_P_2_M_0,
1509 VEX_W_0F382A_P_2_M_0,
1511 VEX_W_0F382C_P_2_M_0,
1512 VEX_W_0F382D_P_2_M_0,
1513 VEX_W_0F382E_P_2_M_0,
1514 VEX_W_0F382F_P_2_M_0,
1536 VEX_W_0F385A_P_2_M_0,
1583 typedef void (*op_rtn) (int bytemode, int sizeflag);
1594 /* Upper case letters in the instruction names here are macros.
1595 'A' => print 'b' if no register operands or suffix_always is true
1596 'B' => print 'b' if suffix_always is true
1597 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1599 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1600 suffix_always is true
1601 'E' => print 'e' if 32-bit form of jcxz
1602 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1603 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1604 'H' => print ",pt" or ",pn" branch hint
1605 'I' => honor following macro letter even in Intel mode (implemented only
1606 for some of the macro letters)
1608 'K' => print 'd' or 'q' if rex prefix is present.
1609 'L' => print 'l' if suffix_always is true
1610 'M' => print 'r' if intel_mnemonic is false.
1611 'N' => print 'n' if instruction has no wait "prefix"
1612 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1613 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1614 or suffix_always is true. print 'q' if rex prefix is present.
1615 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1617 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1618 'S' => print 'w', 'l' or 'q' if suffix_always is true
1619 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1620 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1621 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1622 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1623 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1624 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1625 suffix_always is true.
1626 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1627 '!' => change condition from true to false or from false to true.
1628 '%' => add 1 upper case letter to the macro.
1630 2 upper case letter macros:
1631 "XY" => print 'x' or 'y' if no register operands or suffix_always
1633 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1634 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1635 or suffix_always is true
1636 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1637 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1638 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1639 "LW" => print 'd', 'q' depending on the VEX.W bit
1641 Many of the above letters print nothing in Intel mode. See "putop"
1644 Braces '{' and '}', and vertical bars '|', indicate alternative
1645 mnemonic strings for AT&T and Intel. */
1647 static const struct dis386 dis386[] = {
1649 { "addB", { Eb, Gb } },
1650 { "addS", { Ev, Gv } },
1651 { "addB", { Gb, EbS } },
1652 { "addS", { Gv, EvS } },
1653 { "addB", { AL, Ib } },
1654 { "addS", { eAX, Iv } },
1655 { X86_64_TABLE (X86_64_06) },
1656 { X86_64_TABLE (X86_64_07) },
1658 { "orB", { Eb, Gb } },
1659 { "orS", { Ev, Gv } },
1660 { "orB", { Gb, EbS } },
1661 { "orS", { Gv, EvS } },
1662 { "orB", { AL, Ib } },
1663 { "orS", { eAX, Iv } },
1664 { X86_64_TABLE (X86_64_0D) },
1665 { Bad_Opcode }, /* 0x0f extended opcode escape */
1667 { "adcB", { Eb, Gb } },
1668 { "adcS", { Ev, Gv } },
1669 { "adcB", { Gb, EbS } },
1670 { "adcS", { Gv, EvS } },
1671 { "adcB", { AL, Ib } },
1672 { "adcS", { eAX, Iv } },
1673 { X86_64_TABLE (X86_64_16) },
1674 { X86_64_TABLE (X86_64_17) },
1676 { "sbbB", { Eb, Gb } },
1677 { "sbbS", { Ev, Gv } },
1678 { "sbbB", { Gb, EbS } },
1679 { "sbbS", { Gv, EvS } },
1680 { "sbbB", { AL, Ib } },
1681 { "sbbS", { eAX, Iv } },
1682 { X86_64_TABLE (X86_64_1E) },
1683 { X86_64_TABLE (X86_64_1F) },
1685 { "andB", { Eb, Gb } },
1686 { "andS", { Ev, Gv } },
1687 { "andB", { Gb, EbS } },
1688 { "andS", { Gv, EvS } },
1689 { "andB", { AL, Ib } },
1690 { "andS", { eAX, Iv } },
1691 { Bad_Opcode }, /* SEG ES prefix */
1692 { X86_64_TABLE (X86_64_27) },
1694 { "subB", { Eb, Gb } },
1695 { "subS", { Ev, Gv } },
1696 { "subB", { Gb, EbS } },
1697 { "subS", { Gv, EvS } },
1698 { "subB", { AL, Ib } },
1699 { "subS", { eAX, Iv } },
1700 { Bad_Opcode }, /* SEG CS prefix */
1701 { X86_64_TABLE (X86_64_2F) },
1703 { "xorB", { Eb, Gb } },
1704 { "xorS", { Ev, Gv } },
1705 { "xorB", { Gb, EbS } },
1706 { "xorS", { Gv, EvS } },
1707 { "xorB", { AL, Ib } },
1708 { "xorS", { eAX, Iv } },
1709 { Bad_Opcode }, /* SEG SS prefix */
1710 { X86_64_TABLE (X86_64_37) },
1712 { "cmpB", { Eb, Gb } },
1713 { "cmpS", { Ev, Gv } },
1714 { "cmpB", { Gb, EbS } },
1715 { "cmpS", { Gv, EvS } },
1716 { "cmpB", { AL, Ib } },
1717 { "cmpS", { eAX, Iv } },
1718 { Bad_Opcode }, /* SEG DS prefix */
1719 { X86_64_TABLE (X86_64_3F) },
1721 { "inc{S|}", { RMeAX } },
1722 { "inc{S|}", { RMeCX } },
1723 { "inc{S|}", { RMeDX } },
1724 { "inc{S|}", { RMeBX } },
1725 { "inc{S|}", { RMeSP } },
1726 { "inc{S|}", { RMeBP } },
1727 { "inc{S|}", { RMeSI } },
1728 { "inc{S|}", { RMeDI } },
1730 { "dec{S|}", { RMeAX } },
1731 { "dec{S|}", { RMeCX } },
1732 { "dec{S|}", { RMeDX } },
1733 { "dec{S|}", { RMeBX } },
1734 { "dec{S|}", { RMeSP } },
1735 { "dec{S|}", { RMeBP } },
1736 { "dec{S|}", { RMeSI } },
1737 { "dec{S|}", { RMeDI } },
1739 { "pushV", { RMrAX } },
1740 { "pushV", { RMrCX } },
1741 { "pushV", { RMrDX } },
1742 { "pushV", { RMrBX } },
1743 { "pushV", { RMrSP } },
1744 { "pushV", { RMrBP } },
1745 { "pushV", { RMrSI } },
1746 { "pushV", { RMrDI } },
1748 { "popV", { RMrAX } },
1749 { "popV", { RMrCX } },
1750 { "popV", { RMrDX } },
1751 { "popV", { RMrBX } },
1752 { "popV", { RMrSP } },
1753 { "popV", { RMrBP } },
1754 { "popV", { RMrSI } },
1755 { "popV", { RMrDI } },
1757 { X86_64_TABLE (X86_64_60) },
1758 { X86_64_TABLE (X86_64_61) },
1759 { X86_64_TABLE (X86_64_62) },
1760 { X86_64_TABLE (X86_64_63) },
1761 { Bad_Opcode }, /* seg fs */
1762 { Bad_Opcode }, /* seg gs */
1763 { Bad_Opcode }, /* op size prefix */
1764 { Bad_Opcode }, /* adr size prefix */
1766 { "pushT", { sIv } },
1767 { "imulS", { Gv, Ev, Iv } },
1768 { "pushT", { sIbT } },
1769 { "imulS", { Gv, Ev, sIb } },
1770 { "ins{b|}", { Ybr, indirDX } },
1771 { X86_64_TABLE (X86_64_6D) },
1772 { "outs{b|}", { indirDXr, Xb } },
1773 { X86_64_TABLE (X86_64_6F) },
1775 { "joH", { Jb, XX, cond_jump_flag } },
1776 { "jnoH", { Jb, XX, cond_jump_flag } },
1777 { "jbH", { Jb, XX, cond_jump_flag } },
1778 { "jaeH", { Jb, XX, cond_jump_flag } },
1779 { "jeH", { Jb, XX, cond_jump_flag } },
1780 { "jneH", { Jb, XX, cond_jump_flag } },
1781 { "jbeH", { Jb, XX, cond_jump_flag } },
1782 { "jaH", { Jb, XX, cond_jump_flag } },
1784 { "jsH", { Jb, XX, cond_jump_flag } },
1785 { "jnsH", { Jb, XX, cond_jump_flag } },
1786 { "jpH", { Jb, XX, cond_jump_flag } },
1787 { "jnpH", { Jb, XX, cond_jump_flag } },
1788 { "jlH", { Jb, XX, cond_jump_flag } },
1789 { "jgeH", { Jb, XX, cond_jump_flag } },
1790 { "jleH", { Jb, XX, cond_jump_flag } },
1791 { "jgH", { Jb, XX, cond_jump_flag } },
1793 { REG_TABLE (REG_80) },
1794 { REG_TABLE (REG_81) },
1796 { REG_TABLE (REG_82) },
1797 { "testB", { Eb, Gb } },
1798 { "testS", { Ev, Gv } },
1799 { "xchgB", { Eb, Gb } },
1800 { "xchgS", { Ev, Gv } },
1802 { "movB", { Eb, Gb } },
1803 { "movS", { Ev, Gv } },
1804 { "movB", { Gb, EbS } },
1805 { "movS", { Gv, EvS } },
1806 { "movD", { Sv, Sw } },
1807 { MOD_TABLE (MOD_8D) },
1808 { "movD", { Sw, Sv } },
1809 { REG_TABLE (REG_8F) },
1811 { PREFIX_TABLE (PREFIX_90) },
1812 { "xchgS", { RMeCX, eAX } },
1813 { "xchgS", { RMeDX, eAX } },
1814 { "xchgS", { RMeBX, eAX } },
1815 { "xchgS", { RMeSP, eAX } },
1816 { "xchgS", { RMeBP, eAX } },
1817 { "xchgS", { RMeSI, eAX } },
1818 { "xchgS", { RMeDI, eAX } },
1820 { "cW{t|}R", { XX } },
1821 { "cR{t|}O", { XX } },
1822 { X86_64_TABLE (X86_64_9A) },
1823 { Bad_Opcode }, /* fwait */
1824 { "pushfT", { XX } },
1825 { "popfT", { XX } },
1829 { "mov%LB", { AL, Ob } },
1830 { "mov%LS", { eAX, Ov } },
1831 { "mov%LB", { Ob, AL } },
1832 { "mov%LS", { Ov, eAX } },
1833 { "movs{b|}", { Ybr, Xb } },
1834 { "movs{R|}", { Yvr, Xv } },
1835 { "cmps{b|}", { Xb, Yb } },
1836 { "cmps{R|}", { Xv, Yv } },
1838 { "testB", { AL, Ib } },
1839 { "testS", { eAX, Iv } },
1840 { "stosB", { Ybr, AL } },
1841 { "stosS", { Yvr, eAX } },
1842 { "lodsB", { ALr, Xb } },
1843 { "lodsS", { eAXr, Xv } },
1844 { "scasB", { AL, Yb } },
1845 { "scasS", { eAX, Yv } },
1847 { "movB", { RMAL, Ib } },
1848 { "movB", { RMCL, Ib } },
1849 { "movB", { RMDL, Ib } },
1850 { "movB", { RMBL, Ib } },
1851 { "movB", { RMAH, Ib } },
1852 { "movB", { RMCH, Ib } },
1853 { "movB", { RMDH, Ib } },
1854 { "movB", { RMBH, Ib } },
1856 { "mov%LV", { RMeAX, Iv64 } },
1857 { "mov%LV", { RMeCX, Iv64 } },
1858 { "mov%LV", { RMeDX, Iv64 } },
1859 { "mov%LV", { RMeBX, Iv64 } },
1860 { "mov%LV", { RMeSP, Iv64 } },
1861 { "mov%LV", { RMeBP, Iv64 } },
1862 { "mov%LV", { RMeSI, Iv64 } },
1863 { "mov%LV", { RMeDI, Iv64 } },
1865 { REG_TABLE (REG_C0) },
1866 { REG_TABLE (REG_C1) },
1869 { X86_64_TABLE (X86_64_C4) },
1870 { X86_64_TABLE (X86_64_C5) },
1871 { REG_TABLE (REG_C6) },
1872 { REG_TABLE (REG_C7) },
1874 { "enterT", { Iw, Ib } },
1875 { "leaveT", { XX } },
1876 { "Jret{|f}P", { Iw } },
1877 { "Jret{|f}P", { XX } },
1880 { X86_64_TABLE (X86_64_CE) },
1881 { "iretP", { XX } },
1883 { REG_TABLE (REG_D0) },
1884 { REG_TABLE (REG_D1) },
1885 { REG_TABLE (REG_D2) },
1886 { REG_TABLE (REG_D3) },
1887 { X86_64_TABLE (X86_64_D4) },
1888 { X86_64_TABLE (X86_64_D5) },
1890 { "xlat", { DSBX } },
1901 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
1902 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
1903 { "loopFH", { Jb, XX, loop_jcxz_flag } },
1904 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
1905 { "inB", { AL, Ib } },
1906 { "inG", { zAX, Ib } },
1907 { "outB", { Ib, AL } },
1908 { "outG", { Ib, zAX } },
1910 { "callT", { Jv } },
1912 { X86_64_TABLE (X86_64_EA) },
1914 { "inB", { AL, indirDX } },
1915 { "inG", { zAX, indirDX } },
1916 { "outB", { indirDX, AL } },
1917 { "outG", { indirDX, zAX } },
1919 { Bad_Opcode }, /* lock prefix */
1920 { "icebp", { XX } },
1921 { Bad_Opcode }, /* repne */
1922 { Bad_Opcode }, /* repz */
1925 { REG_TABLE (REG_F6) },
1926 { REG_TABLE (REG_F7) },
1934 { REG_TABLE (REG_FE) },
1935 { REG_TABLE (REG_FF) },
1938 static const struct dis386 dis386_twobyte[] = {
1940 { REG_TABLE (REG_0F00 ) },
1941 { REG_TABLE (REG_0F01 ) },
1942 { "larS", { Gv, Ew } },
1943 { "lslS", { Gv, Ew } },
1945 { "syscall", { XX } },
1947 { "sysretP", { XX } },
1950 { "wbinvd", { XX } },
1954 { REG_TABLE (REG_0F0D) },
1955 { "femms", { XX } },
1956 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
1958 { PREFIX_TABLE (PREFIX_0F10) },
1959 { PREFIX_TABLE (PREFIX_0F11) },
1960 { PREFIX_TABLE (PREFIX_0F12) },
1961 { MOD_TABLE (MOD_0F13) },
1962 { "unpcklpX", { XM, EXx } },
1963 { "unpckhpX", { XM, EXx } },
1964 { PREFIX_TABLE (PREFIX_0F16) },
1965 { MOD_TABLE (MOD_0F17) },
1967 { REG_TABLE (REG_0F18) },
1976 { MOD_TABLE (MOD_0F20) },
1977 { MOD_TABLE (MOD_0F21) },
1978 { MOD_TABLE (MOD_0F22) },
1979 { MOD_TABLE (MOD_0F23) },
1980 { MOD_TABLE (MOD_0F24) },
1982 { MOD_TABLE (MOD_0F26) },
1985 { "movapX", { XM, EXx } },
1986 { "movapX", { EXxS, XM } },
1987 { PREFIX_TABLE (PREFIX_0F2A) },
1988 { PREFIX_TABLE (PREFIX_0F2B) },
1989 { PREFIX_TABLE (PREFIX_0F2C) },
1990 { PREFIX_TABLE (PREFIX_0F2D) },
1991 { PREFIX_TABLE (PREFIX_0F2E) },
1992 { PREFIX_TABLE (PREFIX_0F2F) },
1994 { "wrmsr", { XX } },
1995 { "rdtsc", { XX } },
1996 { "rdmsr", { XX } },
1997 { "rdpmc", { XX } },
1998 { "sysenter", { XX } },
1999 { "sysexit", { XX } },
2001 { "getsec", { XX } },
2003 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2005 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2012 { "cmovoS", { Gv, Ev } },
2013 { "cmovnoS", { Gv, Ev } },
2014 { "cmovbS", { Gv, Ev } },
2015 { "cmovaeS", { Gv, Ev } },
2016 { "cmoveS", { Gv, Ev } },
2017 { "cmovneS", { Gv, Ev } },
2018 { "cmovbeS", { Gv, Ev } },
2019 { "cmovaS", { Gv, Ev } },
2021 { "cmovsS", { Gv, Ev } },
2022 { "cmovnsS", { Gv, Ev } },
2023 { "cmovpS", { Gv, Ev } },
2024 { "cmovnpS", { Gv, Ev } },
2025 { "cmovlS", { Gv, Ev } },
2026 { "cmovgeS", { Gv, Ev } },
2027 { "cmovleS", { Gv, Ev } },
2028 { "cmovgS", { Gv, Ev } },
2030 { MOD_TABLE (MOD_0F51) },
2031 { PREFIX_TABLE (PREFIX_0F51) },
2032 { PREFIX_TABLE (PREFIX_0F52) },
2033 { PREFIX_TABLE (PREFIX_0F53) },
2034 { "andpX", { XM, EXx } },
2035 { "andnpX", { XM, EXx } },
2036 { "orpX", { XM, EXx } },
2037 { "xorpX", { XM, EXx } },
2039 { PREFIX_TABLE (PREFIX_0F58) },
2040 { PREFIX_TABLE (PREFIX_0F59) },
2041 { PREFIX_TABLE (PREFIX_0F5A) },
2042 { PREFIX_TABLE (PREFIX_0F5B) },
2043 { PREFIX_TABLE (PREFIX_0F5C) },
2044 { PREFIX_TABLE (PREFIX_0F5D) },
2045 { PREFIX_TABLE (PREFIX_0F5E) },
2046 { PREFIX_TABLE (PREFIX_0F5F) },
2048 { PREFIX_TABLE (PREFIX_0F60) },
2049 { PREFIX_TABLE (PREFIX_0F61) },
2050 { PREFIX_TABLE (PREFIX_0F62) },
2051 { "packsswb", { MX, EM } },
2052 { "pcmpgtb", { MX, EM } },
2053 { "pcmpgtw", { MX, EM } },
2054 { "pcmpgtd", { MX, EM } },
2055 { "packuswb", { MX, EM } },
2057 { "punpckhbw", { MX, EM } },
2058 { "punpckhwd", { MX, EM } },
2059 { "punpckhdq", { MX, EM } },
2060 { "packssdw", { MX, EM } },
2061 { PREFIX_TABLE (PREFIX_0F6C) },
2062 { PREFIX_TABLE (PREFIX_0F6D) },
2063 { "movK", { MX, Edq } },
2064 { PREFIX_TABLE (PREFIX_0F6F) },
2066 { PREFIX_TABLE (PREFIX_0F70) },
2067 { REG_TABLE (REG_0F71) },
2068 { REG_TABLE (REG_0F72) },
2069 { REG_TABLE (REG_0F73) },
2070 { "pcmpeqb", { MX, EM } },
2071 { "pcmpeqw", { MX, EM } },
2072 { "pcmpeqd", { MX, EM } },
2075 { PREFIX_TABLE (PREFIX_0F78) },
2076 { PREFIX_TABLE (PREFIX_0F79) },
2077 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2079 { PREFIX_TABLE (PREFIX_0F7C) },
2080 { PREFIX_TABLE (PREFIX_0F7D) },
2081 { PREFIX_TABLE (PREFIX_0F7E) },
2082 { PREFIX_TABLE (PREFIX_0F7F) },
2084 { "joH", { Jv, XX, cond_jump_flag } },
2085 { "jnoH", { Jv, XX, cond_jump_flag } },
2086 { "jbH", { Jv, XX, cond_jump_flag } },
2087 { "jaeH", { Jv, XX, cond_jump_flag } },
2088 { "jeH", { Jv, XX, cond_jump_flag } },
2089 { "jneH", { Jv, XX, cond_jump_flag } },
2090 { "jbeH", { Jv, XX, cond_jump_flag } },
2091 { "jaH", { Jv, XX, cond_jump_flag } },
2093 { "jsH", { Jv, XX, cond_jump_flag } },
2094 { "jnsH", { Jv, XX, cond_jump_flag } },
2095 { "jpH", { Jv, XX, cond_jump_flag } },
2096 { "jnpH", { Jv, XX, cond_jump_flag } },
2097 { "jlH", { Jv, XX, cond_jump_flag } },
2098 { "jgeH", { Jv, XX, cond_jump_flag } },
2099 { "jleH", { Jv, XX, cond_jump_flag } },
2100 { "jgH", { Jv, XX, cond_jump_flag } },
2103 { "setno", { Eb } },
2105 { "setae", { Eb } },
2107 { "setne", { Eb } },
2108 { "setbe", { Eb } },
2112 { "setns", { Eb } },
2114 { "setnp", { Eb } },
2116 { "setge", { Eb } },
2117 { "setle", { Eb } },
2120 { "pushT", { fs } },
2122 { "cpuid", { XX } },
2123 { "btS", { Ev, Gv } },
2124 { "shldS", { Ev, Gv, Ib } },
2125 { "shldS", { Ev, Gv, CL } },
2126 { REG_TABLE (REG_0FA6) },
2127 { REG_TABLE (REG_0FA7) },
2129 { "pushT", { gs } },
2132 { "btsS", { Ev, Gv } },
2133 { "shrdS", { Ev, Gv, Ib } },
2134 { "shrdS", { Ev, Gv, CL } },
2135 { REG_TABLE (REG_0FAE) },
2136 { "imulS", { Gv, Ev } },
2138 { "cmpxchgB", { Eb, Gb } },
2139 { "cmpxchgS", { Ev, Gv } },
2140 { MOD_TABLE (MOD_0FB2) },
2141 { "btrS", { Ev, Gv } },
2142 { MOD_TABLE (MOD_0FB4) },
2143 { MOD_TABLE (MOD_0FB5) },
2144 { "movz{bR|x}", { Gv, Eb } },
2145 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
2147 { PREFIX_TABLE (PREFIX_0FB8) },
2149 { REG_TABLE (REG_0FBA) },
2150 { "btcS", { Ev, Gv } },
2151 { PREFIX_TABLE (PREFIX_0FBC) },
2152 { PREFIX_TABLE (PREFIX_0FBD) },
2153 { "movs{bR|x}", { Gv, Eb } },
2154 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
2156 { "xaddB", { Eb, Gb } },
2157 { "xaddS", { Ev, Gv } },
2158 { PREFIX_TABLE (PREFIX_0FC2) },
2159 { PREFIX_TABLE (PREFIX_0FC3) },
2160 { "pinsrw", { MX, Edqw, Ib } },
2161 { "pextrw", { Gdq, MS, Ib } },
2162 { "shufpX", { XM, EXx, Ib } },
2163 { REG_TABLE (REG_0FC7) },
2165 { "bswap", { RMeAX } },
2166 { "bswap", { RMeCX } },
2167 { "bswap", { RMeDX } },
2168 { "bswap", { RMeBX } },
2169 { "bswap", { RMeSP } },
2170 { "bswap", { RMeBP } },
2171 { "bswap", { RMeSI } },
2172 { "bswap", { RMeDI } },
2174 { PREFIX_TABLE (PREFIX_0FD0) },
2175 { "psrlw", { MX, EM } },
2176 { "psrld", { MX, EM } },
2177 { "psrlq", { MX, EM } },
2178 { "paddq", { MX, EM } },
2179 { "pmullw", { MX, EM } },
2180 { PREFIX_TABLE (PREFIX_0FD6) },
2181 { MOD_TABLE (MOD_0FD7) },
2183 { "psubusb", { MX, EM } },
2184 { "psubusw", { MX, EM } },
2185 { "pminub", { MX, EM } },
2186 { "pand", { MX, EM } },
2187 { "paddusb", { MX, EM } },
2188 { "paddusw", { MX, EM } },
2189 { "pmaxub", { MX, EM } },
2190 { "pandn", { MX, EM } },
2192 { "pavgb", { MX, EM } },
2193 { "psraw", { MX, EM } },
2194 { "psrad", { MX, EM } },
2195 { "pavgw", { MX, EM } },
2196 { "pmulhuw", { MX, EM } },
2197 { "pmulhw", { MX, EM } },
2198 { PREFIX_TABLE (PREFIX_0FE6) },
2199 { PREFIX_TABLE (PREFIX_0FE7) },
2201 { "psubsb", { MX, EM } },
2202 { "psubsw", { MX, EM } },
2203 { "pminsw", { MX, EM } },
2204 { "por", { MX, EM } },
2205 { "paddsb", { MX, EM } },
2206 { "paddsw", { MX, EM } },
2207 { "pmaxsw", { MX, EM } },
2208 { "pxor", { MX, EM } },
2210 { PREFIX_TABLE (PREFIX_0FF0) },
2211 { "psllw", { MX, EM } },
2212 { "pslld", { MX, EM } },
2213 { "psllq", { MX, EM } },
2214 { "pmuludq", { MX, EM } },
2215 { "pmaddwd", { MX, EM } },
2216 { "psadbw", { MX, EM } },
2217 { PREFIX_TABLE (PREFIX_0FF7) },
2219 { "psubb", { MX, EM } },
2220 { "psubw", { MX, EM } },
2221 { "psubd", { MX, EM } },
2222 { "psubq", { MX, EM } },
2223 { "paddb", { MX, EM } },
2224 { "paddw", { MX, EM } },
2225 { "paddd", { MX, EM } },
2229 static const unsigned char onebyte_has_modrm[256] = {
2230 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2231 /* ------------------------------- */
2232 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2233 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2234 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2235 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2236 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2237 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2238 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2239 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2240 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2241 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2242 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2243 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2244 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2245 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2246 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2247 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2248 /* ------------------------------- */
2249 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2252 static const unsigned char twobyte_has_modrm[256] = {
2253 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2254 /* ------------------------------- */
2255 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2256 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2257 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2258 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2259 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2260 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2261 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2262 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2263 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2264 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2265 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2266 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2267 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2268 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2269 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2270 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
2271 /* ------------------------------- */
2272 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2275 static char obuf[100];
2277 static char *mnemonicendp;
2278 static char scratchbuf[100];
2279 static unsigned char *start_codep;
2280 static unsigned char *insn_codep;
2281 static unsigned char *codep;
2282 static int last_lock_prefix;
2283 static int last_repz_prefix;
2284 static int last_repnz_prefix;
2285 static int last_data_prefix;
2286 static int last_addr_prefix;
2287 static int last_rex_prefix;
2288 static int last_seg_prefix;
2289 #define MAX_CODE_LENGTH 15
2290 /* We can up to 14 prefixes since the maximum instruction length is
2292 static int all_prefixes[MAX_CODE_LENGTH - 1];
2293 static disassemble_info *the_info;
2301 static unsigned char need_modrm;
2311 int register_specifier;
2317 static unsigned char need_vex;
2318 static unsigned char need_vex_reg;
2319 static unsigned char vex_w_done;
2327 /* If we are accessing mod/rm/reg without need_modrm set, then the
2328 values are stale. Hitting this abort likely indicates that you
2329 need to update onebyte_has_modrm or twobyte_has_modrm. */
2330 #define MODRM_CHECK if (!need_modrm) abort ()
2332 static const char **names64;
2333 static const char **names32;
2334 static const char **names16;
2335 static const char **names8;
2336 static const char **names8rex;
2337 static const char **names_seg;
2338 static const char *index64;
2339 static const char *index32;
2340 static const char **index16;
2342 static const char *intel_names64[] = {
2343 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2344 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2346 static const char *intel_names32[] = {
2347 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2348 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2350 static const char *intel_names16[] = {
2351 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2352 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2354 static const char *intel_names8[] = {
2355 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2357 static const char *intel_names8rex[] = {
2358 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2359 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2361 static const char *intel_names_seg[] = {
2362 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2364 static const char *intel_index64 = "riz";
2365 static const char *intel_index32 = "eiz";
2366 static const char *intel_index16[] = {
2367 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2370 static const char *att_names64[] = {
2371 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2372 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2374 static const char *att_names32[] = {
2375 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2376 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2378 static const char *att_names16[] = {
2379 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2380 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2382 static const char *att_names8[] = {
2383 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2385 static const char *att_names8rex[] = {
2386 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2387 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2389 static const char *att_names_seg[] = {
2390 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2392 static const char *att_index64 = "%riz";
2393 static const char *att_index32 = "%eiz";
2394 static const char *att_index16[] = {
2395 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2398 static const char **names_mm;
2399 static const char *intel_names_mm[] = {
2400 "mm0", "mm1", "mm2", "mm3",
2401 "mm4", "mm5", "mm6", "mm7"
2403 static const char *att_names_mm[] = {
2404 "%mm0", "%mm1", "%mm2", "%mm3",
2405 "%mm4", "%mm5", "%mm6", "%mm7"
2408 static const char **names_xmm;
2409 static const char *intel_names_xmm[] = {
2410 "xmm0", "xmm1", "xmm2", "xmm3",
2411 "xmm4", "xmm5", "xmm6", "xmm7",
2412 "xmm8", "xmm9", "xmm10", "xmm11",
2413 "xmm12", "xmm13", "xmm14", "xmm15"
2415 static const char *att_names_xmm[] = {
2416 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2417 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2418 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2419 "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2422 static const char **names_ymm;
2423 static const char *intel_names_ymm[] = {
2424 "ymm0", "ymm1", "ymm2", "ymm3",
2425 "ymm4", "ymm5", "ymm6", "ymm7",
2426 "ymm8", "ymm9", "ymm10", "ymm11",
2427 "ymm12", "ymm13", "ymm14", "ymm15"
2429 static const char *att_names_ymm[] = {
2430 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2431 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2432 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2433 "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2436 static const struct dis386 reg_table[][8] = {
2439 { "addA", { Eb, Ib } },
2440 { "orA", { Eb, Ib } },
2441 { "adcA", { Eb, Ib } },
2442 { "sbbA", { Eb, Ib } },
2443 { "andA", { Eb, Ib } },
2444 { "subA", { Eb, Ib } },
2445 { "xorA", { Eb, Ib } },
2446 { "cmpA", { Eb, Ib } },
2450 { "addQ", { Ev, Iv } },
2451 { "orQ", { Ev, Iv } },
2452 { "adcQ", { Ev, Iv } },
2453 { "sbbQ", { Ev, Iv } },
2454 { "andQ", { Ev, Iv } },
2455 { "subQ", { Ev, Iv } },
2456 { "xorQ", { Ev, Iv } },
2457 { "cmpQ", { Ev, Iv } },
2461 { "addQ", { Ev, sIb } },
2462 { "orQ", { Ev, sIb } },
2463 { "adcQ", { Ev, sIb } },
2464 { "sbbQ", { Ev, sIb } },
2465 { "andQ", { Ev, sIb } },
2466 { "subQ", { Ev, sIb } },
2467 { "xorQ", { Ev, sIb } },
2468 { "cmpQ", { Ev, sIb } },
2472 { "popU", { stackEv } },
2473 { XOP_8F_TABLE (XOP_09) },
2477 { XOP_8F_TABLE (XOP_09) },
2481 { "rolA", { Eb, Ib } },
2482 { "rorA", { Eb, Ib } },
2483 { "rclA", { Eb, Ib } },
2484 { "rcrA", { Eb, Ib } },
2485 { "shlA", { Eb, Ib } },
2486 { "shrA", { Eb, Ib } },
2488 { "sarA", { Eb, Ib } },
2492 { "rolQ", { Ev, Ib } },
2493 { "rorQ", { Ev, Ib } },
2494 { "rclQ", { Ev, Ib } },
2495 { "rcrQ", { Ev, Ib } },
2496 { "shlQ", { Ev, Ib } },
2497 { "shrQ", { Ev, Ib } },
2499 { "sarQ", { Ev, Ib } },
2503 { "movA", { Eb, Ib } },
2507 { "movQ", { Ev, Iv } },
2511 { "rolA", { Eb, I1 } },
2512 { "rorA", { Eb, I1 } },
2513 { "rclA", { Eb, I1 } },
2514 { "rcrA", { Eb, I1 } },
2515 { "shlA", { Eb, I1 } },
2516 { "shrA", { Eb, I1 } },
2518 { "sarA", { Eb, I1 } },
2522 { "rolQ", { Ev, I1 } },
2523 { "rorQ", { Ev, I1 } },
2524 { "rclQ", { Ev, I1 } },
2525 { "rcrQ", { Ev, I1 } },
2526 { "shlQ", { Ev, I1 } },
2527 { "shrQ", { Ev, I1 } },
2529 { "sarQ", { Ev, I1 } },
2533 { "rolA", { Eb, CL } },
2534 { "rorA", { Eb, CL } },
2535 { "rclA", { Eb, CL } },
2536 { "rcrA", { Eb, CL } },
2537 { "shlA", { Eb, CL } },
2538 { "shrA", { Eb, CL } },
2540 { "sarA", { Eb, CL } },
2544 { "rolQ", { Ev, CL } },
2545 { "rorQ", { Ev, CL } },
2546 { "rclQ", { Ev, CL } },
2547 { "rcrQ", { Ev, CL } },
2548 { "shlQ", { Ev, CL } },
2549 { "shrQ", { Ev, CL } },
2551 { "sarQ", { Ev, CL } },
2555 { "testA", { Eb, Ib } },
2559 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
2560 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
2561 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
2562 { "idivA", { Eb } }, /* and idiv for consistency. */
2566 { "testQ", { Ev, Iv } },
2570 { "mulQ", { Ev } }, /* Don't print the implicit register. */
2571 { "imulQ", { Ev } },
2573 { "idivQ", { Ev } },
2584 { "call{T|}", { indirEv } },
2585 { "Jcall{T|}", { indirEp } },
2586 { "jmp{T|}", { indirEv } },
2587 { "Jjmp{T|}", { indirEp } },
2588 { "pushU", { stackEv } },
2593 { "sldtD", { Sv } },
2604 { MOD_TABLE (MOD_0F01_REG_0) },
2605 { MOD_TABLE (MOD_0F01_REG_1) },
2606 { MOD_TABLE (MOD_0F01_REG_2) },
2607 { MOD_TABLE (MOD_0F01_REG_3) },
2608 { "smswD", { Sv } },
2611 { MOD_TABLE (MOD_0F01_REG_7) },
2615 { "prefetch", { Mb } },
2616 { "prefetchw", { Mb } },
2620 { MOD_TABLE (MOD_0F18_REG_0) },
2621 { MOD_TABLE (MOD_0F18_REG_1) },
2622 { MOD_TABLE (MOD_0F18_REG_2) },
2623 { MOD_TABLE (MOD_0F18_REG_3) },
2629 { MOD_TABLE (MOD_0F71_REG_2) },
2631 { MOD_TABLE (MOD_0F71_REG_4) },
2633 { MOD_TABLE (MOD_0F71_REG_6) },
2639 { MOD_TABLE (MOD_0F72_REG_2) },
2641 { MOD_TABLE (MOD_0F72_REG_4) },
2643 { MOD_TABLE (MOD_0F72_REG_6) },
2649 { MOD_TABLE (MOD_0F73_REG_2) },
2650 { MOD_TABLE (MOD_0F73_REG_3) },
2653 { MOD_TABLE (MOD_0F73_REG_6) },
2654 { MOD_TABLE (MOD_0F73_REG_7) },
2658 { "montmul", { { OP_0f07, 0 } } },
2659 { "xsha1", { { OP_0f07, 0 } } },
2660 { "xsha256", { { OP_0f07, 0 } } },
2664 { "xstore-rng", { { OP_0f07, 0 } } },
2665 { "xcrypt-ecb", { { OP_0f07, 0 } } },
2666 { "xcrypt-cbc", { { OP_0f07, 0 } } },
2667 { "xcrypt-ctr", { { OP_0f07, 0 } } },
2668 { "xcrypt-cfb", { { OP_0f07, 0 } } },
2669 { "xcrypt-ofb", { { OP_0f07, 0 } } },
2673 { MOD_TABLE (MOD_0FAE_REG_0) },
2674 { MOD_TABLE (MOD_0FAE_REG_1) },
2675 { MOD_TABLE (MOD_0FAE_REG_2) },
2676 { MOD_TABLE (MOD_0FAE_REG_3) },
2677 { MOD_TABLE (MOD_0FAE_REG_4) },
2678 { MOD_TABLE (MOD_0FAE_REG_5) },
2679 { MOD_TABLE (MOD_0FAE_REG_6) },
2680 { MOD_TABLE (MOD_0FAE_REG_7) },
2688 { "btQ", { Ev, Ib } },
2689 { "btsQ", { Ev, Ib } },
2690 { "btrQ", { Ev, Ib } },
2691 { "btcQ", { Ev, Ib } },
2696 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2701 { MOD_TABLE (MOD_0FC7_REG_6) },
2702 { MOD_TABLE (MOD_0FC7_REG_7) },
2708 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
2710 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
2712 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
2718 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
2720 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
2722 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
2728 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
2729 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
2732 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
2733 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
2739 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2740 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2742 /* REG_VEX_0F38F3 */
2745 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
2746 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
2747 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
2751 { "llwpcb", { { OP_LWPCB_E, 0 } } },
2752 { "slwpcb", { { OP_LWPCB_E, 0 } } },
2756 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
2757 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
2759 /* REG_XOP_TBM_01 */
2762 { "blcfill", { { OP_LWP_E, 0 }, Ev } },
2763 { "blsfill", { { OP_LWP_E, 0 }, Ev } },
2764 { "blcs", { { OP_LWP_E, 0 }, Ev } },
2765 { "tzmsk", { { OP_LWP_E, 0 }, Ev } },
2766 { "blcic", { { OP_LWP_E, 0 }, Ev } },
2767 { "blsic", { { OP_LWP_E, 0 }, Ev } },
2768 { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
2770 /* REG_XOP_TBM_02 */
2773 { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
2778 { "blci", { { OP_LWP_E, 0 }, Ev } },
2782 static const struct dis386 prefix_table[][4] = {
2785 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2786 { "pause", { XX } },
2787 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2792 { "movups", { XM, EXx } },
2793 { "movss", { XM, EXd } },
2794 { "movupd", { XM, EXx } },
2795 { "movsd", { XM, EXq } },
2800 { "movups", { EXxS, XM } },
2801 { "movss", { EXdS, XM } },
2802 { "movupd", { EXxS, XM } },
2803 { "movsd", { EXqS, XM } },
2808 { MOD_TABLE (MOD_0F12_PREFIX_0) },
2809 { "movsldup", { XM, EXx } },
2810 { "movlpd", { XM, EXq } },
2811 { "movddup", { XM, EXq } },
2816 { MOD_TABLE (MOD_0F16_PREFIX_0) },
2817 { "movshdup", { XM, EXx } },
2818 { "movhpd", { XM, EXq } },
2823 { "cvtpi2ps", { XM, EMCq } },
2824 { "cvtsi2ss%LQ", { XM, Ev } },
2825 { "cvtpi2pd", { XM, EMCq } },
2826 { "cvtsi2sd%LQ", { XM, Ev } },
2831 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2832 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2833 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2834 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2839 { "cvttps2pi", { MXC, EXq } },
2840 { "cvttss2siY", { Gv, EXd } },
2841 { "cvttpd2pi", { MXC, EXx } },
2842 { "cvttsd2siY", { Gv, EXq } },
2847 { "cvtps2pi", { MXC, EXq } },
2848 { "cvtss2siY", { Gv, EXd } },
2849 { "cvtpd2pi", { MXC, EXx } },
2850 { "cvtsd2siY", { Gv, EXq } },
2855 { "ucomiss",{ XM, EXd } },
2857 { "ucomisd",{ XM, EXq } },
2862 { "comiss", { XM, EXd } },
2864 { "comisd", { XM, EXq } },
2869 { "sqrtps", { XM, EXx } },
2870 { "sqrtss", { XM, EXd } },
2871 { "sqrtpd", { XM, EXx } },
2872 { "sqrtsd", { XM, EXq } },
2877 { "rsqrtps",{ XM, EXx } },
2878 { "rsqrtss",{ XM, EXd } },
2883 { "rcpps", { XM, EXx } },
2884 { "rcpss", { XM, EXd } },
2889 { "addps", { XM, EXx } },
2890 { "addss", { XM, EXd } },
2891 { "addpd", { XM, EXx } },
2892 { "addsd", { XM, EXq } },
2897 { "mulps", { XM, EXx } },
2898 { "mulss", { XM, EXd } },
2899 { "mulpd", { XM, EXx } },
2900 { "mulsd", { XM, EXq } },
2905 { "cvtps2pd", { XM, EXq } },
2906 { "cvtss2sd", { XM, EXd } },
2907 { "cvtpd2ps", { XM, EXx } },
2908 { "cvtsd2ss", { XM, EXq } },
2913 { "cvtdq2ps", { XM, EXx } },
2914 { "cvttps2dq", { XM, EXx } },
2915 { "cvtps2dq", { XM, EXx } },
2920 { "subps", { XM, EXx } },
2921 { "subss", { XM, EXd } },
2922 { "subpd", { XM, EXx } },
2923 { "subsd", { XM, EXq } },
2928 { "minps", { XM, EXx } },
2929 { "minss", { XM, EXd } },
2930 { "minpd", { XM, EXx } },
2931 { "minsd", { XM, EXq } },
2936 { "divps", { XM, EXx } },
2937 { "divss", { XM, EXd } },
2938 { "divpd", { XM, EXx } },
2939 { "divsd", { XM, EXq } },
2944 { "maxps", { XM, EXx } },
2945 { "maxss", { XM, EXd } },
2946 { "maxpd", { XM, EXx } },
2947 { "maxsd", { XM, EXq } },
2952 { "punpcklbw",{ MX, EMd } },
2954 { "punpcklbw",{ MX, EMx } },
2959 { "punpcklwd",{ MX, EMd } },
2961 { "punpcklwd",{ MX, EMx } },
2966 { "punpckldq",{ MX, EMd } },
2968 { "punpckldq",{ MX, EMx } },
2975 { "punpcklqdq", { XM, EXx } },
2982 { "punpckhqdq", { XM, EXx } },
2987 { "movq", { MX, EM } },
2988 { "movdqu", { XM, EXx } },
2989 { "movdqa", { XM, EXx } },
2994 { "pshufw", { MX, EM, Ib } },
2995 { "pshufhw",{ XM, EXx, Ib } },
2996 { "pshufd", { XM, EXx, Ib } },
2997 { "pshuflw",{ XM, EXx, Ib } },
3000 /* PREFIX_0F73_REG_3 */
3004 { "psrldq", { XS, Ib } },
3007 /* PREFIX_0F73_REG_7 */
3011 { "pslldq", { XS, Ib } },
3016 {"vmread", { Em, Gm } },
3018 {"extrq", { XS, Ib, Ib } },
3019 {"insertq", { XM, XS, Ib, Ib } },
3024 {"vmwrite", { Gm, Em } },
3026 {"extrq", { XM, XS } },
3027 {"insertq", { XM, XS } },
3034 { "haddpd", { XM, EXx } },
3035 { "haddps", { XM, EXx } },
3042 { "hsubpd", { XM, EXx } },
3043 { "hsubps", { XM, EXx } },
3048 { "movK", { Edq, MX } },
3049 { "movq", { XM, EXq } },
3050 { "movK", { Edq, XM } },
3055 { "movq", { EMS, MX } },
3056 { "movdqu", { EXxS, XM } },
3057 { "movdqa", { EXxS, XM } },
3060 /* PREFIX_0FAE_REG_0 */
3063 { "rdfsbase", { Ev } },
3066 /* PREFIX_0FAE_REG_1 */
3069 { "rdgsbase", { Ev } },
3072 /* PREFIX_0FAE_REG_2 */
3075 { "wrfsbase", { Ev } },
3078 /* PREFIX_0FAE_REG_3 */
3081 { "wrgsbase", { Ev } },
3087 { "popcntS", { Gv, Ev } },
3092 { "bsfS", { Gv, Ev } },
3093 { "tzcntS", { Gv, Ev } },
3094 { "bsfS", { Gv, Ev } },
3099 { "bsrS", { Gv, Ev } },
3100 { "lzcntS", { Gv, Ev } },
3101 { "bsrS", { Gv, Ev } },
3106 { "cmpps", { XM, EXx, CMP } },
3107 { "cmpss", { XM, EXd, CMP } },
3108 { "cmppd", { XM, EXx, CMP } },
3109 { "cmpsd", { XM, EXq, CMP } },
3114 { "movntiS", { Ma, Gv } },
3117 /* PREFIX_0FC7_REG_6 */
3119 { "vmptrld",{ Mq } },
3120 { "vmxon", { Mq } },
3121 { "vmclear",{ Mq } },
3128 { "addsubpd", { XM, EXx } },
3129 { "addsubps", { XM, EXx } },
3135 { "movq2dq",{ XM, MS } },
3136 { "movq", { EXqS, XM } },
3137 { "movdq2q",{ MX, XS } },
3143 { "cvtdq2pd", { XM, EXq } },
3144 { "cvttpd2dq", { XM, EXx } },
3145 { "cvtpd2dq", { XM, EXx } },
3150 { "movntq", { Mq, MX } },
3152 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3160 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3165 { "maskmovq", { MX, MS } },
3167 { "maskmovdqu", { XM, XS } },
3174 { "pblendvb", { XM, EXx, XMM0 } },
3181 { "blendvps", { XM, EXx, XMM0 } },
3188 { "blendvpd", { XM, EXx, XMM0 } },
3195 { "ptest", { XM, EXx } },
3202 { "pmovsxbw", { XM, EXq } },
3209 { "pmovsxbd", { XM, EXd } },
3216 { "pmovsxbq", { XM, EXw } },
3223 { "pmovsxwd", { XM, EXq } },
3230 { "pmovsxwq", { XM, EXd } },
3237 { "pmovsxdq", { XM, EXq } },
3244 { "pmuldq", { XM, EXx } },
3251 { "pcmpeqq", { XM, EXx } },
3258 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3265 { "packusdw", { XM, EXx } },
3272 { "pmovzxbw", { XM, EXq } },
3279 { "pmovzxbd", { XM, EXd } },
3286 { "pmovzxbq", { XM, EXw } },
3293 { "pmovzxwd", { XM, EXq } },
3300 { "pmovzxwq", { XM, EXd } },
3307 { "pmovzxdq", { XM, EXq } },
3314 { "pcmpgtq", { XM, EXx } },
3321 { "pminsb", { XM, EXx } },
3328 { "pminsd", { XM, EXx } },
3335 { "pminuw", { XM, EXx } },
3342 { "pminud", { XM, EXx } },
3349 { "pmaxsb", { XM, EXx } },
3356 { "pmaxsd", { XM, EXx } },
3363 { "pmaxuw", { XM, EXx } },
3370 { "pmaxud", { XM, EXx } },
3377 { "pmulld", { XM, EXx } },
3384 { "phminposuw", { XM, EXx } },
3391 { "invept", { Gm, Mo } },
3398 { "invvpid", { Gm, Mo } },
3405 { "invpcid", { Gm, M } },
3412 { "aesimc", { XM, EXx } },
3419 { "aesenc", { XM, EXx } },
3426 { "aesenclast", { XM, EXx } },
3433 { "aesdec", { XM, EXx } },
3440 { "aesdeclast", { XM, EXx } },
3445 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3447 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3448 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
3453 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3455 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3456 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
3463 { "roundps", { XM, EXx, Ib } },
3470 { "roundpd", { XM, EXx, Ib } },
3477 { "roundss", { XM, EXd, Ib } },
3484 { "roundsd", { XM, EXq, Ib } },
3491 { "blendps", { XM, EXx, Ib } },
3498 { "blendpd", { XM, EXx, Ib } },
3505 { "pblendw", { XM, EXx, Ib } },
3512 { "pextrb", { Edqb, XM, Ib } },
3519 { "pextrw", { Edqw, XM, Ib } },
3526 { "pextrK", { Edq, XM, Ib } },
3533 { "extractps", { Edqd, XM, Ib } },
3540 { "pinsrb", { XM, Edqb, Ib } },
3547 { "insertps", { XM, EXd, Ib } },
3554 { "pinsrK", { XM, Edq, Ib } },
3561 { "dpps", { XM, EXx, Ib } },
3568 { "dppd", { XM, EXx, Ib } },
3575 { "mpsadbw", { XM, EXx, Ib } },
3582 { "pclmulqdq", { XM, EXx, PCLMUL } },
3589 { "pcmpestrm", { XM, EXx, Ib } },
3596 { "pcmpestri", { XM, EXx, Ib } },
3603 { "pcmpistrm", { XM, EXx, Ib } },
3610 { "pcmpistri", { XM, EXx, Ib } },
3617 { "aeskeygenassist", { XM, EXx, Ib } },
3620 /* PREFIX_VEX_0F10 */
3622 { VEX_W_TABLE (VEX_W_0F10_P_0) },
3623 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
3624 { VEX_W_TABLE (VEX_W_0F10_P_2) },
3625 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
3628 /* PREFIX_VEX_0F11 */
3630 { VEX_W_TABLE (VEX_W_0F11_P_0) },
3631 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
3632 { VEX_W_TABLE (VEX_W_0F11_P_2) },
3633 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
3636 /* PREFIX_VEX_0F12 */
3638 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3639 { VEX_W_TABLE (VEX_W_0F12_P_1) },
3640 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
3641 { VEX_W_TABLE (VEX_W_0F12_P_3) },
3644 /* PREFIX_VEX_0F16 */
3646 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3647 { VEX_W_TABLE (VEX_W_0F16_P_1) },
3648 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
3651 /* PREFIX_VEX_0F2A */
3654 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
3656 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
3659 /* PREFIX_VEX_0F2C */
3662 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
3664 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
3667 /* PREFIX_VEX_0F2D */
3670 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
3672 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
3675 /* PREFIX_VEX_0F2E */
3677 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
3679 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
3682 /* PREFIX_VEX_0F2F */
3684 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
3686 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
3689 /* PREFIX_VEX_0F51 */
3691 { VEX_W_TABLE (VEX_W_0F51_P_0) },
3692 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
3693 { VEX_W_TABLE (VEX_W_0F51_P_2) },
3694 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
3697 /* PREFIX_VEX_0F52 */
3699 { VEX_W_TABLE (VEX_W_0F52_P_0) },
3700 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
3703 /* PREFIX_VEX_0F53 */
3705 { VEX_W_TABLE (VEX_W_0F53_P_0) },
3706 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
3709 /* PREFIX_VEX_0F58 */
3711 { VEX_W_TABLE (VEX_W_0F58_P_0) },
3712 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
3713 { VEX_W_TABLE (VEX_W_0F58_P_2) },
3714 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
3717 /* PREFIX_VEX_0F59 */
3719 { VEX_W_TABLE (VEX_W_0F59_P_0) },
3720 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
3721 { VEX_W_TABLE (VEX_W_0F59_P_2) },
3722 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
3725 /* PREFIX_VEX_0F5A */
3727 { VEX_W_TABLE (VEX_W_0F5A_P_0) },
3728 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
3729 { "vcvtpd2ps%XY", { XMM, EXx } },
3730 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
3733 /* PREFIX_VEX_0F5B */
3735 { VEX_W_TABLE (VEX_W_0F5B_P_0) },
3736 { VEX_W_TABLE (VEX_W_0F5B_P_1) },
3737 { VEX_W_TABLE (VEX_W_0F5B_P_2) },
3740 /* PREFIX_VEX_0F5C */
3742 { VEX_W_TABLE (VEX_W_0F5C_P_0) },
3743 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
3744 { VEX_W_TABLE (VEX_W_0F5C_P_2) },
3745 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
3748 /* PREFIX_VEX_0F5D */
3750 { VEX_W_TABLE (VEX_W_0F5D_P_0) },
3751 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
3752 { VEX_W_TABLE (VEX_W_0F5D_P_2) },
3753 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
3756 /* PREFIX_VEX_0F5E */
3758 { VEX_W_TABLE (VEX_W_0F5E_P_0) },
3759 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
3760 { VEX_W_TABLE (VEX_W_0F5E_P_2) },
3761 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
3764 /* PREFIX_VEX_0F5F */
3766 { VEX_W_TABLE (VEX_W_0F5F_P_0) },
3767 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
3768 { VEX_W_TABLE (VEX_W_0F5F_P_2) },
3769 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
3772 /* PREFIX_VEX_0F60 */
3776 { VEX_W_TABLE (VEX_W_0F60_P_2) },
3779 /* PREFIX_VEX_0F61 */
3783 { VEX_W_TABLE (VEX_W_0F61_P_2) },
3786 /* PREFIX_VEX_0F62 */
3790 { VEX_W_TABLE (VEX_W_0F62_P_2) },
3793 /* PREFIX_VEX_0F63 */
3797 { VEX_W_TABLE (VEX_W_0F63_P_2) },
3800 /* PREFIX_VEX_0F64 */
3804 { VEX_W_TABLE (VEX_W_0F64_P_2) },
3807 /* PREFIX_VEX_0F65 */
3811 { VEX_W_TABLE (VEX_W_0F65_P_2) },
3814 /* PREFIX_VEX_0F66 */
3818 { VEX_W_TABLE (VEX_W_0F66_P_2) },
3821 /* PREFIX_VEX_0F67 */
3825 { VEX_W_TABLE (VEX_W_0F67_P_2) },
3828 /* PREFIX_VEX_0F68 */
3832 { VEX_W_TABLE (VEX_W_0F68_P_2) },
3835 /* PREFIX_VEX_0F69 */
3839 { VEX_W_TABLE (VEX_W_0F69_P_2) },
3842 /* PREFIX_VEX_0F6A */
3846 { VEX_W_TABLE (VEX_W_0F6A_P_2) },
3849 /* PREFIX_VEX_0F6B */
3853 { VEX_W_TABLE (VEX_W_0F6B_P_2) },
3856 /* PREFIX_VEX_0F6C */
3860 { VEX_W_TABLE (VEX_W_0F6C_P_2) },
3863 /* PREFIX_VEX_0F6D */
3867 { VEX_W_TABLE (VEX_W_0F6D_P_2) },
3870 /* PREFIX_VEX_0F6E */
3874 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
3877 /* PREFIX_VEX_0F6F */
3880 { VEX_W_TABLE (VEX_W_0F6F_P_1) },
3881 { VEX_W_TABLE (VEX_W_0F6F_P_2) },
3884 /* PREFIX_VEX_0F70 */
3887 { VEX_W_TABLE (VEX_W_0F70_P_1) },
3888 { VEX_W_TABLE (VEX_W_0F70_P_2) },
3889 { VEX_W_TABLE (VEX_W_0F70_P_3) },
3892 /* PREFIX_VEX_0F71_REG_2 */
3896 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
3899 /* PREFIX_VEX_0F71_REG_4 */
3903 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
3906 /* PREFIX_VEX_0F71_REG_6 */
3910 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
3913 /* PREFIX_VEX_0F72_REG_2 */
3917 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
3920 /* PREFIX_VEX_0F72_REG_4 */
3924 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
3927 /* PREFIX_VEX_0F72_REG_6 */
3931 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
3934 /* PREFIX_VEX_0F73_REG_2 */
3938 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
3941 /* PREFIX_VEX_0F73_REG_3 */
3945 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
3948 /* PREFIX_VEX_0F73_REG_6 */
3952 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
3955 /* PREFIX_VEX_0F73_REG_7 */
3959 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
3962 /* PREFIX_VEX_0F74 */
3966 { VEX_W_TABLE (VEX_W_0F74_P_2) },
3969 /* PREFIX_VEX_0F75 */
3973 { VEX_W_TABLE (VEX_W_0F75_P_2) },
3976 /* PREFIX_VEX_0F76 */
3980 { VEX_W_TABLE (VEX_W_0F76_P_2) },
3983 /* PREFIX_VEX_0F77 */
3985 { VEX_W_TABLE (VEX_W_0F77_P_0) },
3988 /* PREFIX_VEX_0F7C */
3992 { VEX_W_TABLE (VEX_W_0F7C_P_2) },
3993 { VEX_W_TABLE (VEX_W_0F7C_P_3) },
3996 /* PREFIX_VEX_0F7D */
4000 { VEX_W_TABLE (VEX_W_0F7D_P_2) },
4001 { VEX_W_TABLE (VEX_W_0F7D_P_3) },
4004 /* PREFIX_VEX_0F7E */
4007 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4008 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4011 /* PREFIX_VEX_0F7F */
4014 { VEX_W_TABLE (VEX_W_0F7F_P_1) },
4015 { VEX_W_TABLE (VEX_W_0F7F_P_2) },
4018 /* PREFIX_VEX_0FC2 */
4020 { VEX_W_TABLE (VEX_W_0FC2_P_0) },
4021 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
4022 { VEX_W_TABLE (VEX_W_0FC2_P_2) },
4023 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
4026 /* PREFIX_VEX_0FC4 */
4030 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
4033 /* PREFIX_VEX_0FC5 */
4037 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
4040 /* PREFIX_VEX_0FD0 */
4044 { VEX_W_TABLE (VEX_W_0FD0_P_2) },
4045 { VEX_W_TABLE (VEX_W_0FD0_P_3) },
4048 /* PREFIX_VEX_0FD1 */
4052 { VEX_W_TABLE (VEX_W_0FD1_P_2) },
4055 /* PREFIX_VEX_0FD2 */
4059 { VEX_W_TABLE (VEX_W_0FD2_P_2) },
4062 /* PREFIX_VEX_0FD3 */
4066 { VEX_W_TABLE (VEX_W_0FD3_P_2) },
4069 /* PREFIX_VEX_0FD4 */
4073 { VEX_W_TABLE (VEX_W_0FD4_P_2) },
4076 /* PREFIX_VEX_0FD5 */
4080 { VEX_W_TABLE (VEX_W_0FD5_P_2) },
4083 /* PREFIX_VEX_0FD6 */
4087 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
4090 /* PREFIX_VEX_0FD7 */
4094 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
4097 /* PREFIX_VEX_0FD8 */
4101 { VEX_W_TABLE (VEX_W_0FD8_P_2) },
4104 /* PREFIX_VEX_0FD9 */
4108 { VEX_W_TABLE (VEX_W_0FD9_P_2) },
4111 /* PREFIX_VEX_0FDA */
4115 { VEX_W_TABLE (VEX_W_0FDA_P_2) },
4118 /* PREFIX_VEX_0FDB */
4122 { VEX_W_TABLE (VEX_W_0FDB_P_2) },
4125 /* PREFIX_VEX_0FDC */
4129 { VEX_W_TABLE (VEX_W_0FDC_P_2) },
4132 /* PREFIX_VEX_0FDD */
4136 { VEX_W_TABLE (VEX_W_0FDD_P_2) },
4139 /* PREFIX_VEX_0FDE */
4143 { VEX_W_TABLE (VEX_W_0FDE_P_2) },
4146 /* PREFIX_VEX_0FDF */
4150 { VEX_W_TABLE (VEX_W_0FDF_P_2) },
4153 /* PREFIX_VEX_0FE0 */
4157 { VEX_W_TABLE (VEX_W_0FE0_P_2) },
4160 /* PREFIX_VEX_0FE1 */
4164 { VEX_W_TABLE (VEX_W_0FE1_P_2) },
4167 /* PREFIX_VEX_0FE2 */
4171 { VEX_W_TABLE (VEX_W_0FE2_P_2) },
4174 /* PREFIX_VEX_0FE3 */
4178 { VEX_W_TABLE (VEX_W_0FE3_P_2) },
4181 /* PREFIX_VEX_0FE4 */
4185 { VEX_W_TABLE (VEX_W_0FE4_P_2) },
4188 /* PREFIX_VEX_0FE5 */
4192 { VEX_W_TABLE (VEX_W_0FE5_P_2) },
4195 /* PREFIX_VEX_0FE6 */
4198 { VEX_W_TABLE (VEX_W_0FE6_P_1) },
4199 { VEX_W_TABLE (VEX_W_0FE6_P_2) },
4200 { VEX_W_TABLE (VEX_W_0FE6_P_3) },
4203 /* PREFIX_VEX_0FE7 */
4207 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
4210 /* PREFIX_VEX_0FE8 */
4214 { VEX_W_TABLE (VEX_W_0FE8_P_2) },
4217 /* PREFIX_VEX_0FE9 */
4221 { VEX_W_TABLE (VEX_W_0FE9_P_2) },
4224 /* PREFIX_VEX_0FEA */
4228 { VEX_W_TABLE (VEX_W_0FEA_P_2) },
4231 /* PREFIX_VEX_0FEB */
4235 { VEX_W_TABLE (VEX_W_0FEB_P_2) },
4238 /* PREFIX_VEX_0FEC */
4242 { VEX_W_TABLE (VEX_W_0FEC_P_2) },
4245 /* PREFIX_VEX_0FED */
4249 { VEX_W_TABLE (VEX_W_0FED_P_2) },
4252 /* PREFIX_VEX_0FEE */
4256 { VEX_W_TABLE (VEX_W_0FEE_P_2) },
4259 /* PREFIX_VEX_0FEF */
4263 { VEX_W_TABLE (VEX_W_0FEF_P_2) },
4266 /* PREFIX_VEX_0FF0 */
4271 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4274 /* PREFIX_VEX_0FF1 */
4278 { VEX_W_TABLE (VEX_W_0FF1_P_2) },
4281 /* PREFIX_VEX_0FF2 */
4285 { VEX_W_TABLE (VEX_W_0FF2_P_2) },
4288 /* PREFIX_VEX_0FF3 */
4292 { VEX_W_TABLE (VEX_W_0FF3_P_2) },
4295 /* PREFIX_VEX_0FF4 */
4299 { VEX_W_TABLE (VEX_W_0FF4_P_2) },
4302 /* PREFIX_VEX_0FF5 */
4306 { VEX_W_TABLE (VEX_W_0FF5_P_2) },
4309 /* PREFIX_VEX_0FF6 */
4313 { VEX_W_TABLE (VEX_W_0FF6_P_2) },
4316 /* PREFIX_VEX_0FF7 */
4320 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
4323 /* PREFIX_VEX_0FF8 */
4327 { VEX_W_TABLE (VEX_W_0FF8_P_2) },
4330 /* PREFIX_VEX_0FF9 */
4334 { VEX_W_TABLE (VEX_W_0FF9_P_2) },
4337 /* PREFIX_VEX_0FFA */
4341 { VEX_W_TABLE (VEX_W_0FFA_P_2) },
4344 /* PREFIX_VEX_0FFB */
4348 { VEX_W_TABLE (VEX_W_0FFB_P_2) },
4351 /* PREFIX_VEX_0FFC */
4355 { VEX_W_TABLE (VEX_W_0FFC_P_2) },
4358 /* PREFIX_VEX_0FFD */
4362 { VEX_W_TABLE (VEX_W_0FFD_P_2) },
4365 /* PREFIX_VEX_0FFE */
4369 { VEX_W_TABLE (VEX_W_0FFE_P_2) },
4372 /* PREFIX_VEX_0F3800 */
4376 { VEX_W_TABLE (VEX_W_0F3800_P_2) },
4379 /* PREFIX_VEX_0F3801 */
4383 { VEX_W_TABLE (VEX_W_0F3801_P_2) },
4386 /* PREFIX_VEX_0F3802 */
4390 { VEX_W_TABLE (VEX_W_0F3802_P_2) },
4393 /* PREFIX_VEX_0F3803 */
4397 { VEX_W_TABLE (VEX_W_0F3803_P_2) },
4400 /* PREFIX_VEX_0F3804 */
4404 { VEX_W_TABLE (VEX_W_0F3804_P_2) },
4407 /* PREFIX_VEX_0F3805 */
4411 { VEX_W_TABLE (VEX_W_0F3805_P_2) },
4414 /* PREFIX_VEX_0F3806 */
4418 { VEX_W_TABLE (VEX_W_0F3806_P_2) },
4421 /* PREFIX_VEX_0F3807 */
4425 { VEX_W_TABLE (VEX_W_0F3807_P_2) },
4428 /* PREFIX_VEX_0F3808 */
4432 { VEX_W_TABLE (VEX_W_0F3808_P_2) },
4435 /* PREFIX_VEX_0F3809 */
4439 { VEX_W_TABLE (VEX_W_0F3809_P_2) },
4442 /* PREFIX_VEX_0F380A */
4446 { VEX_W_TABLE (VEX_W_0F380A_P_2) },
4449 /* PREFIX_VEX_0F380B */
4453 { VEX_W_TABLE (VEX_W_0F380B_P_2) },
4456 /* PREFIX_VEX_0F380C */
4460 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
4463 /* PREFIX_VEX_0F380D */
4467 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
4470 /* PREFIX_VEX_0F380E */
4474 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
4477 /* PREFIX_VEX_0F380F */
4481 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
4484 /* PREFIX_VEX_0F3813 */
4488 { "vcvtph2ps", { XM, EXxmmq } },
4491 /* PREFIX_VEX_0F3816 */
4495 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
4498 /* PREFIX_VEX_0F3817 */
4502 { VEX_W_TABLE (VEX_W_0F3817_P_2) },
4505 /* PREFIX_VEX_0F3818 */
4509 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
4512 /* PREFIX_VEX_0F3819 */
4516 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
4519 /* PREFIX_VEX_0F381A */
4523 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
4526 /* PREFIX_VEX_0F381C */
4530 { VEX_W_TABLE (VEX_W_0F381C_P_2) },
4533 /* PREFIX_VEX_0F381D */
4537 { VEX_W_TABLE (VEX_W_0F381D_P_2) },
4540 /* PREFIX_VEX_0F381E */
4544 { VEX_W_TABLE (VEX_W_0F381E_P_2) },
4547 /* PREFIX_VEX_0F3820 */
4551 { VEX_W_TABLE (VEX_W_0F3820_P_2) },
4554 /* PREFIX_VEX_0F3821 */
4558 { VEX_W_TABLE (VEX_W_0F3821_P_2) },
4561 /* PREFIX_VEX_0F3822 */
4565 { VEX_W_TABLE (VEX_W_0F3822_P_2) },
4568 /* PREFIX_VEX_0F3823 */
4572 { VEX_W_TABLE (VEX_W_0F3823_P_2) },
4575 /* PREFIX_VEX_0F3824 */
4579 { VEX_W_TABLE (VEX_W_0F3824_P_2) },
4582 /* PREFIX_VEX_0F3825 */
4586 { VEX_W_TABLE (VEX_W_0F3825_P_2) },
4589 /* PREFIX_VEX_0F3828 */
4593 { VEX_W_TABLE (VEX_W_0F3828_P_2) },
4596 /* PREFIX_VEX_0F3829 */
4600 { VEX_W_TABLE (VEX_W_0F3829_P_2) },
4603 /* PREFIX_VEX_0F382A */
4607 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
4610 /* PREFIX_VEX_0F382B */
4614 { VEX_W_TABLE (VEX_W_0F382B_P_2) },
4617 /* PREFIX_VEX_0F382C */
4621 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
4624 /* PREFIX_VEX_0F382D */
4628 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
4631 /* PREFIX_VEX_0F382E */
4635 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
4638 /* PREFIX_VEX_0F382F */
4642 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
4645 /* PREFIX_VEX_0F3830 */
4649 { VEX_W_TABLE (VEX_W_0F3830_P_2) },
4652 /* PREFIX_VEX_0F3831 */
4656 { VEX_W_TABLE (VEX_W_0F3831_P_2) },
4659 /* PREFIX_VEX_0F3832 */
4663 { VEX_W_TABLE (VEX_W_0F3832_P_2) },
4666 /* PREFIX_VEX_0F3833 */
4670 { VEX_W_TABLE (VEX_W_0F3833_P_2) },
4673 /* PREFIX_VEX_0F3834 */
4677 { VEX_W_TABLE (VEX_W_0F3834_P_2) },
4680 /* PREFIX_VEX_0F3835 */
4684 { VEX_W_TABLE (VEX_W_0F3835_P_2) },
4687 /* PREFIX_VEX_0F3836 */
4691 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
4694 /* PREFIX_VEX_0F3837 */
4698 { VEX_W_TABLE (VEX_W_0F3837_P_2) },
4701 /* PREFIX_VEX_0F3838 */
4705 { VEX_W_TABLE (VEX_W_0F3838_P_2) },
4708 /* PREFIX_VEX_0F3839 */
4712 { VEX_W_TABLE (VEX_W_0F3839_P_2) },
4715 /* PREFIX_VEX_0F383A */
4719 { VEX_W_TABLE (VEX_W_0F383A_P_2) },
4722 /* PREFIX_VEX_0F383B */
4726 { VEX_W_TABLE (VEX_W_0F383B_P_2) },
4729 /* PREFIX_VEX_0F383C */
4733 { VEX_W_TABLE (VEX_W_0F383C_P_2) },
4736 /* PREFIX_VEX_0F383D */
4740 { VEX_W_TABLE (VEX_W_0F383D_P_2) },
4743 /* PREFIX_VEX_0F383E */
4747 { VEX_W_TABLE (VEX_W_0F383E_P_2) },
4750 /* PREFIX_VEX_0F383F */
4754 { VEX_W_TABLE (VEX_W_0F383F_P_2) },
4757 /* PREFIX_VEX_0F3840 */
4761 { VEX_W_TABLE (VEX_W_0F3840_P_2) },
4764 /* PREFIX_VEX_0F3841 */
4768 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
4771 /* PREFIX_VEX_0F3845 */
4775 { "vpsrlv%LW", { XM, Vex, EXx } },
4778 /* PREFIX_VEX_0F3846 */
4782 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
4785 /* PREFIX_VEX_0F3847 */
4789 { "vpsllv%LW", { XM, Vex, EXx } },
4792 /* PREFIX_VEX_0F3858 */
4796 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
4799 /* PREFIX_VEX_0F3859 */
4803 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
4806 /* PREFIX_VEX_0F385A */
4810 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
4813 /* PREFIX_VEX_0F3878 */
4817 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
4820 /* PREFIX_VEX_0F3879 */
4824 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
4827 /* PREFIX_VEX_0F388C */
4831 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
4834 /* PREFIX_VEX_0F388E */
4838 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
4841 /* PREFIX_VEX_0F3890 */
4845 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
4848 /* PREFIX_VEX_0F3891 */
4852 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
4855 /* PREFIX_VEX_0F3892 */
4859 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
4862 /* PREFIX_VEX_0F3893 */
4866 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
4869 /* PREFIX_VEX_0F3896 */
4873 { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4876 /* PREFIX_VEX_0F3897 */
4880 { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4883 /* PREFIX_VEX_0F3898 */
4887 { "vfmadd132p%XW", { XM, Vex, EXx } },
4890 /* PREFIX_VEX_0F3899 */
4894 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4897 /* PREFIX_VEX_0F389A */
4901 { "vfmsub132p%XW", { XM, Vex, EXx } },
4904 /* PREFIX_VEX_0F389B */
4908 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4911 /* PREFIX_VEX_0F389C */
4915 { "vfnmadd132p%XW", { XM, Vex, EXx } },
4918 /* PREFIX_VEX_0F389D */
4922 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4925 /* PREFIX_VEX_0F389E */
4929 { "vfnmsub132p%XW", { XM, Vex, EXx } },
4932 /* PREFIX_VEX_0F389F */
4936 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4939 /* PREFIX_VEX_0F38A6 */
4943 { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4947 /* PREFIX_VEX_0F38A7 */
4951 { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4954 /* PREFIX_VEX_0F38A8 */
4958 { "vfmadd213p%XW", { XM, Vex, EXx } },
4961 /* PREFIX_VEX_0F38A9 */
4965 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4968 /* PREFIX_VEX_0F38AA */
4972 { "vfmsub213p%XW", { XM, Vex, EXx } },
4975 /* PREFIX_VEX_0F38AB */
4979 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4982 /* PREFIX_VEX_0F38AC */
4986 { "vfnmadd213p%XW", { XM, Vex, EXx } },
4989 /* PREFIX_VEX_0F38AD */
4993 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4996 /* PREFIX_VEX_0F38AE */
5000 { "vfnmsub213p%XW", { XM, Vex, EXx } },
5003 /* PREFIX_VEX_0F38AF */
5007 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5010 /* PREFIX_VEX_0F38B6 */
5014 { "vfmaddsub231p%XW", { XM, Vex, EXx } },
5017 /* PREFIX_VEX_0F38B7 */
5021 { "vfmsubadd231p%XW", { XM, Vex, EXx } },
5024 /* PREFIX_VEX_0F38B8 */
5028 { "vfmadd231p%XW", { XM, Vex, EXx } },
5031 /* PREFIX_VEX_0F38B9 */
5035 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5038 /* PREFIX_VEX_0F38BA */
5042 { "vfmsub231p%XW", { XM, Vex, EXx } },
5045 /* PREFIX_VEX_0F38BB */
5049 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5052 /* PREFIX_VEX_0F38BC */
5056 { "vfnmadd231p%XW", { XM, Vex, EXx } },
5059 /* PREFIX_VEX_0F38BD */
5063 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5066 /* PREFIX_VEX_0F38BE */
5070 { "vfnmsub231p%XW", { XM, Vex, EXx } },
5073 /* PREFIX_VEX_0F38BF */
5077 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5080 /* PREFIX_VEX_0F38DB */
5084 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
5087 /* PREFIX_VEX_0F38DC */
5091 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
5094 /* PREFIX_VEX_0F38DD */
5098 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
5101 /* PREFIX_VEX_0F38DE */
5105 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
5108 /* PREFIX_VEX_0F38DF */
5112 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
5115 /* PREFIX_VEX_0F38F2 */
5117 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
5120 /* PREFIX_VEX_0F38F3_REG_1 */
5122 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
5125 /* PREFIX_VEX_0F38F3_REG_2 */
5127 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
5130 /* PREFIX_VEX_0F38F3_REG_3 */
5132 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
5135 /* PREFIX_VEX_0F38F5 */
5137 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
5138 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
5140 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
5143 /* PREFIX_VEX_0F38F6 */
5148 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
5151 /* PREFIX_VEX_0F38F7 */
5153 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
5154 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
5155 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
5156 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
5159 /* PREFIX_VEX_0F3A00 */
5163 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
5166 /* PREFIX_VEX_0F3A01 */
5170 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
5173 /* PREFIX_VEX_0F3A02 */
5177 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
5180 /* PREFIX_VEX_0F3A04 */
5184 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
5187 /* PREFIX_VEX_0F3A05 */
5191 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
5194 /* PREFIX_VEX_0F3A06 */
5198 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
5201 /* PREFIX_VEX_0F3A08 */
5205 { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
5208 /* PREFIX_VEX_0F3A09 */
5212 { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
5215 /* PREFIX_VEX_0F3A0A */
5219 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
5222 /* PREFIX_VEX_0F3A0B */
5226 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
5229 /* PREFIX_VEX_0F3A0C */
5233 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
5236 /* PREFIX_VEX_0F3A0D */
5240 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
5243 /* PREFIX_VEX_0F3A0E */
5247 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
5250 /* PREFIX_VEX_0F3A0F */
5254 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
5257 /* PREFIX_VEX_0F3A14 */
5261 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
5264 /* PREFIX_VEX_0F3A15 */
5268 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
5271 /* PREFIX_VEX_0F3A16 */
5275 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
5278 /* PREFIX_VEX_0F3A17 */
5282 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
5285 /* PREFIX_VEX_0F3A18 */
5289 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
5292 /* PREFIX_VEX_0F3A19 */
5296 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
5299 /* PREFIX_VEX_0F3A1D */
5303 { "vcvtps2ph", { EXxmmq, XM, Ib } },
5306 /* PREFIX_VEX_0F3A20 */
5310 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
5313 /* PREFIX_VEX_0F3A21 */
5317 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
5320 /* PREFIX_VEX_0F3A22 */
5324 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
5327 /* PREFIX_VEX_0F3A38 */
5331 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
5334 /* PREFIX_VEX_0F3A39 */
5338 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
5341 /* PREFIX_VEX_0F3A40 */
5345 { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
5348 /* PREFIX_VEX_0F3A41 */
5352 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
5355 /* PREFIX_VEX_0F3A42 */
5359 { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
5362 /* PREFIX_VEX_0F3A44 */
5366 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
5369 /* PREFIX_VEX_0F3A46 */
5373 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
5376 /* PREFIX_VEX_0F3A48 */
5380 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
5383 /* PREFIX_VEX_0F3A49 */
5387 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
5390 /* PREFIX_VEX_0F3A4A */
5394 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
5397 /* PREFIX_VEX_0F3A4B */
5401 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
5404 /* PREFIX_VEX_0F3A4C */
5408 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
5411 /* PREFIX_VEX_0F3A5C */
5415 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5418 /* PREFIX_VEX_0F3A5D */
5422 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5425 /* PREFIX_VEX_0F3A5E */
5429 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5432 /* PREFIX_VEX_0F3A5F */
5436 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5439 /* PREFIX_VEX_0F3A60 */
5443 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
5447 /* PREFIX_VEX_0F3A61 */
5451 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
5454 /* PREFIX_VEX_0F3A62 */
5458 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
5461 /* PREFIX_VEX_0F3A63 */
5465 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
5468 /* PREFIX_VEX_0F3A68 */
5472 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5475 /* PREFIX_VEX_0F3A69 */
5479 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5482 /* PREFIX_VEX_0F3A6A */
5486 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
5489 /* PREFIX_VEX_0F3A6B */
5493 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
5496 /* PREFIX_VEX_0F3A6C */
5500 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5503 /* PREFIX_VEX_0F3A6D */
5507 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5510 /* PREFIX_VEX_0F3A6E */
5514 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
5517 /* PREFIX_VEX_0F3A6F */
5521 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
5524 /* PREFIX_VEX_0F3A78 */
5528 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5531 /* PREFIX_VEX_0F3A79 */
5535 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5538 /* PREFIX_VEX_0F3A7A */
5542 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
5545 /* PREFIX_VEX_0F3A7B */
5549 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
5552 /* PREFIX_VEX_0F3A7C */
5556 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5560 /* PREFIX_VEX_0F3A7D */
5564 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5567 /* PREFIX_VEX_0F3A7E */
5571 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
5574 /* PREFIX_VEX_0F3A7F */
5578 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
5581 /* PREFIX_VEX_0F3ADF */
5585 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
5588 /* PREFIX_VEX_0F3AF0 */
5593 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
5597 static const struct dis386 x86_64_table[][2] = {
5600 { "pushP", { es } },
5610 { "pushP", { cs } },
5615 { "pushP", { ss } },
5625 { "pushP", { ds } },
5655 { "pushaP", { XX } },
5660 { "popaP", { XX } },
5665 { MOD_TABLE (MOD_62_32BIT) },
5670 { "arpl", { Ew, Gw } },
5671 { "movs{lq|xd}", { Gv, Ed } },
5676 { "ins{R|}", { Yzr, indirDX } },
5677 { "ins{G|}", { Yzr, indirDX } },
5682 { "outs{R|}", { indirDXr, Xz } },
5683 { "outs{G|}", { indirDXr, Xz } },
5688 { "Jcall{T|}", { Ap } },
5693 { MOD_TABLE (MOD_C4_32BIT) },
5694 { VEX_C4_TABLE (VEX_0F) },
5699 { MOD_TABLE (MOD_C5_32BIT) },
5700 { VEX_C5_TABLE (VEX_0F) },
5720 { "Jjmp{T|}", { Ap } },
5723 /* X86_64_0F01_REG_0 */
5725 { "sgdt{Q|IQ}", { M } },
5729 /* X86_64_0F01_REG_1 */
5731 { "sidt{Q|IQ}", { M } },
5735 /* X86_64_0F01_REG_2 */
5737 { "lgdt{Q|Q}", { M } },
5741 /* X86_64_0F01_REG_3 */
5743 { "lidt{Q|Q}", { M } },
5748 static const struct dis386 three_byte_table[][256] = {
5750 /* THREE_BYTE_0F38 */
5753 { "pshufb", { MX, EM } },
5754 { "phaddw", { MX, EM } },
5755 { "phaddd", { MX, EM } },
5756 { "phaddsw", { MX, EM } },
5757 { "pmaddubsw", { MX, EM } },
5758 { "phsubw", { MX, EM } },
5759 { "phsubd", { MX, EM } },
5760 { "phsubsw", { MX, EM } },
5762 { "psignb", { MX, EM } },
5763 { "psignw", { MX, EM } },
5764 { "psignd", { MX, EM } },
5765 { "pmulhrsw", { MX, EM } },
5771 { PREFIX_TABLE (PREFIX_0F3810) },
5775 { PREFIX_TABLE (PREFIX_0F3814) },
5776 { PREFIX_TABLE (PREFIX_0F3815) },
5778 { PREFIX_TABLE (PREFIX_0F3817) },
5784 { "pabsb", { MX, EM } },
5785 { "pabsw", { MX, EM } },
5786 { "pabsd", { MX, EM } },
5789 { PREFIX_TABLE (PREFIX_0F3820) },
5790 { PREFIX_TABLE (PREFIX_0F3821) },
5791 { PREFIX_TABLE (PREFIX_0F3822) },
5792 { PREFIX_TABLE (PREFIX_0F3823) },
5793 { PREFIX_TABLE (PREFIX_0F3824) },
5794 { PREFIX_TABLE (PREFIX_0F3825) },
5798 { PREFIX_TABLE (PREFIX_0F3828) },
5799 { PREFIX_TABLE (PREFIX_0F3829) },
5800 { PREFIX_TABLE (PREFIX_0F382A) },
5801 { PREFIX_TABLE (PREFIX_0F382B) },
5807 { PREFIX_TABLE (PREFIX_0F3830) },
5808 { PREFIX_TABLE (PREFIX_0F3831) },
5809 { PREFIX_TABLE (PREFIX_0F3832) },
5810 { PREFIX_TABLE (PREFIX_0F3833) },
5811 { PREFIX_TABLE (PREFIX_0F3834) },
5812 { PREFIX_TABLE (PREFIX_0F3835) },
5814 { PREFIX_TABLE (PREFIX_0F3837) },
5816 { PREFIX_TABLE (PREFIX_0F3838) },
5817 { PREFIX_TABLE (PREFIX_0F3839) },
5818 { PREFIX_TABLE (PREFIX_0F383A) },
5819 { PREFIX_TABLE (PREFIX_0F383B) },
5820 { PREFIX_TABLE (PREFIX_0F383C) },
5821 { PREFIX_TABLE (PREFIX_0F383D) },
5822 { PREFIX_TABLE (PREFIX_0F383E) },
5823 { PREFIX_TABLE (PREFIX_0F383F) },
5825 { PREFIX_TABLE (PREFIX_0F3840) },
5826 { PREFIX_TABLE (PREFIX_0F3841) },
5897 { PREFIX_TABLE (PREFIX_0F3880) },
5898 { PREFIX_TABLE (PREFIX_0F3881) },
5899 { PREFIX_TABLE (PREFIX_0F3882) },
5999 { PREFIX_TABLE (PREFIX_0F38DB) },
6000 { PREFIX_TABLE (PREFIX_0F38DC) },
6001 { PREFIX_TABLE (PREFIX_0F38DD) },
6002 { PREFIX_TABLE (PREFIX_0F38DE) },
6003 { PREFIX_TABLE (PREFIX_0F38DF) },
6023 { PREFIX_TABLE (PREFIX_0F38F0) },
6024 { PREFIX_TABLE (PREFIX_0F38F1) },
6041 /* THREE_BYTE_0F3A */
6053 { PREFIX_TABLE (PREFIX_0F3A08) },
6054 { PREFIX_TABLE (PREFIX_0F3A09) },
6055 { PREFIX_TABLE (PREFIX_0F3A0A) },
6056 { PREFIX_TABLE (PREFIX_0F3A0B) },
6057 { PREFIX_TABLE (PREFIX_0F3A0C) },
6058 { PREFIX_TABLE (PREFIX_0F3A0D) },
6059 { PREFIX_TABLE (PREFIX_0F3A0E) },
6060 { "palignr", { MX, EM, Ib } },
6066 { PREFIX_TABLE (PREFIX_0F3A14) },
6067 { PREFIX_TABLE (PREFIX_0F3A15) },
6068 { PREFIX_TABLE (PREFIX_0F3A16) },
6069 { PREFIX_TABLE (PREFIX_0F3A17) },
6080 { PREFIX_TABLE (PREFIX_0F3A20) },
6081 { PREFIX_TABLE (PREFIX_0F3A21) },
6082 { PREFIX_TABLE (PREFIX_0F3A22) },
6116 { PREFIX_TABLE (PREFIX_0F3A40) },
6117 { PREFIX_TABLE (PREFIX_0F3A41) },
6118 { PREFIX_TABLE (PREFIX_0F3A42) },
6120 { PREFIX_TABLE (PREFIX_0F3A44) },
6152 { PREFIX_TABLE (PREFIX_0F3A60) },
6153 { PREFIX_TABLE (PREFIX_0F3A61) },
6154 { PREFIX_TABLE (PREFIX_0F3A62) },
6155 { PREFIX_TABLE (PREFIX_0F3A63) },
6294 { PREFIX_TABLE (PREFIX_0F3ADF) },
6333 /* THREE_BYTE_0F7A */
6372 { "ptest", { XX } },
6409 { "phaddbw", { XM, EXq } },
6410 { "phaddbd", { XM, EXq } },
6411 { "phaddbq", { XM, EXq } },
6414 { "phaddwd", { XM, EXq } },
6415 { "phaddwq", { XM, EXq } },
6420 { "phadddq", { XM, EXq } },
6427 { "phaddubw", { XM, EXq } },
6428 { "phaddubd", { XM, EXq } },
6429 { "phaddubq", { XM, EXq } },
6432 { "phadduwd", { XM, EXq } },
6433 { "phadduwq", { XM, EXq } },
6438 { "phaddudq", { XM, EXq } },
6445 { "phsubbw", { XM, EXq } },
6446 { "phsubbd", { XM, EXq } },
6447 { "phsubbq", { XM, EXq } },
6626 static const struct dis386 xop_table[][256] = {
6648 { "bextr", { Gv, Ev, Iq } },
6779 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6780 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6781 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6789 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6790 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6797 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6798 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6799 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6807 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6808 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6812 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6813 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6816 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6834 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6846 { "vprotb", { XM, Vex_2src_1, Ib } },
6847 { "vprotw", { XM, Vex_2src_1, Ib } },
6848 { "vprotd", { XM, Vex_2src_1, Ib } },
6849 { "vprotq", { XM, Vex_2src_1, Ib } },
6859 { "vpcomb", { XM, Vex128, EXx, Ib } },
6860 { "vpcomw", { XM, Vex128, EXx, Ib } },
6861 { "vpcomd", { XM, Vex128, EXx, Ib } },
6862 { "vpcomq", { XM, Vex128, EXx, Ib } },
6895 { "vpcomub", { XM, Vex128, EXx, Ib } },
6896 { "vpcomuw", { XM, Vex128, EXx, Ib } },
6897 { "vpcomud", { XM, Vex128, EXx, Ib } },
6898 { "vpcomuq", { XM, Vex128, EXx, Ib } },
6922 { REG_TABLE (REG_XOP_TBM_01) },
6923 { REG_TABLE (REG_XOP_TBM_02) },
6941 { REG_TABLE (REG_XOP_LWPCB) },
7065 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7066 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7067 { "vfrczss", { XM, EXd } },
7068 { "vfrczsd", { XM, EXq } },
7083 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } },
7084 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } },
7085 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } },
7086 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } },
7087 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } },
7088 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } },
7089 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } },
7090 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } },
7092 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } },
7093 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } },
7094 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } },
7095 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } },
7138 { "vphaddbw", { XM, EXxmm } },
7139 { "vphaddbd", { XM, EXxmm } },
7140 { "vphaddbq", { XM, EXxmm } },
7143 { "vphaddwd", { XM, EXxmm } },
7144 { "vphaddwq", { XM, EXxmm } },
7149 { "vphadddq", { XM, EXxmm } },
7156 { "vphaddubw", { XM, EXxmm } },
7157 { "vphaddubd", { XM, EXxmm } },
7158 { "vphaddubq", { XM, EXxmm } },
7161 { "vphadduwd", { XM, EXxmm } },
7162 { "vphadduwq", { XM, EXxmm } },
7167 { "vphaddudq", { XM, EXxmm } },
7174 { "vphsubbw", { XM, EXxmm } },
7175 { "vphsubwd", { XM, EXxmm } },
7176 { "vphsubdq", { XM, EXxmm } },
7230 { "bextr", { Gv, Ev, Iq } },
7232 { REG_TABLE (REG_XOP_LWP) },
7502 static const struct dis386 vex_table[][256] = {
7524 { PREFIX_TABLE (PREFIX_VEX_0F10) },
7525 { PREFIX_TABLE (PREFIX_VEX_0F11) },
7526 { PREFIX_TABLE (PREFIX_VEX_0F12) },
7527 { MOD_TABLE (MOD_VEX_0F13) },
7528 { VEX_W_TABLE (VEX_W_0F14) },
7529 { VEX_W_TABLE (VEX_W_0F15) },
7530 { PREFIX_TABLE (PREFIX_VEX_0F16) },
7531 { MOD_TABLE (MOD_VEX_0F17) },
7551 { VEX_W_TABLE (VEX_W_0F28) },
7552 { VEX_W_TABLE (VEX_W_0F29) },
7553 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
7554 { MOD_TABLE (MOD_VEX_0F2B) },
7555 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
7556 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
7557 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
7558 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
7596 { MOD_TABLE (MOD_VEX_0F50) },
7597 { PREFIX_TABLE (PREFIX_VEX_0F51) },
7598 { PREFIX_TABLE (PREFIX_VEX_0F52) },
7599 { PREFIX_TABLE (PREFIX_VEX_0F53) },
7600 { "vandpX", { XM, Vex, EXx } },
7601 { "vandnpX", { XM, Vex, EXx } },
7602 { "vorpX", { XM, Vex, EXx } },
7603 { "vxorpX", { XM, Vex, EXx } },
7605 { PREFIX_TABLE (PREFIX_VEX_0F58) },
7606 { PREFIX_TABLE (PREFIX_VEX_0F59) },
7607 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
7608 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
7609 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
7610 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
7611 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
7612 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
7614 { PREFIX_TABLE (PREFIX_VEX_0F60) },
7615 { PREFIX_TABLE (PREFIX_VEX_0F61) },
7616 { PREFIX_TABLE (PREFIX_VEX_0F62) },
7617 { PREFIX_TABLE (PREFIX_VEX_0F63) },
7618 { PREFIX_TABLE (PREFIX_VEX_0F64) },
7619 { PREFIX_TABLE (PREFIX_VEX_0F65) },
7620 { PREFIX_TABLE (PREFIX_VEX_0F66) },
7621 { PREFIX_TABLE (PREFIX_VEX_0F67) },
7623 { PREFIX_TABLE (PREFIX_VEX_0F68) },
7624 { PREFIX_TABLE (PREFIX_VEX_0F69) },
7625 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
7626 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
7627 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
7628 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
7629 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
7630 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
7632 { PREFIX_TABLE (PREFIX_VEX_0F70) },
7633 { REG_TABLE (REG_VEX_0F71) },
7634 { REG_TABLE (REG_VEX_0F72) },
7635 { REG_TABLE (REG_VEX_0F73) },
7636 { PREFIX_TABLE (PREFIX_VEX_0F74) },
7637 { PREFIX_TABLE (PREFIX_VEX_0F75) },
7638 { PREFIX_TABLE (PREFIX_VEX_0F76) },
7639 { PREFIX_TABLE (PREFIX_VEX_0F77) },
7645 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
7646 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
7647 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
7648 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
7701 { REG_TABLE (REG_VEX_0FAE) },
7724 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
7726 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
7727 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
7728 { "vshufpX", { XM, Vex, EXx, Ib } },
7740 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
7741 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
7742 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
7743 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
7744 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
7745 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
7746 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
7747 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
7749 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
7750 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
7751 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
7752 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
7753 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
7754 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
7755 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
7756 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
7758 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
7759 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
7760 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
7761 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
7762 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
7763 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
7764 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
7765 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
7767 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
7768 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
7769 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
7770 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
7771 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
7772 { PREFIX_TABLE (PREFIX_VEX_0FED) },
7773 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
7774 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
7776 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
7777 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
7778 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
7779 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
7780 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
7781 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
7782 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
7783 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
7785 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
7786 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
7787 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
7788 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
7789 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
7790 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
7791 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
7797 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
7798 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
7799 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
7800 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
7801 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
7802 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
7803 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
7804 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
7806 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
7807 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
7808 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
7809 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
7810 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
7811 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
7812 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
7813 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
7818 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
7821 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
7822 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
7824 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
7825 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
7826 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
7828 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
7829 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
7830 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
7833 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
7834 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
7835 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
7836 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
7837 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
7838 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
7842 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
7843 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
7844 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
7845 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
7846 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
7847 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
7848 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
7849 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
7851 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
7852 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
7853 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
7854 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
7855 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
7856 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
7857 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
7858 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
7860 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
7861 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
7862 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
7863 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
7864 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
7865 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
7866 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
7867 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
7869 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
7870 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
7874 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
7875 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
7876 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
7896 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
7897 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
7898 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
7932 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
7933 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
7954 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
7956 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
7959 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
7960 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
7961 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
7962 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
7965 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
7966 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
7968 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
7969 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
7970 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
7971 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
7972 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
7973 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
7974 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
7975 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
7983 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
7984 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
7986 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
7987 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
7988 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
7989 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
7990 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
7991 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
7992 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
7993 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8001 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8002 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8004 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8005 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8006 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8007 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8008 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8009 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8010 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8011 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8043 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8044 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8045 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8046 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8047 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8069 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8070 { REG_TABLE (REG_VEX_0F38F3) },
8072 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8073 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8074 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8088 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8089 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8090 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8092 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8093 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8094 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8097 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8098 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8099 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8100 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8101 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8102 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8103 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8104 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8110 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8111 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8112 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8113 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8115 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8116 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8120 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8124 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8125 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8126 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8151 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8152 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8160 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8161 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8162 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8164 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8166 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8169 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8170 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8171 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8172 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8173 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8191 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
8192 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
8193 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
8194 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
8196 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
8197 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
8198 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
8199 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
8205 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
8206 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
8207 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
8208 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
8209 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
8210 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
8211 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
8212 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
8223 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
8224 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
8225 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
8226 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
8227 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
8228 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
8229 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
8230 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
8338 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
8358 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
8378 static const struct dis386 vex_len_table[][2] = {
8379 /* VEX_LEN_0F10_P_1 */
8381 { VEX_W_TABLE (VEX_W_0F10_P_1) },
8382 { VEX_W_TABLE (VEX_W_0F10_P_1) },
8385 /* VEX_LEN_0F10_P_3 */
8387 { VEX_W_TABLE (VEX_W_0F10_P_3) },
8388 { VEX_W_TABLE (VEX_W_0F10_P_3) },
8391 /* VEX_LEN_0F11_P_1 */
8393 { VEX_W_TABLE (VEX_W_0F11_P_1) },
8394 { VEX_W_TABLE (VEX_W_0F11_P_1) },
8397 /* VEX_LEN_0F11_P_3 */
8399 { VEX_W_TABLE (VEX_W_0F11_P_3) },
8400 { VEX_W_TABLE (VEX_W_0F11_P_3) },
8403 /* VEX_LEN_0F12_P_0_M_0 */
8405 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
8408 /* VEX_LEN_0F12_P_0_M_1 */
8410 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
8413 /* VEX_LEN_0F12_P_2 */
8415 { VEX_W_TABLE (VEX_W_0F12_P_2) },
8418 /* VEX_LEN_0F13_M_0 */
8420 { VEX_W_TABLE (VEX_W_0F13_M_0) },
8423 /* VEX_LEN_0F16_P_0_M_0 */
8425 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
8428 /* VEX_LEN_0F16_P_0_M_1 */
8430 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
8433 /* VEX_LEN_0F16_P_2 */
8435 { VEX_W_TABLE (VEX_W_0F16_P_2) },
8438 /* VEX_LEN_0F17_M_0 */
8440 { VEX_W_TABLE (VEX_W_0F17_M_0) },
8443 /* VEX_LEN_0F2A_P_1 */
8445 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
8446 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
8449 /* VEX_LEN_0F2A_P_3 */
8451 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
8452 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
8455 /* VEX_LEN_0F2C_P_1 */
8457 { "vcvttss2siY", { Gv, EXdScalar } },
8458 { "vcvttss2siY", { Gv, EXdScalar } },
8461 /* VEX_LEN_0F2C_P_3 */
8463 { "vcvttsd2siY", { Gv, EXqScalar } },
8464 { "vcvttsd2siY", { Gv, EXqScalar } },
8467 /* VEX_LEN_0F2D_P_1 */
8469 { "vcvtss2siY", { Gv, EXdScalar } },
8470 { "vcvtss2siY", { Gv, EXdScalar } },
8473 /* VEX_LEN_0F2D_P_3 */
8475 { "vcvtsd2siY", { Gv, EXqScalar } },
8476 { "vcvtsd2siY", { Gv, EXqScalar } },
8479 /* VEX_LEN_0F2E_P_0 */
8481 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
8482 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
8485 /* VEX_LEN_0F2E_P_2 */
8487 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
8488 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
8491 /* VEX_LEN_0F2F_P_0 */
8493 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
8494 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
8497 /* VEX_LEN_0F2F_P_2 */
8499 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
8500 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
8503 /* VEX_LEN_0F51_P_1 */
8505 { VEX_W_TABLE (VEX_W_0F51_P_1) },
8506 { VEX_W_TABLE (VEX_W_0F51_P_1) },
8509 /* VEX_LEN_0F51_P_3 */
8511 { VEX_W_TABLE (VEX_W_0F51_P_3) },
8512 { VEX_W_TABLE (VEX_W_0F51_P_3) },
8515 /* VEX_LEN_0F52_P_1 */
8517 { VEX_W_TABLE (VEX_W_0F52_P_1) },
8518 { VEX_W_TABLE (VEX_W_0F52_P_1) },
8521 /* VEX_LEN_0F53_P_1 */
8523 { VEX_W_TABLE (VEX_W_0F53_P_1) },
8524 { VEX_W_TABLE (VEX_W_0F53_P_1) },
8527 /* VEX_LEN_0F58_P_1 */
8529 { VEX_W_TABLE (VEX_W_0F58_P_1) },
8530 { VEX_W_TABLE (VEX_W_0F58_P_1) },
8533 /* VEX_LEN_0F58_P_3 */
8535 { VEX_W_TABLE (VEX_W_0F58_P_3) },
8536 { VEX_W_TABLE (VEX_W_0F58_P_3) },
8539 /* VEX_LEN_0F59_P_1 */
8541 { VEX_W_TABLE (VEX_W_0F59_P_1) },
8542 { VEX_W_TABLE (VEX_W_0F59_P_1) },
8545 /* VEX_LEN_0F59_P_3 */
8547 { VEX_W_TABLE (VEX_W_0F59_P_3) },
8548 { VEX_W_TABLE (VEX_W_0F59_P_3) },
8551 /* VEX_LEN_0F5A_P_1 */
8553 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
8554 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
8557 /* VEX_LEN_0F5A_P_3 */
8559 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
8560 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
8563 /* VEX_LEN_0F5C_P_1 */
8565 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
8566 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
8569 /* VEX_LEN_0F5C_P_3 */
8571 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
8572 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
8575 /* VEX_LEN_0F5D_P_1 */
8577 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
8578 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
8581 /* VEX_LEN_0F5D_P_3 */
8583 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
8584 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
8587 /* VEX_LEN_0F5E_P_1 */
8589 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
8590 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
8593 /* VEX_LEN_0F5E_P_3 */
8595 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
8596 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
8599 /* VEX_LEN_0F5F_P_1 */
8601 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
8602 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
8605 /* VEX_LEN_0F5F_P_3 */
8607 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
8608 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
8611 /* VEX_LEN_0F6E_P_2 */
8613 { "vmovK", { XMScalar, Edq } },
8614 { "vmovK", { XMScalar, Edq } },
8617 /* VEX_LEN_0F7E_P_1 */
8619 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
8620 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
8623 /* VEX_LEN_0F7E_P_2 */
8625 { "vmovK", { Edq, XMScalar } },
8626 { "vmovK", { Edq, XMScalar } },
8629 /* VEX_LEN_0FAE_R_2_M_0 */
8631 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
8634 /* VEX_LEN_0FAE_R_3_M_0 */
8636 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
8639 /* VEX_LEN_0FC2_P_1 */
8641 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
8642 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
8645 /* VEX_LEN_0FC2_P_3 */
8647 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
8648 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
8651 /* VEX_LEN_0FC4_P_2 */
8653 { VEX_W_TABLE (VEX_W_0FC4_P_2) },
8656 /* VEX_LEN_0FC5_P_2 */
8658 { VEX_W_TABLE (VEX_W_0FC5_P_2) },
8661 /* VEX_LEN_0FD6_P_2 */
8663 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
8664 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
8667 /* VEX_LEN_0FF7_P_2 */
8669 { VEX_W_TABLE (VEX_W_0FF7_P_2) },
8672 /* VEX_LEN_0F3816_P_2 */
8675 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
8678 /* VEX_LEN_0F3819_P_2 */
8681 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
8684 /* VEX_LEN_0F381A_P_2_M_0 */
8687 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
8690 /* VEX_LEN_0F3836_P_2 */
8693 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
8696 /* VEX_LEN_0F3841_P_2 */
8698 { VEX_W_TABLE (VEX_W_0F3841_P_2) },
8701 /* VEX_LEN_0F385A_P_2_M_0 */
8704 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
8707 /* VEX_LEN_0F38DB_P_2 */
8709 { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
8712 /* VEX_LEN_0F38DC_P_2 */
8714 { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
8717 /* VEX_LEN_0F38DD_P_2 */
8719 { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
8722 /* VEX_LEN_0F38DE_P_2 */
8724 { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
8727 /* VEX_LEN_0F38DF_P_2 */
8729 { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
8732 /* VEX_LEN_0F38F2_P_0 */
8734 { "andnS", { Gdq, VexGdq, Edq } },
8737 /* VEX_LEN_0F38F3_R_1_P_0 */
8739 { "blsrS", { VexGdq, Edq } },
8742 /* VEX_LEN_0F38F3_R_2_P_0 */
8744 { "blsmskS", { VexGdq, Edq } },
8747 /* VEX_LEN_0F38F3_R_3_P_0 */
8749 { "blsiS", { VexGdq, Edq } },
8752 /* VEX_LEN_0F38F5_P_0 */
8754 { "bzhiS", { Gdq, Edq, VexGdq } },
8757 /* VEX_LEN_0F38F5_P_1 */
8759 { "pextS", { Gdq, VexGdq, Edq } },
8762 /* VEX_LEN_0F38F5_P_3 */
8764 { "pdepS", { Gdq, VexGdq, Edq } },
8767 /* VEX_LEN_0F38F6_P_3 */
8769 { "mulxS", { Gdq, VexGdq, Edq } },
8772 /* VEX_LEN_0F38F7_P_0 */
8774 { "bextrS", { Gdq, Edq, VexGdq } },
8777 /* VEX_LEN_0F38F7_P_1 */
8779 { "sarxS", { Gdq, Edq, VexGdq } },
8782 /* VEX_LEN_0F38F7_P_2 */
8784 { "shlxS", { Gdq, Edq, VexGdq } },
8787 /* VEX_LEN_0F38F7_P_3 */
8789 { "shrxS", { Gdq, Edq, VexGdq } },
8792 /* VEX_LEN_0F3A00_P_2 */
8795 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
8798 /* VEX_LEN_0F3A01_P_2 */
8801 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
8804 /* VEX_LEN_0F3A06_P_2 */
8807 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
8810 /* VEX_LEN_0F3A0A_P_2 */
8812 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
8813 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
8816 /* VEX_LEN_0F3A0B_P_2 */
8818 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
8819 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
8822 /* VEX_LEN_0F3A14_P_2 */
8824 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
8827 /* VEX_LEN_0F3A15_P_2 */
8829 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
8832 /* VEX_LEN_0F3A16_P_2 */
8834 { "vpextrK", { Edq, XM, Ib } },
8837 /* VEX_LEN_0F3A17_P_2 */
8839 { "vextractps", { Edqd, XM, Ib } },
8842 /* VEX_LEN_0F3A18_P_2 */
8845 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
8848 /* VEX_LEN_0F3A19_P_2 */
8851 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
8854 /* VEX_LEN_0F3A20_P_2 */
8856 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
8859 /* VEX_LEN_0F3A21_P_2 */
8861 { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
8864 /* VEX_LEN_0F3A22_P_2 */
8866 { "vpinsrK", { XM, Vex128, Edq, Ib } },
8869 /* VEX_LEN_0F3A38_P_2 */
8872 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
8875 /* VEX_LEN_0F3A39_P_2 */
8878 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
8881 /* VEX_LEN_0F3A41_P_2 */
8883 { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
8886 /* VEX_LEN_0F3A44_P_2 */
8888 { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
8891 /* VEX_LEN_0F3A46_P_2 */
8894 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
8897 /* VEX_LEN_0F3A60_P_2 */
8899 { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
8902 /* VEX_LEN_0F3A61_P_2 */
8904 { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
8907 /* VEX_LEN_0F3A62_P_2 */
8909 { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
8912 /* VEX_LEN_0F3A63_P_2 */
8914 { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
8917 /* VEX_LEN_0F3A6A_P_2 */
8919 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8922 /* VEX_LEN_0F3A6B_P_2 */
8924 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8927 /* VEX_LEN_0F3A6E_P_2 */
8929 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8932 /* VEX_LEN_0F3A6F_P_2 */
8934 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8937 /* VEX_LEN_0F3A7A_P_2 */
8939 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8942 /* VEX_LEN_0F3A7B_P_2 */
8944 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8947 /* VEX_LEN_0F3A7E_P_2 */
8949 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8952 /* VEX_LEN_0F3A7F_P_2 */
8954 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8957 /* VEX_LEN_0F3ADF_P_2 */
8959 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
8962 /* VEX_LEN_0F3AF0_P_3 */
8964 { "rorxS", { Gdq, Edq, Ib } },
8967 /* VEX_LEN_0FXOP_09_80 */
8969 { "vfrczps", { XM, EXxmm } },
8970 { "vfrczps", { XM, EXymmq } },
8973 /* VEX_LEN_0FXOP_09_81 */
8975 { "vfrczpd", { XM, EXxmm } },
8976 { "vfrczpd", { XM, EXymmq } },
8980 static const struct dis386 vex_w_table[][2] = {
8982 /* VEX_W_0F10_P_0 */
8983 { "vmovups", { XM, EXx } },
8986 /* VEX_W_0F10_P_1 */
8987 { "vmovss", { XMVexScalar, VexScalar, EXdScalar } },
8990 /* VEX_W_0F10_P_2 */
8991 { "vmovupd", { XM, EXx } },
8994 /* VEX_W_0F10_P_3 */
8995 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } },
8998 /* VEX_W_0F11_P_0 */
8999 { "vmovups", { EXxS, XM } },
9002 /* VEX_W_0F11_P_1 */
9003 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } },
9006 /* VEX_W_0F11_P_2 */
9007 { "vmovupd", { EXxS, XM } },
9010 /* VEX_W_0F11_P_3 */
9011 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } },
9014 /* VEX_W_0F12_P_0_M_0 */
9015 { "vmovlps", { XM, Vex128, EXq } },
9018 /* VEX_W_0F12_P_0_M_1 */
9019 { "vmovhlps", { XM, Vex128, EXq } },
9022 /* VEX_W_0F12_P_1 */
9023 { "vmovsldup", { XM, EXx } },
9026 /* VEX_W_0F12_P_2 */
9027 { "vmovlpd", { XM, Vex128, EXq } },
9030 /* VEX_W_0F12_P_3 */
9031 { "vmovddup", { XM, EXymmq } },
9034 /* VEX_W_0F13_M_0 */
9035 { "vmovlpX", { EXq, XM } },
9039 { "vunpcklpX", { XM, Vex, EXx } },
9043 { "vunpckhpX", { XM, Vex, EXx } },
9046 /* VEX_W_0F16_P_0_M_0 */
9047 { "vmovhps", { XM, Vex128, EXq } },
9050 /* VEX_W_0F16_P_0_M_1 */
9051 { "vmovlhps", { XM, Vex128, EXq } },
9054 /* VEX_W_0F16_P_1 */
9055 { "vmovshdup", { XM, EXx } },
9058 /* VEX_W_0F16_P_2 */
9059 { "vmovhpd", { XM, Vex128, EXq } },
9062 /* VEX_W_0F17_M_0 */
9063 { "vmovhpX", { EXq, XM } },
9067 { "vmovapX", { XM, EXx } },
9071 { "vmovapX", { EXxS, XM } },
9074 /* VEX_W_0F2B_M_0 */
9075 { "vmovntpX", { Mx, XM } },
9078 /* VEX_W_0F2E_P_0 */
9079 { "vucomiss", { XMScalar, EXdScalar } },
9082 /* VEX_W_0F2E_P_2 */
9083 { "vucomisd", { XMScalar, EXqScalar } },
9086 /* VEX_W_0F2F_P_0 */
9087 { "vcomiss", { XMScalar, EXdScalar } },
9090 /* VEX_W_0F2F_P_2 */
9091 { "vcomisd", { XMScalar, EXqScalar } },
9094 /* VEX_W_0F50_M_0 */
9095 { "vmovmskpX", { Gdq, XS } },
9098 /* VEX_W_0F51_P_0 */
9099 { "vsqrtps", { XM, EXx } },
9102 /* VEX_W_0F51_P_1 */
9103 { "vsqrtss", { XMScalar, VexScalar, EXdScalar } },
9106 /* VEX_W_0F51_P_2 */
9107 { "vsqrtpd", { XM, EXx } },
9110 /* VEX_W_0F51_P_3 */
9111 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar } },
9114 /* VEX_W_0F52_P_0 */
9115 { "vrsqrtps", { XM, EXx } },
9118 /* VEX_W_0F52_P_1 */
9119 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar } },
9122 /* VEX_W_0F53_P_0 */
9123 { "vrcpps", { XM, EXx } },
9126 /* VEX_W_0F53_P_1 */
9127 { "vrcpss", { XMScalar, VexScalar, EXdScalar } },
9130 /* VEX_W_0F58_P_0 */
9131 { "vaddps", { XM, Vex, EXx } },
9134 /* VEX_W_0F58_P_1 */
9135 { "vaddss", { XMScalar, VexScalar, EXdScalar } },
9138 /* VEX_W_0F58_P_2 */
9139 { "vaddpd", { XM, Vex, EXx } },
9142 /* VEX_W_0F58_P_3 */
9143 { "vaddsd", { XMScalar, VexScalar, EXqScalar } },
9146 /* VEX_W_0F59_P_0 */
9147 { "vmulps", { XM, Vex, EXx } },
9150 /* VEX_W_0F59_P_1 */
9151 { "vmulss", { XMScalar, VexScalar, EXdScalar } },
9154 /* VEX_W_0F59_P_2 */
9155 { "vmulpd", { XM, Vex, EXx } },
9158 /* VEX_W_0F59_P_3 */
9159 { "vmulsd", { XMScalar, VexScalar, EXqScalar } },
9162 /* VEX_W_0F5A_P_0 */
9163 { "vcvtps2pd", { XM, EXxmmq } },
9166 /* VEX_W_0F5A_P_1 */
9167 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar } },
9170 /* VEX_W_0F5A_P_3 */
9171 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar } },
9174 /* VEX_W_0F5B_P_0 */
9175 { "vcvtdq2ps", { XM, EXx } },
9178 /* VEX_W_0F5B_P_1 */
9179 { "vcvttps2dq", { XM, EXx } },
9182 /* VEX_W_0F5B_P_2 */
9183 { "vcvtps2dq", { XM, EXx } },
9186 /* VEX_W_0F5C_P_0 */
9187 { "vsubps", { XM, Vex, EXx } },
9190 /* VEX_W_0F5C_P_1 */
9191 { "vsubss", { XMScalar, VexScalar, EXdScalar } },
9194 /* VEX_W_0F5C_P_2 */
9195 { "vsubpd", { XM, Vex, EXx } },
9198 /* VEX_W_0F5C_P_3 */
9199 { "vsubsd", { XMScalar, VexScalar, EXqScalar } },
9202 /* VEX_W_0F5D_P_0 */
9203 { "vminps", { XM, Vex, EXx } },
9206 /* VEX_W_0F5D_P_1 */
9207 { "vminss", { XMScalar, VexScalar, EXdScalar } },
9210 /* VEX_W_0F5D_P_2 */
9211 { "vminpd", { XM, Vex, EXx } },
9214 /* VEX_W_0F5D_P_3 */
9215 { "vminsd", { XMScalar, VexScalar, EXqScalar } },
9218 /* VEX_W_0F5E_P_0 */
9219 { "vdivps", { XM, Vex, EXx } },
9222 /* VEX_W_0F5E_P_1 */
9223 { "vdivss", { XMScalar, VexScalar, EXdScalar } },
9226 /* VEX_W_0F5E_P_2 */
9227 { "vdivpd", { XM, Vex, EXx } },
9230 /* VEX_W_0F5E_P_3 */
9231 { "vdivsd", { XMScalar, VexScalar, EXqScalar } },
9234 /* VEX_W_0F5F_P_0 */
9235 { "vmaxps", { XM, Vex, EXx } },
9238 /* VEX_W_0F5F_P_1 */
9239 { "vmaxss", { XMScalar, VexScalar, EXdScalar } },
9242 /* VEX_W_0F5F_P_2 */
9243 { "vmaxpd", { XM, Vex, EXx } },
9246 /* VEX_W_0F5F_P_3 */
9247 { "vmaxsd", { XMScalar, VexScalar, EXqScalar } },
9250 /* VEX_W_0F60_P_2 */
9251 { "vpunpcklbw", { XM, Vex, EXx } },
9254 /* VEX_W_0F61_P_2 */
9255 { "vpunpcklwd", { XM, Vex, EXx } },
9258 /* VEX_W_0F62_P_2 */
9259 { "vpunpckldq", { XM, Vex, EXx } },
9262 /* VEX_W_0F63_P_2 */
9263 { "vpacksswb", { XM, Vex, EXx } },
9266 /* VEX_W_0F64_P_2 */
9267 { "vpcmpgtb", { XM, Vex, EXx } },
9270 /* VEX_W_0F65_P_2 */
9271 { "vpcmpgtw", { XM, Vex, EXx } },
9274 /* VEX_W_0F66_P_2 */
9275 { "vpcmpgtd", { XM, Vex, EXx } },
9278 /* VEX_W_0F67_P_2 */
9279 { "vpackuswb", { XM, Vex, EXx } },
9282 /* VEX_W_0F68_P_2 */
9283 { "vpunpckhbw", { XM, Vex, EXx } },
9286 /* VEX_W_0F69_P_2 */
9287 { "vpunpckhwd", { XM, Vex, EXx } },
9290 /* VEX_W_0F6A_P_2 */
9291 { "vpunpckhdq", { XM, Vex, EXx } },
9294 /* VEX_W_0F6B_P_2 */
9295 { "vpackssdw", { XM, Vex, EXx } },
9298 /* VEX_W_0F6C_P_2 */
9299 { "vpunpcklqdq", { XM, Vex, EXx } },
9302 /* VEX_W_0F6D_P_2 */
9303 { "vpunpckhqdq", { XM, Vex, EXx } },
9306 /* VEX_W_0F6F_P_1 */
9307 { "vmovdqu", { XM, EXx } },
9310 /* VEX_W_0F6F_P_2 */
9311 { "vmovdqa", { XM, EXx } },
9314 /* VEX_W_0F70_P_1 */
9315 { "vpshufhw", { XM, EXx, Ib } },
9318 /* VEX_W_0F70_P_2 */
9319 { "vpshufd", { XM, EXx, Ib } },
9322 /* VEX_W_0F70_P_3 */
9323 { "vpshuflw", { XM, EXx, Ib } },
9326 /* VEX_W_0F71_R_2_P_2 */
9327 { "vpsrlw", { Vex, XS, Ib } },
9330 /* VEX_W_0F71_R_4_P_2 */
9331 { "vpsraw", { Vex, XS, Ib } },
9334 /* VEX_W_0F71_R_6_P_2 */
9335 { "vpsllw", { Vex, XS, Ib } },
9338 /* VEX_W_0F72_R_2_P_2 */
9339 { "vpsrld", { Vex, XS, Ib } },
9342 /* VEX_W_0F72_R_4_P_2 */
9343 { "vpsrad", { Vex, XS, Ib } },
9346 /* VEX_W_0F72_R_6_P_2 */
9347 { "vpslld", { Vex, XS, Ib } },
9350 /* VEX_W_0F73_R_2_P_2 */
9351 { "vpsrlq", { Vex, XS, Ib } },
9354 /* VEX_W_0F73_R_3_P_2 */
9355 { "vpsrldq", { Vex, XS, Ib } },
9358 /* VEX_W_0F73_R_6_P_2 */
9359 { "vpsllq", { Vex, XS, Ib } },
9362 /* VEX_W_0F73_R_7_P_2 */
9363 { "vpslldq", { Vex, XS, Ib } },
9366 /* VEX_W_0F74_P_2 */
9367 { "vpcmpeqb", { XM, Vex, EXx } },
9370 /* VEX_W_0F75_P_2 */
9371 { "vpcmpeqw", { XM, Vex, EXx } },
9374 /* VEX_W_0F76_P_2 */
9375 { "vpcmpeqd", { XM, Vex, EXx } },
9378 /* VEX_W_0F77_P_0 */
9382 /* VEX_W_0F7C_P_2 */
9383 { "vhaddpd", { XM, Vex, EXx } },
9386 /* VEX_W_0F7C_P_3 */
9387 { "vhaddps", { XM, Vex, EXx } },
9390 /* VEX_W_0F7D_P_2 */
9391 { "vhsubpd", { XM, Vex, EXx } },
9394 /* VEX_W_0F7D_P_3 */
9395 { "vhsubps", { XM, Vex, EXx } },
9398 /* VEX_W_0F7E_P_1 */
9399 { "vmovq", { XMScalar, EXqScalar } },
9402 /* VEX_W_0F7F_P_1 */
9403 { "vmovdqu", { EXxS, XM } },
9406 /* VEX_W_0F7F_P_2 */
9407 { "vmovdqa", { EXxS, XM } },
9410 /* VEX_W_0FAE_R_2_M_0 */
9411 { "vldmxcsr", { Md } },
9414 /* VEX_W_0FAE_R_3_M_0 */
9415 { "vstmxcsr", { Md } },
9418 /* VEX_W_0FC2_P_0 */
9419 { "vcmpps", { XM, Vex, EXx, VCMP } },
9422 /* VEX_W_0FC2_P_1 */
9423 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP } },
9426 /* VEX_W_0FC2_P_2 */
9427 { "vcmppd", { XM, Vex, EXx, VCMP } },
9430 /* VEX_W_0FC2_P_3 */
9431 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP } },
9434 /* VEX_W_0FC4_P_2 */
9435 { "vpinsrw", { XM, Vex128, Edqw, Ib } },
9438 /* VEX_W_0FC5_P_2 */
9439 { "vpextrw", { Gdq, XS, Ib } },
9442 /* VEX_W_0FD0_P_2 */
9443 { "vaddsubpd", { XM, Vex, EXx } },
9446 /* VEX_W_0FD0_P_3 */
9447 { "vaddsubps", { XM, Vex, EXx } },
9450 /* VEX_W_0FD1_P_2 */
9451 { "vpsrlw", { XM, Vex, EXxmm } },
9454 /* VEX_W_0FD2_P_2 */
9455 { "vpsrld", { XM, Vex, EXxmm } },
9458 /* VEX_W_0FD3_P_2 */
9459 { "vpsrlq", { XM, Vex, EXxmm } },
9462 /* VEX_W_0FD4_P_2 */
9463 { "vpaddq", { XM, Vex, EXx } },
9466 /* VEX_W_0FD5_P_2 */
9467 { "vpmullw", { XM, Vex, EXx } },
9470 /* VEX_W_0FD6_P_2 */
9471 { "vmovq", { EXqScalarS, XMScalar } },
9474 /* VEX_W_0FD7_P_2_M_1 */
9475 { "vpmovmskb", { Gdq, XS } },
9478 /* VEX_W_0FD8_P_2 */
9479 { "vpsubusb", { XM, Vex, EXx } },
9482 /* VEX_W_0FD9_P_2 */
9483 { "vpsubusw", { XM, Vex, EXx } },
9486 /* VEX_W_0FDA_P_2 */
9487 { "vpminub", { XM, Vex, EXx } },
9490 /* VEX_W_0FDB_P_2 */
9491 { "vpand", { XM, Vex, EXx } },
9494 /* VEX_W_0FDC_P_2 */
9495 { "vpaddusb", { XM, Vex, EXx } },
9498 /* VEX_W_0FDD_P_2 */
9499 { "vpaddusw", { XM, Vex, EXx } },
9502 /* VEX_W_0FDE_P_2 */
9503 { "vpmaxub", { XM, Vex, EXx } },
9506 /* VEX_W_0FDF_P_2 */
9507 { "vpandn", { XM, Vex, EXx } },
9510 /* VEX_W_0FE0_P_2 */
9511 { "vpavgb", { XM, Vex, EXx } },
9514 /* VEX_W_0FE1_P_2 */
9515 { "vpsraw", { XM, Vex, EXxmm } },
9518 /* VEX_W_0FE2_P_2 */
9519 { "vpsrad", { XM, Vex, EXxmm } },
9522 /* VEX_W_0FE3_P_2 */
9523 { "vpavgw", { XM, Vex, EXx } },
9526 /* VEX_W_0FE4_P_2 */
9527 { "vpmulhuw", { XM, Vex, EXx } },
9530 /* VEX_W_0FE5_P_2 */
9531 { "vpmulhw", { XM, Vex, EXx } },
9534 /* VEX_W_0FE6_P_1 */
9535 { "vcvtdq2pd", { XM, EXxmmq } },
9538 /* VEX_W_0FE6_P_2 */
9539 { "vcvttpd2dq%XY", { XMM, EXx } },
9542 /* VEX_W_0FE6_P_3 */
9543 { "vcvtpd2dq%XY", { XMM, EXx } },
9546 /* VEX_W_0FE7_P_2_M_0 */
9547 { "vmovntdq", { Mx, XM } },
9550 /* VEX_W_0FE8_P_2 */
9551 { "vpsubsb", { XM, Vex, EXx } },
9554 /* VEX_W_0FE9_P_2 */
9555 { "vpsubsw", { XM, Vex, EXx } },
9558 /* VEX_W_0FEA_P_2 */
9559 { "vpminsw", { XM, Vex, EXx } },
9562 /* VEX_W_0FEB_P_2 */
9563 { "vpor", { XM, Vex, EXx } },
9566 /* VEX_W_0FEC_P_2 */
9567 { "vpaddsb", { XM, Vex, EXx } },
9570 /* VEX_W_0FED_P_2 */
9571 { "vpaddsw", { XM, Vex, EXx } },
9574 /* VEX_W_0FEE_P_2 */
9575 { "vpmaxsw", { XM, Vex, EXx } },
9578 /* VEX_W_0FEF_P_2 */
9579 { "vpxor", { XM, Vex, EXx } },
9582 /* VEX_W_0FF0_P_3_M_0 */
9583 { "vlddqu", { XM, M } },
9586 /* VEX_W_0FF1_P_2 */
9587 { "vpsllw", { XM, Vex, EXxmm } },
9590 /* VEX_W_0FF2_P_2 */
9591 { "vpslld", { XM, Vex, EXxmm } },
9594 /* VEX_W_0FF3_P_2 */
9595 { "vpsllq", { XM, Vex, EXxmm } },
9598 /* VEX_W_0FF4_P_2 */
9599 { "vpmuludq", { XM, Vex, EXx } },
9602 /* VEX_W_0FF5_P_2 */
9603 { "vpmaddwd", { XM, Vex, EXx } },
9606 /* VEX_W_0FF6_P_2 */
9607 { "vpsadbw", { XM, Vex, EXx } },
9610 /* VEX_W_0FF7_P_2 */
9611 { "vmaskmovdqu", { XM, XS } },
9614 /* VEX_W_0FF8_P_2 */
9615 { "vpsubb", { XM, Vex, EXx } },
9618 /* VEX_W_0FF9_P_2 */
9619 { "vpsubw", { XM, Vex, EXx } },
9622 /* VEX_W_0FFA_P_2 */
9623 { "vpsubd", { XM, Vex, EXx } },
9626 /* VEX_W_0FFB_P_2 */
9627 { "vpsubq", { XM, Vex, EXx } },
9630 /* VEX_W_0FFC_P_2 */
9631 { "vpaddb", { XM, Vex, EXx } },
9634 /* VEX_W_0FFD_P_2 */
9635 { "vpaddw", { XM, Vex, EXx } },
9638 /* VEX_W_0FFE_P_2 */
9639 { "vpaddd", { XM, Vex, EXx } },
9642 /* VEX_W_0F3800_P_2 */
9643 { "vpshufb", { XM, Vex, EXx } },
9646 /* VEX_W_0F3801_P_2 */
9647 { "vphaddw", { XM, Vex, EXx } },
9650 /* VEX_W_0F3802_P_2 */
9651 { "vphaddd", { XM, Vex, EXx } },
9654 /* VEX_W_0F3803_P_2 */
9655 { "vphaddsw", { XM, Vex, EXx } },
9658 /* VEX_W_0F3804_P_2 */
9659 { "vpmaddubsw", { XM, Vex, EXx } },
9662 /* VEX_W_0F3805_P_2 */
9663 { "vphsubw", { XM, Vex, EXx } },
9666 /* VEX_W_0F3806_P_2 */
9667 { "vphsubd", { XM, Vex, EXx } },
9670 /* VEX_W_0F3807_P_2 */
9671 { "vphsubsw", { XM, Vex, EXx } },
9674 /* VEX_W_0F3808_P_2 */
9675 { "vpsignb", { XM, Vex, EXx } },
9678 /* VEX_W_0F3809_P_2 */
9679 { "vpsignw", { XM, Vex, EXx } },
9682 /* VEX_W_0F380A_P_2 */
9683 { "vpsignd", { XM, Vex, EXx } },
9686 /* VEX_W_0F380B_P_2 */
9687 { "vpmulhrsw", { XM, Vex, EXx } },
9690 /* VEX_W_0F380C_P_2 */
9691 { "vpermilps", { XM, Vex, EXx } },
9694 /* VEX_W_0F380D_P_2 */
9695 { "vpermilpd", { XM, Vex, EXx } },
9698 /* VEX_W_0F380E_P_2 */
9699 { "vtestps", { XM, EXx } },
9702 /* VEX_W_0F380F_P_2 */
9703 { "vtestpd", { XM, EXx } },
9706 /* VEX_W_0F3816_P_2 */
9707 { "vpermps", { XM, Vex, EXx } },
9710 /* VEX_W_0F3817_P_2 */
9711 { "vptest", { XM, EXx } },
9714 /* VEX_W_0F3818_P_2 */
9715 { "vbroadcastss", { XM, EXxmm_md } },
9718 /* VEX_W_0F3819_P_2 */
9719 { "vbroadcastsd", { XM, EXxmm_mq } },
9722 /* VEX_W_0F381A_P_2_M_0 */
9723 { "vbroadcastf128", { XM, Mxmm } },
9726 /* VEX_W_0F381C_P_2 */
9727 { "vpabsb", { XM, EXx } },
9730 /* VEX_W_0F381D_P_2 */
9731 { "vpabsw", { XM, EXx } },
9734 /* VEX_W_0F381E_P_2 */
9735 { "vpabsd", { XM, EXx } },
9738 /* VEX_W_0F3820_P_2 */
9739 { "vpmovsxbw", { XM, EXxmmq } },
9742 /* VEX_W_0F3821_P_2 */
9743 { "vpmovsxbd", { XM, EXxmmqd } },
9746 /* VEX_W_0F3822_P_2 */
9747 { "vpmovsxbq", { XM, EXxmmdw } },
9750 /* VEX_W_0F3823_P_2 */
9751 { "vpmovsxwd", { XM, EXxmmq } },
9754 /* VEX_W_0F3824_P_2 */
9755 { "vpmovsxwq", { XM, EXxmmqd } },
9758 /* VEX_W_0F3825_P_2 */
9759 { "vpmovsxdq", { XM, EXxmmq } },
9762 /* VEX_W_0F3828_P_2 */
9763 { "vpmuldq", { XM, Vex, EXx } },
9766 /* VEX_W_0F3829_P_2 */
9767 { "vpcmpeqq", { XM, Vex, EXx } },
9770 /* VEX_W_0F382A_P_2_M_0 */
9771 { "vmovntdqa", { XM, Mx } },
9774 /* VEX_W_0F382B_P_2 */
9775 { "vpackusdw", { XM, Vex, EXx } },
9778 /* VEX_W_0F382C_P_2_M_0 */
9779 { "vmaskmovps", { XM, Vex, Mx } },
9782 /* VEX_W_0F382D_P_2_M_0 */
9783 { "vmaskmovpd", { XM, Vex, Mx } },
9786 /* VEX_W_0F382E_P_2_M_0 */
9787 { "vmaskmovps", { Mx, Vex, XM } },
9790 /* VEX_W_0F382F_P_2_M_0 */
9791 { "vmaskmovpd", { Mx, Vex, XM } },
9794 /* VEX_W_0F3830_P_2 */
9795 { "vpmovzxbw", { XM, EXxmmq } },
9798 /* VEX_W_0F3831_P_2 */
9799 { "vpmovzxbd", { XM, EXxmmqd } },
9802 /* VEX_W_0F3832_P_2 */
9803 { "vpmovzxbq", { XM, EXxmmdw } },
9806 /* VEX_W_0F3833_P_2 */
9807 { "vpmovzxwd", { XM, EXxmmq } },
9810 /* VEX_W_0F3834_P_2 */
9811 { "vpmovzxwq", { XM, EXxmmqd } },
9814 /* VEX_W_0F3835_P_2 */
9815 { "vpmovzxdq", { XM, EXxmmq } },
9818 /* VEX_W_0F3836_P_2 */
9819 { "vpermd", { XM, Vex, EXx } },
9822 /* VEX_W_0F3837_P_2 */
9823 { "vpcmpgtq", { XM, Vex, EXx } },
9826 /* VEX_W_0F3838_P_2 */
9827 { "vpminsb", { XM, Vex, EXx } },
9830 /* VEX_W_0F3839_P_2 */
9831 { "vpminsd", { XM, Vex, EXx } },
9834 /* VEX_W_0F383A_P_2 */
9835 { "vpminuw", { XM, Vex, EXx } },
9838 /* VEX_W_0F383B_P_2 */
9839 { "vpminud", { XM, Vex, EXx } },
9842 /* VEX_W_0F383C_P_2 */
9843 { "vpmaxsb", { XM, Vex, EXx } },
9846 /* VEX_W_0F383D_P_2 */
9847 { "vpmaxsd", { XM, Vex, EXx } },
9850 /* VEX_W_0F383E_P_2 */
9851 { "vpmaxuw", { XM, Vex, EXx } },
9854 /* VEX_W_0F383F_P_2 */
9855 { "vpmaxud", { XM, Vex, EXx } },
9858 /* VEX_W_0F3840_P_2 */
9859 { "vpmulld", { XM, Vex, EXx } },
9862 /* VEX_W_0F3841_P_2 */
9863 { "vphminposuw", { XM, EXx } },
9866 /* VEX_W_0F3846_P_2 */
9867 { "vpsravd", { XM, Vex, EXx } },
9870 /* VEX_W_0F3858_P_2 */
9871 { "vpbroadcastd", { XM, EXxmm_md } },
9874 /* VEX_W_0F3859_P_2 */
9875 { "vpbroadcastq", { XM, EXxmm_mq } },
9878 /* VEX_W_0F385A_P_2_M_0 */
9879 { "vbroadcasti128", { XM, Mxmm } },
9882 /* VEX_W_0F3878_P_2 */
9883 { "vpbroadcastb", { XM, EXxmm_mb } },
9886 /* VEX_W_0F3879_P_2 */
9887 { "vpbroadcastw", { XM, EXxmm_mw } },
9890 /* VEX_W_0F38DB_P_2 */
9891 { "vaesimc", { XM, EXx } },
9894 /* VEX_W_0F38DC_P_2 */
9895 { "vaesenc", { XM, Vex128, EXx } },
9898 /* VEX_W_0F38DD_P_2 */
9899 { "vaesenclast", { XM, Vex128, EXx } },
9902 /* VEX_W_0F38DE_P_2 */
9903 { "vaesdec", { XM, Vex128, EXx } },
9906 /* VEX_W_0F38DF_P_2 */
9907 { "vaesdeclast", { XM, Vex128, EXx } },
9910 /* VEX_W_0F3A00_P_2 */
9912 { "vpermq", { XM, EXx, Ib } },
9915 /* VEX_W_0F3A01_P_2 */
9917 { "vpermpd", { XM, EXx, Ib } },
9920 /* VEX_W_0F3A02_P_2 */
9921 { "vpblendd", { XM, Vex, EXx, Ib } },
9924 /* VEX_W_0F3A04_P_2 */
9925 { "vpermilps", { XM, EXx, Ib } },
9928 /* VEX_W_0F3A05_P_2 */
9929 { "vpermilpd", { XM, EXx, Ib } },
9932 /* VEX_W_0F3A06_P_2 */
9933 { "vperm2f128", { XM, Vex256, EXx, Ib } },
9936 /* VEX_W_0F3A08_P_2 */
9937 { "vroundps", { XM, EXx, Ib } },
9940 /* VEX_W_0F3A09_P_2 */
9941 { "vroundpd", { XM, EXx, Ib } },
9944 /* VEX_W_0F3A0A_P_2 */
9945 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib } },
9948 /* VEX_W_0F3A0B_P_2 */
9949 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib } },
9952 /* VEX_W_0F3A0C_P_2 */
9953 { "vblendps", { XM, Vex, EXx, Ib } },
9956 /* VEX_W_0F3A0D_P_2 */
9957 { "vblendpd", { XM, Vex, EXx, Ib } },
9960 /* VEX_W_0F3A0E_P_2 */
9961 { "vpblendw", { XM, Vex, EXx, Ib } },
9964 /* VEX_W_0F3A0F_P_2 */
9965 { "vpalignr", { XM, Vex, EXx, Ib } },
9968 /* VEX_W_0F3A14_P_2 */
9969 { "vpextrb", { Edqb, XM, Ib } },
9972 /* VEX_W_0F3A15_P_2 */
9973 { "vpextrw", { Edqw, XM, Ib } },
9976 /* VEX_W_0F3A18_P_2 */
9977 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },
9980 /* VEX_W_0F3A19_P_2 */
9981 { "vextractf128", { EXxmm, XM, Ib } },
9984 /* VEX_W_0F3A20_P_2 */
9985 { "vpinsrb", { XM, Vex128, Edqb, Ib } },
9988 /* VEX_W_0F3A21_P_2 */
9989 { "vinsertps", { XM, Vex128, EXd, Ib } },
9992 /* VEX_W_0F3A38_P_2 */
9993 { "vinserti128", { XM, Vex256, EXxmm, Ib } },
9996 /* VEX_W_0F3A39_P_2 */
9997 { "vextracti128", { EXxmm, XM, Ib } },
10000 /* VEX_W_0F3A40_P_2 */
10001 { "vdpps", { XM, Vex, EXx, Ib } },
10004 /* VEX_W_0F3A41_P_2 */
10005 { "vdppd", { XM, Vex128, EXx, Ib } },
10008 /* VEX_W_0F3A42_P_2 */
10009 { "vmpsadbw", { XM, Vex, EXx, Ib } },
10012 /* VEX_W_0F3A44_P_2 */
10013 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } },
10016 /* VEX_W_0F3A46_P_2 */
10017 { "vperm2i128", { XM, Vex256, EXx, Ib } },
10020 /* VEX_W_0F3A48_P_2 */
10021 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10022 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10025 /* VEX_W_0F3A49_P_2 */
10026 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10027 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10030 /* VEX_W_0F3A4A_P_2 */
10031 { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
10034 /* VEX_W_0F3A4B_P_2 */
10035 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
10038 /* VEX_W_0F3A4C_P_2 */
10039 { "vpblendvb", { XM, Vex, EXx, XMVexI4 } },
10042 /* VEX_W_0F3A60_P_2 */
10043 { "vpcmpestrm", { XM, EXx, Ib } },
10046 /* VEX_W_0F3A61_P_2 */
10047 { "vpcmpestri", { XM, EXx, Ib } },
10050 /* VEX_W_0F3A62_P_2 */
10051 { "vpcmpistrm", { XM, EXx, Ib } },
10054 /* VEX_W_0F3A63_P_2 */
10055 { "vpcmpistri", { XM, EXx, Ib } },
10058 /* VEX_W_0F3ADF_P_2 */
10059 { "vaeskeygenassist", { XM, EXx, Ib } },
10063 static const struct dis386 mod_table[][2] = {
10066 { "leaS", { Gv, M } },
10069 /* MOD_0F01_REG_0 */
10070 { X86_64_TABLE (X86_64_0F01_REG_0) },
10071 { RM_TABLE (RM_0F01_REG_0) },
10074 /* MOD_0F01_REG_1 */
10075 { X86_64_TABLE (X86_64_0F01_REG_1) },
10076 { RM_TABLE (RM_0F01_REG_1) },
10079 /* MOD_0F01_REG_2 */
10080 { X86_64_TABLE (X86_64_0F01_REG_2) },
10081 { RM_TABLE (RM_0F01_REG_2) },
10084 /* MOD_0F01_REG_3 */
10085 { X86_64_TABLE (X86_64_0F01_REG_3) },
10086 { RM_TABLE (RM_0F01_REG_3) },
10089 /* MOD_0F01_REG_7 */
10090 { "invlpg", { Mb } },
10091 { RM_TABLE (RM_0F01_REG_7) },
10094 /* MOD_0F12_PREFIX_0 */
10095 { "movlps", { XM, EXq } },
10096 { "movhlps", { XM, EXq } },
10100 { "movlpX", { EXq, XM } },
10103 /* MOD_0F16_PREFIX_0 */
10104 { "movhps", { XM, EXq } },
10105 { "movlhps", { XM, EXq } },
10109 { "movhpX", { EXq, XM } },
10112 /* MOD_0F18_REG_0 */
10113 { "prefetchnta", { Mb } },
10116 /* MOD_0F18_REG_1 */
10117 { "prefetcht0", { Mb } },
10120 /* MOD_0F18_REG_2 */
10121 { "prefetcht1", { Mb } },
10124 /* MOD_0F18_REG_3 */
10125 { "prefetcht2", { Mb } },
10130 { "movZ", { Rm, Cm } },
10135 { "movZ", { Rm, Dm } },
10140 { "movZ", { Cm, Rm } },
10145 { "movZ", { Dm, Rm } },
10150 { "movL", { Rd, Td } },
10155 { "movL", { Td, Rd } },
10158 /* MOD_0F2B_PREFIX_0 */
10159 {"movntps", { Mx, XM } },
10162 /* MOD_0F2B_PREFIX_1 */
10163 {"movntss", { Md, XM } },
10166 /* MOD_0F2B_PREFIX_2 */
10167 {"movntpd", { Mx, XM } },
10170 /* MOD_0F2B_PREFIX_3 */
10171 {"movntsd", { Mq, XM } },
10176 { "movmskpX", { Gdq, XS } },
10179 /* MOD_0F71_REG_2 */
10181 { "psrlw", { MS, Ib } },
10184 /* MOD_0F71_REG_4 */
10186 { "psraw", { MS, Ib } },
10189 /* MOD_0F71_REG_6 */
10191 { "psllw", { MS, Ib } },
10194 /* MOD_0F72_REG_2 */
10196 { "psrld", { MS, Ib } },
10199 /* MOD_0F72_REG_4 */
10201 { "psrad", { MS, Ib } },
10204 /* MOD_0F72_REG_6 */
10206 { "pslld", { MS, Ib } },
10209 /* MOD_0F73_REG_2 */
10211 { "psrlq", { MS, Ib } },
10214 /* MOD_0F73_REG_3 */
10216 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10219 /* MOD_0F73_REG_6 */
10221 { "psllq", { MS, Ib } },
10224 /* MOD_0F73_REG_7 */
10226 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10229 /* MOD_0FAE_REG_0 */
10230 { "fxsave", { FXSAVE } },
10231 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10234 /* MOD_0FAE_REG_1 */
10235 { "fxrstor", { FXSAVE } },
10236 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10239 /* MOD_0FAE_REG_2 */
10240 { "ldmxcsr", { Md } },
10241 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10244 /* MOD_0FAE_REG_3 */
10245 { "stmxcsr", { Md } },
10246 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10249 /* MOD_0FAE_REG_4 */
10250 { "xsave", { FXSAVE } },
10253 /* MOD_0FAE_REG_5 */
10254 { "xrstor", { FXSAVE } },
10255 { RM_TABLE (RM_0FAE_REG_5) },
10258 /* MOD_0FAE_REG_6 */
10259 { "xsaveopt", { FXSAVE } },
10260 { RM_TABLE (RM_0FAE_REG_6) },
10263 /* MOD_0FAE_REG_7 */
10264 { "clflush", { Mb } },
10265 { RM_TABLE (RM_0FAE_REG_7) },
10269 { "lssS", { Gv, Mp } },
10273 { "lfsS", { Gv, Mp } },
10277 { "lgsS", { Gv, Mp } },
10280 /* MOD_0FC7_REG_6 */
10281 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
10282 { "rdrand", { Ev } },
10285 /* MOD_0FC7_REG_7 */
10286 { "vmptrst", { Mq } },
10291 { "pmovmskb", { Gdq, MS } },
10294 /* MOD_0FE7_PREFIX_2 */
10295 { "movntdq", { Mx, XM } },
10298 /* MOD_0FF0_PREFIX_3 */
10299 { "lddqu", { XM, M } },
10302 /* MOD_0F382A_PREFIX_2 */
10303 { "movntdqa", { XM, Mx } },
10307 { "bound{S|}", { Gv, Ma } },
10311 { "lesS", { Gv, Mp } },
10312 { VEX_C4_TABLE (VEX_0F) },
10316 { "ldsS", { Gv, Mp } },
10317 { VEX_C5_TABLE (VEX_0F) },
10320 /* MOD_VEX_0F12_PREFIX_0 */
10321 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10322 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10326 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10329 /* MOD_VEX_0F16_PREFIX_0 */
10330 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10331 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10335 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10339 { VEX_W_TABLE (VEX_W_0F2B_M_0) },
10344 { VEX_W_TABLE (VEX_W_0F50_M_0) },
10347 /* MOD_VEX_0F71_REG_2 */
10349 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10352 /* MOD_VEX_0F71_REG_4 */
10354 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10357 /* MOD_VEX_0F71_REG_6 */
10359 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10362 /* MOD_VEX_0F72_REG_2 */
10364 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10367 /* MOD_VEX_0F72_REG_4 */
10369 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10372 /* MOD_VEX_0F72_REG_6 */
10374 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10377 /* MOD_VEX_0F73_REG_2 */
10379 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10382 /* MOD_VEX_0F73_REG_3 */
10384 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10387 /* MOD_VEX_0F73_REG_6 */
10389 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10392 /* MOD_VEX_0F73_REG_7 */
10394 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10397 /* MOD_VEX_0FAE_REG_2 */
10398 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10401 /* MOD_VEX_0FAE_REG_3 */
10402 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10405 /* MOD_VEX_0FD7_PREFIX_2 */
10407 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
10410 /* MOD_VEX_0FE7_PREFIX_2 */
10411 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
10414 /* MOD_VEX_0FF0_PREFIX_3 */
10415 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
10418 /* MOD_VEX_0F381A_PREFIX_2 */
10419 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10422 /* MOD_VEX_0F382A_PREFIX_2 */
10423 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
10426 /* MOD_VEX_0F382C_PREFIX_2 */
10427 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10430 /* MOD_VEX_0F382D_PREFIX_2 */
10431 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10434 /* MOD_VEX_0F382E_PREFIX_2 */
10435 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10438 /* MOD_VEX_0F382F_PREFIX_2 */
10439 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10442 /* MOD_VEX_0F385A_PREFIX_2 */
10443 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10446 /* MOD_VEX_0F388C_PREFIX_2 */
10447 { "vpmaskmov%LW", { XM, Vex, Mx } },
10450 /* MOD_VEX_0F388E_PREFIX_2 */
10451 { "vpmaskmov%LW", { Mx, Vex, XM } },
10455 static const struct dis386 rm_table[][8] = {
10457 /* RM_0F01_REG_0 */
10459 { "vmcall", { Skip_MODRM } },
10460 { "vmlaunch", { Skip_MODRM } },
10461 { "vmresume", { Skip_MODRM } },
10462 { "vmxoff", { Skip_MODRM } },
10465 /* RM_0F01_REG_1 */
10466 { "monitor", { { OP_Monitor, 0 } } },
10467 { "mwait", { { OP_Mwait, 0 } } },
10470 /* RM_0F01_REG_2 */
10471 { "xgetbv", { Skip_MODRM } },
10472 { "xsetbv", { Skip_MODRM } },
10475 /* RM_0F01_REG_3 */
10476 { "vmrun", { Skip_MODRM } },
10477 { "vmmcall", { Skip_MODRM } },
10478 { "vmload", { Skip_MODRM } },
10479 { "vmsave", { Skip_MODRM } },
10480 { "stgi", { Skip_MODRM } },
10481 { "clgi", { Skip_MODRM } },
10482 { "skinit", { Skip_MODRM } },
10483 { "invlpga", { Skip_MODRM } },
10486 /* RM_0F01_REG_7 */
10487 { "swapgs", { Skip_MODRM } },
10488 { "rdtscp", { Skip_MODRM } },
10491 /* RM_0FAE_REG_5 */
10492 { "lfence", { Skip_MODRM } },
10495 /* RM_0FAE_REG_6 */
10496 { "mfence", { Skip_MODRM } },
10499 /* RM_0FAE_REG_7 */
10500 { "sfence", { Skip_MODRM } },
10504 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10506 /* We use the high bit to indicate different name for the same
10508 #define ADDR16_PREFIX (0x67 | 0x100)
10509 #define ADDR32_PREFIX (0x67 | 0x200)
10510 #define DATA16_PREFIX (0x66 | 0x100)
10511 #define DATA32_PREFIX (0x66 | 0x200)
10512 #define REP_PREFIX (0xf3 | 0x100)
10517 int newrex, i, length;
10523 last_lock_prefix = -1;
10524 last_repz_prefix = -1;
10525 last_repnz_prefix = -1;
10526 last_data_prefix = -1;
10527 last_addr_prefix = -1;
10528 last_rex_prefix = -1;
10529 last_seg_prefix = -1;
10530 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10531 all_prefixes[i] = 0;
10534 /* The maximum instruction length is 15bytes. */
10535 while (length < MAX_CODE_LENGTH - 1)
10537 FETCH_DATA (the_info, codep + 1);
10541 /* REX prefixes family. */
10558 if (address_mode == mode_64bit)
10562 last_rex_prefix = i;
10565 prefixes |= PREFIX_REPZ;
10566 last_repz_prefix = i;
10569 prefixes |= PREFIX_REPNZ;
10570 last_repnz_prefix = i;
10573 prefixes |= PREFIX_LOCK;
10574 last_lock_prefix = i;
10577 prefixes |= PREFIX_CS;
10578 last_seg_prefix = i;
10581 prefixes |= PREFIX_SS;
10582 last_seg_prefix = i;
10585 prefixes |= PREFIX_DS;
10586 last_seg_prefix = i;
10589 prefixes |= PREFIX_ES;
10590 last_seg_prefix = i;
10593 prefixes |= PREFIX_FS;
10594 last_seg_prefix = i;
10597 prefixes |= PREFIX_GS;
10598 last_seg_prefix = i;
10601 prefixes |= PREFIX_DATA;
10602 last_data_prefix = i;
10605 prefixes |= PREFIX_ADDR;
10606 last_addr_prefix = i;
10609 /* fwait is really an instruction. If there are prefixes
10610 before the fwait, they belong to the fwait, *not* to the
10611 following instruction. */
10612 if (prefixes || rex)
10614 prefixes |= PREFIX_FWAIT;
10618 prefixes = PREFIX_FWAIT;
10623 /* Rex is ignored when followed by another prefix. */
10629 if (*codep != FWAIT_OPCODE)
10630 all_prefixes[i++] = *codep;
10639 seg_prefix (int pref)
10660 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10663 static const char *
10664 prefix_name (int pref, int sizeflag)
10666 static const char *rexes [16] =
10669 "rex.B", /* 0x41 */
10670 "rex.X", /* 0x42 */
10671 "rex.XB", /* 0x43 */
10672 "rex.R", /* 0x44 */
10673 "rex.RB", /* 0x45 */
10674 "rex.RX", /* 0x46 */
10675 "rex.RXB", /* 0x47 */
10676 "rex.W", /* 0x48 */
10677 "rex.WB", /* 0x49 */
10678 "rex.WX", /* 0x4a */
10679 "rex.WXB", /* 0x4b */
10680 "rex.WR", /* 0x4c */
10681 "rex.WRB", /* 0x4d */
10682 "rex.WRX", /* 0x4e */
10683 "rex.WRXB", /* 0x4f */
10688 /* REX prefixes family. */
10705 return rexes [pref - 0x40];
10725 return (sizeflag & DFLAG) ? "data16" : "data32";
10727 if (address_mode == mode_64bit)
10728 return (sizeflag & AFLAG) ? "addr32" : "addr64";
10730 return (sizeflag & AFLAG) ? "addr16" : "addr32";
10733 case ADDR16_PREFIX:
10735 case ADDR32_PREFIX:
10737 case DATA16_PREFIX:
10739 case DATA32_PREFIX:
10748 static char op_out[MAX_OPERANDS][100];
10749 static int op_ad, op_index[MAX_OPERANDS];
10750 static int two_source_ops;
10751 static bfd_vma op_address[MAX_OPERANDS];
10752 static bfd_vma op_riprel[MAX_OPERANDS];
10753 static bfd_vma start_pc;
10756 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10757 * (see topic "Redundant prefixes" in the "Differences from 8086"
10758 * section of the "Virtual 8086 Mode" chapter.)
10759 * 'pc' should be the address of this instruction, it will
10760 * be used to print the target address if this is a relative jump or call
10761 * The function returns the length of this instruction in bytes.
10764 static char intel_syntax;
10765 static char intel_mnemonic = !SYSV386_COMPAT;
10766 static char open_char;
10767 static char close_char;
10768 static char separator_char;
10769 static char scale_char;
10771 /* Here for backwards compatibility. When gdb stops using
10772 print_insn_i386_att and print_insn_i386_intel these functions can
10773 disappear, and print_insn_i386 be merged into print_insn. */
10775 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10779 return print_insn (pc, info);
10783 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10787 return print_insn (pc, info);
10791 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10795 return print_insn (pc, info);
10799 print_i386_disassembler_options (FILE *stream)
10801 fprintf (stream, _("\n\
10802 The following i386/x86-64 specific disassembler options are supported for use\n\
10803 with the -M switch (multiple options should be separated by commas):\n"));
10805 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
10806 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
10807 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
10808 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
10809 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
10810 fprintf (stream, _(" att-mnemonic\n"
10811 " Display instruction in AT&T mnemonic\n"));
10812 fprintf (stream, _(" intel-mnemonic\n"
10813 " Display instruction in Intel mnemonic\n"));
10814 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
10815 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
10816 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
10817 fprintf (stream, _(" data32 Assume 32bit data size\n"));
10818 fprintf (stream, _(" data16 Assume 16bit data size\n"));
10819 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
10823 static const struct dis386 bad_opcode = { "(bad)", { XX } };
10825 /* Get a pointer to struct dis386 with a valid name. */
10827 static const struct dis386 *
10828 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
10830 int vindex, vex_table_index;
10832 if (dp->name != NULL)
10835 switch (dp->op[0].bytemode)
10837 case USE_REG_TABLE:
10838 dp = ®_table[dp->op[1].bytemode][modrm.reg];
10841 case USE_MOD_TABLE:
10842 vindex = modrm.mod == 0x3 ? 1 : 0;
10843 dp = &mod_table[dp->op[1].bytemode][vindex];
10847 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
10850 case USE_PREFIX_TABLE:
10853 /* The prefix in VEX is implicit. */
10854 switch (vex.prefix)
10859 case REPE_PREFIX_OPCODE:
10862 case DATA_PREFIX_OPCODE:
10865 case REPNE_PREFIX_OPCODE:
10876 used_prefixes |= (prefixes & PREFIX_REPZ);
10877 if (prefixes & PREFIX_REPZ)
10880 all_prefixes[last_repz_prefix] = 0;
10884 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
10886 used_prefixes |= (prefixes & PREFIX_REPNZ);
10887 if (prefixes & PREFIX_REPNZ)
10890 all_prefixes[last_repnz_prefix] = 0;
10894 used_prefixes |= (prefixes & PREFIX_DATA);
10895 if (prefixes & PREFIX_DATA)
10898 all_prefixes[last_data_prefix] = 0;
10903 dp = &prefix_table[dp->op[1].bytemode][vindex];
10906 case USE_X86_64_TABLE:
10907 vindex = address_mode == mode_64bit ? 1 : 0;
10908 dp = &x86_64_table[dp->op[1].bytemode][vindex];
10911 case USE_3BYTE_TABLE:
10912 FETCH_DATA (info, codep + 2);
10914 dp = &three_byte_table[dp->op[1].bytemode][vindex];
10915 modrm.mod = (*codep >> 6) & 3;
10916 modrm.reg = (*codep >> 3) & 7;
10917 modrm.rm = *codep & 7;
10920 case USE_VEX_LEN_TABLE:
10924 switch (vex.length)
10937 dp = &vex_len_table[dp->op[1].bytemode][vindex];
10940 case USE_XOP_8F_TABLE:
10941 FETCH_DATA (info, codep + 3);
10942 /* All bits in the REX prefix are ignored. */
10944 rex = ~(*codep >> 5) & 0x7;
10946 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
10947 switch ((*codep & 0x1f))
10953 vex_table_index = XOP_08;
10956 vex_table_index = XOP_09;
10959 vex_table_index = XOP_0A;
10963 vex.w = *codep & 0x80;
10964 if (vex.w && address_mode == mode_64bit)
10967 vex.register_specifier = (~(*codep >> 3)) & 0xf;
10968 if (address_mode != mode_64bit
10969 && vex.register_specifier > 0x7)
10975 vex.length = (*codep & 0x4) ? 256 : 128;
10976 switch ((*codep & 0x3))
10982 vex.prefix = DATA_PREFIX_OPCODE;
10985 vex.prefix = REPE_PREFIX_OPCODE;
10988 vex.prefix = REPNE_PREFIX_OPCODE;
10995 dp = &xop_table[vex_table_index][vindex];
10997 FETCH_DATA (info, codep + 1);
10998 modrm.mod = (*codep >> 6) & 3;
10999 modrm.reg = (*codep >> 3) & 7;
11000 modrm.rm = *codep & 7;
11003 case USE_VEX_C4_TABLE:
11004 FETCH_DATA (info, codep + 3);
11005 /* All bits in the REX prefix are ignored. */
11007 rex = ~(*codep >> 5) & 0x7;
11008 switch ((*codep & 0x1f))
11014 vex_table_index = VEX_0F;
11017 vex_table_index = VEX_0F38;
11020 vex_table_index = VEX_0F3A;
11024 vex.w = *codep & 0x80;
11025 if (vex.w && address_mode == mode_64bit)
11028 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11029 if (address_mode != mode_64bit
11030 && vex.register_specifier > 0x7)
11036 vex.length = (*codep & 0x4) ? 256 : 128;
11037 switch ((*codep & 0x3))
11043 vex.prefix = DATA_PREFIX_OPCODE;
11046 vex.prefix = REPE_PREFIX_OPCODE;
11049 vex.prefix = REPNE_PREFIX_OPCODE;
11056 dp = &vex_table[vex_table_index][vindex];
11057 /* There is no MODRM byte for VEX [82|77]. */
11058 if (vindex != 0x77 && vindex != 0x82)
11060 FETCH_DATA (info, codep + 1);
11061 modrm.mod = (*codep >> 6) & 3;
11062 modrm.reg = (*codep >> 3) & 7;
11063 modrm.rm = *codep & 7;
11067 case USE_VEX_C5_TABLE:
11068 FETCH_DATA (info, codep + 2);
11069 /* All bits in the REX prefix are ignored. */
11071 rex = (*codep & 0x80) ? 0 : REX_R;
11073 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11074 if (address_mode != mode_64bit
11075 && vex.register_specifier > 0x7)
11083 vex.length = (*codep & 0x4) ? 256 : 128;
11084 switch ((*codep & 0x3))
11090 vex.prefix = DATA_PREFIX_OPCODE;
11093 vex.prefix = REPE_PREFIX_OPCODE;
11096 vex.prefix = REPNE_PREFIX_OPCODE;
11103 dp = &vex_table[dp->op[1].bytemode][vindex];
11104 /* There is no MODRM byte for VEX [82|77]. */
11105 if (vindex != 0x77 && vindex != 0x82)
11107 FETCH_DATA (info, codep + 1);
11108 modrm.mod = (*codep >> 6) & 3;
11109 modrm.reg = (*codep >> 3) & 7;
11110 modrm.rm = *codep & 7;
11114 case USE_VEX_W_TABLE:
11118 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11129 if (dp->name != NULL)
11132 return get_valid_dis386 (dp, info);
11136 get_sib (disassemble_info *info)
11138 /* If modrm.mod == 3, operand must be register. */
11140 && address_mode != mode_16bit
11144 FETCH_DATA (info, codep + 2);
11145 sib.index = (codep [1] >> 3) & 7;
11146 sib.scale = (codep [1] >> 6) & 3;
11147 sib.base = codep [1] & 7;
11152 print_insn (bfd_vma pc, disassemble_info *info)
11154 const struct dis386 *dp;
11156 char *op_txt[MAX_OPERANDS];
11160 struct dis_private priv;
11162 int default_prefixes;
11164 if (info->mach == bfd_mach_x86_64_intel_syntax
11165 || info->mach == bfd_mach_x86_64
11166 || info->mach == bfd_mach_x64_32_intel_syntax
11167 || info->mach == bfd_mach_x64_32
11168 || info->mach == bfd_mach_l1om
11169 || info->mach == bfd_mach_l1om_intel_syntax)
11170 address_mode = mode_64bit;
11172 address_mode = mode_32bit;
11174 if (intel_syntax == (char) -1)
11175 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
11176 || info->mach == bfd_mach_x86_64_intel_syntax
11177 || info->mach == bfd_mach_x64_32_intel_syntax
11178 || info->mach == bfd_mach_l1om_intel_syntax);
11180 if (info->mach == bfd_mach_i386_i386
11181 || info->mach == bfd_mach_x86_64
11182 || info->mach == bfd_mach_x64_32
11183 || info->mach == bfd_mach_l1om
11184 || info->mach == bfd_mach_i386_i386_intel_syntax
11185 || info->mach == bfd_mach_x86_64_intel_syntax
11186 || info->mach == bfd_mach_x64_32_intel_syntax
11187 || info->mach == bfd_mach_l1om_intel_syntax)
11188 priv.orig_sizeflag = AFLAG | DFLAG;
11189 else if (info->mach == bfd_mach_i386_i8086)
11190 priv.orig_sizeflag = 0;
11194 for (p = info->disassembler_options; p != NULL; )
11196 if (CONST_STRNEQ (p, "x86-64"))
11198 address_mode = mode_64bit;
11199 priv.orig_sizeflag = AFLAG | DFLAG;
11201 else if (CONST_STRNEQ (p, "i386"))
11203 address_mode = mode_32bit;
11204 priv.orig_sizeflag = AFLAG | DFLAG;
11206 else if (CONST_STRNEQ (p, "i8086"))
11208 address_mode = mode_16bit;
11209 priv.orig_sizeflag = 0;
11211 else if (CONST_STRNEQ (p, "intel"))
11214 if (CONST_STRNEQ (p + 5, "-mnemonic"))
11215 intel_mnemonic = 1;
11217 else if (CONST_STRNEQ (p, "att"))
11220 if (CONST_STRNEQ (p + 3, "-mnemonic"))
11221 intel_mnemonic = 0;
11223 else if (CONST_STRNEQ (p, "addr"))
11225 if (address_mode == mode_64bit)
11227 if (p[4] == '3' && p[5] == '2')
11228 priv.orig_sizeflag &= ~AFLAG;
11229 else if (p[4] == '6' && p[5] == '4')
11230 priv.orig_sizeflag |= AFLAG;
11234 if (p[4] == '1' && p[5] == '6')
11235 priv.orig_sizeflag &= ~AFLAG;
11236 else if (p[4] == '3' && p[5] == '2')
11237 priv.orig_sizeflag |= AFLAG;
11240 else if (CONST_STRNEQ (p, "data"))
11242 if (p[4] == '1' && p[5] == '6')
11243 priv.orig_sizeflag &= ~DFLAG;
11244 else if (p[4] == '3' && p[5] == '2')
11245 priv.orig_sizeflag |= DFLAG;
11247 else if (CONST_STRNEQ (p, "suffix"))
11248 priv.orig_sizeflag |= SUFFIX_ALWAYS;
11250 p = strchr (p, ',');
11257 names64 = intel_names64;
11258 names32 = intel_names32;
11259 names16 = intel_names16;
11260 names8 = intel_names8;
11261 names8rex = intel_names8rex;
11262 names_seg = intel_names_seg;
11263 names_mm = intel_names_mm;
11264 names_xmm = intel_names_xmm;
11265 names_ymm = intel_names_ymm;
11266 index64 = intel_index64;
11267 index32 = intel_index32;
11268 index16 = intel_index16;
11271 separator_char = '+';
11276 names64 = att_names64;
11277 names32 = att_names32;
11278 names16 = att_names16;
11279 names8 = att_names8;
11280 names8rex = att_names8rex;
11281 names_seg = att_names_seg;
11282 names_mm = att_names_mm;
11283 names_xmm = att_names_xmm;
11284 names_ymm = att_names_ymm;
11285 index64 = att_index64;
11286 index32 = att_index32;
11287 index16 = att_index16;
11290 separator_char = ',';
11294 /* The output looks better if we put 7 bytes on a line, since that
11295 puts most long word instructions on a single line. Use 8 bytes
11297 if (info->mach == bfd_mach_l1om
11298 || info->mach == bfd_mach_l1om_intel_syntax)
11299 info->bytes_per_line = 8;
11301 info->bytes_per_line = 7;
11303 info->private_data = &priv;
11304 priv.max_fetched = priv.the_buffer;
11305 priv.insn_start = pc;
11308 for (i = 0; i < MAX_OPERANDS; ++i)
11316 start_codep = priv.the_buffer;
11317 codep = priv.the_buffer;
11319 if (setjmp (priv.bailout) != 0)
11323 /* Getting here means we tried for data but didn't get it. That
11324 means we have an incomplete instruction of some sort. Just
11325 print the first byte as a prefix or a .byte pseudo-op. */
11326 if (codep > priv.the_buffer)
11328 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11330 (*info->fprintf_func) (info->stream, "%s", name);
11333 /* Just print the first byte as a .byte instruction. */
11334 (*info->fprintf_func) (info->stream, ".byte 0x%x",
11335 (unsigned int) priv.the_buffer[0]);
11345 sizeflag = priv.orig_sizeflag;
11347 if (!ckprefix () || rex_used)
11349 /* Too many prefixes or unused REX prefixes. */
11351 all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes);
11353 (*info->fprintf_func) (info->stream, "%s",
11354 prefix_name (all_prefixes[i], sizeflag));
11358 insn_codep = codep;
11360 FETCH_DATA (info, codep + 1);
11361 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11363 if (((prefixes & PREFIX_FWAIT)
11364 && ((*codep < 0xd8) || (*codep > 0xdf))))
11366 (*info->fprintf_func) (info->stream, "fwait");
11370 if (*codep == 0x0f)
11372 unsigned char threebyte;
11373 FETCH_DATA (info, codep + 2);
11374 threebyte = *++codep;
11375 dp = &dis386_twobyte[threebyte];
11376 need_modrm = twobyte_has_modrm[*codep];
11381 dp = &dis386[*codep];
11382 need_modrm = onebyte_has_modrm[*codep];
11386 if ((prefixes & PREFIX_REPZ))
11387 used_prefixes |= PREFIX_REPZ;
11388 if ((prefixes & PREFIX_REPNZ))
11389 used_prefixes |= PREFIX_REPNZ;
11390 if ((prefixes & PREFIX_LOCK))
11391 used_prefixes |= PREFIX_LOCK;
11393 default_prefixes = 0;
11394 if (prefixes & PREFIX_ADDR)
11397 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
11399 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11400 all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
11402 all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
11403 default_prefixes |= PREFIX_ADDR;
11407 if ((prefixes & PREFIX_DATA))
11410 if (dp->op[2].bytemode == cond_jump_mode
11411 && dp->op[0].bytemode == v_mode
11414 if (sizeflag & DFLAG)
11415 all_prefixes[last_data_prefix] = DATA32_PREFIX;
11417 all_prefixes[last_data_prefix] = DATA16_PREFIX;
11418 default_prefixes |= PREFIX_DATA;
11420 else if (rex & REX_W)
11422 /* REX_W will override PREFIX_DATA. */
11423 default_prefixes |= PREFIX_DATA;
11429 FETCH_DATA (info, codep + 1);
11430 modrm.mod = (*codep >> 6) & 3;
11431 modrm.reg = (*codep >> 3) & 7;
11432 modrm.rm = *codep & 7;
11439 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11442 dofloat (sizeflag);
11446 dp = get_valid_dis386 (dp, info);
11447 if (dp != NULL && putop (dp->name, sizeflag) == 0)
11450 for (i = 0; i < MAX_OPERANDS; ++i)
11453 op_ad = MAX_OPERANDS - 1 - i;
11455 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
11460 /* See if any prefixes were not used. If so, print the first one
11461 separately. If we don't do this, we'll wind up printing an
11462 instruction stream which does not precisely correspond to the
11463 bytes we are disassembling. */
11464 if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
11466 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11467 if (all_prefixes[i])
11470 name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
11472 name = INTERNAL_DISASSEMBLER_ERROR;
11473 (*info->fprintf_func) (info->stream, "%s", name);
11478 /* Check if the REX prefix is used. */
11479 if (rex_ignored == 0 && (rex ^ rex_used) == 0)
11480 all_prefixes[last_rex_prefix] = 0;
11482 /* Check if the SEG prefix is used. */
11483 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
11484 | PREFIX_FS | PREFIX_GS)) != 0
11486 & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
11487 all_prefixes[last_seg_prefix] = 0;
11489 /* Check if the ADDR prefix is used. */
11490 if ((prefixes & PREFIX_ADDR) != 0
11491 && (used_prefixes & PREFIX_ADDR) != 0)
11492 all_prefixes[last_addr_prefix] = 0;
11494 /* Check if the DATA prefix is used. */
11495 if ((prefixes & PREFIX_DATA) != 0
11496 && (used_prefixes & PREFIX_DATA) != 0)
11497 all_prefixes[last_data_prefix] = 0;
11500 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11501 if (all_prefixes[i])
11504 name = prefix_name (all_prefixes[i], sizeflag);
11507 prefix_length += strlen (name) + 1;
11508 (*info->fprintf_func) (info->stream, "%s ", name);
11511 /* Check maximum code length. */
11512 if ((codep - start_codep) > MAX_CODE_LENGTH)
11514 (*info->fprintf_func) (info->stream, "(bad)");
11515 return MAX_CODE_LENGTH;
11518 obufp = mnemonicendp;
11519 for (i = strlen (obuf) + prefix_length; i < 6; i++)
11522 (*info->fprintf_func) (info->stream, "%s", obuf);
11524 /* The enter and bound instructions are printed with operands in the same
11525 order as the intel book; everything else is printed in reverse order. */
11526 if (intel_syntax || two_source_ops)
11530 for (i = 0; i < MAX_OPERANDS; ++i)
11531 op_txt[i] = op_out[i];
11533 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
11535 op_ad = op_index[i];
11536 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
11537 op_index[MAX_OPERANDS - 1 - i] = op_ad;
11538 riprel = op_riprel[i];
11539 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
11540 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
11545 for (i = 0; i < MAX_OPERANDS; ++i)
11546 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
11550 for (i = 0; i < MAX_OPERANDS; ++i)
11554 (*info->fprintf_func) (info->stream, ",");
11555 if (op_index[i] != -1 && !op_riprel[i])
11556 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
11558 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
11562 for (i = 0; i < MAX_OPERANDS; i++)
11563 if (op_index[i] != -1 && op_riprel[i])
11565 (*info->fprintf_func) (info->stream, " # ");
11566 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
11567 + op_address[op_index[i]]), info);
11570 return codep - priv.the_buffer;
11573 static const char *float_mem[] = {
11648 static const unsigned char float_mem_mode[] = {
11723 #define ST { OP_ST, 0 }
11724 #define STi { OP_STi, 0 }
11726 #define FGRPd9_2 NULL, { { NULL, 0 } }
11727 #define FGRPd9_4 NULL, { { NULL, 1 } }
11728 #define FGRPd9_5 NULL, { { NULL, 2 } }
11729 #define FGRPd9_6 NULL, { { NULL, 3 } }
11730 #define FGRPd9_7 NULL, { { NULL, 4 } }
11731 #define FGRPda_5 NULL, { { NULL, 5 } }
11732 #define FGRPdb_4 NULL, { { NULL, 6 } }
11733 #define FGRPde_3 NULL, { { NULL, 7 } }
11734 #define FGRPdf_4 NULL, { { NULL, 8 } }
11736 static const struct dis386 float_reg[][8] = {
11739 { "fadd", { ST, STi } },
11740 { "fmul", { ST, STi } },
11741 { "fcom", { STi } },
11742 { "fcomp", { STi } },
11743 { "fsub", { ST, STi } },
11744 { "fsubr", { ST, STi } },
11745 { "fdiv", { ST, STi } },
11746 { "fdivr", { ST, STi } },
11750 { "fld", { STi } },
11751 { "fxch", { STi } },
11761 { "fcmovb", { ST, STi } },
11762 { "fcmove", { ST, STi } },
11763 { "fcmovbe",{ ST, STi } },
11764 { "fcmovu", { ST, STi } },
11772 { "fcmovnb",{ ST, STi } },
11773 { "fcmovne",{ ST, STi } },
11774 { "fcmovnbe",{ ST, STi } },
11775 { "fcmovnu",{ ST, STi } },
11777 { "fucomi", { ST, STi } },
11778 { "fcomi", { ST, STi } },
11783 { "fadd", { STi, ST } },
11784 { "fmul", { STi, ST } },
11787 { "fsub!M", { STi, ST } },
11788 { "fsubM", { STi, ST } },
11789 { "fdiv!M", { STi, ST } },
11790 { "fdivM", { STi, ST } },
11794 { "ffree", { STi } },
11796 { "fst", { STi } },
11797 { "fstp", { STi } },
11798 { "fucom", { STi } },
11799 { "fucomp", { STi } },
11805 { "faddp", { STi, ST } },
11806 { "fmulp", { STi, ST } },
11809 { "fsub!Mp", { STi, ST } },
11810 { "fsubMp", { STi, ST } },
11811 { "fdiv!Mp", { STi, ST } },
11812 { "fdivMp", { STi, ST } },
11816 { "ffreep", { STi } },
11821 { "fucomip", { ST, STi } },
11822 { "fcomip", { ST, STi } },
11827 static char *fgrps[][8] = {
11830 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11835 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
11840 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
11845 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
11850 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
11855 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11860 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
11861 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
11866 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11871 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11876 swap_operand (void)
11878 mnemonicendp[0] = '.';
11879 mnemonicendp[1] = 's';
11884 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
11885 int sizeflag ATTRIBUTE_UNUSED)
11887 /* Skip mod/rm byte. */
11893 dofloat (int sizeflag)
11895 const struct dis386 *dp;
11896 unsigned char floatop;
11898 floatop = codep[-1];
11900 if (modrm.mod != 3)
11902 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
11904 putop (float_mem[fp_indx], sizeflag);
11907 OP_E (float_mem_mode[fp_indx], sizeflag);
11910 /* Skip mod/rm byte. */
11914 dp = &float_reg[floatop - 0xd8][modrm.reg];
11915 if (dp->name == NULL)
11917 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
11919 /* Instruction fnstsw is only one with strange arg. */
11920 if (floatop == 0xdf && codep[-1] == 0xe0)
11921 strcpy (op_out[0], names16[0]);
11925 putop (dp->name, sizeflag);
11930 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
11935 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
11940 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11942 oappend ("%st" + intel_syntax);
11946 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11948 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
11949 oappend (scratchbuf + intel_syntax);
11952 /* Capital letters in template are macros. */
11954 putop (const char *in_template, int sizeflag)
11959 unsigned int l = 0, len = 1;
11962 #define SAVE_LAST(c) \
11963 if (l < len && l < sizeof (last)) \
11968 for (p = in_template; *p; p++)
11985 while (*++p != '|')
11986 if (*p == '}' || *p == '\0')
11989 /* Fall through. */
11994 while (*++p != '}')
12005 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12009 if (l == 0 && len == 1)
12014 if (sizeflag & SUFFIX_ALWAYS)
12027 if (address_mode == mode_64bit
12028 && !(prefixes & PREFIX_ADDR))
12039 if (intel_syntax && !alt)
12041 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12043 if (sizeflag & DFLAG)
12044 *obufp++ = intel_syntax ? 'd' : 'l';
12046 *obufp++ = intel_syntax ? 'w' : 's';
12047 used_prefixes |= (prefixes & PREFIX_DATA);
12051 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12054 if (modrm.mod == 3)
12060 if (sizeflag & DFLAG)
12061 *obufp++ = intel_syntax ? 'd' : 'l';
12064 used_prefixes |= (prefixes & PREFIX_DATA);
12070 case 'E': /* For jcxz/jecxz */
12071 if (address_mode == mode_64bit)
12073 if (sizeflag & AFLAG)
12079 if (sizeflag & AFLAG)
12081 used_prefixes |= (prefixes & PREFIX_ADDR);
12086 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12088 if (sizeflag & AFLAG)
12089 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12091 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12092 used_prefixes |= (prefixes & PREFIX_ADDR);
12096 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12098 if ((rex & REX_W) || (sizeflag & DFLAG))
12102 if (!(rex & REX_W))
12103 used_prefixes |= (prefixes & PREFIX_DATA);
12108 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12109 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12111 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12114 if (prefixes & PREFIX_DS)
12135 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12140 /* Fall through. */
12143 if (l != 0 || len != 1)
12151 if (sizeflag & SUFFIX_ALWAYS)
12155 if (intel_mnemonic != cond)
12159 if ((prefixes & PREFIX_FWAIT) == 0)
12162 used_prefixes |= PREFIX_FWAIT;
12168 else if (intel_syntax && (sizeflag & DFLAG))
12172 if (!(rex & REX_W))
12173 used_prefixes |= (prefixes & PREFIX_DATA);
12177 && address_mode == mode_64bit
12178 && (sizeflag & DFLAG))
12183 /* Fall through. */
12187 if ((rex & REX_W) == 0
12188 && (prefixes & PREFIX_DATA))
12190 if ((sizeflag & DFLAG) == 0)
12192 used_prefixes |= (prefixes & PREFIX_DATA);
12196 if ((prefixes & PREFIX_DATA)
12198 || (sizeflag & SUFFIX_ALWAYS))
12205 if (sizeflag & DFLAG)
12209 used_prefixes |= (prefixes & PREFIX_DATA);
12216 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12218 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12222 /* Fall through. */
12225 if (l == 0 && len == 1)
12228 if (intel_syntax && !alt)
12231 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12237 if (sizeflag & DFLAG)
12238 *obufp++ = intel_syntax ? 'd' : 'l';
12241 used_prefixes |= (prefixes & PREFIX_DATA);
12247 if (l != 1 || len != 2 || last[0] != 'L')
12253 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12268 else if (sizeflag & DFLAG)
12277 if (intel_syntax && !p[1]
12278 && ((rex & REX_W) || (sizeflag & DFLAG)))
12280 if (!(rex & REX_W))
12281 used_prefixes |= (prefixes & PREFIX_DATA);
12284 if (l == 0 && len == 1)
12288 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12290 if (sizeflag & SUFFIX_ALWAYS)
12312 /* Fall through. */
12315 if (l == 0 && len == 1)
12320 if (sizeflag & SUFFIX_ALWAYS)
12326 if (sizeflag & DFLAG)
12330 used_prefixes |= (prefixes & PREFIX_DATA);
12344 if (address_mode == mode_64bit
12345 && !(prefixes & PREFIX_ADDR))
12356 if (l != 0 || len != 1)
12361 if (need_vex && vex.prefix)
12363 if (vex.prefix == DATA_PREFIX_OPCODE)
12370 if (prefixes & PREFIX_DATA)
12374 used_prefixes |= (prefixes & PREFIX_DATA);
12378 if (l == 0 && len == 1)
12380 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12391 if (l != 1 || len != 2 || last[0] != 'X')
12399 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12401 switch (vex.length)
12415 if (l == 0 && len == 1)
12417 /* operand size flag for cwtl, cbtw */
12426 else if (sizeflag & DFLAG)
12430 if (!(rex & REX_W))
12431 used_prefixes |= (prefixes & PREFIX_DATA);
12438 && last[0] != 'L'))
12445 if (last[0] == 'X')
12446 *obufp++ = vex.w ? 'd': 's';
12448 *obufp++ = vex.w ? 'q': 'd';
12455 mnemonicendp = obufp;
12460 oappend (const char *s)
12462 obufp = stpcpy (obufp, s);
12468 if (prefixes & PREFIX_CS)
12470 used_prefixes |= PREFIX_CS;
12471 oappend ("%cs:" + intel_syntax);
12473 if (prefixes & PREFIX_DS)
12475 used_prefixes |= PREFIX_DS;
12476 oappend ("%ds:" + intel_syntax);
12478 if (prefixes & PREFIX_SS)
12480 used_prefixes |= PREFIX_SS;
12481 oappend ("%ss:" + intel_syntax);
12483 if (prefixes & PREFIX_ES)
12485 used_prefixes |= PREFIX_ES;
12486 oappend ("%es:" + intel_syntax);
12488 if (prefixes & PREFIX_FS)
12490 used_prefixes |= PREFIX_FS;
12491 oappend ("%fs:" + intel_syntax);
12493 if (prefixes & PREFIX_GS)
12495 used_prefixes |= PREFIX_GS;
12496 oappend ("%gs:" + intel_syntax);
12501 OP_indirE (int bytemode, int sizeflag)
12505 OP_E (bytemode, sizeflag);
12509 print_operand_value (char *buf, int hex, bfd_vma disp)
12511 if (address_mode == mode_64bit)
12519 sprintf_vma (tmp, disp);
12520 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
12521 strcpy (buf + 2, tmp + i);
12525 bfd_signed_vma v = disp;
12532 /* Check for possible overflow on 0x8000000000000000. */
12535 strcpy (buf, "9223372036854775808");
12549 tmp[28 - i] = (v % 10) + '0';
12553 strcpy (buf, tmp + 29 - i);
12559 sprintf (buf, "0x%x", (unsigned int) disp);
12561 sprintf (buf, "%d", (int) disp);
12565 /* Put DISP in BUF as signed hex number. */
12568 print_displacement (char *buf, bfd_vma disp)
12570 bfd_signed_vma val = disp;
12579 /* Check for possible overflow. */
12582 switch (address_mode)
12585 strcpy (buf + j, "0x8000000000000000");
12588 strcpy (buf + j, "0x80000000");
12591 strcpy (buf + j, "0x8000");
12601 sprintf_vma (tmp, (bfd_vma) val);
12602 for (i = 0; tmp[i] == '0'; i++)
12604 if (tmp[i] == '\0')
12606 strcpy (buf + j, tmp + i);
12610 intel_operand_size (int bytemode, int sizeflag)
12617 oappend ("BYTE PTR ");
12621 oappend ("WORD PTR ");
12624 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12626 oappend ("QWORD PTR ");
12635 oappend ("QWORD PTR ");
12638 if ((sizeflag & DFLAG) || bytemode == dq_mode)
12639 oappend ("DWORD PTR ");
12641 oappend ("WORD PTR ");
12642 used_prefixes |= (prefixes & PREFIX_DATA);
12646 if ((rex & REX_W) || (sizeflag & DFLAG))
12648 oappend ("WORD PTR ");
12649 if (!(rex & REX_W))
12650 used_prefixes |= (prefixes & PREFIX_DATA);
12653 if (sizeflag & DFLAG)
12654 oappend ("QWORD PTR ");
12656 oappend ("DWORD PTR ");
12657 used_prefixes |= (prefixes & PREFIX_DATA);
12660 case d_scalar_mode:
12661 case d_scalar_swap_mode:
12664 oappend ("DWORD PTR ");
12667 case q_scalar_mode:
12668 case q_scalar_swap_mode:
12670 oappend ("QWORD PTR ");
12673 if (address_mode == mode_64bit)
12674 oappend ("QWORD PTR ");
12676 oappend ("DWORD PTR ");
12679 if (sizeflag & DFLAG)
12680 oappend ("FWORD PTR ");
12682 oappend ("DWORD PTR ");
12683 used_prefixes |= (prefixes & PREFIX_DATA);
12686 oappend ("TBYTE PTR ");
12692 switch (vex.length)
12695 oappend ("XMMWORD PTR ");
12698 oappend ("YMMWORD PTR ");
12705 oappend ("XMMWORD PTR ");
12708 oappend ("XMMWORD PTR ");
12714 switch (vex.length)
12717 oappend ("QWORD PTR ");
12720 oappend ("XMMWORD PTR ");
12730 switch (vex.length)
12734 oappend ("BYTE PTR ");
12744 switch (vex.length)
12748 oappend ("WORD PTR ");
12758 switch (vex.length)
12762 oappend ("DWORD PTR ");
12772 switch (vex.length)
12776 oappend ("QWORD PTR ");
12786 switch (vex.length)
12789 oappend ("WORD PTR ");
12792 oappend ("DWORD PTR ");
12802 switch (vex.length)
12805 oappend ("DWORD PTR ");
12808 oappend ("QWORD PTR ");
12818 switch (vex.length)
12821 oappend ("QWORD PTR ");
12824 oappend ("YMMWORD PTR ");
12834 switch (vex.length)
12838 oappend ("XMMWORD PTR ");
12845 oappend ("OWORD PTR ");
12847 case vex_w_dq_mode:
12848 case vex_scalar_w_dq_mode:
12849 case vex_vsib_d_w_dq_mode:
12850 case vex_vsib_q_w_dq_mode:
12855 oappend ("QWORD PTR ");
12857 oappend ("DWORD PTR ");
12865 OP_E_register (int bytemode, int sizeflag)
12867 int reg = modrm.rm;
12868 const char **names;
12874 if ((sizeflag & SUFFIX_ALWAYS)
12875 && (bytemode == b_swap_mode || bytemode == v_swap_mode))
12898 names = address_mode == mode_64bit ? names64 : names32;
12901 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12919 if ((sizeflag & DFLAG)
12920 || (bytemode != v_mode
12921 && bytemode != v_swap_mode))
12925 used_prefixes |= (prefixes & PREFIX_DATA);
12931 oappend (INTERNAL_DISASSEMBLER_ERROR);
12934 oappend (names[reg]);
12938 OP_E_memory (int bytemode, int sizeflag)
12941 int add = (rex & REX_B) ? 8 : 0;
12946 intel_operand_size (bytemode, sizeflag);
12949 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12951 /* 32/64 bit address mode */
12960 const char **indexes64 = names64;
12961 const char **indexes32 = names32;
12971 vindex = sib.index;
12977 case vex_vsib_d_w_dq_mode:
12978 case vex_vsib_q_w_dq_mode:
12983 switch (vex.length)
12986 indexes64 = indexes32 = names_xmm;
12989 if (!vex.w || bytemode == vex_vsib_q_w_dq_mode)
12990 indexes64 = indexes32 = names_ymm;
12992 indexes64 = indexes32 = names_xmm;
12999 haveindex = vindex != 4;
13006 rbase = base + add;
13014 if (address_mode == mode_64bit && !havesib)
13020 FETCH_DATA (the_info, codep + 1);
13022 if ((disp & 0x80) != 0)
13030 /* In 32bit mode, we need index register to tell [offset] from
13031 [eiz*1 + offset]. */
13032 needindex = (havesib
13035 && address_mode == mode_32bit);
13036 havedisp = (havebase
13038 || (havesib && (haveindex || scale != 0)));
13041 if (modrm.mod != 0 || base == 5)
13043 if (havedisp || riprel)
13044 print_displacement (scratchbuf, disp);
13046 print_operand_value (scratchbuf, 1, disp);
13047 oappend (scratchbuf);
13051 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
13055 if (havebase || haveindex || riprel)
13056 used_prefixes |= PREFIX_ADDR;
13058 if (havedisp || (intel_syntax && riprel))
13060 *obufp++ = open_char;
13061 if (intel_syntax && riprel)
13064 oappend (sizeflag & AFLAG ? "rip" : "eip");
13068 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
13069 ? names64[rbase] : names32[rbase]);
13072 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
13073 print index to tell base + index from base. */
13077 || (havebase && base != ESP_REG_NUM))
13079 if (!intel_syntax || havebase)
13081 *obufp++ = separator_char;
13085 oappend (address_mode == mode_64bit
13086 && (sizeflag & AFLAG)
13087 ? indexes64[vindex] : indexes32[vindex]);
13089 oappend (address_mode == mode_64bit
13090 && (sizeflag & AFLAG)
13091 ? index64 : index32);
13093 *obufp++ = scale_char;
13095 sprintf (scratchbuf, "%d", 1 << scale);
13096 oappend (scratchbuf);
13100 && (disp || modrm.mod != 0 || base == 5))
13102 if (!havedisp || (bfd_signed_vma) disp >= 0)
13107 else if (modrm.mod != 1 && disp != -disp)
13111 disp = - (bfd_signed_vma) disp;
13115 print_displacement (scratchbuf, disp);
13117 print_operand_value (scratchbuf, 1, disp);
13118 oappend (scratchbuf);
13121 *obufp++ = close_char;
13124 else if (intel_syntax)
13126 if (modrm.mod != 0 || base == 5)
13128 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13129 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13133 oappend (names_seg[ds_reg - es_reg]);
13136 print_operand_value (scratchbuf, 1, disp);
13137 oappend (scratchbuf);
13143 /* 16 bit address mode */
13144 used_prefixes |= prefixes & PREFIX_ADDR;
13151 if ((disp & 0x8000) != 0)
13156 FETCH_DATA (the_info, codep + 1);
13158 if ((disp & 0x80) != 0)
13163 if ((disp & 0x8000) != 0)
13169 if (modrm.mod != 0 || modrm.rm == 6)
13171 print_displacement (scratchbuf, disp);
13172 oappend (scratchbuf);
13175 if (modrm.mod != 0 || modrm.rm != 6)
13177 *obufp++ = open_char;
13179 oappend (index16[modrm.rm]);
13181 && (disp || modrm.mod != 0 || modrm.rm == 6))
13183 if ((bfd_signed_vma) disp >= 0)
13188 else if (modrm.mod != 1)
13192 disp = - (bfd_signed_vma) disp;
13195 print_displacement (scratchbuf, disp);
13196 oappend (scratchbuf);
13199 *obufp++ = close_char;
13202 else if (intel_syntax)
13204 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13205 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13209 oappend (names_seg[ds_reg - es_reg]);
13212 print_operand_value (scratchbuf, 1, disp & 0xffff);
13213 oappend (scratchbuf);
13219 OP_E (int bytemode, int sizeflag)
13221 /* Skip mod/rm byte. */
13225 if (modrm.mod == 3)
13226 OP_E_register (bytemode, sizeflag);
13228 OP_E_memory (bytemode, sizeflag);
13232 OP_G (int bytemode, int sizeflag)
13243 oappend (names8rex[modrm.reg + add]);
13245 oappend (names8[modrm.reg + add]);
13248 oappend (names16[modrm.reg + add]);
13251 oappend (names32[modrm.reg + add]);
13254 oappend (names64[modrm.reg + add]);
13263 oappend (names64[modrm.reg + add]);
13266 if ((sizeflag & DFLAG) || bytemode != v_mode)
13267 oappend (names32[modrm.reg + add]);
13269 oappend (names16[modrm.reg + add]);
13270 used_prefixes |= (prefixes & PREFIX_DATA);
13274 if (address_mode == mode_64bit)
13275 oappend (names64[modrm.reg + add]);
13277 oappend (names32[modrm.reg + add]);
13280 oappend (INTERNAL_DISASSEMBLER_ERROR);
13293 FETCH_DATA (the_info, codep + 8);
13294 a = *codep++ & 0xff;
13295 a |= (*codep++ & 0xff) << 8;
13296 a |= (*codep++ & 0xff) << 16;
13297 a |= (*codep++ & 0xff) << 24;
13298 b = *codep++ & 0xff;
13299 b |= (*codep++ & 0xff) << 8;
13300 b |= (*codep++ & 0xff) << 16;
13301 b |= (*codep++ & 0xff) << 24;
13302 x = a + ((bfd_vma) b << 32);
13310 static bfd_signed_vma
13313 bfd_signed_vma x = 0;
13315 FETCH_DATA (the_info, codep + 4);
13316 x = *codep++ & (bfd_signed_vma) 0xff;
13317 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13318 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13319 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13323 static bfd_signed_vma
13326 bfd_signed_vma x = 0;
13328 FETCH_DATA (the_info, codep + 4);
13329 x = *codep++ & (bfd_signed_vma) 0xff;
13330 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13331 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13332 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13334 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
13344 FETCH_DATA (the_info, codep + 2);
13345 x = *codep++ & 0xff;
13346 x |= (*codep++ & 0xff) << 8;
13351 set_op (bfd_vma op, int riprel)
13353 op_index[op_ad] = op_ad;
13354 if (address_mode == mode_64bit)
13356 op_address[op_ad] = op;
13357 op_riprel[op_ad] = riprel;
13361 /* Mask to get a 32-bit address. */
13362 op_address[op_ad] = op & 0xffffffff;
13363 op_riprel[op_ad] = riprel & 0xffffffff;
13368 OP_REG (int code, int sizeflag)
13380 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13381 case sp_reg: case bp_reg: case si_reg: case di_reg:
13382 s = names16[code - ax_reg + add];
13384 case es_reg: case ss_reg: case cs_reg:
13385 case ds_reg: case fs_reg: case gs_reg:
13386 s = names_seg[code - es_reg + add];
13388 case al_reg: case ah_reg: case cl_reg: case ch_reg:
13389 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13392 s = names8rex[code - al_reg + add];
13394 s = names8[code - al_reg];
13396 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
13397 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
13398 if (address_mode == mode_64bit && (sizeflag & DFLAG))
13400 s = names64[code - rAX_reg + add];
13403 code += eAX_reg - rAX_reg;
13404 /* Fall through. */
13405 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13406 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13409 s = names64[code - eAX_reg + add];
13412 if (sizeflag & DFLAG)
13413 s = names32[code - eAX_reg + add];
13415 s = names16[code - eAX_reg + add];
13416 used_prefixes |= (prefixes & PREFIX_DATA);
13420 s = INTERNAL_DISASSEMBLER_ERROR;
13427 OP_IMREG (int code, int sizeflag)
13439 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13440 case sp_reg: case bp_reg: case si_reg: case di_reg:
13441 s = names16[code - ax_reg];
13443 case es_reg: case ss_reg: case cs_reg:
13444 case ds_reg: case fs_reg: case gs_reg:
13445 s = names_seg[code - es_reg];
13447 case al_reg: case ah_reg: case cl_reg: case ch_reg:
13448 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13451 s = names8rex[code - al_reg];
13453 s = names8[code - al_reg];
13455 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13456 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13459 s = names64[code - eAX_reg];
13462 if (sizeflag & DFLAG)
13463 s = names32[code - eAX_reg];
13465 s = names16[code - eAX_reg];
13466 used_prefixes |= (prefixes & PREFIX_DATA);
13469 case z_mode_ax_reg:
13470 if ((rex & REX_W) || (sizeflag & DFLAG))
13474 if (!(rex & REX_W))
13475 used_prefixes |= (prefixes & PREFIX_DATA);
13478 s = INTERNAL_DISASSEMBLER_ERROR;
13485 OP_I (int bytemode, int sizeflag)
13488 bfd_signed_vma mask = -1;
13493 FETCH_DATA (the_info, codep + 1);
13498 if (address_mode == mode_64bit)
13503 /* Fall through. */
13510 if (sizeflag & DFLAG)
13520 used_prefixes |= (prefixes & PREFIX_DATA);
13532 oappend (INTERNAL_DISASSEMBLER_ERROR);
13537 scratchbuf[0] = '$';
13538 print_operand_value (scratchbuf + 1, 1, op);
13539 oappend (scratchbuf + intel_syntax);
13540 scratchbuf[0] = '\0';
13544 OP_I64 (int bytemode, int sizeflag)
13547 bfd_signed_vma mask = -1;
13549 if (address_mode != mode_64bit)
13551 OP_I (bytemode, sizeflag);
13558 FETCH_DATA (the_info, codep + 1);
13568 if (sizeflag & DFLAG)
13578 used_prefixes |= (prefixes & PREFIX_DATA);
13586 oappend (INTERNAL_DISASSEMBLER_ERROR);
13591 scratchbuf[0] = '$';
13592 print_operand_value (scratchbuf + 1, 1, op);
13593 oappend (scratchbuf + intel_syntax);
13594 scratchbuf[0] = '\0';
13598 OP_sI (int bytemode, int sizeflag)
13606 FETCH_DATA (the_info, codep + 1);
13608 if ((op & 0x80) != 0)
13610 if (bytemode == b_T_mode)
13612 if (address_mode != mode_64bit
13613 || !(sizeflag & DFLAG))
13615 if (sizeflag & DFLAG)
13623 if (!(rex & REX_W))
13625 if (sizeflag & DFLAG)
13633 if (sizeflag & DFLAG)
13639 oappend (INTERNAL_DISASSEMBLER_ERROR);
13643 scratchbuf[0] = '$';
13644 print_operand_value (scratchbuf + 1, 1, op);
13645 oappend (scratchbuf + intel_syntax);
13649 OP_J (int bytemode, int sizeflag)
13653 bfd_vma segment = 0;
13658 FETCH_DATA (the_info, codep + 1);
13660 if ((disp & 0x80) != 0)
13665 if ((sizeflag & DFLAG) || (rex & REX_W))
13670 if ((disp & 0x8000) != 0)
13672 /* In 16bit mode, address is wrapped around at 64k within
13673 the same segment. Otherwise, a data16 prefix on a jump
13674 instruction means that the pc is masked to 16 bits after
13675 the displacement is added! */
13677 if ((prefixes & PREFIX_DATA) == 0)
13678 segment = ((start_pc + codep - start_codep)
13679 & ~((bfd_vma) 0xffff));
13681 if (!(rex & REX_W))
13682 used_prefixes |= (prefixes & PREFIX_DATA);
13685 oappend (INTERNAL_DISASSEMBLER_ERROR);
13688 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
13690 print_operand_value (scratchbuf, 1, disp);
13691 oappend (scratchbuf);
13695 OP_SEG (int bytemode, int sizeflag)
13697 if (bytemode == w_mode)
13698 oappend (names_seg[modrm.reg]);
13700 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
13704 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
13708 if (sizeflag & DFLAG)
13718 used_prefixes |= (prefixes & PREFIX_DATA);
13720 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
13722 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
13723 oappend (scratchbuf);
13727 OP_OFF (int bytemode, int sizeflag)
13731 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13732 intel_operand_size (bytemode, sizeflag);
13735 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13742 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13743 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13745 oappend (names_seg[ds_reg - es_reg]);
13749 print_operand_value (scratchbuf, 1, off);
13750 oappend (scratchbuf);
13754 OP_OFF64 (int bytemode, int sizeflag)
13758 if (address_mode != mode_64bit
13759 || (prefixes & PREFIX_ADDR))
13761 OP_OFF (bytemode, sizeflag);
13765 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13766 intel_operand_size (bytemode, sizeflag);
13773 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13774 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13776 oappend (names_seg[ds_reg - es_reg]);
13780 print_operand_value (scratchbuf, 1, off);
13781 oappend (scratchbuf);
13785 ptr_reg (int code, int sizeflag)
13789 *obufp++ = open_char;
13790 used_prefixes |= (prefixes & PREFIX_ADDR);
13791 if (address_mode == mode_64bit)
13793 if (!(sizeflag & AFLAG))
13794 s = names32[code - eAX_reg];
13796 s = names64[code - eAX_reg];
13798 else if (sizeflag & AFLAG)
13799 s = names32[code - eAX_reg];
13801 s = names16[code - eAX_reg];
13803 *obufp++ = close_char;
13808 OP_ESreg (int code, int sizeflag)
13814 case 0x6d: /* insw/insl */
13815 intel_operand_size (z_mode, sizeflag);
13817 case 0xa5: /* movsw/movsl/movsq */
13818 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13819 case 0xab: /* stosw/stosl */
13820 case 0xaf: /* scasw/scasl */
13821 intel_operand_size (v_mode, sizeflag);
13824 intel_operand_size (b_mode, sizeflag);
13827 oappend ("%es:" + intel_syntax);
13828 ptr_reg (code, sizeflag);
13832 OP_DSreg (int code, int sizeflag)
13838 case 0x6f: /* outsw/outsl */
13839 intel_operand_size (z_mode, sizeflag);
13841 case 0xa5: /* movsw/movsl/movsq */
13842 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13843 case 0xad: /* lodsw/lodsl/lodsq */
13844 intel_operand_size (v_mode, sizeflag);
13847 intel_operand_size (b_mode, sizeflag);
13856 | PREFIX_GS)) == 0)
13857 prefixes |= PREFIX_DS;
13859 ptr_reg (code, sizeflag);
13863 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13871 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
13873 all_prefixes[last_lock_prefix] = 0;
13874 used_prefixes |= PREFIX_LOCK;
13879 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
13880 oappend (scratchbuf + intel_syntax);
13884 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13893 sprintf (scratchbuf, "db%d", modrm.reg + add);
13895 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
13896 oappend (scratchbuf);
13900 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13902 sprintf (scratchbuf, "%%tr%d", modrm.reg);
13903 oappend (scratchbuf + intel_syntax);
13907 OP_R (int bytemode, int sizeflag)
13909 if (modrm.mod == 3)
13910 OP_E (bytemode, sizeflag);
13916 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13918 int reg = modrm.reg;
13919 const char **names;
13921 used_prefixes |= (prefixes & PREFIX_DATA);
13922 if (prefixes & PREFIX_DATA)
13931 oappend (names[reg]);
13935 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13937 int reg = modrm.reg;
13938 const char **names;
13944 && bytemode != xmm_mode
13945 && bytemode != scalar_mode)
13947 switch (vex.length)
13953 if (vex.w || bytemode != vex_vsib_q_w_dq_mode)
13964 oappend (names[reg]);
13968 OP_EM (int bytemode, int sizeflag)
13971 const char **names;
13973 if (modrm.mod != 3)
13976 && (bytemode == v_mode || bytemode == v_swap_mode))
13978 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13979 used_prefixes |= (prefixes & PREFIX_DATA);
13981 OP_E (bytemode, sizeflag);
13985 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13988 /* Skip mod/rm byte. */
13991 used_prefixes |= (prefixes & PREFIX_DATA);
13993 if (prefixes & PREFIX_DATA)
14002 oappend (names[reg]);
14005 /* cvt* are the only instructions in sse2 which have
14006 both SSE and MMX operands and also have 0x66 prefix
14007 in their opcode. 0x66 was originally used to differentiate
14008 between SSE and MMX instruction(operands). So we have to handle the
14009 cvt* separately using OP_EMC and OP_MXC */
14011 OP_EMC (int bytemode, int sizeflag)
14013 if (modrm.mod != 3)
14015 if (intel_syntax && bytemode == v_mode)
14017 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14018 used_prefixes |= (prefixes & PREFIX_DATA);
14020 OP_E (bytemode, sizeflag);
14024 /* Skip mod/rm byte. */
14027 used_prefixes |= (prefixes & PREFIX_DATA);
14028 oappend (names_mm[modrm.rm]);
14032 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14034 used_prefixes |= (prefixes & PREFIX_DATA);
14035 oappend (names_mm[modrm.reg]);
14039 OP_EX (int bytemode, int sizeflag)
14042 const char **names;
14044 /* Skip mod/rm byte. */
14048 if (modrm.mod != 3)
14050 OP_E_memory (bytemode, sizeflag);
14059 if ((sizeflag & SUFFIX_ALWAYS)
14060 && (bytemode == x_swap_mode
14061 || bytemode == d_swap_mode
14062 || bytemode == d_scalar_swap_mode
14063 || bytemode == q_swap_mode
14064 || bytemode == q_scalar_swap_mode))
14068 && bytemode != xmm_mode
14069 && bytemode != xmmdw_mode
14070 && bytemode != xmmqd_mode
14071 && bytemode != xmm_mb_mode
14072 && bytemode != xmm_mw_mode
14073 && bytemode != xmm_md_mode
14074 && bytemode != xmm_mq_mode
14075 && bytemode != xmmq_mode
14076 && bytemode != d_scalar_mode
14077 && bytemode != d_scalar_swap_mode
14078 && bytemode != q_scalar_mode
14079 && bytemode != q_scalar_swap_mode
14080 && bytemode != vex_scalar_w_dq_mode)
14082 switch (vex.length)
14096 oappend (names[reg]);
14100 OP_MS (int bytemode, int sizeflag)
14102 if (modrm.mod == 3)
14103 OP_EM (bytemode, sizeflag);
14109 OP_XS (int bytemode, int sizeflag)
14111 if (modrm.mod == 3)
14112 OP_EX (bytemode, sizeflag);
14118 OP_M (int bytemode, int sizeflag)
14120 if (modrm.mod == 3)
14121 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14124 OP_E (bytemode, sizeflag);
14128 OP_0f07 (int bytemode, int sizeflag)
14130 if (modrm.mod != 3 || modrm.rm != 0)
14133 OP_E (bytemode, sizeflag);
14136 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
14137 32bit mode and "xchg %rax,%rax" in 64bit mode. */
14140 NOP_Fixup1 (int bytemode, int sizeflag)
14142 if ((prefixes & PREFIX_DATA) != 0
14145 && address_mode == mode_64bit))
14146 OP_REG (bytemode, sizeflag);
14148 strcpy (obuf, "nop");
14152 NOP_Fixup2 (int bytemode, int sizeflag)
14154 if ((prefixes & PREFIX_DATA) != 0
14157 && address_mode == mode_64bit))
14158 OP_IMREG (bytemode, sizeflag);
14161 static const char *const Suffix3DNow[] = {
14162 /* 00 */ NULL, NULL, NULL, NULL,
14163 /* 04 */ NULL, NULL, NULL, NULL,
14164 /* 08 */ NULL, NULL, NULL, NULL,
14165 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
14166 /* 10 */ NULL, NULL, NULL, NULL,
14167 /* 14 */ NULL, NULL, NULL, NULL,
14168 /* 18 */ NULL, NULL, NULL, NULL,
14169 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
14170 /* 20 */ NULL, NULL, NULL, NULL,
14171 /* 24 */ NULL, NULL, NULL, NULL,
14172 /* 28 */ NULL, NULL, NULL, NULL,
14173 /* 2C */ NULL, NULL, NULL, NULL,
14174 /* 30 */ NULL, NULL, NULL, NULL,
14175 /* 34 */ NULL, NULL, NULL, NULL,
14176 /* 38 */ NULL, NULL, NULL, NULL,
14177 /* 3C */ NULL, NULL, NULL, NULL,
14178 /* 40 */ NULL, NULL, NULL, NULL,
14179 /* 44 */ NULL, NULL, NULL, NULL,
14180 /* 48 */ NULL, NULL, NULL, NULL,
14181 /* 4C */ NULL, NULL, NULL, NULL,
14182 /* 50 */ NULL, NULL, NULL, NULL,
14183 /* 54 */ NULL, NULL, NULL, NULL,
14184 /* 58 */ NULL, NULL, NULL, NULL,
14185 /* 5C */ NULL, NULL, NULL, NULL,
14186 /* 60 */ NULL, NULL, NULL, NULL,
14187 /* 64 */ NULL, NULL, NULL, NULL,
14188 /* 68 */ NULL, NULL, NULL, NULL,
14189 /* 6C */ NULL, NULL, NULL, NULL,
14190 /* 70 */ NULL, NULL, NULL, NULL,
14191 /* 74 */ NULL, NULL, NULL, NULL,
14192 /* 78 */ NULL, NULL, NULL, NULL,
14193 /* 7C */ NULL, NULL, NULL, NULL,
14194 /* 80 */ NULL, NULL, NULL, NULL,
14195 /* 84 */ NULL, NULL, NULL, NULL,
14196 /* 88 */ NULL, NULL, "pfnacc", NULL,
14197 /* 8C */ NULL, NULL, "pfpnacc", NULL,
14198 /* 90 */ "pfcmpge", NULL, NULL, NULL,
14199 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
14200 /* 98 */ NULL, NULL, "pfsub", NULL,
14201 /* 9C */ NULL, NULL, "pfadd", NULL,
14202 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
14203 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
14204 /* A8 */ NULL, NULL, "pfsubr", NULL,
14205 /* AC */ NULL, NULL, "pfacc", NULL,
14206 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
14207 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
14208 /* B8 */ NULL, NULL, NULL, "pswapd",
14209 /* BC */ NULL, NULL, NULL, "pavgusb",
14210 /* C0 */ NULL, NULL, NULL, NULL,
14211 /* C4 */ NULL, NULL, NULL, NULL,
14212 /* C8 */ NULL, NULL, NULL, NULL,
14213 /* CC */ NULL, NULL, NULL, NULL,
14214 /* D0 */ NULL, NULL, NULL, NULL,
14215 /* D4 */ NULL, NULL, NULL, NULL,
14216 /* D8 */ NULL, NULL, NULL, NULL,
14217 /* DC */ NULL, NULL, NULL, NULL,
14218 /* E0 */ NULL, NULL, NULL, NULL,
14219 /* E4 */ NULL, NULL, NULL, NULL,
14220 /* E8 */ NULL, NULL, NULL, NULL,
14221 /* EC */ NULL, NULL, NULL, NULL,
14222 /* F0 */ NULL, NULL, NULL, NULL,
14223 /* F4 */ NULL, NULL, NULL, NULL,
14224 /* F8 */ NULL, NULL, NULL, NULL,
14225 /* FC */ NULL, NULL, NULL, NULL,
14229 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14231 const char *mnemonic;
14233 FETCH_DATA (the_info, codep + 1);
14234 /* AMD 3DNow! instructions are specified by an opcode suffix in the
14235 place where an 8-bit immediate would normally go. ie. the last
14236 byte of the instruction. */
14237 obufp = mnemonicendp;
14238 mnemonic = Suffix3DNow[*codep++ & 0xff];
14240 oappend (mnemonic);
14243 /* Since a variable sized modrm/sib chunk is between the start
14244 of the opcode (0x0f0f) and the opcode suffix, we need to do
14245 all the modrm processing first, and don't know until now that
14246 we have a bad opcode. This necessitates some cleaning up. */
14247 op_out[0][0] = '\0';
14248 op_out[1][0] = '\0';
14251 mnemonicendp = obufp;
14254 static struct op simd_cmp_op[] =
14256 { STRING_COMMA_LEN ("eq") },
14257 { STRING_COMMA_LEN ("lt") },
14258 { STRING_COMMA_LEN ("le") },
14259 { STRING_COMMA_LEN ("unord") },
14260 { STRING_COMMA_LEN ("neq") },
14261 { STRING_COMMA_LEN ("nlt") },
14262 { STRING_COMMA_LEN ("nle") },
14263 { STRING_COMMA_LEN ("ord") }
14267 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14269 unsigned int cmp_type;
14271 FETCH_DATA (the_info, codep + 1);
14272 cmp_type = *codep++ & 0xff;
14273 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
14276 char *p = mnemonicendp - 2;
14280 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14281 mnemonicendp += simd_cmp_op[cmp_type].len;
14285 /* We have a reserved extension byte. Output it directly. */
14286 scratchbuf[0] = '$';
14287 print_operand_value (scratchbuf + 1, 1, cmp_type);
14288 oappend (scratchbuf + intel_syntax);
14289 scratchbuf[0] = '\0';
14294 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
14295 int sizeflag ATTRIBUTE_UNUSED)
14297 /* mwait %eax,%ecx */
14300 const char **names = (address_mode == mode_64bit
14301 ? names64 : names32);
14302 strcpy (op_out[0], names[0]);
14303 strcpy (op_out[1], names[1]);
14304 two_source_ops = 1;
14306 /* Skip mod/rm byte. */
14312 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
14313 int sizeflag ATTRIBUTE_UNUSED)
14315 /* monitor %eax,%ecx,%edx" */
14318 const char **op1_names;
14319 const char **names = (address_mode == mode_64bit
14320 ? names64 : names32);
14322 if (!(prefixes & PREFIX_ADDR))
14323 op1_names = (address_mode == mode_16bit
14324 ? names16 : names);
14327 /* Remove "addr16/addr32". */
14328 all_prefixes[last_addr_prefix] = 0;
14329 op1_names = (address_mode != mode_32bit
14330 ? names32 : names16);
14331 used_prefixes |= PREFIX_ADDR;
14333 strcpy (op_out[0], op1_names[0]);
14334 strcpy (op_out[1], names[1]);
14335 strcpy (op_out[2], names[2]);
14336 two_source_ops = 1;
14338 /* Skip mod/rm byte. */
14346 /* Throw away prefixes and 1st. opcode byte. */
14347 codep = insn_codep + 1;
14352 REP_Fixup (int bytemode, int sizeflag)
14354 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14356 if (prefixes & PREFIX_REPZ)
14357 all_prefixes[last_repz_prefix] = REP_PREFIX;
14364 OP_IMREG (bytemode, sizeflag);
14367 OP_ESreg (bytemode, sizeflag);
14370 OP_DSreg (bytemode, sizeflag);
14379 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
14384 /* Change cmpxchg8b to cmpxchg16b. */
14385 char *p = mnemonicendp - 2;
14386 mnemonicendp = stpcpy (p, "16b");
14389 OP_M (bytemode, sizeflag);
14393 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
14395 const char **names;
14399 switch (vex.length)
14413 oappend (names[reg]);
14417 CRC32_Fixup (int bytemode, int sizeflag)
14419 /* Add proper suffix to "crc32". */
14420 char *p = mnemonicendp;
14439 if (sizeflag & DFLAG)
14443 used_prefixes |= (prefixes & PREFIX_DATA);
14447 oappend (INTERNAL_DISASSEMBLER_ERROR);
14454 if (modrm.mod == 3)
14458 /* Skip mod/rm byte. */
14463 add = (rex & REX_B) ? 8 : 0;
14464 if (bytemode == b_mode)
14468 oappend (names8rex[modrm.rm + add]);
14470 oappend (names8[modrm.rm + add]);
14476 oappend (names64[modrm.rm + add]);
14477 else if ((prefixes & PREFIX_DATA))
14478 oappend (names16[modrm.rm + add]);
14480 oappend (names32[modrm.rm + add]);
14484 OP_E (bytemode, sizeflag);
14488 FXSAVE_Fixup (int bytemode, int sizeflag)
14490 /* Add proper suffix to "fxsave" and "fxrstor". */
14494 char *p = mnemonicendp;
14500 OP_M (bytemode, sizeflag);
14503 /* Display the destination register operand for instructions with
14507 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14510 const char **names;
14518 reg = vex.register_specifier;
14519 if (bytemode == vex_scalar_mode)
14521 oappend (names_xmm[reg]);
14525 switch (vex.length)
14532 case vex_vsib_q_w_dq_mode:
14553 case vex_vsib_q_w_dq_mode:
14554 names = vex.w ? names_ymm : names_xmm;
14565 oappend (names[reg]);
14568 /* Get the VEX immediate byte without moving codep. */
14570 static unsigned char
14571 get_vex_imm8 (int sizeflag, int opnum)
14573 int bytes_before_imm = 0;
14575 if (modrm.mod != 3)
14577 /* There are SIB/displacement bytes. */
14578 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14580 /* 32/64 bit address mode */
14581 int base = modrm.rm;
14583 /* Check SIB byte. */
14586 FETCH_DATA (the_info, codep + 1);
14588 /* When decoding the third source, don't increase
14589 bytes_before_imm as this has already been incremented
14590 by one in OP_E_memory while decoding the second
14593 bytes_before_imm++;
14596 /* Don't increase bytes_before_imm when decoding the third source,
14597 it has already been incremented by OP_E_memory while decoding
14598 the second source operand. */
14604 /* When modrm.rm == 5 or modrm.rm == 4 and base in
14605 SIB == 5, there is a 4 byte displacement. */
14607 /* No displacement. */
14610 /* 4 byte displacement. */
14611 bytes_before_imm += 4;
14614 /* 1 byte displacement. */
14615 bytes_before_imm++;
14622 /* 16 bit address mode */
14623 /* Don't increase bytes_before_imm when decoding the third source,
14624 it has already been incremented by OP_E_memory while decoding
14625 the second source operand. */
14631 /* When modrm.rm == 6, there is a 2 byte displacement. */
14633 /* No displacement. */
14636 /* 2 byte displacement. */
14637 bytes_before_imm += 2;
14640 /* 1 byte displacement: when decoding the third source,
14641 don't increase bytes_before_imm as this has already
14642 been incremented by one in OP_E_memory while decoding
14643 the second source operand. */
14645 bytes_before_imm++;
14653 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
14654 return codep [bytes_before_imm];
14658 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
14660 const char **names;
14662 if (reg == -1 && modrm.mod != 3)
14664 OP_E_memory (bytemode, sizeflag);
14676 else if (reg > 7 && address_mode != mode_64bit)
14680 switch (vex.length)
14691 oappend (names[reg]);
14695 OP_EX_VexImmW (int bytemode, int sizeflag)
14698 static unsigned char vex_imm8;
14700 if (vex_w_done == 0)
14704 /* Skip mod/rm byte. */
14708 vex_imm8 = get_vex_imm8 (sizeflag, 0);
14711 reg = vex_imm8 >> 4;
14713 OP_EX_VexReg (bytemode, sizeflag, reg);
14715 else if (vex_w_done == 1)
14720 reg = vex_imm8 >> 4;
14722 OP_EX_VexReg (bytemode, sizeflag, reg);
14726 /* Output the imm8 directly. */
14727 scratchbuf[0] = '$';
14728 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
14729 oappend (scratchbuf + intel_syntax);
14730 scratchbuf[0] = '\0';
14736 OP_Vex_2src (int bytemode, int sizeflag)
14738 if (modrm.mod == 3)
14740 int reg = modrm.rm;
14744 oappend (names_xmm[reg]);
14749 && (bytemode == v_mode || bytemode == v_swap_mode))
14751 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14752 used_prefixes |= (prefixes & PREFIX_DATA);
14754 OP_E (bytemode, sizeflag);
14759 OP_Vex_2src_1 (int bytemode, int sizeflag)
14761 if (modrm.mod == 3)
14763 /* Skip mod/rm byte. */
14769 oappend (names_xmm[vex.register_specifier]);
14771 OP_Vex_2src (bytemode, sizeflag);
14775 OP_Vex_2src_2 (int bytemode, int sizeflag)
14778 OP_Vex_2src (bytemode, sizeflag);
14780 oappend (names_xmm[vex.register_specifier]);
14784 OP_EX_VexW (int bytemode, int sizeflag)
14792 /* Skip mod/rm byte. */
14797 reg = get_vex_imm8 (sizeflag, 0) >> 4;
14802 reg = get_vex_imm8 (sizeflag, 1) >> 4;
14805 OP_EX_VexReg (bytemode, sizeflag, reg);
14809 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
14810 int sizeflag ATTRIBUTE_UNUSED)
14812 /* Skip the immediate byte and check for invalid bits. */
14813 FETCH_DATA (the_info, codep + 1);
14814 if (*codep++ & 0xf)
14819 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14822 const char **names;
14824 FETCH_DATA (the_info, codep + 1);
14827 if (bytemode != x_mode)
14834 if (reg > 7 && address_mode != mode_64bit)
14837 switch (vex.length)
14848 oappend (names[reg]);
14852 OP_XMM_VexW (int bytemode, int sizeflag)
14854 /* Turn off the REX.W bit since it is used for swapping operands
14857 OP_XMM (bytemode, sizeflag);
14861 OP_EX_Vex (int bytemode, int sizeflag)
14863 if (modrm.mod != 3)
14865 if (vex.register_specifier != 0)
14869 OP_EX (bytemode, sizeflag);
14873 OP_XMM_Vex (int bytemode, int sizeflag)
14875 if (modrm.mod != 3)
14877 if (vex.register_specifier != 0)
14881 OP_XMM (bytemode, sizeflag);
14885 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14887 switch (vex.length)
14890 mnemonicendp = stpcpy (obuf, "vzeroupper");
14893 mnemonicendp = stpcpy (obuf, "vzeroall");
14900 static struct op vex_cmp_op[] =
14902 { STRING_COMMA_LEN ("eq") },
14903 { STRING_COMMA_LEN ("lt") },
14904 { STRING_COMMA_LEN ("le") },
14905 { STRING_COMMA_LEN ("unord") },
14906 { STRING_COMMA_LEN ("neq") },
14907 { STRING_COMMA_LEN ("nlt") },
14908 { STRING_COMMA_LEN ("nle") },
14909 { STRING_COMMA_LEN ("ord") },
14910 { STRING_COMMA_LEN ("eq_uq") },
14911 { STRING_COMMA_LEN ("nge") },
14912 { STRING_COMMA_LEN ("ngt") },
14913 { STRING_COMMA_LEN ("false") },
14914 { STRING_COMMA_LEN ("neq_oq") },
14915 { STRING_COMMA_LEN ("ge") },
14916 { STRING_COMMA_LEN ("gt") },
14917 { STRING_COMMA_LEN ("true") },
14918 { STRING_COMMA_LEN ("eq_os") },
14919 { STRING_COMMA_LEN ("lt_oq") },
14920 { STRING_COMMA_LEN ("le_oq") },
14921 { STRING_COMMA_LEN ("unord_s") },
14922 { STRING_COMMA_LEN ("neq_us") },
14923 { STRING_COMMA_LEN ("nlt_uq") },
14924 { STRING_COMMA_LEN ("nle_uq") },
14925 { STRING_COMMA_LEN ("ord_s") },
14926 { STRING_COMMA_LEN ("eq_us") },
14927 { STRING_COMMA_LEN ("nge_uq") },
14928 { STRING_COMMA_LEN ("ngt_uq") },
14929 { STRING_COMMA_LEN ("false_os") },
14930 { STRING_COMMA_LEN ("neq_os") },
14931 { STRING_COMMA_LEN ("ge_oq") },
14932 { STRING_COMMA_LEN ("gt_oq") },
14933 { STRING_COMMA_LEN ("true_us") },
14937 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14939 unsigned int cmp_type;
14941 FETCH_DATA (the_info, codep + 1);
14942 cmp_type = *codep++ & 0xff;
14943 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
14946 char *p = mnemonicendp - 2;
14950 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
14951 mnemonicendp += vex_cmp_op[cmp_type].len;
14955 /* We have a reserved extension byte. Output it directly. */
14956 scratchbuf[0] = '$';
14957 print_operand_value (scratchbuf + 1, 1, cmp_type);
14958 oappend (scratchbuf + intel_syntax);
14959 scratchbuf[0] = '\0';
14963 static const struct op pclmul_op[] =
14965 { STRING_COMMA_LEN ("lql") },
14966 { STRING_COMMA_LEN ("hql") },
14967 { STRING_COMMA_LEN ("lqh") },
14968 { STRING_COMMA_LEN ("hqh") }
14972 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
14973 int sizeflag ATTRIBUTE_UNUSED)
14975 unsigned int pclmul_type;
14977 FETCH_DATA (the_info, codep + 1);
14978 pclmul_type = *codep++ & 0xff;
14979 switch (pclmul_type)
14990 if (pclmul_type < ARRAY_SIZE (pclmul_op))
14993 char *p = mnemonicendp - 3;
14998 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
14999 mnemonicendp += pclmul_op[pclmul_type].len;
15003 /* We have a reserved extension byte. Output it directly. */
15004 scratchbuf[0] = '$';
15005 print_operand_value (scratchbuf + 1, 1, pclmul_type);
15006 oappend (scratchbuf + intel_syntax);
15007 scratchbuf[0] = '\0';
15012 MOVBE_Fixup (int bytemode, int sizeflag)
15014 /* Add proper suffix to "movbe". */
15015 char *p = mnemonicendp;
15024 if (sizeflag & SUFFIX_ALWAYS)
15030 if (sizeflag & DFLAG)
15034 used_prefixes |= (prefixes & PREFIX_DATA);
15039 oappend (INTERNAL_DISASSEMBLER_ERROR);
15046 OP_M (bytemode, sizeflag);
15050 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15053 const char **names;
15055 /* Skip mod/rm byte. */
15069 oappend (names[reg]);
15073 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15075 const char **names;
15082 oappend (names[vex.register_specifier]);