1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2015 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma, disassemble_info *);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma get64 (void);
58 static bfd_signed_vma get32 (void);
59 static bfd_signed_vma get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void HLE_Fixup1 (int, int);
113 static void HLE_Fixup2 (int, int);
114 static void HLE_Fixup3 (int, int);
115 static void CMPXCHG8B_Fixup (int, int);
116 static void XMM_Fixup (int, int);
117 static void CRC32_Fixup (int, int);
118 static void FXSAVE_Fixup (int, int);
119 static void OP_LWPCB_E (int, int);
120 static void OP_LWP_E (int, int);
121 static void OP_Vex_2src_1 (int, int);
122 static void OP_Vex_2src_2 (int, int);
124 static void MOVBE_Fixup (int, int);
126 static void OP_Mask (int, int);
129 /* Points to first byte not fetched. */
130 bfd_byte *max_fetched;
131 bfd_byte the_buffer[MAX_MNEM_SIZE];
134 OPCODES_SIGJMP_BUF bailout;
144 enum address_mode address_mode;
146 /* Flags for the prefixes for the current instruction. See below. */
149 /* REX prefix the current instruction. See below. */
151 /* Bits of REX we've already used. */
153 /* REX bits in original REX prefix ignored. */
154 static int rex_ignored;
155 /* Mark parts used in the REX prefix. When we are testing for
156 empty prefix (for 8bit register REX extension), just mask it
157 out. Otherwise test for REX bit is excuse for existence of REX
158 only in case value is nonzero. */
159 #define USED_REX(value) \
164 rex_used |= (value) | REX_OPCODE; \
167 rex_used |= REX_OPCODE; \
170 /* Flags for prefixes which we somehow handled when printing the
171 current instruction. */
172 static int used_prefixes;
174 /* Flags stored in PREFIXES. */
175 #define PREFIX_REPZ 1
176 #define PREFIX_REPNZ 2
177 #define PREFIX_LOCK 4
179 #define PREFIX_SS 0x10
180 #define PREFIX_DS 0x20
181 #define PREFIX_ES 0x40
182 #define PREFIX_FS 0x80
183 #define PREFIX_GS 0x100
184 #define PREFIX_DATA 0x200
185 #define PREFIX_ADDR 0x400
186 #define PREFIX_FWAIT 0x800
188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
189 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
191 #define FETCH_DATA(info, addr) \
192 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
193 ? 1 : fetch_data ((info), (addr)))
196 fetch_data (struct disassemble_info *info, bfd_byte *addr)
199 struct dis_private *priv = (struct dis_private *) info->private_data;
200 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
202 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
203 status = (*info->read_memory_func) (start,
205 addr - priv->max_fetched,
211 /* If we did manage to read at least one byte, then
212 print_insn_i386 will do something sensible. Otherwise, print
213 an error. We do that here because this is where we know
215 if (priv->max_fetched == priv->the_buffer)
216 (*info->memory_error_func) (status, start, info);
217 OPCODES_SIGLONGJMP (priv->bailout, 1);
220 priv->max_fetched = addr;
224 /* Possible values for prefix requirement. */
225 #define PREFIX_IGNORED_SHIFT 16
226 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
227 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
228 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
232 /* Opcode prefixes. */
233 #define PREFIX_OPCODE (PREFIX_REPZ \
237 /* Prefixes ignored. */
238 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
239 | PREFIX_IGNORED_REPNZ \
240 | PREFIX_IGNORED_DATA)
242 #define XX { NULL, 0 }
243 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
245 #define Eb { OP_E, b_mode }
246 #define Ebnd { OP_E, bnd_mode }
247 #define EbS { OP_E, b_swap_mode }
248 #define Ev { OP_E, v_mode }
249 #define Ev_bnd { OP_E, v_bnd_mode }
250 #define EvS { OP_E, v_swap_mode }
251 #define Ed { OP_E, d_mode }
252 #define Edq { OP_E, dq_mode }
253 #define Edqw { OP_E, dqw_mode }
254 #define EdqwS { OP_E, dqw_swap_mode }
255 #define Edqb { OP_E, dqb_mode }
256 #define Edb { OP_E, db_mode }
257 #define Edw { OP_E, dw_mode }
258 #define Edqd { OP_E, dqd_mode }
259 #define Eq { OP_E, q_mode }
260 #define indirEv { OP_indirE, stack_v_mode }
261 #define indirEp { OP_indirE, f_mode }
262 #define stackEv { OP_E, stack_v_mode }
263 #define Em { OP_E, m_mode }
264 #define Ew { OP_E, w_mode }
265 #define M { OP_M, 0 } /* lea, lgdt, etc. */
266 #define Ma { OP_M, a_mode }
267 #define Mb { OP_M, b_mode }
268 #define Md { OP_M, d_mode }
269 #define Mo { OP_M, o_mode }
270 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
271 #define Mq { OP_M, q_mode }
272 #define Mx { OP_M, x_mode }
273 #define Mxmm { OP_M, xmm_mode }
274 #define Gb { OP_G, b_mode }
275 #define Gbnd { OP_G, bnd_mode }
276 #define Gv { OP_G, v_mode }
277 #define Gd { OP_G, d_mode }
278 #define Gdq { OP_G, dq_mode }
279 #define Gm { OP_G, m_mode }
280 #define Gw { OP_G, w_mode }
281 #define Rd { OP_R, d_mode }
282 #define Rdq { OP_R, dq_mode }
283 #define Rm { OP_R, m_mode }
284 #define Ib { OP_I, b_mode }
285 #define sIb { OP_sI, b_mode } /* sign extened byte */
286 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
287 #define Iv { OP_I, v_mode }
288 #define sIv { OP_sI, v_mode }
289 #define Iq { OP_I, q_mode }
290 #define Iv64 { OP_I64, v_mode }
291 #define Iw { OP_I, w_mode }
292 #define I1 { OP_I, const_1_mode }
293 #define Jb { OP_J, b_mode }
294 #define Jv { OP_J, v_mode }
295 #define Cm { OP_C, m_mode }
296 #define Dm { OP_D, m_mode }
297 #define Td { OP_T, d_mode }
298 #define Skip_MODRM { OP_Skip_MODRM, 0 }
300 #define RMeAX { OP_REG, eAX_reg }
301 #define RMeBX { OP_REG, eBX_reg }
302 #define RMeCX { OP_REG, eCX_reg }
303 #define RMeDX { OP_REG, eDX_reg }
304 #define RMeSP { OP_REG, eSP_reg }
305 #define RMeBP { OP_REG, eBP_reg }
306 #define RMeSI { OP_REG, eSI_reg }
307 #define RMeDI { OP_REG, eDI_reg }
308 #define RMrAX { OP_REG, rAX_reg }
309 #define RMrBX { OP_REG, rBX_reg }
310 #define RMrCX { OP_REG, rCX_reg }
311 #define RMrDX { OP_REG, rDX_reg }
312 #define RMrSP { OP_REG, rSP_reg }
313 #define RMrBP { OP_REG, rBP_reg }
314 #define RMrSI { OP_REG, rSI_reg }
315 #define RMrDI { OP_REG, rDI_reg }
316 #define RMAL { OP_REG, al_reg }
317 #define RMCL { OP_REG, cl_reg }
318 #define RMDL { OP_REG, dl_reg }
319 #define RMBL { OP_REG, bl_reg }
320 #define RMAH { OP_REG, ah_reg }
321 #define RMCH { OP_REG, ch_reg }
322 #define RMDH { OP_REG, dh_reg }
323 #define RMBH { OP_REG, bh_reg }
324 #define RMAX { OP_REG, ax_reg }
325 #define RMDX { OP_REG, dx_reg }
327 #define eAX { OP_IMREG, eAX_reg }
328 #define eBX { OP_IMREG, eBX_reg }
329 #define eCX { OP_IMREG, eCX_reg }
330 #define eDX { OP_IMREG, eDX_reg }
331 #define eSP { OP_IMREG, eSP_reg }
332 #define eBP { OP_IMREG, eBP_reg }
333 #define eSI { OP_IMREG, eSI_reg }
334 #define eDI { OP_IMREG, eDI_reg }
335 #define AL { OP_IMREG, al_reg }
336 #define CL { OP_IMREG, cl_reg }
337 #define DL { OP_IMREG, dl_reg }
338 #define BL { OP_IMREG, bl_reg }
339 #define AH { OP_IMREG, ah_reg }
340 #define CH { OP_IMREG, ch_reg }
341 #define DH { OP_IMREG, dh_reg }
342 #define BH { OP_IMREG, bh_reg }
343 #define AX { OP_IMREG, ax_reg }
344 #define DX { OP_IMREG, dx_reg }
345 #define zAX { OP_IMREG, z_mode_ax_reg }
346 #define indirDX { OP_IMREG, indir_dx_reg }
348 #define Sw { OP_SEG, w_mode }
349 #define Sv { OP_SEG, v_mode }
350 #define Ap { OP_DIR, 0 }
351 #define Ob { OP_OFF64, b_mode }
352 #define Ov { OP_OFF64, v_mode }
353 #define Xb { OP_DSreg, eSI_reg }
354 #define Xv { OP_DSreg, eSI_reg }
355 #define Xz { OP_DSreg, eSI_reg }
356 #define Yb { OP_ESreg, eDI_reg }
357 #define Yv { OP_ESreg, eDI_reg }
358 #define DSBX { OP_DSreg, eBX_reg }
360 #define es { OP_REG, es_reg }
361 #define ss { OP_REG, ss_reg }
362 #define cs { OP_REG, cs_reg }
363 #define ds { OP_REG, ds_reg }
364 #define fs { OP_REG, fs_reg }
365 #define gs { OP_REG, gs_reg }
367 #define MX { OP_MMX, 0 }
368 #define XM { OP_XMM, 0 }
369 #define XMScalar { OP_XMM, scalar_mode }
370 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
371 #define XMM { OP_XMM, xmm_mode }
372 #define XMxmmq { OP_XMM, xmmq_mode }
373 #define EM { OP_EM, v_mode }
374 #define EMS { OP_EM, v_swap_mode }
375 #define EMd { OP_EM, d_mode }
376 #define EMx { OP_EM, x_mode }
377 #define EXw { OP_EX, w_mode }
378 #define EXd { OP_EX, d_mode }
379 #define EXdScalar { OP_EX, d_scalar_mode }
380 #define EXdS { OP_EX, d_swap_mode }
381 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
382 #define EXq { OP_EX, q_mode }
383 #define EXqScalar { OP_EX, q_scalar_mode }
384 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
385 #define EXqS { OP_EX, q_swap_mode }
386 #define EXx { OP_EX, x_mode }
387 #define EXxS { OP_EX, x_swap_mode }
388 #define EXxmm { OP_EX, xmm_mode }
389 #define EXymm { OP_EX, ymm_mode }
390 #define EXxmmq { OP_EX, xmmq_mode }
391 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
392 #define EXxmm_mb { OP_EX, xmm_mb_mode }
393 #define EXxmm_mw { OP_EX, xmm_mw_mode }
394 #define EXxmm_md { OP_EX, xmm_md_mode }
395 #define EXxmm_mq { OP_EX, xmm_mq_mode }
396 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
397 #define EXxmmdw { OP_EX, xmmdw_mode }
398 #define EXxmmqd { OP_EX, xmmqd_mode }
399 #define EXymmq { OP_EX, ymmq_mode }
400 #define EXVexWdq { OP_EX, vex_w_dq_mode }
401 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
402 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
403 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
404 #define MS { OP_MS, v_mode }
405 #define XS { OP_XS, v_mode }
406 #define EMCq { OP_EMC, q_mode }
407 #define MXC { OP_MXC, 0 }
408 #define OPSUF { OP_3DNowSuffix, 0 }
409 #define CMP { CMP_Fixup, 0 }
410 #define XMM0 { XMM_Fixup, 0 }
411 #define FXSAVE { FXSAVE_Fixup, 0 }
412 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
413 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
415 #define Vex { OP_VEX, vex_mode }
416 #define VexScalar { OP_VEX, vex_scalar_mode }
417 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
418 #define Vex128 { OP_VEX, vex128_mode }
419 #define Vex256 { OP_VEX, vex256_mode }
420 #define VexGdq { OP_VEX, dq_mode }
421 #define VexI4 { VEXI4_Fixup, 0}
422 #define EXdVex { OP_EX_Vex, d_mode }
423 #define EXdVexS { OP_EX_Vex, d_swap_mode }
424 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
425 #define EXqVex { OP_EX_Vex, q_mode }
426 #define EXqVexS { OP_EX_Vex, q_swap_mode }
427 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
428 #define EXVexW { OP_EX_VexW, x_mode }
429 #define EXdVexW { OP_EX_VexW, d_mode }
430 #define EXqVexW { OP_EX_VexW, q_mode }
431 #define EXVexImmW { OP_EX_VexImmW, x_mode }
432 #define XMVex { OP_XMM_Vex, 0 }
433 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
434 #define XMVexW { OP_XMM_VexW, 0 }
435 #define XMVexI4 { OP_REG_VexI4, x_mode }
436 #define PCLMUL { PCLMUL_Fixup, 0 }
437 #define VZERO { VZERO_Fixup, 0 }
438 #define VCMP { VCMP_Fixup, 0 }
439 #define VPCMP { VPCMP_Fixup, 0 }
441 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
442 #define EXxEVexS { OP_Rounding, evex_sae_mode }
444 #define XMask { OP_Mask, mask_mode }
445 #define MaskG { OP_G, mask_mode }
446 #define MaskE { OP_E, mask_mode }
447 #define MaskBDE { OP_E, mask_bd_mode }
448 #define MaskR { OP_R, mask_mode }
449 #define MaskVex { OP_VEX, mask_mode }
451 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
452 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
453 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
454 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
456 /* Used handle "rep" prefix for string instructions. */
457 #define Xbr { REP_Fixup, eSI_reg }
458 #define Xvr { REP_Fixup, eSI_reg }
459 #define Ybr { REP_Fixup, eDI_reg }
460 #define Yvr { REP_Fixup, eDI_reg }
461 #define Yzr { REP_Fixup, eDI_reg }
462 #define indirDXr { REP_Fixup, indir_dx_reg }
463 #define ALr { REP_Fixup, al_reg }
464 #define eAXr { REP_Fixup, eAX_reg }
466 /* Used handle HLE prefix for lockable instructions. */
467 #define Ebh1 { HLE_Fixup1, b_mode }
468 #define Evh1 { HLE_Fixup1, v_mode }
469 #define Ebh2 { HLE_Fixup2, b_mode }
470 #define Evh2 { HLE_Fixup2, v_mode }
471 #define Ebh3 { HLE_Fixup3, b_mode }
472 #define Evh3 { HLE_Fixup3, v_mode }
474 #define BND { BND_Fixup, 0 }
476 #define cond_jump_flag { NULL, cond_jump_mode }
477 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
479 /* bits in sizeflag */
480 #define SUFFIX_ALWAYS 4
488 /* byte operand with operand swapped */
490 /* byte operand, sign extend like 'T' suffix */
492 /* operand size depends on prefixes */
494 /* operand size depends on prefixes with operand swapped */
498 /* double word operand */
500 /* double word operand with operand swapped */
502 /* quad word operand */
504 /* quad word operand with operand swapped */
506 /* ten-byte operand */
508 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
509 broadcast enabled. */
511 /* Similar to x_mode, but with different EVEX mem shifts. */
513 /* Similar to x_mode, but with disabled broadcast. */
515 /* Similar to x_mode, but with operands swapped and disabled broadcast
518 /* 16-byte XMM operand */
520 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
521 memory operand (depending on vector length). Broadcast isn't
524 /* Same as xmmq_mode, but broadcast is allowed. */
525 evex_half_bcst_xmmq_mode,
526 /* XMM register or byte memory operand */
528 /* XMM register or word memory operand */
530 /* XMM register or double word memory operand */
532 /* XMM register or quad word memory operand */
534 /* XMM register or double/quad word memory operand, depending on
537 /* 16-byte XMM, word, double word or quad word operand. */
539 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
541 /* 32-byte YMM operand */
543 /* quad word, ymmword or zmmword memory operand. */
545 /* 32-byte YMM or 16-byte word operand */
547 /* d_mode in 32bit, q_mode in 64bit mode. */
549 /* pair of v_mode operands */
554 /* operand size depends on REX prefixes. */
556 /* registers like dq_mode, memory like w_mode. */
560 /* 4- or 6-byte pointer operand */
563 /* v_mode for stack-related opcodes. */
565 /* non-quad operand size depends on prefixes */
567 /* 16-byte operand */
569 /* registers like dq_mode, memory like b_mode. */
571 /* registers like d_mode, memory like b_mode. */
573 /* registers like d_mode, memory like w_mode. */
575 /* registers like dq_mode, memory like d_mode. */
577 /* normal vex mode */
579 /* 128bit vex mode */
581 /* 256bit vex mode */
583 /* operand size depends on the VEX.W bit. */
586 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
587 vex_vsib_d_w_dq_mode,
588 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
590 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
591 vex_vsib_q_w_dq_mode,
592 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
595 /* scalar, ignore vector length. */
597 /* like d_mode, ignore vector length. */
599 /* like d_swap_mode, ignore vector length. */
601 /* like q_mode, ignore vector length. */
603 /* like q_swap_mode, ignore vector length. */
605 /* like vex_mode, ignore vector length. */
607 /* like vex_w_dq_mode, ignore vector length. */
608 vex_scalar_w_dq_mode,
610 /* Static rounding. */
612 /* Supress all exceptions. */
615 /* Mask register operand. */
617 /* Mask register operand. */
684 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
686 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
687 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
688 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
689 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
690 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
691 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
692 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
693 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
694 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
695 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
696 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
697 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
698 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
699 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
700 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
816 MOD_VEX_0F12_PREFIX_0,
818 MOD_VEX_0F16_PREFIX_0,
834 MOD_VEX_0FD7_PREFIX_2,
835 MOD_VEX_0FE7_PREFIX_2,
836 MOD_VEX_0FF0_PREFIX_3,
837 MOD_VEX_0F381A_PREFIX_2,
838 MOD_VEX_0F382A_PREFIX_2,
839 MOD_VEX_0F382C_PREFIX_2,
840 MOD_VEX_0F382D_PREFIX_2,
841 MOD_VEX_0F382E_PREFIX_2,
842 MOD_VEX_0F382F_PREFIX_2,
843 MOD_VEX_0F385A_PREFIX_2,
844 MOD_VEX_0F388C_PREFIX_2,
845 MOD_VEX_0F388E_PREFIX_2,
847 MOD_EVEX_0F10_PREFIX_1,
848 MOD_EVEX_0F10_PREFIX_3,
849 MOD_EVEX_0F11_PREFIX_1,
850 MOD_EVEX_0F11_PREFIX_3,
851 MOD_EVEX_0F12_PREFIX_0,
852 MOD_EVEX_0F16_PREFIX_0,
853 MOD_EVEX_0F38C6_REG_1,
854 MOD_EVEX_0F38C6_REG_2,
855 MOD_EVEX_0F38C6_REG_5,
856 MOD_EVEX_0F38C6_REG_6,
857 MOD_EVEX_0F38C7_REG_1,
858 MOD_EVEX_0F38C7_REG_2,
859 MOD_EVEX_0F38C7_REG_5,
860 MOD_EVEX_0F38C7_REG_6
924 PREFIX_RM_0_0FAE_REG_7,
930 PREFIX_MOD_0_0FC7_REG_6,
931 PREFIX_MOD_3_0FC7_REG_6,
932 PREFIX_MOD_3_0FC7_REG_7,
1056 PREFIX_VEX_0F71_REG_2,
1057 PREFIX_VEX_0F71_REG_4,
1058 PREFIX_VEX_0F71_REG_6,
1059 PREFIX_VEX_0F72_REG_2,
1060 PREFIX_VEX_0F72_REG_4,
1061 PREFIX_VEX_0F72_REG_6,
1062 PREFIX_VEX_0F73_REG_2,
1063 PREFIX_VEX_0F73_REG_3,
1064 PREFIX_VEX_0F73_REG_6,
1065 PREFIX_VEX_0F73_REG_7,
1237 PREFIX_VEX_0F38F3_REG_1,
1238 PREFIX_VEX_0F38F3_REG_2,
1239 PREFIX_VEX_0F38F3_REG_3,
1356 PREFIX_EVEX_0F71_REG_2,
1357 PREFIX_EVEX_0F71_REG_4,
1358 PREFIX_EVEX_0F71_REG_6,
1359 PREFIX_EVEX_0F72_REG_0,
1360 PREFIX_EVEX_0F72_REG_1,
1361 PREFIX_EVEX_0F72_REG_2,
1362 PREFIX_EVEX_0F72_REG_4,
1363 PREFIX_EVEX_0F72_REG_6,
1364 PREFIX_EVEX_0F73_REG_2,
1365 PREFIX_EVEX_0F73_REG_3,
1366 PREFIX_EVEX_0F73_REG_6,
1367 PREFIX_EVEX_0F73_REG_7,
1550 PREFIX_EVEX_0F38C6_REG_1,
1551 PREFIX_EVEX_0F38C6_REG_2,
1552 PREFIX_EVEX_0F38C6_REG_5,
1553 PREFIX_EVEX_0F38C6_REG_6,
1554 PREFIX_EVEX_0F38C7_REG_1,
1555 PREFIX_EVEX_0F38C7_REG_2,
1556 PREFIX_EVEX_0F38C7_REG_5,
1557 PREFIX_EVEX_0F38C7_REG_6,
1644 THREE_BYTE_0F38 = 0,
1672 VEX_LEN_0F10_P_1 = 0,
1676 VEX_LEN_0F12_P_0_M_0,
1677 VEX_LEN_0F12_P_0_M_1,
1680 VEX_LEN_0F16_P_0_M_0,
1681 VEX_LEN_0F16_P_0_M_1,
1745 VEX_LEN_0FAE_R_2_M_0,
1746 VEX_LEN_0FAE_R_3_M_0,
1755 VEX_LEN_0F381A_P_2_M_0,
1758 VEX_LEN_0F385A_P_2_M_0,
1765 VEX_LEN_0F38F3_R_1_P_0,
1766 VEX_LEN_0F38F3_R_2_P_0,
1767 VEX_LEN_0F38F3_R_3_P_0,
1813 VEX_LEN_0FXOP_08_CC,
1814 VEX_LEN_0FXOP_08_CD,
1815 VEX_LEN_0FXOP_08_CE,
1816 VEX_LEN_0FXOP_08_CF,
1817 VEX_LEN_0FXOP_08_EC,
1818 VEX_LEN_0FXOP_08_ED,
1819 VEX_LEN_0FXOP_08_EE,
1820 VEX_LEN_0FXOP_08_EF,
1821 VEX_LEN_0FXOP_09_80,
1855 VEX_W_0F41_P_0_LEN_1,
1856 VEX_W_0F41_P_2_LEN_1,
1857 VEX_W_0F42_P_0_LEN_1,
1858 VEX_W_0F42_P_2_LEN_1,
1859 VEX_W_0F44_P_0_LEN_0,
1860 VEX_W_0F44_P_2_LEN_0,
1861 VEX_W_0F45_P_0_LEN_1,
1862 VEX_W_0F45_P_2_LEN_1,
1863 VEX_W_0F46_P_0_LEN_1,
1864 VEX_W_0F46_P_2_LEN_1,
1865 VEX_W_0F47_P_0_LEN_1,
1866 VEX_W_0F47_P_2_LEN_1,
1867 VEX_W_0F4A_P_0_LEN_1,
1868 VEX_W_0F4A_P_2_LEN_1,
1869 VEX_W_0F4B_P_0_LEN_1,
1870 VEX_W_0F4B_P_2_LEN_1,
1950 VEX_W_0F90_P_0_LEN_0,
1951 VEX_W_0F90_P_2_LEN_0,
1952 VEX_W_0F91_P_0_LEN_0,
1953 VEX_W_0F91_P_2_LEN_0,
1954 VEX_W_0F92_P_0_LEN_0,
1955 VEX_W_0F92_P_2_LEN_0,
1956 VEX_W_0F92_P_3_LEN_0,
1957 VEX_W_0F93_P_0_LEN_0,
1958 VEX_W_0F93_P_2_LEN_0,
1959 VEX_W_0F93_P_3_LEN_0,
1960 VEX_W_0F98_P_0_LEN_0,
1961 VEX_W_0F98_P_2_LEN_0,
1962 VEX_W_0F99_P_0_LEN_0,
1963 VEX_W_0F99_P_2_LEN_0,
2042 VEX_W_0F381A_P_2_M_0,
2054 VEX_W_0F382A_P_2_M_0,
2056 VEX_W_0F382C_P_2_M_0,
2057 VEX_W_0F382D_P_2_M_0,
2058 VEX_W_0F382E_P_2_M_0,
2059 VEX_W_0F382F_P_2_M_0,
2081 VEX_W_0F385A_P_2_M_0,
2109 VEX_W_0F3A30_P_2_LEN_0,
2110 VEX_W_0F3A31_P_2_LEN_0,
2111 VEX_W_0F3A32_P_2_LEN_0,
2112 VEX_W_0F3A33_P_2_LEN_0,
2132 EVEX_W_0F10_P_1_M_0,
2133 EVEX_W_0F10_P_1_M_1,
2135 EVEX_W_0F10_P_3_M_0,
2136 EVEX_W_0F10_P_3_M_1,
2138 EVEX_W_0F11_P_1_M_0,
2139 EVEX_W_0F11_P_1_M_1,
2141 EVEX_W_0F11_P_3_M_0,
2142 EVEX_W_0F11_P_3_M_1,
2143 EVEX_W_0F12_P_0_M_0,
2144 EVEX_W_0F12_P_0_M_1,
2154 EVEX_W_0F16_P_0_M_0,
2155 EVEX_W_0F16_P_0_M_1,
2226 EVEX_W_0F72_R_2_P_2,
2227 EVEX_W_0F72_R_6_P_2,
2228 EVEX_W_0F73_R_2_P_2,
2229 EVEX_W_0F73_R_6_P_2,
2329 EVEX_W_0F38C7_R_1_P_2,
2330 EVEX_W_0F38C7_R_2_P_2,
2331 EVEX_W_0F38C7_R_5_P_2,
2332 EVEX_W_0F38C7_R_6_P_2,
2367 typedef void (*op_rtn) (int bytemode, int sizeflag);
2376 unsigned int prefix_requirement;
2379 /* Upper case letters in the instruction names here are macros.
2380 'A' => print 'b' if no register operands or suffix_always is true
2381 'B' => print 'b' if suffix_always is true
2382 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2384 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2385 suffix_always is true
2386 'E' => print 'e' if 32-bit form of jcxz
2387 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2388 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2389 'H' => print ",pt" or ",pn" branch hint
2390 'I' => honor following macro letter even in Intel mode (implemented only
2391 for some of the macro letters)
2393 'K' => print 'd' or 'q' if rex prefix is present.
2394 'L' => print 'l' if suffix_always is true
2395 'M' => print 'r' if intel_mnemonic is false.
2396 'N' => print 'n' if instruction has no wait "prefix"
2397 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2398 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2399 or suffix_always is true. print 'q' if rex prefix is present.
2400 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2402 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2403 'S' => print 'w', 'l' or 'q' if suffix_always is true
2404 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2405 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2406 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2407 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2408 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2409 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2410 suffix_always is true.
2411 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2412 '!' => change condition from true to false or from false to true.
2413 '%' => add 1 upper case letter to the macro.
2415 2 upper case letter macros:
2416 "XY" => print 'x' or 'y' if no register operands or suffix_always
2418 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2419 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2420 or suffix_always is true
2421 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2422 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2423 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2424 "LW" => print 'd', 'q' depending on the VEX.W bit
2425 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2426 an operand size prefix, or suffix_always is true. print
2427 'q' if rex prefix is present.
2429 Many of the above letters print nothing in Intel mode. See "putop"
2432 Braces '{' and '}', and vertical bars '|', indicate alternative
2433 mnemonic strings for AT&T and Intel. */
2435 static const struct dis386 dis386[] = {
2437 { "addB", { Ebh1, Gb }, 0 },
2438 { "addS", { Evh1, Gv }, 0 },
2439 { "addB", { Gb, EbS }, 0 },
2440 { "addS", { Gv, EvS }, 0 },
2441 { "addB", { AL, Ib }, 0 },
2442 { "addS", { eAX, Iv }, 0 },
2443 { X86_64_TABLE (X86_64_06) },
2444 { X86_64_TABLE (X86_64_07) },
2446 { "orB", { Ebh1, Gb }, 0 },
2447 { "orS", { Evh1, Gv }, 0 },
2448 { "orB", { Gb, EbS }, 0 },
2449 { "orS", { Gv, EvS }, 0 },
2450 { "orB", { AL, Ib }, 0 },
2451 { "orS", { eAX, Iv }, 0 },
2452 { X86_64_TABLE (X86_64_0D) },
2453 { Bad_Opcode }, /* 0x0f extended opcode escape */
2455 { "adcB", { Ebh1, Gb }, 0 },
2456 { "adcS", { Evh1, Gv }, 0 },
2457 { "adcB", { Gb, EbS }, 0 },
2458 { "adcS", { Gv, EvS }, 0 },
2459 { "adcB", { AL, Ib }, 0 },
2460 { "adcS", { eAX, Iv }, 0 },
2461 { X86_64_TABLE (X86_64_16) },
2462 { X86_64_TABLE (X86_64_17) },
2464 { "sbbB", { Ebh1, Gb }, 0 },
2465 { "sbbS", { Evh1, Gv }, 0 },
2466 { "sbbB", { Gb, EbS }, 0 },
2467 { "sbbS", { Gv, EvS }, 0 },
2468 { "sbbB", { AL, Ib }, 0 },
2469 { "sbbS", { eAX, Iv }, 0 },
2470 { X86_64_TABLE (X86_64_1E) },
2471 { X86_64_TABLE (X86_64_1F) },
2473 { "andB", { Ebh1, Gb }, 0 },
2474 { "andS", { Evh1, Gv }, 0 },
2475 { "andB", { Gb, EbS }, 0 },
2476 { "andS", { Gv, EvS }, 0 },
2477 { "andB", { AL, Ib }, 0 },
2478 { "andS", { eAX, Iv }, 0 },
2479 { Bad_Opcode }, /* SEG ES prefix */
2480 { X86_64_TABLE (X86_64_27) },
2482 { "subB", { Ebh1, Gb }, 0 },
2483 { "subS", { Evh1, Gv }, 0 },
2484 { "subB", { Gb, EbS }, 0 },
2485 { "subS", { Gv, EvS }, 0 },
2486 { "subB", { AL, Ib }, 0 },
2487 { "subS", { eAX, Iv }, 0 },
2488 { Bad_Opcode }, /* SEG CS prefix */
2489 { X86_64_TABLE (X86_64_2F) },
2491 { "xorB", { Ebh1, Gb }, 0 },
2492 { "xorS", { Evh1, Gv }, 0 },
2493 { "xorB", { Gb, EbS }, 0 },
2494 { "xorS", { Gv, EvS }, 0 },
2495 { "xorB", { AL, Ib }, 0 },
2496 { "xorS", { eAX, Iv }, 0 },
2497 { Bad_Opcode }, /* SEG SS prefix */
2498 { X86_64_TABLE (X86_64_37) },
2500 { "cmpB", { Eb, Gb }, 0 },
2501 { "cmpS", { Ev, Gv }, 0 },
2502 { "cmpB", { Gb, EbS }, 0 },
2503 { "cmpS", { Gv, EvS }, 0 },
2504 { "cmpB", { AL, Ib }, 0 },
2505 { "cmpS", { eAX, Iv }, 0 },
2506 { Bad_Opcode }, /* SEG DS prefix */
2507 { X86_64_TABLE (X86_64_3F) },
2509 { "inc{S|}", { RMeAX }, 0 },
2510 { "inc{S|}", { RMeCX }, 0 },
2511 { "inc{S|}", { RMeDX }, 0 },
2512 { "inc{S|}", { RMeBX }, 0 },
2513 { "inc{S|}", { RMeSP }, 0 },
2514 { "inc{S|}", { RMeBP }, 0 },
2515 { "inc{S|}", { RMeSI }, 0 },
2516 { "inc{S|}", { RMeDI }, 0 },
2518 { "dec{S|}", { RMeAX }, 0 },
2519 { "dec{S|}", { RMeCX }, 0 },
2520 { "dec{S|}", { RMeDX }, 0 },
2521 { "dec{S|}", { RMeBX }, 0 },
2522 { "dec{S|}", { RMeSP }, 0 },
2523 { "dec{S|}", { RMeBP }, 0 },
2524 { "dec{S|}", { RMeSI }, 0 },
2525 { "dec{S|}", { RMeDI }, 0 },
2527 { "pushV", { RMrAX }, 0 },
2528 { "pushV", { RMrCX }, 0 },
2529 { "pushV", { RMrDX }, 0 },
2530 { "pushV", { RMrBX }, 0 },
2531 { "pushV", { RMrSP }, 0 },
2532 { "pushV", { RMrBP }, 0 },
2533 { "pushV", { RMrSI }, 0 },
2534 { "pushV", { RMrDI }, 0 },
2536 { "popV", { RMrAX }, 0 },
2537 { "popV", { RMrCX }, 0 },
2538 { "popV", { RMrDX }, 0 },
2539 { "popV", { RMrBX }, 0 },
2540 { "popV", { RMrSP }, 0 },
2541 { "popV", { RMrBP }, 0 },
2542 { "popV", { RMrSI }, 0 },
2543 { "popV", { RMrDI }, 0 },
2545 { X86_64_TABLE (X86_64_60) },
2546 { X86_64_TABLE (X86_64_61) },
2547 { X86_64_TABLE (X86_64_62) },
2548 { X86_64_TABLE (X86_64_63) },
2549 { Bad_Opcode }, /* seg fs */
2550 { Bad_Opcode }, /* seg gs */
2551 { Bad_Opcode }, /* op size prefix */
2552 { Bad_Opcode }, /* adr size prefix */
2554 { "pushT", { sIv }, 0 },
2555 { "imulS", { Gv, Ev, Iv }, 0 },
2556 { "pushT", { sIbT }, 0 },
2557 { "imulS", { Gv, Ev, sIb }, 0 },
2558 { "ins{b|}", { Ybr, indirDX }, 0 },
2559 { X86_64_TABLE (X86_64_6D) },
2560 { "outs{b|}", { indirDXr, Xb }, 0 },
2561 { X86_64_TABLE (X86_64_6F) },
2563 { "joH", { Jb, BND, cond_jump_flag }, 0 },
2564 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
2565 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
2566 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
2567 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
2568 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
2569 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
2570 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
2572 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
2573 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
2574 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
2575 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
2576 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
2577 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
2578 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
2579 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
2581 { REG_TABLE (REG_80) },
2582 { REG_TABLE (REG_81) },
2584 { REG_TABLE (REG_82) },
2585 { "testB", { Eb, Gb }, 0 },
2586 { "testS", { Ev, Gv }, 0 },
2587 { "xchgB", { Ebh2, Gb }, 0 },
2588 { "xchgS", { Evh2, Gv }, 0 },
2590 { "movB", { Ebh3, Gb }, 0 },
2591 { "movS", { Evh3, Gv }, 0 },
2592 { "movB", { Gb, EbS }, 0 },
2593 { "movS", { Gv, EvS }, 0 },
2594 { "movD", { Sv, Sw }, 0 },
2595 { MOD_TABLE (MOD_8D) },
2596 { "movD", { Sw, Sv }, 0 },
2597 { REG_TABLE (REG_8F) },
2599 { PREFIX_TABLE (PREFIX_90) },
2600 { "xchgS", { RMeCX, eAX }, 0 },
2601 { "xchgS", { RMeDX, eAX }, 0 },
2602 { "xchgS", { RMeBX, eAX }, 0 },
2603 { "xchgS", { RMeSP, eAX }, 0 },
2604 { "xchgS", { RMeBP, eAX }, 0 },
2605 { "xchgS", { RMeSI, eAX }, 0 },
2606 { "xchgS", { RMeDI, eAX }, 0 },
2608 { "cW{t|}R", { XX }, 0 },
2609 { "cR{t|}O", { XX }, 0 },
2610 { X86_64_TABLE (X86_64_9A) },
2611 { Bad_Opcode }, /* fwait */
2612 { "pushfT", { XX }, 0 },
2613 { "popfT", { XX }, 0 },
2614 { "sahf", { XX }, 0 },
2615 { "lahf", { XX }, 0 },
2617 { "mov%LB", { AL, Ob }, 0 },
2618 { "mov%LS", { eAX, Ov }, 0 },
2619 { "mov%LB", { Ob, AL }, 0 },
2620 { "mov%LS", { Ov, eAX }, 0 },
2621 { "movs{b|}", { Ybr, Xb }, 0 },
2622 { "movs{R|}", { Yvr, Xv }, 0 },
2623 { "cmps{b|}", { Xb, Yb }, 0 },
2624 { "cmps{R|}", { Xv, Yv }, 0 },
2626 { "testB", { AL, Ib }, 0 },
2627 { "testS", { eAX, Iv }, 0 },
2628 { "stosB", { Ybr, AL }, 0 },
2629 { "stosS", { Yvr, eAX }, 0 },
2630 { "lodsB", { ALr, Xb }, 0 },
2631 { "lodsS", { eAXr, Xv }, 0 },
2632 { "scasB", { AL, Yb }, 0 },
2633 { "scasS", { eAX, Yv }, 0 },
2635 { "movB", { RMAL, Ib }, 0 },
2636 { "movB", { RMCL, Ib }, 0 },
2637 { "movB", { RMDL, Ib }, 0 },
2638 { "movB", { RMBL, Ib }, 0 },
2639 { "movB", { RMAH, Ib }, 0 },
2640 { "movB", { RMCH, Ib }, 0 },
2641 { "movB", { RMDH, Ib }, 0 },
2642 { "movB", { RMBH, Ib }, 0 },
2644 { "mov%LV", { RMeAX, Iv64 }, 0 },
2645 { "mov%LV", { RMeCX, Iv64 }, 0 },
2646 { "mov%LV", { RMeDX, Iv64 }, 0 },
2647 { "mov%LV", { RMeBX, Iv64 }, 0 },
2648 { "mov%LV", { RMeSP, Iv64 }, 0 },
2649 { "mov%LV", { RMeBP, Iv64 }, 0 },
2650 { "mov%LV", { RMeSI, Iv64 }, 0 },
2651 { "mov%LV", { RMeDI, Iv64 }, 0 },
2653 { REG_TABLE (REG_C0) },
2654 { REG_TABLE (REG_C1) },
2655 { "retT", { Iw, BND }, 0 },
2656 { "retT", { BND }, 0 },
2657 { X86_64_TABLE (X86_64_C4) },
2658 { X86_64_TABLE (X86_64_C5) },
2659 { REG_TABLE (REG_C6) },
2660 { REG_TABLE (REG_C7) },
2662 { "enterT", { Iw, Ib }, 0 },
2663 { "leaveT", { XX }, 0 },
2664 { "Jret{|f}P", { Iw }, 0 },
2665 { "Jret{|f}P", { XX }, 0 },
2666 { "int3", { XX }, 0 },
2667 { "int", { Ib }, 0 },
2668 { X86_64_TABLE (X86_64_CE) },
2669 { "iret%LP", { XX }, 0 },
2671 { REG_TABLE (REG_D0) },
2672 { REG_TABLE (REG_D1) },
2673 { REG_TABLE (REG_D2) },
2674 { REG_TABLE (REG_D3) },
2675 { X86_64_TABLE (X86_64_D4) },
2676 { X86_64_TABLE (X86_64_D5) },
2678 { "xlat", { DSBX }, 0 },
2689 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2690 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2691 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2692 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2693 { "inB", { AL, Ib }, 0 },
2694 { "inG", { zAX, Ib }, 0 },
2695 { "outB", { Ib, AL }, 0 },
2696 { "outG", { Ib, zAX }, 0 },
2698 { "callT", { Jv, BND }, 0 },
2699 { "jmpT", { Jv, BND }, 0 },
2700 { X86_64_TABLE (X86_64_EA) },
2701 { "jmp", { Jb, BND }, 0 },
2702 { "inB", { AL, indirDX }, 0 },
2703 { "inG", { zAX, indirDX }, 0 },
2704 { "outB", { indirDX, AL }, 0 },
2705 { "outG", { indirDX, zAX }, 0 },
2707 { Bad_Opcode }, /* lock prefix */
2708 { "icebp", { XX }, 0 },
2709 { Bad_Opcode }, /* repne */
2710 { Bad_Opcode }, /* repz */
2711 { "hlt", { XX }, 0 },
2712 { "cmc", { XX }, 0 },
2713 { REG_TABLE (REG_F6) },
2714 { REG_TABLE (REG_F7) },
2716 { "clc", { XX }, 0 },
2717 { "stc", { XX }, 0 },
2718 { "cli", { XX }, 0 },
2719 { "sti", { XX }, 0 },
2720 { "cld", { XX }, 0 },
2721 { "std", { XX }, 0 },
2722 { REG_TABLE (REG_FE) },
2723 { REG_TABLE (REG_FF) },
2726 static const struct dis386 dis386_twobyte[] = {
2728 { REG_TABLE (REG_0F00 ) },
2729 { REG_TABLE (REG_0F01 ) },
2730 { "larS", { Gv, Ew }, 0 },
2731 { "lslS", { Gv, Ew }, 0 },
2733 { "syscall", { XX }, 0 },
2734 { "clts", { XX }, 0 },
2735 { "sysret%LP", { XX }, 0 },
2737 { "invd", { XX }, 0 },
2738 { "wbinvd", { XX }, 0 },
2740 { "ud2", { XX }, 0 },
2742 { REG_TABLE (REG_0F0D) },
2743 { "femms", { XX }, 0 },
2744 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2746 { PREFIX_TABLE (PREFIX_0F10) },
2747 { PREFIX_TABLE (PREFIX_0F11) },
2748 { PREFIX_TABLE (PREFIX_0F12) },
2749 { MOD_TABLE (MOD_0F13) },
2750 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2751 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2752 { PREFIX_TABLE (PREFIX_0F16) },
2753 { MOD_TABLE (MOD_0F17) },
2755 { REG_TABLE (REG_0F18) },
2756 { "nopQ", { Ev }, 0 },
2757 { PREFIX_TABLE (PREFIX_0F1A) },
2758 { PREFIX_TABLE (PREFIX_0F1B) },
2759 { "nopQ", { Ev }, 0 },
2760 { "nopQ", { Ev }, 0 },
2761 { "nopQ", { Ev }, 0 },
2762 { "nopQ", { Ev }, 0 },
2764 { "movZ", { Rm, Cm }, 0 },
2765 { "movZ", { Rm, Dm }, 0 },
2766 { "movZ", { Cm, Rm }, 0 },
2767 { "movZ", { Dm, Rm }, 0 },
2768 { MOD_TABLE (MOD_0F24) },
2770 { MOD_TABLE (MOD_0F26) },
2773 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2774 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2775 { PREFIX_TABLE (PREFIX_0F2A) },
2776 { PREFIX_TABLE (PREFIX_0F2B) },
2777 { PREFIX_TABLE (PREFIX_0F2C) },
2778 { PREFIX_TABLE (PREFIX_0F2D) },
2779 { PREFIX_TABLE (PREFIX_0F2E) },
2780 { PREFIX_TABLE (PREFIX_0F2F) },
2782 { "wrmsr", { XX }, 0 },
2783 { "rdtsc", { XX }, 0 },
2784 { "rdmsr", { XX }, 0 },
2785 { "rdpmc", { XX }, 0 },
2786 { "sysenter", { XX }, 0 },
2787 { "sysexit", { XX }, 0 },
2789 { "getsec", { XX }, 0 },
2791 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2793 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2800 { "cmovoS", { Gv, Ev }, 0 },
2801 { "cmovnoS", { Gv, Ev }, 0 },
2802 { "cmovbS", { Gv, Ev }, 0 },
2803 { "cmovaeS", { Gv, Ev }, 0 },
2804 { "cmoveS", { Gv, Ev }, 0 },
2805 { "cmovneS", { Gv, Ev }, 0 },
2806 { "cmovbeS", { Gv, Ev }, 0 },
2807 { "cmovaS", { Gv, Ev }, 0 },
2809 { "cmovsS", { Gv, Ev }, 0 },
2810 { "cmovnsS", { Gv, Ev }, 0 },
2811 { "cmovpS", { Gv, Ev }, 0 },
2812 { "cmovnpS", { Gv, Ev }, 0 },
2813 { "cmovlS", { Gv, Ev }, 0 },
2814 { "cmovgeS", { Gv, Ev }, 0 },
2815 { "cmovleS", { Gv, Ev }, 0 },
2816 { "cmovgS", { Gv, Ev }, 0 },
2818 { MOD_TABLE (MOD_0F51) },
2819 { PREFIX_TABLE (PREFIX_0F51) },
2820 { PREFIX_TABLE (PREFIX_0F52) },
2821 { PREFIX_TABLE (PREFIX_0F53) },
2822 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2823 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2824 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2825 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2827 { PREFIX_TABLE (PREFIX_0F58) },
2828 { PREFIX_TABLE (PREFIX_0F59) },
2829 { PREFIX_TABLE (PREFIX_0F5A) },
2830 { PREFIX_TABLE (PREFIX_0F5B) },
2831 { PREFIX_TABLE (PREFIX_0F5C) },
2832 { PREFIX_TABLE (PREFIX_0F5D) },
2833 { PREFIX_TABLE (PREFIX_0F5E) },
2834 { PREFIX_TABLE (PREFIX_0F5F) },
2836 { PREFIX_TABLE (PREFIX_0F60) },
2837 { PREFIX_TABLE (PREFIX_0F61) },
2838 { PREFIX_TABLE (PREFIX_0F62) },
2839 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2840 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2841 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2842 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2843 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2845 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2846 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2847 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2848 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2849 { PREFIX_TABLE (PREFIX_0F6C) },
2850 { PREFIX_TABLE (PREFIX_0F6D) },
2851 { "movK", { MX, Edq }, PREFIX_OPCODE },
2852 { PREFIX_TABLE (PREFIX_0F6F) },
2854 { PREFIX_TABLE (PREFIX_0F70) },
2855 { REG_TABLE (REG_0F71) },
2856 { REG_TABLE (REG_0F72) },
2857 { REG_TABLE (REG_0F73) },
2858 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2859 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2860 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2861 { "emms", { XX }, PREFIX_OPCODE },
2863 { PREFIX_TABLE (PREFIX_0F78) },
2864 { PREFIX_TABLE (PREFIX_0F79) },
2865 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2867 { PREFIX_TABLE (PREFIX_0F7C) },
2868 { PREFIX_TABLE (PREFIX_0F7D) },
2869 { PREFIX_TABLE (PREFIX_0F7E) },
2870 { PREFIX_TABLE (PREFIX_0F7F) },
2872 { "joH", { Jv, BND, cond_jump_flag }, 0 },
2873 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
2874 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
2875 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
2876 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
2877 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
2878 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
2879 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
2881 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
2882 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
2883 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
2884 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
2885 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
2886 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
2887 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
2888 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
2890 { "seto", { Eb }, 0 },
2891 { "setno", { Eb }, 0 },
2892 { "setb", { Eb }, 0 },
2893 { "setae", { Eb }, 0 },
2894 { "sete", { Eb }, 0 },
2895 { "setne", { Eb }, 0 },
2896 { "setbe", { Eb }, 0 },
2897 { "seta", { Eb }, 0 },
2899 { "sets", { Eb }, 0 },
2900 { "setns", { Eb }, 0 },
2901 { "setp", { Eb }, 0 },
2902 { "setnp", { Eb }, 0 },
2903 { "setl", { Eb }, 0 },
2904 { "setge", { Eb }, 0 },
2905 { "setle", { Eb }, 0 },
2906 { "setg", { Eb }, 0 },
2908 { "pushT", { fs }, 0 },
2909 { "popT", { fs }, 0 },
2910 { "cpuid", { XX }, 0 },
2911 { "btS", { Ev, Gv }, 0 },
2912 { "shldS", { Ev, Gv, Ib }, 0 },
2913 { "shldS", { Ev, Gv, CL }, 0 },
2914 { REG_TABLE (REG_0FA6) },
2915 { REG_TABLE (REG_0FA7) },
2917 { "pushT", { gs }, 0 },
2918 { "popT", { gs }, 0 },
2919 { "rsm", { XX }, 0 },
2920 { "btsS", { Evh1, Gv }, 0 },
2921 { "shrdS", { Ev, Gv, Ib }, 0 },
2922 { "shrdS", { Ev, Gv, CL }, 0 },
2923 { REG_TABLE (REG_0FAE) },
2924 { "imulS", { Gv, Ev }, 0 },
2926 { "cmpxchgB", { Ebh1, Gb }, 0 },
2927 { "cmpxchgS", { Evh1, Gv }, 0 },
2928 { MOD_TABLE (MOD_0FB2) },
2929 { "btrS", { Evh1, Gv }, 0 },
2930 { MOD_TABLE (MOD_0FB4) },
2931 { MOD_TABLE (MOD_0FB5) },
2932 { "movz{bR|x}", { Gv, Eb }, 0 },
2933 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2935 { PREFIX_TABLE (PREFIX_0FB8) },
2936 { "ud1", { XX }, 0 },
2937 { REG_TABLE (REG_0FBA) },
2938 { "btcS", { Evh1, Gv }, 0 },
2939 { PREFIX_TABLE (PREFIX_0FBC) },
2940 { PREFIX_TABLE (PREFIX_0FBD) },
2941 { "movs{bR|x}", { Gv, Eb }, 0 },
2942 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2944 { "xaddB", { Ebh1, Gb }, 0 },
2945 { "xaddS", { Evh1, Gv }, 0 },
2946 { PREFIX_TABLE (PREFIX_0FC2) },
2947 { PREFIX_TABLE (PREFIX_0FC3) },
2948 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
2949 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
2950 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
2951 { REG_TABLE (REG_0FC7) },
2953 { "bswap", { RMeAX }, 0 },
2954 { "bswap", { RMeCX }, 0 },
2955 { "bswap", { RMeDX }, 0 },
2956 { "bswap", { RMeBX }, 0 },
2957 { "bswap", { RMeSP }, 0 },
2958 { "bswap", { RMeBP }, 0 },
2959 { "bswap", { RMeSI }, 0 },
2960 { "bswap", { RMeDI }, 0 },
2962 { PREFIX_TABLE (PREFIX_0FD0) },
2963 { "psrlw", { MX, EM }, PREFIX_OPCODE },
2964 { "psrld", { MX, EM }, PREFIX_OPCODE },
2965 { "psrlq", { MX, EM }, PREFIX_OPCODE },
2966 { "paddq", { MX, EM }, PREFIX_OPCODE },
2967 { "pmullw", { MX, EM }, PREFIX_OPCODE },
2968 { PREFIX_TABLE (PREFIX_0FD6) },
2969 { MOD_TABLE (MOD_0FD7) },
2971 { "psubusb", { MX, EM }, PREFIX_OPCODE },
2972 { "psubusw", { MX, EM }, PREFIX_OPCODE },
2973 { "pminub", { MX, EM }, PREFIX_OPCODE },
2974 { "pand", { MX, EM }, PREFIX_OPCODE },
2975 { "paddusb", { MX, EM }, PREFIX_OPCODE },
2976 { "paddusw", { MX, EM }, PREFIX_OPCODE },
2977 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
2978 { "pandn", { MX, EM }, PREFIX_OPCODE },
2980 { "pavgb", { MX, EM }, PREFIX_OPCODE },
2981 { "psraw", { MX, EM }, PREFIX_OPCODE },
2982 { "psrad", { MX, EM }, PREFIX_OPCODE },
2983 { "pavgw", { MX, EM }, PREFIX_OPCODE },
2984 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
2985 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
2986 { PREFIX_TABLE (PREFIX_0FE6) },
2987 { PREFIX_TABLE (PREFIX_0FE7) },
2989 { "psubsb", { MX, EM }, PREFIX_OPCODE },
2990 { "psubsw", { MX, EM }, PREFIX_OPCODE },
2991 { "pminsw", { MX, EM }, PREFIX_OPCODE },
2992 { "por", { MX, EM }, PREFIX_OPCODE },
2993 { "paddsb", { MX, EM }, PREFIX_OPCODE },
2994 { "paddsw", { MX, EM }, PREFIX_OPCODE },
2995 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
2996 { "pxor", { MX, EM }, PREFIX_OPCODE },
2998 { PREFIX_TABLE (PREFIX_0FF0) },
2999 { "psllw", { MX, EM }, PREFIX_OPCODE },
3000 { "pslld", { MX, EM }, PREFIX_OPCODE },
3001 { "psllq", { MX, EM }, PREFIX_OPCODE },
3002 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
3003 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
3004 { "psadbw", { MX, EM }, PREFIX_OPCODE },
3005 { PREFIX_TABLE (PREFIX_0FF7) },
3007 { "psubb", { MX, EM }, PREFIX_OPCODE },
3008 { "psubw", { MX, EM }, PREFIX_OPCODE },
3009 { "psubd", { MX, EM }, PREFIX_OPCODE },
3010 { "psubq", { MX, EM }, PREFIX_OPCODE },
3011 { "paddb", { MX, EM }, PREFIX_OPCODE },
3012 { "paddw", { MX, EM }, PREFIX_OPCODE },
3013 { "paddd", { MX, EM }, PREFIX_OPCODE },
3017 static const unsigned char onebyte_has_modrm[256] = {
3018 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3019 /* ------------------------------- */
3020 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3021 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3022 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3023 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3024 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3025 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3026 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3027 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3028 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3029 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3030 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3031 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3032 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3033 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3034 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3035 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3036 /* ------------------------------- */
3037 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3040 static const unsigned char twobyte_has_modrm[256] = {
3041 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3042 /* ------------------------------- */
3043 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3044 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3045 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3046 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3047 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3048 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3049 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3050 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3051 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3052 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3053 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3054 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3055 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3056 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3057 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3058 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3059 /* ------------------------------- */
3060 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3063 static char obuf[100];
3065 static char *mnemonicendp;
3066 static char scratchbuf[100];
3067 static unsigned char *start_codep;
3068 static unsigned char *insn_codep;
3069 static unsigned char *codep;
3070 static unsigned char *end_codep;
3071 static int last_lock_prefix;
3072 static int last_repz_prefix;
3073 static int last_repnz_prefix;
3074 static int last_data_prefix;
3075 static int last_addr_prefix;
3076 static int last_rex_prefix;
3077 static int last_seg_prefix;
3078 static int fwait_prefix;
3079 /* The active segment register prefix. */
3080 static int active_seg_prefix;
3081 #define MAX_CODE_LENGTH 15
3082 /* We can up to 14 prefixes since the maximum instruction length is
3084 static int all_prefixes[MAX_CODE_LENGTH - 1];
3085 static disassemble_info *the_info;
3093 static unsigned char need_modrm;
3103 int register_specifier;
3110 int mask_register_specifier;
3116 static unsigned char need_vex;
3117 static unsigned char need_vex_reg;
3118 static unsigned char vex_w_done;
3126 /* If we are accessing mod/rm/reg without need_modrm set, then the
3127 values are stale. Hitting this abort likely indicates that you
3128 need to update onebyte_has_modrm or twobyte_has_modrm. */
3129 #define MODRM_CHECK if (!need_modrm) abort ()
3131 static const char **names64;
3132 static const char **names32;
3133 static const char **names16;
3134 static const char **names8;
3135 static const char **names8rex;
3136 static const char **names_seg;
3137 static const char *index64;
3138 static const char *index32;
3139 static const char **index16;
3140 static const char **names_bnd;
3142 static const char *intel_names64[] = {
3143 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3144 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3146 static const char *intel_names32[] = {
3147 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3148 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3150 static const char *intel_names16[] = {
3151 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3152 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3154 static const char *intel_names8[] = {
3155 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3157 static const char *intel_names8rex[] = {
3158 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3159 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3161 static const char *intel_names_seg[] = {
3162 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3164 static const char *intel_index64 = "riz";
3165 static const char *intel_index32 = "eiz";
3166 static const char *intel_index16[] = {
3167 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3170 static const char *att_names64[] = {
3171 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3172 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3174 static const char *att_names32[] = {
3175 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3176 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3178 static const char *att_names16[] = {
3179 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3180 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3182 static const char *att_names8[] = {
3183 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3185 static const char *att_names8rex[] = {
3186 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3187 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3189 static const char *att_names_seg[] = {
3190 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3192 static const char *att_index64 = "%riz";
3193 static const char *att_index32 = "%eiz";
3194 static const char *att_index16[] = {
3195 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3198 static const char **names_mm;
3199 static const char *intel_names_mm[] = {
3200 "mm0", "mm1", "mm2", "mm3",
3201 "mm4", "mm5", "mm6", "mm7"
3203 static const char *att_names_mm[] = {
3204 "%mm0", "%mm1", "%mm2", "%mm3",
3205 "%mm4", "%mm5", "%mm6", "%mm7"
3208 static const char *intel_names_bnd[] = {
3209 "bnd0", "bnd1", "bnd2", "bnd3"
3212 static const char *att_names_bnd[] = {
3213 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3216 static const char **names_xmm;
3217 static const char *intel_names_xmm[] = {
3218 "xmm0", "xmm1", "xmm2", "xmm3",
3219 "xmm4", "xmm5", "xmm6", "xmm7",
3220 "xmm8", "xmm9", "xmm10", "xmm11",
3221 "xmm12", "xmm13", "xmm14", "xmm15",
3222 "xmm16", "xmm17", "xmm18", "xmm19",
3223 "xmm20", "xmm21", "xmm22", "xmm23",
3224 "xmm24", "xmm25", "xmm26", "xmm27",
3225 "xmm28", "xmm29", "xmm30", "xmm31"
3227 static const char *att_names_xmm[] = {
3228 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3229 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3230 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3231 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3232 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3233 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3234 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3235 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3238 static const char **names_ymm;
3239 static const char *intel_names_ymm[] = {
3240 "ymm0", "ymm1", "ymm2", "ymm3",
3241 "ymm4", "ymm5", "ymm6", "ymm7",
3242 "ymm8", "ymm9", "ymm10", "ymm11",
3243 "ymm12", "ymm13", "ymm14", "ymm15",
3244 "ymm16", "ymm17", "ymm18", "ymm19",
3245 "ymm20", "ymm21", "ymm22", "ymm23",
3246 "ymm24", "ymm25", "ymm26", "ymm27",
3247 "ymm28", "ymm29", "ymm30", "ymm31"
3249 static const char *att_names_ymm[] = {
3250 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3251 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3252 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3253 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3254 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3255 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3256 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3257 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3260 static const char **names_zmm;
3261 static const char *intel_names_zmm[] = {
3262 "zmm0", "zmm1", "zmm2", "zmm3",
3263 "zmm4", "zmm5", "zmm6", "zmm7",
3264 "zmm8", "zmm9", "zmm10", "zmm11",
3265 "zmm12", "zmm13", "zmm14", "zmm15",
3266 "zmm16", "zmm17", "zmm18", "zmm19",
3267 "zmm20", "zmm21", "zmm22", "zmm23",
3268 "zmm24", "zmm25", "zmm26", "zmm27",
3269 "zmm28", "zmm29", "zmm30", "zmm31"
3271 static const char *att_names_zmm[] = {
3272 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3273 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3274 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3275 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3276 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3277 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3278 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3279 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3282 static const char **names_mask;
3283 static const char *intel_names_mask[] = {
3284 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3286 static const char *att_names_mask[] = {
3287 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3290 static const char *names_rounding[] =
3298 static const struct dis386 reg_table[][8] = {
3301 { "addA", { Ebh1, Ib }, 0 },
3302 { "orA", { Ebh1, Ib }, 0 },
3303 { "adcA", { Ebh1, Ib }, 0 },
3304 { "sbbA", { Ebh1, Ib }, 0 },
3305 { "andA", { Ebh1, Ib }, 0 },
3306 { "subA", { Ebh1, Ib }, 0 },
3307 { "xorA", { Ebh1, Ib }, 0 },
3308 { "cmpA", { Eb, Ib }, 0 },
3312 { "addQ", { Evh1, Iv }, 0 },
3313 { "orQ", { Evh1, Iv }, 0 },
3314 { "adcQ", { Evh1, Iv }, 0 },
3315 { "sbbQ", { Evh1, Iv }, 0 },
3316 { "andQ", { Evh1, Iv }, 0 },
3317 { "subQ", { Evh1, Iv }, 0 },
3318 { "xorQ", { Evh1, Iv }, 0 },
3319 { "cmpQ", { Ev, Iv }, 0 },
3323 { "addQ", { Evh1, sIb }, 0 },
3324 { "orQ", { Evh1, sIb }, 0 },
3325 { "adcQ", { Evh1, sIb }, 0 },
3326 { "sbbQ", { Evh1, sIb }, 0 },
3327 { "andQ", { Evh1, sIb }, 0 },
3328 { "subQ", { Evh1, sIb }, 0 },
3329 { "xorQ", { Evh1, sIb }, 0 },
3330 { "cmpQ", { Ev, sIb }, 0 },
3334 { "popU", { stackEv }, 0 },
3335 { XOP_8F_TABLE (XOP_09) },
3339 { XOP_8F_TABLE (XOP_09) },
3343 { "rolA", { Eb, Ib }, 0 },
3344 { "rorA", { Eb, Ib }, 0 },
3345 { "rclA", { Eb, Ib }, 0 },
3346 { "rcrA", { Eb, Ib }, 0 },
3347 { "shlA", { Eb, Ib }, 0 },
3348 { "shrA", { Eb, Ib }, 0 },
3350 { "sarA", { Eb, Ib }, 0 },
3354 { "rolQ", { Ev, Ib }, 0 },
3355 { "rorQ", { Ev, Ib }, 0 },
3356 { "rclQ", { Ev, Ib }, 0 },
3357 { "rcrQ", { Ev, Ib }, 0 },
3358 { "shlQ", { Ev, Ib }, 0 },
3359 { "shrQ", { Ev, Ib }, 0 },
3361 { "sarQ", { Ev, Ib }, 0 },
3365 { "movA", { Ebh3, Ib }, 0 },
3372 { MOD_TABLE (MOD_C6_REG_7) },
3376 { "movQ", { Evh3, Iv }, 0 },
3383 { MOD_TABLE (MOD_C7_REG_7) },
3387 { "rolA", { Eb, I1 }, 0 },
3388 { "rorA", { Eb, I1 }, 0 },
3389 { "rclA", { Eb, I1 }, 0 },
3390 { "rcrA", { Eb, I1 }, 0 },
3391 { "shlA", { Eb, I1 }, 0 },
3392 { "shrA", { Eb, I1 }, 0 },
3394 { "sarA", { Eb, I1 }, 0 },
3398 { "rolQ", { Ev, I1 }, 0 },
3399 { "rorQ", { Ev, I1 }, 0 },
3400 { "rclQ", { Ev, I1 }, 0 },
3401 { "rcrQ", { Ev, I1 }, 0 },
3402 { "shlQ", { Ev, I1 }, 0 },
3403 { "shrQ", { Ev, I1 }, 0 },
3405 { "sarQ", { Ev, I1 }, 0 },
3409 { "rolA", { Eb, CL }, 0 },
3410 { "rorA", { Eb, CL }, 0 },
3411 { "rclA", { Eb, CL }, 0 },
3412 { "rcrA", { Eb, CL }, 0 },
3413 { "shlA", { Eb, CL }, 0 },
3414 { "shrA", { Eb, CL }, 0 },
3416 { "sarA", { Eb, CL }, 0 },
3420 { "rolQ", { Ev, CL }, 0 },
3421 { "rorQ", { Ev, CL }, 0 },
3422 { "rclQ", { Ev, CL }, 0 },
3423 { "rcrQ", { Ev, CL }, 0 },
3424 { "shlQ", { Ev, CL }, 0 },
3425 { "shrQ", { Ev, CL }, 0 },
3427 { "sarQ", { Ev, CL }, 0 },
3431 { "testA", { Eb, Ib }, 0 },
3433 { "notA", { Ebh1 }, 0 },
3434 { "negA", { Ebh1 }, 0 },
3435 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
3436 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
3437 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
3438 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
3442 { "testQ", { Ev, Iv }, 0 },
3444 { "notQ", { Evh1 }, 0 },
3445 { "negQ", { Evh1 }, 0 },
3446 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
3447 { "imulQ", { Ev }, 0 },
3448 { "divQ", { Ev }, 0 },
3449 { "idivQ", { Ev }, 0 },
3453 { "incA", { Ebh1 }, 0 },
3454 { "decA", { Ebh1 }, 0 },
3458 { "incQ", { Evh1 }, 0 },
3459 { "decQ", { Evh1 }, 0 },
3460 { "call{T|}", { indirEv, BND }, 0 },
3461 { MOD_TABLE (MOD_FF_REG_3) },
3462 { "jmp{T|}", { indirEv, BND }, 0 },
3463 { MOD_TABLE (MOD_FF_REG_5) },
3464 { "pushU", { stackEv }, 0 },
3469 { "sldtD", { Sv }, 0 },
3470 { "strD", { Sv }, 0 },
3471 { "lldt", { Ew }, 0 },
3472 { "ltr", { Ew }, 0 },
3473 { "verr", { Ew }, 0 },
3474 { "verw", { Ew }, 0 },
3480 { MOD_TABLE (MOD_0F01_REG_0) },
3481 { MOD_TABLE (MOD_0F01_REG_1) },
3482 { MOD_TABLE (MOD_0F01_REG_2) },
3483 { MOD_TABLE (MOD_0F01_REG_3) },
3484 { "smswD", { Sv }, 0 },
3486 { "lmsw", { Ew }, 0 },
3487 { MOD_TABLE (MOD_0F01_REG_7) },
3491 { "prefetch", { Mb }, 0 },
3492 { "prefetchw", { Mb }, 0 },
3493 { "prefetchwt1", { Mb }, 0 },
3494 { "prefetch", { Mb }, 0 },
3495 { "prefetch", { Mb }, 0 },
3496 { "prefetch", { Mb }, 0 },
3497 { "prefetch", { Mb }, 0 },
3498 { "prefetch", { Mb }, 0 },
3502 { MOD_TABLE (MOD_0F18_REG_0) },
3503 { MOD_TABLE (MOD_0F18_REG_1) },
3504 { MOD_TABLE (MOD_0F18_REG_2) },
3505 { MOD_TABLE (MOD_0F18_REG_3) },
3506 { MOD_TABLE (MOD_0F18_REG_4) },
3507 { MOD_TABLE (MOD_0F18_REG_5) },
3508 { MOD_TABLE (MOD_0F18_REG_6) },
3509 { MOD_TABLE (MOD_0F18_REG_7) },
3515 { MOD_TABLE (MOD_0F71_REG_2) },
3517 { MOD_TABLE (MOD_0F71_REG_4) },
3519 { MOD_TABLE (MOD_0F71_REG_6) },
3525 { MOD_TABLE (MOD_0F72_REG_2) },
3527 { MOD_TABLE (MOD_0F72_REG_4) },
3529 { MOD_TABLE (MOD_0F72_REG_6) },
3535 { MOD_TABLE (MOD_0F73_REG_2) },
3536 { MOD_TABLE (MOD_0F73_REG_3) },
3539 { MOD_TABLE (MOD_0F73_REG_6) },
3540 { MOD_TABLE (MOD_0F73_REG_7) },
3544 { "montmul", { { OP_0f07, 0 } }, 0 },
3545 { "xsha1", { { OP_0f07, 0 } }, 0 },
3546 { "xsha256", { { OP_0f07, 0 } }, 0 },
3550 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
3551 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
3552 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
3553 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
3554 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
3555 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
3559 { MOD_TABLE (MOD_0FAE_REG_0) },
3560 { MOD_TABLE (MOD_0FAE_REG_1) },
3561 { MOD_TABLE (MOD_0FAE_REG_2) },
3562 { MOD_TABLE (MOD_0FAE_REG_3) },
3563 { MOD_TABLE (MOD_0FAE_REG_4) },
3564 { MOD_TABLE (MOD_0FAE_REG_5) },
3565 { MOD_TABLE (MOD_0FAE_REG_6) },
3566 { MOD_TABLE (MOD_0FAE_REG_7) },
3574 { "btQ", { Ev, Ib }, 0 },
3575 { "btsQ", { Evh1, Ib }, 0 },
3576 { "btrQ", { Evh1, Ib }, 0 },
3577 { "btcQ", { Evh1, Ib }, 0 },
3582 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3584 { MOD_TABLE (MOD_0FC7_REG_3) },
3585 { MOD_TABLE (MOD_0FC7_REG_4) },
3586 { MOD_TABLE (MOD_0FC7_REG_5) },
3587 { MOD_TABLE (MOD_0FC7_REG_6) },
3588 { MOD_TABLE (MOD_0FC7_REG_7) },
3594 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3596 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3598 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3604 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3606 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3608 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3614 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3615 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3618 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3619 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3625 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3626 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3628 /* REG_VEX_0F38F3 */
3631 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3632 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3633 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3637 { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3638 { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3642 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3643 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3645 /* REG_XOP_TBM_01 */
3648 { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3649 { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3650 { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 },
3651 { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3652 { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 },
3653 { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 },
3654 { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3656 /* REG_XOP_TBM_02 */
3659 { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3664 { "blci", { { OP_LWP_E, 0 }, Ev }, 0 },
3666 #define NEED_REG_TABLE
3667 #include "i386-dis-evex.h"
3668 #undef NEED_REG_TABLE
3671 static const struct dis386 prefix_table[][4] = {
3674 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3675 { "pause", { XX }, 0 },
3676 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3677 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3682 { "movups", { XM, EXx }, PREFIX_OPCODE },
3683 { "movss", { XM, EXd }, PREFIX_OPCODE },
3684 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3685 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3690 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3691 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3692 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3693 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3698 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3699 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3700 { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3701 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3706 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3707 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3708 { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3713 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3714 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3715 { "bndmov", { Gbnd, Ebnd }, 0 },
3716 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3721 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3722 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3723 { "bndmov", { Ebnd, Gbnd }, 0 },
3724 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3729 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3730 { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3731 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3732 { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3737 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3738 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3739 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3740 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3745 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3746 { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3747 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3748 { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3753 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3754 { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3755 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3756 { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3761 { "ucomiss",{ XM, EXd }, 0 },
3763 { "ucomisd",{ XM, EXq }, 0 },
3768 { "comiss", { XM, EXd }, 0 },
3770 { "comisd", { XM, EXq }, 0 },
3775 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3776 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3777 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3778 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3783 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3784 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3789 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3790 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3795 { "addps", { XM, EXx }, PREFIX_OPCODE },
3796 { "addss", { XM, EXd }, PREFIX_OPCODE },
3797 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3798 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3803 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3804 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3805 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3806 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3811 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3812 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3813 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3814 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3819 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3820 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3821 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3826 { "subps", { XM, EXx }, PREFIX_OPCODE },
3827 { "subss", { XM, EXd }, PREFIX_OPCODE },
3828 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3829 { "subsd", { XM, EXq }, PREFIX_OPCODE },
3834 { "minps", { XM, EXx }, PREFIX_OPCODE },
3835 { "minss", { XM, EXd }, PREFIX_OPCODE },
3836 { "minpd", { XM, EXx }, PREFIX_OPCODE },
3837 { "minsd", { XM, EXq }, PREFIX_OPCODE },
3842 { "divps", { XM, EXx }, PREFIX_OPCODE },
3843 { "divss", { XM, EXd }, PREFIX_OPCODE },
3844 { "divpd", { XM, EXx }, PREFIX_OPCODE },
3845 { "divsd", { XM, EXq }, PREFIX_OPCODE },
3850 { "maxps", { XM, EXx }, PREFIX_OPCODE },
3851 { "maxss", { XM, EXd }, PREFIX_OPCODE },
3852 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
3853 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
3858 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3860 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3865 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3867 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3872 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3874 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3881 { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3888 { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3893 { "movq", { MX, EM }, PREFIX_OPCODE },
3894 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3895 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3900 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3901 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3902 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3903 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3906 /* PREFIX_0F73_REG_3 */
3910 { "psrldq", { XS, Ib }, 0 },
3913 /* PREFIX_0F73_REG_7 */
3917 { "pslldq", { XS, Ib }, 0 },
3922 {"vmread", { Em, Gm }, 0 },
3924 {"extrq", { XS, Ib, Ib }, 0 },
3925 {"insertq", { XM, XS, Ib, Ib }, 0 },
3930 {"vmwrite", { Gm, Em }, 0 },
3932 {"extrq", { XM, XS }, 0 },
3933 {"insertq", { XM, XS }, 0 },
3940 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3941 { "haddps", { XM, EXx }, PREFIX_OPCODE },
3948 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3949 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3954 { "movK", { Edq, MX }, PREFIX_OPCODE },
3955 { "movq", { XM, EXq }, PREFIX_OPCODE },
3956 { "movK", { Edq, XM }, PREFIX_OPCODE },
3961 { "movq", { EMS, MX }, PREFIX_OPCODE },
3962 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3963 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3966 /* PREFIX_0FAE_REG_0 */
3969 { "rdfsbase", { Ev }, 0 },
3972 /* PREFIX_0FAE_REG_1 */
3975 { "rdgsbase", { Ev }, 0 },
3978 /* PREFIX_0FAE_REG_2 */
3981 { "wrfsbase", { Ev }, 0 },
3984 /* PREFIX_0FAE_REG_3 */
3987 { "wrgsbase", { Ev }, 0 },
3990 /* PREFIX_0FAE_REG_6 */
3992 { "xsaveopt", { FXSAVE }, 0 },
3994 { "clwb", { Mb }, 0 },
3997 /* PREFIX_0FAE_REG_7 */
3999 { "clflush", { Mb }, 0 },
4001 { "clflushopt", { Mb }, 0 },
4004 /* PREFIX_RM_0_0FAE_REG_7 */
4006 { "sfence", { Skip_MODRM }, 0 },
4008 { "pcommit", { Skip_MODRM }, 0 },
4014 { "popcntS", { Gv, Ev }, 0 },
4019 { "bsfS", { Gv, Ev }, 0 },
4020 { "tzcntS", { Gv, Ev }, 0 },
4021 { "bsfS", { Gv, Ev }, 0 },
4026 { "bsrS", { Gv, Ev }, 0 },
4027 { "lzcntS", { Gv, Ev }, 0 },
4028 { "bsrS", { Gv, Ev }, 0 },
4033 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
4034 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
4035 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
4036 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
4041 { "movntiS", { Ma, Gv }, PREFIX_OPCODE },
4044 /* PREFIX_MOD_0_0FC7_REG_6 */
4046 { "vmptrld",{ Mq }, 0 },
4047 { "vmxon", { Mq }, 0 },
4048 { "vmclear",{ Mq }, 0 },
4051 /* PREFIX_MOD_3_0FC7_REG_6 */
4053 { "rdrand", { Ev }, 0 },
4055 { "rdrand", { Ev }, 0 }
4058 /* PREFIX_MOD_3_0FC7_REG_7 */
4060 { "rdseed", { Ev }, 0 },
4062 { "rdseed", { Ev }, 0 },
4069 { "addsubpd", { XM, EXx }, 0 },
4070 { "addsubps", { XM, EXx }, 0 },
4076 { "movq2dq",{ XM, MS }, 0 },
4077 { "movq", { EXqS, XM }, 0 },
4078 { "movdq2q",{ MX, XS }, 0 },
4084 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4085 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4086 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4091 { "movntq", { Mq, MX }, PREFIX_OPCODE },
4093 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4101 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4106 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4108 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4115 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4122 { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4129 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4136 { "ptest", { XM, EXx }, PREFIX_OPCODE },
4143 { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4150 { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4157 { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4164 { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4171 { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4178 { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4185 { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4192 { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4199 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4206 { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4213 { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4220 { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4227 { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4234 { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4241 { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4248 { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4255 { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4262 { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4269 { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4276 { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4283 { "pminud", { XM, EXx }, PREFIX_OPCODE },
4290 { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4297 { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4304 { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4311 { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4318 { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4325 { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4332 { "invept", { Gm, Mo }, PREFIX_OPCODE },
4339 { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4346 { "invpcid", { Gm, M }, PREFIX_OPCODE },
4351 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4356 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4361 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4366 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4371 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4376 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4383 { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4390 { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4397 { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4404 { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4411 { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4416 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4418 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4419 { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4424 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4426 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4427 { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4433 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
4434 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
4442 { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4449 { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4456 { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4463 { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4470 { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4477 { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4484 { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4491 { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4498 { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4505 { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4512 { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4519 { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4526 { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4533 { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4540 { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE },
4547 { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE },
4554 { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4561 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4568 { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4575 { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE },
4582 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4589 { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4594 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4601 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4604 /* PREFIX_VEX_0F10 */
4606 { VEX_W_TABLE (VEX_W_0F10_P_0) },
4607 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4608 { VEX_W_TABLE (VEX_W_0F10_P_2) },
4609 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4612 /* PREFIX_VEX_0F11 */
4614 { VEX_W_TABLE (VEX_W_0F11_P_0) },
4615 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4616 { VEX_W_TABLE (VEX_W_0F11_P_2) },
4617 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4620 /* PREFIX_VEX_0F12 */
4622 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4623 { VEX_W_TABLE (VEX_W_0F12_P_1) },
4624 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4625 { VEX_W_TABLE (VEX_W_0F12_P_3) },
4628 /* PREFIX_VEX_0F16 */
4630 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4631 { VEX_W_TABLE (VEX_W_0F16_P_1) },
4632 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4635 /* PREFIX_VEX_0F2A */
4638 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4640 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4643 /* PREFIX_VEX_0F2C */
4646 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4648 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4651 /* PREFIX_VEX_0F2D */
4654 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4656 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4659 /* PREFIX_VEX_0F2E */
4661 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4663 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4666 /* PREFIX_VEX_0F2F */
4668 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4670 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4673 /* PREFIX_VEX_0F41 */
4675 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4677 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4680 /* PREFIX_VEX_0F42 */
4682 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4684 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4687 /* PREFIX_VEX_0F44 */
4689 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4691 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4694 /* PREFIX_VEX_0F45 */
4696 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4698 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4701 /* PREFIX_VEX_0F46 */
4703 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4705 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4708 /* PREFIX_VEX_0F47 */
4710 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4712 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4715 /* PREFIX_VEX_0F4A */
4717 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4719 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4722 /* PREFIX_VEX_0F4B */
4724 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4726 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4729 /* PREFIX_VEX_0F51 */
4731 { VEX_W_TABLE (VEX_W_0F51_P_0) },
4732 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4733 { VEX_W_TABLE (VEX_W_0F51_P_2) },
4734 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4737 /* PREFIX_VEX_0F52 */
4739 { VEX_W_TABLE (VEX_W_0F52_P_0) },
4740 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4743 /* PREFIX_VEX_0F53 */
4745 { VEX_W_TABLE (VEX_W_0F53_P_0) },
4746 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4749 /* PREFIX_VEX_0F58 */
4751 { VEX_W_TABLE (VEX_W_0F58_P_0) },
4752 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4753 { VEX_W_TABLE (VEX_W_0F58_P_2) },
4754 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4757 /* PREFIX_VEX_0F59 */
4759 { VEX_W_TABLE (VEX_W_0F59_P_0) },
4760 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4761 { VEX_W_TABLE (VEX_W_0F59_P_2) },
4762 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4765 /* PREFIX_VEX_0F5A */
4767 { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4768 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4769 { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4770 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4773 /* PREFIX_VEX_0F5B */
4775 { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4776 { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4777 { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4780 /* PREFIX_VEX_0F5C */
4782 { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4783 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4784 { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4785 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4788 /* PREFIX_VEX_0F5D */
4790 { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4791 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4792 { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4793 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4796 /* PREFIX_VEX_0F5E */
4798 { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4799 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4800 { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4801 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4804 /* PREFIX_VEX_0F5F */
4806 { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4807 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4808 { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4809 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4812 /* PREFIX_VEX_0F60 */
4816 { VEX_W_TABLE (VEX_W_0F60_P_2) },
4819 /* PREFIX_VEX_0F61 */
4823 { VEX_W_TABLE (VEX_W_0F61_P_2) },
4826 /* PREFIX_VEX_0F62 */
4830 { VEX_W_TABLE (VEX_W_0F62_P_2) },
4833 /* PREFIX_VEX_0F63 */
4837 { VEX_W_TABLE (VEX_W_0F63_P_2) },
4840 /* PREFIX_VEX_0F64 */
4844 { VEX_W_TABLE (VEX_W_0F64_P_2) },
4847 /* PREFIX_VEX_0F65 */
4851 { VEX_W_TABLE (VEX_W_0F65_P_2) },
4854 /* PREFIX_VEX_0F66 */
4858 { VEX_W_TABLE (VEX_W_0F66_P_2) },
4861 /* PREFIX_VEX_0F67 */
4865 { VEX_W_TABLE (VEX_W_0F67_P_2) },
4868 /* PREFIX_VEX_0F68 */
4872 { VEX_W_TABLE (VEX_W_0F68_P_2) },
4875 /* PREFIX_VEX_0F69 */
4879 { VEX_W_TABLE (VEX_W_0F69_P_2) },
4882 /* PREFIX_VEX_0F6A */
4886 { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4889 /* PREFIX_VEX_0F6B */
4893 { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4896 /* PREFIX_VEX_0F6C */
4900 { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4903 /* PREFIX_VEX_0F6D */
4907 { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4910 /* PREFIX_VEX_0F6E */
4914 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4917 /* PREFIX_VEX_0F6F */
4920 { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4921 { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4924 /* PREFIX_VEX_0F70 */
4927 { VEX_W_TABLE (VEX_W_0F70_P_1) },
4928 { VEX_W_TABLE (VEX_W_0F70_P_2) },
4929 { VEX_W_TABLE (VEX_W_0F70_P_3) },
4932 /* PREFIX_VEX_0F71_REG_2 */
4936 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4939 /* PREFIX_VEX_0F71_REG_4 */
4943 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4946 /* PREFIX_VEX_0F71_REG_6 */
4950 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4953 /* PREFIX_VEX_0F72_REG_2 */
4957 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4960 /* PREFIX_VEX_0F72_REG_4 */
4964 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4967 /* PREFIX_VEX_0F72_REG_6 */
4971 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4974 /* PREFIX_VEX_0F73_REG_2 */
4978 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4981 /* PREFIX_VEX_0F73_REG_3 */
4985 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4988 /* PREFIX_VEX_0F73_REG_6 */
4992 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4995 /* PREFIX_VEX_0F73_REG_7 */
4999 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5002 /* PREFIX_VEX_0F74 */
5006 { VEX_W_TABLE (VEX_W_0F74_P_2) },
5009 /* PREFIX_VEX_0F75 */
5013 { VEX_W_TABLE (VEX_W_0F75_P_2) },
5016 /* PREFIX_VEX_0F76 */
5020 { VEX_W_TABLE (VEX_W_0F76_P_2) },
5023 /* PREFIX_VEX_0F77 */
5025 { VEX_W_TABLE (VEX_W_0F77_P_0) },
5028 /* PREFIX_VEX_0F7C */
5032 { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5033 { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5036 /* PREFIX_VEX_0F7D */
5040 { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5041 { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5044 /* PREFIX_VEX_0F7E */
5047 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5048 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5051 /* PREFIX_VEX_0F7F */
5054 { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5055 { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5058 /* PREFIX_VEX_0F90 */
5060 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5062 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5065 /* PREFIX_VEX_0F91 */
5067 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5069 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5072 /* PREFIX_VEX_0F92 */
5074 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5076 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5077 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5080 /* PREFIX_VEX_0F93 */
5082 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5084 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5085 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5088 /* PREFIX_VEX_0F98 */
5090 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5092 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5095 /* PREFIX_VEX_0F99 */
5097 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5099 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5102 /* PREFIX_VEX_0FC2 */
5104 { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5105 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5106 { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5107 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5110 /* PREFIX_VEX_0FC4 */
5114 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5117 /* PREFIX_VEX_0FC5 */
5121 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5124 /* PREFIX_VEX_0FD0 */
5128 { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5129 { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5132 /* PREFIX_VEX_0FD1 */
5136 { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5139 /* PREFIX_VEX_0FD2 */
5143 { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5146 /* PREFIX_VEX_0FD3 */
5150 { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5153 /* PREFIX_VEX_0FD4 */
5157 { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5160 /* PREFIX_VEX_0FD5 */
5164 { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5167 /* PREFIX_VEX_0FD6 */
5171 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5174 /* PREFIX_VEX_0FD7 */
5178 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5181 /* PREFIX_VEX_0FD8 */
5185 { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5188 /* PREFIX_VEX_0FD9 */
5192 { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5195 /* PREFIX_VEX_0FDA */
5199 { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5202 /* PREFIX_VEX_0FDB */
5206 { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5209 /* PREFIX_VEX_0FDC */
5213 { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5216 /* PREFIX_VEX_0FDD */
5220 { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5223 /* PREFIX_VEX_0FDE */
5227 { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5230 /* PREFIX_VEX_0FDF */
5234 { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5237 /* PREFIX_VEX_0FE0 */
5241 { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5244 /* PREFIX_VEX_0FE1 */
5248 { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5251 /* PREFIX_VEX_0FE2 */
5255 { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5258 /* PREFIX_VEX_0FE3 */
5262 { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5265 /* PREFIX_VEX_0FE4 */
5269 { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5272 /* PREFIX_VEX_0FE5 */
5276 { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5279 /* PREFIX_VEX_0FE6 */
5282 { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5283 { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5284 { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5287 /* PREFIX_VEX_0FE7 */
5291 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5294 /* PREFIX_VEX_0FE8 */
5298 { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5301 /* PREFIX_VEX_0FE9 */
5305 { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5308 /* PREFIX_VEX_0FEA */
5312 { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5315 /* PREFIX_VEX_0FEB */
5319 { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5322 /* PREFIX_VEX_0FEC */
5326 { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5329 /* PREFIX_VEX_0FED */
5333 { VEX_W_TABLE (VEX_W_0FED_P_2) },
5336 /* PREFIX_VEX_0FEE */
5340 { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5343 /* PREFIX_VEX_0FEF */
5347 { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5350 /* PREFIX_VEX_0FF0 */
5355 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5358 /* PREFIX_VEX_0FF1 */
5362 { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5365 /* PREFIX_VEX_0FF2 */
5369 { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5372 /* PREFIX_VEX_0FF3 */
5376 { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5379 /* PREFIX_VEX_0FF4 */
5383 { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5386 /* PREFIX_VEX_0FF5 */
5390 { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5393 /* PREFIX_VEX_0FF6 */
5397 { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5400 /* PREFIX_VEX_0FF7 */
5404 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5407 /* PREFIX_VEX_0FF8 */
5411 { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5414 /* PREFIX_VEX_0FF9 */
5418 { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5421 /* PREFIX_VEX_0FFA */
5425 { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5428 /* PREFIX_VEX_0FFB */
5432 { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5435 /* PREFIX_VEX_0FFC */
5439 { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5442 /* PREFIX_VEX_0FFD */
5446 { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5449 /* PREFIX_VEX_0FFE */
5453 { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5456 /* PREFIX_VEX_0F3800 */
5460 { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5463 /* PREFIX_VEX_0F3801 */
5467 { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5470 /* PREFIX_VEX_0F3802 */
5474 { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5477 /* PREFIX_VEX_0F3803 */
5481 { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5484 /* PREFIX_VEX_0F3804 */
5488 { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5491 /* PREFIX_VEX_0F3805 */
5495 { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5498 /* PREFIX_VEX_0F3806 */
5502 { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5505 /* PREFIX_VEX_0F3807 */
5509 { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5512 /* PREFIX_VEX_0F3808 */
5516 { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5519 /* PREFIX_VEX_0F3809 */
5523 { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5526 /* PREFIX_VEX_0F380A */
5530 { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5533 /* PREFIX_VEX_0F380B */
5537 { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5540 /* PREFIX_VEX_0F380C */
5544 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5547 /* PREFIX_VEX_0F380D */
5551 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5554 /* PREFIX_VEX_0F380E */
5558 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5561 /* PREFIX_VEX_0F380F */
5565 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5568 /* PREFIX_VEX_0F3813 */
5572 { "vcvtph2ps", { XM, EXxmmq }, 0 },
5575 /* PREFIX_VEX_0F3816 */
5579 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5582 /* PREFIX_VEX_0F3817 */
5586 { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5589 /* PREFIX_VEX_0F3818 */
5593 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5596 /* PREFIX_VEX_0F3819 */
5600 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5603 /* PREFIX_VEX_0F381A */
5607 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5610 /* PREFIX_VEX_0F381C */
5614 { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5617 /* PREFIX_VEX_0F381D */
5621 { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5624 /* PREFIX_VEX_0F381E */
5628 { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5631 /* PREFIX_VEX_0F3820 */
5635 { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5638 /* PREFIX_VEX_0F3821 */
5642 { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5645 /* PREFIX_VEX_0F3822 */
5649 { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5652 /* PREFIX_VEX_0F3823 */
5656 { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5659 /* PREFIX_VEX_0F3824 */
5663 { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5666 /* PREFIX_VEX_0F3825 */
5670 { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5673 /* PREFIX_VEX_0F3828 */
5677 { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5680 /* PREFIX_VEX_0F3829 */
5684 { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5687 /* PREFIX_VEX_0F382A */
5691 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5694 /* PREFIX_VEX_0F382B */
5698 { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5701 /* PREFIX_VEX_0F382C */
5705 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5708 /* PREFIX_VEX_0F382D */
5712 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5715 /* PREFIX_VEX_0F382E */
5719 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5722 /* PREFIX_VEX_0F382F */
5726 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5729 /* PREFIX_VEX_0F3830 */
5733 { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5736 /* PREFIX_VEX_0F3831 */
5740 { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5743 /* PREFIX_VEX_0F3832 */
5747 { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5750 /* PREFIX_VEX_0F3833 */
5754 { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5757 /* PREFIX_VEX_0F3834 */
5761 { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5764 /* PREFIX_VEX_0F3835 */
5768 { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5771 /* PREFIX_VEX_0F3836 */
5775 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5778 /* PREFIX_VEX_0F3837 */
5782 { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5785 /* PREFIX_VEX_0F3838 */
5789 { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5792 /* PREFIX_VEX_0F3839 */
5796 { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5799 /* PREFIX_VEX_0F383A */
5803 { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5806 /* PREFIX_VEX_0F383B */
5810 { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5813 /* PREFIX_VEX_0F383C */
5817 { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5820 /* PREFIX_VEX_0F383D */
5824 { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5827 /* PREFIX_VEX_0F383E */
5831 { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5834 /* PREFIX_VEX_0F383F */
5838 { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5841 /* PREFIX_VEX_0F3840 */
5845 { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5848 /* PREFIX_VEX_0F3841 */
5852 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5855 /* PREFIX_VEX_0F3845 */
5859 { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5862 /* PREFIX_VEX_0F3846 */
5866 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5869 /* PREFIX_VEX_0F3847 */
5873 { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5876 /* PREFIX_VEX_0F3858 */
5880 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5883 /* PREFIX_VEX_0F3859 */
5887 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5890 /* PREFIX_VEX_0F385A */
5894 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5897 /* PREFIX_VEX_0F3878 */
5901 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5904 /* PREFIX_VEX_0F3879 */
5908 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5911 /* PREFIX_VEX_0F388C */
5915 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5918 /* PREFIX_VEX_0F388E */
5922 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5925 /* PREFIX_VEX_0F3890 */
5929 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5932 /* PREFIX_VEX_0F3891 */
5936 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5939 /* PREFIX_VEX_0F3892 */
5943 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5946 /* PREFIX_VEX_0F3893 */
5950 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5953 /* PREFIX_VEX_0F3896 */
5957 { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
5960 /* PREFIX_VEX_0F3897 */
5964 { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
5967 /* PREFIX_VEX_0F3898 */
5971 { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
5974 /* PREFIX_VEX_0F3899 */
5978 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5981 /* PREFIX_VEX_0F389A */
5985 { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
5988 /* PREFIX_VEX_0F389B */
5992 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5995 /* PREFIX_VEX_0F389C */
5999 { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6002 /* PREFIX_VEX_0F389D */
6006 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6009 /* PREFIX_VEX_0F389E */
6013 { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6016 /* PREFIX_VEX_0F389F */
6020 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6023 /* PREFIX_VEX_0F38A6 */
6027 { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6031 /* PREFIX_VEX_0F38A7 */
6035 { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6038 /* PREFIX_VEX_0F38A8 */
6042 { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6045 /* PREFIX_VEX_0F38A9 */
6049 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6052 /* PREFIX_VEX_0F38AA */
6056 { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6059 /* PREFIX_VEX_0F38AB */
6063 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6066 /* PREFIX_VEX_0F38AC */
6070 { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6073 /* PREFIX_VEX_0F38AD */
6077 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6080 /* PREFIX_VEX_0F38AE */
6084 { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6087 /* PREFIX_VEX_0F38AF */
6091 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6094 /* PREFIX_VEX_0F38B6 */
6098 { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6101 /* PREFIX_VEX_0F38B7 */
6105 { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6108 /* PREFIX_VEX_0F38B8 */
6112 { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6115 /* PREFIX_VEX_0F38B9 */
6119 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6122 /* PREFIX_VEX_0F38BA */
6126 { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6129 /* PREFIX_VEX_0F38BB */
6133 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6136 /* PREFIX_VEX_0F38BC */
6140 { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6143 /* PREFIX_VEX_0F38BD */
6147 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6150 /* PREFIX_VEX_0F38BE */
6154 { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6157 /* PREFIX_VEX_0F38BF */
6161 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6164 /* PREFIX_VEX_0F38DB */
6168 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6171 /* PREFIX_VEX_0F38DC */
6175 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6178 /* PREFIX_VEX_0F38DD */
6182 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6185 /* PREFIX_VEX_0F38DE */
6189 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6192 /* PREFIX_VEX_0F38DF */
6196 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6199 /* PREFIX_VEX_0F38F2 */
6201 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6204 /* PREFIX_VEX_0F38F3_REG_1 */
6206 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6209 /* PREFIX_VEX_0F38F3_REG_2 */
6211 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6214 /* PREFIX_VEX_0F38F3_REG_3 */
6216 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6219 /* PREFIX_VEX_0F38F5 */
6221 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6222 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6224 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6227 /* PREFIX_VEX_0F38F6 */
6232 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6235 /* PREFIX_VEX_0F38F7 */
6237 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6238 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6239 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6240 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6243 /* PREFIX_VEX_0F3A00 */
6247 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6250 /* PREFIX_VEX_0F3A01 */
6254 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6257 /* PREFIX_VEX_0F3A02 */
6261 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6264 /* PREFIX_VEX_0F3A04 */
6268 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6271 /* PREFIX_VEX_0F3A05 */
6275 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6278 /* PREFIX_VEX_0F3A06 */
6282 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6285 /* PREFIX_VEX_0F3A08 */
6289 { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6292 /* PREFIX_VEX_0F3A09 */
6296 { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6299 /* PREFIX_VEX_0F3A0A */
6303 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6306 /* PREFIX_VEX_0F3A0B */
6310 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6313 /* PREFIX_VEX_0F3A0C */
6317 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6320 /* PREFIX_VEX_0F3A0D */
6324 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6327 /* PREFIX_VEX_0F3A0E */
6331 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6334 /* PREFIX_VEX_0F3A0F */
6338 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6341 /* PREFIX_VEX_0F3A14 */
6345 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6348 /* PREFIX_VEX_0F3A15 */
6352 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6355 /* PREFIX_VEX_0F3A16 */
6359 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6362 /* PREFIX_VEX_0F3A17 */
6366 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6369 /* PREFIX_VEX_0F3A18 */
6373 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6376 /* PREFIX_VEX_0F3A19 */
6380 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6383 /* PREFIX_VEX_0F3A1D */
6387 { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6390 /* PREFIX_VEX_0F3A20 */
6394 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6397 /* PREFIX_VEX_0F3A21 */
6401 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6404 /* PREFIX_VEX_0F3A22 */
6408 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6411 /* PREFIX_VEX_0F3A30 */
6415 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6418 /* PREFIX_VEX_0F3A31 */
6422 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6425 /* PREFIX_VEX_0F3A32 */
6429 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6432 /* PREFIX_VEX_0F3A33 */
6436 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6439 /* PREFIX_VEX_0F3A38 */
6443 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6446 /* PREFIX_VEX_0F3A39 */
6450 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6453 /* PREFIX_VEX_0F3A40 */
6457 { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6460 /* PREFIX_VEX_0F3A41 */
6464 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6467 /* PREFIX_VEX_0F3A42 */
6471 { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6474 /* PREFIX_VEX_0F3A44 */
6478 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6481 /* PREFIX_VEX_0F3A46 */
6485 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6488 /* PREFIX_VEX_0F3A48 */
6492 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6495 /* PREFIX_VEX_0F3A49 */
6499 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6502 /* PREFIX_VEX_0F3A4A */
6506 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6509 /* PREFIX_VEX_0F3A4B */
6513 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6516 /* PREFIX_VEX_0F3A4C */
6520 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6523 /* PREFIX_VEX_0F3A5C */
6527 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6530 /* PREFIX_VEX_0F3A5D */
6534 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6537 /* PREFIX_VEX_0F3A5E */
6541 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6544 /* PREFIX_VEX_0F3A5F */
6548 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6551 /* PREFIX_VEX_0F3A60 */
6555 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6559 /* PREFIX_VEX_0F3A61 */
6563 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6566 /* PREFIX_VEX_0F3A62 */
6570 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6573 /* PREFIX_VEX_0F3A63 */
6577 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6580 /* PREFIX_VEX_0F3A68 */
6584 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6587 /* PREFIX_VEX_0F3A69 */
6591 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6594 /* PREFIX_VEX_0F3A6A */
6598 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6601 /* PREFIX_VEX_0F3A6B */
6605 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6608 /* PREFIX_VEX_0F3A6C */
6612 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6615 /* PREFIX_VEX_0F3A6D */
6619 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6622 /* PREFIX_VEX_0F3A6E */
6626 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6629 /* PREFIX_VEX_0F3A6F */
6633 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6636 /* PREFIX_VEX_0F3A78 */
6640 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6643 /* PREFIX_VEX_0F3A79 */
6647 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6650 /* PREFIX_VEX_0F3A7A */
6654 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6657 /* PREFIX_VEX_0F3A7B */
6661 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6664 /* PREFIX_VEX_0F3A7C */
6668 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6672 /* PREFIX_VEX_0F3A7D */
6676 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6679 /* PREFIX_VEX_0F3A7E */
6683 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6686 /* PREFIX_VEX_0F3A7F */
6690 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6693 /* PREFIX_VEX_0F3ADF */
6697 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6700 /* PREFIX_VEX_0F3AF0 */
6705 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6708 #define NEED_PREFIX_TABLE
6709 #include "i386-dis-evex.h"
6710 #undef NEED_PREFIX_TABLE
6713 static const struct dis386 x86_64_table[][2] = {
6716 { "pushP", { es }, 0 },
6721 { "popP", { es }, 0 },
6726 { "pushP", { cs }, 0 },
6731 { "pushP", { ss }, 0 },
6736 { "popP", { ss }, 0 },
6741 { "pushP", { ds }, 0 },
6746 { "popP", { ds }, 0 },
6751 { "daa", { XX }, 0 },
6756 { "das", { XX }, 0 },
6761 { "aaa", { XX }, 0 },
6766 { "aas", { XX }, 0 },
6771 { "pushaP", { XX }, 0 },
6776 { "popaP", { XX }, 0 },
6781 { MOD_TABLE (MOD_62_32BIT) },
6782 { EVEX_TABLE (EVEX_0F) },
6787 { "arpl", { Ew, Gw }, 0 },
6788 { "movs{lq|xd}", { Gv, Ed }, 0 },
6793 { "ins{R|}", { Yzr, indirDX }, 0 },
6794 { "ins{G|}", { Yzr, indirDX }, 0 },
6799 { "outs{R|}", { indirDXr, Xz }, 0 },
6800 { "outs{G|}", { indirDXr, Xz }, 0 },
6805 { "Jcall{T|}", { Ap }, 0 },
6810 { MOD_TABLE (MOD_C4_32BIT) },
6811 { VEX_C4_TABLE (VEX_0F) },
6816 { MOD_TABLE (MOD_C5_32BIT) },
6817 { VEX_C5_TABLE (VEX_0F) },
6822 { "into", { XX }, 0 },
6827 { "aam", { Ib }, 0 },
6832 { "aad", { Ib }, 0 },
6837 { "Jjmp{T|}", { Ap }, 0 },
6840 /* X86_64_0F01_REG_0 */
6842 { "sgdt{Q|IQ}", { M }, 0 },
6843 { "sgdt", { M }, 0 },
6846 /* X86_64_0F01_REG_1 */
6848 { "sidt{Q|IQ}", { M }, 0 },
6849 { "sidt", { M }, 0 },
6852 /* X86_64_0F01_REG_2 */
6854 { "lgdt{Q|Q}", { M }, 0 },
6855 { "lgdt", { M }, 0 },
6858 /* X86_64_0F01_REG_3 */
6860 { "lidt{Q|Q}", { M }, 0 },
6861 { "lidt", { M }, 0 },
6865 static const struct dis386 three_byte_table[][256] = {
6867 /* THREE_BYTE_0F38 */
6870 { "pshufb", { MX, EM }, PREFIX_OPCODE },
6871 { "phaddw", { MX, EM }, PREFIX_OPCODE },
6872 { "phaddd", { MX, EM }, PREFIX_OPCODE },
6873 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
6874 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
6875 { "phsubw", { MX, EM }, PREFIX_OPCODE },
6876 { "phsubd", { MX, EM }, PREFIX_OPCODE },
6877 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
6879 { "psignb", { MX, EM }, PREFIX_OPCODE },
6880 { "psignw", { MX, EM }, PREFIX_OPCODE },
6881 { "psignd", { MX, EM }, PREFIX_OPCODE },
6882 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
6888 { PREFIX_TABLE (PREFIX_0F3810) },
6892 { PREFIX_TABLE (PREFIX_0F3814) },
6893 { PREFIX_TABLE (PREFIX_0F3815) },
6895 { PREFIX_TABLE (PREFIX_0F3817) },
6901 { "pabsb", { MX, EM }, PREFIX_OPCODE },
6902 { "pabsw", { MX, EM }, PREFIX_OPCODE },
6903 { "pabsd", { MX, EM }, PREFIX_OPCODE },
6906 { PREFIX_TABLE (PREFIX_0F3820) },
6907 { PREFIX_TABLE (PREFIX_0F3821) },
6908 { PREFIX_TABLE (PREFIX_0F3822) },
6909 { PREFIX_TABLE (PREFIX_0F3823) },
6910 { PREFIX_TABLE (PREFIX_0F3824) },
6911 { PREFIX_TABLE (PREFIX_0F3825) },
6915 { PREFIX_TABLE (PREFIX_0F3828) },
6916 { PREFIX_TABLE (PREFIX_0F3829) },
6917 { PREFIX_TABLE (PREFIX_0F382A) },
6918 { PREFIX_TABLE (PREFIX_0F382B) },
6924 { PREFIX_TABLE (PREFIX_0F3830) },
6925 { PREFIX_TABLE (PREFIX_0F3831) },
6926 { PREFIX_TABLE (PREFIX_0F3832) },
6927 { PREFIX_TABLE (PREFIX_0F3833) },
6928 { PREFIX_TABLE (PREFIX_0F3834) },
6929 { PREFIX_TABLE (PREFIX_0F3835) },
6931 { PREFIX_TABLE (PREFIX_0F3837) },
6933 { PREFIX_TABLE (PREFIX_0F3838) },
6934 { PREFIX_TABLE (PREFIX_0F3839) },
6935 { PREFIX_TABLE (PREFIX_0F383A) },
6936 { PREFIX_TABLE (PREFIX_0F383B) },
6937 { PREFIX_TABLE (PREFIX_0F383C) },
6938 { PREFIX_TABLE (PREFIX_0F383D) },
6939 { PREFIX_TABLE (PREFIX_0F383E) },
6940 { PREFIX_TABLE (PREFIX_0F383F) },
6942 { PREFIX_TABLE (PREFIX_0F3840) },
6943 { PREFIX_TABLE (PREFIX_0F3841) },
7014 { PREFIX_TABLE (PREFIX_0F3880) },
7015 { PREFIX_TABLE (PREFIX_0F3881) },
7016 { PREFIX_TABLE (PREFIX_0F3882) },
7095 { PREFIX_TABLE (PREFIX_0F38C8) },
7096 { PREFIX_TABLE (PREFIX_0F38C9) },
7097 { PREFIX_TABLE (PREFIX_0F38CA) },
7098 { PREFIX_TABLE (PREFIX_0F38CB) },
7099 { PREFIX_TABLE (PREFIX_0F38CC) },
7100 { PREFIX_TABLE (PREFIX_0F38CD) },
7116 { PREFIX_TABLE (PREFIX_0F38DB) },
7117 { PREFIX_TABLE (PREFIX_0F38DC) },
7118 { PREFIX_TABLE (PREFIX_0F38DD) },
7119 { PREFIX_TABLE (PREFIX_0F38DE) },
7120 { PREFIX_TABLE (PREFIX_0F38DF) },
7140 { PREFIX_TABLE (PREFIX_0F38F0) },
7141 { PREFIX_TABLE (PREFIX_0F38F1) },
7146 { PREFIX_TABLE (PREFIX_0F38F6) },
7158 /* THREE_BYTE_0F3A */
7170 { PREFIX_TABLE (PREFIX_0F3A08) },
7171 { PREFIX_TABLE (PREFIX_0F3A09) },
7172 { PREFIX_TABLE (PREFIX_0F3A0A) },
7173 { PREFIX_TABLE (PREFIX_0F3A0B) },
7174 { PREFIX_TABLE (PREFIX_0F3A0C) },
7175 { PREFIX_TABLE (PREFIX_0F3A0D) },
7176 { PREFIX_TABLE (PREFIX_0F3A0E) },
7177 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
7183 { PREFIX_TABLE (PREFIX_0F3A14) },
7184 { PREFIX_TABLE (PREFIX_0F3A15) },
7185 { PREFIX_TABLE (PREFIX_0F3A16) },
7186 { PREFIX_TABLE (PREFIX_0F3A17) },
7197 { PREFIX_TABLE (PREFIX_0F3A20) },
7198 { PREFIX_TABLE (PREFIX_0F3A21) },
7199 { PREFIX_TABLE (PREFIX_0F3A22) },
7233 { PREFIX_TABLE (PREFIX_0F3A40) },
7234 { PREFIX_TABLE (PREFIX_0F3A41) },
7235 { PREFIX_TABLE (PREFIX_0F3A42) },
7237 { PREFIX_TABLE (PREFIX_0F3A44) },
7269 { PREFIX_TABLE (PREFIX_0F3A60) },
7270 { PREFIX_TABLE (PREFIX_0F3A61) },
7271 { PREFIX_TABLE (PREFIX_0F3A62) },
7272 { PREFIX_TABLE (PREFIX_0F3A63) },
7390 { PREFIX_TABLE (PREFIX_0F3ACC) },
7411 { PREFIX_TABLE (PREFIX_0F3ADF) },
7450 /* THREE_BYTE_0F7A */
7489 { "ptest", { XX }, PREFIX_OPCODE },
7526 { "phaddbw", { XM, EXq }, PREFIX_OPCODE },
7527 { "phaddbd", { XM, EXq }, PREFIX_OPCODE },
7528 { "phaddbq", { XM, EXq }, PREFIX_OPCODE },
7531 { "phaddwd", { XM, EXq }, PREFIX_OPCODE },
7532 { "phaddwq", { XM, EXq }, PREFIX_OPCODE },
7537 { "phadddq", { XM, EXq }, PREFIX_OPCODE },
7544 { "phaddubw", { XM, EXq }, PREFIX_OPCODE },
7545 { "phaddubd", { XM, EXq }, PREFIX_OPCODE },
7546 { "phaddubq", { XM, EXq }, PREFIX_OPCODE },
7549 { "phadduwd", { XM, EXq }, PREFIX_OPCODE },
7550 { "phadduwq", { XM, EXq }, PREFIX_OPCODE },
7555 { "phaddudq", { XM, EXq }, PREFIX_OPCODE },
7562 { "phsubbw", { XM, EXq }, PREFIX_OPCODE },
7563 { "phsubbd", { XM, EXq }, PREFIX_OPCODE },
7564 { "phsubbq", { XM, EXq }, PREFIX_OPCODE },
7743 static const struct dis386 xop_table[][256] = {
7896 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7897 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7898 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7906 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7907 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7914 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7915 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7916 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7924 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7925 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7929 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7930 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7933 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7951 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7963 { "vprotb", { XM, Vex_2src_1, Ib }, 0 },
7964 { "vprotw", { XM, Vex_2src_1, Ib }, 0 },
7965 { "vprotd", { XM, Vex_2src_1, Ib }, 0 },
7966 { "vprotq", { XM, Vex_2src_1, Ib }, 0 },
7976 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7977 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7978 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7979 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
8012 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8013 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8014 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8015 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8039 { REG_TABLE (REG_XOP_TBM_01) },
8040 { REG_TABLE (REG_XOP_TBM_02) },
8058 { REG_TABLE (REG_XOP_LWPCB) },
8182 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8183 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8184 { "vfrczss", { XM, EXd }, 0 },
8185 { "vfrczsd", { XM, EXq }, 0 },
8200 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8201 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8202 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8203 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8204 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8205 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8206 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8207 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8209 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8210 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8211 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8212 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8255 { "vphaddbw", { XM, EXxmm }, 0 },
8256 { "vphaddbd", { XM, EXxmm }, 0 },
8257 { "vphaddbq", { XM, EXxmm }, 0 },
8260 { "vphaddwd", { XM, EXxmm }, 0 },
8261 { "vphaddwq", { XM, EXxmm }, 0 },
8266 { "vphadddq", { XM, EXxmm }, 0 },
8273 { "vphaddubw", { XM, EXxmm }, 0 },
8274 { "vphaddubd", { XM, EXxmm }, 0 },
8275 { "vphaddubq", { XM, EXxmm }, 0 },
8278 { "vphadduwd", { XM, EXxmm }, 0 },
8279 { "vphadduwq", { XM, EXxmm }, 0 },
8284 { "vphaddudq", { XM, EXxmm }, 0 },
8291 { "vphsubbw", { XM, EXxmm }, 0 },
8292 { "vphsubwd", { XM, EXxmm }, 0 },
8293 { "vphsubdq", { XM, EXxmm }, 0 },
8347 { "bextr", { Gv, Ev, Iq }, 0 },
8349 { REG_TABLE (REG_XOP_LWP) },
8619 static const struct dis386 vex_table[][256] = {
8641 { PREFIX_TABLE (PREFIX_VEX_0F10) },
8642 { PREFIX_TABLE (PREFIX_VEX_0F11) },
8643 { PREFIX_TABLE (PREFIX_VEX_0F12) },
8644 { MOD_TABLE (MOD_VEX_0F13) },
8645 { VEX_W_TABLE (VEX_W_0F14) },
8646 { VEX_W_TABLE (VEX_W_0F15) },
8647 { PREFIX_TABLE (PREFIX_VEX_0F16) },
8648 { MOD_TABLE (MOD_VEX_0F17) },
8668 { VEX_W_TABLE (VEX_W_0F28) },
8669 { VEX_W_TABLE (VEX_W_0F29) },
8670 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8671 { MOD_TABLE (MOD_VEX_0F2B) },
8672 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8673 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8674 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8675 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8696 { PREFIX_TABLE (PREFIX_VEX_0F41) },
8697 { PREFIX_TABLE (PREFIX_VEX_0F42) },
8699 { PREFIX_TABLE (PREFIX_VEX_0F44) },
8700 { PREFIX_TABLE (PREFIX_VEX_0F45) },
8701 { PREFIX_TABLE (PREFIX_VEX_0F46) },
8702 { PREFIX_TABLE (PREFIX_VEX_0F47) },
8706 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8707 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8713 { MOD_TABLE (MOD_VEX_0F50) },
8714 { PREFIX_TABLE (PREFIX_VEX_0F51) },
8715 { PREFIX_TABLE (PREFIX_VEX_0F52) },
8716 { PREFIX_TABLE (PREFIX_VEX_0F53) },
8717 { "vandpX", { XM, Vex, EXx }, 0 },
8718 { "vandnpX", { XM, Vex, EXx }, 0 },
8719 { "vorpX", { XM, Vex, EXx }, 0 },
8720 { "vxorpX", { XM, Vex, EXx }, 0 },
8722 { PREFIX_TABLE (PREFIX_VEX_0F58) },
8723 { PREFIX_TABLE (PREFIX_VEX_0F59) },
8724 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8725 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F60) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F61) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F62) },
8734 { PREFIX_TABLE (PREFIX_VEX_0F63) },
8735 { PREFIX_TABLE (PREFIX_VEX_0F64) },
8736 { PREFIX_TABLE (PREFIX_VEX_0F65) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F66) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F67) },
8740 { PREFIX_TABLE (PREFIX_VEX_0F68) },
8741 { PREFIX_TABLE (PREFIX_VEX_0F69) },
8742 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8743 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8744 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8745 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8746 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F70) },
8750 { REG_TABLE (REG_VEX_0F71) },
8751 { REG_TABLE (REG_VEX_0F72) },
8752 { REG_TABLE (REG_VEX_0F73) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F74) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F75) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F76) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F77) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F90) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F91) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F92) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F93) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F98) },
8795 { PREFIX_TABLE (PREFIX_VEX_0F99) },
8818 { REG_TABLE (REG_VEX_0FAE) },
8841 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8843 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8844 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8845 { "vshufpX", { XM, Vex, EXx, Ib }, 0 },
8857 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8858 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8859 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8860 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8861 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8862 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8863 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8864 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8866 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8867 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8868 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8869 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8870 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8871 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8872 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8873 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8875 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8876 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8877 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8878 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8879 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8880 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8881 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8882 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8884 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8885 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8886 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8887 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8888 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8889 { PREFIX_TABLE (PREFIX_VEX_0FED) },
8890 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8891 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8893 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8894 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8895 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8896 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8897 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8898 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8899 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8900 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8902 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8903 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8904 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8905 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8906 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8907 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8908 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8923 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8924 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8925 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8926 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8927 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8928 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8929 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8954 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8959 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8960 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8961 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8962 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8963 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8964 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8965 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8966 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8968 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8969 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8972 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8973 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8974 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8975 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8977 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8978 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8979 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8980 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8981 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8982 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8983 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8984 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8986 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8987 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8991 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8992 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8993 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
9013 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9014 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9015 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9049 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9050 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9077 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9078 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9079 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9082 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9083 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9085 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9086 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9087 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9088 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9101 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9103 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9104 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9105 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9106 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9107 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9108 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9109 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9110 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9118 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9119 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9121 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9122 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9123 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9124 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9125 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9126 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9127 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9128 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9160 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9161 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9162 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9163 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9164 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9186 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9187 { REG_TABLE (REG_VEX_0F38F3) },
9189 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9190 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9191 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9205 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9206 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9207 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9209 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9210 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9211 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9214 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9215 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9216 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9217 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9218 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9219 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9220 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9221 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9227 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9228 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9229 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9230 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9232 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9233 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9237 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9241 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9242 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9243 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9259 { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9260 { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9261 { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9262 { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9268 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9269 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9277 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9278 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9279 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9281 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9283 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9286 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9287 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9288 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9289 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9290 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9308 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9309 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9310 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9311 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9313 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9314 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9315 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9316 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9322 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9323 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9324 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9325 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9326 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9327 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9328 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9329 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9340 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9341 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9342 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9343 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9344 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9345 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9346 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9347 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9455 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9475 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9495 #define NEED_OPCODE_TABLE
9496 #include "i386-dis-evex.h"
9497 #undef NEED_OPCODE_TABLE
9498 static const struct dis386 vex_len_table[][2] = {
9499 /* VEX_LEN_0F10_P_1 */
9501 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9502 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9505 /* VEX_LEN_0F10_P_3 */
9507 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9508 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9511 /* VEX_LEN_0F11_P_1 */
9513 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9514 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9517 /* VEX_LEN_0F11_P_3 */
9519 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9520 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9523 /* VEX_LEN_0F12_P_0_M_0 */
9525 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9528 /* VEX_LEN_0F12_P_0_M_1 */
9530 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9533 /* VEX_LEN_0F12_P_2 */
9535 { VEX_W_TABLE (VEX_W_0F12_P_2) },
9538 /* VEX_LEN_0F13_M_0 */
9540 { VEX_W_TABLE (VEX_W_0F13_M_0) },
9543 /* VEX_LEN_0F16_P_0_M_0 */
9545 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9548 /* VEX_LEN_0F16_P_0_M_1 */
9550 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9553 /* VEX_LEN_0F16_P_2 */
9555 { VEX_W_TABLE (VEX_W_0F16_P_2) },
9558 /* VEX_LEN_0F17_M_0 */
9560 { VEX_W_TABLE (VEX_W_0F17_M_0) },
9563 /* VEX_LEN_0F2A_P_1 */
9565 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9566 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9569 /* VEX_LEN_0F2A_P_3 */
9571 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9572 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9575 /* VEX_LEN_0F2C_P_1 */
9577 { "vcvttss2siY", { Gv, EXdScalar }, 0 },
9578 { "vcvttss2siY", { Gv, EXdScalar }, 0 },
9581 /* VEX_LEN_0F2C_P_3 */
9583 { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
9584 { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
9587 /* VEX_LEN_0F2D_P_1 */
9589 { "vcvtss2siY", { Gv, EXdScalar }, 0 },
9590 { "vcvtss2siY", { Gv, EXdScalar }, 0 },
9593 /* VEX_LEN_0F2D_P_3 */
9595 { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
9596 { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
9599 /* VEX_LEN_0F2E_P_0 */
9601 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9602 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9605 /* VEX_LEN_0F2E_P_2 */
9607 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9608 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9611 /* VEX_LEN_0F2F_P_0 */
9613 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9614 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9617 /* VEX_LEN_0F2F_P_2 */
9619 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9620 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9623 /* VEX_LEN_0F41_P_0 */
9626 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9628 /* VEX_LEN_0F41_P_2 */
9631 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9633 /* VEX_LEN_0F42_P_0 */
9636 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9638 /* VEX_LEN_0F42_P_2 */
9641 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9643 /* VEX_LEN_0F44_P_0 */
9645 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9647 /* VEX_LEN_0F44_P_2 */
9649 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9651 /* VEX_LEN_0F45_P_0 */
9654 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9656 /* VEX_LEN_0F45_P_2 */
9659 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9661 /* VEX_LEN_0F46_P_0 */
9664 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9666 /* VEX_LEN_0F46_P_2 */
9669 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9671 /* VEX_LEN_0F47_P_0 */
9674 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9676 /* VEX_LEN_0F47_P_2 */
9679 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9681 /* VEX_LEN_0F4A_P_0 */
9684 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9686 /* VEX_LEN_0F4A_P_2 */
9689 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9691 /* VEX_LEN_0F4B_P_0 */
9694 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9696 /* VEX_LEN_0F4B_P_2 */
9699 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9702 /* VEX_LEN_0F51_P_1 */
9704 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9705 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9708 /* VEX_LEN_0F51_P_3 */
9710 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9711 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9714 /* VEX_LEN_0F52_P_1 */
9716 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9717 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9720 /* VEX_LEN_0F53_P_1 */
9722 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9723 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9726 /* VEX_LEN_0F58_P_1 */
9728 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9729 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9732 /* VEX_LEN_0F58_P_3 */
9734 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9735 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9738 /* VEX_LEN_0F59_P_1 */
9740 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9741 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9744 /* VEX_LEN_0F59_P_3 */
9746 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9747 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9750 /* VEX_LEN_0F5A_P_1 */
9752 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9753 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9756 /* VEX_LEN_0F5A_P_3 */
9758 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9759 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9762 /* VEX_LEN_0F5C_P_1 */
9764 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9765 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9768 /* VEX_LEN_0F5C_P_3 */
9770 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9771 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9774 /* VEX_LEN_0F5D_P_1 */
9776 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9777 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9780 /* VEX_LEN_0F5D_P_3 */
9782 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9783 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9786 /* VEX_LEN_0F5E_P_1 */
9788 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9789 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9792 /* VEX_LEN_0F5E_P_3 */
9794 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9795 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9798 /* VEX_LEN_0F5F_P_1 */
9800 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9801 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9804 /* VEX_LEN_0F5F_P_3 */
9806 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9807 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9810 /* VEX_LEN_0F6E_P_2 */
9812 { "vmovK", { XMScalar, Edq }, 0 },
9813 { "vmovK", { XMScalar, Edq }, 0 },
9816 /* VEX_LEN_0F7E_P_1 */
9818 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9819 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9822 /* VEX_LEN_0F7E_P_2 */
9824 { "vmovK", { Edq, XMScalar }, 0 },
9825 { "vmovK", { Edq, XMScalar }, 0 },
9828 /* VEX_LEN_0F90_P_0 */
9830 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9833 /* VEX_LEN_0F90_P_2 */
9835 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9838 /* VEX_LEN_0F91_P_0 */
9840 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9843 /* VEX_LEN_0F91_P_2 */
9845 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9848 /* VEX_LEN_0F92_P_0 */
9850 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9853 /* VEX_LEN_0F92_P_2 */
9855 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9858 /* VEX_LEN_0F92_P_3 */
9860 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9863 /* VEX_LEN_0F93_P_0 */
9865 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9868 /* VEX_LEN_0F93_P_2 */
9870 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9873 /* VEX_LEN_0F93_P_3 */
9875 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9878 /* VEX_LEN_0F98_P_0 */
9880 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9883 /* VEX_LEN_0F98_P_2 */
9885 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9888 /* VEX_LEN_0F99_P_0 */
9890 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9893 /* VEX_LEN_0F99_P_2 */
9895 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9898 /* VEX_LEN_0FAE_R_2_M_0 */
9900 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9903 /* VEX_LEN_0FAE_R_3_M_0 */
9905 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9908 /* VEX_LEN_0FC2_P_1 */
9910 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9911 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9914 /* VEX_LEN_0FC2_P_3 */
9916 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9917 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9920 /* VEX_LEN_0FC4_P_2 */
9922 { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9925 /* VEX_LEN_0FC5_P_2 */
9927 { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9930 /* VEX_LEN_0FD6_P_2 */
9932 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9933 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9936 /* VEX_LEN_0FF7_P_2 */
9938 { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9941 /* VEX_LEN_0F3816_P_2 */
9944 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9947 /* VEX_LEN_0F3819_P_2 */
9950 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9953 /* VEX_LEN_0F381A_P_2_M_0 */
9956 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9959 /* VEX_LEN_0F3836_P_2 */
9962 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9965 /* VEX_LEN_0F3841_P_2 */
9967 { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9970 /* VEX_LEN_0F385A_P_2_M_0 */
9973 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9976 /* VEX_LEN_0F38DB_P_2 */
9978 { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9981 /* VEX_LEN_0F38DC_P_2 */
9983 { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9986 /* VEX_LEN_0F38DD_P_2 */
9988 { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9991 /* VEX_LEN_0F38DE_P_2 */
9993 { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9996 /* VEX_LEN_0F38DF_P_2 */
9998 { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
10001 /* VEX_LEN_0F38F2_P_0 */
10003 { "andnS", { Gdq, VexGdq, Edq }, 0 },
10006 /* VEX_LEN_0F38F3_R_1_P_0 */
10008 { "blsrS", { VexGdq, Edq }, 0 },
10011 /* VEX_LEN_0F38F3_R_2_P_0 */
10013 { "blsmskS", { VexGdq, Edq }, 0 },
10016 /* VEX_LEN_0F38F3_R_3_P_0 */
10018 { "blsiS", { VexGdq, Edq }, 0 },
10021 /* VEX_LEN_0F38F5_P_0 */
10023 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
10026 /* VEX_LEN_0F38F5_P_1 */
10028 { "pextS", { Gdq, VexGdq, Edq }, 0 },
10031 /* VEX_LEN_0F38F5_P_3 */
10033 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
10036 /* VEX_LEN_0F38F6_P_3 */
10038 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
10041 /* VEX_LEN_0F38F7_P_0 */
10043 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
10046 /* VEX_LEN_0F38F7_P_1 */
10048 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
10051 /* VEX_LEN_0F38F7_P_2 */
10053 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
10056 /* VEX_LEN_0F38F7_P_3 */
10058 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
10061 /* VEX_LEN_0F3A00_P_2 */
10064 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10067 /* VEX_LEN_0F3A01_P_2 */
10070 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10073 /* VEX_LEN_0F3A06_P_2 */
10076 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10079 /* VEX_LEN_0F3A0A_P_2 */
10081 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10082 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10085 /* VEX_LEN_0F3A0B_P_2 */
10087 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10088 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10091 /* VEX_LEN_0F3A14_P_2 */
10093 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10096 /* VEX_LEN_0F3A15_P_2 */
10098 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10101 /* VEX_LEN_0F3A16_P_2 */
10103 { "vpextrK", { Edq, XM, Ib }, 0 },
10106 /* VEX_LEN_0F3A17_P_2 */
10108 { "vextractps", { Edqd, XM, Ib }, 0 },
10111 /* VEX_LEN_0F3A18_P_2 */
10114 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10117 /* VEX_LEN_0F3A19_P_2 */
10120 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10123 /* VEX_LEN_0F3A20_P_2 */
10125 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10128 /* VEX_LEN_0F3A21_P_2 */
10130 { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10133 /* VEX_LEN_0F3A22_P_2 */
10135 { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 },
10138 /* VEX_LEN_0F3A30_P_2 */
10140 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10143 /* VEX_LEN_0F3A31_P_2 */
10145 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10148 /* VEX_LEN_0F3A32_P_2 */
10150 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10153 /* VEX_LEN_0F3A33_P_2 */
10155 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10158 /* VEX_LEN_0F3A38_P_2 */
10161 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10164 /* VEX_LEN_0F3A39_P_2 */
10167 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10170 /* VEX_LEN_0F3A41_P_2 */
10172 { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10175 /* VEX_LEN_0F3A44_P_2 */
10177 { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10180 /* VEX_LEN_0F3A46_P_2 */
10183 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10186 /* VEX_LEN_0F3A60_P_2 */
10188 { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10191 /* VEX_LEN_0F3A61_P_2 */
10193 { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10196 /* VEX_LEN_0F3A62_P_2 */
10198 { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10201 /* VEX_LEN_0F3A63_P_2 */
10203 { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10206 /* VEX_LEN_0F3A6A_P_2 */
10208 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10211 /* VEX_LEN_0F3A6B_P_2 */
10213 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10216 /* VEX_LEN_0F3A6E_P_2 */
10218 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10221 /* VEX_LEN_0F3A6F_P_2 */
10223 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10226 /* VEX_LEN_0F3A7A_P_2 */
10228 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10231 /* VEX_LEN_0F3A7B_P_2 */
10233 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10236 /* VEX_LEN_0F3A7E_P_2 */
10238 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10241 /* VEX_LEN_0F3A7F_P_2 */
10243 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10246 /* VEX_LEN_0F3ADF_P_2 */
10248 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10251 /* VEX_LEN_0F3AF0_P_3 */
10253 { "rorxS", { Gdq, Edq, Ib }, 0 },
10256 /* VEX_LEN_0FXOP_08_CC */
10258 { "vpcomb", { XM, Vex128, EXx, Ib }, 0 },
10261 /* VEX_LEN_0FXOP_08_CD */
10263 { "vpcomw", { XM, Vex128, EXx, Ib }, 0 },
10266 /* VEX_LEN_0FXOP_08_CE */
10268 { "vpcomd", { XM, Vex128, EXx, Ib }, 0 },
10271 /* VEX_LEN_0FXOP_08_CF */
10273 { "vpcomq", { XM, Vex128, EXx, Ib }, 0 },
10276 /* VEX_LEN_0FXOP_08_EC */
10278 { "vpcomub", { XM, Vex128, EXx, Ib }, 0 },
10281 /* VEX_LEN_0FXOP_08_ED */
10283 { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 },
10286 /* VEX_LEN_0FXOP_08_EE */
10288 { "vpcomud", { XM, Vex128, EXx, Ib }, 0 },
10291 /* VEX_LEN_0FXOP_08_EF */
10293 { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 },
10296 /* VEX_LEN_0FXOP_09_80 */
10298 { "vfrczps", { XM, EXxmm }, 0 },
10299 { "vfrczps", { XM, EXymmq }, 0 },
10302 /* VEX_LEN_0FXOP_09_81 */
10304 { "vfrczpd", { XM, EXxmm }, 0 },
10305 { "vfrczpd", { XM, EXymmq }, 0 },
10309 static const struct dis386 vex_w_table[][2] = {
10311 /* VEX_W_0F10_P_0 */
10312 { "vmovups", { XM, EXx }, 0 },
10315 /* VEX_W_0F10_P_1 */
10316 { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
10319 /* VEX_W_0F10_P_2 */
10320 { "vmovupd", { XM, EXx }, 0 },
10323 /* VEX_W_0F10_P_3 */
10324 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
10327 /* VEX_W_0F11_P_0 */
10328 { "vmovups", { EXxS, XM }, 0 },
10331 /* VEX_W_0F11_P_1 */
10332 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10335 /* VEX_W_0F11_P_2 */
10336 { "vmovupd", { EXxS, XM }, 0 },
10339 /* VEX_W_0F11_P_3 */
10340 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10343 /* VEX_W_0F12_P_0_M_0 */
10344 { "vmovlps", { XM, Vex128, EXq }, 0 },
10347 /* VEX_W_0F12_P_0_M_1 */
10348 { "vmovhlps", { XM, Vex128, EXq }, 0 },
10351 /* VEX_W_0F12_P_1 */
10352 { "vmovsldup", { XM, EXx }, 0 },
10355 /* VEX_W_0F12_P_2 */
10356 { "vmovlpd", { XM, Vex128, EXq }, 0 },
10359 /* VEX_W_0F12_P_3 */
10360 { "vmovddup", { XM, EXymmq }, 0 },
10363 /* VEX_W_0F13_M_0 */
10364 { "vmovlpX", { EXq, XM }, 0 },
10368 { "vunpcklpX", { XM, Vex, EXx }, 0 },
10372 { "vunpckhpX", { XM, Vex, EXx }, 0 },
10375 /* VEX_W_0F16_P_0_M_0 */
10376 { "vmovhps", { XM, Vex128, EXq }, 0 },
10379 /* VEX_W_0F16_P_0_M_1 */
10380 { "vmovlhps", { XM, Vex128, EXq }, 0 },
10383 /* VEX_W_0F16_P_1 */
10384 { "vmovshdup", { XM, EXx }, 0 },
10387 /* VEX_W_0F16_P_2 */
10388 { "vmovhpd", { XM, Vex128, EXq }, 0 },
10391 /* VEX_W_0F17_M_0 */
10392 { "vmovhpX", { EXq, XM }, 0 },
10396 { "vmovapX", { XM, EXx }, 0 },
10400 { "vmovapX", { EXxS, XM }, 0 },
10403 /* VEX_W_0F2B_M_0 */
10404 { "vmovntpX", { Mx, XM }, 0 },
10407 /* VEX_W_0F2E_P_0 */
10408 { "vucomiss", { XMScalar, EXdScalar }, 0 },
10411 /* VEX_W_0F2E_P_2 */
10412 { "vucomisd", { XMScalar, EXqScalar }, 0 },
10415 /* VEX_W_0F2F_P_0 */
10416 { "vcomiss", { XMScalar, EXdScalar }, 0 },
10419 /* VEX_W_0F2F_P_2 */
10420 { "vcomisd", { XMScalar, EXqScalar }, 0 },
10423 /* VEX_W_0F41_P_0_LEN_1 */
10424 { "kandw", { MaskG, MaskVex, MaskR }, 0 },
10425 { "kandq", { MaskG, MaskVex, MaskR }, 0 },
10428 /* VEX_W_0F41_P_2_LEN_1 */
10429 { "kandb", { MaskG, MaskVex, MaskR }, 0 },
10430 { "kandd", { MaskG, MaskVex, MaskR }, 0 },
10433 /* VEX_W_0F42_P_0_LEN_1 */
10434 { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
10435 { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
10438 /* VEX_W_0F42_P_2_LEN_1 */
10439 { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
10440 { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
10443 /* VEX_W_0F44_P_0_LEN_0 */
10444 { "knotw", { MaskG, MaskR }, 0 },
10445 { "knotq", { MaskG, MaskR }, 0 },
10448 /* VEX_W_0F44_P_2_LEN_0 */
10449 { "knotb", { MaskG, MaskR }, 0 },
10450 { "knotd", { MaskG, MaskR }, 0 },
10453 /* VEX_W_0F45_P_0_LEN_1 */
10454 { "korw", { MaskG, MaskVex, MaskR }, 0 },
10455 { "korq", { MaskG, MaskVex, MaskR }, 0 },
10458 /* VEX_W_0F45_P_2_LEN_1 */
10459 { "korb", { MaskG, MaskVex, MaskR }, 0 },
10460 { "kord", { MaskG, MaskVex, MaskR }, 0 },
10463 /* VEX_W_0F46_P_0_LEN_1 */
10464 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
10465 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
10468 /* VEX_W_0F46_P_2_LEN_1 */
10469 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
10470 { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
10473 /* VEX_W_0F47_P_0_LEN_1 */
10474 { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
10475 { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
10478 /* VEX_W_0F47_P_2_LEN_1 */
10479 { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
10480 { "kxord", { MaskG, MaskVex, MaskR }, 0 },
10483 /* VEX_W_0F4A_P_0_LEN_1 */
10484 { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
10485 { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
10488 /* VEX_W_0F4A_P_2_LEN_1 */
10489 { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
10490 { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
10493 /* VEX_W_0F4B_P_0_LEN_1 */
10494 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
10495 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
10498 /* VEX_W_0F4B_P_2_LEN_1 */
10499 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
10502 /* VEX_W_0F50_M_0 */
10503 { "vmovmskpX", { Gdq, XS }, 0 },
10506 /* VEX_W_0F51_P_0 */
10507 { "vsqrtps", { XM, EXx }, 0 },
10510 /* VEX_W_0F51_P_1 */
10511 { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10514 /* VEX_W_0F51_P_2 */
10515 { "vsqrtpd", { XM, EXx }, 0 },
10518 /* VEX_W_0F51_P_3 */
10519 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10522 /* VEX_W_0F52_P_0 */
10523 { "vrsqrtps", { XM, EXx }, 0 },
10526 /* VEX_W_0F52_P_1 */
10527 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10530 /* VEX_W_0F53_P_0 */
10531 { "vrcpps", { XM, EXx }, 0 },
10534 /* VEX_W_0F53_P_1 */
10535 { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
10538 /* VEX_W_0F58_P_0 */
10539 { "vaddps", { XM, Vex, EXx }, 0 },
10542 /* VEX_W_0F58_P_1 */
10543 { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
10546 /* VEX_W_0F58_P_2 */
10547 { "vaddpd", { XM, Vex, EXx }, 0 },
10550 /* VEX_W_0F58_P_3 */
10551 { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10554 /* VEX_W_0F59_P_0 */
10555 { "vmulps", { XM, Vex, EXx }, 0 },
10558 /* VEX_W_0F59_P_1 */
10559 { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
10562 /* VEX_W_0F59_P_2 */
10563 { "vmulpd", { XM, Vex, EXx }, 0 },
10566 /* VEX_W_0F59_P_3 */
10567 { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10570 /* VEX_W_0F5A_P_0 */
10571 { "vcvtps2pd", { XM, EXxmmq }, 0 },
10574 /* VEX_W_0F5A_P_1 */
10575 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
10578 /* VEX_W_0F5A_P_3 */
10579 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
10582 /* VEX_W_0F5B_P_0 */
10583 { "vcvtdq2ps", { XM, EXx }, 0 },
10586 /* VEX_W_0F5B_P_1 */
10587 { "vcvttps2dq", { XM, EXx }, 0 },
10590 /* VEX_W_0F5B_P_2 */
10591 { "vcvtps2dq", { XM, EXx }, 0 },
10594 /* VEX_W_0F5C_P_0 */
10595 { "vsubps", { XM, Vex, EXx }, 0 },
10598 /* VEX_W_0F5C_P_1 */
10599 { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
10602 /* VEX_W_0F5C_P_2 */
10603 { "vsubpd", { XM, Vex, EXx }, 0 },
10606 /* VEX_W_0F5C_P_3 */
10607 { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10610 /* VEX_W_0F5D_P_0 */
10611 { "vminps", { XM, Vex, EXx }, 0 },
10614 /* VEX_W_0F5D_P_1 */
10615 { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
10618 /* VEX_W_0F5D_P_2 */
10619 { "vminpd", { XM, Vex, EXx }, 0 },
10622 /* VEX_W_0F5D_P_3 */
10623 { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10626 /* VEX_W_0F5E_P_0 */
10627 { "vdivps", { XM, Vex, EXx }, 0 },
10630 /* VEX_W_0F5E_P_1 */
10631 { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
10634 /* VEX_W_0F5E_P_2 */
10635 { "vdivpd", { XM, Vex, EXx }, 0 },
10638 /* VEX_W_0F5E_P_3 */
10639 { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10642 /* VEX_W_0F5F_P_0 */
10643 { "vmaxps", { XM, Vex, EXx }, 0 },
10646 /* VEX_W_0F5F_P_1 */
10647 { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
10650 /* VEX_W_0F5F_P_2 */
10651 { "vmaxpd", { XM, Vex, EXx }, 0 },
10654 /* VEX_W_0F5F_P_3 */
10655 { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10658 /* VEX_W_0F60_P_2 */
10659 { "vpunpcklbw", { XM, Vex, EXx }, 0 },
10662 /* VEX_W_0F61_P_2 */
10663 { "vpunpcklwd", { XM, Vex, EXx }, 0 },
10666 /* VEX_W_0F62_P_2 */
10667 { "vpunpckldq", { XM, Vex, EXx }, 0 },
10670 /* VEX_W_0F63_P_2 */
10671 { "vpacksswb", { XM, Vex, EXx }, 0 },
10674 /* VEX_W_0F64_P_2 */
10675 { "vpcmpgtb", { XM, Vex, EXx }, 0 },
10678 /* VEX_W_0F65_P_2 */
10679 { "vpcmpgtw", { XM, Vex, EXx }, 0 },
10682 /* VEX_W_0F66_P_2 */
10683 { "vpcmpgtd", { XM, Vex, EXx }, 0 },
10686 /* VEX_W_0F67_P_2 */
10687 { "vpackuswb", { XM, Vex, EXx }, 0 },
10690 /* VEX_W_0F68_P_2 */
10691 { "vpunpckhbw", { XM, Vex, EXx }, 0 },
10694 /* VEX_W_0F69_P_2 */
10695 { "vpunpckhwd", { XM, Vex, EXx }, 0 },
10698 /* VEX_W_0F6A_P_2 */
10699 { "vpunpckhdq", { XM, Vex, EXx }, 0 },
10702 /* VEX_W_0F6B_P_2 */
10703 { "vpackssdw", { XM, Vex, EXx }, 0 },
10706 /* VEX_W_0F6C_P_2 */
10707 { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
10710 /* VEX_W_0F6D_P_2 */
10711 { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
10714 /* VEX_W_0F6F_P_1 */
10715 { "vmovdqu", { XM, EXx }, 0 },
10718 /* VEX_W_0F6F_P_2 */
10719 { "vmovdqa", { XM, EXx }, 0 },
10722 /* VEX_W_0F70_P_1 */
10723 { "vpshufhw", { XM, EXx, Ib }, 0 },
10726 /* VEX_W_0F70_P_2 */
10727 { "vpshufd", { XM, EXx, Ib }, 0 },
10730 /* VEX_W_0F70_P_3 */
10731 { "vpshuflw", { XM, EXx, Ib }, 0 },
10734 /* VEX_W_0F71_R_2_P_2 */
10735 { "vpsrlw", { Vex, XS, Ib }, 0 },
10738 /* VEX_W_0F71_R_4_P_2 */
10739 { "vpsraw", { Vex, XS, Ib }, 0 },
10742 /* VEX_W_0F71_R_6_P_2 */
10743 { "vpsllw", { Vex, XS, Ib }, 0 },
10746 /* VEX_W_0F72_R_2_P_2 */
10747 { "vpsrld", { Vex, XS, Ib }, 0 },
10750 /* VEX_W_0F72_R_4_P_2 */
10751 { "vpsrad", { Vex, XS, Ib }, 0 },
10754 /* VEX_W_0F72_R_6_P_2 */
10755 { "vpslld", { Vex, XS, Ib }, 0 },
10758 /* VEX_W_0F73_R_2_P_2 */
10759 { "vpsrlq", { Vex, XS, Ib }, 0 },
10762 /* VEX_W_0F73_R_3_P_2 */
10763 { "vpsrldq", { Vex, XS, Ib }, 0 },
10766 /* VEX_W_0F73_R_6_P_2 */
10767 { "vpsllq", { Vex, XS, Ib }, 0 },
10770 /* VEX_W_0F73_R_7_P_2 */
10771 { "vpslldq", { Vex, XS, Ib }, 0 },
10774 /* VEX_W_0F74_P_2 */
10775 { "vpcmpeqb", { XM, Vex, EXx }, 0 },
10778 /* VEX_W_0F75_P_2 */
10779 { "vpcmpeqw", { XM, Vex, EXx }, 0 },
10782 /* VEX_W_0F76_P_2 */
10783 { "vpcmpeqd", { XM, Vex, EXx }, 0 },
10786 /* VEX_W_0F77_P_0 */
10787 { "", { VZERO }, 0 },
10790 /* VEX_W_0F7C_P_2 */
10791 { "vhaddpd", { XM, Vex, EXx }, 0 },
10794 /* VEX_W_0F7C_P_3 */
10795 { "vhaddps", { XM, Vex, EXx }, 0 },
10798 /* VEX_W_0F7D_P_2 */
10799 { "vhsubpd", { XM, Vex, EXx }, 0 },
10802 /* VEX_W_0F7D_P_3 */
10803 { "vhsubps", { XM, Vex, EXx }, 0 },
10806 /* VEX_W_0F7E_P_1 */
10807 { "vmovq", { XMScalar, EXqScalar }, 0 },
10810 /* VEX_W_0F7F_P_1 */
10811 { "vmovdqu", { EXxS, XM }, 0 },
10814 /* VEX_W_0F7F_P_2 */
10815 { "vmovdqa", { EXxS, XM }, 0 },
10818 /* VEX_W_0F90_P_0_LEN_0 */
10819 { "kmovw", { MaskG, MaskE }, 0 },
10820 { "kmovq", { MaskG, MaskE }, 0 },
10823 /* VEX_W_0F90_P_2_LEN_0 */
10824 { "kmovb", { MaskG, MaskBDE }, 0 },
10825 { "kmovd", { MaskG, MaskBDE }, 0 },
10828 /* VEX_W_0F91_P_0_LEN_0 */
10829 { "kmovw", { Ew, MaskG }, 0 },
10830 { "kmovq", { Eq, MaskG }, 0 },
10833 /* VEX_W_0F91_P_2_LEN_0 */
10834 { "kmovb", { Eb, MaskG }, 0 },
10835 { "kmovd", { Ed, MaskG }, 0 },
10838 /* VEX_W_0F92_P_0_LEN_0 */
10839 { "kmovw", { MaskG, Rdq }, 0 },
10842 /* VEX_W_0F92_P_2_LEN_0 */
10843 { "kmovb", { MaskG, Rdq }, 0 },
10846 /* VEX_W_0F92_P_3_LEN_0 */
10847 { "kmovd", { MaskG, Rdq }, 0 },
10848 { "kmovq", { MaskG, Rdq }, 0 },
10851 /* VEX_W_0F93_P_0_LEN_0 */
10852 { "kmovw", { Gdq, MaskR }, 0 },
10855 /* VEX_W_0F93_P_2_LEN_0 */
10856 { "kmovb", { Gdq, MaskR }, 0 },
10859 /* VEX_W_0F93_P_3_LEN_0 */
10860 { "kmovd", { Gdq, MaskR }, 0 },
10861 { "kmovq", { Gdq, MaskR }, 0 },
10864 /* VEX_W_0F98_P_0_LEN_0 */
10865 { "kortestw", { MaskG, MaskR }, 0 },
10866 { "kortestq", { MaskG, MaskR }, 0 },
10869 /* VEX_W_0F98_P_2_LEN_0 */
10870 { "kortestb", { MaskG, MaskR }, 0 },
10871 { "kortestd", { MaskG, MaskR }, 0 },
10874 /* VEX_W_0F99_P_0_LEN_0 */
10875 { "ktestw", { MaskG, MaskR }, 0 },
10876 { "ktestq", { MaskG, MaskR }, 0 },
10879 /* VEX_W_0F99_P_2_LEN_0 */
10880 { "ktestb", { MaskG, MaskR }, 0 },
10881 { "ktestd", { MaskG, MaskR }, 0 },
10884 /* VEX_W_0FAE_R_2_M_0 */
10885 { "vldmxcsr", { Md }, 0 },
10888 /* VEX_W_0FAE_R_3_M_0 */
10889 { "vstmxcsr", { Md }, 0 },
10892 /* VEX_W_0FC2_P_0 */
10893 { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
10896 /* VEX_W_0FC2_P_1 */
10897 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10900 /* VEX_W_0FC2_P_2 */
10901 { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
10904 /* VEX_W_0FC2_P_3 */
10905 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10908 /* VEX_W_0FC4_P_2 */
10909 { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
10912 /* VEX_W_0FC5_P_2 */
10913 { "vpextrw", { Gdq, XS, Ib }, 0 },
10916 /* VEX_W_0FD0_P_2 */
10917 { "vaddsubpd", { XM, Vex, EXx }, 0 },
10920 /* VEX_W_0FD0_P_3 */
10921 { "vaddsubps", { XM, Vex, EXx }, 0 },
10924 /* VEX_W_0FD1_P_2 */
10925 { "vpsrlw", { XM, Vex, EXxmm }, 0 },
10928 /* VEX_W_0FD2_P_2 */
10929 { "vpsrld", { XM, Vex, EXxmm }, 0 },
10932 /* VEX_W_0FD3_P_2 */
10933 { "vpsrlq", { XM, Vex, EXxmm }, 0 },
10936 /* VEX_W_0FD4_P_2 */
10937 { "vpaddq", { XM, Vex, EXx }, 0 },
10940 /* VEX_W_0FD5_P_2 */
10941 { "vpmullw", { XM, Vex, EXx }, 0 },
10944 /* VEX_W_0FD6_P_2 */
10945 { "vmovq", { EXqScalarS, XMScalar }, 0 },
10948 /* VEX_W_0FD7_P_2_M_1 */
10949 { "vpmovmskb", { Gdq, XS }, 0 },
10952 /* VEX_W_0FD8_P_2 */
10953 { "vpsubusb", { XM, Vex, EXx }, 0 },
10956 /* VEX_W_0FD9_P_2 */
10957 { "vpsubusw", { XM, Vex, EXx }, 0 },
10960 /* VEX_W_0FDA_P_2 */
10961 { "vpminub", { XM, Vex, EXx }, 0 },
10964 /* VEX_W_0FDB_P_2 */
10965 { "vpand", { XM, Vex, EXx }, 0 },
10968 /* VEX_W_0FDC_P_2 */
10969 { "vpaddusb", { XM, Vex, EXx }, 0 },
10972 /* VEX_W_0FDD_P_2 */
10973 { "vpaddusw", { XM, Vex, EXx }, 0 },
10976 /* VEX_W_0FDE_P_2 */
10977 { "vpmaxub", { XM, Vex, EXx }, 0 },
10980 /* VEX_W_0FDF_P_2 */
10981 { "vpandn", { XM, Vex, EXx }, 0 },
10984 /* VEX_W_0FE0_P_2 */
10985 { "vpavgb", { XM, Vex, EXx }, 0 },
10988 /* VEX_W_0FE1_P_2 */
10989 { "vpsraw", { XM, Vex, EXxmm }, 0 },
10992 /* VEX_W_0FE2_P_2 */
10993 { "vpsrad", { XM, Vex, EXxmm }, 0 },
10996 /* VEX_W_0FE3_P_2 */
10997 { "vpavgw", { XM, Vex, EXx }, 0 },
11000 /* VEX_W_0FE4_P_2 */
11001 { "vpmulhuw", { XM, Vex, EXx }, 0 },
11004 /* VEX_W_0FE5_P_2 */
11005 { "vpmulhw", { XM, Vex, EXx }, 0 },
11008 /* VEX_W_0FE6_P_1 */
11009 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
11012 /* VEX_W_0FE6_P_2 */
11013 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
11016 /* VEX_W_0FE6_P_3 */
11017 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
11020 /* VEX_W_0FE7_P_2_M_0 */
11021 { "vmovntdq", { Mx, XM }, 0 },
11024 /* VEX_W_0FE8_P_2 */
11025 { "vpsubsb", { XM, Vex, EXx }, 0 },
11028 /* VEX_W_0FE9_P_2 */
11029 { "vpsubsw", { XM, Vex, EXx }, 0 },
11032 /* VEX_W_0FEA_P_2 */
11033 { "vpminsw", { XM, Vex, EXx }, 0 },
11036 /* VEX_W_0FEB_P_2 */
11037 { "vpor", { XM, Vex, EXx }, 0 },
11040 /* VEX_W_0FEC_P_2 */
11041 { "vpaddsb", { XM, Vex, EXx }, 0 },
11044 /* VEX_W_0FED_P_2 */
11045 { "vpaddsw", { XM, Vex, EXx }, 0 },
11048 /* VEX_W_0FEE_P_2 */
11049 { "vpmaxsw", { XM, Vex, EXx }, 0 },
11052 /* VEX_W_0FEF_P_2 */
11053 { "vpxor", { XM, Vex, EXx }, 0 },
11056 /* VEX_W_0FF0_P_3_M_0 */
11057 { "vlddqu", { XM, M }, 0 },
11060 /* VEX_W_0FF1_P_2 */
11061 { "vpsllw", { XM, Vex, EXxmm }, 0 },
11064 /* VEX_W_0FF2_P_2 */
11065 { "vpslld", { XM, Vex, EXxmm }, 0 },
11068 /* VEX_W_0FF3_P_2 */
11069 { "vpsllq", { XM, Vex, EXxmm }, 0 },
11072 /* VEX_W_0FF4_P_2 */
11073 { "vpmuludq", { XM, Vex, EXx }, 0 },
11076 /* VEX_W_0FF5_P_2 */
11077 { "vpmaddwd", { XM, Vex, EXx }, 0 },
11080 /* VEX_W_0FF6_P_2 */
11081 { "vpsadbw", { XM, Vex, EXx }, 0 },
11084 /* VEX_W_0FF7_P_2 */
11085 { "vmaskmovdqu", { XM, XS }, 0 },
11088 /* VEX_W_0FF8_P_2 */
11089 { "vpsubb", { XM, Vex, EXx }, 0 },
11092 /* VEX_W_0FF9_P_2 */
11093 { "vpsubw", { XM, Vex, EXx }, 0 },
11096 /* VEX_W_0FFA_P_2 */
11097 { "vpsubd", { XM, Vex, EXx }, 0 },
11100 /* VEX_W_0FFB_P_2 */
11101 { "vpsubq", { XM, Vex, EXx }, 0 },
11104 /* VEX_W_0FFC_P_2 */
11105 { "vpaddb", { XM, Vex, EXx }, 0 },
11108 /* VEX_W_0FFD_P_2 */
11109 { "vpaddw", { XM, Vex, EXx }, 0 },
11112 /* VEX_W_0FFE_P_2 */
11113 { "vpaddd", { XM, Vex, EXx }, 0 },
11116 /* VEX_W_0F3800_P_2 */
11117 { "vpshufb", { XM, Vex, EXx }, 0 },
11120 /* VEX_W_0F3801_P_2 */
11121 { "vphaddw", { XM, Vex, EXx }, 0 },
11124 /* VEX_W_0F3802_P_2 */
11125 { "vphaddd", { XM, Vex, EXx }, 0 },
11128 /* VEX_W_0F3803_P_2 */
11129 { "vphaddsw", { XM, Vex, EXx }, 0 },
11132 /* VEX_W_0F3804_P_2 */
11133 { "vpmaddubsw", { XM, Vex, EXx }, 0 },
11136 /* VEX_W_0F3805_P_2 */
11137 { "vphsubw", { XM, Vex, EXx }, 0 },
11140 /* VEX_W_0F3806_P_2 */
11141 { "vphsubd", { XM, Vex, EXx }, 0 },
11144 /* VEX_W_0F3807_P_2 */
11145 { "vphsubsw", { XM, Vex, EXx }, 0 },
11148 /* VEX_W_0F3808_P_2 */
11149 { "vpsignb", { XM, Vex, EXx }, 0 },
11152 /* VEX_W_0F3809_P_2 */
11153 { "vpsignw", { XM, Vex, EXx }, 0 },
11156 /* VEX_W_0F380A_P_2 */
11157 { "vpsignd", { XM, Vex, EXx }, 0 },
11160 /* VEX_W_0F380B_P_2 */
11161 { "vpmulhrsw", { XM, Vex, EXx }, 0 },
11164 /* VEX_W_0F380C_P_2 */
11165 { "vpermilps", { XM, Vex, EXx }, 0 },
11168 /* VEX_W_0F380D_P_2 */
11169 { "vpermilpd", { XM, Vex, EXx }, 0 },
11172 /* VEX_W_0F380E_P_2 */
11173 { "vtestps", { XM, EXx }, 0 },
11176 /* VEX_W_0F380F_P_2 */
11177 { "vtestpd", { XM, EXx }, 0 },
11180 /* VEX_W_0F3816_P_2 */
11181 { "vpermps", { XM, Vex, EXx }, 0 },
11184 /* VEX_W_0F3817_P_2 */
11185 { "vptest", { XM, EXx }, 0 },
11188 /* VEX_W_0F3818_P_2 */
11189 { "vbroadcastss", { XM, EXxmm_md }, 0 },
11192 /* VEX_W_0F3819_P_2 */
11193 { "vbroadcastsd", { XM, EXxmm_mq }, 0 },
11196 /* VEX_W_0F381A_P_2_M_0 */
11197 { "vbroadcastf128", { XM, Mxmm }, 0 },
11200 /* VEX_W_0F381C_P_2 */
11201 { "vpabsb", { XM, EXx }, 0 },
11204 /* VEX_W_0F381D_P_2 */
11205 { "vpabsw", { XM, EXx }, 0 },
11208 /* VEX_W_0F381E_P_2 */
11209 { "vpabsd", { XM, EXx }, 0 },
11212 /* VEX_W_0F3820_P_2 */
11213 { "vpmovsxbw", { XM, EXxmmq }, 0 },
11216 /* VEX_W_0F3821_P_2 */
11217 { "vpmovsxbd", { XM, EXxmmqd }, 0 },
11220 /* VEX_W_0F3822_P_2 */
11221 { "vpmovsxbq", { XM, EXxmmdw }, 0 },
11224 /* VEX_W_0F3823_P_2 */
11225 { "vpmovsxwd", { XM, EXxmmq }, 0 },
11228 /* VEX_W_0F3824_P_2 */
11229 { "vpmovsxwq", { XM, EXxmmqd }, 0 },
11232 /* VEX_W_0F3825_P_2 */
11233 { "vpmovsxdq", { XM, EXxmmq }, 0 },
11236 /* VEX_W_0F3828_P_2 */
11237 { "vpmuldq", { XM, Vex, EXx }, 0 },
11240 /* VEX_W_0F3829_P_2 */
11241 { "vpcmpeqq", { XM, Vex, EXx }, 0 },
11244 /* VEX_W_0F382A_P_2_M_0 */
11245 { "vmovntdqa", { XM, Mx }, 0 },
11248 /* VEX_W_0F382B_P_2 */
11249 { "vpackusdw", { XM, Vex, EXx }, 0 },
11252 /* VEX_W_0F382C_P_2_M_0 */
11253 { "vmaskmovps", { XM, Vex, Mx }, 0 },
11256 /* VEX_W_0F382D_P_2_M_0 */
11257 { "vmaskmovpd", { XM, Vex, Mx }, 0 },
11260 /* VEX_W_0F382E_P_2_M_0 */
11261 { "vmaskmovps", { Mx, Vex, XM }, 0 },
11264 /* VEX_W_0F382F_P_2_M_0 */
11265 { "vmaskmovpd", { Mx, Vex, XM }, 0 },
11268 /* VEX_W_0F3830_P_2 */
11269 { "vpmovzxbw", { XM, EXxmmq }, 0 },
11272 /* VEX_W_0F3831_P_2 */
11273 { "vpmovzxbd", { XM, EXxmmqd }, 0 },
11276 /* VEX_W_0F3832_P_2 */
11277 { "vpmovzxbq", { XM, EXxmmdw }, 0 },
11280 /* VEX_W_0F3833_P_2 */
11281 { "vpmovzxwd", { XM, EXxmmq }, 0 },
11284 /* VEX_W_0F3834_P_2 */
11285 { "vpmovzxwq", { XM, EXxmmqd }, 0 },
11288 /* VEX_W_0F3835_P_2 */
11289 { "vpmovzxdq", { XM, EXxmmq }, 0 },
11292 /* VEX_W_0F3836_P_2 */
11293 { "vpermd", { XM, Vex, EXx }, 0 },
11296 /* VEX_W_0F3837_P_2 */
11297 { "vpcmpgtq", { XM, Vex, EXx }, 0 },
11300 /* VEX_W_0F3838_P_2 */
11301 { "vpminsb", { XM, Vex, EXx }, 0 },
11304 /* VEX_W_0F3839_P_2 */
11305 { "vpminsd", { XM, Vex, EXx }, 0 },
11308 /* VEX_W_0F383A_P_2 */
11309 { "vpminuw", { XM, Vex, EXx }, 0 },
11312 /* VEX_W_0F383B_P_2 */
11313 { "vpminud", { XM, Vex, EXx }, 0 },
11316 /* VEX_W_0F383C_P_2 */
11317 { "vpmaxsb", { XM, Vex, EXx }, 0 },
11320 /* VEX_W_0F383D_P_2 */
11321 { "vpmaxsd", { XM, Vex, EXx }, 0 },
11324 /* VEX_W_0F383E_P_2 */
11325 { "vpmaxuw", { XM, Vex, EXx }, 0 },
11328 /* VEX_W_0F383F_P_2 */
11329 { "vpmaxud", { XM, Vex, EXx }, 0 },
11332 /* VEX_W_0F3840_P_2 */
11333 { "vpmulld", { XM, Vex, EXx }, 0 },
11336 /* VEX_W_0F3841_P_2 */
11337 { "vphminposuw", { XM, EXx }, 0 },
11340 /* VEX_W_0F3846_P_2 */
11341 { "vpsravd", { XM, Vex, EXx }, 0 },
11344 /* VEX_W_0F3858_P_2 */
11345 { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11348 /* VEX_W_0F3859_P_2 */
11349 { "vpbroadcastq", { XM, EXxmm_mq }, 0 },
11352 /* VEX_W_0F385A_P_2_M_0 */
11353 { "vbroadcasti128", { XM, Mxmm }, 0 },
11356 /* VEX_W_0F3878_P_2 */
11357 { "vpbroadcastb", { XM, EXxmm_mb }, 0 },
11360 /* VEX_W_0F3879_P_2 */
11361 { "vpbroadcastw", { XM, EXxmm_mw }, 0 },
11364 /* VEX_W_0F38DB_P_2 */
11365 { "vaesimc", { XM, EXx }, 0 },
11368 /* VEX_W_0F38DC_P_2 */
11369 { "vaesenc", { XM, Vex128, EXx }, 0 },
11372 /* VEX_W_0F38DD_P_2 */
11373 { "vaesenclast", { XM, Vex128, EXx }, 0 },
11376 /* VEX_W_0F38DE_P_2 */
11377 { "vaesdec", { XM, Vex128, EXx }, 0 },
11380 /* VEX_W_0F38DF_P_2 */
11381 { "vaesdeclast", { XM, Vex128, EXx }, 0 },
11384 /* VEX_W_0F3A00_P_2 */
11386 { "vpermq", { XM, EXx, Ib }, 0 },
11389 /* VEX_W_0F3A01_P_2 */
11391 { "vpermpd", { XM, EXx, Ib }, 0 },
11394 /* VEX_W_0F3A02_P_2 */
11395 { "vpblendd", { XM, Vex, EXx, Ib }, 0 },
11398 /* VEX_W_0F3A04_P_2 */
11399 { "vpermilps", { XM, EXx, Ib }, 0 },
11402 /* VEX_W_0F3A05_P_2 */
11403 { "vpermilpd", { XM, EXx, Ib }, 0 },
11406 /* VEX_W_0F3A06_P_2 */
11407 { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 },
11410 /* VEX_W_0F3A08_P_2 */
11411 { "vroundps", { XM, EXx, Ib }, 0 },
11414 /* VEX_W_0F3A09_P_2 */
11415 { "vroundpd", { XM, EXx, Ib }, 0 },
11418 /* VEX_W_0F3A0A_P_2 */
11419 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11422 /* VEX_W_0F3A0B_P_2 */
11423 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11426 /* VEX_W_0F3A0C_P_2 */
11427 { "vblendps", { XM, Vex, EXx, Ib }, 0 },
11430 /* VEX_W_0F3A0D_P_2 */
11431 { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
11434 /* VEX_W_0F3A0E_P_2 */
11435 { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
11438 /* VEX_W_0F3A0F_P_2 */
11439 { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
11442 /* VEX_W_0F3A14_P_2 */
11443 { "vpextrb", { Edqb, XM, Ib }, 0 },
11446 /* VEX_W_0F3A15_P_2 */
11447 { "vpextrw", { Edqw, XM, Ib }, 0 },
11450 /* VEX_W_0F3A18_P_2 */
11451 { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 },
11454 /* VEX_W_0F3A19_P_2 */
11455 { "vextractf128", { EXxmm, XM, Ib }, 0 },
11458 /* VEX_W_0F3A20_P_2 */
11459 { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
11462 /* VEX_W_0F3A21_P_2 */
11463 { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
11466 /* VEX_W_0F3A30_P_2_LEN_0 */
11467 { "kshiftrb", { MaskG, MaskR, Ib }, 0 },
11468 { "kshiftrw", { MaskG, MaskR, Ib }, 0 },
11471 /* VEX_W_0F3A31_P_2_LEN_0 */
11472 { "kshiftrd", { MaskG, MaskR, Ib }, 0 },
11473 { "kshiftrq", { MaskG, MaskR, Ib }, 0 },
11476 /* VEX_W_0F3A32_P_2_LEN_0 */
11477 { "kshiftlb", { MaskG, MaskR, Ib }, 0 },
11478 { "kshiftlw", { MaskG, MaskR, Ib }, 0 },
11481 /* VEX_W_0F3A33_P_2_LEN_0 */
11482 { "kshiftld", { MaskG, MaskR, Ib }, 0 },
11483 { "kshiftlq", { MaskG, MaskR, Ib }, 0 },
11486 /* VEX_W_0F3A38_P_2 */
11487 { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 },
11490 /* VEX_W_0F3A39_P_2 */
11491 { "vextracti128", { EXxmm, XM, Ib }, 0 },
11494 /* VEX_W_0F3A40_P_2 */
11495 { "vdpps", { XM, Vex, EXx, Ib }, 0 },
11498 /* VEX_W_0F3A41_P_2 */
11499 { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
11502 /* VEX_W_0F3A42_P_2 */
11503 { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
11506 /* VEX_W_0F3A44_P_2 */
11507 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL }, 0 },
11510 /* VEX_W_0F3A46_P_2 */
11511 { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
11514 /* VEX_W_0F3A48_P_2 */
11515 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11516 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11519 /* VEX_W_0F3A49_P_2 */
11520 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11521 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11524 /* VEX_W_0F3A4A_P_2 */
11525 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 },
11528 /* VEX_W_0F3A4B_P_2 */
11529 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 },
11532 /* VEX_W_0F3A4C_P_2 */
11533 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
11536 /* VEX_W_0F3A60_P_2 */
11537 { "vpcmpestrm", { XM, EXx, Ib }, 0 },
11540 /* VEX_W_0F3A61_P_2 */
11541 { "vpcmpestri", { XM, EXx, Ib }, 0 },
11544 /* VEX_W_0F3A62_P_2 */
11545 { "vpcmpistrm", { XM, EXx, Ib }, 0 },
11548 /* VEX_W_0F3A63_P_2 */
11549 { "vpcmpistri", { XM, EXx, Ib }, 0 },
11552 /* VEX_W_0F3ADF_P_2 */
11553 { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11555 #define NEED_VEX_W_TABLE
11556 #include "i386-dis-evex.h"
11557 #undef NEED_VEX_W_TABLE
11560 static const struct dis386 mod_table[][2] = {
11563 { "leaS", { Gv, M }, 0 },
11568 { RM_TABLE (RM_C6_REG_7) },
11573 { RM_TABLE (RM_C7_REG_7) },
11577 { "Jcall{T|}", { indirEp }, 0 },
11581 { "Jjmp{T|}", { indirEp }, 0 },
11584 /* MOD_0F01_REG_0 */
11585 { X86_64_TABLE (X86_64_0F01_REG_0) },
11586 { RM_TABLE (RM_0F01_REG_0) },
11589 /* MOD_0F01_REG_1 */
11590 { X86_64_TABLE (X86_64_0F01_REG_1) },
11591 { RM_TABLE (RM_0F01_REG_1) },
11594 /* MOD_0F01_REG_2 */
11595 { X86_64_TABLE (X86_64_0F01_REG_2) },
11596 { RM_TABLE (RM_0F01_REG_2) },
11599 /* MOD_0F01_REG_3 */
11600 { X86_64_TABLE (X86_64_0F01_REG_3) },
11601 { RM_TABLE (RM_0F01_REG_3) },
11604 /* MOD_0F01_REG_7 */
11605 { "invlpg", { Mb }, 0 },
11606 { RM_TABLE (RM_0F01_REG_7) },
11609 /* MOD_0F12_PREFIX_0 */
11610 { "movlps", { XM, EXq }, PREFIX_OPCODE },
11611 { "movhlps", { XM, EXq }, PREFIX_OPCODE },
11615 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
11618 /* MOD_0F16_PREFIX_0 */
11619 { "movhps", { XM, EXq }, 0 },
11620 { "movlhps", { XM, EXq }, 0 },
11624 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
11627 /* MOD_0F18_REG_0 */
11628 { "prefetchnta", { Mb }, 0 },
11631 /* MOD_0F18_REG_1 */
11632 { "prefetcht0", { Mb }, 0 },
11635 /* MOD_0F18_REG_2 */
11636 { "prefetcht1", { Mb }, 0 },
11639 /* MOD_0F18_REG_3 */
11640 { "prefetcht2", { Mb }, 0 },
11643 /* MOD_0F18_REG_4 */
11644 { "nop/reserved", { Mb }, 0 },
11647 /* MOD_0F18_REG_5 */
11648 { "nop/reserved", { Mb }, 0 },
11651 /* MOD_0F18_REG_6 */
11652 { "nop/reserved", { Mb }, 0 },
11655 /* MOD_0F18_REG_7 */
11656 { "nop/reserved", { Mb }, 0 },
11659 /* MOD_0F1A_PREFIX_0 */
11660 { "bndldx", { Gbnd, Ev_bnd }, 0 },
11661 { "nopQ", { Ev }, 0 },
11664 /* MOD_0F1B_PREFIX_0 */
11665 { "bndstx", { Ev_bnd, Gbnd }, 0 },
11666 { "nopQ", { Ev }, 0 },
11669 /* MOD_0F1B_PREFIX_1 */
11670 { "bndmk", { Gbnd, Ev_bnd }, 0 },
11671 { "nopQ", { Ev }, 0 },
11676 { "movL", { Rd, Td }, 0 },
11681 { "movL", { Td, Rd }, 0 },
11684 /* MOD_0F2B_PREFIX_0 */
11685 {"movntps", { Mx, XM }, PREFIX_OPCODE },
11688 /* MOD_0F2B_PREFIX_1 */
11689 {"movntss", { Md, XM }, PREFIX_OPCODE },
11692 /* MOD_0F2B_PREFIX_2 */
11693 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
11696 /* MOD_0F2B_PREFIX_3 */
11697 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
11702 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
11705 /* MOD_0F71_REG_2 */
11707 { "psrlw", { MS, Ib }, 0 },
11710 /* MOD_0F71_REG_4 */
11712 { "psraw", { MS, Ib }, 0 },
11715 /* MOD_0F71_REG_6 */
11717 { "psllw", { MS, Ib }, 0 },
11720 /* MOD_0F72_REG_2 */
11722 { "psrld", { MS, Ib }, 0 },
11725 /* MOD_0F72_REG_4 */
11727 { "psrad", { MS, Ib }, 0 },
11730 /* MOD_0F72_REG_6 */
11732 { "pslld", { MS, Ib }, 0 },
11735 /* MOD_0F73_REG_2 */
11737 { "psrlq", { MS, Ib }, 0 },
11740 /* MOD_0F73_REG_3 */
11742 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11745 /* MOD_0F73_REG_6 */
11747 { "psllq", { MS, Ib }, 0 },
11750 /* MOD_0F73_REG_7 */
11752 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11755 /* MOD_0FAE_REG_0 */
11756 { "fxsave", { FXSAVE }, 0 },
11757 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11760 /* MOD_0FAE_REG_1 */
11761 { "fxrstor", { FXSAVE }, 0 },
11762 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11765 /* MOD_0FAE_REG_2 */
11766 { "ldmxcsr", { Md }, 0 },
11767 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11770 /* MOD_0FAE_REG_3 */
11771 { "stmxcsr", { Md }, 0 },
11772 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11775 /* MOD_0FAE_REG_4 */
11776 { "xsave", { FXSAVE }, 0 },
11779 /* MOD_0FAE_REG_5 */
11780 { "xrstor", { FXSAVE }, 0 },
11781 { RM_TABLE (RM_0FAE_REG_5) },
11784 /* MOD_0FAE_REG_6 */
11785 { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11786 { RM_TABLE (RM_0FAE_REG_6) },
11789 /* MOD_0FAE_REG_7 */
11790 { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11791 { RM_TABLE (RM_0FAE_REG_7) },
11795 { "lssS", { Gv, Mp }, 0 },
11799 { "lfsS", { Gv, Mp }, 0 },
11803 { "lgsS", { Gv, Mp }, 0 },
11806 /* MOD_0FC7_REG_3 */
11807 { "xrstors", { FXSAVE }, 0 },
11810 /* MOD_0FC7_REG_4 */
11811 { "xsavec", { FXSAVE }, 0 },
11814 /* MOD_0FC7_REG_5 */
11815 { "xsaves", { FXSAVE }, 0 },
11818 /* MOD_0FC7_REG_6 */
11819 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11820 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11823 /* MOD_0FC7_REG_7 */
11824 { "vmptrst", { Mq }, 0 },
11825 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11830 { "pmovmskb", { Gdq, MS }, 0 },
11833 /* MOD_0FE7_PREFIX_2 */
11834 { "movntdq", { Mx, XM }, 0 },
11837 /* MOD_0FF0_PREFIX_3 */
11838 { "lddqu", { XM, M }, 0 },
11841 /* MOD_0F382A_PREFIX_2 */
11842 { "movntdqa", { XM, Mx }, 0 },
11846 { "bound{S|}", { Gv, Ma }, 0 },
11847 { EVEX_TABLE (EVEX_0F) },
11851 { "lesS", { Gv, Mp }, 0 },
11852 { VEX_C4_TABLE (VEX_0F) },
11856 { "ldsS", { Gv, Mp }, 0 },
11857 { VEX_C5_TABLE (VEX_0F) },
11860 /* MOD_VEX_0F12_PREFIX_0 */
11861 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11862 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11866 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11869 /* MOD_VEX_0F16_PREFIX_0 */
11870 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11871 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11875 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11879 { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11884 { VEX_W_TABLE (VEX_W_0F50_M_0) },
11887 /* MOD_VEX_0F71_REG_2 */
11889 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11892 /* MOD_VEX_0F71_REG_4 */
11894 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11897 /* MOD_VEX_0F71_REG_6 */
11899 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11902 /* MOD_VEX_0F72_REG_2 */
11904 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11907 /* MOD_VEX_0F72_REG_4 */
11909 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11912 /* MOD_VEX_0F72_REG_6 */
11914 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11917 /* MOD_VEX_0F73_REG_2 */
11919 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11922 /* MOD_VEX_0F73_REG_3 */
11924 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11927 /* MOD_VEX_0F73_REG_6 */
11929 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11932 /* MOD_VEX_0F73_REG_7 */
11934 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11937 /* MOD_VEX_0FAE_REG_2 */
11938 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11941 /* MOD_VEX_0FAE_REG_3 */
11942 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11945 /* MOD_VEX_0FD7_PREFIX_2 */
11947 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11950 /* MOD_VEX_0FE7_PREFIX_2 */
11951 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11954 /* MOD_VEX_0FF0_PREFIX_3 */
11955 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11958 /* MOD_VEX_0F381A_PREFIX_2 */
11959 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11962 /* MOD_VEX_0F382A_PREFIX_2 */
11963 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11966 /* MOD_VEX_0F382C_PREFIX_2 */
11967 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11970 /* MOD_VEX_0F382D_PREFIX_2 */
11971 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11974 /* MOD_VEX_0F382E_PREFIX_2 */
11975 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11978 /* MOD_VEX_0F382F_PREFIX_2 */
11979 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11982 /* MOD_VEX_0F385A_PREFIX_2 */
11983 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11986 /* MOD_VEX_0F388C_PREFIX_2 */
11987 { "vpmaskmov%LW", { XM, Vex, Mx }, 0 },
11990 /* MOD_VEX_0F388E_PREFIX_2 */
11991 { "vpmaskmov%LW", { Mx, Vex, XM }, 0 },
11993 #define NEED_MOD_TABLE
11994 #include "i386-dis-evex.h"
11995 #undef NEED_MOD_TABLE
11998 static const struct dis386 rm_table[][8] = {
12001 { "xabort", { Skip_MODRM, Ib }, 0 },
12005 { "xbeginT", { Skip_MODRM, Jv }, 0 },
12008 /* RM_0F01_REG_0 */
12010 { "vmcall", { Skip_MODRM }, 0 },
12011 { "vmlaunch", { Skip_MODRM }, 0 },
12012 { "vmresume", { Skip_MODRM }, 0 },
12013 { "vmxoff", { Skip_MODRM }, 0 },
12016 /* RM_0F01_REG_1 */
12017 { "monitor", { { OP_Monitor, 0 } }, 0 },
12018 { "mwait", { { OP_Mwait, 0 } }, 0 },
12019 { "clac", { Skip_MODRM }, 0 },
12020 { "stac", { Skip_MODRM }, 0 },
12024 { "encls", { Skip_MODRM }, 0 },
12027 /* RM_0F01_REG_2 */
12028 { "xgetbv", { Skip_MODRM }, 0 },
12029 { "xsetbv", { Skip_MODRM }, 0 },
12032 { "vmfunc", { Skip_MODRM }, 0 },
12033 { "xend", { Skip_MODRM }, 0 },
12034 { "xtest", { Skip_MODRM }, 0 },
12035 { "enclu", { Skip_MODRM }, 0 },
12038 /* RM_0F01_REG_3 */
12039 { "vmrun", { Skip_MODRM }, 0 },
12040 { "vmmcall", { Skip_MODRM }, 0 },
12041 { "vmload", { Skip_MODRM }, 0 },
12042 { "vmsave", { Skip_MODRM }, 0 },
12043 { "stgi", { Skip_MODRM }, 0 },
12044 { "clgi", { Skip_MODRM }, 0 },
12045 { "skinit", { Skip_MODRM }, 0 },
12046 { "invlpga", { Skip_MODRM }, 0 },
12049 /* RM_0F01_REG_7 */
12050 { "swapgs", { Skip_MODRM }, 0 },
12051 { "rdtscp", { Skip_MODRM }, 0 },
12054 { "clzero", { Skip_MODRM }, 0 },
12057 /* RM_0FAE_REG_5 */
12058 { "lfence", { Skip_MODRM }, 0 },
12061 /* RM_0FAE_REG_6 */
12062 { "mfence", { Skip_MODRM }, 0 },
12065 /* RM_0FAE_REG_7 */
12066 { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) },
12070 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12072 /* We use the high bit to indicate different name for the same
12074 #define REP_PREFIX (0xf3 | 0x100)
12075 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12076 #define XRELEASE_PREFIX (0xf3 | 0x400)
12077 #define BND_PREFIX (0xf2 | 0x400)
12082 int newrex, i, length;
12088 last_lock_prefix = -1;
12089 last_repz_prefix = -1;
12090 last_repnz_prefix = -1;
12091 last_data_prefix = -1;
12092 last_addr_prefix = -1;
12093 last_rex_prefix = -1;
12094 last_seg_prefix = -1;
12096 active_seg_prefix = 0;
12097 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12098 all_prefixes[i] = 0;
12101 /* The maximum instruction length is 15bytes. */
12102 while (length < MAX_CODE_LENGTH - 1)
12104 FETCH_DATA (the_info, codep + 1);
12108 /* REX prefixes family. */
12125 if (address_mode == mode_64bit)
12129 last_rex_prefix = i;
12132 prefixes |= PREFIX_REPZ;
12133 last_repz_prefix = i;
12136 prefixes |= PREFIX_REPNZ;
12137 last_repnz_prefix = i;
12140 prefixes |= PREFIX_LOCK;
12141 last_lock_prefix = i;
12144 prefixes |= PREFIX_CS;
12145 last_seg_prefix = i;
12146 active_seg_prefix = PREFIX_CS;
12149 prefixes |= PREFIX_SS;
12150 last_seg_prefix = i;
12151 active_seg_prefix = PREFIX_SS;
12154 prefixes |= PREFIX_DS;
12155 last_seg_prefix = i;
12156 active_seg_prefix = PREFIX_DS;
12159 prefixes |= PREFIX_ES;
12160 last_seg_prefix = i;
12161 active_seg_prefix = PREFIX_ES;
12164 prefixes |= PREFIX_FS;
12165 last_seg_prefix = i;
12166 active_seg_prefix = PREFIX_FS;
12169 prefixes |= PREFIX_GS;
12170 last_seg_prefix = i;
12171 active_seg_prefix = PREFIX_GS;
12174 prefixes |= PREFIX_DATA;
12175 last_data_prefix = i;
12178 prefixes |= PREFIX_ADDR;
12179 last_addr_prefix = i;
12182 /* fwait is really an instruction. If there are prefixes
12183 before the fwait, they belong to the fwait, *not* to the
12184 following instruction. */
12186 if (prefixes || rex)
12188 prefixes |= PREFIX_FWAIT;
12190 /* This ensures that the previous REX prefixes are noticed
12191 as unused prefixes, as in the return case below. */
12195 prefixes = PREFIX_FWAIT;
12200 /* Rex is ignored when followed by another prefix. */
12206 if (*codep != FWAIT_OPCODE)
12207 all_prefixes[i++] = *codep;
12215 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12218 static const char *
12219 prefix_name (int pref, int sizeflag)
12221 static const char *rexes [16] =
12224 "rex.B", /* 0x41 */
12225 "rex.X", /* 0x42 */
12226 "rex.XB", /* 0x43 */
12227 "rex.R", /* 0x44 */
12228 "rex.RB", /* 0x45 */
12229 "rex.RX", /* 0x46 */
12230 "rex.RXB", /* 0x47 */
12231 "rex.W", /* 0x48 */
12232 "rex.WB", /* 0x49 */
12233 "rex.WX", /* 0x4a */
12234 "rex.WXB", /* 0x4b */
12235 "rex.WR", /* 0x4c */
12236 "rex.WRB", /* 0x4d */
12237 "rex.WRX", /* 0x4e */
12238 "rex.WRXB", /* 0x4f */
12243 /* REX prefixes family. */
12260 return rexes [pref - 0x40];
12280 return (sizeflag & DFLAG) ? "data16" : "data32";
12282 if (address_mode == mode_64bit)
12283 return (sizeflag & AFLAG) ? "addr32" : "addr64";
12285 return (sizeflag & AFLAG) ? "addr16" : "addr32";
12290 case XACQUIRE_PREFIX:
12292 case XRELEASE_PREFIX:
12301 static char op_out[MAX_OPERANDS][100];
12302 static int op_ad, op_index[MAX_OPERANDS];
12303 static int two_source_ops;
12304 static bfd_vma op_address[MAX_OPERANDS];
12305 static bfd_vma op_riprel[MAX_OPERANDS];
12306 static bfd_vma start_pc;
12309 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12310 * (see topic "Redundant prefixes" in the "Differences from 8086"
12311 * section of the "Virtual 8086 Mode" chapter.)
12312 * 'pc' should be the address of this instruction, it will
12313 * be used to print the target address if this is a relative jump or call
12314 * The function returns the length of this instruction in bytes.
12317 static char intel_syntax;
12318 static char intel_mnemonic = !SYSV386_COMPAT;
12319 static char open_char;
12320 static char close_char;
12321 static char separator_char;
12322 static char scale_char;
12324 /* Here for backwards compatibility. When gdb stops using
12325 print_insn_i386_att and print_insn_i386_intel these functions can
12326 disappear, and print_insn_i386 be merged into print_insn. */
12328 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12332 return print_insn (pc, info);
12336 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12340 return print_insn (pc, info);
12344 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12348 return print_insn (pc, info);
12352 print_i386_disassembler_options (FILE *stream)
12354 fprintf (stream, _("\n\
12355 The following i386/x86-64 specific disassembler options are supported for use\n\
12356 with the -M switch (multiple options should be separated by commas):\n"));
12358 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
12359 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
12360 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
12361 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
12362 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
12363 fprintf (stream, _(" att-mnemonic\n"
12364 " Display instruction in AT&T mnemonic\n"));
12365 fprintf (stream, _(" intel-mnemonic\n"
12366 " Display instruction in Intel mnemonic\n"));
12367 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
12368 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
12369 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
12370 fprintf (stream, _(" data32 Assume 32bit data size\n"));
12371 fprintf (stream, _(" data16 Assume 16bit data size\n"));
12372 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12376 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12378 /* Get a pointer to struct dis386 with a valid name. */
12380 static const struct dis386 *
12381 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12383 int vindex, vex_table_index;
12385 if (dp->name != NULL)
12388 switch (dp->op[0].bytemode)
12390 case USE_REG_TABLE:
12391 dp = ®_table[dp->op[1].bytemode][modrm.reg];
12394 case USE_MOD_TABLE:
12395 vindex = modrm.mod == 0x3 ? 1 : 0;
12396 dp = &mod_table[dp->op[1].bytemode][vindex];
12400 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12403 case USE_PREFIX_TABLE:
12406 /* The prefix in VEX is implicit. */
12407 switch (vex.prefix)
12412 case REPE_PREFIX_OPCODE:
12415 case DATA_PREFIX_OPCODE:
12418 case REPNE_PREFIX_OPCODE:
12428 int last_prefix = -1;
12431 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12432 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12434 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12436 if (last_repz_prefix > last_repnz_prefix)
12439 prefix = PREFIX_REPZ;
12440 last_prefix = last_repz_prefix;
12445 prefix = PREFIX_REPNZ;
12446 last_prefix = last_repnz_prefix;
12449 /* Check if prefix should be ignored. */
12450 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12451 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12456 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12459 prefix = PREFIX_DATA;
12460 last_prefix = last_data_prefix;
12465 used_prefixes |= prefix;
12466 all_prefixes[last_prefix] = 0;
12469 dp = &prefix_table[dp->op[1].bytemode][vindex];
12472 case USE_X86_64_TABLE:
12473 vindex = address_mode == mode_64bit ? 1 : 0;
12474 dp = &x86_64_table[dp->op[1].bytemode][vindex];
12477 case USE_3BYTE_TABLE:
12478 FETCH_DATA (info, codep + 2);
12480 dp = &three_byte_table[dp->op[1].bytemode][vindex];
12482 modrm.mod = (*codep >> 6) & 3;
12483 modrm.reg = (*codep >> 3) & 7;
12484 modrm.rm = *codep & 7;
12487 case USE_VEX_LEN_TABLE:
12491 switch (vex.length)
12504 dp = &vex_len_table[dp->op[1].bytemode][vindex];
12507 case USE_XOP_8F_TABLE:
12508 FETCH_DATA (info, codep + 3);
12509 /* All bits in the REX prefix are ignored. */
12511 rex = ~(*codep >> 5) & 0x7;
12513 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12514 switch ((*codep & 0x1f))
12520 vex_table_index = XOP_08;
12523 vex_table_index = XOP_09;
12526 vex_table_index = XOP_0A;
12530 vex.w = *codep & 0x80;
12531 if (vex.w && address_mode == mode_64bit)
12534 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12535 if (address_mode != mode_64bit
12536 && vex.register_specifier > 0x7)
12542 vex.length = (*codep & 0x4) ? 256 : 128;
12543 switch ((*codep & 0x3))
12549 vex.prefix = DATA_PREFIX_OPCODE;
12552 vex.prefix = REPE_PREFIX_OPCODE;
12555 vex.prefix = REPNE_PREFIX_OPCODE;
12562 dp = &xop_table[vex_table_index][vindex];
12565 FETCH_DATA (info, codep + 1);
12566 modrm.mod = (*codep >> 6) & 3;
12567 modrm.reg = (*codep >> 3) & 7;
12568 modrm.rm = *codep & 7;
12571 case USE_VEX_C4_TABLE:
12573 FETCH_DATA (info, codep + 3);
12574 /* All bits in the REX prefix are ignored. */
12576 rex = ~(*codep >> 5) & 0x7;
12577 switch ((*codep & 0x1f))
12583 vex_table_index = VEX_0F;
12586 vex_table_index = VEX_0F38;
12589 vex_table_index = VEX_0F3A;
12593 vex.w = *codep & 0x80;
12594 if (vex.w && address_mode == mode_64bit)
12597 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12598 if (address_mode != mode_64bit
12599 && vex.register_specifier > 0x7)
12605 vex.length = (*codep & 0x4) ? 256 : 128;
12606 switch ((*codep & 0x3))
12612 vex.prefix = DATA_PREFIX_OPCODE;
12615 vex.prefix = REPE_PREFIX_OPCODE;
12618 vex.prefix = REPNE_PREFIX_OPCODE;
12625 dp = &vex_table[vex_table_index][vindex];
12627 /* There is no MODRM byte for VEX [82|77]. */
12628 if (vindex != 0x77 && vindex != 0x82)
12630 FETCH_DATA (info, codep + 1);
12631 modrm.mod = (*codep >> 6) & 3;
12632 modrm.reg = (*codep >> 3) & 7;
12633 modrm.rm = *codep & 7;
12637 case USE_VEX_C5_TABLE:
12639 FETCH_DATA (info, codep + 2);
12640 /* All bits in the REX prefix are ignored. */
12642 rex = (*codep & 0x80) ? 0 : REX_R;
12644 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12645 if (address_mode != mode_64bit
12646 && vex.register_specifier > 0x7)
12654 vex.length = (*codep & 0x4) ? 256 : 128;
12655 switch ((*codep & 0x3))
12661 vex.prefix = DATA_PREFIX_OPCODE;
12664 vex.prefix = REPE_PREFIX_OPCODE;
12667 vex.prefix = REPNE_PREFIX_OPCODE;
12674 dp = &vex_table[dp->op[1].bytemode][vindex];
12676 /* There is no MODRM byte for VEX [82|77]. */
12677 if (vindex != 0x77 && vindex != 0x82)
12679 FETCH_DATA (info, codep + 1);
12680 modrm.mod = (*codep >> 6) & 3;
12681 modrm.reg = (*codep >> 3) & 7;
12682 modrm.rm = *codep & 7;
12686 case USE_VEX_W_TABLE:
12690 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12693 case USE_EVEX_TABLE:
12694 two_source_ops = 0;
12697 FETCH_DATA (info, codep + 4);
12698 /* All bits in the REX prefix are ignored. */
12700 /* The first byte after 0x62. */
12701 rex = ~(*codep >> 5) & 0x7;
12702 vex.r = *codep & 0x10;
12703 switch ((*codep & 0xf))
12706 return &bad_opcode;
12708 vex_table_index = EVEX_0F;
12711 vex_table_index = EVEX_0F38;
12714 vex_table_index = EVEX_0F3A;
12718 /* The second byte after 0x62. */
12720 vex.w = *codep & 0x80;
12721 if (vex.w && address_mode == mode_64bit)
12724 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12725 if (address_mode != mode_64bit)
12727 /* In 16/32-bit mode silently ignore following bits. */
12731 vex.register_specifier &= 0x7;
12735 if (!(*codep & 0x4))
12736 return &bad_opcode;
12738 switch ((*codep & 0x3))
12744 vex.prefix = DATA_PREFIX_OPCODE;
12747 vex.prefix = REPE_PREFIX_OPCODE;
12750 vex.prefix = REPNE_PREFIX_OPCODE;
12754 /* The third byte after 0x62. */
12757 /* Remember the static rounding bits. */
12758 vex.ll = (*codep >> 5) & 3;
12759 vex.b = (*codep & 0x10) != 0;
12761 vex.v = *codep & 0x8;
12762 vex.mask_register_specifier = *codep & 0x7;
12763 vex.zeroing = *codep & 0x80;
12769 dp = &evex_table[vex_table_index][vindex];
12771 FETCH_DATA (info, codep + 1);
12772 modrm.mod = (*codep >> 6) & 3;
12773 modrm.reg = (*codep >> 3) & 7;
12774 modrm.rm = *codep & 7;
12776 /* Set vector length. */
12777 if (modrm.mod == 3 && vex.b)
12793 return &bad_opcode;
12806 if (dp->name != NULL)
12809 return get_valid_dis386 (dp, info);
12813 get_sib (disassemble_info *info, int sizeflag)
12815 /* If modrm.mod == 3, operand must be register. */
12817 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12821 FETCH_DATA (info, codep + 2);
12822 sib.index = (codep [1] >> 3) & 7;
12823 sib.scale = (codep [1] >> 6) & 3;
12824 sib.base = codep [1] & 7;
12829 print_insn (bfd_vma pc, disassemble_info *info)
12831 const struct dis386 *dp;
12833 char *op_txt[MAX_OPERANDS];
12835 int sizeflag, orig_sizeflag;
12837 struct dis_private priv;
12840 priv.orig_sizeflag = AFLAG | DFLAG;
12841 if ((info->mach & bfd_mach_i386_i386) != 0)
12842 address_mode = mode_32bit;
12843 else if (info->mach == bfd_mach_i386_i8086)
12845 address_mode = mode_16bit;
12846 priv.orig_sizeflag = 0;
12849 address_mode = mode_64bit;
12851 if (intel_syntax == (char) -1)
12852 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12854 for (p = info->disassembler_options; p != NULL; )
12856 if (CONST_STRNEQ (p, "x86-64"))
12858 address_mode = mode_64bit;
12859 priv.orig_sizeflag = AFLAG | DFLAG;
12861 else if (CONST_STRNEQ (p, "i386"))
12863 address_mode = mode_32bit;
12864 priv.orig_sizeflag = AFLAG | DFLAG;
12866 else if (CONST_STRNEQ (p, "i8086"))
12868 address_mode = mode_16bit;
12869 priv.orig_sizeflag = 0;
12871 else if (CONST_STRNEQ (p, "intel"))
12874 if (CONST_STRNEQ (p + 5, "-mnemonic"))
12875 intel_mnemonic = 1;
12877 else if (CONST_STRNEQ (p, "att"))
12880 if (CONST_STRNEQ (p + 3, "-mnemonic"))
12881 intel_mnemonic = 0;
12883 else if (CONST_STRNEQ (p, "addr"))
12885 if (address_mode == mode_64bit)
12887 if (p[4] == '3' && p[5] == '2')
12888 priv.orig_sizeflag &= ~AFLAG;
12889 else if (p[4] == '6' && p[5] == '4')
12890 priv.orig_sizeflag |= AFLAG;
12894 if (p[4] == '1' && p[5] == '6')
12895 priv.orig_sizeflag &= ~AFLAG;
12896 else if (p[4] == '3' && p[5] == '2')
12897 priv.orig_sizeflag |= AFLAG;
12900 else if (CONST_STRNEQ (p, "data"))
12902 if (p[4] == '1' && p[5] == '6')
12903 priv.orig_sizeflag &= ~DFLAG;
12904 else if (p[4] == '3' && p[5] == '2')
12905 priv.orig_sizeflag |= DFLAG;
12907 else if (CONST_STRNEQ (p, "suffix"))
12908 priv.orig_sizeflag |= SUFFIX_ALWAYS;
12910 p = strchr (p, ',');
12917 names64 = intel_names64;
12918 names32 = intel_names32;
12919 names16 = intel_names16;
12920 names8 = intel_names8;
12921 names8rex = intel_names8rex;
12922 names_seg = intel_names_seg;
12923 names_mm = intel_names_mm;
12924 names_bnd = intel_names_bnd;
12925 names_xmm = intel_names_xmm;
12926 names_ymm = intel_names_ymm;
12927 names_zmm = intel_names_zmm;
12928 index64 = intel_index64;
12929 index32 = intel_index32;
12930 names_mask = intel_names_mask;
12931 index16 = intel_index16;
12934 separator_char = '+';
12939 names64 = att_names64;
12940 names32 = att_names32;
12941 names16 = att_names16;
12942 names8 = att_names8;
12943 names8rex = att_names8rex;
12944 names_seg = att_names_seg;
12945 names_mm = att_names_mm;
12946 names_bnd = att_names_bnd;
12947 names_xmm = att_names_xmm;
12948 names_ymm = att_names_ymm;
12949 names_zmm = att_names_zmm;
12950 index64 = att_index64;
12951 index32 = att_index32;
12952 names_mask = att_names_mask;
12953 index16 = att_index16;
12956 separator_char = ',';
12960 /* The output looks better if we put 7 bytes on a line, since that
12961 puts most long word instructions on a single line. Use 8 bytes
12963 if ((info->mach & bfd_mach_l1om) != 0)
12964 info->bytes_per_line = 8;
12966 info->bytes_per_line = 7;
12968 info->private_data = &priv;
12969 priv.max_fetched = priv.the_buffer;
12970 priv.insn_start = pc;
12973 for (i = 0; i < MAX_OPERANDS; ++i)
12981 start_codep = priv.the_buffer;
12982 codep = priv.the_buffer;
12984 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12988 /* Getting here means we tried for data but didn't get it. That
12989 means we have an incomplete instruction of some sort. Just
12990 print the first byte as a prefix or a .byte pseudo-op. */
12991 if (codep > priv.the_buffer)
12993 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12995 (*info->fprintf_func) (info->stream, "%s", name);
12998 /* Just print the first byte as a .byte instruction. */
12999 (*info->fprintf_func) (info->stream, ".byte 0x%x",
13000 (unsigned int) priv.the_buffer[0]);
13010 sizeflag = priv.orig_sizeflag;
13012 if (!ckprefix () || rex_used)
13014 /* Too many prefixes or unused REX prefixes. */
13016 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13018 (*info->fprintf_func) (info->stream, "%s%s",
13020 prefix_name (all_prefixes[i], sizeflag));
13024 insn_codep = codep;
13026 FETCH_DATA (info, codep + 1);
13027 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13029 if (((prefixes & PREFIX_FWAIT)
13030 && ((*codep < 0xd8) || (*codep > 0xdf))))
13032 /* Handle prefixes before fwait. */
13033 for (i = 0; i < fwait_prefix && all_prefixes[i];
13035 (*info->fprintf_func) (info->stream, "%s ",
13036 prefix_name (all_prefixes[i], sizeflag));
13037 (*info->fprintf_func) (info->stream, "fwait");
13041 if (*codep == 0x0f)
13043 unsigned char threebyte;
13044 FETCH_DATA (info, codep + 2);
13045 threebyte = *++codep;
13046 dp = &dis386_twobyte[threebyte];
13047 need_modrm = twobyte_has_modrm[*codep];
13052 dp = &dis386[*codep];
13053 need_modrm = onebyte_has_modrm[*codep];
13057 /* Save sizeflag for printing the extra prefixes later before updating
13058 it for mnemonic and operand processing. The prefix names depend
13059 only on the address mode. */
13060 orig_sizeflag = sizeflag;
13061 if (prefixes & PREFIX_ADDR)
13063 if ((prefixes & PREFIX_DATA))
13069 FETCH_DATA (info, codep + 1);
13070 modrm.mod = (*codep >> 6) & 3;
13071 modrm.reg = (*codep >> 3) & 7;
13072 modrm.rm = *codep & 7;
13080 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13082 get_sib (info, sizeflag);
13083 dofloat (sizeflag);
13087 dp = get_valid_dis386 (dp, info);
13088 if (dp != NULL && putop (dp->name, sizeflag) == 0)
13090 get_sib (info, sizeflag);
13091 for (i = 0; i < MAX_OPERANDS; ++i)
13094 op_ad = MAX_OPERANDS - 1 - i;
13096 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13097 /* For EVEX instruction after the last operand masking
13098 should be printed. */
13099 if (i == 0 && vex.evex)
13101 /* Don't print {%k0}. */
13102 if (vex.mask_register_specifier)
13105 oappend (names_mask[vex.mask_register_specifier]);
13115 /* Check if the REX prefix is used. */
13116 if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13117 all_prefixes[last_rex_prefix] = 0;
13119 /* Check if the SEG prefix is used. */
13120 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13121 | PREFIX_FS | PREFIX_GS)) != 0
13122 && (used_prefixes & active_seg_prefix) != 0)
13123 all_prefixes[last_seg_prefix] = 0;
13125 /* Check if the ADDR prefix is used. */
13126 if ((prefixes & PREFIX_ADDR) != 0
13127 && (used_prefixes & PREFIX_ADDR) != 0)
13128 all_prefixes[last_addr_prefix] = 0;
13130 /* Check if the DATA prefix is used. */
13131 if ((prefixes & PREFIX_DATA) != 0
13132 && (used_prefixes & PREFIX_DATA) != 0)
13133 all_prefixes[last_data_prefix] = 0;
13135 /* Print the extra prefixes. */
13137 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13138 if (all_prefixes[i])
13141 name = prefix_name (all_prefixes[i], orig_sizeflag);
13144 prefix_length += strlen (name) + 1;
13145 (*info->fprintf_func) (info->stream, "%s ", name);
13148 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13149 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13150 used by putop and MMX/SSE operand and may be overriden by the
13151 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13153 if (dp->prefix_requirement == PREFIX_OPCODE
13154 && dp != &bad_opcode
13156 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13158 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13160 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13162 && (used_prefixes & PREFIX_DATA) == 0))))
13164 (*info->fprintf_func) (info->stream, "(bad)");
13165 return end_codep - priv.the_buffer;
13168 /* Check maximum code length. */
13169 if ((codep - start_codep) > MAX_CODE_LENGTH)
13171 (*info->fprintf_func) (info->stream, "(bad)");
13172 return MAX_CODE_LENGTH;
13175 obufp = mnemonicendp;
13176 for (i = strlen (obuf) + prefix_length; i < 6; i++)
13179 (*info->fprintf_func) (info->stream, "%s", obuf);
13181 /* The enter and bound instructions are printed with operands in the same
13182 order as the intel book; everything else is printed in reverse order. */
13183 if (intel_syntax || two_source_ops)
13187 for (i = 0; i < MAX_OPERANDS; ++i)
13188 op_txt[i] = op_out[i];
13190 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13192 op_ad = op_index[i];
13193 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13194 op_index[MAX_OPERANDS - 1 - i] = op_ad;
13195 riprel = op_riprel[i];
13196 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13197 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13202 for (i = 0; i < MAX_OPERANDS; ++i)
13203 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13207 for (i = 0; i < MAX_OPERANDS; ++i)
13211 (*info->fprintf_func) (info->stream, ",");
13212 if (op_index[i] != -1 && !op_riprel[i])
13213 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13215 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13219 for (i = 0; i < MAX_OPERANDS; i++)
13220 if (op_index[i] != -1 && op_riprel[i])
13222 (*info->fprintf_func) (info->stream, " # ");
13223 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
13224 + op_address[op_index[i]]), info);
13227 return codep - priv.the_buffer;
13230 static const char *float_mem[] = {
13305 static const unsigned char float_mem_mode[] = {
13380 #define ST { OP_ST, 0 }
13381 #define STi { OP_STi, 0 }
13383 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13384 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13385 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13386 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13387 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13388 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13389 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13390 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13391 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13393 static const struct dis386 float_reg[][8] = {
13396 { "fadd", { ST, STi }, 0 },
13397 { "fmul", { ST, STi }, 0 },
13398 { "fcom", { STi }, 0 },
13399 { "fcomp", { STi }, 0 },
13400 { "fsub", { ST, STi }, 0 },
13401 { "fsubr", { ST, STi }, 0 },
13402 { "fdiv", { ST, STi }, 0 },
13403 { "fdivr", { ST, STi }, 0 },
13407 { "fld", { STi }, 0 },
13408 { "fxch", { STi }, 0 },
13418 { "fcmovb", { ST, STi }, 0 },
13419 { "fcmove", { ST, STi }, 0 },
13420 { "fcmovbe",{ ST, STi }, 0 },
13421 { "fcmovu", { ST, STi }, 0 },
13429 { "fcmovnb",{ ST, STi }, 0 },
13430 { "fcmovne",{ ST, STi }, 0 },
13431 { "fcmovnbe",{ ST, STi }, 0 },
13432 { "fcmovnu",{ ST, STi }, 0 },
13434 { "fucomi", { ST, STi }, 0 },
13435 { "fcomi", { ST, STi }, 0 },
13440 { "fadd", { STi, ST }, 0 },
13441 { "fmul", { STi, ST }, 0 },
13444 { "fsub!M", { STi, ST }, 0 },
13445 { "fsubM", { STi, ST }, 0 },
13446 { "fdiv!M", { STi, ST }, 0 },
13447 { "fdivM", { STi, ST }, 0 },
13451 { "ffree", { STi }, 0 },
13453 { "fst", { STi }, 0 },
13454 { "fstp", { STi }, 0 },
13455 { "fucom", { STi }, 0 },
13456 { "fucomp", { STi }, 0 },
13462 { "faddp", { STi, ST }, 0 },
13463 { "fmulp", { STi, ST }, 0 },
13466 { "fsub!Mp", { STi, ST }, 0 },
13467 { "fsubMp", { STi, ST }, 0 },
13468 { "fdiv!Mp", { STi, ST }, 0 },
13469 { "fdivMp", { STi, ST }, 0 },
13473 { "ffreep", { STi }, 0 },
13478 { "fucomip", { ST, STi }, 0 },
13479 { "fcomip", { ST, STi }, 0 },
13484 static char *fgrps[][8] = {
13487 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13492 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13497 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13502 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13507 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13512 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13517 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13518 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13523 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13528 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13533 swap_operand (void)
13535 mnemonicendp[0] = '.';
13536 mnemonicendp[1] = 's';
13541 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13542 int sizeflag ATTRIBUTE_UNUSED)
13544 /* Skip mod/rm byte. */
13550 dofloat (int sizeflag)
13552 const struct dis386 *dp;
13553 unsigned char floatop;
13555 floatop = codep[-1];
13557 if (modrm.mod != 3)
13559 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13561 putop (float_mem[fp_indx], sizeflag);
13564 OP_E (float_mem_mode[fp_indx], sizeflag);
13567 /* Skip mod/rm byte. */
13571 dp = &float_reg[floatop - 0xd8][modrm.reg];
13572 if (dp->name == NULL)
13574 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13576 /* Instruction fnstsw is only one with strange arg. */
13577 if (floatop == 0xdf && codep[-1] == 0xe0)
13578 strcpy (op_out[0], names16[0]);
13582 putop (dp->name, sizeflag);
13587 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13592 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13596 /* Like oappend (below), but S is a string starting with '%'.
13597 In Intel syntax, the '%' is elided. */
13599 oappend_maybe_intel (const char *s)
13601 oappend (s + intel_syntax);
13605 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13607 oappend_maybe_intel ("%st");
13611 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13613 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13614 oappend_maybe_intel (scratchbuf);
13617 /* Capital letters in template are macros. */
13619 putop (const char *in_template, int sizeflag)
13624 unsigned int l = 0, len = 1;
13627 #define SAVE_LAST(c) \
13628 if (l < len && l < sizeof (last)) \
13633 for (p = in_template; *p; p++)
13650 while (*++p != '|')
13651 if (*p == '}' || *p == '\0')
13654 /* Fall through. */
13659 while (*++p != '}')
13670 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13674 if (l == 0 && len == 1)
13679 if (sizeflag & SUFFIX_ALWAYS)
13692 if (address_mode == mode_64bit
13693 && !(prefixes & PREFIX_ADDR))
13704 if (intel_syntax && !alt)
13706 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13708 if (sizeflag & DFLAG)
13709 *obufp++ = intel_syntax ? 'd' : 'l';
13711 *obufp++ = intel_syntax ? 'w' : 's';
13712 used_prefixes |= (prefixes & PREFIX_DATA);
13716 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13719 if (modrm.mod == 3)
13725 if (sizeflag & DFLAG)
13726 *obufp++ = intel_syntax ? 'd' : 'l';
13729 used_prefixes |= (prefixes & PREFIX_DATA);
13735 case 'E': /* For jcxz/jecxz */
13736 if (address_mode == mode_64bit)
13738 if (sizeflag & AFLAG)
13744 if (sizeflag & AFLAG)
13746 used_prefixes |= (prefixes & PREFIX_ADDR);
13751 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13753 if (sizeflag & AFLAG)
13754 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13756 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13757 used_prefixes |= (prefixes & PREFIX_ADDR);
13761 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13763 if ((rex & REX_W) || (sizeflag & DFLAG))
13767 if (!(rex & REX_W))
13768 used_prefixes |= (prefixes & PREFIX_DATA);
13773 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13774 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13776 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13779 if (prefixes & PREFIX_DS)
13800 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13805 /* Fall through. */
13808 if (l != 0 || len != 1)
13816 if (sizeflag & SUFFIX_ALWAYS)
13820 if (intel_mnemonic != cond)
13824 if ((prefixes & PREFIX_FWAIT) == 0)
13827 used_prefixes |= PREFIX_FWAIT;
13833 else if (intel_syntax && (sizeflag & DFLAG))
13837 if (!(rex & REX_W))
13838 used_prefixes |= (prefixes & PREFIX_DATA);
13842 && address_mode == mode_64bit
13843 && ((sizeflag & DFLAG) || (rex & REX_W)))
13848 /* Fall through. */
13851 if (l == 0 && len == 1)
13856 if ((rex & REX_W) == 0
13857 && (prefixes & PREFIX_DATA))
13859 if ((sizeflag & DFLAG) == 0)
13861 used_prefixes |= (prefixes & PREFIX_DATA);
13865 if ((prefixes & PREFIX_DATA)
13867 || (sizeflag & SUFFIX_ALWAYS))
13874 if (sizeflag & DFLAG)
13878 used_prefixes |= (prefixes & PREFIX_DATA);
13884 if (l != 1 || len != 2 || last[0] != 'L')
13890 if ((prefixes & PREFIX_DATA)
13892 || (sizeflag & SUFFIX_ALWAYS))
13899 if (sizeflag & DFLAG)
13900 *obufp++ = intel_syntax ? 'd' : 'l';
13903 used_prefixes |= (prefixes & PREFIX_DATA);
13911 if (address_mode == mode_64bit
13912 && ((sizeflag & DFLAG) || (rex & REX_W)))
13914 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13918 /* Fall through. */
13921 if (l == 0 && len == 1)
13924 if (intel_syntax && !alt)
13927 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13933 if (sizeflag & DFLAG)
13934 *obufp++ = intel_syntax ? 'd' : 'l';
13937 used_prefixes |= (prefixes & PREFIX_DATA);
13943 if (l != 1 || len != 2 || last[0] != 'L')
13949 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13964 else if (sizeflag & DFLAG)
13973 if (intel_syntax && !p[1]
13974 && ((rex & REX_W) || (sizeflag & DFLAG)))
13976 if (!(rex & REX_W))
13977 used_prefixes |= (prefixes & PREFIX_DATA);
13980 if (l == 0 && len == 1)
13984 if (address_mode == mode_64bit
13985 && ((sizeflag & DFLAG) || (rex & REX_W)))
13987 if (sizeflag & SUFFIX_ALWAYS)
14009 /* Fall through. */
14012 if (l == 0 && len == 1)
14017 if (sizeflag & SUFFIX_ALWAYS)
14023 if (sizeflag & DFLAG)
14027 used_prefixes |= (prefixes & PREFIX_DATA);
14041 if (address_mode == mode_64bit
14042 && !(prefixes & PREFIX_ADDR))
14053 if (l != 0 || len != 1)
14058 if (need_vex && vex.prefix)
14060 if (vex.prefix == DATA_PREFIX_OPCODE)
14067 if (prefixes & PREFIX_DATA)
14071 used_prefixes |= (prefixes & PREFIX_DATA);
14075 if (l == 0 && len == 1)
14077 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14088 if (l != 1 || len != 2 || last[0] != 'X')
14096 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14098 switch (vex.length)
14112 if (l == 0 && len == 1)
14114 /* operand size flag for cwtl, cbtw */
14123 else if (sizeflag & DFLAG)
14127 if (!(rex & REX_W))
14128 used_prefixes |= (prefixes & PREFIX_DATA);
14135 && last[0] != 'L'))
14142 if (last[0] == 'X')
14143 *obufp++ = vex.w ? 'd': 's';
14145 *obufp++ = vex.w ? 'q': 'd';
14152 mnemonicendp = obufp;
14157 oappend (const char *s)
14159 obufp = stpcpy (obufp, s);
14165 /* Only print the active segment register. */
14166 if (!active_seg_prefix)
14169 used_prefixes |= active_seg_prefix;
14170 switch (active_seg_prefix)
14173 oappend_maybe_intel ("%cs:");
14176 oappend_maybe_intel ("%ds:");
14179 oappend_maybe_intel ("%ss:");
14182 oappend_maybe_intel ("%es:");
14185 oappend_maybe_intel ("%fs:");
14188 oappend_maybe_intel ("%gs:");
14196 OP_indirE (int bytemode, int sizeflag)
14200 OP_E (bytemode, sizeflag);
14204 print_operand_value (char *buf, int hex, bfd_vma disp)
14206 if (address_mode == mode_64bit)
14214 sprintf_vma (tmp, disp);
14215 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14216 strcpy (buf + 2, tmp + i);
14220 bfd_signed_vma v = disp;
14227 /* Check for possible overflow on 0x8000000000000000. */
14230 strcpy (buf, "9223372036854775808");
14244 tmp[28 - i] = (v % 10) + '0';
14248 strcpy (buf, tmp + 29 - i);
14254 sprintf (buf, "0x%x", (unsigned int) disp);
14256 sprintf (buf, "%d", (int) disp);
14260 /* Put DISP in BUF as signed hex number. */
14263 print_displacement (char *buf, bfd_vma disp)
14265 bfd_signed_vma val = disp;
14274 /* Check for possible overflow. */
14277 switch (address_mode)
14280 strcpy (buf + j, "0x8000000000000000");
14283 strcpy (buf + j, "0x80000000");
14286 strcpy (buf + j, "0x8000");
14296 sprintf_vma (tmp, (bfd_vma) val);
14297 for (i = 0; tmp[i] == '0'; i++)
14299 if (tmp[i] == '\0')
14301 strcpy (buf + j, tmp + i);
14305 intel_operand_size (int bytemode, int sizeflag)
14309 && (bytemode == x_mode
14310 || bytemode == evex_half_bcst_xmmq_mode))
14313 oappend ("QWORD PTR ");
14315 oappend ("DWORD PTR ");
14324 oappend ("BYTE PTR ");
14329 case dqw_swap_mode:
14330 oappend ("WORD PTR ");
14333 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14335 oappend ("QWORD PTR ");
14344 oappend ("QWORD PTR ");
14347 if ((sizeflag & DFLAG) || bytemode == dq_mode)
14348 oappend ("DWORD PTR ");
14350 oappend ("WORD PTR ");
14351 used_prefixes |= (prefixes & PREFIX_DATA);
14355 if ((rex & REX_W) || (sizeflag & DFLAG))
14357 oappend ("WORD PTR ");
14358 if (!(rex & REX_W))
14359 used_prefixes |= (prefixes & PREFIX_DATA);
14362 if (sizeflag & DFLAG)
14363 oappend ("QWORD PTR ");
14365 oappend ("DWORD PTR ");
14366 used_prefixes |= (prefixes & PREFIX_DATA);
14369 case d_scalar_mode:
14370 case d_scalar_swap_mode:
14373 oappend ("DWORD PTR ");
14376 case q_scalar_mode:
14377 case q_scalar_swap_mode:
14379 oappend ("QWORD PTR ");
14382 if (address_mode == mode_64bit)
14383 oappend ("QWORD PTR ");
14385 oappend ("DWORD PTR ");
14388 if (sizeflag & DFLAG)
14389 oappend ("FWORD PTR ");
14391 oappend ("DWORD PTR ");
14392 used_prefixes |= (prefixes & PREFIX_DATA);
14395 oappend ("TBYTE PTR ");
14399 case evex_x_gscat_mode:
14400 case evex_x_nobcst_mode:
14403 switch (vex.length)
14406 oappend ("XMMWORD PTR ");
14409 oappend ("YMMWORD PTR ");
14412 oappend ("ZMMWORD PTR ");
14419 oappend ("XMMWORD PTR ");
14422 oappend ("XMMWORD PTR ");
14425 oappend ("YMMWORD PTR ");
14428 case evex_half_bcst_xmmq_mode:
14432 switch (vex.length)
14435 oappend ("QWORD PTR ");
14438 oappend ("XMMWORD PTR ");
14441 oappend ("YMMWORD PTR ");
14451 switch (vex.length)
14456 oappend ("BYTE PTR ");
14466 switch (vex.length)
14471 oappend ("WORD PTR ");
14481 switch (vex.length)
14486 oappend ("DWORD PTR ");
14496 switch (vex.length)
14501 oappend ("QWORD PTR ");
14511 switch (vex.length)
14514 oappend ("WORD PTR ");
14517 oappend ("DWORD PTR ");
14520 oappend ("QWORD PTR ");
14530 switch (vex.length)
14533 oappend ("DWORD PTR ");
14536 oappend ("QWORD PTR ");
14539 oappend ("XMMWORD PTR ");
14549 switch (vex.length)
14552 oappend ("QWORD PTR ");
14555 oappend ("YMMWORD PTR ");
14558 oappend ("ZMMWORD PTR ");
14568 switch (vex.length)
14572 oappend ("XMMWORD PTR ");
14579 oappend ("OWORD PTR ");
14582 case vex_w_dq_mode:
14583 case vex_scalar_w_dq_mode:
14588 oappend ("QWORD PTR ");
14590 oappend ("DWORD PTR ");
14592 case vex_vsib_d_w_dq_mode:
14593 case vex_vsib_q_w_dq_mode:
14600 oappend ("QWORD PTR ");
14602 oappend ("DWORD PTR ");
14606 switch (vex.length)
14609 oappend ("XMMWORD PTR ");
14612 oappend ("YMMWORD PTR ");
14615 oappend ("ZMMWORD PTR ");
14622 case vex_vsib_q_w_d_mode:
14623 case vex_vsib_d_w_d_mode:
14624 if (!need_vex || !vex.evex)
14627 switch (vex.length)
14630 oappend ("QWORD PTR ");
14633 oappend ("XMMWORD PTR ");
14636 oappend ("YMMWORD PTR ");
14644 if (!need_vex || vex.length != 128)
14647 oappend ("DWORD PTR ");
14649 oappend ("BYTE PTR ");
14655 oappend ("QWORD PTR ");
14657 oappend ("WORD PTR ");
14666 OP_E_register (int bytemode, int sizeflag)
14668 int reg = modrm.rm;
14669 const char **names;
14675 if ((sizeflag & SUFFIX_ALWAYS)
14676 && (bytemode == b_swap_mode
14677 || bytemode == v_swap_mode
14678 || bytemode == dqw_swap_mode))
14704 names = address_mode == mode_64bit ? names64 : names32;
14710 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14723 case dqw_swap_mode:
14729 if ((sizeflag & DFLAG)
14730 || (bytemode != v_mode
14731 && bytemode != v_swap_mode))
14735 used_prefixes |= (prefixes & PREFIX_DATA);
14740 names = names_mask;
14745 oappend (INTERNAL_DISASSEMBLER_ERROR);
14748 oappend (names[reg]);
14752 OP_E_memory (int bytemode, int sizeflag)
14755 int add = (rex & REX_B) ? 8 : 0;
14761 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
14763 && bytemode != x_mode
14764 && bytemode != xmmq_mode
14765 && bytemode != evex_half_bcst_xmmq_mode)
14774 case dqw_swap_mode:
14781 case vex_vsib_d_w_dq_mode:
14782 case vex_vsib_d_w_d_mode:
14783 case vex_vsib_q_w_dq_mode:
14784 case vex_vsib_q_w_d_mode:
14785 case evex_x_gscat_mode:
14787 shift = vex.w ? 3 : 2;
14790 case evex_half_bcst_xmmq_mode:
14794 shift = vex.w ? 3 : 2;
14797 /* Fall through if vex.b == 0. */
14801 case evex_x_nobcst_mode:
14803 switch (vex.length)
14826 case q_scalar_mode:
14828 case q_scalar_swap_mode:
14834 case d_scalar_mode:
14836 case d_scalar_swap_mode:
14848 /* Make necessary corrections to shift for modes that need it.
14849 For these modes we currently have shift 4, 5 or 6 depending on
14850 vex.length (it corresponds to xmmword, ymmword or zmmword
14851 operand). We might want to make it 3, 4 or 5 (e.g. for
14852 xmmq_mode). In case of broadcast enabled the corrections
14853 aren't needed, as element size is always 32 or 64 bits. */
14855 && (bytemode == xmmq_mode
14856 || bytemode == evex_half_bcst_xmmq_mode))
14858 else if (bytemode == xmmqd_mode)
14860 else if (bytemode == xmmdw_mode)
14862 else if (bytemode == ymmq_mode && vex.length == 128)
14870 intel_operand_size (bytemode, sizeflag);
14873 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14875 /* 32/64 bit address mode */
14884 int addr32flag = !((sizeflag & AFLAG)
14885 || bytemode == v_bnd_mode
14886 || bytemode == bnd_mode);
14887 const char **indexes64 = names64;
14888 const char **indexes32 = names32;
14898 vindex = sib.index;
14904 case vex_vsib_d_w_dq_mode:
14905 case vex_vsib_d_w_d_mode:
14906 case vex_vsib_q_w_dq_mode:
14907 case vex_vsib_q_w_d_mode:
14917 switch (vex.length)
14920 indexes64 = indexes32 = names_xmm;
14924 || bytemode == vex_vsib_q_w_dq_mode
14925 || bytemode == vex_vsib_q_w_d_mode)
14926 indexes64 = indexes32 = names_ymm;
14928 indexes64 = indexes32 = names_xmm;
14932 || bytemode == vex_vsib_q_w_dq_mode
14933 || bytemode == vex_vsib_q_w_d_mode)
14934 indexes64 = indexes32 = names_zmm;
14936 indexes64 = indexes32 = names_ymm;
14943 haveindex = vindex != 4;
14950 rbase = base + add;
14958 if (address_mode == mode_64bit && !havesib)
14964 FETCH_DATA (the_info, codep + 1);
14966 if ((disp & 0x80) != 0)
14968 if (vex.evex && shift > 0)
14976 /* In 32bit mode, we need index register to tell [offset] from
14977 [eiz*1 + offset]. */
14978 needindex = (havesib
14981 && address_mode == mode_32bit);
14982 havedisp = (havebase
14984 || (havesib && (haveindex || scale != 0)));
14987 if (modrm.mod != 0 || base == 5)
14989 if (havedisp || riprel)
14990 print_displacement (scratchbuf, disp);
14992 print_operand_value (scratchbuf, 1, disp);
14993 oappend (scratchbuf);
14997 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
15001 if ((havebase || haveindex || riprel)
15002 && (bytemode != v_bnd_mode)
15003 && (bytemode != bnd_mode))
15004 used_prefixes |= PREFIX_ADDR;
15006 if (havedisp || (intel_syntax && riprel))
15008 *obufp++ = open_char;
15009 if (intel_syntax && riprel)
15012 oappend (sizeflag & AFLAG ? "rip" : "eip");
15016 oappend (address_mode == mode_64bit && !addr32flag
15017 ? names64[rbase] : names32[rbase]);
15020 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15021 print index to tell base + index from base. */
15025 || (havebase && base != ESP_REG_NUM))
15027 if (!intel_syntax || havebase)
15029 *obufp++ = separator_char;
15033 oappend (address_mode == mode_64bit && !addr32flag
15034 ? indexes64[vindex] : indexes32[vindex]);
15036 oappend (address_mode == mode_64bit && !addr32flag
15037 ? index64 : index32);
15039 *obufp++ = scale_char;
15041 sprintf (scratchbuf, "%d", 1 << scale);
15042 oappend (scratchbuf);
15046 && (disp || modrm.mod != 0 || base == 5))
15048 if (!havedisp || (bfd_signed_vma) disp >= 0)
15053 else if (modrm.mod != 1 && disp != -disp)
15057 disp = - (bfd_signed_vma) disp;
15061 print_displacement (scratchbuf, disp);
15063 print_operand_value (scratchbuf, 1, disp);
15064 oappend (scratchbuf);
15067 *obufp++ = close_char;
15070 else if (intel_syntax)
15072 if (modrm.mod != 0 || base == 5)
15074 if (!active_seg_prefix)
15076 oappend (names_seg[ds_reg - es_reg]);
15079 print_operand_value (scratchbuf, 1, disp);
15080 oappend (scratchbuf);
15086 /* 16 bit address mode */
15087 used_prefixes |= prefixes & PREFIX_ADDR;
15094 if ((disp & 0x8000) != 0)
15099 FETCH_DATA (the_info, codep + 1);
15101 if ((disp & 0x80) != 0)
15106 if ((disp & 0x8000) != 0)
15112 if (modrm.mod != 0 || modrm.rm == 6)
15114 print_displacement (scratchbuf, disp);
15115 oappend (scratchbuf);
15118 if (modrm.mod != 0 || modrm.rm != 6)
15120 *obufp++ = open_char;
15122 oappend (index16[modrm.rm]);
15124 && (disp || modrm.mod != 0 || modrm.rm == 6))
15126 if ((bfd_signed_vma) disp >= 0)
15131 else if (modrm.mod != 1)
15135 disp = - (bfd_signed_vma) disp;
15138 print_displacement (scratchbuf, disp);
15139 oappend (scratchbuf);
15142 *obufp++ = close_char;
15145 else if (intel_syntax)
15147 if (!active_seg_prefix)
15149 oappend (names_seg[ds_reg - es_reg]);
15152 print_operand_value (scratchbuf, 1, disp & 0xffff);
15153 oappend (scratchbuf);
15156 if (vex.evex && vex.b
15157 && (bytemode == x_mode
15158 || bytemode == xmmq_mode
15159 || bytemode == evex_half_bcst_xmmq_mode))
15162 || bytemode == xmmq_mode
15163 || bytemode == evex_half_bcst_xmmq_mode)
15165 switch (vex.length)
15168 oappend ("{1to2}");
15171 oappend ("{1to4}");
15174 oappend ("{1to8}");
15182 switch (vex.length)
15185 oappend ("{1to4}");
15188 oappend ("{1to8}");
15191 oappend ("{1to16}");
15201 OP_E (int bytemode, int sizeflag)
15203 /* Skip mod/rm byte. */
15207 if (modrm.mod == 3)
15208 OP_E_register (bytemode, sizeflag);
15210 OP_E_memory (bytemode, sizeflag);
15214 OP_G (int bytemode, int sizeflag)
15225 oappend (names8rex[modrm.reg + add]);
15227 oappend (names8[modrm.reg + add]);
15230 oappend (names16[modrm.reg + add]);
15235 oappend (names32[modrm.reg + add]);
15238 oappend (names64[modrm.reg + add]);
15241 oappend (names_bnd[modrm.reg]);
15248 case dqw_swap_mode:
15251 oappend (names64[modrm.reg + add]);
15254 if ((sizeflag & DFLAG) || bytemode != v_mode)
15255 oappend (names32[modrm.reg + add]);
15257 oappend (names16[modrm.reg + add]);
15258 used_prefixes |= (prefixes & PREFIX_DATA);
15262 if (address_mode == mode_64bit)
15263 oappend (names64[modrm.reg + add]);
15265 oappend (names32[modrm.reg + add]);
15269 oappend (names_mask[modrm.reg + add]);
15272 oappend (INTERNAL_DISASSEMBLER_ERROR);
15285 FETCH_DATA (the_info, codep + 8);
15286 a = *codep++ & 0xff;
15287 a |= (*codep++ & 0xff) << 8;
15288 a |= (*codep++ & 0xff) << 16;
15289 a |= (*codep++ & 0xff) << 24;
15290 b = *codep++ & 0xff;
15291 b |= (*codep++ & 0xff) << 8;
15292 b |= (*codep++ & 0xff) << 16;
15293 b |= (*codep++ & 0xff) << 24;
15294 x = a + ((bfd_vma) b << 32);
15302 static bfd_signed_vma
15305 bfd_signed_vma x = 0;
15307 FETCH_DATA (the_info, codep + 4);
15308 x = *codep++ & (bfd_signed_vma) 0xff;
15309 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15310 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15311 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15315 static bfd_signed_vma
15318 bfd_signed_vma x = 0;
15320 FETCH_DATA (the_info, codep + 4);
15321 x = *codep++ & (bfd_signed_vma) 0xff;
15322 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15323 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15324 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15326 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15336 FETCH_DATA (the_info, codep + 2);
15337 x = *codep++ & 0xff;
15338 x |= (*codep++ & 0xff) << 8;
15343 set_op (bfd_vma op, int riprel)
15345 op_index[op_ad] = op_ad;
15346 if (address_mode == mode_64bit)
15348 op_address[op_ad] = op;
15349 op_riprel[op_ad] = riprel;
15353 /* Mask to get a 32-bit address. */
15354 op_address[op_ad] = op & 0xffffffff;
15355 op_riprel[op_ad] = riprel & 0xffffffff;
15360 OP_REG (int code, int sizeflag)
15367 case es_reg: case ss_reg: case cs_reg:
15368 case ds_reg: case fs_reg: case gs_reg:
15369 oappend (names_seg[code - es_reg]);
15381 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15382 case sp_reg: case bp_reg: case si_reg: case di_reg:
15383 s = names16[code - ax_reg + add];
15385 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15386 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15389 s = names8rex[code - al_reg + add];
15391 s = names8[code - al_reg];
15393 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15394 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15395 if (address_mode == mode_64bit
15396 && ((sizeflag & DFLAG) || (rex & REX_W)))
15398 s = names64[code - rAX_reg + add];
15401 code += eAX_reg - rAX_reg;
15402 /* Fall through. */
15403 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15404 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15407 s = names64[code - eAX_reg + add];
15410 if (sizeflag & DFLAG)
15411 s = names32[code - eAX_reg + add];
15413 s = names16[code - eAX_reg + add];
15414 used_prefixes |= (prefixes & PREFIX_DATA);
15418 s = INTERNAL_DISASSEMBLER_ERROR;
15425 OP_IMREG (int code, int sizeflag)
15437 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15438 case sp_reg: case bp_reg: case si_reg: case di_reg:
15439 s = names16[code - ax_reg];
15441 case es_reg: case ss_reg: case cs_reg:
15442 case ds_reg: case fs_reg: case gs_reg:
15443 s = names_seg[code - es_reg];
15445 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15446 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15449 s = names8rex[code - al_reg];
15451 s = names8[code - al_reg];
15453 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15454 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15457 s = names64[code - eAX_reg];
15460 if (sizeflag & DFLAG)
15461 s = names32[code - eAX_reg];
15463 s = names16[code - eAX_reg];
15464 used_prefixes |= (prefixes & PREFIX_DATA);
15467 case z_mode_ax_reg:
15468 if ((rex & REX_W) || (sizeflag & DFLAG))
15472 if (!(rex & REX_W))
15473 used_prefixes |= (prefixes & PREFIX_DATA);
15476 s = INTERNAL_DISASSEMBLER_ERROR;
15483 OP_I (int bytemode, int sizeflag)
15486 bfd_signed_vma mask = -1;
15491 FETCH_DATA (the_info, codep + 1);
15496 if (address_mode == mode_64bit)
15501 /* Fall through. */
15508 if (sizeflag & DFLAG)
15518 used_prefixes |= (prefixes & PREFIX_DATA);
15530 oappend (INTERNAL_DISASSEMBLER_ERROR);
15535 scratchbuf[0] = '$';
15536 print_operand_value (scratchbuf + 1, 1, op);
15537 oappend_maybe_intel (scratchbuf);
15538 scratchbuf[0] = '\0';
15542 OP_I64 (int bytemode, int sizeflag)
15545 bfd_signed_vma mask = -1;
15547 if (address_mode != mode_64bit)
15549 OP_I (bytemode, sizeflag);
15556 FETCH_DATA (the_info, codep + 1);
15566 if (sizeflag & DFLAG)
15576 used_prefixes |= (prefixes & PREFIX_DATA);
15584 oappend (INTERNAL_DISASSEMBLER_ERROR);
15589 scratchbuf[0] = '$';
15590 print_operand_value (scratchbuf + 1, 1, op);
15591 oappend_maybe_intel (scratchbuf);
15592 scratchbuf[0] = '\0';
15596 OP_sI (int bytemode, int sizeflag)
15604 FETCH_DATA (the_info, codep + 1);
15606 if ((op & 0x80) != 0)
15608 if (bytemode == b_T_mode)
15610 if (address_mode != mode_64bit
15611 || !((sizeflag & DFLAG) || (rex & REX_W)))
15613 /* The operand-size prefix is overridden by a REX prefix. */
15614 if ((sizeflag & DFLAG) || (rex & REX_W))
15622 if (!(rex & REX_W))
15624 if (sizeflag & DFLAG)
15632 /* The operand-size prefix is overridden by a REX prefix. */
15633 if ((sizeflag & DFLAG) || (rex & REX_W))
15639 oappend (INTERNAL_DISASSEMBLER_ERROR);
15643 scratchbuf[0] = '$';
15644 print_operand_value (scratchbuf + 1, 1, op);
15645 oappend_maybe_intel (scratchbuf);
15649 OP_J (int bytemode, int sizeflag)
15653 bfd_vma segment = 0;
15658 FETCH_DATA (the_info, codep + 1);
15660 if ((disp & 0x80) != 0)
15665 if ((sizeflag & DFLAG) || (rex & REX_W))
15670 if ((disp & 0x8000) != 0)
15672 /* In 16bit mode, address is wrapped around at 64k within
15673 the same segment. Otherwise, a data16 prefix on a jump
15674 instruction means that the pc is masked to 16 bits after
15675 the displacement is added! */
15677 if ((prefixes & PREFIX_DATA) == 0)
15678 segment = ((start_pc + codep - start_codep)
15679 & ~((bfd_vma) 0xffff));
15681 if (!(rex & REX_W))
15682 used_prefixes |= (prefixes & PREFIX_DATA);
15685 oappend (INTERNAL_DISASSEMBLER_ERROR);
15688 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15690 print_operand_value (scratchbuf, 1, disp);
15691 oappend (scratchbuf);
15695 OP_SEG (int bytemode, int sizeflag)
15697 if (bytemode == w_mode)
15698 oappend (names_seg[modrm.reg]);
15700 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15704 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15708 if (sizeflag & DFLAG)
15718 used_prefixes |= (prefixes & PREFIX_DATA);
15720 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15722 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15723 oappend (scratchbuf);
15727 OP_OFF (int bytemode, int sizeflag)
15731 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15732 intel_operand_size (bytemode, sizeflag);
15735 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15742 if (!active_seg_prefix)
15744 oappend (names_seg[ds_reg - es_reg]);
15748 print_operand_value (scratchbuf, 1, off);
15749 oappend (scratchbuf);
15753 OP_OFF64 (int bytemode, int sizeflag)
15757 if (address_mode != mode_64bit
15758 || (prefixes & PREFIX_ADDR))
15760 OP_OFF (bytemode, sizeflag);
15764 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15765 intel_operand_size (bytemode, sizeflag);
15772 if (!active_seg_prefix)
15774 oappend (names_seg[ds_reg - es_reg]);
15778 print_operand_value (scratchbuf, 1, off);
15779 oappend (scratchbuf);
15783 ptr_reg (int code, int sizeflag)
15787 *obufp++ = open_char;
15788 used_prefixes |= (prefixes & PREFIX_ADDR);
15789 if (address_mode == mode_64bit)
15791 if (!(sizeflag & AFLAG))
15792 s = names32[code - eAX_reg];
15794 s = names64[code - eAX_reg];
15796 else if (sizeflag & AFLAG)
15797 s = names32[code - eAX_reg];
15799 s = names16[code - eAX_reg];
15801 *obufp++ = close_char;
15806 OP_ESreg (int code, int sizeflag)
15812 case 0x6d: /* insw/insl */
15813 intel_operand_size (z_mode, sizeflag);
15815 case 0xa5: /* movsw/movsl/movsq */
15816 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15817 case 0xab: /* stosw/stosl */
15818 case 0xaf: /* scasw/scasl */
15819 intel_operand_size (v_mode, sizeflag);
15822 intel_operand_size (b_mode, sizeflag);
15825 oappend_maybe_intel ("%es:");
15826 ptr_reg (code, sizeflag);
15830 OP_DSreg (int code, int sizeflag)
15836 case 0x6f: /* outsw/outsl */
15837 intel_operand_size (z_mode, sizeflag);
15839 case 0xa5: /* movsw/movsl/movsq */
15840 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15841 case 0xad: /* lodsw/lodsl/lodsq */
15842 intel_operand_size (v_mode, sizeflag);
15845 intel_operand_size (b_mode, sizeflag);
15848 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15849 default segment register DS is printed. */
15850 if (!active_seg_prefix)
15851 active_seg_prefix = PREFIX_DS;
15853 ptr_reg (code, sizeflag);
15857 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15865 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15867 all_prefixes[last_lock_prefix] = 0;
15868 used_prefixes |= PREFIX_LOCK;
15873 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15874 oappend_maybe_intel (scratchbuf);
15878 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15887 sprintf (scratchbuf, "db%d", modrm.reg + add);
15889 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15890 oappend (scratchbuf);
15894 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15896 sprintf (scratchbuf, "%%tr%d", modrm.reg);
15897 oappend_maybe_intel (scratchbuf);
15901 OP_R (int bytemode, int sizeflag)
15903 /* Skip mod/rm byte. */
15906 OP_E_register (bytemode, sizeflag);
15910 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15912 int reg = modrm.reg;
15913 const char **names;
15915 used_prefixes |= (prefixes & PREFIX_DATA);
15916 if (prefixes & PREFIX_DATA)
15925 oappend (names[reg]);
15929 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15931 int reg = modrm.reg;
15932 const char **names;
15944 && bytemode != xmm_mode
15945 && bytemode != xmmq_mode
15946 && bytemode != evex_half_bcst_xmmq_mode
15947 && bytemode != ymm_mode
15948 && bytemode != scalar_mode)
15950 switch (vex.length)
15957 || (bytemode != vex_vsib_q_w_dq_mode
15958 && bytemode != vex_vsib_q_w_d_mode))
15970 else if (bytemode == xmmq_mode
15971 || bytemode == evex_half_bcst_xmmq_mode)
15973 switch (vex.length)
15986 else if (bytemode == ymm_mode)
15990 oappend (names[reg]);
15994 OP_EM (int bytemode, int sizeflag)
15997 const char **names;
15999 if (modrm.mod != 3)
16002 && (bytemode == v_mode || bytemode == v_swap_mode))
16004 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16005 used_prefixes |= (prefixes & PREFIX_DATA);
16007 OP_E (bytemode, sizeflag);
16011 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16014 /* Skip mod/rm byte. */
16017 used_prefixes |= (prefixes & PREFIX_DATA);
16019 if (prefixes & PREFIX_DATA)
16028 oappend (names[reg]);
16031 /* cvt* are the only instructions in sse2 which have
16032 both SSE and MMX operands and also have 0x66 prefix
16033 in their opcode. 0x66 was originally used to differentiate
16034 between SSE and MMX instruction(operands). So we have to handle the
16035 cvt* separately using OP_EMC and OP_MXC */
16037 OP_EMC (int bytemode, int sizeflag)
16039 if (modrm.mod != 3)
16041 if (intel_syntax && bytemode == v_mode)
16043 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16044 used_prefixes |= (prefixes & PREFIX_DATA);
16046 OP_E (bytemode, sizeflag);
16050 /* Skip mod/rm byte. */
16053 used_prefixes |= (prefixes & PREFIX_DATA);
16054 oappend (names_mm[modrm.rm]);
16058 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16060 used_prefixes |= (prefixes & PREFIX_DATA);
16061 oappend (names_mm[modrm.reg]);
16065 OP_EX (int bytemode, int sizeflag)
16068 const char **names;
16070 /* Skip mod/rm byte. */
16074 if (modrm.mod != 3)
16076 OP_E_memory (bytemode, sizeflag);
16091 if ((sizeflag & SUFFIX_ALWAYS)
16092 && (bytemode == x_swap_mode
16093 || bytemode == d_swap_mode
16094 || bytemode == dqw_swap_mode
16095 || bytemode == d_scalar_swap_mode
16096 || bytemode == q_swap_mode
16097 || bytemode == q_scalar_swap_mode))
16101 && bytemode != xmm_mode
16102 && bytemode != xmmdw_mode
16103 && bytemode != xmmqd_mode
16104 && bytemode != xmm_mb_mode
16105 && bytemode != xmm_mw_mode
16106 && bytemode != xmm_md_mode
16107 && bytemode != xmm_mq_mode
16108 && bytemode != xmm_mdq_mode
16109 && bytemode != xmmq_mode
16110 && bytemode != evex_half_bcst_xmmq_mode
16111 && bytemode != ymm_mode
16112 && bytemode != d_scalar_mode
16113 && bytemode != d_scalar_swap_mode
16114 && bytemode != q_scalar_mode
16115 && bytemode != q_scalar_swap_mode
16116 && bytemode != vex_scalar_w_dq_mode)
16118 switch (vex.length)
16133 else if (bytemode == xmmq_mode
16134 || bytemode == evex_half_bcst_xmmq_mode)
16136 switch (vex.length)
16149 else if (bytemode == ymm_mode)
16153 oappend (names[reg]);
16157 OP_MS (int bytemode, int sizeflag)
16159 if (modrm.mod == 3)
16160 OP_EM (bytemode, sizeflag);
16166 OP_XS (int bytemode, int sizeflag)
16168 if (modrm.mod == 3)
16169 OP_EX (bytemode, sizeflag);
16175 OP_M (int bytemode, int sizeflag)
16177 if (modrm.mod == 3)
16178 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16181 OP_E (bytemode, sizeflag);
16185 OP_0f07 (int bytemode, int sizeflag)
16187 if (modrm.mod != 3 || modrm.rm != 0)
16190 OP_E (bytemode, sizeflag);
16193 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16194 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16197 NOP_Fixup1 (int bytemode, int sizeflag)
16199 if ((prefixes & PREFIX_DATA) != 0
16202 && address_mode == mode_64bit))
16203 OP_REG (bytemode, sizeflag);
16205 strcpy (obuf, "nop");
16209 NOP_Fixup2 (int bytemode, int sizeflag)
16211 if ((prefixes & PREFIX_DATA) != 0
16214 && address_mode == mode_64bit))
16215 OP_IMREG (bytemode, sizeflag);
16218 static const char *const Suffix3DNow[] = {
16219 /* 00 */ NULL, NULL, NULL, NULL,
16220 /* 04 */ NULL, NULL, NULL, NULL,
16221 /* 08 */ NULL, NULL, NULL, NULL,
16222 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
16223 /* 10 */ NULL, NULL, NULL, NULL,
16224 /* 14 */ NULL, NULL, NULL, NULL,
16225 /* 18 */ NULL, NULL, NULL, NULL,
16226 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
16227 /* 20 */ NULL, NULL, NULL, NULL,
16228 /* 24 */ NULL, NULL, NULL, NULL,
16229 /* 28 */ NULL, NULL, NULL, NULL,
16230 /* 2C */ NULL, NULL, NULL, NULL,
16231 /* 30 */ NULL, NULL, NULL, NULL,
16232 /* 34 */ NULL, NULL, NULL, NULL,
16233 /* 38 */ NULL, NULL, NULL, NULL,
16234 /* 3C */ NULL, NULL, NULL, NULL,
16235 /* 40 */ NULL, NULL, NULL, NULL,
16236 /* 44 */ NULL, NULL, NULL, NULL,
16237 /* 48 */ NULL, NULL, NULL, NULL,
16238 /* 4C */ NULL, NULL, NULL, NULL,
16239 /* 50 */ NULL, NULL, NULL, NULL,
16240 /* 54 */ NULL, NULL, NULL, NULL,
16241 /* 58 */ NULL, NULL, NULL, NULL,
16242 /* 5C */ NULL, NULL, NULL, NULL,
16243 /* 60 */ NULL, NULL, NULL, NULL,
16244 /* 64 */ NULL, NULL, NULL, NULL,
16245 /* 68 */ NULL, NULL, NULL, NULL,
16246 /* 6C */ NULL, NULL, NULL, NULL,
16247 /* 70 */ NULL, NULL, NULL, NULL,
16248 /* 74 */ NULL, NULL, NULL, NULL,
16249 /* 78 */ NULL, NULL, NULL, NULL,
16250 /* 7C */ NULL, NULL, NULL, NULL,
16251 /* 80 */ NULL, NULL, NULL, NULL,
16252 /* 84 */ NULL, NULL, NULL, NULL,
16253 /* 88 */ NULL, NULL, "pfnacc", NULL,
16254 /* 8C */ NULL, NULL, "pfpnacc", NULL,
16255 /* 90 */ "pfcmpge", NULL, NULL, NULL,
16256 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
16257 /* 98 */ NULL, NULL, "pfsub", NULL,
16258 /* 9C */ NULL, NULL, "pfadd", NULL,
16259 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
16260 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
16261 /* A8 */ NULL, NULL, "pfsubr", NULL,
16262 /* AC */ NULL, NULL, "pfacc", NULL,
16263 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
16264 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
16265 /* B8 */ NULL, NULL, NULL, "pswapd",
16266 /* BC */ NULL, NULL, NULL, "pavgusb",
16267 /* C0 */ NULL, NULL, NULL, NULL,
16268 /* C4 */ NULL, NULL, NULL, NULL,
16269 /* C8 */ NULL, NULL, NULL, NULL,
16270 /* CC */ NULL, NULL, NULL, NULL,
16271 /* D0 */ NULL, NULL, NULL, NULL,
16272 /* D4 */ NULL, NULL, NULL, NULL,
16273 /* D8 */ NULL, NULL, NULL, NULL,
16274 /* DC */ NULL, NULL, NULL, NULL,
16275 /* E0 */ NULL, NULL, NULL, NULL,
16276 /* E4 */ NULL, NULL, NULL, NULL,
16277 /* E8 */ NULL, NULL, NULL, NULL,
16278 /* EC */ NULL, NULL, NULL, NULL,
16279 /* F0 */ NULL, NULL, NULL, NULL,
16280 /* F4 */ NULL, NULL, NULL, NULL,
16281 /* F8 */ NULL, NULL, NULL, NULL,
16282 /* FC */ NULL, NULL, NULL, NULL,
16286 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16288 const char *mnemonic;
16290 FETCH_DATA (the_info, codep + 1);
16291 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16292 place where an 8-bit immediate would normally go. ie. the last
16293 byte of the instruction. */
16294 obufp = mnemonicendp;
16295 mnemonic = Suffix3DNow[*codep++ & 0xff];
16297 oappend (mnemonic);
16300 /* Since a variable sized modrm/sib chunk is between the start
16301 of the opcode (0x0f0f) and the opcode suffix, we need to do
16302 all the modrm processing first, and don't know until now that
16303 we have a bad opcode. This necessitates some cleaning up. */
16304 op_out[0][0] = '\0';
16305 op_out[1][0] = '\0';
16308 mnemonicendp = obufp;
16311 static struct op simd_cmp_op[] =
16313 { STRING_COMMA_LEN ("eq") },
16314 { STRING_COMMA_LEN ("lt") },
16315 { STRING_COMMA_LEN ("le") },
16316 { STRING_COMMA_LEN ("unord") },
16317 { STRING_COMMA_LEN ("neq") },
16318 { STRING_COMMA_LEN ("nlt") },
16319 { STRING_COMMA_LEN ("nle") },
16320 { STRING_COMMA_LEN ("ord") }
16324 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16326 unsigned int cmp_type;
16328 FETCH_DATA (the_info, codep + 1);
16329 cmp_type = *codep++ & 0xff;
16330 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16333 char *p = mnemonicendp - 2;
16337 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16338 mnemonicendp += simd_cmp_op[cmp_type].len;
16342 /* We have a reserved extension byte. Output it directly. */
16343 scratchbuf[0] = '$';
16344 print_operand_value (scratchbuf + 1, 1, cmp_type);
16345 oappend_maybe_intel (scratchbuf);
16346 scratchbuf[0] = '\0';
16351 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16352 int sizeflag ATTRIBUTE_UNUSED)
16354 /* mwait %eax,%ecx */
16357 const char **names = (address_mode == mode_64bit
16358 ? names64 : names32);
16359 strcpy (op_out[0], names[0]);
16360 strcpy (op_out[1], names[1]);
16361 two_source_ops = 1;
16363 /* Skip mod/rm byte. */
16369 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16370 int sizeflag ATTRIBUTE_UNUSED)
16372 /* monitor %eax,%ecx,%edx" */
16375 const char **op1_names;
16376 const char **names = (address_mode == mode_64bit
16377 ? names64 : names32);
16379 if (!(prefixes & PREFIX_ADDR))
16380 op1_names = (address_mode == mode_16bit
16381 ? names16 : names);
16384 /* Remove "addr16/addr32". */
16385 all_prefixes[last_addr_prefix] = 0;
16386 op1_names = (address_mode != mode_32bit
16387 ? names32 : names16);
16388 used_prefixes |= PREFIX_ADDR;
16390 strcpy (op_out[0], op1_names[0]);
16391 strcpy (op_out[1], names[1]);
16392 strcpy (op_out[2], names[2]);
16393 two_source_ops = 1;
16395 /* Skip mod/rm byte. */
16403 /* Throw away prefixes and 1st. opcode byte. */
16404 codep = insn_codep + 1;
16409 REP_Fixup (int bytemode, int sizeflag)
16411 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16413 if (prefixes & PREFIX_REPZ)
16414 all_prefixes[last_repz_prefix] = REP_PREFIX;
16421 OP_IMREG (bytemode, sizeflag);
16424 OP_ESreg (bytemode, sizeflag);
16427 OP_DSreg (bytemode, sizeflag);
16435 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16439 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16441 if (prefixes & PREFIX_REPNZ)
16442 all_prefixes[last_repnz_prefix] = BND_PREFIX;
16445 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16446 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16450 HLE_Fixup1 (int bytemode, int sizeflag)
16453 && (prefixes & PREFIX_LOCK) != 0)
16455 if (prefixes & PREFIX_REPZ)
16456 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16457 if (prefixes & PREFIX_REPNZ)
16458 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16461 OP_E (bytemode, sizeflag);
16464 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16465 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16469 HLE_Fixup2 (int bytemode, int sizeflag)
16471 if (modrm.mod != 3)
16473 if (prefixes & PREFIX_REPZ)
16474 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16475 if (prefixes & PREFIX_REPNZ)
16476 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16479 OP_E (bytemode, sizeflag);
16482 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16483 "xrelease" for memory operand. No check for LOCK prefix. */
16486 HLE_Fixup3 (int bytemode, int sizeflag)
16489 && last_repz_prefix > last_repnz_prefix
16490 && (prefixes & PREFIX_REPZ) != 0)
16491 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16493 OP_E (bytemode, sizeflag);
16497 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16502 /* Change cmpxchg8b to cmpxchg16b. */
16503 char *p = mnemonicendp - 2;
16504 mnemonicendp = stpcpy (p, "16b");
16507 else if ((prefixes & PREFIX_LOCK) != 0)
16509 if (prefixes & PREFIX_REPZ)
16510 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16511 if (prefixes & PREFIX_REPNZ)
16512 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16515 OP_M (bytemode, sizeflag);
16519 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16521 const char **names;
16525 switch (vex.length)
16539 oappend (names[reg]);
16543 CRC32_Fixup (int bytemode, int sizeflag)
16545 /* Add proper suffix to "crc32". */
16546 char *p = mnemonicendp;
16565 if (sizeflag & DFLAG)
16569 used_prefixes |= (prefixes & PREFIX_DATA);
16573 oappend (INTERNAL_DISASSEMBLER_ERROR);
16580 if (modrm.mod == 3)
16584 /* Skip mod/rm byte. */
16589 add = (rex & REX_B) ? 8 : 0;
16590 if (bytemode == b_mode)
16594 oappend (names8rex[modrm.rm + add]);
16596 oappend (names8[modrm.rm + add]);
16602 oappend (names64[modrm.rm + add]);
16603 else if ((prefixes & PREFIX_DATA))
16604 oappend (names16[modrm.rm + add]);
16606 oappend (names32[modrm.rm + add]);
16610 OP_E (bytemode, sizeflag);
16614 FXSAVE_Fixup (int bytemode, int sizeflag)
16616 /* Add proper suffix to "fxsave" and "fxrstor". */
16620 char *p = mnemonicendp;
16626 OP_M (bytemode, sizeflag);
16629 /* Display the destination register operand for instructions with
16633 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16636 const char **names;
16644 reg = vex.register_specifier;
16651 if (bytemode == vex_scalar_mode)
16653 oappend (names_xmm[reg]);
16657 switch (vex.length)
16664 case vex_vsib_q_w_dq_mode:
16665 case vex_vsib_q_w_d_mode:
16676 names = names_mask;
16690 case vex_vsib_q_w_dq_mode:
16691 case vex_vsib_q_w_d_mode:
16692 names = vex.w ? names_ymm : names_xmm;
16696 names = names_mask;
16710 oappend (names[reg]);
16713 /* Get the VEX immediate byte without moving codep. */
16715 static unsigned char
16716 get_vex_imm8 (int sizeflag, int opnum)
16718 int bytes_before_imm = 0;
16720 if (modrm.mod != 3)
16722 /* There are SIB/displacement bytes. */
16723 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16725 /* 32/64 bit address mode */
16726 int base = modrm.rm;
16728 /* Check SIB byte. */
16731 FETCH_DATA (the_info, codep + 1);
16733 /* When decoding the third source, don't increase
16734 bytes_before_imm as this has already been incremented
16735 by one in OP_E_memory while decoding the second
16738 bytes_before_imm++;
16741 /* Don't increase bytes_before_imm when decoding the third source,
16742 it has already been incremented by OP_E_memory while decoding
16743 the second source operand. */
16749 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16750 SIB == 5, there is a 4 byte displacement. */
16752 /* No displacement. */
16755 /* 4 byte displacement. */
16756 bytes_before_imm += 4;
16759 /* 1 byte displacement. */
16760 bytes_before_imm++;
16767 /* 16 bit address mode */
16768 /* Don't increase bytes_before_imm when decoding the third source,
16769 it has already been incremented by OP_E_memory while decoding
16770 the second source operand. */
16776 /* When modrm.rm == 6, there is a 2 byte displacement. */
16778 /* No displacement. */
16781 /* 2 byte displacement. */
16782 bytes_before_imm += 2;
16785 /* 1 byte displacement: when decoding the third source,
16786 don't increase bytes_before_imm as this has already
16787 been incremented by one in OP_E_memory while decoding
16788 the second source operand. */
16790 bytes_before_imm++;
16798 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16799 return codep [bytes_before_imm];
16803 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16805 const char **names;
16807 if (reg == -1 && modrm.mod != 3)
16809 OP_E_memory (bytemode, sizeflag);
16821 else if (reg > 7 && address_mode != mode_64bit)
16825 switch (vex.length)
16836 oappend (names[reg]);
16840 OP_EX_VexImmW (int bytemode, int sizeflag)
16843 static unsigned char vex_imm8;
16845 if (vex_w_done == 0)
16849 /* Skip mod/rm byte. */
16853 vex_imm8 = get_vex_imm8 (sizeflag, 0);
16856 reg = vex_imm8 >> 4;
16858 OP_EX_VexReg (bytemode, sizeflag, reg);
16860 else if (vex_w_done == 1)
16865 reg = vex_imm8 >> 4;
16867 OP_EX_VexReg (bytemode, sizeflag, reg);
16871 /* Output the imm8 directly. */
16872 scratchbuf[0] = '$';
16873 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16874 oappend_maybe_intel (scratchbuf);
16875 scratchbuf[0] = '\0';
16881 OP_Vex_2src (int bytemode, int sizeflag)
16883 if (modrm.mod == 3)
16885 int reg = modrm.rm;
16889 oappend (names_xmm[reg]);
16894 && (bytemode == v_mode || bytemode == v_swap_mode))
16896 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16897 used_prefixes |= (prefixes & PREFIX_DATA);
16899 OP_E (bytemode, sizeflag);
16904 OP_Vex_2src_1 (int bytemode, int sizeflag)
16906 if (modrm.mod == 3)
16908 /* Skip mod/rm byte. */
16914 oappend (names_xmm[vex.register_specifier]);
16916 OP_Vex_2src (bytemode, sizeflag);
16920 OP_Vex_2src_2 (int bytemode, int sizeflag)
16923 OP_Vex_2src (bytemode, sizeflag);
16925 oappend (names_xmm[vex.register_specifier]);
16929 OP_EX_VexW (int bytemode, int sizeflag)
16937 /* Skip mod/rm byte. */
16942 reg = get_vex_imm8 (sizeflag, 0) >> 4;
16947 reg = get_vex_imm8 (sizeflag, 1) >> 4;
16950 OP_EX_VexReg (bytemode, sizeflag, reg);
16954 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16955 int sizeflag ATTRIBUTE_UNUSED)
16957 /* Skip the immediate byte and check for invalid bits. */
16958 FETCH_DATA (the_info, codep + 1);
16959 if (*codep++ & 0xf)
16964 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16967 const char **names;
16969 FETCH_DATA (the_info, codep + 1);
16972 if (bytemode != x_mode)
16979 if (reg > 7 && address_mode != mode_64bit)
16982 switch (vex.length)
16993 oappend (names[reg]);
16997 OP_XMM_VexW (int bytemode, int sizeflag)
16999 /* Turn off the REX.W bit since it is used for swapping operands
17002 OP_XMM (bytemode, sizeflag);
17006 OP_EX_Vex (int bytemode, int sizeflag)
17008 if (modrm.mod != 3)
17010 if (vex.register_specifier != 0)
17014 OP_EX (bytemode, sizeflag);
17018 OP_XMM_Vex (int bytemode, int sizeflag)
17020 if (modrm.mod != 3)
17022 if (vex.register_specifier != 0)
17026 OP_XMM (bytemode, sizeflag);
17030 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17032 switch (vex.length)
17035 mnemonicendp = stpcpy (obuf, "vzeroupper");
17038 mnemonicendp = stpcpy (obuf, "vzeroall");
17045 static struct op vex_cmp_op[] =
17047 { STRING_COMMA_LEN ("eq") },
17048 { STRING_COMMA_LEN ("lt") },
17049 { STRING_COMMA_LEN ("le") },
17050 { STRING_COMMA_LEN ("unord") },
17051 { STRING_COMMA_LEN ("neq") },
17052 { STRING_COMMA_LEN ("nlt") },
17053 { STRING_COMMA_LEN ("nle") },
17054 { STRING_COMMA_LEN ("ord") },
17055 { STRING_COMMA_LEN ("eq_uq") },
17056 { STRING_COMMA_LEN ("nge") },
17057 { STRING_COMMA_LEN ("ngt") },
17058 { STRING_COMMA_LEN ("false") },
17059 { STRING_COMMA_LEN ("neq_oq") },
17060 { STRING_COMMA_LEN ("ge") },
17061 { STRING_COMMA_LEN ("gt") },
17062 { STRING_COMMA_LEN ("true") },
17063 { STRING_COMMA_LEN ("eq_os") },
17064 { STRING_COMMA_LEN ("lt_oq") },
17065 { STRING_COMMA_LEN ("le_oq") },
17066 { STRING_COMMA_LEN ("unord_s") },
17067 { STRING_COMMA_LEN ("neq_us") },
17068 { STRING_COMMA_LEN ("nlt_uq") },
17069 { STRING_COMMA_LEN ("nle_uq") },
17070 { STRING_COMMA_LEN ("ord_s") },
17071 { STRING_COMMA_LEN ("eq_us") },
17072 { STRING_COMMA_LEN ("nge_uq") },
17073 { STRING_COMMA_LEN ("ngt_uq") },
17074 { STRING_COMMA_LEN ("false_os") },
17075 { STRING_COMMA_LEN ("neq_os") },
17076 { STRING_COMMA_LEN ("ge_oq") },
17077 { STRING_COMMA_LEN ("gt_oq") },
17078 { STRING_COMMA_LEN ("true_us") },
17082 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17084 unsigned int cmp_type;
17086 FETCH_DATA (the_info, codep + 1);
17087 cmp_type = *codep++ & 0xff;
17088 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17091 char *p = mnemonicendp - 2;
17095 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17096 mnemonicendp += vex_cmp_op[cmp_type].len;
17100 /* We have a reserved extension byte. Output it directly. */
17101 scratchbuf[0] = '$';
17102 print_operand_value (scratchbuf + 1, 1, cmp_type);
17103 oappend_maybe_intel (scratchbuf);
17104 scratchbuf[0] = '\0';
17109 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17110 int sizeflag ATTRIBUTE_UNUSED)
17112 unsigned int cmp_type;
17117 FETCH_DATA (the_info, codep + 1);
17118 cmp_type = *codep++ & 0xff;
17119 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17120 If it's the case, print suffix, otherwise - print the immediate. */
17121 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17126 char *p = mnemonicendp - 2;
17128 /* vpcmp* can have both one- and two-lettered suffix. */
17142 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17143 mnemonicendp += simd_cmp_op[cmp_type].len;
17147 /* We have a reserved extension byte. Output it directly. */
17148 scratchbuf[0] = '$';
17149 print_operand_value (scratchbuf + 1, 1, cmp_type);
17150 oappend_maybe_intel (scratchbuf);
17151 scratchbuf[0] = '\0';
17155 static const struct op pclmul_op[] =
17157 { STRING_COMMA_LEN ("lql") },
17158 { STRING_COMMA_LEN ("hql") },
17159 { STRING_COMMA_LEN ("lqh") },
17160 { STRING_COMMA_LEN ("hqh") }
17164 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17165 int sizeflag ATTRIBUTE_UNUSED)
17167 unsigned int pclmul_type;
17169 FETCH_DATA (the_info, codep + 1);
17170 pclmul_type = *codep++ & 0xff;
17171 switch (pclmul_type)
17182 if (pclmul_type < ARRAY_SIZE (pclmul_op))
17185 char *p = mnemonicendp - 3;
17190 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17191 mnemonicendp += pclmul_op[pclmul_type].len;
17195 /* We have a reserved extension byte. Output it directly. */
17196 scratchbuf[0] = '$';
17197 print_operand_value (scratchbuf + 1, 1, pclmul_type);
17198 oappend_maybe_intel (scratchbuf);
17199 scratchbuf[0] = '\0';
17204 MOVBE_Fixup (int bytemode, int sizeflag)
17206 /* Add proper suffix to "movbe". */
17207 char *p = mnemonicendp;
17216 if (sizeflag & SUFFIX_ALWAYS)
17222 if (sizeflag & DFLAG)
17226 used_prefixes |= (prefixes & PREFIX_DATA);
17231 oappend (INTERNAL_DISASSEMBLER_ERROR);
17238 OP_M (bytemode, sizeflag);
17242 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17245 const char **names;
17247 /* Skip mod/rm byte. */
17261 oappend (names[reg]);
17265 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17267 const char **names;
17274 oappend (names[vex.register_specifier]);
17278 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17281 || (bytemode != mask_mode && bytemode != mask_bd_mode))
17285 if ((rex & REX_R) != 0 || !vex.r)
17291 oappend (names_mask [modrm.reg]);
17295 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17298 || (bytemode != evex_rounding_mode
17299 && bytemode != evex_sae_mode))
17301 if (modrm.mod == 3 && vex.b)
17304 case evex_rounding_mode:
17305 oappend (names_rounding[vex.ll]);
17307 case evex_sae_mode: