1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2017 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma, disassemble_info *);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma get64 (void);
58 static bfd_signed_vma get32 (void);
59 static bfd_signed_vma get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void OP_Mwaitx (int, int);
106 static void NOP_Fixup1 (int, int);
107 static void NOP_Fixup2 (int, int);
108 static void OP_3DNowSuffix (int, int);
109 static void CMP_Fixup (int, int);
110 static void BadOp (void);
111 static void REP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void NOTRACK_Fixup (int, int);
114 static void HLE_Fixup1 (int, int);
115 static void HLE_Fixup2 (int, int);
116 static void HLE_Fixup3 (int, int);
117 static void CMPXCHG8B_Fixup (int, int);
118 static void XMM_Fixup (int, int);
119 static void CRC32_Fixup (int, int);
120 static void FXSAVE_Fixup (int, int);
121 static void PCMPESTR_Fixup (int, int);
122 static void OP_LWPCB_E (int, int);
123 static void OP_LWP_E (int, int);
124 static void OP_Vex_2src_1 (int, int);
125 static void OP_Vex_2src_2 (int, int);
127 static void MOVBE_Fixup (int, int);
129 static void OP_Mask (int, int);
132 /* Points to first byte not fetched. */
133 bfd_byte *max_fetched;
134 bfd_byte the_buffer[MAX_MNEM_SIZE];
137 OPCODES_SIGJMP_BUF bailout;
147 enum address_mode address_mode;
149 /* Flags for the prefixes for the current instruction. See below. */
152 /* REX prefix the current instruction. See below. */
154 /* Bits of REX we've already used. */
156 /* REX bits in original REX prefix ignored. */
157 static int rex_ignored;
158 /* Mark parts used in the REX prefix. When we are testing for
159 empty prefix (for 8bit register REX extension), just mask it
160 out. Otherwise test for REX bit is excuse for existence of REX
161 only in case value is nonzero. */
162 #define USED_REX(value) \
167 rex_used |= (value) | REX_OPCODE; \
170 rex_used |= REX_OPCODE; \
173 /* Flags for prefixes which we somehow handled when printing the
174 current instruction. */
175 static int used_prefixes;
177 /* Flags stored in PREFIXES. */
178 #define PREFIX_REPZ 1
179 #define PREFIX_REPNZ 2
180 #define PREFIX_LOCK 4
182 #define PREFIX_SS 0x10
183 #define PREFIX_DS 0x20
184 #define PREFIX_ES 0x40
185 #define PREFIX_FS 0x80
186 #define PREFIX_GS 0x100
187 #define PREFIX_DATA 0x200
188 #define PREFIX_ADDR 0x400
189 #define PREFIX_FWAIT 0x800
191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
192 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
194 #define FETCH_DATA(info, addr) \
195 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
196 ? 1 : fetch_data ((info), (addr)))
199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
202 struct dis_private *priv = (struct dis_private *) info->private_data;
203 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
205 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
206 status = (*info->read_memory_func) (start,
208 addr - priv->max_fetched,
214 /* If we did manage to read at least one byte, then
215 print_insn_i386 will do something sensible. Otherwise, print
216 an error. We do that here because this is where we know
218 if (priv->max_fetched == priv->the_buffer)
219 (*info->memory_error_func) (status, start, info);
220 OPCODES_SIGLONGJMP (priv->bailout, 1);
223 priv->max_fetched = addr;
227 /* Possible values for prefix requirement. */
228 #define PREFIX_IGNORED_SHIFT 16
229 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
233 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
235 /* Opcode prefixes. */
236 #define PREFIX_OPCODE (PREFIX_REPZ \
240 /* Prefixes ignored. */
241 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
242 | PREFIX_IGNORED_REPNZ \
243 | PREFIX_IGNORED_DATA)
245 #define XX { NULL, 0 }
246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
248 #define Eb { OP_E, b_mode }
249 #define Ebnd { OP_E, bnd_mode }
250 #define EbS { OP_E, b_swap_mode }
251 #define Ev { OP_E, v_mode }
252 #define Ev_bnd { OP_E, v_bnd_mode }
253 #define EvS { OP_E, v_swap_mode }
254 #define Ed { OP_E, d_mode }
255 #define Edq { OP_E, dq_mode }
256 #define Edqw { OP_E, dqw_mode }
257 #define Edqb { OP_E, dqb_mode }
258 #define Edb { OP_E, db_mode }
259 #define Edw { OP_E, dw_mode }
260 #define Edqd { OP_E, dqd_mode }
261 #define Eq { OP_E, q_mode }
262 #define indirEv { OP_indirE, indir_v_mode }
263 #define indirEp { OP_indirE, f_mode }
264 #define stackEv { OP_E, stack_v_mode }
265 #define Em { OP_E, m_mode }
266 #define Ew { OP_E, w_mode }
267 #define M { OP_M, 0 } /* lea, lgdt, etc. */
268 #define Ma { OP_M, a_mode }
269 #define Mb { OP_M, b_mode }
270 #define Md { OP_M, d_mode }
271 #define Mo { OP_M, o_mode }
272 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
273 #define Mq { OP_M, q_mode }
274 #define Mx { OP_M, x_mode }
275 #define Mxmm { OP_M, xmm_mode }
276 #define Gb { OP_G, b_mode }
277 #define Gbnd { OP_G, bnd_mode }
278 #define Gv { OP_G, v_mode }
279 #define Gd { OP_G, d_mode }
280 #define Gdq { OP_G, dq_mode }
281 #define Gm { OP_G, m_mode }
282 #define Gw { OP_G, w_mode }
283 #define Rd { OP_R, d_mode }
284 #define Rdq { OP_R, dq_mode }
285 #define Rm { OP_R, m_mode }
286 #define Ib { OP_I, b_mode }
287 #define sIb { OP_sI, b_mode } /* sign extened byte */
288 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
289 #define Iv { OP_I, v_mode }
290 #define sIv { OP_sI, v_mode }
291 #define Iq { OP_I, q_mode }
292 #define Iv64 { OP_I64, v_mode }
293 #define Iw { OP_I, w_mode }
294 #define I1 { OP_I, const_1_mode }
295 #define Jb { OP_J, b_mode }
296 #define Jv { OP_J, v_mode }
297 #define Cm { OP_C, m_mode }
298 #define Dm { OP_D, m_mode }
299 #define Td { OP_T, d_mode }
300 #define Skip_MODRM { OP_Skip_MODRM, 0 }
302 #define RMeAX { OP_REG, eAX_reg }
303 #define RMeBX { OP_REG, eBX_reg }
304 #define RMeCX { OP_REG, eCX_reg }
305 #define RMeDX { OP_REG, eDX_reg }
306 #define RMeSP { OP_REG, eSP_reg }
307 #define RMeBP { OP_REG, eBP_reg }
308 #define RMeSI { OP_REG, eSI_reg }
309 #define RMeDI { OP_REG, eDI_reg }
310 #define RMrAX { OP_REG, rAX_reg }
311 #define RMrBX { OP_REG, rBX_reg }
312 #define RMrCX { OP_REG, rCX_reg }
313 #define RMrDX { OP_REG, rDX_reg }
314 #define RMrSP { OP_REG, rSP_reg }
315 #define RMrBP { OP_REG, rBP_reg }
316 #define RMrSI { OP_REG, rSI_reg }
317 #define RMrDI { OP_REG, rDI_reg }
318 #define RMAL { OP_REG, al_reg }
319 #define RMCL { OP_REG, cl_reg }
320 #define RMDL { OP_REG, dl_reg }
321 #define RMBL { OP_REG, bl_reg }
322 #define RMAH { OP_REG, ah_reg }
323 #define RMCH { OP_REG, ch_reg }
324 #define RMDH { OP_REG, dh_reg }
325 #define RMBH { OP_REG, bh_reg }
326 #define RMAX { OP_REG, ax_reg }
327 #define RMDX { OP_REG, dx_reg }
329 #define eAX { OP_IMREG, eAX_reg }
330 #define eBX { OP_IMREG, eBX_reg }
331 #define eCX { OP_IMREG, eCX_reg }
332 #define eDX { OP_IMREG, eDX_reg }
333 #define eSP { OP_IMREG, eSP_reg }
334 #define eBP { OP_IMREG, eBP_reg }
335 #define eSI { OP_IMREG, eSI_reg }
336 #define eDI { OP_IMREG, eDI_reg }
337 #define AL { OP_IMREG, al_reg }
338 #define CL { OP_IMREG, cl_reg }
339 #define DL { OP_IMREG, dl_reg }
340 #define BL { OP_IMREG, bl_reg }
341 #define AH { OP_IMREG, ah_reg }
342 #define CH { OP_IMREG, ch_reg }
343 #define DH { OP_IMREG, dh_reg }
344 #define BH { OP_IMREG, bh_reg }
345 #define AX { OP_IMREG, ax_reg }
346 #define DX { OP_IMREG, dx_reg }
347 #define zAX { OP_IMREG, z_mode_ax_reg }
348 #define indirDX { OP_IMREG, indir_dx_reg }
350 #define Sw { OP_SEG, w_mode }
351 #define Sv { OP_SEG, v_mode }
352 #define Ap { OP_DIR, 0 }
353 #define Ob { OP_OFF64, b_mode }
354 #define Ov { OP_OFF64, v_mode }
355 #define Xb { OP_DSreg, eSI_reg }
356 #define Xv { OP_DSreg, eSI_reg }
357 #define Xz { OP_DSreg, eSI_reg }
358 #define Yb { OP_ESreg, eDI_reg }
359 #define Yv { OP_ESreg, eDI_reg }
360 #define DSBX { OP_DSreg, eBX_reg }
362 #define es { OP_REG, es_reg }
363 #define ss { OP_REG, ss_reg }
364 #define cs { OP_REG, cs_reg }
365 #define ds { OP_REG, ds_reg }
366 #define fs { OP_REG, fs_reg }
367 #define gs { OP_REG, gs_reg }
369 #define MX { OP_MMX, 0 }
370 #define XM { OP_XMM, 0 }
371 #define XMScalar { OP_XMM, scalar_mode }
372 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
373 #define XMM { OP_XMM, xmm_mode }
374 #define XMxmmq { OP_XMM, xmmq_mode }
375 #define EM { OP_EM, v_mode }
376 #define EMS { OP_EM, v_swap_mode }
377 #define EMd { OP_EM, d_mode }
378 #define EMx { OP_EM, x_mode }
379 #define EXw { OP_EX, w_mode }
380 #define EXd { OP_EX, d_mode }
381 #define EXdScalar { OP_EX, d_scalar_mode }
382 #define EXdS { OP_EX, d_swap_mode }
383 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
384 #define EXq { OP_EX, q_mode }
385 #define EXqScalar { OP_EX, q_scalar_mode }
386 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
387 #define EXqS { OP_EX, q_swap_mode }
388 #define EXx { OP_EX, x_mode }
389 #define EXxS { OP_EX, x_swap_mode }
390 #define EXxmm { OP_EX, xmm_mode }
391 #define EXymm { OP_EX, ymm_mode }
392 #define EXxmmq { OP_EX, xmmq_mode }
393 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
394 #define EXxmm_mb { OP_EX, xmm_mb_mode }
395 #define EXxmm_mw { OP_EX, xmm_mw_mode }
396 #define EXxmm_md { OP_EX, xmm_md_mode }
397 #define EXxmm_mq { OP_EX, xmm_mq_mode }
398 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
399 #define EXxmmdw { OP_EX, xmmdw_mode }
400 #define EXxmmqd { OP_EX, xmmqd_mode }
401 #define EXymmq { OP_EX, ymmq_mode }
402 #define EXVexWdq { OP_EX, vex_w_dq_mode }
403 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
404 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
405 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
406 #define MS { OP_MS, v_mode }
407 #define XS { OP_XS, v_mode }
408 #define EMCq { OP_EMC, q_mode }
409 #define MXC { OP_MXC, 0 }
410 #define OPSUF { OP_3DNowSuffix, 0 }
411 #define CMP { CMP_Fixup, 0 }
412 #define XMM0 { XMM_Fixup, 0 }
413 #define FXSAVE { FXSAVE_Fixup, 0 }
414 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
415 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
417 #define Vex { OP_VEX, vex_mode }
418 #define VexScalar { OP_VEX, vex_scalar_mode }
419 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
420 #define Vex128 { OP_VEX, vex128_mode }
421 #define Vex256 { OP_VEX, vex256_mode }
422 #define VexGdq { OP_VEX, dq_mode }
423 #define VexI4 { VEXI4_Fixup, 0}
424 #define EXdVex { OP_EX_Vex, d_mode }
425 #define EXdVexS { OP_EX_Vex, d_swap_mode }
426 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
427 #define EXqVex { OP_EX_Vex, q_mode }
428 #define EXqVexS { OP_EX_Vex, q_swap_mode }
429 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
430 #define EXVexW { OP_EX_VexW, x_mode }
431 #define EXdVexW { OP_EX_VexW, d_mode }
432 #define EXqVexW { OP_EX_VexW, q_mode }
433 #define EXVexImmW { OP_EX_VexImmW, x_mode }
434 #define XMVex { OP_XMM_Vex, 0 }
435 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
436 #define XMVexW { OP_XMM_VexW, 0 }
437 #define XMVexI4 { OP_REG_VexI4, x_mode }
438 #define PCLMUL { PCLMUL_Fixup, 0 }
439 #define VZERO { VZERO_Fixup, 0 }
440 #define VCMP { VCMP_Fixup, 0 }
441 #define VPCMP { VPCMP_Fixup, 0 }
443 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
444 #define EXxEVexS { OP_Rounding, evex_sae_mode }
446 #define XMask { OP_Mask, mask_mode }
447 #define MaskG { OP_G, mask_mode }
448 #define MaskE { OP_E, mask_mode }
449 #define MaskBDE { OP_E, mask_bd_mode }
450 #define MaskR { OP_R, mask_mode }
451 #define MaskVex { OP_VEX, mask_mode }
453 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
454 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
455 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
456 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
458 /* Used handle "rep" prefix for string instructions. */
459 #define Xbr { REP_Fixup, eSI_reg }
460 #define Xvr { REP_Fixup, eSI_reg }
461 #define Ybr { REP_Fixup, eDI_reg }
462 #define Yvr { REP_Fixup, eDI_reg }
463 #define Yzr { REP_Fixup, eDI_reg }
464 #define indirDXr { REP_Fixup, indir_dx_reg }
465 #define ALr { REP_Fixup, al_reg }
466 #define eAXr { REP_Fixup, eAX_reg }
468 /* Used handle HLE prefix for lockable instructions. */
469 #define Ebh1 { HLE_Fixup1, b_mode }
470 #define Evh1 { HLE_Fixup1, v_mode }
471 #define Ebh2 { HLE_Fixup2, b_mode }
472 #define Evh2 { HLE_Fixup2, v_mode }
473 #define Ebh3 { HLE_Fixup3, b_mode }
474 #define Evh3 { HLE_Fixup3, v_mode }
476 #define BND { BND_Fixup, 0 }
477 #define NOTRACK { NOTRACK_Fixup, 0 }
479 #define cond_jump_flag { NULL, cond_jump_mode }
480 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
482 /* bits in sizeflag */
483 #define SUFFIX_ALWAYS 4
491 /* byte operand with operand swapped */
493 /* byte operand, sign extend like 'T' suffix */
495 /* operand size depends on prefixes */
497 /* operand size depends on prefixes with operand swapped */
501 /* double word operand */
503 /* double word operand with operand swapped */
505 /* quad word operand */
507 /* quad word operand with operand swapped */
509 /* ten-byte operand */
511 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
512 broadcast enabled. */
514 /* Similar to x_mode, but with different EVEX mem shifts. */
516 /* Similar to x_mode, but with disabled broadcast. */
518 /* Similar to x_mode, but with operands swapped and disabled broadcast
521 /* 16-byte XMM operand */
523 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
524 memory operand (depending on vector length). Broadcast isn't
527 /* Same as xmmq_mode, but broadcast is allowed. */
528 evex_half_bcst_xmmq_mode,
529 /* XMM register or byte memory operand */
531 /* XMM register or word memory operand */
533 /* XMM register or double word memory operand */
535 /* XMM register or quad word memory operand */
537 /* XMM register or double/quad word memory operand, depending on
540 /* 16-byte XMM, word, double word or quad word operand. */
542 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
544 /* 32-byte YMM operand */
546 /* quad word, ymmword or zmmword memory operand. */
548 /* 32-byte YMM or 16-byte word operand */
550 /* d_mode in 32bit, q_mode in 64bit mode. */
552 /* pair of v_mode operands */
557 /* operand size depends on REX prefixes. */
559 /* registers like dq_mode, memory like w_mode. */
562 /* 4- or 6-byte pointer operand */
565 /* v_mode for indirect branch opcodes. */
567 /* v_mode for stack-related opcodes. */
569 /* non-quad operand size depends on prefixes */
571 /* 16-byte operand */
573 /* registers like dq_mode, memory like b_mode. */
575 /* registers like d_mode, memory like b_mode. */
577 /* registers like d_mode, memory like w_mode. */
579 /* registers like dq_mode, memory like d_mode. */
581 /* normal vex mode */
583 /* 128bit vex mode */
585 /* 256bit vex mode */
587 /* operand size depends on the VEX.W bit. */
590 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
591 vex_vsib_d_w_dq_mode,
592 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
594 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
595 vex_vsib_q_w_dq_mode,
596 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
599 /* scalar, ignore vector length. */
601 /* like d_mode, ignore vector length. */
603 /* like d_swap_mode, ignore vector length. */
605 /* like q_mode, ignore vector length. */
607 /* like q_swap_mode, ignore vector length. */
609 /* like vex_mode, ignore vector length. */
611 /* like vex_w_dq_mode, ignore vector length. */
612 vex_scalar_w_dq_mode,
614 /* Static rounding. */
616 /* Supress all exceptions. */
619 /* Mask register operand. */
621 /* Mask register operand. */
688 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
690 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
691 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
692 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
693 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
694 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
695 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
696 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
697 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
698 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
699 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
700 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
701 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
702 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
703 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
704 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
826 MOD_VEX_0F12_PREFIX_0,
828 MOD_VEX_0F16_PREFIX_0,
831 MOD_VEX_W_0_0F41_P_0_LEN_1,
832 MOD_VEX_W_1_0F41_P_0_LEN_1,
833 MOD_VEX_W_0_0F41_P_2_LEN_1,
834 MOD_VEX_W_1_0F41_P_2_LEN_1,
835 MOD_VEX_W_0_0F42_P_0_LEN_1,
836 MOD_VEX_W_1_0F42_P_0_LEN_1,
837 MOD_VEX_W_0_0F42_P_2_LEN_1,
838 MOD_VEX_W_1_0F42_P_2_LEN_1,
839 MOD_VEX_W_0_0F44_P_0_LEN_1,
840 MOD_VEX_W_1_0F44_P_0_LEN_1,
841 MOD_VEX_W_0_0F44_P_2_LEN_1,
842 MOD_VEX_W_1_0F44_P_2_LEN_1,
843 MOD_VEX_W_0_0F45_P_0_LEN_1,
844 MOD_VEX_W_1_0F45_P_0_LEN_1,
845 MOD_VEX_W_0_0F45_P_2_LEN_1,
846 MOD_VEX_W_1_0F45_P_2_LEN_1,
847 MOD_VEX_W_0_0F46_P_0_LEN_1,
848 MOD_VEX_W_1_0F46_P_0_LEN_1,
849 MOD_VEX_W_0_0F46_P_2_LEN_1,
850 MOD_VEX_W_1_0F46_P_2_LEN_1,
851 MOD_VEX_W_0_0F47_P_0_LEN_1,
852 MOD_VEX_W_1_0F47_P_0_LEN_1,
853 MOD_VEX_W_0_0F47_P_2_LEN_1,
854 MOD_VEX_W_1_0F47_P_2_LEN_1,
855 MOD_VEX_W_0_0F4A_P_0_LEN_1,
856 MOD_VEX_W_1_0F4A_P_0_LEN_1,
857 MOD_VEX_W_0_0F4A_P_2_LEN_1,
858 MOD_VEX_W_1_0F4A_P_2_LEN_1,
859 MOD_VEX_W_0_0F4B_P_0_LEN_1,
860 MOD_VEX_W_1_0F4B_P_0_LEN_1,
861 MOD_VEX_W_0_0F4B_P_2_LEN_1,
873 MOD_VEX_W_0_0F91_P_0_LEN_0,
874 MOD_VEX_W_1_0F91_P_0_LEN_0,
875 MOD_VEX_W_0_0F91_P_2_LEN_0,
876 MOD_VEX_W_1_0F91_P_2_LEN_0,
877 MOD_VEX_W_0_0F92_P_0_LEN_0,
878 MOD_VEX_W_0_0F92_P_2_LEN_0,
879 MOD_VEX_W_0_0F92_P_3_LEN_0,
880 MOD_VEX_W_1_0F92_P_3_LEN_0,
881 MOD_VEX_W_0_0F93_P_0_LEN_0,
882 MOD_VEX_W_0_0F93_P_2_LEN_0,
883 MOD_VEX_W_0_0F93_P_3_LEN_0,
884 MOD_VEX_W_1_0F93_P_3_LEN_0,
885 MOD_VEX_W_0_0F98_P_0_LEN_0,
886 MOD_VEX_W_1_0F98_P_0_LEN_0,
887 MOD_VEX_W_0_0F98_P_2_LEN_0,
888 MOD_VEX_W_1_0F98_P_2_LEN_0,
889 MOD_VEX_W_0_0F99_P_0_LEN_0,
890 MOD_VEX_W_1_0F99_P_0_LEN_0,
891 MOD_VEX_W_0_0F99_P_2_LEN_0,
892 MOD_VEX_W_1_0F99_P_2_LEN_0,
895 MOD_VEX_0FD7_PREFIX_2,
896 MOD_VEX_0FE7_PREFIX_2,
897 MOD_VEX_0FF0_PREFIX_3,
898 MOD_VEX_0F381A_PREFIX_2,
899 MOD_VEX_0F382A_PREFIX_2,
900 MOD_VEX_0F382C_PREFIX_2,
901 MOD_VEX_0F382D_PREFIX_2,
902 MOD_VEX_0F382E_PREFIX_2,
903 MOD_VEX_0F382F_PREFIX_2,
904 MOD_VEX_0F385A_PREFIX_2,
905 MOD_VEX_0F388C_PREFIX_2,
906 MOD_VEX_0F388E_PREFIX_2,
907 MOD_VEX_W_0_0F3A30_P_2_LEN_0,
908 MOD_VEX_W_1_0F3A30_P_2_LEN_0,
909 MOD_VEX_W_0_0F3A31_P_2_LEN_0,
910 MOD_VEX_W_1_0F3A31_P_2_LEN_0,
911 MOD_VEX_W_0_0F3A32_P_2_LEN_0,
912 MOD_VEX_W_1_0F3A32_P_2_LEN_0,
913 MOD_VEX_W_0_0F3A33_P_2_LEN_0,
914 MOD_VEX_W_1_0F3A33_P_2_LEN_0,
916 MOD_EVEX_0F10_PREFIX_1,
917 MOD_EVEX_0F10_PREFIX_3,
918 MOD_EVEX_0F11_PREFIX_1,
919 MOD_EVEX_0F11_PREFIX_3,
920 MOD_EVEX_0F12_PREFIX_0,
921 MOD_EVEX_0F16_PREFIX_0,
922 MOD_EVEX_0F38C6_REG_1,
923 MOD_EVEX_0F38C6_REG_2,
924 MOD_EVEX_0F38C6_REG_5,
925 MOD_EVEX_0F38C6_REG_6,
926 MOD_EVEX_0F38C7_REG_1,
927 MOD_EVEX_0F38C7_REG_2,
928 MOD_EVEX_0F38C7_REG_5,
929 MOD_EVEX_0F38C7_REG_6
950 PREFIX_MOD_0_0F01_REG_5,
951 PREFIX_MOD_3_0F01_REG_5_RM_0,
952 PREFIX_MOD_3_0F01_REG_5_RM_2,
996 PREFIX_MOD_0_0FAE_REG_4,
997 PREFIX_MOD_3_0FAE_REG_4,
998 PREFIX_MOD_0_0FAE_REG_5,
999 PREFIX_MOD_3_0FAE_REG_5,
1007 PREFIX_MOD_0_0FC7_REG_6,
1008 PREFIX_MOD_3_0FC7_REG_6,
1009 PREFIX_MOD_3_0FC7_REG_7,
1134 PREFIX_VEX_0F71_REG_2,
1135 PREFIX_VEX_0F71_REG_4,
1136 PREFIX_VEX_0F71_REG_6,
1137 PREFIX_VEX_0F72_REG_2,
1138 PREFIX_VEX_0F72_REG_4,
1139 PREFIX_VEX_0F72_REG_6,
1140 PREFIX_VEX_0F73_REG_2,
1141 PREFIX_VEX_0F73_REG_3,
1142 PREFIX_VEX_0F73_REG_6,
1143 PREFIX_VEX_0F73_REG_7,
1315 PREFIX_VEX_0F38F3_REG_1,
1316 PREFIX_VEX_0F38F3_REG_2,
1317 PREFIX_VEX_0F38F3_REG_3,
1434 PREFIX_EVEX_0F71_REG_2,
1435 PREFIX_EVEX_0F71_REG_4,
1436 PREFIX_EVEX_0F71_REG_6,
1437 PREFIX_EVEX_0F72_REG_0,
1438 PREFIX_EVEX_0F72_REG_1,
1439 PREFIX_EVEX_0F72_REG_2,
1440 PREFIX_EVEX_0F72_REG_4,
1441 PREFIX_EVEX_0F72_REG_6,
1442 PREFIX_EVEX_0F73_REG_2,
1443 PREFIX_EVEX_0F73_REG_3,
1444 PREFIX_EVEX_0F73_REG_6,
1445 PREFIX_EVEX_0F73_REG_7,
1631 PREFIX_EVEX_0F38C6_REG_1,
1632 PREFIX_EVEX_0F38C6_REG_2,
1633 PREFIX_EVEX_0F38C6_REG_5,
1634 PREFIX_EVEX_0F38C6_REG_6,
1635 PREFIX_EVEX_0F38C7_REG_1,
1636 PREFIX_EVEX_0F38C7_REG_2,
1637 PREFIX_EVEX_0F38C7_REG_5,
1638 PREFIX_EVEX_0F38C7_REG_6,
1728 THREE_BYTE_0F38 = 0,
1755 VEX_LEN_0F10_P_1 = 0,
1759 VEX_LEN_0F12_P_0_M_0,
1760 VEX_LEN_0F12_P_0_M_1,
1763 VEX_LEN_0F16_P_0_M_0,
1764 VEX_LEN_0F16_P_0_M_1,
1828 VEX_LEN_0FAE_R_2_M_0,
1829 VEX_LEN_0FAE_R_3_M_0,
1838 VEX_LEN_0F381A_P_2_M_0,
1841 VEX_LEN_0F385A_P_2_M_0,
1848 VEX_LEN_0F38F3_R_1_P_0,
1849 VEX_LEN_0F38F3_R_2_P_0,
1850 VEX_LEN_0F38F3_R_3_P_0,
1896 VEX_LEN_0FXOP_08_CC,
1897 VEX_LEN_0FXOP_08_CD,
1898 VEX_LEN_0FXOP_08_CE,
1899 VEX_LEN_0FXOP_08_CF,
1900 VEX_LEN_0FXOP_08_EC,
1901 VEX_LEN_0FXOP_08_ED,
1902 VEX_LEN_0FXOP_08_EE,
1903 VEX_LEN_0FXOP_08_EF,
1904 VEX_LEN_0FXOP_09_80,
1938 VEX_W_0F41_P_0_LEN_1,
1939 VEX_W_0F41_P_2_LEN_1,
1940 VEX_W_0F42_P_0_LEN_1,
1941 VEX_W_0F42_P_2_LEN_1,
1942 VEX_W_0F44_P_0_LEN_0,
1943 VEX_W_0F44_P_2_LEN_0,
1944 VEX_W_0F45_P_0_LEN_1,
1945 VEX_W_0F45_P_2_LEN_1,
1946 VEX_W_0F46_P_0_LEN_1,
1947 VEX_W_0F46_P_2_LEN_1,
1948 VEX_W_0F47_P_0_LEN_1,
1949 VEX_W_0F47_P_2_LEN_1,
1950 VEX_W_0F4A_P_0_LEN_1,
1951 VEX_W_0F4A_P_2_LEN_1,
1952 VEX_W_0F4B_P_0_LEN_1,
1953 VEX_W_0F4B_P_2_LEN_1,
2033 VEX_W_0F90_P_0_LEN_0,
2034 VEX_W_0F90_P_2_LEN_0,
2035 VEX_W_0F91_P_0_LEN_0,
2036 VEX_W_0F91_P_2_LEN_0,
2037 VEX_W_0F92_P_0_LEN_0,
2038 VEX_W_0F92_P_2_LEN_0,
2039 VEX_W_0F92_P_3_LEN_0,
2040 VEX_W_0F93_P_0_LEN_0,
2041 VEX_W_0F93_P_2_LEN_0,
2042 VEX_W_0F93_P_3_LEN_0,
2043 VEX_W_0F98_P_0_LEN_0,
2044 VEX_W_0F98_P_2_LEN_0,
2045 VEX_W_0F99_P_0_LEN_0,
2046 VEX_W_0F99_P_2_LEN_0,
2125 VEX_W_0F381A_P_2_M_0,
2137 VEX_W_0F382A_P_2_M_0,
2139 VEX_W_0F382C_P_2_M_0,
2140 VEX_W_0F382D_P_2_M_0,
2141 VEX_W_0F382E_P_2_M_0,
2142 VEX_W_0F382F_P_2_M_0,
2164 VEX_W_0F385A_P_2_M_0,
2192 VEX_W_0F3A30_P_2_LEN_0,
2193 VEX_W_0F3A31_P_2_LEN_0,
2194 VEX_W_0F3A32_P_2_LEN_0,
2195 VEX_W_0F3A33_P_2_LEN_0,
2213 EVEX_W_0F10_P_1_M_0,
2214 EVEX_W_0F10_P_1_M_1,
2216 EVEX_W_0F10_P_3_M_0,
2217 EVEX_W_0F10_P_3_M_1,
2219 EVEX_W_0F11_P_1_M_0,
2220 EVEX_W_0F11_P_1_M_1,
2222 EVEX_W_0F11_P_3_M_0,
2223 EVEX_W_0F11_P_3_M_1,
2224 EVEX_W_0F12_P_0_M_0,
2225 EVEX_W_0F12_P_0_M_1,
2235 EVEX_W_0F16_P_0_M_0,
2236 EVEX_W_0F16_P_0_M_1,
2307 EVEX_W_0F72_R_2_P_2,
2308 EVEX_W_0F72_R_6_P_2,
2309 EVEX_W_0F73_R_2_P_2,
2310 EVEX_W_0F73_R_6_P_2,
2411 EVEX_W_0F38C7_R_1_P_2,
2412 EVEX_W_0F38C7_R_2_P_2,
2413 EVEX_W_0F38C7_R_5_P_2,
2414 EVEX_W_0F38C7_R_6_P_2,
2449 typedef void (*op_rtn) (int bytemode, int sizeflag);
2458 unsigned int prefix_requirement;
2461 /* Upper case letters in the instruction names here are macros.
2462 'A' => print 'b' if no register operands or suffix_always is true
2463 'B' => print 'b' if suffix_always is true
2464 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2466 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2467 suffix_always is true
2468 'E' => print 'e' if 32-bit form of jcxz
2469 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2470 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2471 'H' => print ",pt" or ",pn" branch hint
2472 'I' => honor following macro letter even in Intel mode (implemented only
2473 for some of the macro letters)
2475 'K' => print 'd' or 'q' if rex prefix is present.
2476 'L' => print 'l' if suffix_always is true
2477 'M' => print 'r' if intel_mnemonic is false.
2478 'N' => print 'n' if instruction has no wait "prefix"
2479 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2480 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2481 or suffix_always is true. print 'q' if rex prefix is present.
2482 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2484 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2485 'S' => print 'w', 'l' or 'q' if suffix_always is true
2486 'T' => print 'q' in 64bit mode if instruction has no operand size
2487 prefix and behave as 'P' otherwise
2488 'U' => print 'q' in 64bit mode if instruction has no operand size
2489 prefix and behave as 'Q' otherwise
2490 'V' => print 'q' in 64bit mode if instruction has no operand size
2491 prefix and behave as 'S' otherwise
2492 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2493 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2494 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2495 suffix_always is true.
2496 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2497 '!' => change condition from true to false or from false to true.
2498 '%' => add 1 upper case letter to the macro.
2499 '^' => print 'w' or 'l' depending on operand size prefix or
2500 suffix_always is true (lcall/ljmp).
2501 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2502 on operand size prefix.
2503 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2504 has no operand size prefix for AMD64 ISA, behave as 'P'
2507 2 upper case letter macros:
2508 "XY" => print 'x' or 'y' if suffix_always is true or no register
2509 operands and no broadcast.
2510 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2511 register operands and no broadcast.
2512 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2513 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2514 or suffix_always is true
2515 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2516 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2517 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2518 "LW" => print 'd', 'q' depending on the VEX.W bit
2519 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2520 an operand size prefix, or suffix_always is true. print
2521 'q' if rex prefix is present.
2523 Many of the above letters print nothing in Intel mode. See "putop"
2526 Braces '{' and '}', and vertical bars '|', indicate alternative
2527 mnemonic strings for AT&T and Intel. */
2529 static const struct dis386 dis386[] = {
2531 { "addB", { Ebh1, Gb }, 0 },
2532 { "addS", { Evh1, Gv }, 0 },
2533 { "addB", { Gb, EbS }, 0 },
2534 { "addS", { Gv, EvS }, 0 },
2535 { "addB", { AL, Ib }, 0 },
2536 { "addS", { eAX, Iv }, 0 },
2537 { X86_64_TABLE (X86_64_06) },
2538 { X86_64_TABLE (X86_64_07) },
2540 { "orB", { Ebh1, Gb }, 0 },
2541 { "orS", { Evh1, Gv }, 0 },
2542 { "orB", { Gb, EbS }, 0 },
2543 { "orS", { Gv, EvS }, 0 },
2544 { "orB", { AL, Ib }, 0 },
2545 { "orS", { eAX, Iv }, 0 },
2546 { X86_64_TABLE (X86_64_0D) },
2547 { Bad_Opcode }, /* 0x0f extended opcode escape */
2549 { "adcB", { Ebh1, Gb }, 0 },
2550 { "adcS", { Evh1, Gv }, 0 },
2551 { "adcB", { Gb, EbS }, 0 },
2552 { "adcS", { Gv, EvS }, 0 },
2553 { "adcB", { AL, Ib }, 0 },
2554 { "adcS", { eAX, Iv }, 0 },
2555 { X86_64_TABLE (X86_64_16) },
2556 { X86_64_TABLE (X86_64_17) },
2558 { "sbbB", { Ebh1, Gb }, 0 },
2559 { "sbbS", { Evh1, Gv }, 0 },
2560 { "sbbB", { Gb, EbS }, 0 },
2561 { "sbbS", { Gv, EvS }, 0 },
2562 { "sbbB", { AL, Ib }, 0 },
2563 { "sbbS", { eAX, Iv }, 0 },
2564 { X86_64_TABLE (X86_64_1E) },
2565 { X86_64_TABLE (X86_64_1F) },
2567 { "andB", { Ebh1, Gb }, 0 },
2568 { "andS", { Evh1, Gv }, 0 },
2569 { "andB", { Gb, EbS }, 0 },
2570 { "andS", { Gv, EvS }, 0 },
2571 { "andB", { AL, Ib }, 0 },
2572 { "andS", { eAX, Iv }, 0 },
2573 { Bad_Opcode }, /* SEG ES prefix */
2574 { X86_64_TABLE (X86_64_27) },
2576 { "subB", { Ebh1, Gb }, 0 },
2577 { "subS", { Evh1, Gv }, 0 },
2578 { "subB", { Gb, EbS }, 0 },
2579 { "subS", { Gv, EvS }, 0 },
2580 { "subB", { AL, Ib }, 0 },
2581 { "subS", { eAX, Iv }, 0 },
2582 { Bad_Opcode }, /* SEG CS prefix */
2583 { X86_64_TABLE (X86_64_2F) },
2585 { "xorB", { Ebh1, Gb }, 0 },
2586 { "xorS", { Evh1, Gv }, 0 },
2587 { "xorB", { Gb, EbS }, 0 },
2588 { "xorS", { Gv, EvS }, 0 },
2589 { "xorB", { AL, Ib }, 0 },
2590 { "xorS", { eAX, Iv }, 0 },
2591 { Bad_Opcode }, /* SEG SS prefix */
2592 { X86_64_TABLE (X86_64_37) },
2594 { "cmpB", { Eb, Gb }, 0 },
2595 { "cmpS", { Ev, Gv }, 0 },
2596 { "cmpB", { Gb, EbS }, 0 },
2597 { "cmpS", { Gv, EvS }, 0 },
2598 { "cmpB", { AL, Ib }, 0 },
2599 { "cmpS", { eAX, Iv }, 0 },
2600 { Bad_Opcode }, /* SEG DS prefix */
2601 { X86_64_TABLE (X86_64_3F) },
2603 { "inc{S|}", { RMeAX }, 0 },
2604 { "inc{S|}", { RMeCX }, 0 },
2605 { "inc{S|}", { RMeDX }, 0 },
2606 { "inc{S|}", { RMeBX }, 0 },
2607 { "inc{S|}", { RMeSP }, 0 },
2608 { "inc{S|}", { RMeBP }, 0 },
2609 { "inc{S|}", { RMeSI }, 0 },
2610 { "inc{S|}", { RMeDI }, 0 },
2612 { "dec{S|}", { RMeAX }, 0 },
2613 { "dec{S|}", { RMeCX }, 0 },
2614 { "dec{S|}", { RMeDX }, 0 },
2615 { "dec{S|}", { RMeBX }, 0 },
2616 { "dec{S|}", { RMeSP }, 0 },
2617 { "dec{S|}", { RMeBP }, 0 },
2618 { "dec{S|}", { RMeSI }, 0 },
2619 { "dec{S|}", { RMeDI }, 0 },
2621 { "pushV", { RMrAX }, 0 },
2622 { "pushV", { RMrCX }, 0 },
2623 { "pushV", { RMrDX }, 0 },
2624 { "pushV", { RMrBX }, 0 },
2625 { "pushV", { RMrSP }, 0 },
2626 { "pushV", { RMrBP }, 0 },
2627 { "pushV", { RMrSI }, 0 },
2628 { "pushV", { RMrDI }, 0 },
2630 { "popV", { RMrAX }, 0 },
2631 { "popV", { RMrCX }, 0 },
2632 { "popV", { RMrDX }, 0 },
2633 { "popV", { RMrBX }, 0 },
2634 { "popV", { RMrSP }, 0 },
2635 { "popV", { RMrBP }, 0 },
2636 { "popV", { RMrSI }, 0 },
2637 { "popV", { RMrDI }, 0 },
2639 { X86_64_TABLE (X86_64_60) },
2640 { X86_64_TABLE (X86_64_61) },
2641 { X86_64_TABLE (X86_64_62) },
2642 { X86_64_TABLE (X86_64_63) },
2643 { Bad_Opcode }, /* seg fs */
2644 { Bad_Opcode }, /* seg gs */
2645 { Bad_Opcode }, /* op size prefix */
2646 { Bad_Opcode }, /* adr size prefix */
2648 { "pushT", { sIv }, 0 },
2649 { "imulS", { Gv, Ev, Iv }, 0 },
2650 { "pushT", { sIbT }, 0 },
2651 { "imulS", { Gv, Ev, sIb }, 0 },
2652 { "ins{b|}", { Ybr, indirDX }, 0 },
2653 { X86_64_TABLE (X86_64_6D) },
2654 { "outs{b|}", { indirDXr, Xb }, 0 },
2655 { X86_64_TABLE (X86_64_6F) },
2657 { "joH", { Jb, BND, cond_jump_flag }, 0 },
2658 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
2659 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
2660 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
2661 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
2662 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
2663 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
2664 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
2666 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
2667 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
2668 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
2669 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
2670 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
2671 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
2672 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
2673 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
2675 { REG_TABLE (REG_80) },
2676 { REG_TABLE (REG_81) },
2677 { X86_64_TABLE (X86_64_82) },
2678 { REG_TABLE (REG_83) },
2679 { "testB", { Eb, Gb }, 0 },
2680 { "testS", { Ev, Gv }, 0 },
2681 { "xchgB", { Ebh2, Gb }, 0 },
2682 { "xchgS", { Evh2, Gv }, 0 },
2684 { "movB", { Ebh3, Gb }, 0 },
2685 { "movS", { Evh3, Gv }, 0 },
2686 { "movB", { Gb, EbS }, 0 },
2687 { "movS", { Gv, EvS }, 0 },
2688 { "movD", { Sv, Sw }, 0 },
2689 { MOD_TABLE (MOD_8D) },
2690 { "movD", { Sw, Sv }, 0 },
2691 { REG_TABLE (REG_8F) },
2693 { PREFIX_TABLE (PREFIX_90) },
2694 { "xchgS", { RMeCX, eAX }, 0 },
2695 { "xchgS", { RMeDX, eAX }, 0 },
2696 { "xchgS", { RMeBX, eAX }, 0 },
2697 { "xchgS", { RMeSP, eAX }, 0 },
2698 { "xchgS", { RMeBP, eAX }, 0 },
2699 { "xchgS", { RMeSI, eAX }, 0 },
2700 { "xchgS", { RMeDI, eAX }, 0 },
2702 { "cW{t|}R", { XX }, 0 },
2703 { "cR{t|}O", { XX }, 0 },
2704 { X86_64_TABLE (X86_64_9A) },
2705 { Bad_Opcode }, /* fwait */
2706 { "pushfT", { XX }, 0 },
2707 { "popfT", { XX }, 0 },
2708 { "sahf", { XX }, 0 },
2709 { "lahf", { XX }, 0 },
2711 { "mov%LB", { AL, Ob }, 0 },
2712 { "mov%LS", { eAX, Ov }, 0 },
2713 { "mov%LB", { Ob, AL }, 0 },
2714 { "mov%LS", { Ov, eAX }, 0 },
2715 { "movs{b|}", { Ybr, Xb }, 0 },
2716 { "movs{R|}", { Yvr, Xv }, 0 },
2717 { "cmps{b|}", { Xb, Yb }, 0 },
2718 { "cmps{R|}", { Xv, Yv }, 0 },
2720 { "testB", { AL, Ib }, 0 },
2721 { "testS", { eAX, Iv }, 0 },
2722 { "stosB", { Ybr, AL }, 0 },
2723 { "stosS", { Yvr, eAX }, 0 },
2724 { "lodsB", { ALr, Xb }, 0 },
2725 { "lodsS", { eAXr, Xv }, 0 },
2726 { "scasB", { AL, Yb }, 0 },
2727 { "scasS", { eAX, Yv }, 0 },
2729 { "movB", { RMAL, Ib }, 0 },
2730 { "movB", { RMCL, Ib }, 0 },
2731 { "movB", { RMDL, Ib }, 0 },
2732 { "movB", { RMBL, Ib }, 0 },
2733 { "movB", { RMAH, Ib }, 0 },
2734 { "movB", { RMCH, Ib }, 0 },
2735 { "movB", { RMDH, Ib }, 0 },
2736 { "movB", { RMBH, Ib }, 0 },
2738 { "mov%LV", { RMeAX, Iv64 }, 0 },
2739 { "mov%LV", { RMeCX, Iv64 }, 0 },
2740 { "mov%LV", { RMeDX, Iv64 }, 0 },
2741 { "mov%LV", { RMeBX, Iv64 }, 0 },
2742 { "mov%LV", { RMeSP, Iv64 }, 0 },
2743 { "mov%LV", { RMeBP, Iv64 }, 0 },
2744 { "mov%LV", { RMeSI, Iv64 }, 0 },
2745 { "mov%LV", { RMeDI, Iv64 }, 0 },
2747 { REG_TABLE (REG_C0) },
2748 { REG_TABLE (REG_C1) },
2749 { "retT", { Iw, BND }, 0 },
2750 { "retT", { BND }, 0 },
2751 { X86_64_TABLE (X86_64_C4) },
2752 { X86_64_TABLE (X86_64_C5) },
2753 { REG_TABLE (REG_C6) },
2754 { REG_TABLE (REG_C7) },
2756 { "enterT", { Iw, Ib }, 0 },
2757 { "leaveT", { XX }, 0 },
2758 { "Jret{|f}P", { Iw }, 0 },
2759 { "Jret{|f}P", { XX }, 0 },
2760 { "int3", { XX }, 0 },
2761 { "int", { Ib }, 0 },
2762 { X86_64_TABLE (X86_64_CE) },
2763 { "iret%LP", { XX }, 0 },
2765 { REG_TABLE (REG_D0) },
2766 { REG_TABLE (REG_D1) },
2767 { REG_TABLE (REG_D2) },
2768 { REG_TABLE (REG_D3) },
2769 { X86_64_TABLE (X86_64_D4) },
2770 { X86_64_TABLE (X86_64_D5) },
2772 { "xlat", { DSBX }, 0 },
2783 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2784 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2785 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2786 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2787 { "inB", { AL, Ib }, 0 },
2788 { "inG", { zAX, Ib }, 0 },
2789 { "outB", { Ib, AL }, 0 },
2790 { "outG", { Ib, zAX }, 0 },
2792 { X86_64_TABLE (X86_64_E8) },
2793 { X86_64_TABLE (X86_64_E9) },
2794 { X86_64_TABLE (X86_64_EA) },
2795 { "jmp", { Jb, BND }, 0 },
2796 { "inB", { AL, indirDX }, 0 },
2797 { "inG", { zAX, indirDX }, 0 },
2798 { "outB", { indirDX, AL }, 0 },
2799 { "outG", { indirDX, zAX }, 0 },
2801 { Bad_Opcode }, /* lock prefix */
2802 { "icebp", { XX }, 0 },
2803 { Bad_Opcode }, /* repne */
2804 { Bad_Opcode }, /* repz */
2805 { "hlt", { XX }, 0 },
2806 { "cmc", { XX }, 0 },
2807 { REG_TABLE (REG_F6) },
2808 { REG_TABLE (REG_F7) },
2810 { "clc", { XX }, 0 },
2811 { "stc", { XX }, 0 },
2812 { "cli", { XX }, 0 },
2813 { "sti", { XX }, 0 },
2814 { "cld", { XX }, 0 },
2815 { "std", { XX }, 0 },
2816 { REG_TABLE (REG_FE) },
2817 { REG_TABLE (REG_FF) },
2820 static const struct dis386 dis386_twobyte[] = {
2822 { REG_TABLE (REG_0F00 ) },
2823 { REG_TABLE (REG_0F01 ) },
2824 { "larS", { Gv, Ew }, 0 },
2825 { "lslS", { Gv, Ew }, 0 },
2827 { "syscall", { XX }, 0 },
2828 { "clts", { XX }, 0 },
2829 { "sysret%LP", { XX }, 0 },
2831 { "invd", { XX }, 0 },
2832 { "wbinvd", { XX }, 0 },
2834 { "ud2", { XX }, 0 },
2836 { REG_TABLE (REG_0F0D) },
2837 { "femms", { XX }, 0 },
2838 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2840 { PREFIX_TABLE (PREFIX_0F10) },
2841 { PREFIX_TABLE (PREFIX_0F11) },
2842 { PREFIX_TABLE (PREFIX_0F12) },
2843 { MOD_TABLE (MOD_0F13) },
2844 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2845 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2846 { PREFIX_TABLE (PREFIX_0F16) },
2847 { MOD_TABLE (MOD_0F17) },
2849 { REG_TABLE (REG_0F18) },
2850 { "nopQ", { Ev }, 0 },
2851 { PREFIX_TABLE (PREFIX_0F1A) },
2852 { PREFIX_TABLE (PREFIX_0F1B) },
2853 { "nopQ", { Ev }, 0 },
2854 { "nopQ", { Ev }, 0 },
2855 { PREFIX_TABLE (PREFIX_0F1E) },
2856 { "nopQ", { Ev }, 0 },
2858 { "movZ", { Rm, Cm }, 0 },
2859 { "movZ", { Rm, Dm }, 0 },
2860 { "movZ", { Cm, Rm }, 0 },
2861 { "movZ", { Dm, Rm }, 0 },
2862 { MOD_TABLE (MOD_0F24) },
2864 { MOD_TABLE (MOD_0F26) },
2867 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2868 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2869 { PREFIX_TABLE (PREFIX_0F2A) },
2870 { PREFIX_TABLE (PREFIX_0F2B) },
2871 { PREFIX_TABLE (PREFIX_0F2C) },
2872 { PREFIX_TABLE (PREFIX_0F2D) },
2873 { PREFIX_TABLE (PREFIX_0F2E) },
2874 { PREFIX_TABLE (PREFIX_0F2F) },
2876 { "wrmsr", { XX }, 0 },
2877 { "rdtsc", { XX }, 0 },
2878 { "rdmsr", { XX }, 0 },
2879 { "rdpmc", { XX }, 0 },
2880 { "sysenter", { XX }, 0 },
2881 { "sysexit", { XX }, 0 },
2883 { "getsec", { XX }, 0 },
2885 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2887 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2894 { "cmovoS", { Gv, Ev }, 0 },
2895 { "cmovnoS", { Gv, Ev }, 0 },
2896 { "cmovbS", { Gv, Ev }, 0 },
2897 { "cmovaeS", { Gv, Ev }, 0 },
2898 { "cmoveS", { Gv, Ev }, 0 },
2899 { "cmovneS", { Gv, Ev }, 0 },
2900 { "cmovbeS", { Gv, Ev }, 0 },
2901 { "cmovaS", { Gv, Ev }, 0 },
2903 { "cmovsS", { Gv, Ev }, 0 },
2904 { "cmovnsS", { Gv, Ev }, 0 },
2905 { "cmovpS", { Gv, Ev }, 0 },
2906 { "cmovnpS", { Gv, Ev }, 0 },
2907 { "cmovlS", { Gv, Ev }, 0 },
2908 { "cmovgeS", { Gv, Ev }, 0 },
2909 { "cmovleS", { Gv, Ev }, 0 },
2910 { "cmovgS", { Gv, Ev }, 0 },
2912 { MOD_TABLE (MOD_0F51) },
2913 { PREFIX_TABLE (PREFIX_0F51) },
2914 { PREFIX_TABLE (PREFIX_0F52) },
2915 { PREFIX_TABLE (PREFIX_0F53) },
2916 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2917 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2918 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2919 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2921 { PREFIX_TABLE (PREFIX_0F58) },
2922 { PREFIX_TABLE (PREFIX_0F59) },
2923 { PREFIX_TABLE (PREFIX_0F5A) },
2924 { PREFIX_TABLE (PREFIX_0F5B) },
2925 { PREFIX_TABLE (PREFIX_0F5C) },
2926 { PREFIX_TABLE (PREFIX_0F5D) },
2927 { PREFIX_TABLE (PREFIX_0F5E) },
2928 { PREFIX_TABLE (PREFIX_0F5F) },
2930 { PREFIX_TABLE (PREFIX_0F60) },
2931 { PREFIX_TABLE (PREFIX_0F61) },
2932 { PREFIX_TABLE (PREFIX_0F62) },
2933 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2934 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2935 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2936 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2937 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2939 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2940 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2941 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2942 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2943 { PREFIX_TABLE (PREFIX_0F6C) },
2944 { PREFIX_TABLE (PREFIX_0F6D) },
2945 { "movK", { MX, Edq }, PREFIX_OPCODE },
2946 { PREFIX_TABLE (PREFIX_0F6F) },
2948 { PREFIX_TABLE (PREFIX_0F70) },
2949 { REG_TABLE (REG_0F71) },
2950 { REG_TABLE (REG_0F72) },
2951 { REG_TABLE (REG_0F73) },
2952 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2953 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2954 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2955 { "emms", { XX }, PREFIX_OPCODE },
2957 { PREFIX_TABLE (PREFIX_0F78) },
2958 { PREFIX_TABLE (PREFIX_0F79) },
2961 { PREFIX_TABLE (PREFIX_0F7C) },
2962 { PREFIX_TABLE (PREFIX_0F7D) },
2963 { PREFIX_TABLE (PREFIX_0F7E) },
2964 { PREFIX_TABLE (PREFIX_0F7F) },
2966 { "joH", { Jv, BND, cond_jump_flag }, 0 },
2967 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
2968 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
2969 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
2970 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
2971 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
2972 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
2973 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
2975 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
2976 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
2977 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
2978 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
2979 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
2980 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
2981 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
2982 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
2984 { "seto", { Eb }, 0 },
2985 { "setno", { Eb }, 0 },
2986 { "setb", { Eb }, 0 },
2987 { "setae", { Eb }, 0 },
2988 { "sete", { Eb }, 0 },
2989 { "setne", { Eb }, 0 },
2990 { "setbe", { Eb }, 0 },
2991 { "seta", { Eb }, 0 },
2993 { "sets", { Eb }, 0 },
2994 { "setns", { Eb }, 0 },
2995 { "setp", { Eb }, 0 },
2996 { "setnp", { Eb }, 0 },
2997 { "setl", { Eb }, 0 },
2998 { "setge", { Eb }, 0 },
2999 { "setle", { Eb }, 0 },
3000 { "setg", { Eb }, 0 },
3002 { "pushT", { fs }, 0 },
3003 { "popT", { fs }, 0 },
3004 { "cpuid", { XX }, 0 },
3005 { "btS", { Ev, Gv }, 0 },
3006 { "shldS", { Ev, Gv, Ib }, 0 },
3007 { "shldS", { Ev, Gv, CL }, 0 },
3008 { REG_TABLE (REG_0FA6) },
3009 { REG_TABLE (REG_0FA7) },
3011 { "pushT", { gs }, 0 },
3012 { "popT", { gs }, 0 },
3013 { "rsm", { XX }, 0 },
3014 { "btsS", { Evh1, Gv }, 0 },
3015 { "shrdS", { Ev, Gv, Ib }, 0 },
3016 { "shrdS", { Ev, Gv, CL }, 0 },
3017 { REG_TABLE (REG_0FAE) },
3018 { "imulS", { Gv, Ev }, 0 },
3020 { "cmpxchgB", { Ebh1, Gb }, 0 },
3021 { "cmpxchgS", { Evh1, Gv }, 0 },
3022 { MOD_TABLE (MOD_0FB2) },
3023 { "btrS", { Evh1, Gv }, 0 },
3024 { MOD_TABLE (MOD_0FB4) },
3025 { MOD_TABLE (MOD_0FB5) },
3026 { "movz{bR|x}", { Gv, Eb }, 0 },
3027 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3029 { PREFIX_TABLE (PREFIX_0FB8) },
3030 { "ud1", { XX }, 0 },
3031 { REG_TABLE (REG_0FBA) },
3032 { "btcS", { Evh1, Gv }, 0 },
3033 { PREFIX_TABLE (PREFIX_0FBC) },
3034 { PREFIX_TABLE (PREFIX_0FBD) },
3035 { "movs{bR|x}", { Gv, Eb }, 0 },
3036 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3038 { "xaddB", { Ebh1, Gb }, 0 },
3039 { "xaddS", { Evh1, Gv }, 0 },
3040 { PREFIX_TABLE (PREFIX_0FC2) },
3041 { MOD_TABLE (MOD_0FC3) },
3042 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
3043 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
3044 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
3045 { REG_TABLE (REG_0FC7) },
3047 { "bswap", { RMeAX }, 0 },
3048 { "bswap", { RMeCX }, 0 },
3049 { "bswap", { RMeDX }, 0 },
3050 { "bswap", { RMeBX }, 0 },
3051 { "bswap", { RMeSP }, 0 },
3052 { "bswap", { RMeBP }, 0 },
3053 { "bswap", { RMeSI }, 0 },
3054 { "bswap", { RMeDI }, 0 },
3056 { PREFIX_TABLE (PREFIX_0FD0) },
3057 { "psrlw", { MX, EM }, PREFIX_OPCODE },
3058 { "psrld", { MX, EM }, PREFIX_OPCODE },
3059 { "psrlq", { MX, EM }, PREFIX_OPCODE },
3060 { "paddq", { MX, EM }, PREFIX_OPCODE },
3061 { "pmullw", { MX, EM }, PREFIX_OPCODE },
3062 { PREFIX_TABLE (PREFIX_0FD6) },
3063 { MOD_TABLE (MOD_0FD7) },
3065 { "psubusb", { MX, EM }, PREFIX_OPCODE },
3066 { "psubusw", { MX, EM }, PREFIX_OPCODE },
3067 { "pminub", { MX, EM }, PREFIX_OPCODE },
3068 { "pand", { MX, EM }, PREFIX_OPCODE },
3069 { "paddusb", { MX, EM }, PREFIX_OPCODE },
3070 { "paddusw", { MX, EM }, PREFIX_OPCODE },
3071 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
3072 { "pandn", { MX, EM }, PREFIX_OPCODE },
3074 { "pavgb", { MX, EM }, PREFIX_OPCODE },
3075 { "psraw", { MX, EM }, PREFIX_OPCODE },
3076 { "psrad", { MX, EM }, PREFIX_OPCODE },
3077 { "pavgw", { MX, EM }, PREFIX_OPCODE },
3078 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
3079 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
3080 { PREFIX_TABLE (PREFIX_0FE6) },
3081 { PREFIX_TABLE (PREFIX_0FE7) },
3083 { "psubsb", { MX, EM }, PREFIX_OPCODE },
3084 { "psubsw", { MX, EM }, PREFIX_OPCODE },
3085 { "pminsw", { MX, EM }, PREFIX_OPCODE },
3086 { "por", { MX, EM }, PREFIX_OPCODE },
3087 { "paddsb", { MX, EM }, PREFIX_OPCODE },
3088 { "paddsw", { MX, EM }, PREFIX_OPCODE },
3089 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
3090 { "pxor", { MX, EM }, PREFIX_OPCODE },
3092 { PREFIX_TABLE (PREFIX_0FF0) },
3093 { "psllw", { MX, EM }, PREFIX_OPCODE },
3094 { "pslld", { MX, EM }, PREFIX_OPCODE },
3095 { "psllq", { MX, EM }, PREFIX_OPCODE },
3096 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
3097 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
3098 { "psadbw", { MX, EM }, PREFIX_OPCODE },
3099 { PREFIX_TABLE (PREFIX_0FF7) },
3101 { "psubb", { MX, EM }, PREFIX_OPCODE },
3102 { "psubw", { MX, EM }, PREFIX_OPCODE },
3103 { "psubd", { MX, EM }, PREFIX_OPCODE },
3104 { "psubq", { MX, EM }, PREFIX_OPCODE },
3105 { "paddb", { MX, EM }, PREFIX_OPCODE },
3106 { "paddw", { MX, EM }, PREFIX_OPCODE },
3107 { "paddd", { MX, EM }, PREFIX_OPCODE },
3111 static const unsigned char onebyte_has_modrm[256] = {
3112 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3113 /* ------------------------------- */
3114 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3115 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3116 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3117 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3118 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3119 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3120 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3121 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3122 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3123 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3124 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3125 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3126 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3127 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3128 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3129 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3130 /* ------------------------------- */
3131 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3134 static const unsigned char twobyte_has_modrm[256] = {
3135 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3136 /* ------------------------------- */
3137 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3138 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3139 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3140 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3141 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3142 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3143 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3144 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3145 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3146 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3147 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3148 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3149 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3150 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3151 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3152 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3153 /* ------------------------------- */
3154 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3157 static char obuf[100];
3159 static char *mnemonicendp;
3160 static char scratchbuf[100];
3161 static unsigned char *start_codep;
3162 static unsigned char *insn_codep;
3163 static unsigned char *codep;
3164 static unsigned char *end_codep;
3165 static int last_lock_prefix;
3166 static int last_repz_prefix;
3167 static int last_repnz_prefix;
3168 static int last_data_prefix;
3169 static int last_addr_prefix;
3170 static int last_rex_prefix;
3171 static int last_seg_prefix;
3172 static int fwait_prefix;
3173 /* The active segment register prefix. */
3174 static int active_seg_prefix;
3175 #define MAX_CODE_LENGTH 15
3176 /* We can up to 14 prefixes since the maximum instruction length is
3178 static int all_prefixes[MAX_CODE_LENGTH - 1];
3179 static disassemble_info *the_info;
3187 static unsigned char need_modrm;
3197 int register_specifier;
3204 int mask_register_specifier;
3210 static unsigned char need_vex;
3211 static unsigned char need_vex_reg;
3212 static unsigned char vex_w_done;
3220 /* If we are accessing mod/rm/reg without need_modrm set, then the
3221 values are stale. Hitting this abort likely indicates that you
3222 need to update onebyte_has_modrm or twobyte_has_modrm. */
3223 #define MODRM_CHECK if (!need_modrm) abort ()
3225 static const char **names64;
3226 static const char **names32;
3227 static const char **names16;
3228 static const char **names8;
3229 static const char **names8rex;
3230 static const char **names_seg;
3231 static const char *index64;
3232 static const char *index32;
3233 static const char **index16;
3234 static const char **names_bnd;
3236 static const char *intel_names64[] = {
3237 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3238 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3240 static const char *intel_names32[] = {
3241 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3242 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3244 static const char *intel_names16[] = {
3245 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3246 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3248 static const char *intel_names8[] = {
3249 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3251 static const char *intel_names8rex[] = {
3252 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3253 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3255 static const char *intel_names_seg[] = {
3256 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3258 static const char *intel_index64 = "riz";
3259 static const char *intel_index32 = "eiz";
3260 static const char *intel_index16[] = {
3261 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3264 static const char *att_names64[] = {
3265 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3266 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3268 static const char *att_names32[] = {
3269 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3270 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3272 static const char *att_names16[] = {
3273 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3274 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3276 static const char *att_names8[] = {
3277 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3279 static const char *att_names8rex[] = {
3280 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3281 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3283 static const char *att_names_seg[] = {
3284 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3286 static const char *att_index64 = "%riz";
3287 static const char *att_index32 = "%eiz";
3288 static const char *att_index16[] = {
3289 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3292 static const char **names_mm;
3293 static const char *intel_names_mm[] = {
3294 "mm0", "mm1", "mm2", "mm3",
3295 "mm4", "mm5", "mm6", "mm7"
3297 static const char *att_names_mm[] = {
3298 "%mm0", "%mm1", "%mm2", "%mm3",
3299 "%mm4", "%mm5", "%mm6", "%mm7"
3302 static const char *intel_names_bnd[] = {
3303 "bnd0", "bnd1", "bnd2", "bnd3"
3306 static const char *att_names_bnd[] = {
3307 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3310 static const char **names_xmm;
3311 static const char *intel_names_xmm[] = {
3312 "xmm0", "xmm1", "xmm2", "xmm3",
3313 "xmm4", "xmm5", "xmm6", "xmm7",
3314 "xmm8", "xmm9", "xmm10", "xmm11",
3315 "xmm12", "xmm13", "xmm14", "xmm15",
3316 "xmm16", "xmm17", "xmm18", "xmm19",
3317 "xmm20", "xmm21", "xmm22", "xmm23",
3318 "xmm24", "xmm25", "xmm26", "xmm27",
3319 "xmm28", "xmm29", "xmm30", "xmm31"
3321 static const char *att_names_xmm[] = {
3322 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3323 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3324 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3325 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3326 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3327 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3328 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3329 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3332 static const char **names_ymm;
3333 static const char *intel_names_ymm[] = {
3334 "ymm0", "ymm1", "ymm2", "ymm3",
3335 "ymm4", "ymm5", "ymm6", "ymm7",
3336 "ymm8", "ymm9", "ymm10", "ymm11",
3337 "ymm12", "ymm13", "ymm14", "ymm15",
3338 "ymm16", "ymm17", "ymm18", "ymm19",
3339 "ymm20", "ymm21", "ymm22", "ymm23",
3340 "ymm24", "ymm25", "ymm26", "ymm27",
3341 "ymm28", "ymm29", "ymm30", "ymm31"
3343 static const char *att_names_ymm[] = {
3344 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3345 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3346 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3347 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3348 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3349 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3350 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3351 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3354 static const char **names_zmm;
3355 static const char *intel_names_zmm[] = {
3356 "zmm0", "zmm1", "zmm2", "zmm3",
3357 "zmm4", "zmm5", "zmm6", "zmm7",
3358 "zmm8", "zmm9", "zmm10", "zmm11",
3359 "zmm12", "zmm13", "zmm14", "zmm15",
3360 "zmm16", "zmm17", "zmm18", "zmm19",
3361 "zmm20", "zmm21", "zmm22", "zmm23",
3362 "zmm24", "zmm25", "zmm26", "zmm27",
3363 "zmm28", "zmm29", "zmm30", "zmm31"
3365 static const char *att_names_zmm[] = {
3366 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3367 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3368 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3369 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3370 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3371 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3372 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3373 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3376 static const char **names_mask;
3377 static const char *intel_names_mask[] = {
3378 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3380 static const char *att_names_mask[] = {
3381 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3384 static const char *names_rounding[] =
3392 static const struct dis386 reg_table[][8] = {
3395 { "addA", { Ebh1, Ib }, 0 },
3396 { "orA", { Ebh1, Ib }, 0 },
3397 { "adcA", { Ebh1, Ib }, 0 },
3398 { "sbbA", { Ebh1, Ib }, 0 },
3399 { "andA", { Ebh1, Ib }, 0 },
3400 { "subA", { Ebh1, Ib }, 0 },
3401 { "xorA", { Ebh1, Ib }, 0 },
3402 { "cmpA", { Eb, Ib }, 0 },
3406 { "addQ", { Evh1, Iv }, 0 },
3407 { "orQ", { Evh1, Iv }, 0 },
3408 { "adcQ", { Evh1, Iv }, 0 },
3409 { "sbbQ", { Evh1, Iv }, 0 },
3410 { "andQ", { Evh1, Iv }, 0 },
3411 { "subQ", { Evh1, Iv }, 0 },
3412 { "xorQ", { Evh1, Iv }, 0 },
3413 { "cmpQ", { Ev, Iv }, 0 },
3417 { "addQ", { Evh1, sIb }, 0 },
3418 { "orQ", { Evh1, sIb }, 0 },
3419 { "adcQ", { Evh1, sIb }, 0 },
3420 { "sbbQ", { Evh1, sIb }, 0 },
3421 { "andQ", { Evh1, sIb }, 0 },
3422 { "subQ", { Evh1, sIb }, 0 },
3423 { "xorQ", { Evh1, sIb }, 0 },
3424 { "cmpQ", { Ev, sIb }, 0 },
3428 { "popU", { stackEv }, 0 },
3429 { XOP_8F_TABLE (XOP_09) },
3433 { XOP_8F_TABLE (XOP_09) },
3437 { "rolA", { Eb, Ib }, 0 },
3438 { "rorA", { Eb, Ib }, 0 },
3439 { "rclA", { Eb, Ib }, 0 },
3440 { "rcrA", { Eb, Ib }, 0 },
3441 { "shlA", { Eb, Ib }, 0 },
3442 { "shrA", { Eb, Ib }, 0 },
3443 { "shlA", { Eb, Ib }, 0 },
3444 { "sarA", { Eb, Ib }, 0 },
3448 { "rolQ", { Ev, Ib }, 0 },
3449 { "rorQ", { Ev, Ib }, 0 },
3450 { "rclQ", { Ev, Ib }, 0 },
3451 { "rcrQ", { Ev, Ib }, 0 },
3452 { "shlQ", { Ev, Ib }, 0 },
3453 { "shrQ", { Ev, Ib }, 0 },
3454 { "shlQ", { Ev, Ib }, 0 },
3455 { "sarQ", { Ev, Ib }, 0 },
3459 { "movA", { Ebh3, Ib }, 0 },
3466 { MOD_TABLE (MOD_C6_REG_7) },
3470 { "movQ", { Evh3, Iv }, 0 },
3477 { MOD_TABLE (MOD_C7_REG_7) },
3481 { "rolA", { Eb, I1 }, 0 },
3482 { "rorA", { Eb, I1 }, 0 },
3483 { "rclA", { Eb, I1 }, 0 },
3484 { "rcrA", { Eb, I1 }, 0 },
3485 { "shlA", { Eb, I1 }, 0 },
3486 { "shrA", { Eb, I1 }, 0 },
3487 { "shlA", { Eb, I1 }, 0 },
3488 { "sarA", { Eb, I1 }, 0 },
3492 { "rolQ", { Ev, I1 }, 0 },
3493 { "rorQ", { Ev, I1 }, 0 },
3494 { "rclQ", { Ev, I1 }, 0 },
3495 { "rcrQ", { Ev, I1 }, 0 },
3496 { "shlQ", { Ev, I1 }, 0 },
3497 { "shrQ", { Ev, I1 }, 0 },
3498 { "shlQ", { Ev, I1 }, 0 },
3499 { "sarQ", { Ev, I1 }, 0 },
3503 { "rolA", { Eb, CL }, 0 },
3504 { "rorA", { Eb, CL }, 0 },
3505 { "rclA", { Eb, CL }, 0 },
3506 { "rcrA", { Eb, CL }, 0 },
3507 { "shlA", { Eb, CL }, 0 },
3508 { "shrA", { Eb, CL }, 0 },
3509 { "shlA", { Eb, CL }, 0 },
3510 { "sarA", { Eb, CL }, 0 },
3514 { "rolQ", { Ev, CL }, 0 },
3515 { "rorQ", { Ev, CL }, 0 },
3516 { "rclQ", { Ev, CL }, 0 },
3517 { "rcrQ", { Ev, CL }, 0 },
3518 { "shlQ", { Ev, CL }, 0 },
3519 { "shrQ", { Ev, CL }, 0 },
3520 { "shlQ", { Ev, CL }, 0 },
3521 { "sarQ", { Ev, CL }, 0 },
3525 { "testA", { Eb, Ib }, 0 },
3526 { "testA", { Eb, Ib }, 0 },
3527 { "notA", { Ebh1 }, 0 },
3528 { "negA", { Ebh1 }, 0 },
3529 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
3530 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
3531 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
3532 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
3536 { "testQ", { Ev, Iv }, 0 },
3537 { "testQ", { Ev, Iv }, 0 },
3538 { "notQ", { Evh1 }, 0 },
3539 { "negQ", { Evh1 }, 0 },
3540 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
3541 { "imulQ", { Ev }, 0 },
3542 { "divQ", { Ev }, 0 },
3543 { "idivQ", { Ev }, 0 },
3547 { "incA", { Ebh1 }, 0 },
3548 { "decA", { Ebh1 }, 0 },
3552 { "incQ", { Evh1 }, 0 },
3553 { "decQ", { Evh1 }, 0 },
3554 { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3555 { MOD_TABLE (MOD_FF_REG_3) },
3556 { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3557 { MOD_TABLE (MOD_FF_REG_5) },
3558 { "pushU", { stackEv }, 0 },
3563 { "sldtD", { Sv }, 0 },
3564 { "strD", { Sv }, 0 },
3565 { "lldt", { Ew }, 0 },
3566 { "ltr", { Ew }, 0 },
3567 { "verr", { Ew }, 0 },
3568 { "verw", { Ew }, 0 },
3574 { MOD_TABLE (MOD_0F01_REG_0) },
3575 { MOD_TABLE (MOD_0F01_REG_1) },
3576 { MOD_TABLE (MOD_0F01_REG_2) },
3577 { MOD_TABLE (MOD_0F01_REG_3) },
3578 { "smswD", { Sv }, 0 },
3579 { MOD_TABLE (MOD_0F01_REG_5) },
3580 { "lmsw", { Ew }, 0 },
3581 { MOD_TABLE (MOD_0F01_REG_7) },
3585 { "prefetch", { Mb }, 0 },
3586 { "prefetchw", { Mb }, 0 },
3587 { "prefetchwt1", { Mb }, 0 },
3588 { "prefetch", { Mb }, 0 },
3589 { "prefetch", { Mb }, 0 },
3590 { "prefetch", { Mb }, 0 },
3591 { "prefetch", { Mb }, 0 },
3592 { "prefetch", { Mb }, 0 },
3596 { MOD_TABLE (MOD_0F18_REG_0) },
3597 { MOD_TABLE (MOD_0F18_REG_1) },
3598 { MOD_TABLE (MOD_0F18_REG_2) },
3599 { MOD_TABLE (MOD_0F18_REG_3) },
3600 { MOD_TABLE (MOD_0F18_REG_4) },
3601 { MOD_TABLE (MOD_0F18_REG_5) },
3602 { MOD_TABLE (MOD_0F18_REG_6) },
3603 { MOD_TABLE (MOD_0F18_REG_7) },
3605 /* REG_0F1E_MOD_3 */
3607 { "nopQ", { Ev }, 0 },
3608 { "rdsspK", { Rdq }, PREFIX_OPCODE },
3609 { "nopQ", { Ev }, 0 },
3610 { "nopQ", { Ev }, 0 },
3611 { "nopQ", { Ev }, 0 },
3612 { "nopQ", { Ev }, 0 },
3613 { "nopQ", { Ev }, 0 },
3614 { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3620 { MOD_TABLE (MOD_0F71_REG_2) },
3622 { MOD_TABLE (MOD_0F71_REG_4) },
3624 { MOD_TABLE (MOD_0F71_REG_6) },
3630 { MOD_TABLE (MOD_0F72_REG_2) },
3632 { MOD_TABLE (MOD_0F72_REG_4) },
3634 { MOD_TABLE (MOD_0F72_REG_6) },
3640 { MOD_TABLE (MOD_0F73_REG_2) },
3641 { MOD_TABLE (MOD_0F73_REG_3) },
3644 { MOD_TABLE (MOD_0F73_REG_6) },
3645 { MOD_TABLE (MOD_0F73_REG_7) },
3649 { "montmul", { { OP_0f07, 0 } }, 0 },
3650 { "xsha1", { { OP_0f07, 0 } }, 0 },
3651 { "xsha256", { { OP_0f07, 0 } }, 0 },
3655 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
3656 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
3657 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
3658 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
3659 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
3660 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
3664 { MOD_TABLE (MOD_0FAE_REG_0) },
3665 { MOD_TABLE (MOD_0FAE_REG_1) },
3666 { MOD_TABLE (MOD_0FAE_REG_2) },
3667 { MOD_TABLE (MOD_0FAE_REG_3) },
3668 { MOD_TABLE (MOD_0FAE_REG_4) },
3669 { MOD_TABLE (MOD_0FAE_REG_5) },
3670 { MOD_TABLE (MOD_0FAE_REG_6) },
3671 { MOD_TABLE (MOD_0FAE_REG_7) },
3679 { "btQ", { Ev, Ib }, 0 },
3680 { "btsQ", { Evh1, Ib }, 0 },
3681 { "btrQ", { Evh1, Ib }, 0 },
3682 { "btcQ", { Evh1, Ib }, 0 },
3687 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3689 { MOD_TABLE (MOD_0FC7_REG_3) },
3690 { MOD_TABLE (MOD_0FC7_REG_4) },
3691 { MOD_TABLE (MOD_0FC7_REG_5) },
3692 { MOD_TABLE (MOD_0FC7_REG_6) },
3693 { MOD_TABLE (MOD_0FC7_REG_7) },
3699 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3701 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3703 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3709 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3711 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3713 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3719 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3720 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3723 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3724 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3730 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3731 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3733 /* REG_VEX_0F38F3 */
3736 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3737 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3738 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3742 { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3743 { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3747 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3748 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3750 /* REG_XOP_TBM_01 */
3753 { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3754 { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3755 { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 },
3756 { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3757 { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 },
3758 { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 },
3759 { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3761 /* REG_XOP_TBM_02 */
3764 { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3769 { "blci", { { OP_LWP_E, 0 }, Ev }, 0 },
3771 #define NEED_REG_TABLE
3772 #include "i386-dis-evex.h"
3773 #undef NEED_REG_TABLE
3776 static const struct dis386 prefix_table[][4] = {
3779 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3780 { "pause", { XX }, 0 },
3781 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3782 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3785 /* PREFIX_MOD_0_0F01_REG_5 */
3788 { "rstorssp", { Mq }, PREFIX_OPCODE },
3791 /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3794 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3797 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3800 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3805 { "movups", { XM, EXx }, PREFIX_OPCODE },
3806 { "movss", { XM, EXd }, PREFIX_OPCODE },
3807 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3808 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3813 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3814 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3815 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3816 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3821 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3822 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3823 { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3824 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3829 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3830 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3831 { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3836 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3837 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3838 { "bndmov", { Gbnd, Ebnd }, 0 },
3839 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3844 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3845 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3846 { "bndmov", { Ebnd, Gbnd }, 0 },
3847 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3852 { "nopQ", { Ev }, PREFIX_OPCODE },
3853 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3854 { "nopQ", { Ev }, PREFIX_OPCODE },
3855 { "nopQ", { Ev }, PREFIX_OPCODE },
3860 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3861 { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3862 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3863 { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3868 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3869 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3870 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3871 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3876 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3877 { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3878 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3879 { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3884 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3885 { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3886 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3887 { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3892 { "ucomiss",{ XM, EXd }, 0 },
3894 { "ucomisd",{ XM, EXq }, 0 },
3899 { "comiss", { XM, EXd }, 0 },
3901 { "comisd", { XM, EXq }, 0 },
3906 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3907 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3908 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3909 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3914 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3915 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3920 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3921 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3926 { "addps", { XM, EXx }, PREFIX_OPCODE },
3927 { "addss", { XM, EXd }, PREFIX_OPCODE },
3928 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3929 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3934 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3935 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3936 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3937 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3942 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3943 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3944 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3945 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3950 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3951 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3952 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3957 { "subps", { XM, EXx }, PREFIX_OPCODE },
3958 { "subss", { XM, EXd }, PREFIX_OPCODE },
3959 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3960 { "subsd", { XM, EXq }, PREFIX_OPCODE },
3965 { "minps", { XM, EXx }, PREFIX_OPCODE },
3966 { "minss", { XM, EXd }, PREFIX_OPCODE },
3967 { "minpd", { XM, EXx }, PREFIX_OPCODE },
3968 { "minsd", { XM, EXq }, PREFIX_OPCODE },
3973 { "divps", { XM, EXx }, PREFIX_OPCODE },
3974 { "divss", { XM, EXd }, PREFIX_OPCODE },
3975 { "divpd", { XM, EXx }, PREFIX_OPCODE },
3976 { "divsd", { XM, EXq }, PREFIX_OPCODE },
3981 { "maxps", { XM, EXx }, PREFIX_OPCODE },
3982 { "maxss", { XM, EXd }, PREFIX_OPCODE },
3983 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
3984 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
3989 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3991 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3996 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3998 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
4003 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
4005 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
4012 { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
4019 { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
4024 { "movq", { MX, EM }, PREFIX_OPCODE },
4025 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
4026 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4031 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4032 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4033 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4034 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4037 /* PREFIX_0F73_REG_3 */
4041 { "psrldq", { XS, Ib }, 0 },
4044 /* PREFIX_0F73_REG_7 */
4048 { "pslldq", { XS, Ib }, 0 },
4053 {"vmread", { Em, Gm }, 0 },
4055 {"extrq", { XS, Ib, Ib }, 0 },
4056 {"insertq", { XM, XS, Ib, Ib }, 0 },
4061 {"vmwrite", { Gm, Em }, 0 },
4063 {"extrq", { XM, XS }, 0 },
4064 {"insertq", { XM, XS }, 0 },
4071 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4072 { "haddps", { XM, EXx }, PREFIX_OPCODE },
4079 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4080 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4085 { "movK", { Edq, MX }, PREFIX_OPCODE },
4086 { "movq", { XM, EXq }, PREFIX_OPCODE },
4087 { "movK", { Edq, XM }, PREFIX_OPCODE },
4092 { "movq", { EMS, MX }, PREFIX_OPCODE },
4093 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4094 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4097 /* PREFIX_0FAE_REG_0 */
4100 { "rdfsbase", { Ev }, 0 },
4103 /* PREFIX_0FAE_REG_1 */
4106 { "rdgsbase", { Ev }, 0 },
4109 /* PREFIX_0FAE_REG_2 */
4112 { "wrfsbase", { Ev }, 0 },
4115 /* PREFIX_0FAE_REG_3 */
4118 { "wrgsbase", { Ev }, 0 },
4121 /* PREFIX_MOD_0_0FAE_REG_4 */
4123 { "xsave", { FXSAVE }, 0 },
4124 { "ptwrite%LQ", { Edq }, 0 },
4127 /* PREFIX_MOD_3_0FAE_REG_4 */
4130 { "ptwrite%LQ", { Edq }, 0 },
4133 /* PREFIX_MOD_0_0FAE_REG_5 */
4135 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
4138 /* PREFIX_MOD_3_0FAE_REG_5 */
4140 { "lfence", { Skip_MODRM }, 0 },
4141 { "incsspK", { Rdq }, PREFIX_OPCODE },
4144 /* PREFIX_0FAE_REG_6 */
4146 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
4147 { "clrssbsy", { Mq }, PREFIX_OPCODE },
4148 { "clwb", { Mb }, PREFIX_OPCODE },
4151 /* PREFIX_0FAE_REG_7 */
4153 { "clflush", { Mb }, 0 },
4155 { "clflushopt", { Mb }, 0 },
4161 { "popcntS", { Gv, Ev }, 0 },
4166 { "bsfS", { Gv, Ev }, 0 },
4167 { "tzcntS", { Gv, Ev }, 0 },
4168 { "bsfS", { Gv, Ev }, 0 },
4173 { "bsrS", { Gv, Ev }, 0 },
4174 { "lzcntS", { Gv, Ev }, 0 },
4175 { "bsrS", { Gv, Ev }, 0 },
4180 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
4181 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
4182 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
4183 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
4186 /* PREFIX_MOD_0_0FC3 */
4188 { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4191 /* PREFIX_MOD_0_0FC7_REG_6 */
4193 { "vmptrld",{ Mq }, 0 },
4194 { "vmxon", { Mq }, 0 },
4195 { "vmclear",{ Mq }, 0 },
4198 /* PREFIX_MOD_3_0FC7_REG_6 */
4200 { "rdrand", { Ev }, 0 },
4202 { "rdrand", { Ev }, 0 }
4205 /* PREFIX_MOD_3_0FC7_REG_7 */
4207 { "rdseed", { Ev }, 0 },
4208 { "rdpid", { Em }, 0 },
4209 { "rdseed", { Ev }, 0 },
4216 { "addsubpd", { XM, EXx }, 0 },
4217 { "addsubps", { XM, EXx }, 0 },
4223 { "movq2dq",{ XM, MS }, 0 },
4224 { "movq", { EXqS, XM }, 0 },
4225 { "movdq2q",{ MX, XS }, 0 },
4231 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4232 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4233 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4238 { "movntq", { Mq, MX }, PREFIX_OPCODE },
4240 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4248 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4253 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4255 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4262 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4269 { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4276 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4283 { "ptest", { XM, EXx }, PREFIX_OPCODE },
4290 { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4297 { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4304 { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4311 { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4318 { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4325 { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4332 { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4339 { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4346 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4353 { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4360 { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4367 { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4374 { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4381 { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4388 { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4395 { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4402 { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4409 { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4416 { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4423 { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4430 { "pminud", { XM, EXx }, PREFIX_OPCODE },
4437 { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4444 { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4451 { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4458 { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4465 { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4472 { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4479 { "invept", { Gm, Mo }, PREFIX_OPCODE },
4486 { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4493 { "invpcid", { Gm, M }, PREFIX_OPCODE },
4498 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4503 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4508 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4513 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4518 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4523 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4530 { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4537 { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4544 { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4551 { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4558 { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4563 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4565 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4566 { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4571 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4573 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4574 { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4581 { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4586 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4587 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
4588 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
4596 { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4603 { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4610 { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4617 { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4624 { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4631 { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4638 { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4645 { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4652 { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4659 { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4666 { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4673 { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4680 { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4687 { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4694 { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE },
4701 { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE },
4708 { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4715 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4722 { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4729 { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4736 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4743 { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4748 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4755 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4758 /* PREFIX_VEX_0F10 */
4760 { VEX_W_TABLE (VEX_W_0F10_P_0) },
4761 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4762 { VEX_W_TABLE (VEX_W_0F10_P_2) },
4763 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4766 /* PREFIX_VEX_0F11 */
4768 { VEX_W_TABLE (VEX_W_0F11_P_0) },
4769 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4770 { VEX_W_TABLE (VEX_W_0F11_P_2) },
4771 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4774 /* PREFIX_VEX_0F12 */
4776 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4777 { VEX_W_TABLE (VEX_W_0F12_P_1) },
4778 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4779 { VEX_W_TABLE (VEX_W_0F12_P_3) },
4782 /* PREFIX_VEX_0F16 */
4784 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4785 { VEX_W_TABLE (VEX_W_0F16_P_1) },
4786 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4789 /* PREFIX_VEX_0F2A */
4792 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4794 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4797 /* PREFIX_VEX_0F2C */
4800 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4802 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4805 /* PREFIX_VEX_0F2D */
4808 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4810 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4813 /* PREFIX_VEX_0F2E */
4815 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4817 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4820 /* PREFIX_VEX_0F2F */
4822 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4824 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4827 /* PREFIX_VEX_0F41 */
4829 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4831 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4834 /* PREFIX_VEX_0F42 */
4836 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4838 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4841 /* PREFIX_VEX_0F44 */
4843 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4845 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4848 /* PREFIX_VEX_0F45 */
4850 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4852 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4855 /* PREFIX_VEX_0F46 */
4857 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4859 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4862 /* PREFIX_VEX_0F47 */
4864 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4866 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4869 /* PREFIX_VEX_0F4A */
4871 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4873 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4876 /* PREFIX_VEX_0F4B */
4878 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4880 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4883 /* PREFIX_VEX_0F51 */
4885 { VEX_W_TABLE (VEX_W_0F51_P_0) },
4886 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4887 { VEX_W_TABLE (VEX_W_0F51_P_2) },
4888 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4891 /* PREFIX_VEX_0F52 */
4893 { VEX_W_TABLE (VEX_W_0F52_P_0) },
4894 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4897 /* PREFIX_VEX_0F53 */
4899 { VEX_W_TABLE (VEX_W_0F53_P_0) },
4900 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4903 /* PREFIX_VEX_0F58 */
4905 { VEX_W_TABLE (VEX_W_0F58_P_0) },
4906 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4907 { VEX_W_TABLE (VEX_W_0F58_P_2) },
4908 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4911 /* PREFIX_VEX_0F59 */
4913 { VEX_W_TABLE (VEX_W_0F59_P_0) },
4914 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4915 { VEX_W_TABLE (VEX_W_0F59_P_2) },
4916 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4919 /* PREFIX_VEX_0F5A */
4921 { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4922 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4923 { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4924 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4927 /* PREFIX_VEX_0F5B */
4929 { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4930 { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4931 { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4934 /* PREFIX_VEX_0F5C */
4936 { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4937 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4938 { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4939 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4942 /* PREFIX_VEX_0F5D */
4944 { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4945 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4946 { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4947 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4950 /* PREFIX_VEX_0F5E */
4952 { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4953 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4954 { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4955 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4958 /* PREFIX_VEX_0F5F */
4960 { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4961 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4962 { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4963 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4966 /* PREFIX_VEX_0F60 */
4970 { VEX_W_TABLE (VEX_W_0F60_P_2) },
4973 /* PREFIX_VEX_0F61 */
4977 { VEX_W_TABLE (VEX_W_0F61_P_2) },
4980 /* PREFIX_VEX_0F62 */
4984 { VEX_W_TABLE (VEX_W_0F62_P_2) },
4987 /* PREFIX_VEX_0F63 */
4991 { VEX_W_TABLE (VEX_W_0F63_P_2) },
4994 /* PREFIX_VEX_0F64 */
4998 { VEX_W_TABLE (VEX_W_0F64_P_2) },
5001 /* PREFIX_VEX_0F65 */
5005 { VEX_W_TABLE (VEX_W_0F65_P_2) },
5008 /* PREFIX_VEX_0F66 */
5012 { VEX_W_TABLE (VEX_W_0F66_P_2) },
5015 /* PREFIX_VEX_0F67 */
5019 { VEX_W_TABLE (VEX_W_0F67_P_2) },
5022 /* PREFIX_VEX_0F68 */
5026 { VEX_W_TABLE (VEX_W_0F68_P_2) },
5029 /* PREFIX_VEX_0F69 */
5033 { VEX_W_TABLE (VEX_W_0F69_P_2) },
5036 /* PREFIX_VEX_0F6A */
5040 { VEX_W_TABLE (VEX_W_0F6A_P_2) },
5043 /* PREFIX_VEX_0F6B */
5047 { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5050 /* PREFIX_VEX_0F6C */
5054 { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5057 /* PREFIX_VEX_0F6D */
5061 { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5064 /* PREFIX_VEX_0F6E */
5068 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5071 /* PREFIX_VEX_0F6F */
5074 { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5075 { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5078 /* PREFIX_VEX_0F70 */
5081 { VEX_W_TABLE (VEX_W_0F70_P_1) },
5082 { VEX_W_TABLE (VEX_W_0F70_P_2) },
5083 { VEX_W_TABLE (VEX_W_0F70_P_3) },
5086 /* PREFIX_VEX_0F71_REG_2 */
5090 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5093 /* PREFIX_VEX_0F71_REG_4 */
5097 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5100 /* PREFIX_VEX_0F71_REG_6 */
5104 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5107 /* PREFIX_VEX_0F72_REG_2 */
5111 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5114 /* PREFIX_VEX_0F72_REG_4 */
5118 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5121 /* PREFIX_VEX_0F72_REG_6 */
5125 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5128 /* PREFIX_VEX_0F73_REG_2 */
5132 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5135 /* PREFIX_VEX_0F73_REG_3 */
5139 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5142 /* PREFIX_VEX_0F73_REG_6 */
5146 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5149 /* PREFIX_VEX_0F73_REG_7 */
5153 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5156 /* PREFIX_VEX_0F74 */
5160 { VEX_W_TABLE (VEX_W_0F74_P_2) },
5163 /* PREFIX_VEX_0F75 */
5167 { VEX_W_TABLE (VEX_W_0F75_P_2) },
5170 /* PREFIX_VEX_0F76 */
5174 { VEX_W_TABLE (VEX_W_0F76_P_2) },
5177 /* PREFIX_VEX_0F77 */
5179 { VEX_W_TABLE (VEX_W_0F77_P_0) },
5182 /* PREFIX_VEX_0F7C */
5186 { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5187 { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5190 /* PREFIX_VEX_0F7D */
5194 { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5195 { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5198 /* PREFIX_VEX_0F7E */
5201 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5202 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5205 /* PREFIX_VEX_0F7F */
5208 { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5209 { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5212 /* PREFIX_VEX_0F90 */
5214 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5216 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5219 /* PREFIX_VEX_0F91 */
5221 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5223 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5226 /* PREFIX_VEX_0F92 */
5228 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5230 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5231 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5234 /* PREFIX_VEX_0F93 */
5236 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5238 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5239 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5242 /* PREFIX_VEX_0F98 */
5244 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5246 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5249 /* PREFIX_VEX_0F99 */
5251 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5253 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5256 /* PREFIX_VEX_0FC2 */
5258 { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5259 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5260 { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5261 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5264 /* PREFIX_VEX_0FC4 */
5268 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5271 /* PREFIX_VEX_0FC5 */
5275 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5278 /* PREFIX_VEX_0FD0 */
5282 { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5283 { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5286 /* PREFIX_VEX_0FD1 */
5290 { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5293 /* PREFIX_VEX_0FD2 */
5297 { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5300 /* PREFIX_VEX_0FD3 */
5304 { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5307 /* PREFIX_VEX_0FD4 */
5311 { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5314 /* PREFIX_VEX_0FD5 */
5318 { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5321 /* PREFIX_VEX_0FD6 */
5325 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5328 /* PREFIX_VEX_0FD7 */
5332 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5335 /* PREFIX_VEX_0FD8 */
5339 { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5342 /* PREFIX_VEX_0FD9 */
5346 { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5349 /* PREFIX_VEX_0FDA */
5353 { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5356 /* PREFIX_VEX_0FDB */
5360 { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5363 /* PREFIX_VEX_0FDC */
5367 { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5370 /* PREFIX_VEX_0FDD */
5374 { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5377 /* PREFIX_VEX_0FDE */
5381 { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5384 /* PREFIX_VEX_0FDF */
5388 { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5391 /* PREFIX_VEX_0FE0 */
5395 { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5398 /* PREFIX_VEX_0FE1 */
5402 { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5405 /* PREFIX_VEX_0FE2 */
5409 { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5412 /* PREFIX_VEX_0FE3 */
5416 { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5419 /* PREFIX_VEX_0FE4 */
5423 { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5426 /* PREFIX_VEX_0FE5 */
5430 { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5433 /* PREFIX_VEX_0FE6 */
5436 { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5437 { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5438 { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5441 /* PREFIX_VEX_0FE7 */
5445 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5448 /* PREFIX_VEX_0FE8 */
5452 { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5455 /* PREFIX_VEX_0FE9 */
5459 { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5462 /* PREFIX_VEX_0FEA */
5466 { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5469 /* PREFIX_VEX_0FEB */
5473 { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5476 /* PREFIX_VEX_0FEC */
5480 { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5483 /* PREFIX_VEX_0FED */
5487 { VEX_W_TABLE (VEX_W_0FED_P_2) },
5490 /* PREFIX_VEX_0FEE */
5494 { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5497 /* PREFIX_VEX_0FEF */
5501 { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5504 /* PREFIX_VEX_0FF0 */
5509 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5512 /* PREFIX_VEX_0FF1 */
5516 { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5519 /* PREFIX_VEX_0FF2 */
5523 { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5526 /* PREFIX_VEX_0FF3 */
5530 { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5533 /* PREFIX_VEX_0FF4 */
5537 { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5540 /* PREFIX_VEX_0FF5 */
5544 { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5547 /* PREFIX_VEX_0FF6 */
5551 { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5554 /* PREFIX_VEX_0FF7 */
5558 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5561 /* PREFIX_VEX_0FF8 */
5565 { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5568 /* PREFIX_VEX_0FF9 */
5572 { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5575 /* PREFIX_VEX_0FFA */
5579 { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5582 /* PREFIX_VEX_0FFB */
5586 { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5589 /* PREFIX_VEX_0FFC */
5593 { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5596 /* PREFIX_VEX_0FFD */
5600 { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5603 /* PREFIX_VEX_0FFE */
5607 { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5610 /* PREFIX_VEX_0F3800 */
5614 { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5617 /* PREFIX_VEX_0F3801 */
5621 { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5624 /* PREFIX_VEX_0F3802 */
5628 { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5631 /* PREFIX_VEX_0F3803 */
5635 { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5638 /* PREFIX_VEX_0F3804 */
5642 { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5645 /* PREFIX_VEX_0F3805 */
5649 { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5652 /* PREFIX_VEX_0F3806 */
5656 { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5659 /* PREFIX_VEX_0F3807 */
5663 { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5666 /* PREFIX_VEX_0F3808 */
5670 { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5673 /* PREFIX_VEX_0F3809 */
5677 { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5680 /* PREFIX_VEX_0F380A */
5684 { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5687 /* PREFIX_VEX_0F380B */
5691 { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5694 /* PREFIX_VEX_0F380C */
5698 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5701 /* PREFIX_VEX_0F380D */
5705 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5708 /* PREFIX_VEX_0F380E */
5712 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5715 /* PREFIX_VEX_0F380F */
5719 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5722 /* PREFIX_VEX_0F3813 */
5726 { "vcvtph2ps", { XM, EXxmmq }, 0 },
5729 /* PREFIX_VEX_0F3816 */
5733 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5736 /* PREFIX_VEX_0F3817 */
5740 { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5743 /* PREFIX_VEX_0F3818 */
5747 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5750 /* PREFIX_VEX_0F3819 */
5754 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5757 /* PREFIX_VEX_0F381A */
5761 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5764 /* PREFIX_VEX_0F381C */
5768 { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5771 /* PREFIX_VEX_0F381D */
5775 { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5778 /* PREFIX_VEX_0F381E */
5782 { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5785 /* PREFIX_VEX_0F3820 */
5789 { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5792 /* PREFIX_VEX_0F3821 */
5796 { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5799 /* PREFIX_VEX_0F3822 */
5803 { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5806 /* PREFIX_VEX_0F3823 */
5810 { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5813 /* PREFIX_VEX_0F3824 */
5817 { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5820 /* PREFIX_VEX_0F3825 */
5824 { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5827 /* PREFIX_VEX_0F3828 */
5831 { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5834 /* PREFIX_VEX_0F3829 */
5838 { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5841 /* PREFIX_VEX_0F382A */
5845 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5848 /* PREFIX_VEX_0F382B */
5852 { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5855 /* PREFIX_VEX_0F382C */
5859 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5862 /* PREFIX_VEX_0F382D */
5866 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5869 /* PREFIX_VEX_0F382E */
5873 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5876 /* PREFIX_VEX_0F382F */
5880 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5883 /* PREFIX_VEX_0F3830 */
5887 { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5890 /* PREFIX_VEX_0F3831 */
5894 { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5897 /* PREFIX_VEX_0F3832 */
5901 { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5904 /* PREFIX_VEX_0F3833 */
5908 { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5911 /* PREFIX_VEX_0F3834 */
5915 { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5918 /* PREFIX_VEX_0F3835 */
5922 { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5925 /* PREFIX_VEX_0F3836 */
5929 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5932 /* PREFIX_VEX_0F3837 */
5936 { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5939 /* PREFIX_VEX_0F3838 */
5943 { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5946 /* PREFIX_VEX_0F3839 */
5950 { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5953 /* PREFIX_VEX_0F383A */
5957 { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5960 /* PREFIX_VEX_0F383B */
5964 { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5967 /* PREFIX_VEX_0F383C */
5971 { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5974 /* PREFIX_VEX_0F383D */
5978 { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5981 /* PREFIX_VEX_0F383E */
5985 { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5988 /* PREFIX_VEX_0F383F */
5992 { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5995 /* PREFIX_VEX_0F3840 */
5999 { VEX_W_TABLE (VEX_W_0F3840_P_2) },
6002 /* PREFIX_VEX_0F3841 */
6006 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
6009 /* PREFIX_VEX_0F3845 */
6013 { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
6016 /* PREFIX_VEX_0F3846 */
6020 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
6023 /* PREFIX_VEX_0F3847 */
6027 { "vpsllv%LW", { XM, Vex, EXx }, 0 },
6030 /* PREFIX_VEX_0F3858 */
6034 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
6037 /* PREFIX_VEX_0F3859 */
6041 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
6044 /* PREFIX_VEX_0F385A */
6048 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6051 /* PREFIX_VEX_0F3878 */
6055 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6058 /* PREFIX_VEX_0F3879 */
6062 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6065 /* PREFIX_VEX_0F388C */
6069 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6072 /* PREFIX_VEX_0F388E */
6076 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6079 /* PREFIX_VEX_0F3890 */
6083 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6086 /* PREFIX_VEX_0F3891 */
6090 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6093 /* PREFIX_VEX_0F3892 */
6097 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6100 /* PREFIX_VEX_0F3893 */
6104 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6107 /* PREFIX_VEX_0F3896 */
6111 { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6114 /* PREFIX_VEX_0F3897 */
6118 { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6121 /* PREFIX_VEX_0F3898 */
6125 { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6128 /* PREFIX_VEX_0F3899 */
6132 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6135 /* PREFIX_VEX_0F389A */
6139 { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6142 /* PREFIX_VEX_0F389B */
6146 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6149 /* PREFIX_VEX_0F389C */
6153 { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6156 /* PREFIX_VEX_0F389D */
6160 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6163 /* PREFIX_VEX_0F389E */
6167 { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6170 /* PREFIX_VEX_0F389F */
6174 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6177 /* PREFIX_VEX_0F38A6 */
6181 { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6185 /* PREFIX_VEX_0F38A7 */
6189 { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6192 /* PREFIX_VEX_0F38A8 */
6196 { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6199 /* PREFIX_VEX_0F38A9 */
6203 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6206 /* PREFIX_VEX_0F38AA */
6210 { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6213 /* PREFIX_VEX_0F38AB */
6217 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6220 /* PREFIX_VEX_0F38AC */
6224 { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6227 /* PREFIX_VEX_0F38AD */
6231 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6234 /* PREFIX_VEX_0F38AE */
6238 { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6241 /* PREFIX_VEX_0F38AF */
6245 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6248 /* PREFIX_VEX_0F38B6 */
6252 { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6255 /* PREFIX_VEX_0F38B7 */
6259 { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6262 /* PREFIX_VEX_0F38B8 */
6266 { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6269 /* PREFIX_VEX_0F38B9 */
6273 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6276 /* PREFIX_VEX_0F38BA */
6280 { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6283 /* PREFIX_VEX_0F38BB */
6287 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6290 /* PREFIX_VEX_0F38BC */
6294 { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6297 /* PREFIX_VEX_0F38BD */
6301 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6304 /* PREFIX_VEX_0F38BE */
6308 { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6311 /* PREFIX_VEX_0F38BF */
6315 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6318 /* PREFIX_VEX_0F38DB */
6322 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6325 /* PREFIX_VEX_0F38DC */
6329 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6332 /* PREFIX_VEX_0F38DD */
6336 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6339 /* PREFIX_VEX_0F38DE */
6343 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6346 /* PREFIX_VEX_0F38DF */
6350 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6353 /* PREFIX_VEX_0F38F2 */
6355 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6358 /* PREFIX_VEX_0F38F3_REG_1 */
6360 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6363 /* PREFIX_VEX_0F38F3_REG_2 */
6365 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6368 /* PREFIX_VEX_0F38F3_REG_3 */
6370 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6373 /* PREFIX_VEX_0F38F5 */
6375 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6376 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6378 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6381 /* PREFIX_VEX_0F38F6 */
6386 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6389 /* PREFIX_VEX_0F38F7 */
6391 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6392 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6393 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6394 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6397 /* PREFIX_VEX_0F3A00 */
6401 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6404 /* PREFIX_VEX_0F3A01 */
6408 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6411 /* PREFIX_VEX_0F3A02 */
6415 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6418 /* PREFIX_VEX_0F3A04 */
6422 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6425 /* PREFIX_VEX_0F3A05 */
6429 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6432 /* PREFIX_VEX_0F3A06 */
6436 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6439 /* PREFIX_VEX_0F3A08 */
6443 { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6446 /* PREFIX_VEX_0F3A09 */
6450 { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6453 /* PREFIX_VEX_0F3A0A */
6457 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6460 /* PREFIX_VEX_0F3A0B */
6464 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6467 /* PREFIX_VEX_0F3A0C */
6471 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6474 /* PREFIX_VEX_0F3A0D */
6478 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6481 /* PREFIX_VEX_0F3A0E */
6485 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6488 /* PREFIX_VEX_0F3A0F */
6492 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6495 /* PREFIX_VEX_0F3A14 */
6499 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6502 /* PREFIX_VEX_0F3A15 */
6506 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6509 /* PREFIX_VEX_0F3A16 */
6513 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6516 /* PREFIX_VEX_0F3A17 */
6520 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6523 /* PREFIX_VEX_0F3A18 */
6527 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6530 /* PREFIX_VEX_0F3A19 */
6534 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6537 /* PREFIX_VEX_0F3A1D */
6541 { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6544 /* PREFIX_VEX_0F3A20 */
6548 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6551 /* PREFIX_VEX_0F3A21 */
6555 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6558 /* PREFIX_VEX_0F3A22 */
6562 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6565 /* PREFIX_VEX_0F3A30 */
6569 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6572 /* PREFIX_VEX_0F3A31 */
6576 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6579 /* PREFIX_VEX_0F3A32 */
6583 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6586 /* PREFIX_VEX_0F3A33 */
6590 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6593 /* PREFIX_VEX_0F3A38 */
6597 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6600 /* PREFIX_VEX_0F3A39 */
6604 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6607 /* PREFIX_VEX_0F3A40 */
6611 { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6614 /* PREFIX_VEX_0F3A41 */
6618 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6621 /* PREFIX_VEX_0F3A42 */
6625 { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6628 /* PREFIX_VEX_0F3A44 */
6632 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6635 /* PREFIX_VEX_0F3A46 */
6639 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6642 /* PREFIX_VEX_0F3A48 */
6646 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6649 /* PREFIX_VEX_0F3A49 */
6653 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6656 /* PREFIX_VEX_0F3A4A */
6660 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6663 /* PREFIX_VEX_0F3A4B */
6667 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6670 /* PREFIX_VEX_0F3A4C */
6674 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6677 /* PREFIX_VEX_0F3A5C */
6681 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6684 /* PREFIX_VEX_0F3A5D */
6688 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6691 /* PREFIX_VEX_0F3A5E */
6695 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6698 /* PREFIX_VEX_0F3A5F */
6702 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6705 /* PREFIX_VEX_0F3A60 */
6709 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6713 /* PREFIX_VEX_0F3A61 */
6717 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6720 /* PREFIX_VEX_0F3A62 */
6724 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6727 /* PREFIX_VEX_0F3A63 */
6731 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6734 /* PREFIX_VEX_0F3A68 */
6738 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6741 /* PREFIX_VEX_0F3A69 */
6745 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6748 /* PREFIX_VEX_0F3A6A */
6752 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6755 /* PREFIX_VEX_0F3A6B */
6759 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6762 /* PREFIX_VEX_0F3A6C */
6766 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6769 /* PREFIX_VEX_0F3A6D */
6773 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6776 /* PREFIX_VEX_0F3A6E */
6780 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6783 /* PREFIX_VEX_0F3A6F */
6787 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6790 /* PREFIX_VEX_0F3A78 */
6794 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6797 /* PREFIX_VEX_0F3A79 */
6801 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6804 /* PREFIX_VEX_0F3A7A */
6808 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6811 /* PREFIX_VEX_0F3A7B */
6815 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6818 /* PREFIX_VEX_0F3A7C */
6822 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6826 /* PREFIX_VEX_0F3A7D */
6830 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6833 /* PREFIX_VEX_0F3A7E */
6837 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6840 /* PREFIX_VEX_0F3A7F */
6844 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6847 /* PREFIX_VEX_0F3ADF */
6851 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6854 /* PREFIX_VEX_0F3AF0 */
6859 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6862 #define NEED_PREFIX_TABLE
6863 #include "i386-dis-evex.h"
6864 #undef NEED_PREFIX_TABLE
6867 static const struct dis386 x86_64_table[][2] = {
6870 { "pushP", { es }, 0 },
6875 { "popP", { es }, 0 },
6880 { "pushP", { cs }, 0 },
6885 { "pushP", { ss }, 0 },
6890 { "popP", { ss }, 0 },
6895 { "pushP", { ds }, 0 },
6900 { "popP", { ds }, 0 },
6905 { "daa", { XX }, 0 },
6910 { "das", { XX }, 0 },
6915 { "aaa", { XX }, 0 },
6920 { "aas", { XX }, 0 },
6925 { "pushaP", { XX }, 0 },
6930 { "popaP", { XX }, 0 },
6935 { MOD_TABLE (MOD_62_32BIT) },
6936 { EVEX_TABLE (EVEX_0F) },
6941 { "arpl", { Ew, Gw }, 0 },
6942 { "movs{lq|xd}", { Gv, Ed }, 0 },
6947 { "ins{R|}", { Yzr, indirDX }, 0 },
6948 { "ins{G|}", { Yzr, indirDX }, 0 },
6953 { "outs{R|}", { indirDXr, Xz }, 0 },
6954 { "outs{G|}", { indirDXr, Xz }, 0 },
6959 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6960 { REG_TABLE (REG_80) },
6965 { "Jcall{T|}", { Ap }, 0 },
6970 { MOD_TABLE (MOD_C4_32BIT) },
6971 { VEX_C4_TABLE (VEX_0F) },
6976 { MOD_TABLE (MOD_C5_32BIT) },
6977 { VEX_C5_TABLE (VEX_0F) },
6982 { "into", { XX }, 0 },
6987 { "aam", { Ib }, 0 },
6992 { "aad", { Ib }, 0 },
6997 { "callP", { Jv, BND }, 0 },
6998 { "call@", { Jv, BND }, 0 }
7003 { "jmpP", { Jv, BND }, 0 },
7004 { "jmp@", { Jv, BND }, 0 }
7009 { "Jjmp{T|}", { Ap }, 0 },
7012 /* X86_64_0F01_REG_0 */
7014 { "sgdt{Q|IQ}", { M }, 0 },
7015 { "sgdt", { M }, 0 },
7018 /* X86_64_0F01_REG_1 */
7020 { "sidt{Q|IQ}", { M }, 0 },
7021 { "sidt", { M }, 0 },
7024 /* X86_64_0F01_REG_2 */
7026 { "lgdt{Q|Q}", { M }, 0 },
7027 { "lgdt", { M }, 0 },
7030 /* X86_64_0F01_REG_3 */
7032 { "lidt{Q|Q}", { M }, 0 },
7033 { "lidt", { M }, 0 },
7037 static const struct dis386 three_byte_table[][256] = {
7039 /* THREE_BYTE_0F38 */
7042 { "pshufb", { MX, EM }, PREFIX_OPCODE },
7043 { "phaddw", { MX, EM }, PREFIX_OPCODE },
7044 { "phaddd", { MX, EM }, PREFIX_OPCODE },
7045 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
7046 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
7047 { "phsubw", { MX, EM }, PREFIX_OPCODE },
7048 { "phsubd", { MX, EM }, PREFIX_OPCODE },
7049 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
7051 { "psignb", { MX, EM }, PREFIX_OPCODE },
7052 { "psignw", { MX, EM }, PREFIX_OPCODE },
7053 { "psignd", { MX, EM }, PREFIX_OPCODE },
7054 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
7060 { PREFIX_TABLE (PREFIX_0F3810) },
7064 { PREFIX_TABLE (PREFIX_0F3814) },
7065 { PREFIX_TABLE (PREFIX_0F3815) },
7067 { PREFIX_TABLE (PREFIX_0F3817) },
7073 { "pabsb", { MX, EM }, PREFIX_OPCODE },
7074 { "pabsw", { MX, EM }, PREFIX_OPCODE },
7075 { "pabsd", { MX, EM }, PREFIX_OPCODE },
7078 { PREFIX_TABLE (PREFIX_0F3820) },
7079 { PREFIX_TABLE (PREFIX_0F3821) },
7080 { PREFIX_TABLE (PREFIX_0F3822) },
7081 { PREFIX_TABLE (PREFIX_0F3823) },
7082 { PREFIX_TABLE (PREFIX_0F3824) },
7083 { PREFIX_TABLE (PREFIX_0F3825) },
7087 { PREFIX_TABLE (PREFIX_0F3828) },
7088 { PREFIX_TABLE (PREFIX_0F3829) },
7089 { PREFIX_TABLE (PREFIX_0F382A) },
7090 { PREFIX_TABLE (PREFIX_0F382B) },
7096 { PREFIX_TABLE (PREFIX_0F3830) },
7097 { PREFIX_TABLE (PREFIX_0F3831) },
7098 { PREFIX_TABLE (PREFIX_0F3832) },
7099 { PREFIX_TABLE (PREFIX_0F3833) },
7100 { PREFIX_TABLE (PREFIX_0F3834) },
7101 { PREFIX_TABLE (PREFIX_0F3835) },
7103 { PREFIX_TABLE (PREFIX_0F3837) },
7105 { PREFIX_TABLE (PREFIX_0F3838) },
7106 { PREFIX_TABLE (PREFIX_0F3839) },
7107 { PREFIX_TABLE (PREFIX_0F383A) },
7108 { PREFIX_TABLE (PREFIX_0F383B) },
7109 { PREFIX_TABLE (PREFIX_0F383C) },
7110 { PREFIX_TABLE (PREFIX_0F383D) },
7111 { PREFIX_TABLE (PREFIX_0F383E) },
7112 { PREFIX_TABLE (PREFIX_0F383F) },
7114 { PREFIX_TABLE (PREFIX_0F3840) },
7115 { PREFIX_TABLE (PREFIX_0F3841) },
7186 { PREFIX_TABLE (PREFIX_0F3880) },
7187 { PREFIX_TABLE (PREFIX_0F3881) },
7188 { PREFIX_TABLE (PREFIX_0F3882) },
7267 { PREFIX_TABLE (PREFIX_0F38C8) },
7268 { PREFIX_TABLE (PREFIX_0F38C9) },
7269 { PREFIX_TABLE (PREFIX_0F38CA) },
7270 { PREFIX_TABLE (PREFIX_0F38CB) },
7271 { PREFIX_TABLE (PREFIX_0F38CC) },
7272 { PREFIX_TABLE (PREFIX_0F38CD) },
7288 { PREFIX_TABLE (PREFIX_0F38DB) },
7289 { PREFIX_TABLE (PREFIX_0F38DC) },
7290 { PREFIX_TABLE (PREFIX_0F38DD) },
7291 { PREFIX_TABLE (PREFIX_0F38DE) },
7292 { PREFIX_TABLE (PREFIX_0F38DF) },
7312 { PREFIX_TABLE (PREFIX_0F38F0) },
7313 { PREFIX_TABLE (PREFIX_0F38F1) },
7317 { PREFIX_TABLE (PREFIX_0F38F5) },
7318 { PREFIX_TABLE (PREFIX_0F38F6) },
7330 /* THREE_BYTE_0F3A */
7342 { PREFIX_TABLE (PREFIX_0F3A08) },
7343 { PREFIX_TABLE (PREFIX_0F3A09) },
7344 { PREFIX_TABLE (PREFIX_0F3A0A) },
7345 { PREFIX_TABLE (PREFIX_0F3A0B) },
7346 { PREFIX_TABLE (PREFIX_0F3A0C) },
7347 { PREFIX_TABLE (PREFIX_0F3A0D) },
7348 { PREFIX_TABLE (PREFIX_0F3A0E) },
7349 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
7355 { PREFIX_TABLE (PREFIX_0F3A14) },
7356 { PREFIX_TABLE (PREFIX_0F3A15) },
7357 { PREFIX_TABLE (PREFIX_0F3A16) },
7358 { PREFIX_TABLE (PREFIX_0F3A17) },
7369 { PREFIX_TABLE (PREFIX_0F3A20) },
7370 { PREFIX_TABLE (PREFIX_0F3A21) },
7371 { PREFIX_TABLE (PREFIX_0F3A22) },
7405 { PREFIX_TABLE (PREFIX_0F3A40) },
7406 { PREFIX_TABLE (PREFIX_0F3A41) },
7407 { PREFIX_TABLE (PREFIX_0F3A42) },
7409 { PREFIX_TABLE (PREFIX_0F3A44) },
7441 { PREFIX_TABLE (PREFIX_0F3A60) },
7442 { PREFIX_TABLE (PREFIX_0F3A61) },
7443 { PREFIX_TABLE (PREFIX_0F3A62) },
7444 { PREFIX_TABLE (PREFIX_0F3A63) },
7562 { PREFIX_TABLE (PREFIX_0F3ACC) },
7583 { PREFIX_TABLE (PREFIX_0F3ADF) },
7623 static const struct dis386 xop_table[][256] = {
7776 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7777 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7778 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7786 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7787 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7794 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7795 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7796 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7804 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7805 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7809 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7810 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7813 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7831 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7843 { "vprotb", { XM, Vex_2src_1, Ib }, 0 },
7844 { "vprotw", { XM, Vex_2src_1, Ib }, 0 },
7845 { "vprotd", { XM, Vex_2src_1, Ib }, 0 },
7846 { "vprotq", { XM, Vex_2src_1, Ib }, 0 },
7856 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7857 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7858 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7859 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7892 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7893 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7894 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7895 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7919 { REG_TABLE (REG_XOP_TBM_01) },
7920 { REG_TABLE (REG_XOP_TBM_02) },
7938 { REG_TABLE (REG_XOP_LWPCB) },
8062 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8063 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8064 { "vfrczss", { XM, EXd }, 0 },
8065 { "vfrczsd", { XM, EXq }, 0 },
8080 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8081 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8082 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8083 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8084 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8085 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8086 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8087 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8089 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8090 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8091 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8092 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8135 { "vphaddbw", { XM, EXxmm }, 0 },
8136 { "vphaddbd", { XM, EXxmm }, 0 },
8137 { "vphaddbq", { XM, EXxmm }, 0 },
8140 { "vphaddwd", { XM, EXxmm }, 0 },
8141 { "vphaddwq", { XM, EXxmm }, 0 },
8146 { "vphadddq", { XM, EXxmm }, 0 },
8153 { "vphaddubw", { XM, EXxmm }, 0 },
8154 { "vphaddubd", { XM, EXxmm }, 0 },
8155 { "vphaddubq", { XM, EXxmm }, 0 },
8158 { "vphadduwd", { XM, EXxmm }, 0 },
8159 { "vphadduwq", { XM, EXxmm }, 0 },
8164 { "vphaddudq", { XM, EXxmm }, 0 },
8171 { "vphsubbw", { XM, EXxmm }, 0 },
8172 { "vphsubwd", { XM, EXxmm }, 0 },
8173 { "vphsubdq", { XM, EXxmm }, 0 },
8227 { "bextr", { Gv, Ev, Iq }, 0 },
8229 { REG_TABLE (REG_XOP_LWP) },
8499 static const struct dis386 vex_table[][256] = {
8521 { PREFIX_TABLE (PREFIX_VEX_0F10) },
8522 { PREFIX_TABLE (PREFIX_VEX_0F11) },
8523 { PREFIX_TABLE (PREFIX_VEX_0F12) },
8524 { MOD_TABLE (MOD_VEX_0F13) },
8525 { VEX_W_TABLE (VEX_W_0F14) },
8526 { VEX_W_TABLE (VEX_W_0F15) },
8527 { PREFIX_TABLE (PREFIX_VEX_0F16) },
8528 { MOD_TABLE (MOD_VEX_0F17) },
8548 { VEX_W_TABLE (VEX_W_0F28) },
8549 { VEX_W_TABLE (VEX_W_0F29) },
8550 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8551 { MOD_TABLE (MOD_VEX_0F2B) },
8552 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8553 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8554 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8555 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8576 { PREFIX_TABLE (PREFIX_VEX_0F41) },
8577 { PREFIX_TABLE (PREFIX_VEX_0F42) },
8579 { PREFIX_TABLE (PREFIX_VEX_0F44) },
8580 { PREFIX_TABLE (PREFIX_VEX_0F45) },
8581 { PREFIX_TABLE (PREFIX_VEX_0F46) },
8582 { PREFIX_TABLE (PREFIX_VEX_0F47) },
8586 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8587 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8593 { MOD_TABLE (MOD_VEX_0F50) },
8594 { PREFIX_TABLE (PREFIX_VEX_0F51) },
8595 { PREFIX_TABLE (PREFIX_VEX_0F52) },
8596 { PREFIX_TABLE (PREFIX_VEX_0F53) },
8597 { "vandpX", { XM, Vex, EXx }, 0 },
8598 { "vandnpX", { XM, Vex, EXx }, 0 },
8599 { "vorpX", { XM, Vex, EXx }, 0 },
8600 { "vxorpX", { XM, Vex, EXx }, 0 },
8602 { PREFIX_TABLE (PREFIX_VEX_0F58) },
8603 { PREFIX_TABLE (PREFIX_VEX_0F59) },
8604 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8605 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8606 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8607 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8608 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8609 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8611 { PREFIX_TABLE (PREFIX_VEX_0F60) },
8612 { PREFIX_TABLE (PREFIX_VEX_0F61) },
8613 { PREFIX_TABLE (PREFIX_VEX_0F62) },
8614 { PREFIX_TABLE (PREFIX_VEX_0F63) },
8615 { PREFIX_TABLE (PREFIX_VEX_0F64) },
8616 { PREFIX_TABLE (PREFIX_VEX_0F65) },
8617 { PREFIX_TABLE (PREFIX_VEX_0F66) },
8618 { PREFIX_TABLE (PREFIX_VEX_0F67) },
8620 { PREFIX_TABLE (PREFIX_VEX_0F68) },
8621 { PREFIX_TABLE (PREFIX_VEX_0F69) },
8622 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8623 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8624 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8625 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8626 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8627 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8629 { PREFIX_TABLE (PREFIX_VEX_0F70) },
8630 { REG_TABLE (REG_VEX_0F71) },
8631 { REG_TABLE (REG_VEX_0F72) },
8632 { REG_TABLE (REG_VEX_0F73) },
8633 { PREFIX_TABLE (PREFIX_VEX_0F74) },
8634 { PREFIX_TABLE (PREFIX_VEX_0F75) },
8635 { PREFIX_TABLE (PREFIX_VEX_0F76) },
8636 { PREFIX_TABLE (PREFIX_VEX_0F77) },
8642 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8643 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8644 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8645 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8665 { PREFIX_TABLE (PREFIX_VEX_0F90) },
8666 { PREFIX_TABLE (PREFIX_VEX_0F91) },
8667 { PREFIX_TABLE (PREFIX_VEX_0F92) },
8668 { PREFIX_TABLE (PREFIX_VEX_0F93) },
8674 { PREFIX_TABLE (PREFIX_VEX_0F98) },
8675 { PREFIX_TABLE (PREFIX_VEX_0F99) },
8698 { REG_TABLE (REG_VEX_0FAE) },
8721 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8723 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8724 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8725 { "vshufpX", { XM, Vex, EXx, Ib }, 0 },
8737 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8738 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8739 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8740 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8741 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8742 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8743 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8744 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8746 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8747 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8748 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8749 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8750 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8751 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8752 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8753 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8755 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8756 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8757 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8758 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8759 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8760 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8761 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8762 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8764 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8765 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8766 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8767 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8768 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8769 { PREFIX_TABLE (PREFIX_VEX_0FED) },
8770 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8771 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8773 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8774 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8775 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8776 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8777 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8778 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8779 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8780 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8782 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8783 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8784 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8785 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8786 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8787 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8788 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8795 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8797 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8798 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8799 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8800 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8803 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8804 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8806 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8807 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8808 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8809 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8810 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8815 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8818 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8819 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8821 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8822 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8823 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8825 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8826 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8827 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8830 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8831 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8832 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8833 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8834 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8835 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8839 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8840 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8841 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8842 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8843 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8844 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8845 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8846 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8848 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8849 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8850 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8851 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8852 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8853 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8854 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8855 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8857 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8858 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8859 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8860 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8861 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8862 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8863 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8864 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8866 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8867 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8871 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8872 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8873 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8895 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8929 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8956 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8957 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8959 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8962 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8963 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8965 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8966 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8967 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8968 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8969 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8972 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8980 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8981 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8983 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8984 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8985 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8986 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8987 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8988 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8989 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8990 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8999 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9001 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9002 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9004 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9005 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9006 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9008 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9066 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9067 { REG_TABLE (REG_VEX_0F38F3) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9085 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9086 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9087 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9094 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9096 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9098 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9099 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9101 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9107 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9108 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9109 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9110 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9112 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9113 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9117 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9121 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9122 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9123 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9139 { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9140 { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9141 { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9142 { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9148 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9149 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9157 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9158 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9159 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9161 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9163 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9166 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9167 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9168 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9169 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9170 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9188 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9189 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9190 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9191 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9193 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9194 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9195 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9196 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9202 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9203 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9204 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9205 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9206 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9207 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9208 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9209 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9220 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9221 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9222 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9223 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9224 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9225 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9226 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9227 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9335 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9355 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9375 #define NEED_OPCODE_TABLE
9376 #include "i386-dis-evex.h"
9377 #undef NEED_OPCODE_TABLE
9378 static const struct dis386 vex_len_table[][2] = {
9379 /* VEX_LEN_0F10_P_1 */
9381 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9382 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9385 /* VEX_LEN_0F10_P_3 */
9387 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9388 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9391 /* VEX_LEN_0F11_P_1 */
9393 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9394 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9397 /* VEX_LEN_0F11_P_3 */
9399 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9400 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9403 /* VEX_LEN_0F12_P_0_M_0 */
9405 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9408 /* VEX_LEN_0F12_P_0_M_1 */
9410 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9413 /* VEX_LEN_0F12_P_2 */
9415 { VEX_W_TABLE (VEX_W_0F12_P_2) },
9418 /* VEX_LEN_0F13_M_0 */
9420 { VEX_W_TABLE (VEX_W_0F13_M_0) },
9423 /* VEX_LEN_0F16_P_0_M_0 */
9425 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9428 /* VEX_LEN_0F16_P_0_M_1 */
9430 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9433 /* VEX_LEN_0F16_P_2 */
9435 { VEX_W_TABLE (VEX_W_0F16_P_2) },
9438 /* VEX_LEN_0F17_M_0 */
9440 { VEX_W_TABLE (VEX_W_0F17_M_0) },
9443 /* VEX_LEN_0F2A_P_1 */
9445 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9446 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9449 /* VEX_LEN_0F2A_P_3 */
9451 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9452 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9455 /* VEX_LEN_0F2C_P_1 */
9457 { "vcvttss2siY", { Gv, EXdScalar }, 0 },
9458 { "vcvttss2siY", { Gv, EXdScalar }, 0 },
9461 /* VEX_LEN_0F2C_P_3 */
9463 { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
9464 { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
9467 /* VEX_LEN_0F2D_P_1 */
9469 { "vcvtss2siY", { Gv, EXdScalar }, 0 },
9470 { "vcvtss2siY", { Gv, EXdScalar }, 0 },
9473 /* VEX_LEN_0F2D_P_3 */
9475 { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
9476 { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
9479 /* VEX_LEN_0F2E_P_0 */
9481 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9482 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9485 /* VEX_LEN_0F2E_P_2 */
9487 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9488 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9491 /* VEX_LEN_0F2F_P_0 */
9493 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9494 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9497 /* VEX_LEN_0F2F_P_2 */
9499 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9500 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9503 /* VEX_LEN_0F41_P_0 */
9506 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9508 /* VEX_LEN_0F41_P_2 */
9511 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9513 /* VEX_LEN_0F42_P_0 */
9516 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9518 /* VEX_LEN_0F42_P_2 */
9521 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9523 /* VEX_LEN_0F44_P_0 */
9525 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9527 /* VEX_LEN_0F44_P_2 */
9529 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9531 /* VEX_LEN_0F45_P_0 */
9534 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9536 /* VEX_LEN_0F45_P_2 */
9539 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9541 /* VEX_LEN_0F46_P_0 */
9544 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9546 /* VEX_LEN_0F46_P_2 */
9549 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9551 /* VEX_LEN_0F47_P_0 */
9554 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9556 /* VEX_LEN_0F47_P_2 */
9559 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9561 /* VEX_LEN_0F4A_P_0 */
9564 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9566 /* VEX_LEN_0F4A_P_2 */
9569 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9571 /* VEX_LEN_0F4B_P_0 */
9574 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9576 /* VEX_LEN_0F4B_P_2 */
9579 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9582 /* VEX_LEN_0F51_P_1 */
9584 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9585 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9588 /* VEX_LEN_0F51_P_3 */
9590 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9591 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9594 /* VEX_LEN_0F52_P_1 */
9596 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9597 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9600 /* VEX_LEN_0F53_P_1 */
9602 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9603 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9606 /* VEX_LEN_0F58_P_1 */
9608 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9609 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9612 /* VEX_LEN_0F58_P_3 */
9614 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9615 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9618 /* VEX_LEN_0F59_P_1 */
9620 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9621 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9624 /* VEX_LEN_0F59_P_3 */
9626 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9627 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9630 /* VEX_LEN_0F5A_P_1 */
9632 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9633 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9636 /* VEX_LEN_0F5A_P_3 */
9638 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9639 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9642 /* VEX_LEN_0F5C_P_1 */
9644 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9645 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9648 /* VEX_LEN_0F5C_P_3 */
9650 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9651 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9654 /* VEX_LEN_0F5D_P_1 */
9656 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9657 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9660 /* VEX_LEN_0F5D_P_3 */
9662 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9663 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9666 /* VEX_LEN_0F5E_P_1 */
9668 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9669 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9672 /* VEX_LEN_0F5E_P_3 */
9674 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9675 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9678 /* VEX_LEN_0F5F_P_1 */
9680 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9681 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9684 /* VEX_LEN_0F5F_P_3 */
9686 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9687 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9690 /* VEX_LEN_0F6E_P_2 */
9692 { "vmovK", { XMScalar, Edq }, 0 },
9693 { "vmovK", { XMScalar, Edq }, 0 },
9696 /* VEX_LEN_0F7E_P_1 */
9698 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9699 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9702 /* VEX_LEN_0F7E_P_2 */
9704 { "vmovK", { Edq, XMScalar }, 0 },
9705 { "vmovK", { Edq, XMScalar }, 0 },
9708 /* VEX_LEN_0F90_P_0 */
9710 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9713 /* VEX_LEN_0F90_P_2 */
9715 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9718 /* VEX_LEN_0F91_P_0 */
9720 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9723 /* VEX_LEN_0F91_P_2 */
9725 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9728 /* VEX_LEN_0F92_P_0 */
9730 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9733 /* VEX_LEN_0F92_P_2 */
9735 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9738 /* VEX_LEN_0F92_P_3 */
9740 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9743 /* VEX_LEN_0F93_P_0 */
9745 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9748 /* VEX_LEN_0F93_P_2 */
9750 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9753 /* VEX_LEN_0F93_P_3 */
9755 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9758 /* VEX_LEN_0F98_P_0 */
9760 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9763 /* VEX_LEN_0F98_P_2 */
9765 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9768 /* VEX_LEN_0F99_P_0 */
9770 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9773 /* VEX_LEN_0F99_P_2 */
9775 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9778 /* VEX_LEN_0FAE_R_2_M_0 */
9780 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9783 /* VEX_LEN_0FAE_R_3_M_0 */
9785 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9788 /* VEX_LEN_0FC2_P_1 */
9790 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9791 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9794 /* VEX_LEN_0FC2_P_3 */
9796 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9797 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9800 /* VEX_LEN_0FC4_P_2 */
9802 { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9805 /* VEX_LEN_0FC5_P_2 */
9807 { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9810 /* VEX_LEN_0FD6_P_2 */
9812 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9813 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9816 /* VEX_LEN_0FF7_P_2 */
9818 { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9821 /* VEX_LEN_0F3816_P_2 */
9824 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9827 /* VEX_LEN_0F3819_P_2 */
9830 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9833 /* VEX_LEN_0F381A_P_2_M_0 */
9836 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9839 /* VEX_LEN_0F3836_P_2 */
9842 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9845 /* VEX_LEN_0F3841_P_2 */
9847 { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9850 /* VEX_LEN_0F385A_P_2_M_0 */
9853 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9856 /* VEX_LEN_0F38DB_P_2 */
9858 { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9861 /* VEX_LEN_0F38DC_P_2 */
9863 { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9866 /* VEX_LEN_0F38DD_P_2 */
9868 { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9871 /* VEX_LEN_0F38DE_P_2 */
9873 { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9876 /* VEX_LEN_0F38DF_P_2 */
9878 { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9881 /* VEX_LEN_0F38F2_P_0 */
9883 { "andnS", { Gdq, VexGdq, Edq }, 0 },
9886 /* VEX_LEN_0F38F3_R_1_P_0 */
9888 { "blsrS", { VexGdq, Edq }, 0 },
9891 /* VEX_LEN_0F38F3_R_2_P_0 */
9893 { "blsmskS", { VexGdq, Edq }, 0 },
9896 /* VEX_LEN_0F38F3_R_3_P_0 */
9898 { "blsiS", { VexGdq, Edq }, 0 },
9901 /* VEX_LEN_0F38F5_P_0 */
9903 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
9906 /* VEX_LEN_0F38F5_P_1 */
9908 { "pextS", { Gdq, VexGdq, Edq }, 0 },
9911 /* VEX_LEN_0F38F5_P_3 */
9913 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
9916 /* VEX_LEN_0F38F6_P_3 */
9918 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
9921 /* VEX_LEN_0F38F7_P_0 */
9923 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
9926 /* VEX_LEN_0F38F7_P_1 */
9928 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
9931 /* VEX_LEN_0F38F7_P_2 */
9933 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
9936 /* VEX_LEN_0F38F7_P_3 */
9938 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
9941 /* VEX_LEN_0F3A00_P_2 */
9944 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9947 /* VEX_LEN_0F3A01_P_2 */
9950 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9953 /* VEX_LEN_0F3A06_P_2 */
9956 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9959 /* VEX_LEN_0F3A0A_P_2 */
9961 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9962 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9965 /* VEX_LEN_0F3A0B_P_2 */
9967 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9968 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9971 /* VEX_LEN_0F3A14_P_2 */
9973 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9976 /* VEX_LEN_0F3A15_P_2 */
9978 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9981 /* VEX_LEN_0F3A16_P_2 */
9983 { "vpextrK", { Edq, XM, Ib }, 0 },
9986 /* VEX_LEN_0F3A17_P_2 */
9988 { "vextractps", { Edqd, XM, Ib }, 0 },
9991 /* VEX_LEN_0F3A18_P_2 */
9994 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9997 /* VEX_LEN_0F3A19_P_2 */
10000 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10003 /* VEX_LEN_0F3A20_P_2 */
10005 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10008 /* VEX_LEN_0F3A21_P_2 */
10010 { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10013 /* VEX_LEN_0F3A22_P_2 */
10015 { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 },
10018 /* VEX_LEN_0F3A30_P_2 */
10020 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10023 /* VEX_LEN_0F3A31_P_2 */
10025 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10028 /* VEX_LEN_0F3A32_P_2 */
10030 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10033 /* VEX_LEN_0F3A33_P_2 */
10035 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10038 /* VEX_LEN_0F3A38_P_2 */
10041 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10044 /* VEX_LEN_0F3A39_P_2 */
10047 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10050 /* VEX_LEN_0F3A41_P_2 */
10052 { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10055 /* VEX_LEN_0F3A44_P_2 */
10057 { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10060 /* VEX_LEN_0F3A46_P_2 */
10063 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10066 /* VEX_LEN_0F3A60_P_2 */
10068 { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10071 /* VEX_LEN_0F3A61_P_2 */
10073 { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10076 /* VEX_LEN_0F3A62_P_2 */
10078 { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10081 /* VEX_LEN_0F3A63_P_2 */
10083 { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10086 /* VEX_LEN_0F3A6A_P_2 */
10088 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10091 /* VEX_LEN_0F3A6B_P_2 */
10093 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10096 /* VEX_LEN_0F3A6E_P_2 */
10098 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10101 /* VEX_LEN_0F3A6F_P_2 */
10103 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10106 /* VEX_LEN_0F3A7A_P_2 */
10108 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10111 /* VEX_LEN_0F3A7B_P_2 */
10113 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10116 /* VEX_LEN_0F3A7E_P_2 */
10118 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10121 /* VEX_LEN_0F3A7F_P_2 */
10123 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10126 /* VEX_LEN_0F3ADF_P_2 */
10128 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10131 /* VEX_LEN_0F3AF0_P_3 */
10133 { "rorxS", { Gdq, Edq, Ib }, 0 },
10136 /* VEX_LEN_0FXOP_08_CC */
10138 { "vpcomb", { XM, Vex128, EXx, Ib }, 0 },
10141 /* VEX_LEN_0FXOP_08_CD */
10143 { "vpcomw", { XM, Vex128, EXx, Ib }, 0 },
10146 /* VEX_LEN_0FXOP_08_CE */
10148 { "vpcomd", { XM, Vex128, EXx, Ib }, 0 },
10151 /* VEX_LEN_0FXOP_08_CF */
10153 { "vpcomq", { XM, Vex128, EXx, Ib }, 0 },
10156 /* VEX_LEN_0FXOP_08_EC */
10158 { "vpcomub", { XM, Vex128, EXx, Ib }, 0 },
10161 /* VEX_LEN_0FXOP_08_ED */
10163 { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 },
10166 /* VEX_LEN_0FXOP_08_EE */
10168 { "vpcomud", { XM, Vex128, EXx, Ib }, 0 },
10171 /* VEX_LEN_0FXOP_08_EF */
10173 { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 },
10176 /* VEX_LEN_0FXOP_09_80 */
10178 { "vfrczps", { XM, EXxmm }, 0 },
10179 { "vfrczps", { XM, EXymmq }, 0 },
10182 /* VEX_LEN_0FXOP_09_81 */
10184 { "vfrczpd", { XM, EXxmm }, 0 },
10185 { "vfrczpd", { XM, EXymmq }, 0 },
10189 static const struct dis386 vex_w_table[][2] = {
10191 /* VEX_W_0F10_P_0 */
10192 { "vmovups", { XM, EXx }, 0 },
10195 /* VEX_W_0F10_P_1 */
10196 { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
10199 /* VEX_W_0F10_P_2 */
10200 { "vmovupd", { XM, EXx }, 0 },
10203 /* VEX_W_0F10_P_3 */
10204 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
10207 /* VEX_W_0F11_P_0 */
10208 { "vmovups", { EXxS, XM }, 0 },
10211 /* VEX_W_0F11_P_1 */
10212 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10215 /* VEX_W_0F11_P_2 */
10216 { "vmovupd", { EXxS, XM }, 0 },
10219 /* VEX_W_0F11_P_3 */
10220 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10223 /* VEX_W_0F12_P_0_M_0 */
10224 { "vmovlps", { XM, Vex128, EXq }, 0 },
10227 /* VEX_W_0F12_P_0_M_1 */
10228 { "vmovhlps", { XM, Vex128, EXq }, 0 },
10231 /* VEX_W_0F12_P_1 */
10232 { "vmovsldup", { XM, EXx }, 0 },
10235 /* VEX_W_0F12_P_2 */
10236 { "vmovlpd", { XM, Vex128, EXq }, 0 },
10239 /* VEX_W_0F12_P_3 */
10240 { "vmovddup", { XM, EXymmq }, 0 },
10243 /* VEX_W_0F13_M_0 */
10244 { "vmovlpX", { EXq, XM }, 0 },
10248 { "vunpcklpX", { XM, Vex, EXx }, 0 },
10252 { "vunpckhpX", { XM, Vex, EXx }, 0 },
10255 /* VEX_W_0F16_P_0_M_0 */
10256 { "vmovhps", { XM, Vex128, EXq }, 0 },
10259 /* VEX_W_0F16_P_0_M_1 */
10260 { "vmovlhps", { XM, Vex128, EXq }, 0 },
10263 /* VEX_W_0F16_P_1 */
10264 { "vmovshdup", { XM, EXx }, 0 },
10267 /* VEX_W_0F16_P_2 */
10268 { "vmovhpd", { XM, Vex128, EXq }, 0 },
10271 /* VEX_W_0F17_M_0 */
10272 { "vmovhpX", { EXq, XM }, 0 },
10276 { "vmovapX", { XM, EXx }, 0 },
10280 { "vmovapX", { EXxS, XM }, 0 },
10283 /* VEX_W_0F2B_M_0 */
10284 { "vmovntpX", { Mx, XM }, 0 },
10287 /* VEX_W_0F2E_P_0 */
10288 { "vucomiss", { XMScalar, EXdScalar }, 0 },
10291 /* VEX_W_0F2E_P_2 */
10292 { "vucomisd", { XMScalar, EXqScalar }, 0 },
10295 /* VEX_W_0F2F_P_0 */
10296 { "vcomiss", { XMScalar, EXdScalar }, 0 },
10299 /* VEX_W_0F2F_P_2 */
10300 { "vcomisd", { XMScalar, EXqScalar }, 0 },
10303 /* VEX_W_0F41_P_0_LEN_1 */
10304 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10305 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10308 /* VEX_W_0F41_P_2_LEN_1 */
10309 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10310 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10313 /* VEX_W_0F42_P_0_LEN_1 */
10314 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10315 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10318 /* VEX_W_0F42_P_2_LEN_1 */
10319 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10320 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10323 /* VEX_W_0F44_P_0_LEN_0 */
10324 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10325 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10328 /* VEX_W_0F44_P_2_LEN_0 */
10329 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10330 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10333 /* VEX_W_0F45_P_0_LEN_1 */
10334 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10335 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10338 /* VEX_W_0F45_P_2_LEN_1 */
10339 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10340 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10343 /* VEX_W_0F46_P_0_LEN_1 */
10344 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10345 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10348 /* VEX_W_0F46_P_2_LEN_1 */
10349 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10350 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10353 /* VEX_W_0F47_P_0_LEN_1 */
10354 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10355 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10358 /* VEX_W_0F47_P_2_LEN_1 */
10359 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10360 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10363 /* VEX_W_0F4A_P_0_LEN_1 */
10364 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10365 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10368 /* VEX_W_0F4A_P_2_LEN_1 */
10369 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10370 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10373 /* VEX_W_0F4B_P_0_LEN_1 */
10374 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10375 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10378 /* VEX_W_0F4B_P_2_LEN_1 */
10379 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10382 /* VEX_W_0F50_M_0 */
10383 { "vmovmskpX", { Gdq, XS }, 0 },
10386 /* VEX_W_0F51_P_0 */
10387 { "vsqrtps", { XM, EXx }, 0 },
10390 /* VEX_W_0F51_P_1 */
10391 { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10394 /* VEX_W_0F51_P_2 */
10395 { "vsqrtpd", { XM, EXx }, 0 },
10398 /* VEX_W_0F51_P_3 */
10399 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10402 /* VEX_W_0F52_P_0 */
10403 { "vrsqrtps", { XM, EXx }, 0 },
10406 /* VEX_W_0F52_P_1 */
10407 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10410 /* VEX_W_0F53_P_0 */
10411 { "vrcpps", { XM, EXx }, 0 },
10414 /* VEX_W_0F53_P_1 */
10415 { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
10418 /* VEX_W_0F58_P_0 */
10419 { "vaddps", { XM, Vex, EXx }, 0 },
10422 /* VEX_W_0F58_P_1 */
10423 { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
10426 /* VEX_W_0F58_P_2 */
10427 { "vaddpd", { XM, Vex, EXx }, 0 },
10430 /* VEX_W_0F58_P_3 */
10431 { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10434 /* VEX_W_0F59_P_0 */
10435 { "vmulps", { XM, Vex, EXx }, 0 },
10438 /* VEX_W_0F59_P_1 */
10439 { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
10442 /* VEX_W_0F59_P_2 */
10443 { "vmulpd", { XM, Vex, EXx }, 0 },
10446 /* VEX_W_0F59_P_3 */
10447 { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10450 /* VEX_W_0F5A_P_0 */
10451 { "vcvtps2pd", { XM, EXxmmq }, 0 },
10454 /* VEX_W_0F5A_P_1 */
10455 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
10458 /* VEX_W_0F5A_P_3 */
10459 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
10462 /* VEX_W_0F5B_P_0 */
10463 { "vcvtdq2ps", { XM, EXx }, 0 },
10466 /* VEX_W_0F5B_P_1 */
10467 { "vcvttps2dq", { XM, EXx }, 0 },
10470 /* VEX_W_0F5B_P_2 */
10471 { "vcvtps2dq", { XM, EXx }, 0 },
10474 /* VEX_W_0F5C_P_0 */
10475 { "vsubps", { XM, Vex, EXx }, 0 },
10478 /* VEX_W_0F5C_P_1 */
10479 { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
10482 /* VEX_W_0F5C_P_2 */
10483 { "vsubpd", { XM, Vex, EXx }, 0 },
10486 /* VEX_W_0F5C_P_3 */
10487 { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10490 /* VEX_W_0F5D_P_0 */
10491 { "vminps", { XM, Vex, EXx }, 0 },
10494 /* VEX_W_0F5D_P_1 */
10495 { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
10498 /* VEX_W_0F5D_P_2 */
10499 { "vminpd", { XM, Vex, EXx }, 0 },
10502 /* VEX_W_0F5D_P_3 */
10503 { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10506 /* VEX_W_0F5E_P_0 */
10507 { "vdivps", { XM, Vex, EXx }, 0 },
10510 /* VEX_W_0F5E_P_1 */
10511 { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
10514 /* VEX_W_0F5E_P_2 */
10515 { "vdivpd", { XM, Vex, EXx }, 0 },
10518 /* VEX_W_0F5E_P_3 */
10519 { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10522 /* VEX_W_0F5F_P_0 */
10523 { "vmaxps", { XM, Vex, EXx }, 0 },
10526 /* VEX_W_0F5F_P_1 */
10527 { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
10530 /* VEX_W_0F5F_P_2 */
10531 { "vmaxpd", { XM, Vex, EXx }, 0 },
10534 /* VEX_W_0F5F_P_3 */
10535 { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10538 /* VEX_W_0F60_P_2 */
10539 { "vpunpcklbw", { XM, Vex, EXx }, 0 },
10542 /* VEX_W_0F61_P_2 */
10543 { "vpunpcklwd", { XM, Vex, EXx }, 0 },
10546 /* VEX_W_0F62_P_2 */
10547 { "vpunpckldq", { XM, Vex, EXx }, 0 },
10550 /* VEX_W_0F63_P_2 */
10551 { "vpacksswb", { XM, Vex, EXx }, 0 },
10554 /* VEX_W_0F64_P_2 */
10555 { "vpcmpgtb", { XM, Vex, EXx }, 0 },
10558 /* VEX_W_0F65_P_2 */
10559 { "vpcmpgtw", { XM, Vex, EXx }, 0 },
10562 /* VEX_W_0F66_P_2 */
10563 { "vpcmpgtd", { XM, Vex, EXx }, 0 },
10566 /* VEX_W_0F67_P_2 */
10567 { "vpackuswb", { XM, Vex, EXx }, 0 },
10570 /* VEX_W_0F68_P_2 */
10571 { "vpunpckhbw", { XM, Vex, EXx }, 0 },
10574 /* VEX_W_0F69_P_2 */
10575 { "vpunpckhwd", { XM, Vex, EXx }, 0 },
10578 /* VEX_W_0F6A_P_2 */
10579 { "vpunpckhdq", { XM, Vex, EXx }, 0 },
10582 /* VEX_W_0F6B_P_2 */
10583 { "vpackssdw", { XM, Vex, EXx }, 0 },
10586 /* VEX_W_0F6C_P_2 */
10587 { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
10590 /* VEX_W_0F6D_P_2 */
10591 { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
10594 /* VEX_W_0F6F_P_1 */
10595 { "vmovdqu", { XM, EXx }, 0 },
10598 /* VEX_W_0F6F_P_2 */
10599 { "vmovdqa", { XM, EXx }, 0 },
10602 /* VEX_W_0F70_P_1 */
10603 { "vpshufhw", { XM, EXx, Ib }, 0 },
10606 /* VEX_W_0F70_P_2 */
10607 { "vpshufd", { XM, EXx, Ib }, 0 },
10610 /* VEX_W_0F70_P_3 */
10611 { "vpshuflw", { XM, EXx, Ib }, 0 },
10614 /* VEX_W_0F71_R_2_P_2 */
10615 { "vpsrlw", { Vex, XS, Ib }, 0 },
10618 /* VEX_W_0F71_R_4_P_2 */
10619 { "vpsraw", { Vex, XS, Ib }, 0 },
10622 /* VEX_W_0F71_R_6_P_2 */
10623 { "vpsllw", { Vex, XS, Ib }, 0 },
10626 /* VEX_W_0F72_R_2_P_2 */
10627 { "vpsrld", { Vex, XS, Ib }, 0 },
10630 /* VEX_W_0F72_R_4_P_2 */
10631 { "vpsrad", { Vex, XS, Ib }, 0 },
10634 /* VEX_W_0F72_R_6_P_2 */
10635 { "vpslld", { Vex, XS, Ib }, 0 },
10638 /* VEX_W_0F73_R_2_P_2 */
10639 { "vpsrlq", { Vex, XS, Ib }, 0 },
10642 /* VEX_W_0F73_R_3_P_2 */
10643 { "vpsrldq", { Vex, XS, Ib }, 0 },
10646 /* VEX_W_0F73_R_6_P_2 */
10647 { "vpsllq", { Vex, XS, Ib }, 0 },
10650 /* VEX_W_0F73_R_7_P_2 */
10651 { "vpslldq", { Vex, XS, Ib }, 0 },
10654 /* VEX_W_0F74_P_2 */
10655 { "vpcmpeqb", { XM, Vex, EXx }, 0 },
10658 /* VEX_W_0F75_P_2 */
10659 { "vpcmpeqw", { XM, Vex, EXx }, 0 },
10662 /* VEX_W_0F76_P_2 */
10663 { "vpcmpeqd", { XM, Vex, EXx }, 0 },
10666 /* VEX_W_0F77_P_0 */
10667 { "", { VZERO }, 0 },
10670 /* VEX_W_0F7C_P_2 */
10671 { "vhaddpd", { XM, Vex, EXx }, 0 },
10674 /* VEX_W_0F7C_P_3 */
10675 { "vhaddps", { XM, Vex, EXx }, 0 },
10678 /* VEX_W_0F7D_P_2 */
10679 { "vhsubpd", { XM, Vex, EXx }, 0 },
10682 /* VEX_W_0F7D_P_3 */
10683 { "vhsubps", { XM, Vex, EXx }, 0 },
10686 /* VEX_W_0F7E_P_1 */
10687 { "vmovq", { XMScalar, EXqScalar }, 0 },
10690 /* VEX_W_0F7F_P_1 */
10691 { "vmovdqu", { EXxS, XM }, 0 },
10694 /* VEX_W_0F7F_P_2 */
10695 { "vmovdqa", { EXxS, XM }, 0 },
10698 /* VEX_W_0F90_P_0_LEN_0 */
10699 { "kmovw", { MaskG, MaskE }, 0 },
10700 { "kmovq", { MaskG, MaskE }, 0 },
10703 /* VEX_W_0F90_P_2_LEN_0 */
10704 { "kmovb", { MaskG, MaskBDE }, 0 },
10705 { "kmovd", { MaskG, MaskBDE }, 0 },
10708 /* VEX_W_0F91_P_0_LEN_0 */
10709 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10710 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10713 /* VEX_W_0F91_P_2_LEN_0 */
10714 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10715 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10718 /* VEX_W_0F92_P_0_LEN_0 */
10719 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10722 /* VEX_W_0F92_P_2_LEN_0 */
10723 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10726 /* VEX_W_0F92_P_3_LEN_0 */
10727 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10728 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10731 /* VEX_W_0F93_P_0_LEN_0 */
10732 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10735 /* VEX_W_0F93_P_2_LEN_0 */
10736 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10739 /* VEX_W_0F93_P_3_LEN_0 */
10740 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10741 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10744 /* VEX_W_0F98_P_0_LEN_0 */
10745 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10746 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10749 /* VEX_W_0F98_P_2_LEN_0 */
10750 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10751 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10754 /* VEX_W_0F99_P_0_LEN_0 */
10755 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10756 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10759 /* VEX_W_0F99_P_2_LEN_0 */
10760 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10761 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10764 /* VEX_W_0FAE_R_2_M_0 */
10765 { "vldmxcsr", { Md }, 0 },
10768 /* VEX_W_0FAE_R_3_M_0 */
10769 { "vstmxcsr", { Md }, 0 },
10772 /* VEX_W_0FC2_P_0 */
10773 { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
10776 /* VEX_W_0FC2_P_1 */
10777 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10780 /* VEX_W_0FC2_P_2 */
10781 { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
10784 /* VEX_W_0FC2_P_3 */
10785 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10788 /* VEX_W_0FC4_P_2 */
10789 { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
10792 /* VEX_W_0FC5_P_2 */
10793 { "vpextrw", { Gdq, XS, Ib }, 0 },
10796 /* VEX_W_0FD0_P_2 */
10797 { "vaddsubpd", { XM, Vex, EXx }, 0 },
10800 /* VEX_W_0FD0_P_3 */
10801 { "vaddsubps", { XM, Vex, EXx }, 0 },
10804 /* VEX_W_0FD1_P_2 */
10805 { "vpsrlw", { XM, Vex, EXxmm }, 0 },
10808 /* VEX_W_0FD2_P_2 */
10809 { "vpsrld", { XM, Vex, EXxmm }, 0 },
10812 /* VEX_W_0FD3_P_2 */
10813 { "vpsrlq", { XM, Vex, EXxmm }, 0 },
10816 /* VEX_W_0FD4_P_2 */
10817 { "vpaddq", { XM, Vex, EXx }, 0 },
10820 /* VEX_W_0FD5_P_2 */
10821 { "vpmullw", { XM, Vex, EXx }, 0 },
10824 /* VEX_W_0FD6_P_2 */
10825 { "vmovq", { EXqScalarS, XMScalar }, 0 },
10828 /* VEX_W_0FD7_P_2_M_1 */
10829 { "vpmovmskb", { Gdq, XS }, 0 },
10832 /* VEX_W_0FD8_P_2 */
10833 { "vpsubusb", { XM, Vex, EXx }, 0 },
10836 /* VEX_W_0FD9_P_2 */
10837 { "vpsubusw", { XM, Vex, EXx }, 0 },
10840 /* VEX_W_0FDA_P_2 */
10841 { "vpminub", { XM, Vex, EXx }, 0 },
10844 /* VEX_W_0FDB_P_2 */
10845 { "vpand", { XM, Vex, EXx }, 0 },
10848 /* VEX_W_0FDC_P_2 */
10849 { "vpaddusb", { XM, Vex, EXx }, 0 },
10852 /* VEX_W_0FDD_P_2 */
10853 { "vpaddusw", { XM, Vex, EXx }, 0 },
10856 /* VEX_W_0FDE_P_2 */
10857 { "vpmaxub", { XM, Vex, EXx }, 0 },
10860 /* VEX_W_0FDF_P_2 */
10861 { "vpandn", { XM, Vex, EXx }, 0 },
10864 /* VEX_W_0FE0_P_2 */
10865 { "vpavgb", { XM, Vex, EXx }, 0 },
10868 /* VEX_W_0FE1_P_2 */
10869 { "vpsraw", { XM, Vex, EXxmm }, 0 },
10872 /* VEX_W_0FE2_P_2 */
10873 { "vpsrad", { XM, Vex, EXxmm }, 0 },
10876 /* VEX_W_0FE3_P_2 */
10877 { "vpavgw", { XM, Vex, EXx }, 0 },
10880 /* VEX_W_0FE4_P_2 */
10881 { "vpmulhuw", { XM, Vex, EXx }, 0 },
10884 /* VEX_W_0FE5_P_2 */
10885 { "vpmulhw", { XM, Vex, EXx }, 0 },
10888 /* VEX_W_0FE6_P_1 */
10889 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
10892 /* VEX_W_0FE6_P_2 */
10893 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
10896 /* VEX_W_0FE6_P_3 */
10897 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
10900 /* VEX_W_0FE7_P_2_M_0 */
10901 { "vmovntdq", { Mx, XM }, 0 },
10904 /* VEX_W_0FE8_P_2 */
10905 { "vpsubsb", { XM, Vex, EXx }, 0 },
10908 /* VEX_W_0FE9_P_2 */
10909 { "vpsubsw", { XM, Vex, EXx }, 0 },
10912 /* VEX_W_0FEA_P_2 */
10913 { "vpminsw", { XM, Vex, EXx }, 0 },
10916 /* VEX_W_0FEB_P_2 */
10917 { "vpor", { XM, Vex, EXx }, 0 },
10920 /* VEX_W_0FEC_P_2 */
10921 { "vpaddsb", { XM, Vex, EXx }, 0 },
10924 /* VEX_W_0FED_P_2 */
10925 { "vpaddsw", { XM, Vex, EXx }, 0 },
10928 /* VEX_W_0FEE_P_2 */
10929 { "vpmaxsw", { XM, Vex, EXx }, 0 },
10932 /* VEX_W_0FEF_P_2 */
10933 { "vpxor", { XM, Vex, EXx }, 0 },
10936 /* VEX_W_0FF0_P_3_M_0 */
10937 { "vlddqu", { XM, M }, 0 },
10940 /* VEX_W_0FF1_P_2 */
10941 { "vpsllw", { XM, Vex, EXxmm }, 0 },
10944 /* VEX_W_0FF2_P_2 */
10945 { "vpslld", { XM, Vex, EXxmm }, 0 },
10948 /* VEX_W_0FF3_P_2 */
10949 { "vpsllq", { XM, Vex, EXxmm }, 0 },
10952 /* VEX_W_0FF4_P_2 */
10953 { "vpmuludq", { XM, Vex, EXx }, 0 },
10956 /* VEX_W_0FF5_P_2 */
10957 { "vpmaddwd", { XM, Vex, EXx }, 0 },
10960 /* VEX_W_0FF6_P_2 */
10961 { "vpsadbw", { XM, Vex, EXx }, 0 },
10964 /* VEX_W_0FF7_P_2 */
10965 { "vmaskmovdqu", { XM, XS }, 0 },
10968 /* VEX_W_0FF8_P_2 */
10969 { "vpsubb", { XM, Vex, EXx }, 0 },
10972 /* VEX_W_0FF9_P_2 */
10973 { "vpsubw", { XM, Vex, EXx }, 0 },
10976 /* VEX_W_0FFA_P_2 */
10977 { "vpsubd", { XM, Vex, EXx }, 0 },
10980 /* VEX_W_0FFB_P_2 */
10981 { "vpsubq", { XM, Vex, EXx }, 0 },
10984 /* VEX_W_0FFC_P_2 */
10985 { "vpaddb", { XM, Vex, EXx }, 0 },
10988 /* VEX_W_0FFD_P_2 */
10989 { "vpaddw", { XM, Vex, EXx }, 0 },
10992 /* VEX_W_0FFE_P_2 */
10993 { "vpaddd", { XM, Vex, EXx }, 0 },
10996 /* VEX_W_0F3800_P_2 */
10997 { "vpshufb", { XM, Vex, EXx }, 0 },
11000 /* VEX_W_0F3801_P_2 */
11001 { "vphaddw", { XM, Vex, EXx }, 0 },
11004 /* VEX_W_0F3802_P_2 */
11005 { "vphaddd", { XM, Vex, EXx }, 0 },
11008 /* VEX_W_0F3803_P_2 */
11009 { "vphaddsw", { XM, Vex, EXx }, 0 },
11012 /* VEX_W_0F3804_P_2 */
11013 { "vpmaddubsw", { XM, Vex, EXx }, 0 },
11016 /* VEX_W_0F3805_P_2 */
11017 { "vphsubw", { XM, Vex, EXx }, 0 },
11020 /* VEX_W_0F3806_P_2 */
11021 { "vphsubd", { XM, Vex, EXx }, 0 },
11024 /* VEX_W_0F3807_P_2 */
11025 { "vphsubsw", { XM, Vex, EXx }, 0 },
11028 /* VEX_W_0F3808_P_2 */
11029 { "vpsignb", { XM, Vex, EXx }, 0 },
11032 /* VEX_W_0F3809_P_2 */
11033 { "vpsignw", { XM, Vex, EXx }, 0 },
11036 /* VEX_W_0F380A_P_2 */
11037 { "vpsignd", { XM, Vex, EXx }, 0 },
11040 /* VEX_W_0F380B_P_2 */
11041 { "vpmulhrsw", { XM, Vex, EXx }, 0 },
11044 /* VEX_W_0F380C_P_2 */
11045 { "vpermilps", { XM, Vex, EXx }, 0 },
11048 /* VEX_W_0F380D_P_2 */
11049 { "vpermilpd", { XM, Vex, EXx }, 0 },
11052 /* VEX_W_0F380E_P_2 */
11053 { "vtestps", { XM, EXx }, 0 },
11056 /* VEX_W_0F380F_P_2 */
11057 { "vtestpd", { XM, EXx }, 0 },
11060 /* VEX_W_0F3816_P_2 */
11061 { "vpermps", { XM, Vex, EXx }, 0 },
11064 /* VEX_W_0F3817_P_2 */
11065 { "vptest", { XM, EXx }, 0 },
11068 /* VEX_W_0F3818_P_2 */
11069 { "vbroadcastss", { XM, EXxmm_md }, 0 },
11072 /* VEX_W_0F3819_P_2 */
11073 { "vbroadcastsd", { XM, EXxmm_mq }, 0 },
11076 /* VEX_W_0F381A_P_2_M_0 */
11077 { "vbroadcastf128", { XM, Mxmm }, 0 },
11080 /* VEX_W_0F381C_P_2 */
11081 { "vpabsb", { XM, EXx }, 0 },
11084 /* VEX_W_0F381D_P_2 */
11085 { "vpabsw", { XM, EXx }, 0 },
11088 /* VEX_W_0F381E_P_2 */
11089 { "vpabsd", { XM, EXx }, 0 },
11092 /* VEX_W_0F3820_P_2 */
11093 { "vpmovsxbw", { XM, EXxmmq }, 0 },
11096 /* VEX_W_0F3821_P_2 */
11097 { "vpmovsxbd", { XM, EXxmmqd }, 0 },
11100 /* VEX_W_0F3822_P_2 */
11101 { "vpmovsxbq", { XM, EXxmmdw }, 0 },
11104 /* VEX_W_0F3823_P_2 */
11105 { "vpmovsxwd", { XM, EXxmmq }, 0 },
11108 /* VEX_W_0F3824_P_2 */
11109 { "vpmovsxwq", { XM, EXxmmqd }, 0 },
11112 /* VEX_W_0F3825_P_2 */
11113 { "vpmovsxdq", { XM, EXxmmq }, 0 },
11116 /* VEX_W_0F3828_P_2 */
11117 { "vpmuldq", { XM, Vex, EXx }, 0 },
11120 /* VEX_W_0F3829_P_2 */
11121 { "vpcmpeqq", { XM, Vex, EXx }, 0 },
11124 /* VEX_W_0F382A_P_2_M_0 */
11125 { "vmovntdqa", { XM, Mx }, 0 },
11128 /* VEX_W_0F382B_P_2 */
11129 { "vpackusdw", { XM, Vex, EXx }, 0 },
11132 /* VEX_W_0F382C_P_2_M_0 */
11133 { "vmaskmovps", { XM, Vex, Mx }, 0 },
11136 /* VEX_W_0F382D_P_2_M_0 */
11137 { "vmaskmovpd", { XM, Vex, Mx }, 0 },
11140 /* VEX_W_0F382E_P_2_M_0 */
11141 { "vmaskmovps", { Mx, Vex, XM }, 0 },
11144 /* VEX_W_0F382F_P_2_M_0 */
11145 { "vmaskmovpd", { Mx, Vex, XM }, 0 },
11148 /* VEX_W_0F3830_P_2 */
11149 { "vpmovzxbw", { XM, EXxmmq }, 0 },
11152 /* VEX_W_0F3831_P_2 */
11153 { "vpmovzxbd", { XM, EXxmmqd }, 0 },
11156 /* VEX_W_0F3832_P_2 */
11157 { "vpmovzxbq", { XM, EXxmmdw }, 0 },
11160 /* VEX_W_0F3833_P_2 */
11161 { "vpmovzxwd", { XM, EXxmmq }, 0 },
11164 /* VEX_W_0F3834_P_2 */
11165 { "vpmovzxwq", { XM, EXxmmqd }, 0 },
11168 /* VEX_W_0F3835_P_2 */
11169 { "vpmovzxdq", { XM, EXxmmq }, 0 },
11172 /* VEX_W_0F3836_P_2 */
11173 { "vpermd", { XM, Vex, EXx }, 0 },
11176 /* VEX_W_0F3837_P_2 */
11177 { "vpcmpgtq", { XM, Vex, EXx }, 0 },
11180 /* VEX_W_0F3838_P_2 */
11181 { "vpminsb", { XM, Vex, EXx }, 0 },
11184 /* VEX_W_0F3839_P_2 */
11185 { "vpminsd", { XM, Vex, EXx }, 0 },
11188 /* VEX_W_0F383A_P_2 */
11189 { "vpminuw", { XM, Vex, EXx }, 0 },
11192 /* VEX_W_0F383B_P_2 */
11193 { "vpminud", { XM, Vex, EXx }, 0 },
11196 /* VEX_W_0F383C_P_2 */
11197 { "vpmaxsb", { XM, Vex, EXx }, 0 },
11200 /* VEX_W_0F383D_P_2 */
11201 { "vpmaxsd", { XM, Vex, EXx }, 0 },
11204 /* VEX_W_0F383E_P_2 */
11205 { "vpmaxuw", { XM, Vex, EXx }, 0 },
11208 /* VEX_W_0F383F_P_2 */
11209 { "vpmaxud", { XM, Vex, EXx }, 0 },
11212 /* VEX_W_0F3840_P_2 */
11213 { "vpmulld", { XM, Vex, EXx }, 0 },
11216 /* VEX_W_0F3841_P_2 */
11217 { "vphminposuw", { XM, EXx }, 0 },
11220 /* VEX_W_0F3846_P_2 */
11221 { "vpsravd", { XM, Vex, EXx }, 0 },
11224 /* VEX_W_0F3858_P_2 */
11225 { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11228 /* VEX_W_0F3859_P_2 */
11229 { "vpbroadcastq", { XM, EXxmm_mq }, 0 },
11232 /* VEX_W_0F385A_P_2_M_0 */
11233 { "vbroadcasti128", { XM, Mxmm }, 0 },
11236 /* VEX_W_0F3878_P_2 */
11237 { "vpbroadcastb", { XM, EXxmm_mb }, 0 },
11240 /* VEX_W_0F3879_P_2 */
11241 { "vpbroadcastw", { XM, EXxmm_mw }, 0 },
11244 /* VEX_W_0F38DB_P_2 */
11245 { "vaesimc", { XM, EXx }, 0 },
11248 /* VEX_W_0F38DC_P_2 */
11249 { "vaesenc", { XM, Vex128, EXx }, 0 },
11252 /* VEX_W_0F38DD_P_2 */
11253 { "vaesenclast", { XM, Vex128, EXx }, 0 },
11256 /* VEX_W_0F38DE_P_2 */
11257 { "vaesdec", { XM, Vex128, EXx }, 0 },
11260 /* VEX_W_0F38DF_P_2 */
11261 { "vaesdeclast", { XM, Vex128, EXx }, 0 },
11264 /* VEX_W_0F3A00_P_2 */
11266 { "vpermq", { XM, EXx, Ib }, 0 },
11269 /* VEX_W_0F3A01_P_2 */
11271 { "vpermpd", { XM, EXx, Ib }, 0 },
11274 /* VEX_W_0F3A02_P_2 */
11275 { "vpblendd", { XM, Vex, EXx, Ib }, 0 },
11278 /* VEX_W_0F3A04_P_2 */
11279 { "vpermilps", { XM, EXx, Ib }, 0 },
11282 /* VEX_W_0F3A05_P_2 */
11283 { "vpermilpd", { XM, EXx, Ib }, 0 },
11286 /* VEX_W_0F3A06_P_2 */
11287 { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 },
11290 /* VEX_W_0F3A08_P_2 */
11291 { "vroundps", { XM, EXx, Ib }, 0 },
11294 /* VEX_W_0F3A09_P_2 */
11295 { "vroundpd", { XM, EXx, Ib }, 0 },
11298 /* VEX_W_0F3A0A_P_2 */
11299 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11302 /* VEX_W_0F3A0B_P_2 */
11303 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11306 /* VEX_W_0F3A0C_P_2 */
11307 { "vblendps", { XM, Vex, EXx, Ib }, 0 },
11310 /* VEX_W_0F3A0D_P_2 */
11311 { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
11314 /* VEX_W_0F3A0E_P_2 */
11315 { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
11318 /* VEX_W_0F3A0F_P_2 */
11319 { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
11322 /* VEX_W_0F3A14_P_2 */
11323 { "vpextrb", { Edqb, XM, Ib }, 0 },
11326 /* VEX_W_0F3A15_P_2 */
11327 { "vpextrw", { Edqw, XM, Ib }, 0 },
11330 /* VEX_W_0F3A18_P_2 */
11331 { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 },
11334 /* VEX_W_0F3A19_P_2 */
11335 { "vextractf128", { EXxmm, XM, Ib }, 0 },
11338 /* VEX_W_0F3A20_P_2 */
11339 { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
11342 /* VEX_W_0F3A21_P_2 */
11343 { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
11346 /* VEX_W_0F3A30_P_2_LEN_0 */
11347 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11348 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11351 /* VEX_W_0F3A31_P_2_LEN_0 */
11352 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11353 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11356 /* VEX_W_0F3A32_P_2_LEN_0 */
11357 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11358 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11361 /* VEX_W_0F3A33_P_2_LEN_0 */
11362 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11363 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11366 /* VEX_W_0F3A38_P_2 */
11367 { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 },
11370 /* VEX_W_0F3A39_P_2 */
11371 { "vextracti128", { EXxmm, XM, Ib }, 0 },
11374 /* VEX_W_0F3A40_P_2 */
11375 { "vdpps", { XM, Vex, EXx, Ib }, 0 },
11378 /* VEX_W_0F3A41_P_2 */
11379 { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
11382 /* VEX_W_0F3A42_P_2 */
11383 { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
11386 /* VEX_W_0F3A44_P_2 */
11387 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL }, 0 },
11390 /* VEX_W_0F3A46_P_2 */
11391 { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
11394 /* VEX_W_0F3A48_P_2 */
11395 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11396 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11399 /* VEX_W_0F3A49_P_2 */
11400 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11401 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11404 /* VEX_W_0F3A4A_P_2 */
11405 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 },
11408 /* VEX_W_0F3A4B_P_2 */
11409 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 },
11412 /* VEX_W_0F3A4C_P_2 */
11413 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
11416 /* VEX_W_0F3A62_P_2 */
11417 { "vpcmpistrm", { XM, EXx, Ib }, 0 },
11420 /* VEX_W_0F3A63_P_2 */
11421 { "vpcmpistri", { XM, EXx, Ib }, 0 },
11424 /* VEX_W_0F3ADF_P_2 */
11425 { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11427 #define NEED_VEX_W_TABLE
11428 #include "i386-dis-evex.h"
11429 #undef NEED_VEX_W_TABLE
11432 static const struct dis386 mod_table[][2] = {
11435 { "leaS", { Gv, M }, 0 },
11440 { RM_TABLE (RM_C6_REG_7) },
11445 { RM_TABLE (RM_C7_REG_7) },
11449 { "Jcall^", { indirEp }, 0 },
11453 { "Jjmp^", { indirEp }, 0 },
11456 /* MOD_0F01_REG_0 */
11457 { X86_64_TABLE (X86_64_0F01_REG_0) },
11458 { RM_TABLE (RM_0F01_REG_0) },
11461 /* MOD_0F01_REG_1 */
11462 { X86_64_TABLE (X86_64_0F01_REG_1) },
11463 { RM_TABLE (RM_0F01_REG_1) },
11466 /* MOD_0F01_REG_2 */
11467 { X86_64_TABLE (X86_64_0F01_REG_2) },
11468 { RM_TABLE (RM_0F01_REG_2) },
11471 /* MOD_0F01_REG_3 */
11472 { X86_64_TABLE (X86_64_0F01_REG_3) },
11473 { RM_TABLE (RM_0F01_REG_3) },
11476 /* MOD_0F01_REG_5 */
11477 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
11478 { RM_TABLE (RM_0F01_REG_5) },
11481 /* MOD_0F01_REG_7 */
11482 { "invlpg", { Mb }, 0 },
11483 { RM_TABLE (RM_0F01_REG_7) },
11486 /* MOD_0F12_PREFIX_0 */
11487 { "movlps", { XM, EXq }, PREFIX_OPCODE },
11488 { "movhlps", { XM, EXq }, PREFIX_OPCODE },
11492 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
11495 /* MOD_0F16_PREFIX_0 */
11496 { "movhps", { XM, EXq }, 0 },
11497 { "movlhps", { XM, EXq }, 0 },
11501 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
11504 /* MOD_0F18_REG_0 */
11505 { "prefetchnta", { Mb }, 0 },
11508 /* MOD_0F18_REG_1 */
11509 { "prefetcht0", { Mb }, 0 },
11512 /* MOD_0F18_REG_2 */
11513 { "prefetcht1", { Mb }, 0 },
11516 /* MOD_0F18_REG_3 */
11517 { "prefetcht2", { Mb }, 0 },
11520 /* MOD_0F18_REG_4 */
11521 { "nop/reserved", { Mb }, 0 },
11524 /* MOD_0F18_REG_5 */
11525 { "nop/reserved", { Mb }, 0 },
11528 /* MOD_0F18_REG_6 */
11529 { "nop/reserved", { Mb }, 0 },
11532 /* MOD_0F18_REG_7 */
11533 { "nop/reserved", { Mb }, 0 },
11536 /* MOD_0F1A_PREFIX_0 */
11537 { "bndldx", { Gbnd, Ev_bnd }, 0 },
11538 { "nopQ", { Ev }, 0 },
11541 /* MOD_0F1B_PREFIX_0 */
11542 { "bndstx", { Ev_bnd, Gbnd }, 0 },
11543 { "nopQ", { Ev }, 0 },
11546 /* MOD_0F1B_PREFIX_1 */
11547 { "bndmk", { Gbnd, Ev_bnd }, 0 },
11548 { "nopQ", { Ev }, 0 },
11551 /* MOD_0F1E_PREFIX_1 */
11552 { "nopQ", { Ev }, 0 },
11553 { REG_TABLE (REG_0F1E_MOD_3) },
11558 { "movL", { Rd, Td }, 0 },
11563 { "movL", { Td, Rd }, 0 },
11566 /* MOD_0F2B_PREFIX_0 */
11567 {"movntps", { Mx, XM }, PREFIX_OPCODE },
11570 /* MOD_0F2B_PREFIX_1 */
11571 {"movntss", { Md, XM }, PREFIX_OPCODE },
11574 /* MOD_0F2B_PREFIX_2 */
11575 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
11578 /* MOD_0F2B_PREFIX_3 */
11579 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
11584 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
11587 /* MOD_0F71_REG_2 */
11589 { "psrlw", { MS, Ib }, 0 },
11592 /* MOD_0F71_REG_4 */
11594 { "psraw", { MS, Ib }, 0 },
11597 /* MOD_0F71_REG_6 */
11599 { "psllw", { MS, Ib }, 0 },
11602 /* MOD_0F72_REG_2 */
11604 { "psrld", { MS, Ib }, 0 },
11607 /* MOD_0F72_REG_4 */
11609 { "psrad", { MS, Ib }, 0 },
11612 /* MOD_0F72_REG_6 */
11614 { "pslld", { MS, Ib }, 0 },
11617 /* MOD_0F73_REG_2 */
11619 { "psrlq", { MS, Ib }, 0 },
11622 /* MOD_0F73_REG_3 */
11624 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11627 /* MOD_0F73_REG_6 */
11629 { "psllq", { MS, Ib }, 0 },
11632 /* MOD_0F73_REG_7 */
11634 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11637 /* MOD_0FAE_REG_0 */
11638 { "fxsave", { FXSAVE }, 0 },
11639 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11642 /* MOD_0FAE_REG_1 */
11643 { "fxrstor", { FXSAVE }, 0 },
11644 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11647 /* MOD_0FAE_REG_2 */
11648 { "ldmxcsr", { Md }, 0 },
11649 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11652 /* MOD_0FAE_REG_3 */
11653 { "stmxcsr", { Md }, 0 },
11654 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11657 /* MOD_0FAE_REG_4 */
11658 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11659 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11662 /* MOD_0FAE_REG_5 */
11663 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
11664 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
11667 /* MOD_0FAE_REG_6 */
11668 { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11669 { RM_TABLE (RM_0FAE_REG_6) },
11672 /* MOD_0FAE_REG_7 */
11673 { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11674 { RM_TABLE (RM_0FAE_REG_7) },
11678 { "lssS", { Gv, Mp }, 0 },
11682 { "lfsS", { Gv, Mp }, 0 },
11686 { "lgsS", { Gv, Mp }, 0 },
11690 { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11693 /* MOD_0FC7_REG_3 */
11694 { "xrstors", { FXSAVE }, 0 },
11697 /* MOD_0FC7_REG_4 */
11698 { "xsavec", { FXSAVE }, 0 },
11701 /* MOD_0FC7_REG_5 */
11702 { "xsaves", { FXSAVE }, 0 },
11705 /* MOD_0FC7_REG_6 */
11706 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11707 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11710 /* MOD_0FC7_REG_7 */
11711 { "vmptrst", { Mq }, 0 },
11712 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11717 { "pmovmskb", { Gdq, MS }, 0 },
11720 /* MOD_0FE7_PREFIX_2 */
11721 { "movntdq", { Mx, XM }, 0 },
11724 /* MOD_0FF0_PREFIX_3 */
11725 { "lddqu", { XM, M }, 0 },
11728 /* MOD_0F382A_PREFIX_2 */
11729 { "movntdqa", { XM, Mx }, 0 },
11732 /* MOD_0F38F5_PREFIX_2 */
11733 { "wrussK", { M, Gdq }, PREFIX_OPCODE },
11736 /* MOD_0F38F6_PREFIX_0 */
11737 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
11741 { "bound{S|}", { Gv, Ma }, 0 },
11742 { EVEX_TABLE (EVEX_0F) },
11746 { "lesS", { Gv, Mp }, 0 },
11747 { VEX_C4_TABLE (VEX_0F) },
11751 { "ldsS", { Gv, Mp }, 0 },
11752 { VEX_C5_TABLE (VEX_0F) },
11755 /* MOD_VEX_0F12_PREFIX_0 */
11756 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11757 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11761 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11764 /* MOD_VEX_0F16_PREFIX_0 */
11765 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11766 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11770 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11774 { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11777 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11779 { "kandw", { MaskG, MaskVex, MaskR }, 0 },
11782 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11784 { "kandq", { MaskG, MaskVex, MaskR }, 0 },
11787 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11789 { "kandb", { MaskG, MaskVex, MaskR }, 0 },
11792 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11794 { "kandd", { MaskG, MaskVex, MaskR }, 0 },
11797 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11799 { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
11802 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11804 { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
11807 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11809 { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
11812 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11814 { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
11817 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11819 { "knotw", { MaskG, MaskR }, 0 },
11822 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11824 { "knotq", { MaskG, MaskR }, 0 },
11827 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11829 { "knotb", { MaskG, MaskR }, 0 },
11832 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11834 { "knotd", { MaskG, MaskR }, 0 },
11837 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11839 { "korw", { MaskG, MaskVex, MaskR }, 0 },
11842 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11844 { "korq", { MaskG, MaskVex, MaskR }, 0 },
11847 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11849 { "korb", { MaskG, MaskVex, MaskR }, 0 },
11852 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11854 { "kord", { MaskG, MaskVex, MaskR }, 0 },
11857 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11859 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
11862 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11864 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
11867 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11869 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
11872 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11874 { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
11877 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11879 { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
11882 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11884 { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
11887 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11889 { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
11892 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11894 { "kxord", { MaskG, MaskVex, MaskR }, 0 },
11897 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11899 { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
11902 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11904 { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
11907 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11909 { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
11912 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11914 { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
11917 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11919 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
11922 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11924 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
11927 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11929 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
11934 { VEX_W_TABLE (VEX_W_0F50_M_0) },
11937 /* MOD_VEX_0F71_REG_2 */
11939 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11942 /* MOD_VEX_0F71_REG_4 */
11944 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11947 /* MOD_VEX_0F71_REG_6 */
11949 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11952 /* MOD_VEX_0F72_REG_2 */
11954 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11957 /* MOD_VEX_0F72_REG_4 */
11959 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11962 /* MOD_VEX_0F72_REG_6 */
11964 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11967 /* MOD_VEX_0F73_REG_2 */
11969 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11972 /* MOD_VEX_0F73_REG_3 */
11974 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11977 /* MOD_VEX_0F73_REG_6 */
11979 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11982 /* MOD_VEX_0F73_REG_7 */
11984 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11987 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11988 { "kmovw", { Ew, MaskG }, 0 },
11992 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11993 { "kmovq", { Eq, MaskG }, 0 },
11997 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11998 { "kmovb", { Eb, MaskG }, 0 },
12002 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12003 { "kmovd", { Ed, MaskG }, 0 },
12007 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12009 { "kmovw", { MaskG, Rdq }, 0 },
12012 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12014 { "kmovb", { MaskG, Rdq }, 0 },
12017 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12019 { "kmovd", { MaskG, Rdq }, 0 },
12022 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12024 { "kmovq", { MaskG, Rdq }, 0 },
12027 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12029 { "kmovw", { Gdq, MaskR }, 0 },
12032 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12034 { "kmovb", { Gdq, MaskR }, 0 },
12037 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12039 { "kmovd", { Gdq, MaskR }, 0 },
12042 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12044 { "kmovq", { Gdq, MaskR }, 0 },
12047 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12049 { "kortestw", { MaskG, MaskR }, 0 },
12052 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12054 { "kortestq", { MaskG, MaskR }, 0 },
12057 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12059 { "kortestb", { MaskG, MaskR }, 0 },
12062 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12064 { "kortestd", { MaskG, MaskR }, 0 },
12067 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12069 { "ktestw", { MaskG, MaskR }, 0 },
12072 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12074 { "ktestq", { MaskG, MaskR }, 0 },
12077 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12079 { "ktestb", { MaskG, MaskR }, 0 },
12082 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12084 { "ktestd", { MaskG, MaskR }, 0 },
12087 /* MOD_VEX_0FAE_REG_2 */
12088 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12091 /* MOD_VEX_0FAE_REG_3 */
12092 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12095 /* MOD_VEX_0FD7_PREFIX_2 */
12097 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12100 /* MOD_VEX_0FE7_PREFIX_2 */
12101 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12104 /* MOD_VEX_0FF0_PREFIX_3 */
12105 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12108 /* MOD_VEX_0F381A_PREFIX_2 */
12109 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12112 /* MOD_VEX_0F382A_PREFIX_2 */
12113 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12116 /* MOD_VEX_0F382C_PREFIX_2 */
12117 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12120 /* MOD_VEX_0F382D_PREFIX_2 */
12121 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12124 /* MOD_VEX_0F382E_PREFIX_2 */
12125 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12128 /* MOD_VEX_0F382F_PREFIX_2 */
12129 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12132 /* MOD_VEX_0F385A_PREFIX_2 */
12133 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12136 /* MOD_VEX_0F388C_PREFIX_2 */
12137 { "vpmaskmov%LW", { XM, Vex, Mx }, 0 },
12140 /* MOD_VEX_0F388E_PREFIX_2 */
12141 { "vpmaskmov%LW", { Mx, Vex, XM }, 0 },
12144 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12146 { "kshiftrb", { MaskG, MaskR, Ib }, 0 },
12149 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12151 { "kshiftrw", { MaskG, MaskR, Ib }, 0 },
12154 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12156 { "kshiftrd", { MaskG, MaskR, Ib }, 0 },
12159 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12161 { "kshiftrq", { MaskG, MaskR, Ib }, 0 },
12164 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12166 { "kshiftlb", { MaskG, MaskR, Ib }, 0 },
12169 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12171 { "kshiftlw", { MaskG, MaskR, Ib }, 0 },
12174 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12176 { "kshiftld", { MaskG, MaskR, Ib }, 0 },
12179 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12181 { "kshiftlq", { MaskG, MaskR, Ib }, 0 },
12183 #define NEED_MOD_TABLE
12184 #include "i386-dis-evex.h"
12185 #undef NEED_MOD_TABLE
12188 static const struct dis386 rm_table[][8] = {
12191 { "xabort", { Skip_MODRM, Ib }, 0 },
12195 { "xbeginT", { Skip_MODRM, Jv }, 0 },
12198 /* RM_0F01_REG_0 */
12200 { "vmcall", { Skip_MODRM }, 0 },
12201 { "vmlaunch", { Skip_MODRM }, 0 },
12202 { "vmresume", { Skip_MODRM }, 0 },
12203 { "vmxoff", { Skip_MODRM }, 0 },
12206 /* RM_0F01_REG_1 */
12207 { "monitor", { { OP_Monitor, 0 } }, 0 },
12208 { "mwait", { { OP_Mwait, 0 } }, 0 },
12209 { "clac", { Skip_MODRM }, 0 },
12210 { "stac", { Skip_MODRM }, 0 },
12214 { "encls", { Skip_MODRM }, 0 },
12217 /* RM_0F01_REG_2 */
12218 { "xgetbv", { Skip_MODRM }, 0 },
12219 { "xsetbv", { Skip_MODRM }, 0 },
12222 { "vmfunc", { Skip_MODRM }, 0 },
12223 { "xend", { Skip_MODRM }, 0 },
12224 { "xtest", { Skip_MODRM }, 0 },
12225 { "enclu", { Skip_MODRM }, 0 },
12228 /* RM_0F01_REG_3 */
12229 { "vmrun", { Skip_MODRM }, 0 },
12230 { "vmmcall", { Skip_MODRM }, 0 },
12231 { "vmload", { Skip_MODRM }, 0 },
12232 { "vmsave", { Skip_MODRM }, 0 },
12233 { "stgi", { Skip_MODRM }, 0 },
12234 { "clgi", { Skip_MODRM }, 0 },
12235 { "skinit", { Skip_MODRM }, 0 },
12236 { "invlpga", { Skip_MODRM }, 0 },
12239 /* RM_0F01_REG_5 */
12240 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
12242 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
12246 { "rdpkru", { Skip_MODRM }, 0 },
12247 { "wrpkru", { Skip_MODRM }, 0 },
12250 /* RM_0F01_REG_7 */
12251 { "swapgs", { Skip_MODRM }, 0 },
12252 { "rdtscp", { Skip_MODRM }, 0 },
12253 { "monitorx", { { OP_Monitor, 0 } }, 0 },
12254 { "mwaitx", { { OP_Mwaitx, 0 } }, 0 },
12255 { "clzero", { Skip_MODRM }, 0 },
12258 /* RM_0F1E_MOD_3_REG_7 */
12259 { "nopQ", { Ev }, 0 },
12260 { "nopQ", { Ev }, 0 },
12261 { "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
12262 { "endbr32", { Skip_MODRM }, PREFIX_OPCODE },
12263 { "nopQ", { Ev }, 0 },
12264 { "nopQ", { Ev }, 0 },
12265 { "nopQ", { Ev }, 0 },
12266 { "nopQ", { Ev }, 0 },
12269 /* RM_0FAE_REG_6 */
12270 { "mfence", { Skip_MODRM }, 0 },
12273 /* RM_0FAE_REG_7 */
12274 { "sfence", { Skip_MODRM }, 0 },
12279 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12281 /* We use the high bit to indicate different name for the same
12283 #define REP_PREFIX (0xf3 | 0x100)
12284 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12285 #define XRELEASE_PREFIX (0xf3 | 0x400)
12286 #define BND_PREFIX (0xf2 | 0x400)
12287 #define NOTRACK_PREFIX (0x3e | 0x100)
12292 int newrex, i, length;
12298 last_lock_prefix = -1;
12299 last_repz_prefix = -1;
12300 last_repnz_prefix = -1;
12301 last_data_prefix = -1;
12302 last_addr_prefix = -1;
12303 last_rex_prefix = -1;
12304 last_seg_prefix = -1;
12306 active_seg_prefix = 0;
12307 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12308 all_prefixes[i] = 0;
12311 /* The maximum instruction length is 15bytes. */
12312 while (length < MAX_CODE_LENGTH - 1)
12314 FETCH_DATA (the_info, codep + 1);
12318 /* REX prefixes family. */
12335 if (address_mode == mode_64bit)
12339 last_rex_prefix = i;
12342 prefixes |= PREFIX_REPZ;
12343 last_repz_prefix = i;
12346 prefixes |= PREFIX_REPNZ;
12347 last_repnz_prefix = i;
12350 prefixes |= PREFIX_LOCK;
12351 last_lock_prefix = i;
12354 prefixes |= PREFIX_CS;
12355 last_seg_prefix = i;
12356 active_seg_prefix = PREFIX_CS;
12359 prefixes |= PREFIX_SS;
12360 last_seg_prefix = i;
12361 active_seg_prefix = PREFIX_SS;
12364 prefixes |= PREFIX_DS;
12365 last_seg_prefix = i;
12366 active_seg_prefix = PREFIX_DS;
12369 prefixes |= PREFIX_ES;
12370 last_seg_prefix = i;
12371 active_seg_prefix = PREFIX_ES;
12374 prefixes |= PREFIX_FS;
12375 last_seg_prefix = i;
12376 active_seg_prefix = PREFIX_FS;
12379 prefixes |= PREFIX_GS;
12380 last_seg_prefix = i;
12381 active_seg_prefix = PREFIX_GS;
12384 prefixes |= PREFIX_DATA;
12385 last_data_prefix = i;
12388 prefixes |= PREFIX_ADDR;
12389 last_addr_prefix = i;
12392 /* fwait is really an instruction. If there are prefixes
12393 before the fwait, they belong to the fwait, *not* to the
12394 following instruction. */
12396 if (prefixes || rex)
12398 prefixes |= PREFIX_FWAIT;
12400 /* This ensures that the previous REX prefixes are noticed
12401 as unused prefixes, as in the return case below. */
12405 prefixes = PREFIX_FWAIT;
12410 /* Rex is ignored when followed by another prefix. */
12416 if (*codep != FWAIT_OPCODE)
12417 all_prefixes[i++] = *codep;
12425 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12428 static const char *
12429 prefix_name (int pref, int sizeflag)
12431 static const char *rexes [16] =
12434 "rex.B", /* 0x41 */
12435 "rex.X", /* 0x42 */
12436 "rex.XB", /* 0x43 */
12437 "rex.R", /* 0x44 */
12438 "rex.RB", /* 0x45 */
12439 "rex.RX", /* 0x46 */
12440 "rex.RXB", /* 0x47 */
12441 "rex.W", /* 0x48 */
12442 "rex.WB", /* 0x49 */
12443 "rex.WX", /* 0x4a */
12444 "rex.WXB", /* 0x4b */
12445 "rex.WR", /* 0x4c */
12446 "rex.WRB", /* 0x4d */
12447 "rex.WRX", /* 0x4e */
12448 "rex.WRXB", /* 0x4f */
12453 /* REX prefixes family. */
12470 return rexes [pref - 0x40];
12490 return (sizeflag & DFLAG) ? "data16" : "data32";
12492 if (address_mode == mode_64bit)
12493 return (sizeflag & AFLAG) ? "addr32" : "addr64";
12495 return (sizeflag & AFLAG) ? "addr16" : "addr32";
12500 case XACQUIRE_PREFIX:
12502 case XRELEASE_PREFIX:
12506 case NOTRACK_PREFIX:
12513 static char op_out[MAX_OPERANDS][100];
12514 static int op_ad, op_index[MAX_OPERANDS];
12515 static int two_source_ops;
12516 static bfd_vma op_address[MAX_OPERANDS];
12517 static bfd_vma op_riprel[MAX_OPERANDS];
12518 static bfd_vma start_pc;
12521 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12522 * (see topic "Redundant prefixes" in the "Differences from 8086"
12523 * section of the "Virtual 8086 Mode" chapter.)
12524 * 'pc' should be the address of this instruction, it will
12525 * be used to print the target address if this is a relative jump or call
12526 * The function returns the length of this instruction in bytes.
12529 static char intel_syntax;
12530 static char intel_mnemonic = !SYSV386_COMPAT;
12531 static char open_char;
12532 static char close_char;
12533 static char separator_char;
12534 static char scale_char;
12542 static enum x86_64_isa isa64;
12544 /* Here for backwards compatibility. When gdb stops using
12545 print_insn_i386_att and print_insn_i386_intel these functions can
12546 disappear, and print_insn_i386 be merged into print_insn. */
12548 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12552 return print_insn (pc, info);
12556 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12560 return print_insn (pc, info);
12564 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12568 return print_insn (pc, info);
12572 print_i386_disassembler_options (FILE *stream)
12574 fprintf (stream, _("\n\
12575 The following i386/x86-64 specific disassembler options are supported for use\n\
12576 with the -M switch (multiple options should be separated by commas):\n"));
12578 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
12579 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
12580 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
12581 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
12582 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
12583 fprintf (stream, _(" att-mnemonic\n"
12584 " Display instruction in AT&T mnemonic\n"));
12585 fprintf (stream, _(" intel-mnemonic\n"
12586 " Display instruction in Intel mnemonic\n"));
12587 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
12588 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
12589 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
12590 fprintf (stream, _(" data32 Assume 32bit data size\n"));
12591 fprintf (stream, _(" data16 Assume 16bit data size\n"));
12592 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12593 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
12594 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
12598 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12600 /* Get a pointer to struct dis386 with a valid name. */
12602 static const struct dis386 *
12603 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12605 int vindex, vex_table_index;
12607 if (dp->name != NULL)
12610 switch (dp->op[0].bytemode)
12612 case USE_REG_TABLE:
12613 dp = ®_table[dp->op[1].bytemode][modrm.reg];
12616 case USE_MOD_TABLE:
12617 vindex = modrm.mod == 0x3 ? 1 : 0;
12618 dp = &mod_table[dp->op[1].bytemode][vindex];
12622 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12625 case USE_PREFIX_TABLE:
12628 /* The prefix in VEX is implicit. */
12629 switch (vex.prefix)
12634 case REPE_PREFIX_OPCODE:
12637 case DATA_PREFIX_OPCODE:
12640 case REPNE_PREFIX_OPCODE:
12650 int last_prefix = -1;
12653 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12654 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12656 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12658 if (last_repz_prefix > last_repnz_prefix)
12661 prefix = PREFIX_REPZ;
12662 last_prefix = last_repz_prefix;
12667 prefix = PREFIX_REPNZ;
12668 last_prefix = last_repnz_prefix;
12671 /* Check if prefix should be ignored. */
12672 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12673 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12678 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12681 prefix = PREFIX_DATA;
12682 last_prefix = last_data_prefix;
12687 used_prefixes |= prefix;
12688 all_prefixes[last_prefix] = 0;
12691 dp = &prefix_table[dp->op[1].bytemode][vindex];
12694 case USE_X86_64_TABLE:
12695 vindex = address_mode == mode_64bit ? 1 : 0;
12696 dp = &x86_64_table[dp->op[1].bytemode][vindex];
12699 case USE_3BYTE_TABLE:
12700 FETCH_DATA (info, codep + 2);
12702 dp = &three_byte_table[dp->op[1].bytemode][vindex];
12704 modrm.mod = (*codep >> 6) & 3;
12705 modrm.reg = (*codep >> 3) & 7;
12706 modrm.rm = *codep & 7;
12709 case USE_VEX_LEN_TABLE:
12713 switch (vex.length)
12726 dp = &vex_len_table[dp->op[1].bytemode][vindex];
12729 case USE_XOP_8F_TABLE:
12730 FETCH_DATA (info, codep + 3);
12731 /* All bits in the REX prefix are ignored. */
12733 rex = ~(*codep >> 5) & 0x7;
12735 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12736 switch ((*codep & 0x1f))
12742 vex_table_index = XOP_08;
12745 vex_table_index = XOP_09;
12748 vex_table_index = XOP_0A;
12752 vex.w = *codep & 0x80;
12753 if (vex.w && address_mode == mode_64bit)
12756 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12757 if (address_mode != mode_64bit)
12759 /* In 16/32-bit mode REX_B is silently ignored. */
12761 if (vex.register_specifier > 0x7)
12768 vex.length = (*codep & 0x4) ? 256 : 128;
12769 switch ((*codep & 0x3))
12775 vex.prefix = DATA_PREFIX_OPCODE;
12778 vex.prefix = REPE_PREFIX_OPCODE;
12781 vex.prefix = REPNE_PREFIX_OPCODE;
12788 dp = &xop_table[vex_table_index][vindex];
12791 FETCH_DATA (info, codep + 1);
12792 modrm.mod = (*codep >> 6) & 3;
12793 modrm.reg = (*codep >> 3) & 7;
12794 modrm.rm = *codep & 7;
12797 case USE_VEX_C4_TABLE:
12799 FETCH_DATA (info, codep + 3);
12800 /* All bits in the REX prefix are ignored. */
12802 rex = ~(*codep >> 5) & 0x7;
12803 switch ((*codep & 0x1f))
12809 vex_table_index = VEX_0F;
12812 vex_table_index = VEX_0F38;
12815 vex_table_index = VEX_0F3A;
12819 vex.w = *codep & 0x80;
12820 if (address_mode == mode_64bit)
12824 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12828 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12829 is ignored, other REX bits are 0 and the highest bit in
12830 VEX.vvvv is also ignored. */
12832 vex.register_specifier = (~(*codep >> 3)) & 0x7;
12834 vex.length = (*codep & 0x4) ? 256 : 128;
12835 switch ((*codep & 0x3))
12841 vex.prefix = DATA_PREFIX_OPCODE;
12844 vex.prefix = REPE_PREFIX_OPCODE;
12847 vex.prefix = REPNE_PREFIX_OPCODE;
12854 dp = &vex_table[vex_table_index][vindex];
12856 /* There is no MODRM byte for VEX0F 77. */
12857 if (vex_table_index != VEX_0F || vindex != 0x77)
12859 FETCH_DATA (info, codep + 1);
12860 modrm.mod = (*codep >> 6) & 3;
12861 modrm.reg = (*codep >> 3) & 7;
12862 modrm.rm = *codep & 7;
12866 case USE_VEX_C5_TABLE:
12868 FETCH_DATA (info, codep + 2);
12869 /* All bits in the REX prefix are ignored. */
12871 rex = (*codep & 0x80) ? 0 : REX_R;
12873 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12875 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12877 vex.length = (*codep & 0x4) ? 256 : 128;
12878 switch ((*codep & 0x3))
12884 vex.prefix = DATA_PREFIX_OPCODE;
12887 vex.prefix = REPE_PREFIX_OPCODE;
12890 vex.prefix = REPNE_PREFIX_OPCODE;
12897 dp = &vex_table[dp->op[1].bytemode][vindex];
12899 /* There is no MODRM byte for VEX 77. */
12900 if (vindex != 0x77)
12902 FETCH_DATA (info, codep + 1);
12903 modrm.mod = (*codep >> 6) & 3;
12904 modrm.reg = (*codep >> 3) & 7;
12905 modrm.rm = *codep & 7;
12909 case USE_VEX_W_TABLE:
12913 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12916 case USE_EVEX_TABLE:
12917 two_source_ops = 0;
12920 FETCH_DATA (info, codep + 4);
12921 /* All bits in the REX prefix are ignored. */
12923 /* The first byte after 0x62. */
12924 rex = ~(*codep >> 5) & 0x7;
12925 vex.r = *codep & 0x10;
12926 switch ((*codep & 0xf))
12929 return &bad_opcode;
12931 vex_table_index = EVEX_0F;
12934 vex_table_index = EVEX_0F38;
12937 vex_table_index = EVEX_0F3A;
12941 /* The second byte after 0x62. */
12943 vex.w = *codep & 0x80;
12944 if (vex.w && address_mode == mode_64bit)
12947 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12948 if (address_mode != mode_64bit)
12950 /* In 16/32-bit mode silently ignore following bits. */
12954 vex.register_specifier &= 0x7;
12958 if (!(*codep & 0x4))
12959 return &bad_opcode;
12961 switch ((*codep & 0x3))
12967 vex.prefix = DATA_PREFIX_OPCODE;
12970 vex.prefix = REPE_PREFIX_OPCODE;
12973 vex.prefix = REPNE_PREFIX_OPCODE;
12977 /* The third byte after 0x62. */
12980 /* Remember the static rounding bits. */
12981 vex.ll = (*codep >> 5) & 3;
12982 vex.b = (*codep & 0x10) != 0;
12984 vex.v = *codep & 0x8;
12985 vex.mask_register_specifier = *codep & 0x7;
12986 vex.zeroing = *codep & 0x80;
12992 dp = &evex_table[vex_table_index][vindex];
12994 FETCH_DATA (info, codep + 1);
12995 modrm.mod = (*codep >> 6) & 3;
12996 modrm.reg = (*codep >> 3) & 7;
12997 modrm.rm = *codep & 7;
12999 /* Set vector length. */
13000 if (modrm.mod == 3 && vex.b)
13016 return &bad_opcode;
13029 if (dp->name != NULL)
13032 return get_valid_dis386 (dp, info);
13036 get_sib (disassemble_info *info, int sizeflag)
13038 /* If modrm.mod == 3, operand must be register. */
13040 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13044 FETCH_DATA (info, codep + 2);
13045 sib.index = (codep [1] >> 3) & 7;
13046 sib.scale = (codep [1] >> 6) & 3;
13047 sib.base = codep [1] & 7;
13052 print_insn (bfd_vma pc, disassemble_info *info)
13054 const struct dis386 *dp;
13056 char *op_txt[MAX_OPERANDS];
13058 int sizeflag, orig_sizeflag;
13060 struct dis_private priv;
13063 priv.orig_sizeflag = AFLAG | DFLAG;
13064 if ((info->mach & bfd_mach_i386_i386) != 0)
13065 address_mode = mode_32bit;
13066 else if (info->mach == bfd_mach_i386_i8086)
13068 address_mode = mode_16bit;
13069 priv.orig_sizeflag = 0;
13072 address_mode = mode_64bit;
13074 if (intel_syntax == (char) -1)
13075 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13077 for (p = info->disassembler_options; p != NULL; )
13079 if (CONST_STRNEQ (p, "amd64"))
13081 else if (CONST_STRNEQ (p, "intel64"))
13083 else if (CONST_STRNEQ (p, "x86-64"))
13085 address_mode = mode_64bit;
13086 priv.orig_sizeflag = AFLAG | DFLAG;
13088 else if (CONST_STRNEQ (p, "i386"))
13090 address_mode = mode_32bit;
13091 priv.orig_sizeflag = AFLAG | DFLAG;
13093 else if (CONST_STRNEQ (p, "i8086"))
13095 address_mode = mode_16bit;
13096 priv.orig_sizeflag = 0;
13098 else if (CONST_STRNEQ (p, "intel"))
13101 if (CONST_STRNEQ (p + 5, "-mnemonic"))
13102 intel_mnemonic = 1;
13104 else if (CONST_STRNEQ (p, "att"))
13107 if (CONST_STRNEQ (p + 3, "-mnemonic"))
13108 intel_mnemonic = 0;
13110 else if (CONST_STRNEQ (p, "addr"))
13112 if (address_mode == mode_64bit)
13114 if (p[4] == '3' && p[5] == '2')
13115 priv.orig_sizeflag &= ~AFLAG;
13116 else if (p[4] == '6' && p[5] == '4')
13117 priv.orig_sizeflag |= AFLAG;
13121 if (p[4] == '1' && p[5] == '6')
13122 priv.orig_sizeflag &= ~AFLAG;
13123 else if (p[4] == '3' && p[5] == '2')
13124 priv.orig_sizeflag |= AFLAG;
13127 else if (CONST_STRNEQ (p, "data"))
13129 if (p[4] == '1' && p[5] == '6')
13130 priv.orig_sizeflag &= ~DFLAG;
13131 else if (p[4] == '3' && p[5] == '2')
13132 priv.orig_sizeflag |= DFLAG;
13134 else if (CONST_STRNEQ (p, "suffix"))
13135 priv.orig_sizeflag |= SUFFIX_ALWAYS;
13137 p = strchr (p, ',');
13142 if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13144 (*info->fprintf_func) (info->stream,
13145 _("64-bit address is disabled"));
13151 names64 = intel_names64;
13152 names32 = intel_names32;
13153 names16 = intel_names16;
13154 names8 = intel_names8;
13155 names8rex = intel_names8rex;
13156 names_seg = intel_names_seg;
13157 names_mm = intel_names_mm;
13158 names_bnd = intel_names_bnd;
13159 names_xmm = intel_names_xmm;
13160 names_ymm = intel_names_ymm;
13161 names_zmm = intel_names_zmm;
13162 index64 = intel_index64;
13163 index32 = intel_index32;
13164 names_mask = intel_names_mask;
13165 index16 = intel_index16;
13168 separator_char = '+';
13173 names64 = att_names64;
13174 names32 = att_names32;
13175 names16 = att_names16;
13176 names8 = att_names8;
13177 names8rex = att_names8rex;
13178 names_seg = att_names_seg;
13179 names_mm = att_names_mm;
13180 names_bnd = att_names_bnd;
13181 names_xmm = att_names_xmm;
13182 names_ymm = att_names_ymm;
13183 names_zmm = att_names_zmm;
13184 index64 = att_index64;
13185 index32 = att_index32;
13186 names_mask = att_names_mask;
13187 index16 = att_index16;
13190 separator_char = ',';
13194 /* The output looks better if we put 7 bytes on a line, since that
13195 puts most long word instructions on a single line. Use 8 bytes
13197 if ((info->mach & bfd_mach_l1om) != 0)
13198 info->bytes_per_line = 8;
13200 info->bytes_per_line = 7;
13202 info->private_data = &priv;
13203 priv.max_fetched = priv.the_buffer;
13204 priv.insn_start = pc;
13207 for (i = 0; i < MAX_OPERANDS; ++i)
13215 start_codep = priv.the_buffer;
13216 codep = priv.the_buffer;
13218 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13222 /* Getting here means we tried for data but didn't get it. That
13223 means we have an incomplete instruction of some sort. Just
13224 print the first byte as a prefix or a .byte pseudo-op. */
13225 if (codep > priv.the_buffer)
13227 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13229 (*info->fprintf_func) (info->stream, "%s", name);
13232 /* Just print the first byte as a .byte instruction. */
13233 (*info->fprintf_func) (info->stream, ".byte 0x%x",
13234 (unsigned int) priv.the_buffer[0]);
13244 sizeflag = priv.orig_sizeflag;
13246 if (!ckprefix () || rex_used)
13248 /* Too many prefixes or unused REX prefixes. */
13250 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13252 (*info->fprintf_func) (info->stream, "%s%s",
13254 prefix_name (all_prefixes[i], sizeflag));
13258 insn_codep = codep;
13260 FETCH_DATA (info, codep + 1);
13261 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13263 if (((prefixes & PREFIX_FWAIT)
13264 && ((*codep < 0xd8) || (*codep > 0xdf))))
13266 /* Handle prefixes before fwait. */
13267 for (i = 0; i < fwait_prefix && all_prefixes[i];
13269 (*info->fprintf_func) (info->stream, "%s ",
13270 prefix_name (all_prefixes[i], sizeflag));
13271 (*info->fprintf_func) (info->stream, "fwait");
13275 if (*codep == 0x0f)
13277 unsigned char threebyte;
13280 FETCH_DATA (info, codep + 1);
13281 threebyte = *codep;
13282 dp = &dis386_twobyte[threebyte];
13283 need_modrm = twobyte_has_modrm[*codep];
13288 dp = &dis386[*codep];
13289 need_modrm = onebyte_has_modrm[*codep];
13293 /* Save sizeflag for printing the extra prefixes later before updating
13294 it for mnemonic and operand processing. The prefix names depend
13295 only on the address mode. */
13296 orig_sizeflag = sizeflag;
13297 if (prefixes & PREFIX_ADDR)
13299 if ((prefixes & PREFIX_DATA))
13305 FETCH_DATA (info, codep + 1);
13306 modrm.mod = (*codep >> 6) & 3;
13307 modrm.reg = (*codep >> 3) & 7;
13308 modrm.rm = *codep & 7;
13316 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13318 get_sib (info, sizeflag);
13319 dofloat (sizeflag);
13323 dp = get_valid_dis386 (dp, info);
13324 if (dp != NULL && putop (dp->name, sizeflag) == 0)
13326 get_sib (info, sizeflag);
13327 for (i = 0; i < MAX_OPERANDS; ++i)
13330 op_ad = MAX_OPERANDS - 1 - i;
13332 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13333 /* For EVEX instruction after the last operand masking
13334 should be printed. */
13335 if (i == 0 && vex.evex)
13337 /* Don't print {%k0}. */
13338 if (vex.mask_register_specifier)
13341 oappend (names_mask[vex.mask_register_specifier]);
13351 /* Check if the REX prefix is used. */
13352 if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13353 all_prefixes[last_rex_prefix] = 0;
13355 /* Check if the SEG prefix is used. */
13356 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13357 | PREFIX_FS | PREFIX_GS)) != 0
13358 && (used_prefixes & active_seg_prefix) != 0)
13359 all_prefixes[last_seg_prefix] = 0;
13361 /* Check if the ADDR prefix is used. */
13362 if ((prefixes & PREFIX_ADDR) != 0
13363 && (used_prefixes & PREFIX_ADDR) != 0)
13364 all_prefixes[last_addr_prefix] = 0;
13366 /* Check if the DATA prefix is used. */
13367 if ((prefixes & PREFIX_DATA) != 0
13368 && (used_prefixes & PREFIX_DATA) != 0)
13369 all_prefixes[last_data_prefix] = 0;
13371 /* Print the extra prefixes. */
13373 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13374 if (all_prefixes[i])
13377 name = prefix_name (all_prefixes[i], orig_sizeflag);
13380 prefix_length += strlen (name) + 1;
13381 (*info->fprintf_func) (info->stream, "%s ", name);
13384 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13385 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13386 used by putop and MMX/SSE operand and may be overriden by the
13387 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13389 if (dp->prefix_requirement == PREFIX_OPCODE
13390 && dp != &bad_opcode
13392 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13394 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13396 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13398 && (used_prefixes & PREFIX_DATA) == 0))))
13400 (*info->fprintf_func) (info->stream, "(bad)");
13401 return end_codep - priv.the_buffer;
13404 /* Check maximum code length. */
13405 if ((codep - start_codep) > MAX_CODE_LENGTH)
13407 (*info->fprintf_func) (info->stream, "(bad)");
13408 return MAX_CODE_LENGTH;
13411 obufp = mnemonicendp;
13412 for (i = strlen (obuf) + prefix_length; i < 6; i++)
13415 (*info->fprintf_func) (info->stream, "%s", obuf);
13417 /* The enter and bound instructions are printed with operands in the same
13418 order as the intel book; everything else is printed in reverse order. */
13419 if (intel_syntax || two_source_ops)
13423 for (i = 0; i < MAX_OPERANDS; ++i)
13424 op_txt[i] = op_out[i];
13426 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13427 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13429 op_txt[2] = op_out[3];
13430 op_txt[3] = op_out[2];
13433 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13435 op_ad = op_index[i];
13436 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13437 op_index[MAX_OPERANDS - 1 - i] = op_ad;
13438 riprel = op_riprel[i];
13439 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13440 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13445 for (i = 0; i < MAX_OPERANDS; ++i)
13446 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13450 for (i = 0; i < MAX_OPERANDS; ++i)
13454 (*info->fprintf_func) (info->stream, ",");
13455 if (op_index[i] != -1 && !op_riprel[i])
13456 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13458 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13462 for (i = 0; i < MAX_OPERANDS; i++)
13463 if (op_index[i] != -1 && op_riprel[i])
13465 (*info->fprintf_func) (info->stream, " # ");
13466 (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13467 + op_address[op_index[i]]), info);
13470 return codep - priv.the_buffer;
13473 static const char *float_mem[] = {
13548 static const unsigned char float_mem_mode[] = {
13623 #define ST { OP_ST, 0 }
13624 #define STi { OP_STi, 0 }
13626 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13627 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13628 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13629 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13630 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13631 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13632 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13633 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13634 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13636 static const struct dis386 float_reg[][8] = {
13639 { "fadd", { ST, STi }, 0 },
13640 { "fmul", { ST, STi }, 0 },
13641 { "fcom", { STi }, 0 },
13642 { "fcomp", { STi }, 0 },
13643 { "fsub", { ST, STi }, 0 },
13644 { "fsubr", { ST, STi }, 0 },
13645 { "fdiv", { ST, STi }, 0 },
13646 { "fdivr", { ST, STi }, 0 },
13650 { "fld", { STi }, 0 },
13651 { "fxch", { STi }, 0 },
13661 { "fcmovb", { ST, STi }, 0 },
13662 { "fcmove", { ST, STi }, 0 },
13663 { "fcmovbe",{ ST, STi }, 0 },
13664 { "fcmovu", { ST, STi }, 0 },
13672 { "fcmovnb",{ ST, STi }, 0 },
13673 { "fcmovne",{ ST, STi }, 0 },
13674 { "fcmovnbe",{ ST, STi }, 0 },
13675 { "fcmovnu",{ ST, STi }, 0 },
13677 { "fucomi", { ST, STi }, 0 },
13678 { "fcomi", { ST, STi }, 0 },
13683 { "fadd", { STi, ST }, 0 },
13684 { "fmul", { STi, ST }, 0 },
13687 { "fsub!M", { STi, ST }, 0 },
13688 { "fsubM", { STi, ST }, 0 },
13689 { "fdiv!M", { STi, ST }, 0 },
13690 { "fdivM", { STi, ST }, 0 },
13694 { "ffree", { STi }, 0 },
13696 { "fst", { STi }, 0 },
13697 { "fstp", { STi }, 0 },
13698 { "fucom", { STi }, 0 },
13699 { "fucomp", { STi }, 0 },
13705 { "faddp", { STi, ST }, 0 },
13706 { "fmulp", { STi, ST }, 0 },
13709 { "fsub!Mp", { STi, ST }, 0 },
13710 { "fsubMp", { STi, ST }, 0 },
13711 { "fdiv!Mp", { STi, ST }, 0 },
13712 { "fdivMp", { STi, ST }, 0 },
13716 { "ffreep", { STi }, 0 },
13721 { "fucomip", { ST, STi }, 0 },
13722 { "fcomip", { ST, STi }, 0 },
13727 static char *fgrps[][8] = {
13730 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13735 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13740 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13745 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13750 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13755 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13760 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13765 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13766 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13771 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13776 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13781 swap_operand (void)
13783 mnemonicendp[0] = '.';
13784 mnemonicendp[1] = 's';
13789 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13790 int sizeflag ATTRIBUTE_UNUSED)
13792 /* Skip mod/rm byte. */
13798 dofloat (int sizeflag)
13800 const struct dis386 *dp;
13801 unsigned char floatop;
13803 floatop = codep[-1];
13805 if (modrm.mod != 3)
13807 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13809 putop (float_mem[fp_indx], sizeflag);
13812 OP_E (float_mem_mode[fp_indx], sizeflag);
13815 /* Skip mod/rm byte. */
13819 dp = &float_reg[floatop - 0xd8][modrm.reg];
13820 if (dp->name == NULL)
13822 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13824 /* Instruction fnstsw is only one with strange arg. */
13825 if (floatop == 0xdf && codep[-1] == 0xe0)
13826 strcpy (op_out[0], names16[0]);
13830 putop (dp->name, sizeflag);
13835 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13840 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13844 /* Like oappend (below), but S is a string starting with '%'.
13845 In Intel syntax, the '%' is elided. */
13847 oappend_maybe_intel (const char *s)
13849 oappend (s + intel_syntax);
13853 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13855 oappend_maybe_intel ("%st");
13859 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13861 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13862 oappend_maybe_intel (scratchbuf);
13865 /* Capital letters in template are macros. */
13867 putop (const char *in_template, int sizeflag)
13872 unsigned int l = 0, len = 1;
13875 #define SAVE_LAST(c) \
13876 if (l < len && l < sizeof (last)) \
13881 for (p = in_template; *p; p++)
13897 while (*++p != '|')
13898 if (*p == '}' || *p == '\0')
13901 /* Fall through. */
13906 while (*++p != '}')
13917 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13921 if (l == 0 && len == 1)
13926 if (sizeflag & SUFFIX_ALWAYS)
13939 if (address_mode == mode_64bit
13940 && !(prefixes & PREFIX_ADDR))
13951 if (intel_syntax && !alt)
13953 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13955 if (sizeflag & DFLAG)
13956 *obufp++ = intel_syntax ? 'd' : 'l';
13958 *obufp++ = intel_syntax ? 'w' : 's';
13959 used_prefixes |= (prefixes & PREFIX_DATA);
13963 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13966 if (modrm.mod == 3)
13972 if (sizeflag & DFLAG)
13973 *obufp++ = intel_syntax ? 'd' : 'l';
13976 used_prefixes |= (prefixes & PREFIX_DATA);
13982 case 'E': /* For jcxz/jecxz */
13983 if (address_mode == mode_64bit)
13985 if (sizeflag & AFLAG)
13991 if (sizeflag & AFLAG)
13993 used_prefixes |= (prefixes & PREFIX_ADDR);
13998 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14000 if (sizeflag & AFLAG)
14001 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14003 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14004 used_prefixes |= (prefixes & PREFIX_ADDR);
14008 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14010 if ((rex & REX_W) || (sizeflag & DFLAG))
14014 if (!(rex & REX_W))
14015 used_prefixes |= (prefixes & PREFIX_DATA);
14020 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14021 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14023 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14026 if (prefixes & PREFIX_DS)
14045 if (l != 0 || len != 1)
14047 if (l != 1 || len != 2 || last[0] != 'X')
14052 if (!need_vex || !vex.evex)
14055 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14057 switch (vex.length)
14075 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14080 /* Fall through. */
14083 if (l != 0 || len != 1)
14091 if (sizeflag & SUFFIX_ALWAYS)
14095 if (intel_mnemonic != cond)
14099 if ((prefixes & PREFIX_FWAIT) == 0)
14102 used_prefixes |= PREFIX_FWAIT;
14108 else if (intel_syntax && (sizeflag & DFLAG))
14112 if (!(rex & REX_W))
14113 used_prefixes |= (prefixes & PREFIX_DATA);
14117 && address_mode == mode_64bit
14118 && isa64 == intel64)
14123 /* Fall through. */
14126 && address_mode == mode_64bit
14127 && ((sizeflag & DFLAG) || (rex & REX_W)))
14132 /* Fall through. */
14135 if (l == 0 && len == 1)
14140 if ((rex & REX_W) == 0
14141 && (prefixes & PREFIX_DATA))
14143 if ((sizeflag & DFLAG) == 0)
14145 used_prefixes |= (prefixes & PREFIX_DATA);
14149 if ((prefixes & PREFIX_DATA)
14151 || (sizeflag & SUFFIX_ALWAYS))
14158 if (sizeflag & DFLAG)
14162 used_prefixes |= (prefixes & PREFIX_DATA);
14168 if (l != 1 || len != 2 || last[0] != 'L')
14174 if ((prefixes & PREFIX_DATA)
14176 || (sizeflag & SUFFIX_ALWAYS))
14183 if (sizeflag & DFLAG)
14184 *obufp++ = intel_syntax ? 'd' : 'l';
14187 used_prefixes |= (prefixes & PREFIX_DATA);
14195 if (address_mode == mode_64bit
14196 && ((sizeflag & DFLAG) || (rex & REX_W)))
14198 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14202 /* Fall through. */
14205 if (l == 0 && len == 1)
14208 if (intel_syntax && !alt)
14211 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14217 if (sizeflag & DFLAG)
14218 *obufp++ = intel_syntax ? 'd' : 'l';
14221 used_prefixes |= (prefixes & PREFIX_DATA);
14227 if (l != 1 || len != 2 || last[0] != 'L')
14233 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14248 else if (sizeflag & DFLAG)
14257 if (intel_syntax && !p[1]
14258 && ((rex & REX_W) || (sizeflag & DFLAG)))
14260 if (!(rex & REX_W))
14261 used_prefixes |= (prefixes & PREFIX_DATA);
14264 if (l == 0 && len == 1)
14268 if (address_mode == mode_64bit
14269 && ((sizeflag & DFLAG) || (rex & REX_W)))
14271 if (sizeflag & SUFFIX_ALWAYS)
14293 /* Fall through. */
14296 if (l == 0 && len == 1)
14301 if (sizeflag & SUFFIX_ALWAYS)
14307 if (sizeflag & DFLAG)
14311 used_prefixes |= (prefixes & PREFIX_DATA);
14325 if (address_mode == mode_64bit
14326 && !(prefixes & PREFIX_ADDR))
14337 if (l != 0 || len != 1)
14342 if (need_vex && vex.prefix)
14344 if (vex.prefix == DATA_PREFIX_OPCODE)
14351 if (prefixes & PREFIX_DATA)
14355 used_prefixes |= (prefixes & PREFIX_DATA);
14359 if (l == 0 && len == 1)
14361 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14372 if (l != 1 || len != 2 || last[0] != 'X')
14380 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14382 switch (vex.length)
14398 if (l == 0 && len == 1)
14400 /* operand size flag for cwtl, cbtw */
14409 else if (sizeflag & DFLAG)
14413 if (!(rex & REX_W))
14414 used_prefixes |= (prefixes & PREFIX_DATA);
14421 && last[0] != 'L'))
14428 if (last[0] == 'X')
14429 *obufp++ = vex.w ? 'd': 's';
14431 *obufp++ = vex.w ? 'q': 'd';
14437 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14439 if (sizeflag & DFLAG)
14443 used_prefixes |= (prefixes & PREFIX_DATA);
14449 if (address_mode == mode_64bit
14450 && (isa64 == intel64
14451 || ((sizeflag & DFLAG) || (rex & REX_W))))
14453 else if ((prefixes & PREFIX_DATA))
14455 if (!(sizeflag & DFLAG))
14457 used_prefixes |= (prefixes & PREFIX_DATA);
14464 mnemonicendp = obufp;
14469 oappend (const char *s)
14471 obufp = stpcpy (obufp, s);
14477 /* Only print the active segment register. */
14478 if (!active_seg_prefix)
14481 used_prefixes |= active_seg_prefix;
14482 switch (active_seg_prefix)
14485 oappend_maybe_intel ("%cs:");
14488 oappend_maybe_intel ("%ds:");
14491 oappend_maybe_intel ("%ss:");
14494 oappend_maybe_intel ("%es:");
14497 oappend_maybe_intel ("%fs:");
14500 oappend_maybe_intel ("%gs:");
14508 OP_indirE (int bytemode, int sizeflag)
14512 OP_E (bytemode, sizeflag);
14516 print_operand_value (char *buf, int hex, bfd_vma disp)
14518 if (address_mode == mode_64bit)
14526 sprintf_vma (tmp, disp);
14527 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14528 strcpy (buf + 2, tmp + i);
14532 bfd_signed_vma v = disp;
14539 /* Check for possible overflow on 0x8000000000000000. */
14542 strcpy (buf, "9223372036854775808");
14556 tmp[28 - i] = (v % 10) + '0';
14560 strcpy (buf, tmp + 29 - i);
14566 sprintf (buf, "0x%x", (unsigned int) disp);
14568 sprintf (buf, "%d", (int) disp);
14572 /* Put DISP in BUF as signed hex number. */
14575 print_displacement (char *buf, bfd_vma disp)
14577 bfd_signed_vma val = disp;
14586 /* Check for possible overflow. */
14589 switch (address_mode)
14592 strcpy (buf + j, "0x8000000000000000");
14595 strcpy (buf + j, "0x80000000");
14598 strcpy (buf + j, "0x8000");
14608 sprintf_vma (tmp, (bfd_vma) val);
14609 for (i = 0; tmp[i] == '0'; i++)
14611 if (tmp[i] == '\0')
14613 strcpy (buf + j, tmp + i);
14617 intel_operand_size (int bytemode, int sizeflag)
14621 && (bytemode == x_mode
14622 || bytemode == evex_half_bcst_xmmq_mode))
14625 oappend ("QWORD PTR ");
14627 oappend ("DWORD PTR ");
14636 oappend ("BYTE PTR ");
14641 oappend ("WORD PTR ");
14644 if (address_mode == mode_64bit && isa64 == intel64)
14646 oappend ("QWORD PTR ");
14649 /* Fall through. */
14651 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14653 oappend ("QWORD PTR ");
14656 /* Fall through. */
14662 oappend ("QWORD PTR ");
14665 if ((sizeflag & DFLAG) || bytemode == dq_mode)
14666 oappend ("DWORD PTR ");
14668 oappend ("WORD PTR ");
14669 used_prefixes |= (prefixes & PREFIX_DATA);
14673 if ((rex & REX_W) || (sizeflag & DFLAG))
14675 oappend ("WORD PTR ");
14676 if (!(rex & REX_W))
14677 used_prefixes |= (prefixes & PREFIX_DATA);
14680 if (sizeflag & DFLAG)
14681 oappend ("QWORD PTR ");
14683 oappend ("DWORD PTR ");
14684 used_prefixes |= (prefixes & PREFIX_DATA);
14687 case d_scalar_mode:
14688 case d_scalar_swap_mode:
14691 oappend ("DWORD PTR ");
14694 case q_scalar_mode:
14695 case q_scalar_swap_mode:
14697 oappend ("QWORD PTR ");
14700 if (address_mode == mode_64bit)
14701 oappend ("QWORD PTR ");
14703 oappend ("DWORD PTR ");
14706 if (sizeflag & DFLAG)
14707 oappend ("FWORD PTR ");
14709 oappend ("DWORD PTR ");
14710 used_prefixes |= (prefixes & PREFIX_DATA);
14713 oappend ("TBYTE PTR ");
14717 case evex_x_gscat_mode:
14718 case evex_x_nobcst_mode:
14721 switch (vex.length)
14724 oappend ("XMMWORD PTR ");
14727 oappend ("YMMWORD PTR ");
14730 oappend ("ZMMWORD PTR ");
14737 oappend ("XMMWORD PTR ");
14740 oappend ("XMMWORD PTR ");
14743 oappend ("YMMWORD PTR ");
14746 case evex_half_bcst_xmmq_mode:
14750 switch (vex.length)
14753 oappend ("QWORD PTR ");
14756 oappend ("XMMWORD PTR ");
14759 oappend ("YMMWORD PTR ");
14769 switch (vex.length)
14774 oappend ("BYTE PTR ");
14784 switch (vex.length)
14789 oappend ("WORD PTR ");
14799 switch (vex.length)
14804 oappend ("DWORD PTR ");
14814 switch (vex.length)
14819 oappend ("QWORD PTR ");
14829 switch (vex.length)
14832 oappend ("WORD PTR ");
14835 oappend ("DWORD PTR ");
14838 oappend ("QWORD PTR ");
14848 switch (vex.length)
14851 oappend ("DWORD PTR ");
14854 oappend ("QWORD PTR ");
14857 oappend ("XMMWORD PTR ");
14867 switch (vex.length)
14870 oappend ("QWORD PTR ");
14873 oappend ("YMMWORD PTR ");
14876 oappend ("ZMMWORD PTR ");
14886 switch (vex.length)
14890 oappend ("XMMWORD PTR ");
14897 oappend ("OWORD PTR ");
14900 case vex_w_dq_mode:
14901 case vex_scalar_w_dq_mode:
14906 oappend ("QWORD PTR ");
14908 oappend ("DWORD PTR ");
14910 case vex_vsib_d_w_dq_mode:
14911 case vex_vsib_q_w_dq_mode:
14918 oappend ("QWORD PTR ");
14920 oappend ("DWORD PTR ");
14924 switch (vex.length)
14927 oappend ("XMMWORD PTR ");
14930 oappend ("YMMWORD PTR ");
14933 oappend ("ZMMWORD PTR ");
14940 case vex_vsib_q_w_d_mode:
14941 case vex_vsib_d_w_d_mode:
14942 if (!need_vex || !vex.evex)
14945 switch (vex.length)
14948 oappend ("QWORD PTR ");
14951 oappend ("XMMWORD PTR ");
14954 oappend ("YMMWORD PTR ");
14962 if (!need_vex || vex.length != 128)
14965 oappend ("DWORD PTR ");
14967 oappend ("BYTE PTR ");
14973 oappend ("QWORD PTR ");
14975 oappend ("WORD PTR ");
14984 OP_E_register (int bytemode, int sizeflag)
14986 int reg = modrm.rm;
14987 const char **names;
14993 if ((sizeflag & SUFFIX_ALWAYS)
14994 && (bytemode == b_swap_mode
14995 || bytemode == v_swap_mode))
15021 names = address_mode == mode_64bit ? names64 : names32;
15032 if (address_mode == mode_64bit && isa64 == intel64)
15037 /* Fall through. */
15039 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15045 /* Fall through. */
15057 if ((sizeflag & DFLAG)
15058 || (bytemode != v_mode
15059 && bytemode != v_swap_mode))
15063 used_prefixes |= (prefixes & PREFIX_DATA);
15073 names = names_mask;
15078 oappend (INTERNAL_DISASSEMBLER_ERROR);
15081 oappend (names[reg]);
15085 OP_E_memory (int bytemode, int sizeflag)
15088 int add = (rex & REX_B) ? 8 : 0;
15094 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
15096 && bytemode != x_mode
15097 && bytemode != xmmq_mode
15098 && bytemode != evex_half_bcst_xmmq_mode)
15113 case vex_vsib_d_w_dq_mode:
15114 case vex_vsib_d_w_d_mode:
15115 case vex_vsib_q_w_dq_mode:
15116 case vex_vsib_q_w_d_mode:
15117 case evex_x_gscat_mode:
15119 shift = vex.w ? 3 : 2;
15122 case evex_half_bcst_xmmq_mode:
15126 shift = vex.w ? 3 : 2;
15129 /* Fall through. */
15133 case evex_x_nobcst_mode:
15135 switch (vex.length)
15158 case q_scalar_mode:
15160 case q_scalar_swap_mode:
15166 case d_scalar_mode:
15168 case d_scalar_swap_mode:
15180 /* Make necessary corrections to shift for modes that need it.
15181 For these modes we currently have shift 4, 5 or 6 depending on
15182 vex.length (it corresponds to xmmword, ymmword or zmmword
15183 operand). We might want to make it 3, 4 or 5 (e.g. for
15184 xmmq_mode). In case of broadcast enabled the corrections
15185 aren't needed, as element size is always 32 or 64 bits. */
15187 && (bytemode == xmmq_mode
15188 || bytemode == evex_half_bcst_xmmq_mode))
15190 else if (bytemode == xmmqd_mode)
15192 else if (bytemode == xmmdw_mode)
15194 else if (bytemode == ymmq_mode && vex.length == 128)
15202 intel_operand_size (bytemode, sizeflag);
15205 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15207 /* 32/64 bit address mode */
15216 int addr32flag = !((sizeflag & AFLAG)
15217 || bytemode == v_bnd_mode
15218 || bytemode == bnd_mode);
15219 const char **indexes64 = names64;
15220 const char **indexes32 = names32;
15230 vindex = sib.index;
15236 case vex_vsib_d_w_dq_mode:
15237 case vex_vsib_d_w_d_mode:
15238 case vex_vsib_q_w_dq_mode:
15239 case vex_vsib_q_w_d_mode:
15249 switch (vex.length)
15252 indexes64 = indexes32 = names_xmm;
15256 || bytemode == vex_vsib_q_w_dq_mode
15257 || bytemode == vex_vsib_q_w_d_mode)
15258 indexes64 = indexes32 = names_ymm;
15260 indexes64 = indexes32 = names_xmm;
15264 || bytemode == vex_vsib_q_w_dq_mode
15265 || bytemode == vex_vsib_q_w_d_mode)
15266 indexes64 = indexes32 = names_zmm;
15268 indexes64 = indexes32 = names_ymm;
15275 haveindex = vindex != 4;
15282 rbase = base + add;
15290 if (address_mode == mode_64bit && !havesib)
15296 FETCH_DATA (the_info, codep + 1);
15298 if ((disp & 0x80) != 0)
15300 if (vex.evex && shift > 0)
15308 /* In 32bit mode, we need index register to tell [offset] from
15309 [eiz*1 + offset]. */
15310 needindex = (havesib
15313 && address_mode == mode_32bit);
15314 havedisp = (havebase
15316 || (havesib && (haveindex || scale != 0)));
15319 if (modrm.mod != 0 || base == 5)
15321 if (havedisp || riprel)
15322 print_displacement (scratchbuf, disp);
15324 print_operand_value (scratchbuf, 1, disp);
15325 oappend (scratchbuf);
15329 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15333 if ((havebase || haveindex || riprel)
15334 && (bytemode != v_bnd_mode)
15335 && (bytemode != bnd_mode))
15336 used_prefixes |= PREFIX_ADDR;
15338 if (havedisp || (intel_syntax && riprel))
15340 *obufp++ = open_char;
15341 if (intel_syntax && riprel)
15344 oappend (!addr32flag ? "rip" : "eip");
15348 oappend (address_mode == mode_64bit && !addr32flag
15349 ? names64[rbase] : names32[rbase]);
15352 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15353 print index to tell base + index from base. */
15357 || (havebase && base != ESP_REG_NUM))
15359 if (!intel_syntax || havebase)
15361 *obufp++ = separator_char;
15365 oappend (address_mode == mode_64bit && !addr32flag
15366 ? indexes64[vindex] : indexes32[vindex]);
15368 oappend (address_mode == mode_64bit && !addr32flag
15369 ? index64 : index32);
15371 *obufp++ = scale_char;
15373 sprintf (scratchbuf, "%d", 1 << scale);
15374 oappend (scratchbuf);
15378 && (disp || modrm.mod != 0 || base == 5))
15380 if (!havedisp || (bfd_signed_vma) disp >= 0)
15385 else if (modrm.mod != 1 && disp != -disp)
15389 disp = - (bfd_signed_vma) disp;
15393 print_displacement (scratchbuf, disp);
15395 print_operand_value (scratchbuf, 1, disp);
15396 oappend (scratchbuf);
15399 *obufp++ = close_char;
15402 else if (intel_syntax)
15404 if (modrm.mod != 0 || base == 5)
15406 if (!active_seg_prefix)
15408 oappend (names_seg[ds_reg - es_reg]);
15411 print_operand_value (scratchbuf, 1, disp);
15412 oappend (scratchbuf);
15418 /* 16 bit address mode */
15419 used_prefixes |= prefixes & PREFIX_ADDR;
15426 if ((disp & 0x8000) != 0)
15431 FETCH_DATA (the_info, codep + 1);
15433 if ((disp & 0x80) != 0)
15438 if ((disp & 0x8000) != 0)
15444 if (modrm.mod != 0 || modrm.rm == 6)
15446 print_displacement (scratchbuf, disp);
15447 oappend (scratchbuf);
15450 if (modrm.mod != 0 || modrm.rm != 6)
15452 *obufp++ = open_char;
15454 oappend (index16[modrm.rm]);
15456 && (disp || modrm.mod != 0 || modrm.rm == 6))
15458 if ((bfd_signed_vma) disp >= 0)
15463 else if (modrm.mod != 1)
15467 disp = - (bfd_signed_vma) disp;
15470 print_displacement (scratchbuf, disp);
15471 oappend (scratchbuf);
15474 *obufp++ = close_char;
15477 else if (intel_syntax)
15479 if (!active_seg_prefix)
15481 oappend (names_seg[ds_reg - es_reg]);
15484 print_operand_value (scratchbuf, 1, disp & 0xffff);
15485 oappend (scratchbuf);
15488 if (vex.evex && vex.b
15489 && (bytemode == x_mode
15490 || bytemode == xmmq_mode
15491 || bytemode == evex_half_bcst_xmmq_mode))
15494 || bytemode == xmmq_mode
15495 || bytemode == evex_half_bcst_xmmq_mode)
15497 switch (vex.length)
15500 oappend ("{1to2}");
15503 oappend ("{1to4}");
15506 oappend ("{1to8}");
15514 switch (vex.length)
15517 oappend ("{1to4}");
15520 oappend ("{1to8}");
15523 oappend ("{1to16}");
15533 OP_E (int bytemode, int sizeflag)
15535 /* Skip mod/rm byte. */
15539 if (modrm.mod == 3)
15540 OP_E_register (bytemode, sizeflag);
15542 OP_E_memory (bytemode, sizeflag);
15546 OP_G (int bytemode, int sizeflag)
15557 oappend (names8rex[modrm.reg + add]);
15559 oappend (names8[modrm.reg + add]);
15562 oappend (names16[modrm.reg + add]);
15567 oappend (names32[modrm.reg + add]);
15570 oappend (names64[modrm.reg + add]);
15573 if (modrm.reg > 0x3)
15578 oappend (names_bnd[modrm.reg]);
15587 oappend (names64[modrm.reg + add]);
15590 if ((sizeflag & DFLAG) || bytemode != v_mode)
15591 oappend (names32[modrm.reg + add]);
15593 oappend (names16[modrm.reg + add]);
15594 used_prefixes |= (prefixes & PREFIX_DATA);
15598 if (address_mode == mode_64bit)
15599 oappend (names64[modrm.reg + add]);
15601 oappend (names32[modrm.reg + add]);
15605 if ((modrm.reg + add) > 0x7)
15610 oappend (names_mask[modrm.reg + add]);
15613 oappend (INTERNAL_DISASSEMBLER_ERROR);
15626 FETCH_DATA (the_info, codep + 8);
15627 a = *codep++ & 0xff;
15628 a |= (*codep++ & 0xff) << 8;
15629 a |= (*codep++ & 0xff) << 16;
15630 a |= (*codep++ & 0xffu) << 24;
15631 b = *codep++ & 0xff;
15632 b |= (*codep++ & 0xff) << 8;
15633 b |= (*codep++ & 0xff) << 16;
15634 b |= (*codep++ & 0xffu) << 24;
15635 x = a + ((bfd_vma) b << 32);
15643 static bfd_signed_vma
15646 bfd_signed_vma x = 0;
15648 FETCH_DATA (the_info, codep + 4);
15649 x = *codep++ & (bfd_signed_vma) 0xff;
15650 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15651 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15652 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15656 static bfd_signed_vma
15659 bfd_signed_vma x = 0;
15661 FETCH_DATA (the_info, codep + 4);
15662 x = *codep++ & (bfd_signed_vma) 0xff;
15663 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15664 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15665 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15667 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15677 FETCH_DATA (the_info, codep + 2);
15678 x = *codep++ & 0xff;
15679 x |= (*codep++ & 0xff) << 8;
15684 set_op (bfd_vma op, int riprel)
15686 op_index[op_ad] = op_ad;
15687 if (address_mode == mode_64bit)
15689 op_address[op_ad] = op;
15690 op_riprel[op_ad] = riprel;
15694 /* Mask to get a 32-bit address. */
15695 op_address[op_ad] = op & 0xffffffff;
15696 op_riprel[op_ad] = riprel & 0xffffffff;
15701 OP_REG (int code, int sizeflag)
15708 case es_reg: case ss_reg: case cs_reg:
15709 case ds_reg: case fs_reg: case gs_reg:
15710 oappend (names_seg[code - es_reg]);
15722 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15723 case sp_reg: case bp_reg: case si_reg: case di_reg:
15724 s = names16[code - ax_reg + add];
15726 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15727 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15730 s = names8rex[code - al_reg + add];
15732 s = names8[code - al_reg];
15734 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15735 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15736 if (address_mode == mode_64bit
15737 && ((sizeflag & DFLAG) || (rex & REX_W)))
15739 s = names64[code - rAX_reg + add];
15742 code += eAX_reg - rAX_reg;
15743 /* Fall through. */
15744 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15745 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15748 s = names64[code - eAX_reg + add];
15751 if (sizeflag & DFLAG)
15752 s = names32[code - eAX_reg + add];
15754 s = names16[code - eAX_reg + add];
15755 used_prefixes |= (prefixes & PREFIX_DATA);
15759 s = INTERNAL_DISASSEMBLER_ERROR;
15766 OP_IMREG (int code, int sizeflag)
15778 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15779 case sp_reg: case bp_reg: case si_reg: case di_reg:
15780 s = names16[code - ax_reg];
15782 case es_reg: case ss_reg: case cs_reg:
15783 case ds_reg: case fs_reg: case gs_reg:
15784 s = names_seg[code - es_reg];
15786 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15787 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15790 s = names8rex[code - al_reg];
15792 s = names8[code - al_reg];
15794 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15795 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15798 s = names64[code - eAX_reg];
15801 if (sizeflag & DFLAG)
15802 s = names32[code - eAX_reg];
15804 s = names16[code - eAX_reg];
15805 used_prefixes |= (prefixes & PREFIX_DATA);
15808 case z_mode_ax_reg:
15809 if ((rex & REX_W) || (sizeflag & DFLAG))
15813 if (!(rex & REX_W))
15814 used_prefixes |= (prefixes & PREFIX_DATA);
15817 s = INTERNAL_DISASSEMBLER_ERROR;
15824 OP_I (int bytemode, int sizeflag)
15827 bfd_signed_vma mask = -1;
15832 FETCH_DATA (the_info, codep + 1);
15837 if (address_mode == mode_64bit)
15842 /* Fall through. */
15849 if (sizeflag & DFLAG)
15859 used_prefixes |= (prefixes & PREFIX_DATA);
15871 oappend (INTERNAL_DISASSEMBLER_ERROR);
15876 scratchbuf[0] = '$';
15877 print_operand_value (scratchbuf + 1, 1, op);
15878 oappend_maybe_intel (scratchbuf);
15879 scratchbuf[0] = '\0';
15883 OP_I64 (int bytemode, int sizeflag)
15886 bfd_signed_vma mask = -1;
15888 if (address_mode != mode_64bit)
15890 OP_I (bytemode, sizeflag);
15897 FETCH_DATA (the_info, codep + 1);
15907 if (sizeflag & DFLAG)
15917 used_prefixes |= (prefixes & PREFIX_DATA);
15925 oappend (INTERNAL_DISASSEMBLER_ERROR);
15930 scratchbuf[0] = '$';
15931 print_operand_value (scratchbuf + 1, 1, op);
15932 oappend_maybe_intel (scratchbuf);
15933 scratchbuf[0] = '\0';
15937 OP_sI (int bytemode, int sizeflag)
15945 FETCH_DATA (the_info, codep + 1);
15947 if ((op & 0x80) != 0)
15949 if (bytemode == b_T_mode)
15951 if (address_mode != mode_64bit
15952 || !((sizeflag & DFLAG) || (rex & REX_W)))
15954 /* The operand-size prefix is overridden by a REX prefix. */
15955 if ((sizeflag & DFLAG) || (rex & REX_W))
15963 if (!(rex & REX_W))
15965 if (sizeflag & DFLAG)
15973 /* The operand-size prefix is overridden by a REX prefix. */
15974 if ((sizeflag & DFLAG) || (rex & REX_W))
15980 oappend (INTERNAL_DISASSEMBLER_ERROR);
15984 scratchbuf[0] = '$';
15985 print_operand_value (scratchbuf + 1, 1, op);
15986 oappend_maybe_intel (scratchbuf);
15990 OP_J (int bytemode, int sizeflag)
15994 bfd_vma segment = 0;
15999 FETCH_DATA (the_info, codep + 1);
16001 if ((disp & 0x80) != 0)
16005 if (isa64 == amd64)
16007 if ((sizeflag & DFLAG)
16008 || (address_mode == mode_64bit
16009 && (isa64 != amd64 || (rex & REX_W))))
16014 if ((disp & 0x8000) != 0)
16016 /* In 16bit mode, address is wrapped around at 64k within
16017 the same segment. Otherwise, a data16 prefix on a jump
16018 instruction means that the pc is masked to 16 bits after
16019 the displacement is added! */
16021 if ((prefixes & PREFIX_DATA) == 0)
16022 segment = ((start_pc + (codep - start_codep))
16023 & ~((bfd_vma) 0xffff));
16025 if (address_mode != mode_64bit
16026 || (isa64 == amd64 && !(rex & REX_W)))
16027 used_prefixes |= (prefixes & PREFIX_DATA);
16030 oappend (INTERNAL_DISASSEMBLER_ERROR);
16033 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16035 print_operand_value (scratchbuf, 1, disp);
16036 oappend (scratchbuf);
16040 OP_SEG (int bytemode, int sizeflag)
16042 if (bytemode == w_mode)
16043 oappend (names_seg[modrm.reg]);
16045 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16049 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16053 if (sizeflag & DFLAG)
16063 used_prefixes |= (prefixes & PREFIX_DATA);
16065 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16067 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16068 oappend (scratchbuf);
16072 OP_OFF (int bytemode, int sizeflag)
16076 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16077 intel_operand_size (bytemode, sizeflag);
16080 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16087 if (!active_seg_prefix)
16089 oappend (names_seg[ds_reg - es_reg]);
16093 print_operand_value (scratchbuf, 1, off);
16094 oappend (scratchbuf);
16098 OP_OFF64 (int bytemode, int sizeflag)
16102 if (address_mode != mode_64bit
16103 || (prefixes & PREFIX_ADDR))
16105 OP_OFF (bytemode, sizeflag);
16109 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16110 intel_operand_size (bytemode, sizeflag);
16117 if (!active_seg_prefix)
16119 oappend (names_seg[ds_reg - es_reg]);
16123 print_operand_value (scratchbuf, 1, off);
16124 oappend (scratchbuf);
16128 ptr_reg (int code, int sizeflag)
16132 *obufp++ = open_char;
16133 used_prefixes |= (prefixes & PREFIX_ADDR);
16134 if (address_mode == mode_64bit)
16136 if (!(sizeflag & AFLAG))
16137 s = names32[code - eAX_reg];
16139 s = names64[code - eAX_reg];
16141 else if (sizeflag & AFLAG)
16142 s = names32[code - eAX_reg];
16144 s = names16[code - eAX_reg];
16146 *obufp++ = close_char;
16151 OP_ESreg (int code, int sizeflag)
16157 case 0x6d: /* insw/insl */
16158 intel_operand_size (z_mode, sizeflag);
16160 case 0xa5: /* movsw/movsl/movsq */
16161 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16162 case 0xab: /* stosw/stosl */
16163 case 0xaf: /* scasw/scasl */
16164 intel_operand_size (v_mode, sizeflag);
16167 intel_operand_size (b_mode, sizeflag);
16170 oappend_maybe_intel ("%es:");
16171 ptr_reg (code, sizeflag);
16175 OP_DSreg (int code, int sizeflag)
16181 case 0x6f: /* outsw/outsl */
16182 intel_operand_size (z_mode, sizeflag);
16184 case 0xa5: /* movsw/movsl/movsq */
16185 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16186 case 0xad: /* lodsw/lodsl/lodsq */
16187 intel_operand_size (v_mode, sizeflag);
16190 intel_operand_size (b_mode, sizeflag);
16193 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16194 default segment register DS is printed. */
16195 if (!active_seg_prefix)
16196 active_seg_prefix = PREFIX_DS;
16198 ptr_reg (code, sizeflag);
16202 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16210 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16212 all_prefixes[last_lock_prefix] = 0;
16213 used_prefixes |= PREFIX_LOCK;
16218 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16219 oappend_maybe_intel (scratchbuf);
16223 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16232 sprintf (scratchbuf, "db%d", modrm.reg + add);
16234 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16235 oappend (scratchbuf);
16239 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16241 sprintf (scratchbuf, "%%tr%d", modrm.reg);
16242 oappend_maybe_intel (scratchbuf);
16246 OP_R (int bytemode, int sizeflag)
16248 /* Skip mod/rm byte. */
16251 OP_E_register (bytemode, sizeflag);
16255 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16257 int reg = modrm.reg;
16258 const char **names;
16260 used_prefixes |= (prefixes & PREFIX_DATA);
16261 if (prefixes & PREFIX_DATA)
16270 oappend (names[reg]);
16274 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16276 int reg = modrm.reg;
16277 const char **names;
16289 && bytemode != xmm_mode
16290 && bytemode != xmmq_mode
16291 && bytemode != evex_half_bcst_xmmq_mode
16292 && bytemode != ymm_mode
16293 && bytemode != scalar_mode)
16295 switch (vex.length)
16302 || (bytemode != vex_vsib_q_w_dq_mode
16303 && bytemode != vex_vsib_q_w_d_mode))
16315 else if (bytemode == xmmq_mode
16316 || bytemode == evex_half_bcst_xmmq_mode)
16318 switch (vex.length)
16331 else if (bytemode == ymm_mode)
16335 oappend (names[reg]);
16339 OP_EM (int bytemode, int sizeflag)
16342 const char **names;
16344 if (modrm.mod != 3)
16347 && (bytemode == v_mode || bytemode == v_swap_mode))
16349 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16350 used_prefixes |= (prefixes & PREFIX_DATA);
16352 OP_E (bytemode, sizeflag);
16356 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16359 /* Skip mod/rm byte. */
16362 used_prefixes |= (prefixes & PREFIX_DATA);
16364 if (prefixes & PREFIX_DATA)
16373 oappend (names[reg]);
16376 /* cvt* are the only instructions in sse2 which have
16377 both SSE and MMX operands and also have 0x66 prefix
16378 in their opcode. 0x66 was originally used to differentiate
16379 between SSE and MMX instruction(operands). So we have to handle the
16380 cvt* separately using OP_EMC and OP_MXC */
16382 OP_EMC (int bytemode, int sizeflag)
16384 if (modrm.mod != 3)
16386 if (intel_syntax && bytemode == v_mode)
16388 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16389 used_prefixes |= (prefixes & PREFIX_DATA);
16391 OP_E (bytemode, sizeflag);
16395 /* Skip mod/rm byte. */
16398 used_prefixes |= (prefixes & PREFIX_DATA);
16399 oappend (names_mm[modrm.rm]);
16403 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16405 used_prefixes |= (prefixes & PREFIX_DATA);
16406 oappend (names_mm[modrm.reg]);
16410 OP_EX (int bytemode, int sizeflag)
16413 const char **names;
16415 /* Skip mod/rm byte. */
16419 if (modrm.mod != 3)
16421 OP_E_memory (bytemode, sizeflag);
16436 if ((sizeflag & SUFFIX_ALWAYS)
16437 && (bytemode == x_swap_mode
16438 || bytemode == d_swap_mode
16439 || bytemode == d_scalar_swap_mode
16440 || bytemode == q_swap_mode
16441 || bytemode == q_scalar_swap_mode))
16445 && bytemode != xmm_mode
16446 && bytemode != xmmdw_mode
16447 && bytemode != xmmqd_mode
16448 && bytemode != xmm_mb_mode
16449 && bytemode != xmm_mw_mode
16450 && bytemode != xmm_md_mode
16451 && bytemode != xmm_mq_mode
16452 && bytemode != xmm_mdq_mode
16453 && bytemode != xmmq_mode
16454 && bytemode != evex_half_bcst_xmmq_mode
16455 && bytemode != ymm_mode
16456 && bytemode != d_scalar_mode
16457 && bytemode != d_scalar_swap_mode
16458 && bytemode != q_scalar_mode
16459 && bytemode != q_scalar_swap_mode
16460 && bytemode != vex_scalar_w_dq_mode)
16462 switch (vex.length)
16477 else if (bytemode == xmmq_mode
16478 || bytemode == evex_half_bcst_xmmq_mode)
16480 switch (vex.length)
16493 else if (bytemode == ymm_mode)
16497 oappend (names[reg]);
16501 OP_MS (int bytemode, int sizeflag)
16503 if (modrm.mod == 3)
16504 OP_EM (bytemode, sizeflag);
16510 OP_XS (int bytemode, int sizeflag)
16512 if (modrm.mod == 3)
16513 OP_EX (bytemode, sizeflag);
16519 OP_M (int bytemode, int sizeflag)
16521 if (modrm.mod == 3)
16522 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16525 OP_E (bytemode, sizeflag);
16529 OP_0f07 (int bytemode, int sizeflag)
16531 if (modrm.mod != 3 || modrm.rm != 0)
16534 OP_E (bytemode, sizeflag);
16537 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16538 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16541 NOP_Fixup1 (int bytemode, int sizeflag)
16543 if ((prefixes & PREFIX_DATA) != 0
16546 && address_mode == mode_64bit))
16547 OP_REG (bytemode, sizeflag);
16549 strcpy (obuf, "nop");
16553 NOP_Fixup2 (int bytemode, int sizeflag)
16555 if ((prefixes & PREFIX_DATA) != 0
16558 && address_mode == mode_64bit))
16559 OP_IMREG (bytemode, sizeflag);
16562 static const char *const Suffix3DNow[] = {
16563 /* 00 */ NULL, NULL, NULL, NULL,
16564 /* 04 */ NULL, NULL, NULL, NULL,
16565 /* 08 */ NULL, NULL, NULL, NULL,
16566 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
16567 /* 10 */ NULL, NULL, NULL, NULL,
16568 /* 14 */ NULL, NULL, NULL, NULL,
16569 /* 18 */ NULL, NULL, NULL, NULL,
16570 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
16571 /* 20 */ NULL, NULL, NULL, NULL,
16572 /* 24 */ NULL, NULL, NULL, NULL,
16573 /* 28 */ NULL, NULL, NULL, NULL,
16574 /* 2C */ NULL, NULL, NULL, NULL,
16575 /* 30 */ NULL, NULL, NULL, NULL,
16576 /* 34 */ NULL, NULL, NULL, NULL,
16577 /* 38 */ NULL, NULL, NULL, NULL,
16578 /* 3C */ NULL, NULL, NULL, NULL,
16579 /* 40 */ NULL, NULL, NULL, NULL,
16580 /* 44 */ NULL, NULL, NULL, NULL,
16581 /* 48 */ NULL, NULL, NULL, NULL,
16582 /* 4C */ NULL, NULL, NULL, NULL,
16583 /* 50 */ NULL, NULL, NULL, NULL,
16584 /* 54 */ NULL, NULL, NULL, NULL,
16585 /* 58 */ NULL, NULL, NULL, NULL,
16586 /* 5C */ NULL, NULL, NULL, NULL,
16587 /* 60 */ NULL, NULL, NULL, NULL,
16588 /* 64 */ NULL, NULL, NULL, NULL,
16589 /* 68 */ NULL, NULL, NULL, NULL,
16590 /* 6C */ NULL, NULL, NULL, NULL,
16591 /* 70 */ NULL, NULL, NULL, NULL,
16592 /* 74 */ NULL, NULL, NULL, NULL,
16593 /* 78 */ NULL, NULL, NULL, NULL,
16594 /* 7C */ NULL, NULL, NULL, NULL,
16595 /* 80 */ NULL, NULL, NULL, NULL,
16596 /* 84 */ NULL, NULL, NULL, NULL,
16597 /* 88 */ NULL, NULL, "pfnacc", NULL,
16598 /* 8C */ NULL, NULL, "pfpnacc", NULL,
16599 /* 90 */ "pfcmpge", NULL, NULL, NULL,
16600 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
16601 /* 98 */ NULL, NULL, "pfsub", NULL,
16602 /* 9C */ NULL, NULL, "pfadd", NULL,
16603 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
16604 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
16605 /* A8 */ NULL, NULL, "pfsubr", NULL,
16606 /* AC */ NULL, NULL, "pfacc", NULL,
16607 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
16608 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
16609 /* B8 */ NULL, NULL, NULL, "pswapd",
16610 /* BC */ NULL, NULL, NULL, "pavgusb",
16611 /* C0 */ NULL, NULL, NULL, NULL,
16612 /* C4 */ NULL, NULL, NULL, NULL,
16613 /* C8 */ NULL, NULL, NULL, NULL,
16614 /* CC */ NULL, NULL, NULL, NULL,
16615 /* D0 */ NULL, NULL, NULL, NULL,
16616 /* D4 */ NULL, NULL, NULL, NULL,
16617 /* D8 */ NULL, NULL, NULL, NULL,
16618 /* DC */ NULL, NULL, NULL, NULL,
16619 /* E0 */ NULL, NULL, NULL, NULL,
16620 /* E4 */ NULL, NULL, NULL, NULL,
16621 /* E8 */ NULL, NULL, NULL, NULL,
16622 /* EC */ NULL, NULL, NULL, NULL,
16623 /* F0 */ NULL, NULL, NULL, NULL,
16624 /* F4 */ NULL, NULL, NULL, NULL,
16625 /* F8 */ NULL, NULL, NULL, NULL,
16626 /* FC */ NULL, NULL, NULL, NULL,
16630 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16632 const char *mnemonic;
16634 FETCH_DATA (the_info, codep + 1);
16635 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16636 place where an 8-bit immediate would normally go. ie. the last
16637 byte of the instruction. */
16638 obufp = mnemonicendp;
16639 mnemonic = Suffix3DNow[*codep++ & 0xff];
16641 oappend (mnemonic);
16644 /* Since a variable sized modrm/sib chunk is between the start
16645 of the opcode (0x0f0f) and the opcode suffix, we need to do
16646 all the modrm processing first, and don't know until now that
16647 we have a bad opcode. This necessitates some cleaning up. */
16648 op_out[0][0] = '\0';
16649 op_out[1][0] = '\0';
16652 mnemonicendp = obufp;
16655 static struct op simd_cmp_op[] =
16657 { STRING_COMMA_LEN ("eq") },
16658 { STRING_COMMA_LEN ("lt") },
16659 { STRING_COMMA_LEN ("le") },
16660 { STRING_COMMA_LEN ("unord") },
16661 { STRING_COMMA_LEN ("neq") },
16662 { STRING_COMMA_LEN ("nlt") },
16663 { STRING_COMMA_LEN ("nle") },
16664 { STRING_COMMA_LEN ("ord") }
16668 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16670 unsigned int cmp_type;
16672 FETCH_DATA (the_info, codep + 1);
16673 cmp_type = *codep++ & 0xff;
16674 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16677 char *p = mnemonicendp - 2;
16681 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16682 mnemonicendp += simd_cmp_op[cmp_type].len;
16686 /* We have a reserved extension byte. Output it directly. */
16687 scratchbuf[0] = '$';
16688 print_operand_value (scratchbuf + 1, 1, cmp_type);
16689 oappend_maybe_intel (scratchbuf);
16690 scratchbuf[0] = '\0';
16695 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16696 int sizeflag ATTRIBUTE_UNUSED)
16698 /* mwaitx %eax,%ecx,%ebx */
16701 const char **names = (address_mode == mode_64bit
16702 ? names64 : names32);
16703 strcpy (op_out[0], names[0]);
16704 strcpy (op_out[1], names[1]);
16705 strcpy (op_out[2], names[3]);
16706 two_source_ops = 1;
16708 /* Skip mod/rm byte. */
16714 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16715 int sizeflag ATTRIBUTE_UNUSED)
16717 /* mwait %eax,%ecx */
16720 const char **names = (address_mode == mode_64bit
16721 ? names64 : names32);
16722 strcpy (op_out[0], names[0]);
16723 strcpy (op_out[1], names[1]);
16724 two_source_ops = 1;
16726 /* Skip mod/rm byte. */
16732 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16733 int sizeflag ATTRIBUTE_UNUSED)
16735 /* monitor %eax,%ecx,%edx" */
16738 const char **op1_names;
16739 const char **names = (address_mode == mode_64bit
16740 ? names64 : names32);
16742 if (!(prefixes & PREFIX_ADDR))
16743 op1_names = (address_mode == mode_16bit
16744 ? names16 : names);
16747 /* Remove "addr16/addr32". */
16748 all_prefixes[last_addr_prefix] = 0;
16749 op1_names = (address_mode != mode_32bit
16750 ? names32 : names16);
16751 used_prefixes |= PREFIX_ADDR;
16753 strcpy (op_out[0], op1_names[0]);
16754 strcpy (op_out[1], names[1]);
16755 strcpy (op_out[2], names[2]);
16756 two_source_ops = 1;
16758 /* Skip mod/rm byte. */
16766 /* Throw away prefixes and 1st. opcode byte. */
16767 codep = insn_codep + 1;
16772 REP_Fixup (int bytemode, int sizeflag)
16774 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16776 if (prefixes & PREFIX_REPZ)
16777 all_prefixes[last_repz_prefix] = REP_PREFIX;
16784 OP_IMREG (bytemode, sizeflag);
16787 OP_ESreg (bytemode, sizeflag);
16790 OP_DSreg (bytemode, sizeflag);
16798 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16802 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16804 if (prefixes & PREFIX_REPNZ)
16805 all_prefixes[last_repnz_prefix] = BND_PREFIX;
16808 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16812 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16813 int sizeflag ATTRIBUTE_UNUSED)
16815 if (active_seg_prefix == PREFIX_DS
16816 && (address_mode != mode_64bit || last_data_prefix < 0))
16818 /* NOTRACK prefix is only valid on indirect branch instructions.
16819 NB: DATA prefix is unsupported for Intel64. */
16820 active_seg_prefix = 0;
16821 all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
16825 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16826 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16830 HLE_Fixup1 (int bytemode, int sizeflag)
16833 && (prefixes & PREFIX_LOCK) != 0)
16835 if (prefixes & PREFIX_REPZ)
16836 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16837 if (prefixes & PREFIX_REPNZ)
16838 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16841 OP_E (bytemode, sizeflag);
16844 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16845 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16849 HLE_Fixup2 (int bytemode, int sizeflag)
16851 if (modrm.mod != 3)
16853 if (prefixes & PREFIX_REPZ)
16854 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16855 if (prefixes & PREFIX_REPNZ)
16856 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16859 OP_E (bytemode, sizeflag);
16862 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16863 "xrelease" for memory operand. No check for LOCK prefix. */
16866 HLE_Fixup3 (int bytemode, int sizeflag)
16869 && last_repz_prefix > last_repnz_prefix
16870 && (prefixes & PREFIX_REPZ) != 0)
16871 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16873 OP_E (bytemode, sizeflag);
16877 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16882 /* Change cmpxchg8b to cmpxchg16b. */
16883 char *p = mnemonicendp - 2;
16884 mnemonicendp = stpcpy (p, "16b");
16887 else if ((prefixes & PREFIX_LOCK) != 0)
16889 if (prefixes & PREFIX_REPZ)
16890 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16891 if (prefixes & PREFIX_REPNZ)
16892 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16895 OP_M (bytemode, sizeflag);
16899 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16901 const char **names;
16905 switch (vex.length)
16919 oappend (names[reg]);
16923 CRC32_Fixup (int bytemode, int sizeflag)
16925 /* Add proper suffix to "crc32". */
16926 char *p = mnemonicendp;
16945 if (sizeflag & DFLAG)
16949 used_prefixes |= (prefixes & PREFIX_DATA);
16953 oappend (INTERNAL_DISASSEMBLER_ERROR);
16960 if (modrm.mod == 3)
16964 /* Skip mod/rm byte. */
16969 add = (rex & REX_B) ? 8 : 0;
16970 if (bytemode == b_mode)
16974 oappend (names8rex[modrm.rm + add]);
16976 oappend (names8[modrm.rm + add]);
16982 oappend (names64[modrm.rm + add]);
16983 else if ((prefixes & PREFIX_DATA))
16984 oappend (names16[modrm.rm + add]);
16986 oappend (names32[modrm.rm + add]);
16990 OP_E (bytemode, sizeflag);
16994 FXSAVE_Fixup (int bytemode, int sizeflag)
16996 /* Add proper suffix to "fxsave" and "fxrstor". */
17000 char *p = mnemonicendp;
17006 OP_M (bytemode, sizeflag);
17010 PCMPESTR_Fixup (int bytemode, int sizeflag)
17012 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
17015 char *p = mnemonicendp;
17020 else if (sizeflag & SUFFIX_ALWAYS)
17027 OP_EX (bytemode, sizeflag);
17030 /* Display the destination register operand for instructions with
17034 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17037 const char **names;
17045 reg = vex.register_specifier;
17052 if (bytemode == vex_scalar_mode)
17054 oappend (names_xmm[reg]);
17058 switch (vex.length)
17065 case vex_vsib_q_w_dq_mode:
17066 case vex_vsib_q_w_d_mode:
17082 names = names_mask;
17096 case vex_vsib_q_w_dq_mode:
17097 case vex_vsib_q_w_d_mode:
17098 names = vex.w ? names_ymm : names_xmm;
17107 names = names_mask;
17110 /* See PR binutils/20893 for a reproducer. */
17122 oappend (names[reg]);
17125 /* Get the VEX immediate byte without moving codep. */
17127 static unsigned char
17128 get_vex_imm8 (int sizeflag, int opnum)
17130 int bytes_before_imm = 0;
17132 if (modrm.mod != 3)
17134 /* There are SIB/displacement bytes. */
17135 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17137 /* 32/64 bit address mode */
17138 int base = modrm.rm;
17140 /* Check SIB byte. */
17143 FETCH_DATA (the_info, codep + 1);
17145 /* When decoding the third source, don't increase
17146 bytes_before_imm as this has already been incremented
17147 by one in OP_E_memory while decoding the second
17150 bytes_before_imm++;
17153 /* Don't increase bytes_before_imm when decoding the third source,
17154 it has already been incremented by OP_E_memory while decoding
17155 the second source operand. */
17161 /* When modrm.rm == 5 or modrm.rm == 4 and base in
17162 SIB == 5, there is a 4 byte displacement. */
17164 /* No displacement. */
17166 /* Fall through. */
17168 /* 4 byte displacement. */
17169 bytes_before_imm += 4;
17172 /* 1 byte displacement. */
17173 bytes_before_imm++;
17180 /* 16 bit address mode */
17181 /* Don't increase bytes_before_imm when decoding the third source,
17182 it has already been incremented by OP_E_memory while decoding
17183 the second source operand. */
17189 /* When modrm.rm == 6, there is a 2 byte displacement. */
17191 /* No displacement. */
17193 /* Fall through. */
17195 /* 2 byte displacement. */
17196 bytes_before_imm += 2;
17199 /* 1 byte displacement: when decoding the third source,
17200 don't increase bytes_before_imm as this has already
17201 been incremented by one in OP_E_memory while decoding
17202 the second source operand. */
17204 bytes_before_imm++;
17212 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17213 return codep [bytes_before_imm];
17217 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17219 const char **names;
17221 if (reg == -1 && modrm.mod != 3)
17223 OP_E_memory (bytemode, sizeflag);
17235 else if (reg > 7 && address_mode != mode_64bit)
17239 switch (vex.length)
17250 oappend (names[reg]);
17254 OP_EX_VexImmW (int bytemode, int sizeflag)
17257 static unsigned char vex_imm8;
17259 if (vex_w_done == 0)
17263 /* Skip mod/rm byte. */
17267 vex_imm8 = get_vex_imm8 (sizeflag, 0);
17270 reg = vex_imm8 >> 4;
17272 OP_EX_VexReg (bytemode, sizeflag, reg);
17274 else if (vex_w_done == 1)
17279 reg = vex_imm8 >> 4;
17281 OP_EX_VexReg (bytemode, sizeflag, reg);
17285 /* Output the imm8 directly. */
17286 scratchbuf[0] = '$';
17287 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17288 oappend_maybe_intel (scratchbuf);
17289 scratchbuf[0] = '\0';
17295 OP_Vex_2src (int bytemode, int sizeflag)
17297 if (modrm.mod == 3)
17299 int reg = modrm.rm;
17303 oappend (names_xmm[reg]);
17308 && (bytemode == v_mode || bytemode == v_swap_mode))
17310 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17311 used_prefixes |= (prefixes & PREFIX_DATA);
17313 OP_E (bytemode, sizeflag);
17318 OP_Vex_2src_1 (int bytemode, int sizeflag)
17320 if (modrm.mod == 3)
17322 /* Skip mod/rm byte. */
17328 oappend (names_xmm[vex.register_specifier]);
17330 OP_Vex_2src (bytemode, sizeflag);
17334 OP_Vex_2src_2 (int bytemode, int sizeflag)
17337 OP_Vex_2src (bytemode, sizeflag);
17339 oappend (names_xmm[vex.register_specifier]);
17343 OP_EX_VexW (int bytemode, int sizeflag)
17351 /* Skip mod/rm byte. */
17356 reg = get_vex_imm8 (sizeflag, 0) >> 4;
17361 reg = get_vex_imm8 (sizeflag, 1) >> 4;
17364 OP_EX_VexReg (bytemode, sizeflag, reg);
17368 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17369 int sizeflag ATTRIBUTE_UNUSED)
17371 /* Skip the immediate byte and check for invalid bits. */
17372 FETCH_DATA (the_info, codep + 1);
17373 if (*codep++ & 0xf)
17378 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17381 const char **names;
17383 FETCH_DATA (the_info, codep + 1);
17386 if (bytemode != x_mode)
17393 if (reg > 7 && address_mode != mode_64bit)
17396 switch (vex.length)
17407 oappend (names[reg]);
17411 OP_XMM_VexW (int bytemode, int sizeflag)
17413 /* Turn off the REX.W bit since it is used for swapping operands
17416 OP_XMM (bytemode, sizeflag);
17420 OP_EX_Vex (int bytemode, int sizeflag)
17422 if (modrm.mod != 3)
17424 if (vex.register_specifier != 0)
17428 OP_EX (bytemode, sizeflag);
17432 OP_XMM_Vex (int bytemode, int sizeflag)
17434 if (modrm.mod != 3)
17436 if (vex.register_specifier != 0)
17440 OP_XMM (bytemode, sizeflag);
17444 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17446 switch (vex.length)
17449 mnemonicendp = stpcpy (obuf, "vzeroupper");
17452 mnemonicendp = stpcpy (obuf, "vzeroall");
17459 static struct op vex_cmp_op[] =
17461 { STRING_COMMA_LEN ("eq") },
17462 { STRING_COMMA_LEN ("lt") },
17463 { STRING_COMMA_LEN ("le") },
17464 { STRING_COMMA_LEN ("unord") },
17465 { STRING_COMMA_LEN ("neq") },
17466 { STRING_COMMA_LEN ("nlt") },
17467 { STRING_COMMA_LEN ("nle") },
17468 { STRING_COMMA_LEN ("ord") },
17469 { STRING_COMMA_LEN ("eq_uq") },
17470 { STRING_COMMA_LEN ("nge") },
17471 { STRING_COMMA_LEN ("ngt") },
17472 { STRING_COMMA_LEN ("false") },
17473 { STRING_COMMA_LEN ("neq_oq") },
17474 { STRING_COMMA_LEN ("ge") },
17475 { STRING_COMMA_LEN ("gt") },
17476 { STRING_COMMA_LEN ("true") },
17477 { STRING_COMMA_LEN ("eq_os") },
17478 { STRING_COMMA_LEN ("lt_oq") },
17479 { STRING_COMMA_LEN ("le_oq") },
17480 { STRING_COMMA_LEN ("unord_s") },
17481 { STRING_COMMA_LEN ("neq_us") },
17482 { STRING_COMMA_LEN ("nlt_uq") },
17483 { STRING_COMMA_LEN ("nle_uq") },
17484 { STRING_COMMA_LEN ("ord_s") },
17485 { STRING_COMMA_LEN ("eq_us") },
17486 { STRING_COMMA_LEN ("nge_uq") },
17487 { STRING_COMMA_LEN ("ngt_uq") },
17488 { STRING_COMMA_LEN ("false_os") },
17489 { STRING_COMMA_LEN ("neq_os") },
17490 { STRING_COMMA_LEN ("ge_oq") },
17491 { STRING_COMMA_LEN ("gt_oq") },
17492 { STRING_COMMA_LEN ("true_us") },
17496 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17498 unsigned int cmp_type;
17500 FETCH_DATA (the_info, codep + 1);
17501 cmp_type = *codep++ & 0xff;
17502 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17505 char *p = mnemonicendp - 2;
17509 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17510 mnemonicendp += vex_cmp_op[cmp_type].len;
17514 /* We have a reserved extension byte. Output it directly. */
17515 scratchbuf[0] = '$';
17516 print_operand_value (scratchbuf + 1, 1, cmp_type);
17517 oappend_maybe_intel (scratchbuf);
17518 scratchbuf[0] = '\0';
17523 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17524 int sizeflag ATTRIBUTE_UNUSED)
17526 unsigned int cmp_type;
17531 FETCH_DATA (the_info, codep + 1);
17532 cmp_type = *codep++ & 0xff;
17533 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17534 If it's the case, print suffix, otherwise - print the immediate. */
17535 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17540 char *p = mnemonicendp - 2;
17542 /* vpcmp* can have both one- and two-lettered suffix. */
17556 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17557 mnemonicendp += simd_cmp_op[cmp_type].len;
17561 /* We have a reserved extension byte. Output it directly. */
17562 scratchbuf[0] = '$';
17563 print_operand_value (scratchbuf + 1, 1, cmp_type);
17564 oappend_maybe_intel (scratchbuf);
17565 scratchbuf[0] = '\0';
17569 static const struct op pclmul_op[] =
17571 { STRING_COMMA_LEN ("lql") },
17572 { STRING_COMMA_LEN ("hql") },
17573 { STRING_COMMA_LEN ("lqh") },
17574 { STRING_COMMA_LEN ("hqh") }
17578 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17579 int sizeflag ATTRIBUTE_UNUSED)
17581 unsigned int pclmul_type;
17583 FETCH_DATA (the_info, codep + 1);
17584 pclmul_type = *codep++ & 0xff;
17585 switch (pclmul_type)
17596 if (pclmul_type < ARRAY_SIZE (pclmul_op))
17599 char *p = mnemonicendp - 3;
17604 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17605 mnemonicendp += pclmul_op[pclmul_type].len;
17609 /* We have a reserved extension byte. Output it directly. */
17610 scratchbuf[0] = '$';
17611 print_operand_value (scratchbuf + 1, 1, pclmul_type);
17612 oappend_maybe_intel (scratchbuf);
17613 scratchbuf[0] = '\0';
17618 MOVBE_Fixup (int bytemode, int sizeflag)
17620 /* Add proper suffix to "movbe". */
17621 char *p = mnemonicendp;
17630 if (sizeflag & SUFFIX_ALWAYS)
17636 if (sizeflag & DFLAG)
17640 used_prefixes |= (prefixes & PREFIX_DATA);
17645 oappend (INTERNAL_DISASSEMBLER_ERROR);
17652 OP_M (bytemode, sizeflag);
17656 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17659 const char **names;
17661 /* Skip mod/rm byte. */
17675 oappend (names[reg]);
17679 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17681 const char **names;
17688 oappend (names[vex.register_specifier]);
17692 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17695 || (bytemode != mask_mode && bytemode != mask_bd_mode))
17699 if ((rex & REX_R) != 0 || !vex.r)
17705 oappend (names_mask [modrm.reg]);
17709 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17712 || (bytemode != evex_rounding_mode
17713 && bytemode != evex_sae_mode))
17715 if (modrm.mod == 3 && vex.b)
17718 case evex_rounding_mode:
17719 oappend (names_rounding[vex.ll]);
17721 case evex_sae_mode: