1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2016 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma, disassemble_info *);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma get64 (void);
58 static bfd_signed_vma get32 (void);
59 static bfd_signed_vma get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void OP_Mwaitx (int, int);
106 static void NOP_Fixup1 (int, int);
107 static void NOP_Fixup2 (int, int);
108 static void OP_3DNowSuffix (int, int);
109 static void CMP_Fixup (int, int);
110 static void BadOp (void);
111 static void REP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void OP_LWPCB_E (int, int);
121 static void OP_LWP_E (int, int);
122 static void OP_Vex_2src_1 (int, int);
123 static void OP_Vex_2src_2 (int, int);
125 static void MOVBE_Fixup (int, int);
127 static void OP_Mask (int, int);
130 /* Points to first byte not fetched. */
131 bfd_byte *max_fetched;
132 bfd_byte the_buffer[MAX_MNEM_SIZE];
135 OPCODES_SIGJMP_BUF bailout;
145 enum address_mode address_mode;
147 /* Flags for the prefixes for the current instruction. See below. */
150 /* REX prefix the current instruction. See below. */
152 /* Bits of REX we've already used. */
154 /* REX bits in original REX prefix ignored. */
155 static int rex_ignored;
156 /* Mark parts used in the REX prefix. When we are testing for
157 empty prefix (for 8bit register REX extension), just mask it
158 out. Otherwise test for REX bit is excuse for existence of REX
159 only in case value is nonzero. */
160 #define USED_REX(value) \
165 rex_used |= (value) | REX_OPCODE; \
168 rex_used |= REX_OPCODE; \
171 /* Flags for prefixes which we somehow handled when printing the
172 current instruction. */
173 static int used_prefixes;
175 /* Flags stored in PREFIXES. */
176 #define PREFIX_REPZ 1
177 #define PREFIX_REPNZ 2
178 #define PREFIX_LOCK 4
180 #define PREFIX_SS 0x10
181 #define PREFIX_DS 0x20
182 #define PREFIX_ES 0x40
183 #define PREFIX_FS 0x80
184 #define PREFIX_GS 0x100
185 #define PREFIX_DATA 0x200
186 #define PREFIX_ADDR 0x400
187 #define PREFIX_FWAIT 0x800
189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
190 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
192 #define FETCH_DATA(info, addr) \
193 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
194 ? 1 : fetch_data ((info), (addr)))
197 fetch_data (struct disassemble_info *info, bfd_byte *addr)
200 struct dis_private *priv = (struct dis_private *) info->private_data;
201 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
203 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
204 status = (*info->read_memory_func) (start,
206 addr - priv->max_fetched,
212 /* If we did manage to read at least one byte, then
213 print_insn_i386 will do something sensible. Otherwise, print
214 an error. We do that here because this is where we know
216 if (priv->max_fetched == priv->the_buffer)
217 (*info->memory_error_func) (status, start, info);
218 OPCODES_SIGLONGJMP (priv->bailout, 1);
221 priv->max_fetched = addr;
225 /* Possible values for prefix requirement. */
226 #define PREFIX_IGNORED_SHIFT 16
227 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
228 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
233 /* Opcode prefixes. */
234 #define PREFIX_OPCODE (PREFIX_REPZ \
238 /* Prefixes ignored. */
239 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
240 | PREFIX_IGNORED_REPNZ \
241 | PREFIX_IGNORED_DATA)
243 #define XX { NULL, 0 }
244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
246 #define Eb { OP_E, b_mode }
247 #define Ebnd { OP_E, bnd_mode }
248 #define EbS { OP_E, b_swap_mode }
249 #define Ev { OP_E, v_mode }
250 #define Ev_bnd { OP_E, v_bnd_mode }
251 #define EvS { OP_E, v_swap_mode }
252 #define Ed { OP_E, d_mode }
253 #define Edq { OP_E, dq_mode }
254 #define Edqw { OP_E, dqw_mode }
255 #define EdqwS { OP_E, dqw_swap_mode }
256 #define Edqb { OP_E, dqb_mode }
257 #define Edb { OP_E, db_mode }
258 #define Edw { OP_E, dw_mode }
259 #define Edqd { OP_E, dqd_mode }
260 #define Eq { OP_E, q_mode }
261 #define indirEv { OP_indirE, indir_v_mode }
262 #define indirEp { OP_indirE, f_mode }
263 #define stackEv { OP_E, stack_v_mode }
264 #define Em { OP_E, m_mode }
265 #define Ew { OP_E, w_mode }
266 #define M { OP_M, 0 } /* lea, lgdt, etc. */
267 #define Ma { OP_M, a_mode }
268 #define Mb { OP_M, b_mode }
269 #define Md { OP_M, d_mode }
270 #define Mo { OP_M, o_mode }
271 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
272 #define Mq { OP_M, q_mode }
273 #define Mx { OP_M, x_mode }
274 #define Mxmm { OP_M, xmm_mode }
275 #define Gb { OP_G, b_mode }
276 #define Gbnd { OP_G, bnd_mode }
277 #define Gv { OP_G, v_mode }
278 #define Gd { OP_G, d_mode }
279 #define Gdq { OP_G, dq_mode }
280 #define Gm { OP_G, m_mode }
281 #define Gw { OP_G, w_mode }
282 #define Rd { OP_R, d_mode }
283 #define Rdq { OP_R, dq_mode }
284 #define Rm { OP_R, m_mode }
285 #define Ib { OP_I, b_mode }
286 #define sIb { OP_sI, b_mode } /* sign extened byte */
287 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
288 #define Iv { OP_I, v_mode }
289 #define sIv { OP_sI, v_mode }
290 #define Iq { OP_I, q_mode }
291 #define Iv64 { OP_I64, v_mode }
292 #define Iw { OP_I, w_mode }
293 #define I1 { OP_I, const_1_mode }
294 #define Jb { OP_J, b_mode }
295 #define Jv { OP_J, v_mode }
296 #define Cm { OP_C, m_mode }
297 #define Dm { OP_D, m_mode }
298 #define Td { OP_T, d_mode }
299 #define Skip_MODRM { OP_Skip_MODRM, 0 }
301 #define RMeAX { OP_REG, eAX_reg }
302 #define RMeBX { OP_REG, eBX_reg }
303 #define RMeCX { OP_REG, eCX_reg }
304 #define RMeDX { OP_REG, eDX_reg }
305 #define RMeSP { OP_REG, eSP_reg }
306 #define RMeBP { OP_REG, eBP_reg }
307 #define RMeSI { OP_REG, eSI_reg }
308 #define RMeDI { OP_REG, eDI_reg }
309 #define RMrAX { OP_REG, rAX_reg }
310 #define RMrBX { OP_REG, rBX_reg }
311 #define RMrCX { OP_REG, rCX_reg }
312 #define RMrDX { OP_REG, rDX_reg }
313 #define RMrSP { OP_REG, rSP_reg }
314 #define RMrBP { OP_REG, rBP_reg }
315 #define RMrSI { OP_REG, rSI_reg }
316 #define RMrDI { OP_REG, rDI_reg }
317 #define RMAL { OP_REG, al_reg }
318 #define RMCL { OP_REG, cl_reg }
319 #define RMDL { OP_REG, dl_reg }
320 #define RMBL { OP_REG, bl_reg }
321 #define RMAH { OP_REG, ah_reg }
322 #define RMCH { OP_REG, ch_reg }
323 #define RMDH { OP_REG, dh_reg }
324 #define RMBH { OP_REG, bh_reg }
325 #define RMAX { OP_REG, ax_reg }
326 #define RMDX { OP_REG, dx_reg }
328 #define eAX { OP_IMREG, eAX_reg }
329 #define eBX { OP_IMREG, eBX_reg }
330 #define eCX { OP_IMREG, eCX_reg }
331 #define eDX { OP_IMREG, eDX_reg }
332 #define eSP { OP_IMREG, eSP_reg }
333 #define eBP { OP_IMREG, eBP_reg }
334 #define eSI { OP_IMREG, eSI_reg }
335 #define eDI { OP_IMREG, eDI_reg }
336 #define AL { OP_IMREG, al_reg }
337 #define CL { OP_IMREG, cl_reg }
338 #define DL { OP_IMREG, dl_reg }
339 #define BL { OP_IMREG, bl_reg }
340 #define AH { OP_IMREG, ah_reg }
341 #define CH { OP_IMREG, ch_reg }
342 #define DH { OP_IMREG, dh_reg }
343 #define BH { OP_IMREG, bh_reg }
344 #define AX { OP_IMREG, ax_reg }
345 #define DX { OP_IMREG, dx_reg }
346 #define zAX { OP_IMREG, z_mode_ax_reg }
347 #define indirDX { OP_IMREG, indir_dx_reg }
349 #define Sw { OP_SEG, w_mode }
350 #define Sv { OP_SEG, v_mode }
351 #define Ap { OP_DIR, 0 }
352 #define Ob { OP_OFF64, b_mode }
353 #define Ov { OP_OFF64, v_mode }
354 #define Xb { OP_DSreg, eSI_reg }
355 #define Xv { OP_DSreg, eSI_reg }
356 #define Xz { OP_DSreg, eSI_reg }
357 #define Yb { OP_ESreg, eDI_reg }
358 #define Yv { OP_ESreg, eDI_reg }
359 #define DSBX { OP_DSreg, eBX_reg }
361 #define es { OP_REG, es_reg }
362 #define ss { OP_REG, ss_reg }
363 #define cs { OP_REG, cs_reg }
364 #define ds { OP_REG, ds_reg }
365 #define fs { OP_REG, fs_reg }
366 #define gs { OP_REG, gs_reg }
368 #define MX { OP_MMX, 0 }
369 #define XM { OP_XMM, 0 }
370 #define XMScalar { OP_XMM, scalar_mode }
371 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
372 #define XMM { OP_XMM, xmm_mode }
373 #define XMxmmq { OP_XMM, xmmq_mode }
374 #define EM { OP_EM, v_mode }
375 #define EMS { OP_EM, v_swap_mode }
376 #define EMd { OP_EM, d_mode }
377 #define EMx { OP_EM, x_mode }
378 #define EXw { OP_EX, w_mode }
379 #define EXd { OP_EX, d_mode }
380 #define EXdScalar { OP_EX, d_scalar_mode }
381 #define EXdS { OP_EX, d_swap_mode }
382 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
383 #define EXq { OP_EX, q_mode }
384 #define EXqScalar { OP_EX, q_scalar_mode }
385 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
386 #define EXqS { OP_EX, q_swap_mode }
387 #define EXx { OP_EX, x_mode }
388 #define EXxS { OP_EX, x_swap_mode }
389 #define EXxmm { OP_EX, xmm_mode }
390 #define EXymm { OP_EX, ymm_mode }
391 #define EXxmmq { OP_EX, xmmq_mode }
392 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
393 #define EXxmm_mb { OP_EX, xmm_mb_mode }
394 #define EXxmm_mw { OP_EX, xmm_mw_mode }
395 #define EXxmm_md { OP_EX, xmm_md_mode }
396 #define EXxmm_mq { OP_EX, xmm_mq_mode }
397 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
398 #define EXxmmdw { OP_EX, xmmdw_mode }
399 #define EXxmmqd { OP_EX, xmmqd_mode }
400 #define EXymmq { OP_EX, ymmq_mode }
401 #define EXVexWdq { OP_EX, vex_w_dq_mode }
402 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
403 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
404 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
405 #define MS { OP_MS, v_mode }
406 #define XS { OP_XS, v_mode }
407 #define EMCq { OP_EMC, q_mode }
408 #define MXC { OP_MXC, 0 }
409 #define OPSUF { OP_3DNowSuffix, 0 }
410 #define CMP { CMP_Fixup, 0 }
411 #define XMM0 { XMM_Fixup, 0 }
412 #define FXSAVE { FXSAVE_Fixup, 0 }
413 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
414 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
416 #define Vex { OP_VEX, vex_mode }
417 #define VexScalar { OP_VEX, vex_scalar_mode }
418 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
419 #define Vex128 { OP_VEX, vex128_mode }
420 #define Vex256 { OP_VEX, vex256_mode }
421 #define VexGdq { OP_VEX, dq_mode }
422 #define VexI4 { VEXI4_Fixup, 0}
423 #define EXdVex { OP_EX_Vex, d_mode }
424 #define EXdVexS { OP_EX_Vex, d_swap_mode }
425 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
426 #define EXqVex { OP_EX_Vex, q_mode }
427 #define EXqVexS { OP_EX_Vex, q_swap_mode }
428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
429 #define EXVexW { OP_EX_VexW, x_mode }
430 #define EXdVexW { OP_EX_VexW, d_mode }
431 #define EXqVexW { OP_EX_VexW, q_mode }
432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
433 #define XMVex { OP_XMM_Vex, 0 }
434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
435 #define XMVexW { OP_XMM_VexW, 0 }
436 #define XMVexI4 { OP_REG_VexI4, x_mode }
437 #define PCLMUL { PCLMUL_Fixup, 0 }
438 #define VZERO { VZERO_Fixup, 0 }
439 #define VCMP { VCMP_Fixup, 0 }
440 #define VPCMP { VPCMP_Fixup, 0 }
442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
445 #define XMask { OP_Mask, mask_mode }
446 #define MaskG { OP_G, mask_mode }
447 #define MaskE { OP_E, mask_mode }
448 #define MaskBDE { OP_E, mask_bd_mode }
449 #define MaskR { OP_R, mask_mode }
450 #define MaskVex { OP_VEX, mask_mode }
452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
457 /* Used handle "rep" prefix for string instructions. */
458 #define Xbr { REP_Fixup, eSI_reg }
459 #define Xvr { REP_Fixup, eSI_reg }
460 #define Ybr { REP_Fixup, eDI_reg }
461 #define Yvr { REP_Fixup, eDI_reg }
462 #define Yzr { REP_Fixup, eDI_reg }
463 #define indirDXr { REP_Fixup, indir_dx_reg }
464 #define ALr { REP_Fixup, al_reg }
465 #define eAXr { REP_Fixup, eAX_reg }
467 /* Used handle HLE prefix for lockable instructions. */
468 #define Ebh1 { HLE_Fixup1, b_mode }
469 #define Evh1 { HLE_Fixup1, v_mode }
470 #define Ebh2 { HLE_Fixup2, b_mode }
471 #define Evh2 { HLE_Fixup2, v_mode }
472 #define Ebh3 { HLE_Fixup3, b_mode }
473 #define Evh3 { HLE_Fixup3, v_mode }
475 #define BND { BND_Fixup, 0 }
477 #define cond_jump_flag { NULL, cond_jump_mode }
478 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
480 /* bits in sizeflag */
481 #define SUFFIX_ALWAYS 4
489 /* byte operand with operand swapped */
491 /* byte operand, sign extend like 'T' suffix */
493 /* operand size depends on prefixes */
495 /* operand size depends on prefixes with operand swapped */
499 /* double word operand */
501 /* double word operand with operand swapped */
503 /* quad word operand */
505 /* quad word operand with operand swapped */
507 /* ten-byte operand */
509 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
510 broadcast enabled. */
512 /* Similar to x_mode, but with different EVEX mem shifts. */
514 /* Similar to x_mode, but with disabled broadcast. */
516 /* Similar to x_mode, but with operands swapped and disabled broadcast
519 /* 16-byte XMM operand */
521 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
522 memory operand (depending on vector length). Broadcast isn't
525 /* Same as xmmq_mode, but broadcast is allowed. */
526 evex_half_bcst_xmmq_mode,
527 /* XMM register or byte memory operand */
529 /* XMM register or word memory operand */
531 /* XMM register or double word memory operand */
533 /* XMM register or quad word memory operand */
535 /* XMM register or double/quad word memory operand, depending on
538 /* 16-byte XMM, word, double word or quad word operand. */
540 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
542 /* 32-byte YMM operand */
544 /* quad word, ymmword or zmmword memory operand. */
546 /* 32-byte YMM or 16-byte word operand */
548 /* d_mode in 32bit, q_mode in 64bit mode. */
550 /* pair of v_mode operands */
555 /* operand size depends on REX prefixes. */
557 /* registers like dq_mode, memory like w_mode. */
561 /* 4- or 6-byte pointer operand */
564 /* v_mode for indirect branch opcodes. */
566 /* v_mode for stack-related opcodes. */
568 /* non-quad operand size depends on prefixes */
570 /* 16-byte operand */
572 /* registers like dq_mode, memory like b_mode. */
574 /* registers like d_mode, memory like b_mode. */
576 /* registers like d_mode, memory like w_mode. */
578 /* registers like dq_mode, memory like d_mode. */
580 /* normal vex mode */
582 /* 128bit vex mode */
584 /* 256bit vex mode */
586 /* operand size depends on the VEX.W bit. */
589 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
590 vex_vsib_d_w_dq_mode,
591 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
593 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
594 vex_vsib_q_w_dq_mode,
595 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
598 /* scalar, ignore vector length. */
600 /* like d_mode, ignore vector length. */
602 /* like d_swap_mode, ignore vector length. */
604 /* like q_mode, ignore vector length. */
606 /* like q_swap_mode, ignore vector length. */
608 /* like vex_mode, ignore vector length. */
610 /* like vex_w_dq_mode, ignore vector length. */
611 vex_scalar_w_dq_mode,
613 /* Static rounding. */
615 /* Supress all exceptions. */
618 /* Mask register operand. */
620 /* Mask register operand. */
687 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
689 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
690 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
691 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
692 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
693 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
694 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
695 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
696 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
697 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
698 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
699 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
700 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
701 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
702 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
703 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
822 MOD_VEX_0F12_PREFIX_0,
824 MOD_VEX_0F16_PREFIX_0,
827 MOD_VEX_W_0_0F41_P_0_LEN_1,
828 MOD_VEX_W_1_0F41_P_0_LEN_1,
829 MOD_VEX_W_0_0F41_P_2_LEN_1,
830 MOD_VEX_W_1_0F41_P_2_LEN_1,
831 MOD_VEX_W_0_0F42_P_0_LEN_1,
832 MOD_VEX_W_1_0F42_P_0_LEN_1,
833 MOD_VEX_W_0_0F42_P_2_LEN_1,
834 MOD_VEX_W_1_0F42_P_2_LEN_1,
835 MOD_VEX_W_0_0F44_P_0_LEN_1,
836 MOD_VEX_W_1_0F44_P_0_LEN_1,
837 MOD_VEX_W_0_0F44_P_2_LEN_1,
838 MOD_VEX_W_1_0F44_P_2_LEN_1,
839 MOD_VEX_W_0_0F45_P_0_LEN_1,
840 MOD_VEX_W_1_0F45_P_0_LEN_1,
841 MOD_VEX_W_0_0F45_P_2_LEN_1,
842 MOD_VEX_W_1_0F45_P_2_LEN_1,
843 MOD_VEX_W_0_0F46_P_0_LEN_1,
844 MOD_VEX_W_1_0F46_P_0_LEN_1,
845 MOD_VEX_W_0_0F46_P_2_LEN_1,
846 MOD_VEX_W_1_0F46_P_2_LEN_1,
847 MOD_VEX_W_0_0F47_P_0_LEN_1,
848 MOD_VEX_W_1_0F47_P_0_LEN_1,
849 MOD_VEX_W_0_0F47_P_2_LEN_1,
850 MOD_VEX_W_1_0F47_P_2_LEN_1,
851 MOD_VEX_W_0_0F4A_P_0_LEN_1,
852 MOD_VEX_W_1_0F4A_P_0_LEN_1,
853 MOD_VEX_W_0_0F4A_P_2_LEN_1,
854 MOD_VEX_W_1_0F4A_P_2_LEN_1,
855 MOD_VEX_W_0_0F4B_P_0_LEN_1,
856 MOD_VEX_W_1_0F4B_P_0_LEN_1,
857 MOD_VEX_W_0_0F4B_P_2_LEN_1,
869 MOD_VEX_W_0_0F91_P_0_LEN_0,
870 MOD_VEX_W_1_0F91_P_0_LEN_0,
871 MOD_VEX_W_0_0F91_P_2_LEN_0,
872 MOD_VEX_W_1_0F91_P_2_LEN_0,
873 MOD_VEX_W_0_0F92_P_0_LEN_0,
874 MOD_VEX_W_0_0F92_P_2_LEN_0,
875 MOD_VEX_W_0_0F92_P_3_LEN_0,
876 MOD_VEX_W_1_0F92_P_3_LEN_0,
877 MOD_VEX_W_0_0F93_P_0_LEN_0,
878 MOD_VEX_W_0_0F93_P_2_LEN_0,
879 MOD_VEX_W_0_0F93_P_3_LEN_0,
880 MOD_VEX_W_1_0F93_P_3_LEN_0,
881 MOD_VEX_W_0_0F98_P_0_LEN_0,
882 MOD_VEX_W_1_0F98_P_0_LEN_0,
883 MOD_VEX_W_0_0F98_P_2_LEN_0,
884 MOD_VEX_W_1_0F98_P_2_LEN_0,
885 MOD_VEX_W_0_0F99_P_0_LEN_0,
886 MOD_VEX_W_1_0F99_P_0_LEN_0,
887 MOD_VEX_W_0_0F99_P_2_LEN_0,
888 MOD_VEX_W_1_0F99_P_2_LEN_0,
891 MOD_VEX_0FD7_PREFIX_2,
892 MOD_VEX_0FE7_PREFIX_2,
893 MOD_VEX_0FF0_PREFIX_3,
894 MOD_VEX_0F381A_PREFIX_2,
895 MOD_VEX_0F382A_PREFIX_2,
896 MOD_VEX_0F382C_PREFIX_2,
897 MOD_VEX_0F382D_PREFIX_2,
898 MOD_VEX_0F382E_PREFIX_2,
899 MOD_VEX_0F382F_PREFIX_2,
900 MOD_VEX_0F385A_PREFIX_2,
901 MOD_VEX_0F388C_PREFIX_2,
902 MOD_VEX_0F388E_PREFIX_2,
903 MOD_VEX_W_0_0F3A30_P_2_LEN_0,
904 MOD_VEX_W_1_0F3A30_P_2_LEN_0,
905 MOD_VEX_W_0_0F3A31_P_2_LEN_0,
906 MOD_VEX_W_1_0F3A31_P_2_LEN_0,
907 MOD_VEX_W_0_0F3A32_P_2_LEN_0,
908 MOD_VEX_W_1_0F3A32_P_2_LEN_0,
909 MOD_VEX_W_0_0F3A33_P_2_LEN_0,
910 MOD_VEX_W_1_0F3A33_P_2_LEN_0,
912 MOD_EVEX_0F10_PREFIX_1,
913 MOD_EVEX_0F10_PREFIX_3,
914 MOD_EVEX_0F11_PREFIX_1,
915 MOD_EVEX_0F11_PREFIX_3,
916 MOD_EVEX_0F12_PREFIX_0,
917 MOD_EVEX_0F16_PREFIX_0,
918 MOD_EVEX_0F38C6_REG_1,
919 MOD_EVEX_0F38C6_REG_2,
920 MOD_EVEX_0F38C6_REG_5,
921 MOD_EVEX_0F38C6_REG_6,
922 MOD_EVEX_0F38C7_REG_1,
923 MOD_EVEX_0F38C7_REG_2,
924 MOD_EVEX_0F38C7_REG_5,
925 MOD_EVEX_0F38C7_REG_6
988 PREFIX_MOD_0_0FAE_REG_4,
989 PREFIX_MOD_3_0FAE_REG_4,
997 PREFIX_MOD_0_0FC7_REG_6,
998 PREFIX_MOD_3_0FC7_REG_6,
999 PREFIX_MOD_3_0FC7_REG_7,
1123 PREFIX_VEX_0F71_REG_2,
1124 PREFIX_VEX_0F71_REG_4,
1125 PREFIX_VEX_0F71_REG_6,
1126 PREFIX_VEX_0F72_REG_2,
1127 PREFIX_VEX_0F72_REG_4,
1128 PREFIX_VEX_0F72_REG_6,
1129 PREFIX_VEX_0F73_REG_2,
1130 PREFIX_VEX_0F73_REG_3,
1131 PREFIX_VEX_0F73_REG_6,
1132 PREFIX_VEX_0F73_REG_7,
1304 PREFIX_VEX_0F38F3_REG_1,
1305 PREFIX_VEX_0F38F3_REG_2,
1306 PREFIX_VEX_0F38F3_REG_3,
1423 PREFIX_EVEX_0F71_REG_2,
1424 PREFIX_EVEX_0F71_REG_4,
1425 PREFIX_EVEX_0F71_REG_6,
1426 PREFIX_EVEX_0F72_REG_0,
1427 PREFIX_EVEX_0F72_REG_1,
1428 PREFIX_EVEX_0F72_REG_2,
1429 PREFIX_EVEX_0F72_REG_4,
1430 PREFIX_EVEX_0F72_REG_6,
1431 PREFIX_EVEX_0F73_REG_2,
1432 PREFIX_EVEX_0F73_REG_3,
1433 PREFIX_EVEX_0F73_REG_6,
1434 PREFIX_EVEX_0F73_REG_7,
1619 PREFIX_EVEX_0F38C6_REG_1,
1620 PREFIX_EVEX_0F38C6_REG_2,
1621 PREFIX_EVEX_0F38C6_REG_5,
1622 PREFIX_EVEX_0F38C6_REG_6,
1623 PREFIX_EVEX_0F38C7_REG_1,
1624 PREFIX_EVEX_0F38C7_REG_2,
1625 PREFIX_EVEX_0F38C7_REG_5,
1626 PREFIX_EVEX_0F38C7_REG_6,
1723 THREE_BYTE_0F38 = 0,
1751 VEX_LEN_0F10_P_1 = 0,
1755 VEX_LEN_0F12_P_0_M_0,
1756 VEX_LEN_0F12_P_0_M_1,
1759 VEX_LEN_0F16_P_0_M_0,
1760 VEX_LEN_0F16_P_0_M_1,
1824 VEX_LEN_0FAE_R_2_M_0,
1825 VEX_LEN_0FAE_R_3_M_0,
1834 VEX_LEN_0F381A_P_2_M_0,
1837 VEX_LEN_0F385A_P_2_M_0,
1844 VEX_LEN_0F38F3_R_1_P_0,
1845 VEX_LEN_0F38F3_R_2_P_0,
1846 VEX_LEN_0F38F3_R_3_P_0,
1892 VEX_LEN_0FXOP_08_CC,
1893 VEX_LEN_0FXOP_08_CD,
1894 VEX_LEN_0FXOP_08_CE,
1895 VEX_LEN_0FXOP_08_CF,
1896 VEX_LEN_0FXOP_08_EC,
1897 VEX_LEN_0FXOP_08_ED,
1898 VEX_LEN_0FXOP_08_EE,
1899 VEX_LEN_0FXOP_08_EF,
1900 VEX_LEN_0FXOP_09_80,
1934 VEX_W_0F41_P_0_LEN_1,
1935 VEX_W_0F41_P_2_LEN_1,
1936 VEX_W_0F42_P_0_LEN_1,
1937 VEX_W_0F42_P_2_LEN_1,
1938 VEX_W_0F44_P_0_LEN_0,
1939 VEX_W_0F44_P_2_LEN_0,
1940 VEX_W_0F45_P_0_LEN_1,
1941 VEX_W_0F45_P_2_LEN_1,
1942 VEX_W_0F46_P_0_LEN_1,
1943 VEX_W_0F46_P_2_LEN_1,
1944 VEX_W_0F47_P_0_LEN_1,
1945 VEX_W_0F47_P_2_LEN_1,
1946 VEX_W_0F4A_P_0_LEN_1,
1947 VEX_W_0F4A_P_2_LEN_1,
1948 VEX_W_0F4B_P_0_LEN_1,
1949 VEX_W_0F4B_P_2_LEN_1,
2029 VEX_W_0F90_P_0_LEN_0,
2030 VEX_W_0F90_P_2_LEN_0,
2031 VEX_W_0F91_P_0_LEN_0,
2032 VEX_W_0F91_P_2_LEN_0,
2033 VEX_W_0F92_P_0_LEN_0,
2034 VEX_W_0F92_P_2_LEN_0,
2035 VEX_W_0F92_P_3_LEN_0,
2036 VEX_W_0F93_P_0_LEN_0,
2037 VEX_W_0F93_P_2_LEN_0,
2038 VEX_W_0F93_P_3_LEN_0,
2039 VEX_W_0F98_P_0_LEN_0,
2040 VEX_W_0F98_P_2_LEN_0,
2041 VEX_W_0F99_P_0_LEN_0,
2042 VEX_W_0F99_P_2_LEN_0,
2121 VEX_W_0F381A_P_2_M_0,
2133 VEX_W_0F382A_P_2_M_0,
2135 VEX_W_0F382C_P_2_M_0,
2136 VEX_W_0F382D_P_2_M_0,
2137 VEX_W_0F382E_P_2_M_0,
2138 VEX_W_0F382F_P_2_M_0,
2160 VEX_W_0F385A_P_2_M_0,
2188 VEX_W_0F3A30_P_2_LEN_0,
2189 VEX_W_0F3A31_P_2_LEN_0,
2190 VEX_W_0F3A32_P_2_LEN_0,
2191 VEX_W_0F3A33_P_2_LEN_0,
2211 EVEX_W_0F10_P_1_M_0,
2212 EVEX_W_0F10_P_1_M_1,
2214 EVEX_W_0F10_P_3_M_0,
2215 EVEX_W_0F10_P_3_M_1,
2217 EVEX_W_0F11_P_1_M_0,
2218 EVEX_W_0F11_P_1_M_1,
2220 EVEX_W_0F11_P_3_M_0,
2221 EVEX_W_0F11_P_3_M_1,
2222 EVEX_W_0F12_P_0_M_0,
2223 EVEX_W_0F12_P_0_M_1,
2233 EVEX_W_0F16_P_0_M_0,
2234 EVEX_W_0F16_P_0_M_1,
2305 EVEX_W_0F72_R_2_P_2,
2306 EVEX_W_0F72_R_6_P_2,
2307 EVEX_W_0F73_R_2_P_2,
2308 EVEX_W_0F73_R_6_P_2,
2408 EVEX_W_0F38C7_R_1_P_2,
2409 EVEX_W_0F38C7_R_2_P_2,
2410 EVEX_W_0F38C7_R_5_P_2,
2411 EVEX_W_0F38C7_R_6_P_2,
2446 typedef void (*op_rtn) (int bytemode, int sizeflag);
2455 unsigned int prefix_requirement;
2458 /* Upper case letters in the instruction names here are macros.
2459 'A' => print 'b' if no register operands or suffix_always is true
2460 'B' => print 'b' if suffix_always is true
2461 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2463 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2464 suffix_always is true
2465 'E' => print 'e' if 32-bit form of jcxz
2466 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2467 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2468 'H' => print ",pt" or ",pn" branch hint
2469 'I' => honor following macro letter even in Intel mode (implemented only
2470 for some of the macro letters)
2472 'K' => print 'd' or 'q' if rex prefix is present.
2473 'L' => print 'l' if suffix_always is true
2474 'M' => print 'r' if intel_mnemonic is false.
2475 'N' => print 'n' if instruction has no wait "prefix"
2476 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2477 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2478 or suffix_always is true. print 'q' if rex prefix is present.
2479 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2481 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2482 'S' => print 'w', 'l' or 'q' if suffix_always is true
2483 'T' => print 'q' in 64bit mode if instruction has no operand size
2484 prefix and behave as 'P' otherwise
2485 'U' => print 'q' in 64bit mode if instruction has no operand size
2486 prefix and behave as 'Q' otherwise
2487 'V' => print 'q' in 64bit mode if instruction has no operand size
2488 prefix and behave as 'S' otherwise
2489 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2490 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2491 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2492 suffix_always is true.
2493 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2494 '!' => change condition from true to false or from false to true.
2495 '%' => add 1 upper case letter to the macro.
2496 '^' => print 'w' or 'l' depending on operand size prefix or
2497 suffix_always is true (lcall/ljmp).
2498 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2499 on operand size prefix.
2500 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2501 has no operand size prefix for AMD64 ISA, behave as 'P'
2504 2 upper case letter macros:
2505 "XY" => print 'x' or 'y' if suffix_always is true or no register
2506 operands and no broadcast.
2507 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2508 register operands and no broadcast.
2509 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2510 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2511 or suffix_always is true
2512 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2513 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2514 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2515 "LW" => print 'd', 'q' depending on the VEX.W bit
2516 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2517 an operand size prefix, or suffix_always is true. print
2518 'q' if rex prefix is present.
2520 Many of the above letters print nothing in Intel mode. See "putop"
2523 Braces '{' and '}', and vertical bars '|', indicate alternative
2524 mnemonic strings for AT&T and Intel. */
2526 static const struct dis386 dis386[] = {
2528 { "addB", { Ebh1, Gb }, 0 },
2529 { "addS", { Evh1, Gv }, 0 },
2530 { "addB", { Gb, EbS }, 0 },
2531 { "addS", { Gv, EvS }, 0 },
2532 { "addB", { AL, Ib }, 0 },
2533 { "addS", { eAX, Iv }, 0 },
2534 { X86_64_TABLE (X86_64_06) },
2535 { X86_64_TABLE (X86_64_07) },
2537 { "orB", { Ebh1, Gb }, 0 },
2538 { "orS", { Evh1, Gv }, 0 },
2539 { "orB", { Gb, EbS }, 0 },
2540 { "orS", { Gv, EvS }, 0 },
2541 { "orB", { AL, Ib }, 0 },
2542 { "orS", { eAX, Iv }, 0 },
2543 { X86_64_TABLE (X86_64_0D) },
2544 { Bad_Opcode }, /* 0x0f extended opcode escape */
2546 { "adcB", { Ebh1, Gb }, 0 },
2547 { "adcS", { Evh1, Gv }, 0 },
2548 { "adcB", { Gb, EbS }, 0 },
2549 { "adcS", { Gv, EvS }, 0 },
2550 { "adcB", { AL, Ib }, 0 },
2551 { "adcS", { eAX, Iv }, 0 },
2552 { X86_64_TABLE (X86_64_16) },
2553 { X86_64_TABLE (X86_64_17) },
2555 { "sbbB", { Ebh1, Gb }, 0 },
2556 { "sbbS", { Evh1, Gv }, 0 },
2557 { "sbbB", { Gb, EbS }, 0 },
2558 { "sbbS", { Gv, EvS }, 0 },
2559 { "sbbB", { AL, Ib }, 0 },
2560 { "sbbS", { eAX, Iv }, 0 },
2561 { X86_64_TABLE (X86_64_1E) },
2562 { X86_64_TABLE (X86_64_1F) },
2564 { "andB", { Ebh1, Gb }, 0 },
2565 { "andS", { Evh1, Gv }, 0 },
2566 { "andB", { Gb, EbS }, 0 },
2567 { "andS", { Gv, EvS }, 0 },
2568 { "andB", { AL, Ib }, 0 },
2569 { "andS", { eAX, Iv }, 0 },
2570 { Bad_Opcode }, /* SEG ES prefix */
2571 { X86_64_TABLE (X86_64_27) },
2573 { "subB", { Ebh1, Gb }, 0 },
2574 { "subS", { Evh1, Gv }, 0 },
2575 { "subB", { Gb, EbS }, 0 },
2576 { "subS", { Gv, EvS }, 0 },
2577 { "subB", { AL, Ib }, 0 },
2578 { "subS", { eAX, Iv }, 0 },
2579 { Bad_Opcode }, /* SEG CS prefix */
2580 { X86_64_TABLE (X86_64_2F) },
2582 { "xorB", { Ebh1, Gb }, 0 },
2583 { "xorS", { Evh1, Gv }, 0 },
2584 { "xorB", { Gb, EbS }, 0 },
2585 { "xorS", { Gv, EvS }, 0 },
2586 { "xorB", { AL, Ib }, 0 },
2587 { "xorS", { eAX, Iv }, 0 },
2588 { Bad_Opcode }, /* SEG SS prefix */
2589 { X86_64_TABLE (X86_64_37) },
2591 { "cmpB", { Eb, Gb }, 0 },
2592 { "cmpS", { Ev, Gv }, 0 },
2593 { "cmpB", { Gb, EbS }, 0 },
2594 { "cmpS", { Gv, EvS }, 0 },
2595 { "cmpB", { AL, Ib }, 0 },
2596 { "cmpS", { eAX, Iv }, 0 },
2597 { Bad_Opcode }, /* SEG DS prefix */
2598 { X86_64_TABLE (X86_64_3F) },
2600 { "inc{S|}", { RMeAX }, 0 },
2601 { "inc{S|}", { RMeCX }, 0 },
2602 { "inc{S|}", { RMeDX }, 0 },
2603 { "inc{S|}", { RMeBX }, 0 },
2604 { "inc{S|}", { RMeSP }, 0 },
2605 { "inc{S|}", { RMeBP }, 0 },
2606 { "inc{S|}", { RMeSI }, 0 },
2607 { "inc{S|}", { RMeDI }, 0 },
2609 { "dec{S|}", { RMeAX }, 0 },
2610 { "dec{S|}", { RMeCX }, 0 },
2611 { "dec{S|}", { RMeDX }, 0 },
2612 { "dec{S|}", { RMeBX }, 0 },
2613 { "dec{S|}", { RMeSP }, 0 },
2614 { "dec{S|}", { RMeBP }, 0 },
2615 { "dec{S|}", { RMeSI }, 0 },
2616 { "dec{S|}", { RMeDI }, 0 },
2618 { "pushV", { RMrAX }, 0 },
2619 { "pushV", { RMrCX }, 0 },
2620 { "pushV", { RMrDX }, 0 },
2621 { "pushV", { RMrBX }, 0 },
2622 { "pushV", { RMrSP }, 0 },
2623 { "pushV", { RMrBP }, 0 },
2624 { "pushV", { RMrSI }, 0 },
2625 { "pushV", { RMrDI }, 0 },
2627 { "popV", { RMrAX }, 0 },
2628 { "popV", { RMrCX }, 0 },
2629 { "popV", { RMrDX }, 0 },
2630 { "popV", { RMrBX }, 0 },
2631 { "popV", { RMrSP }, 0 },
2632 { "popV", { RMrBP }, 0 },
2633 { "popV", { RMrSI }, 0 },
2634 { "popV", { RMrDI }, 0 },
2636 { X86_64_TABLE (X86_64_60) },
2637 { X86_64_TABLE (X86_64_61) },
2638 { X86_64_TABLE (X86_64_62) },
2639 { X86_64_TABLE (X86_64_63) },
2640 { Bad_Opcode }, /* seg fs */
2641 { Bad_Opcode }, /* seg gs */
2642 { Bad_Opcode }, /* op size prefix */
2643 { Bad_Opcode }, /* adr size prefix */
2645 { "pushT", { sIv }, 0 },
2646 { "imulS", { Gv, Ev, Iv }, 0 },
2647 { "pushT", { sIbT }, 0 },
2648 { "imulS", { Gv, Ev, sIb }, 0 },
2649 { "ins{b|}", { Ybr, indirDX }, 0 },
2650 { X86_64_TABLE (X86_64_6D) },
2651 { "outs{b|}", { indirDXr, Xb }, 0 },
2652 { X86_64_TABLE (X86_64_6F) },
2654 { "joH", { Jb, BND, cond_jump_flag }, 0 },
2655 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
2656 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
2657 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
2658 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
2659 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
2660 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
2661 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
2663 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
2664 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
2665 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
2666 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
2667 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
2668 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
2669 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
2670 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
2672 { REG_TABLE (REG_80) },
2673 { REG_TABLE (REG_81) },
2674 { REG_TABLE (REG_82) },
2675 { REG_TABLE (REG_83) },
2676 { "testB", { Eb, Gb }, 0 },
2677 { "testS", { Ev, Gv }, 0 },
2678 { "xchgB", { Ebh2, Gb }, 0 },
2679 { "xchgS", { Evh2, Gv }, 0 },
2681 { "movB", { Ebh3, Gb }, 0 },
2682 { "movS", { Evh3, Gv }, 0 },
2683 { "movB", { Gb, EbS }, 0 },
2684 { "movS", { Gv, EvS }, 0 },
2685 { "movD", { Sv, Sw }, 0 },
2686 { MOD_TABLE (MOD_8D) },
2687 { "movD", { Sw, Sv }, 0 },
2688 { REG_TABLE (REG_8F) },
2690 { PREFIX_TABLE (PREFIX_90) },
2691 { "xchgS", { RMeCX, eAX }, 0 },
2692 { "xchgS", { RMeDX, eAX }, 0 },
2693 { "xchgS", { RMeBX, eAX }, 0 },
2694 { "xchgS", { RMeSP, eAX }, 0 },
2695 { "xchgS", { RMeBP, eAX }, 0 },
2696 { "xchgS", { RMeSI, eAX }, 0 },
2697 { "xchgS", { RMeDI, eAX }, 0 },
2699 { "cW{t|}R", { XX }, 0 },
2700 { "cR{t|}O", { XX }, 0 },
2701 { X86_64_TABLE (X86_64_9A) },
2702 { Bad_Opcode }, /* fwait */
2703 { "pushfT", { XX }, 0 },
2704 { "popfT", { XX }, 0 },
2705 { "sahf", { XX }, 0 },
2706 { "lahf", { XX }, 0 },
2708 { "mov%LB", { AL, Ob }, 0 },
2709 { "mov%LS", { eAX, Ov }, 0 },
2710 { "mov%LB", { Ob, AL }, 0 },
2711 { "mov%LS", { Ov, eAX }, 0 },
2712 { "movs{b|}", { Ybr, Xb }, 0 },
2713 { "movs{R|}", { Yvr, Xv }, 0 },
2714 { "cmps{b|}", { Xb, Yb }, 0 },
2715 { "cmps{R|}", { Xv, Yv }, 0 },
2717 { "testB", { AL, Ib }, 0 },
2718 { "testS", { eAX, Iv }, 0 },
2719 { "stosB", { Ybr, AL }, 0 },
2720 { "stosS", { Yvr, eAX }, 0 },
2721 { "lodsB", { ALr, Xb }, 0 },
2722 { "lodsS", { eAXr, Xv }, 0 },
2723 { "scasB", { AL, Yb }, 0 },
2724 { "scasS", { eAX, Yv }, 0 },
2726 { "movB", { RMAL, Ib }, 0 },
2727 { "movB", { RMCL, Ib }, 0 },
2728 { "movB", { RMDL, Ib }, 0 },
2729 { "movB", { RMBL, Ib }, 0 },
2730 { "movB", { RMAH, Ib }, 0 },
2731 { "movB", { RMCH, Ib }, 0 },
2732 { "movB", { RMDH, Ib }, 0 },
2733 { "movB", { RMBH, Ib }, 0 },
2735 { "mov%LV", { RMeAX, Iv64 }, 0 },
2736 { "mov%LV", { RMeCX, Iv64 }, 0 },
2737 { "mov%LV", { RMeDX, Iv64 }, 0 },
2738 { "mov%LV", { RMeBX, Iv64 }, 0 },
2739 { "mov%LV", { RMeSP, Iv64 }, 0 },
2740 { "mov%LV", { RMeBP, Iv64 }, 0 },
2741 { "mov%LV", { RMeSI, Iv64 }, 0 },
2742 { "mov%LV", { RMeDI, Iv64 }, 0 },
2744 { REG_TABLE (REG_C0) },
2745 { REG_TABLE (REG_C1) },
2746 { "retT", { Iw, BND }, 0 },
2747 { "retT", { BND }, 0 },
2748 { X86_64_TABLE (X86_64_C4) },
2749 { X86_64_TABLE (X86_64_C5) },
2750 { REG_TABLE (REG_C6) },
2751 { REG_TABLE (REG_C7) },
2753 { "enterT", { Iw, Ib }, 0 },
2754 { "leaveT", { XX }, 0 },
2755 { "Jret{|f}P", { Iw }, 0 },
2756 { "Jret{|f}P", { XX }, 0 },
2757 { "int3", { XX }, 0 },
2758 { "int", { Ib }, 0 },
2759 { X86_64_TABLE (X86_64_CE) },
2760 { "iret%LP", { XX }, 0 },
2762 { REG_TABLE (REG_D0) },
2763 { REG_TABLE (REG_D1) },
2764 { REG_TABLE (REG_D2) },
2765 { REG_TABLE (REG_D3) },
2766 { X86_64_TABLE (X86_64_D4) },
2767 { X86_64_TABLE (X86_64_D5) },
2769 { "xlat", { DSBX }, 0 },
2780 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2781 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2782 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2783 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2784 { "inB", { AL, Ib }, 0 },
2785 { "inG", { zAX, Ib }, 0 },
2786 { "outB", { Ib, AL }, 0 },
2787 { "outG", { Ib, zAX }, 0 },
2789 { X86_64_TABLE (X86_64_E8) },
2790 { X86_64_TABLE (X86_64_E9) },
2791 { X86_64_TABLE (X86_64_EA) },
2792 { "jmp", { Jb, BND }, 0 },
2793 { "inB", { AL, indirDX }, 0 },
2794 { "inG", { zAX, indirDX }, 0 },
2795 { "outB", { indirDX, AL }, 0 },
2796 { "outG", { indirDX, zAX }, 0 },
2798 { Bad_Opcode }, /* lock prefix */
2799 { "icebp", { XX }, 0 },
2800 { Bad_Opcode }, /* repne */
2801 { Bad_Opcode }, /* repz */
2802 { "hlt", { XX }, 0 },
2803 { "cmc", { XX }, 0 },
2804 { REG_TABLE (REG_F6) },
2805 { REG_TABLE (REG_F7) },
2807 { "clc", { XX }, 0 },
2808 { "stc", { XX }, 0 },
2809 { "cli", { XX }, 0 },
2810 { "sti", { XX }, 0 },
2811 { "cld", { XX }, 0 },
2812 { "std", { XX }, 0 },
2813 { REG_TABLE (REG_FE) },
2814 { REG_TABLE (REG_FF) },
2817 static const struct dis386 dis386_twobyte[] = {
2819 { REG_TABLE (REG_0F00 ) },
2820 { REG_TABLE (REG_0F01 ) },
2821 { "larS", { Gv, Ew }, 0 },
2822 { "lslS", { Gv, Ew }, 0 },
2824 { "syscall", { XX }, 0 },
2825 { "clts", { XX }, 0 },
2826 { "sysret%LP", { XX }, 0 },
2828 { "invd", { XX }, 0 },
2829 { "wbinvd", { XX }, 0 },
2831 { "ud2", { XX }, 0 },
2833 { REG_TABLE (REG_0F0D) },
2834 { "femms", { XX }, 0 },
2835 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2837 { PREFIX_TABLE (PREFIX_0F10) },
2838 { PREFIX_TABLE (PREFIX_0F11) },
2839 { PREFIX_TABLE (PREFIX_0F12) },
2840 { MOD_TABLE (MOD_0F13) },
2841 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2842 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2843 { PREFIX_TABLE (PREFIX_0F16) },
2844 { MOD_TABLE (MOD_0F17) },
2846 { REG_TABLE (REG_0F18) },
2847 { "nopQ", { Ev }, 0 },
2848 { PREFIX_TABLE (PREFIX_0F1A) },
2849 { PREFIX_TABLE (PREFIX_0F1B) },
2850 { "nopQ", { Ev }, 0 },
2851 { "nopQ", { Ev }, 0 },
2852 { "nopQ", { Ev }, 0 },
2853 { "nopQ", { Ev }, 0 },
2855 { "movZ", { Rm, Cm }, 0 },
2856 { "movZ", { Rm, Dm }, 0 },
2857 { "movZ", { Cm, Rm }, 0 },
2858 { "movZ", { Dm, Rm }, 0 },
2859 { MOD_TABLE (MOD_0F24) },
2861 { MOD_TABLE (MOD_0F26) },
2864 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2865 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2866 { PREFIX_TABLE (PREFIX_0F2A) },
2867 { PREFIX_TABLE (PREFIX_0F2B) },
2868 { PREFIX_TABLE (PREFIX_0F2C) },
2869 { PREFIX_TABLE (PREFIX_0F2D) },
2870 { PREFIX_TABLE (PREFIX_0F2E) },
2871 { PREFIX_TABLE (PREFIX_0F2F) },
2873 { "wrmsr", { XX }, 0 },
2874 { "rdtsc", { XX }, 0 },
2875 { "rdmsr", { XX }, 0 },
2876 { "rdpmc", { XX }, 0 },
2877 { "sysenter", { XX }, 0 },
2878 { "sysexit", { XX }, 0 },
2880 { "getsec", { XX }, 0 },
2882 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2884 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2891 { "cmovoS", { Gv, Ev }, 0 },
2892 { "cmovnoS", { Gv, Ev }, 0 },
2893 { "cmovbS", { Gv, Ev }, 0 },
2894 { "cmovaeS", { Gv, Ev }, 0 },
2895 { "cmoveS", { Gv, Ev }, 0 },
2896 { "cmovneS", { Gv, Ev }, 0 },
2897 { "cmovbeS", { Gv, Ev }, 0 },
2898 { "cmovaS", { Gv, Ev }, 0 },
2900 { "cmovsS", { Gv, Ev }, 0 },
2901 { "cmovnsS", { Gv, Ev }, 0 },
2902 { "cmovpS", { Gv, Ev }, 0 },
2903 { "cmovnpS", { Gv, Ev }, 0 },
2904 { "cmovlS", { Gv, Ev }, 0 },
2905 { "cmovgeS", { Gv, Ev }, 0 },
2906 { "cmovleS", { Gv, Ev }, 0 },
2907 { "cmovgS", { Gv, Ev }, 0 },
2909 { MOD_TABLE (MOD_0F51) },
2910 { PREFIX_TABLE (PREFIX_0F51) },
2911 { PREFIX_TABLE (PREFIX_0F52) },
2912 { PREFIX_TABLE (PREFIX_0F53) },
2913 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2914 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2915 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2916 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2918 { PREFIX_TABLE (PREFIX_0F58) },
2919 { PREFIX_TABLE (PREFIX_0F59) },
2920 { PREFIX_TABLE (PREFIX_0F5A) },
2921 { PREFIX_TABLE (PREFIX_0F5B) },
2922 { PREFIX_TABLE (PREFIX_0F5C) },
2923 { PREFIX_TABLE (PREFIX_0F5D) },
2924 { PREFIX_TABLE (PREFIX_0F5E) },
2925 { PREFIX_TABLE (PREFIX_0F5F) },
2927 { PREFIX_TABLE (PREFIX_0F60) },
2928 { PREFIX_TABLE (PREFIX_0F61) },
2929 { PREFIX_TABLE (PREFIX_0F62) },
2930 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2931 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2932 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2933 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2934 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2936 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2937 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2938 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2939 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2940 { PREFIX_TABLE (PREFIX_0F6C) },
2941 { PREFIX_TABLE (PREFIX_0F6D) },
2942 { "movK", { MX, Edq }, PREFIX_OPCODE },
2943 { PREFIX_TABLE (PREFIX_0F6F) },
2945 { PREFIX_TABLE (PREFIX_0F70) },
2946 { REG_TABLE (REG_0F71) },
2947 { REG_TABLE (REG_0F72) },
2948 { REG_TABLE (REG_0F73) },
2949 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2950 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2951 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2952 { "emms", { XX }, PREFIX_OPCODE },
2954 { PREFIX_TABLE (PREFIX_0F78) },
2955 { PREFIX_TABLE (PREFIX_0F79) },
2956 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2958 { PREFIX_TABLE (PREFIX_0F7C) },
2959 { PREFIX_TABLE (PREFIX_0F7D) },
2960 { PREFIX_TABLE (PREFIX_0F7E) },
2961 { PREFIX_TABLE (PREFIX_0F7F) },
2963 { "joH", { Jv, BND, cond_jump_flag }, 0 },
2964 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
2965 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
2966 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
2967 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
2968 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
2969 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
2970 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
2972 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
2973 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
2974 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
2975 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
2976 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
2977 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
2978 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
2979 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
2981 { "seto", { Eb }, 0 },
2982 { "setno", { Eb }, 0 },
2983 { "setb", { Eb }, 0 },
2984 { "setae", { Eb }, 0 },
2985 { "sete", { Eb }, 0 },
2986 { "setne", { Eb }, 0 },
2987 { "setbe", { Eb }, 0 },
2988 { "seta", { Eb }, 0 },
2990 { "sets", { Eb }, 0 },
2991 { "setns", { Eb }, 0 },
2992 { "setp", { Eb }, 0 },
2993 { "setnp", { Eb }, 0 },
2994 { "setl", { Eb }, 0 },
2995 { "setge", { Eb }, 0 },
2996 { "setle", { Eb }, 0 },
2997 { "setg", { Eb }, 0 },
2999 { "pushT", { fs }, 0 },
3000 { "popT", { fs }, 0 },
3001 { "cpuid", { XX }, 0 },
3002 { "btS", { Ev, Gv }, 0 },
3003 { "shldS", { Ev, Gv, Ib }, 0 },
3004 { "shldS", { Ev, Gv, CL }, 0 },
3005 { REG_TABLE (REG_0FA6) },
3006 { REG_TABLE (REG_0FA7) },
3008 { "pushT", { gs }, 0 },
3009 { "popT", { gs }, 0 },
3010 { "rsm", { XX }, 0 },
3011 { "btsS", { Evh1, Gv }, 0 },
3012 { "shrdS", { Ev, Gv, Ib }, 0 },
3013 { "shrdS", { Ev, Gv, CL }, 0 },
3014 { REG_TABLE (REG_0FAE) },
3015 { "imulS", { Gv, Ev }, 0 },
3017 { "cmpxchgB", { Ebh1, Gb }, 0 },
3018 { "cmpxchgS", { Evh1, Gv }, 0 },
3019 { MOD_TABLE (MOD_0FB2) },
3020 { "btrS", { Evh1, Gv }, 0 },
3021 { MOD_TABLE (MOD_0FB4) },
3022 { MOD_TABLE (MOD_0FB5) },
3023 { "movz{bR|x}", { Gv, Eb }, 0 },
3024 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3026 { PREFIX_TABLE (PREFIX_0FB8) },
3027 { "ud1", { XX }, 0 },
3028 { REG_TABLE (REG_0FBA) },
3029 { "btcS", { Evh1, Gv }, 0 },
3030 { PREFIX_TABLE (PREFIX_0FBC) },
3031 { PREFIX_TABLE (PREFIX_0FBD) },
3032 { "movs{bR|x}", { Gv, Eb }, 0 },
3033 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3035 { "xaddB", { Ebh1, Gb }, 0 },
3036 { "xaddS", { Evh1, Gv }, 0 },
3037 { PREFIX_TABLE (PREFIX_0FC2) },
3038 { MOD_TABLE (MOD_0FC3) },
3039 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
3040 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
3041 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
3042 { REG_TABLE (REG_0FC7) },
3044 { "bswap", { RMeAX }, 0 },
3045 { "bswap", { RMeCX }, 0 },
3046 { "bswap", { RMeDX }, 0 },
3047 { "bswap", { RMeBX }, 0 },
3048 { "bswap", { RMeSP }, 0 },
3049 { "bswap", { RMeBP }, 0 },
3050 { "bswap", { RMeSI }, 0 },
3051 { "bswap", { RMeDI }, 0 },
3053 { PREFIX_TABLE (PREFIX_0FD0) },
3054 { "psrlw", { MX, EM }, PREFIX_OPCODE },
3055 { "psrld", { MX, EM }, PREFIX_OPCODE },
3056 { "psrlq", { MX, EM }, PREFIX_OPCODE },
3057 { "paddq", { MX, EM }, PREFIX_OPCODE },
3058 { "pmullw", { MX, EM }, PREFIX_OPCODE },
3059 { PREFIX_TABLE (PREFIX_0FD6) },
3060 { MOD_TABLE (MOD_0FD7) },
3062 { "psubusb", { MX, EM }, PREFIX_OPCODE },
3063 { "psubusw", { MX, EM }, PREFIX_OPCODE },
3064 { "pminub", { MX, EM }, PREFIX_OPCODE },
3065 { "pand", { MX, EM }, PREFIX_OPCODE },
3066 { "paddusb", { MX, EM }, PREFIX_OPCODE },
3067 { "paddusw", { MX, EM }, PREFIX_OPCODE },
3068 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
3069 { "pandn", { MX, EM }, PREFIX_OPCODE },
3071 { "pavgb", { MX, EM }, PREFIX_OPCODE },
3072 { "psraw", { MX, EM }, PREFIX_OPCODE },
3073 { "psrad", { MX, EM }, PREFIX_OPCODE },
3074 { "pavgw", { MX, EM }, PREFIX_OPCODE },
3075 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
3076 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
3077 { PREFIX_TABLE (PREFIX_0FE6) },
3078 { PREFIX_TABLE (PREFIX_0FE7) },
3080 { "psubsb", { MX, EM }, PREFIX_OPCODE },
3081 { "psubsw", { MX, EM }, PREFIX_OPCODE },
3082 { "pminsw", { MX, EM }, PREFIX_OPCODE },
3083 { "por", { MX, EM }, PREFIX_OPCODE },
3084 { "paddsb", { MX, EM }, PREFIX_OPCODE },
3085 { "paddsw", { MX, EM }, PREFIX_OPCODE },
3086 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
3087 { "pxor", { MX, EM }, PREFIX_OPCODE },
3089 { PREFIX_TABLE (PREFIX_0FF0) },
3090 { "psllw", { MX, EM }, PREFIX_OPCODE },
3091 { "pslld", { MX, EM }, PREFIX_OPCODE },
3092 { "psllq", { MX, EM }, PREFIX_OPCODE },
3093 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
3094 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
3095 { "psadbw", { MX, EM }, PREFIX_OPCODE },
3096 { PREFIX_TABLE (PREFIX_0FF7) },
3098 { "psubb", { MX, EM }, PREFIX_OPCODE },
3099 { "psubw", { MX, EM }, PREFIX_OPCODE },
3100 { "psubd", { MX, EM }, PREFIX_OPCODE },
3101 { "psubq", { MX, EM }, PREFIX_OPCODE },
3102 { "paddb", { MX, EM }, PREFIX_OPCODE },
3103 { "paddw", { MX, EM }, PREFIX_OPCODE },
3104 { "paddd", { MX, EM }, PREFIX_OPCODE },
3108 static const unsigned char onebyte_has_modrm[256] = {
3109 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3110 /* ------------------------------- */
3111 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3112 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3113 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3114 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3115 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3116 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3117 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3118 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3119 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3120 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3121 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3122 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3123 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3124 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3125 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3126 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3127 /* ------------------------------- */
3128 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3131 static const unsigned char twobyte_has_modrm[256] = {
3132 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3133 /* ------------------------------- */
3134 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3135 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3136 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3137 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3138 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3139 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3140 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3141 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3142 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3143 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3144 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3145 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3146 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3147 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3148 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3149 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3150 /* ------------------------------- */
3151 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3154 static char obuf[100];
3156 static char *mnemonicendp;
3157 static char scratchbuf[100];
3158 static unsigned char *start_codep;
3159 static unsigned char *insn_codep;
3160 static unsigned char *codep;
3161 static unsigned char *end_codep;
3162 static int last_lock_prefix;
3163 static int last_repz_prefix;
3164 static int last_repnz_prefix;
3165 static int last_data_prefix;
3166 static int last_addr_prefix;
3167 static int last_rex_prefix;
3168 static int last_seg_prefix;
3169 static int fwait_prefix;
3170 /* The active segment register prefix. */
3171 static int active_seg_prefix;
3172 #define MAX_CODE_LENGTH 15
3173 /* We can up to 14 prefixes since the maximum instruction length is
3175 static int all_prefixes[MAX_CODE_LENGTH - 1];
3176 static disassemble_info *the_info;
3184 static unsigned char need_modrm;
3194 int register_specifier;
3201 int mask_register_specifier;
3207 static unsigned char need_vex;
3208 static unsigned char need_vex_reg;
3209 static unsigned char vex_w_done;
3217 /* If we are accessing mod/rm/reg without need_modrm set, then the
3218 values are stale. Hitting this abort likely indicates that you
3219 need to update onebyte_has_modrm or twobyte_has_modrm. */
3220 #define MODRM_CHECK if (!need_modrm) abort ()
3222 static const char **names64;
3223 static const char **names32;
3224 static const char **names16;
3225 static const char **names8;
3226 static const char **names8rex;
3227 static const char **names_seg;
3228 static const char *index64;
3229 static const char *index32;
3230 static const char **index16;
3231 static const char **names_bnd;
3233 static const char *intel_names64[] = {
3234 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3235 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3237 static const char *intel_names32[] = {
3238 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3239 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3241 static const char *intel_names16[] = {
3242 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3243 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3245 static const char *intel_names8[] = {
3246 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3248 static const char *intel_names8rex[] = {
3249 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3250 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3252 static const char *intel_names_seg[] = {
3253 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3255 static const char *intel_index64 = "riz";
3256 static const char *intel_index32 = "eiz";
3257 static const char *intel_index16[] = {
3258 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3261 static const char *att_names64[] = {
3262 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3263 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3265 static const char *att_names32[] = {
3266 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3267 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3269 static const char *att_names16[] = {
3270 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3271 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3273 static const char *att_names8[] = {
3274 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3276 static const char *att_names8rex[] = {
3277 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3278 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3280 static const char *att_names_seg[] = {
3281 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3283 static const char *att_index64 = "%riz";
3284 static const char *att_index32 = "%eiz";
3285 static const char *att_index16[] = {
3286 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3289 static const char **names_mm;
3290 static const char *intel_names_mm[] = {
3291 "mm0", "mm1", "mm2", "mm3",
3292 "mm4", "mm5", "mm6", "mm7"
3294 static const char *att_names_mm[] = {
3295 "%mm0", "%mm1", "%mm2", "%mm3",
3296 "%mm4", "%mm5", "%mm6", "%mm7"
3299 static const char *intel_names_bnd[] = {
3300 "bnd0", "bnd1", "bnd2", "bnd3"
3303 static const char *att_names_bnd[] = {
3304 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3307 static const char **names_xmm;
3308 static const char *intel_names_xmm[] = {
3309 "xmm0", "xmm1", "xmm2", "xmm3",
3310 "xmm4", "xmm5", "xmm6", "xmm7",
3311 "xmm8", "xmm9", "xmm10", "xmm11",
3312 "xmm12", "xmm13", "xmm14", "xmm15",
3313 "xmm16", "xmm17", "xmm18", "xmm19",
3314 "xmm20", "xmm21", "xmm22", "xmm23",
3315 "xmm24", "xmm25", "xmm26", "xmm27",
3316 "xmm28", "xmm29", "xmm30", "xmm31"
3318 static const char *att_names_xmm[] = {
3319 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3320 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3321 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3322 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3323 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3324 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3325 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3326 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3329 static const char **names_ymm;
3330 static const char *intel_names_ymm[] = {
3331 "ymm0", "ymm1", "ymm2", "ymm3",
3332 "ymm4", "ymm5", "ymm6", "ymm7",
3333 "ymm8", "ymm9", "ymm10", "ymm11",
3334 "ymm12", "ymm13", "ymm14", "ymm15",
3335 "ymm16", "ymm17", "ymm18", "ymm19",
3336 "ymm20", "ymm21", "ymm22", "ymm23",
3337 "ymm24", "ymm25", "ymm26", "ymm27",
3338 "ymm28", "ymm29", "ymm30", "ymm31"
3340 static const char *att_names_ymm[] = {
3341 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3342 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3343 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3344 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3345 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3346 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3347 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3348 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3351 static const char **names_zmm;
3352 static const char *intel_names_zmm[] = {
3353 "zmm0", "zmm1", "zmm2", "zmm3",
3354 "zmm4", "zmm5", "zmm6", "zmm7",
3355 "zmm8", "zmm9", "zmm10", "zmm11",
3356 "zmm12", "zmm13", "zmm14", "zmm15",
3357 "zmm16", "zmm17", "zmm18", "zmm19",
3358 "zmm20", "zmm21", "zmm22", "zmm23",
3359 "zmm24", "zmm25", "zmm26", "zmm27",
3360 "zmm28", "zmm29", "zmm30", "zmm31"
3362 static const char *att_names_zmm[] = {
3363 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3364 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3365 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3366 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3367 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3368 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3369 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3370 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3373 static const char **names_mask;
3374 static const char *intel_names_mask[] = {
3375 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3377 static const char *att_names_mask[] = {
3378 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3381 static const char *names_rounding[] =
3389 static const struct dis386 reg_table[][8] = {
3392 { "addA", { Ebh1, Ib }, 0 },
3393 { "orA", { Ebh1, Ib }, 0 },
3394 { "adcA", { Ebh1, Ib }, 0 },
3395 { "sbbA", { Ebh1, Ib }, 0 },
3396 { "andA", { Ebh1, Ib }, 0 },
3397 { "subA", { Ebh1, Ib }, 0 },
3398 { "xorA", { Ebh1, Ib }, 0 },
3399 { "cmpA", { Eb, Ib }, 0 },
3403 { "addQ", { Evh1, Iv }, 0 },
3404 { "orQ", { Evh1, Iv }, 0 },
3405 { "adcQ", { Evh1, Iv }, 0 },
3406 { "sbbQ", { Evh1, Iv }, 0 },
3407 { "andQ", { Evh1, Iv }, 0 },
3408 { "subQ", { Evh1, Iv }, 0 },
3409 { "xorQ", { Evh1, Iv }, 0 },
3410 { "cmpQ", { Ev, Iv }, 0 },
3414 { X86_64_TABLE (X86_64_82_REG_0) },
3415 { X86_64_TABLE (X86_64_82_REG_1) },
3416 { X86_64_TABLE (X86_64_82_REG_2) },
3417 { X86_64_TABLE (X86_64_82_REG_3) },
3418 { X86_64_TABLE (X86_64_82_REG_4) },
3419 { X86_64_TABLE (X86_64_82_REG_5) },
3420 { X86_64_TABLE (X86_64_82_REG_6) },
3421 { X86_64_TABLE (X86_64_82_REG_7) },
3425 { "addQ", { Evh1, sIb }, 0 },
3426 { "orQ", { Evh1, sIb }, 0 },
3427 { "adcQ", { Evh1, sIb }, 0 },
3428 { "sbbQ", { Evh1, sIb }, 0 },
3429 { "andQ", { Evh1, sIb }, 0 },
3430 { "subQ", { Evh1, sIb }, 0 },
3431 { "xorQ", { Evh1, sIb }, 0 },
3432 { "cmpQ", { Ev, sIb }, 0 },
3436 { "popU", { stackEv }, 0 },
3437 { XOP_8F_TABLE (XOP_09) },
3441 { XOP_8F_TABLE (XOP_09) },
3445 { "rolA", { Eb, Ib }, 0 },
3446 { "rorA", { Eb, Ib }, 0 },
3447 { "rclA", { Eb, Ib }, 0 },
3448 { "rcrA", { Eb, Ib }, 0 },
3449 { "shlA", { Eb, Ib }, 0 },
3450 { "shrA", { Eb, Ib }, 0 },
3452 { "sarA", { Eb, Ib }, 0 },
3456 { "rolQ", { Ev, Ib }, 0 },
3457 { "rorQ", { Ev, Ib }, 0 },
3458 { "rclQ", { Ev, Ib }, 0 },
3459 { "rcrQ", { Ev, Ib }, 0 },
3460 { "shlQ", { Ev, Ib }, 0 },
3461 { "shrQ", { Ev, Ib }, 0 },
3463 { "sarQ", { Ev, Ib }, 0 },
3467 { "movA", { Ebh3, Ib }, 0 },
3474 { MOD_TABLE (MOD_C6_REG_7) },
3478 { "movQ", { Evh3, Iv }, 0 },
3485 { MOD_TABLE (MOD_C7_REG_7) },
3489 { "rolA", { Eb, I1 }, 0 },
3490 { "rorA", { Eb, I1 }, 0 },
3491 { "rclA", { Eb, I1 }, 0 },
3492 { "rcrA", { Eb, I1 }, 0 },
3493 { "shlA", { Eb, I1 }, 0 },
3494 { "shrA", { Eb, I1 }, 0 },
3496 { "sarA", { Eb, I1 }, 0 },
3500 { "rolQ", { Ev, I1 }, 0 },
3501 { "rorQ", { Ev, I1 }, 0 },
3502 { "rclQ", { Ev, I1 }, 0 },
3503 { "rcrQ", { Ev, I1 }, 0 },
3504 { "shlQ", { Ev, I1 }, 0 },
3505 { "shrQ", { Ev, I1 }, 0 },
3507 { "sarQ", { Ev, I1 }, 0 },
3511 { "rolA", { Eb, CL }, 0 },
3512 { "rorA", { Eb, CL }, 0 },
3513 { "rclA", { Eb, CL }, 0 },
3514 { "rcrA", { Eb, CL }, 0 },
3515 { "shlA", { Eb, CL }, 0 },
3516 { "shrA", { Eb, CL }, 0 },
3518 { "sarA", { Eb, CL }, 0 },
3522 { "rolQ", { Ev, CL }, 0 },
3523 { "rorQ", { Ev, CL }, 0 },
3524 { "rclQ", { Ev, CL }, 0 },
3525 { "rcrQ", { Ev, CL }, 0 },
3526 { "shlQ", { Ev, CL }, 0 },
3527 { "shrQ", { Ev, CL }, 0 },
3529 { "sarQ", { Ev, CL }, 0 },
3533 { "testA", { Eb, Ib }, 0 },
3535 { "notA", { Ebh1 }, 0 },
3536 { "negA", { Ebh1 }, 0 },
3537 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
3538 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
3539 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
3540 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
3544 { "testQ", { Ev, Iv }, 0 },
3546 { "notQ", { Evh1 }, 0 },
3547 { "negQ", { Evh1 }, 0 },
3548 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
3549 { "imulQ", { Ev }, 0 },
3550 { "divQ", { Ev }, 0 },
3551 { "idivQ", { Ev }, 0 },
3555 { "incA", { Ebh1 }, 0 },
3556 { "decA", { Ebh1 }, 0 },
3560 { "incQ", { Evh1 }, 0 },
3561 { "decQ", { Evh1 }, 0 },
3562 { "call{&|}", { indirEv, BND }, 0 },
3563 { MOD_TABLE (MOD_FF_REG_3) },
3564 { "jmp{&|}", { indirEv, BND }, 0 },
3565 { MOD_TABLE (MOD_FF_REG_5) },
3566 { "pushU", { stackEv }, 0 },
3571 { "sldtD", { Sv }, 0 },
3572 { "strD", { Sv }, 0 },
3573 { "lldt", { Ew }, 0 },
3574 { "ltr", { Ew }, 0 },
3575 { "verr", { Ew }, 0 },
3576 { "verw", { Ew }, 0 },
3582 { MOD_TABLE (MOD_0F01_REG_0) },
3583 { MOD_TABLE (MOD_0F01_REG_1) },
3584 { MOD_TABLE (MOD_0F01_REG_2) },
3585 { MOD_TABLE (MOD_0F01_REG_3) },
3586 { "smswD", { Sv }, 0 },
3587 { MOD_TABLE (MOD_0F01_REG_5) },
3588 { "lmsw", { Ew }, 0 },
3589 { MOD_TABLE (MOD_0F01_REG_7) },
3593 { "prefetch", { Mb }, 0 },
3594 { "prefetchw", { Mb }, 0 },
3595 { "prefetchwt1", { Mb }, 0 },
3596 { "prefetch", { Mb }, 0 },
3597 { "prefetch", { Mb }, 0 },
3598 { "prefetch", { Mb }, 0 },
3599 { "prefetch", { Mb }, 0 },
3600 { "prefetch", { Mb }, 0 },
3604 { MOD_TABLE (MOD_0F18_REG_0) },
3605 { MOD_TABLE (MOD_0F18_REG_1) },
3606 { MOD_TABLE (MOD_0F18_REG_2) },
3607 { MOD_TABLE (MOD_0F18_REG_3) },
3608 { MOD_TABLE (MOD_0F18_REG_4) },
3609 { MOD_TABLE (MOD_0F18_REG_5) },
3610 { MOD_TABLE (MOD_0F18_REG_6) },
3611 { MOD_TABLE (MOD_0F18_REG_7) },
3617 { MOD_TABLE (MOD_0F71_REG_2) },
3619 { MOD_TABLE (MOD_0F71_REG_4) },
3621 { MOD_TABLE (MOD_0F71_REG_6) },
3627 { MOD_TABLE (MOD_0F72_REG_2) },
3629 { MOD_TABLE (MOD_0F72_REG_4) },
3631 { MOD_TABLE (MOD_0F72_REG_6) },
3637 { MOD_TABLE (MOD_0F73_REG_2) },
3638 { MOD_TABLE (MOD_0F73_REG_3) },
3641 { MOD_TABLE (MOD_0F73_REG_6) },
3642 { MOD_TABLE (MOD_0F73_REG_7) },
3646 { "montmul", { { OP_0f07, 0 } }, 0 },
3647 { "xsha1", { { OP_0f07, 0 } }, 0 },
3648 { "xsha256", { { OP_0f07, 0 } }, 0 },
3652 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
3653 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
3654 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
3655 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
3656 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
3657 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
3661 { MOD_TABLE (MOD_0FAE_REG_0) },
3662 { MOD_TABLE (MOD_0FAE_REG_1) },
3663 { MOD_TABLE (MOD_0FAE_REG_2) },
3664 { MOD_TABLE (MOD_0FAE_REG_3) },
3665 { MOD_TABLE (MOD_0FAE_REG_4) },
3666 { MOD_TABLE (MOD_0FAE_REG_5) },
3667 { MOD_TABLE (MOD_0FAE_REG_6) },
3668 { MOD_TABLE (MOD_0FAE_REG_7) },
3676 { "btQ", { Ev, Ib }, 0 },
3677 { "btsQ", { Evh1, Ib }, 0 },
3678 { "btrQ", { Evh1, Ib }, 0 },
3679 { "btcQ", { Evh1, Ib }, 0 },
3684 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3686 { MOD_TABLE (MOD_0FC7_REG_3) },
3687 { MOD_TABLE (MOD_0FC7_REG_4) },
3688 { MOD_TABLE (MOD_0FC7_REG_5) },
3689 { MOD_TABLE (MOD_0FC7_REG_6) },
3690 { MOD_TABLE (MOD_0FC7_REG_7) },
3696 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3698 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3700 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3706 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3708 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3710 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3716 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3717 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3720 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3721 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3727 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3728 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3730 /* REG_VEX_0F38F3 */
3733 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3734 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3735 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3739 { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3740 { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3744 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3745 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3747 /* REG_XOP_TBM_01 */
3750 { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3751 { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3752 { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 },
3753 { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3754 { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 },
3755 { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 },
3756 { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3758 /* REG_XOP_TBM_02 */
3761 { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3766 { "blci", { { OP_LWP_E, 0 }, Ev }, 0 },
3768 #define NEED_REG_TABLE
3769 #include "i386-dis-evex.h"
3770 #undef NEED_REG_TABLE
3773 static const struct dis386 prefix_table[][4] = {
3776 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3777 { "pause", { XX }, 0 },
3778 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3779 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3784 { "movups", { XM, EXx }, PREFIX_OPCODE },
3785 { "movss", { XM, EXd }, PREFIX_OPCODE },
3786 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3787 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3792 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3793 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3794 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3795 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3800 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3801 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3802 { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3803 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3808 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3809 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3810 { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3815 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3816 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3817 { "bndmov", { Gbnd, Ebnd }, 0 },
3818 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3823 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3824 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3825 { "bndmov", { Ebnd, Gbnd }, 0 },
3826 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3831 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3832 { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3833 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3834 { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3839 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3840 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3841 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3842 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3847 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3848 { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3849 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3850 { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3855 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3856 { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3857 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3858 { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3863 { "ucomiss",{ XM, EXd }, 0 },
3865 { "ucomisd",{ XM, EXq }, 0 },
3870 { "comiss", { XM, EXd }, 0 },
3872 { "comisd", { XM, EXq }, 0 },
3877 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3878 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3879 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3880 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3885 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3886 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3891 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3892 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3897 { "addps", { XM, EXx }, PREFIX_OPCODE },
3898 { "addss", { XM, EXd }, PREFIX_OPCODE },
3899 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3900 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3905 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3906 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3907 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3908 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3913 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3914 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3915 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3916 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3921 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3922 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3923 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3928 { "subps", { XM, EXx }, PREFIX_OPCODE },
3929 { "subss", { XM, EXd }, PREFIX_OPCODE },
3930 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3931 { "subsd", { XM, EXq }, PREFIX_OPCODE },
3936 { "minps", { XM, EXx }, PREFIX_OPCODE },
3937 { "minss", { XM, EXd }, PREFIX_OPCODE },
3938 { "minpd", { XM, EXx }, PREFIX_OPCODE },
3939 { "minsd", { XM, EXq }, PREFIX_OPCODE },
3944 { "divps", { XM, EXx }, PREFIX_OPCODE },
3945 { "divss", { XM, EXd }, PREFIX_OPCODE },
3946 { "divpd", { XM, EXx }, PREFIX_OPCODE },
3947 { "divsd", { XM, EXq }, PREFIX_OPCODE },
3952 { "maxps", { XM, EXx }, PREFIX_OPCODE },
3953 { "maxss", { XM, EXd }, PREFIX_OPCODE },
3954 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
3955 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
3960 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3962 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3967 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3969 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3974 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3976 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3983 { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3990 { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3995 { "movq", { MX, EM }, PREFIX_OPCODE },
3996 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3997 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4002 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4003 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4004 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4005 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4008 /* PREFIX_0F73_REG_3 */
4012 { "psrldq", { XS, Ib }, 0 },
4015 /* PREFIX_0F73_REG_7 */
4019 { "pslldq", { XS, Ib }, 0 },
4024 {"vmread", { Em, Gm }, 0 },
4026 {"extrq", { XS, Ib, Ib }, 0 },
4027 {"insertq", { XM, XS, Ib, Ib }, 0 },
4032 {"vmwrite", { Gm, Em }, 0 },
4034 {"extrq", { XM, XS }, 0 },
4035 {"insertq", { XM, XS }, 0 },
4042 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4043 { "haddps", { XM, EXx }, PREFIX_OPCODE },
4050 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4051 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4056 { "movK", { Edq, MX }, PREFIX_OPCODE },
4057 { "movq", { XM, EXq }, PREFIX_OPCODE },
4058 { "movK", { Edq, XM }, PREFIX_OPCODE },
4063 { "movq", { EMS, MX }, PREFIX_OPCODE },
4064 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4065 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4068 /* PREFIX_0FAE_REG_0 */
4071 { "rdfsbase", { Ev }, 0 },
4074 /* PREFIX_0FAE_REG_1 */
4077 { "rdgsbase", { Ev }, 0 },
4080 /* PREFIX_0FAE_REG_2 */
4083 { "wrfsbase", { Ev }, 0 },
4086 /* PREFIX_0FAE_REG_3 */
4089 { "wrgsbase", { Ev }, 0 },
4092 /* PREFIX_MOD_0_0FAE_REG_4 */
4094 { "xsave", { FXSAVE }, 0 },
4095 { "ptwrite%LQ", { Edq }, 0 },
4098 /* PREFIX_MOD_3_0FAE_REG_4 */
4101 { "ptwrite%LQ", { Edq }, 0 },
4104 /* PREFIX_0FAE_REG_6 */
4106 { "xsaveopt", { FXSAVE }, 0 },
4108 { "clwb", { Mb }, 0 },
4111 /* PREFIX_0FAE_REG_7 */
4113 { "clflush", { Mb }, 0 },
4115 { "clflushopt", { Mb }, 0 },
4121 { "popcntS", { Gv, Ev }, 0 },
4126 { "bsfS", { Gv, Ev }, 0 },
4127 { "tzcntS", { Gv, Ev }, 0 },
4128 { "bsfS", { Gv, Ev }, 0 },
4133 { "bsrS", { Gv, Ev }, 0 },
4134 { "lzcntS", { Gv, Ev }, 0 },
4135 { "bsrS", { Gv, Ev }, 0 },
4140 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
4141 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
4142 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
4143 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
4146 /* PREFIX_MOD_0_0FC3 */
4148 { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4151 /* PREFIX_MOD_0_0FC7_REG_6 */
4153 { "vmptrld",{ Mq }, 0 },
4154 { "vmxon", { Mq }, 0 },
4155 { "vmclear",{ Mq }, 0 },
4158 /* PREFIX_MOD_3_0FC7_REG_6 */
4160 { "rdrand", { Ev }, 0 },
4162 { "rdrand", { Ev }, 0 }
4165 /* PREFIX_MOD_3_0FC7_REG_7 */
4167 { "rdseed", { Ev }, 0 },
4168 { "rdpid", { Em }, 0 },
4169 { "rdseed", { Ev }, 0 },
4176 { "addsubpd", { XM, EXx }, 0 },
4177 { "addsubps", { XM, EXx }, 0 },
4183 { "movq2dq",{ XM, MS }, 0 },
4184 { "movq", { EXqS, XM }, 0 },
4185 { "movdq2q",{ MX, XS }, 0 },
4191 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4192 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4193 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4198 { "movntq", { Mq, MX }, PREFIX_OPCODE },
4200 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4208 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4213 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4215 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4222 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4229 { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4236 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4243 { "ptest", { XM, EXx }, PREFIX_OPCODE },
4250 { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4257 { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4264 { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4271 { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4278 { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4285 { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4292 { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4299 { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4306 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4313 { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4320 { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4327 { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4334 { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4341 { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4348 { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4355 { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4362 { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4369 { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4376 { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4383 { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4390 { "pminud", { XM, EXx }, PREFIX_OPCODE },
4397 { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4404 { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4411 { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4418 { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4425 { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4432 { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4439 { "invept", { Gm, Mo }, PREFIX_OPCODE },
4446 { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4453 { "invpcid", { Gm, M }, PREFIX_OPCODE },
4458 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4463 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4468 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4473 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4478 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4483 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4490 { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4497 { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4504 { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4511 { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4518 { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4523 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4525 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4526 { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4531 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4533 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4534 { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4540 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
4541 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
4549 { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4556 { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4563 { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4570 { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4577 { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4584 { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4591 { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4598 { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4605 { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4612 { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4619 { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4626 { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4633 { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4640 { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4647 { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE },
4654 { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE },
4661 { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4668 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4675 { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4682 { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE },
4689 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4696 { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4701 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4708 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4711 /* PREFIX_VEX_0F10 */
4713 { VEX_W_TABLE (VEX_W_0F10_P_0) },
4714 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4715 { VEX_W_TABLE (VEX_W_0F10_P_2) },
4716 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4719 /* PREFIX_VEX_0F11 */
4721 { VEX_W_TABLE (VEX_W_0F11_P_0) },
4722 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4723 { VEX_W_TABLE (VEX_W_0F11_P_2) },
4724 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4727 /* PREFIX_VEX_0F12 */
4729 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4730 { VEX_W_TABLE (VEX_W_0F12_P_1) },
4731 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4732 { VEX_W_TABLE (VEX_W_0F12_P_3) },
4735 /* PREFIX_VEX_0F16 */
4737 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4738 { VEX_W_TABLE (VEX_W_0F16_P_1) },
4739 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4742 /* PREFIX_VEX_0F2A */
4745 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4747 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4750 /* PREFIX_VEX_0F2C */
4753 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4755 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4758 /* PREFIX_VEX_0F2D */
4761 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4763 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4766 /* PREFIX_VEX_0F2E */
4768 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4770 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4773 /* PREFIX_VEX_0F2F */
4775 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4777 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4780 /* PREFIX_VEX_0F41 */
4782 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4784 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4787 /* PREFIX_VEX_0F42 */
4789 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4791 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4794 /* PREFIX_VEX_0F44 */
4796 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4798 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4801 /* PREFIX_VEX_0F45 */
4803 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4805 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4808 /* PREFIX_VEX_0F46 */
4810 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4812 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4815 /* PREFIX_VEX_0F47 */
4817 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4819 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4822 /* PREFIX_VEX_0F4A */
4824 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4826 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4829 /* PREFIX_VEX_0F4B */
4831 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4833 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4836 /* PREFIX_VEX_0F51 */
4838 { VEX_W_TABLE (VEX_W_0F51_P_0) },
4839 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4840 { VEX_W_TABLE (VEX_W_0F51_P_2) },
4841 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4844 /* PREFIX_VEX_0F52 */
4846 { VEX_W_TABLE (VEX_W_0F52_P_0) },
4847 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4850 /* PREFIX_VEX_0F53 */
4852 { VEX_W_TABLE (VEX_W_0F53_P_0) },
4853 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4856 /* PREFIX_VEX_0F58 */
4858 { VEX_W_TABLE (VEX_W_0F58_P_0) },
4859 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4860 { VEX_W_TABLE (VEX_W_0F58_P_2) },
4861 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4864 /* PREFIX_VEX_0F59 */
4866 { VEX_W_TABLE (VEX_W_0F59_P_0) },
4867 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4868 { VEX_W_TABLE (VEX_W_0F59_P_2) },
4869 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4872 /* PREFIX_VEX_0F5A */
4874 { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4875 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4876 { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4877 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4880 /* PREFIX_VEX_0F5B */
4882 { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4883 { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4884 { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4887 /* PREFIX_VEX_0F5C */
4889 { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4890 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4891 { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4892 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4895 /* PREFIX_VEX_0F5D */
4897 { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4898 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4899 { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4900 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4903 /* PREFIX_VEX_0F5E */
4905 { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4906 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4907 { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4908 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4911 /* PREFIX_VEX_0F5F */
4913 { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4914 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4915 { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4916 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4919 /* PREFIX_VEX_0F60 */
4923 { VEX_W_TABLE (VEX_W_0F60_P_2) },
4926 /* PREFIX_VEX_0F61 */
4930 { VEX_W_TABLE (VEX_W_0F61_P_2) },
4933 /* PREFIX_VEX_0F62 */
4937 { VEX_W_TABLE (VEX_W_0F62_P_2) },
4940 /* PREFIX_VEX_0F63 */
4944 { VEX_W_TABLE (VEX_W_0F63_P_2) },
4947 /* PREFIX_VEX_0F64 */
4951 { VEX_W_TABLE (VEX_W_0F64_P_2) },
4954 /* PREFIX_VEX_0F65 */
4958 { VEX_W_TABLE (VEX_W_0F65_P_2) },
4961 /* PREFIX_VEX_0F66 */
4965 { VEX_W_TABLE (VEX_W_0F66_P_2) },
4968 /* PREFIX_VEX_0F67 */
4972 { VEX_W_TABLE (VEX_W_0F67_P_2) },
4975 /* PREFIX_VEX_0F68 */
4979 { VEX_W_TABLE (VEX_W_0F68_P_2) },
4982 /* PREFIX_VEX_0F69 */
4986 { VEX_W_TABLE (VEX_W_0F69_P_2) },
4989 /* PREFIX_VEX_0F6A */
4993 { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4996 /* PREFIX_VEX_0F6B */
5000 { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5003 /* PREFIX_VEX_0F6C */
5007 { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5010 /* PREFIX_VEX_0F6D */
5014 { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5017 /* PREFIX_VEX_0F6E */
5021 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5024 /* PREFIX_VEX_0F6F */
5027 { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5028 { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5031 /* PREFIX_VEX_0F70 */
5034 { VEX_W_TABLE (VEX_W_0F70_P_1) },
5035 { VEX_W_TABLE (VEX_W_0F70_P_2) },
5036 { VEX_W_TABLE (VEX_W_0F70_P_3) },
5039 /* PREFIX_VEX_0F71_REG_2 */
5043 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5046 /* PREFIX_VEX_0F71_REG_4 */
5050 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5053 /* PREFIX_VEX_0F71_REG_6 */
5057 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5060 /* PREFIX_VEX_0F72_REG_2 */
5064 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5067 /* PREFIX_VEX_0F72_REG_4 */
5071 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5074 /* PREFIX_VEX_0F72_REG_6 */
5078 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5081 /* PREFIX_VEX_0F73_REG_2 */
5085 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5088 /* PREFIX_VEX_0F73_REG_3 */
5092 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5095 /* PREFIX_VEX_0F73_REG_6 */
5099 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5102 /* PREFIX_VEX_0F73_REG_7 */
5106 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5109 /* PREFIX_VEX_0F74 */
5113 { VEX_W_TABLE (VEX_W_0F74_P_2) },
5116 /* PREFIX_VEX_0F75 */
5120 { VEX_W_TABLE (VEX_W_0F75_P_2) },
5123 /* PREFIX_VEX_0F76 */
5127 { VEX_W_TABLE (VEX_W_0F76_P_2) },
5130 /* PREFIX_VEX_0F77 */
5132 { VEX_W_TABLE (VEX_W_0F77_P_0) },
5135 /* PREFIX_VEX_0F7C */
5139 { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5140 { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5143 /* PREFIX_VEX_0F7D */
5147 { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5148 { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5151 /* PREFIX_VEX_0F7E */
5154 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5155 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5158 /* PREFIX_VEX_0F7F */
5161 { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5162 { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5165 /* PREFIX_VEX_0F90 */
5167 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5169 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5172 /* PREFIX_VEX_0F91 */
5174 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5176 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5179 /* PREFIX_VEX_0F92 */
5181 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5183 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5184 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5187 /* PREFIX_VEX_0F93 */
5189 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5191 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5192 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5195 /* PREFIX_VEX_0F98 */
5197 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5199 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5202 /* PREFIX_VEX_0F99 */
5204 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5206 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5209 /* PREFIX_VEX_0FC2 */
5211 { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5212 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5213 { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5214 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5217 /* PREFIX_VEX_0FC4 */
5221 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5224 /* PREFIX_VEX_0FC5 */
5228 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5231 /* PREFIX_VEX_0FD0 */
5235 { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5236 { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5239 /* PREFIX_VEX_0FD1 */
5243 { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5246 /* PREFIX_VEX_0FD2 */
5250 { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5253 /* PREFIX_VEX_0FD3 */
5257 { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5260 /* PREFIX_VEX_0FD4 */
5264 { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5267 /* PREFIX_VEX_0FD5 */
5271 { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5274 /* PREFIX_VEX_0FD6 */
5278 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5281 /* PREFIX_VEX_0FD7 */
5285 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5288 /* PREFIX_VEX_0FD8 */
5292 { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5295 /* PREFIX_VEX_0FD9 */
5299 { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5302 /* PREFIX_VEX_0FDA */
5306 { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5309 /* PREFIX_VEX_0FDB */
5313 { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5316 /* PREFIX_VEX_0FDC */
5320 { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5323 /* PREFIX_VEX_0FDD */
5327 { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5330 /* PREFIX_VEX_0FDE */
5334 { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5337 /* PREFIX_VEX_0FDF */
5341 { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5344 /* PREFIX_VEX_0FE0 */
5348 { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5351 /* PREFIX_VEX_0FE1 */
5355 { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5358 /* PREFIX_VEX_0FE2 */
5362 { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5365 /* PREFIX_VEX_0FE3 */
5369 { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5372 /* PREFIX_VEX_0FE4 */
5376 { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5379 /* PREFIX_VEX_0FE5 */
5383 { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5386 /* PREFIX_VEX_0FE6 */
5389 { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5390 { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5391 { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5394 /* PREFIX_VEX_0FE7 */
5398 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5401 /* PREFIX_VEX_0FE8 */
5405 { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5408 /* PREFIX_VEX_0FE9 */
5412 { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5415 /* PREFIX_VEX_0FEA */
5419 { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5422 /* PREFIX_VEX_0FEB */
5426 { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5429 /* PREFIX_VEX_0FEC */
5433 { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5436 /* PREFIX_VEX_0FED */
5440 { VEX_W_TABLE (VEX_W_0FED_P_2) },
5443 /* PREFIX_VEX_0FEE */
5447 { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5450 /* PREFIX_VEX_0FEF */
5454 { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5457 /* PREFIX_VEX_0FF0 */
5462 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5465 /* PREFIX_VEX_0FF1 */
5469 { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5472 /* PREFIX_VEX_0FF2 */
5476 { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5479 /* PREFIX_VEX_0FF3 */
5483 { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5486 /* PREFIX_VEX_0FF4 */
5490 { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5493 /* PREFIX_VEX_0FF5 */
5497 { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5500 /* PREFIX_VEX_0FF6 */
5504 { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5507 /* PREFIX_VEX_0FF7 */
5511 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5514 /* PREFIX_VEX_0FF8 */
5518 { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5521 /* PREFIX_VEX_0FF9 */
5525 { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5528 /* PREFIX_VEX_0FFA */
5532 { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5535 /* PREFIX_VEX_0FFB */
5539 { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5542 /* PREFIX_VEX_0FFC */
5546 { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5549 /* PREFIX_VEX_0FFD */
5553 { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5556 /* PREFIX_VEX_0FFE */
5560 { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5563 /* PREFIX_VEX_0F3800 */
5567 { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5570 /* PREFIX_VEX_0F3801 */
5574 { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5577 /* PREFIX_VEX_0F3802 */
5581 { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5584 /* PREFIX_VEX_0F3803 */
5588 { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5591 /* PREFIX_VEX_0F3804 */
5595 { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5598 /* PREFIX_VEX_0F3805 */
5602 { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5605 /* PREFIX_VEX_0F3806 */
5609 { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5612 /* PREFIX_VEX_0F3807 */
5616 { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5619 /* PREFIX_VEX_0F3808 */
5623 { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5626 /* PREFIX_VEX_0F3809 */
5630 { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5633 /* PREFIX_VEX_0F380A */
5637 { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5640 /* PREFIX_VEX_0F380B */
5644 { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5647 /* PREFIX_VEX_0F380C */
5651 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5654 /* PREFIX_VEX_0F380D */
5658 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5661 /* PREFIX_VEX_0F380E */
5665 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5668 /* PREFIX_VEX_0F380F */
5672 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5675 /* PREFIX_VEX_0F3813 */
5679 { "vcvtph2ps", { XM, EXxmmq }, 0 },
5682 /* PREFIX_VEX_0F3816 */
5686 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5689 /* PREFIX_VEX_0F3817 */
5693 { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5696 /* PREFIX_VEX_0F3818 */
5700 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5703 /* PREFIX_VEX_0F3819 */
5707 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5710 /* PREFIX_VEX_0F381A */
5714 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5717 /* PREFIX_VEX_0F381C */
5721 { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5724 /* PREFIX_VEX_0F381D */
5728 { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5731 /* PREFIX_VEX_0F381E */
5735 { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5738 /* PREFIX_VEX_0F3820 */
5742 { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5745 /* PREFIX_VEX_0F3821 */
5749 { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5752 /* PREFIX_VEX_0F3822 */
5756 { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5759 /* PREFIX_VEX_0F3823 */
5763 { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5766 /* PREFIX_VEX_0F3824 */
5770 { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5773 /* PREFIX_VEX_0F3825 */
5777 { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5780 /* PREFIX_VEX_0F3828 */
5784 { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5787 /* PREFIX_VEX_0F3829 */
5791 { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5794 /* PREFIX_VEX_0F382A */
5798 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5801 /* PREFIX_VEX_0F382B */
5805 { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5808 /* PREFIX_VEX_0F382C */
5812 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5815 /* PREFIX_VEX_0F382D */
5819 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5822 /* PREFIX_VEX_0F382E */
5826 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5829 /* PREFIX_VEX_0F382F */
5833 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5836 /* PREFIX_VEX_0F3830 */
5840 { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5843 /* PREFIX_VEX_0F3831 */
5847 { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5850 /* PREFIX_VEX_0F3832 */
5854 { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5857 /* PREFIX_VEX_0F3833 */
5861 { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5864 /* PREFIX_VEX_0F3834 */
5868 { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5871 /* PREFIX_VEX_0F3835 */
5875 { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5878 /* PREFIX_VEX_0F3836 */
5882 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5885 /* PREFIX_VEX_0F3837 */
5889 { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5892 /* PREFIX_VEX_0F3838 */
5896 { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5899 /* PREFIX_VEX_0F3839 */
5903 { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5906 /* PREFIX_VEX_0F383A */
5910 { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5913 /* PREFIX_VEX_0F383B */
5917 { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5920 /* PREFIX_VEX_0F383C */
5924 { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5927 /* PREFIX_VEX_0F383D */
5931 { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5934 /* PREFIX_VEX_0F383E */
5938 { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5941 /* PREFIX_VEX_0F383F */
5945 { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5948 /* PREFIX_VEX_0F3840 */
5952 { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5955 /* PREFIX_VEX_0F3841 */
5959 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5962 /* PREFIX_VEX_0F3845 */
5966 { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5969 /* PREFIX_VEX_0F3846 */
5973 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5976 /* PREFIX_VEX_0F3847 */
5980 { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5983 /* PREFIX_VEX_0F3858 */
5987 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5990 /* PREFIX_VEX_0F3859 */
5994 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5997 /* PREFIX_VEX_0F385A */
6001 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6004 /* PREFIX_VEX_0F3878 */
6008 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6011 /* PREFIX_VEX_0F3879 */
6015 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6018 /* PREFIX_VEX_0F388C */
6022 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6025 /* PREFIX_VEX_0F388E */
6029 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6032 /* PREFIX_VEX_0F3890 */
6036 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6039 /* PREFIX_VEX_0F3891 */
6043 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6046 /* PREFIX_VEX_0F3892 */
6050 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6053 /* PREFIX_VEX_0F3893 */
6057 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6060 /* PREFIX_VEX_0F3896 */
6064 { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6067 /* PREFIX_VEX_0F3897 */
6071 { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6074 /* PREFIX_VEX_0F3898 */
6078 { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6081 /* PREFIX_VEX_0F3899 */
6085 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6088 /* PREFIX_VEX_0F389A */
6092 { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6095 /* PREFIX_VEX_0F389B */
6099 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6102 /* PREFIX_VEX_0F389C */
6106 { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6109 /* PREFIX_VEX_0F389D */
6113 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6116 /* PREFIX_VEX_0F389E */
6120 { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6123 /* PREFIX_VEX_0F389F */
6127 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6130 /* PREFIX_VEX_0F38A6 */
6134 { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6138 /* PREFIX_VEX_0F38A7 */
6142 { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6145 /* PREFIX_VEX_0F38A8 */
6149 { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6152 /* PREFIX_VEX_0F38A9 */
6156 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6159 /* PREFIX_VEX_0F38AA */
6163 { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6166 /* PREFIX_VEX_0F38AB */
6170 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6173 /* PREFIX_VEX_0F38AC */
6177 { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6180 /* PREFIX_VEX_0F38AD */
6184 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6187 /* PREFIX_VEX_0F38AE */
6191 { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6194 /* PREFIX_VEX_0F38AF */
6198 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6201 /* PREFIX_VEX_0F38B6 */
6205 { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6208 /* PREFIX_VEX_0F38B7 */
6212 { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6215 /* PREFIX_VEX_0F38B8 */
6219 { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6222 /* PREFIX_VEX_0F38B9 */
6226 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6229 /* PREFIX_VEX_0F38BA */
6233 { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6236 /* PREFIX_VEX_0F38BB */
6240 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6243 /* PREFIX_VEX_0F38BC */
6247 { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6250 /* PREFIX_VEX_0F38BD */
6254 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6257 /* PREFIX_VEX_0F38BE */
6261 { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6264 /* PREFIX_VEX_0F38BF */
6268 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6271 /* PREFIX_VEX_0F38DB */
6275 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6278 /* PREFIX_VEX_0F38DC */
6282 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6285 /* PREFIX_VEX_0F38DD */
6289 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6292 /* PREFIX_VEX_0F38DE */
6296 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6299 /* PREFIX_VEX_0F38DF */
6303 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6306 /* PREFIX_VEX_0F38F2 */
6308 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6311 /* PREFIX_VEX_0F38F3_REG_1 */
6313 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6316 /* PREFIX_VEX_0F38F3_REG_2 */
6318 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6321 /* PREFIX_VEX_0F38F3_REG_3 */
6323 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6326 /* PREFIX_VEX_0F38F5 */
6328 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6329 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6331 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6334 /* PREFIX_VEX_0F38F6 */
6339 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6342 /* PREFIX_VEX_0F38F7 */
6344 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6345 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6346 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6347 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6350 /* PREFIX_VEX_0F3A00 */
6354 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6357 /* PREFIX_VEX_0F3A01 */
6361 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6364 /* PREFIX_VEX_0F3A02 */
6368 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6371 /* PREFIX_VEX_0F3A04 */
6375 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6378 /* PREFIX_VEX_0F3A05 */
6382 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6385 /* PREFIX_VEX_0F3A06 */
6389 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6392 /* PREFIX_VEX_0F3A08 */
6396 { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6399 /* PREFIX_VEX_0F3A09 */
6403 { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6406 /* PREFIX_VEX_0F3A0A */
6410 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6413 /* PREFIX_VEX_0F3A0B */
6417 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6420 /* PREFIX_VEX_0F3A0C */
6424 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6427 /* PREFIX_VEX_0F3A0D */
6431 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6434 /* PREFIX_VEX_0F3A0E */
6438 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6441 /* PREFIX_VEX_0F3A0F */
6445 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6448 /* PREFIX_VEX_0F3A14 */
6452 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6455 /* PREFIX_VEX_0F3A15 */
6459 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6462 /* PREFIX_VEX_0F3A16 */
6466 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6469 /* PREFIX_VEX_0F3A17 */
6473 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6476 /* PREFIX_VEX_0F3A18 */
6480 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6483 /* PREFIX_VEX_0F3A19 */
6487 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6490 /* PREFIX_VEX_0F3A1D */
6494 { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6497 /* PREFIX_VEX_0F3A20 */
6501 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6504 /* PREFIX_VEX_0F3A21 */
6508 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6511 /* PREFIX_VEX_0F3A22 */
6515 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6518 /* PREFIX_VEX_0F3A30 */
6522 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6525 /* PREFIX_VEX_0F3A31 */
6529 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6532 /* PREFIX_VEX_0F3A32 */
6536 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6539 /* PREFIX_VEX_0F3A33 */
6543 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6546 /* PREFIX_VEX_0F3A38 */
6550 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6553 /* PREFIX_VEX_0F3A39 */
6557 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6560 /* PREFIX_VEX_0F3A40 */
6564 { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6567 /* PREFIX_VEX_0F3A41 */
6571 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6574 /* PREFIX_VEX_0F3A42 */
6578 { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6581 /* PREFIX_VEX_0F3A44 */
6585 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6588 /* PREFIX_VEX_0F3A46 */
6592 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6595 /* PREFIX_VEX_0F3A48 */
6599 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6602 /* PREFIX_VEX_0F3A49 */
6606 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6609 /* PREFIX_VEX_0F3A4A */
6613 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6616 /* PREFIX_VEX_0F3A4B */
6620 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6623 /* PREFIX_VEX_0F3A4C */
6627 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6630 /* PREFIX_VEX_0F3A5C */
6634 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6637 /* PREFIX_VEX_0F3A5D */
6641 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6644 /* PREFIX_VEX_0F3A5E */
6648 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6651 /* PREFIX_VEX_0F3A5F */
6655 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6658 /* PREFIX_VEX_0F3A60 */
6662 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6666 /* PREFIX_VEX_0F3A61 */
6670 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6673 /* PREFIX_VEX_0F3A62 */
6677 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6680 /* PREFIX_VEX_0F3A63 */
6684 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6687 /* PREFIX_VEX_0F3A68 */
6691 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6694 /* PREFIX_VEX_0F3A69 */
6698 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6701 /* PREFIX_VEX_0F3A6A */
6705 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6708 /* PREFIX_VEX_0F3A6B */
6712 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6715 /* PREFIX_VEX_0F3A6C */
6719 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6722 /* PREFIX_VEX_0F3A6D */
6726 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6729 /* PREFIX_VEX_0F3A6E */
6733 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6736 /* PREFIX_VEX_0F3A6F */
6740 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6743 /* PREFIX_VEX_0F3A78 */
6747 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6750 /* PREFIX_VEX_0F3A79 */
6754 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6757 /* PREFIX_VEX_0F3A7A */
6761 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6764 /* PREFIX_VEX_0F3A7B */
6768 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6771 /* PREFIX_VEX_0F3A7C */
6775 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6779 /* PREFIX_VEX_0F3A7D */
6783 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6786 /* PREFIX_VEX_0F3A7E */
6790 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6793 /* PREFIX_VEX_0F3A7F */
6797 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6800 /* PREFIX_VEX_0F3ADF */
6804 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6807 /* PREFIX_VEX_0F3AF0 */
6812 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6815 #define NEED_PREFIX_TABLE
6816 #include "i386-dis-evex.h"
6817 #undef NEED_PREFIX_TABLE
6820 static const struct dis386 x86_64_table[][2] = {
6823 { "pushP", { es }, 0 },
6828 { "popP", { es }, 0 },
6833 { "pushP", { cs }, 0 },
6838 { "pushP", { ss }, 0 },
6843 { "popP", { ss }, 0 },
6848 { "pushP", { ds }, 0 },
6853 { "popP", { ds }, 0 },
6858 { "daa", { XX }, 0 },
6863 { "das", { XX }, 0 },
6868 { "aaa", { XX }, 0 },
6873 { "aas", { XX }, 0 },
6878 { "pushaP", { XX }, 0 },
6883 { "popaP", { XX }, 0 },
6888 { MOD_TABLE (MOD_62_32BIT) },
6889 { EVEX_TABLE (EVEX_0F) },
6894 { "arpl", { Ew, Gw }, 0 },
6895 { "movs{lq|xd}", { Gv, Ed }, 0 },
6900 { "ins{R|}", { Yzr, indirDX }, 0 },
6901 { "ins{G|}", { Yzr, indirDX }, 0 },
6906 { "outs{R|}", { indirDXr, Xz }, 0 },
6907 { "outs{G|}", { indirDXr, Xz }, 0 },
6910 /* X86_64_82_REG_0 */
6912 { "addA", { Ebh1, Ib }, 0 },
6915 /* X86_64_82_REG_1 */
6917 { "orA", { Ebh1, Ib }, 0 },
6920 /* X86_64_82_REG_2 */
6922 { "adcA", { Ebh1, Ib }, 0 },
6925 /* X86_64_82_REG_3 */
6927 { "sbbA", { Ebh1, Ib }, 0 },
6930 /* X86_64_82_REG_4 */
6932 { "andA", { Ebh1, Ib }, 0 },
6935 /* X86_64_82_REG_5 */
6937 { "subA", { Ebh1, Ib }, 0 },
6940 /* X86_64_82_REG_6 */
6942 { "xorA", { Ebh1, Ib }, 0 },
6945 /* X86_64_82_REG_7 */
6947 { "cmpA", { Eb, Ib }, 0 },
6952 { "Jcall{T|}", { Ap }, 0 },
6957 { MOD_TABLE (MOD_C4_32BIT) },
6958 { VEX_C4_TABLE (VEX_0F) },
6963 { MOD_TABLE (MOD_C5_32BIT) },
6964 { VEX_C5_TABLE (VEX_0F) },
6969 { "into", { XX }, 0 },
6974 { "aam", { Ib }, 0 },
6979 { "aad", { Ib }, 0 },
6984 { "callP", { Jv, BND }, 0 },
6985 { "call@", { Jv, BND }, 0 }
6990 { "jmpP", { Jv, BND }, 0 },
6991 { "jmp@", { Jv, BND }, 0 }
6996 { "Jjmp{T|}", { Ap }, 0 },
6999 /* X86_64_0F01_REG_0 */
7001 { "sgdt{Q|IQ}", { M }, 0 },
7002 { "sgdt", { M }, 0 },
7005 /* X86_64_0F01_REG_1 */
7007 { "sidt{Q|IQ}", { M }, 0 },
7008 { "sidt", { M }, 0 },
7011 /* X86_64_0F01_REG_2 */
7013 { "lgdt{Q|Q}", { M }, 0 },
7014 { "lgdt", { M }, 0 },
7017 /* X86_64_0F01_REG_3 */
7019 { "lidt{Q|Q}", { M }, 0 },
7020 { "lidt", { M }, 0 },
7024 static const struct dis386 three_byte_table[][256] = {
7026 /* THREE_BYTE_0F38 */
7029 { "pshufb", { MX, EM }, PREFIX_OPCODE },
7030 { "phaddw", { MX, EM }, PREFIX_OPCODE },
7031 { "phaddd", { MX, EM }, PREFIX_OPCODE },
7032 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
7033 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
7034 { "phsubw", { MX, EM }, PREFIX_OPCODE },
7035 { "phsubd", { MX, EM }, PREFIX_OPCODE },
7036 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
7038 { "psignb", { MX, EM }, PREFIX_OPCODE },
7039 { "psignw", { MX, EM }, PREFIX_OPCODE },
7040 { "psignd", { MX, EM }, PREFIX_OPCODE },
7041 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
7047 { PREFIX_TABLE (PREFIX_0F3810) },
7051 { PREFIX_TABLE (PREFIX_0F3814) },
7052 { PREFIX_TABLE (PREFIX_0F3815) },
7054 { PREFIX_TABLE (PREFIX_0F3817) },
7060 { "pabsb", { MX, EM }, PREFIX_OPCODE },
7061 { "pabsw", { MX, EM }, PREFIX_OPCODE },
7062 { "pabsd", { MX, EM }, PREFIX_OPCODE },
7065 { PREFIX_TABLE (PREFIX_0F3820) },
7066 { PREFIX_TABLE (PREFIX_0F3821) },
7067 { PREFIX_TABLE (PREFIX_0F3822) },
7068 { PREFIX_TABLE (PREFIX_0F3823) },
7069 { PREFIX_TABLE (PREFIX_0F3824) },
7070 { PREFIX_TABLE (PREFIX_0F3825) },
7074 { PREFIX_TABLE (PREFIX_0F3828) },
7075 { PREFIX_TABLE (PREFIX_0F3829) },
7076 { PREFIX_TABLE (PREFIX_0F382A) },
7077 { PREFIX_TABLE (PREFIX_0F382B) },
7083 { PREFIX_TABLE (PREFIX_0F3830) },
7084 { PREFIX_TABLE (PREFIX_0F3831) },
7085 { PREFIX_TABLE (PREFIX_0F3832) },
7086 { PREFIX_TABLE (PREFIX_0F3833) },
7087 { PREFIX_TABLE (PREFIX_0F3834) },
7088 { PREFIX_TABLE (PREFIX_0F3835) },
7090 { PREFIX_TABLE (PREFIX_0F3837) },
7092 { PREFIX_TABLE (PREFIX_0F3838) },
7093 { PREFIX_TABLE (PREFIX_0F3839) },
7094 { PREFIX_TABLE (PREFIX_0F383A) },
7095 { PREFIX_TABLE (PREFIX_0F383B) },
7096 { PREFIX_TABLE (PREFIX_0F383C) },
7097 { PREFIX_TABLE (PREFIX_0F383D) },
7098 { PREFIX_TABLE (PREFIX_0F383E) },
7099 { PREFIX_TABLE (PREFIX_0F383F) },
7101 { PREFIX_TABLE (PREFIX_0F3840) },
7102 { PREFIX_TABLE (PREFIX_0F3841) },
7173 { PREFIX_TABLE (PREFIX_0F3880) },
7174 { PREFIX_TABLE (PREFIX_0F3881) },
7175 { PREFIX_TABLE (PREFIX_0F3882) },
7254 { PREFIX_TABLE (PREFIX_0F38C8) },
7255 { PREFIX_TABLE (PREFIX_0F38C9) },
7256 { PREFIX_TABLE (PREFIX_0F38CA) },
7257 { PREFIX_TABLE (PREFIX_0F38CB) },
7258 { PREFIX_TABLE (PREFIX_0F38CC) },
7259 { PREFIX_TABLE (PREFIX_0F38CD) },
7275 { PREFIX_TABLE (PREFIX_0F38DB) },
7276 { PREFIX_TABLE (PREFIX_0F38DC) },
7277 { PREFIX_TABLE (PREFIX_0F38DD) },
7278 { PREFIX_TABLE (PREFIX_0F38DE) },
7279 { PREFIX_TABLE (PREFIX_0F38DF) },
7299 { PREFIX_TABLE (PREFIX_0F38F0) },
7300 { PREFIX_TABLE (PREFIX_0F38F1) },
7305 { PREFIX_TABLE (PREFIX_0F38F6) },
7317 /* THREE_BYTE_0F3A */
7329 { PREFIX_TABLE (PREFIX_0F3A08) },
7330 { PREFIX_TABLE (PREFIX_0F3A09) },
7331 { PREFIX_TABLE (PREFIX_0F3A0A) },
7332 { PREFIX_TABLE (PREFIX_0F3A0B) },
7333 { PREFIX_TABLE (PREFIX_0F3A0C) },
7334 { PREFIX_TABLE (PREFIX_0F3A0D) },
7335 { PREFIX_TABLE (PREFIX_0F3A0E) },
7336 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
7342 { PREFIX_TABLE (PREFIX_0F3A14) },
7343 { PREFIX_TABLE (PREFIX_0F3A15) },
7344 { PREFIX_TABLE (PREFIX_0F3A16) },
7345 { PREFIX_TABLE (PREFIX_0F3A17) },
7356 { PREFIX_TABLE (PREFIX_0F3A20) },
7357 { PREFIX_TABLE (PREFIX_0F3A21) },
7358 { PREFIX_TABLE (PREFIX_0F3A22) },
7392 { PREFIX_TABLE (PREFIX_0F3A40) },
7393 { PREFIX_TABLE (PREFIX_0F3A41) },
7394 { PREFIX_TABLE (PREFIX_0F3A42) },
7396 { PREFIX_TABLE (PREFIX_0F3A44) },
7428 { PREFIX_TABLE (PREFIX_0F3A60) },
7429 { PREFIX_TABLE (PREFIX_0F3A61) },
7430 { PREFIX_TABLE (PREFIX_0F3A62) },
7431 { PREFIX_TABLE (PREFIX_0F3A63) },
7549 { PREFIX_TABLE (PREFIX_0F3ACC) },
7570 { PREFIX_TABLE (PREFIX_0F3ADF) },
7609 /* THREE_BYTE_0F7A */
7685 { "phaddbw", { XM, EXq }, PREFIX_OPCODE },
7686 { "phaddbd", { XM, EXq }, PREFIX_OPCODE },
7687 { "phaddbq", { XM, EXq }, PREFIX_OPCODE },
7690 { "phaddwd", { XM, EXq }, PREFIX_OPCODE },
7691 { "phaddwq", { XM, EXq }, PREFIX_OPCODE },
7696 { "phadddq", { XM, EXq }, PREFIX_OPCODE },
7703 { "phaddubw", { XM, EXq }, PREFIX_OPCODE },
7704 { "phaddubd", { XM, EXq }, PREFIX_OPCODE },
7705 { "phaddubq", { XM, EXq }, PREFIX_OPCODE },
7708 { "phadduwd", { XM, EXq }, PREFIX_OPCODE },
7709 { "phadduwq", { XM, EXq }, PREFIX_OPCODE },
7714 { "phaddudq", { XM, EXq }, PREFIX_OPCODE },
7721 { "phsubbw", { XM, EXq }, PREFIX_OPCODE },
7722 { "phsubbd", { XM, EXq }, PREFIX_OPCODE },
7723 { "phsubbq", { XM, EXq }, PREFIX_OPCODE },
7902 static const struct dis386 xop_table[][256] = {
8055 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8056 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8057 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8065 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8066 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8073 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8074 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8075 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8083 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8084 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8088 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8089 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8092 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8110 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8122 { "vprotb", { XM, Vex_2src_1, Ib }, 0 },
8123 { "vprotw", { XM, Vex_2src_1, Ib }, 0 },
8124 { "vprotd", { XM, Vex_2src_1, Ib }, 0 },
8125 { "vprotq", { XM, Vex_2src_1, Ib }, 0 },
8135 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
8136 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
8137 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
8138 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
8171 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8172 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8173 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8174 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8198 { REG_TABLE (REG_XOP_TBM_01) },
8199 { REG_TABLE (REG_XOP_TBM_02) },
8217 { REG_TABLE (REG_XOP_LWPCB) },
8341 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8342 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8343 { "vfrczss", { XM, EXd }, 0 },
8344 { "vfrczsd", { XM, EXq }, 0 },
8359 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8360 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8361 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8362 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8363 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8364 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8365 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8366 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8368 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8369 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8370 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8371 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8414 { "vphaddbw", { XM, EXxmm }, 0 },
8415 { "vphaddbd", { XM, EXxmm }, 0 },
8416 { "vphaddbq", { XM, EXxmm }, 0 },
8419 { "vphaddwd", { XM, EXxmm }, 0 },
8420 { "vphaddwq", { XM, EXxmm }, 0 },
8425 { "vphadddq", { XM, EXxmm }, 0 },
8432 { "vphaddubw", { XM, EXxmm }, 0 },
8433 { "vphaddubd", { XM, EXxmm }, 0 },
8434 { "vphaddubq", { XM, EXxmm }, 0 },
8437 { "vphadduwd", { XM, EXxmm }, 0 },
8438 { "vphadduwq", { XM, EXxmm }, 0 },
8443 { "vphaddudq", { XM, EXxmm }, 0 },
8450 { "vphsubbw", { XM, EXxmm }, 0 },
8451 { "vphsubwd", { XM, EXxmm }, 0 },
8452 { "vphsubdq", { XM, EXxmm }, 0 },
8506 { "bextr", { Gv, Ev, Iq }, 0 },
8508 { REG_TABLE (REG_XOP_LWP) },
8778 static const struct dis386 vex_table[][256] = {
8800 { PREFIX_TABLE (PREFIX_VEX_0F10) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F11) },
8802 { PREFIX_TABLE (PREFIX_VEX_0F12) },
8803 { MOD_TABLE (MOD_VEX_0F13) },
8804 { VEX_W_TABLE (VEX_W_0F14) },
8805 { VEX_W_TABLE (VEX_W_0F15) },
8806 { PREFIX_TABLE (PREFIX_VEX_0F16) },
8807 { MOD_TABLE (MOD_VEX_0F17) },
8827 { VEX_W_TABLE (VEX_W_0F28) },
8828 { VEX_W_TABLE (VEX_W_0F29) },
8829 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8830 { MOD_TABLE (MOD_VEX_0F2B) },
8831 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8832 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8833 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8834 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8855 { PREFIX_TABLE (PREFIX_VEX_0F41) },
8856 { PREFIX_TABLE (PREFIX_VEX_0F42) },
8858 { PREFIX_TABLE (PREFIX_VEX_0F44) },
8859 { PREFIX_TABLE (PREFIX_VEX_0F45) },
8860 { PREFIX_TABLE (PREFIX_VEX_0F46) },
8861 { PREFIX_TABLE (PREFIX_VEX_0F47) },
8865 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8866 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8872 { MOD_TABLE (MOD_VEX_0F50) },
8873 { PREFIX_TABLE (PREFIX_VEX_0F51) },
8874 { PREFIX_TABLE (PREFIX_VEX_0F52) },
8875 { PREFIX_TABLE (PREFIX_VEX_0F53) },
8876 { "vandpX", { XM, Vex, EXx }, 0 },
8877 { "vandnpX", { XM, Vex, EXx }, 0 },
8878 { "vorpX", { XM, Vex, EXx }, 0 },
8879 { "vxorpX", { XM, Vex, EXx }, 0 },
8881 { PREFIX_TABLE (PREFIX_VEX_0F58) },
8882 { PREFIX_TABLE (PREFIX_VEX_0F59) },
8883 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8884 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8885 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8886 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F60) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F61) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F62) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F63) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F64) },
8895 { PREFIX_TABLE (PREFIX_VEX_0F65) },
8896 { PREFIX_TABLE (PREFIX_VEX_0F66) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F67) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F68) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F69) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8905 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F70) },
8909 { REG_TABLE (REG_VEX_0F71) },
8910 { REG_TABLE (REG_VEX_0F72) },
8911 { REG_TABLE (REG_VEX_0F73) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F74) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F75) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F76) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F77) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8923 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8924 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F90) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F91) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F92) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F93) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F98) },
8954 { PREFIX_TABLE (PREFIX_VEX_0F99) },
8977 { REG_TABLE (REG_VEX_0FAE) },
9000 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
9002 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
9003 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
9004 { "vshufpX", { XM, Vex, EXx, Ib }, 0 },
9016 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
9017 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
9018 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
9019 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
9020 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
9021 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
9022 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
9023 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
9025 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
9026 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
9027 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
9028 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
9029 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
9030 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
9031 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
9032 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
9034 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
9035 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
9036 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
9037 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
9038 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
9039 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
9040 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
9041 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
9043 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
9044 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
9045 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
9046 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
9047 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
9048 { PREFIX_TABLE (PREFIX_VEX_0FED) },
9049 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
9050 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
9052 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
9053 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
9054 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
9055 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
9056 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
9057 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
9058 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
9059 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
9061 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
9062 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
9063 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
9064 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
9065 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
9066 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
9067 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
9077 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
9078 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
9079 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
9080 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
9082 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
9083 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
9084 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
9085 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
9086 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
9087 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
9088 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
9094 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
9098 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
9101 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
9102 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
9104 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
9105 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
9106 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
9109 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
9110 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
9111 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
9112 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
9113 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
9114 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
9118 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
9119 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
9120 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
9121 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
9122 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
9123 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
9124 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
9125 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
9127 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
9128 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
9129 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
9130 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
9131 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
9132 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
9134 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
9136 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
9137 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
9138 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
9139 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
9140 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
9141 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
9142 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
9143 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
9145 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
9146 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
9150 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
9151 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
9152 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
9172 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9173 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9174 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9208 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9209 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9230 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9232 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9235 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9236 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9237 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9238 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9241 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9242 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9244 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9245 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9246 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9247 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9248 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9249 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9250 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9251 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9259 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9260 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9262 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9263 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9264 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9265 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9266 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9267 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9268 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9269 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9277 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9278 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9280 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9281 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9282 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9283 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9284 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9285 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9286 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9287 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9319 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9320 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9321 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9322 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9323 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9345 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9346 { REG_TABLE (REG_VEX_0F38F3) },
9348 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9349 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9350 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9364 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9365 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9366 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9368 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9369 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9370 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9373 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9374 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9375 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9376 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9377 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9378 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9379 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9380 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9386 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9387 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9388 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9389 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9391 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9392 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9396 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9400 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9401 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9402 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9418 { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9419 { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9420 { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9421 { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9427 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9428 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9436 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9437 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9438 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9440 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9442 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9445 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9446 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9447 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9448 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9449 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9467 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9468 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9469 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9470 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9472 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9473 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9474 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9475 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9481 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9482 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9483 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9484 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9485 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9486 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9487 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9488 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9499 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9500 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9501 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9502 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9503 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9504 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9505 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9506 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9614 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9634 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9654 #define NEED_OPCODE_TABLE
9655 #include "i386-dis-evex.h"
9656 #undef NEED_OPCODE_TABLE
9657 static const struct dis386 vex_len_table[][2] = {
9658 /* VEX_LEN_0F10_P_1 */
9660 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9661 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9664 /* VEX_LEN_0F10_P_3 */
9666 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9667 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9670 /* VEX_LEN_0F11_P_1 */
9672 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9673 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9676 /* VEX_LEN_0F11_P_3 */
9678 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9679 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9682 /* VEX_LEN_0F12_P_0_M_0 */
9684 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9687 /* VEX_LEN_0F12_P_0_M_1 */
9689 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9692 /* VEX_LEN_0F12_P_2 */
9694 { VEX_W_TABLE (VEX_W_0F12_P_2) },
9697 /* VEX_LEN_0F13_M_0 */
9699 { VEX_W_TABLE (VEX_W_0F13_M_0) },
9702 /* VEX_LEN_0F16_P_0_M_0 */
9704 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9707 /* VEX_LEN_0F16_P_0_M_1 */
9709 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9712 /* VEX_LEN_0F16_P_2 */
9714 { VEX_W_TABLE (VEX_W_0F16_P_2) },
9717 /* VEX_LEN_0F17_M_0 */
9719 { VEX_W_TABLE (VEX_W_0F17_M_0) },
9722 /* VEX_LEN_0F2A_P_1 */
9724 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9725 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9728 /* VEX_LEN_0F2A_P_3 */
9730 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9731 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9734 /* VEX_LEN_0F2C_P_1 */
9736 { "vcvttss2siY", { Gv, EXdScalar }, 0 },
9737 { "vcvttss2siY", { Gv, EXdScalar }, 0 },
9740 /* VEX_LEN_0F2C_P_3 */
9742 { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
9743 { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
9746 /* VEX_LEN_0F2D_P_1 */
9748 { "vcvtss2siY", { Gv, EXdScalar }, 0 },
9749 { "vcvtss2siY", { Gv, EXdScalar }, 0 },
9752 /* VEX_LEN_0F2D_P_3 */
9754 { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
9755 { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
9758 /* VEX_LEN_0F2E_P_0 */
9760 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9761 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9764 /* VEX_LEN_0F2E_P_2 */
9766 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9767 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9770 /* VEX_LEN_0F2F_P_0 */
9772 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9773 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9776 /* VEX_LEN_0F2F_P_2 */
9778 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9779 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9782 /* VEX_LEN_0F41_P_0 */
9785 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9787 /* VEX_LEN_0F41_P_2 */
9790 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9792 /* VEX_LEN_0F42_P_0 */
9795 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9797 /* VEX_LEN_0F42_P_2 */
9800 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9802 /* VEX_LEN_0F44_P_0 */
9804 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9806 /* VEX_LEN_0F44_P_2 */
9808 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9810 /* VEX_LEN_0F45_P_0 */
9813 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9815 /* VEX_LEN_0F45_P_2 */
9818 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9820 /* VEX_LEN_0F46_P_0 */
9823 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9825 /* VEX_LEN_0F46_P_2 */
9828 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9830 /* VEX_LEN_0F47_P_0 */
9833 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9835 /* VEX_LEN_0F47_P_2 */
9838 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9840 /* VEX_LEN_0F4A_P_0 */
9843 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9845 /* VEX_LEN_0F4A_P_2 */
9848 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9850 /* VEX_LEN_0F4B_P_0 */
9853 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9855 /* VEX_LEN_0F4B_P_2 */
9858 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9861 /* VEX_LEN_0F51_P_1 */
9863 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9864 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9867 /* VEX_LEN_0F51_P_3 */
9869 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9870 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9873 /* VEX_LEN_0F52_P_1 */
9875 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9876 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9879 /* VEX_LEN_0F53_P_1 */
9881 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9882 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9885 /* VEX_LEN_0F58_P_1 */
9887 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9888 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9891 /* VEX_LEN_0F58_P_3 */
9893 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9894 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9897 /* VEX_LEN_0F59_P_1 */
9899 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9900 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9903 /* VEX_LEN_0F59_P_3 */
9905 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9906 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9909 /* VEX_LEN_0F5A_P_1 */
9911 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9912 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9915 /* VEX_LEN_0F5A_P_3 */
9917 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9918 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9921 /* VEX_LEN_0F5C_P_1 */
9923 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9924 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9927 /* VEX_LEN_0F5C_P_3 */
9929 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9930 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9933 /* VEX_LEN_0F5D_P_1 */
9935 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9936 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9939 /* VEX_LEN_0F5D_P_3 */
9941 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9942 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9945 /* VEX_LEN_0F5E_P_1 */
9947 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9948 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9951 /* VEX_LEN_0F5E_P_3 */
9953 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9954 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9957 /* VEX_LEN_0F5F_P_1 */
9959 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9960 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9963 /* VEX_LEN_0F5F_P_3 */
9965 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9966 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9969 /* VEX_LEN_0F6E_P_2 */
9971 { "vmovK", { XMScalar, Edq }, 0 },
9972 { "vmovK", { XMScalar, Edq }, 0 },
9975 /* VEX_LEN_0F7E_P_1 */
9977 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9978 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9981 /* VEX_LEN_0F7E_P_2 */
9983 { "vmovK", { Edq, XMScalar }, 0 },
9984 { "vmovK", { Edq, XMScalar }, 0 },
9987 /* VEX_LEN_0F90_P_0 */
9989 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9992 /* VEX_LEN_0F90_P_2 */
9994 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9997 /* VEX_LEN_0F91_P_0 */
9999 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
10002 /* VEX_LEN_0F91_P_2 */
10004 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
10007 /* VEX_LEN_0F92_P_0 */
10009 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
10012 /* VEX_LEN_0F92_P_2 */
10014 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
10017 /* VEX_LEN_0F92_P_3 */
10019 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
10022 /* VEX_LEN_0F93_P_0 */
10024 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
10027 /* VEX_LEN_0F93_P_2 */
10029 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
10032 /* VEX_LEN_0F93_P_3 */
10034 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
10037 /* VEX_LEN_0F98_P_0 */
10039 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
10042 /* VEX_LEN_0F98_P_2 */
10044 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
10047 /* VEX_LEN_0F99_P_0 */
10049 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
10052 /* VEX_LEN_0F99_P_2 */
10054 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
10057 /* VEX_LEN_0FAE_R_2_M_0 */
10059 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
10062 /* VEX_LEN_0FAE_R_3_M_0 */
10064 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
10067 /* VEX_LEN_0FC2_P_1 */
10069 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
10070 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
10073 /* VEX_LEN_0FC2_P_3 */
10075 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
10076 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
10079 /* VEX_LEN_0FC4_P_2 */
10081 { VEX_W_TABLE (VEX_W_0FC4_P_2) },
10084 /* VEX_LEN_0FC5_P_2 */
10086 { VEX_W_TABLE (VEX_W_0FC5_P_2) },
10089 /* VEX_LEN_0FD6_P_2 */
10091 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
10092 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
10095 /* VEX_LEN_0FF7_P_2 */
10097 { VEX_W_TABLE (VEX_W_0FF7_P_2) },
10100 /* VEX_LEN_0F3816_P_2 */
10103 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
10106 /* VEX_LEN_0F3819_P_2 */
10109 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
10112 /* VEX_LEN_0F381A_P_2_M_0 */
10115 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
10118 /* VEX_LEN_0F3836_P_2 */
10121 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
10124 /* VEX_LEN_0F3841_P_2 */
10126 { VEX_W_TABLE (VEX_W_0F3841_P_2) },
10129 /* VEX_LEN_0F385A_P_2_M_0 */
10132 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
10135 /* VEX_LEN_0F38DB_P_2 */
10137 { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
10140 /* VEX_LEN_0F38DC_P_2 */
10142 { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
10145 /* VEX_LEN_0F38DD_P_2 */
10147 { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
10150 /* VEX_LEN_0F38DE_P_2 */
10152 { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
10155 /* VEX_LEN_0F38DF_P_2 */
10157 { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
10160 /* VEX_LEN_0F38F2_P_0 */
10162 { "andnS", { Gdq, VexGdq, Edq }, 0 },
10165 /* VEX_LEN_0F38F3_R_1_P_0 */
10167 { "blsrS", { VexGdq, Edq }, 0 },
10170 /* VEX_LEN_0F38F3_R_2_P_0 */
10172 { "blsmskS", { VexGdq, Edq }, 0 },
10175 /* VEX_LEN_0F38F3_R_3_P_0 */
10177 { "blsiS", { VexGdq, Edq }, 0 },
10180 /* VEX_LEN_0F38F5_P_0 */
10182 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
10185 /* VEX_LEN_0F38F5_P_1 */
10187 { "pextS", { Gdq, VexGdq, Edq }, 0 },
10190 /* VEX_LEN_0F38F5_P_3 */
10192 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
10195 /* VEX_LEN_0F38F6_P_3 */
10197 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
10200 /* VEX_LEN_0F38F7_P_0 */
10202 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
10205 /* VEX_LEN_0F38F7_P_1 */
10207 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
10210 /* VEX_LEN_0F38F7_P_2 */
10212 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
10215 /* VEX_LEN_0F38F7_P_3 */
10217 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
10220 /* VEX_LEN_0F3A00_P_2 */
10223 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10226 /* VEX_LEN_0F3A01_P_2 */
10229 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10232 /* VEX_LEN_0F3A06_P_2 */
10235 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10238 /* VEX_LEN_0F3A0A_P_2 */
10240 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10241 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10244 /* VEX_LEN_0F3A0B_P_2 */
10246 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10247 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10250 /* VEX_LEN_0F3A14_P_2 */
10252 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10255 /* VEX_LEN_0F3A15_P_2 */
10257 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10260 /* VEX_LEN_0F3A16_P_2 */
10262 { "vpextrK", { Edq, XM, Ib }, 0 },
10265 /* VEX_LEN_0F3A17_P_2 */
10267 { "vextractps", { Edqd, XM, Ib }, 0 },
10270 /* VEX_LEN_0F3A18_P_2 */
10273 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10276 /* VEX_LEN_0F3A19_P_2 */
10279 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10282 /* VEX_LEN_0F3A20_P_2 */
10284 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10287 /* VEX_LEN_0F3A21_P_2 */
10289 { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10292 /* VEX_LEN_0F3A22_P_2 */
10294 { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 },
10297 /* VEX_LEN_0F3A30_P_2 */
10299 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10302 /* VEX_LEN_0F3A31_P_2 */
10304 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10307 /* VEX_LEN_0F3A32_P_2 */
10309 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10312 /* VEX_LEN_0F3A33_P_2 */
10314 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10317 /* VEX_LEN_0F3A38_P_2 */
10320 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10323 /* VEX_LEN_0F3A39_P_2 */
10326 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10329 /* VEX_LEN_0F3A41_P_2 */
10331 { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10334 /* VEX_LEN_0F3A44_P_2 */
10336 { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10339 /* VEX_LEN_0F3A46_P_2 */
10342 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10345 /* VEX_LEN_0F3A60_P_2 */
10347 { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10350 /* VEX_LEN_0F3A61_P_2 */
10352 { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10355 /* VEX_LEN_0F3A62_P_2 */
10357 { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10360 /* VEX_LEN_0F3A63_P_2 */
10362 { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10365 /* VEX_LEN_0F3A6A_P_2 */
10367 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10370 /* VEX_LEN_0F3A6B_P_2 */
10372 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10375 /* VEX_LEN_0F3A6E_P_2 */
10377 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10380 /* VEX_LEN_0F3A6F_P_2 */
10382 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10385 /* VEX_LEN_0F3A7A_P_2 */
10387 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10390 /* VEX_LEN_0F3A7B_P_2 */
10392 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10395 /* VEX_LEN_0F3A7E_P_2 */
10397 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10400 /* VEX_LEN_0F3A7F_P_2 */
10402 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10405 /* VEX_LEN_0F3ADF_P_2 */
10407 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10410 /* VEX_LEN_0F3AF0_P_3 */
10412 { "rorxS", { Gdq, Edq, Ib }, 0 },
10415 /* VEX_LEN_0FXOP_08_CC */
10417 { "vpcomb", { XM, Vex128, EXx, Ib }, 0 },
10420 /* VEX_LEN_0FXOP_08_CD */
10422 { "vpcomw", { XM, Vex128, EXx, Ib }, 0 },
10425 /* VEX_LEN_0FXOP_08_CE */
10427 { "vpcomd", { XM, Vex128, EXx, Ib }, 0 },
10430 /* VEX_LEN_0FXOP_08_CF */
10432 { "vpcomq", { XM, Vex128, EXx, Ib }, 0 },
10435 /* VEX_LEN_0FXOP_08_EC */
10437 { "vpcomub", { XM, Vex128, EXx, Ib }, 0 },
10440 /* VEX_LEN_0FXOP_08_ED */
10442 { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 },
10445 /* VEX_LEN_0FXOP_08_EE */
10447 { "vpcomud", { XM, Vex128, EXx, Ib }, 0 },
10450 /* VEX_LEN_0FXOP_08_EF */
10452 { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 },
10455 /* VEX_LEN_0FXOP_09_80 */
10457 { "vfrczps", { XM, EXxmm }, 0 },
10458 { "vfrczps", { XM, EXymmq }, 0 },
10461 /* VEX_LEN_0FXOP_09_81 */
10463 { "vfrczpd", { XM, EXxmm }, 0 },
10464 { "vfrczpd", { XM, EXymmq }, 0 },
10468 static const struct dis386 vex_w_table[][2] = {
10470 /* VEX_W_0F10_P_0 */
10471 { "vmovups", { XM, EXx }, 0 },
10474 /* VEX_W_0F10_P_1 */
10475 { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
10478 /* VEX_W_0F10_P_2 */
10479 { "vmovupd", { XM, EXx }, 0 },
10482 /* VEX_W_0F10_P_3 */
10483 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
10486 /* VEX_W_0F11_P_0 */
10487 { "vmovups", { EXxS, XM }, 0 },
10490 /* VEX_W_0F11_P_1 */
10491 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10494 /* VEX_W_0F11_P_2 */
10495 { "vmovupd", { EXxS, XM }, 0 },
10498 /* VEX_W_0F11_P_3 */
10499 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10502 /* VEX_W_0F12_P_0_M_0 */
10503 { "vmovlps", { XM, Vex128, EXq }, 0 },
10506 /* VEX_W_0F12_P_0_M_1 */
10507 { "vmovhlps", { XM, Vex128, EXq }, 0 },
10510 /* VEX_W_0F12_P_1 */
10511 { "vmovsldup", { XM, EXx }, 0 },
10514 /* VEX_W_0F12_P_2 */
10515 { "vmovlpd", { XM, Vex128, EXq }, 0 },
10518 /* VEX_W_0F12_P_3 */
10519 { "vmovddup", { XM, EXymmq }, 0 },
10522 /* VEX_W_0F13_M_0 */
10523 { "vmovlpX", { EXq, XM }, 0 },
10527 { "vunpcklpX", { XM, Vex, EXx }, 0 },
10531 { "vunpckhpX", { XM, Vex, EXx }, 0 },
10534 /* VEX_W_0F16_P_0_M_0 */
10535 { "vmovhps", { XM, Vex128, EXq }, 0 },
10538 /* VEX_W_0F16_P_0_M_1 */
10539 { "vmovlhps", { XM, Vex128, EXq }, 0 },
10542 /* VEX_W_0F16_P_1 */
10543 { "vmovshdup", { XM, EXx }, 0 },
10546 /* VEX_W_0F16_P_2 */
10547 { "vmovhpd", { XM, Vex128, EXq }, 0 },
10550 /* VEX_W_0F17_M_0 */
10551 { "vmovhpX", { EXq, XM }, 0 },
10555 { "vmovapX", { XM, EXx }, 0 },
10559 { "vmovapX", { EXxS, XM }, 0 },
10562 /* VEX_W_0F2B_M_0 */
10563 { "vmovntpX", { Mx, XM }, 0 },
10566 /* VEX_W_0F2E_P_0 */
10567 { "vucomiss", { XMScalar, EXdScalar }, 0 },
10570 /* VEX_W_0F2E_P_2 */
10571 { "vucomisd", { XMScalar, EXqScalar }, 0 },
10574 /* VEX_W_0F2F_P_0 */
10575 { "vcomiss", { XMScalar, EXdScalar }, 0 },
10578 /* VEX_W_0F2F_P_2 */
10579 { "vcomisd", { XMScalar, EXqScalar }, 0 },
10582 /* VEX_W_0F41_P_0_LEN_1 */
10583 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10584 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10587 /* VEX_W_0F41_P_2_LEN_1 */
10588 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10589 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10592 /* VEX_W_0F42_P_0_LEN_1 */
10593 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10594 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10597 /* VEX_W_0F42_P_2_LEN_1 */
10598 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10599 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10602 /* VEX_W_0F44_P_0_LEN_0 */
10603 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10604 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10607 /* VEX_W_0F44_P_2_LEN_0 */
10608 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10609 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10612 /* VEX_W_0F45_P_0_LEN_1 */
10613 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10614 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10617 /* VEX_W_0F45_P_2_LEN_1 */
10618 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10619 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10622 /* VEX_W_0F46_P_0_LEN_1 */
10623 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10624 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10627 /* VEX_W_0F46_P_2_LEN_1 */
10628 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10629 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10632 /* VEX_W_0F47_P_0_LEN_1 */
10633 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10634 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10637 /* VEX_W_0F47_P_2_LEN_1 */
10638 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10639 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10642 /* VEX_W_0F4A_P_0_LEN_1 */
10643 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10644 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10647 /* VEX_W_0F4A_P_2_LEN_1 */
10648 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10649 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10652 /* VEX_W_0F4B_P_0_LEN_1 */
10653 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10654 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10657 /* VEX_W_0F4B_P_2_LEN_1 */
10658 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10661 /* VEX_W_0F50_M_0 */
10662 { "vmovmskpX", { Gdq, XS }, 0 },
10665 /* VEX_W_0F51_P_0 */
10666 { "vsqrtps", { XM, EXx }, 0 },
10669 /* VEX_W_0F51_P_1 */
10670 { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10673 /* VEX_W_0F51_P_2 */
10674 { "vsqrtpd", { XM, EXx }, 0 },
10677 /* VEX_W_0F51_P_3 */
10678 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10681 /* VEX_W_0F52_P_0 */
10682 { "vrsqrtps", { XM, EXx }, 0 },
10685 /* VEX_W_0F52_P_1 */
10686 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10689 /* VEX_W_0F53_P_0 */
10690 { "vrcpps", { XM, EXx }, 0 },
10693 /* VEX_W_0F53_P_1 */
10694 { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
10697 /* VEX_W_0F58_P_0 */
10698 { "vaddps", { XM, Vex, EXx }, 0 },
10701 /* VEX_W_0F58_P_1 */
10702 { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
10705 /* VEX_W_0F58_P_2 */
10706 { "vaddpd", { XM, Vex, EXx }, 0 },
10709 /* VEX_W_0F58_P_3 */
10710 { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10713 /* VEX_W_0F59_P_0 */
10714 { "vmulps", { XM, Vex, EXx }, 0 },
10717 /* VEX_W_0F59_P_1 */
10718 { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
10721 /* VEX_W_0F59_P_2 */
10722 { "vmulpd", { XM, Vex, EXx }, 0 },
10725 /* VEX_W_0F59_P_3 */
10726 { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10729 /* VEX_W_0F5A_P_0 */
10730 { "vcvtps2pd", { XM, EXxmmq }, 0 },
10733 /* VEX_W_0F5A_P_1 */
10734 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
10737 /* VEX_W_0F5A_P_3 */
10738 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
10741 /* VEX_W_0F5B_P_0 */
10742 { "vcvtdq2ps", { XM, EXx }, 0 },
10745 /* VEX_W_0F5B_P_1 */
10746 { "vcvttps2dq", { XM, EXx }, 0 },
10749 /* VEX_W_0F5B_P_2 */
10750 { "vcvtps2dq", { XM, EXx }, 0 },
10753 /* VEX_W_0F5C_P_0 */
10754 { "vsubps", { XM, Vex, EXx }, 0 },
10757 /* VEX_W_0F5C_P_1 */
10758 { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
10761 /* VEX_W_0F5C_P_2 */
10762 { "vsubpd", { XM, Vex, EXx }, 0 },
10765 /* VEX_W_0F5C_P_3 */
10766 { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10769 /* VEX_W_0F5D_P_0 */
10770 { "vminps", { XM, Vex, EXx }, 0 },
10773 /* VEX_W_0F5D_P_1 */
10774 { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
10777 /* VEX_W_0F5D_P_2 */
10778 { "vminpd", { XM, Vex, EXx }, 0 },
10781 /* VEX_W_0F5D_P_3 */
10782 { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10785 /* VEX_W_0F5E_P_0 */
10786 { "vdivps", { XM, Vex, EXx }, 0 },
10789 /* VEX_W_0F5E_P_1 */
10790 { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
10793 /* VEX_W_0F5E_P_2 */
10794 { "vdivpd", { XM, Vex, EXx }, 0 },
10797 /* VEX_W_0F5E_P_3 */
10798 { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10801 /* VEX_W_0F5F_P_0 */
10802 { "vmaxps", { XM, Vex, EXx }, 0 },
10805 /* VEX_W_0F5F_P_1 */
10806 { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
10809 /* VEX_W_0F5F_P_2 */
10810 { "vmaxpd", { XM, Vex, EXx }, 0 },
10813 /* VEX_W_0F5F_P_3 */
10814 { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10817 /* VEX_W_0F60_P_2 */
10818 { "vpunpcklbw", { XM, Vex, EXx }, 0 },
10821 /* VEX_W_0F61_P_2 */
10822 { "vpunpcklwd", { XM, Vex, EXx }, 0 },
10825 /* VEX_W_0F62_P_2 */
10826 { "vpunpckldq", { XM, Vex, EXx }, 0 },
10829 /* VEX_W_0F63_P_2 */
10830 { "vpacksswb", { XM, Vex, EXx }, 0 },
10833 /* VEX_W_0F64_P_2 */
10834 { "vpcmpgtb", { XM, Vex, EXx }, 0 },
10837 /* VEX_W_0F65_P_2 */
10838 { "vpcmpgtw", { XM, Vex, EXx }, 0 },
10841 /* VEX_W_0F66_P_2 */
10842 { "vpcmpgtd", { XM, Vex, EXx }, 0 },
10845 /* VEX_W_0F67_P_2 */
10846 { "vpackuswb", { XM, Vex, EXx }, 0 },
10849 /* VEX_W_0F68_P_2 */
10850 { "vpunpckhbw", { XM, Vex, EXx }, 0 },
10853 /* VEX_W_0F69_P_2 */
10854 { "vpunpckhwd", { XM, Vex, EXx }, 0 },
10857 /* VEX_W_0F6A_P_2 */
10858 { "vpunpckhdq", { XM, Vex, EXx }, 0 },
10861 /* VEX_W_0F6B_P_2 */
10862 { "vpackssdw", { XM, Vex, EXx }, 0 },
10865 /* VEX_W_0F6C_P_2 */
10866 { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
10869 /* VEX_W_0F6D_P_2 */
10870 { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
10873 /* VEX_W_0F6F_P_1 */
10874 { "vmovdqu", { XM, EXx }, 0 },
10877 /* VEX_W_0F6F_P_2 */
10878 { "vmovdqa", { XM, EXx }, 0 },
10881 /* VEX_W_0F70_P_1 */
10882 { "vpshufhw", { XM, EXx, Ib }, 0 },
10885 /* VEX_W_0F70_P_2 */
10886 { "vpshufd", { XM, EXx, Ib }, 0 },
10889 /* VEX_W_0F70_P_3 */
10890 { "vpshuflw", { XM, EXx, Ib }, 0 },
10893 /* VEX_W_0F71_R_2_P_2 */
10894 { "vpsrlw", { Vex, XS, Ib }, 0 },
10897 /* VEX_W_0F71_R_4_P_2 */
10898 { "vpsraw", { Vex, XS, Ib }, 0 },
10901 /* VEX_W_0F71_R_6_P_2 */
10902 { "vpsllw", { Vex, XS, Ib }, 0 },
10905 /* VEX_W_0F72_R_2_P_2 */
10906 { "vpsrld", { Vex, XS, Ib }, 0 },
10909 /* VEX_W_0F72_R_4_P_2 */
10910 { "vpsrad", { Vex, XS, Ib }, 0 },
10913 /* VEX_W_0F72_R_6_P_2 */
10914 { "vpslld", { Vex, XS, Ib }, 0 },
10917 /* VEX_W_0F73_R_2_P_2 */
10918 { "vpsrlq", { Vex, XS, Ib }, 0 },
10921 /* VEX_W_0F73_R_3_P_2 */
10922 { "vpsrldq", { Vex, XS, Ib }, 0 },
10925 /* VEX_W_0F73_R_6_P_2 */
10926 { "vpsllq", { Vex, XS, Ib }, 0 },
10929 /* VEX_W_0F73_R_7_P_2 */
10930 { "vpslldq", { Vex, XS, Ib }, 0 },
10933 /* VEX_W_0F74_P_2 */
10934 { "vpcmpeqb", { XM, Vex, EXx }, 0 },
10937 /* VEX_W_0F75_P_2 */
10938 { "vpcmpeqw", { XM, Vex, EXx }, 0 },
10941 /* VEX_W_0F76_P_2 */
10942 { "vpcmpeqd", { XM, Vex, EXx }, 0 },
10945 /* VEX_W_0F77_P_0 */
10946 { "", { VZERO }, 0 },
10949 /* VEX_W_0F7C_P_2 */
10950 { "vhaddpd", { XM, Vex, EXx }, 0 },
10953 /* VEX_W_0F7C_P_3 */
10954 { "vhaddps", { XM, Vex, EXx }, 0 },
10957 /* VEX_W_0F7D_P_2 */
10958 { "vhsubpd", { XM, Vex, EXx }, 0 },
10961 /* VEX_W_0F7D_P_3 */
10962 { "vhsubps", { XM, Vex, EXx }, 0 },
10965 /* VEX_W_0F7E_P_1 */
10966 { "vmovq", { XMScalar, EXqScalar }, 0 },
10969 /* VEX_W_0F7F_P_1 */
10970 { "vmovdqu", { EXxS, XM }, 0 },
10973 /* VEX_W_0F7F_P_2 */
10974 { "vmovdqa", { EXxS, XM }, 0 },
10977 /* VEX_W_0F90_P_0_LEN_0 */
10978 { "kmovw", { MaskG, MaskE }, 0 },
10979 { "kmovq", { MaskG, MaskE }, 0 },
10982 /* VEX_W_0F90_P_2_LEN_0 */
10983 { "kmovb", { MaskG, MaskBDE }, 0 },
10984 { "kmovd", { MaskG, MaskBDE }, 0 },
10987 /* VEX_W_0F91_P_0_LEN_0 */
10988 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10989 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10992 /* VEX_W_0F91_P_2_LEN_0 */
10993 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10994 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10997 /* VEX_W_0F92_P_0_LEN_0 */
10998 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
11001 /* VEX_W_0F92_P_2_LEN_0 */
11002 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
11005 /* VEX_W_0F92_P_3_LEN_0 */
11006 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
11007 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
11010 /* VEX_W_0F93_P_0_LEN_0 */
11011 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
11014 /* VEX_W_0F93_P_2_LEN_0 */
11015 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
11018 /* VEX_W_0F93_P_3_LEN_0 */
11019 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
11020 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
11023 /* VEX_W_0F98_P_0_LEN_0 */
11024 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
11025 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
11028 /* VEX_W_0F98_P_2_LEN_0 */
11029 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
11030 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
11033 /* VEX_W_0F99_P_0_LEN_0 */
11034 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
11035 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
11038 /* VEX_W_0F99_P_2_LEN_0 */
11039 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
11040 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
11043 /* VEX_W_0FAE_R_2_M_0 */
11044 { "vldmxcsr", { Md }, 0 },
11047 /* VEX_W_0FAE_R_3_M_0 */
11048 { "vstmxcsr", { Md }, 0 },
11051 /* VEX_W_0FC2_P_0 */
11052 { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
11055 /* VEX_W_0FC2_P_1 */
11056 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
11059 /* VEX_W_0FC2_P_2 */
11060 { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
11063 /* VEX_W_0FC2_P_3 */
11064 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
11067 /* VEX_W_0FC4_P_2 */
11068 { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
11071 /* VEX_W_0FC5_P_2 */
11072 { "vpextrw", { Gdq, XS, Ib }, 0 },
11075 /* VEX_W_0FD0_P_2 */
11076 { "vaddsubpd", { XM, Vex, EXx }, 0 },
11079 /* VEX_W_0FD0_P_3 */
11080 { "vaddsubps", { XM, Vex, EXx }, 0 },
11083 /* VEX_W_0FD1_P_2 */
11084 { "vpsrlw", { XM, Vex, EXxmm }, 0 },
11087 /* VEX_W_0FD2_P_2 */
11088 { "vpsrld", { XM, Vex, EXxmm }, 0 },
11091 /* VEX_W_0FD3_P_2 */
11092 { "vpsrlq", { XM, Vex, EXxmm }, 0 },
11095 /* VEX_W_0FD4_P_2 */
11096 { "vpaddq", { XM, Vex, EXx }, 0 },
11099 /* VEX_W_0FD5_P_2 */
11100 { "vpmullw", { XM, Vex, EXx }, 0 },
11103 /* VEX_W_0FD6_P_2 */
11104 { "vmovq", { EXqScalarS, XMScalar }, 0 },
11107 /* VEX_W_0FD7_P_2_M_1 */
11108 { "vpmovmskb", { Gdq, XS }, 0 },
11111 /* VEX_W_0FD8_P_2 */
11112 { "vpsubusb", { XM, Vex, EXx }, 0 },
11115 /* VEX_W_0FD9_P_2 */
11116 { "vpsubusw", { XM, Vex, EXx }, 0 },
11119 /* VEX_W_0FDA_P_2 */
11120 { "vpminub", { XM, Vex, EXx }, 0 },
11123 /* VEX_W_0FDB_P_2 */
11124 { "vpand", { XM, Vex, EXx }, 0 },
11127 /* VEX_W_0FDC_P_2 */
11128 { "vpaddusb", { XM, Vex, EXx }, 0 },
11131 /* VEX_W_0FDD_P_2 */
11132 { "vpaddusw", { XM, Vex, EXx }, 0 },
11135 /* VEX_W_0FDE_P_2 */
11136 { "vpmaxub", { XM, Vex, EXx }, 0 },
11139 /* VEX_W_0FDF_P_2 */
11140 { "vpandn", { XM, Vex, EXx }, 0 },
11143 /* VEX_W_0FE0_P_2 */
11144 { "vpavgb", { XM, Vex, EXx }, 0 },
11147 /* VEX_W_0FE1_P_2 */
11148 { "vpsraw", { XM, Vex, EXxmm }, 0 },
11151 /* VEX_W_0FE2_P_2 */
11152 { "vpsrad", { XM, Vex, EXxmm }, 0 },
11155 /* VEX_W_0FE3_P_2 */
11156 { "vpavgw", { XM, Vex, EXx }, 0 },
11159 /* VEX_W_0FE4_P_2 */
11160 { "vpmulhuw", { XM, Vex, EXx }, 0 },
11163 /* VEX_W_0FE5_P_2 */
11164 { "vpmulhw", { XM, Vex, EXx }, 0 },
11167 /* VEX_W_0FE6_P_1 */
11168 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
11171 /* VEX_W_0FE6_P_2 */
11172 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
11175 /* VEX_W_0FE6_P_3 */
11176 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
11179 /* VEX_W_0FE7_P_2_M_0 */
11180 { "vmovntdq", { Mx, XM }, 0 },
11183 /* VEX_W_0FE8_P_2 */
11184 { "vpsubsb", { XM, Vex, EXx }, 0 },
11187 /* VEX_W_0FE9_P_2 */
11188 { "vpsubsw", { XM, Vex, EXx }, 0 },
11191 /* VEX_W_0FEA_P_2 */
11192 { "vpminsw", { XM, Vex, EXx }, 0 },
11195 /* VEX_W_0FEB_P_2 */
11196 { "vpor", { XM, Vex, EXx }, 0 },
11199 /* VEX_W_0FEC_P_2 */
11200 { "vpaddsb", { XM, Vex, EXx }, 0 },
11203 /* VEX_W_0FED_P_2 */
11204 { "vpaddsw", { XM, Vex, EXx }, 0 },
11207 /* VEX_W_0FEE_P_2 */
11208 { "vpmaxsw", { XM, Vex, EXx }, 0 },
11211 /* VEX_W_0FEF_P_2 */
11212 { "vpxor", { XM, Vex, EXx }, 0 },
11215 /* VEX_W_0FF0_P_3_M_0 */
11216 { "vlddqu", { XM, M }, 0 },
11219 /* VEX_W_0FF1_P_2 */
11220 { "vpsllw", { XM, Vex, EXxmm }, 0 },
11223 /* VEX_W_0FF2_P_2 */
11224 { "vpslld", { XM, Vex, EXxmm }, 0 },
11227 /* VEX_W_0FF3_P_2 */
11228 { "vpsllq", { XM, Vex, EXxmm }, 0 },
11231 /* VEX_W_0FF4_P_2 */
11232 { "vpmuludq", { XM, Vex, EXx }, 0 },
11235 /* VEX_W_0FF5_P_2 */
11236 { "vpmaddwd", { XM, Vex, EXx }, 0 },
11239 /* VEX_W_0FF6_P_2 */
11240 { "vpsadbw", { XM, Vex, EXx }, 0 },
11243 /* VEX_W_0FF7_P_2 */
11244 { "vmaskmovdqu", { XM, XS }, 0 },
11247 /* VEX_W_0FF8_P_2 */
11248 { "vpsubb", { XM, Vex, EXx }, 0 },
11251 /* VEX_W_0FF9_P_2 */
11252 { "vpsubw", { XM, Vex, EXx }, 0 },
11255 /* VEX_W_0FFA_P_2 */
11256 { "vpsubd", { XM, Vex, EXx }, 0 },
11259 /* VEX_W_0FFB_P_2 */
11260 { "vpsubq", { XM, Vex, EXx }, 0 },
11263 /* VEX_W_0FFC_P_2 */
11264 { "vpaddb", { XM, Vex, EXx }, 0 },
11267 /* VEX_W_0FFD_P_2 */
11268 { "vpaddw", { XM, Vex, EXx }, 0 },
11271 /* VEX_W_0FFE_P_2 */
11272 { "vpaddd", { XM, Vex, EXx }, 0 },
11275 /* VEX_W_0F3800_P_2 */
11276 { "vpshufb", { XM, Vex, EXx }, 0 },
11279 /* VEX_W_0F3801_P_2 */
11280 { "vphaddw", { XM, Vex, EXx }, 0 },
11283 /* VEX_W_0F3802_P_2 */
11284 { "vphaddd", { XM, Vex, EXx }, 0 },
11287 /* VEX_W_0F3803_P_2 */
11288 { "vphaddsw", { XM, Vex, EXx }, 0 },
11291 /* VEX_W_0F3804_P_2 */
11292 { "vpmaddubsw", { XM, Vex, EXx }, 0 },
11295 /* VEX_W_0F3805_P_2 */
11296 { "vphsubw", { XM, Vex, EXx }, 0 },
11299 /* VEX_W_0F3806_P_2 */
11300 { "vphsubd", { XM, Vex, EXx }, 0 },
11303 /* VEX_W_0F3807_P_2 */
11304 { "vphsubsw", { XM, Vex, EXx }, 0 },
11307 /* VEX_W_0F3808_P_2 */
11308 { "vpsignb", { XM, Vex, EXx }, 0 },
11311 /* VEX_W_0F3809_P_2 */
11312 { "vpsignw", { XM, Vex, EXx }, 0 },
11315 /* VEX_W_0F380A_P_2 */
11316 { "vpsignd", { XM, Vex, EXx }, 0 },
11319 /* VEX_W_0F380B_P_2 */
11320 { "vpmulhrsw", { XM, Vex, EXx }, 0 },
11323 /* VEX_W_0F380C_P_2 */
11324 { "vpermilps", { XM, Vex, EXx }, 0 },
11327 /* VEX_W_0F380D_P_2 */
11328 { "vpermilpd", { XM, Vex, EXx }, 0 },
11331 /* VEX_W_0F380E_P_2 */
11332 { "vtestps", { XM, EXx }, 0 },
11335 /* VEX_W_0F380F_P_2 */
11336 { "vtestpd", { XM, EXx }, 0 },
11339 /* VEX_W_0F3816_P_2 */
11340 { "vpermps", { XM, Vex, EXx }, 0 },
11343 /* VEX_W_0F3817_P_2 */
11344 { "vptest", { XM, EXx }, 0 },
11347 /* VEX_W_0F3818_P_2 */
11348 { "vbroadcastss", { XM, EXxmm_md }, 0 },
11351 /* VEX_W_0F3819_P_2 */
11352 { "vbroadcastsd", { XM, EXxmm_mq }, 0 },
11355 /* VEX_W_0F381A_P_2_M_0 */
11356 { "vbroadcastf128", { XM, Mxmm }, 0 },
11359 /* VEX_W_0F381C_P_2 */
11360 { "vpabsb", { XM, EXx }, 0 },
11363 /* VEX_W_0F381D_P_2 */
11364 { "vpabsw", { XM, EXx }, 0 },
11367 /* VEX_W_0F381E_P_2 */
11368 { "vpabsd", { XM, EXx }, 0 },
11371 /* VEX_W_0F3820_P_2 */
11372 { "vpmovsxbw", { XM, EXxmmq }, 0 },
11375 /* VEX_W_0F3821_P_2 */
11376 { "vpmovsxbd", { XM, EXxmmqd }, 0 },
11379 /* VEX_W_0F3822_P_2 */
11380 { "vpmovsxbq", { XM, EXxmmdw }, 0 },
11383 /* VEX_W_0F3823_P_2 */
11384 { "vpmovsxwd", { XM, EXxmmq }, 0 },
11387 /* VEX_W_0F3824_P_2 */
11388 { "vpmovsxwq", { XM, EXxmmqd }, 0 },
11391 /* VEX_W_0F3825_P_2 */
11392 { "vpmovsxdq", { XM, EXxmmq }, 0 },
11395 /* VEX_W_0F3828_P_2 */
11396 { "vpmuldq", { XM, Vex, EXx }, 0 },
11399 /* VEX_W_0F3829_P_2 */
11400 { "vpcmpeqq", { XM, Vex, EXx }, 0 },
11403 /* VEX_W_0F382A_P_2_M_0 */
11404 { "vmovntdqa", { XM, Mx }, 0 },
11407 /* VEX_W_0F382B_P_2 */
11408 { "vpackusdw", { XM, Vex, EXx }, 0 },
11411 /* VEX_W_0F382C_P_2_M_0 */
11412 { "vmaskmovps", { XM, Vex, Mx }, 0 },
11415 /* VEX_W_0F382D_P_2_M_0 */
11416 { "vmaskmovpd", { XM, Vex, Mx }, 0 },
11419 /* VEX_W_0F382E_P_2_M_0 */
11420 { "vmaskmovps", { Mx, Vex, XM }, 0 },
11423 /* VEX_W_0F382F_P_2_M_0 */
11424 { "vmaskmovpd", { Mx, Vex, XM }, 0 },
11427 /* VEX_W_0F3830_P_2 */
11428 { "vpmovzxbw", { XM, EXxmmq }, 0 },
11431 /* VEX_W_0F3831_P_2 */
11432 { "vpmovzxbd", { XM, EXxmmqd }, 0 },
11435 /* VEX_W_0F3832_P_2 */
11436 { "vpmovzxbq", { XM, EXxmmdw }, 0 },
11439 /* VEX_W_0F3833_P_2 */
11440 { "vpmovzxwd", { XM, EXxmmq }, 0 },
11443 /* VEX_W_0F3834_P_2 */
11444 { "vpmovzxwq", { XM, EXxmmqd }, 0 },
11447 /* VEX_W_0F3835_P_2 */
11448 { "vpmovzxdq", { XM, EXxmmq }, 0 },
11451 /* VEX_W_0F3836_P_2 */
11452 { "vpermd", { XM, Vex, EXx }, 0 },
11455 /* VEX_W_0F3837_P_2 */
11456 { "vpcmpgtq", { XM, Vex, EXx }, 0 },
11459 /* VEX_W_0F3838_P_2 */
11460 { "vpminsb", { XM, Vex, EXx }, 0 },
11463 /* VEX_W_0F3839_P_2 */
11464 { "vpminsd", { XM, Vex, EXx }, 0 },
11467 /* VEX_W_0F383A_P_2 */
11468 { "vpminuw", { XM, Vex, EXx }, 0 },
11471 /* VEX_W_0F383B_P_2 */
11472 { "vpminud", { XM, Vex, EXx }, 0 },
11475 /* VEX_W_0F383C_P_2 */
11476 { "vpmaxsb", { XM, Vex, EXx }, 0 },
11479 /* VEX_W_0F383D_P_2 */
11480 { "vpmaxsd", { XM, Vex, EXx }, 0 },
11483 /* VEX_W_0F383E_P_2 */
11484 { "vpmaxuw", { XM, Vex, EXx }, 0 },
11487 /* VEX_W_0F383F_P_2 */
11488 { "vpmaxud", { XM, Vex, EXx }, 0 },
11491 /* VEX_W_0F3840_P_2 */
11492 { "vpmulld", { XM, Vex, EXx }, 0 },
11495 /* VEX_W_0F3841_P_2 */
11496 { "vphminposuw", { XM, EXx }, 0 },
11499 /* VEX_W_0F3846_P_2 */
11500 { "vpsravd", { XM, Vex, EXx }, 0 },
11503 /* VEX_W_0F3858_P_2 */
11504 { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11507 /* VEX_W_0F3859_P_2 */
11508 { "vpbroadcastq", { XM, EXxmm_mq }, 0 },
11511 /* VEX_W_0F385A_P_2_M_0 */
11512 { "vbroadcasti128", { XM, Mxmm }, 0 },
11515 /* VEX_W_0F3878_P_2 */
11516 { "vpbroadcastb", { XM, EXxmm_mb }, 0 },
11519 /* VEX_W_0F3879_P_2 */
11520 { "vpbroadcastw", { XM, EXxmm_mw }, 0 },
11523 /* VEX_W_0F38DB_P_2 */
11524 { "vaesimc", { XM, EXx }, 0 },
11527 /* VEX_W_0F38DC_P_2 */
11528 { "vaesenc", { XM, Vex128, EXx }, 0 },
11531 /* VEX_W_0F38DD_P_2 */
11532 { "vaesenclast", { XM, Vex128, EXx }, 0 },
11535 /* VEX_W_0F38DE_P_2 */
11536 { "vaesdec", { XM, Vex128, EXx }, 0 },
11539 /* VEX_W_0F38DF_P_2 */
11540 { "vaesdeclast", { XM, Vex128, EXx }, 0 },
11543 /* VEX_W_0F3A00_P_2 */
11545 { "vpermq", { XM, EXx, Ib }, 0 },
11548 /* VEX_W_0F3A01_P_2 */
11550 { "vpermpd", { XM, EXx, Ib }, 0 },
11553 /* VEX_W_0F3A02_P_2 */
11554 { "vpblendd", { XM, Vex, EXx, Ib }, 0 },
11557 /* VEX_W_0F3A04_P_2 */
11558 { "vpermilps", { XM, EXx, Ib }, 0 },
11561 /* VEX_W_0F3A05_P_2 */
11562 { "vpermilpd", { XM, EXx, Ib }, 0 },
11565 /* VEX_W_0F3A06_P_2 */
11566 { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 },
11569 /* VEX_W_0F3A08_P_2 */
11570 { "vroundps", { XM, EXx, Ib }, 0 },
11573 /* VEX_W_0F3A09_P_2 */
11574 { "vroundpd", { XM, EXx, Ib }, 0 },
11577 /* VEX_W_0F3A0A_P_2 */
11578 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11581 /* VEX_W_0F3A0B_P_2 */
11582 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11585 /* VEX_W_0F3A0C_P_2 */
11586 { "vblendps", { XM, Vex, EXx, Ib }, 0 },
11589 /* VEX_W_0F3A0D_P_2 */
11590 { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
11593 /* VEX_W_0F3A0E_P_2 */
11594 { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
11597 /* VEX_W_0F3A0F_P_2 */
11598 { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
11601 /* VEX_W_0F3A14_P_2 */
11602 { "vpextrb", { Edqb, XM, Ib }, 0 },
11605 /* VEX_W_0F3A15_P_2 */
11606 { "vpextrw", { Edqw, XM, Ib }, 0 },
11609 /* VEX_W_0F3A18_P_2 */
11610 { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 },
11613 /* VEX_W_0F3A19_P_2 */
11614 { "vextractf128", { EXxmm, XM, Ib }, 0 },
11617 /* VEX_W_0F3A20_P_2 */
11618 { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
11621 /* VEX_W_0F3A21_P_2 */
11622 { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
11625 /* VEX_W_0F3A30_P_2_LEN_0 */
11626 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11627 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11630 /* VEX_W_0F3A31_P_2_LEN_0 */
11631 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11632 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11635 /* VEX_W_0F3A32_P_2_LEN_0 */
11636 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11637 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11640 /* VEX_W_0F3A33_P_2_LEN_0 */
11641 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11642 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11645 /* VEX_W_0F3A38_P_2 */
11646 { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 },
11649 /* VEX_W_0F3A39_P_2 */
11650 { "vextracti128", { EXxmm, XM, Ib }, 0 },
11653 /* VEX_W_0F3A40_P_2 */
11654 { "vdpps", { XM, Vex, EXx, Ib }, 0 },
11657 /* VEX_W_0F3A41_P_2 */
11658 { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
11661 /* VEX_W_0F3A42_P_2 */
11662 { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
11665 /* VEX_W_0F3A44_P_2 */
11666 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL }, 0 },
11669 /* VEX_W_0F3A46_P_2 */
11670 { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
11673 /* VEX_W_0F3A48_P_2 */
11674 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11675 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11678 /* VEX_W_0F3A49_P_2 */
11679 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11680 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11683 /* VEX_W_0F3A4A_P_2 */
11684 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 },
11687 /* VEX_W_0F3A4B_P_2 */
11688 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 },
11691 /* VEX_W_0F3A4C_P_2 */
11692 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
11695 /* VEX_W_0F3A60_P_2 */
11696 { "vpcmpestrm", { XM, EXx, Ib }, 0 },
11699 /* VEX_W_0F3A61_P_2 */
11700 { "vpcmpestri", { XM, EXx, Ib }, 0 },
11703 /* VEX_W_0F3A62_P_2 */
11704 { "vpcmpistrm", { XM, EXx, Ib }, 0 },
11707 /* VEX_W_0F3A63_P_2 */
11708 { "vpcmpistri", { XM, EXx, Ib }, 0 },
11711 /* VEX_W_0F3ADF_P_2 */
11712 { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11714 #define NEED_VEX_W_TABLE
11715 #include "i386-dis-evex.h"
11716 #undef NEED_VEX_W_TABLE
11719 static const struct dis386 mod_table[][2] = {
11722 { "leaS", { Gv, M }, 0 },
11727 { RM_TABLE (RM_C6_REG_7) },
11732 { RM_TABLE (RM_C7_REG_7) },
11736 { "Jcall^", { indirEp }, 0 },
11740 { "Jjmp^", { indirEp }, 0 },
11743 /* MOD_0F01_REG_0 */
11744 { X86_64_TABLE (X86_64_0F01_REG_0) },
11745 { RM_TABLE (RM_0F01_REG_0) },
11748 /* MOD_0F01_REG_1 */
11749 { X86_64_TABLE (X86_64_0F01_REG_1) },
11750 { RM_TABLE (RM_0F01_REG_1) },
11753 /* MOD_0F01_REG_2 */
11754 { X86_64_TABLE (X86_64_0F01_REG_2) },
11755 { RM_TABLE (RM_0F01_REG_2) },
11758 /* MOD_0F01_REG_3 */
11759 { X86_64_TABLE (X86_64_0F01_REG_3) },
11760 { RM_TABLE (RM_0F01_REG_3) },
11763 /* MOD_0F01_REG_5 */
11765 { RM_TABLE (RM_0F01_REG_5) },
11768 /* MOD_0F01_REG_7 */
11769 { "invlpg", { Mb }, 0 },
11770 { RM_TABLE (RM_0F01_REG_7) },
11773 /* MOD_0F12_PREFIX_0 */
11774 { "movlps", { XM, EXq }, PREFIX_OPCODE },
11775 { "movhlps", { XM, EXq }, PREFIX_OPCODE },
11779 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
11782 /* MOD_0F16_PREFIX_0 */
11783 { "movhps", { XM, EXq }, 0 },
11784 { "movlhps", { XM, EXq }, 0 },
11788 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
11791 /* MOD_0F18_REG_0 */
11792 { "prefetchnta", { Mb }, 0 },
11795 /* MOD_0F18_REG_1 */
11796 { "prefetcht0", { Mb }, 0 },
11799 /* MOD_0F18_REG_2 */
11800 { "prefetcht1", { Mb }, 0 },
11803 /* MOD_0F18_REG_3 */
11804 { "prefetcht2", { Mb }, 0 },
11807 /* MOD_0F18_REG_4 */
11808 { "nop/reserved", { Mb }, 0 },
11811 /* MOD_0F18_REG_5 */
11812 { "nop/reserved", { Mb }, 0 },
11815 /* MOD_0F18_REG_6 */
11816 { "nop/reserved", { Mb }, 0 },
11819 /* MOD_0F18_REG_7 */
11820 { "nop/reserved", { Mb }, 0 },
11823 /* MOD_0F1A_PREFIX_0 */
11824 { "bndldx", { Gbnd, Ev_bnd }, 0 },
11825 { "nopQ", { Ev }, 0 },
11828 /* MOD_0F1B_PREFIX_0 */
11829 { "bndstx", { Ev_bnd, Gbnd }, 0 },
11830 { "nopQ", { Ev }, 0 },
11833 /* MOD_0F1B_PREFIX_1 */
11834 { "bndmk", { Gbnd, Ev_bnd }, 0 },
11835 { "nopQ", { Ev }, 0 },
11840 { "movL", { Rd, Td }, 0 },
11845 { "movL", { Td, Rd }, 0 },
11848 /* MOD_0F2B_PREFIX_0 */
11849 {"movntps", { Mx, XM }, PREFIX_OPCODE },
11852 /* MOD_0F2B_PREFIX_1 */
11853 {"movntss", { Md, XM }, PREFIX_OPCODE },
11856 /* MOD_0F2B_PREFIX_2 */
11857 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
11860 /* MOD_0F2B_PREFIX_3 */
11861 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
11866 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
11869 /* MOD_0F71_REG_2 */
11871 { "psrlw", { MS, Ib }, 0 },
11874 /* MOD_0F71_REG_4 */
11876 { "psraw", { MS, Ib }, 0 },
11879 /* MOD_0F71_REG_6 */
11881 { "psllw", { MS, Ib }, 0 },
11884 /* MOD_0F72_REG_2 */
11886 { "psrld", { MS, Ib }, 0 },
11889 /* MOD_0F72_REG_4 */
11891 { "psrad", { MS, Ib }, 0 },
11894 /* MOD_0F72_REG_6 */
11896 { "pslld", { MS, Ib }, 0 },
11899 /* MOD_0F73_REG_2 */
11901 { "psrlq", { MS, Ib }, 0 },
11904 /* MOD_0F73_REG_3 */
11906 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11909 /* MOD_0F73_REG_6 */
11911 { "psllq", { MS, Ib }, 0 },
11914 /* MOD_0F73_REG_7 */
11916 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11919 /* MOD_0FAE_REG_0 */
11920 { "fxsave", { FXSAVE }, 0 },
11921 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11924 /* MOD_0FAE_REG_1 */
11925 { "fxrstor", { FXSAVE }, 0 },
11926 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11929 /* MOD_0FAE_REG_2 */
11930 { "ldmxcsr", { Md }, 0 },
11931 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11934 /* MOD_0FAE_REG_3 */
11935 { "stmxcsr", { Md }, 0 },
11936 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11939 /* MOD_0FAE_REG_4 */
11940 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11941 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11944 /* MOD_0FAE_REG_5 */
11945 { "xrstor", { FXSAVE }, 0 },
11946 { RM_TABLE (RM_0FAE_REG_5) },
11949 /* MOD_0FAE_REG_6 */
11950 { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11951 { RM_TABLE (RM_0FAE_REG_6) },
11954 /* MOD_0FAE_REG_7 */
11955 { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11956 { RM_TABLE (RM_0FAE_REG_7) },
11960 { "lssS", { Gv, Mp }, 0 },
11964 { "lfsS", { Gv, Mp }, 0 },
11968 { "lgsS", { Gv, Mp }, 0 },
11972 { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11975 /* MOD_0FC7_REG_3 */
11976 { "xrstors", { FXSAVE }, 0 },
11979 /* MOD_0FC7_REG_4 */
11980 { "xsavec", { FXSAVE }, 0 },
11983 /* MOD_0FC7_REG_5 */
11984 { "xsaves", { FXSAVE }, 0 },
11987 /* MOD_0FC7_REG_6 */
11988 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11989 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11992 /* MOD_0FC7_REG_7 */
11993 { "vmptrst", { Mq }, 0 },
11994 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11999 { "pmovmskb", { Gdq, MS }, 0 },
12002 /* MOD_0FE7_PREFIX_2 */
12003 { "movntdq", { Mx, XM }, 0 },
12006 /* MOD_0FF0_PREFIX_3 */
12007 { "lddqu", { XM, M }, 0 },
12010 /* MOD_0F382A_PREFIX_2 */
12011 { "movntdqa", { XM, Mx }, 0 },
12015 { "bound{S|}", { Gv, Ma }, 0 },
12016 { EVEX_TABLE (EVEX_0F) },
12020 { "lesS", { Gv, Mp }, 0 },
12021 { VEX_C4_TABLE (VEX_0F) },
12025 { "ldsS", { Gv, Mp }, 0 },
12026 { VEX_C5_TABLE (VEX_0F) },
12029 /* MOD_VEX_0F12_PREFIX_0 */
12030 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
12031 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
12035 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
12038 /* MOD_VEX_0F16_PREFIX_0 */
12039 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
12040 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
12044 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
12048 { VEX_W_TABLE (VEX_W_0F2B_M_0) },
12051 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
12053 { "kandw", { MaskG, MaskVex, MaskR }, 0 },
12056 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
12058 { "kandq", { MaskG, MaskVex, MaskR }, 0 },
12061 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
12063 { "kandb", { MaskG, MaskVex, MaskR }, 0 },
12066 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
12068 { "kandd", { MaskG, MaskVex, MaskR }, 0 },
12071 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
12073 { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
12076 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
12078 { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
12081 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
12083 { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
12086 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
12088 { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
12091 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
12093 { "knotw", { MaskG, MaskR }, 0 },
12096 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
12098 { "knotq", { MaskG, MaskR }, 0 },
12101 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
12103 { "knotb", { MaskG, MaskR }, 0 },
12106 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
12108 { "knotd", { MaskG, MaskR }, 0 },
12111 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
12113 { "korw", { MaskG, MaskVex, MaskR }, 0 },
12116 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
12118 { "korq", { MaskG, MaskVex, MaskR }, 0 },
12121 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
12123 { "korb", { MaskG, MaskVex, MaskR }, 0 },
12126 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
12128 { "kord", { MaskG, MaskVex, MaskR }, 0 },
12131 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
12133 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
12136 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
12138 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
12141 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
12143 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
12146 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
12148 { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
12151 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
12153 { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
12156 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
12158 { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
12161 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
12163 { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
12166 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
12168 { "kxord", { MaskG, MaskVex, MaskR }, 0 },
12171 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
12173 { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
12176 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
12178 { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
12181 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
12183 { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
12186 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
12188 { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
12191 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
12193 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
12196 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
12198 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
12201 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
12203 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
12208 { VEX_W_TABLE (VEX_W_0F50_M_0) },
12211 /* MOD_VEX_0F71_REG_2 */
12213 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
12216 /* MOD_VEX_0F71_REG_4 */
12218 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
12221 /* MOD_VEX_0F71_REG_6 */
12223 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
12226 /* MOD_VEX_0F72_REG_2 */
12228 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12231 /* MOD_VEX_0F72_REG_4 */
12233 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12236 /* MOD_VEX_0F72_REG_6 */
12238 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12241 /* MOD_VEX_0F73_REG_2 */
12243 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12246 /* MOD_VEX_0F73_REG_3 */
12248 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12251 /* MOD_VEX_0F73_REG_6 */
12253 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12256 /* MOD_VEX_0F73_REG_7 */
12258 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12261 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12262 { "kmovw", { Ew, MaskG }, 0 },
12266 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12267 { "kmovq", { Eq, MaskG }, 0 },
12271 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12272 { "kmovb", { Eb, MaskG }, 0 },
12276 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12277 { "kmovd", { Ed, MaskG }, 0 },
12281 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12283 { "kmovw", { MaskG, Rdq }, 0 },
12286 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12288 { "kmovb", { MaskG, Rdq }, 0 },
12291 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12293 { "kmovd", { MaskG, Rdq }, 0 },
12296 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12298 { "kmovq", { MaskG, Rdq }, 0 },
12301 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12303 { "kmovw", { Gdq, MaskR }, 0 },
12306 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12308 { "kmovb", { Gdq, MaskR }, 0 },
12311 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12313 { "kmovd", { Gdq, MaskR }, 0 },
12316 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12318 { "kmovq", { Gdq, MaskR }, 0 },
12321 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12323 { "kortestw", { MaskG, MaskR }, 0 },
12326 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12328 { "kortestq", { MaskG, MaskR }, 0 },
12331 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12333 { "kortestb", { MaskG, MaskR }, 0 },
12336 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12338 { "kortestd", { MaskG, MaskR }, 0 },
12341 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12343 { "ktestw", { MaskG, MaskR }, 0 },
12346 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12348 { "ktestq", { MaskG, MaskR }, 0 },
12351 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12353 { "ktestb", { MaskG, MaskR }, 0 },
12356 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12358 { "ktestd", { MaskG, MaskR }, 0 },
12361 /* MOD_VEX_0FAE_REG_2 */
12362 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12365 /* MOD_VEX_0FAE_REG_3 */
12366 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12369 /* MOD_VEX_0FD7_PREFIX_2 */
12371 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12374 /* MOD_VEX_0FE7_PREFIX_2 */
12375 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12378 /* MOD_VEX_0FF0_PREFIX_3 */
12379 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12382 /* MOD_VEX_0F381A_PREFIX_2 */
12383 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12386 /* MOD_VEX_0F382A_PREFIX_2 */
12387 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12390 /* MOD_VEX_0F382C_PREFIX_2 */
12391 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12394 /* MOD_VEX_0F382D_PREFIX_2 */
12395 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12398 /* MOD_VEX_0F382E_PREFIX_2 */
12399 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12402 /* MOD_VEX_0F382F_PREFIX_2 */
12403 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12406 /* MOD_VEX_0F385A_PREFIX_2 */
12407 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12410 /* MOD_VEX_0F388C_PREFIX_2 */
12411 { "vpmaskmov%LW", { XM, Vex, Mx }, 0 },
12414 /* MOD_VEX_0F388E_PREFIX_2 */
12415 { "vpmaskmov%LW", { Mx, Vex, XM }, 0 },
12418 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12420 { "kshiftrb", { MaskG, MaskR, Ib }, 0 },
12423 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12425 { "kshiftrw", { MaskG, MaskR, Ib }, 0 },
12428 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12430 { "kshiftrd", { MaskG, MaskR, Ib }, 0 },
12433 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12435 { "kshiftrq", { MaskG, MaskR, Ib }, 0 },
12438 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12440 { "kshiftlb", { MaskG, MaskR, Ib }, 0 },
12443 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12445 { "kshiftlw", { MaskG, MaskR, Ib }, 0 },
12448 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12450 { "kshiftld", { MaskG, MaskR, Ib }, 0 },
12453 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12455 { "kshiftlq", { MaskG, MaskR, Ib }, 0 },
12457 #define NEED_MOD_TABLE
12458 #include "i386-dis-evex.h"
12459 #undef NEED_MOD_TABLE
12462 static const struct dis386 rm_table[][8] = {
12465 { "xabort", { Skip_MODRM, Ib }, 0 },
12469 { "xbeginT", { Skip_MODRM, Jv }, 0 },
12472 /* RM_0F01_REG_0 */
12474 { "vmcall", { Skip_MODRM }, 0 },
12475 { "vmlaunch", { Skip_MODRM }, 0 },
12476 { "vmresume", { Skip_MODRM }, 0 },
12477 { "vmxoff", { Skip_MODRM }, 0 },
12480 /* RM_0F01_REG_1 */
12481 { "monitor", { { OP_Monitor, 0 } }, 0 },
12482 { "mwait", { { OP_Mwait, 0 } }, 0 },
12483 { "clac", { Skip_MODRM }, 0 },
12484 { "stac", { Skip_MODRM }, 0 },
12488 { "encls", { Skip_MODRM }, 0 },
12491 /* RM_0F01_REG_2 */
12492 { "xgetbv", { Skip_MODRM }, 0 },
12493 { "xsetbv", { Skip_MODRM }, 0 },
12496 { "vmfunc", { Skip_MODRM }, 0 },
12497 { "xend", { Skip_MODRM }, 0 },
12498 { "xtest", { Skip_MODRM }, 0 },
12499 { "enclu", { Skip_MODRM }, 0 },
12502 /* RM_0F01_REG_3 */
12503 { "vmrun", { Skip_MODRM }, 0 },
12504 { "vmmcall", { Skip_MODRM }, 0 },
12505 { "vmload", { Skip_MODRM }, 0 },
12506 { "vmsave", { Skip_MODRM }, 0 },
12507 { "stgi", { Skip_MODRM }, 0 },
12508 { "clgi", { Skip_MODRM }, 0 },
12509 { "skinit", { Skip_MODRM }, 0 },
12510 { "invlpga", { Skip_MODRM }, 0 },
12513 /* RM_0F01_REG_5 */
12520 { "rdpkru", { Skip_MODRM }, 0 },
12521 { "wrpkru", { Skip_MODRM }, 0 },
12524 /* RM_0F01_REG_7 */
12525 { "swapgs", { Skip_MODRM }, 0 },
12526 { "rdtscp", { Skip_MODRM }, 0 },
12527 { "monitorx", { { OP_Monitor, 0 } }, 0 },
12528 { "mwaitx", { { OP_Mwaitx, 0 } }, 0 },
12529 { "clzero", { Skip_MODRM }, 0 },
12532 /* RM_0FAE_REG_5 */
12533 { "lfence", { Skip_MODRM }, 0 },
12536 /* RM_0FAE_REG_6 */
12537 { "mfence", { Skip_MODRM }, 0 },
12540 /* RM_0FAE_REG_7 */
12541 { "sfence", { Skip_MODRM }, 0 },
12546 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12548 /* We use the high bit to indicate different name for the same
12550 #define REP_PREFIX (0xf3 | 0x100)
12551 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12552 #define XRELEASE_PREFIX (0xf3 | 0x400)
12553 #define BND_PREFIX (0xf2 | 0x400)
12558 int newrex, i, length;
12564 last_lock_prefix = -1;
12565 last_repz_prefix = -1;
12566 last_repnz_prefix = -1;
12567 last_data_prefix = -1;
12568 last_addr_prefix = -1;
12569 last_rex_prefix = -1;
12570 last_seg_prefix = -1;
12572 active_seg_prefix = 0;
12573 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12574 all_prefixes[i] = 0;
12577 /* The maximum instruction length is 15bytes. */
12578 while (length < MAX_CODE_LENGTH - 1)
12580 FETCH_DATA (the_info, codep + 1);
12584 /* REX prefixes family. */
12601 if (address_mode == mode_64bit)
12605 last_rex_prefix = i;
12608 prefixes |= PREFIX_REPZ;
12609 last_repz_prefix = i;
12612 prefixes |= PREFIX_REPNZ;
12613 last_repnz_prefix = i;
12616 prefixes |= PREFIX_LOCK;
12617 last_lock_prefix = i;
12620 prefixes |= PREFIX_CS;
12621 last_seg_prefix = i;
12622 active_seg_prefix = PREFIX_CS;
12625 prefixes |= PREFIX_SS;
12626 last_seg_prefix = i;
12627 active_seg_prefix = PREFIX_SS;
12630 prefixes |= PREFIX_DS;
12631 last_seg_prefix = i;
12632 active_seg_prefix = PREFIX_DS;
12635 prefixes |= PREFIX_ES;
12636 last_seg_prefix = i;
12637 active_seg_prefix = PREFIX_ES;
12640 prefixes |= PREFIX_FS;
12641 last_seg_prefix = i;
12642 active_seg_prefix = PREFIX_FS;
12645 prefixes |= PREFIX_GS;
12646 last_seg_prefix = i;
12647 active_seg_prefix = PREFIX_GS;
12650 prefixes |= PREFIX_DATA;
12651 last_data_prefix = i;
12654 prefixes |= PREFIX_ADDR;
12655 last_addr_prefix = i;
12658 /* fwait is really an instruction. If there are prefixes
12659 before the fwait, they belong to the fwait, *not* to the
12660 following instruction. */
12662 if (prefixes || rex)
12664 prefixes |= PREFIX_FWAIT;
12666 /* This ensures that the previous REX prefixes are noticed
12667 as unused prefixes, as in the return case below. */
12671 prefixes = PREFIX_FWAIT;
12676 /* Rex is ignored when followed by another prefix. */
12682 if (*codep != FWAIT_OPCODE)
12683 all_prefixes[i++] = *codep;
12691 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12694 static const char *
12695 prefix_name (int pref, int sizeflag)
12697 static const char *rexes [16] =
12700 "rex.B", /* 0x41 */
12701 "rex.X", /* 0x42 */
12702 "rex.XB", /* 0x43 */
12703 "rex.R", /* 0x44 */
12704 "rex.RB", /* 0x45 */
12705 "rex.RX", /* 0x46 */
12706 "rex.RXB", /* 0x47 */
12707 "rex.W", /* 0x48 */
12708 "rex.WB", /* 0x49 */
12709 "rex.WX", /* 0x4a */
12710 "rex.WXB", /* 0x4b */
12711 "rex.WR", /* 0x4c */
12712 "rex.WRB", /* 0x4d */
12713 "rex.WRX", /* 0x4e */
12714 "rex.WRXB", /* 0x4f */
12719 /* REX prefixes family. */
12736 return rexes [pref - 0x40];
12756 return (sizeflag & DFLAG) ? "data16" : "data32";
12758 if (address_mode == mode_64bit)
12759 return (sizeflag & AFLAG) ? "addr32" : "addr64";
12761 return (sizeflag & AFLAG) ? "addr16" : "addr32";
12766 case XACQUIRE_PREFIX:
12768 case XRELEASE_PREFIX:
12777 static char op_out[MAX_OPERANDS][100];
12778 static int op_ad, op_index[MAX_OPERANDS];
12779 static int two_source_ops;
12780 static bfd_vma op_address[MAX_OPERANDS];
12781 static bfd_vma op_riprel[MAX_OPERANDS];
12782 static bfd_vma start_pc;
12785 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12786 * (see topic "Redundant prefixes" in the "Differences from 8086"
12787 * section of the "Virtual 8086 Mode" chapter.)
12788 * 'pc' should be the address of this instruction, it will
12789 * be used to print the target address if this is a relative jump or call
12790 * The function returns the length of this instruction in bytes.
12793 static char intel_syntax;
12794 static char intel_mnemonic = !SYSV386_COMPAT;
12795 static char open_char;
12796 static char close_char;
12797 static char separator_char;
12798 static char scale_char;
12806 static enum x86_64_isa isa64;
12808 /* Here for backwards compatibility. When gdb stops using
12809 print_insn_i386_att and print_insn_i386_intel these functions can
12810 disappear, and print_insn_i386 be merged into print_insn. */
12812 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12816 return print_insn (pc, info);
12820 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12824 return print_insn (pc, info);
12828 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12832 return print_insn (pc, info);
12836 print_i386_disassembler_options (FILE *stream)
12838 fprintf (stream, _("\n\
12839 The following i386/x86-64 specific disassembler options are supported for use\n\
12840 with the -M switch (multiple options should be separated by commas):\n"));
12842 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
12843 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
12844 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
12845 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
12846 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
12847 fprintf (stream, _(" att-mnemonic\n"
12848 " Display instruction in AT&T mnemonic\n"));
12849 fprintf (stream, _(" intel-mnemonic\n"
12850 " Display instruction in Intel mnemonic\n"));
12851 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
12852 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
12853 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
12854 fprintf (stream, _(" data32 Assume 32bit data size\n"));
12855 fprintf (stream, _(" data16 Assume 16bit data size\n"));
12856 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12857 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
12858 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
12862 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12864 /* Get a pointer to struct dis386 with a valid name. */
12866 static const struct dis386 *
12867 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12869 int vindex, vex_table_index;
12871 if (dp->name != NULL)
12874 switch (dp->op[0].bytemode)
12876 case USE_REG_TABLE:
12877 dp = ®_table[dp->op[1].bytemode][modrm.reg];
12880 case USE_MOD_TABLE:
12881 vindex = modrm.mod == 0x3 ? 1 : 0;
12882 dp = &mod_table[dp->op[1].bytemode][vindex];
12886 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12889 case USE_PREFIX_TABLE:
12892 /* The prefix in VEX is implicit. */
12893 switch (vex.prefix)
12898 case REPE_PREFIX_OPCODE:
12901 case DATA_PREFIX_OPCODE:
12904 case REPNE_PREFIX_OPCODE:
12914 int last_prefix = -1;
12917 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12918 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12920 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12922 if (last_repz_prefix > last_repnz_prefix)
12925 prefix = PREFIX_REPZ;
12926 last_prefix = last_repz_prefix;
12931 prefix = PREFIX_REPNZ;
12932 last_prefix = last_repnz_prefix;
12935 /* Check if prefix should be ignored. */
12936 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12937 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12942 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12945 prefix = PREFIX_DATA;
12946 last_prefix = last_data_prefix;
12951 used_prefixes |= prefix;
12952 all_prefixes[last_prefix] = 0;
12955 dp = &prefix_table[dp->op[1].bytemode][vindex];
12958 case USE_X86_64_TABLE:
12959 vindex = address_mode == mode_64bit ? 1 : 0;
12960 dp = &x86_64_table[dp->op[1].bytemode][vindex];
12963 case USE_3BYTE_TABLE:
12964 FETCH_DATA (info, codep + 2);
12966 dp = &three_byte_table[dp->op[1].bytemode][vindex];
12968 modrm.mod = (*codep >> 6) & 3;
12969 modrm.reg = (*codep >> 3) & 7;
12970 modrm.rm = *codep & 7;
12973 case USE_VEX_LEN_TABLE:
12977 switch (vex.length)
12990 dp = &vex_len_table[dp->op[1].bytemode][vindex];
12993 case USE_XOP_8F_TABLE:
12994 FETCH_DATA (info, codep + 3);
12995 /* All bits in the REX prefix are ignored. */
12997 rex = ~(*codep >> 5) & 0x7;
12999 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
13000 switch ((*codep & 0x1f))
13006 vex_table_index = XOP_08;
13009 vex_table_index = XOP_09;
13012 vex_table_index = XOP_0A;
13016 vex.w = *codep & 0x80;
13017 if (vex.w && address_mode == mode_64bit)
13020 vex.register_specifier = (~(*codep >> 3)) & 0xf;
13021 if (address_mode != mode_64bit
13022 && vex.register_specifier > 0x7)
13028 vex.length = (*codep & 0x4) ? 256 : 128;
13029 switch ((*codep & 0x3))
13035 vex.prefix = DATA_PREFIX_OPCODE;
13038 vex.prefix = REPE_PREFIX_OPCODE;
13041 vex.prefix = REPNE_PREFIX_OPCODE;
13048 dp = &xop_table[vex_table_index][vindex];
13051 FETCH_DATA (info, codep + 1);
13052 modrm.mod = (*codep >> 6) & 3;
13053 modrm.reg = (*codep >> 3) & 7;
13054 modrm.rm = *codep & 7;
13057 case USE_VEX_C4_TABLE:
13059 FETCH_DATA (info, codep + 3);
13060 /* All bits in the REX prefix are ignored. */
13062 rex = ~(*codep >> 5) & 0x7;
13063 switch ((*codep & 0x1f))
13069 vex_table_index = VEX_0F;
13072 vex_table_index = VEX_0F38;
13075 vex_table_index = VEX_0F3A;
13079 vex.w = *codep & 0x80;
13080 if (address_mode == mode_64bit)
13084 vex.register_specifier = (~(*codep >> 3)) & 0xf;
13088 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
13089 is ignored, other REX bits are 0 and the highest bit in
13090 VEX.vvvv is also ignored. */
13092 vex.register_specifier = (~(*codep >> 3)) & 0x7;
13094 vex.length = (*codep & 0x4) ? 256 : 128;
13095 switch ((*codep & 0x3))
13101 vex.prefix = DATA_PREFIX_OPCODE;
13104 vex.prefix = REPE_PREFIX_OPCODE;
13107 vex.prefix = REPNE_PREFIX_OPCODE;
13114 dp = &vex_table[vex_table_index][vindex];
13116 /* There is no MODRM byte for VEX [82|77]. */
13117 if (vindex != 0x77 && vindex != 0x82)
13119 FETCH_DATA (info, codep + 1);
13120 modrm.mod = (*codep >> 6) & 3;
13121 modrm.reg = (*codep >> 3) & 7;
13122 modrm.rm = *codep & 7;
13126 case USE_VEX_C5_TABLE:
13128 FETCH_DATA (info, codep + 2);
13129 /* All bits in the REX prefix are ignored. */
13131 rex = (*codep & 0x80) ? 0 : REX_R;
13133 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
13135 vex.register_specifier = (~(*codep >> 3)) & 0xf;
13137 vex.length = (*codep & 0x4) ? 256 : 128;
13138 switch ((*codep & 0x3))
13144 vex.prefix = DATA_PREFIX_OPCODE;
13147 vex.prefix = REPE_PREFIX_OPCODE;
13150 vex.prefix = REPNE_PREFIX_OPCODE;
13157 dp = &vex_table[dp->op[1].bytemode][vindex];
13159 /* There is no MODRM byte for VEX [82|77]. */
13160 if (vindex != 0x77 && vindex != 0x82)
13162 FETCH_DATA (info, codep + 1);
13163 modrm.mod = (*codep >> 6) & 3;
13164 modrm.reg = (*codep >> 3) & 7;
13165 modrm.rm = *codep & 7;
13169 case USE_VEX_W_TABLE:
13173 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
13176 case USE_EVEX_TABLE:
13177 two_source_ops = 0;
13180 FETCH_DATA (info, codep + 4);
13181 /* All bits in the REX prefix are ignored. */
13183 /* The first byte after 0x62. */
13184 rex = ~(*codep >> 5) & 0x7;
13185 vex.r = *codep & 0x10;
13186 switch ((*codep & 0xf))
13189 return &bad_opcode;
13191 vex_table_index = EVEX_0F;
13194 vex_table_index = EVEX_0F38;
13197 vex_table_index = EVEX_0F3A;
13201 /* The second byte after 0x62. */
13203 vex.w = *codep & 0x80;
13204 if (vex.w && address_mode == mode_64bit)
13207 vex.register_specifier = (~(*codep >> 3)) & 0xf;
13208 if (address_mode != mode_64bit)
13210 /* In 16/32-bit mode silently ignore following bits. */
13214 vex.register_specifier &= 0x7;
13218 if (!(*codep & 0x4))
13219 return &bad_opcode;
13221 switch ((*codep & 0x3))
13227 vex.prefix = DATA_PREFIX_OPCODE;
13230 vex.prefix = REPE_PREFIX_OPCODE;
13233 vex.prefix = REPNE_PREFIX_OPCODE;
13237 /* The third byte after 0x62. */
13240 /* Remember the static rounding bits. */
13241 vex.ll = (*codep >> 5) & 3;
13242 vex.b = (*codep & 0x10) != 0;
13244 vex.v = *codep & 0x8;
13245 vex.mask_register_specifier = *codep & 0x7;
13246 vex.zeroing = *codep & 0x80;
13252 dp = &evex_table[vex_table_index][vindex];
13254 FETCH_DATA (info, codep + 1);
13255 modrm.mod = (*codep >> 6) & 3;
13256 modrm.reg = (*codep >> 3) & 7;
13257 modrm.rm = *codep & 7;
13259 /* Set vector length. */
13260 if (modrm.mod == 3 && vex.b)
13276 return &bad_opcode;
13289 if (dp->name != NULL)
13292 return get_valid_dis386 (dp, info);
13296 get_sib (disassemble_info *info, int sizeflag)
13298 /* If modrm.mod == 3, operand must be register. */
13300 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13304 FETCH_DATA (info, codep + 2);
13305 sib.index = (codep [1] >> 3) & 7;
13306 sib.scale = (codep [1] >> 6) & 3;
13307 sib.base = codep [1] & 7;
13312 print_insn (bfd_vma pc, disassemble_info *info)
13314 const struct dis386 *dp;
13316 char *op_txt[MAX_OPERANDS];
13318 int sizeflag, orig_sizeflag;
13320 struct dis_private priv;
13323 priv.orig_sizeflag = AFLAG | DFLAG;
13324 if ((info->mach & bfd_mach_i386_i386) != 0)
13325 address_mode = mode_32bit;
13326 else if (info->mach == bfd_mach_i386_i8086)
13328 address_mode = mode_16bit;
13329 priv.orig_sizeflag = 0;
13332 address_mode = mode_64bit;
13334 if (intel_syntax == (char) -1)
13335 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13337 for (p = info->disassembler_options; p != NULL; )
13339 if (CONST_STRNEQ (p, "amd64"))
13341 else if (CONST_STRNEQ (p, "intel64"))
13343 else if (CONST_STRNEQ (p, "x86-64"))
13345 address_mode = mode_64bit;
13346 priv.orig_sizeflag = AFLAG | DFLAG;
13348 else if (CONST_STRNEQ (p, "i386"))
13350 address_mode = mode_32bit;
13351 priv.orig_sizeflag = AFLAG | DFLAG;
13353 else if (CONST_STRNEQ (p, "i8086"))
13355 address_mode = mode_16bit;
13356 priv.orig_sizeflag = 0;
13358 else if (CONST_STRNEQ (p, "intel"))
13361 if (CONST_STRNEQ (p + 5, "-mnemonic"))
13362 intel_mnemonic = 1;
13364 else if (CONST_STRNEQ (p, "att"))
13367 if (CONST_STRNEQ (p + 3, "-mnemonic"))
13368 intel_mnemonic = 0;
13370 else if (CONST_STRNEQ (p, "addr"))
13372 if (address_mode == mode_64bit)
13374 if (p[4] == '3' && p[5] == '2')
13375 priv.orig_sizeflag &= ~AFLAG;
13376 else if (p[4] == '6' && p[5] == '4')
13377 priv.orig_sizeflag |= AFLAG;
13381 if (p[4] == '1' && p[5] == '6')
13382 priv.orig_sizeflag &= ~AFLAG;
13383 else if (p[4] == '3' && p[5] == '2')
13384 priv.orig_sizeflag |= AFLAG;
13387 else if (CONST_STRNEQ (p, "data"))
13389 if (p[4] == '1' && p[5] == '6')
13390 priv.orig_sizeflag &= ~DFLAG;
13391 else if (p[4] == '3' && p[5] == '2')
13392 priv.orig_sizeflag |= DFLAG;
13394 else if (CONST_STRNEQ (p, "suffix"))
13395 priv.orig_sizeflag |= SUFFIX_ALWAYS;
13397 p = strchr (p, ',');
13402 if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13404 (*info->fprintf_func) (info->stream,
13405 _("64-bit address is disabled"));
13411 names64 = intel_names64;
13412 names32 = intel_names32;
13413 names16 = intel_names16;
13414 names8 = intel_names8;
13415 names8rex = intel_names8rex;
13416 names_seg = intel_names_seg;
13417 names_mm = intel_names_mm;
13418 names_bnd = intel_names_bnd;
13419 names_xmm = intel_names_xmm;
13420 names_ymm = intel_names_ymm;
13421 names_zmm = intel_names_zmm;
13422 index64 = intel_index64;
13423 index32 = intel_index32;
13424 names_mask = intel_names_mask;
13425 index16 = intel_index16;
13428 separator_char = '+';
13433 names64 = att_names64;
13434 names32 = att_names32;
13435 names16 = att_names16;
13436 names8 = att_names8;
13437 names8rex = att_names8rex;
13438 names_seg = att_names_seg;
13439 names_mm = att_names_mm;
13440 names_bnd = att_names_bnd;
13441 names_xmm = att_names_xmm;
13442 names_ymm = att_names_ymm;
13443 names_zmm = att_names_zmm;
13444 index64 = att_index64;
13445 index32 = att_index32;
13446 names_mask = att_names_mask;
13447 index16 = att_index16;
13450 separator_char = ',';
13454 /* The output looks better if we put 7 bytes on a line, since that
13455 puts most long word instructions on a single line. Use 8 bytes
13457 if ((info->mach & bfd_mach_l1om) != 0)
13458 info->bytes_per_line = 8;
13460 info->bytes_per_line = 7;
13462 info->private_data = &priv;
13463 priv.max_fetched = priv.the_buffer;
13464 priv.insn_start = pc;
13467 for (i = 0; i < MAX_OPERANDS; ++i)
13475 start_codep = priv.the_buffer;
13476 codep = priv.the_buffer;
13478 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13482 /* Getting here means we tried for data but didn't get it. That
13483 means we have an incomplete instruction of some sort. Just
13484 print the first byte as a prefix or a .byte pseudo-op. */
13485 if (codep > priv.the_buffer)
13487 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13489 (*info->fprintf_func) (info->stream, "%s", name);
13492 /* Just print the first byte as a .byte instruction. */
13493 (*info->fprintf_func) (info->stream, ".byte 0x%x",
13494 (unsigned int) priv.the_buffer[0]);
13504 sizeflag = priv.orig_sizeflag;
13506 if (!ckprefix () || rex_used)
13508 /* Too many prefixes or unused REX prefixes. */
13510 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13512 (*info->fprintf_func) (info->stream, "%s%s",
13514 prefix_name (all_prefixes[i], sizeflag));
13518 insn_codep = codep;
13520 FETCH_DATA (info, codep + 1);
13521 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13523 if (((prefixes & PREFIX_FWAIT)
13524 && ((*codep < 0xd8) || (*codep > 0xdf))))
13526 /* Handle prefixes before fwait. */
13527 for (i = 0; i < fwait_prefix && all_prefixes[i];
13529 (*info->fprintf_func) (info->stream, "%s ",
13530 prefix_name (all_prefixes[i], sizeflag));
13531 (*info->fprintf_func) (info->stream, "fwait");
13535 if (*codep == 0x0f)
13537 unsigned char threebyte;
13540 FETCH_DATA (info, codep + 1);
13541 threebyte = *codep;
13542 dp = &dis386_twobyte[threebyte];
13543 need_modrm = twobyte_has_modrm[*codep];
13548 dp = &dis386[*codep];
13549 need_modrm = onebyte_has_modrm[*codep];
13553 /* Save sizeflag for printing the extra prefixes later before updating
13554 it for mnemonic and operand processing. The prefix names depend
13555 only on the address mode. */
13556 orig_sizeflag = sizeflag;
13557 if (prefixes & PREFIX_ADDR)
13559 if ((prefixes & PREFIX_DATA))
13565 FETCH_DATA (info, codep + 1);
13566 modrm.mod = (*codep >> 6) & 3;
13567 modrm.reg = (*codep >> 3) & 7;
13568 modrm.rm = *codep & 7;
13576 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13578 get_sib (info, sizeflag);
13579 dofloat (sizeflag);
13583 dp = get_valid_dis386 (dp, info);
13584 if (dp != NULL && putop (dp->name, sizeflag) == 0)
13586 get_sib (info, sizeflag);
13587 for (i = 0; i < MAX_OPERANDS; ++i)
13590 op_ad = MAX_OPERANDS - 1 - i;
13592 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13593 /* For EVEX instruction after the last operand masking
13594 should be printed. */
13595 if (i == 0 && vex.evex)
13597 /* Don't print {%k0}. */
13598 if (vex.mask_register_specifier)
13601 oappend (names_mask[vex.mask_register_specifier]);
13611 /* Check if the REX prefix is used. */
13612 if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13613 all_prefixes[last_rex_prefix] = 0;
13615 /* Check if the SEG prefix is used. */
13616 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13617 | PREFIX_FS | PREFIX_GS)) != 0
13618 && (used_prefixes & active_seg_prefix) != 0)
13619 all_prefixes[last_seg_prefix] = 0;
13621 /* Check if the ADDR prefix is used. */
13622 if ((prefixes & PREFIX_ADDR) != 0
13623 && (used_prefixes & PREFIX_ADDR) != 0)
13624 all_prefixes[last_addr_prefix] = 0;
13626 /* Check if the DATA prefix is used. */
13627 if ((prefixes & PREFIX_DATA) != 0
13628 && (used_prefixes & PREFIX_DATA) != 0)
13629 all_prefixes[last_data_prefix] = 0;
13631 /* Print the extra prefixes. */
13633 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13634 if (all_prefixes[i])
13637 name = prefix_name (all_prefixes[i], orig_sizeflag);
13640 prefix_length += strlen (name) + 1;
13641 (*info->fprintf_func) (info->stream, "%s ", name);
13644 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13645 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13646 used by putop and MMX/SSE operand and may be overriden by the
13647 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13649 if (dp->prefix_requirement == PREFIX_OPCODE
13650 && dp != &bad_opcode
13652 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13654 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13656 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13658 && (used_prefixes & PREFIX_DATA) == 0))))
13660 (*info->fprintf_func) (info->stream, "(bad)");
13661 return end_codep - priv.the_buffer;
13664 /* Check maximum code length. */
13665 if ((codep - start_codep) > MAX_CODE_LENGTH)
13667 (*info->fprintf_func) (info->stream, "(bad)");
13668 return MAX_CODE_LENGTH;
13671 obufp = mnemonicendp;
13672 for (i = strlen (obuf) + prefix_length; i < 6; i++)
13675 (*info->fprintf_func) (info->stream, "%s", obuf);
13677 /* The enter and bound instructions are printed with operands in the same
13678 order as the intel book; everything else is printed in reverse order. */
13679 if (intel_syntax || two_source_ops)
13683 for (i = 0; i < MAX_OPERANDS; ++i)
13684 op_txt[i] = op_out[i];
13686 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13687 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13689 op_txt[2] = op_out[3];
13690 op_txt[3] = op_out[2];
13693 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13695 op_ad = op_index[i];
13696 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13697 op_index[MAX_OPERANDS - 1 - i] = op_ad;
13698 riprel = op_riprel[i];
13699 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13700 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13705 for (i = 0; i < MAX_OPERANDS; ++i)
13706 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13710 for (i = 0; i < MAX_OPERANDS; ++i)
13714 (*info->fprintf_func) (info->stream, ",");
13715 if (op_index[i] != -1 && !op_riprel[i])
13716 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13718 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13722 for (i = 0; i < MAX_OPERANDS; i++)
13723 if (op_index[i] != -1 && op_riprel[i])
13725 (*info->fprintf_func) (info->stream, " # ");
13726 (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13727 + op_address[op_index[i]]), info);
13730 return codep - priv.the_buffer;
13733 static const char *float_mem[] = {
13808 static const unsigned char float_mem_mode[] = {
13883 #define ST { OP_ST, 0 }
13884 #define STi { OP_STi, 0 }
13886 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13887 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13888 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13889 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13890 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13891 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13892 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13893 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13894 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13896 static const struct dis386 float_reg[][8] = {
13899 { "fadd", { ST, STi }, 0 },
13900 { "fmul", { ST, STi }, 0 },
13901 { "fcom", { STi }, 0 },
13902 { "fcomp", { STi }, 0 },
13903 { "fsub", { ST, STi }, 0 },
13904 { "fsubr", { ST, STi }, 0 },
13905 { "fdiv", { ST, STi }, 0 },
13906 { "fdivr", { ST, STi }, 0 },
13910 { "fld", { STi }, 0 },
13911 { "fxch", { STi }, 0 },
13921 { "fcmovb", { ST, STi }, 0 },
13922 { "fcmove", { ST, STi }, 0 },
13923 { "fcmovbe",{ ST, STi }, 0 },
13924 { "fcmovu", { ST, STi }, 0 },
13932 { "fcmovnb",{ ST, STi }, 0 },
13933 { "fcmovne",{ ST, STi }, 0 },
13934 { "fcmovnbe",{ ST, STi }, 0 },
13935 { "fcmovnu",{ ST, STi }, 0 },
13937 { "fucomi", { ST, STi }, 0 },
13938 { "fcomi", { ST, STi }, 0 },
13943 { "fadd", { STi, ST }, 0 },
13944 { "fmul", { STi, ST }, 0 },
13947 { "fsub!M", { STi, ST }, 0 },
13948 { "fsubM", { STi, ST }, 0 },
13949 { "fdiv!M", { STi, ST }, 0 },
13950 { "fdivM", { STi, ST }, 0 },
13954 { "ffree", { STi }, 0 },
13956 { "fst", { STi }, 0 },
13957 { "fstp", { STi }, 0 },
13958 { "fucom", { STi }, 0 },
13959 { "fucomp", { STi }, 0 },
13965 { "faddp", { STi, ST }, 0 },
13966 { "fmulp", { STi, ST }, 0 },
13969 { "fsub!Mp", { STi, ST }, 0 },
13970 { "fsubMp", { STi, ST }, 0 },
13971 { "fdiv!Mp", { STi, ST }, 0 },
13972 { "fdivMp", { STi, ST }, 0 },
13976 { "ffreep", { STi }, 0 },
13981 { "fucomip", { ST, STi }, 0 },
13982 { "fcomip", { ST, STi }, 0 },
13987 static char *fgrps[][8] = {
13990 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13995 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
14000 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
14005 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
14010 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
14015 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
14020 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
14021 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
14026 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
14031 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
14036 swap_operand (void)
14038 mnemonicendp[0] = '.';
14039 mnemonicendp[1] = 's';
14044 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
14045 int sizeflag ATTRIBUTE_UNUSED)
14047 /* Skip mod/rm byte. */
14053 dofloat (int sizeflag)
14055 const struct dis386 *dp;
14056 unsigned char floatop;
14058 floatop = codep[-1];
14060 if (modrm.mod != 3)
14062 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
14064 putop (float_mem[fp_indx], sizeflag);
14067 OP_E (float_mem_mode[fp_indx], sizeflag);
14070 /* Skip mod/rm byte. */
14074 dp = &float_reg[floatop - 0xd8][modrm.reg];
14075 if (dp->name == NULL)
14077 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
14079 /* Instruction fnstsw is only one with strange arg. */
14080 if (floatop == 0xdf && codep[-1] == 0xe0)
14081 strcpy (op_out[0], names16[0]);
14085 putop (dp->name, sizeflag);
14090 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
14095 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
14099 /* Like oappend (below), but S is a string starting with '%'.
14100 In Intel syntax, the '%' is elided. */
14102 oappend_maybe_intel (const char *s)
14104 oappend (s + intel_syntax);
14108 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14110 oappend_maybe_intel ("%st");
14114 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14116 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
14117 oappend_maybe_intel (scratchbuf);
14120 /* Capital letters in template are macros. */
14122 putop (const char *in_template, int sizeflag)
14127 unsigned int l = 0, len = 1;
14130 #define SAVE_LAST(c) \
14131 if (l < len && l < sizeof (last)) \
14136 for (p = in_template; *p; p++)
14152 while (*++p != '|')
14153 if (*p == '}' || *p == '\0')
14156 /* Fall through. */
14161 while (*++p != '}')
14172 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14176 if (l == 0 && len == 1)
14181 if (sizeflag & SUFFIX_ALWAYS)
14194 if (address_mode == mode_64bit
14195 && !(prefixes & PREFIX_ADDR))
14206 if (intel_syntax && !alt)
14208 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14210 if (sizeflag & DFLAG)
14211 *obufp++ = intel_syntax ? 'd' : 'l';
14213 *obufp++ = intel_syntax ? 'w' : 's';
14214 used_prefixes |= (prefixes & PREFIX_DATA);
14218 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14221 if (modrm.mod == 3)
14227 if (sizeflag & DFLAG)
14228 *obufp++ = intel_syntax ? 'd' : 'l';
14231 used_prefixes |= (prefixes & PREFIX_DATA);
14237 case 'E': /* For jcxz/jecxz */
14238 if (address_mode == mode_64bit)
14240 if (sizeflag & AFLAG)
14246 if (sizeflag & AFLAG)
14248 used_prefixes |= (prefixes & PREFIX_ADDR);
14253 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14255 if (sizeflag & AFLAG)
14256 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14258 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14259 used_prefixes |= (prefixes & PREFIX_ADDR);
14263 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14265 if ((rex & REX_W) || (sizeflag & DFLAG))
14269 if (!(rex & REX_W))
14270 used_prefixes |= (prefixes & PREFIX_DATA);
14275 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14276 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14278 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14281 if (prefixes & PREFIX_DS)
14300 if (l != 0 || len != 1)
14302 if (l != 1 || len != 2 || last[0] != 'X')
14307 if (!need_vex || !vex.evex)
14310 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14312 switch (vex.length)
14330 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14335 /* Fall through. */
14338 if (l != 0 || len != 1)
14346 if (sizeflag & SUFFIX_ALWAYS)
14350 if (intel_mnemonic != cond)
14354 if ((prefixes & PREFIX_FWAIT) == 0)
14357 used_prefixes |= PREFIX_FWAIT;
14363 else if (intel_syntax && (sizeflag & DFLAG))
14367 if (!(rex & REX_W))
14368 used_prefixes |= (prefixes & PREFIX_DATA);
14372 && address_mode == mode_64bit
14373 && isa64 == intel64)
14378 /* Fall through. */
14381 && address_mode == mode_64bit
14382 && ((sizeflag & DFLAG) || (rex & REX_W)))
14387 /* Fall through. */
14390 if (l == 0 && len == 1)
14395 if ((rex & REX_W) == 0
14396 && (prefixes & PREFIX_DATA))
14398 if ((sizeflag & DFLAG) == 0)
14400 used_prefixes |= (prefixes & PREFIX_DATA);
14404 if ((prefixes & PREFIX_DATA)
14406 || (sizeflag & SUFFIX_ALWAYS))
14413 if (sizeflag & DFLAG)
14417 used_prefixes |= (prefixes & PREFIX_DATA);
14423 if (l != 1 || len != 2 || last[0] != 'L')
14429 if ((prefixes & PREFIX_DATA)
14431 || (sizeflag & SUFFIX_ALWAYS))
14438 if (sizeflag & DFLAG)
14439 *obufp++ = intel_syntax ? 'd' : 'l';
14442 used_prefixes |= (prefixes & PREFIX_DATA);
14450 if (address_mode == mode_64bit
14451 && ((sizeflag & DFLAG) || (rex & REX_W)))
14453 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14457 /* Fall through. */
14460 if (l == 0 && len == 1)
14463 if (intel_syntax && !alt)
14466 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14472 if (sizeflag & DFLAG)
14473 *obufp++ = intel_syntax ? 'd' : 'l';
14476 used_prefixes |= (prefixes & PREFIX_DATA);
14482 if (l != 1 || len != 2 || last[0] != 'L')
14488 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14503 else if (sizeflag & DFLAG)
14512 if (intel_syntax && !p[1]
14513 && ((rex & REX_W) || (sizeflag & DFLAG)))
14515 if (!(rex & REX_W))
14516 used_prefixes |= (prefixes & PREFIX_DATA);
14519 if (l == 0 && len == 1)
14523 if (address_mode == mode_64bit
14524 && ((sizeflag & DFLAG) || (rex & REX_W)))
14526 if (sizeflag & SUFFIX_ALWAYS)
14548 /* Fall through. */
14551 if (l == 0 && len == 1)
14556 if (sizeflag & SUFFIX_ALWAYS)
14562 if (sizeflag & DFLAG)
14566 used_prefixes |= (prefixes & PREFIX_DATA);
14580 if (address_mode == mode_64bit
14581 && !(prefixes & PREFIX_ADDR))
14592 if (l != 0 || len != 1)
14597 if (need_vex && vex.prefix)
14599 if (vex.prefix == DATA_PREFIX_OPCODE)
14606 if (prefixes & PREFIX_DATA)
14610 used_prefixes |= (prefixes & PREFIX_DATA);
14614 if (l == 0 && len == 1)
14616 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14627 if (l != 1 || len != 2 || last[0] != 'X')
14635 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14637 switch (vex.length)
14653 if (l == 0 && len == 1)
14655 /* operand size flag for cwtl, cbtw */
14664 else if (sizeflag & DFLAG)
14668 if (!(rex & REX_W))
14669 used_prefixes |= (prefixes & PREFIX_DATA);
14676 && last[0] != 'L'))
14683 if (last[0] == 'X')
14684 *obufp++ = vex.w ? 'd': 's';
14686 *obufp++ = vex.w ? 'q': 'd';
14692 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14694 if (sizeflag & DFLAG)
14698 used_prefixes |= (prefixes & PREFIX_DATA);
14704 if (address_mode == mode_64bit
14705 && (isa64 == intel64
14706 || ((sizeflag & DFLAG) || (rex & REX_W))))
14708 else if ((prefixes & PREFIX_DATA))
14710 if (!(sizeflag & DFLAG))
14712 used_prefixes |= (prefixes & PREFIX_DATA);
14719 mnemonicendp = obufp;
14724 oappend (const char *s)
14726 obufp = stpcpy (obufp, s);
14732 /* Only print the active segment register. */
14733 if (!active_seg_prefix)
14736 used_prefixes |= active_seg_prefix;
14737 switch (active_seg_prefix)
14740 oappend_maybe_intel ("%cs:");
14743 oappend_maybe_intel ("%ds:");
14746 oappend_maybe_intel ("%ss:");
14749 oappend_maybe_intel ("%es:");
14752 oappend_maybe_intel ("%fs:");
14755 oappend_maybe_intel ("%gs:");
14763 OP_indirE (int bytemode, int sizeflag)
14767 OP_E (bytemode, sizeflag);
14771 print_operand_value (char *buf, int hex, bfd_vma disp)
14773 if (address_mode == mode_64bit)
14781 sprintf_vma (tmp, disp);
14782 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14783 strcpy (buf + 2, tmp + i);
14787 bfd_signed_vma v = disp;
14794 /* Check for possible overflow on 0x8000000000000000. */
14797 strcpy (buf, "9223372036854775808");
14811 tmp[28 - i] = (v % 10) + '0';
14815 strcpy (buf, tmp + 29 - i);
14821 sprintf (buf, "0x%x", (unsigned int) disp);
14823 sprintf (buf, "%d", (int) disp);
14827 /* Put DISP in BUF as signed hex number. */
14830 print_displacement (char *buf, bfd_vma disp)
14832 bfd_signed_vma val = disp;
14841 /* Check for possible overflow. */
14844 switch (address_mode)
14847 strcpy (buf + j, "0x8000000000000000");
14850 strcpy (buf + j, "0x80000000");
14853 strcpy (buf + j, "0x8000");
14863 sprintf_vma (tmp, (bfd_vma) val);
14864 for (i = 0; tmp[i] == '0'; i++)
14866 if (tmp[i] == '\0')
14868 strcpy (buf + j, tmp + i);
14872 intel_operand_size (int bytemode, int sizeflag)
14876 && (bytemode == x_mode
14877 || bytemode == evex_half_bcst_xmmq_mode))
14880 oappend ("QWORD PTR ");
14882 oappend ("DWORD PTR ");
14891 oappend ("BYTE PTR ");
14896 case dqw_swap_mode:
14897 oappend ("WORD PTR ");
14900 if (address_mode == mode_64bit && isa64 == intel64)
14902 oappend ("QWORD PTR ");
14905 /* Fall through. */
14907 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14909 oappend ("QWORD PTR ");
14912 /* Fall through. */
14918 oappend ("QWORD PTR ");
14921 if ((sizeflag & DFLAG) || bytemode == dq_mode)
14922 oappend ("DWORD PTR ");
14924 oappend ("WORD PTR ");
14925 used_prefixes |= (prefixes & PREFIX_DATA);
14929 if ((rex & REX_W) || (sizeflag & DFLAG))
14931 oappend ("WORD PTR ");
14932 if (!(rex & REX_W))
14933 used_prefixes |= (prefixes & PREFIX_DATA);
14936 if (sizeflag & DFLAG)
14937 oappend ("QWORD PTR ");
14939 oappend ("DWORD PTR ");
14940 used_prefixes |= (prefixes & PREFIX_DATA);
14943 case d_scalar_mode:
14944 case d_scalar_swap_mode:
14947 oappend ("DWORD PTR ");
14950 case q_scalar_mode:
14951 case q_scalar_swap_mode:
14953 oappend ("QWORD PTR ");
14956 if (address_mode == mode_64bit)
14957 oappend ("QWORD PTR ");
14959 oappend ("DWORD PTR ");
14962 if (sizeflag & DFLAG)
14963 oappend ("FWORD PTR ");
14965 oappend ("DWORD PTR ");
14966 used_prefixes |= (prefixes & PREFIX_DATA);
14969 oappend ("TBYTE PTR ");
14973 case evex_x_gscat_mode:
14974 case evex_x_nobcst_mode:
14977 switch (vex.length)
14980 oappend ("XMMWORD PTR ");
14983 oappend ("YMMWORD PTR ");
14986 oappend ("ZMMWORD PTR ");
14993 oappend ("XMMWORD PTR ");
14996 oappend ("XMMWORD PTR ");
14999 oappend ("YMMWORD PTR ");
15002 case evex_half_bcst_xmmq_mode:
15006 switch (vex.length)
15009 oappend ("QWORD PTR ");
15012 oappend ("XMMWORD PTR ");
15015 oappend ("YMMWORD PTR ");
15025 switch (vex.length)
15030 oappend ("BYTE PTR ");
15040 switch (vex.length)
15045 oappend ("WORD PTR ");
15055 switch (vex.length)
15060 oappend ("DWORD PTR ");
15070 switch (vex.length)
15075 oappend ("QWORD PTR ");
15085 switch (vex.length)
15088 oappend ("WORD PTR ");
15091 oappend ("DWORD PTR ");
15094 oappend ("QWORD PTR ");
15104 switch (vex.length)
15107 oappend ("DWORD PTR ");
15110 oappend ("QWORD PTR ");
15113 oappend ("XMMWORD PTR ");
15123 switch (vex.length)
15126 oappend ("QWORD PTR ");
15129 oappend ("YMMWORD PTR ");
15132 oappend ("ZMMWORD PTR ");
15142 switch (vex.length)
15146 oappend ("XMMWORD PTR ");
15153 oappend ("OWORD PTR ");
15156 case vex_w_dq_mode:
15157 case vex_scalar_w_dq_mode:
15162 oappend ("QWORD PTR ");
15164 oappend ("DWORD PTR ");
15166 case vex_vsib_d_w_dq_mode:
15167 case vex_vsib_q_w_dq_mode:
15174 oappend ("QWORD PTR ");
15176 oappend ("DWORD PTR ");
15180 switch (vex.length)
15183 oappend ("XMMWORD PTR ");
15186 oappend ("YMMWORD PTR ");
15189 oappend ("ZMMWORD PTR ");
15196 case vex_vsib_q_w_d_mode:
15197 case vex_vsib_d_w_d_mode:
15198 if (!need_vex || !vex.evex)
15201 switch (vex.length)
15204 oappend ("QWORD PTR ");
15207 oappend ("XMMWORD PTR ");
15210 oappend ("YMMWORD PTR ");
15218 if (!need_vex || vex.length != 128)
15221 oappend ("DWORD PTR ");
15223 oappend ("BYTE PTR ");
15229 oappend ("QWORD PTR ");
15231 oappend ("WORD PTR ");
15240 OP_E_register (int bytemode, int sizeflag)
15242 int reg = modrm.rm;
15243 const char **names;
15249 if ((sizeflag & SUFFIX_ALWAYS)
15250 && (bytemode == b_swap_mode
15251 || bytemode == v_swap_mode
15252 || bytemode == dqw_swap_mode))
15278 names = address_mode == mode_64bit ? names64 : names32;
15284 if (address_mode == mode_64bit && isa64 == intel64)
15289 /* Fall through. */
15291 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15297 /* Fall through. */
15304 case dqw_swap_mode:
15310 if ((sizeflag & DFLAG)
15311 || (bytemode != v_mode
15312 && bytemode != v_swap_mode))
15316 used_prefixes |= (prefixes & PREFIX_DATA);
15326 names = names_mask;
15331 oappend (INTERNAL_DISASSEMBLER_ERROR);
15334 oappend (names[reg]);
15338 OP_E_memory (int bytemode, int sizeflag)
15341 int add = (rex & REX_B) ? 8 : 0;
15347 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
15349 && bytemode != x_mode
15350 && bytemode != xmmq_mode
15351 && bytemode != evex_half_bcst_xmmq_mode)
15360 case dqw_swap_mode:
15367 case vex_vsib_d_w_dq_mode:
15368 case vex_vsib_d_w_d_mode:
15369 case vex_vsib_q_w_dq_mode:
15370 case vex_vsib_q_w_d_mode:
15371 case evex_x_gscat_mode:
15373 shift = vex.w ? 3 : 2;
15376 case evex_half_bcst_xmmq_mode:
15380 shift = vex.w ? 3 : 2;
15383 /* Fall through. */
15387 case evex_x_nobcst_mode:
15389 switch (vex.length)
15412 case q_scalar_mode:
15414 case q_scalar_swap_mode:
15420 case d_scalar_mode:
15422 case d_scalar_swap_mode:
15434 /* Make necessary corrections to shift for modes that need it.
15435 For these modes we currently have shift 4, 5 or 6 depending on
15436 vex.length (it corresponds to xmmword, ymmword or zmmword
15437 operand). We might want to make it 3, 4 or 5 (e.g. for
15438 xmmq_mode). In case of broadcast enabled the corrections
15439 aren't needed, as element size is always 32 or 64 bits. */
15441 && (bytemode == xmmq_mode
15442 || bytemode == evex_half_bcst_xmmq_mode))
15444 else if (bytemode == xmmqd_mode)
15446 else if (bytemode == xmmdw_mode)
15448 else if (bytemode == ymmq_mode && vex.length == 128)
15456 intel_operand_size (bytemode, sizeflag);
15459 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15461 /* 32/64 bit address mode */
15470 int addr32flag = !((sizeflag & AFLAG)
15471 || bytemode == v_bnd_mode
15472 || bytemode == bnd_mode);
15473 const char **indexes64 = names64;
15474 const char **indexes32 = names32;
15484 vindex = sib.index;
15490 case vex_vsib_d_w_dq_mode:
15491 case vex_vsib_d_w_d_mode:
15492 case vex_vsib_q_w_dq_mode:
15493 case vex_vsib_q_w_d_mode:
15503 switch (vex.length)
15506 indexes64 = indexes32 = names_xmm;
15510 || bytemode == vex_vsib_q_w_dq_mode
15511 || bytemode == vex_vsib_q_w_d_mode)
15512 indexes64 = indexes32 = names_ymm;
15514 indexes64 = indexes32 = names_xmm;
15518 || bytemode == vex_vsib_q_w_dq_mode
15519 || bytemode == vex_vsib_q_w_d_mode)
15520 indexes64 = indexes32 = names_zmm;
15522 indexes64 = indexes32 = names_ymm;
15529 haveindex = vindex != 4;
15536 rbase = base + add;
15544 if (address_mode == mode_64bit && !havesib)
15550 FETCH_DATA (the_info, codep + 1);
15552 if ((disp & 0x80) != 0)
15554 if (vex.evex && shift > 0)
15562 /* In 32bit mode, we need index register to tell [offset] from
15563 [eiz*1 + offset]. */
15564 needindex = (havesib
15567 && address_mode == mode_32bit);
15568 havedisp = (havebase
15570 || (havesib && (haveindex || scale != 0)));
15573 if (modrm.mod != 0 || base == 5)
15575 if (havedisp || riprel)
15576 print_displacement (scratchbuf, disp);
15578 print_operand_value (scratchbuf, 1, disp);
15579 oappend (scratchbuf);
15583 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15587 if ((havebase || haveindex || riprel)
15588 && (bytemode != v_bnd_mode)
15589 && (bytemode != bnd_mode))
15590 used_prefixes |= PREFIX_ADDR;
15592 if (havedisp || (intel_syntax && riprel))
15594 *obufp++ = open_char;
15595 if (intel_syntax && riprel)
15598 oappend (!addr32flag ? "rip" : "eip");
15602 oappend (address_mode == mode_64bit && !addr32flag
15603 ? names64[rbase] : names32[rbase]);
15606 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15607 print index to tell base + index from base. */
15611 || (havebase && base != ESP_REG_NUM))
15613 if (!intel_syntax || havebase)
15615 *obufp++ = separator_char;
15619 oappend (address_mode == mode_64bit && !addr32flag
15620 ? indexes64[vindex] : indexes32[vindex]);
15622 oappend (address_mode == mode_64bit && !addr32flag
15623 ? index64 : index32);
15625 *obufp++ = scale_char;
15627 sprintf (scratchbuf, "%d", 1 << scale);
15628 oappend (scratchbuf);
15632 && (disp || modrm.mod != 0 || base == 5))
15634 if (!havedisp || (bfd_signed_vma) disp >= 0)
15639 else if (modrm.mod != 1 && disp != -disp)
15643 disp = - (bfd_signed_vma) disp;
15647 print_displacement (scratchbuf, disp);
15649 print_operand_value (scratchbuf, 1, disp);
15650 oappend (scratchbuf);
15653 *obufp++ = close_char;
15656 else if (intel_syntax)
15658 if (modrm.mod != 0 || base == 5)
15660 if (!active_seg_prefix)
15662 oappend (names_seg[ds_reg - es_reg]);
15665 print_operand_value (scratchbuf, 1, disp);
15666 oappend (scratchbuf);
15672 /* 16 bit address mode */
15673 used_prefixes |= prefixes & PREFIX_ADDR;
15680 if ((disp & 0x8000) != 0)
15685 FETCH_DATA (the_info, codep + 1);
15687 if ((disp & 0x80) != 0)
15692 if ((disp & 0x8000) != 0)
15698 if (modrm.mod != 0 || modrm.rm == 6)
15700 print_displacement (scratchbuf, disp);
15701 oappend (scratchbuf);
15704 if (modrm.mod != 0 || modrm.rm != 6)
15706 *obufp++ = open_char;
15708 oappend (index16[modrm.rm]);
15710 && (disp || modrm.mod != 0 || modrm.rm == 6))
15712 if ((bfd_signed_vma) disp >= 0)
15717 else if (modrm.mod != 1)
15721 disp = - (bfd_signed_vma) disp;
15724 print_displacement (scratchbuf, disp);
15725 oappend (scratchbuf);
15728 *obufp++ = close_char;
15731 else if (intel_syntax)
15733 if (!active_seg_prefix)
15735 oappend (names_seg[ds_reg - es_reg]);
15738 print_operand_value (scratchbuf, 1, disp & 0xffff);
15739 oappend (scratchbuf);
15742 if (vex.evex && vex.b
15743 && (bytemode == x_mode
15744 || bytemode == xmmq_mode
15745 || bytemode == evex_half_bcst_xmmq_mode))
15748 || bytemode == xmmq_mode
15749 || bytemode == evex_half_bcst_xmmq_mode)
15751 switch (vex.length)
15754 oappend ("{1to2}");
15757 oappend ("{1to4}");
15760 oappend ("{1to8}");
15768 switch (vex.length)
15771 oappend ("{1to4}");
15774 oappend ("{1to8}");
15777 oappend ("{1to16}");
15787 OP_E (int bytemode, int sizeflag)
15789 /* Skip mod/rm byte. */
15793 if (modrm.mod == 3)
15794 OP_E_register (bytemode, sizeflag);
15796 OP_E_memory (bytemode, sizeflag);
15800 OP_G (int bytemode, int sizeflag)
15811 oappend (names8rex[modrm.reg + add]);
15813 oappend (names8[modrm.reg + add]);
15816 oappend (names16[modrm.reg + add]);
15821 oappend (names32[modrm.reg + add]);
15824 oappend (names64[modrm.reg + add]);
15827 oappend (names_bnd[modrm.reg]);
15834 case dqw_swap_mode:
15837 oappend (names64[modrm.reg + add]);
15840 if ((sizeflag & DFLAG) || bytemode != v_mode)
15841 oappend (names32[modrm.reg + add]);
15843 oappend (names16[modrm.reg + add]);
15844 used_prefixes |= (prefixes & PREFIX_DATA);
15848 if (address_mode == mode_64bit)
15849 oappend (names64[modrm.reg + add]);
15851 oappend (names32[modrm.reg + add]);
15855 if ((modrm.reg + add) > 0x7)
15860 oappend (names_mask[modrm.reg + add]);
15863 oappend (INTERNAL_DISASSEMBLER_ERROR);
15876 FETCH_DATA (the_info, codep + 8);
15877 a = *codep++ & 0xff;
15878 a |= (*codep++ & 0xff) << 8;
15879 a |= (*codep++ & 0xff) << 16;
15880 a |= (*codep++ & 0xffu) << 24;
15881 b = *codep++ & 0xff;
15882 b |= (*codep++ & 0xff) << 8;
15883 b |= (*codep++ & 0xff) << 16;
15884 b |= (*codep++ & 0xffu) << 24;
15885 x = a + ((bfd_vma) b << 32);
15893 static bfd_signed_vma
15896 bfd_signed_vma x = 0;
15898 FETCH_DATA (the_info, codep + 4);
15899 x = *codep++ & (bfd_signed_vma) 0xff;
15900 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15901 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15902 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15906 static bfd_signed_vma
15909 bfd_signed_vma x = 0;
15911 FETCH_DATA (the_info, codep + 4);
15912 x = *codep++ & (bfd_signed_vma) 0xff;
15913 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15914 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15915 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15917 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15927 FETCH_DATA (the_info, codep + 2);
15928 x = *codep++ & 0xff;
15929 x |= (*codep++ & 0xff) << 8;
15934 set_op (bfd_vma op, int riprel)
15936 op_index[op_ad] = op_ad;
15937 if (address_mode == mode_64bit)
15939 op_address[op_ad] = op;
15940 op_riprel[op_ad] = riprel;
15944 /* Mask to get a 32-bit address. */
15945 op_address[op_ad] = op & 0xffffffff;
15946 op_riprel[op_ad] = riprel & 0xffffffff;
15951 OP_REG (int code, int sizeflag)
15958 case es_reg: case ss_reg: case cs_reg:
15959 case ds_reg: case fs_reg: case gs_reg:
15960 oappend (names_seg[code - es_reg]);
15972 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15973 case sp_reg: case bp_reg: case si_reg: case di_reg:
15974 s = names16[code - ax_reg + add];
15976 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15977 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15980 s = names8rex[code - al_reg + add];
15982 s = names8[code - al_reg];
15984 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15985 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15986 if (address_mode == mode_64bit
15987 && ((sizeflag & DFLAG) || (rex & REX_W)))
15989 s = names64[code - rAX_reg + add];
15992 code += eAX_reg - rAX_reg;
15993 /* Fall through. */
15994 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15995 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15998 s = names64[code - eAX_reg + add];
16001 if (sizeflag & DFLAG)
16002 s = names32[code - eAX_reg + add];
16004 s = names16[code - eAX_reg + add];
16005 used_prefixes |= (prefixes & PREFIX_DATA);
16009 s = INTERNAL_DISASSEMBLER_ERROR;
16016 OP_IMREG (int code, int sizeflag)
16028 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
16029 case sp_reg: case bp_reg: case si_reg: case di_reg:
16030 s = names16[code - ax_reg];
16032 case es_reg: case ss_reg: case cs_reg:
16033 case ds_reg: case fs_reg: case gs_reg:
16034 s = names_seg[code - es_reg];
16036 case al_reg: case ah_reg: case cl_reg: case ch_reg:
16037 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
16040 s = names8rex[code - al_reg];
16042 s = names8[code - al_reg];
16044 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
16045 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
16048 s = names64[code - eAX_reg];
16051 if (sizeflag & DFLAG)
16052 s = names32[code - eAX_reg];
16054 s = names16[code - eAX_reg];
16055 used_prefixes |= (prefixes & PREFIX_DATA);
16058 case z_mode_ax_reg:
16059 if ((rex & REX_W) || (sizeflag & DFLAG))
16063 if (!(rex & REX_W))
16064 used_prefixes |= (prefixes & PREFIX_DATA);
16067 s = INTERNAL_DISASSEMBLER_ERROR;
16074 OP_I (int bytemode, int sizeflag)
16077 bfd_signed_vma mask = -1;
16082 FETCH_DATA (the_info, codep + 1);
16087 if (address_mode == mode_64bit)
16092 /* Fall through. */
16099 if (sizeflag & DFLAG)
16109 used_prefixes |= (prefixes & PREFIX_DATA);
16121 oappend (INTERNAL_DISASSEMBLER_ERROR);
16126 scratchbuf[0] = '$';
16127 print_operand_value (scratchbuf + 1, 1, op);
16128 oappend_maybe_intel (scratchbuf);
16129 scratchbuf[0] = '\0';
16133 OP_I64 (int bytemode, int sizeflag)
16136 bfd_signed_vma mask = -1;
16138 if (address_mode != mode_64bit)
16140 OP_I (bytemode, sizeflag);
16147 FETCH_DATA (the_info, codep + 1);
16157 if (sizeflag & DFLAG)
16167 used_prefixes |= (prefixes & PREFIX_DATA);
16175 oappend (INTERNAL_DISASSEMBLER_ERROR);
16180 scratchbuf[0] = '$';
16181 print_operand_value (scratchbuf + 1, 1, op);
16182 oappend_maybe_intel (scratchbuf);
16183 scratchbuf[0] = '\0';
16187 OP_sI (int bytemode, int sizeflag)
16195 FETCH_DATA (the_info, codep + 1);
16197 if ((op & 0x80) != 0)
16199 if (bytemode == b_T_mode)
16201 if (address_mode != mode_64bit
16202 || !((sizeflag & DFLAG) || (rex & REX_W)))
16204 /* The operand-size prefix is overridden by a REX prefix. */
16205 if ((sizeflag & DFLAG) || (rex & REX_W))
16213 if (!(rex & REX_W))
16215 if (sizeflag & DFLAG)
16223 /* The operand-size prefix is overridden by a REX prefix. */
16224 if ((sizeflag & DFLAG) || (rex & REX_W))
16230 oappend (INTERNAL_DISASSEMBLER_ERROR);
16234 scratchbuf[0] = '$';
16235 print_operand_value (scratchbuf + 1, 1, op);
16236 oappend_maybe_intel (scratchbuf);
16240 OP_J (int bytemode, int sizeflag)
16244 bfd_vma segment = 0;
16249 FETCH_DATA (the_info, codep + 1);
16251 if ((disp & 0x80) != 0)
16255 if (isa64 == amd64)
16257 if ((sizeflag & DFLAG)
16258 || (address_mode == mode_64bit
16259 && (isa64 != amd64 || (rex & REX_W))))
16264 if ((disp & 0x8000) != 0)
16266 /* In 16bit mode, address is wrapped around at 64k within
16267 the same segment. Otherwise, a data16 prefix on a jump
16268 instruction means that the pc is masked to 16 bits after
16269 the displacement is added! */
16271 if ((prefixes & PREFIX_DATA) == 0)
16272 segment = ((start_pc + (codep - start_codep))
16273 & ~((bfd_vma) 0xffff));
16275 if (address_mode != mode_64bit
16276 || (isa64 == amd64 && !(rex & REX_W)))
16277 used_prefixes |= (prefixes & PREFIX_DATA);
16280 oappend (INTERNAL_DISASSEMBLER_ERROR);
16283 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16285 print_operand_value (scratchbuf, 1, disp);
16286 oappend (scratchbuf);
16290 OP_SEG (int bytemode, int sizeflag)
16292 if (bytemode == w_mode)
16293 oappend (names_seg[modrm.reg]);
16295 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16299 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16303 if (sizeflag & DFLAG)
16313 used_prefixes |= (prefixes & PREFIX_DATA);
16315 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16317 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16318 oappend (scratchbuf);
16322 OP_OFF (int bytemode, int sizeflag)
16326 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16327 intel_operand_size (bytemode, sizeflag);
16330 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16337 if (!active_seg_prefix)
16339 oappend (names_seg[ds_reg - es_reg]);
16343 print_operand_value (scratchbuf, 1, off);
16344 oappend (scratchbuf);
16348 OP_OFF64 (int bytemode, int sizeflag)
16352 if (address_mode != mode_64bit
16353 || (prefixes & PREFIX_ADDR))
16355 OP_OFF (bytemode, sizeflag);
16359 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16360 intel_operand_size (bytemode, sizeflag);
16367 if (!active_seg_prefix)
16369 oappend (names_seg[ds_reg - es_reg]);
16373 print_operand_value (scratchbuf, 1, off);
16374 oappend (scratchbuf);
16378 ptr_reg (int code, int sizeflag)
16382 *obufp++ = open_char;
16383 used_prefixes |= (prefixes & PREFIX_ADDR);
16384 if (address_mode == mode_64bit)
16386 if (!(sizeflag & AFLAG))
16387 s = names32[code - eAX_reg];
16389 s = names64[code - eAX_reg];
16391 else if (sizeflag & AFLAG)
16392 s = names32[code - eAX_reg];
16394 s = names16[code - eAX_reg];
16396 *obufp++ = close_char;
16401 OP_ESreg (int code, int sizeflag)
16407 case 0x6d: /* insw/insl */
16408 intel_operand_size (z_mode, sizeflag);
16410 case 0xa5: /* movsw/movsl/movsq */
16411 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16412 case 0xab: /* stosw/stosl */
16413 case 0xaf: /* scasw/scasl */
16414 intel_operand_size (v_mode, sizeflag);
16417 intel_operand_size (b_mode, sizeflag);
16420 oappend_maybe_intel ("%es:");
16421 ptr_reg (code, sizeflag);
16425 OP_DSreg (int code, int sizeflag)
16431 case 0x6f: /* outsw/outsl */
16432 intel_operand_size (z_mode, sizeflag);
16434 case 0xa5: /* movsw/movsl/movsq */
16435 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16436 case 0xad: /* lodsw/lodsl/lodsq */
16437 intel_operand_size (v_mode, sizeflag);
16440 intel_operand_size (b_mode, sizeflag);
16443 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16444 default segment register DS is printed. */
16445 if (!active_seg_prefix)
16446 active_seg_prefix = PREFIX_DS;
16448 ptr_reg (code, sizeflag);
16452 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16460 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16462 all_prefixes[last_lock_prefix] = 0;
16463 used_prefixes |= PREFIX_LOCK;
16468 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16469 oappend_maybe_intel (scratchbuf);
16473 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16482 sprintf (scratchbuf, "db%d", modrm.reg + add);
16484 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16485 oappend (scratchbuf);
16489 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16491 sprintf (scratchbuf, "%%tr%d", modrm.reg);
16492 oappend_maybe_intel (scratchbuf);
16496 OP_R (int bytemode, int sizeflag)
16498 /* Skip mod/rm byte. */
16501 OP_E_register (bytemode, sizeflag);
16505 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16507 int reg = modrm.reg;
16508 const char **names;
16510 used_prefixes |= (prefixes & PREFIX_DATA);
16511 if (prefixes & PREFIX_DATA)
16520 oappend (names[reg]);
16524 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16526 int reg = modrm.reg;
16527 const char **names;
16539 && bytemode != xmm_mode
16540 && bytemode != xmmq_mode
16541 && bytemode != evex_half_bcst_xmmq_mode
16542 && bytemode != ymm_mode
16543 && bytemode != scalar_mode)
16545 switch (vex.length)
16552 || (bytemode != vex_vsib_q_w_dq_mode
16553 && bytemode != vex_vsib_q_w_d_mode))
16565 else if (bytemode == xmmq_mode
16566 || bytemode == evex_half_bcst_xmmq_mode)
16568 switch (vex.length)
16581 else if (bytemode == ymm_mode)
16585 oappend (names[reg]);
16589 OP_EM (int bytemode, int sizeflag)
16592 const char **names;
16594 if (modrm.mod != 3)
16597 && (bytemode == v_mode || bytemode == v_swap_mode))
16599 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16600 used_prefixes |= (prefixes & PREFIX_DATA);
16602 OP_E (bytemode, sizeflag);
16606 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16609 /* Skip mod/rm byte. */
16612 used_prefixes |= (prefixes & PREFIX_DATA);
16614 if (prefixes & PREFIX_DATA)
16623 oappend (names[reg]);
16626 /* cvt* are the only instructions in sse2 which have
16627 both SSE and MMX operands and also have 0x66 prefix
16628 in their opcode. 0x66 was originally used to differentiate
16629 between SSE and MMX instruction(operands). So we have to handle the
16630 cvt* separately using OP_EMC and OP_MXC */
16632 OP_EMC (int bytemode, int sizeflag)
16634 if (modrm.mod != 3)
16636 if (intel_syntax && bytemode == v_mode)
16638 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16639 used_prefixes |= (prefixes & PREFIX_DATA);
16641 OP_E (bytemode, sizeflag);
16645 /* Skip mod/rm byte. */
16648 used_prefixes |= (prefixes & PREFIX_DATA);
16649 oappend (names_mm[modrm.rm]);
16653 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16655 used_prefixes |= (prefixes & PREFIX_DATA);
16656 oappend (names_mm[modrm.reg]);
16660 OP_EX (int bytemode, int sizeflag)
16663 const char **names;
16665 /* Skip mod/rm byte. */
16669 if (modrm.mod != 3)
16671 OP_E_memory (bytemode, sizeflag);
16686 if ((sizeflag & SUFFIX_ALWAYS)
16687 && (bytemode == x_swap_mode
16688 || bytemode == d_swap_mode
16689 || bytemode == dqw_swap_mode
16690 || bytemode == d_scalar_swap_mode
16691 || bytemode == q_swap_mode
16692 || bytemode == q_scalar_swap_mode))
16696 && bytemode != xmm_mode
16697 && bytemode != xmmdw_mode
16698 && bytemode != xmmqd_mode
16699 && bytemode != xmm_mb_mode
16700 && bytemode != xmm_mw_mode
16701 && bytemode != xmm_md_mode
16702 && bytemode != xmm_mq_mode
16703 && bytemode != xmm_mdq_mode
16704 && bytemode != xmmq_mode
16705 && bytemode != evex_half_bcst_xmmq_mode
16706 && bytemode != ymm_mode
16707 && bytemode != d_scalar_mode
16708 && bytemode != d_scalar_swap_mode
16709 && bytemode != q_scalar_mode
16710 && bytemode != q_scalar_swap_mode
16711 && bytemode != vex_scalar_w_dq_mode)
16713 switch (vex.length)
16728 else if (bytemode == xmmq_mode
16729 || bytemode == evex_half_bcst_xmmq_mode)
16731 switch (vex.length)
16744 else if (bytemode == ymm_mode)
16748 oappend (names[reg]);
16752 OP_MS (int bytemode, int sizeflag)
16754 if (modrm.mod == 3)
16755 OP_EM (bytemode, sizeflag);
16761 OP_XS (int bytemode, int sizeflag)
16763 if (modrm.mod == 3)
16764 OP_EX (bytemode, sizeflag);
16770 OP_M (int bytemode, int sizeflag)
16772 if (modrm.mod == 3)
16773 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16776 OP_E (bytemode, sizeflag);
16780 OP_0f07 (int bytemode, int sizeflag)
16782 if (modrm.mod != 3 || modrm.rm != 0)
16785 OP_E (bytemode, sizeflag);
16788 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16789 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16792 NOP_Fixup1 (int bytemode, int sizeflag)
16794 if ((prefixes & PREFIX_DATA) != 0
16797 && address_mode == mode_64bit))
16798 OP_REG (bytemode, sizeflag);
16800 strcpy (obuf, "nop");
16804 NOP_Fixup2 (int bytemode, int sizeflag)
16806 if ((prefixes & PREFIX_DATA) != 0
16809 && address_mode == mode_64bit))
16810 OP_IMREG (bytemode, sizeflag);
16813 static const char *const Suffix3DNow[] = {
16814 /* 00 */ NULL, NULL, NULL, NULL,
16815 /* 04 */ NULL, NULL, NULL, NULL,
16816 /* 08 */ NULL, NULL, NULL, NULL,
16817 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
16818 /* 10 */ NULL, NULL, NULL, NULL,
16819 /* 14 */ NULL, NULL, NULL, NULL,
16820 /* 18 */ NULL, NULL, NULL, NULL,
16821 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
16822 /* 20 */ NULL, NULL, NULL, NULL,
16823 /* 24 */ NULL, NULL, NULL, NULL,
16824 /* 28 */ NULL, NULL, NULL, NULL,
16825 /* 2C */ NULL, NULL, NULL, NULL,
16826 /* 30 */ NULL, NULL, NULL, NULL,
16827 /* 34 */ NULL, NULL, NULL, NULL,
16828 /* 38 */ NULL, NULL, NULL, NULL,
16829 /* 3C */ NULL, NULL, NULL, NULL,
16830 /* 40 */ NULL, NULL, NULL, NULL,
16831 /* 44 */ NULL, NULL, NULL, NULL,
16832 /* 48 */ NULL, NULL, NULL, NULL,
16833 /* 4C */ NULL, NULL, NULL, NULL,
16834 /* 50 */ NULL, NULL, NULL, NULL,
16835 /* 54 */ NULL, NULL, NULL, NULL,
16836 /* 58 */ NULL, NULL, NULL, NULL,
16837 /* 5C */ NULL, NULL, NULL, NULL,
16838 /* 60 */ NULL, NULL, NULL, NULL,
16839 /* 64 */ NULL, NULL, NULL, NULL,
16840 /* 68 */ NULL, NULL, NULL, NULL,
16841 /* 6C */ NULL, NULL, NULL, NULL,
16842 /* 70 */ NULL, NULL, NULL, NULL,
16843 /* 74 */ NULL, NULL, NULL, NULL,
16844 /* 78 */ NULL, NULL, NULL, NULL,
16845 /* 7C */ NULL, NULL, NULL, NULL,
16846 /* 80 */ NULL, NULL, NULL, NULL,
16847 /* 84 */ NULL, NULL, NULL, NULL,
16848 /* 88 */ NULL, NULL, "pfnacc", NULL,
16849 /* 8C */ NULL, NULL, "pfpnacc", NULL,
16850 /* 90 */ "pfcmpge", NULL, NULL, NULL,
16851 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
16852 /* 98 */ NULL, NULL, "pfsub", NULL,
16853 /* 9C */ NULL, NULL, "pfadd", NULL,
16854 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
16855 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
16856 /* A8 */ NULL, NULL, "pfsubr", NULL,
16857 /* AC */ NULL, NULL, "pfacc", NULL,
16858 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
16859 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
16860 /* B8 */ NULL, NULL, NULL, "pswapd",
16861 /* BC */ NULL, NULL, NULL, "pavgusb",
16862 /* C0 */ NULL, NULL, NULL, NULL,
16863 /* C4 */ NULL, NULL, NULL, NULL,
16864 /* C8 */ NULL, NULL, NULL, NULL,
16865 /* CC */ NULL, NULL, NULL, NULL,
16866 /* D0 */ NULL, NULL, NULL, NULL,
16867 /* D4 */ NULL, NULL, NULL, NULL,
16868 /* D8 */ NULL, NULL, NULL, NULL,
16869 /* DC */ NULL, NULL, NULL, NULL,
16870 /* E0 */ NULL, NULL, NULL, NULL,
16871 /* E4 */ NULL, NULL, NULL, NULL,
16872 /* E8 */ NULL, NULL, NULL, NULL,
16873 /* EC */ NULL, NULL, NULL, NULL,
16874 /* F0 */ NULL, NULL, NULL, NULL,
16875 /* F4 */ NULL, NULL, NULL, NULL,
16876 /* F8 */ NULL, NULL, NULL, NULL,
16877 /* FC */ NULL, NULL, NULL, NULL,
16881 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16883 const char *mnemonic;
16885 FETCH_DATA (the_info, codep + 1);
16886 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16887 place where an 8-bit immediate would normally go. ie. the last
16888 byte of the instruction. */
16889 obufp = mnemonicendp;
16890 mnemonic = Suffix3DNow[*codep++ & 0xff];
16892 oappend (mnemonic);
16895 /* Since a variable sized modrm/sib chunk is between the start
16896 of the opcode (0x0f0f) and the opcode suffix, we need to do
16897 all the modrm processing first, and don't know until now that
16898 we have a bad opcode. This necessitates some cleaning up. */
16899 op_out[0][0] = '\0';
16900 op_out[1][0] = '\0';
16903 mnemonicendp = obufp;
16906 static struct op simd_cmp_op[] =
16908 { STRING_COMMA_LEN ("eq") },
16909 { STRING_COMMA_LEN ("lt") },
16910 { STRING_COMMA_LEN ("le") },
16911 { STRING_COMMA_LEN ("unord") },
16912 { STRING_COMMA_LEN ("neq") },
16913 { STRING_COMMA_LEN ("nlt") },
16914 { STRING_COMMA_LEN ("nle") },
16915 { STRING_COMMA_LEN ("ord") }
16919 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16921 unsigned int cmp_type;
16923 FETCH_DATA (the_info, codep + 1);
16924 cmp_type = *codep++ & 0xff;
16925 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16928 char *p = mnemonicendp - 2;
16932 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16933 mnemonicendp += simd_cmp_op[cmp_type].len;
16937 /* We have a reserved extension byte. Output it directly. */
16938 scratchbuf[0] = '$';
16939 print_operand_value (scratchbuf + 1, 1, cmp_type);
16940 oappend_maybe_intel (scratchbuf);
16941 scratchbuf[0] = '\0';
16946 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16947 int sizeflag ATTRIBUTE_UNUSED)
16949 /* mwaitx %eax,%ecx,%ebx */
16952 const char **names = (address_mode == mode_64bit
16953 ? names64 : names32);
16954 strcpy (op_out[0], names[0]);
16955 strcpy (op_out[1], names[1]);
16956 strcpy (op_out[2], names[3]);
16957 two_source_ops = 1;
16959 /* Skip mod/rm byte. */
16965 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16966 int sizeflag ATTRIBUTE_UNUSED)
16968 /* mwait %eax,%ecx */
16971 const char **names = (address_mode == mode_64bit
16972 ? names64 : names32);
16973 strcpy (op_out[0], names[0]);
16974 strcpy (op_out[1], names[1]);
16975 two_source_ops = 1;
16977 /* Skip mod/rm byte. */
16983 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16984 int sizeflag ATTRIBUTE_UNUSED)
16986 /* monitor %eax,%ecx,%edx" */
16989 const char **op1_names;
16990 const char **names = (address_mode == mode_64bit
16991 ? names64 : names32);
16993 if (!(prefixes & PREFIX_ADDR))
16994 op1_names = (address_mode == mode_16bit
16995 ? names16 : names);
16998 /* Remove "addr16/addr32". */
16999 all_prefixes[last_addr_prefix] = 0;
17000 op1_names = (address_mode != mode_32bit
17001 ? names32 : names16);
17002 used_prefixes |= PREFIX_ADDR;
17004 strcpy (op_out[0], op1_names[0]);
17005 strcpy (op_out[1], names[1]);
17006 strcpy (op_out[2], names[2]);
17007 two_source_ops = 1;
17009 /* Skip mod/rm byte. */
17017 /* Throw away prefixes and 1st. opcode byte. */
17018 codep = insn_codep + 1;
17023 REP_Fixup (int bytemode, int sizeflag)
17025 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
17027 if (prefixes & PREFIX_REPZ)
17028 all_prefixes[last_repz_prefix] = REP_PREFIX;
17035 OP_IMREG (bytemode, sizeflag);
17038 OP_ESreg (bytemode, sizeflag);
17041 OP_DSreg (bytemode, sizeflag);
17049 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
17053 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17055 if (prefixes & PREFIX_REPNZ)
17056 all_prefixes[last_repnz_prefix] = BND_PREFIX;
17059 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
17060 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
17064 HLE_Fixup1 (int bytemode, int sizeflag)
17067 && (prefixes & PREFIX_LOCK) != 0)
17069 if (prefixes & PREFIX_REPZ)
17070 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17071 if (prefixes & PREFIX_REPNZ)
17072 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17075 OP_E (bytemode, sizeflag);
17078 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
17079 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
17083 HLE_Fixup2 (int bytemode, int sizeflag)
17085 if (modrm.mod != 3)
17087 if (prefixes & PREFIX_REPZ)
17088 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17089 if (prefixes & PREFIX_REPNZ)
17090 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17093 OP_E (bytemode, sizeflag);
17096 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
17097 "xrelease" for memory operand. No check for LOCK prefix. */
17100 HLE_Fixup3 (int bytemode, int sizeflag)
17103 && last_repz_prefix > last_repnz_prefix
17104 && (prefixes & PREFIX_REPZ) != 0)
17105 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17107 OP_E (bytemode, sizeflag);
17111 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
17116 /* Change cmpxchg8b to cmpxchg16b. */
17117 char *p = mnemonicendp - 2;
17118 mnemonicendp = stpcpy (p, "16b");
17121 else if ((prefixes & PREFIX_LOCK) != 0)
17123 if (prefixes & PREFIX_REPZ)
17124 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17125 if (prefixes & PREFIX_REPNZ)
17126 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17129 OP_M (bytemode, sizeflag);
17133 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
17135 const char **names;
17139 switch (vex.length)
17153 oappend (names[reg]);
17157 CRC32_Fixup (int bytemode, int sizeflag)
17159 /* Add proper suffix to "crc32". */
17160 char *p = mnemonicendp;
17179 if (sizeflag & DFLAG)
17183 used_prefixes |= (prefixes & PREFIX_DATA);
17187 oappend (INTERNAL_DISASSEMBLER_ERROR);
17194 if (modrm.mod == 3)
17198 /* Skip mod/rm byte. */
17203 add = (rex & REX_B) ? 8 : 0;
17204 if (bytemode == b_mode)
17208 oappend (names8rex[modrm.rm + add]);
17210 oappend (names8[modrm.rm + add]);
17216 oappend (names64[modrm.rm + add]);
17217 else if ((prefixes & PREFIX_DATA))
17218 oappend (names16[modrm.rm + add]);
17220 oappend (names32[modrm.rm + add]);
17224 OP_E (bytemode, sizeflag);
17228 FXSAVE_Fixup (int bytemode, int sizeflag)
17230 /* Add proper suffix to "fxsave" and "fxrstor". */
17234 char *p = mnemonicendp;
17240 OP_M (bytemode, sizeflag);
17243 /* Display the destination register operand for instructions with
17247 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17250 const char **names;
17258 reg = vex.register_specifier;
17265 if (bytemode == vex_scalar_mode)
17267 oappend (names_xmm[reg]);
17271 switch (vex.length)
17278 case vex_vsib_q_w_dq_mode:
17279 case vex_vsib_q_w_d_mode:
17295 names = names_mask;
17309 case vex_vsib_q_w_dq_mode:
17310 case vex_vsib_q_w_d_mode:
17311 names = vex.w ? names_ymm : names_xmm;
17320 names = names_mask;
17334 oappend (names[reg]);
17337 /* Get the VEX immediate byte without moving codep. */
17339 static unsigned char
17340 get_vex_imm8 (int sizeflag, int opnum)
17342 int bytes_before_imm = 0;
17344 if (modrm.mod != 3)
17346 /* There are SIB/displacement bytes. */
17347 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17349 /* 32/64 bit address mode */
17350 int base = modrm.rm;
17352 /* Check SIB byte. */
17355 FETCH_DATA (the_info, codep + 1);
17357 /* When decoding the third source, don't increase
17358 bytes_before_imm as this has already been incremented
17359 by one in OP_E_memory while decoding the second
17362 bytes_before_imm++;
17365 /* Don't increase bytes_before_imm when decoding the third source,
17366 it has already been incremented by OP_E_memory while decoding
17367 the second source operand. */
17373 /* When modrm.rm == 5 or modrm.rm == 4 and base in
17374 SIB == 5, there is a 4 byte displacement. */
17376 /* No displacement. */
17378 /* Fall through. */
17380 /* 4 byte displacement. */
17381 bytes_before_imm += 4;
17384 /* 1 byte displacement. */
17385 bytes_before_imm++;
17392 /* 16 bit address mode */
17393 /* Don't increase bytes_before_imm when decoding the third source,
17394 it has already been incremented by OP_E_memory while decoding
17395 the second source operand. */
17401 /* When modrm.rm == 6, there is a 2 byte displacement. */
17403 /* No displacement. */
17405 /* Fall through. */
17407 /* 2 byte displacement. */
17408 bytes_before_imm += 2;
17411 /* 1 byte displacement: when decoding the third source,
17412 don't increase bytes_before_imm as this has already
17413 been incremented by one in OP_E_memory while decoding
17414 the second source operand. */
17416 bytes_before_imm++;
17424 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17425 return codep [bytes_before_imm];
17429 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17431 const char **names;
17433 if (reg == -1 && modrm.mod != 3)
17435 OP_E_memory (bytemode, sizeflag);
17447 else if (reg > 7 && address_mode != mode_64bit)
17451 switch (vex.length)
17462 oappend (names[reg]);
17466 OP_EX_VexImmW (int bytemode, int sizeflag)
17469 static unsigned char vex_imm8;
17471 if (vex_w_done == 0)
17475 /* Skip mod/rm byte. */
17479 vex_imm8 = get_vex_imm8 (sizeflag, 0);
17482 reg = vex_imm8 >> 4;
17484 OP_EX_VexReg (bytemode, sizeflag, reg);
17486 else if (vex_w_done == 1)
17491 reg = vex_imm8 >> 4;
17493 OP_EX_VexReg (bytemode, sizeflag, reg);
17497 /* Output the imm8 directly. */
17498 scratchbuf[0] = '$';
17499 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17500 oappend_maybe_intel (scratchbuf);
17501 scratchbuf[0] = '\0';
17507 OP_Vex_2src (int bytemode, int sizeflag)
17509 if (modrm.mod == 3)
17511 int reg = modrm.rm;
17515 oappend (names_xmm[reg]);
17520 && (bytemode == v_mode || bytemode == v_swap_mode))
17522 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17523 used_prefixes |= (prefixes & PREFIX_DATA);
17525 OP_E (bytemode, sizeflag);
17530 OP_Vex_2src_1 (int bytemode, int sizeflag)
17532 if (modrm.mod == 3)
17534 /* Skip mod/rm byte. */
17540 oappend (names_xmm[vex.register_specifier]);
17542 OP_Vex_2src (bytemode, sizeflag);
17546 OP_Vex_2src_2 (int bytemode, int sizeflag)
17549 OP_Vex_2src (bytemode, sizeflag);
17551 oappend (names_xmm[vex.register_specifier]);
17555 OP_EX_VexW (int bytemode, int sizeflag)
17563 /* Skip mod/rm byte. */
17568 reg = get_vex_imm8 (sizeflag, 0) >> 4;
17573 reg = get_vex_imm8 (sizeflag, 1) >> 4;
17576 OP_EX_VexReg (bytemode, sizeflag, reg);
17580 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17581 int sizeflag ATTRIBUTE_UNUSED)
17583 /* Skip the immediate byte and check for invalid bits. */
17584 FETCH_DATA (the_info, codep + 1);
17585 if (*codep++ & 0xf)
17590 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17593 const char **names;
17595 FETCH_DATA (the_info, codep + 1);
17598 if (bytemode != x_mode)
17605 if (reg > 7 && address_mode != mode_64bit)
17608 switch (vex.length)
17619 oappend (names[reg]);
17623 OP_XMM_VexW (int bytemode, int sizeflag)
17625 /* Turn off the REX.W bit since it is used for swapping operands
17628 OP_XMM (bytemode, sizeflag);
17632 OP_EX_Vex (int bytemode, int sizeflag)
17634 if (modrm.mod != 3)
17636 if (vex.register_specifier != 0)
17640 OP_EX (bytemode, sizeflag);
17644 OP_XMM_Vex (int bytemode, int sizeflag)
17646 if (modrm.mod != 3)
17648 if (vex.register_specifier != 0)
17652 OP_XMM (bytemode, sizeflag);
17656 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17658 switch (vex.length)
17661 mnemonicendp = stpcpy (obuf, "vzeroupper");
17664 mnemonicendp = stpcpy (obuf, "vzeroall");
17671 static struct op vex_cmp_op[] =
17673 { STRING_COMMA_LEN ("eq") },
17674 { STRING_COMMA_LEN ("lt") },
17675 { STRING_COMMA_LEN ("le") },
17676 { STRING_COMMA_LEN ("unord") },
17677 { STRING_COMMA_LEN ("neq") },
17678 { STRING_COMMA_LEN ("nlt") },
17679 { STRING_COMMA_LEN ("nle") },
17680 { STRING_COMMA_LEN ("ord") },
17681 { STRING_COMMA_LEN ("eq_uq") },
17682 { STRING_COMMA_LEN ("nge") },
17683 { STRING_COMMA_LEN ("ngt") },
17684 { STRING_COMMA_LEN ("false") },
17685 { STRING_COMMA_LEN ("neq_oq") },
17686 { STRING_COMMA_LEN ("ge") },
17687 { STRING_COMMA_LEN ("gt") },
17688 { STRING_COMMA_LEN ("true") },
17689 { STRING_COMMA_LEN ("eq_os") },
17690 { STRING_COMMA_LEN ("lt_oq") },
17691 { STRING_COMMA_LEN ("le_oq") },
17692 { STRING_COMMA_LEN ("unord_s") },
17693 { STRING_COMMA_LEN ("neq_us") },
17694 { STRING_COMMA_LEN ("nlt_uq") },
17695 { STRING_COMMA_LEN ("nle_uq") },
17696 { STRING_COMMA_LEN ("ord_s") },
17697 { STRING_COMMA_LEN ("eq_us") },
17698 { STRING_COMMA_LEN ("nge_uq") },
17699 { STRING_COMMA_LEN ("ngt_uq") },
17700 { STRING_COMMA_LEN ("false_os") },
17701 { STRING_COMMA_LEN ("neq_os") },
17702 { STRING_COMMA_LEN ("ge_oq") },
17703 { STRING_COMMA_LEN ("gt_oq") },
17704 { STRING_COMMA_LEN ("true_us") },
17708 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17710 unsigned int cmp_type;
17712 FETCH_DATA (the_info, codep + 1);
17713 cmp_type = *codep++ & 0xff;
17714 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17717 char *p = mnemonicendp - 2;
17721 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17722 mnemonicendp += vex_cmp_op[cmp_type].len;
17726 /* We have a reserved extension byte. Output it directly. */
17727 scratchbuf[0] = '$';
17728 print_operand_value (scratchbuf + 1, 1, cmp_type);
17729 oappend_maybe_intel (scratchbuf);
17730 scratchbuf[0] = '\0';
17735 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17736 int sizeflag ATTRIBUTE_UNUSED)
17738 unsigned int cmp_type;
17743 FETCH_DATA (the_info, codep + 1);
17744 cmp_type = *codep++ & 0xff;
17745 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17746 If it's the case, print suffix, otherwise - print the immediate. */
17747 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17752 char *p = mnemonicendp - 2;
17754 /* vpcmp* can have both one- and two-lettered suffix. */
17768 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17769 mnemonicendp += simd_cmp_op[cmp_type].len;
17773 /* We have a reserved extension byte. Output it directly. */
17774 scratchbuf[0] = '$';
17775 print_operand_value (scratchbuf + 1, 1, cmp_type);
17776 oappend_maybe_intel (scratchbuf);
17777 scratchbuf[0] = '\0';
17781 static const struct op pclmul_op[] =
17783 { STRING_COMMA_LEN ("lql") },
17784 { STRING_COMMA_LEN ("hql") },
17785 { STRING_COMMA_LEN ("lqh") },
17786 { STRING_COMMA_LEN ("hqh") }
17790 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17791 int sizeflag ATTRIBUTE_UNUSED)
17793 unsigned int pclmul_type;
17795 FETCH_DATA (the_info, codep + 1);
17796 pclmul_type = *codep++ & 0xff;
17797 switch (pclmul_type)
17808 if (pclmul_type < ARRAY_SIZE (pclmul_op))
17811 char *p = mnemonicendp - 3;
17816 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17817 mnemonicendp += pclmul_op[pclmul_type].len;
17821 /* We have a reserved extension byte. Output it directly. */
17822 scratchbuf[0] = '$';
17823 print_operand_value (scratchbuf + 1, 1, pclmul_type);
17824 oappend_maybe_intel (scratchbuf);
17825 scratchbuf[0] = '\0';
17830 MOVBE_Fixup (int bytemode, int sizeflag)
17832 /* Add proper suffix to "movbe". */
17833 char *p = mnemonicendp;
17842 if (sizeflag & SUFFIX_ALWAYS)
17848 if (sizeflag & DFLAG)
17852 used_prefixes |= (prefixes & PREFIX_DATA);
17857 oappend (INTERNAL_DISASSEMBLER_ERROR);
17864 OP_M (bytemode, sizeflag);
17868 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17871 const char **names;
17873 /* Skip mod/rm byte. */
17887 oappend (names[reg]);
17891 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17893 const char **names;
17900 oappend (names[vex.register_specifier]);
17904 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17907 || (bytemode != mask_mode && bytemode != mask_bd_mode))
17911 if ((rex & REX_R) != 0 || !vex.r)
17917 oappend (names_mask [modrm.reg]);
17921 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17924 || (bytemode != evex_rounding_mode
17925 && bytemode != evex_sae_mode))
17927 if (modrm.mod == 3 && vex.b)
17930 case evex_rounding_mode:
17931 oappend (names_rounding[vex.ll]);
17933 case evex_sae_mode: