1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2018 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma, disassemble_info *);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma get64 (void);
58 static bfd_signed_vma get32 (void);
59 static bfd_signed_vma get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VCMP_Fixup (int, int);
99 static void VPCMP_Fixup (int, int);
100 static void VPCOM_Fixup (int, int);
101 static void OP_0f07 (int, int);
102 static void OP_Monitor (int, int);
103 static void OP_Mwait (int, int);
104 static void OP_Mwaitx (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void NOTRACK_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void PCMPESTR_Fixup (int, int);
121 static void OP_LWPCB_E (int, int);
122 static void OP_LWP_E (int, int);
123 static void OP_Vex_2src_1 (int, int);
124 static void OP_Vex_2src_2 (int, int);
126 static void MOVBE_Fixup (int, int);
128 static void OP_Mask (int, int);
131 /* Points to first byte not fetched. */
132 bfd_byte *max_fetched;
133 bfd_byte the_buffer[MAX_MNEM_SIZE];
136 OPCODES_SIGJMP_BUF bailout;
146 enum address_mode address_mode;
148 /* Flags for the prefixes for the current instruction. See below. */
151 /* REX prefix the current instruction. See below. */
153 /* Bits of REX we've already used. */
155 /* REX bits in original REX prefix ignored. */
156 static int rex_ignored;
157 /* Mark parts used in the REX prefix. When we are testing for
158 empty prefix (for 8bit register REX extension), just mask it
159 out. Otherwise test for REX bit is excuse for existence of REX
160 only in case value is nonzero. */
161 #define USED_REX(value) \
166 rex_used |= (value) | REX_OPCODE; \
169 rex_used |= REX_OPCODE; \
172 /* Flags for prefixes which we somehow handled when printing the
173 current instruction. */
174 static int used_prefixes;
176 /* Flags stored in PREFIXES. */
177 #define PREFIX_REPZ 1
178 #define PREFIX_REPNZ 2
179 #define PREFIX_LOCK 4
181 #define PREFIX_SS 0x10
182 #define PREFIX_DS 0x20
183 #define PREFIX_ES 0x40
184 #define PREFIX_FS 0x80
185 #define PREFIX_GS 0x100
186 #define PREFIX_DATA 0x200
187 #define PREFIX_ADDR 0x400
188 #define PREFIX_FWAIT 0x800
190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
191 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
193 #define FETCH_DATA(info, addr) \
194 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
195 ? 1 : fetch_data ((info), (addr)))
198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
201 struct dis_private *priv = (struct dis_private *) info->private_data;
202 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
204 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
205 status = (*info->read_memory_func) (start,
207 addr - priv->max_fetched,
213 /* If we did manage to read at least one byte, then
214 print_insn_i386 will do something sensible. Otherwise, print
215 an error. We do that here because this is where we know
217 if (priv->max_fetched == priv->the_buffer)
218 (*info->memory_error_func) (status, start, info);
219 OPCODES_SIGLONGJMP (priv->bailout, 1);
222 priv->max_fetched = addr;
226 /* Possible values for prefix requirement. */
227 #define PREFIX_IGNORED_SHIFT 16
228 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
234 /* Opcode prefixes. */
235 #define PREFIX_OPCODE (PREFIX_REPZ \
239 /* Prefixes ignored. */
240 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
241 | PREFIX_IGNORED_REPNZ \
242 | PREFIX_IGNORED_DATA)
244 #define XX { NULL, 0 }
245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
247 #define Eb { OP_E, b_mode }
248 #define Ebnd { OP_E, bnd_mode }
249 #define EbS { OP_E, b_swap_mode }
250 #define EbndS { OP_E, bnd_swap_mode }
251 #define Ev { OP_E, v_mode }
252 #define Eva { OP_E, va_mode }
253 #define Ev_bnd { OP_E, v_bnd_mode }
254 #define EvS { OP_E, v_swap_mode }
255 #define Ed { OP_E, d_mode }
256 #define Edq { OP_E, dq_mode }
257 #define Edqw { OP_E, dqw_mode }
258 #define Edqb { OP_E, dqb_mode }
259 #define Edb { OP_E, db_mode }
260 #define Edw { OP_E, dw_mode }
261 #define Edqd { OP_E, dqd_mode }
262 #define Edqa { OP_E, dqa_mode }
263 #define Eq { OP_E, q_mode }
264 #define indirEv { OP_indirE, indir_v_mode }
265 #define indirEp { OP_indirE, f_mode }
266 #define stackEv { OP_E, stack_v_mode }
267 #define Em { OP_E, m_mode }
268 #define Ew { OP_E, w_mode }
269 #define M { OP_M, 0 } /* lea, lgdt, etc. */
270 #define Ma { OP_M, a_mode }
271 #define Mb { OP_M, b_mode }
272 #define Md { OP_M, d_mode }
273 #define Mo { OP_M, o_mode }
274 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
275 #define Mq { OP_M, q_mode }
276 #define Mv_bnd { OP_M, v_bndmk_mode }
277 #define Mx { OP_M, x_mode }
278 #define Mxmm { OP_M, xmm_mode }
279 #define Gb { OP_G, b_mode }
280 #define Gbnd { OP_G, bnd_mode }
281 #define Gv { OP_G, v_mode }
282 #define Gd { OP_G, d_mode }
283 #define Gdq { OP_G, dq_mode }
284 #define Gm { OP_G, m_mode }
285 #define Gva { OP_G, va_mode }
286 #define Gw { OP_G, w_mode }
287 #define Rd { OP_R, d_mode }
288 #define Rdq { OP_R, dq_mode }
289 #define Rm { OP_R, m_mode }
290 #define Ib { OP_I, b_mode }
291 #define sIb { OP_sI, b_mode } /* sign extened byte */
292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
293 #define Iv { OP_I, v_mode }
294 #define sIv { OP_sI, v_mode }
295 #define Iq { OP_I, q_mode }
296 #define Iv64 { OP_I64, v_mode }
297 #define Iw { OP_I, w_mode }
298 #define I1 { OP_I, const_1_mode }
299 #define Jb { OP_J, b_mode }
300 #define Jv { OP_J, v_mode }
301 #define Cm { OP_C, m_mode }
302 #define Dm { OP_D, m_mode }
303 #define Td { OP_T, d_mode }
304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
306 #define RMeAX { OP_REG, eAX_reg }
307 #define RMeBX { OP_REG, eBX_reg }
308 #define RMeCX { OP_REG, eCX_reg }
309 #define RMeDX { OP_REG, eDX_reg }
310 #define RMeSP { OP_REG, eSP_reg }
311 #define RMeBP { OP_REG, eBP_reg }
312 #define RMeSI { OP_REG, eSI_reg }
313 #define RMeDI { OP_REG, eDI_reg }
314 #define RMrAX { OP_REG, rAX_reg }
315 #define RMrBX { OP_REG, rBX_reg }
316 #define RMrCX { OP_REG, rCX_reg }
317 #define RMrDX { OP_REG, rDX_reg }
318 #define RMrSP { OP_REG, rSP_reg }
319 #define RMrBP { OP_REG, rBP_reg }
320 #define RMrSI { OP_REG, rSI_reg }
321 #define RMrDI { OP_REG, rDI_reg }
322 #define RMAL { OP_REG, al_reg }
323 #define RMCL { OP_REG, cl_reg }
324 #define RMDL { OP_REG, dl_reg }
325 #define RMBL { OP_REG, bl_reg }
326 #define RMAH { OP_REG, ah_reg }
327 #define RMCH { OP_REG, ch_reg }
328 #define RMDH { OP_REG, dh_reg }
329 #define RMBH { OP_REG, bh_reg }
330 #define RMAX { OP_REG, ax_reg }
331 #define RMDX { OP_REG, dx_reg }
333 #define eAX { OP_IMREG, eAX_reg }
334 #define eBX { OP_IMREG, eBX_reg }
335 #define eCX { OP_IMREG, eCX_reg }
336 #define eDX { OP_IMREG, eDX_reg }
337 #define eSP { OP_IMREG, eSP_reg }
338 #define eBP { OP_IMREG, eBP_reg }
339 #define eSI { OP_IMREG, eSI_reg }
340 #define eDI { OP_IMREG, eDI_reg }
341 #define AL { OP_IMREG, al_reg }
342 #define CL { OP_IMREG, cl_reg }
343 #define DL { OP_IMREG, dl_reg }
344 #define BL { OP_IMREG, bl_reg }
345 #define AH { OP_IMREG, ah_reg }
346 #define CH { OP_IMREG, ch_reg }
347 #define DH { OP_IMREG, dh_reg }
348 #define BH { OP_IMREG, bh_reg }
349 #define AX { OP_IMREG, ax_reg }
350 #define DX { OP_IMREG, dx_reg }
351 #define zAX { OP_IMREG, z_mode_ax_reg }
352 #define indirDX { OP_IMREG, indir_dx_reg }
354 #define Sw { OP_SEG, w_mode }
355 #define Sv { OP_SEG, v_mode }
356 #define Ap { OP_DIR, 0 }
357 #define Ob { OP_OFF64, b_mode }
358 #define Ov { OP_OFF64, v_mode }
359 #define Xb { OP_DSreg, eSI_reg }
360 #define Xv { OP_DSreg, eSI_reg }
361 #define Xz { OP_DSreg, eSI_reg }
362 #define Yb { OP_ESreg, eDI_reg }
363 #define Yv { OP_ESreg, eDI_reg }
364 #define DSBX { OP_DSreg, eBX_reg }
366 #define es { OP_REG, es_reg }
367 #define ss { OP_REG, ss_reg }
368 #define cs { OP_REG, cs_reg }
369 #define ds { OP_REG, ds_reg }
370 #define fs { OP_REG, fs_reg }
371 #define gs { OP_REG, gs_reg }
373 #define MX { OP_MMX, 0 }
374 #define XM { OP_XMM, 0 }
375 #define XMScalar { OP_XMM, scalar_mode }
376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
377 #define XMM { OP_XMM, xmm_mode }
378 #define XMxmmq { OP_XMM, xmmq_mode }
379 #define EM { OP_EM, v_mode }
380 #define EMS { OP_EM, v_swap_mode }
381 #define EMd { OP_EM, d_mode }
382 #define EMx { OP_EM, x_mode }
383 #define EXbScalar { OP_EX, b_scalar_mode }
384 #define EXw { OP_EX, w_mode }
385 #define EXwScalar { OP_EX, w_scalar_mode }
386 #define EXd { OP_EX, d_mode }
387 #define EXdScalar { OP_EX, d_scalar_mode }
388 #define EXdS { OP_EX, d_swap_mode }
389 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
390 #define EXq { OP_EX, q_mode }
391 #define EXqScalar { OP_EX, q_scalar_mode }
392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
393 #define EXqS { OP_EX, q_swap_mode }
394 #define EXx { OP_EX, x_mode }
395 #define EXxS { OP_EX, x_swap_mode }
396 #define EXxmm { OP_EX, xmm_mode }
397 #define EXymm { OP_EX, ymm_mode }
398 #define EXxmmq { OP_EX, xmmq_mode }
399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
402 #define EXxmm_md { OP_EX, xmm_md_mode }
403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
404 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
405 #define EXxmmdw { OP_EX, xmmdw_mode }
406 #define EXxmmqd { OP_EX, xmmqd_mode }
407 #define EXymmq { OP_EX, ymmq_mode }
408 #define EXVexWdq { OP_EX, vex_w_dq_mode }
409 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
410 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
411 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
412 #define MS { OP_MS, v_mode }
413 #define XS { OP_XS, v_mode }
414 #define EMCq { OP_EMC, q_mode }
415 #define MXC { OP_MXC, 0 }
416 #define OPSUF { OP_3DNowSuffix, 0 }
417 #define CMP { CMP_Fixup, 0 }
418 #define XMM0 { XMM_Fixup, 0 }
419 #define FXSAVE { FXSAVE_Fixup, 0 }
420 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
421 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
423 #define Vex { OP_VEX, vex_mode }
424 #define VexScalar { OP_VEX, vex_scalar_mode }
425 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
426 #define Vex128 { OP_VEX, vex128_mode }
427 #define Vex256 { OP_VEX, vex256_mode }
428 #define VexGdq { OP_VEX, dq_mode }
429 #define EXdVex { OP_EX_Vex, d_mode }
430 #define EXdVexS { OP_EX_Vex, d_swap_mode }
431 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
432 #define EXqVex { OP_EX_Vex, q_mode }
433 #define EXqVexS { OP_EX_Vex, q_swap_mode }
434 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
435 #define EXVexW { OP_EX_VexW, x_mode }
436 #define EXdVexW { OP_EX_VexW, d_mode }
437 #define EXqVexW { OP_EX_VexW, q_mode }
438 #define EXVexImmW { OP_EX_VexImmW, x_mode }
439 #define XMVex { OP_XMM_Vex, 0 }
440 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
441 #define XMVexW { OP_XMM_VexW, 0 }
442 #define XMVexI4 { OP_REG_VexI4, x_mode }
443 #define PCLMUL { PCLMUL_Fixup, 0 }
444 #define VCMP { VCMP_Fixup, 0 }
445 #define VPCMP { VPCMP_Fixup, 0 }
446 #define VPCOM { VPCOM_Fixup, 0 }
448 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
449 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
450 #define EXxEVexS { OP_Rounding, evex_sae_mode }
452 #define XMask { OP_Mask, mask_mode }
453 #define MaskG { OP_G, mask_mode }
454 #define MaskE { OP_E, mask_mode }
455 #define MaskBDE { OP_E, mask_bd_mode }
456 #define MaskR { OP_R, mask_mode }
457 #define MaskVex { OP_VEX, mask_mode }
459 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
460 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
461 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
462 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
464 /* Used handle "rep" prefix for string instructions. */
465 #define Xbr { REP_Fixup, eSI_reg }
466 #define Xvr { REP_Fixup, eSI_reg }
467 #define Ybr { REP_Fixup, eDI_reg }
468 #define Yvr { REP_Fixup, eDI_reg }
469 #define Yzr { REP_Fixup, eDI_reg }
470 #define indirDXr { REP_Fixup, indir_dx_reg }
471 #define ALr { REP_Fixup, al_reg }
472 #define eAXr { REP_Fixup, eAX_reg }
474 /* Used handle HLE prefix for lockable instructions. */
475 #define Ebh1 { HLE_Fixup1, b_mode }
476 #define Evh1 { HLE_Fixup1, v_mode }
477 #define Ebh2 { HLE_Fixup2, b_mode }
478 #define Evh2 { HLE_Fixup2, v_mode }
479 #define Ebh3 { HLE_Fixup3, b_mode }
480 #define Evh3 { HLE_Fixup3, v_mode }
482 #define BND { BND_Fixup, 0 }
483 #define NOTRACK { NOTRACK_Fixup, 0 }
485 #define cond_jump_flag { NULL, cond_jump_mode }
486 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
488 /* bits in sizeflag */
489 #define SUFFIX_ALWAYS 4
497 /* byte operand with operand swapped */
499 /* byte operand, sign extend like 'T' suffix */
501 /* operand size depends on prefixes */
503 /* operand size depends on prefixes with operand swapped */
505 /* operand size depends on address prefix */
509 /* double word operand */
511 /* double word operand with operand swapped */
513 /* quad word operand */
515 /* quad word operand with operand swapped */
517 /* ten-byte operand */
519 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
520 broadcast enabled. */
522 /* Similar to x_mode, but with different EVEX mem shifts. */
524 /* Similar to x_mode, but with disabled broadcast. */
526 /* Similar to x_mode, but with operands swapped and disabled broadcast
529 /* 16-byte XMM operand */
531 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
532 memory operand (depending on vector length). Broadcast isn't
535 /* Same as xmmq_mode, but broadcast is allowed. */
536 evex_half_bcst_xmmq_mode,
537 /* XMM register or byte memory operand */
539 /* XMM register or word memory operand */
541 /* XMM register or double word memory operand */
543 /* XMM register or quad word memory operand */
545 /* XMM register or double/quad word memory operand, depending on
548 /* 16-byte XMM, word, double word or quad word operand. */
550 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
552 /* 32-byte YMM operand */
554 /* quad word, ymmword or zmmword memory operand. */
556 /* 32-byte YMM or 16-byte word operand */
558 /* d_mode in 32bit, q_mode in 64bit mode. */
560 /* pair of v_mode operands */
565 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
567 /* operand size depends on REX prefixes. */
569 /* registers like dq_mode, memory like w_mode. */
573 /* bounds operand with operand swapped */
575 /* 4- or 6-byte pointer operand */
578 /* v_mode for indirect branch opcodes. */
580 /* v_mode for stack-related opcodes. */
582 /* non-quad operand size depends on prefixes */
584 /* 16-byte operand */
586 /* registers like dq_mode, memory like b_mode. */
588 /* registers like d_mode, memory like b_mode. */
590 /* registers like d_mode, memory like w_mode. */
592 /* registers like dq_mode, memory like d_mode. */
594 /* operand size depends on the W bit as well as address mode. */
596 /* normal vex mode */
598 /* 128bit vex mode */
600 /* 256bit vex mode */
602 /* operand size depends on the VEX.W bit. */
605 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
606 vex_vsib_d_w_dq_mode,
607 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
609 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
610 vex_vsib_q_w_dq_mode,
611 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
614 /* scalar, ignore vector length. */
616 /* like b_mode, ignore vector length. */
618 /* like w_mode, ignore vector length. */
620 /* like d_mode, ignore vector length. */
622 /* like d_swap_mode, ignore vector length. */
624 /* like q_mode, ignore vector length. */
626 /* like q_swap_mode, ignore vector length. */
628 /* like vex_mode, ignore vector length. */
630 /* like vex_w_dq_mode, ignore vector length. */
631 vex_scalar_w_dq_mode,
633 /* Static rounding. */
635 /* Static rounding, 64-bit mode only. */
636 evex_rounding_64_mode,
637 /* Supress all exceptions. */
640 /* Mask register operand. */
642 /* Mask register operand. */
710 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
712 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
713 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
714 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
715 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
716 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
717 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
718 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
719 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
720 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
721 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
722 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
723 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
724 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
725 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
726 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
727 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
853 MOD_VEX_0F12_PREFIX_0,
855 MOD_VEX_0F16_PREFIX_0,
858 MOD_VEX_W_0_0F41_P_0_LEN_1,
859 MOD_VEX_W_1_0F41_P_0_LEN_1,
860 MOD_VEX_W_0_0F41_P_2_LEN_1,
861 MOD_VEX_W_1_0F41_P_2_LEN_1,
862 MOD_VEX_W_0_0F42_P_0_LEN_1,
863 MOD_VEX_W_1_0F42_P_0_LEN_1,
864 MOD_VEX_W_0_0F42_P_2_LEN_1,
865 MOD_VEX_W_1_0F42_P_2_LEN_1,
866 MOD_VEX_W_0_0F44_P_0_LEN_1,
867 MOD_VEX_W_1_0F44_P_0_LEN_1,
868 MOD_VEX_W_0_0F44_P_2_LEN_1,
869 MOD_VEX_W_1_0F44_P_2_LEN_1,
870 MOD_VEX_W_0_0F45_P_0_LEN_1,
871 MOD_VEX_W_1_0F45_P_0_LEN_1,
872 MOD_VEX_W_0_0F45_P_2_LEN_1,
873 MOD_VEX_W_1_0F45_P_2_LEN_1,
874 MOD_VEX_W_0_0F46_P_0_LEN_1,
875 MOD_VEX_W_1_0F46_P_0_LEN_1,
876 MOD_VEX_W_0_0F46_P_2_LEN_1,
877 MOD_VEX_W_1_0F46_P_2_LEN_1,
878 MOD_VEX_W_0_0F47_P_0_LEN_1,
879 MOD_VEX_W_1_0F47_P_0_LEN_1,
880 MOD_VEX_W_0_0F47_P_2_LEN_1,
881 MOD_VEX_W_1_0F47_P_2_LEN_1,
882 MOD_VEX_W_0_0F4A_P_0_LEN_1,
883 MOD_VEX_W_1_0F4A_P_0_LEN_1,
884 MOD_VEX_W_0_0F4A_P_2_LEN_1,
885 MOD_VEX_W_1_0F4A_P_2_LEN_1,
886 MOD_VEX_W_0_0F4B_P_0_LEN_1,
887 MOD_VEX_W_1_0F4B_P_0_LEN_1,
888 MOD_VEX_W_0_0F4B_P_2_LEN_1,
900 MOD_VEX_W_0_0F91_P_0_LEN_0,
901 MOD_VEX_W_1_0F91_P_0_LEN_0,
902 MOD_VEX_W_0_0F91_P_2_LEN_0,
903 MOD_VEX_W_1_0F91_P_2_LEN_0,
904 MOD_VEX_W_0_0F92_P_0_LEN_0,
905 MOD_VEX_W_0_0F92_P_2_LEN_0,
906 MOD_VEX_W_0_0F92_P_3_LEN_0,
907 MOD_VEX_W_1_0F92_P_3_LEN_0,
908 MOD_VEX_W_0_0F93_P_0_LEN_0,
909 MOD_VEX_W_0_0F93_P_2_LEN_0,
910 MOD_VEX_W_0_0F93_P_3_LEN_0,
911 MOD_VEX_W_1_0F93_P_3_LEN_0,
912 MOD_VEX_W_0_0F98_P_0_LEN_0,
913 MOD_VEX_W_1_0F98_P_0_LEN_0,
914 MOD_VEX_W_0_0F98_P_2_LEN_0,
915 MOD_VEX_W_1_0F98_P_2_LEN_0,
916 MOD_VEX_W_0_0F99_P_0_LEN_0,
917 MOD_VEX_W_1_0F99_P_0_LEN_0,
918 MOD_VEX_W_0_0F99_P_2_LEN_0,
919 MOD_VEX_W_1_0F99_P_2_LEN_0,
922 MOD_VEX_0FD7_PREFIX_2,
923 MOD_VEX_0FE7_PREFIX_2,
924 MOD_VEX_0FF0_PREFIX_3,
925 MOD_VEX_0F381A_PREFIX_2,
926 MOD_VEX_0F382A_PREFIX_2,
927 MOD_VEX_0F382C_PREFIX_2,
928 MOD_VEX_0F382D_PREFIX_2,
929 MOD_VEX_0F382E_PREFIX_2,
930 MOD_VEX_0F382F_PREFIX_2,
931 MOD_VEX_0F385A_PREFIX_2,
932 MOD_VEX_0F388C_PREFIX_2,
933 MOD_VEX_0F388E_PREFIX_2,
934 MOD_VEX_W_0_0F3A30_P_2_LEN_0,
935 MOD_VEX_W_1_0F3A30_P_2_LEN_0,
936 MOD_VEX_W_0_0F3A31_P_2_LEN_0,
937 MOD_VEX_W_1_0F3A31_P_2_LEN_0,
938 MOD_VEX_W_0_0F3A32_P_2_LEN_0,
939 MOD_VEX_W_1_0F3A32_P_2_LEN_0,
940 MOD_VEX_W_0_0F3A33_P_2_LEN_0,
941 MOD_VEX_W_1_0F3A33_P_2_LEN_0,
943 MOD_EVEX_0F10_PREFIX_1,
944 MOD_EVEX_0F10_PREFIX_3,
945 MOD_EVEX_0F11_PREFIX_1,
946 MOD_EVEX_0F11_PREFIX_3,
947 MOD_EVEX_0F12_PREFIX_0,
948 MOD_EVEX_0F16_PREFIX_0,
949 MOD_EVEX_0F38C6_REG_1,
950 MOD_EVEX_0F38C6_REG_2,
951 MOD_EVEX_0F38C6_REG_5,
952 MOD_EVEX_0F38C6_REG_6,
953 MOD_EVEX_0F38C7_REG_1,
954 MOD_EVEX_0F38C7_REG_2,
955 MOD_EVEX_0F38C7_REG_5,
956 MOD_EVEX_0F38C7_REG_6
977 PREFIX_MOD_0_0F01_REG_5,
978 PREFIX_MOD_3_0F01_REG_5_RM_0,
979 PREFIX_MOD_3_0F01_REG_5_RM_2,
1025 PREFIX_MOD_0_0FAE_REG_4,
1026 PREFIX_MOD_3_0FAE_REG_4,
1027 PREFIX_MOD_0_0FAE_REG_5,
1028 PREFIX_MOD_3_0FAE_REG_5,
1029 PREFIX_MOD_0_0FAE_REG_6,
1030 PREFIX_MOD_1_0FAE_REG_6,
1037 PREFIX_MOD_0_0FC7_REG_6,
1038 PREFIX_MOD_3_0FC7_REG_6,
1039 PREFIX_MOD_3_0FC7_REG_7,
1169 PREFIX_VEX_0F71_REG_2,
1170 PREFIX_VEX_0F71_REG_4,
1171 PREFIX_VEX_0F71_REG_6,
1172 PREFIX_VEX_0F72_REG_2,
1173 PREFIX_VEX_0F72_REG_4,
1174 PREFIX_VEX_0F72_REG_6,
1175 PREFIX_VEX_0F73_REG_2,
1176 PREFIX_VEX_0F73_REG_3,
1177 PREFIX_VEX_0F73_REG_6,
1178 PREFIX_VEX_0F73_REG_7,
1351 PREFIX_VEX_0F38F3_REG_1,
1352 PREFIX_VEX_0F38F3_REG_2,
1353 PREFIX_VEX_0F38F3_REG_3,
1472 PREFIX_EVEX_0F71_REG_2,
1473 PREFIX_EVEX_0F71_REG_4,
1474 PREFIX_EVEX_0F71_REG_6,
1475 PREFIX_EVEX_0F72_REG_0,
1476 PREFIX_EVEX_0F72_REG_1,
1477 PREFIX_EVEX_0F72_REG_2,
1478 PREFIX_EVEX_0F72_REG_4,
1479 PREFIX_EVEX_0F72_REG_6,
1480 PREFIX_EVEX_0F73_REG_2,
1481 PREFIX_EVEX_0F73_REG_3,
1482 PREFIX_EVEX_0F73_REG_6,
1483 PREFIX_EVEX_0F73_REG_7,
1679 PREFIX_EVEX_0F38C6_REG_1,
1680 PREFIX_EVEX_0F38C6_REG_2,
1681 PREFIX_EVEX_0F38C6_REG_5,
1682 PREFIX_EVEX_0F38C6_REG_6,
1683 PREFIX_EVEX_0F38C7_REG_1,
1684 PREFIX_EVEX_0F38C7_REG_2,
1685 PREFIX_EVEX_0F38C7_REG_5,
1686 PREFIX_EVEX_0F38C7_REG_6,
1788 THREE_BYTE_0F38 = 0,
1815 VEX_LEN_0F12_P_0_M_0 = 0,
1816 VEX_LEN_0F12_P_0_M_1,
1819 VEX_LEN_0F16_P_0_M_0,
1820 VEX_LEN_0F16_P_0_M_1,
1863 VEX_LEN_0FAE_R_2_M_0,
1864 VEX_LEN_0FAE_R_3_M_0,
1871 VEX_LEN_0F381A_P_2_M_0,
1874 VEX_LEN_0F385A_P_2_M_0,
1877 VEX_LEN_0F38F3_R_1_P_0,
1878 VEX_LEN_0F38F3_R_2_P_0,
1879 VEX_LEN_0F38F3_R_3_P_0,
1922 VEX_LEN_0FXOP_08_CC,
1923 VEX_LEN_0FXOP_08_CD,
1924 VEX_LEN_0FXOP_08_CE,
1925 VEX_LEN_0FXOP_08_CF,
1926 VEX_LEN_0FXOP_08_EC,
1927 VEX_LEN_0FXOP_08_ED,
1928 VEX_LEN_0FXOP_08_EE,
1929 VEX_LEN_0FXOP_08_EF,
1930 VEX_LEN_0FXOP_09_80,
1936 EVEX_LEN_0F6E_P_2 = 0,
1944 VEX_W_0F41_P_0_LEN_1 = 0,
1945 VEX_W_0F41_P_2_LEN_1,
1946 VEX_W_0F42_P_0_LEN_1,
1947 VEX_W_0F42_P_2_LEN_1,
1948 VEX_W_0F44_P_0_LEN_0,
1949 VEX_W_0F44_P_2_LEN_0,
1950 VEX_W_0F45_P_0_LEN_1,
1951 VEX_W_0F45_P_2_LEN_1,
1952 VEX_W_0F46_P_0_LEN_1,
1953 VEX_W_0F46_P_2_LEN_1,
1954 VEX_W_0F47_P_0_LEN_1,
1955 VEX_W_0F47_P_2_LEN_1,
1956 VEX_W_0F4A_P_0_LEN_1,
1957 VEX_W_0F4A_P_2_LEN_1,
1958 VEX_W_0F4B_P_0_LEN_1,
1959 VEX_W_0F4B_P_2_LEN_1,
1960 VEX_W_0F90_P_0_LEN_0,
1961 VEX_W_0F90_P_2_LEN_0,
1962 VEX_W_0F91_P_0_LEN_0,
1963 VEX_W_0F91_P_2_LEN_0,
1964 VEX_W_0F92_P_0_LEN_0,
1965 VEX_W_0F92_P_2_LEN_0,
1966 VEX_W_0F92_P_3_LEN_0,
1967 VEX_W_0F93_P_0_LEN_0,
1968 VEX_W_0F93_P_2_LEN_0,
1969 VEX_W_0F93_P_3_LEN_0,
1970 VEX_W_0F98_P_0_LEN_0,
1971 VEX_W_0F98_P_2_LEN_0,
1972 VEX_W_0F99_P_0_LEN_0,
1973 VEX_W_0F99_P_2_LEN_0,
1983 VEX_W_0F381A_P_2_M_0,
1984 VEX_W_0F382C_P_2_M_0,
1985 VEX_W_0F382D_P_2_M_0,
1986 VEX_W_0F382E_P_2_M_0,
1987 VEX_W_0F382F_P_2_M_0,
1992 VEX_W_0F385A_P_2_M_0,
2007 VEX_W_0F3A30_P_2_LEN_0,
2008 VEX_W_0F3A31_P_2_LEN_0,
2009 VEX_W_0F3A32_P_2_LEN_0,
2010 VEX_W_0F3A33_P_2_LEN_0,
2023 EVEX_W_0F10_P_1_M_0,
2024 EVEX_W_0F10_P_1_M_1,
2026 EVEX_W_0F10_P_3_M_0,
2027 EVEX_W_0F10_P_3_M_1,
2029 EVEX_W_0F11_P_1_M_0,
2030 EVEX_W_0F11_P_1_M_1,
2032 EVEX_W_0F11_P_3_M_0,
2033 EVEX_W_0F11_P_3_M_1,
2034 EVEX_W_0F12_P_0_M_0,
2035 EVEX_W_0F12_P_0_M_1,
2045 EVEX_W_0F16_P_0_M_0,
2046 EVEX_W_0F16_P_0_M_1,
2117 EVEX_W_0F72_R_2_P_2,
2118 EVEX_W_0F72_R_6_P_2,
2119 EVEX_W_0F73_R_2_P_2,
2120 EVEX_W_0F73_R_6_P_2,
2228 EVEX_W_0F38C7_R_1_P_2,
2229 EVEX_W_0F38C7_R_2_P_2,
2230 EVEX_W_0F38C7_R_5_P_2,
2231 EVEX_W_0F38C7_R_6_P_2,
2272 typedef void (*op_rtn) (int bytemode, int sizeflag);
2281 unsigned int prefix_requirement;
2284 /* Upper case letters in the instruction names here are macros.
2285 'A' => print 'b' if no register operands or suffix_always is true
2286 'B' => print 'b' if suffix_always is true
2287 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2289 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2290 suffix_always is true
2291 'E' => print 'e' if 32-bit form of jcxz
2292 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2293 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2294 'H' => print ",pt" or ",pn" branch hint
2295 'I' => honor following macro letter even in Intel mode (implemented only
2296 for some of the macro letters)
2298 'K' => print 'd' or 'q' if rex prefix is present.
2299 'L' => print 'l' if suffix_always is true
2300 'M' => print 'r' if intel_mnemonic is false.
2301 'N' => print 'n' if instruction has no wait "prefix"
2302 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2303 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2304 or suffix_always is true. print 'q' if rex prefix is present.
2305 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2307 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2308 'S' => print 'w', 'l' or 'q' if suffix_always is true
2309 'T' => print 'q' in 64bit mode if instruction has no operand size
2310 prefix and behave as 'P' otherwise
2311 'U' => print 'q' in 64bit mode if instruction has no operand size
2312 prefix and behave as 'Q' otherwise
2313 'V' => print 'q' in 64bit mode if instruction has no operand size
2314 prefix and behave as 'S' otherwise
2315 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2316 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2318 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2319 '!' => change condition from true to false or from false to true.
2320 '%' => add 1 upper case letter to the macro.
2321 '^' => print 'w' or 'l' depending on operand size prefix or
2322 suffix_always is true (lcall/ljmp).
2323 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2324 on operand size prefix.
2325 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2326 has no operand size prefix for AMD64 ISA, behave as 'P'
2329 2 upper case letter macros:
2330 "XY" => print 'x' or 'y' if suffix_always is true or no register
2331 operands and no broadcast.
2332 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2333 register operands and no broadcast.
2334 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2335 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2336 or suffix_always is true
2337 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2338 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2339 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2340 "LW" => print 'd', 'q' depending on the VEX.W bit
2341 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2342 an operand size prefix, or suffix_always is true. print
2343 'q' if rex prefix is present.
2345 Many of the above letters print nothing in Intel mode. See "putop"
2348 Braces '{' and '}', and vertical bars '|', indicate alternative
2349 mnemonic strings for AT&T and Intel. */
2351 static const struct dis386 dis386[] = {
2353 { "addB", { Ebh1, Gb }, 0 },
2354 { "addS", { Evh1, Gv }, 0 },
2355 { "addB", { Gb, EbS }, 0 },
2356 { "addS", { Gv, EvS }, 0 },
2357 { "addB", { AL, Ib }, 0 },
2358 { "addS", { eAX, Iv }, 0 },
2359 { X86_64_TABLE (X86_64_06) },
2360 { X86_64_TABLE (X86_64_07) },
2362 { "orB", { Ebh1, Gb }, 0 },
2363 { "orS", { Evh1, Gv }, 0 },
2364 { "orB", { Gb, EbS }, 0 },
2365 { "orS", { Gv, EvS }, 0 },
2366 { "orB", { AL, Ib }, 0 },
2367 { "orS", { eAX, Iv }, 0 },
2368 { X86_64_TABLE (X86_64_0D) },
2369 { Bad_Opcode }, /* 0x0f extended opcode escape */
2371 { "adcB", { Ebh1, Gb }, 0 },
2372 { "adcS", { Evh1, Gv }, 0 },
2373 { "adcB", { Gb, EbS }, 0 },
2374 { "adcS", { Gv, EvS }, 0 },
2375 { "adcB", { AL, Ib }, 0 },
2376 { "adcS", { eAX, Iv }, 0 },
2377 { X86_64_TABLE (X86_64_16) },
2378 { X86_64_TABLE (X86_64_17) },
2380 { "sbbB", { Ebh1, Gb }, 0 },
2381 { "sbbS", { Evh1, Gv }, 0 },
2382 { "sbbB", { Gb, EbS }, 0 },
2383 { "sbbS", { Gv, EvS }, 0 },
2384 { "sbbB", { AL, Ib }, 0 },
2385 { "sbbS", { eAX, Iv }, 0 },
2386 { X86_64_TABLE (X86_64_1E) },
2387 { X86_64_TABLE (X86_64_1F) },
2389 { "andB", { Ebh1, Gb }, 0 },
2390 { "andS", { Evh1, Gv }, 0 },
2391 { "andB", { Gb, EbS }, 0 },
2392 { "andS", { Gv, EvS }, 0 },
2393 { "andB", { AL, Ib }, 0 },
2394 { "andS", { eAX, Iv }, 0 },
2395 { Bad_Opcode }, /* SEG ES prefix */
2396 { X86_64_TABLE (X86_64_27) },
2398 { "subB", { Ebh1, Gb }, 0 },
2399 { "subS", { Evh1, Gv }, 0 },
2400 { "subB", { Gb, EbS }, 0 },
2401 { "subS", { Gv, EvS }, 0 },
2402 { "subB", { AL, Ib }, 0 },
2403 { "subS", { eAX, Iv }, 0 },
2404 { Bad_Opcode }, /* SEG CS prefix */
2405 { X86_64_TABLE (X86_64_2F) },
2407 { "xorB", { Ebh1, Gb }, 0 },
2408 { "xorS", { Evh1, Gv }, 0 },
2409 { "xorB", { Gb, EbS }, 0 },
2410 { "xorS", { Gv, EvS }, 0 },
2411 { "xorB", { AL, Ib }, 0 },
2412 { "xorS", { eAX, Iv }, 0 },
2413 { Bad_Opcode }, /* SEG SS prefix */
2414 { X86_64_TABLE (X86_64_37) },
2416 { "cmpB", { Eb, Gb }, 0 },
2417 { "cmpS", { Ev, Gv }, 0 },
2418 { "cmpB", { Gb, EbS }, 0 },
2419 { "cmpS", { Gv, EvS }, 0 },
2420 { "cmpB", { AL, Ib }, 0 },
2421 { "cmpS", { eAX, Iv }, 0 },
2422 { Bad_Opcode }, /* SEG DS prefix */
2423 { X86_64_TABLE (X86_64_3F) },
2425 { "inc{S|}", { RMeAX }, 0 },
2426 { "inc{S|}", { RMeCX }, 0 },
2427 { "inc{S|}", { RMeDX }, 0 },
2428 { "inc{S|}", { RMeBX }, 0 },
2429 { "inc{S|}", { RMeSP }, 0 },
2430 { "inc{S|}", { RMeBP }, 0 },
2431 { "inc{S|}", { RMeSI }, 0 },
2432 { "inc{S|}", { RMeDI }, 0 },
2434 { "dec{S|}", { RMeAX }, 0 },
2435 { "dec{S|}", { RMeCX }, 0 },
2436 { "dec{S|}", { RMeDX }, 0 },
2437 { "dec{S|}", { RMeBX }, 0 },
2438 { "dec{S|}", { RMeSP }, 0 },
2439 { "dec{S|}", { RMeBP }, 0 },
2440 { "dec{S|}", { RMeSI }, 0 },
2441 { "dec{S|}", { RMeDI }, 0 },
2443 { "pushV", { RMrAX }, 0 },
2444 { "pushV", { RMrCX }, 0 },
2445 { "pushV", { RMrDX }, 0 },
2446 { "pushV", { RMrBX }, 0 },
2447 { "pushV", { RMrSP }, 0 },
2448 { "pushV", { RMrBP }, 0 },
2449 { "pushV", { RMrSI }, 0 },
2450 { "pushV", { RMrDI }, 0 },
2452 { "popV", { RMrAX }, 0 },
2453 { "popV", { RMrCX }, 0 },
2454 { "popV", { RMrDX }, 0 },
2455 { "popV", { RMrBX }, 0 },
2456 { "popV", { RMrSP }, 0 },
2457 { "popV", { RMrBP }, 0 },
2458 { "popV", { RMrSI }, 0 },
2459 { "popV", { RMrDI }, 0 },
2461 { X86_64_TABLE (X86_64_60) },
2462 { X86_64_TABLE (X86_64_61) },
2463 { X86_64_TABLE (X86_64_62) },
2464 { X86_64_TABLE (X86_64_63) },
2465 { Bad_Opcode }, /* seg fs */
2466 { Bad_Opcode }, /* seg gs */
2467 { Bad_Opcode }, /* op size prefix */
2468 { Bad_Opcode }, /* adr size prefix */
2470 { "pushT", { sIv }, 0 },
2471 { "imulS", { Gv, Ev, Iv }, 0 },
2472 { "pushT", { sIbT }, 0 },
2473 { "imulS", { Gv, Ev, sIb }, 0 },
2474 { "ins{b|}", { Ybr, indirDX }, 0 },
2475 { X86_64_TABLE (X86_64_6D) },
2476 { "outs{b|}", { indirDXr, Xb }, 0 },
2477 { X86_64_TABLE (X86_64_6F) },
2479 { "joH", { Jb, BND, cond_jump_flag }, 0 },
2480 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
2481 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
2482 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
2483 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
2484 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
2485 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
2486 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
2488 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
2489 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
2490 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
2491 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
2492 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
2493 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
2494 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
2495 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
2497 { REG_TABLE (REG_80) },
2498 { REG_TABLE (REG_81) },
2499 { X86_64_TABLE (X86_64_82) },
2500 { REG_TABLE (REG_83) },
2501 { "testB", { Eb, Gb }, 0 },
2502 { "testS", { Ev, Gv }, 0 },
2503 { "xchgB", { Ebh2, Gb }, 0 },
2504 { "xchgS", { Evh2, Gv }, 0 },
2506 { "movB", { Ebh3, Gb }, 0 },
2507 { "movS", { Evh3, Gv }, 0 },
2508 { "movB", { Gb, EbS }, 0 },
2509 { "movS", { Gv, EvS }, 0 },
2510 { "movD", { Sv, Sw }, 0 },
2511 { MOD_TABLE (MOD_8D) },
2512 { "movD", { Sw, Sv }, 0 },
2513 { REG_TABLE (REG_8F) },
2515 { PREFIX_TABLE (PREFIX_90) },
2516 { "xchgS", { RMeCX, eAX }, 0 },
2517 { "xchgS", { RMeDX, eAX }, 0 },
2518 { "xchgS", { RMeBX, eAX }, 0 },
2519 { "xchgS", { RMeSP, eAX }, 0 },
2520 { "xchgS", { RMeBP, eAX }, 0 },
2521 { "xchgS", { RMeSI, eAX }, 0 },
2522 { "xchgS", { RMeDI, eAX }, 0 },
2524 { "cW{t|}R", { XX }, 0 },
2525 { "cR{t|}O", { XX }, 0 },
2526 { X86_64_TABLE (X86_64_9A) },
2527 { Bad_Opcode }, /* fwait */
2528 { "pushfT", { XX }, 0 },
2529 { "popfT", { XX }, 0 },
2530 { "sahf", { XX }, 0 },
2531 { "lahf", { XX }, 0 },
2533 { "mov%LB", { AL, Ob }, 0 },
2534 { "mov%LS", { eAX, Ov }, 0 },
2535 { "mov%LB", { Ob, AL }, 0 },
2536 { "mov%LS", { Ov, eAX }, 0 },
2537 { "movs{b|}", { Ybr, Xb }, 0 },
2538 { "movs{R|}", { Yvr, Xv }, 0 },
2539 { "cmps{b|}", { Xb, Yb }, 0 },
2540 { "cmps{R|}", { Xv, Yv }, 0 },
2542 { "testB", { AL, Ib }, 0 },
2543 { "testS", { eAX, Iv }, 0 },
2544 { "stosB", { Ybr, AL }, 0 },
2545 { "stosS", { Yvr, eAX }, 0 },
2546 { "lodsB", { ALr, Xb }, 0 },
2547 { "lodsS", { eAXr, Xv }, 0 },
2548 { "scasB", { AL, Yb }, 0 },
2549 { "scasS", { eAX, Yv }, 0 },
2551 { "movB", { RMAL, Ib }, 0 },
2552 { "movB", { RMCL, Ib }, 0 },
2553 { "movB", { RMDL, Ib }, 0 },
2554 { "movB", { RMBL, Ib }, 0 },
2555 { "movB", { RMAH, Ib }, 0 },
2556 { "movB", { RMCH, Ib }, 0 },
2557 { "movB", { RMDH, Ib }, 0 },
2558 { "movB", { RMBH, Ib }, 0 },
2560 { "mov%LV", { RMeAX, Iv64 }, 0 },
2561 { "mov%LV", { RMeCX, Iv64 }, 0 },
2562 { "mov%LV", { RMeDX, Iv64 }, 0 },
2563 { "mov%LV", { RMeBX, Iv64 }, 0 },
2564 { "mov%LV", { RMeSP, Iv64 }, 0 },
2565 { "mov%LV", { RMeBP, Iv64 }, 0 },
2566 { "mov%LV", { RMeSI, Iv64 }, 0 },
2567 { "mov%LV", { RMeDI, Iv64 }, 0 },
2569 { REG_TABLE (REG_C0) },
2570 { REG_TABLE (REG_C1) },
2571 { "retT", { Iw, BND }, 0 },
2572 { "retT", { BND }, 0 },
2573 { X86_64_TABLE (X86_64_C4) },
2574 { X86_64_TABLE (X86_64_C5) },
2575 { REG_TABLE (REG_C6) },
2576 { REG_TABLE (REG_C7) },
2578 { "enterT", { Iw, Ib }, 0 },
2579 { "leaveT", { XX }, 0 },
2580 { "Jret{|f}P", { Iw }, 0 },
2581 { "Jret{|f}P", { XX }, 0 },
2582 { "int3", { XX }, 0 },
2583 { "int", { Ib }, 0 },
2584 { X86_64_TABLE (X86_64_CE) },
2585 { "iret%LP", { XX }, 0 },
2587 { REG_TABLE (REG_D0) },
2588 { REG_TABLE (REG_D1) },
2589 { REG_TABLE (REG_D2) },
2590 { REG_TABLE (REG_D3) },
2591 { X86_64_TABLE (X86_64_D4) },
2592 { X86_64_TABLE (X86_64_D5) },
2594 { "xlat", { DSBX }, 0 },
2605 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2606 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2607 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2608 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2609 { "inB", { AL, Ib }, 0 },
2610 { "inG", { zAX, Ib }, 0 },
2611 { "outB", { Ib, AL }, 0 },
2612 { "outG", { Ib, zAX }, 0 },
2614 { X86_64_TABLE (X86_64_E8) },
2615 { X86_64_TABLE (X86_64_E9) },
2616 { X86_64_TABLE (X86_64_EA) },
2617 { "jmp", { Jb, BND }, 0 },
2618 { "inB", { AL, indirDX }, 0 },
2619 { "inG", { zAX, indirDX }, 0 },
2620 { "outB", { indirDX, AL }, 0 },
2621 { "outG", { indirDX, zAX }, 0 },
2623 { Bad_Opcode }, /* lock prefix */
2624 { "icebp", { XX }, 0 },
2625 { Bad_Opcode }, /* repne */
2626 { Bad_Opcode }, /* repz */
2627 { "hlt", { XX }, 0 },
2628 { "cmc", { XX }, 0 },
2629 { REG_TABLE (REG_F6) },
2630 { REG_TABLE (REG_F7) },
2632 { "clc", { XX }, 0 },
2633 { "stc", { XX }, 0 },
2634 { "cli", { XX }, 0 },
2635 { "sti", { XX }, 0 },
2636 { "cld", { XX }, 0 },
2637 { "std", { XX }, 0 },
2638 { REG_TABLE (REG_FE) },
2639 { REG_TABLE (REG_FF) },
2642 static const struct dis386 dis386_twobyte[] = {
2644 { REG_TABLE (REG_0F00 ) },
2645 { REG_TABLE (REG_0F01 ) },
2646 { "larS", { Gv, Ew }, 0 },
2647 { "lslS", { Gv, Ew }, 0 },
2649 { "syscall", { XX }, 0 },
2650 { "clts", { XX }, 0 },
2651 { "sysret%LP", { XX }, 0 },
2653 { "invd", { XX }, 0 },
2654 { PREFIX_TABLE (PREFIX_0F09) },
2656 { "ud2", { XX }, 0 },
2658 { REG_TABLE (REG_0F0D) },
2659 { "femms", { XX }, 0 },
2660 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2662 { PREFIX_TABLE (PREFIX_0F10) },
2663 { PREFIX_TABLE (PREFIX_0F11) },
2664 { PREFIX_TABLE (PREFIX_0F12) },
2665 { MOD_TABLE (MOD_0F13) },
2666 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2667 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2668 { PREFIX_TABLE (PREFIX_0F16) },
2669 { MOD_TABLE (MOD_0F17) },
2671 { REG_TABLE (REG_0F18) },
2672 { "nopQ", { Ev }, 0 },
2673 { PREFIX_TABLE (PREFIX_0F1A) },
2674 { PREFIX_TABLE (PREFIX_0F1B) },
2675 { PREFIX_TABLE (PREFIX_0F1C) },
2676 { "nopQ", { Ev }, 0 },
2677 { PREFIX_TABLE (PREFIX_0F1E) },
2678 { "nopQ", { Ev }, 0 },
2680 { "movZ", { Rm, Cm }, 0 },
2681 { "movZ", { Rm, Dm }, 0 },
2682 { "movZ", { Cm, Rm }, 0 },
2683 { "movZ", { Dm, Rm }, 0 },
2684 { MOD_TABLE (MOD_0F24) },
2686 { MOD_TABLE (MOD_0F26) },
2689 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2690 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2691 { PREFIX_TABLE (PREFIX_0F2A) },
2692 { PREFIX_TABLE (PREFIX_0F2B) },
2693 { PREFIX_TABLE (PREFIX_0F2C) },
2694 { PREFIX_TABLE (PREFIX_0F2D) },
2695 { PREFIX_TABLE (PREFIX_0F2E) },
2696 { PREFIX_TABLE (PREFIX_0F2F) },
2698 { "wrmsr", { XX }, 0 },
2699 { "rdtsc", { XX }, 0 },
2700 { "rdmsr", { XX }, 0 },
2701 { "rdpmc", { XX }, 0 },
2702 { "sysenter", { XX }, 0 },
2703 { "sysexit", { XX }, 0 },
2705 { "getsec", { XX }, 0 },
2707 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2709 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2716 { "cmovoS", { Gv, Ev }, 0 },
2717 { "cmovnoS", { Gv, Ev }, 0 },
2718 { "cmovbS", { Gv, Ev }, 0 },
2719 { "cmovaeS", { Gv, Ev }, 0 },
2720 { "cmoveS", { Gv, Ev }, 0 },
2721 { "cmovneS", { Gv, Ev }, 0 },
2722 { "cmovbeS", { Gv, Ev }, 0 },
2723 { "cmovaS", { Gv, Ev }, 0 },
2725 { "cmovsS", { Gv, Ev }, 0 },
2726 { "cmovnsS", { Gv, Ev }, 0 },
2727 { "cmovpS", { Gv, Ev }, 0 },
2728 { "cmovnpS", { Gv, Ev }, 0 },
2729 { "cmovlS", { Gv, Ev }, 0 },
2730 { "cmovgeS", { Gv, Ev }, 0 },
2731 { "cmovleS", { Gv, Ev }, 0 },
2732 { "cmovgS", { Gv, Ev }, 0 },
2734 { MOD_TABLE (MOD_0F51) },
2735 { PREFIX_TABLE (PREFIX_0F51) },
2736 { PREFIX_TABLE (PREFIX_0F52) },
2737 { PREFIX_TABLE (PREFIX_0F53) },
2738 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2739 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2740 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2741 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2743 { PREFIX_TABLE (PREFIX_0F58) },
2744 { PREFIX_TABLE (PREFIX_0F59) },
2745 { PREFIX_TABLE (PREFIX_0F5A) },
2746 { PREFIX_TABLE (PREFIX_0F5B) },
2747 { PREFIX_TABLE (PREFIX_0F5C) },
2748 { PREFIX_TABLE (PREFIX_0F5D) },
2749 { PREFIX_TABLE (PREFIX_0F5E) },
2750 { PREFIX_TABLE (PREFIX_0F5F) },
2752 { PREFIX_TABLE (PREFIX_0F60) },
2753 { PREFIX_TABLE (PREFIX_0F61) },
2754 { PREFIX_TABLE (PREFIX_0F62) },
2755 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2756 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2757 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2758 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2759 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2761 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2762 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2763 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2764 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2765 { PREFIX_TABLE (PREFIX_0F6C) },
2766 { PREFIX_TABLE (PREFIX_0F6D) },
2767 { "movK", { MX, Edq }, PREFIX_OPCODE },
2768 { PREFIX_TABLE (PREFIX_0F6F) },
2770 { PREFIX_TABLE (PREFIX_0F70) },
2771 { REG_TABLE (REG_0F71) },
2772 { REG_TABLE (REG_0F72) },
2773 { REG_TABLE (REG_0F73) },
2774 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2775 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2776 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2777 { "emms", { XX }, PREFIX_OPCODE },
2779 { PREFIX_TABLE (PREFIX_0F78) },
2780 { PREFIX_TABLE (PREFIX_0F79) },
2783 { PREFIX_TABLE (PREFIX_0F7C) },
2784 { PREFIX_TABLE (PREFIX_0F7D) },
2785 { PREFIX_TABLE (PREFIX_0F7E) },
2786 { PREFIX_TABLE (PREFIX_0F7F) },
2788 { "joH", { Jv, BND, cond_jump_flag }, 0 },
2789 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
2790 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
2791 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
2792 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
2793 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
2794 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
2795 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
2797 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
2798 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
2799 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
2800 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
2801 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
2802 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
2803 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
2804 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
2806 { "seto", { Eb }, 0 },
2807 { "setno", { Eb }, 0 },
2808 { "setb", { Eb }, 0 },
2809 { "setae", { Eb }, 0 },
2810 { "sete", { Eb }, 0 },
2811 { "setne", { Eb }, 0 },
2812 { "setbe", { Eb }, 0 },
2813 { "seta", { Eb }, 0 },
2815 { "sets", { Eb }, 0 },
2816 { "setns", { Eb }, 0 },
2817 { "setp", { Eb }, 0 },
2818 { "setnp", { Eb }, 0 },
2819 { "setl", { Eb }, 0 },
2820 { "setge", { Eb }, 0 },
2821 { "setle", { Eb }, 0 },
2822 { "setg", { Eb }, 0 },
2824 { "pushT", { fs }, 0 },
2825 { "popT", { fs }, 0 },
2826 { "cpuid", { XX }, 0 },
2827 { "btS", { Ev, Gv }, 0 },
2828 { "shldS", { Ev, Gv, Ib }, 0 },
2829 { "shldS", { Ev, Gv, CL }, 0 },
2830 { REG_TABLE (REG_0FA6) },
2831 { REG_TABLE (REG_0FA7) },
2833 { "pushT", { gs }, 0 },
2834 { "popT", { gs }, 0 },
2835 { "rsm", { XX }, 0 },
2836 { "btsS", { Evh1, Gv }, 0 },
2837 { "shrdS", { Ev, Gv, Ib }, 0 },
2838 { "shrdS", { Ev, Gv, CL }, 0 },
2839 { REG_TABLE (REG_0FAE) },
2840 { "imulS", { Gv, Ev }, 0 },
2842 { "cmpxchgB", { Ebh1, Gb }, 0 },
2843 { "cmpxchgS", { Evh1, Gv }, 0 },
2844 { MOD_TABLE (MOD_0FB2) },
2845 { "btrS", { Evh1, Gv }, 0 },
2846 { MOD_TABLE (MOD_0FB4) },
2847 { MOD_TABLE (MOD_0FB5) },
2848 { "movz{bR|x}", { Gv, Eb }, 0 },
2849 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2851 { PREFIX_TABLE (PREFIX_0FB8) },
2852 { "ud1S", { Gv, Ev }, 0 },
2853 { REG_TABLE (REG_0FBA) },
2854 { "btcS", { Evh1, Gv }, 0 },
2855 { PREFIX_TABLE (PREFIX_0FBC) },
2856 { PREFIX_TABLE (PREFIX_0FBD) },
2857 { "movs{bR|x}", { Gv, Eb }, 0 },
2858 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2860 { "xaddB", { Ebh1, Gb }, 0 },
2861 { "xaddS", { Evh1, Gv }, 0 },
2862 { PREFIX_TABLE (PREFIX_0FC2) },
2863 { MOD_TABLE (MOD_0FC3) },
2864 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
2865 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
2866 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
2867 { REG_TABLE (REG_0FC7) },
2869 { "bswap", { RMeAX }, 0 },
2870 { "bswap", { RMeCX }, 0 },
2871 { "bswap", { RMeDX }, 0 },
2872 { "bswap", { RMeBX }, 0 },
2873 { "bswap", { RMeSP }, 0 },
2874 { "bswap", { RMeBP }, 0 },
2875 { "bswap", { RMeSI }, 0 },
2876 { "bswap", { RMeDI }, 0 },
2878 { PREFIX_TABLE (PREFIX_0FD0) },
2879 { "psrlw", { MX, EM }, PREFIX_OPCODE },
2880 { "psrld", { MX, EM }, PREFIX_OPCODE },
2881 { "psrlq", { MX, EM }, PREFIX_OPCODE },
2882 { "paddq", { MX, EM }, PREFIX_OPCODE },
2883 { "pmullw", { MX, EM }, PREFIX_OPCODE },
2884 { PREFIX_TABLE (PREFIX_0FD6) },
2885 { MOD_TABLE (MOD_0FD7) },
2887 { "psubusb", { MX, EM }, PREFIX_OPCODE },
2888 { "psubusw", { MX, EM }, PREFIX_OPCODE },
2889 { "pminub", { MX, EM }, PREFIX_OPCODE },
2890 { "pand", { MX, EM }, PREFIX_OPCODE },
2891 { "paddusb", { MX, EM }, PREFIX_OPCODE },
2892 { "paddusw", { MX, EM }, PREFIX_OPCODE },
2893 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
2894 { "pandn", { MX, EM }, PREFIX_OPCODE },
2896 { "pavgb", { MX, EM }, PREFIX_OPCODE },
2897 { "psraw", { MX, EM }, PREFIX_OPCODE },
2898 { "psrad", { MX, EM }, PREFIX_OPCODE },
2899 { "pavgw", { MX, EM }, PREFIX_OPCODE },
2900 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
2901 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
2902 { PREFIX_TABLE (PREFIX_0FE6) },
2903 { PREFIX_TABLE (PREFIX_0FE7) },
2905 { "psubsb", { MX, EM }, PREFIX_OPCODE },
2906 { "psubsw", { MX, EM }, PREFIX_OPCODE },
2907 { "pminsw", { MX, EM }, PREFIX_OPCODE },
2908 { "por", { MX, EM }, PREFIX_OPCODE },
2909 { "paddsb", { MX, EM }, PREFIX_OPCODE },
2910 { "paddsw", { MX, EM }, PREFIX_OPCODE },
2911 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
2912 { "pxor", { MX, EM }, PREFIX_OPCODE },
2914 { PREFIX_TABLE (PREFIX_0FF0) },
2915 { "psllw", { MX, EM }, PREFIX_OPCODE },
2916 { "pslld", { MX, EM }, PREFIX_OPCODE },
2917 { "psllq", { MX, EM }, PREFIX_OPCODE },
2918 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
2919 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
2920 { "psadbw", { MX, EM }, PREFIX_OPCODE },
2921 { PREFIX_TABLE (PREFIX_0FF7) },
2923 { "psubb", { MX, EM }, PREFIX_OPCODE },
2924 { "psubw", { MX, EM }, PREFIX_OPCODE },
2925 { "psubd", { MX, EM }, PREFIX_OPCODE },
2926 { "psubq", { MX, EM }, PREFIX_OPCODE },
2927 { "paddb", { MX, EM }, PREFIX_OPCODE },
2928 { "paddw", { MX, EM }, PREFIX_OPCODE },
2929 { "paddd", { MX, EM }, PREFIX_OPCODE },
2930 { "ud0S", { Gv, Ev }, 0 },
2933 static const unsigned char onebyte_has_modrm[256] = {
2934 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2935 /* ------------------------------- */
2936 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2937 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2938 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2939 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2940 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2941 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2942 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2943 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2944 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2945 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2946 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2947 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2948 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2949 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2950 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2951 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2952 /* ------------------------------- */
2953 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2956 static const unsigned char twobyte_has_modrm[256] = {
2957 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2958 /* ------------------------------- */
2959 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2960 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2961 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2962 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2963 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2964 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2965 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2966 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2967 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2968 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2969 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2970 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2971 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2972 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2973 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2974 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2975 /* ------------------------------- */
2976 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2979 static char obuf[100];
2981 static char *mnemonicendp;
2982 static char scratchbuf[100];
2983 static unsigned char *start_codep;
2984 static unsigned char *insn_codep;
2985 static unsigned char *codep;
2986 static unsigned char *end_codep;
2987 static int last_lock_prefix;
2988 static int last_repz_prefix;
2989 static int last_repnz_prefix;
2990 static int last_data_prefix;
2991 static int last_addr_prefix;
2992 static int last_rex_prefix;
2993 static int last_seg_prefix;
2994 static int fwait_prefix;
2995 /* The active segment register prefix. */
2996 static int active_seg_prefix;
2997 #define MAX_CODE_LENGTH 15
2998 /* We can up to 14 prefixes since the maximum instruction length is
3000 static int all_prefixes[MAX_CODE_LENGTH - 1];
3001 static disassemble_info *the_info;
3009 static unsigned char need_modrm;
3019 int register_specifier;
3026 int mask_register_specifier;
3032 static unsigned char need_vex;
3033 static unsigned char need_vex_reg;
3034 static unsigned char vex_w_done;
3042 /* If we are accessing mod/rm/reg without need_modrm set, then the
3043 values are stale. Hitting this abort likely indicates that you
3044 need to update onebyte_has_modrm or twobyte_has_modrm. */
3045 #define MODRM_CHECK if (!need_modrm) abort ()
3047 static const char **names64;
3048 static const char **names32;
3049 static const char **names16;
3050 static const char **names8;
3051 static const char **names8rex;
3052 static const char **names_seg;
3053 static const char *index64;
3054 static const char *index32;
3055 static const char **index16;
3056 static const char **names_bnd;
3058 static const char *intel_names64[] = {
3059 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3060 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3062 static const char *intel_names32[] = {
3063 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3064 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3066 static const char *intel_names16[] = {
3067 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3068 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3070 static const char *intel_names8[] = {
3071 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3073 static const char *intel_names8rex[] = {
3074 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3075 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3077 static const char *intel_names_seg[] = {
3078 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3080 static const char *intel_index64 = "riz";
3081 static const char *intel_index32 = "eiz";
3082 static const char *intel_index16[] = {
3083 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3086 static const char *att_names64[] = {
3087 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3088 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3090 static const char *att_names32[] = {
3091 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3092 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3094 static const char *att_names16[] = {
3095 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3096 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3098 static const char *att_names8[] = {
3099 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3101 static const char *att_names8rex[] = {
3102 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3103 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3105 static const char *att_names_seg[] = {
3106 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3108 static const char *att_index64 = "%riz";
3109 static const char *att_index32 = "%eiz";
3110 static const char *att_index16[] = {
3111 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3114 static const char **names_mm;
3115 static const char *intel_names_mm[] = {
3116 "mm0", "mm1", "mm2", "mm3",
3117 "mm4", "mm5", "mm6", "mm7"
3119 static const char *att_names_mm[] = {
3120 "%mm0", "%mm1", "%mm2", "%mm3",
3121 "%mm4", "%mm5", "%mm6", "%mm7"
3124 static const char *intel_names_bnd[] = {
3125 "bnd0", "bnd1", "bnd2", "bnd3"
3128 static const char *att_names_bnd[] = {
3129 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3132 static const char **names_xmm;
3133 static const char *intel_names_xmm[] = {
3134 "xmm0", "xmm1", "xmm2", "xmm3",
3135 "xmm4", "xmm5", "xmm6", "xmm7",
3136 "xmm8", "xmm9", "xmm10", "xmm11",
3137 "xmm12", "xmm13", "xmm14", "xmm15",
3138 "xmm16", "xmm17", "xmm18", "xmm19",
3139 "xmm20", "xmm21", "xmm22", "xmm23",
3140 "xmm24", "xmm25", "xmm26", "xmm27",
3141 "xmm28", "xmm29", "xmm30", "xmm31"
3143 static const char *att_names_xmm[] = {
3144 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3145 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3146 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3147 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3148 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3149 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3150 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3151 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3154 static const char **names_ymm;
3155 static const char *intel_names_ymm[] = {
3156 "ymm0", "ymm1", "ymm2", "ymm3",
3157 "ymm4", "ymm5", "ymm6", "ymm7",
3158 "ymm8", "ymm9", "ymm10", "ymm11",
3159 "ymm12", "ymm13", "ymm14", "ymm15",
3160 "ymm16", "ymm17", "ymm18", "ymm19",
3161 "ymm20", "ymm21", "ymm22", "ymm23",
3162 "ymm24", "ymm25", "ymm26", "ymm27",
3163 "ymm28", "ymm29", "ymm30", "ymm31"
3165 static const char *att_names_ymm[] = {
3166 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3167 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3168 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3169 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3170 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3171 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3172 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3173 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3176 static const char **names_zmm;
3177 static const char *intel_names_zmm[] = {
3178 "zmm0", "zmm1", "zmm2", "zmm3",
3179 "zmm4", "zmm5", "zmm6", "zmm7",
3180 "zmm8", "zmm9", "zmm10", "zmm11",
3181 "zmm12", "zmm13", "zmm14", "zmm15",
3182 "zmm16", "zmm17", "zmm18", "zmm19",
3183 "zmm20", "zmm21", "zmm22", "zmm23",
3184 "zmm24", "zmm25", "zmm26", "zmm27",
3185 "zmm28", "zmm29", "zmm30", "zmm31"
3187 static const char *att_names_zmm[] = {
3188 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3189 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3190 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3191 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3192 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3193 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3194 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3195 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3198 static const char **names_mask;
3199 static const char *intel_names_mask[] = {
3200 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3202 static const char *att_names_mask[] = {
3203 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3206 static const char *names_rounding[] =
3214 static const struct dis386 reg_table[][8] = {
3217 { "addA", { Ebh1, Ib }, 0 },
3218 { "orA", { Ebh1, Ib }, 0 },
3219 { "adcA", { Ebh1, Ib }, 0 },
3220 { "sbbA", { Ebh1, Ib }, 0 },
3221 { "andA", { Ebh1, Ib }, 0 },
3222 { "subA", { Ebh1, Ib }, 0 },
3223 { "xorA", { Ebh1, Ib }, 0 },
3224 { "cmpA", { Eb, Ib }, 0 },
3228 { "addQ", { Evh1, Iv }, 0 },
3229 { "orQ", { Evh1, Iv }, 0 },
3230 { "adcQ", { Evh1, Iv }, 0 },
3231 { "sbbQ", { Evh1, Iv }, 0 },
3232 { "andQ", { Evh1, Iv }, 0 },
3233 { "subQ", { Evh1, Iv }, 0 },
3234 { "xorQ", { Evh1, Iv }, 0 },
3235 { "cmpQ", { Ev, Iv }, 0 },
3239 { "addQ", { Evh1, sIb }, 0 },
3240 { "orQ", { Evh1, sIb }, 0 },
3241 { "adcQ", { Evh1, sIb }, 0 },
3242 { "sbbQ", { Evh1, sIb }, 0 },
3243 { "andQ", { Evh1, sIb }, 0 },
3244 { "subQ", { Evh1, sIb }, 0 },
3245 { "xorQ", { Evh1, sIb }, 0 },
3246 { "cmpQ", { Ev, sIb }, 0 },
3250 { "popU", { stackEv }, 0 },
3251 { XOP_8F_TABLE (XOP_09) },
3255 { XOP_8F_TABLE (XOP_09) },
3259 { "rolA", { Eb, Ib }, 0 },
3260 { "rorA", { Eb, Ib }, 0 },
3261 { "rclA", { Eb, Ib }, 0 },
3262 { "rcrA", { Eb, Ib }, 0 },
3263 { "shlA", { Eb, Ib }, 0 },
3264 { "shrA", { Eb, Ib }, 0 },
3265 { "shlA", { Eb, Ib }, 0 },
3266 { "sarA", { Eb, Ib }, 0 },
3270 { "rolQ", { Ev, Ib }, 0 },
3271 { "rorQ", { Ev, Ib }, 0 },
3272 { "rclQ", { Ev, Ib }, 0 },
3273 { "rcrQ", { Ev, Ib }, 0 },
3274 { "shlQ", { Ev, Ib }, 0 },
3275 { "shrQ", { Ev, Ib }, 0 },
3276 { "shlQ", { Ev, Ib }, 0 },
3277 { "sarQ", { Ev, Ib }, 0 },
3281 { "movA", { Ebh3, Ib }, 0 },
3288 { MOD_TABLE (MOD_C6_REG_7) },
3292 { "movQ", { Evh3, Iv }, 0 },
3299 { MOD_TABLE (MOD_C7_REG_7) },
3303 { "rolA", { Eb, I1 }, 0 },
3304 { "rorA", { Eb, I1 }, 0 },
3305 { "rclA", { Eb, I1 }, 0 },
3306 { "rcrA", { Eb, I1 }, 0 },
3307 { "shlA", { Eb, I1 }, 0 },
3308 { "shrA", { Eb, I1 }, 0 },
3309 { "shlA", { Eb, I1 }, 0 },
3310 { "sarA", { Eb, I1 }, 0 },
3314 { "rolQ", { Ev, I1 }, 0 },
3315 { "rorQ", { Ev, I1 }, 0 },
3316 { "rclQ", { Ev, I1 }, 0 },
3317 { "rcrQ", { Ev, I1 }, 0 },
3318 { "shlQ", { Ev, I1 }, 0 },
3319 { "shrQ", { Ev, I1 }, 0 },
3320 { "shlQ", { Ev, I1 }, 0 },
3321 { "sarQ", { Ev, I1 }, 0 },
3325 { "rolA", { Eb, CL }, 0 },
3326 { "rorA", { Eb, CL }, 0 },
3327 { "rclA", { Eb, CL }, 0 },
3328 { "rcrA", { Eb, CL }, 0 },
3329 { "shlA", { Eb, CL }, 0 },
3330 { "shrA", { Eb, CL }, 0 },
3331 { "shlA", { Eb, CL }, 0 },
3332 { "sarA", { Eb, CL }, 0 },
3336 { "rolQ", { Ev, CL }, 0 },
3337 { "rorQ", { Ev, CL }, 0 },
3338 { "rclQ", { Ev, CL }, 0 },
3339 { "rcrQ", { Ev, CL }, 0 },
3340 { "shlQ", { Ev, CL }, 0 },
3341 { "shrQ", { Ev, CL }, 0 },
3342 { "shlQ", { Ev, CL }, 0 },
3343 { "sarQ", { Ev, CL }, 0 },
3347 { "testA", { Eb, Ib }, 0 },
3348 { "testA", { Eb, Ib }, 0 },
3349 { "notA", { Ebh1 }, 0 },
3350 { "negA", { Ebh1 }, 0 },
3351 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
3352 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
3353 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
3354 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
3358 { "testQ", { Ev, Iv }, 0 },
3359 { "testQ", { Ev, Iv }, 0 },
3360 { "notQ", { Evh1 }, 0 },
3361 { "negQ", { Evh1 }, 0 },
3362 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
3363 { "imulQ", { Ev }, 0 },
3364 { "divQ", { Ev }, 0 },
3365 { "idivQ", { Ev }, 0 },
3369 { "incA", { Ebh1 }, 0 },
3370 { "decA", { Ebh1 }, 0 },
3374 { "incQ", { Evh1 }, 0 },
3375 { "decQ", { Evh1 }, 0 },
3376 { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3377 { MOD_TABLE (MOD_FF_REG_3) },
3378 { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3379 { MOD_TABLE (MOD_FF_REG_5) },
3380 { "pushU", { stackEv }, 0 },
3385 { "sldtD", { Sv }, 0 },
3386 { "strD", { Sv }, 0 },
3387 { "lldt", { Ew }, 0 },
3388 { "ltr", { Ew }, 0 },
3389 { "verr", { Ew }, 0 },
3390 { "verw", { Ew }, 0 },
3396 { MOD_TABLE (MOD_0F01_REG_0) },
3397 { MOD_TABLE (MOD_0F01_REG_1) },
3398 { MOD_TABLE (MOD_0F01_REG_2) },
3399 { MOD_TABLE (MOD_0F01_REG_3) },
3400 { "smswD", { Sv }, 0 },
3401 { MOD_TABLE (MOD_0F01_REG_5) },
3402 { "lmsw", { Ew }, 0 },
3403 { MOD_TABLE (MOD_0F01_REG_7) },
3407 { "prefetch", { Mb }, 0 },
3408 { "prefetchw", { Mb }, 0 },
3409 { "prefetchwt1", { Mb }, 0 },
3410 { "prefetch", { Mb }, 0 },
3411 { "prefetch", { Mb }, 0 },
3412 { "prefetch", { Mb }, 0 },
3413 { "prefetch", { Mb }, 0 },
3414 { "prefetch", { Mb }, 0 },
3418 { MOD_TABLE (MOD_0F18_REG_0) },
3419 { MOD_TABLE (MOD_0F18_REG_1) },
3420 { MOD_TABLE (MOD_0F18_REG_2) },
3421 { MOD_TABLE (MOD_0F18_REG_3) },
3422 { MOD_TABLE (MOD_0F18_REG_4) },
3423 { MOD_TABLE (MOD_0F18_REG_5) },
3424 { MOD_TABLE (MOD_0F18_REG_6) },
3425 { MOD_TABLE (MOD_0F18_REG_7) },
3427 /* REG_0F1C_MOD_0 */
3429 { "cldemote", { Mb }, 0 },
3430 { "nopQ", { Ev }, 0 },
3431 { "nopQ", { Ev }, 0 },
3432 { "nopQ", { Ev }, 0 },
3433 { "nopQ", { Ev }, 0 },
3434 { "nopQ", { Ev }, 0 },
3435 { "nopQ", { Ev }, 0 },
3436 { "nopQ", { Ev }, 0 },
3438 /* REG_0F1E_MOD_3 */
3440 { "nopQ", { Ev }, 0 },
3441 { "rdsspK", { Rdq }, PREFIX_OPCODE },
3442 { "nopQ", { Ev }, 0 },
3443 { "nopQ", { Ev }, 0 },
3444 { "nopQ", { Ev }, 0 },
3445 { "nopQ", { Ev }, 0 },
3446 { "nopQ", { Ev }, 0 },
3447 { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3453 { MOD_TABLE (MOD_0F71_REG_2) },
3455 { MOD_TABLE (MOD_0F71_REG_4) },
3457 { MOD_TABLE (MOD_0F71_REG_6) },
3463 { MOD_TABLE (MOD_0F72_REG_2) },
3465 { MOD_TABLE (MOD_0F72_REG_4) },
3467 { MOD_TABLE (MOD_0F72_REG_6) },
3473 { MOD_TABLE (MOD_0F73_REG_2) },
3474 { MOD_TABLE (MOD_0F73_REG_3) },
3477 { MOD_TABLE (MOD_0F73_REG_6) },
3478 { MOD_TABLE (MOD_0F73_REG_7) },
3482 { "montmul", { { OP_0f07, 0 } }, 0 },
3483 { "xsha1", { { OP_0f07, 0 } }, 0 },
3484 { "xsha256", { { OP_0f07, 0 } }, 0 },
3488 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
3489 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
3490 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
3491 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
3492 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
3493 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
3497 { MOD_TABLE (MOD_0FAE_REG_0) },
3498 { MOD_TABLE (MOD_0FAE_REG_1) },
3499 { MOD_TABLE (MOD_0FAE_REG_2) },
3500 { MOD_TABLE (MOD_0FAE_REG_3) },
3501 { MOD_TABLE (MOD_0FAE_REG_4) },
3502 { MOD_TABLE (MOD_0FAE_REG_5) },
3503 { MOD_TABLE (MOD_0FAE_REG_6) },
3504 { MOD_TABLE (MOD_0FAE_REG_7) },
3512 { "btQ", { Ev, Ib }, 0 },
3513 { "btsQ", { Evh1, Ib }, 0 },
3514 { "btrQ", { Evh1, Ib }, 0 },
3515 { "btcQ", { Evh1, Ib }, 0 },
3520 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3522 { MOD_TABLE (MOD_0FC7_REG_3) },
3523 { MOD_TABLE (MOD_0FC7_REG_4) },
3524 { MOD_TABLE (MOD_0FC7_REG_5) },
3525 { MOD_TABLE (MOD_0FC7_REG_6) },
3526 { MOD_TABLE (MOD_0FC7_REG_7) },
3532 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3534 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3536 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3542 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3544 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3546 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3552 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3553 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3556 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3557 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3563 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3564 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3566 /* REG_VEX_0F38F3 */
3569 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3570 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3571 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3575 { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3576 { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3580 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3581 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3583 /* REG_XOP_TBM_01 */
3586 { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3587 { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3588 { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 },
3589 { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3590 { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 },
3591 { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 },
3592 { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3594 /* REG_XOP_TBM_02 */
3597 { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3602 { "blci", { { OP_LWP_E, 0 }, Ev }, 0 },
3604 #define NEED_REG_TABLE
3605 #include "i386-dis-evex.h"
3606 #undef NEED_REG_TABLE
3609 static const struct dis386 prefix_table[][4] = {
3612 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3613 { "pause", { XX }, 0 },
3614 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3615 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3618 /* PREFIX_MOD_0_0F01_REG_5 */
3621 { "rstorssp", { Mq }, PREFIX_OPCODE },
3624 /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3627 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3630 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3633 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3638 { "wbinvd", { XX }, 0 },
3639 { "wbnoinvd", { XX }, 0 },
3644 { "movups", { XM, EXx }, PREFIX_OPCODE },
3645 { "movss", { XM, EXd }, PREFIX_OPCODE },
3646 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3647 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3652 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3653 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3654 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3655 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3660 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3661 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3662 { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3663 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3668 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3669 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3670 { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3675 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3676 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3677 { "bndmov", { Gbnd, Ebnd }, 0 },
3678 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3683 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3684 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3685 { "bndmov", { EbndS, Gbnd }, 0 },
3686 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3691 { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3692 { "nopQ", { Ev }, PREFIX_OPCODE },
3693 { "nopQ", { Ev }, PREFIX_OPCODE },
3694 { "nopQ", { Ev }, PREFIX_OPCODE },
3699 { "nopQ", { Ev }, PREFIX_OPCODE },
3700 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3701 { "nopQ", { Ev }, PREFIX_OPCODE },
3702 { "nopQ", { Ev }, PREFIX_OPCODE },
3707 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3708 { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3709 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3710 { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3715 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3716 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3717 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3718 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3723 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3724 { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE },
3725 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3726 { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE },
3731 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3732 { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE },
3733 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3734 { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE },
3739 { "ucomiss",{ XM, EXd }, 0 },
3741 { "ucomisd",{ XM, EXq }, 0 },
3746 { "comiss", { XM, EXd }, 0 },
3748 { "comisd", { XM, EXq }, 0 },
3753 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3754 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3755 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3756 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3761 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3762 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3767 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3768 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3773 { "addps", { XM, EXx }, PREFIX_OPCODE },
3774 { "addss", { XM, EXd }, PREFIX_OPCODE },
3775 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3776 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3781 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3782 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3783 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3784 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3789 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3790 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3791 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3792 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3797 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3798 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3799 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3804 { "subps", { XM, EXx }, PREFIX_OPCODE },
3805 { "subss", { XM, EXd }, PREFIX_OPCODE },
3806 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3807 { "subsd", { XM, EXq }, PREFIX_OPCODE },
3812 { "minps", { XM, EXx }, PREFIX_OPCODE },
3813 { "minss", { XM, EXd }, PREFIX_OPCODE },
3814 { "minpd", { XM, EXx }, PREFIX_OPCODE },
3815 { "minsd", { XM, EXq }, PREFIX_OPCODE },
3820 { "divps", { XM, EXx }, PREFIX_OPCODE },
3821 { "divss", { XM, EXd }, PREFIX_OPCODE },
3822 { "divpd", { XM, EXx }, PREFIX_OPCODE },
3823 { "divsd", { XM, EXq }, PREFIX_OPCODE },
3828 { "maxps", { XM, EXx }, PREFIX_OPCODE },
3829 { "maxss", { XM, EXd }, PREFIX_OPCODE },
3830 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
3831 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
3836 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3838 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3843 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3845 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3850 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3852 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3859 { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3866 { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3871 { "movq", { MX, EM }, PREFIX_OPCODE },
3872 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3873 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3878 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3879 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3880 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3881 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3884 /* PREFIX_0F73_REG_3 */
3888 { "psrldq", { XS, Ib }, 0 },
3891 /* PREFIX_0F73_REG_7 */
3895 { "pslldq", { XS, Ib }, 0 },
3900 {"vmread", { Em, Gm }, 0 },
3902 {"extrq", { XS, Ib, Ib }, 0 },
3903 {"insertq", { XM, XS, Ib, Ib }, 0 },
3908 {"vmwrite", { Gm, Em }, 0 },
3910 {"extrq", { XM, XS }, 0 },
3911 {"insertq", { XM, XS }, 0 },
3918 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3919 { "haddps", { XM, EXx }, PREFIX_OPCODE },
3926 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3927 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3932 { "movK", { Edq, MX }, PREFIX_OPCODE },
3933 { "movq", { XM, EXq }, PREFIX_OPCODE },
3934 { "movK", { Edq, XM }, PREFIX_OPCODE },
3939 { "movq", { EMS, MX }, PREFIX_OPCODE },
3940 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3941 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3944 /* PREFIX_0FAE_REG_0 */
3947 { "rdfsbase", { Ev }, 0 },
3950 /* PREFIX_0FAE_REG_1 */
3953 { "rdgsbase", { Ev }, 0 },
3956 /* PREFIX_0FAE_REG_2 */
3959 { "wrfsbase", { Ev }, 0 },
3962 /* PREFIX_0FAE_REG_3 */
3965 { "wrgsbase", { Ev }, 0 },
3968 /* PREFIX_MOD_0_0FAE_REG_4 */
3970 { "xsave", { FXSAVE }, 0 },
3971 { "ptwrite%LQ", { Edq }, 0 },
3974 /* PREFIX_MOD_3_0FAE_REG_4 */
3977 { "ptwrite%LQ", { Edq }, 0 },
3980 /* PREFIX_MOD_0_0FAE_REG_5 */
3982 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
3985 /* PREFIX_MOD_3_0FAE_REG_5 */
3987 { "lfence", { Skip_MODRM }, 0 },
3988 { "incsspK", { Rdq }, PREFIX_OPCODE },
3991 /* PREFIX_MOD_0_0FAE_REG_6 */
3993 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
3994 { "clrssbsy", { Mq }, PREFIX_OPCODE },
3995 { "clwb", { Mb }, PREFIX_OPCODE },
3998 /* PREFIX_MOD_1_0FAE_REG_6 */
4000 { RM_TABLE (RM_0FAE_REG_6) },
4001 { "umonitor", { Eva }, PREFIX_OPCODE },
4002 { "tpause", { Edq }, PREFIX_OPCODE },
4003 { "umwait", { Edq }, PREFIX_OPCODE },
4006 /* PREFIX_0FAE_REG_7 */
4008 { "clflush", { Mb }, 0 },
4010 { "clflushopt", { Mb }, 0 },
4016 { "popcntS", { Gv, Ev }, 0 },
4021 { "bsfS", { Gv, Ev }, 0 },
4022 { "tzcntS", { Gv, Ev }, 0 },
4023 { "bsfS", { Gv, Ev }, 0 },
4028 { "bsrS", { Gv, Ev }, 0 },
4029 { "lzcntS", { Gv, Ev }, 0 },
4030 { "bsrS", { Gv, Ev }, 0 },
4035 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
4036 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
4037 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
4038 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
4041 /* PREFIX_MOD_0_0FC3 */
4043 { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4046 /* PREFIX_MOD_0_0FC7_REG_6 */
4048 { "vmptrld",{ Mq }, 0 },
4049 { "vmxon", { Mq }, 0 },
4050 { "vmclear",{ Mq }, 0 },
4053 /* PREFIX_MOD_3_0FC7_REG_6 */
4055 { "rdrand", { Ev }, 0 },
4057 { "rdrand", { Ev }, 0 }
4060 /* PREFIX_MOD_3_0FC7_REG_7 */
4062 { "rdseed", { Ev }, 0 },
4063 { "rdpid", { Em }, 0 },
4064 { "rdseed", { Ev }, 0 },
4071 { "addsubpd", { XM, EXx }, 0 },
4072 { "addsubps", { XM, EXx }, 0 },
4078 { "movq2dq",{ XM, MS }, 0 },
4079 { "movq", { EXqS, XM }, 0 },
4080 { "movdq2q",{ MX, XS }, 0 },
4086 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4087 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4088 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4093 { "movntq", { Mq, MX }, PREFIX_OPCODE },
4095 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4103 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4108 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4110 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4117 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4124 { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4131 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4138 { "ptest", { XM, EXx }, PREFIX_OPCODE },
4145 { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4152 { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4159 { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4166 { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4173 { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4180 { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4187 { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4194 { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4201 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4208 { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4215 { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4222 { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4229 { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4236 { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4243 { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4250 { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4257 { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4264 { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4271 { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4278 { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4285 { "pminud", { XM, EXx }, PREFIX_OPCODE },
4292 { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4299 { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4306 { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4313 { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4320 { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4327 { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4334 { "invept", { Gm, Mo }, PREFIX_OPCODE },
4341 { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4348 { "invpcid", { Gm, M }, PREFIX_OPCODE },
4353 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4358 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4363 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4368 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4373 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4378 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4385 { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4392 { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4399 { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4406 { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4413 { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4420 { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4425 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4427 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4428 { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4433 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4435 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4436 { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4443 { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4448 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4449 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
4450 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
4458 { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4463 { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4470 { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4477 { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4484 { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4491 { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4498 { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4505 { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4512 { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4519 { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4526 { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4533 { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4540 { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4547 { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4554 { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4561 { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4568 { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE },
4575 { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE },
4582 { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4589 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4596 { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4603 { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4610 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4617 { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4622 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4629 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4636 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4643 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4646 /* PREFIX_VEX_0F10 */
4648 { "vmovups", { XM, EXx }, 0 },
4649 { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
4650 { "vmovupd", { XM, EXx }, 0 },
4651 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
4654 /* PREFIX_VEX_0F11 */
4656 { "vmovups", { EXxS, XM }, 0 },
4657 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4658 { "vmovupd", { EXxS, XM }, 0 },
4659 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4662 /* PREFIX_VEX_0F12 */
4664 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4665 { "vmovsldup", { XM, EXx }, 0 },
4666 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4667 { "vmovddup", { XM, EXymmq }, 0 },
4670 /* PREFIX_VEX_0F16 */
4672 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4673 { "vmovshdup", { XM, EXx }, 0 },
4674 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4677 /* PREFIX_VEX_0F2A */
4680 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4682 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4685 /* PREFIX_VEX_0F2C */
4688 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4690 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4693 /* PREFIX_VEX_0F2D */
4696 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4698 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4701 /* PREFIX_VEX_0F2E */
4703 { "vucomiss", { XMScalar, EXdScalar }, 0 },
4705 { "vucomisd", { XMScalar, EXqScalar }, 0 },
4708 /* PREFIX_VEX_0F2F */
4710 { "vcomiss", { XMScalar, EXdScalar }, 0 },
4712 { "vcomisd", { XMScalar, EXqScalar }, 0 },
4715 /* PREFIX_VEX_0F41 */
4717 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4719 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4722 /* PREFIX_VEX_0F42 */
4724 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4726 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4729 /* PREFIX_VEX_0F44 */
4731 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4733 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4736 /* PREFIX_VEX_0F45 */
4738 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4740 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4743 /* PREFIX_VEX_0F46 */
4745 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4747 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4750 /* PREFIX_VEX_0F47 */
4752 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4754 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4757 /* PREFIX_VEX_0F4A */
4759 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4761 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4764 /* PREFIX_VEX_0F4B */
4766 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4768 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4771 /* PREFIX_VEX_0F51 */
4773 { "vsqrtps", { XM, EXx }, 0 },
4774 { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
4775 { "vsqrtpd", { XM, EXx }, 0 },
4776 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4779 /* PREFIX_VEX_0F52 */
4781 { "vrsqrtps", { XM, EXx }, 0 },
4782 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
4785 /* PREFIX_VEX_0F53 */
4787 { "vrcpps", { XM, EXx }, 0 },
4788 { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
4791 /* PREFIX_VEX_0F58 */
4793 { "vaddps", { XM, Vex, EXx }, 0 },
4794 { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
4795 { "vaddpd", { XM, Vex, EXx }, 0 },
4796 { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4799 /* PREFIX_VEX_0F59 */
4801 { "vmulps", { XM, Vex, EXx }, 0 },
4802 { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
4803 { "vmulpd", { XM, Vex, EXx }, 0 },
4804 { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4807 /* PREFIX_VEX_0F5A */
4809 { "vcvtps2pd", { XM, EXxmmq }, 0 },
4810 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
4811 { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4812 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
4815 /* PREFIX_VEX_0F5B */
4817 { "vcvtdq2ps", { XM, EXx }, 0 },
4818 { "vcvttps2dq", { XM, EXx }, 0 },
4819 { "vcvtps2dq", { XM, EXx }, 0 },
4822 /* PREFIX_VEX_0F5C */
4824 { "vsubps", { XM, Vex, EXx }, 0 },
4825 { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
4826 { "vsubpd", { XM, Vex, EXx }, 0 },
4827 { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4830 /* PREFIX_VEX_0F5D */
4832 { "vminps", { XM, Vex, EXx }, 0 },
4833 { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
4834 { "vminpd", { XM, Vex, EXx }, 0 },
4835 { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4838 /* PREFIX_VEX_0F5E */
4840 { "vdivps", { XM, Vex, EXx }, 0 },
4841 { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
4842 { "vdivpd", { XM, Vex, EXx }, 0 },
4843 { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4846 /* PREFIX_VEX_0F5F */
4848 { "vmaxps", { XM, Vex, EXx }, 0 },
4849 { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
4850 { "vmaxpd", { XM, Vex, EXx }, 0 },
4851 { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4854 /* PREFIX_VEX_0F60 */
4858 { "vpunpcklbw", { XM, Vex, EXx }, 0 },
4861 /* PREFIX_VEX_0F61 */
4865 { "vpunpcklwd", { XM, Vex, EXx }, 0 },
4868 /* PREFIX_VEX_0F62 */
4872 { "vpunpckldq", { XM, Vex, EXx }, 0 },
4875 /* PREFIX_VEX_0F63 */
4879 { "vpacksswb", { XM, Vex, EXx }, 0 },
4882 /* PREFIX_VEX_0F64 */
4886 { "vpcmpgtb", { XM, Vex, EXx }, 0 },
4889 /* PREFIX_VEX_0F65 */
4893 { "vpcmpgtw", { XM, Vex, EXx }, 0 },
4896 /* PREFIX_VEX_0F66 */
4900 { "vpcmpgtd", { XM, Vex, EXx }, 0 },
4903 /* PREFIX_VEX_0F67 */
4907 { "vpackuswb", { XM, Vex, EXx }, 0 },
4910 /* PREFIX_VEX_0F68 */
4914 { "vpunpckhbw", { XM, Vex, EXx }, 0 },
4917 /* PREFIX_VEX_0F69 */
4921 { "vpunpckhwd", { XM, Vex, EXx }, 0 },
4924 /* PREFIX_VEX_0F6A */
4928 { "vpunpckhdq", { XM, Vex, EXx }, 0 },
4931 /* PREFIX_VEX_0F6B */
4935 { "vpackssdw", { XM, Vex, EXx }, 0 },
4938 /* PREFIX_VEX_0F6C */
4942 { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
4945 /* PREFIX_VEX_0F6D */
4949 { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
4952 /* PREFIX_VEX_0F6E */
4956 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4959 /* PREFIX_VEX_0F6F */
4962 { "vmovdqu", { XM, EXx }, 0 },
4963 { "vmovdqa", { XM, EXx }, 0 },
4966 /* PREFIX_VEX_0F70 */
4969 { "vpshufhw", { XM, EXx, Ib }, 0 },
4970 { "vpshufd", { XM, EXx, Ib }, 0 },
4971 { "vpshuflw", { XM, EXx, Ib }, 0 },
4974 /* PREFIX_VEX_0F71_REG_2 */
4978 { "vpsrlw", { Vex, XS, Ib }, 0 },
4981 /* PREFIX_VEX_0F71_REG_4 */
4985 { "vpsraw", { Vex, XS, Ib }, 0 },
4988 /* PREFIX_VEX_0F71_REG_6 */
4992 { "vpsllw", { Vex, XS, Ib }, 0 },
4995 /* PREFIX_VEX_0F72_REG_2 */
4999 { "vpsrld", { Vex, XS, Ib }, 0 },
5002 /* PREFIX_VEX_0F72_REG_4 */
5006 { "vpsrad", { Vex, XS, Ib }, 0 },
5009 /* PREFIX_VEX_0F72_REG_6 */
5013 { "vpslld", { Vex, XS, Ib }, 0 },
5016 /* PREFIX_VEX_0F73_REG_2 */
5020 { "vpsrlq", { Vex, XS, Ib }, 0 },
5023 /* PREFIX_VEX_0F73_REG_3 */
5027 { "vpsrldq", { Vex, XS, Ib }, 0 },
5030 /* PREFIX_VEX_0F73_REG_6 */
5034 { "vpsllq", { Vex, XS, Ib }, 0 },
5037 /* PREFIX_VEX_0F73_REG_7 */
5041 { "vpslldq", { Vex, XS, Ib }, 0 },
5044 /* PREFIX_VEX_0F74 */
5048 { "vpcmpeqb", { XM, Vex, EXx }, 0 },
5051 /* PREFIX_VEX_0F75 */
5055 { "vpcmpeqw", { XM, Vex, EXx }, 0 },
5058 /* PREFIX_VEX_0F76 */
5062 { "vpcmpeqd", { XM, Vex, EXx }, 0 },
5065 /* PREFIX_VEX_0F77 */
5067 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5070 /* PREFIX_VEX_0F7C */
5074 { "vhaddpd", { XM, Vex, EXx }, 0 },
5075 { "vhaddps", { XM, Vex, EXx }, 0 },
5078 /* PREFIX_VEX_0F7D */
5082 { "vhsubpd", { XM, Vex, EXx }, 0 },
5083 { "vhsubps", { XM, Vex, EXx }, 0 },
5086 /* PREFIX_VEX_0F7E */
5089 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5090 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5093 /* PREFIX_VEX_0F7F */
5096 { "vmovdqu", { EXxS, XM }, 0 },
5097 { "vmovdqa", { EXxS, XM }, 0 },
5100 /* PREFIX_VEX_0F90 */
5102 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5104 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5107 /* PREFIX_VEX_0F91 */
5109 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5111 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5114 /* PREFIX_VEX_0F92 */
5116 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5118 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5119 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5122 /* PREFIX_VEX_0F93 */
5124 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5126 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5127 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5130 /* PREFIX_VEX_0F98 */
5132 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5134 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5137 /* PREFIX_VEX_0F99 */
5139 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5141 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5144 /* PREFIX_VEX_0FC2 */
5146 { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
5147 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5148 { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
5149 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5152 /* PREFIX_VEX_0FC4 */
5156 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5159 /* PREFIX_VEX_0FC5 */
5163 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5166 /* PREFIX_VEX_0FD0 */
5170 { "vaddsubpd", { XM, Vex, EXx }, 0 },
5171 { "vaddsubps", { XM, Vex, EXx }, 0 },
5174 /* PREFIX_VEX_0FD1 */
5178 { "vpsrlw", { XM, Vex, EXxmm }, 0 },
5181 /* PREFIX_VEX_0FD2 */
5185 { "vpsrld", { XM, Vex, EXxmm }, 0 },
5188 /* PREFIX_VEX_0FD3 */
5192 { "vpsrlq", { XM, Vex, EXxmm }, 0 },
5195 /* PREFIX_VEX_0FD4 */
5199 { "vpaddq", { XM, Vex, EXx }, 0 },
5202 /* PREFIX_VEX_0FD5 */
5206 { "vpmullw", { XM, Vex, EXx }, 0 },
5209 /* PREFIX_VEX_0FD6 */
5213 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5216 /* PREFIX_VEX_0FD7 */
5220 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5223 /* PREFIX_VEX_0FD8 */
5227 { "vpsubusb", { XM, Vex, EXx }, 0 },
5230 /* PREFIX_VEX_0FD9 */
5234 { "vpsubusw", { XM, Vex, EXx }, 0 },
5237 /* PREFIX_VEX_0FDA */
5241 { "vpminub", { XM, Vex, EXx }, 0 },
5244 /* PREFIX_VEX_0FDB */
5248 { "vpand", { XM, Vex, EXx }, 0 },
5251 /* PREFIX_VEX_0FDC */
5255 { "vpaddusb", { XM, Vex, EXx }, 0 },
5258 /* PREFIX_VEX_0FDD */
5262 { "vpaddusw", { XM, Vex, EXx }, 0 },
5265 /* PREFIX_VEX_0FDE */
5269 { "vpmaxub", { XM, Vex, EXx }, 0 },
5272 /* PREFIX_VEX_0FDF */
5276 { "vpandn", { XM, Vex, EXx }, 0 },
5279 /* PREFIX_VEX_0FE0 */
5283 { "vpavgb", { XM, Vex, EXx }, 0 },
5286 /* PREFIX_VEX_0FE1 */
5290 { "vpsraw", { XM, Vex, EXxmm }, 0 },
5293 /* PREFIX_VEX_0FE2 */
5297 { "vpsrad", { XM, Vex, EXxmm }, 0 },
5300 /* PREFIX_VEX_0FE3 */
5304 { "vpavgw", { XM, Vex, EXx }, 0 },
5307 /* PREFIX_VEX_0FE4 */
5311 { "vpmulhuw", { XM, Vex, EXx }, 0 },
5314 /* PREFIX_VEX_0FE5 */
5318 { "vpmulhw", { XM, Vex, EXx }, 0 },
5321 /* PREFIX_VEX_0FE6 */
5324 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
5325 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
5326 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
5329 /* PREFIX_VEX_0FE7 */
5333 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5336 /* PREFIX_VEX_0FE8 */
5340 { "vpsubsb", { XM, Vex, EXx }, 0 },
5343 /* PREFIX_VEX_0FE9 */
5347 { "vpsubsw", { XM, Vex, EXx }, 0 },
5350 /* PREFIX_VEX_0FEA */
5354 { "vpminsw", { XM, Vex, EXx }, 0 },
5357 /* PREFIX_VEX_0FEB */
5361 { "vpor", { XM, Vex, EXx }, 0 },
5364 /* PREFIX_VEX_0FEC */
5368 { "vpaddsb", { XM, Vex, EXx }, 0 },
5371 /* PREFIX_VEX_0FED */
5375 { "vpaddsw", { XM, Vex, EXx }, 0 },
5378 /* PREFIX_VEX_0FEE */
5382 { "vpmaxsw", { XM, Vex, EXx }, 0 },
5385 /* PREFIX_VEX_0FEF */
5389 { "vpxor", { XM, Vex, EXx }, 0 },
5392 /* PREFIX_VEX_0FF0 */
5397 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5400 /* PREFIX_VEX_0FF1 */
5404 { "vpsllw", { XM, Vex, EXxmm }, 0 },
5407 /* PREFIX_VEX_0FF2 */
5411 { "vpslld", { XM, Vex, EXxmm }, 0 },
5414 /* PREFIX_VEX_0FF3 */
5418 { "vpsllq", { XM, Vex, EXxmm }, 0 },
5421 /* PREFIX_VEX_0FF4 */
5425 { "vpmuludq", { XM, Vex, EXx }, 0 },
5428 /* PREFIX_VEX_0FF5 */
5432 { "vpmaddwd", { XM, Vex, EXx }, 0 },
5435 /* PREFIX_VEX_0FF6 */
5439 { "vpsadbw", { XM, Vex, EXx }, 0 },
5442 /* PREFIX_VEX_0FF7 */
5446 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5449 /* PREFIX_VEX_0FF8 */
5453 { "vpsubb", { XM, Vex, EXx }, 0 },
5456 /* PREFIX_VEX_0FF9 */
5460 { "vpsubw", { XM, Vex, EXx }, 0 },
5463 /* PREFIX_VEX_0FFA */
5467 { "vpsubd", { XM, Vex, EXx }, 0 },
5470 /* PREFIX_VEX_0FFB */
5474 { "vpsubq", { XM, Vex, EXx }, 0 },
5477 /* PREFIX_VEX_0FFC */
5481 { "vpaddb", { XM, Vex, EXx }, 0 },
5484 /* PREFIX_VEX_0FFD */
5488 { "vpaddw", { XM, Vex, EXx }, 0 },
5491 /* PREFIX_VEX_0FFE */
5495 { "vpaddd", { XM, Vex, EXx }, 0 },
5498 /* PREFIX_VEX_0F3800 */
5502 { "vpshufb", { XM, Vex, EXx }, 0 },
5505 /* PREFIX_VEX_0F3801 */
5509 { "vphaddw", { XM, Vex, EXx }, 0 },
5512 /* PREFIX_VEX_0F3802 */
5516 { "vphaddd", { XM, Vex, EXx }, 0 },
5519 /* PREFIX_VEX_0F3803 */
5523 { "vphaddsw", { XM, Vex, EXx }, 0 },
5526 /* PREFIX_VEX_0F3804 */
5530 { "vpmaddubsw", { XM, Vex, EXx }, 0 },
5533 /* PREFIX_VEX_0F3805 */
5537 { "vphsubw", { XM, Vex, EXx }, 0 },
5540 /* PREFIX_VEX_0F3806 */
5544 { "vphsubd", { XM, Vex, EXx }, 0 },
5547 /* PREFIX_VEX_0F3807 */
5551 { "vphsubsw", { XM, Vex, EXx }, 0 },
5554 /* PREFIX_VEX_0F3808 */
5558 { "vpsignb", { XM, Vex, EXx }, 0 },
5561 /* PREFIX_VEX_0F3809 */
5565 { "vpsignw", { XM, Vex, EXx }, 0 },
5568 /* PREFIX_VEX_0F380A */
5572 { "vpsignd", { XM, Vex, EXx }, 0 },
5575 /* PREFIX_VEX_0F380B */
5579 { "vpmulhrsw", { XM, Vex, EXx }, 0 },
5582 /* PREFIX_VEX_0F380C */
5586 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5589 /* PREFIX_VEX_0F380D */
5593 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5596 /* PREFIX_VEX_0F380E */
5600 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5603 /* PREFIX_VEX_0F380F */
5607 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5610 /* PREFIX_VEX_0F3813 */
5614 { "vcvtph2ps", { XM, EXxmmq }, 0 },
5617 /* PREFIX_VEX_0F3816 */
5621 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5624 /* PREFIX_VEX_0F3817 */
5628 { "vptest", { XM, EXx }, 0 },
5631 /* PREFIX_VEX_0F3818 */
5635 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5638 /* PREFIX_VEX_0F3819 */
5642 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5645 /* PREFIX_VEX_0F381A */
5649 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5652 /* PREFIX_VEX_0F381C */
5656 { "vpabsb", { XM, EXx }, 0 },
5659 /* PREFIX_VEX_0F381D */
5663 { "vpabsw", { XM, EXx }, 0 },
5666 /* PREFIX_VEX_0F381E */
5670 { "vpabsd", { XM, EXx }, 0 },
5673 /* PREFIX_VEX_0F3820 */
5677 { "vpmovsxbw", { XM, EXxmmq }, 0 },
5680 /* PREFIX_VEX_0F3821 */
5684 { "vpmovsxbd", { XM, EXxmmqd }, 0 },
5687 /* PREFIX_VEX_0F3822 */
5691 { "vpmovsxbq", { XM, EXxmmdw }, 0 },
5694 /* PREFIX_VEX_0F3823 */
5698 { "vpmovsxwd", { XM, EXxmmq }, 0 },
5701 /* PREFIX_VEX_0F3824 */
5705 { "vpmovsxwq", { XM, EXxmmqd }, 0 },
5708 /* PREFIX_VEX_0F3825 */
5712 { "vpmovsxdq", { XM, EXxmmq }, 0 },
5715 /* PREFIX_VEX_0F3828 */
5719 { "vpmuldq", { XM, Vex, EXx }, 0 },
5722 /* PREFIX_VEX_0F3829 */
5726 { "vpcmpeqq", { XM, Vex, EXx }, 0 },
5729 /* PREFIX_VEX_0F382A */
5733 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5736 /* PREFIX_VEX_0F382B */
5740 { "vpackusdw", { XM, Vex, EXx }, 0 },
5743 /* PREFIX_VEX_0F382C */
5747 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5750 /* PREFIX_VEX_0F382D */
5754 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5757 /* PREFIX_VEX_0F382E */
5761 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5764 /* PREFIX_VEX_0F382F */
5768 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5771 /* PREFIX_VEX_0F3830 */
5775 { "vpmovzxbw", { XM, EXxmmq }, 0 },
5778 /* PREFIX_VEX_0F3831 */
5782 { "vpmovzxbd", { XM, EXxmmqd }, 0 },
5785 /* PREFIX_VEX_0F3832 */
5789 { "vpmovzxbq", { XM, EXxmmdw }, 0 },
5792 /* PREFIX_VEX_0F3833 */
5796 { "vpmovzxwd", { XM, EXxmmq }, 0 },
5799 /* PREFIX_VEX_0F3834 */
5803 { "vpmovzxwq", { XM, EXxmmqd }, 0 },
5806 /* PREFIX_VEX_0F3835 */
5810 { "vpmovzxdq", { XM, EXxmmq }, 0 },
5813 /* PREFIX_VEX_0F3836 */
5817 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5820 /* PREFIX_VEX_0F3837 */
5824 { "vpcmpgtq", { XM, Vex, EXx }, 0 },
5827 /* PREFIX_VEX_0F3838 */
5831 { "vpminsb", { XM, Vex, EXx }, 0 },
5834 /* PREFIX_VEX_0F3839 */
5838 { "vpminsd", { XM, Vex, EXx }, 0 },
5841 /* PREFIX_VEX_0F383A */
5845 { "vpminuw", { XM, Vex, EXx }, 0 },
5848 /* PREFIX_VEX_0F383B */
5852 { "vpminud", { XM, Vex, EXx }, 0 },
5855 /* PREFIX_VEX_0F383C */
5859 { "vpmaxsb", { XM, Vex, EXx }, 0 },
5862 /* PREFIX_VEX_0F383D */
5866 { "vpmaxsd", { XM, Vex, EXx }, 0 },
5869 /* PREFIX_VEX_0F383E */
5873 { "vpmaxuw", { XM, Vex, EXx }, 0 },
5876 /* PREFIX_VEX_0F383F */
5880 { "vpmaxud", { XM, Vex, EXx }, 0 },
5883 /* PREFIX_VEX_0F3840 */
5887 { "vpmulld", { XM, Vex, EXx }, 0 },
5890 /* PREFIX_VEX_0F3841 */
5894 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5897 /* PREFIX_VEX_0F3845 */
5901 { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5904 /* PREFIX_VEX_0F3846 */
5908 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5911 /* PREFIX_VEX_0F3847 */
5915 { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5918 /* PREFIX_VEX_0F3858 */
5922 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5925 /* PREFIX_VEX_0F3859 */
5929 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5932 /* PREFIX_VEX_0F385A */
5936 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5939 /* PREFIX_VEX_0F3878 */
5943 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5946 /* PREFIX_VEX_0F3879 */
5950 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5953 /* PREFIX_VEX_0F388C */
5957 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5960 /* PREFIX_VEX_0F388E */
5964 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5967 /* PREFIX_VEX_0F3890 */
5971 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5974 /* PREFIX_VEX_0F3891 */
5978 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5981 /* PREFIX_VEX_0F3892 */
5985 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5988 /* PREFIX_VEX_0F3893 */
5992 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5995 /* PREFIX_VEX_0F3896 */
5999 { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6002 /* PREFIX_VEX_0F3897 */
6006 { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6009 /* PREFIX_VEX_0F3898 */
6013 { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6016 /* PREFIX_VEX_0F3899 */
6020 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6023 /* PREFIX_VEX_0F389A */
6027 { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6030 /* PREFIX_VEX_0F389B */
6034 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6037 /* PREFIX_VEX_0F389C */
6041 { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6044 /* PREFIX_VEX_0F389D */
6048 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6051 /* PREFIX_VEX_0F389E */
6055 { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6058 /* PREFIX_VEX_0F389F */
6062 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6065 /* PREFIX_VEX_0F38A6 */
6069 { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6073 /* PREFIX_VEX_0F38A7 */
6077 { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6080 /* PREFIX_VEX_0F38A8 */
6084 { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6087 /* PREFIX_VEX_0F38A9 */
6091 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6094 /* PREFIX_VEX_0F38AA */
6098 { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6101 /* PREFIX_VEX_0F38AB */
6105 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6108 /* PREFIX_VEX_0F38AC */
6112 { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6115 /* PREFIX_VEX_0F38AD */
6119 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6122 /* PREFIX_VEX_0F38AE */
6126 { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6129 /* PREFIX_VEX_0F38AF */
6133 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6136 /* PREFIX_VEX_0F38B6 */
6140 { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6143 /* PREFIX_VEX_0F38B7 */
6147 { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6150 /* PREFIX_VEX_0F38B8 */
6154 { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6157 /* PREFIX_VEX_0F38B9 */
6161 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6164 /* PREFIX_VEX_0F38BA */
6168 { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6171 /* PREFIX_VEX_0F38BB */
6175 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6178 /* PREFIX_VEX_0F38BC */
6182 { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6185 /* PREFIX_VEX_0F38BD */
6189 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6192 /* PREFIX_VEX_0F38BE */
6196 { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6199 /* PREFIX_VEX_0F38BF */
6203 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6206 /* PREFIX_VEX_0F38CF */
6210 { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6213 /* PREFIX_VEX_0F38DB */
6217 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6220 /* PREFIX_VEX_0F38DC */
6224 { "vaesenc", { XM, Vex, EXx }, 0 },
6227 /* PREFIX_VEX_0F38DD */
6231 { "vaesenclast", { XM, Vex, EXx }, 0 },
6234 /* PREFIX_VEX_0F38DE */
6238 { "vaesdec", { XM, Vex, EXx }, 0 },
6241 /* PREFIX_VEX_0F38DF */
6245 { "vaesdeclast", { XM, Vex, EXx }, 0 },
6248 /* PREFIX_VEX_0F38F2 */
6250 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6253 /* PREFIX_VEX_0F38F3_REG_1 */
6255 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6258 /* PREFIX_VEX_0F38F3_REG_2 */
6260 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6263 /* PREFIX_VEX_0F38F3_REG_3 */
6265 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6268 /* PREFIX_VEX_0F38F5 */
6270 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6271 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6273 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6276 /* PREFIX_VEX_0F38F6 */
6281 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6284 /* PREFIX_VEX_0F38F7 */
6286 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6287 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6288 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6289 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6292 /* PREFIX_VEX_0F3A00 */
6296 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6299 /* PREFIX_VEX_0F3A01 */
6303 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6306 /* PREFIX_VEX_0F3A02 */
6310 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6313 /* PREFIX_VEX_0F3A04 */
6317 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6320 /* PREFIX_VEX_0F3A05 */
6324 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6327 /* PREFIX_VEX_0F3A06 */
6331 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6334 /* PREFIX_VEX_0F3A08 */
6338 { "vroundps", { XM, EXx, Ib }, 0 },
6341 /* PREFIX_VEX_0F3A09 */
6345 { "vroundpd", { XM, EXx, Ib }, 0 },
6348 /* PREFIX_VEX_0F3A0A */
6352 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6355 /* PREFIX_VEX_0F3A0B */
6359 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6362 /* PREFIX_VEX_0F3A0C */
6366 { "vblendps", { XM, Vex, EXx, Ib }, 0 },
6369 /* PREFIX_VEX_0F3A0D */
6373 { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
6376 /* PREFIX_VEX_0F3A0E */
6380 { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
6383 /* PREFIX_VEX_0F3A0F */
6387 { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
6390 /* PREFIX_VEX_0F3A14 */
6394 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6397 /* PREFIX_VEX_0F3A15 */
6401 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6404 /* PREFIX_VEX_0F3A16 */
6408 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6411 /* PREFIX_VEX_0F3A17 */
6415 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6418 /* PREFIX_VEX_0F3A18 */
6422 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6425 /* PREFIX_VEX_0F3A19 */
6429 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6432 /* PREFIX_VEX_0F3A1D */
6436 { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6439 /* PREFIX_VEX_0F3A20 */
6443 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6446 /* PREFIX_VEX_0F3A21 */
6450 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6453 /* PREFIX_VEX_0F3A22 */
6457 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6460 /* PREFIX_VEX_0F3A30 */
6464 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6467 /* PREFIX_VEX_0F3A31 */
6471 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6474 /* PREFIX_VEX_0F3A32 */
6478 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6481 /* PREFIX_VEX_0F3A33 */
6485 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6488 /* PREFIX_VEX_0F3A38 */
6492 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6495 /* PREFIX_VEX_0F3A39 */
6499 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6502 /* PREFIX_VEX_0F3A40 */
6506 { "vdpps", { XM, Vex, EXx, Ib }, 0 },
6509 /* PREFIX_VEX_0F3A41 */
6513 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6516 /* PREFIX_VEX_0F3A42 */
6520 { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
6523 /* PREFIX_VEX_0F3A44 */
6527 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 },
6530 /* PREFIX_VEX_0F3A46 */
6534 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6537 /* PREFIX_VEX_0F3A48 */
6541 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6544 /* PREFIX_VEX_0F3A49 */
6548 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6551 /* PREFIX_VEX_0F3A4A */
6555 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6558 /* PREFIX_VEX_0F3A4B */
6562 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6565 /* PREFIX_VEX_0F3A4C */
6569 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6572 /* PREFIX_VEX_0F3A5C */
6576 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6579 /* PREFIX_VEX_0F3A5D */
6583 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6586 /* PREFIX_VEX_0F3A5E */
6590 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6593 /* PREFIX_VEX_0F3A5F */
6597 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6600 /* PREFIX_VEX_0F3A60 */
6604 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6608 /* PREFIX_VEX_0F3A61 */
6612 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6615 /* PREFIX_VEX_0F3A62 */
6619 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6622 /* PREFIX_VEX_0F3A63 */
6626 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6629 /* PREFIX_VEX_0F3A68 */
6633 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6636 /* PREFIX_VEX_0F3A69 */
6640 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6643 /* PREFIX_VEX_0F3A6A */
6647 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6650 /* PREFIX_VEX_0F3A6B */
6654 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6657 /* PREFIX_VEX_0F3A6C */
6661 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6664 /* PREFIX_VEX_0F3A6D */
6668 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6671 /* PREFIX_VEX_0F3A6E */
6675 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6678 /* PREFIX_VEX_0F3A6F */
6682 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6685 /* PREFIX_VEX_0F3A78 */
6689 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6692 /* PREFIX_VEX_0F3A79 */
6696 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6699 /* PREFIX_VEX_0F3A7A */
6703 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6706 /* PREFIX_VEX_0F3A7B */
6710 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6713 /* PREFIX_VEX_0F3A7C */
6717 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6721 /* PREFIX_VEX_0F3A7D */
6725 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6728 /* PREFIX_VEX_0F3A7E */
6732 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6735 /* PREFIX_VEX_0F3A7F */
6739 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6742 /* PREFIX_VEX_0F3ACE */
6746 { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6749 /* PREFIX_VEX_0F3ACF */
6753 { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6756 /* PREFIX_VEX_0F3ADF */
6760 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6763 /* PREFIX_VEX_0F3AF0 */
6768 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6771 #define NEED_PREFIX_TABLE
6772 #include "i386-dis-evex.h"
6773 #undef NEED_PREFIX_TABLE
6776 static const struct dis386 x86_64_table[][2] = {
6779 { "pushP", { es }, 0 },
6784 { "popP", { es }, 0 },
6789 { "pushP", { cs }, 0 },
6794 { "pushP", { ss }, 0 },
6799 { "popP", { ss }, 0 },
6804 { "pushP", { ds }, 0 },
6809 { "popP", { ds }, 0 },
6814 { "daa", { XX }, 0 },
6819 { "das", { XX }, 0 },
6824 { "aaa", { XX }, 0 },
6829 { "aas", { XX }, 0 },
6834 { "pushaP", { XX }, 0 },
6839 { "popaP", { XX }, 0 },
6844 { MOD_TABLE (MOD_62_32BIT) },
6845 { EVEX_TABLE (EVEX_0F) },
6850 { "arpl", { Ew, Gw }, 0 },
6851 { "movs{lq|xd}", { Gv, Ed }, 0 },
6856 { "ins{R|}", { Yzr, indirDX }, 0 },
6857 { "ins{G|}", { Yzr, indirDX }, 0 },
6862 { "outs{R|}", { indirDXr, Xz }, 0 },
6863 { "outs{G|}", { indirDXr, Xz }, 0 },
6868 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6869 { REG_TABLE (REG_80) },
6874 { "Jcall{T|}", { Ap }, 0 },
6879 { MOD_TABLE (MOD_C4_32BIT) },
6880 { VEX_C4_TABLE (VEX_0F) },
6885 { MOD_TABLE (MOD_C5_32BIT) },
6886 { VEX_C5_TABLE (VEX_0F) },
6891 { "into", { XX }, 0 },
6896 { "aam", { Ib }, 0 },
6901 { "aad", { Ib }, 0 },
6906 { "callP", { Jv, BND }, 0 },
6907 { "call@", { Jv, BND }, 0 }
6912 { "jmpP", { Jv, BND }, 0 },
6913 { "jmp@", { Jv, BND }, 0 }
6918 { "Jjmp{T|}", { Ap }, 0 },
6921 /* X86_64_0F01_REG_0 */
6923 { "sgdt{Q|IQ}", { M }, 0 },
6924 { "sgdt", { M }, 0 },
6927 /* X86_64_0F01_REG_1 */
6929 { "sidt{Q|IQ}", { M }, 0 },
6930 { "sidt", { M }, 0 },
6933 /* X86_64_0F01_REG_2 */
6935 { "lgdt{Q|Q}", { M }, 0 },
6936 { "lgdt", { M }, 0 },
6939 /* X86_64_0F01_REG_3 */
6941 { "lidt{Q|Q}", { M }, 0 },
6942 { "lidt", { M }, 0 },
6946 static const struct dis386 three_byte_table[][256] = {
6948 /* THREE_BYTE_0F38 */
6951 { "pshufb", { MX, EM }, PREFIX_OPCODE },
6952 { "phaddw", { MX, EM }, PREFIX_OPCODE },
6953 { "phaddd", { MX, EM }, PREFIX_OPCODE },
6954 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
6955 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
6956 { "phsubw", { MX, EM }, PREFIX_OPCODE },
6957 { "phsubd", { MX, EM }, PREFIX_OPCODE },
6958 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
6960 { "psignb", { MX, EM }, PREFIX_OPCODE },
6961 { "psignw", { MX, EM }, PREFIX_OPCODE },
6962 { "psignd", { MX, EM }, PREFIX_OPCODE },
6963 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
6969 { PREFIX_TABLE (PREFIX_0F3810) },
6973 { PREFIX_TABLE (PREFIX_0F3814) },
6974 { PREFIX_TABLE (PREFIX_0F3815) },
6976 { PREFIX_TABLE (PREFIX_0F3817) },
6982 { "pabsb", { MX, EM }, PREFIX_OPCODE },
6983 { "pabsw", { MX, EM }, PREFIX_OPCODE },
6984 { "pabsd", { MX, EM }, PREFIX_OPCODE },
6987 { PREFIX_TABLE (PREFIX_0F3820) },
6988 { PREFIX_TABLE (PREFIX_0F3821) },
6989 { PREFIX_TABLE (PREFIX_0F3822) },
6990 { PREFIX_TABLE (PREFIX_0F3823) },
6991 { PREFIX_TABLE (PREFIX_0F3824) },
6992 { PREFIX_TABLE (PREFIX_0F3825) },
6996 { PREFIX_TABLE (PREFIX_0F3828) },
6997 { PREFIX_TABLE (PREFIX_0F3829) },
6998 { PREFIX_TABLE (PREFIX_0F382A) },
6999 { PREFIX_TABLE (PREFIX_0F382B) },
7005 { PREFIX_TABLE (PREFIX_0F3830) },
7006 { PREFIX_TABLE (PREFIX_0F3831) },
7007 { PREFIX_TABLE (PREFIX_0F3832) },
7008 { PREFIX_TABLE (PREFIX_0F3833) },
7009 { PREFIX_TABLE (PREFIX_0F3834) },
7010 { PREFIX_TABLE (PREFIX_0F3835) },
7012 { PREFIX_TABLE (PREFIX_0F3837) },
7014 { PREFIX_TABLE (PREFIX_0F3838) },
7015 { PREFIX_TABLE (PREFIX_0F3839) },
7016 { PREFIX_TABLE (PREFIX_0F383A) },
7017 { PREFIX_TABLE (PREFIX_0F383B) },
7018 { PREFIX_TABLE (PREFIX_0F383C) },
7019 { PREFIX_TABLE (PREFIX_0F383D) },
7020 { PREFIX_TABLE (PREFIX_0F383E) },
7021 { PREFIX_TABLE (PREFIX_0F383F) },
7023 { PREFIX_TABLE (PREFIX_0F3840) },
7024 { PREFIX_TABLE (PREFIX_0F3841) },
7095 { PREFIX_TABLE (PREFIX_0F3880) },
7096 { PREFIX_TABLE (PREFIX_0F3881) },
7097 { PREFIX_TABLE (PREFIX_0F3882) },
7176 { PREFIX_TABLE (PREFIX_0F38C8) },
7177 { PREFIX_TABLE (PREFIX_0F38C9) },
7178 { PREFIX_TABLE (PREFIX_0F38CA) },
7179 { PREFIX_TABLE (PREFIX_0F38CB) },
7180 { PREFIX_TABLE (PREFIX_0F38CC) },
7181 { PREFIX_TABLE (PREFIX_0F38CD) },
7183 { PREFIX_TABLE (PREFIX_0F38CF) },
7197 { PREFIX_TABLE (PREFIX_0F38DB) },
7198 { PREFIX_TABLE (PREFIX_0F38DC) },
7199 { PREFIX_TABLE (PREFIX_0F38DD) },
7200 { PREFIX_TABLE (PREFIX_0F38DE) },
7201 { PREFIX_TABLE (PREFIX_0F38DF) },
7221 { PREFIX_TABLE (PREFIX_0F38F0) },
7222 { PREFIX_TABLE (PREFIX_0F38F1) },
7226 { PREFIX_TABLE (PREFIX_0F38F5) },
7227 { PREFIX_TABLE (PREFIX_0F38F6) },
7230 { PREFIX_TABLE (PREFIX_0F38F8) },
7231 { PREFIX_TABLE (PREFIX_0F38F9) },
7239 /* THREE_BYTE_0F3A */
7251 { PREFIX_TABLE (PREFIX_0F3A08) },
7252 { PREFIX_TABLE (PREFIX_0F3A09) },
7253 { PREFIX_TABLE (PREFIX_0F3A0A) },
7254 { PREFIX_TABLE (PREFIX_0F3A0B) },
7255 { PREFIX_TABLE (PREFIX_0F3A0C) },
7256 { PREFIX_TABLE (PREFIX_0F3A0D) },
7257 { PREFIX_TABLE (PREFIX_0F3A0E) },
7258 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
7264 { PREFIX_TABLE (PREFIX_0F3A14) },
7265 { PREFIX_TABLE (PREFIX_0F3A15) },
7266 { PREFIX_TABLE (PREFIX_0F3A16) },
7267 { PREFIX_TABLE (PREFIX_0F3A17) },
7278 { PREFIX_TABLE (PREFIX_0F3A20) },
7279 { PREFIX_TABLE (PREFIX_0F3A21) },
7280 { PREFIX_TABLE (PREFIX_0F3A22) },
7314 { PREFIX_TABLE (PREFIX_0F3A40) },
7315 { PREFIX_TABLE (PREFIX_0F3A41) },
7316 { PREFIX_TABLE (PREFIX_0F3A42) },
7318 { PREFIX_TABLE (PREFIX_0F3A44) },
7350 { PREFIX_TABLE (PREFIX_0F3A60) },
7351 { PREFIX_TABLE (PREFIX_0F3A61) },
7352 { PREFIX_TABLE (PREFIX_0F3A62) },
7353 { PREFIX_TABLE (PREFIX_0F3A63) },
7471 { PREFIX_TABLE (PREFIX_0F3ACC) },
7473 { PREFIX_TABLE (PREFIX_0F3ACE) },
7474 { PREFIX_TABLE (PREFIX_0F3ACF) },
7492 { PREFIX_TABLE (PREFIX_0F3ADF) },
7532 static const struct dis386 xop_table[][256] = {
7685 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7686 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7687 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7695 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7696 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7703 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7704 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7705 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7713 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7714 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7718 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7719 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7722 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7740 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7752 { "vprotb", { XM, Vex_2src_1, Ib }, 0 },
7753 { "vprotw", { XM, Vex_2src_1, Ib }, 0 },
7754 { "vprotd", { XM, Vex_2src_1, Ib }, 0 },
7755 { "vprotq", { XM, Vex_2src_1, Ib }, 0 },
7765 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7766 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7767 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7768 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7801 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7802 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7803 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7804 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7828 { REG_TABLE (REG_XOP_TBM_01) },
7829 { REG_TABLE (REG_XOP_TBM_02) },
7847 { REG_TABLE (REG_XOP_LWPCB) },
7971 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7972 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7973 { "vfrczss", { XM, EXd }, 0 },
7974 { "vfrczsd", { XM, EXq }, 0 },
7989 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7990 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7991 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7992 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7993 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7994 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7995 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7996 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7998 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7999 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8000 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8001 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8044 { "vphaddbw", { XM, EXxmm }, 0 },
8045 { "vphaddbd", { XM, EXxmm }, 0 },
8046 { "vphaddbq", { XM, EXxmm }, 0 },
8049 { "vphaddwd", { XM, EXxmm }, 0 },
8050 { "vphaddwq", { XM, EXxmm }, 0 },
8055 { "vphadddq", { XM, EXxmm }, 0 },
8062 { "vphaddubw", { XM, EXxmm }, 0 },
8063 { "vphaddubd", { XM, EXxmm }, 0 },
8064 { "vphaddubq", { XM, EXxmm }, 0 },
8067 { "vphadduwd", { XM, EXxmm }, 0 },
8068 { "vphadduwq", { XM, EXxmm }, 0 },
8073 { "vphaddudq", { XM, EXxmm }, 0 },
8080 { "vphsubbw", { XM, EXxmm }, 0 },
8081 { "vphsubwd", { XM, EXxmm }, 0 },
8082 { "vphsubdq", { XM, EXxmm }, 0 },
8136 { "bextr", { Gv, Ev, Iq }, 0 },
8138 { REG_TABLE (REG_XOP_LWP) },
8408 static const struct dis386 vex_table[][256] = {
8430 { PREFIX_TABLE (PREFIX_VEX_0F10) },
8431 { PREFIX_TABLE (PREFIX_VEX_0F11) },
8432 { PREFIX_TABLE (PREFIX_VEX_0F12) },
8433 { MOD_TABLE (MOD_VEX_0F13) },
8434 { "vunpcklpX", { XM, Vex, EXx }, 0 },
8435 { "vunpckhpX", { XM, Vex, EXx }, 0 },
8436 { PREFIX_TABLE (PREFIX_VEX_0F16) },
8437 { MOD_TABLE (MOD_VEX_0F17) },
8457 { "vmovapX", { XM, EXx }, 0 },
8458 { "vmovapX", { EXxS, XM }, 0 },
8459 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8460 { MOD_TABLE (MOD_VEX_0F2B) },
8461 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8462 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8463 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8464 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8485 { PREFIX_TABLE (PREFIX_VEX_0F41) },
8486 { PREFIX_TABLE (PREFIX_VEX_0F42) },
8488 { PREFIX_TABLE (PREFIX_VEX_0F44) },
8489 { PREFIX_TABLE (PREFIX_VEX_0F45) },
8490 { PREFIX_TABLE (PREFIX_VEX_0F46) },
8491 { PREFIX_TABLE (PREFIX_VEX_0F47) },
8495 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8496 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8502 { MOD_TABLE (MOD_VEX_0F50) },
8503 { PREFIX_TABLE (PREFIX_VEX_0F51) },
8504 { PREFIX_TABLE (PREFIX_VEX_0F52) },
8505 { PREFIX_TABLE (PREFIX_VEX_0F53) },
8506 { "vandpX", { XM, Vex, EXx }, 0 },
8507 { "vandnpX", { XM, Vex, EXx }, 0 },
8508 { "vorpX", { XM, Vex, EXx }, 0 },
8509 { "vxorpX", { XM, Vex, EXx }, 0 },
8511 { PREFIX_TABLE (PREFIX_VEX_0F58) },
8512 { PREFIX_TABLE (PREFIX_VEX_0F59) },
8513 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8514 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8515 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8516 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8517 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8518 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8520 { PREFIX_TABLE (PREFIX_VEX_0F60) },
8521 { PREFIX_TABLE (PREFIX_VEX_0F61) },
8522 { PREFIX_TABLE (PREFIX_VEX_0F62) },
8523 { PREFIX_TABLE (PREFIX_VEX_0F63) },
8524 { PREFIX_TABLE (PREFIX_VEX_0F64) },
8525 { PREFIX_TABLE (PREFIX_VEX_0F65) },
8526 { PREFIX_TABLE (PREFIX_VEX_0F66) },
8527 { PREFIX_TABLE (PREFIX_VEX_0F67) },
8529 { PREFIX_TABLE (PREFIX_VEX_0F68) },
8530 { PREFIX_TABLE (PREFIX_VEX_0F69) },
8531 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8532 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8533 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8534 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8535 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8536 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8538 { PREFIX_TABLE (PREFIX_VEX_0F70) },
8539 { REG_TABLE (REG_VEX_0F71) },
8540 { REG_TABLE (REG_VEX_0F72) },
8541 { REG_TABLE (REG_VEX_0F73) },
8542 { PREFIX_TABLE (PREFIX_VEX_0F74) },
8543 { PREFIX_TABLE (PREFIX_VEX_0F75) },
8544 { PREFIX_TABLE (PREFIX_VEX_0F76) },
8545 { PREFIX_TABLE (PREFIX_VEX_0F77) },
8551 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8552 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8553 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8554 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8574 { PREFIX_TABLE (PREFIX_VEX_0F90) },
8575 { PREFIX_TABLE (PREFIX_VEX_0F91) },
8576 { PREFIX_TABLE (PREFIX_VEX_0F92) },
8577 { PREFIX_TABLE (PREFIX_VEX_0F93) },
8583 { PREFIX_TABLE (PREFIX_VEX_0F98) },
8584 { PREFIX_TABLE (PREFIX_VEX_0F99) },
8607 { REG_TABLE (REG_VEX_0FAE) },
8630 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8632 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8633 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8634 { "vshufpX", { XM, Vex, EXx, Ib }, 0 },
8646 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8647 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8648 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8649 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8650 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8651 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8652 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8653 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8655 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8656 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8657 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8658 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8659 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8660 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8661 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8662 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8664 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8665 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8666 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8667 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8668 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8669 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8670 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8671 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8673 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8674 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8675 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8676 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8677 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8678 { PREFIX_TABLE (PREFIX_VEX_0FED) },
8679 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8680 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8682 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8683 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8684 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8685 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8686 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8687 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8688 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8689 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8691 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8692 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8693 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8694 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8695 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8696 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8697 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8703 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8704 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8705 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8706 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8707 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8708 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8709 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8710 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8712 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8713 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8714 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8715 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8716 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8717 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8718 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8719 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8724 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8734 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8735 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8736 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8740 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8741 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8742 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8743 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8744 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8780 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8781 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8802 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8803 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8804 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8838 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8839 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8860 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8862 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8865 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8866 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8867 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8868 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8871 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8872 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8874 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8875 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8876 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8877 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8878 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8879 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8880 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8881 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8895 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8896 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8907 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8975 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8976 { REG_TABLE (REG_VEX_0F38F3) },
8978 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8979 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8980 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8994 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8995 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8996 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8999 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9004 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9005 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9006 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9008 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9009 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9010 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9017 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9022 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9026 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9030 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9031 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9032 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9048 { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9049 { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9050 { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9051 { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9057 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9058 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9066 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9067 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9068 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9077 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9078 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9079 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9098 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9099 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9102 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9103 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9104 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9105 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9111 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9112 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9113 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9114 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9115 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9116 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9117 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9118 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9129 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9130 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9131 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9132 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9134 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9135 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9136 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9225 { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9226 { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9244 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9264 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9284 #define NEED_OPCODE_TABLE
9285 #include "i386-dis-evex.h"
9286 #undef NEED_OPCODE_TABLE
9287 static const struct dis386 vex_len_table[][2] = {
9288 /* VEX_LEN_0F12_P_0_M_0 */
9290 { "vmovlps", { XM, Vex128, EXq }, 0 },
9293 /* VEX_LEN_0F12_P_0_M_1 */
9295 { "vmovhlps", { XM, Vex128, EXq }, 0 },
9298 /* VEX_LEN_0F12_P_2 */
9300 { "vmovlpd", { XM, Vex128, EXq }, 0 },
9303 /* VEX_LEN_0F13_M_0 */
9305 { "vmovlpX", { EXq, XM }, 0 },
9308 /* VEX_LEN_0F16_P_0_M_0 */
9310 { "vmovhps", { XM, Vex128, EXq }, 0 },
9313 /* VEX_LEN_0F16_P_0_M_1 */
9315 { "vmovlhps", { XM, Vex128, EXq }, 0 },
9318 /* VEX_LEN_0F16_P_2 */
9320 { "vmovhpd", { XM, Vex128, EXq }, 0 },
9323 /* VEX_LEN_0F17_M_0 */
9325 { "vmovhpX", { EXq, XM }, 0 },
9328 /* VEX_LEN_0F2A_P_1 */
9330 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9331 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9334 /* VEX_LEN_0F2A_P_3 */
9336 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9337 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9340 /* VEX_LEN_0F2C_P_1 */
9342 { "vcvttss2si", { Gv, EXdScalar }, 0 },
9343 { "vcvttss2si", { Gv, EXdScalar }, 0 },
9346 /* VEX_LEN_0F2C_P_3 */
9348 { "vcvttsd2si", { Gv, EXqScalar }, 0 },
9349 { "vcvttsd2si", { Gv, EXqScalar }, 0 },
9352 /* VEX_LEN_0F2D_P_1 */
9354 { "vcvtss2si", { Gv, EXdScalar }, 0 },
9355 { "vcvtss2si", { Gv, EXdScalar }, 0 },
9358 /* VEX_LEN_0F2D_P_3 */
9360 { "vcvtsd2si", { Gv, EXqScalar }, 0 },
9361 { "vcvtsd2si", { Gv, EXqScalar }, 0 },
9364 /* VEX_LEN_0F41_P_0 */
9367 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9369 /* VEX_LEN_0F41_P_2 */
9372 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9374 /* VEX_LEN_0F42_P_0 */
9377 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9379 /* VEX_LEN_0F42_P_2 */
9382 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9384 /* VEX_LEN_0F44_P_0 */
9386 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9388 /* VEX_LEN_0F44_P_2 */
9390 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9392 /* VEX_LEN_0F45_P_0 */
9395 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9397 /* VEX_LEN_0F45_P_2 */
9400 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9402 /* VEX_LEN_0F46_P_0 */
9405 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9407 /* VEX_LEN_0F46_P_2 */
9410 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9412 /* VEX_LEN_0F47_P_0 */
9415 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9417 /* VEX_LEN_0F47_P_2 */
9420 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9422 /* VEX_LEN_0F4A_P_0 */
9425 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9427 /* VEX_LEN_0F4A_P_2 */
9430 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9432 /* VEX_LEN_0F4B_P_0 */
9435 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9437 /* VEX_LEN_0F4B_P_2 */
9440 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9443 /* VEX_LEN_0F6E_P_2 */
9445 { "vmovK", { XMScalar, Edq }, 0 },
9448 /* VEX_LEN_0F77_P_1 */
9450 { "vzeroupper", { XX }, 0 },
9451 { "vzeroall", { XX }, 0 },
9454 /* VEX_LEN_0F7E_P_1 */
9456 { "vmovq", { XMScalar, EXqScalar }, 0 },
9459 /* VEX_LEN_0F7E_P_2 */
9461 { "vmovK", { Edq, XMScalar }, 0 },
9464 /* VEX_LEN_0F90_P_0 */
9466 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9469 /* VEX_LEN_0F90_P_2 */
9471 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9474 /* VEX_LEN_0F91_P_0 */
9476 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9479 /* VEX_LEN_0F91_P_2 */
9481 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9484 /* VEX_LEN_0F92_P_0 */
9486 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9489 /* VEX_LEN_0F92_P_2 */
9491 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9494 /* VEX_LEN_0F92_P_3 */
9496 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9499 /* VEX_LEN_0F93_P_0 */
9501 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9504 /* VEX_LEN_0F93_P_2 */
9506 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9509 /* VEX_LEN_0F93_P_3 */
9511 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9514 /* VEX_LEN_0F98_P_0 */
9516 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9519 /* VEX_LEN_0F98_P_2 */
9521 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9524 /* VEX_LEN_0F99_P_0 */
9526 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9529 /* VEX_LEN_0F99_P_2 */
9531 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9534 /* VEX_LEN_0FAE_R_2_M_0 */
9536 { "vldmxcsr", { Md }, 0 },
9539 /* VEX_LEN_0FAE_R_3_M_0 */
9541 { "vstmxcsr", { Md }, 0 },
9544 /* VEX_LEN_0FC4_P_2 */
9546 { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9549 /* VEX_LEN_0FC5_P_2 */
9551 { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9554 /* VEX_LEN_0FD6_P_2 */
9556 { "vmovq", { EXqScalarS, XMScalar }, 0 },
9559 /* VEX_LEN_0FF7_P_2 */
9561 { "vmaskmovdqu", { XM, XS }, 0 },
9564 /* VEX_LEN_0F3816_P_2 */
9567 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9570 /* VEX_LEN_0F3819_P_2 */
9573 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9576 /* VEX_LEN_0F381A_P_2_M_0 */
9579 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9582 /* VEX_LEN_0F3836_P_2 */
9585 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9588 /* VEX_LEN_0F3841_P_2 */
9590 { "vphminposuw", { XM, EXx }, 0 },
9593 /* VEX_LEN_0F385A_P_2_M_0 */
9596 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9599 /* VEX_LEN_0F38DB_P_2 */
9601 { "vaesimc", { XM, EXx }, 0 },
9604 /* VEX_LEN_0F38F2_P_0 */
9606 { "andnS", { Gdq, VexGdq, Edq }, 0 },
9609 /* VEX_LEN_0F38F3_R_1_P_0 */
9611 { "blsrS", { VexGdq, Edq }, 0 },
9614 /* VEX_LEN_0F38F3_R_2_P_0 */
9616 { "blsmskS", { VexGdq, Edq }, 0 },
9619 /* VEX_LEN_0F38F3_R_3_P_0 */
9621 { "blsiS", { VexGdq, Edq }, 0 },
9624 /* VEX_LEN_0F38F5_P_0 */
9626 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
9629 /* VEX_LEN_0F38F5_P_1 */
9631 { "pextS", { Gdq, VexGdq, Edq }, 0 },
9634 /* VEX_LEN_0F38F5_P_3 */
9636 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
9639 /* VEX_LEN_0F38F6_P_3 */
9641 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
9644 /* VEX_LEN_0F38F7_P_0 */
9646 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
9649 /* VEX_LEN_0F38F7_P_1 */
9651 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
9654 /* VEX_LEN_0F38F7_P_2 */
9656 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
9659 /* VEX_LEN_0F38F7_P_3 */
9661 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
9664 /* VEX_LEN_0F3A00_P_2 */
9667 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9670 /* VEX_LEN_0F3A01_P_2 */
9673 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9676 /* VEX_LEN_0F3A06_P_2 */
9679 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9682 /* VEX_LEN_0F3A14_P_2 */
9684 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9687 /* VEX_LEN_0F3A15_P_2 */
9689 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9692 /* VEX_LEN_0F3A16_P_2 */
9694 { "vpextrK", { Edq, XM, Ib }, 0 },
9697 /* VEX_LEN_0F3A17_P_2 */
9699 { "vextractps", { Edqd, XM, Ib }, 0 },
9702 /* VEX_LEN_0F3A18_P_2 */
9705 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9708 /* VEX_LEN_0F3A19_P_2 */
9711 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9714 /* VEX_LEN_0F3A20_P_2 */
9716 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
9719 /* VEX_LEN_0F3A21_P_2 */
9721 { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
9724 /* VEX_LEN_0F3A22_P_2 */
9726 { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 },
9729 /* VEX_LEN_0F3A30_P_2 */
9731 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9734 /* VEX_LEN_0F3A31_P_2 */
9736 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9739 /* VEX_LEN_0F3A32_P_2 */
9741 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9744 /* VEX_LEN_0F3A33_P_2 */
9746 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9749 /* VEX_LEN_0F3A38_P_2 */
9752 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9755 /* VEX_LEN_0F3A39_P_2 */
9758 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9761 /* VEX_LEN_0F3A41_P_2 */
9763 { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
9766 /* VEX_LEN_0F3A46_P_2 */
9769 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9772 /* VEX_LEN_0F3A60_P_2 */
9774 { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9777 /* VEX_LEN_0F3A61_P_2 */
9779 { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9782 /* VEX_LEN_0F3A62_P_2 */
9784 { "vpcmpistrm", { XM, EXx, Ib }, 0 },
9787 /* VEX_LEN_0F3A63_P_2 */
9789 { "vpcmpistri", { XM, EXx, Ib }, 0 },
9792 /* VEX_LEN_0F3A6A_P_2 */
9794 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9797 /* VEX_LEN_0F3A6B_P_2 */
9799 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9802 /* VEX_LEN_0F3A6E_P_2 */
9804 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9807 /* VEX_LEN_0F3A6F_P_2 */
9809 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9812 /* VEX_LEN_0F3A7A_P_2 */
9814 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9817 /* VEX_LEN_0F3A7B_P_2 */
9819 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9822 /* VEX_LEN_0F3A7E_P_2 */
9824 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9827 /* VEX_LEN_0F3A7F_P_2 */
9829 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9832 /* VEX_LEN_0F3ADF_P_2 */
9834 { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9837 /* VEX_LEN_0F3AF0_P_3 */
9839 { "rorxS", { Gdq, Edq, Ib }, 0 },
9842 /* VEX_LEN_0FXOP_08_CC */
9844 { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 },
9847 /* VEX_LEN_0FXOP_08_CD */
9849 { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 },
9852 /* VEX_LEN_0FXOP_08_CE */
9854 { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 },
9857 /* VEX_LEN_0FXOP_08_CF */
9859 { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 },
9862 /* VEX_LEN_0FXOP_08_EC */
9864 { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 },
9867 /* VEX_LEN_0FXOP_08_ED */
9869 { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 },
9872 /* VEX_LEN_0FXOP_08_EE */
9874 { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 },
9877 /* VEX_LEN_0FXOP_08_EF */
9879 { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 },
9882 /* VEX_LEN_0FXOP_09_80 */
9884 { "vfrczps", { XM, EXxmm }, 0 },
9885 { "vfrczps", { XM, EXymmq }, 0 },
9888 /* VEX_LEN_0FXOP_09_81 */
9890 { "vfrczpd", { XM, EXxmm }, 0 },
9891 { "vfrczpd", { XM, EXymmq }, 0 },
9895 static const struct dis386 evex_len_table[][3] = {
9896 #define NEED_EVEX_LEN_TABLE
9897 #include "i386-dis-evex.h"
9898 #undef NEED_EVEX_LEN_TABLE
9901 static const struct dis386 vex_w_table[][2] = {
9903 /* VEX_W_0F41_P_0_LEN_1 */
9904 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9905 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9908 /* VEX_W_0F41_P_2_LEN_1 */
9909 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9910 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9913 /* VEX_W_0F42_P_0_LEN_1 */
9914 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9915 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9918 /* VEX_W_0F42_P_2_LEN_1 */
9919 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9920 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9923 /* VEX_W_0F44_P_0_LEN_0 */
9924 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9925 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9928 /* VEX_W_0F44_P_2_LEN_0 */
9929 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9930 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9933 /* VEX_W_0F45_P_0_LEN_1 */
9934 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9935 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9938 /* VEX_W_0F45_P_2_LEN_1 */
9939 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9940 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9943 /* VEX_W_0F46_P_0_LEN_1 */
9944 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9945 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9948 /* VEX_W_0F46_P_2_LEN_1 */
9949 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9950 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9953 /* VEX_W_0F47_P_0_LEN_1 */
9954 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9955 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9958 /* VEX_W_0F47_P_2_LEN_1 */
9959 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9960 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9963 /* VEX_W_0F4A_P_0_LEN_1 */
9964 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9965 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9968 /* VEX_W_0F4A_P_2_LEN_1 */
9969 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9970 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9973 /* VEX_W_0F4B_P_0_LEN_1 */
9974 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9975 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9978 /* VEX_W_0F4B_P_2_LEN_1 */
9979 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9982 /* VEX_W_0F90_P_0_LEN_0 */
9983 { "kmovw", { MaskG, MaskE }, 0 },
9984 { "kmovq", { MaskG, MaskE }, 0 },
9987 /* VEX_W_0F90_P_2_LEN_0 */
9988 { "kmovb", { MaskG, MaskBDE }, 0 },
9989 { "kmovd", { MaskG, MaskBDE }, 0 },
9992 /* VEX_W_0F91_P_0_LEN_0 */
9993 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9994 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9997 /* VEX_W_0F91_P_2_LEN_0 */
9998 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9999 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10002 /* VEX_W_0F92_P_0_LEN_0 */
10003 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10006 /* VEX_W_0F92_P_2_LEN_0 */
10007 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10010 /* VEX_W_0F92_P_3_LEN_0 */
10011 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10012 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10015 /* VEX_W_0F93_P_0_LEN_0 */
10016 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10019 /* VEX_W_0F93_P_2_LEN_0 */
10020 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10023 /* VEX_W_0F93_P_3_LEN_0 */
10024 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10025 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10028 /* VEX_W_0F98_P_0_LEN_0 */
10029 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10030 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10033 /* VEX_W_0F98_P_2_LEN_0 */
10034 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10035 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10038 /* VEX_W_0F99_P_0_LEN_0 */
10039 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10040 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10043 /* VEX_W_0F99_P_2_LEN_0 */
10044 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10045 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10048 /* VEX_W_0FC4_P_2 */
10049 { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
10052 /* VEX_W_0FC5_P_2 */
10053 { "vpextrw", { Gdq, XS, Ib }, 0 },
10056 /* VEX_W_0F380C_P_2 */
10057 { "vpermilps", { XM, Vex, EXx }, 0 },
10060 /* VEX_W_0F380D_P_2 */
10061 { "vpermilpd", { XM, Vex, EXx }, 0 },
10064 /* VEX_W_0F380E_P_2 */
10065 { "vtestps", { XM, EXx }, 0 },
10068 /* VEX_W_0F380F_P_2 */
10069 { "vtestpd", { XM, EXx }, 0 },
10072 /* VEX_W_0F3816_P_2 */
10073 { "vpermps", { XM, Vex, EXx }, 0 },
10076 /* VEX_W_0F3818_P_2 */
10077 { "vbroadcastss", { XM, EXxmm_md }, 0 },
10080 /* VEX_W_0F3819_P_2 */
10081 { "vbroadcastsd", { XM, EXxmm_mq }, 0 },
10084 /* VEX_W_0F381A_P_2_M_0 */
10085 { "vbroadcastf128", { XM, Mxmm }, 0 },
10088 /* VEX_W_0F382C_P_2_M_0 */
10089 { "vmaskmovps", { XM, Vex, Mx }, 0 },
10092 /* VEX_W_0F382D_P_2_M_0 */
10093 { "vmaskmovpd", { XM, Vex, Mx }, 0 },
10096 /* VEX_W_0F382E_P_2_M_0 */
10097 { "vmaskmovps", { Mx, Vex, XM }, 0 },
10100 /* VEX_W_0F382F_P_2_M_0 */
10101 { "vmaskmovpd", { Mx, Vex, XM }, 0 },
10104 /* VEX_W_0F3836_P_2 */
10105 { "vpermd", { XM, Vex, EXx }, 0 },
10108 /* VEX_W_0F3846_P_2 */
10109 { "vpsravd", { XM, Vex, EXx }, 0 },
10112 /* VEX_W_0F3858_P_2 */
10113 { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10116 /* VEX_W_0F3859_P_2 */
10117 { "vpbroadcastq", { XM, EXxmm_mq }, 0 },
10120 /* VEX_W_0F385A_P_2_M_0 */
10121 { "vbroadcasti128", { XM, Mxmm }, 0 },
10124 /* VEX_W_0F3878_P_2 */
10125 { "vpbroadcastb", { XM, EXxmm_mb }, 0 },
10128 /* VEX_W_0F3879_P_2 */
10129 { "vpbroadcastw", { XM, EXxmm_mw }, 0 },
10132 /* VEX_W_0F38CF_P_2 */
10133 { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10136 /* VEX_W_0F3A00_P_2 */
10138 { "vpermq", { XM, EXx, Ib }, 0 },
10141 /* VEX_W_0F3A01_P_2 */
10143 { "vpermpd", { XM, EXx, Ib }, 0 },
10146 /* VEX_W_0F3A02_P_2 */
10147 { "vpblendd", { XM, Vex, EXx, Ib }, 0 },
10150 /* VEX_W_0F3A04_P_2 */
10151 { "vpermilps", { XM, EXx, Ib }, 0 },
10154 /* VEX_W_0F3A05_P_2 */
10155 { "vpermilpd", { XM, EXx, Ib }, 0 },
10158 /* VEX_W_0F3A06_P_2 */
10159 { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 },
10162 /* VEX_W_0F3A14_P_2 */
10163 { "vpextrb", { Edqb, XM, Ib }, 0 },
10166 /* VEX_W_0F3A15_P_2 */
10167 { "vpextrw", { Edqw, XM, Ib }, 0 },
10170 /* VEX_W_0F3A18_P_2 */
10171 { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 },
10174 /* VEX_W_0F3A19_P_2 */
10175 { "vextractf128", { EXxmm, XM, Ib }, 0 },
10178 /* VEX_W_0F3A20_P_2 */
10179 { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
10182 /* VEX_W_0F3A30_P_2_LEN_0 */
10183 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10184 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10187 /* VEX_W_0F3A31_P_2_LEN_0 */
10188 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10189 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10192 /* VEX_W_0F3A32_P_2_LEN_0 */
10193 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10194 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10197 /* VEX_W_0F3A33_P_2_LEN_0 */
10198 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10199 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10202 /* VEX_W_0F3A38_P_2 */
10203 { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 },
10206 /* VEX_W_0F3A39_P_2 */
10207 { "vextracti128", { EXxmm, XM, Ib }, 0 },
10210 /* VEX_W_0F3A46_P_2 */
10211 { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
10214 /* VEX_W_0F3A48_P_2 */
10215 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10216 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10219 /* VEX_W_0F3A49_P_2 */
10220 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10221 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10224 /* VEX_W_0F3A4A_P_2 */
10225 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 },
10228 /* VEX_W_0F3A4B_P_2 */
10229 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 },
10232 /* VEX_W_0F3A4C_P_2 */
10233 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
10236 /* VEX_W_0F3ACE_P_2 */
10238 { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10241 /* VEX_W_0F3ACF_P_2 */
10243 { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 },
10245 #define NEED_VEX_W_TABLE
10246 #include "i386-dis-evex.h"
10247 #undef NEED_VEX_W_TABLE
10250 static const struct dis386 mod_table[][2] = {
10253 { "leaS", { Gv, M }, 0 },
10258 { RM_TABLE (RM_C6_REG_7) },
10263 { RM_TABLE (RM_C7_REG_7) },
10267 { "Jcall^", { indirEp }, 0 },
10271 { "Jjmp^", { indirEp }, 0 },
10274 /* MOD_0F01_REG_0 */
10275 { X86_64_TABLE (X86_64_0F01_REG_0) },
10276 { RM_TABLE (RM_0F01_REG_0) },
10279 /* MOD_0F01_REG_1 */
10280 { X86_64_TABLE (X86_64_0F01_REG_1) },
10281 { RM_TABLE (RM_0F01_REG_1) },
10284 /* MOD_0F01_REG_2 */
10285 { X86_64_TABLE (X86_64_0F01_REG_2) },
10286 { RM_TABLE (RM_0F01_REG_2) },
10289 /* MOD_0F01_REG_3 */
10290 { X86_64_TABLE (X86_64_0F01_REG_3) },
10291 { RM_TABLE (RM_0F01_REG_3) },
10294 /* MOD_0F01_REG_5 */
10295 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
10296 { RM_TABLE (RM_0F01_REG_5) },
10299 /* MOD_0F01_REG_7 */
10300 { "invlpg", { Mb }, 0 },
10301 { RM_TABLE (RM_0F01_REG_7) },
10304 /* MOD_0F12_PREFIX_0 */
10305 { "movlps", { XM, EXq }, PREFIX_OPCODE },
10306 { "movhlps", { XM, EXq }, PREFIX_OPCODE },
10310 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
10313 /* MOD_0F16_PREFIX_0 */
10314 { "movhps", { XM, EXq }, 0 },
10315 { "movlhps", { XM, EXq }, 0 },
10319 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
10322 /* MOD_0F18_REG_0 */
10323 { "prefetchnta", { Mb }, 0 },
10326 /* MOD_0F18_REG_1 */
10327 { "prefetcht0", { Mb }, 0 },
10330 /* MOD_0F18_REG_2 */
10331 { "prefetcht1", { Mb }, 0 },
10334 /* MOD_0F18_REG_3 */
10335 { "prefetcht2", { Mb }, 0 },
10338 /* MOD_0F18_REG_4 */
10339 { "nop/reserved", { Mb }, 0 },
10342 /* MOD_0F18_REG_5 */
10343 { "nop/reserved", { Mb }, 0 },
10346 /* MOD_0F18_REG_6 */
10347 { "nop/reserved", { Mb }, 0 },
10350 /* MOD_0F18_REG_7 */
10351 { "nop/reserved", { Mb }, 0 },
10354 /* MOD_0F1A_PREFIX_0 */
10355 { "bndldx", { Gbnd, Mv_bnd }, 0 },
10356 { "nopQ", { Ev }, 0 },
10359 /* MOD_0F1B_PREFIX_0 */
10360 { "bndstx", { Mv_bnd, Gbnd }, 0 },
10361 { "nopQ", { Ev }, 0 },
10364 /* MOD_0F1B_PREFIX_1 */
10365 { "bndmk", { Gbnd, Mv_bnd }, 0 },
10366 { "nopQ", { Ev }, 0 },
10369 /* MOD_0F1C_PREFIX_0 */
10370 { REG_TABLE (REG_0F1C_MOD_0) },
10371 { "nopQ", { Ev }, 0 },
10374 /* MOD_0F1E_PREFIX_1 */
10375 { "nopQ", { Ev }, 0 },
10376 { REG_TABLE (REG_0F1E_MOD_3) },
10381 { "movL", { Rd, Td }, 0 },
10386 { "movL", { Td, Rd }, 0 },
10389 /* MOD_0F2B_PREFIX_0 */
10390 {"movntps", { Mx, XM }, PREFIX_OPCODE },
10393 /* MOD_0F2B_PREFIX_1 */
10394 {"movntss", { Md, XM }, PREFIX_OPCODE },
10397 /* MOD_0F2B_PREFIX_2 */
10398 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
10401 /* MOD_0F2B_PREFIX_3 */
10402 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
10407 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
10410 /* MOD_0F71_REG_2 */
10412 { "psrlw", { MS, Ib }, 0 },
10415 /* MOD_0F71_REG_4 */
10417 { "psraw", { MS, Ib }, 0 },
10420 /* MOD_0F71_REG_6 */
10422 { "psllw", { MS, Ib }, 0 },
10425 /* MOD_0F72_REG_2 */
10427 { "psrld", { MS, Ib }, 0 },
10430 /* MOD_0F72_REG_4 */
10432 { "psrad", { MS, Ib }, 0 },
10435 /* MOD_0F72_REG_6 */
10437 { "pslld", { MS, Ib }, 0 },
10440 /* MOD_0F73_REG_2 */
10442 { "psrlq", { MS, Ib }, 0 },
10445 /* MOD_0F73_REG_3 */
10447 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10450 /* MOD_0F73_REG_6 */
10452 { "psllq", { MS, Ib }, 0 },
10455 /* MOD_0F73_REG_7 */
10457 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10460 /* MOD_0FAE_REG_0 */
10461 { "fxsave", { FXSAVE }, 0 },
10462 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10465 /* MOD_0FAE_REG_1 */
10466 { "fxrstor", { FXSAVE }, 0 },
10467 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10470 /* MOD_0FAE_REG_2 */
10471 { "ldmxcsr", { Md }, 0 },
10472 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10475 /* MOD_0FAE_REG_3 */
10476 { "stmxcsr", { Md }, 0 },
10477 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10480 /* MOD_0FAE_REG_4 */
10481 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
10482 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
10485 /* MOD_0FAE_REG_5 */
10486 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
10487 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
10490 /* MOD_0FAE_REG_6 */
10491 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
10492 { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
10495 /* MOD_0FAE_REG_7 */
10496 { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
10497 { RM_TABLE (RM_0FAE_REG_7) },
10501 { "lssS", { Gv, Mp }, 0 },
10505 { "lfsS", { Gv, Mp }, 0 },
10509 { "lgsS", { Gv, Mp }, 0 },
10513 { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
10516 /* MOD_0FC7_REG_3 */
10517 { "xrstors", { FXSAVE }, 0 },
10520 /* MOD_0FC7_REG_4 */
10521 { "xsavec", { FXSAVE }, 0 },
10524 /* MOD_0FC7_REG_5 */
10525 { "xsaves", { FXSAVE }, 0 },
10528 /* MOD_0FC7_REG_6 */
10529 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
10530 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
10533 /* MOD_0FC7_REG_7 */
10534 { "vmptrst", { Mq }, 0 },
10535 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
10540 { "pmovmskb", { Gdq, MS }, 0 },
10543 /* MOD_0FE7_PREFIX_2 */
10544 { "movntdq", { Mx, XM }, 0 },
10547 /* MOD_0FF0_PREFIX_3 */
10548 { "lddqu", { XM, M }, 0 },
10551 /* MOD_0F382A_PREFIX_2 */
10552 { "movntdqa", { XM, Mx }, 0 },
10555 /* MOD_0F38F5_PREFIX_2 */
10556 { "wrussK", { M, Gdq }, PREFIX_OPCODE },
10559 /* MOD_0F38F6_PREFIX_0 */
10560 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
10563 /* MOD_0F38F8_PREFIX_2 */
10564 { "movdir64b", { Gva, M }, PREFIX_OPCODE },
10567 /* MOD_0F38F9_PREFIX_0 */
10568 { "movdiri", { Em, Gv }, PREFIX_OPCODE },
10572 { "bound{S|}", { Gv, Ma }, 0 },
10573 { EVEX_TABLE (EVEX_0F) },
10577 { "lesS", { Gv, Mp }, 0 },
10578 { VEX_C4_TABLE (VEX_0F) },
10582 { "ldsS", { Gv, Mp }, 0 },
10583 { VEX_C5_TABLE (VEX_0F) },
10586 /* MOD_VEX_0F12_PREFIX_0 */
10587 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10588 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10592 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10595 /* MOD_VEX_0F16_PREFIX_0 */
10596 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10597 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10601 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10605 { "vmovntpX", { Mx, XM }, 0 },
10608 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10610 { "kandw", { MaskG, MaskVex, MaskR }, 0 },
10613 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10615 { "kandq", { MaskG, MaskVex, MaskR }, 0 },
10618 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10620 { "kandb", { MaskG, MaskVex, MaskR }, 0 },
10623 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10625 { "kandd", { MaskG, MaskVex, MaskR }, 0 },
10628 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10630 { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
10633 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10635 { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
10638 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10640 { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
10643 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10645 { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
10648 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10650 { "knotw", { MaskG, MaskR }, 0 },
10653 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10655 { "knotq", { MaskG, MaskR }, 0 },
10658 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10660 { "knotb", { MaskG, MaskR }, 0 },
10663 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10665 { "knotd", { MaskG, MaskR }, 0 },
10668 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10670 { "korw", { MaskG, MaskVex, MaskR }, 0 },
10673 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10675 { "korq", { MaskG, MaskVex, MaskR }, 0 },
10678 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10680 { "korb", { MaskG, MaskVex, MaskR }, 0 },
10683 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10685 { "kord", { MaskG, MaskVex, MaskR }, 0 },
10688 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10690 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
10693 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10695 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
10698 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10700 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
10703 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10705 { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
10708 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10710 { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
10713 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10715 { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
10718 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10720 { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
10723 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10725 { "kxord", { MaskG, MaskVex, MaskR }, 0 },
10728 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10730 { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
10733 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10735 { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
10738 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10740 { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
10743 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10745 { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
10748 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10750 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
10753 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10755 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
10758 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10760 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
10765 { "vmovmskpX", { Gdq, XS }, 0 },
10768 /* MOD_VEX_0F71_REG_2 */
10770 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10773 /* MOD_VEX_0F71_REG_4 */
10775 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10778 /* MOD_VEX_0F71_REG_6 */
10780 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10783 /* MOD_VEX_0F72_REG_2 */
10785 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10788 /* MOD_VEX_0F72_REG_4 */
10790 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10793 /* MOD_VEX_0F72_REG_6 */
10795 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10798 /* MOD_VEX_0F73_REG_2 */
10800 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10803 /* MOD_VEX_0F73_REG_3 */
10805 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10808 /* MOD_VEX_0F73_REG_6 */
10810 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10813 /* MOD_VEX_0F73_REG_7 */
10815 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10818 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10819 { "kmovw", { Ew, MaskG }, 0 },
10823 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10824 { "kmovq", { Eq, MaskG }, 0 },
10828 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10829 { "kmovb", { Eb, MaskG }, 0 },
10833 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10834 { "kmovd", { Ed, MaskG }, 0 },
10838 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10840 { "kmovw", { MaskG, Rdq }, 0 },
10843 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10845 { "kmovb", { MaskG, Rdq }, 0 },
10848 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
10850 { "kmovd", { MaskG, Rdq }, 0 },
10853 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
10855 { "kmovq", { MaskG, Rdq }, 0 },
10858 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10860 { "kmovw", { Gdq, MaskR }, 0 },
10863 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10865 { "kmovb", { Gdq, MaskR }, 0 },
10868 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
10870 { "kmovd", { Gdq, MaskR }, 0 },
10873 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
10875 { "kmovq", { Gdq, MaskR }, 0 },
10878 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10880 { "kortestw", { MaskG, MaskR }, 0 },
10883 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10885 { "kortestq", { MaskG, MaskR }, 0 },
10888 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10890 { "kortestb", { MaskG, MaskR }, 0 },
10893 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10895 { "kortestd", { MaskG, MaskR }, 0 },
10898 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10900 { "ktestw", { MaskG, MaskR }, 0 },
10903 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10905 { "ktestq", { MaskG, MaskR }, 0 },
10908 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10910 { "ktestb", { MaskG, MaskR }, 0 },
10913 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10915 { "ktestd", { MaskG, MaskR }, 0 },
10918 /* MOD_VEX_0FAE_REG_2 */
10919 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10922 /* MOD_VEX_0FAE_REG_3 */
10923 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10926 /* MOD_VEX_0FD7_PREFIX_2 */
10928 { "vpmovmskb", { Gdq, XS }, 0 },
10931 /* MOD_VEX_0FE7_PREFIX_2 */
10932 { "vmovntdq", { Mx, XM }, 0 },
10935 /* MOD_VEX_0FF0_PREFIX_3 */
10936 { "vlddqu", { XM, M }, 0 },
10939 /* MOD_VEX_0F381A_PREFIX_2 */
10940 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10943 /* MOD_VEX_0F382A_PREFIX_2 */
10944 { "vmovntdqa", { XM, Mx }, 0 },
10947 /* MOD_VEX_0F382C_PREFIX_2 */
10948 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10951 /* MOD_VEX_0F382D_PREFIX_2 */
10952 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10955 /* MOD_VEX_0F382E_PREFIX_2 */
10956 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10959 /* MOD_VEX_0F382F_PREFIX_2 */
10960 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10963 /* MOD_VEX_0F385A_PREFIX_2 */
10964 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10967 /* MOD_VEX_0F388C_PREFIX_2 */
10968 { "vpmaskmov%LW", { XM, Vex, Mx }, 0 },
10971 /* MOD_VEX_0F388E_PREFIX_2 */
10972 { "vpmaskmov%LW", { Mx, Vex, XM }, 0 },
10975 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10977 { "kshiftrb", { MaskG, MaskR, Ib }, 0 },
10980 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10982 { "kshiftrw", { MaskG, MaskR, Ib }, 0 },
10985 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10987 { "kshiftrd", { MaskG, MaskR, Ib }, 0 },
10990 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10992 { "kshiftrq", { MaskG, MaskR, Ib }, 0 },
10995 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10997 { "kshiftlb", { MaskG, MaskR, Ib }, 0 },
11000 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
11002 { "kshiftlw", { MaskG, MaskR, Ib }, 0 },
11005 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
11007 { "kshiftld", { MaskG, MaskR, Ib }, 0 },
11010 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
11012 { "kshiftlq", { MaskG, MaskR, Ib }, 0 },
11014 #define NEED_MOD_TABLE
11015 #include "i386-dis-evex.h"
11016 #undef NEED_MOD_TABLE
11019 static const struct dis386 rm_table[][8] = {
11022 { "xabort", { Skip_MODRM, Ib }, 0 },
11026 { "xbeginT", { Skip_MODRM, Jv }, 0 },
11029 /* RM_0F01_REG_0 */
11030 { "enclv", { Skip_MODRM }, 0 },
11031 { "vmcall", { Skip_MODRM }, 0 },
11032 { "vmlaunch", { Skip_MODRM }, 0 },
11033 { "vmresume", { Skip_MODRM }, 0 },
11034 { "vmxoff", { Skip_MODRM }, 0 },
11035 { "pconfig", { Skip_MODRM }, 0 },
11038 /* RM_0F01_REG_1 */
11039 { "monitor", { { OP_Monitor, 0 } }, 0 },
11040 { "mwait", { { OP_Mwait, 0 } }, 0 },
11041 { "clac", { Skip_MODRM }, 0 },
11042 { "stac", { Skip_MODRM }, 0 },
11046 { "encls", { Skip_MODRM }, 0 },
11049 /* RM_0F01_REG_2 */
11050 { "xgetbv", { Skip_MODRM }, 0 },
11051 { "xsetbv", { Skip_MODRM }, 0 },
11054 { "vmfunc", { Skip_MODRM }, 0 },
11055 { "xend", { Skip_MODRM }, 0 },
11056 { "xtest", { Skip_MODRM }, 0 },
11057 { "enclu", { Skip_MODRM }, 0 },
11060 /* RM_0F01_REG_3 */
11061 { "vmrun", { Skip_MODRM }, 0 },
11062 { "vmmcall", { Skip_MODRM }, 0 },
11063 { "vmload", { Skip_MODRM }, 0 },
11064 { "vmsave", { Skip_MODRM }, 0 },
11065 { "stgi", { Skip_MODRM }, 0 },
11066 { "clgi", { Skip_MODRM }, 0 },
11067 { "skinit", { Skip_MODRM }, 0 },
11068 { "invlpga", { Skip_MODRM }, 0 },
11071 /* RM_0F01_REG_5 */
11072 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
11074 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
11078 { "rdpkru", { Skip_MODRM }, 0 },
11079 { "wrpkru", { Skip_MODRM }, 0 },
11082 /* RM_0F01_REG_7 */
11083 { "swapgs", { Skip_MODRM }, 0 },
11084 { "rdtscp", { Skip_MODRM }, 0 },
11085 { "monitorx", { { OP_Monitor, 0 } }, 0 },
11086 { "mwaitx", { { OP_Mwaitx, 0 } }, 0 },
11087 { "clzero", { Skip_MODRM }, 0 },
11090 /* RM_0F1E_MOD_3_REG_7 */
11091 { "nopQ", { Ev }, 0 },
11092 { "nopQ", { Ev }, 0 },
11093 { "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
11094 { "endbr32", { Skip_MODRM }, PREFIX_OPCODE },
11095 { "nopQ", { Ev }, 0 },
11096 { "nopQ", { Ev }, 0 },
11097 { "nopQ", { Ev }, 0 },
11098 { "nopQ", { Ev }, 0 },
11101 /* RM_0FAE_REG_6 */
11102 { "mfence", { Skip_MODRM }, 0 },
11105 /* RM_0FAE_REG_7 */
11106 { "sfence", { Skip_MODRM }, 0 },
11111 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11113 /* We use the high bit to indicate different name for the same
11115 #define REP_PREFIX (0xf3 | 0x100)
11116 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11117 #define XRELEASE_PREFIX (0xf3 | 0x400)
11118 #define BND_PREFIX (0xf2 | 0x400)
11119 #define NOTRACK_PREFIX (0x3e | 0x100)
11124 int newrex, i, length;
11130 last_lock_prefix = -1;
11131 last_repz_prefix = -1;
11132 last_repnz_prefix = -1;
11133 last_data_prefix = -1;
11134 last_addr_prefix = -1;
11135 last_rex_prefix = -1;
11136 last_seg_prefix = -1;
11138 active_seg_prefix = 0;
11139 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11140 all_prefixes[i] = 0;
11143 /* The maximum instruction length is 15bytes. */
11144 while (length < MAX_CODE_LENGTH - 1)
11146 FETCH_DATA (the_info, codep + 1);
11150 /* REX prefixes family. */
11167 if (address_mode == mode_64bit)
11171 last_rex_prefix = i;
11174 prefixes |= PREFIX_REPZ;
11175 last_repz_prefix = i;
11178 prefixes |= PREFIX_REPNZ;
11179 last_repnz_prefix = i;
11182 prefixes |= PREFIX_LOCK;
11183 last_lock_prefix = i;
11186 prefixes |= PREFIX_CS;
11187 last_seg_prefix = i;
11188 active_seg_prefix = PREFIX_CS;
11191 prefixes |= PREFIX_SS;
11192 last_seg_prefix = i;
11193 active_seg_prefix = PREFIX_SS;
11196 prefixes |= PREFIX_DS;
11197 last_seg_prefix = i;
11198 active_seg_prefix = PREFIX_DS;
11201 prefixes |= PREFIX_ES;
11202 last_seg_prefix = i;
11203 active_seg_prefix = PREFIX_ES;
11206 prefixes |= PREFIX_FS;
11207 last_seg_prefix = i;
11208 active_seg_prefix = PREFIX_FS;
11211 prefixes |= PREFIX_GS;
11212 last_seg_prefix = i;
11213 active_seg_prefix = PREFIX_GS;
11216 prefixes |= PREFIX_DATA;
11217 last_data_prefix = i;
11220 prefixes |= PREFIX_ADDR;
11221 last_addr_prefix = i;
11224 /* fwait is really an instruction. If there are prefixes
11225 before the fwait, they belong to the fwait, *not* to the
11226 following instruction. */
11228 if (prefixes || rex)
11230 prefixes |= PREFIX_FWAIT;
11232 /* This ensures that the previous REX prefixes are noticed
11233 as unused prefixes, as in the return case below. */
11237 prefixes = PREFIX_FWAIT;
11242 /* Rex is ignored when followed by another prefix. */
11248 if (*codep != FWAIT_OPCODE)
11249 all_prefixes[i++] = *codep;
11257 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11260 static const char *
11261 prefix_name (int pref, int sizeflag)
11263 static const char *rexes [16] =
11266 "rex.B", /* 0x41 */
11267 "rex.X", /* 0x42 */
11268 "rex.XB", /* 0x43 */
11269 "rex.R", /* 0x44 */
11270 "rex.RB", /* 0x45 */
11271 "rex.RX", /* 0x46 */
11272 "rex.RXB", /* 0x47 */
11273 "rex.W", /* 0x48 */
11274 "rex.WB", /* 0x49 */
11275 "rex.WX", /* 0x4a */
11276 "rex.WXB", /* 0x4b */
11277 "rex.WR", /* 0x4c */
11278 "rex.WRB", /* 0x4d */
11279 "rex.WRX", /* 0x4e */
11280 "rex.WRXB", /* 0x4f */
11285 /* REX prefixes family. */
11302 return rexes [pref - 0x40];
11322 return (sizeflag & DFLAG) ? "data16" : "data32";
11324 if (address_mode == mode_64bit)
11325 return (sizeflag & AFLAG) ? "addr32" : "addr64";
11327 return (sizeflag & AFLAG) ? "addr16" : "addr32";
11332 case XACQUIRE_PREFIX:
11334 case XRELEASE_PREFIX:
11338 case NOTRACK_PREFIX:
11345 static char op_out[MAX_OPERANDS][100];
11346 static int op_ad, op_index[MAX_OPERANDS];
11347 static int two_source_ops;
11348 static bfd_vma op_address[MAX_OPERANDS];
11349 static bfd_vma op_riprel[MAX_OPERANDS];
11350 static bfd_vma start_pc;
11353 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11354 * (see topic "Redundant prefixes" in the "Differences from 8086"
11355 * section of the "Virtual 8086 Mode" chapter.)
11356 * 'pc' should be the address of this instruction, it will
11357 * be used to print the target address if this is a relative jump or call
11358 * The function returns the length of this instruction in bytes.
11361 static char intel_syntax;
11362 static char intel_mnemonic = !SYSV386_COMPAT;
11363 static char open_char;
11364 static char close_char;
11365 static char separator_char;
11366 static char scale_char;
11374 static enum x86_64_isa isa64;
11376 /* Here for backwards compatibility. When gdb stops using
11377 print_insn_i386_att and print_insn_i386_intel these functions can
11378 disappear, and print_insn_i386 be merged into print_insn. */
11380 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11384 return print_insn (pc, info);
11388 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11392 return print_insn (pc, info);
11396 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11400 return print_insn (pc, info);
11404 print_i386_disassembler_options (FILE *stream)
11406 fprintf (stream, _("\n\
11407 The following i386/x86-64 specific disassembler options are supported for use\n\
11408 with the -M switch (multiple options should be separated by commas):\n"));
11410 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
11411 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
11412 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
11413 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
11414 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
11415 fprintf (stream, _(" att-mnemonic\n"
11416 " Display instruction in AT&T mnemonic\n"));
11417 fprintf (stream, _(" intel-mnemonic\n"
11418 " Display instruction in Intel mnemonic\n"));
11419 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
11420 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
11421 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
11422 fprintf (stream, _(" data32 Assume 32bit data size\n"));
11423 fprintf (stream, _(" data16 Assume 16bit data size\n"));
11424 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11425 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
11426 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
11430 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11432 /* Get a pointer to struct dis386 with a valid name. */
11434 static const struct dis386 *
11435 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11437 int vindex, vex_table_index;
11439 if (dp->name != NULL)
11442 switch (dp->op[0].bytemode)
11444 case USE_REG_TABLE:
11445 dp = ®_table[dp->op[1].bytemode][modrm.reg];
11448 case USE_MOD_TABLE:
11449 vindex = modrm.mod == 0x3 ? 1 : 0;
11450 dp = &mod_table[dp->op[1].bytemode][vindex];
11454 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11457 case USE_PREFIX_TABLE:
11460 /* The prefix in VEX is implicit. */
11461 switch (vex.prefix)
11466 case REPE_PREFIX_OPCODE:
11469 case DATA_PREFIX_OPCODE:
11472 case REPNE_PREFIX_OPCODE:
11482 int last_prefix = -1;
11485 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11486 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11488 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11490 if (last_repz_prefix > last_repnz_prefix)
11493 prefix = PREFIX_REPZ;
11494 last_prefix = last_repz_prefix;
11499 prefix = PREFIX_REPNZ;
11500 last_prefix = last_repnz_prefix;
11503 /* Check if prefix should be ignored. */
11504 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11505 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11510 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11513 prefix = PREFIX_DATA;
11514 last_prefix = last_data_prefix;
11519 used_prefixes |= prefix;
11520 all_prefixes[last_prefix] = 0;
11523 dp = &prefix_table[dp->op[1].bytemode][vindex];
11526 case USE_X86_64_TABLE:
11527 vindex = address_mode == mode_64bit ? 1 : 0;
11528 dp = &x86_64_table[dp->op[1].bytemode][vindex];
11531 case USE_3BYTE_TABLE:
11532 FETCH_DATA (info, codep + 2);
11534 dp = &three_byte_table[dp->op[1].bytemode][vindex];
11536 modrm.mod = (*codep >> 6) & 3;
11537 modrm.reg = (*codep >> 3) & 7;
11538 modrm.rm = *codep & 7;
11541 case USE_VEX_LEN_TABLE:
11545 switch (vex.length)
11558 dp = &vex_len_table[dp->op[1].bytemode][vindex];
11561 case USE_EVEX_LEN_TABLE:
11565 switch (vex.length)
11581 dp = &evex_len_table[dp->op[1].bytemode][vindex];
11584 case USE_XOP_8F_TABLE:
11585 FETCH_DATA (info, codep + 3);
11586 /* All bits in the REX prefix are ignored. */
11588 rex = ~(*codep >> 5) & 0x7;
11590 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11591 switch ((*codep & 0x1f))
11597 vex_table_index = XOP_08;
11600 vex_table_index = XOP_09;
11603 vex_table_index = XOP_0A;
11607 vex.w = *codep & 0x80;
11608 if (vex.w && address_mode == mode_64bit)
11611 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11612 if (address_mode != mode_64bit)
11614 /* In 16/32-bit mode REX_B is silently ignored. */
11618 vex.length = (*codep & 0x4) ? 256 : 128;
11619 switch ((*codep & 0x3))
11624 vex.prefix = DATA_PREFIX_OPCODE;
11627 vex.prefix = REPE_PREFIX_OPCODE;
11630 vex.prefix = REPNE_PREFIX_OPCODE;
11637 dp = &xop_table[vex_table_index][vindex];
11640 FETCH_DATA (info, codep + 1);
11641 modrm.mod = (*codep >> 6) & 3;
11642 modrm.reg = (*codep >> 3) & 7;
11643 modrm.rm = *codep & 7;
11646 case USE_VEX_C4_TABLE:
11648 FETCH_DATA (info, codep + 3);
11649 /* All bits in the REX prefix are ignored. */
11651 rex = ~(*codep >> 5) & 0x7;
11652 switch ((*codep & 0x1f))
11658 vex_table_index = VEX_0F;
11661 vex_table_index = VEX_0F38;
11664 vex_table_index = VEX_0F3A;
11668 vex.w = *codep & 0x80;
11669 if (address_mode == mode_64bit)
11676 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11677 is ignored, other REX bits are 0 and the highest bit in
11678 VEX.vvvv is also ignored (but we mustn't clear it here). */
11681 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11682 vex.length = (*codep & 0x4) ? 256 : 128;
11683 switch ((*codep & 0x3))
11688 vex.prefix = DATA_PREFIX_OPCODE;
11691 vex.prefix = REPE_PREFIX_OPCODE;
11694 vex.prefix = REPNE_PREFIX_OPCODE;
11701 dp = &vex_table[vex_table_index][vindex];
11703 /* There is no MODRM byte for VEX0F 77. */
11704 if (vex_table_index != VEX_0F || vindex != 0x77)
11706 FETCH_DATA (info, codep + 1);
11707 modrm.mod = (*codep >> 6) & 3;
11708 modrm.reg = (*codep >> 3) & 7;
11709 modrm.rm = *codep & 7;
11713 case USE_VEX_C5_TABLE:
11715 FETCH_DATA (info, codep + 2);
11716 /* All bits in the REX prefix are ignored. */
11718 rex = (*codep & 0x80) ? 0 : REX_R;
11720 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11722 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11723 vex.length = (*codep & 0x4) ? 256 : 128;
11724 switch ((*codep & 0x3))
11729 vex.prefix = DATA_PREFIX_OPCODE;
11732 vex.prefix = REPE_PREFIX_OPCODE;
11735 vex.prefix = REPNE_PREFIX_OPCODE;
11742 dp = &vex_table[dp->op[1].bytemode][vindex];
11744 /* There is no MODRM byte for VEX 77. */
11745 if (vindex != 0x77)
11747 FETCH_DATA (info, codep + 1);
11748 modrm.mod = (*codep >> 6) & 3;
11749 modrm.reg = (*codep >> 3) & 7;
11750 modrm.rm = *codep & 7;
11754 case USE_VEX_W_TABLE:
11758 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11761 case USE_EVEX_TABLE:
11762 two_source_ops = 0;
11765 FETCH_DATA (info, codep + 4);
11766 /* All bits in the REX prefix are ignored. */
11768 /* The first byte after 0x62. */
11769 rex = ~(*codep >> 5) & 0x7;
11770 vex.r = *codep & 0x10;
11771 switch ((*codep & 0xf))
11774 return &bad_opcode;
11776 vex_table_index = EVEX_0F;
11779 vex_table_index = EVEX_0F38;
11782 vex_table_index = EVEX_0F3A;
11786 /* The second byte after 0x62. */
11788 vex.w = *codep & 0x80;
11789 if (vex.w && address_mode == mode_64bit)
11792 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11795 if (!(*codep & 0x4))
11796 return &bad_opcode;
11798 switch ((*codep & 0x3))
11803 vex.prefix = DATA_PREFIX_OPCODE;
11806 vex.prefix = REPE_PREFIX_OPCODE;
11809 vex.prefix = REPNE_PREFIX_OPCODE;
11813 /* The third byte after 0x62. */
11816 /* Remember the static rounding bits. */
11817 vex.ll = (*codep >> 5) & 3;
11818 vex.b = (*codep & 0x10) != 0;
11820 vex.v = *codep & 0x8;
11821 vex.mask_register_specifier = *codep & 0x7;
11822 vex.zeroing = *codep & 0x80;
11824 if (address_mode != mode_64bit)
11826 /* In 16/32-bit mode silently ignore following bits. */
11836 dp = &evex_table[vex_table_index][vindex];
11838 FETCH_DATA (info, codep + 1);
11839 modrm.mod = (*codep >> 6) & 3;
11840 modrm.reg = (*codep >> 3) & 7;
11841 modrm.rm = *codep & 7;
11843 /* Set vector length. */
11844 if (modrm.mod == 3 && vex.b)
11860 return &bad_opcode;
11873 if (dp->name != NULL)
11876 return get_valid_dis386 (dp, info);
11880 get_sib (disassemble_info *info, int sizeflag)
11882 /* If modrm.mod == 3, operand must be register. */
11884 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11888 FETCH_DATA (info, codep + 2);
11889 sib.index = (codep [1] >> 3) & 7;
11890 sib.scale = (codep [1] >> 6) & 3;
11891 sib.base = codep [1] & 7;
11896 print_insn (bfd_vma pc, disassemble_info *info)
11898 const struct dis386 *dp;
11900 char *op_txt[MAX_OPERANDS];
11902 int sizeflag, orig_sizeflag;
11904 struct dis_private priv;
11907 priv.orig_sizeflag = AFLAG | DFLAG;
11908 if ((info->mach & bfd_mach_i386_i386) != 0)
11909 address_mode = mode_32bit;
11910 else if (info->mach == bfd_mach_i386_i8086)
11912 address_mode = mode_16bit;
11913 priv.orig_sizeflag = 0;
11916 address_mode = mode_64bit;
11918 if (intel_syntax == (char) -1)
11919 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11921 for (p = info->disassembler_options; p != NULL; )
11923 if (CONST_STRNEQ (p, "amd64"))
11925 else if (CONST_STRNEQ (p, "intel64"))
11927 else if (CONST_STRNEQ (p, "x86-64"))
11929 address_mode = mode_64bit;
11930 priv.orig_sizeflag = AFLAG | DFLAG;
11932 else if (CONST_STRNEQ (p, "i386"))
11934 address_mode = mode_32bit;
11935 priv.orig_sizeflag = AFLAG | DFLAG;
11937 else if (CONST_STRNEQ (p, "i8086"))
11939 address_mode = mode_16bit;
11940 priv.orig_sizeflag = 0;
11942 else if (CONST_STRNEQ (p, "intel"))
11945 if (CONST_STRNEQ (p + 5, "-mnemonic"))
11946 intel_mnemonic = 1;
11948 else if (CONST_STRNEQ (p, "att"))
11951 if (CONST_STRNEQ (p + 3, "-mnemonic"))
11952 intel_mnemonic = 0;
11954 else if (CONST_STRNEQ (p, "addr"))
11956 if (address_mode == mode_64bit)
11958 if (p[4] == '3' && p[5] == '2')
11959 priv.orig_sizeflag &= ~AFLAG;
11960 else if (p[4] == '6' && p[5] == '4')
11961 priv.orig_sizeflag |= AFLAG;
11965 if (p[4] == '1' && p[5] == '6')
11966 priv.orig_sizeflag &= ~AFLAG;
11967 else if (p[4] == '3' && p[5] == '2')
11968 priv.orig_sizeflag |= AFLAG;
11971 else if (CONST_STRNEQ (p, "data"))
11973 if (p[4] == '1' && p[5] == '6')
11974 priv.orig_sizeflag &= ~DFLAG;
11975 else if (p[4] == '3' && p[5] == '2')
11976 priv.orig_sizeflag |= DFLAG;
11978 else if (CONST_STRNEQ (p, "suffix"))
11979 priv.orig_sizeflag |= SUFFIX_ALWAYS;
11981 p = strchr (p, ',');
11986 if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11988 (*info->fprintf_func) (info->stream,
11989 _("64-bit address is disabled"));
11995 names64 = intel_names64;
11996 names32 = intel_names32;
11997 names16 = intel_names16;
11998 names8 = intel_names8;
11999 names8rex = intel_names8rex;
12000 names_seg = intel_names_seg;
12001 names_mm = intel_names_mm;
12002 names_bnd = intel_names_bnd;
12003 names_xmm = intel_names_xmm;
12004 names_ymm = intel_names_ymm;
12005 names_zmm = intel_names_zmm;
12006 index64 = intel_index64;
12007 index32 = intel_index32;
12008 names_mask = intel_names_mask;
12009 index16 = intel_index16;
12012 separator_char = '+';
12017 names64 = att_names64;
12018 names32 = att_names32;
12019 names16 = att_names16;
12020 names8 = att_names8;
12021 names8rex = att_names8rex;
12022 names_seg = att_names_seg;
12023 names_mm = att_names_mm;
12024 names_bnd = att_names_bnd;
12025 names_xmm = att_names_xmm;
12026 names_ymm = att_names_ymm;
12027 names_zmm = att_names_zmm;
12028 index64 = att_index64;
12029 index32 = att_index32;
12030 names_mask = att_names_mask;
12031 index16 = att_index16;
12034 separator_char = ',';
12038 /* The output looks better if we put 7 bytes on a line, since that
12039 puts most long word instructions on a single line. Use 8 bytes
12041 if ((info->mach & bfd_mach_l1om) != 0)
12042 info->bytes_per_line = 8;
12044 info->bytes_per_line = 7;
12046 info->private_data = &priv;
12047 priv.max_fetched = priv.the_buffer;
12048 priv.insn_start = pc;
12051 for (i = 0; i < MAX_OPERANDS; ++i)
12059 start_codep = priv.the_buffer;
12060 codep = priv.the_buffer;
12062 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12066 /* Getting here means we tried for data but didn't get it. That
12067 means we have an incomplete instruction of some sort. Just
12068 print the first byte as a prefix or a .byte pseudo-op. */
12069 if (codep > priv.the_buffer)
12071 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12073 (*info->fprintf_func) (info->stream, "%s", name);
12076 /* Just print the first byte as a .byte instruction. */
12077 (*info->fprintf_func) (info->stream, ".byte 0x%x",
12078 (unsigned int) priv.the_buffer[0]);
12088 sizeflag = priv.orig_sizeflag;
12090 if (!ckprefix () || rex_used)
12092 /* Too many prefixes or unused REX prefixes. */
12094 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12096 (*info->fprintf_func) (info->stream, "%s%s",
12098 prefix_name (all_prefixes[i], sizeflag));
12102 insn_codep = codep;
12104 FETCH_DATA (info, codep + 1);
12105 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12107 if (((prefixes & PREFIX_FWAIT)
12108 && ((*codep < 0xd8) || (*codep > 0xdf))))
12110 /* Handle prefixes before fwait. */
12111 for (i = 0; i < fwait_prefix && all_prefixes[i];
12113 (*info->fprintf_func) (info->stream, "%s ",
12114 prefix_name (all_prefixes[i], sizeflag));
12115 (*info->fprintf_func) (info->stream, "fwait");
12119 if (*codep == 0x0f)
12121 unsigned char threebyte;
12124 FETCH_DATA (info, codep + 1);
12125 threebyte = *codep;
12126 dp = &dis386_twobyte[threebyte];
12127 need_modrm = twobyte_has_modrm[*codep];
12132 dp = &dis386[*codep];
12133 need_modrm = onebyte_has_modrm[*codep];
12137 /* Save sizeflag for printing the extra prefixes later before updating
12138 it for mnemonic and operand processing. The prefix names depend
12139 only on the address mode. */
12140 orig_sizeflag = sizeflag;
12141 if (prefixes & PREFIX_ADDR)
12143 if ((prefixes & PREFIX_DATA))
12149 FETCH_DATA (info, codep + 1);
12150 modrm.mod = (*codep >> 6) & 3;
12151 modrm.reg = (*codep >> 3) & 7;
12152 modrm.rm = *codep & 7;
12158 memset (&vex, 0, sizeof (vex));
12160 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12162 get_sib (info, sizeflag);
12163 dofloat (sizeflag);
12167 dp = get_valid_dis386 (dp, info);
12168 if (dp != NULL && putop (dp->name, sizeflag) == 0)
12170 get_sib (info, sizeflag);
12171 for (i = 0; i < MAX_OPERANDS; ++i)
12174 op_ad = MAX_OPERANDS - 1 - i;
12176 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12177 /* For EVEX instruction after the last operand masking
12178 should be printed. */
12179 if (i == 0 && vex.evex)
12181 /* Don't print {%k0}. */
12182 if (vex.mask_register_specifier)
12185 oappend (names_mask[vex.mask_register_specifier]);
12195 /* Check if the REX prefix is used. */
12196 if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12197 all_prefixes[last_rex_prefix] = 0;
12199 /* Check if the SEG prefix is used. */
12200 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12201 | PREFIX_FS | PREFIX_GS)) != 0
12202 && (used_prefixes & active_seg_prefix) != 0)
12203 all_prefixes[last_seg_prefix] = 0;
12205 /* Check if the ADDR prefix is used. */
12206 if ((prefixes & PREFIX_ADDR) != 0
12207 && (used_prefixes & PREFIX_ADDR) != 0)
12208 all_prefixes[last_addr_prefix] = 0;
12210 /* Check if the DATA prefix is used. */
12211 if ((prefixes & PREFIX_DATA) != 0
12212 && (used_prefixes & PREFIX_DATA) != 0)
12213 all_prefixes[last_data_prefix] = 0;
12215 /* Print the extra prefixes. */
12217 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12218 if (all_prefixes[i])
12221 name = prefix_name (all_prefixes[i], orig_sizeflag);
12224 prefix_length += strlen (name) + 1;
12225 (*info->fprintf_func) (info->stream, "%s ", name);
12228 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12229 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12230 used by putop and MMX/SSE operand and may be overriden by the
12231 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12233 if (dp->prefix_requirement == PREFIX_OPCODE
12234 && dp != &bad_opcode
12236 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12238 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12240 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12242 && (used_prefixes & PREFIX_DATA) == 0))))
12244 (*info->fprintf_func) (info->stream, "(bad)");
12245 return end_codep - priv.the_buffer;
12248 /* Check maximum code length. */
12249 if ((codep - start_codep) > MAX_CODE_LENGTH)
12251 (*info->fprintf_func) (info->stream, "(bad)");
12252 return MAX_CODE_LENGTH;
12255 obufp = mnemonicendp;
12256 for (i = strlen (obuf) + prefix_length; i < 6; i++)
12259 (*info->fprintf_func) (info->stream, "%s", obuf);
12261 /* The enter and bound instructions are printed with operands in the same
12262 order as the intel book; everything else is printed in reverse order. */
12263 if (intel_syntax || two_source_ops)
12267 for (i = 0; i < MAX_OPERANDS; ++i)
12268 op_txt[i] = op_out[i];
12270 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12271 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12273 op_txt[2] = op_out[3];
12274 op_txt[3] = op_out[2];
12277 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12279 op_ad = op_index[i];
12280 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12281 op_index[MAX_OPERANDS - 1 - i] = op_ad;
12282 riprel = op_riprel[i];
12283 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12284 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12289 for (i = 0; i < MAX_OPERANDS; ++i)
12290 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12294 for (i = 0; i < MAX_OPERANDS; ++i)
12298 (*info->fprintf_func) (info->stream, ",");
12299 if (op_index[i] != -1 && !op_riprel[i])
12300 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12302 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12306 for (i = 0; i < MAX_OPERANDS; i++)
12307 if (op_index[i] != -1 && op_riprel[i])
12309 (*info->fprintf_func) (info->stream, " # ");
12310 (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12311 + op_address[op_index[i]]), info);
12314 return codep - priv.the_buffer;
12317 static const char *float_mem[] = {
12392 static const unsigned char float_mem_mode[] = {
12467 #define ST { OP_ST, 0 }
12468 #define STi { OP_STi, 0 }
12470 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12471 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12472 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12473 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12474 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12475 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12476 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12477 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12478 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12480 static const struct dis386 float_reg[][8] = {
12483 { "fadd", { ST, STi }, 0 },
12484 { "fmul", { ST, STi }, 0 },
12485 { "fcom", { STi }, 0 },
12486 { "fcomp", { STi }, 0 },
12487 { "fsub", { ST, STi }, 0 },
12488 { "fsubr", { ST, STi }, 0 },
12489 { "fdiv", { ST, STi }, 0 },
12490 { "fdivr", { ST, STi }, 0 },
12494 { "fld", { STi }, 0 },
12495 { "fxch", { STi }, 0 },
12505 { "fcmovb", { ST, STi }, 0 },
12506 { "fcmove", { ST, STi }, 0 },
12507 { "fcmovbe",{ ST, STi }, 0 },
12508 { "fcmovu", { ST, STi }, 0 },
12516 { "fcmovnb",{ ST, STi }, 0 },
12517 { "fcmovne",{ ST, STi }, 0 },
12518 { "fcmovnbe",{ ST, STi }, 0 },
12519 { "fcmovnu",{ ST, STi }, 0 },
12521 { "fucomi", { ST, STi }, 0 },
12522 { "fcomi", { ST, STi }, 0 },
12527 { "fadd", { STi, ST }, 0 },
12528 { "fmul", { STi, ST }, 0 },
12531 { "fsub{!M|r}", { STi, ST }, 0 },
12532 { "fsub{M|}", { STi, ST }, 0 },
12533 { "fdiv{!M|r}", { STi, ST }, 0 },
12534 { "fdiv{M|}", { STi, ST }, 0 },
12538 { "ffree", { STi }, 0 },
12540 { "fst", { STi }, 0 },
12541 { "fstp", { STi }, 0 },
12542 { "fucom", { STi }, 0 },
12543 { "fucomp", { STi }, 0 },
12549 { "faddp", { STi, ST }, 0 },
12550 { "fmulp", { STi, ST }, 0 },
12553 { "fsub{!M|r}p", { STi, ST }, 0 },
12554 { "fsub{M|}p", { STi, ST }, 0 },
12555 { "fdiv{!M|r}p", { STi, ST }, 0 },
12556 { "fdiv{M|}p", { STi, ST }, 0 },
12560 { "ffreep", { STi }, 0 },
12565 { "fucomip", { ST, STi }, 0 },
12566 { "fcomip", { ST, STi }, 0 },
12571 static char *fgrps[][8] = {
12574 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12579 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12584 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12589 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12594 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12599 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12604 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12609 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12610 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12615 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12620 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12625 swap_operand (void)
12627 mnemonicendp[0] = '.';
12628 mnemonicendp[1] = 's';
12633 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12634 int sizeflag ATTRIBUTE_UNUSED)
12636 /* Skip mod/rm byte. */
12642 dofloat (int sizeflag)
12644 const struct dis386 *dp;
12645 unsigned char floatop;
12647 floatop = codep[-1];
12649 if (modrm.mod != 3)
12651 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12653 putop (float_mem[fp_indx], sizeflag);
12656 OP_E (float_mem_mode[fp_indx], sizeflag);
12659 /* Skip mod/rm byte. */
12663 dp = &float_reg[floatop - 0xd8][modrm.reg];
12664 if (dp->name == NULL)
12666 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12668 /* Instruction fnstsw is only one with strange arg. */
12669 if (floatop == 0xdf && codep[-1] == 0xe0)
12670 strcpy (op_out[0], names16[0]);
12674 putop (dp->name, sizeflag);
12679 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12684 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12688 /* Like oappend (below), but S is a string starting with '%'.
12689 In Intel syntax, the '%' is elided. */
12691 oappend_maybe_intel (const char *s)
12693 oappend (s + intel_syntax);
12697 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12699 oappend_maybe_intel ("%st");
12703 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12705 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12706 oappend_maybe_intel (scratchbuf);
12709 /* Capital letters in template are macros. */
12711 putop (const char *in_template, int sizeflag)
12716 unsigned int l = 0, len = 1;
12719 #define SAVE_LAST(c) \
12720 if (l < len && l < sizeof (last)) \
12725 for (p = in_template; *p; p++)
12741 while (*++p != '|')
12742 if (*p == '}' || *p == '\0')
12745 /* Fall through. */
12750 while (*++p != '}')
12761 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12765 if (l == 0 && len == 1)
12770 if (sizeflag & SUFFIX_ALWAYS)
12783 if (address_mode == mode_64bit
12784 && !(prefixes & PREFIX_ADDR))
12795 if (intel_syntax && !alt)
12797 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12799 if (sizeflag & DFLAG)
12800 *obufp++ = intel_syntax ? 'd' : 'l';
12802 *obufp++ = intel_syntax ? 'w' : 's';
12803 used_prefixes |= (prefixes & PREFIX_DATA);
12807 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12810 if (modrm.mod == 3)
12816 if (sizeflag & DFLAG)
12817 *obufp++ = intel_syntax ? 'd' : 'l';
12820 used_prefixes |= (prefixes & PREFIX_DATA);
12826 case 'E': /* For jcxz/jecxz */
12827 if (address_mode == mode_64bit)
12829 if (sizeflag & AFLAG)
12835 if (sizeflag & AFLAG)
12837 used_prefixes |= (prefixes & PREFIX_ADDR);
12842 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12844 if (sizeflag & AFLAG)
12845 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12847 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12848 used_prefixes |= (prefixes & PREFIX_ADDR);
12852 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12854 if ((rex & REX_W) || (sizeflag & DFLAG))
12858 if (!(rex & REX_W))
12859 used_prefixes |= (prefixes & PREFIX_DATA);
12864 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12865 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12867 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12870 if (prefixes & PREFIX_DS)
12889 if (l != 0 || len != 1)
12891 if (l != 1 || len != 2 || last[0] != 'X')
12896 if (!need_vex || !vex.evex)
12899 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12901 switch (vex.length)
12919 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12924 /* Fall through. */
12927 if (l != 0 || len != 1)
12935 if (sizeflag & SUFFIX_ALWAYS)
12939 if (intel_mnemonic != cond)
12943 if ((prefixes & PREFIX_FWAIT) == 0)
12946 used_prefixes |= PREFIX_FWAIT;
12952 else if (intel_syntax && (sizeflag & DFLAG))
12956 if (!(rex & REX_W))
12957 used_prefixes |= (prefixes & PREFIX_DATA);
12961 && address_mode == mode_64bit
12962 && isa64 == intel64)
12967 /* Fall through. */
12970 && address_mode == mode_64bit
12971 && ((sizeflag & DFLAG) || (rex & REX_W)))
12976 /* Fall through. */
12979 if (l == 0 && len == 1)
12984 if ((rex & REX_W) == 0
12985 && (prefixes & PREFIX_DATA))
12987 if ((sizeflag & DFLAG) == 0)
12989 used_prefixes |= (prefixes & PREFIX_DATA);
12993 if ((prefixes & PREFIX_DATA)
12995 || (sizeflag & SUFFIX_ALWAYS))
13002 if (sizeflag & DFLAG)
13006 used_prefixes |= (prefixes & PREFIX_DATA);
13012 if (l != 1 || len != 2 || last[0] != 'L')
13018 if ((prefixes & PREFIX_DATA)
13020 || (sizeflag & SUFFIX_ALWAYS))
13027 if (sizeflag & DFLAG)
13028 *obufp++ = intel_syntax ? 'd' : 'l';
13031 used_prefixes |= (prefixes & PREFIX_DATA);
13039 if (address_mode == mode_64bit
13040 && ((sizeflag & DFLAG) || (rex & REX_W)))
13042 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13046 /* Fall through. */
13049 if (l == 0 && len == 1)
13052 if (intel_syntax && !alt)
13055 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13061 if (sizeflag & DFLAG)
13062 *obufp++ = intel_syntax ? 'd' : 'l';
13065 used_prefixes |= (prefixes & PREFIX_DATA);
13071 if (l != 1 || len != 2 || last[0] != 'L')
13077 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13092 else if (sizeflag & DFLAG)
13101 if (intel_syntax && !p[1]
13102 && ((rex & REX_W) || (sizeflag & DFLAG)))
13104 if (!(rex & REX_W))
13105 used_prefixes |= (prefixes & PREFIX_DATA);
13108 if (l == 0 && len == 1)
13112 if (address_mode == mode_64bit
13113 && ((sizeflag & DFLAG) || (rex & REX_W)))
13115 if (sizeflag & SUFFIX_ALWAYS)
13137 /* Fall through. */
13140 if (l == 0 && len == 1)
13145 if (sizeflag & SUFFIX_ALWAYS)
13151 if (sizeflag & DFLAG)
13155 used_prefixes |= (prefixes & PREFIX_DATA);
13169 if (address_mode == mode_64bit
13170 && !(prefixes & PREFIX_ADDR))
13181 if (l != 0 || len != 1)
13186 if (need_vex && vex.prefix)
13188 if (vex.prefix == DATA_PREFIX_OPCODE)
13195 if (prefixes & PREFIX_DATA)
13199 used_prefixes |= (prefixes & PREFIX_DATA);
13203 if (l == 0 && len == 1)
13207 if (l != 1 || len != 2 || last[0] != 'X')
13215 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13217 switch (vex.length)
13233 if (l == 0 && len == 1)
13235 /* operand size flag for cwtl, cbtw */
13244 else if (sizeflag & DFLAG)
13248 if (!(rex & REX_W))
13249 used_prefixes |= (prefixes & PREFIX_DATA);
13256 && last[0] != 'L'))
13263 if (last[0] == 'X')
13264 *obufp++ = vex.w ? 'd': 's';
13266 *obufp++ = vex.w ? 'q': 'd';
13272 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13274 if (sizeflag & DFLAG)
13278 used_prefixes |= (prefixes & PREFIX_DATA);
13284 if (address_mode == mode_64bit
13285 && (isa64 == intel64
13286 || ((sizeflag & DFLAG) || (rex & REX_W))))
13288 else if ((prefixes & PREFIX_DATA))
13290 if (!(sizeflag & DFLAG))
13292 used_prefixes |= (prefixes & PREFIX_DATA);
13299 mnemonicendp = obufp;
13304 oappend (const char *s)
13306 obufp = stpcpy (obufp, s);
13312 /* Only print the active segment register. */
13313 if (!active_seg_prefix)
13316 used_prefixes |= active_seg_prefix;
13317 switch (active_seg_prefix)
13320 oappend_maybe_intel ("%cs:");
13323 oappend_maybe_intel ("%ds:");
13326 oappend_maybe_intel ("%ss:");
13329 oappend_maybe_intel ("%es:");
13332 oappend_maybe_intel ("%fs:");
13335 oappend_maybe_intel ("%gs:");
13343 OP_indirE (int bytemode, int sizeflag)
13347 OP_E (bytemode, sizeflag);
13351 print_operand_value (char *buf, int hex, bfd_vma disp)
13353 if (address_mode == mode_64bit)
13361 sprintf_vma (tmp, disp);
13362 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13363 strcpy (buf + 2, tmp + i);
13367 bfd_signed_vma v = disp;
13374 /* Check for possible overflow on 0x8000000000000000. */
13377 strcpy (buf, "9223372036854775808");
13391 tmp[28 - i] = (v % 10) + '0';
13395 strcpy (buf, tmp + 29 - i);
13401 sprintf (buf, "0x%x", (unsigned int) disp);
13403 sprintf (buf, "%d", (int) disp);
13407 /* Put DISP in BUF as signed hex number. */
13410 print_displacement (char *buf, bfd_vma disp)
13412 bfd_signed_vma val = disp;
13421 /* Check for possible overflow. */
13424 switch (address_mode)
13427 strcpy (buf + j, "0x8000000000000000");
13430 strcpy (buf + j, "0x80000000");
13433 strcpy (buf + j, "0x8000");
13443 sprintf_vma (tmp, (bfd_vma) val);
13444 for (i = 0; tmp[i] == '0'; i++)
13446 if (tmp[i] == '\0')
13448 strcpy (buf + j, tmp + i);
13452 intel_operand_size (int bytemode, int sizeflag)
13456 && (bytemode == x_mode
13457 || bytemode == evex_half_bcst_xmmq_mode))
13460 oappend ("QWORD PTR ");
13462 oappend ("DWORD PTR ");
13471 oappend ("BYTE PTR ");
13476 oappend ("WORD PTR ");
13479 if (address_mode == mode_64bit && isa64 == intel64)
13481 oappend ("QWORD PTR ");
13484 /* Fall through. */
13486 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13488 oappend ("QWORD PTR ");
13491 /* Fall through. */
13497 oappend ("QWORD PTR ");
13500 if ((sizeflag & DFLAG) || bytemode == dq_mode)
13501 oappend ("DWORD PTR ");
13503 oappend ("WORD PTR ");
13504 used_prefixes |= (prefixes & PREFIX_DATA);
13508 if ((rex & REX_W) || (sizeflag & DFLAG))
13510 oappend ("WORD PTR ");
13511 if (!(rex & REX_W))
13512 used_prefixes |= (prefixes & PREFIX_DATA);
13515 if (sizeflag & DFLAG)
13516 oappend ("QWORD PTR ");
13518 oappend ("DWORD PTR ");
13519 used_prefixes |= (prefixes & PREFIX_DATA);
13522 case d_scalar_mode:
13523 case d_scalar_swap_mode:
13526 oappend ("DWORD PTR ");
13529 case q_scalar_mode:
13530 case q_scalar_swap_mode:
13532 oappend ("QWORD PTR ");
13536 if (address_mode == mode_64bit)
13537 oappend ("QWORD PTR ");
13539 oappend ("DWORD PTR ");
13542 if (sizeflag & DFLAG)
13543 oappend ("FWORD PTR ");
13545 oappend ("DWORD PTR ");
13546 used_prefixes |= (prefixes & PREFIX_DATA);
13549 oappend ("TBYTE PTR ");
13553 case evex_x_gscat_mode:
13554 case evex_x_nobcst_mode:
13555 case b_scalar_mode:
13556 case w_scalar_mode:
13559 switch (vex.length)
13562 oappend ("XMMWORD PTR ");
13565 oappend ("YMMWORD PTR ");
13568 oappend ("ZMMWORD PTR ");
13575 oappend ("XMMWORD PTR ");
13578 oappend ("XMMWORD PTR ");
13581 oappend ("YMMWORD PTR ");
13584 case evex_half_bcst_xmmq_mode:
13588 switch (vex.length)
13591 oappend ("QWORD PTR ");
13594 oappend ("XMMWORD PTR ");
13597 oappend ("YMMWORD PTR ");
13607 switch (vex.length)
13612 oappend ("BYTE PTR ");
13622 switch (vex.length)
13627 oappend ("WORD PTR ");
13637 switch (vex.length)
13642 oappend ("DWORD PTR ");
13652 switch (vex.length)
13657 oappend ("QWORD PTR ");
13667 switch (vex.length)
13670 oappend ("WORD PTR ");
13673 oappend ("DWORD PTR ");
13676 oappend ("QWORD PTR ");
13686 switch (vex.length)
13689 oappend ("DWORD PTR ");
13692 oappend ("QWORD PTR ");
13695 oappend ("XMMWORD PTR ");
13705 switch (vex.length)
13708 oappend ("QWORD PTR ");
13711 oappend ("YMMWORD PTR ");
13714 oappend ("ZMMWORD PTR ");
13724 switch (vex.length)
13728 oappend ("XMMWORD PTR ");
13735 oappend ("OWORD PTR ");
13738 case vex_w_dq_mode:
13739 case vex_scalar_w_dq_mode:
13744 oappend ("QWORD PTR ");
13746 oappend ("DWORD PTR ");
13748 case vex_vsib_d_w_dq_mode:
13749 case vex_vsib_q_w_dq_mode:
13756 oappend ("QWORD PTR ");
13758 oappend ("DWORD PTR ");
13762 switch (vex.length)
13765 oappend ("XMMWORD PTR ");
13768 oappend ("YMMWORD PTR ");
13771 oappend ("ZMMWORD PTR ");
13778 case vex_vsib_q_w_d_mode:
13779 case vex_vsib_d_w_d_mode:
13780 if (!need_vex || !vex.evex)
13783 switch (vex.length)
13786 oappend ("QWORD PTR ");
13789 oappend ("XMMWORD PTR ");
13792 oappend ("YMMWORD PTR ");
13800 if (!need_vex || vex.length != 128)
13803 oappend ("DWORD PTR ");
13805 oappend ("BYTE PTR ");
13811 oappend ("QWORD PTR ");
13813 oappend ("WORD PTR ");
13823 OP_E_register (int bytemode, int sizeflag)
13825 int reg = modrm.rm;
13826 const char **names;
13832 if ((sizeflag & SUFFIX_ALWAYS)
13833 && (bytemode == b_swap_mode
13834 || bytemode == bnd_swap_mode
13835 || bytemode == v_swap_mode))
13861 names = address_mode == mode_64bit ? names64 : names32;
13864 case bnd_swap_mode:
13873 if (address_mode == mode_64bit && isa64 == intel64)
13878 /* Fall through. */
13880 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13886 /* Fall through. */
13899 if ((sizeflag & DFLAG)
13900 || (bytemode != v_mode
13901 && bytemode != v_swap_mode))
13905 used_prefixes |= (prefixes & PREFIX_DATA);
13909 names = (address_mode == mode_64bit
13910 ? names64 : names32);
13911 if (!(prefixes & PREFIX_ADDR))
13912 names = (address_mode == mode_16bit
13913 ? names16 : names);
13916 /* Remove "addr16/addr32". */
13917 all_prefixes[last_addr_prefix] = 0;
13918 names = (address_mode != mode_32bit
13919 ? names32 : names16);
13920 used_prefixes |= PREFIX_ADDR;
13930 names = names_mask;
13935 oappend (INTERNAL_DISASSEMBLER_ERROR);
13938 oappend (names[reg]);
13942 OP_E_memory (int bytemode, int sizeflag)
13945 int add = (rex & REX_B) ? 8 : 0;
13951 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
13953 && bytemode != x_mode
13954 && bytemode != xmmq_mode
13955 && bytemode != evex_half_bcst_xmmq_mode)
13970 case vex_vsib_d_w_dq_mode:
13971 case vex_vsib_d_w_d_mode:
13972 case vex_vsib_q_w_dq_mode:
13973 case vex_vsib_q_w_d_mode:
13974 case evex_x_gscat_mode:
13976 shift = vex.w ? 3 : 2;
13979 case evex_half_bcst_xmmq_mode:
13983 shift = vex.w ? 3 : 2;
13986 /* Fall through. */
13990 case evex_x_nobcst_mode:
13992 switch (vex.length)
14015 case q_scalar_mode:
14017 case q_scalar_swap_mode:
14023 case d_scalar_mode:
14025 case d_scalar_swap_mode:
14028 case w_scalar_mode:
14032 case b_scalar_mode:
14037 shift = address_mode == mode_64bit ? 3 : 2;
14042 /* Make necessary corrections to shift for modes that need it.
14043 For these modes we currently have shift 4, 5 or 6 depending on
14044 vex.length (it corresponds to xmmword, ymmword or zmmword
14045 operand). We might want to make it 3, 4 or 5 (e.g. for
14046 xmmq_mode). In case of broadcast enabled the corrections
14047 aren't needed, as element size is always 32 or 64 bits. */
14049 && (bytemode == xmmq_mode
14050 || bytemode == evex_half_bcst_xmmq_mode))
14052 else if (bytemode == xmmqd_mode)
14054 else if (bytemode == xmmdw_mode)
14056 else if (bytemode == ymmq_mode && vex.length == 128)
14064 intel_operand_size (bytemode, sizeflag);
14067 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14069 /* 32/64 bit address mode */
14079 int addr32flag = !((sizeflag & AFLAG)
14080 || bytemode == v_bnd_mode
14081 || bytemode == v_bndmk_mode
14082 || bytemode == bnd_mode
14083 || bytemode == bnd_swap_mode);
14084 const char **indexes64 = names64;
14085 const char **indexes32 = names32;
14095 vindex = sib.index;
14101 case vex_vsib_d_w_dq_mode:
14102 case vex_vsib_d_w_d_mode:
14103 case vex_vsib_q_w_dq_mode:
14104 case vex_vsib_q_w_d_mode:
14114 switch (vex.length)
14117 indexes64 = indexes32 = names_xmm;
14121 || bytemode == vex_vsib_q_w_dq_mode
14122 || bytemode == vex_vsib_q_w_d_mode)
14123 indexes64 = indexes32 = names_ymm;
14125 indexes64 = indexes32 = names_xmm;
14129 || bytemode == vex_vsib_q_w_dq_mode
14130 || bytemode == vex_vsib_q_w_d_mode)
14131 indexes64 = indexes32 = names_zmm;
14133 indexes64 = indexes32 = names_ymm;
14140 haveindex = vindex != 4;
14147 rbase = base + add;
14155 if (address_mode == mode_64bit && !havesib)
14158 if (riprel && bytemode == v_bndmk_mode)
14166 FETCH_DATA (the_info, codep + 1);
14168 if ((disp & 0x80) != 0)
14170 if (vex.evex && shift > 0)
14183 && address_mode != mode_16bit)
14185 if (address_mode == mode_64bit)
14187 /* Display eiz instead of addr32. */
14188 needindex = addr32flag;
14193 /* In 32-bit mode, we need index register to tell [offset]
14194 from [eiz*1 + offset]. */
14199 havedisp = (havebase
14201 || (havesib && (haveindex || scale != 0)));
14204 if (modrm.mod != 0 || base == 5)
14206 if (havedisp || riprel)
14207 print_displacement (scratchbuf, disp);
14209 print_operand_value (scratchbuf, 1, disp);
14210 oappend (scratchbuf);
14214 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14218 if ((havebase || haveindex || needaddr32 || riprel)
14219 && (bytemode != v_bnd_mode)
14220 && (bytemode != v_bndmk_mode)
14221 && (bytemode != bnd_mode)
14222 && (bytemode != bnd_swap_mode))
14223 used_prefixes |= PREFIX_ADDR;
14225 if (havedisp || (intel_syntax && riprel))
14227 *obufp++ = open_char;
14228 if (intel_syntax && riprel)
14231 oappend (!addr32flag ? "rip" : "eip");
14235 oappend (address_mode == mode_64bit && !addr32flag
14236 ? names64[rbase] : names32[rbase]);
14239 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14240 print index to tell base + index from base. */
14244 || (havebase && base != ESP_REG_NUM))
14246 if (!intel_syntax || havebase)
14248 *obufp++ = separator_char;
14252 oappend (address_mode == mode_64bit && !addr32flag
14253 ? indexes64[vindex] : indexes32[vindex]);
14255 oappend (address_mode == mode_64bit && !addr32flag
14256 ? index64 : index32);
14258 *obufp++ = scale_char;
14260 sprintf (scratchbuf, "%d", 1 << scale);
14261 oappend (scratchbuf);
14265 && (disp || modrm.mod != 0 || base == 5))
14267 if (!havedisp || (bfd_signed_vma) disp >= 0)
14272 else if (modrm.mod != 1 && disp != -disp)
14276 disp = - (bfd_signed_vma) disp;
14280 print_displacement (scratchbuf, disp);
14282 print_operand_value (scratchbuf, 1, disp);
14283 oappend (scratchbuf);
14286 *obufp++ = close_char;
14289 else if (intel_syntax)
14291 if (modrm.mod != 0 || base == 5)
14293 if (!active_seg_prefix)
14295 oappend (names_seg[ds_reg - es_reg]);
14298 print_operand_value (scratchbuf, 1, disp);
14299 oappend (scratchbuf);
14305 /* 16 bit address mode */
14306 used_prefixes |= prefixes & PREFIX_ADDR;
14313 if ((disp & 0x8000) != 0)
14318 FETCH_DATA (the_info, codep + 1);
14320 if ((disp & 0x80) != 0)
14322 if (vex.evex && shift > 0)
14327 if ((disp & 0x8000) != 0)
14333 if (modrm.mod != 0 || modrm.rm == 6)
14335 print_displacement (scratchbuf, disp);
14336 oappend (scratchbuf);
14339 if (modrm.mod != 0 || modrm.rm != 6)
14341 *obufp++ = open_char;
14343 oappend (index16[modrm.rm]);
14345 && (disp || modrm.mod != 0 || modrm.rm == 6))
14347 if ((bfd_signed_vma) disp >= 0)
14352 else if (modrm.mod != 1)
14356 disp = - (bfd_signed_vma) disp;
14359 print_displacement (scratchbuf, disp);
14360 oappend (scratchbuf);
14363 *obufp++ = close_char;
14366 else if (intel_syntax)
14368 if (!active_seg_prefix)
14370 oappend (names_seg[ds_reg - es_reg]);
14373 print_operand_value (scratchbuf, 1, disp & 0xffff);
14374 oappend (scratchbuf);
14377 if (vex.evex && vex.b
14378 && (bytemode == x_mode
14379 || bytemode == xmmq_mode
14380 || bytemode == evex_half_bcst_xmmq_mode))
14383 || bytemode == xmmq_mode
14384 || bytemode == evex_half_bcst_xmmq_mode)
14386 switch (vex.length)
14389 oappend ("{1to2}");
14392 oappend ("{1to4}");
14395 oappend ("{1to8}");
14403 switch (vex.length)
14406 oappend ("{1to4}");
14409 oappend ("{1to8}");
14412 oappend ("{1to16}");
14422 OP_E (int bytemode, int sizeflag)
14424 /* Skip mod/rm byte. */
14428 if (modrm.mod == 3)
14429 OP_E_register (bytemode, sizeflag);
14431 OP_E_memory (bytemode, sizeflag);
14435 OP_G (int bytemode, int sizeflag)
14438 const char **names;
14447 oappend (names8rex[modrm.reg + add]);
14449 oappend (names8[modrm.reg + add]);
14452 oappend (names16[modrm.reg + add]);
14457 oappend (names32[modrm.reg + add]);
14460 oappend (names64[modrm.reg + add]);
14463 if (modrm.reg > 0x3)
14468 oappend (names_bnd[modrm.reg]);
14477 oappend (names64[modrm.reg + add]);
14480 if ((sizeflag & DFLAG) || bytemode != v_mode)
14481 oappend (names32[modrm.reg + add]);
14483 oappend (names16[modrm.reg + add]);
14484 used_prefixes |= (prefixes & PREFIX_DATA);
14488 names = (address_mode == mode_64bit
14489 ? names64 : names32);
14490 if (!(prefixes & PREFIX_ADDR))
14492 if (address_mode == mode_16bit)
14497 /* Remove "addr16/addr32". */
14498 all_prefixes[last_addr_prefix] = 0;
14499 names = (address_mode != mode_32bit
14500 ? names32 : names16);
14501 used_prefixes |= PREFIX_ADDR;
14503 oappend (names[modrm.reg + add]);
14506 if (address_mode == mode_64bit)
14507 oappend (names64[modrm.reg + add]);
14509 oappend (names32[modrm.reg + add]);
14513 if ((modrm.reg + add) > 0x7)
14518 oappend (names_mask[modrm.reg + add]);
14521 oappend (INTERNAL_DISASSEMBLER_ERROR);
14534 FETCH_DATA (the_info, codep + 8);
14535 a = *codep++ & 0xff;
14536 a |= (*codep++ & 0xff) << 8;
14537 a |= (*codep++ & 0xff) << 16;
14538 a |= (*codep++ & 0xffu) << 24;
14539 b = *codep++ & 0xff;
14540 b |= (*codep++ & 0xff) << 8;
14541 b |= (*codep++ & 0xff) << 16;
14542 b |= (*codep++ & 0xffu) << 24;
14543 x = a + ((bfd_vma) b << 32);
14551 static bfd_signed_vma
14554 bfd_signed_vma x = 0;
14556 FETCH_DATA (the_info, codep + 4);
14557 x = *codep++ & (bfd_signed_vma) 0xff;
14558 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14559 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14560 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14564 static bfd_signed_vma
14567 bfd_signed_vma x = 0;
14569 FETCH_DATA (the_info, codep + 4);
14570 x = *codep++ & (bfd_signed_vma) 0xff;
14571 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14572 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14573 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14575 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14585 FETCH_DATA (the_info, codep + 2);
14586 x = *codep++ & 0xff;
14587 x |= (*codep++ & 0xff) << 8;
14592 set_op (bfd_vma op, int riprel)
14594 op_index[op_ad] = op_ad;
14595 if (address_mode == mode_64bit)
14597 op_address[op_ad] = op;
14598 op_riprel[op_ad] = riprel;
14602 /* Mask to get a 32-bit address. */
14603 op_address[op_ad] = op & 0xffffffff;
14604 op_riprel[op_ad] = riprel & 0xffffffff;
14609 OP_REG (int code, int sizeflag)
14616 case es_reg: case ss_reg: case cs_reg:
14617 case ds_reg: case fs_reg: case gs_reg:
14618 oappend (names_seg[code - es_reg]);
14630 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14631 case sp_reg: case bp_reg: case si_reg: case di_reg:
14632 s = names16[code - ax_reg + add];
14634 case al_reg: case ah_reg: case cl_reg: case ch_reg:
14635 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14638 s = names8rex[code - al_reg + add];
14640 s = names8[code - al_reg];
14642 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14643 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14644 if (address_mode == mode_64bit
14645 && ((sizeflag & DFLAG) || (rex & REX_W)))
14647 s = names64[code - rAX_reg + add];
14650 code += eAX_reg - rAX_reg;
14651 /* Fall through. */
14652 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14653 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14656 s = names64[code - eAX_reg + add];
14659 if (sizeflag & DFLAG)
14660 s = names32[code - eAX_reg + add];
14662 s = names16[code - eAX_reg + add];
14663 used_prefixes |= (prefixes & PREFIX_DATA);
14667 s = INTERNAL_DISASSEMBLER_ERROR;
14674 OP_IMREG (int code, int sizeflag)
14686 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14687 case sp_reg: case bp_reg: case si_reg: case di_reg:
14688 s = names16[code - ax_reg];
14690 case es_reg: case ss_reg: case cs_reg:
14691 case ds_reg: case fs_reg: case gs_reg:
14692 s = names_seg[code - es_reg];
14694 case al_reg: case ah_reg: case cl_reg: case ch_reg:
14695 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14698 s = names8rex[code - al_reg];
14700 s = names8[code - al_reg];
14702 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14703 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14706 s = names64[code - eAX_reg];
14709 if (sizeflag & DFLAG)
14710 s = names32[code - eAX_reg];
14712 s = names16[code - eAX_reg];
14713 used_prefixes |= (prefixes & PREFIX_DATA);
14716 case z_mode_ax_reg:
14717 if ((rex & REX_W) || (sizeflag & DFLAG))
14721 if (!(rex & REX_W))
14722 used_prefixes |= (prefixes & PREFIX_DATA);
14725 s = INTERNAL_DISASSEMBLER_ERROR;
14732 OP_I (int bytemode, int sizeflag)
14735 bfd_signed_vma mask = -1;
14740 FETCH_DATA (the_info, codep + 1);
14745 if (address_mode == mode_64bit)
14750 /* Fall through. */
14757 if (sizeflag & DFLAG)
14767 used_prefixes |= (prefixes & PREFIX_DATA);
14779 oappend (INTERNAL_DISASSEMBLER_ERROR);
14784 scratchbuf[0] = '$';
14785 print_operand_value (scratchbuf + 1, 1, op);
14786 oappend_maybe_intel (scratchbuf);
14787 scratchbuf[0] = '\0';
14791 OP_I64 (int bytemode, int sizeflag)
14794 bfd_signed_vma mask = -1;
14796 if (address_mode != mode_64bit)
14798 OP_I (bytemode, sizeflag);
14805 FETCH_DATA (the_info, codep + 1);
14815 if (sizeflag & DFLAG)
14825 used_prefixes |= (prefixes & PREFIX_DATA);
14833 oappend (INTERNAL_DISASSEMBLER_ERROR);
14838 scratchbuf[0] = '$';
14839 print_operand_value (scratchbuf + 1, 1, op);
14840 oappend_maybe_intel (scratchbuf);
14841 scratchbuf[0] = '\0';
14845 OP_sI (int bytemode, int sizeflag)
14853 FETCH_DATA (the_info, codep + 1);
14855 if ((op & 0x80) != 0)
14857 if (bytemode == b_T_mode)
14859 if (address_mode != mode_64bit
14860 || !((sizeflag & DFLAG) || (rex & REX_W)))
14862 /* The operand-size prefix is overridden by a REX prefix. */
14863 if ((sizeflag & DFLAG) || (rex & REX_W))
14871 if (!(rex & REX_W))
14873 if (sizeflag & DFLAG)
14881 /* The operand-size prefix is overridden by a REX prefix. */
14882 if ((sizeflag & DFLAG) || (rex & REX_W))
14888 oappend (INTERNAL_DISASSEMBLER_ERROR);
14892 scratchbuf[0] = '$';
14893 print_operand_value (scratchbuf + 1, 1, op);
14894 oappend_maybe_intel (scratchbuf);
14898 OP_J (int bytemode, int sizeflag)
14902 bfd_vma segment = 0;
14907 FETCH_DATA (the_info, codep + 1);
14909 if ((disp & 0x80) != 0)
14913 if (isa64 == amd64)
14915 if ((sizeflag & DFLAG)
14916 || (address_mode == mode_64bit
14917 && (isa64 != amd64 || (rex & REX_W))))
14922 if ((disp & 0x8000) != 0)
14924 /* In 16bit mode, address is wrapped around at 64k within
14925 the same segment. Otherwise, a data16 prefix on a jump
14926 instruction means that the pc is masked to 16 bits after
14927 the displacement is added! */
14929 if ((prefixes & PREFIX_DATA) == 0)
14930 segment = ((start_pc + (codep - start_codep))
14931 & ~((bfd_vma) 0xffff));
14933 if (address_mode != mode_64bit
14934 || (isa64 == amd64 && !(rex & REX_W)))
14935 used_prefixes |= (prefixes & PREFIX_DATA);
14938 oappend (INTERNAL_DISASSEMBLER_ERROR);
14941 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14943 print_operand_value (scratchbuf, 1, disp);
14944 oappend (scratchbuf);
14948 OP_SEG (int bytemode, int sizeflag)
14950 if (bytemode == w_mode)
14951 oappend (names_seg[modrm.reg]);
14953 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14957 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14961 if (sizeflag & DFLAG)
14971 used_prefixes |= (prefixes & PREFIX_DATA);
14973 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14975 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14976 oappend (scratchbuf);
14980 OP_OFF (int bytemode, int sizeflag)
14984 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14985 intel_operand_size (bytemode, sizeflag);
14988 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14995 if (!active_seg_prefix)
14997 oappend (names_seg[ds_reg - es_reg]);
15001 print_operand_value (scratchbuf, 1, off);
15002 oappend (scratchbuf);
15006 OP_OFF64 (int bytemode, int sizeflag)
15010 if (address_mode != mode_64bit
15011 || (prefixes & PREFIX_ADDR))
15013 OP_OFF (bytemode, sizeflag);
15017 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15018 intel_operand_size (bytemode, sizeflag);
15025 if (!active_seg_prefix)
15027 oappend (names_seg[ds_reg - es_reg]);
15031 print_operand_value (scratchbuf, 1, off);
15032 oappend (scratchbuf);
15036 ptr_reg (int code, int sizeflag)
15040 *obufp++ = open_char;
15041 used_prefixes |= (prefixes & PREFIX_ADDR);
15042 if (address_mode == mode_64bit)
15044 if (!(sizeflag & AFLAG))
15045 s = names32[code - eAX_reg];
15047 s = names64[code - eAX_reg];
15049 else if (sizeflag & AFLAG)
15050 s = names32[code - eAX_reg];
15052 s = names16[code - eAX_reg];
15054 *obufp++ = close_char;
15059 OP_ESreg (int code, int sizeflag)
15065 case 0x6d: /* insw/insl */
15066 intel_operand_size (z_mode, sizeflag);
15068 case 0xa5: /* movsw/movsl/movsq */
15069 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15070 case 0xab: /* stosw/stosl */
15071 case 0xaf: /* scasw/scasl */
15072 intel_operand_size (v_mode, sizeflag);
15075 intel_operand_size (b_mode, sizeflag);
15078 oappend_maybe_intel ("%es:");
15079 ptr_reg (code, sizeflag);
15083 OP_DSreg (int code, int sizeflag)
15089 case 0x6f: /* outsw/outsl */
15090 intel_operand_size (z_mode, sizeflag);
15092 case 0xa5: /* movsw/movsl/movsq */
15093 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15094 case 0xad: /* lodsw/lodsl/lodsq */
15095 intel_operand_size (v_mode, sizeflag);
15098 intel_operand_size (b_mode, sizeflag);
15101 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15102 default segment register DS is printed. */
15103 if (!active_seg_prefix)
15104 active_seg_prefix = PREFIX_DS;
15106 ptr_reg (code, sizeflag);
15110 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15118 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15120 all_prefixes[last_lock_prefix] = 0;
15121 used_prefixes |= PREFIX_LOCK;
15126 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15127 oappend_maybe_intel (scratchbuf);
15131 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15140 sprintf (scratchbuf, "db%d", modrm.reg + add);
15142 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15143 oappend (scratchbuf);
15147 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15149 sprintf (scratchbuf, "%%tr%d", modrm.reg);
15150 oappend_maybe_intel (scratchbuf);
15154 OP_R (int bytemode, int sizeflag)
15156 /* Skip mod/rm byte. */
15159 OP_E_register (bytemode, sizeflag);
15163 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15165 int reg = modrm.reg;
15166 const char **names;
15168 used_prefixes |= (prefixes & PREFIX_DATA);
15169 if (prefixes & PREFIX_DATA)
15178 oappend (names[reg]);
15182 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15184 int reg = modrm.reg;
15185 const char **names;
15197 && bytemode != xmm_mode
15198 && bytemode != xmmq_mode
15199 && bytemode != evex_half_bcst_xmmq_mode
15200 && bytemode != ymm_mode
15201 && bytemode != scalar_mode)
15203 switch (vex.length)
15210 || (bytemode != vex_vsib_q_w_dq_mode
15211 && bytemode != vex_vsib_q_w_d_mode))
15223 else if (bytemode == xmmq_mode
15224 || bytemode == evex_half_bcst_xmmq_mode)
15226 switch (vex.length)
15239 else if (bytemode == ymm_mode)
15243 oappend (names[reg]);
15247 OP_EM (int bytemode, int sizeflag)
15250 const char **names;
15252 if (modrm.mod != 3)
15255 && (bytemode == v_mode || bytemode == v_swap_mode))
15257 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15258 used_prefixes |= (prefixes & PREFIX_DATA);
15260 OP_E (bytemode, sizeflag);
15264 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15267 /* Skip mod/rm byte. */
15270 used_prefixes |= (prefixes & PREFIX_DATA);
15272 if (prefixes & PREFIX_DATA)
15281 oappend (names[reg]);
15284 /* cvt* are the only instructions in sse2 which have
15285 both SSE and MMX operands and also have 0x66 prefix
15286 in their opcode. 0x66 was originally used to differentiate
15287 between SSE and MMX instruction(operands). So we have to handle the
15288 cvt* separately using OP_EMC and OP_MXC */
15290 OP_EMC (int bytemode, int sizeflag)
15292 if (modrm.mod != 3)
15294 if (intel_syntax && bytemode == v_mode)
15296 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15297 used_prefixes |= (prefixes & PREFIX_DATA);
15299 OP_E (bytemode, sizeflag);
15303 /* Skip mod/rm byte. */
15306 used_prefixes |= (prefixes & PREFIX_DATA);
15307 oappend (names_mm[modrm.rm]);
15311 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15313 used_prefixes |= (prefixes & PREFIX_DATA);
15314 oappend (names_mm[modrm.reg]);
15318 OP_EX (int bytemode, int sizeflag)
15321 const char **names;
15323 /* Skip mod/rm byte. */
15327 if (modrm.mod != 3)
15329 OP_E_memory (bytemode, sizeflag);
15344 if ((sizeflag & SUFFIX_ALWAYS)
15345 && (bytemode == x_swap_mode
15346 || bytemode == d_swap_mode
15347 || bytemode == d_scalar_swap_mode
15348 || bytemode == q_swap_mode
15349 || bytemode == q_scalar_swap_mode))
15353 && bytemode != xmm_mode
15354 && bytemode != xmmdw_mode
15355 && bytemode != xmmqd_mode
15356 && bytemode != xmm_mb_mode
15357 && bytemode != xmm_mw_mode
15358 && bytemode != xmm_md_mode
15359 && bytemode != xmm_mq_mode
15360 && bytemode != xmm_mdq_mode
15361 && bytemode != xmmq_mode
15362 && bytemode != evex_half_bcst_xmmq_mode
15363 && bytemode != ymm_mode
15364 && bytemode != d_scalar_mode
15365 && bytemode != d_scalar_swap_mode
15366 && bytemode != q_scalar_mode
15367 && bytemode != q_scalar_swap_mode
15368 && bytemode != vex_scalar_w_dq_mode)
15370 switch (vex.length)
15385 else if (bytemode == xmmq_mode
15386 || bytemode == evex_half_bcst_xmmq_mode)
15388 switch (vex.length)
15401 else if (bytemode == ymm_mode)
15405 oappend (names[reg]);
15409 OP_MS (int bytemode, int sizeflag)
15411 if (modrm.mod == 3)
15412 OP_EM (bytemode, sizeflag);
15418 OP_XS (int bytemode, int sizeflag)
15420 if (modrm.mod == 3)
15421 OP_EX (bytemode, sizeflag);
15427 OP_M (int bytemode, int sizeflag)
15429 if (modrm.mod == 3)
15430 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15433 OP_E (bytemode, sizeflag);
15437 OP_0f07 (int bytemode, int sizeflag)
15439 if (modrm.mod != 3 || modrm.rm != 0)
15442 OP_E (bytemode, sizeflag);
15445 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15446 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15449 NOP_Fixup1 (int bytemode, int sizeflag)
15451 if ((prefixes & PREFIX_DATA) != 0
15454 && address_mode == mode_64bit))
15455 OP_REG (bytemode, sizeflag);
15457 strcpy (obuf, "nop");
15461 NOP_Fixup2 (int bytemode, int sizeflag)
15463 if ((prefixes & PREFIX_DATA) != 0
15466 && address_mode == mode_64bit))
15467 OP_IMREG (bytemode, sizeflag);
15470 static const char *const Suffix3DNow[] = {
15471 /* 00 */ NULL, NULL, NULL, NULL,
15472 /* 04 */ NULL, NULL, NULL, NULL,
15473 /* 08 */ NULL, NULL, NULL, NULL,
15474 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
15475 /* 10 */ NULL, NULL, NULL, NULL,
15476 /* 14 */ NULL, NULL, NULL, NULL,
15477 /* 18 */ NULL, NULL, NULL, NULL,
15478 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
15479 /* 20 */ NULL, NULL, NULL, NULL,
15480 /* 24 */ NULL, NULL, NULL, NULL,
15481 /* 28 */ NULL, NULL, NULL, NULL,
15482 /* 2C */ NULL, NULL, NULL, NULL,
15483 /* 30 */ NULL, NULL, NULL, NULL,
15484 /* 34 */ NULL, NULL, NULL, NULL,
15485 /* 38 */ NULL, NULL, NULL, NULL,
15486 /* 3C */ NULL, NULL, NULL, NULL,
15487 /* 40 */ NULL, NULL, NULL, NULL,
15488 /* 44 */ NULL, NULL, NULL, NULL,
15489 /* 48 */ NULL, NULL, NULL, NULL,
15490 /* 4C */ NULL, NULL, NULL, NULL,
15491 /* 50 */ NULL, NULL, NULL, NULL,
15492 /* 54 */ NULL, NULL, NULL, NULL,
15493 /* 58 */ NULL, NULL, NULL, NULL,
15494 /* 5C */ NULL, NULL, NULL, NULL,
15495 /* 60 */ NULL, NULL, NULL, NULL,
15496 /* 64 */ NULL, NULL, NULL, NULL,
15497 /* 68 */ NULL, NULL, NULL, NULL,
15498 /* 6C */ NULL, NULL, NULL, NULL,
15499 /* 70 */ NULL, NULL, NULL, NULL,
15500 /* 74 */ NULL, NULL, NULL, NULL,
15501 /* 78 */ NULL, NULL, NULL, NULL,
15502 /* 7C */ NULL, NULL, NULL, NULL,
15503 /* 80 */ NULL, NULL, NULL, NULL,
15504 /* 84 */ NULL, NULL, NULL, NULL,
15505 /* 88 */ NULL, NULL, "pfnacc", NULL,
15506 /* 8C */ NULL, NULL, "pfpnacc", NULL,
15507 /* 90 */ "pfcmpge", NULL, NULL, NULL,
15508 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
15509 /* 98 */ NULL, NULL, "pfsub", NULL,
15510 /* 9C */ NULL, NULL, "pfadd", NULL,
15511 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
15512 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
15513 /* A8 */ NULL, NULL, "pfsubr", NULL,
15514 /* AC */ NULL, NULL, "pfacc", NULL,
15515 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
15516 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
15517 /* B8 */ NULL, NULL, NULL, "pswapd",
15518 /* BC */ NULL, NULL, NULL, "pavgusb",
15519 /* C0 */ NULL, NULL, NULL, NULL,
15520 /* C4 */ NULL, NULL, NULL, NULL,
15521 /* C8 */ NULL, NULL, NULL, NULL,
15522 /* CC */ NULL, NULL, NULL, NULL,
15523 /* D0 */ NULL, NULL, NULL, NULL,
15524 /* D4 */ NULL, NULL, NULL, NULL,
15525 /* D8 */ NULL, NULL, NULL, NULL,
15526 /* DC */ NULL, NULL, NULL, NULL,
15527 /* E0 */ NULL, NULL, NULL, NULL,
15528 /* E4 */ NULL, NULL, NULL, NULL,
15529 /* E8 */ NULL, NULL, NULL, NULL,
15530 /* EC */ NULL, NULL, NULL, NULL,
15531 /* F0 */ NULL, NULL, NULL, NULL,
15532 /* F4 */ NULL, NULL, NULL, NULL,
15533 /* F8 */ NULL, NULL, NULL, NULL,
15534 /* FC */ NULL, NULL, NULL, NULL,
15538 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15540 const char *mnemonic;
15542 FETCH_DATA (the_info, codep + 1);
15543 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15544 place where an 8-bit immediate would normally go. ie. the last
15545 byte of the instruction. */
15546 obufp = mnemonicendp;
15547 mnemonic = Suffix3DNow[*codep++ & 0xff];
15549 oappend (mnemonic);
15552 /* Since a variable sized modrm/sib chunk is between the start
15553 of the opcode (0x0f0f) and the opcode suffix, we need to do
15554 all the modrm processing first, and don't know until now that
15555 we have a bad opcode. This necessitates some cleaning up. */
15556 op_out[0][0] = '\0';
15557 op_out[1][0] = '\0';
15560 mnemonicendp = obufp;
15563 static struct op simd_cmp_op[] =
15565 { STRING_COMMA_LEN ("eq") },
15566 { STRING_COMMA_LEN ("lt") },
15567 { STRING_COMMA_LEN ("le") },
15568 { STRING_COMMA_LEN ("unord") },
15569 { STRING_COMMA_LEN ("neq") },
15570 { STRING_COMMA_LEN ("nlt") },
15571 { STRING_COMMA_LEN ("nle") },
15572 { STRING_COMMA_LEN ("ord") }
15576 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15578 unsigned int cmp_type;
15580 FETCH_DATA (the_info, codep + 1);
15581 cmp_type = *codep++ & 0xff;
15582 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15585 char *p = mnemonicendp - 2;
15589 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15590 mnemonicendp += simd_cmp_op[cmp_type].len;
15594 /* We have a reserved extension byte. Output it directly. */
15595 scratchbuf[0] = '$';
15596 print_operand_value (scratchbuf + 1, 1, cmp_type);
15597 oappend_maybe_intel (scratchbuf);
15598 scratchbuf[0] = '\0';
15603 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
15604 int sizeflag ATTRIBUTE_UNUSED)
15606 /* mwaitx %eax,%ecx,%ebx */
15609 const char **names = (address_mode == mode_64bit
15610 ? names64 : names32);
15611 strcpy (op_out[0], names[0]);
15612 strcpy (op_out[1], names[1]);
15613 strcpy (op_out[2], names[3]);
15614 two_source_ops = 1;
15616 /* Skip mod/rm byte. */
15622 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15623 int sizeflag ATTRIBUTE_UNUSED)
15625 /* mwait %eax,%ecx */
15628 const char **names = (address_mode == mode_64bit
15629 ? names64 : names32);
15630 strcpy (op_out[0], names[0]);
15631 strcpy (op_out[1], names[1]);
15632 two_source_ops = 1;
15634 /* Skip mod/rm byte. */
15640 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15641 int sizeflag ATTRIBUTE_UNUSED)
15643 /* monitor %eax,%ecx,%edx" */
15646 const char **op1_names;
15647 const char **names = (address_mode == mode_64bit
15648 ? names64 : names32);
15650 if (!(prefixes & PREFIX_ADDR))
15651 op1_names = (address_mode == mode_16bit
15652 ? names16 : names);
15655 /* Remove "addr16/addr32". */
15656 all_prefixes[last_addr_prefix] = 0;
15657 op1_names = (address_mode != mode_32bit
15658 ? names32 : names16);
15659 used_prefixes |= PREFIX_ADDR;
15661 strcpy (op_out[0], op1_names[0]);
15662 strcpy (op_out[1], names[1]);
15663 strcpy (op_out[2], names[2]);
15664 two_source_ops = 1;
15666 /* Skip mod/rm byte. */
15674 /* Throw away prefixes and 1st. opcode byte. */
15675 codep = insn_codep + 1;
15680 REP_Fixup (int bytemode, int sizeflag)
15682 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15684 if (prefixes & PREFIX_REPZ)
15685 all_prefixes[last_repz_prefix] = REP_PREFIX;
15692 OP_IMREG (bytemode, sizeflag);
15695 OP_ESreg (bytemode, sizeflag);
15698 OP_DSreg (bytemode, sizeflag);
15706 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15710 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15712 if (prefixes & PREFIX_REPNZ)
15713 all_prefixes[last_repnz_prefix] = BND_PREFIX;
15716 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15720 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15721 int sizeflag ATTRIBUTE_UNUSED)
15723 if (active_seg_prefix == PREFIX_DS
15724 && (address_mode != mode_64bit || last_data_prefix < 0))
15726 /* NOTRACK prefix is only valid on indirect branch instructions.
15727 NB: DATA prefix is unsupported for Intel64. */
15728 active_seg_prefix = 0;
15729 all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15733 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15734 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15738 HLE_Fixup1 (int bytemode, int sizeflag)
15741 && (prefixes & PREFIX_LOCK) != 0)
15743 if (prefixes & PREFIX_REPZ)
15744 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15745 if (prefixes & PREFIX_REPNZ)
15746 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15749 OP_E (bytemode, sizeflag);
15752 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15753 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15757 HLE_Fixup2 (int bytemode, int sizeflag)
15759 if (modrm.mod != 3)
15761 if (prefixes & PREFIX_REPZ)
15762 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15763 if (prefixes & PREFIX_REPNZ)
15764 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15767 OP_E (bytemode, sizeflag);
15770 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15771 "xrelease" for memory operand. No check for LOCK prefix. */
15774 HLE_Fixup3 (int bytemode, int sizeflag)
15777 && last_repz_prefix > last_repnz_prefix
15778 && (prefixes & PREFIX_REPZ) != 0)
15779 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15781 OP_E (bytemode, sizeflag);
15785 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15790 /* Change cmpxchg8b to cmpxchg16b. */
15791 char *p = mnemonicendp - 2;
15792 mnemonicendp = stpcpy (p, "16b");
15795 else if ((prefixes & PREFIX_LOCK) != 0)
15797 if (prefixes & PREFIX_REPZ)
15798 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15799 if (prefixes & PREFIX_REPNZ)
15800 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15803 OP_M (bytemode, sizeflag);
15807 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15809 const char **names;
15813 switch (vex.length)
15827 oappend (names[reg]);
15831 CRC32_Fixup (int bytemode, int sizeflag)
15833 /* Add proper suffix to "crc32". */
15834 char *p = mnemonicendp;
15853 if (sizeflag & DFLAG)
15857 used_prefixes |= (prefixes & PREFIX_DATA);
15861 oappend (INTERNAL_DISASSEMBLER_ERROR);
15868 if (modrm.mod == 3)
15872 /* Skip mod/rm byte. */
15877 add = (rex & REX_B) ? 8 : 0;
15878 if (bytemode == b_mode)
15882 oappend (names8rex[modrm.rm + add]);
15884 oappend (names8[modrm.rm + add]);
15890 oappend (names64[modrm.rm + add]);
15891 else if ((prefixes & PREFIX_DATA))
15892 oappend (names16[modrm.rm + add]);
15894 oappend (names32[modrm.rm + add]);
15898 OP_E (bytemode, sizeflag);
15902 FXSAVE_Fixup (int bytemode, int sizeflag)
15904 /* Add proper suffix to "fxsave" and "fxrstor". */
15908 char *p = mnemonicendp;
15914 OP_M (bytemode, sizeflag);
15918 PCMPESTR_Fixup (int bytemode, int sizeflag)
15920 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15923 char *p = mnemonicendp;
15928 else if (sizeflag & SUFFIX_ALWAYS)
15935 OP_EX (bytemode, sizeflag);
15938 /* Display the destination register operand for instructions with
15942 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15945 const char **names;
15953 reg = vex.register_specifier;
15954 if (address_mode != mode_64bit)
15956 else if (vex.evex && !vex.v)
15959 if (bytemode == vex_scalar_mode)
15961 oappend (names_xmm[reg]);
15965 switch (vex.length)
15972 case vex_vsib_q_w_dq_mode:
15973 case vex_vsib_q_w_d_mode:
15989 names = names_mask;
16003 case vex_vsib_q_w_dq_mode:
16004 case vex_vsib_q_w_d_mode:
16005 names = vex.w ? names_ymm : names_xmm;
16014 names = names_mask;
16017 /* See PR binutils/20893 for a reproducer. */
16029 oappend (names[reg]);
16032 /* Get the VEX immediate byte without moving codep. */
16034 static unsigned char
16035 get_vex_imm8 (int sizeflag, int opnum)
16037 int bytes_before_imm = 0;
16039 if (modrm.mod != 3)
16041 /* There are SIB/displacement bytes. */
16042 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16044 /* 32/64 bit address mode */
16045 int base = modrm.rm;
16047 /* Check SIB byte. */
16050 FETCH_DATA (the_info, codep + 1);
16052 /* When decoding the third source, don't increase
16053 bytes_before_imm as this has already been incremented
16054 by one in OP_E_memory while decoding the second
16057 bytes_before_imm++;
16060 /* Don't increase bytes_before_imm when decoding the third source,
16061 it has already been incremented by OP_E_memory while decoding
16062 the second source operand. */
16068 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16069 SIB == 5, there is a 4 byte displacement. */
16071 /* No displacement. */
16073 /* Fall through. */
16075 /* 4 byte displacement. */
16076 bytes_before_imm += 4;
16079 /* 1 byte displacement. */
16080 bytes_before_imm++;
16087 /* 16 bit address mode */
16088 /* Don't increase bytes_before_imm when decoding the third source,
16089 it has already been incremented by OP_E_memory while decoding
16090 the second source operand. */
16096 /* When modrm.rm == 6, there is a 2 byte displacement. */
16098 /* No displacement. */
16100 /* Fall through. */
16102 /* 2 byte displacement. */
16103 bytes_before_imm += 2;
16106 /* 1 byte displacement: when decoding the third source,
16107 don't increase bytes_before_imm as this has already
16108 been incremented by one in OP_E_memory while decoding
16109 the second source operand. */
16111 bytes_before_imm++;
16119 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16120 return codep [bytes_before_imm];
16124 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16126 const char **names;
16128 if (reg == -1 && modrm.mod != 3)
16130 OP_E_memory (bytemode, sizeflag);
16142 if (address_mode != mode_64bit)
16146 switch (vex.length)
16157 oappend (names[reg]);
16161 OP_EX_VexImmW (int bytemode, int sizeflag)
16164 static unsigned char vex_imm8;
16166 if (vex_w_done == 0)
16170 /* Skip mod/rm byte. */
16174 vex_imm8 = get_vex_imm8 (sizeflag, 0);
16177 reg = vex_imm8 >> 4;
16179 OP_EX_VexReg (bytemode, sizeflag, reg);
16181 else if (vex_w_done == 1)
16186 reg = vex_imm8 >> 4;
16188 OP_EX_VexReg (bytemode, sizeflag, reg);
16192 /* Output the imm8 directly. */
16193 scratchbuf[0] = '$';
16194 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16195 oappend_maybe_intel (scratchbuf);
16196 scratchbuf[0] = '\0';
16202 OP_Vex_2src (int bytemode, int sizeflag)
16204 if (modrm.mod == 3)
16206 int reg = modrm.rm;
16210 oappend (names_xmm[reg]);
16215 && (bytemode == v_mode || bytemode == v_swap_mode))
16217 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16218 used_prefixes |= (prefixes & PREFIX_DATA);
16220 OP_E (bytemode, sizeflag);
16225 OP_Vex_2src_1 (int bytemode, int sizeflag)
16227 if (modrm.mod == 3)
16229 /* Skip mod/rm byte. */
16236 unsigned int reg = vex.register_specifier;
16238 if (address_mode != mode_64bit)
16240 oappend (names_xmm[reg]);
16243 OP_Vex_2src (bytemode, sizeflag);
16247 OP_Vex_2src_2 (int bytemode, int sizeflag)
16250 OP_Vex_2src (bytemode, sizeflag);
16253 unsigned int reg = vex.register_specifier;
16255 if (address_mode != mode_64bit)
16257 oappend (names_xmm[reg]);
16262 OP_EX_VexW (int bytemode, int sizeflag)
16268 /* Skip mod/rm byte. */
16273 reg = get_vex_imm8 (sizeflag, 0) >> 4;
16278 reg = get_vex_imm8 (sizeflag, 1) >> 4;
16281 OP_EX_VexReg (bytemode, sizeflag, reg);
16289 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16292 const char **names;
16294 FETCH_DATA (the_info, codep + 1);
16297 if (bytemode != x_mode)
16301 if (address_mode != mode_64bit)
16304 switch (vex.length)
16315 oappend (names[reg]);
16319 OP_XMM_VexW (int bytemode, int sizeflag)
16321 /* Turn off the REX.W bit since it is used for swapping operands
16324 OP_XMM (bytemode, sizeflag);
16328 OP_EX_Vex (int bytemode, int sizeflag)
16330 if (modrm.mod != 3)
16332 if (vex.register_specifier != 0)
16336 OP_EX (bytemode, sizeflag);
16340 OP_XMM_Vex (int bytemode, int sizeflag)
16342 if (modrm.mod != 3)
16344 if (vex.register_specifier != 0)
16348 OP_XMM (bytemode, sizeflag);
16351 static struct op vex_cmp_op[] =
16353 { STRING_COMMA_LEN ("eq") },
16354 { STRING_COMMA_LEN ("lt") },
16355 { STRING_COMMA_LEN ("le") },
16356 { STRING_COMMA_LEN ("unord") },
16357 { STRING_COMMA_LEN ("neq") },
16358 { STRING_COMMA_LEN ("nlt") },
16359 { STRING_COMMA_LEN ("nle") },
16360 { STRING_COMMA_LEN ("ord") },
16361 { STRING_COMMA_LEN ("eq_uq") },
16362 { STRING_COMMA_LEN ("nge") },
16363 { STRING_COMMA_LEN ("ngt") },
16364 { STRING_COMMA_LEN ("false") },
16365 { STRING_COMMA_LEN ("neq_oq") },
16366 { STRING_COMMA_LEN ("ge") },
16367 { STRING_COMMA_LEN ("gt") },
16368 { STRING_COMMA_LEN ("true") },
16369 { STRING_COMMA_LEN ("eq_os") },
16370 { STRING_COMMA_LEN ("lt_oq") },
16371 { STRING_COMMA_LEN ("le_oq") },
16372 { STRING_COMMA_LEN ("unord_s") },
16373 { STRING_COMMA_LEN ("neq_us") },
16374 { STRING_COMMA_LEN ("nlt_uq") },
16375 { STRING_COMMA_LEN ("nle_uq") },
16376 { STRING_COMMA_LEN ("ord_s") },
16377 { STRING_COMMA_LEN ("eq_us") },
16378 { STRING_COMMA_LEN ("nge_uq") },
16379 { STRING_COMMA_LEN ("ngt_uq") },
16380 { STRING_COMMA_LEN ("false_os") },
16381 { STRING_COMMA_LEN ("neq_os") },
16382 { STRING_COMMA_LEN ("ge_oq") },
16383 { STRING_COMMA_LEN ("gt_oq") },
16384 { STRING_COMMA_LEN ("true_us") },
16388 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16390 unsigned int cmp_type;
16392 FETCH_DATA (the_info, codep + 1);
16393 cmp_type = *codep++ & 0xff;
16394 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16397 char *p = mnemonicendp - 2;
16401 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16402 mnemonicendp += vex_cmp_op[cmp_type].len;
16406 /* We have a reserved extension byte. Output it directly. */
16407 scratchbuf[0] = '$';
16408 print_operand_value (scratchbuf + 1, 1, cmp_type);
16409 oappend_maybe_intel (scratchbuf);
16410 scratchbuf[0] = '\0';
16415 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16416 int sizeflag ATTRIBUTE_UNUSED)
16418 unsigned int cmp_type;
16423 FETCH_DATA (the_info, codep + 1);
16424 cmp_type = *codep++ & 0xff;
16425 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16426 If it's the case, print suffix, otherwise - print the immediate. */
16427 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16432 char *p = mnemonicendp - 2;
16434 /* vpcmp* can have both one- and two-lettered suffix. */
16448 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16449 mnemonicendp += simd_cmp_op[cmp_type].len;
16453 /* We have a reserved extension byte. Output it directly. */
16454 scratchbuf[0] = '$';
16455 print_operand_value (scratchbuf + 1, 1, cmp_type);
16456 oappend_maybe_intel (scratchbuf);
16457 scratchbuf[0] = '\0';
16461 static const struct op xop_cmp_op[] =
16463 { STRING_COMMA_LEN ("lt") },
16464 { STRING_COMMA_LEN ("le") },
16465 { STRING_COMMA_LEN ("gt") },
16466 { STRING_COMMA_LEN ("ge") },
16467 { STRING_COMMA_LEN ("eq") },
16468 { STRING_COMMA_LEN ("neq") },
16469 { STRING_COMMA_LEN ("false") },
16470 { STRING_COMMA_LEN ("true") }
16474 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16475 int sizeflag ATTRIBUTE_UNUSED)
16477 unsigned int cmp_type;
16479 FETCH_DATA (the_info, codep + 1);
16480 cmp_type = *codep++ & 0xff;
16481 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16484 char *p = mnemonicendp - 2;
16486 /* vpcom* can have both one- and two-lettered suffix. */
16500 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16501 mnemonicendp += xop_cmp_op[cmp_type].len;
16505 /* We have a reserved extension byte. Output it directly. */
16506 scratchbuf[0] = '$';
16507 print_operand_value (scratchbuf + 1, 1, cmp_type);
16508 oappend_maybe_intel (scratchbuf);
16509 scratchbuf[0] = '\0';
16513 static const struct op pclmul_op[] =
16515 { STRING_COMMA_LEN ("lql") },
16516 { STRING_COMMA_LEN ("hql") },
16517 { STRING_COMMA_LEN ("lqh") },
16518 { STRING_COMMA_LEN ("hqh") }
16522 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16523 int sizeflag ATTRIBUTE_UNUSED)
16525 unsigned int pclmul_type;
16527 FETCH_DATA (the_info, codep + 1);
16528 pclmul_type = *codep++ & 0xff;
16529 switch (pclmul_type)
16540 if (pclmul_type < ARRAY_SIZE (pclmul_op))
16543 char *p = mnemonicendp - 3;
16548 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16549 mnemonicendp += pclmul_op[pclmul_type].len;
16553 /* We have a reserved extension byte. Output it directly. */
16554 scratchbuf[0] = '$';
16555 print_operand_value (scratchbuf + 1, 1, pclmul_type);
16556 oappend_maybe_intel (scratchbuf);
16557 scratchbuf[0] = '\0';
16562 MOVBE_Fixup (int bytemode, int sizeflag)
16564 /* Add proper suffix to "movbe". */
16565 char *p = mnemonicendp;
16574 if (sizeflag & SUFFIX_ALWAYS)
16580 if (sizeflag & DFLAG)
16584 used_prefixes |= (prefixes & PREFIX_DATA);
16589 oappend (INTERNAL_DISASSEMBLER_ERROR);
16596 OP_M (bytemode, sizeflag);
16600 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16603 const char **names;
16605 /* Skip mod/rm byte. */
16619 oappend (names[reg]);
16623 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16625 const char **names;
16626 unsigned int reg = vex.register_specifier;
16633 if (address_mode != mode_64bit)
16635 oappend (names[reg]);
16639 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16642 || (bytemode != mask_mode && bytemode != mask_bd_mode))
16646 if ((rex & REX_R) != 0 || !vex.r)
16652 oappend (names_mask [modrm.reg]);
16656 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16659 || (bytemode != evex_rounding_mode
16660 && bytemode != evex_rounding_64_mode
16661 && bytemode != evex_sae_mode))
16663 if (modrm.mod == 3 && vex.b)
16666 case evex_rounding_64_mode:
16667 if (address_mode != mode_64bit)
16672 /* Fall through. */
16673 case evex_rounding_mode:
16674 oappend (names_rounding[vex.ll]);
16676 case evex_sae_mode: