1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
30 /* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
40 #include "opcode/i386.h"
41 #include "libiberty.h"
45 static int print_insn (bfd_vma, disassemble_info *);
46 static void dofloat (int);
47 static void OP_ST (int, int);
48 static void OP_STi (int, int);
49 static int putop (const char *, int);
50 static void oappend (const char *);
51 static void append_seg (void);
52 static void OP_indirE (int, int);
53 static void print_operand_value (char *, int, bfd_vma);
54 static void OP_E_register (int, int);
55 static void OP_E_memory (int, int);
56 static void print_displacement (char *, bfd_vma);
57 static void OP_E (int, int);
58 static void OP_G (int, int);
59 static bfd_vma get64 (void);
60 static bfd_signed_vma get32 (void);
61 static bfd_signed_vma get32s (void);
62 static int get16 (void);
63 static void set_op (bfd_vma, int);
64 static void OP_Skip_MODRM (int, int);
65 static void OP_REG (int, int);
66 static void OP_IMREG (int, int);
67 static void OP_I (int, int);
68 static void OP_I64 (int, int);
69 static void OP_sI (int, int);
70 static void OP_J (int, int);
71 static void OP_SEG (int, int);
72 static void OP_DIR (int, int);
73 static void OP_OFF (int, int);
74 static void OP_OFF64 (int, int);
75 static void ptr_reg (int, int);
76 static void OP_ESreg (int, int);
77 static void OP_DSreg (int, int);
78 static void OP_C (int, int);
79 static void OP_D (int, int);
80 static void OP_T (int, int);
81 static void OP_R (int, int);
82 static void OP_MMX (int, int);
83 static void OP_XMM (int, int);
84 static void OP_EM (int, int);
85 static void OP_EX (int, int);
86 static void OP_EMC (int,int);
87 static void OP_MXC (int,int);
88 static void OP_MS (int, int);
89 static void OP_XS (int, int);
90 static void OP_M (int, int);
91 static void OP_VEX (int, int);
92 static void OP_EX_Vex (int, int);
93 static void OP_EX_VexW (int, int);
94 static void OP_EX_VexImmW (int, int);
95 static void OP_XMM_Vex (int, int);
96 static void OP_XMM_VexW (int, int);
97 static void OP_REG_VexI4 (int, int);
98 static void PCLMUL_Fixup (int, int);
99 static void VEXI4_Fixup (int, int);
100 static void VZERO_Fixup (int, int);
101 static void VCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void CMPXCHG8B_Fixup (int, int);
112 static void XMM_Fixup (int, int);
113 static void CRC32_Fixup (int, int);
114 static void FXSAVE_Fixup (int, int);
115 static void OP_LWPCB_E (int, int);
116 static void OP_LWP_E (int, int);
117 static void OP_Vex_2src_1 (int, int);
118 static void OP_Vex_2src_2 (int, int);
120 static void MOVBE_Fixup (int, int);
123 /* Points to first byte not fetched. */
124 bfd_byte *max_fetched;
125 bfd_byte the_buffer[MAX_MNEM_SIZE];
138 enum address_mode address_mode;
140 /* Flags for the prefixes for the current instruction. See below. */
143 /* REX prefix the current instruction. See below. */
145 /* Bits of REX we've already used. */
147 /* REX bits in original REX prefix ignored. */
148 static int rex_ignored;
149 /* Mark parts used in the REX prefix. When we are testing for
150 empty prefix (for 8bit register REX extension), just mask it
151 out. Otherwise test for REX bit is excuse for existence of REX
152 only in case value is nonzero. */
153 #define USED_REX(value) \
158 rex_used |= (value) | REX_OPCODE; \
161 rex_used |= REX_OPCODE; \
164 /* Flags for prefixes which we somehow handled when printing the
165 current instruction. */
166 static int used_prefixes;
168 /* Flags stored in PREFIXES. */
169 #define PREFIX_REPZ 1
170 #define PREFIX_REPNZ 2
171 #define PREFIX_LOCK 4
173 #define PREFIX_SS 0x10
174 #define PREFIX_DS 0x20
175 #define PREFIX_ES 0x40
176 #define PREFIX_FS 0x80
177 #define PREFIX_GS 0x100
178 #define PREFIX_DATA 0x200
179 #define PREFIX_ADDR 0x400
180 #define PREFIX_FWAIT 0x800
182 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
183 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
185 #define FETCH_DATA(info, addr) \
186 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
187 ? 1 : fetch_data ((info), (addr)))
190 fetch_data (struct disassemble_info *info, bfd_byte *addr)
193 struct dis_private *priv = (struct dis_private *) info->private_data;
194 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
196 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
197 status = (*info->read_memory_func) (start,
199 addr - priv->max_fetched,
205 /* If we did manage to read at least one byte, then
206 print_insn_i386 will do something sensible. Otherwise, print
207 an error. We do that here because this is where we know
209 if (priv->max_fetched == priv->the_buffer)
210 (*info->memory_error_func) (status, start, info);
211 longjmp (priv->bailout, 1);
214 priv->max_fetched = addr;
218 #define XX { NULL, 0 }
219 #define Bad_Opcode NULL, { { NULL, 0 } }
221 #define Eb { OP_E, b_mode }
222 #define EbS { OP_E, b_swap_mode }
223 #define Ev { OP_E, v_mode }
224 #define EvS { OP_E, v_swap_mode }
225 #define Ed { OP_E, d_mode }
226 #define Edq { OP_E, dq_mode }
227 #define Edqw { OP_E, dqw_mode }
228 #define Edqb { OP_E, dqb_mode }
229 #define Edqd { OP_E, dqd_mode }
230 #define Eq { OP_E, q_mode }
231 #define indirEv { OP_indirE, stack_v_mode }
232 #define indirEp { OP_indirE, f_mode }
233 #define stackEv { OP_E, stack_v_mode }
234 #define Em { OP_E, m_mode }
235 #define Ew { OP_E, w_mode }
236 #define M { OP_M, 0 } /* lea, lgdt, etc. */
237 #define Ma { OP_M, a_mode }
238 #define Mb { OP_M, b_mode }
239 #define Md { OP_M, d_mode }
240 #define Mo { OP_M, o_mode }
241 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
242 #define Mq { OP_M, q_mode }
243 #define Mx { OP_M, x_mode }
244 #define Mxmm { OP_M, xmm_mode }
245 #define Gb { OP_G, b_mode }
246 #define Gv { OP_G, v_mode }
247 #define Gd { OP_G, d_mode }
248 #define Gdq { OP_G, dq_mode }
249 #define Gm { OP_G, m_mode }
250 #define Gw { OP_G, w_mode }
251 #define Rd { OP_R, d_mode }
252 #define Rm { OP_R, m_mode }
253 #define Ib { OP_I, b_mode }
254 #define sIb { OP_sI, b_mode } /* sign extened byte */
255 #define Iv { OP_I, v_mode }
256 #define Iq { OP_I, q_mode }
257 #define Iv64 { OP_I64, v_mode }
258 #define Iw { OP_I, w_mode }
259 #define I1 { OP_I, const_1_mode }
260 #define Jb { OP_J, b_mode }
261 #define Jv { OP_J, v_mode }
262 #define Cm { OP_C, m_mode }
263 #define Dm { OP_D, m_mode }
264 #define Td { OP_T, d_mode }
265 #define Skip_MODRM { OP_Skip_MODRM, 0 }
267 #define RMeAX { OP_REG, eAX_reg }
268 #define RMeBX { OP_REG, eBX_reg }
269 #define RMeCX { OP_REG, eCX_reg }
270 #define RMeDX { OP_REG, eDX_reg }
271 #define RMeSP { OP_REG, eSP_reg }
272 #define RMeBP { OP_REG, eBP_reg }
273 #define RMeSI { OP_REG, eSI_reg }
274 #define RMeDI { OP_REG, eDI_reg }
275 #define RMrAX { OP_REG, rAX_reg }
276 #define RMrBX { OP_REG, rBX_reg }
277 #define RMrCX { OP_REG, rCX_reg }
278 #define RMrDX { OP_REG, rDX_reg }
279 #define RMrSP { OP_REG, rSP_reg }
280 #define RMrBP { OP_REG, rBP_reg }
281 #define RMrSI { OP_REG, rSI_reg }
282 #define RMrDI { OP_REG, rDI_reg }
283 #define RMAL { OP_REG, al_reg }
284 #define RMAL { OP_REG, al_reg }
285 #define RMCL { OP_REG, cl_reg }
286 #define RMDL { OP_REG, dl_reg }
287 #define RMBL { OP_REG, bl_reg }
288 #define RMAH { OP_REG, ah_reg }
289 #define RMCH { OP_REG, ch_reg }
290 #define RMDH { OP_REG, dh_reg }
291 #define RMBH { OP_REG, bh_reg }
292 #define RMAX { OP_REG, ax_reg }
293 #define RMDX { OP_REG, dx_reg }
295 #define eAX { OP_IMREG, eAX_reg }
296 #define eBX { OP_IMREG, eBX_reg }
297 #define eCX { OP_IMREG, eCX_reg }
298 #define eDX { OP_IMREG, eDX_reg }
299 #define eSP { OP_IMREG, eSP_reg }
300 #define eBP { OP_IMREG, eBP_reg }
301 #define eSI { OP_IMREG, eSI_reg }
302 #define eDI { OP_IMREG, eDI_reg }
303 #define AL { OP_IMREG, al_reg }
304 #define CL { OP_IMREG, cl_reg }
305 #define DL { OP_IMREG, dl_reg }
306 #define BL { OP_IMREG, bl_reg }
307 #define AH { OP_IMREG, ah_reg }
308 #define CH { OP_IMREG, ch_reg }
309 #define DH { OP_IMREG, dh_reg }
310 #define BH { OP_IMREG, bh_reg }
311 #define AX { OP_IMREG, ax_reg }
312 #define DX { OP_IMREG, dx_reg }
313 #define zAX { OP_IMREG, z_mode_ax_reg }
314 #define indirDX { OP_IMREG, indir_dx_reg }
316 #define Sw { OP_SEG, w_mode }
317 #define Sv { OP_SEG, v_mode }
318 #define Ap { OP_DIR, 0 }
319 #define Ob { OP_OFF64, b_mode }
320 #define Ov { OP_OFF64, v_mode }
321 #define Xb { OP_DSreg, eSI_reg }
322 #define Xv { OP_DSreg, eSI_reg }
323 #define Xz { OP_DSreg, eSI_reg }
324 #define Yb { OP_ESreg, eDI_reg }
325 #define Yv { OP_ESreg, eDI_reg }
326 #define DSBX { OP_DSreg, eBX_reg }
328 #define es { OP_REG, es_reg }
329 #define ss { OP_REG, ss_reg }
330 #define cs { OP_REG, cs_reg }
331 #define ds { OP_REG, ds_reg }
332 #define fs { OP_REG, fs_reg }
333 #define gs { OP_REG, gs_reg }
335 #define MX { OP_MMX, 0 }
336 #define XM { OP_XMM, 0 }
337 #define XMScalar { OP_XMM, scalar_mode }
338 #define XMM { OP_XMM, xmm_mode }
339 #define EM { OP_EM, v_mode }
340 #define EMS { OP_EM, v_swap_mode }
341 #define EMd { OP_EM, d_mode }
342 #define EMx { OP_EM, x_mode }
343 #define EXw { OP_EX, w_mode }
344 #define EXd { OP_EX, d_mode }
345 #define EXdScalar { OP_EX, d_scalar_mode }
346 #define EXdS { OP_EX, d_swap_mode }
347 #define EXq { OP_EX, q_mode }
348 #define EXqScalar { OP_EX, q_scalar_mode }
349 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
350 #define EXqS { OP_EX, q_swap_mode }
351 #define EXx { OP_EX, x_mode }
352 #define EXxS { OP_EX, x_swap_mode }
353 #define EXxmm { OP_EX, xmm_mode }
354 #define EXxmmq { OP_EX, xmmq_mode }
355 #define EXymmq { OP_EX, ymmq_mode }
356 #define EXVexWdq { OP_EX, vex_w_dq_mode }
357 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
358 #define MS { OP_MS, v_mode }
359 #define XS { OP_XS, v_mode }
360 #define EMCq { OP_EMC, q_mode }
361 #define MXC { OP_MXC, 0 }
362 #define OPSUF { OP_3DNowSuffix, 0 }
363 #define CMP { CMP_Fixup, 0 }
364 #define XMM0 { XMM_Fixup, 0 }
365 #define FXSAVE { FXSAVE_Fixup, 0 }
366 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
367 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
369 #define Vex { OP_VEX, vex_mode }
370 #define VexScalar { OP_VEX, vex_scalar_mode }
371 #define Vex128 { OP_VEX, vex128_mode }
372 #define Vex256 { OP_VEX, vex256_mode }
373 #define VexI4 { VEXI4_Fixup, 0}
374 #define EXdVex { OP_EX_Vex, d_mode }
375 #define EXdVexS { OP_EX_Vex, d_swap_mode }
376 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
377 #define EXqVex { OP_EX_Vex, q_mode }
378 #define EXqVexS { OP_EX_Vex, q_swap_mode }
379 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
380 #define EXVexW { OP_EX_VexW, x_mode }
381 #define EXdVexW { OP_EX_VexW, d_mode }
382 #define EXqVexW { OP_EX_VexW, q_mode }
383 #define EXVexImmW { OP_EX_VexImmW, x_mode }
384 #define XMVex { OP_XMM_Vex, 0 }
385 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
386 #define XMVexW { OP_XMM_VexW, 0 }
387 #define XMVexI4 { OP_REG_VexI4, x_mode }
388 #define PCLMUL { PCLMUL_Fixup, 0 }
389 #define VZERO { VZERO_Fixup, 0 }
390 #define VCMP { VCMP_Fixup, 0 }
392 /* Used handle "rep" prefix for string instructions. */
393 #define Xbr { REP_Fixup, eSI_reg }
394 #define Xvr { REP_Fixup, eSI_reg }
395 #define Ybr { REP_Fixup, eDI_reg }
396 #define Yvr { REP_Fixup, eDI_reg }
397 #define Yzr { REP_Fixup, eDI_reg }
398 #define indirDXr { REP_Fixup, indir_dx_reg }
399 #define ALr { REP_Fixup, al_reg }
400 #define eAXr { REP_Fixup, eAX_reg }
402 #define cond_jump_flag { NULL, cond_jump_mode }
403 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
405 /* bits in sizeflag */
406 #define SUFFIX_ALWAYS 4
414 /* byte operand with operand swapped */
416 /* operand size depends on prefixes */
418 /* operand size depends on prefixes with operand swapped */
422 /* double word operand */
424 /* double word operand with operand swapped */
426 /* quad word operand */
428 /* quad word operand with operand swapped */
430 /* ten-byte operand */
432 /* 16-byte XMM or 32-byte YMM operand */
434 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
436 /* 16-byte XMM operand */
438 /* 16-byte XMM or quad word operand */
440 /* 32-byte YMM or quad word operand */
442 /* d_mode in 32bit, q_mode in 64bit mode. */
444 /* pair of v_mode operands */
448 /* operand size depends on REX prefixes. */
450 /* registers like dq_mode, memory like w_mode. */
452 /* 4- or 6-byte pointer operand */
455 /* v_mode for stack-related opcodes. */
457 /* non-quad operand size depends on prefixes */
459 /* 16-byte operand */
461 /* registers like dq_mode, memory like b_mode. */
463 /* registers like dq_mode, memory like d_mode. */
465 /* normal vex mode */
467 /* 128bit vex mode */
469 /* 256bit vex mode */
471 /* operand size depends on the VEX.W bit. */
474 /* scalar, ignore vector length. */
476 /* like d_mode, ignore vector length. */
478 /* like d_swap_mode, ignore vector length. */
480 /* like q_mode, ignore vector length. */
482 /* like q_swap_mode, ignore vector length. */
484 /* like vex_mode, ignore vector length. */
486 /* like vex_w_dq_mode, ignore vector length. */
487 vex_scalar_w_dq_mode,
552 #define FLOAT NULL, { { NULL, FLOATCODE } }
554 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
555 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
556 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
557 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
558 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
559 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
560 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
561 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
562 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
563 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
564 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
565 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
683 MOD_VEX_3818_PREFIX_2,
684 MOD_VEX_3819_PREFIX_2,
685 MOD_VEX_381A_PREFIX_2,
686 MOD_VEX_382A_PREFIX_2,
687 MOD_VEX_382C_PREFIX_2,
688 MOD_VEX_382D_PREFIX_2,
689 MOD_VEX_382E_PREFIX_2,
690 MOD_VEX_382F_PREFIX_2
1102 THREE_BYTE_0F38 = 0,
1257 VEX_LEN_3819_P_2_M_0,
1258 VEX_LEN_381A_P_2_M_0,
1270 VEX_LEN_382A_P_2_M_0,
1588 typedef void (*op_rtn) (int bytemode, int sizeflag);
1599 /* Upper case letters in the instruction names here are macros.
1600 'A' => print 'b' if no register operands or suffix_always is true
1601 'B' => print 'b' if suffix_always is true
1602 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1604 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1605 suffix_always is true
1606 'E' => print 'e' if 32-bit form of jcxz
1607 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1608 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1609 'H' => print ",pt" or ",pn" branch hint
1610 'I' => honor following macro letter even in Intel mode (implemented only
1611 for some of the macro letters)
1613 'K' => print 'd' or 'q' if rex prefix is present.
1614 'L' => print 'l' if suffix_always is true
1615 'M' => print 'r' if intel_mnemonic is false.
1616 'N' => print 'n' if instruction has no wait "prefix"
1617 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1618 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1619 or suffix_always is true. print 'q' if rex prefix is present.
1620 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1622 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1623 'S' => print 'w', 'l' or 'q' if suffix_always is true
1624 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1625 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1626 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1627 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1628 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1629 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1630 suffix_always is true.
1631 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1632 '!' => change condition from true to false or from false to true.
1633 '%' => add 1 upper case letter to the macro.
1635 2 upper case letter macros:
1636 "XY" => print 'x' or 'y' if no register operands or suffix_always
1638 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1639 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1640 or suffix_always is true
1641 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1642 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1643 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1645 Many of the above letters print nothing in Intel mode. See "putop"
1648 Braces '{' and '}', and vertical bars '|', indicate alternative
1649 mnemonic strings for AT&T and Intel. */
1651 static const struct dis386 dis386[] = {
1653 { "addB", { Eb, Gb } },
1654 { "addS", { Ev, Gv } },
1655 { "addB", { Gb, EbS } },
1656 { "addS", { Gv, EvS } },
1657 { "addB", { AL, Ib } },
1658 { "addS", { eAX, Iv } },
1659 { X86_64_TABLE (X86_64_06) },
1660 { X86_64_TABLE (X86_64_07) },
1662 { "orB", { Eb, Gb } },
1663 { "orS", { Ev, Gv } },
1664 { "orB", { Gb, EbS } },
1665 { "orS", { Gv, EvS } },
1666 { "orB", { AL, Ib } },
1667 { "orS", { eAX, Iv } },
1668 { X86_64_TABLE (X86_64_0D) },
1669 { Bad_Opcode }, /* 0x0f extended opcode escape */
1671 { "adcB", { Eb, Gb } },
1672 { "adcS", { Ev, Gv } },
1673 { "adcB", { Gb, EbS } },
1674 { "adcS", { Gv, EvS } },
1675 { "adcB", { AL, Ib } },
1676 { "adcS", { eAX, Iv } },
1677 { X86_64_TABLE (X86_64_16) },
1678 { X86_64_TABLE (X86_64_17) },
1680 { "sbbB", { Eb, Gb } },
1681 { "sbbS", { Ev, Gv } },
1682 { "sbbB", { Gb, EbS } },
1683 { "sbbS", { Gv, EvS } },
1684 { "sbbB", { AL, Ib } },
1685 { "sbbS", { eAX, Iv } },
1686 { X86_64_TABLE (X86_64_1E) },
1687 { X86_64_TABLE (X86_64_1F) },
1689 { "andB", { Eb, Gb } },
1690 { "andS", { Ev, Gv } },
1691 { "andB", { Gb, EbS } },
1692 { "andS", { Gv, EvS } },
1693 { "andB", { AL, Ib } },
1694 { "andS", { eAX, Iv } },
1695 { Bad_Opcode }, /* SEG ES prefix */
1696 { X86_64_TABLE (X86_64_27) },
1698 { "subB", { Eb, Gb } },
1699 { "subS", { Ev, Gv } },
1700 { "subB", { Gb, EbS } },
1701 { "subS", { Gv, EvS } },
1702 { "subB", { AL, Ib } },
1703 { "subS", { eAX, Iv } },
1704 { Bad_Opcode }, /* SEG CS prefix */
1705 { X86_64_TABLE (X86_64_2F) },
1707 { "xorB", { Eb, Gb } },
1708 { "xorS", { Ev, Gv } },
1709 { "xorB", { Gb, EbS } },
1710 { "xorS", { Gv, EvS } },
1711 { "xorB", { AL, Ib } },
1712 { "xorS", { eAX, Iv } },
1713 { Bad_Opcode }, /* SEG SS prefix */
1714 { X86_64_TABLE (X86_64_37) },
1716 { "cmpB", { Eb, Gb } },
1717 { "cmpS", { Ev, Gv } },
1718 { "cmpB", { Gb, EbS } },
1719 { "cmpS", { Gv, EvS } },
1720 { "cmpB", { AL, Ib } },
1721 { "cmpS", { eAX, Iv } },
1722 { Bad_Opcode }, /* SEG DS prefix */
1723 { X86_64_TABLE (X86_64_3F) },
1725 { "inc{S|}", { RMeAX } },
1726 { "inc{S|}", { RMeCX } },
1727 { "inc{S|}", { RMeDX } },
1728 { "inc{S|}", { RMeBX } },
1729 { "inc{S|}", { RMeSP } },
1730 { "inc{S|}", { RMeBP } },
1731 { "inc{S|}", { RMeSI } },
1732 { "inc{S|}", { RMeDI } },
1734 { "dec{S|}", { RMeAX } },
1735 { "dec{S|}", { RMeCX } },
1736 { "dec{S|}", { RMeDX } },
1737 { "dec{S|}", { RMeBX } },
1738 { "dec{S|}", { RMeSP } },
1739 { "dec{S|}", { RMeBP } },
1740 { "dec{S|}", { RMeSI } },
1741 { "dec{S|}", { RMeDI } },
1743 { "pushV", { RMrAX } },
1744 { "pushV", { RMrCX } },
1745 { "pushV", { RMrDX } },
1746 { "pushV", { RMrBX } },
1747 { "pushV", { RMrSP } },
1748 { "pushV", { RMrBP } },
1749 { "pushV", { RMrSI } },
1750 { "pushV", { RMrDI } },
1752 { "popV", { RMrAX } },
1753 { "popV", { RMrCX } },
1754 { "popV", { RMrDX } },
1755 { "popV", { RMrBX } },
1756 { "popV", { RMrSP } },
1757 { "popV", { RMrBP } },
1758 { "popV", { RMrSI } },
1759 { "popV", { RMrDI } },
1761 { X86_64_TABLE (X86_64_60) },
1762 { X86_64_TABLE (X86_64_61) },
1763 { X86_64_TABLE (X86_64_62) },
1764 { X86_64_TABLE (X86_64_63) },
1765 { Bad_Opcode }, /* seg fs */
1766 { Bad_Opcode }, /* seg gs */
1767 { Bad_Opcode }, /* op size prefix */
1768 { Bad_Opcode }, /* adr size prefix */
1770 { "pushT", { Iq } },
1771 { "imulS", { Gv, Ev, Iv } },
1772 { "pushT", { sIb } },
1773 { "imulS", { Gv, Ev, sIb } },
1774 { "ins{b|}", { Ybr, indirDX } },
1775 { X86_64_TABLE (X86_64_6D) },
1776 { "outs{b|}", { indirDXr, Xb } },
1777 { X86_64_TABLE (X86_64_6F) },
1779 { "joH", { Jb, XX, cond_jump_flag } },
1780 { "jnoH", { Jb, XX, cond_jump_flag } },
1781 { "jbH", { Jb, XX, cond_jump_flag } },
1782 { "jaeH", { Jb, XX, cond_jump_flag } },
1783 { "jeH", { Jb, XX, cond_jump_flag } },
1784 { "jneH", { Jb, XX, cond_jump_flag } },
1785 { "jbeH", { Jb, XX, cond_jump_flag } },
1786 { "jaH", { Jb, XX, cond_jump_flag } },
1788 { "jsH", { Jb, XX, cond_jump_flag } },
1789 { "jnsH", { Jb, XX, cond_jump_flag } },
1790 { "jpH", { Jb, XX, cond_jump_flag } },
1791 { "jnpH", { Jb, XX, cond_jump_flag } },
1792 { "jlH", { Jb, XX, cond_jump_flag } },
1793 { "jgeH", { Jb, XX, cond_jump_flag } },
1794 { "jleH", { Jb, XX, cond_jump_flag } },
1795 { "jgH", { Jb, XX, cond_jump_flag } },
1797 { REG_TABLE (REG_80) },
1798 { REG_TABLE (REG_81) },
1800 { REG_TABLE (REG_82) },
1801 { "testB", { Eb, Gb } },
1802 { "testS", { Ev, Gv } },
1803 { "xchgB", { Eb, Gb } },
1804 { "xchgS", { Ev, Gv } },
1806 { "movB", { Eb, Gb } },
1807 { "movS", { Ev, Gv } },
1808 { "movB", { Gb, EbS } },
1809 { "movS", { Gv, EvS } },
1810 { "movD", { Sv, Sw } },
1811 { MOD_TABLE (MOD_8D) },
1812 { "movD", { Sw, Sv } },
1813 { REG_TABLE (REG_8F) },
1815 { PREFIX_TABLE (PREFIX_90) },
1816 { "xchgS", { RMeCX, eAX } },
1817 { "xchgS", { RMeDX, eAX } },
1818 { "xchgS", { RMeBX, eAX } },
1819 { "xchgS", { RMeSP, eAX } },
1820 { "xchgS", { RMeBP, eAX } },
1821 { "xchgS", { RMeSI, eAX } },
1822 { "xchgS", { RMeDI, eAX } },
1824 { "cW{t|}R", { XX } },
1825 { "cR{t|}O", { XX } },
1826 { X86_64_TABLE (X86_64_9A) },
1827 { Bad_Opcode }, /* fwait */
1828 { "pushfT", { XX } },
1829 { "popfT", { XX } },
1833 { "mov%LB", { AL, Ob } },
1834 { "mov%LS", { eAX, Ov } },
1835 { "mov%LB", { Ob, AL } },
1836 { "mov%LS", { Ov, eAX } },
1837 { "movs{b|}", { Ybr, Xb } },
1838 { "movs{R|}", { Yvr, Xv } },
1839 { "cmps{b|}", { Xb, Yb } },
1840 { "cmps{R|}", { Xv, Yv } },
1842 { "testB", { AL, Ib } },
1843 { "testS", { eAX, Iv } },
1844 { "stosB", { Ybr, AL } },
1845 { "stosS", { Yvr, eAX } },
1846 { "lodsB", { ALr, Xb } },
1847 { "lodsS", { eAXr, Xv } },
1848 { "scasB", { AL, Yb } },
1849 { "scasS", { eAX, Yv } },
1851 { "movB", { RMAL, Ib } },
1852 { "movB", { RMCL, Ib } },
1853 { "movB", { RMDL, Ib } },
1854 { "movB", { RMBL, Ib } },
1855 { "movB", { RMAH, Ib } },
1856 { "movB", { RMCH, Ib } },
1857 { "movB", { RMDH, Ib } },
1858 { "movB", { RMBH, Ib } },
1860 { "mov%LV", { RMeAX, Iv64 } },
1861 { "mov%LV", { RMeCX, Iv64 } },
1862 { "mov%LV", { RMeDX, Iv64 } },
1863 { "mov%LV", { RMeBX, Iv64 } },
1864 { "mov%LV", { RMeSP, Iv64 } },
1865 { "mov%LV", { RMeBP, Iv64 } },
1866 { "mov%LV", { RMeSI, Iv64 } },
1867 { "mov%LV", { RMeDI, Iv64 } },
1869 { REG_TABLE (REG_C0) },
1870 { REG_TABLE (REG_C1) },
1873 { X86_64_TABLE (X86_64_C4) },
1874 { X86_64_TABLE (X86_64_C5) },
1875 { REG_TABLE (REG_C6) },
1876 { REG_TABLE (REG_C7) },
1878 { "enterT", { Iw, Ib } },
1879 { "leaveT", { XX } },
1880 { "Jret{|f}P", { Iw } },
1881 { "Jret{|f}P", { XX } },
1884 { X86_64_TABLE (X86_64_CE) },
1885 { "iretP", { XX } },
1887 { REG_TABLE (REG_D0) },
1888 { REG_TABLE (REG_D1) },
1889 { REG_TABLE (REG_D2) },
1890 { REG_TABLE (REG_D3) },
1891 { X86_64_TABLE (X86_64_D4) },
1892 { X86_64_TABLE (X86_64_D5) },
1894 { "xlat", { DSBX } },
1905 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
1906 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
1907 { "loopFH", { Jb, XX, loop_jcxz_flag } },
1908 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
1909 { "inB", { AL, Ib } },
1910 { "inG", { zAX, Ib } },
1911 { "outB", { Ib, AL } },
1912 { "outG", { Ib, zAX } },
1914 { "callT", { Jv } },
1916 { X86_64_TABLE (X86_64_EA) },
1918 { "inB", { AL, indirDX } },
1919 { "inG", { zAX, indirDX } },
1920 { "outB", { indirDX, AL } },
1921 { "outG", { indirDX, zAX } },
1923 { Bad_Opcode }, /* lock prefix */
1924 { "icebp", { XX } },
1925 { Bad_Opcode }, /* repne */
1926 { Bad_Opcode }, /* repz */
1929 { REG_TABLE (REG_F6) },
1930 { REG_TABLE (REG_F7) },
1938 { REG_TABLE (REG_FE) },
1939 { REG_TABLE (REG_FF) },
1942 static const struct dis386 dis386_twobyte[] = {
1944 { REG_TABLE (REG_0F00 ) },
1945 { REG_TABLE (REG_0F01 ) },
1946 { "larS", { Gv, Ew } },
1947 { "lslS", { Gv, Ew } },
1949 { "syscall", { XX } },
1951 { "sysretP", { XX } },
1954 { "wbinvd", { XX } },
1958 { REG_TABLE (REG_0F0D) },
1959 { "femms", { XX } },
1960 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
1962 { PREFIX_TABLE (PREFIX_0F10) },
1963 { PREFIX_TABLE (PREFIX_0F11) },
1964 { PREFIX_TABLE (PREFIX_0F12) },
1965 { MOD_TABLE (MOD_0F13) },
1966 { "unpcklpX", { XM, EXx } },
1967 { "unpckhpX", { XM, EXx } },
1968 { PREFIX_TABLE (PREFIX_0F16) },
1969 { MOD_TABLE (MOD_0F17) },
1971 { REG_TABLE (REG_0F18) },
1980 { MOD_TABLE (MOD_0F20) },
1981 { MOD_TABLE (MOD_0F21) },
1982 { MOD_TABLE (MOD_0F22) },
1983 { MOD_TABLE (MOD_0F23) },
1984 { MOD_TABLE (MOD_0F24) },
1986 { MOD_TABLE (MOD_0F26) },
1989 { "movapX", { XM, EXx } },
1990 { "movapX", { EXxS, XM } },
1991 { PREFIX_TABLE (PREFIX_0F2A) },
1992 { PREFIX_TABLE (PREFIX_0F2B) },
1993 { PREFIX_TABLE (PREFIX_0F2C) },
1994 { PREFIX_TABLE (PREFIX_0F2D) },
1995 { PREFIX_TABLE (PREFIX_0F2E) },
1996 { PREFIX_TABLE (PREFIX_0F2F) },
1998 { "wrmsr", { XX } },
1999 { "rdtsc", { XX } },
2000 { "rdmsr", { XX } },
2001 { "rdpmc", { XX } },
2002 { "sysenter", { XX } },
2003 { "sysexit", { XX } },
2005 { "getsec", { XX } },
2007 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2009 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2016 { "cmovoS", { Gv, Ev } },
2017 { "cmovnoS", { Gv, Ev } },
2018 { "cmovbS", { Gv, Ev } },
2019 { "cmovaeS", { Gv, Ev } },
2020 { "cmoveS", { Gv, Ev } },
2021 { "cmovneS", { Gv, Ev } },
2022 { "cmovbeS", { Gv, Ev } },
2023 { "cmovaS", { Gv, Ev } },
2025 { "cmovsS", { Gv, Ev } },
2026 { "cmovnsS", { Gv, Ev } },
2027 { "cmovpS", { Gv, Ev } },
2028 { "cmovnpS", { Gv, Ev } },
2029 { "cmovlS", { Gv, Ev } },
2030 { "cmovgeS", { Gv, Ev } },
2031 { "cmovleS", { Gv, Ev } },
2032 { "cmovgS", { Gv, Ev } },
2034 { MOD_TABLE (MOD_0F51) },
2035 { PREFIX_TABLE (PREFIX_0F51) },
2036 { PREFIX_TABLE (PREFIX_0F52) },
2037 { PREFIX_TABLE (PREFIX_0F53) },
2038 { "andpX", { XM, EXx } },
2039 { "andnpX", { XM, EXx } },
2040 { "orpX", { XM, EXx } },
2041 { "xorpX", { XM, EXx } },
2043 { PREFIX_TABLE (PREFIX_0F58) },
2044 { PREFIX_TABLE (PREFIX_0F59) },
2045 { PREFIX_TABLE (PREFIX_0F5A) },
2046 { PREFIX_TABLE (PREFIX_0F5B) },
2047 { PREFIX_TABLE (PREFIX_0F5C) },
2048 { PREFIX_TABLE (PREFIX_0F5D) },
2049 { PREFIX_TABLE (PREFIX_0F5E) },
2050 { PREFIX_TABLE (PREFIX_0F5F) },
2052 { PREFIX_TABLE (PREFIX_0F60) },
2053 { PREFIX_TABLE (PREFIX_0F61) },
2054 { PREFIX_TABLE (PREFIX_0F62) },
2055 { "packsswb", { MX, EM } },
2056 { "pcmpgtb", { MX, EM } },
2057 { "pcmpgtw", { MX, EM } },
2058 { "pcmpgtd", { MX, EM } },
2059 { "packuswb", { MX, EM } },
2061 { "punpckhbw", { MX, EM } },
2062 { "punpckhwd", { MX, EM } },
2063 { "punpckhdq", { MX, EM } },
2064 { "packssdw", { MX, EM } },
2065 { PREFIX_TABLE (PREFIX_0F6C) },
2066 { PREFIX_TABLE (PREFIX_0F6D) },
2067 { "movK", { MX, Edq } },
2068 { PREFIX_TABLE (PREFIX_0F6F) },
2070 { PREFIX_TABLE (PREFIX_0F70) },
2071 { REG_TABLE (REG_0F71) },
2072 { REG_TABLE (REG_0F72) },
2073 { REG_TABLE (REG_0F73) },
2074 { "pcmpeqb", { MX, EM } },
2075 { "pcmpeqw", { MX, EM } },
2076 { "pcmpeqd", { MX, EM } },
2079 { PREFIX_TABLE (PREFIX_0F78) },
2080 { PREFIX_TABLE (PREFIX_0F79) },
2081 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2083 { PREFIX_TABLE (PREFIX_0F7C) },
2084 { PREFIX_TABLE (PREFIX_0F7D) },
2085 { PREFIX_TABLE (PREFIX_0F7E) },
2086 { PREFIX_TABLE (PREFIX_0F7F) },
2088 { "joH", { Jv, XX, cond_jump_flag } },
2089 { "jnoH", { Jv, XX, cond_jump_flag } },
2090 { "jbH", { Jv, XX, cond_jump_flag } },
2091 { "jaeH", { Jv, XX, cond_jump_flag } },
2092 { "jeH", { Jv, XX, cond_jump_flag } },
2093 { "jneH", { Jv, XX, cond_jump_flag } },
2094 { "jbeH", { Jv, XX, cond_jump_flag } },
2095 { "jaH", { Jv, XX, cond_jump_flag } },
2097 { "jsH", { Jv, XX, cond_jump_flag } },
2098 { "jnsH", { Jv, XX, cond_jump_flag } },
2099 { "jpH", { Jv, XX, cond_jump_flag } },
2100 { "jnpH", { Jv, XX, cond_jump_flag } },
2101 { "jlH", { Jv, XX, cond_jump_flag } },
2102 { "jgeH", { Jv, XX, cond_jump_flag } },
2103 { "jleH", { Jv, XX, cond_jump_flag } },
2104 { "jgH", { Jv, XX, cond_jump_flag } },
2107 { "setno", { Eb } },
2109 { "setae", { Eb } },
2111 { "setne", { Eb } },
2112 { "setbe", { Eb } },
2116 { "setns", { Eb } },
2118 { "setnp", { Eb } },
2120 { "setge", { Eb } },
2121 { "setle", { Eb } },
2124 { "pushT", { fs } },
2126 { "cpuid", { XX } },
2127 { "btS", { Ev, Gv } },
2128 { "shldS", { Ev, Gv, Ib } },
2129 { "shldS", { Ev, Gv, CL } },
2130 { REG_TABLE (REG_0FA6) },
2131 { REG_TABLE (REG_0FA7) },
2133 { "pushT", { gs } },
2136 { "btsS", { Ev, Gv } },
2137 { "shrdS", { Ev, Gv, Ib } },
2138 { "shrdS", { Ev, Gv, CL } },
2139 { REG_TABLE (REG_0FAE) },
2140 { "imulS", { Gv, Ev } },
2142 { "cmpxchgB", { Eb, Gb } },
2143 { "cmpxchgS", { Ev, Gv } },
2144 { MOD_TABLE (MOD_0FB2) },
2145 { "btrS", { Ev, Gv } },
2146 { MOD_TABLE (MOD_0FB4) },
2147 { MOD_TABLE (MOD_0FB5) },
2148 { "movz{bR|x}", { Gv, Eb } },
2149 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
2151 { PREFIX_TABLE (PREFIX_0FB8) },
2153 { REG_TABLE (REG_0FBA) },
2154 { "btcS", { Ev, Gv } },
2155 { "bsfS", { Gv, Ev } },
2156 { PREFIX_TABLE (PREFIX_0FBD) },
2157 { "movs{bR|x}", { Gv, Eb } },
2158 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
2160 { "xaddB", { Eb, Gb } },
2161 { "xaddS", { Ev, Gv } },
2162 { PREFIX_TABLE (PREFIX_0FC2) },
2163 { PREFIX_TABLE (PREFIX_0FC3) },
2164 { "pinsrw", { MX, Edqw, Ib } },
2165 { "pextrw", { Gdq, MS, Ib } },
2166 { "shufpX", { XM, EXx, Ib } },
2167 { REG_TABLE (REG_0FC7) },
2169 { "bswap", { RMeAX } },
2170 { "bswap", { RMeCX } },
2171 { "bswap", { RMeDX } },
2172 { "bswap", { RMeBX } },
2173 { "bswap", { RMeSP } },
2174 { "bswap", { RMeBP } },
2175 { "bswap", { RMeSI } },
2176 { "bswap", { RMeDI } },
2178 { PREFIX_TABLE (PREFIX_0FD0) },
2179 { "psrlw", { MX, EM } },
2180 { "psrld", { MX, EM } },
2181 { "psrlq", { MX, EM } },
2182 { "paddq", { MX, EM } },
2183 { "pmullw", { MX, EM } },
2184 { PREFIX_TABLE (PREFIX_0FD6) },
2185 { MOD_TABLE (MOD_0FD7) },
2187 { "psubusb", { MX, EM } },
2188 { "psubusw", { MX, EM } },
2189 { "pminub", { MX, EM } },
2190 { "pand", { MX, EM } },
2191 { "paddusb", { MX, EM } },
2192 { "paddusw", { MX, EM } },
2193 { "pmaxub", { MX, EM } },
2194 { "pandn", { MX, EM } },
2196 { "pavgb", { MX, EM } },
2197 { "psraw", { MX, EM } },
2198 { "psrad", { MX, EM } },
2199 { "pavgw", { MX, EM } },
2200 { "pmulhuw", { MX, EM } },
2201 { "pmulhw", { MX, EM } },
2202 { PREFIX_TABLE (PREFIX_0FE6) },
2203 { PREFIX_TABLE (PREFIX_0FE7) },
2205 { "psubsb", { MX, EM } },
2206 { "psubsw", { MX, EM } },
2207 { "pminsw", { MX, EM } },
2208 { "por", { MX, EM } },
2209 { "paddsb", { MX, EM } },
2210 { "paddsw", { MX, EM } },
2211 { "pmaxsw", { MX, EM } },
2212 { "pxor", { MX, EM } },
2214 { PREFIX_TABLE (PREFIX_0FF0) },
2215 { "psllw", { MX, EM } },
2216 { "pslld", { MX, EM } },
2217 { "psllq", { MX, EM } },
2218 { "pmuludq", { MX, EM } },
2219 { "pmaddwd", { MX, EM } },
2220 { "psadbw", { MX, EM } },
2221 { PREFIX_TABLE (PREFIX_0FF7) },
2223 { "psubb", { MX, EM } },
2224 { "psubw", { MX, EM } },
2225 { "psubd", { MX, EM } },
2226 { "psubq", { MX, EM } },
2227 { "paddb", { MX, EM } },
2228 { "paddw", { MX, EM } },
2229 { "paddd", { MX, EM } },
2233 static const unsigned char onebyte_has_modrm[256] = {
2234 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2235 /* ------------------------------- */
2236 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2237 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2238 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2239 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2240 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2241 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2242 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2243 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2244 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2245 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2246 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2247 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2248 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2249 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2250 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2251 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2252 /* ------------------------------- */
2253 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2256 static const unsigned char twobyte_has_modrm[256] = {
2257 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2258 /* ------------------------------- */
2259 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2260 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2261 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2262 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2263 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2264 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2265 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2266 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2267 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2268 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2269 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2270 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2271 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2272 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2273 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2274 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
2275 /* ------------------------------- */
2276 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2279 static char obuf[100];
2281 static char *mnemonicendp;
2282 static char scratchbuf[100];
2283 static unsigned char *start_codep;
2284 static unsigned char *insn_codep;
2285 static unsigned char *codep;
2286 static int last_lock_prefix;
2287 static int last_repz_prefix;
2288 static int last_repnz_prefix;
2289 static int last_data_prefix;
2290 static int last_addr_prefix;
2291 static int last_rex_prefix;
2292 static int last_seg_prefix;
2293 #define MAX_CODE_LENGTH 15
2294 /* We can up to 14 prefixes since the maximum instruction length is
2296 static int all_prefixes[MAX_CODE_LENGTH - 1];
2297 static disassemble_info *the_info;
2305 static unsigned char need_modrm;
2308 int register_specifier;
2314 static unsigned char need_vex;
2315 static unsigned char need_vex_reg;
2316 static unsigned char vex_w_done;
2324 /* If we are accessing mod/rm/reg without need_modrm set, then the
2325 values are stale. Hitting this abort likely indicates that you
2326 need to update onebyte_has_modrm or twobyte_has_modrm. */
2327 #define MODRM_CHECK if (!need_modrm) abort ()
2329 static const char **names64;
2330 static const char **names32;
2331 static const char **names16;
2332 static const char **names8;
2333 static const char **names8rex;
2334 static const char **names_seg;
2335 static const char *index64;
2336 static const char *index32;
2337 static const char **index16;
2339 static const char *intel_names64[] = {
2340 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2341 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2343 static const char *intel_names32[] = {
2344 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2345 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2347 static const char *intel_names16[] = {
2348 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2349 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2351 static const char *intel_names8[] = {
2352 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2354 static const char *intel_names8rex[] = {
2355 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2356 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2358 static const char *intel_names_seg[] = {
2359 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2361 static const char *intel_index64 = "riz";
2362 static const char *intel_index32 = "eiz";
2363 static const char *intel_index16[] = {
2364 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2367 static const char *att_names64[] = {
2368 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2369 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2371 static const char *att_names32[] = {
2372 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2373 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2375 static const char *att_names16[] = {
2376 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2377 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2379 static const char *att_names8[] = {
2380 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2382 static const char *att_names8rex[] = {
2383 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2384 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2386 static const char *att_names_seg[] = {
2387 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2389 static const char *att_index64 = "%riz";
2390 static const char *att_index32 = "%eiz";
2391 static const char *att_index16[] = {
2392 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2395 static const char **names_mm;
2396 static const char *intel_names_mm[] = {
2397 "mm0", "mm1", "mm2", "mm3",
2398 "mm4", "mm5", "mm6", "mm7"
2400 static const char *att_names_mm[] = {
2401 "%mm0", "%mm1", "%mm2", "%mm3",
2402 "%mm4", "%mm5", "%mm6", "%mm7"
2405 static const char **names_xmm;
2406 static const char *intel_names_xmm[] = {
2407 "xmm0", "xmm1", "xmm2", "xmm3",
2408 "xmm4", "xmm5", "xmm6", "xmm7",
2409 "xmm8", "xmm9", "xmm10", "xmm11",
2410 "xmm12", "xmm13", "xmm14", "xmm15"
2412 static const char *att_names_xmm[] = {
2413 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2414 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2415 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2416 "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2419 static const char **names_ymm;
2420 static const char *intel_names_ymm[] = {
2421 "ymm0", "ymm1", "ymm2", "ymm3",
2422 "ymm4", "ymm5", "ymm6", "ymm7",
2423 "ymm8", "ymm9", "ymm10", "ymm11",
2424 "ymm12", "ymm13", "ymm14", "ymm15"
2426 static const char *att_names_ymm[] = {
2427 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2428 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2429 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2430 "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2433 static const struct dis386 reg_table[][8] = {
2436 { "addA", { Eb, Ib } },
2437 { "orA", { Eb, Ib } },
2438 { "adcA", { Eb, Ib } },
2439 { "sbbA", { Eb, Ib } },
2440 { "andA", { Eb, Ib } },
2441 { "subA", { Eb, Ib } },
2442 { "xorA", { Eb, Ib } },
2443 { "cmpA", { Eb, Ib } },
2447 { "addQ", { Ev, Iv } },
2448 { "orQ", { Ev, Iv } },
2449 { "adcQ", { Ev, Iv } },
2450 { "sbbQ", { Ev, Iv } },
2451 { "andQ", { Ev, Iv } },
2452 { "subQ", { Ev, Iv } },
2453 { "xorQ", { Ev, Iv } },
2454 { "cmpQ", { Ev, Iv } },
2458 { "addQ", { Ev, sIb } },
2459 { "orQ", { Ev, sIb } },
2460 { "adcQ", { Ev, sIb } },
2461 { "sbbQ", { Ev, sIb } },
2462 { "andQ", { Ev, sIb } },
2463 { "subQ", { Ev, sIb } },
2464 { "xorQ", { Ev, sIb } },
2465 { "cmpQ", { Ev, sIb } },
2469 { "popU", { stackEv } },
2470 { XOP_8F_TABLE (XOP_09) },
2474 { XOP_8F_TABLE (XOP_09) },
2478 { "rolA", { Eb, Ib } },
2479 { "rorA", { Eb, Ib } },
2480 { "rclA", { Eb, Ib } },
2481 { "rcrA", { Eb, Ib } },
2482 { "shlA", { Eb, Ib } },
2483 { "shrA", { Eb, Ib } },
2485 { "sarA", { Eb, Ib } },
2489 { "rolQ", { Ev, Ib } },
2490 { "rorQ", { Ev, Ib } },
2491 { "rclQ", { Ev, Ib } },
2492 { "rcrQ", { Ev, Ib } },
2493 { "shlQ", { Ev, Ib } },
2494 { "shrQ", { Ev, Ib } },
2496 { "sarQ", { Ev, Ib } },
2500 { "movA", { Eb, Ib } },
2504 { "movQ", { Ev, Iv } },
2508 { "rolA", { Eb, I1 } },
2509 { "rorA", { Eb, I1 } },
2510 { "rclA", { Eb, I1 } },
2511 { "rcrA", { Eb, I1 } },
2512 { "shlA", { Eb, I1 } },
2513 { "shrA", { Eb, I1 } },
2515 { "sarA", { Eb, I1 } },
2519 { "rolQ", { Ev, I1 } },
2520 { "rorQ", { Ev, I1 } },
2521 { "rclQ", { Ev, I1 } },
2522 { "rcrQ", { Ev, I1 } },
2523 { "shlQ", { Ev, I1 } },
2524 { "shrQ", { Ev, I1 } },
2526 { "sarQ", { Ev, I1 } },
2530 { "rolA", { Eb, CL } },
2531 { "rorA", { Eb, CL } },
2532 { "rclA", { Eb, CL } },
2533 { "rcrA", { Eb, CL } },
2534 { "shlA", { Eb, CL } },
2535 { "shrA", { Eb, CL } },
2537 { "sarA", { Eb, CL } },
2541 { "rolQ", { Ev, CL } },
2542 { "rorQ", { Ev, CL } },
2543 { "rclQ", { Ev, CL } },
2544 { "rcrQ", { Ev, CL } },
2545 { "shlQ", { Ev, CL } },
2546 { "shrQ", { Ev, CL } },
2548 { "sarQ", { Ev, CL } },
2552 { "testA", { Eb, Ib } },
2556 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
2557 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
2558 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
2559 { "idivA", { Eb } }, /* and idiv for consistency. */
2563 { "testQ", { Ev, Iv } },
2567 { "mulQ", { Ev } }, /* Don't print the implicit register. */
2568 { "imulQ", { Ev } },
2570 { "idivQ", { Ev } },
2581 { "callT", { indirEv } },
2582 { "JcallT", { indirEp } },
2583 { "jmpT", { indirEv } },
2584 { "JjmpT", { indirEp } },
2585 { "pushU", { stackEv } },
2590 { "sldtD", { Sv } },
2601 { MOD_TABLE (MOD_0F01_REG_0) },
2602 { MOD_TABLE (MOD_0F01_REG_1) },
2603 { MOD_TABLE (MOD_0F01_REG_2) },
2604 { MOD_TABLE (MOD_0F01_REG_3) },
2605 { "smswD", { Sv } },
2608 { MOD_TABLE (MOD_0F01_REG_7) },
2612 { "prefetch", { Eb } },
2613 { "prefetchw", { Eb } },
2617 { MOD_TABLE (MOD_0F18_REG_0) },
2618 { MOD_TABLE (MOD_0F18_REG_1) },
2619 { MOD_TABLE (MOD_0F18_REG_2) },
2620 { MOD_TABLE (MOD_0F18_REG_3) },
2626 { MOD_TABLE (MOD_0F71_REG_2) },
2628 { MOD_TABLE (MOD_0F71_REG_4) },
2630 { MOD_TABLE (MOD_0F71_REG_6) },
2636 { MOD_TABLE (MOD_0F72_REG_2) },
2638 { MOD_TABLE (MOD_0F72_REG_4) },
2640 { MOD_TABLE (MOD_0F72_REG_6) },
2646 { MOD_TABLE (MOD_0F73_REG_2) },
2647 { MOD_TABLE (MOD_0F73_REG_3) },
2650 { MOD_TABLE (MOD_0F73_REG_6) },
2651 { MOD_TABLE (MOD_0F73_REG_7) },
2655 { "montmul", { { OP_0f07, 0 } } },
2656 { "xsha1", { { OP_0f07, 0 } } },
2657 { "xsha256", { { OP_0f07, 0 } } },
2661 { "xstore-rng", { { OP_0f07, 0 } } },
2662 { "xcrypt-ecb", { { OP_0f07, 0 } } },
2663 { "xcrypt-cbc", { { OP_0f07, 0 } } },
2664 { "xcrypt-ctr", { { OP_0f07, 0 } } },
2665 { "xcrypt-cfb", { { OP_0f07, 0 } } },
2666 { "xcrypt-ofb", { { OP_0f07, 0 } } },
2670 { MOD_TABLE (MOD_0FAE_REG_0) },
2671 { MOD_TABLE (MOD_0FAE_REG_1) },
2672 { MOD_TABLE (MOD_0FAE_REG_2) },
2673 { MOD_TABLE (MOD_0FAE_REG_3) },
2674 { MOD_TABLE (MOD_0FAE_REG_4) },
2675 { MOD_TABLE (MOD_0FAE_REG_5) },
2676 { MOD_TABLE (MOD_0FAE_REG_6) },
2677 { MOD_TABLE (MOD_0FAE_REG_7) },
2685 { "btQ", { Ev, Ib } },
2686 { "btsQ", { Ev, Ib } },
2687 { "btrQ", { Ev, Ib } },
2688 { "btcQ", { Ev, Ib } },
2693 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2698 { MOD_TABLE (MOD_0FC7_REG_6) },
2699 { MOD_TABLE (MOD_0FC7_REG_7) },
2705 { MOD_TABLE (MOD_VEX_71_REG_2) },
2707 { MOD_TABLE (MOD_VEX_71_REG_4) },
2709 { MOD_TABLE (MOD_VEX_71_REG_6) },
2715 { MOD_TABLE (MOD_VEX_72_REG_2) },
2717 { MOD_TABLE (MOD_VEX_72_REG_4) },
2719 { MOD_TABLE (MOD_VEX_72_REG_6) },
2725 { MOD_TABLE (MOD_VEX_73_REG_2) },
2726 { MOD_TABLE (MOD_VEX_73_REG_3) },
2729 { MOD_TABLE (MOD_VEX_73_REG_6) },
2730 { MOD_TABLE (MOD_VEX_73_REG_7) },
2736 { MOD_TABLE (MOD_VEX_AE_REG_2) },
2737 { MOD_TABLE (MOD_VEX_AE_REG_3) },
2741 { "llwpcb", { { OP_LWPCB_E, 0 } } },
2742 { "slwpcb", { { OP_LWPCB_E, 0 } } },
2746 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
2747 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
2751 static const struct dis386 prefix_table[][4] = {
2754 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2755 { "pause", { XX } },
2756 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2761 { "movups", { XM, EXx } },
2762 { "movss", { XM, EXd } },
2763 { "movupd", { XM, EXx } },
2764 { "movsd", { XM, EXq } },
2769 { "movups", { EXxS, XM } },
2770 { "movss", { EXdS, XM } },
2771 { "movupd", { EXxS, XM } },
2772 { "movsd", { EXqS, XM } },
2777 { MOD_TABLE (MOD_0F12_PREFIX_0) },
2778 { "movsldup", { XM, EXx } },
2779 { "movlpd", { XM, EXq } },
2780 { "movddup", { XM, EXq } },
2785 { MOD_TABLE (MOD_0F16_PREFIX_0) },
2786 { "movshdup", { XM, EXx } },
2787 { "movhpd", { XM, EXq } },
2792 { "cvtpi2ps", { XM, EMCq } },
2793 { "cvtsi2ss%LQ", { XM, Ev } },
2794 { "cvtpi2pd", { XM, EMCq } },
2795 { "cvtsi2sd%LQ", { XM, Ev } },
2800 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2801 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2802 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2803 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2808 { "cvttps2pi", { MXC, EXq } },
2809 { "cvttss2siY", { Gv, EXd } },
2810 { "cvttpd2pi", { MXC, EXx } },
2811 { "cvttsd2siY", { Gv, EXq } },
2816 { "cvtps2pi", { MXC, EXq } },
2817 { "cvtss2siY", { Gv, EXd } },
2818 { "cvtpd2pi", { MXC, EXx } },
2819 { "cvtsd2siY", { Gv, EXq } },
2824 { "ucomiss",{ XM, EXd } },
2826 { "ucomisd",{ XM, EXq } },
2831 { "comiss", { XM, EXd } },
2833 { "comisd", { XM, EXq } },
2838 { "sqrtps", { XM, EXx } },
2839 { "sqrtss", { XM, EXd } },
2840 { "sqrtpd", { XM, EXx } },
2841 { "sqrtsd", { XM, EXq } },
2846 { "rsqrtps",{ XM, EXx } },
2847 { "rsqrtss",{ XM, EXd } },
2852 { "rcpps", { XM, EXx } },
2853 { "rcpss", { XM, EXd } },
2858 { "addps", { XM, EXx } },
2859 { "addss", { XM, EXd } },
2860 { "addpd", { XM, EXx } },
2861 { "addsd", { XM, EXq } },
2866 { "mulps", { XM, EXx } },
2867 { "mulss", { XM, EXd } },
2868 { "mulpd", { XM, EXx } },
2869 { "mulsd", { XM, EXq } },
2874 { "cvtps2pd", { XM, EXq } },
2875 { "cvtss2sd", { XM, EXd } },
2876 { "cvtpd2ps", { XM, EXx } },
2877 { "cvtsd2ss", { XM, EXq } },
2882 { "cvtdq2ps", { XM, EXx } },
2883 { "cvttps2dq", { XM, EXx } },
2884 { "cvtps2dq", { XM, EXx } },
2889 { "subps", { XM, EXx } },
2890 { "subss", { XM, EXd } },
2891 { "subpd", { XM, EXx } },
2892 { "subsd", { XM, EXq } },
2897 { "minps", { XM, EXx } },
2898 { "minss", { XM, EXd } },
2899 { "minpd", { XM, EXx } },
2900 { "minsd", { XM, EXq } },
2905 { "divps", { XM, EXx } },
2906 { "divss", { XM, EXd } },
2907 { "divpd", { XM, EXx } },
2908 { "divsd", { XM, EXq } },
2913 { "maxps", { XM, EXx } },
2914 { "maxss", { XM, EXd } },
2915 { "maxpd", { XM, EXx } },
2916 { "maxsd", { XM, EXq } },
2921 { "punpcklbw",{ MX, EMd } },
2923 { "punpcklbw",{ MX, EMx } },
2928 { "punpcklwd",{ MX, EMd } },
2930 { "punpcklwd",{ MX, EMx } },
2935 { "punpckldq",{ MX, EMd } },
2937 { "punpckldq",{ MX, EMx } },
2944 { "punpcklqdq", { XM, EXx } },
2951 { "punpckhqdq", { XM, EXx } },
2956 { "movq", { MX, EM } },
2957 { "movdqu", { XM, EXx } },
2958 { "movdqa", { XM, EXx } },
2963 { "pshufw", { MX, EM, Ib } },
2964 { "pshufhw",{ XM, EXx, Ib } },
2965 { "pshufd", { XM, EXx, Ib } },
2966 { "pshuflw",{ XM, EXx, Ib } },
2969 /* PREFIX_0F73_REG_3 */
2973 { "psrldq", { XS, Ib } },
2976 /* PREFIX_0F73_REG_7 */
2980 { "pslldq", { XS, Ib } },
2985 {"vmread", { Em, Gm } },
2987 {"extrq", { XS, Ib, Ib } },
2988 {"insertq", { XM, XS, Ib, Ib } },
2993 {"vmwrite", { Gm, Em } },
2995 {"extrq", { XM, XS } },
2996 {"insertq", { XM, XS } },
3003 { "haddpd", { XM, EXx } },
3004 { "haddps", { XM, EXx } },
3011 { "hsubpd", { XM, EXx } },
3012 { "hsubps", { XM, EXx } },
3017 { "movK", { Edq, MX } },
3018 { "movq", { XM, EXq } },
3019 { "movK", { Edq, XM } },
3024 { "movq", { EMS, MX } },
3025 { "movdqu", { EXxS, XM } },
3026 { "movdqa", { EXxS, XM } },
3032 { "popcntS", { Gv, Ev } },
3037 { "bsrS", { Gv, Ev } },
3038 { "lzcntS", { Gv, Ev } },
3039 { "bsrS", { Gv, Ev } },
3044 { "cmpps", { XM, EXx, CMP } },
3045 { "cmpss", { XM, EXd, CMP } },
3046 { "cmppd", { XM, EXx, CMP } },
3047 { "cmpsd", { XM, EXq, CMP } },
3052 { "movntiS", { Ma, Gv } },
3055 /* PREFIX_0FC7_REG_6 */
3057 { "vmptrld",{ Mq } },
3058 { "vmxon", { Mq } },
3059 { "vmclear",{ Mq } },
3066 { "addsubpd", { XM, EXx } },
3067 { "addsubps", { XM, EXx } },
3073 { "movq2dq",{ XM, MS } },
3074 { "movq", { EXqS, XM } },
3075 { "movdq2q",{ MX, XS } },
3081 { "cvtdq2pd", { XM, EXq } },
3082 { "cvttpd2dq", { XM, EXx } },
3083 { "cvtpd2dq", { XM, EXx } },
3088 { "movntq", { Mq, MX } },
3090 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3098 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3103 { "maskmovq", { MX, MS } },
3105 { "maskmovdqu", { XM, XS } },
3112 { "pblendvb", { XM, EXx, XMM0 } },
3119 { "blendvps", { XM, EXx, XMM0 } },
3126 { "blendvpd", { XM, EXx, XMM0 } },
3133 { "ptest", { XM, EXx } },
3140 { "pmovsxbw", { XM, EXq } },
3147 { "pmovsxbd", { XM, EXd } },
3154 { "pmovsxbq", { XM, EXw } },
3161 { "pmovsxwd", { XM, EXq } },
3168 { "pmovsxwq", { XM, EXd } },
3175 { "pmovsxdq", { XM, EXq } },
3182 { "pmuldq", { XM, EXx } },
3189 { "pcmpeqq", { XM, EXx } },
3196 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3203 { "packusdw", { XM, EXx } },
3210 { "pmovzxbw", { XM, EXq } },
3217 { "pmovzxbd", { XM, EXd } },
3224 { "pmovzxbq", { XM, EXw } },
3231 { "pmovzxwd", { XM, EXq } },
3238 { "pmovzxwq", { XM, EXd } },
3245 { "pmovzxdq", { XM, EXq } },
3252 { "pcmpgtq", { XM, EXx } },
3259 { "pminsb", { XM, EXx } },
3266 { "pminsd", { XM, EXx } },
3273 { "pminuw", { XM, EXx } },
3280 { "pminud", { XM, EXx } },
3287 { "pmaxsb", { XM, EXx } },
3294 { "pmaxsd", { XM, EXx } },
3301 { "pmaxuw", { XM, EXx } },
3308 { "pmaxud", { XM, EXx } },
3315 { "pmulld", { XM, EXx } },
3322 { "phminposuw", { XM, EXx } },
3329 { "invept", { Gm, Mo } },
3336 { "invvpid", { Gm, Mo } },
3343 { "aesimc", { XM, EXx } },
3350 { "aesenc", { XM, EXx } },
3357 { "aesenclast", { XM, EXx } },
3364 { "aesdec", { XM, EXx } },
3371 { "aesdeclast", { XM, EXx } },
3376 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3378 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3379 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
3384 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3386 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3387 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
3394 { "roundps", { XM, EXx, Ib } },
3401 { "roundpd", { XM, EXx, Ib } },
3408 { "roundss", { XM, EXd, Ib } },
3415 { "roundsd", { XM, EXq, Ib } },
3422 { "blendps", { XM, EXx, Ib } },
3429 { "blendpd", { XM, EXx, Ib } },
3436 { "pblendw", { XM, EXx, Ib } },
3443 { "pextrb", { Edqb, XM, Ib } },
3450 { "pextrw", { Edqw, XM, Ib } },
3457 { "pextrK", { Edq, XM, Ib } },
3464 { "extractps", { Edqd, XM, Ib } },
3471 { "pinsrb", { XM, Edqb, Ib } },
3478 { "insertps", { XM, EXd, Ib } },
3485 { "pinsrK", { XM, Edq, Ib } },
3492 { "dpps", { XM, EXx, Ib } },
3499 { "dppd", { XM, EXx, Ib } },
3506 { "mpsadbw", { XM, EXx, Ib } },
3513 { "pclmulqdq", { XM, EXx, PCLMUL } },
3520 { "pcmpestrm", { XM, EXx, Ib } },
3527 { "pcmpestri", { XM, EXx, Ib } },
3534 { "pcmpistrm", { XM, EXx, Ib } },
3541 { "pcmpistri", { XM, EXx, Ib } },
3548 { "aeskeygenassist", { XM, EXx, Ib } },
3553 { VEX_W_TABLE (VEX_W_10_P_0) },
3554 { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3555 { VEX_W_TABLE (VEX_W_10_P_2) },
3556 { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3561 { VEX_W_TABLE (VEX_W_11_P_0) },
3562 { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3563 { VEX_W_TABLE (VEX_W_11_P_2) },
3564 { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3569 { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3570 { VEX_W_TABLE (VEX_W_12_P_1) },
3571 { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3572 { VEX_W_TABLE (VEX_W_12_P_3) },
3577 { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3578 { VEX_W_TABLE (VEX_W_16_P_1) },
3579 { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3585 { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3587 { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3593 { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3595 { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3601 { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3603 { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3608 { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3610 { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3615 { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3617 { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3622 { VEX_W_TABLE (VEX_W_51_P_0) },
3623 { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3624 { VEX_W_TABLE (VEX_W_51_P_2) },
3625 { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3630 { VEX_W_TABLE (VEX_W_52_P_0) },
3631 { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3636 { VEX_W_TABLE (VEX_W_53_P_0) },
3637 { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3642 { VEX_W_TABLE (VEX_W_58_P_0) },
3643 { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3644 { VEX_W_TABLE (VEX_W_58_P_2) },
3645 { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3650 { VEX_W_TABLE (VEX_W_59_P_0) },
3651 { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3652 { VEX_W_TABLE (VEX_W_59_P_2) },
3653 { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3658 { VEX_W_TABLE (VEX_W_5A_P_0) },
3659 { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3660 { "vcvtpd2ps%XY", { XMM, EXx } },
3661 { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3666 { VEX_W_TABLE (VEX_W_5B_P_0) },
3667 { VEX_W_TABLE (VEX_W_5B_P_1) },
3668 { VEX_W_TABLE (VEX_W_5B_P_2) },
3673 { VEX_W_TABLE (VEX_W_5C_P_0) },
3674 { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3675 { VEX_W_TABLE (VEX_W_5C_P_2) },
3676 { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3681 { VEX_W_TABLE (VEX_W_5D_P_0) },
3682 { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3683 { VEX_W_TABLE (VEX_W_5D_P_2) },
3684 { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3689 { VEX_W_TABLE (VEX_W_5E_P_0) },
3690 { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3691 { VEX_W_TABLE (VEX_W_5E_P_2) },
3692 { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3697 { VEX_W_TABLE (VEX_W_5F_P_0) },
3698 { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3699 { VEX_W_TABLE (VEX_W_5F_P_2) },
3700 { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3707 { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3714 { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3721 { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3728 { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3735 { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3742 { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3749 { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3756 { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3763 { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3770 { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3777 { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3784 { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3791 { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3798 { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3805 { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3811 { VEX_W_TABLE (VEX_W_6F_P_1) },
3812 { VEX_W_TABLE (VEX_W_6F_P_2) },
3818 { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3819 { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3820 { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3823 /* PREFIX_VEX_71_REG_2 */
3827 { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3830 /* PREFIX_VEX_71_REG_4 */
3834 { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3837 /* PREFIX_VEX_71_REG_6 */
3841 { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3844 /* PREFIX_VEX_72_REG_2 */
3848 { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3851 /* PREFIX_VEX_72_REG_4 */
3855 { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3858 /* PREFIX_VEX_72_REG_6 */
3862 { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3865 /* PREFIX_VEX_73_REG_2 */
3869 { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3872 /* PREFIX_VEX_73_REG_3 */
3876 { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3879 /* PREFIX_VEX_73_REG_6 */
3883 { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3886 /* PREFIX_VEX_73_REG_7 */
3890 { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3897 { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3904 { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3911 { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3916 { VEX_W_TABLE (VEX_W_77_P_0) },
3923 { VEX_W_TABLE (VEX_W_7C_P_2) },
3924 { VEX_W_TABLE (VEX_W_7C_P_3) },
3931 { VEX_W_TABLE (VEX_W_7D_P_2) },
3932 { VEX_W_TABLE (VEX_W_7D_P_3) },
3938 { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3939 { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3945 { VEX_W_TABLE (VEX_W_7F_P_1) },
3946 { VEX_W_TABLE (VEX_W_7F_P_2) },
3951 { VEX_W_TABLE (VEX_W_C2_P_0) },
3952 { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3953 { VEX_W_TABLE (VEX_W_C2_P_2) },
3954 { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3961 { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3968 { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3975 { VEX_W_TABLE (VEX_W_D0_P_2) },
3976 { VEX_W_TABLE (VEX_W_D0_P_3) },
3983 { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3990 { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3997 { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
4004 { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
4011 { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
4018 { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
4025 { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
4032 { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
4039 { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
4046 { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
4053 { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
4060 { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
4067 { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
4074 { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
4081 { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
4088 { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
4095 { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
4102 { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
4109 { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
4116 { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
4123 { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
4129 { VEX_W_TABLE (VEX_W_E6_P_1) },
4130 { VEX_W_TABLE (VEX_W_E6_P_2) },
4131 { VEX_W_TABLE (VEX_W_E6_P_3) },
4138 { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
4145 { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
4152 { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
4159 { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
4166 { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
4173 { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
4180 { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
4187 { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4194 { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4202 { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4209 { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4216 { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4223 { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4230 { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4237 { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4244 { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4251 { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4258 { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4265 { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4272 { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4279 { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4286 { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4293 { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4300 { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4303 /* PREFIX_VEX_3800 */
4307 { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4310 /* PREFIX_VEX_3801 */
4314 { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4317 /* PREFIX_VEX_3802 */
4321 { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4324 /* PREFIX_VEX_3803 */
4328 { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4331 /* PREFIX_VEX_3804 */
4335 { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4338 /* PREFIX_VEX_3805 */
4342 { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4345 /* PREFIX_VEX_3806 */
4349 { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4352 /* PREFIX_VEX_3807 */
4356 { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4359 /* PREFIX_VEX_3808 */
4363 { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4366 /* PREFIX_VEX_3809 */
4370 { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4373 /* PREFIX_VEX_380A */
4377 { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4380 /* PREFIX_VEX_380B */
4384 { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4387 /* PREFIX_VEX_380C */
4391 { VEX_W_TABLE (VEX_W_380C_P_2) },
4394 /* PREFIX_VEX_380D */
4398 { VEX_W_TABLE (VEX_W_380D_P_2) },
4401 /* PREFIX_VEX_380E */
4405 { VEX_W_TABLE (VEX_W_380E_P_2) },
4408 /* PREFIX_VEX_380F */
4412 { VEX_W_TABLE (VEX_W_380F_P_2) },
4415 /* PREFIX_VEX_3817 */
4419 { VEX_W_TABLE (VEX_W_3817_P_2) },
4422 /* PREFIX_VEX_3818 */
4426 { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4429 /* PREFIX_VEX_3819 */
4433 { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4436 /* PREFIX_VEX_381A */
4440 { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4443 /* PREFIX_VEX_381C */
4447 { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4450 /* PREFIX_VEX_381D */
4454 { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4457 /* PREFIX_VEX_381E */
4461 { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4464 /* PREFIX_VEX_3820 */
4468 { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4471 /* PREFIX_VEX_3821 */
4475 { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4478 /* PREFIX_VEX_3822 */
4482 { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4485 /* PREFIX_VEX_3823 */
4489 { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4492 /* PREFIX_VEX_3824 */
4496 { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4499 /* PREFIX_VEX_3825 */
4503 { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4506 /* PREFIX_VEX_3828 */
4510 { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4513 /* PREFIX_VEX_3829 */
4517 { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4520 /* PREFIX_VEX_382A */
4524 { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4527 /* PREFIX_VEX_382B */
4531 { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4534 /* PREFIX_VEX_382C */
4538 { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4541 /* PREFIX_VEX_382D */
4545 { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4548 /* PREFIX_VEX_382E */
4552 { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4555 /* PREFIX_VEX_382F */
4559 { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4562 /* PREFIX_VEX_3830 */
4566 { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4569 /* PREFIX_VEX_3831 */
4573 { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4576 /* PREFIX_VEX_3832 */
4580 { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4583 /* PREFIX_VEX_3833 */
4587 { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4590 /* PREFIX_VEX_3834 */
4594 { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4597 /* PREFIX_VEX_3835 */
4601 { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4604 /* PREFIX_VEX_3837 */
4608 { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4611 /* PREFIX_VEX_3838 */
4615 { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4618 /* PREFIX_VEX_3839 */
4622 { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4625 /* PREFIX_VEX_383A */
4629 { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4632 /* PREFIX_VEX_383B */
4636 { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4639 /* PREFIX_VEX_383C */
4643 { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4646 /* PREFIX_VEX_383D */
4650 { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4653 /* PREFIX_VEX_383E */
4657 { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4660 /* PREFIX_VEX_383F */
4664 { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4667 /* PREFIX_VEX_3840 */
4671 { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4674 /* PREFIX_VEX_3841 */
4678 { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4681 /* PREFIX_VEX_3896 */
4685 { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4688 /* PREFIX_VEX_3897 */
4692 { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4695 /* PREFIX_VEX_3898 */
4699 { "vfmadd132p%XW", { XM, Vex, EXx } },
4702 /* PREFIX_VEX_3899 */
4706 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4709 /* PREFIX_VEX_389A */
4713 { "vfmsub132p%XW", { XM, Vex, EXx } },
4716 /* PREFIX_VEX_389B */
4720 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4723 /* PREFIX_VEX_389C */
4727 { "vfnmadd132p%XW", { XM, Vex, EXx } },
4730 /* PREFIX_VEX_389D */
4734 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4737 /* PREFIX_VEX_389E */
4741 { "vfnmsub132p%XW", { XM, Vex, EXx } },
4744 /* PREFIX_VEX_389F */
4748 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4751 /* PREFIX_VEX_38A6 */
4755 { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4759 /* PREFIX_VEX_38A7 */
4763 { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4766 /* PREFIX_VEX_38A8 */
4770 { "vfmadd213p%XW", { XM, Vex, EXx } },
4773 /* PREFIX_VEX_38A9 */
4777 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4780 /* PREFIX_VEX_38AA */
4784 { "vfmsub213p%XW", { XM, Vex, EXx } },
4787 /* PREFIX_VEX_38AB */
4791 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4794 /* PREFIX_VEX_38AC */
4798 { "vfnmadd213p%XW", { XM, Vex, EXx } },
4801 /* PREFIX_VEX_38AD */
4805 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4808 /* PREFIX_VEX_38AE */
4812 { "vfnmsub213p%XW", { XM, Vex, EXx } },
4815 /* PREFIX_VEX_38AF */
4819 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4822 /* PREFIX_VEX_38B6 */
4826 { "vfmaddsub231p%XW", { XM, Vex, EXx } },
4829 /* PREFIX_VEX_38B7 */
4833 { "vfmsubadd231p%XW", { XM, Vex, EXx } },
4836 /* PREFIX_VEX_38B8 */
4840 { "vfmadd231p%XW", { XM, Vex, EXx } },
4843 /* PREFIX_VEX_38B9 */
4847 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4850 /* PREFIX_VEX_38BA */
4854 { "vfmsub231p%XW", { XM, Vex, EXx } },
4857 /* PREFIX_VEX_38BB */
4861 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4864 /* PREFIX_VEX_38BC */
4868 { "vfnmadd231p%XW", { XM, Vex, EXx } },
4871 /* PREFIX_VEX_38BD */
4875 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4878 /* PREFIX_VEX_38BE */
4882 { "vfnmsub231p%XW", { XM, Vex, EXx } },
4885 /* PREFIX_VEX_38BF */
4889 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4892 /* PREFIX_VEX_38DB */
4896 { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
4899 /* PREFIX_VEX_38DC */
4903 { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
4906 /* PREFIX_VEX_38DD */
4910 { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
4913 /* PREFIX_VEX_38DE */
4917 { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
4920 /* PREFIX_VEX_38DF */
4924 { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
4927 /* PREFIX_VEX_3A04 */
4931 { VEX_W_TABLE (VEX_W_3A04_P_2) },
4934 /* PREFIX_VEX_3A05 */
4938 { VEX_W_TABLE (VEX_W_3A05_P_2) },
4941 /* PREFIX_VEX_3A06 */
4945 { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4948 /* PREFIX_VEX_3A08 */
4952 { VEX_W_TABLE (VEX_W_3A08_P_2) },
4955 /* PREFIX_VEX_3A09 */
4959 { VEX_W_TABLE (VEX_W_3A09_P_2) },
4962 /* PREFIX_VEX_3A0A */
4966 { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4969 /* PREFIX_VEX_3A0B */
4973 { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4976 /* PREFIX_VEX_3A0C */
4980 { VEX_W_TABLE (VEX_W_3A0C_P_2) },
4983 /* PREFIX_VEX_3A0D */
4987 { VEX_W_TABLE (VEX_W_3A0D_P_2) },
4990 /* PREFIX_VEX_3A0E */
4994 { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4997 /* PREFIX_VEX_3A0F */
5001 { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
5004 /* PREFIX_VEX_3A14 */
5008 { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
5011 /* PREFIX_VEX_3A15 */
5015 { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
5018 /* PREFIX_VEX_3A16 */
5022 { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
5025 /* PREFIX_VEX_3A17 */
5029 { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
5032 /* PREFIX_VEX_3A18 */
5036 { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
5039 /* PREFIX_VEX_3A19 */
5043 { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
5046 /* PREFIX_VEX_3A20 */
5050 { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
5053 /* PREFIX_VEX_3A21 */
5057 { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
5060 /* PREFIX_VEX_3A22 */
5064 { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5067 /* PREFIX_VEX_3A40 */
5071 { VEX_W_TABLE (VEX_W_3A40_P_2) },
5074 /* PREFIX_VEX_3A41 */
5078 { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
5081 /* PREFIX_VEX_3A42 */
5085 { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
5088 /* PREFIX_VEX_3A44 */
5092 { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },
5095 /* PREFIX_VEX_3A48 */
5099 { VEX_W_TABLE (VEX_W_3A48_P_2) },
5102 /* PREFIX_VEX_3A49 */
5106 { VEX_W_TABLE (VEX_W_3A49_P_2) },
5109 /* PREFIX_VEX_3A4A */
5113 { VEX_W_TABLE (VEX_W_3A4A_P_2) },
5116 /* PREFIX_VEX_3A4B */
5120 { VEX_W_TABLE (VEX_W_3A4B_P_2) },
5123 /* PREFIX_VEX_3A4C */
5127 { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
5130 /* PREFIX_VEX_3A5C */
5134 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5137 /* PREFIX_VEX_3A5D */
5141 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5144 /* PREFIX_VEX_3A5E */
5148 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5151 /* PREFIX_VEX_3A5F */
5155 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5158 /* PREFIX_VEX_3A60 */
5162 { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
5166 /* PREFIX_VEX_3A61 */
5170 { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
5173 /* PREFIX_VEX_3A62 */
5177 { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
5180 /* PREFIX_VEX_3A63 */
5184 { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
5187 /* PREFIX_VEX_3A68 */
5191 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5194 /* PREFIX_VEX_3A69 */
5198 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5201 /* PREFIX_VEX_3A6A */
5205 { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
5208 /* PREFIX_VEX_3A6B */
5212 { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
5215 /* PREFIX_VEX_3A6C */
5219 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5222 /* PREFIX_VEX_3A6D */
5226 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5229 /* PREFIX_VEX_3A6E */
5233 { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
5236 /* PREFIX_VEX_3A6F */
5240 { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
5243 /* PREFIX_VEX_3A78 */
5247 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5250 /* PREFIX_VEX_3A79 */
5254 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5257 /* PREFIX_VEX_3A7A */
5261 { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
5264 /* PREFIX_VEX_3A7B */
5268 { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
5271 /* PREFIX_VEX_3A7C */
5275 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5279 /* PREFIX_VEX_3A7D */
5283 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5286 /* PREFIX_VEX_3A7E */
5290 { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5293 /* PREFIX_VEX_3A7F */
5297 { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5300 /* PREFIX_VEX_3ADF */
5304 { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5308 static const struct dis386 x86_64_table[][2] = {
5311 { "push{T|}", { es } },
5316 { "pop{T|}", { es } },
5321 { "push{T|}", { cs } },
5326 { "push{T|}", { ss } },
5331 { "pop{T|}", { ss } },
5336 { "push{T|}", { ds } },
5341 { "pop{T|}", { ds } },
5366 { "pusha{P|}", { XX } },
5371 { "popa{P|}", { XX } },
5376 { MOD_TABLE (MOD_62_32BIT) },
5381 { "arpl", { Ew, Gw } },
5382 { "movs{lq|xd}", { Gv, Ed } },
5387 { "ins{R|}", { Yzr, indirDX } },
5388 { "ins{G|}", { Yzr, indirDX } },
5393 { "outs{R|}", { indirDXr, Xz } },
5394 { "outs{G|}", { indirDXr, Xz } },
5399 { "Jcall{T|}", { Ap } },
5404 { MOD_TABLE (MOD_C4_32BIT) },
5405 { VEX_C4_TABLE (VEX_0F) },
5410 { MOD_TABLE (MOD_C5_32BIT) },
5411 { VEX_C5_TABLE (VEX_0F) },
5431 { "Jjmp{T|}", { Ap } },
5434 /* X86_64_0F01_REG_0 */
5436 { "sgdt{Q|IQ}", { M } },
5440 /* X86_64_0F01_REG_1 */
5442 { "sidt{Q|IQ}", { M } },
5446 /* X86_64_0F01_REG_2 */
5448 { "lgdt{Q|Q}", { M } },
5452 /* X86_64_0F01_REG_3 */
5454 { "lidt{Q|Q}", { M } },
5459 static const struct dis386 three_byte_table[][256] = {
5461 /* THREE_BYTE_0F38 */
5464 { "pshufb", { MX, EM } },
5465 { "phaddw", { MX, EM } },
5466 { "phaddd", { MX, EM } },
5467 { "phaddsw", { MX, EM } },
5468 { "pmaddubsw", { MX, EM } },
5469 { "phsubw", { MX, EM } },
5470 { "phsubd", { MX, EM } },
5471 { "phsubsw", { MX, EM } },
5473 { "psignb", { MX, EM } },
5474 { "psignw", { MX, EM } },
5475 { "psignd", { MX, EM } },
5476 { "pmulhrsw", { MX, EM } },
5482 { PREFIX_TABLE (PREFIX_0F3810) },
5486 { PREFIX_TABLE (PREFIX_0F3814) },
5487 { PREFIX_TABLE (PREFIX_0F3815) },
5489 { PREFIX_TABLE (PREFIX_0F3817) },
5495 { "pabsb", { MX, EM } },
5496 { "pabsw", { MX, EM } },
5497 { "pabsd", { MX, EM } },
5500 { PREFIX_TABLE (PREFIX_0F3820) },
5501 { PREFIX_TABLE (PREFIX_0F3821) },
5502 { PREFIX_TABLE (PREFIX_0F3822) },
5503 { PREFIX_TABLE (PREFIX_0F3823) },
5504 { PREFIX_TABLE (PREFIX_0F3824) },
5505 { PREFIX_TABLE (PREFIX_0F3825) },
5509 { PREFIX_TABLE (PREFIX_0F3828) },
5510 { PREFIX_TABLE (PREFIX_0F3829) },
5511 { PREFIX_TABLE (PREFIX_0F382A) },
5512 { PREFIX_TABLE (PREFIX_0F382B) },
5518 { PREFIX_TABLE (PREFIX_0F3830) },
5519 { PREFIX_TABLE (PREFIX_0F3831) },
5520 { PREFIX_TABLE (PREFIX_0F3832) },
5521 { PREFIX_TABLE (PREFIX_0F3833) },
5522 { PREFIX_TABLE (PREFIX_0F3834) },
5523 { PREFIX_TABLE (PREFIX_0F3835) },
5525 { PREFIX_TABLE (PREFIX_0F3837) },
5527 { PREFIX_TABLE (PREFIX_0F3838) },
5528 { PREFIX_TABLE (PREFIX_0F3839) },
5529 { PREFIX_TABLE (PREFIX_0F383A) },
5530 { PREFIX_TABLE (PREFIX_0F383B) },
5531 { PREFIX_TABLE (PREFIX_0F383C) },
5532 { PREFIX_TABLE (PREFIX_0F383D) },
5533 { PREFIX_TABLE (PREFIX_0F383E) },
5534 { PREFIX_TABLE (PREFIX_0F383F) },
5536 { PREFIX_TABLE (PREFIX_0F3840) },
5537 { PREFIX_TABLE (PREFIX_0F3841) },
5608 { PREFIX_TABLE (PREFIX_0F3880) },
5609 { PREFIX_TABLE (PREFIX_0F3881) },
5710 { PREFIX_TABLE (PREFIX_0F38DB) },
5711 { PREFIX_TABLE (PREFIX_0F38DC) },
5712 { PREFIX_TABLE (PREFIX_0F38DD) },
5713 { PREFIX_TABLE (PREFIX_0F38DE) },
5714 { PREFIX_TABLE (PREFIX_0F38DF) },
5734 { PREFIX_TABLE (PREFIX_0F38F0) },
5735 { PREFIX_TABLE (PREFIX_0F38F1) },
5752 /* THREE_BYTE_0F3A */
5764 { PREFIX_TABLE (PREFIX_0F3A08) },
5765 { PREFIX_TABLE (PREFIX_0F3A09) },
5766 { PREFIX_TABLE (PREFIX_0F3A0A) },
5767 { PREFIX_TABLE (PREFIX_0F3A0B) },
5768 { PREFIX_TABLE (PREFIX_0F3A0C) },
5769 { PREFIX_TABLE (PREFIX_0F3A0D) },
5770 { PREFIX_TABLE (PREFIX_0F3A0E) },
5771 { "palignr", { MX, EM, Ib } },
5777 { PREFIX_TABLE (PREFIX_0F3A14) },
5778 { PREFIX_TABLE (PREFIX_0F3A15) },
5779 { PREFIX_TABLE (PREFIX_0F3A16) },
5780 { PREFIX_TABLE (PREFIX_0F3A17) },
5791 { PREFIX_TABLE (PREFIX_0F3A20) },
5792 { PREFIX_TABLE (PREFIX_0F3A21) },
5793 { PREFIX_TABLE (PREFIX_0F3A22) },
5827 { PREFIX_TABLE (PREFIX_0F3A40) },
5828 { PREFIX_TABLE (PREFIX_0F3A41) },
5829 { PREFIX_TABLE (PREFIX_0F3A42) },
5831 { PREFIX_TABLE (PREFIX_0F3A44) },
5863 { PREFIX_TABLE (PREFIX_0F3A60) },
5864 { PREFIX_TABLE (PREFIX_0F3A61) },
5865 { PREFIX_TABLE (PREFIX_0F3A62) },
5866 { PREFIX_TABLE (PREFIX_0F3A63) },
6005 { PREFIX_TABLE (PREFIX_0F3ADF) },
6044 /* THREE_BYTE_0F7A */
6083 { "ptest", { XX } },
6120 { "phaddbw", { XM, EXq } },
6121 { "phaddbd", { XM, EXq } },
6122 { "phaddbq", { XM, EXq } },
6125 { "phaddwd", { XM, EXq } },
6126 { "phaddwq", { XM, EXq } },
6131 { "phadddq", { XM, EXq } },
6138 { "phaddubw", { XM, EXq } },
6139 { "phaddubd", { XM, EXq } },
6140 { "phaddubq", { XM, EXq } },
6143 { "phadduwd", { XM, EXq } },
6144 { "phadduwq", { XM, EXq } },
6149 { "phaddudq", { XM, EXq } },
6156 { "phsubbw", { XM, EXq } },
6157 { "phsubbd", { XM, EXq } },
6158 { "phsubbq", { XM, EXq } },
6337 static const struct dis386 xop_table[][256] = {
6490 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6491 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6492 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6500 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6501 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6508 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6509 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6510 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6518 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6519 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6523 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6524 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6527 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6545 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6557 { "vprotb", { XM, Vex_2src_1, Ib } },
6558 { "vprotw", { XM, Vex_2src_1, Ib } },
6559 { "vprotd", { XM, Vex_2src_1, Ib } },
6560 { "vprotq", { XM, Vex_2src_1, Ib } },
6570 { "vpcomb", { XM, Vex128, EXx, Ib } },
6571 { "vpcomw", { XM, Vex128, EXx, Ib } },
6572 { "vpcomd", { XM, Vex128, EXx, Ib } },
6573 { "vpcomq", { XM, Vex128, EXx, Ib } },
6606 { "vpcomub", { XM, Vex128, EXx, Ib } },
6607 { "vpcomuw", { XM, Vex128, EXx, Ib } },
6608 { "vpcomud", { XM, Vex128, EXx, Ib } },
6609 { "vpcomuq", { XM, Vex128, EXx, Ib } },
6652 { REG_TABLE (REG_XOP_LWPCB) },
6776 { VEX_LEN_TABLE (VEX_LEN_XOP_09_80) },
6777 { VEX_LEN_TABLE (VEX_LEN_XOP_09_81) },
6778 { "vfrczss", { XM, EXd } },
6779 { "vfrczsd", { XM, EXq } },
6794 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } },
6795 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } },
6796 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } },
6797 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } },
6798 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } },
6799 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } },
6800 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } },
6801 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } },
6803 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } },
6804 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } },
6805 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } },
6806 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } },
6849 { "vphaddbw", { XM, EXxmm } },
6850 { "vphaddbd", { XM, EXxmm } },
6851 { "vphaddbq", { XM, EXxmm } },
6854 { "vphaddwd", { XM, EXxmm } },
6855 { "vphaddwq", { XM, EXxmm } },
6860 { "vphadddq", { XM, EXxmm } },
6867 { "vphaddubw", { XM, EXxmm } },
6868 { "vphaddubd", { XM, EXxmm } },
6869 { "vphaddubq", { XM, EXxmm } },
6872 { "vphadduwd", { XM, EXxmm } },
6873 { "vphadduwq", { XM, EXxmm } },
6878 { "vphaddudq", { XM, EXxmm } },
6885 { "vphsubbw", { XM, EXxmm } },
6886 { "vphsubwd", { XM, EXxmm } },
6887 { "vphsubdq", { XM, EXxmm } },
6943 { REG_TABLE (REG_XOP_LWP) },
7213 static const struct dis386 vex_table[][256] = {
7235 { PREFIX_TABLE (PREFIX_VEX_10) },
7236 { PREFIX_TABLE (PREFIX_VEX_11) },
7237 { PREFIX_TABLE (PREFIX_VEX_12) },
7238 { MOD_TABLE (MOD_VEX_13) },
7239 { VEX_W_TABLE (VEX_W_14) },
7240 { VEX_W_TABLE (VEX_W_15) },
7241 { PREFIX_TABLE (PREFIX_VEX_16) },
7242 { MOD_TABLE (MOD_VEX_17) },
7262 { VEX_W_TABLE (VEX_W_28) },
7263 { VEX_W_TABLE (VEX_W_29) },
7264 { PREFIX_TABLE (PREFIX_VEX_2A) },
7265 { MOD_TABLE (MOD_VEX_2B) },
7266 { PREFIX_TABLE (PREFIX_VEX_2C) },
7267 { PREFIX_TABLE (PREFIX_VEX_2D) },
7268 { PREFIX_TABLE (PREFIX_VEX_2E) },
7269 { PREFIX_TABLE (PREFIX_VEX_2F) },
7307 { MOD_TABLE (MOD_VEX_50) },
7308 { PREFIX_TABLE (PREFIX_VEX_51) },
7309 { PREFIX_TABLE (PREFIX_VEX_52) },
7310 { PREFIX_TABLE (PREFIX_VEX_53) },
7311 { "vandpX", { XM, Vex, EXx } },
7312 { "vandnpX", { XM, Vex, EXx } },
7313 { "vorpX", { XM, Vex, EXx } },
7314 { "vxorpX", { XM, Vex, EXx } },
7316 { PREFIX_TABLE (PREFIX_VEX_58) },
7317 { PREFIX_TABLE (PREFIX_VEX_59) },
7318 { PREFIX_TABLE (PREFIX_VEX_5A) },
7319 { PREFIX_TABLE (PREFIX_VEX_5B) },
7320 { PREFIX_TABLE (PREFIX_VEX_5C) },
7321 { PREFIX_TABLE (PREFIX_VEX_5D) },
7322 { PREFIX_TABLE (PREFIX_VEX_5E) },
7323 { PREFIX_TABLE (PREFIX_VEX_5F) },
7325 { PREFIX_TABLE (PREFIX_VEX_60) },
7326 { PREFIX_TABLE (PREFIX_VEX_61) },
7327 { PREFIX_TABLE (PREFIX_VEX_62) },
7328 { PREFIX_TABLE (PREFIX_VEX_63) },
7329 { PREFIX_TABLE (PREFIX_VEX_64) },
7330 { PREFIX_TABLE (PREFIX_VEX_65) },
7331 { PREFIX_TABLE (PREFIX_VEX_66) },
7332 { PREFIX_TABLE (PREFIX_VEX_67) },
7334 { PREFIX_TABLE (PREFIX_VEX_68) },
7335 { PREFIX_TABLE (PREFIX_VEX_69) },
7336 { PREFIX_TABLE (PREFIX_VEX_6A) },
7337 { PREFIX_TABLE (PREFIX_VEX_6B) },
7338 { PREFIX_TABLE (PREFIX_VEX_6C) },
7339 { PREFIX_TABLE (PREFIX_VEX_6D) },
7340 { PREFIX_TABLE (PREFIX_VEX_6E) },
7341 { PREFIX_TABLE (PREFIX_VEX_6F) },
7343 { PREFIX_TABLE (PREFIX_VEX_70) },
7344 { REG_TABLE (REG_VEX_71) },
7345 { REG_TABLE (REG_VEX_72) },
7346 { REG_TABLE (REG_VEX_73) },
7347 { PREFIX_TABLE (PREFIX_VEX_74) },
7348 { PREFIX_TABLE (PREFIX_VEX_75) },
7349 { PREFIX_TABLE (PREFIX_VEX_76) },
7350 { PREFIX_TABLE (PREFIX_VEX_77) },
7356 { PREFIX_TABLE (PREFIX_VEX_7C) },
7357 { PREFIX_TABLE (PREFIX_VEX_7D) },
7358 { PREFIX_TABLE (PREFIX_VEX_7E) },
7359 { PREFIX_TABLE (PREFIX_VEX_7F) },
7412 { REG_TABLE (REG_VEX_AE) },
7435 { PREFIX_TABLE (PREFIX_VEX_C2) },
7437 { PREFIX_TABLE (PREFIX_VEX_C4) },
7438 { PREFIX_TABLE (PREFIX_VEX_C5) },
7439 { "vshufpX", { XM, Vex, EXx, Ib } },
7451 { PREFIX_TABLE (PREFIX_VEX_D0) },
7452 { PREFIX_TABLE (PREFIX_VEX_D1) },
7453 { PREFIX_TABLE (PREFIX_VEX_D2) },
7454 { PREFIX_TABLE (PREFIX_VEX_D3) },
7455 { PREFIX_TABLE (PREFIX_VEX_D4) },
7456 { PREFIX_TABLE (PREFIX_VEX_D5) },
7457 { PREFIX_TABLE (PREFIX_VEX_D6) },
7458 { PREFIX_TABLE (PREFIX_VEX_D7) },
7460 { PREFIX_TABLE (PREFIX_VEX_D8) },
7461 { PREFIX_TABLE (PREFIX_VEX_D9) },
7462 { PREFIX_TABLE (PREFIX_VEX_DA) },
7463 { PREFIX_TABLE (PREFIX_VEX_DB) },
7464 { PREFIX_TABLE (PREFIX_VEX_DC) },
7465 { PREFIX_TABLE (PREFIX_VEX_DD) },
7466 { PREFIX_TABLE (PREFIX_VEX_DE) },
7467 { PREFIX_TABLE (PREFIX_VEX_DF) },
7469 { PREFIX_TABLE (PREFIX_VEX_E0) },
7470 { PREFIX_TABLE (PREFIX_VEX_E1) },
7471 { PREFIX_TABLE (PREFIX_VEX_E2) },
7472 { PREFIX_TABLE (PREFIX_VEX_E3) },
7473 { PREFIX_TABLE (PREFIX_VEX_E4) },
7474 { PREFIX_TABLE (PREFIX_VEX_E5) },
7475 { PREFIX_TABLE (PREFIX_VEX_E6) },
7476 { PREFIX_TABLE (PREFIX_VEX_E7) },
7478 { PREFIX_TABLE (PREFIX_VEX_E8) },
7479 { PREFIX_TABLE (PREFIX_VEX_E9) },
7480 { PREFIX_TABLE (PREFIX_VEX_EA) },
7481 { PREFIX_TABLE (PREFIX_VEX_EB) },
7482 { PREFIX_TABLE (PREFIX_VEX_EC) },
7483 { PREFIX_TABLE (PREFIX_VEX_ED) },
7484 { PREFIX_TABLE (PREFIX_VEX_EE) },
7485 { PREFIX_TABLE (PREFIX_VEX_EF) },
7487 { PREFIX_TABLE (PREFIX_VEX_F0) },
7488 { PREFIX_TABLE (PREFIX_VEX_F1) },
7489 { PREFIX_TABLE (PREFIX_VEX_F2) },
7490 { PREFIX_TABLE (PREFIX_VEX_F3) },
7491 { PREFIX_TABLE (PREFIX_VEX_F4) },
7492 { PREFIX_TABLE (PREFIX_VEX_F5) },
7493 { PREFIX_TABLE (PREFIX_VEX_F6) },
7494 { PREFIX_TABLE (PREFIX_VEX_F7) },
7496 { PREFIX_TABLE (PREFIX_VEX_F8) },
7497 { PREFIX_TABLE (PREFIX_VEX_F9) },
7498 { PREFIX_TABLE (PREFIX_VEX_FA) },
7499 { PREFIX_TABLE (PREFIX_VEX_FB) },
7500 { PREFIX_TABLE (PREFIX_VEX_FC) },
7501 { PREFIX_TABLE (PREFIX_VEX_FD) },
7502 { PREFIX_TABLE (PREFIX_VEX_FE) },
7508 { PREFIX_TABLE (PREFIX_VEX_3800) },
7509 { PREFIX_TABLE (PREFIX_VEX_3801) },
7510 { PREFIX_TABLE (PREFIX_VEX_3802) },
7511 { PREFIX_TABLE (PREFIX_VEX_3803) },
7512 { PREFIX_TABLE (PREFIX_VEX_3804) },
7513 { PREFIX_TABLE (PREFIX_VEX_3805) },
7514 { PREFIX_TABLE (PREFIX_VEX_3806) },
7515 { PREFIX_TABLE (PREFIX_VEX_3807) },
7517 { PREFIX_TABLE (PREFIX_VEX_3808) },
7518 { PREFIX_TABLE (PREFIX_VEX_3809) },
7519 { PREFIX_TABLE (PREFIX_VEX_380A) },
7520 { PREFIX_TABLE (PREFIX_VEX_380B) },
7521 { PREFIX_TABLE (PREFIX_VEX_380C) },
7522 { PREFIX_TABLE (PREFIX_VEX_380D) },
7523 { PREFIX_TABLE (PREFIX_VEX_380E) },
7524 { PREFIX_TABLE (PREFIX_VEX_380F) },
7533 { PREFIX_TABLE (PREFIX_VEX_3817) },
7535 { PREFIX_TABLE (PREFIX_VEX_3818) },
7536 { PREFIX_TABLE (PREFIX_VEX_3819) },
7537 { PREFIX_TABLE (PREFIX_VEX_381A) },
7539 { PREFIX_TABLE (PREFIX_VEX_381C) },
7540 { PREFIX_TABLE (PREFIX_VEX_381D) },
7541 { PREFIX_TABLE (PREFIX_VEX_381E) },
7544 { PREFIX_TABLE (PREFIX_VEX_3820) },
7545 { PREFIX_TABLE (PREFIX_VEX_3821) },
7546 { PREFIX_TABLE (PREFIX_VEX_3822) },
7547 { PREFIX_TABLE (PREFIX_VEX_3823) },
7548 { PREFIX_TABLE (PREFIX_VEX_3824) },
7549 { PREFIX_TABLE (PREFIX_VEX_3825) },
7553 { PREFIX_TABLE (PREFIX_VEX_3828) },
7554 { PREFIX_TABLE (PREFIX_VEX_3829) },
7555 { PREFIX_TABLE (PREFIX_VEX_382A) },
7556 { PREFIX_TABLE (PREFIX_VEX_382B) },
7557 { PREFIX_TABLE (PREFIX_VEX_382C) },
7558 { PREFIX_TABLE (PREFIX_VEX_382D) },
7559 { PREFIX_TABLE (PREFIX_VEX_382E) },
7560 { PREFIX_TABLE (PREFIX_VEX_382F) },
7562 { PREFIX_TABLE (PREFIX_VEX_3830) },
7563 { PREFIX_TABLE (PREFIX_VEX_3831) },
7564 { PREFIX_TABLE (PREFIX_VEX_3832) },
7565 { PREFIX_TABLE (PREFIX_VEX_3833) },
7566 { PREFIX_TABLE (PREFIX_VEX_3834) },
7567 { PREFIX_TABLE (PREFIX_VEX_3835) },
7569 { PREFIX_TABLE (PREFIX_VEX_3837) },
7571 { PREFIX_TABLE (PREFIX_VEX_3838) },
7572 { PREFIX_TABLE (PREFIX_VEX_3839) },
7573 { PREFIX_TABLE (PREFIX_VEX_383A) },
7574 { PREFIX_TABLE (PREFIX_VEX_383B) },
7575 { PREFIX_TABLE (PREFIX_VEX_383C) },
7576 { PREFIX_TABLE (PREFIX_VEX_383D) },
7577 { PREFIX_TABLE (PREFIX_VEX_383E) },
7578 { PREFIX_TABLE (PREFIX_VEX_383F) },
7580 { PREFIX_TABLE (PREFIX_VEX_3840) },
7581 { PREFIX_TABLE (PREFIX_VEX_3841) },
7676 { PREFIX_TABLE (PREFIX_VEX_3896) },
7677 { PREFIX_TABLE (PREFIX_VEX_3897) },
7679 { PREFIX_TABLE (PREFIX_VEX_3898) },
7680 { PREFIX_TABLE (PREFIX_VEX_3899) },
7681 { PREFIX_TABLE (PREFIX_VEX_389A) },
7682 { PREFIX_TABLE (PREFIX_VEX_389B) },
7683 { PREFIX_TABLE (PREFIX_VEX_389C) },
7684 { PREFIX_TABLE (PREFIX_VEX_389D) },
7685 { PREFIX_TABLE (PREFIX_VEX_389E) },
7686 { PREFIX_TABLE (PREFIX_VEX_389F) },
7694 { PREFIX_TABLE (PREFIX_VEX_38A6) },
7695 { PREFIX_TABLE (PREFIX_VEX_38A7) },
7697 { PREFIX_TABLE (PREFIX_VEX_38A8) },
7698 { PREFIX_TABLE (PREFIX_VEX_38A9) },
7699 { PREFIX_TABLE (PREFIX_VEX_38AA) },
7700 { PREFIX_TABLE (PREFIX_VEX_38AB) },
7701 { PREFIX_TABLE (PREFIX_VEX_38AC) },
7702 { PREFIX_TABLE (PREFIX_VEX_38AD) },
7703 { PREFIX_TABLE (PREFIX_VEX_38AE) },
7704 { PREFIX_TABLE (PREFIX_VEX_38AF) },
7712 { PREFIX_TABLE (PREFIX_VEX_38B6) },
7713 { PREFIX_TABLE (PREFIX_VEX_38B7) },
7715 { PREFIX_TABLE (PREFIX_VEX_38B8) },
7716 { PREFIX_TABLE (PREFIX_VEX_38B9) },
7717 { PREFIX_TABLE (PREFIX_VEX_38BA) },
7718 { PREFIX_TABLE (PREFIX_VEX_38BB) },
7719 { PREFIX_TABLE (PREFIX_VEX_38BC) },
7720 { PREFIX_TABLE (PREFIX_VEX_38BD) },
7721 { PREFIX_TABLE (PREFIX_VEX_38BE) },
7722 { PREFIX_TABLE (PREFIX_VEX_38BF) },
7754 { PREFIX_TABLE (PREFIX_VEX_38DB) },
7755 { PREFIX_TABLE (PREFIX_VEX_38DC) },
7756 { PREFIX_TABLE (PREFIX_VEX_38DD) },
7757 { PREFIX_TABLE (PREFIX_VEX_38DE) },
7758 { PREFIX_TABLE (PREFIX_VEX_38DF) },
7803 { PREFIX_TABLE (PREFIX_VEX_3A04) },
7804 { PREFIX_TABLE (PREFIX_VEX_3A05) },
7805 { PREFIX_TABLE (PREFIX_VEX_3A06) },
7808 { PREFIX_TABLE (PREFIX_VEX_3A08) },
7809 { PREFIX_TABLE (PREFIX_VEX_3A09) },
7810 { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7811 { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7812 { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7813 { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7814 { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7815 { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7821 { PREFIX_TABLE (PREFIX_VEX_3A14) },
7822 { PREFIX_TABLE (PREFIX_VEX_3A15) },
7823 { PREFIX_TABLE (PREFIX_VEX_3A16) },
7824 { PREFIX_TABLE (PREFIX_VEX_3A17) },
7826 { PREFIX_TABLE (PREFIX_VEX_3A18) },
7827 { PREFIX_TABLE (PREFIX_VEX_3A19) },
7835 { PREFIX_TABLE (PREFIX_VEX_3A20) },
7836 { PREFIX_TABLE (PREFIX_VEX_3A21) },
7837 { PREFIX_TABLE (PREFIX_VEX_3A22) },
7871 { PREFIX_TABLE (PREFIX_VEX_3A40) },
7872 { PREFIX_TABLE (PREFIX_VEX_3A41) },
7873 { PREFIX_TABLE (PREFIX_VEX_3A42) },
7875 { PREFIX_TABLE (PREFIX_VEX_3A44) },
7880 { PREFIX_TABLE (PREFIX_VEX_3A48) },
7881 { PREFIX_TABLE (PREFIX_VEX_3A49) },
7882 { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7883 { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7884 { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7902 { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7903 { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7904 { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7905 { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7907 { PREFIX_TABLE (PREFIX_VEX_3A60) },
7908 { PREFIX_TABLE (PREFIX_VEX_3A61) },
7909 { PREFIX_TABLE (PREFIX_VEX_3A62) },
7910 { PREFIX_TABLE (PREFIX_VEX_3A63) },
7916 { PREFIX_TABLE (PREFIX_VEX_3A68) },
7917 { PREFIX_TABLE (PREFIX_VEX_3A69) },
7918 { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7919 { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7920 { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7921 { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7922 { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7923 { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7934 { PREFIX_TABLE (PREFIX_VEX_3A78) },
7935 { PREFIX_TABLE (PREFIX_VEX_3A79) },
7936 { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7937 { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7938 { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7939 { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7940 { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7941 { PREFIX_TABLE (PREFIX_VEX_3A7F) },
8049 { PREFIX_TABLE (PREFIX_VEX_3ADF) },
8089 static const struct dis386 vex_len_table[][2] = {
8090 /* VEX_LEN_10_P_1 */
8092 { VEX_W_TABLE (VEX_W_10_P_1) },
8093 { VEX_W_TABLE (VEX_W_10_P_1) },
8096 /* VEX_LEN_10_P_3 */
8098 { VEX_W_TABLE (VEX_W_10_P_3) },
8099 { VEX_W_TABLE (VEX_W_10_P_3) },
8102 /* VEX_LEN_11_P_1 */
8104 { VEX_W_TABLE (VEX_W_11_P_1) },
8105 { VEX_W_TABLE (VEX_W_11_P_1) },
8108 /* VEX_LEN_11_P_3 */
8110 { VEX_W_TABLE (VEX_W_11_P_3) },
8111 { VEX_W_TABLE (VEX_W_11_P_3) },
8114 /* VEX_LEN_12_P_0_M_0 */
8116 { VEX_W_TABLE (VEX_W_12_P_0_M_0) },
8119 /* VEX_LEN_12_P_0_M_1 */
8121 { VEX_W_TABLE (VEX_W_12_P_0_M_1) },
8124 /* VEX_LEN_12_P_2 */
8126 { VEX_W_TABLE (VEX_W_12_P_2) },
8129 /* VEX_LEN_13_M_0 */
8131 { VEX_W_TABLE (VEX_W_13_M_0) },
8134 /* VEX_LEN_16_P_0_M_0 */
8136 { VEX_W_TABLE (VEX_W_16_P_0_M_0) },
8139 /* VEX_LEN_16_P_0_M_1 */
8141 { VEX_W_TABLE (VEX_W_16_P_0_M_1) },
8144 /* VEX_LEN_16_P_2 */
8146 { VEX_W_TABLE (VEX_W_16_P_2) },
8149 /* VEX_LEN_17_M_0 */
8151 { VEX_W_TABLE (VEX_W_17_M_0) },
8154 /* VEX_LEN_2A_P_1 */
8156 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
8157 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
8160 /* VEX_LEN_2A_P_3 */
8162 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
8163 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
8166 /* VEX_LEN_2C_P_1 */
8168 { "vcvttss2siY", { Gv, EXdScalar } },
8169 { "vcvttss2siY", { Gv, EXdScalar } },
8172 /* VEX_LEN_2C_P_3 */
8174 { "vcvttsd2siY", { Gv, EXqScalar } },
8175 { "vcvttsd2siY", { Gv, EXqScalar } },
8178 /* VEX_LEN_2D_P_1 */
8180 { "vcvtss2siY", { Gv, EXdScalar } },
8181 { "vcvtss2siY", { Gv, EXdScalar } },
8184 /* VEX_LEN_2D_P_3 */
8186 { "vcvtsd2siY", { Gv, EXqScalar } },
8187 { "vcvtsd2siY", { Gv, EXqScalar } },
8190 /* VEX_LEN_2E_P_0 */
8192 { VEX_W_TABLE (VEX_W_2E_P_0) },
8193 { VEX_W_TABLE (VEX_W_2E_P_0) },
8196 /* VEX_LEN_2E_P_2 */
8198 { VEX_W_TABLE (VEX_W_2E_P_2) },
8199 { VEX_W_TABLE (VEX_W_2E_P_2) },
8202 /* VEX_LEN_2F_P_0 */
8204 { VEX_W_TABLE (VEX_W_2F_P_0) },
8205 { VEX_W_TABLE (VEX_W_2F_P_0) },
8208 /* VEX_LEN_2F_P_2 */
8210 { VEX_W_TABLE (VEX_W_2F_P_2) },
8211 { VEX_W_TABLE (VEX_W_2F_P_2) },
8214 /* VEX_LEN_51_P_1 */
8216 { VEX_W_TABLE (VEX_W_51_P_1) },
8217 { VEX_W_TABLE (VEX_W_51_P_1) },
8220 /* VEX_LEN_51_P_3 */
8222 { VEX_W_TABLE (VEX_W_51_P_3) },
8223 { VEX_W_TABLE (VEX_W_51_P_3) },
8226 /* VEX_LEN_52_P_1 */
8228 { VEX_W_TABLE (VEX_W_52_P_1) },
8229 { VEX_W_TABLE (VEX_W_52_P_1) },
8232 /* VEX_LEN_53_P_1 */
8234 { VEX_W_TABLE (VEX_W_53_P_1) },
8235 { VEX_W_TABLE (VEX_W_53_P_1) },
8238 /* VEX_LEN_58_P_1 */
8240 { VEX_W_TABLE (VEX_W_58_P_1) },
8241 { VEX_W_TABLE (VEX_W_58_P_1) },
8244 /* VEX_LEN_58_P_3 */
8246 { VEX_W_TABLE (VEX_W_58_P_3) },
8247 { VEX_W_TABLE (VEX_W_58_P_3) },
8250 /* VEX_LEN_59_P_1 */
8252 { VEX_W_TABLE (VEX_W_59_P_1) },
8253 { VEX_W_TABLE (VEX_W_59_P_1) },
8256 /* VEX_LEN_59_P_3 */
8258 { VEX_W_TABLE (VEX_W_59_P_3) },
8259 { VEX_W_TABLE (VEX_W_59_P_3) },
8262 /* VEX_LEN_5A_P_1 */
8264 { VEX_W_TABLE (VEX_W_5A_P_1) },
8265 { VEX_W_TABLE (VEX_W_5A_P_1) },
8268 /* VEX_LEN_5A_P_3 */
8270 { VEX_W_TABLE (VEX_W_5A_P_3) },
8271 { VEX_W_TABLE (VEX_W_5A_P_3) },
8274 /* VEX_LEN_5C_P_1 */
8276 { VEX_W_TABLE (VEX_W_5C_P_1) },
8277 { VEX_W_TABLE (VEX_W_5C_P_1) },
8280 /* VEX_LEN_5C_P_3 */
8282 { VEX_W_TABLE (VEX_W_5C_P_3) },
8283 { VEX_W_TABLE (VEX_W_5C_P_3) },
8286 /* VEX_LEN_5D_P_1 */
8288 { VEX_W_TABLE (VEX_W_5D_P_1) },
8289 { VEX_W_TABLE (VEX_W_5D_P_1) },
8292 /* VEX_LEN_5D_P_3 */
8294 { VEX_W_TABLE (VEX_W_5D_P_3) },
8295 { VEX_W_TABLE (VEX_W_5D_P_3) },
8298 /* VEX_LEN_5E_P_1 */
8300 { VEX_W_TABLE (VEX_W_5E_P_1) },
8301 { VEX_W_TABLE (VEX_W_5E_P_1) },
8304 /* VEX_LEN_5E_P_3 */
8306 { VEX_W_TABLE (VEX_W_5E_P_3) },
8307 { VEX_W_TABLE (VEX_W_5E_P_3) },
8310 /* VEX_LEN_5F_P_1 */
8312 { VEX_W_TABLE (VEX_W_5F_P_1) },
8313 { VEX_W_TABLE (VEX_W_5F_P_1) },
8316 /* VEX_LEN_5F_P_3 */
8318 { VEX_W_TABLE (VEX_W_5F_P_3) },
8319 { VEX_W_TABLE (VEX_W_5F_P_3) },
8322 /* VEX_LEN_60_P_2 */
8324 { VEX_W_TABLE (VEX_W_60_P_2) },
8327 /* VEX_LEN_61_P_2 */
8329 { VEX_W_TABLE (VEX_W_61_P_2) },
8332 /* VEX_LEN_62_P_2 */
8334 { VEX_W_TABLE (VEX_W_62_P_2) },
8337 /* VEX_LEN_63_P_2 */
8339 { VEX_W_TABLE (VEX_W_63_P_2) },
8342 /* VEX_LEN_64_P_2 */
8344 { VEX_W_TABLE (VEX_W_64_P_2) },
8347 /* VEX_LEN_65_P_2 */
8349 { VEX_W_TABLE (VEX_W_65_P_2) },
8352 /* VEX_LEN_66_P_2 */
8354 { VEX_W_TABLE (VEX_W_66_P_2) },
8357 /* VEX_LEN_67_P_2 */
8359 { VEX_W_TABLE (VEX_W_67_P_2) },
8362 /* VEX_LEN_68_P_2 */
8364 { VEX_W_TABLE (VEX_W_68_P_2) },
8367 /* VEX_LEN_69_P_2 */
8369 { VEX_W_TABLE (VEX_W_69_P_2) },
8372 /* VEX_LEN_6A_P_2 */
8374 { VEX_W_TABLE (VEX_W_6A_P_2) },
8377 /* VEX_LEN_6B_P_2 */
8379 { VEX_W_TABLE (VEX_W_6B_P_2) },
8382 /* VEX_LEN_6C_P_2 */
8384 { VEX_W_TABLE (VEX_W_6C_P_2) },
8387 /* VEX_LEN_6D_P_2 */
8389 { VEX_W_TABLE (VEX_W_6D_P_2) },
8392 /* VEX_LEN_6E_P_2 */
8394 { "vmovK", { XMScalar, Edq } },
8395 { "vmovK", { XMScalar, Edq } },
8398 /* VEX_LEN_70_P_1 */
8400 { VEX_W_TABLE (VEX_W_70_P_1) },
8403 /* VEX_LEN_70_P_2 */
8405 { VEX_W_TABLE (VEX_W_70_P_2) },
8408 /* VEX_LEN_70_P_3 */
8410 { VEX_W_TABLE (VEX_W_70_P_3) },
8413 /* VEX_LEN_71_R_2_P_2 */
8415 { VEX_W_TABLE (VEX_W_71_R_2_P_2) },
8418 /* VEX_LEN_71_R_4_P_2 */
8420 { VEX_W_TABLE (VEX_W_71_R_4_P_2) },
8423 /* VEX_LEN_71_R_6_P_2 */
8425 { VEX_W_TABLE (VEX_W_71_R_6_P_2) },
8428 /* VEX_LEN_72_R_2_P_2 */
8430 { VEX_W_TABLE (VEX_W_72_R_2_P_2) },
8433 /* VEX_LEN_72_R_4_P_2 */
8435 { VEX_W_TABLE (VEX_W_72_R_4_P_2) },
8438 /* VEX_LEN_72_R_6_P_2 */
8440 { VEX_W_TABLE (VEX_W_72_R_6_P_2) },
8443 /* VEX_LEN_73_R_2_P_2 */
8445 { VEX_W_TABLE (VEX_W_73_R_2_P_2) },
8448 /* VEX_LEN_73_R_3_P_2 */
8450 { VEX_W_TABLE (VEX_W_73_R_3_P_2) },
8453 /* VEX_LEN_73_R_6_P_2 */
8455 { VEX_W_TABLE (VEX_W_73_R_6_P_2) },
8458 /* VEX_LEN_73_R_7_P_2 */
8460 { VEX_W_TABLE (VEX_W_73_R_7_P_2) },
8463 /* VEX_LEN_74_P_2 */
8465 { VEX_W_TABLE (VEX_W_74_P_2) },
8468 /* VEX_LEN_75_P_2 */
8470 { VEX_W_TABLE (VEX_W_75_P_2) },
8473 /* VEX_LEN_76_P_2 */
8475 { VEX_W_TABLE (VEX_W_76_P_2) },
8478 /* VEX_LEN_7E_P_1 */
8480 { VEX_W_TABLE (VEX_W_7E_P_1) },
8481 { VEX_W_TABLE (VEX_W_7E_P_1) },
8484 /* VEX_LEN_7E_P_2 */
8486 { "vmovK", { Edq, XMScalar } },
8487 { "vmovK", { Edq, XMScalar } },
8490 /* VEX_LEN_AE_R_2_M_0 */
8492 { VEX_W_TABLE (VEX_W_AE_R_2_M_0) },
8495 /* VEX_LEN_AE_R_3_M_0 */
8497 { VEX_W_TABLE (VEX_W_AE_R_3_M_0) },
8500 /* VEX_LEN_C2_P_1 */
8502 { VEX_W_TABLE (VEX_W_C2_P_1) },
8503 { VEX_W_TABLE (VEX_W_C2_P_1) },
8506 /* VEX_LEN_C2_P_3 */
8508 { VEX_W_TABLE (VEX_W_C2_P_3) },
8509 { VEX_W_TABLE (VEX_W_C2_P_3) },
8512 /* VEX_LEN_C4_P_2 */
8514 { VEX_W_TABLE (VEX_W_C4_P_2) },
8517 /* VEX_LEN_C5_P_2 */
8519 { VEX_W_TABLE (VEX_W_C5_P_2) },
8522 /* VEX_LEN_D1_P_2 */
8524 { VEX_W_TABLE (VEX_W_D1_P_2) },
8527 /* VEX_LEN_D2_P_2 */
8529 { VEX_W_TABLE (VEX_W_D2_P_2) },
8532 /* VEX_LEN_D3_P_2 */
8534 { VEX_W_TABLE (VEX_W_D3_P_2) },
8537 /* VEX_LEN_D4_P_2 */
8539 { VEX_W_TABLE (VEX_W_D4_P_2) },
8542 /* VEX_LEN_D5_P_2 */
8544 { VEX_W_TABLE (VEX_W_D5_P_2) },
8547 /* VEX_LEN_D6_P_2 */
8549 { VEX_W_TABLE (VEX_W_D6_P_2) },
8550 { VEX_W_TABLE (VEX_W_D6_P_2) },
8553 /* VEX_LEN_D7_P_2_M_1 */
8555 { VEX_W_TABLE (VEX_W_D7_P_2_M_1) },
8558 /* VEX_LEN_D8_P_2 */
8560 { VEX_W_TABLE (VEX_W_D8_P_2) },
8563 /* VEX_LEN_D9_P_2 */
8565 { VEX_W_TABLE (VEX_W_D9_P_2) },
8568 /* VEX_LEN_DA_P_2 */
8570 { VEX_W_TABLE (VEX_W_DA_P_2) },
8573 /* VEX_LEN_DB_P_2 */
8575 { VEX_W_TABLE (VEX_W_DB_P_2) },
8578 /* VEX_LEN_DC_P_2 */
8580 { VEX_W_TABLE (VEX_W_DC_P_2) },
8583 /* VEX_LEN_DD_P_2 */
8585 { VEX_W_TABLE (VEX_W_DD_P_2) },
8588 /* VEX_LEN_DE_P_2 */
8590 { VEX_W_TABLE (VEX_W_DE_P_2) },
8593 /* VEX_LEN_DF_P_2 */
8595 { VEX_W_TABLE (VEX_W_DF_P_2) },
8598 /* VEX_LEN_E0_P_2 */
8600 { VEX_W_TABLE (VEX_W_E0_P_2) },
8603 /* VEX_LEN_E1_P_2 */
8605 { VEX_W_TABLE (VEX_W_E1_P_2) },
8608 /* VEX_LEN_E2_P_2 */
8610 { VEX_W_TABLE (VEX_W_E2_P_2) },
8613 /* VEX_LEN_E3_P_2 */
8615 { VEX_W_TABLE (VEX_W_E3_P_2) },
8618 /* VEX_LEN_E4_P_2 */
8620 { VEX_W_TABLE (VEX_W_E4_P_2) },
8623 /* VEX_LEN_E5_P_2 */
8625 { VEX_W_TABLE (VEX_W_E5_P_2) },
8628 /* VEX_LEN_E8_P_2 */
8630 { VEX_W_TABLE (VEX_W_E8_P_2) },
8633 /* VEX_LEN_E9_P_2 */
8635 { VEX_W_TABLE (VEX_W_E9_P_2) },
8638 /* VEX_LEN_EA_P_2 */
8640 { VEX_W_TABLE (VEX_W_EA_P_2) },
8643 /* VEX_LEN_EB_P_2 */
8645 { VEX_W_TABLE (VEX_W_EB_P_2) },
8648 /* VEX_LEN_EC_P_2 */
8650 { VEX_W_TABLE (VEX_W_EC_P_2) },
8653 /* VEX_LEN_ED_P_2 */
8655 { VEX_W_TABLE (VEX_W_ED_P_2) },
8658 /* VEX_LEN_EE_P_2 */
8660 { VEX_W_TABLE (VEX_W_EE_P_2) },
8663 /* VEX_LEN_EF_P_2 */
8665 { VEX_W_TABLE (VEX_W_EF_P_2) },
8668 /* VEX_LEN_F1_P_2 */
8670 { VEX_W_TABLE (VEX_W_F1_P_2) },
8673 /* VEX_LEN_F2_P_2 */
8675 { VEX_W_TABLE (VEX_W_F2_P_2) },
8678 /* VEX_LEN_F3_P_2 */
8680 { VEX_W_TABLE (VEX_W_F3_P_2) },
8683 /* VEX_LEN_F4_P_2 */
8685 { VEX_W_TABLE (VEX_W_F4_P_2) },
8688 /* VEX_LEN_F5_P_2 */
8690 { VEX_W_TABLE (VEX_W_F5_P_2) },
8693 /* VEX_LEN_F6_P_2 */
8695 { VEX_W_TABLE (VEX_W_F6_P_2) },
8698 /* VEX_LEN_F7_P_2 */
8700 { VEX_W_TABLE (VEX_W_F7_P_2) },
8703 /* VEX_LEN_F8_P_2 */
8705 { VEX_W_TABLE (VEX_W_F8_P_2) },
8708 /* VEX_LEN_F9_P_2 */
8710 { VEX_W_TABLE (VEX_W_F9_P_2) },
8713 /* VEX_LEN_FA_P_2 */
8715 { VEX_W_TABLE (VEX_W_FA_P_2) },
8718 /* VEX_LEN_FB_P_2 */
8720 { VEX_W_TABLE (VEX_W_FB_P_2) },
8723 /* VEX_LEN_FC_P_2 */
8725 { VEX_W_TABLE (VEX_W_FC_P_2) },
8728 /* VEX_LEN_FD_P_2 */
8730 { VEX_W_TABLE (VEX_W_FD_P_2) },
8733 /* VEX_LEN_FE_P_2 */
8735 { VEX_W_TABLE (VEX_W_FE_P_2) },
8738 /* VEX_LEN_3800_P_2 */
8740 { VEX_W_TABLE (VEX_W_3800_P_2) },
8743 /* VEX_LEN_3801_P_2 */
8745 { VEX_W_TABLE (VEX_W_3801_P_2) },
8748 /* VEX_LEN_3802_P_2 */
8750 { VEX_W_TABLE (VEX_W_3802_P_2) },
8753 /* VEX_LEN_3803_P_2 */
8755 { VEX_W_TABLE (VEX_W_3803_P_2) },
8758 /* VEX_LEN_3804_P_2 */
8760 { VEX_W_TABLE (VEX_W_3804_P_2) },
8763 /* VEX_LEN_3805_P_2 */
8765 { VEX_W_TABLE (VEX_W_3805_P_2) },
8768 /* VEX_LEN_3806_P_2 */
8770 { VEX_W_TABLE (VEX_W_3806_P_2) },
8773 /* VEX_LEN_3807_P_2 */
8775 { VEX_W_TABLE (VEX_W_3807_P_2) },
8778 /* VEX_LEN_3808_P_2 */
8780 { VEX_W_TABLE (VEX_W_3808_P_2) },
8783 /* VEX_LEN_3809_P_2 */
8785 { VEX_W_TABLE (VEX_W_3809_P_2) },
8788 /* VEX_LEN_380A_P_2 */
8790 { VEX_W_TABLE (VEX_W_380A_P_2) },
8793 /* VEX_LEN_380B_P_2 */
8795 { VEX_W_TABLE (VEX_W_380B_P_2) },
8798 /* VEX_LEN_3819_P_2_M_0 */
8801 { VEX_W_TABLE (VEX_W_3819_P_2_M_0) },
8804 /* VEX_LEN_381A_P_2_M_0 */
8807 { VEX_W_TABLE (VEX_W_381A_P_2_M_0) },
8810 /* VEX_LEN_381C_P_2 */
8812 { VEX_W_TABLE (VEX_W_381C_P_2) },
8815 /* VEX_LEN_381D_P_2 */
8817 { VEX_W_TABLE (VEX_W_381D_P_2) },
8820 /* VEX_LEN_381E_P_2 */
8822 { VEX_W_TABLE (VEX_W_381E_P_2) },
8825 /* VEX_LEN_3820_P_2 */
8827 { VEX_W_TABLE (VEX_W_3820_P_2) },
8830 /* VEX_LEN_3821_P_2 */
8832 { VEX_W_TABLE (VEX_W_3821_P_2) },
8835 /* VEX_LEN_3822_P_2 */
8837 { VEX_W_TABLE (VEX_W_3822_P_2) },
8840 /* VEX_LEN_3823_P_2 */
8842 { VEX_W_TABLE (VEX_W_3823_P_2) },
8845 /* VEX_LEN_3824_P_2 */
8847 { VEX_W_TABLE (VEX_W_3824_P_2) },
8850 /* VEX_LEN_3825_P_2 */
8852 { VEX_W_TABLE (VEX_W_3825_P_2) },
8855 /* VEX_LEN_3828_P_2 */
8857 { VEX_W_TABLE (VEX_W_3828_P_2) },
8860 /* VEX_LEN_3829_P_2 */
8862 { VEX_W_TABLE (VEX_W_3829_P_2) },
8865 /* VEX_LEN_382A_P_2_M_0 */
8867 { VEX_W_TABLE (VEX_W_382A_P_2_M_0) },
8870 /* VEX_LEN_382B_P_2 */
8872 { VEX_W_TABLE (VEX_W_382B_P_2) },
8875 /* VEX_LEN_3830_P_2 */
8877 { VEX_W_TABLE (VEX_W_3830_P_2) },
8880 /* VEX_LEN_3831_P_2 */
8882 { VEX_W_TABLE (VEX_W_3831_P_2) },
8885 /* VEX_LEN_3832_P_2 */
8887 { VEX_W_TABLE (VEX_W_3832_P_2) },
8890 /* VEX_LEN_3833_P_2 */
8892 { VEX_W_TABLE (VEX_W_3833_P_2) },
8895 /* VEX_LEN_3834_P_2 */
8897 { VEX_W_TABLE (VEX_W_3834_P_2) },
8900 /* VEX_LEN_3835_P_2 */
8902 { VEX_W_TABLE (VEX_W_3835_P_2) },
8905 /* VEX_LEN_3837_P_2 */
8907 { VEX_W_TABLE (VEX_W_3837_P_2) },
8910 /* VEX_LEN_3838_P_2 */
8912 { VEX_W_TABLE (VEX_W_3838_P_2) },
8915 /* VEX_LEN_3839_P_2 */
8917 { VEX_W_TABLE (VEX_W_3839_P_2) },
8920 /* VEX_LEN_383A_P_2 */
8922 { VEX_W_TABLE (VEX_W_383A_P_2) },
8925 /* VEX_LEN_383B_P_2 */
8927 { VEX_W_TABLE (VEX_W_383B_P_2) },
8930 /* VEX_LEN_383C_P_2 */
8932 { VEX_W_TABLE (VEX_W_383C_P_2) },
8935 /* VEX_LEN_383D_P_2 */
8937 { VEX_W_TABLE (VEX_W_383D_P_2) },
8940 /* VEX_LEN_383E_P_2 */
8942 { VEX_W_TABLE (VEX_W_383E_P_2) },
8945 /* VEX_LEN_383F_P_2 */
8947 { VEX_W_TABLE (VEX_W_383F_P_2) },
8950 /* VEX_LEN_3840_P_2 */
8952 { VEX_W_TABLE (VEX_W_3840_P_2) },
8955 /* VEX_LEN_3841_P_2 */
8957 { VEX_W_TABLE (VEX_W_3841_P_2) },
8960 /* VEX_LEN_38DB_P_2 */
8962 { VEX_W_TABLE (VEX_W_38DB_P_2) },
8965 /* VEX_LEN_38DC_P_2 */
8967 { VEX_W_TABLE (VEX_W_38DC_P_2) },
8970 /* VEX_LEN_38DD_P_2 */
8972 { VEX_W_TABLE (VEX_W_38DD_P_2) },
8975 /* VEX_LEN_38DE_P_2 */
8977 { VEX_W_TABLE (VEX_W_38DE_P_2) },
8980 /* VEX_LEN_38DF_P_2 */
8982 { VEX_W_TABLE (VEX_W_38DF_P_2) },
8985 /* VEX_LEN_3A06_P_2 */
8988 { VEX_W_TABLE (VEX_W_3A06_P_2) },
8991 /* VEX_LEN_3A0A_P_2 */
8993 { VEX_W_TABLE (VEX_W_3A0A_P_2) },
8994 { VEX_W_TABLE (VEX_W_3A0A_P_2) },
8997 /* VEX_LEN_3A0B_P_2 */
8999 { VEX_W_TABLE (VEX_W_3A0B_P_2) },
9000 { VEX_W_TABLE (VEX_W_3A0B_P_2) },
9003 /* VEX_LEN_3A0E_P_2 */
9005 { VEX_W_TABLE (VEX_W_3A0E_P_2) },
9008 /* VEX_LEN_3A0F_P_2 */
9010 { VEX_W_TABLE (VEX_W_3A0F_P_2) },
9013 /* VEX_LEN_3A14_P_2 */
9015 { VEX_W_TABLE (VEX_W_3A14_P_2) },
9018 /* VEX_LEN_3A15_P_2 */
9020 { VEX_W_TABLE (VEX_W_3A15_P_2) },
9023 /* VEX_LEN_3A16_P_2 */
9025 { "vpextrK", { Edq, XM, Ib } },
9028 /* VEX_LEN_3A17_P_2 */
9030 { "vextractps", { Edqd, XM, Ib } },
9033 /* VEX_LEN_3A18_P_2 */
9036 { VEX_W_TABLE (VEX_W_3A18_P_2) },
9039 /* VEX_LEN_3A19_P_2 */
9042 { VEX_W_TABLE (VEX_W_3A19_P_2) },
9045 /* VEX_LEN_3A20_P_2 */
9047 { VEX_W_TABLE (VEX_W_3A20_P_2) },
9050 /* VEX_LEN_3A21_P_2 */
9052 { VEX_W_TABLE (VEX_W_3A21_P_2) },
9055 /* VEX_LEN_3A22_P_2 */
9057 { "vpinsrK", { XM, Vex128, Edq, Ib } },
9060 /* VEX_LEN_3A41_P_2 */
9062 { VEX_W_TABLE (VEX_W_3A41_P_2) },
9065 /* VEX_LEN_3A42_P_2 */
9067 { VEX_W_TABLE (VEX_W_3A42_P_2) },
9070 /* VEX_LEN_3A44_P_2 */
9072 { VEX_W_TABLE (VEX_W_3A44_P_2) },
9075 /* VEX_LEN_3A4C_P_2 */
9077 { VEX_W_TABLE (VEX_W_3A4C_P_2) },
9080 /* VEX_LEN_3A60_P_2 */
9082 { VEX_W_TABLE (VEX_W_3A60_P_2) },
9085 /* VEX_LEN_3A61_P_2 */
9087 { VEX_W_TABLE (VEX_W_3A61_P_2) },
9090 /* VEX_LEN_3A62_P_2 */
9092 { VEX_W_TABLE (VEX_W_3A62_P_2) },
9095 /* VEX_LEN_3A63_P_2 */
9097 { VEX_W_TABLE (VEX_W_3A63_P_2) },
9100 /* VEX_LEN_3A6A_P_2 */
9102 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9105 /* VEX_LEN_3A6B_P_2 */
9107 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9110 /* VEX_LEN_3A6E_P_2 */
9112 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9115 /* VEX_LEN_3A6F_P_2 */
9117 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9120 /* VEX_LEN_3A7A_P_2 */
9122 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9125 /* VEX_LEN_3A7B_P_2 */
9127 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9130 /* VEX_LEN_3A7E_P_2 */
9132 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9135 /* VEX_LEN_3A7F_P_2 */
9137 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9140 /* VEX_LEN_3ADF_P_2 */
9142 { VEX_W_TABLE (VEX_W_3ADF_P_2) },
9145 /* VEX_LEN_XOP_09_80 */
9147 { "vfrczps", { XM, EXxmm } },
9148 { "vfrczps", { XM, EXymmq } },
9151 /* VEX_LEN_XOP_09_81 */
9153 { "vfrczpd", { XM, EXxmm } },
9154 { "vfrczpd", { XM, EXymmq } },
9158 static const struct dis386 vex_w_table[][2] = {
9161 { "vmovups", { XM, EXx } },
9165 { "vmovss", { XMVexScalar, VexScalar, EXdScalar } },
9169 { "vmovupd", { XM, EXx } },
9173 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } },
9177 { "vmovups", { EXxS, XM } },
9181 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } },
9185 { "vmovupd", { EXxS, XM } },
9189 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } },
9192 /* VEX_W_12_P_0_M_0 */
9193 { "vmovlps", { XM, Vex128, EXq } },
9196 /* VEX_W_12_P_0_M_1 */
9197 { "vmovhlps", { XM, Vex128, EXq } },
9201 { "vmovsldup", { XM, EXx } },
9205 { "vmovlpd", { XM, Vex128, EXq } },
9209 { "vmovddup", { XM, EXymmq } },
9213 { "vmovlpX", { EXq, XM } },
9217 { "vunpcklpX", { XM, Vex, EXx } },
9221 { "vunpckhpX", { XM, Vex, EXx } },
9224 /* VEX_W_16_P_0_M_0 */
9225 { "vmovhps", { XM, Vex128, EXq } },
9228 /* VEX_W_16_P_0_M_1 */
9229 { "vmovlhps", { XM, Vex128, EXq } },
9233 { "vmovshdup", { XM, EXx } },
9237 { "vmovhpd", { XM, Vex128, EXq } },
9241 { "vmovhpX", { EXq, XM } },
9245 { "vmovapX", { XM, EXx } },
9249 { "vmovapX", { EXxS, XM } },
9253 { "vmovntpX", { Mx, XM } },
9257 { "vucomiss", { XMScalar, EXdScalar } },
9261 { "vucomisd", { XMScalar, EXqScalar } },
9265 { "vcomiss", { XMScalar, EXdScalar } },
9269 { "vcomisd", { XMScalar, EXqScalar } },
9273 { "vmovmskpX", { Gdq, XS } },
9277 { "vsqrtps", { XM, EXx } },
9281 { "vsqrtss", { XMScalar, VexScalar, EXdScalar } },
9285 { "vsqrtpd", { XM, EXx } },
9289 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar } },
9293 { "vrsqrtps", { XM, EXx } },
9297 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar } },
9301 { "vrcpps", { XM, EXx } },
9305 { "vrcpss", { XMScalar, VexScalar, EXdScalar } },
9309 { "vaddps", { XM, Vex, EXx } },
9313 { "vaddss", { XMScalar, VexScalar, EXdScalar } },
9317 { "vaddpd", { XM, Vex, EXx } },
9321 { "vaddsd", { XMScalar, VexScalar, EXqScalar } },
9325 { "vmulps", { XM, Vex, EXx } },
9329 { "vmulss", { XMScalar, VexScalar, EXdScalar } },
9333 { "vmulpd", { XM, Vex, EXx } },
9337 { "vmulsd", { XMScalar, VexScalar, EXqScalar } },
9341 { "vcvtps2pd", { XM, EXxmmq } },
9345 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar } },
9349 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar } },
9353 { "vcvtdq2ps", { XM, EXx } },
9357 { "vcvttps2dq", { XM, EXx } },
9361 { "vcvtps2dq", { XM, EXx } },
9365 { "vsubps", { XM, Vex, EXx } },
9369 { "vsubss", { XMScalar, VexScalar, EXdScalar } },
9373 { "vsubpd", { XM, Vex, EXx } },
9377 { "vsubsd", { XMScalar, VexScalar, EXqScalar } },
9381 { "vminps", { XM, Vex, EXx } },
9385 { "vminss", { XMScalar, VexScalar, EXdScalar } },
9389 { "vminpd", { XM, Vex, EXx } },
9393 { "vminsd", { XMScalar, VexScalar, EXqScalar } },
9397 { "vdivps", { XM, Vex, EXx } },
9401 { "vdivss", { XMScalar, VexScalar, EXdScalar } },
9405 { "vdivpd", { XM, Vex, EXx } },
9409 { "vdivsd", { XMScalar, VexScalar, EXqScalar } },
9413 { "vmaxps", { XM, Vex, EXx } },
9417 { "vmaxss", { XMScalar, VexScalar, EXdScalar } },
9421 { "vmaxpd", { XM, Vex, EXx } },
9425 { "vmaxsd", { XMScalar, VexScalar, EXqScalar } },
9429 { "vpunpcklbw", { XM, Vex128, EXx } },
9433 { "vpunpcklwd", { XM, Vex128, EXx } },
9437 { "vpunpckldq", { XM, Vex128, EXx } },
9441 { "vpacksswb", { XM, Vex128, EXx } },
9445 { "vpcmpgtb", { XM, Vex128, EXx } },
9449 { "vpcmpgtw", { XM, Vex128, EXx } },
9453 { "vpcmpgtd", { XM, Vex128, EXx } },
9457 { "vpackuswb", { XM, Vex128, EXx } },
9461 { "vpunpckhbw", { XM, Vex128, EXx } },
9465 { "vpunpckhwd", { XM, Vex128, EXx } },
9469 { "vpunpckhdq", { XM, Vex128, EXx } },
9473 { "vpackssdw", { XM, Vex128, EXx } },
9477 { "vpunpcklqdq", { XM, Vex128, EXx } },
9481 { "vpunpckhqdq", { XM, Vex128, EXx } },
9485 { "vmovdqu", { XM, EXx } },
9489 { "vmovdqa", { XM, EXx } },
9493 { "vpshufhw", { XM, EXx, Ib } },
9497 { "vpshufd", { XM, EXx, Ib } },
9501 { "vpshuflw", { XM, EXx, Ib } },
9504 /* VEX_W_71_R_2_P_2 */
9505 { "vpsrlw", { Vex128, XS, Ib } },
9508 /* VEX_W_71_R_4_P_2 */
9509 { "vpsraw", { Vex128, XS, Ib } },
9512 /* VEX_W_71_R_6_P_2 */
9513 { "vpsllw", { Vex128, XS, Ib } },
9516 /* VEX_W_72_R_2_P_2 */
9517 { "vpsrld", { Vex128, XS, Ib } },
9520 /* VEX_W_72_R_4_P_2 */
9521 { "vpsrad", { Vex128, XS, Ib } },
9524 /* VEX_W_72_R_6_P_2 */
9525 { "vpslld", { Vex128, XS, Ib } },
9528 /* VEX_W_73_R_2_P_2 */
9529 { "vpsrlq", { Vex128, XS, Ib } },
9532 /* VEX_W_73_R_3_P_2 */
9533 { "vpsrldq", { Vex128, XS, Ib } },
9536 /* VEX_W_73_R_6_P_2 */
9537 { "vpsllq", { Vex128, XS, Ib } },
9540 /* VEX_W_73_R_7_P_2 */
9541 { "vpslldq", { Vex128, XS, Ib } },
9545 { "vpcmpeqb", { XM, Vex128, EXx } },
9549 { "vpcmpeqw", { XM, Vex128, EXx } },
9553 { "vpcmpeqd", { XM, Vex128, EXx } },
9561 { "vhaddpd", { XM, Vex, EXx } },
9565 { "vhaddps", { XM, Vex, EXx } },
9569 { "vhsubpd", { XM, Vex, EXx } },
9573 { "vhsubps", { XM, Vex, EXx } },
9577 { "vmovq", { XMScalar, EXqScalar } },
9581 { "vmovdqu", { EXxS, XM } },
9585 { "vmovdqa", { EXxS, XM } },
9588 /* VEX_W_AE_R_2_M_0 */
9589 { "vldmxcsr", { Md } },
9592 /* VEX_W_AE_R_3_M_0 */
9593 { "vstmxcsr", { Md } },
9597 { "vcmpps", { XM, Vex, EXx, VCMP } },
9601 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP } },
9605 { "vcmppd", { XM, Vex, EXx, VCMP } },
9609 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP } },
9613 { "vpinsrw", { XM, Vex128, Edqw, Ib } },
9617 { "vpextrw", { Gdq, XS, Ib } },
9621 { "vaddsubpd", { XM, Vex, EXx } },
9625 { "vaddsubps", { XM, Vex, EXx } },
9629 { "vpsrlw", { XM, Vex128, EXx } },
9633 { "vpsrld", { XM, Vex128, EXx } },
9637 { "vpsrlq", { XM, Vex128, EXx } },
9641 { "vpaddq", { XM, Vex128, EXx } },
9645 { "vpmullw", { XM, Vex128, EXx } },
9649 { "vmovq", { EXqScalarS, XMScalar } },
9652 /* VEX_W_D7_P_2_M_1 */
9653 { "vpmovmskb", { Gdq, XS } },
9657 { "vpsubusb", { XM, Vex128, EXx } },
9661 { "vpsubusw", { XM, Vex128, EXx } },
9665 { "vpminub", { XM, Vex128, EXx } },
9669 { "vpand", { XM, Vex128, EXx } },
9673 { "vpaddusb", { XM, Vex128, EXx } },
9677 { "vpaddusw", { XM, Vex128, EXx } },
9681 { "vpmaxub", { XM, Vex128, EXx } },
9685 { "vpandn", { XM, Vex128, EXx } },
9689 { "vpavgb", { XM, Vex128, EXx } },
9693 { "vpsraw", { XM, Vex128, EXx } },
9697 { "vpsrad", { XM, Vex128, EXx } },
9701 { "vpavgw", { XM, Vex128, EXx } },
9705 { "vpmulhuw", { XM, Vex128, EXx } },
9709 { "vpmulhw", { XM, Vex128, EXx } },
9713 { "vcvtdq2pd", { XM, EXxmmq } },
9717 { "vcvttpd2dq%XY", { XMM, EXx } },
9721 { "vcvtpd2dq%XY", { XMM, EXx } },
9724 /* VEX_W_E7_P_2_M_0 */
9725 { "vmovntdq", { Mx, XM } },
9729 { "vpsubsb", { XM, Vex128, EXx } },
9733 { "vpsubsw", { XM, Vex128, EXx } },
9737 { "vpminsw", { XM, Vex128, EXx } },
9741 { "vpor", { XM, Vex128, EXx } },
9745 { "vpaddsb", { XM, Vex128, EXx } },
9749 { "vpaddsw", { XM, Vex128, EXx } },
9753 { "vpmaxsw", { XM, Vex128, EXx } },
9757 { "vpxor", { XM, Vex128, EXx } },
9760 /* VEX_W_F0_P_3_M_0 */
9761 { "vlddqu", { XM, M } },
9765 { "vpsllw", { XM, Vex128, EXx } },
9769 { "vpslld", { XM, Vex128, EXx } },
9773 { "vpsllq", { XM, Vex128, EXx } },
9777 { "vpmuludq", { XM, Vex128, EXx } },
9781 { "vpmaddwd", { XM, Vex128, EXx } },
9785 { "vpsadbw", { XM, Vex128, EXx } },
9789 { "vmaskmovdqu", { XM, XS } },
9793 { "vpsubb", { XM, Vex128, EXx } },
9797 { "vpsubw", { XM, Vex128, EXx } },
9801 { "vpsubd", { XM, Vex128, EXx } },
9805 { "vpsubq", { XM, Vex128, EXx } },
9809 { "vpaddb", { XM, Vex128, EXx } },
9813 { "vpaddw", { XM, Vex128, EXx } },
9817 { "vpaddd", { XM, Vex128, EXx } },
9820 /* VEX_W_3800_P_2 */
9821 { "vpshufb", { XM, Vex128, EXx } },
9824 /* VEX_W_3801_P_2 */
9825 { "vphaddw", { XM, Vex128, EXx } },
9828 /* VEX_W_3802_P_2 */
9829 { "vphaddd", { XM, Vex128, EXx } },
9832 /* VEX_W_3803_P_2 */
9833 { "vphaddsw", { XM, Vex128, EXx } },
9836 /* VEX_W_3804_P_2 */
9837 { "vpmaddubsw", { XM, Vex128, EXx } },
9840 /* VEX_W_3805_P_2 */
9841 { "vphsubw", { XM, Vex128, EXx } },
9844 /* VEX_W_3806_P_2 */
9845 { "vphsubd", { XM, Vex128, EXx } },
9848 /* VEX_W_3807_P_2 */
9849 { "vphsubsw", { XM, Vex128, EXx } },
9852 /* VEX_W_3808_P_2 */
9853 { "vpsignb", { XM, Vex128, EXx } },
9856 /* VEX_W_3809_P_2 */
9857 { "vpsignw", { XM, Vex128, EXx } },
9860 /* VEX_W_380A_P_2 */
9861 { "vpsignd", { XM, Vex128, EXx } },
9864 /* VEX_W_380B_P_2 */
9865 { "vpmulhrsw", { XM, Vex128, EXx } },
9868 /* VEX_W_380C_P_2 */
9869 { "vpermilps", { XM, Vex, EXx } },
9872 /* VEX_W_380D_P_2 */
9873 { "vpermilpd", { XM, Vex, EXx } },
9876 /* VEX_W_380E_P_2 */
9877 { "vtestps", { XM, EXx } },
9880 /* VEX_W_380F_P_2 */
9881 { "vtestpd", { XM, EXx } },
9884 /* VEX_W_3817_P_2 */
9885 { "vptest", { XM, EXx } },
9888 /* VEX_W_3818_P_2_M_0 */
9889 { "vbroadcastss", { XM, Md } },
9892 /* VEX_W_3819_P_2_M_0 */
9893 { "vbroadcastsd", { XM, Mq } },
9896 /* VEX_W_381A_P_2_M_0 */
9897 { "vbroadcastf128", { XM, Mxmm } },
9900 /* VEX_W_381C_P_2 */
9901 { "vpabsb", { XM, EXx } },
9904 /* VEX_W_381D_P_2 */
9905 { "vpabsw", { XM, EXx } },
9908 /* VEX_W_381E_P_2 */
9909 { "vpabsd", { XM, EXx } },
9912 /* VEX_W_3820_P_2 */
9913 { "vpmovsxbw", { XM, EXq } },
9916 /* VEX_W_3821_P_2 */
9917 { "vpmovsxbd", { XM, EXd } },
9920 /* VEX_W_3822_P_2 */
9921 { "vpmovsxbq", { XM, EXw } },
9924 /* VEX_W_3823_P_2 */
9925 { "vpmovsxwd", { XM, EXq } },
9928 /* VEX_W_3824_P_2 */
9929 { "vpmovsxwq", { XM, EXd } },
9932 /* VEX_W_3825_P_2 */
9933 { "vpmovsxdq", { XM, EXq } },
9936 /* VEX_W_3828_P_2 */
9937 { "vpmuldq", { XM, Vex128, EXx } },
9940 /* VEX_W_3829_P_2 */
9941 { "vpcmpeqq", { XM, Vex128, EXx } },
9944 /* VEX_W_382A_P_2_M_0 */
9945 { "vmovntdqa", { XM, Mx } },
9948 /* VEX_W_382B_P_2 */
9949 { "vpackusdw", { XM, Vex128, EXx } },
9952 /* VEX_W_382C_P_2_M_0 */
9953 { "vmaskmovps", { XM, Vex, Mx } },
9956 /* VEX_W_382D_P_2_M_0 */
9957 { "vmaskmovpd", { XM, Vex, Mx } },
9960 /* VEX_W_382E_P_2_M_0 */
9961 { "vmaskmovps", { Mx, Vex, XM } },
9964 /* VEX_W_382F_P_2_M_0 */
9965 { "vmaskmovpd", { Mx, Vex, XM } },
9968 /* VEX_W_3830_P_2 */
9969 { "vpmovzxbw", { XM, EXq } },
9972 /* VEX_W_3831_P_2 */
9973 { "vpmovzxbd", { XM, EXd } },
9976 /* VEX_W_3832_P_2 */
9977 { "vpmovzxbq", { XM, EXw } },
9980 /* VEX_W_3833_P_2 */
9981 { "vpmovzxwd", { XM, EXq } },
9984 /* VEX_W_3834_P_2 */
9985 { "vpmovzxwq", { XM, EXd } },
9988 /* VEX_W_3835_P_2 */
9989 { "vpmovzxdq", { XM, EXq } },
9992 /* VEX_W_3837_P_2 */
9993 { "vpcmpgtq", { XM, Vex128, EXx } },
9996 /* VEX_W_3838_P_2 */
9997 { "vpminsb", { XM, Vex128, EXx } },
10000 /* VEX_W_3839_P_2 */
10001 { "vpminsd", { XM, Vex128, EXx } },
10004 /* VEX_W_383A_P_2 */
10005 { "vpminuw", { XM, Vex128, EXx } },
10008 /* VEX_W_383B_P_2 */
10009 { "vpminud", { XM, Vex128, EXx } },
10012 /* VEX_W_383C_P_2 */
10013 { "vpmaxsb", { XM, Vex128, EXx } },
10016 /* VEX_W_383D_P_2 */
10017 { "vpmaxsd", { XM, Vex128, EXx } },
10020 /* VEX_W_383E_P_2 */
10021 { "vpmaxuw", { XM, Vex128, EXx } },
10024 /* VEX_W_383F_P_2 */
10025 { "vpmaxud", { XM, Vex128, EXx } },
10028 /* VEX_W_3840_P_2 */
10029 { "vpmulld", { XM, Vex128, EXx } },
10032 /* VEX_W_3841_P_2 */
10033 { "vphminposuw", { XM, EXx } },
10036 /* VEX_W_38DB_P_2 */
10037 { "vaesimc", { XM, EXx } },
10040 /* VEX_W_38DC_P_2 */
10041 { "vaesenc", { XM, Vex128, EXx } },
10044 /* VEX_W_38DD_P_2 */
10045 { "vaesenclast", { XM, Vex128, EXx } },
10048 /* VEX_W_38DE_P_2 */
10049 { "vaesdec", { XM, Vex128, EXx } },
10052 /* VEX_W_38DF_P_2 */
10053 { "vaesdeclast", { XM, Vex128, EXx } },
10056 /* VEX_W_3A04_P_2 */
10057 { "vpermilps", { XM, EXx, Ib } },
10060 /* VEX_W_3A05_P_2 */
10061 { "vpermilpd", { XM, EXx, Ib } },
10064 /* VEX_W_3A06_P_2 */
10065 { "vperm2f128", { XM, Vex256, EXx, Ib } },
10068 /* VEX_W_3A08_P_2 */
10069 { "vroundps", { XM, EXx, Ib } },
10072 /* VEX_W_3A09_P_2 */
10073 { "vroundpd", { XM, EXx, Ib } },
10076 /* VEX_W_3A0A_P_2 */
10077 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib } },
10080 /* VEX_W_3A0B_P_2 */
10081 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib } },
10084 /* VEX_W_3A0C_P_2 */
10085 { "vblendps", { XM, Vex, EXx, Ib } },
10088 /* VEX_W_3A0D_P_2 */
10089 { "vblendpd", { XM, Vex, EXx, Ib } },
10092 /* VEX_W_3A0E_P_2 */
10093 { "vpblendw", { XM, Vex128, EXx, Ib } },
10096 /* VEX_W_3A0F_P_2 */
10097 { "vpalignr", { XM, Vex128, EXx, Ib } },
10100 /* VEX_W_3A14_P_2 */
10101 { "vpextrb", { Edqb, XM, Ib } },
10104 /* VEX_W_3A15_P_2 */
10105 { "vpextrw", { Edqw, XM, Ib } },
10108 /* VEX_W_3A18_P_2 */
10109 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },
10112 /* VEX_W_3A19_P_2 */
10113 { "vextractf128", { EXxmm, XM, Ib } },
10116 /* VEX_W_3A20_P_2 */
10117 { "vpinsrb", { XM, Vex128, Edqb, Ib } },
10120 /* VEX_W_3A21_P_2 */
10121 { "vinsertps", { XM, Vex128, EXd, Ib } },
10124 /* VEX_W_3A40_P_2 */
10125 { "vdpps", { XM, Vex, EXx, Ib } },
10128 /* VEX_W_3A41_P_2 */
10129 { "vdppd", { XM, Vex128, EXx, Ib } },
10132 /* VEX_W_3A42_P_2 */
10133 { "vmpsadbw", { XM, Vex128, EXx, Ib } },
10136 /* VEX_W_3A44_P_2 */
10137 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } },
10140 /* VEX_W_3A48_P_2 */
10141 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10142 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10145 /* VEX_W_3A49_P_2 */
10146 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10147 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10150 /* VEX_W_3A4A_P_2 */
10151 { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
10154 /* VEX_W_3A4B_P_2 */
10155 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
10158 /* VEX_W_3A4C_P_2 */
10159 { "vpblendvb", { XM, Vex128, EXx, XMVexI4 } },
10162 /* VEX_W_3A60_P_2 */
10163 { "vpcmpestrm", { XM, EXx, Ib } },
10166 /* VEX_W_3A61_P_2 */
10167 { "vpcmpestri", { XM, EXx, Ib } },
10170 /* VEX_W_3A62_P_2 */
10171 { "vpcmpistrm", { XM, EXx, Ib } },
10174 /* VEX_W_3A63_P_2 */
10175 { "vpcmpistri", { XM, EXx, Ib } },
10178 /* VEX_W_3ADF_P_2 */
10179 { "vaeskeygenassist", { XM, EXx, Ib } },
10183 static const struct dis386 mod_table[][2] = {
10186 { "leaS", { Gv, M } },
10189 /* MOD_0F01_REG_0 */
10190 { X86_64_TABLE (X86_64_0F01_REG_0) },
10191 { RM_TABLE (RM_0F01_REG_0) },
10194 /* MOD_0F01_REG_1 */
10195 { X86_64_TABLE (X86_64_0F01_REG_1) },
10196 { RM_TABLE (RM_0F01_REG_1) },
10199 /* MOD_0F01_REG_2 */
10200 { X86_64_TABLE (X86_64_0F01_REG_2) },
10201 { RM_TABLE (RM_0F01_REG_2) },
10204 /* MOD_0F01_REG_3 */
10205 { X86_64_TABLE (X86_64_0F01_REG_3) },
10206 { RM_TABLE (RM_0F01_REG_3) },
10209 /* MOD_0F01_REG_7 */
10210 { "invlpg", { Mb } },
10211 { RM_TABLE (RM_0F01_REG_7) },
10214 /* MOD_0F12_PREFIX_0 */
10215 { "movlps", { XM, EXq } },
10216 { "movhlps", { XM, EXq } },
10220 { "movlpX", { EXq, XM } },
10223 /* MOD_0F16_PREFIX_0 */
10224 { "movhps", { XM, EXq } },
10225 { "movlhps", { XM, EXq } },
10229 { "movhpX", { EXq, XM } },
10232 /* MOD_0F18_REG_0 */
10233 { "prefetchnta", { Mb } },
10236 /* MOD_0F18_REG_1 */
10237 { "prefetcht0", { Mb } },
10240 /* MOD_0F18_REG_2 */
10241 { "prefetcht1", { Mb } },
10244 /* MOD_0F18_REG_3 */
10245 { "prefetcht2", { Mb } },
10250 { "movZ", { Rm, Cm } },
10255 { "movZ", { Rm, Dm } },
10260 { "movZ", { Cm, Rm } },
10265 { "movZ", { Dm, Rm } },
10270 { "movL", { Rd, Td } },
10275 { "movL", { Td, Rd } },
10278 /* MOD_0F2B_PREFIX_0 */
10279 {"movntps", { Mx, XM } },
10282 /* MOD_0F2B_PREFIX_1 */
10283 {"movntss", { Md, XM } },
10286 /* MOD_0F2B_PREFIX_2 */
10287 {"movntpd", { Mx, XM } },
10290 /* MOD_0F2B_PREFIX_3 */
10291 {"movntsd", { Mq, XM } },
10296 { "movmskpX", { Gdq, XS } },
10299 /* MOD_0F71_REG_2 */
10301 { "psrlw", { MS, Ib } },
10304 /* MOD_0F71_REG_4 */
10306 { "psraw", { MS, Ib } },
10309 /* MOD_0F71_REG_6 */
10311 { "psllw", { MS, Ib } },
10314 /* MOD_0F72_REG_2 */
10316 { "psrld", { MS, Ib } },
10319 /* MOD_0F72_REG_4 */
10321 { "psrad", { MS, Ib } },
10324 /* MOD_0F72_REG_6 */
10326 { "pslld", { MS, Ib } },
10329 /* MOD_0F73_REG_2 */
10331 { "psrlq", { MS, Ib } },
10334 /* MOD_0F73_REG_3 */
10336 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10339 /* MOD_0F73_REG_6 */
10341 { "psllq", { MS, Ib } },
10344 /* MOD_0F73_REG_7 */
10346 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10349 /* MOD_0FAE_REG_0 */
10350 { "fxsave", { FXSAVE } },
10353 /* MOD_0FAE_REG_1 */
10354 { "fxrstor", { FXSAVE } },
10357 /* MOD_0FAE_REG_2 */
10358 { "ldmxcsr", { Md } },
10361 /* MOD_0FAE_REG_3 */
10362 { "stmxcsr", { Md } },
10365 /* MOD_0FAE_REG_4 */
10366 { "xsave", { FXSAVE } },
10369 /* MOD_0FAE_REG_5 */
10370 { "xrstor", { FXSAVE } },
10371 { RM_TABLE (RM_0FAE_REG_5) },
10374 /* MOD_0FAE_REG_6 */
10376 { RM_TABLE (RM_0FAE_REG_6) },
10379 /* MOD_0FAE_REG_7 */
10380 { "clflush", { Mb } },
10381 { RM_TABLE (RM_0FAE_REG_7) },
10385 { "lssS", { Gv, Mp } },
10389 { "lfsS", { Gv, Mp } },
10393 { "lgsS", { Gv, Mp } },
10396 /* MOD_0FC7_REG_6 */
10397 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
10400 /* MOD_0FC7_REG_7 */
10401 { "vmptrst", { Mq } },
10406 { "pmovmskb", { Gdq, MS } },
10409 /* MOD_0FE7_PREFIX_2 */
10410 { "movntdq", { Mx, XM } },
10413 /* MOD_0FF0_PREFIX_3 */
10414 { "lddqu", { XM, M } },
10417 /* MOD_0F382A_PREFIX_2 */
10418 { "movntdqa", { XM, Mx } },
10422 { "bound{S|}", { Gv, Ma } },
10426 { "lesS", { Gv, Mp } },
10427 { VEX_C4_TABLE (VEX_0F) },
10431 { "ldsS", { Gv, Mp } },
10432 { VEX_C5_TABLE (VEX_0F) },
10435 /* MOD_VEX_12_PREFIX_0 */
10436 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
10437 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
10441 { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
10444 /* MOD_VEX_16_PREFIX_0 */
10445 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
10446 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
10450 { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
10454 { VEX_W_TABLE (VEX_W_2B_M_0) },
10459 { VEX_W_TABLE (VEX_W_50_M_0) },
10462 /* MOD_VEX_71_REG_2 */
10464 { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
10467 /* MOD_VEX_71_REG_4 */
10469 { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
10472 /* MOD_VEX_71_REG_6 */
10474 { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
10477 /* MOD_VEX_72_REG_2 */
10479 { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
10482 /* MOD_VEX_72_REG_4 */
10484 { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
10487 /* MOD_VEX_72_REG_6 */
10489 { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
10492 /* MOD_VEX_73_REG_2 */
10494 { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
10497 /* MOD_VEX_73_REG_3 */
10499 { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
10502 /* MOD_VEX_73_REG_6 */
10504 { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
10507 /* MOD_VEX_73_REG_7 */
10509 { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
10512 /* MOD_VEX_AE_REG_2 */
10513 { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
10516 /* MOD_VEX_AE_REG_3 */
10517 { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
10520 /* MOD_VEX_D7_PREFIX_2 */
10522 { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
10525 /* MOD_VEX_E7_PREFIX_2 */
10526 { VEX_W_TABLE (VEX_W_E7_P_2_M_0) },
10529 /* MOD_VEX_F0_PREFIX_3 */
10530 { VEX_W_TABLE (VEX_W_F0_P_3_M_0) },
10533 /* MOD_VEX_3818_PREFIX_2 */
10534 { VEX_W_TABLE (VEX_W_3818_P_2_M_0) },
10537 /* MOD_VEX_3819_PREFIX_2 */
10538 { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
10541 /* MOD_VEX_381A_PREFIX_2 */
10542 { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
10545 /* MOD_VEX_382A_PREFIX_2 */
10546 { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
10549 /* MOD_VEX_382C_PREFIX_2 */
10550 { VEX_W_TABLE (VEX_W_382C_P_2_M_0) },
10553 /* MOD_VEX_382D_PREFIX_2 */
10554 { VEX_W_TABLE (VEX_W_382D_P_2_M_0) },
10557 /* MOD_VEX_382E_PREFIX_2 */
10558 { VEX_W_TABLE (VEX_W_382E_P_2_M_0) },
10561 /* MOD_VEX_382F_PREFIX_2 */
10562 { VEX_W_TABLE (VEX_W_382F_P_2_M_0) },
10566 static const struct dis386 rm_table[][8] = {
10568 /* RM_0F01_REG_0 */
10570 { "vmcall", { Skip_MODRM } },
10571 { "vmlaunch", { Skip_MODRM } },
10572 { "vmresume", { Skip_MODRM } },
10573 { "vmxoff", { Skip_MODRM } },
10576 /* RM_0F01_REG_1 */
10577 { "monitor", { { OP_Monitor, 0 } } },
10578 { "mwait", { { OP_Mwait, 0 } } },
10581 /* RM_0F01_REG_2 */
10582 { "xgetbv", { Skip_MODRM } },
10583 { "xsetbv", { Skip_MODRM } },
10586 /* RM_0F01_REG_3 */
10587 { "vmrun", { Skip_MODRM } },
10588 { "vmmcall", { Skip_MODRM } },
10589 { "vmload", { Skip_MODRM } },
10590 { "vmsave", { Skip_MODRM } },
10591 { "stgi", { Skip_MODRM } },
10592 { "clgi", { Skip_MODRM } },
10593 { "skinit", { Skip_MODRM } },
10594 { "invlpga", { Skip_MODRM } },
10597 /* RM_0F01_REG_7 */
10598 { "swapgs", { Skip_MODRM } },
10599 { "rdtscp", { Skip_MODRM } },
10602 /* RM_0FAE_REG_5 */
10603 { "lfence", { Skip_MODRM } },
10606 /* RM_0FAE_REG_6 */
10607 { "mfence", { Skip_MODRM } },
10610 /* RM_0FAE_REG_7 */
10611 { "sfence", { Skip_MODRM } },
10615 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10617 /* We use the high bit to indicate different name for the same
10619 #define ADDR16_PREFIX (0x67 | 0x100)
10620 #define ADDR32_PREFIX (0x67 | 0x200)
10621 #define DATA16_PREFIX (0x66 | 0x100)
10622 #define DATA32_PREFIX (0x66 | 0x200)
10623 #define REP_PREFIX (0xf3 | 0x100)
10628 int newrex, i, length;
10634 last_lock_prefix = -1;
10635 last_repz_prefix = -1;
10636 last_repnz_prefix = -1;
10637 last_data_prefix = -1;
10638 last_addr_prefix = -1;
10639 last_rex_prefix = -1;
10640 last_seg_prefix = -1;
10641 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10642 all_prefixes[i] = 0;
10645 /* The maximum instruction length is 15bytes. */
10646 while (length < MAX_CODE_LENGTH - 1)
10648 FETCH_DATA (the_info, codep + 1);
10652 /* REX prefixes family. */
10669 if (address_mode == mode_64bit)
10673 last_rex_prefix = i;
10676 prefixes |= PREFIX_REPZ;
10677 last_repz_prefix = i;
10680 prefixes |= PREFIX_REPNZ;
10681 last_repnz_prefix = i;
10684 prefixes |= PREFIX_LOCK;
10685 last_lock_prefix = i;
10688 prefixes |= PREFIX_CS;
10689 last_seg_prefix = i;
10692 prefixes |= PREFIX_SS;
10693 last_seg_prefix = i;
10696 prefixes |= PREFIX_DS;
10697 last_seg_prefix = i;
10700 prefixes |= PREFIX_ES;
10701 last_seg_prefix = i;
10704 prefixes |= PREFIX_FS;
10705 last_seg_prefix = i;
10708 prefixes |= PREFIX_GS;
10709 last_seg_prefix = i;
10712 prefixes |= PREFIX_DATA;
10713 last_data_prefix = i;
10716 prefixes |= PREFIX_ADDR;
10717 last_addr_prefix = i;
10720 /* fwait is really an instruction. If there are prefixes
10721 before the fwait, they belong to the fwait, *not* to the
10722 following instruction. */
10723 if (prefixes || rex)
10725 prefixes |= PREFIX_FWAIT;
10729 prefixes = PREFIX_FWAIT;
10734 /* Rex is ignored when followed by another prefix. */
10740 if (*codep != FWAIT_OPCODE)
10741 all_prefixes[i++] = *codep;
10750 seg_prefix (int pref)
10771 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10774 static const char *
10775 prefix_name (int pref, int sizeflag)
10777 static const char *rexes [16] =
10780 "rex.B", /* 0x41 */
10781 "rex.X", /* 0x42 */
10782 "rex.XB", /* 0x43 */
10783 "rex.R", /* 0x44 */
10784 "rex.RB", /* 0x45 */
10785 "rex.RX", /* 0x46 */
10786 "rex.RXB", /* 0x47 */
10787 "rex.W", /* 0x48 */
10788 "rex.WB", /* 0x49 */
10789 "rex.WX", /* 0x4a */
10790 "rex.WXB", /* 0x4b */
10791 "rex.WR", /* 0x4c */
10792 "rex.WRB", /* 0x4d */
10793 "rex.WRX", /* 0x4e */
10794 "rex.WRXB", /* 0x4f */
10799 /* REX prefixes family. */
10816 return rexes [pref - 0x40];
10836 return (sizeflag & DFLAG) ? "data16" : "data32";
10838 if (address_mode == mode_64bit)
10839 return (sizeflag & AFLAG) ? "addr32" : "addr64";
10841 return (sizeflag & AFLAG) ? "addr16" : "addr32";
10844 case ADDR16_PREFIX:
10846 case ADDR32_PREFIX:
10848 case DATA16_PREFIX:
10850 case DATA32_PREFIX:
10859 static char op_out[MAX_OPERANDS][100];
10860 static int op_ad, op_index[MAX_OPERANDS];
10861 static int two_source_ops;
10862 static bfd_vma op_address[MAX_OPERANDS];
10863 static bfd_vma op_riprel[MAX_OPERANDS];
10864 static bfd_vma start_pc;
10867 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10868 * (see topic "Redundant prefixes" in the "Differences from 8086"
10869 * section of the "Virtual 8086 Mode" chapter.)
10870 * 'pc' should be the address of this instruction, it will
10871 * be used to print the target address if this is a relative jump or call
10872 * The function returns the length of this instruction in bytes.
10875 static char intel_syntax;
10876 static char intel_mnemonic = !SYSV386_COMPAT;
10877 static char open_char;
10878 static char close_char;
10879 static char separator_char;
10880 static char scale_char;
10882 /* Here for backwards compatibility. When gdb stops using
10883 print_insn_i386_att and print_insn_i386_intel these functions can
10884 disappear, and print_insn_i386 be merged into print_insn. */
10886 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10890 return print_insn (pc, info);
10894 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10898 return print_insn (pc, info);
10902 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10906 return print_insn (pc, info);
10910 print_i386_disassembler_options (FILE *stream)
10912 fprintf (stream, _("\n\
10913 The following i386/x86-64 specific disassembler options are supported for use\n\
10914 with the -M switch (multiple options should be separated by commas):\n"));
10916 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
10917 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
10918 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
10919 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
10920 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
10921 fprintf (stream, _(" att-mnemonic\n"
10922 " Display instruction in AT&T mnemonic\n"));
10923 fprintf (stream, _(" intel-mnemonic\n"
10924 " Display instruction in Intel mnemonic\n"));
10925 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
10926 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
10927 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
10928 fprintf (stream, _(" data32 Assume 32bit data size\n"));
10929 fprintf (stream, _(" data16 Assume 16bit data size\n"));
10930 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
10934 static const struct dis386 bad_opcode = { "(bad)", { XX } };
10936 /* Get a pointer to struct dis386 with a valid name. */
10938 static const struct dis386 *
10939 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
10941 int vindex, vex_table_index;
10943 if (dp->name != NULL)
10946 switch (dp->op[0].bytemode)
10948 case USE_REG_TABLE:
10949 dp = ®_table[dp->op[1].bytemode][modrm.reg];
10952 case USE_MOD_TABLE:
10953 vindex = modrm.mod == 0x3 ? 1 : 0;
10954 dp = &mod_table[dp->op[1].bytemode][vindex];
10958 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
10961 case USE_PREFIX_TABLE:
10964 /* The prefix in VEX is implicit. */
10965 switch (vex.prefix)
10970 case REPE_PREFIX_OPCODE:
10973 case DATA_PREFIX_OPCODE:
10976 case REPNE_PREFIX_OPCODE:
10987 used_prefixes |= (prefixes & PREFIX_REPZ);
10988 if (prefixes & PREFIX_REPZ)
10991 all_prefixes[last_repz_prefix] = 0;
10995 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
10997 used_prefixes |= (prefixes & PREFIX_REPNZ);
10998 if (prefixes & PREFIX_REPNZ)
11001 all_prefixes[last_repnz_prefix] = 0;
11005 used_prefixes |= (prefixes & PREFIX_DATA);
11006 if (prefixes & PREFIX_DATA)
11009 all_prefixes[last_data_prefix] = 0;
11014 dp = &prefix_table[dp->op[1].bytemode][vindex];
11017 case USE_X86_64_TABLE:
11018 vindex = address_mode == mode_64bit ? 1 : 0;
11019 dp = &x86_64_table[dp->op[1].bytemode][vindex];
11022 case USE_3BYTE_TABLE:
11023 FETCH_DATA (info, codep + 2);
11025 dp = &three_byte_table[dp->op[1].bytemode][vindex];
11026 modrm.mod = (*codep >> 6) & 3;
11027 modrm.reg = (*codep >> 3) & 7;
11028 modrm.rm = *codep & 7;
11031 case USE_VEX_LEN_TABLE:
11035 switch (vex.length)
11048 dp = &vex_len_table[dp->op[1].bytemode][vindex];
11051 case USE_XOP_8F_TABLE:
11052 FETCH_DATA (info, codep + 3);
11053 /* All bits in the REX prefix are ignored. */
11055 rex = ~(*codep >> 5) & 0x7;
11057 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11058 switch ((*codep & 0x1f))
11063 vex_table_index = XOP_08;
11066 vex_table_index = XOP_09;
11069 vex_table_index = XOP_0A;
11073 vex.w = *codep & 0x80;
11074 if (vex.w && address_mode == mode_64bit)
11077 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11078 if (address_mode != mode_64bit
11079 && vex.register_specifier > 0x7)
11082 vex.length = (*codep & 0x4) ? 256 : 128;
11083 switch ((*codep & 0x3))
11089 vex.prefix = DATA_PREFIX_OPCODE;
11092 vex.prefix = REPE_PREFIX_OPCODE;
11095 vex.prefix = REPNE_PREFIX_OPCODE;
11102 dp = &xop_table[vex_table_index][vindex];
11104 FETCH_DATA (info, codep + 1);
11105 modrm.mod = (*codep >> 6) & 3;
11106 modrm.reg = (*codep >> 3) & 7;
11107 modrm.rm = *codep & 7;
11110 case USE_VEX_C4_TABLE:
11111 FETCH_DATA (info, codep + 3);
11112 /* All bits in the REX prefix are ignored. */
11114 rex = ~(*codep >> 5) & 0x7;
11115 switch ((*codep & 0x1f))
11120 vex_table_index = VEX_0F;
11123 vex_table_index = VEX_0F38;
11126 vex_table_index = VEX_0F3A;
11130 vex.w = *codep & 0x80;
11131 if (vex.w && address_mode == mode_64bit)
11134 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11135 if (address_mode != mode_64bit
11136 && vex.register_specifier > 0x7)
11139 vex.length = (*codep & 0x4) ? 256 : 128;
11140 switch ((*codep & 0x3))
11146 vex.prefix = DATA_PREFIX_OPCODE;
11149 vex.prefix = REPE_PREFIX_OPCODE;
11152 vex.prefix = REPNE_PREFIX_OPCODE;
11159 dp = &vex_table[vex_table_index][vindex];
11160 /* There is no MODRM byte for VEX [82|77]. */
11161 if (vindex != 0x77 && vindex != 0x82)
11163 FETCH_DATA (info, codep + 1);
11164 modrm.mod = (*codep >> 6) & 3;
11165 modrm.reg = (*codep >> 3) & 7;
11166 modrm.rm = *codep & 7;
11170 case USE_VEX_C5_TABLE:
11171 FETCH_DATA (info, codep + 2);
11172 /* All bits in the REX prefix are ignored. */
11174 rex = (*codep & 0x80) ? 0 : REX_R;
11176 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11177 if (address_mode != mode_64bit
11178 && vex.register_specifier > 0x7)
11183 vex.length = (*codep & 0x4) ? 256 : 128;
11184 switch ((*codep & 0x3))
11190 vex.prefix = DATA_PREFIX_OPCODE;
11193 vex.prefix = REPE_PREFIX_OPCODE;
11196 vex.prefix = REPNE_PREFIX_OPCODE;
11203 dp = &vex_table[dp->op[1].bytemode][vindex];
11204 /* There is no MODRM byte for VEX [82|77]. */
11205 if (vindex != 0x77 && vindex != 0x82)
11207 FETCH_DATA (info, codep + 1);
11208 modrm.mod = (*codep >> 6) & 3;
11209 modrm.reg = (*codep >> 3) & 7;
11210 modrm.rm = *codep & 7;
11214 case USE_VEX_W_TABLE:
11218 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11229 if (dp->name != NULL)
11232 return get_valid_dis386 (dp, info);
11236 print_insn (bfd_vma pc, disassemble_info *info)
11238 const struct dis386 *dp;
11240 char *op_txt[MAX_OPERANDS];
11244 struct dis_private priv;
11247 int default_prefixes;
11249 if (info->mach == bfd_mach_x86_64_intel_syntax
11250 || info->mach == bfd_mach_x86_64
11251 || info->mach == bfd_mach_l1om
11252 || info->mach == bfd_mach_l1om_intel_syntax)
11253 address_mode = mode_64bit;
11255 address_mode = mode_32bit;
11257 if (intel_syntax == (char) -1)
11258 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
11259 || info->mach == bfd_mach_x86_64_intel_syntax
11260 || info->mach == bfd_mach_l1om_intel_syntax);
11262 if (info->mach == bfd_mach_i386_i386
11263 || info->mach == bfd_mach_x86_64
11264 || info->mach == bfd_mach_l1om
11265 || info->mach == bfd_mach_i386_i386_intel_syntax
11266 || info->mach == bfd_mach_x86_64_intel_syntax
11267 || info->mach == bfd_mach_l1om_intel_syntax)
11268 priv.orig_sizeflag = AFLAG | DFLAG;
11269 else if (info->mach == bfd_mach_i386_i8086)
11270 priv.orig_sizeflag = 0;
11274 for (p = info->disassembler_options; p != NULL; )
11276 if (CONST_STRNEQ (p, "x86-64"))
11278 address_mode = mode_64bit;
11279 priv.orig_sizeflag = AFLAG | DFLAG;
11281 else if (CONST_STRNEQ (p, "i386"))
11283 address_mode = mode_32bit;
11284 priv.orig_sizeflag = AFLAG | DFLAG;
11286 else if (CONST_STRNEQ (p, "i8086"))
11288 address_mode = mode_16bit;
11289 priv.orig_sizeflag = 0;
11291 else if (CONST_STRNEQ (p, "intel"))
11294 if (CONST_STRNEQ (p + 5, "-mnemonic"))
11295 intel_mnemonic = 1;
11297 else if (CONST_STRNEQ (p, "att"))
11300 if (CONST_STRNEQ (p + 3, "-mnemonic"))
11301 intel_mnemonic = 0;
11303 else if (CONST_STRNEQ (p, "addr"))
11305 if (address_mode == mode_64bit)
11307 if (p[4] == '3' && p[5] == '2')
11308 priv.orig_sizeflag &= ~AFLAG;
11309 else if (p[4] == '6' && p[5] == '4')
11310 priv.orig_sizeflag |= AFLAG;
11314 if (p[4] == '1' && p[5] == '6')
11315 priv.orig_sizeflag &= ~AFLAG;
11316 else if (p[4] == '3' && p[5] == '2')
11317 priv.orig_sizeflag |= AFLAG;
11320 else if (CONST_STRNEQ (p, "data"))
11322 if (p[4] == '1' && p[5] == '6')
11323 priv.orig_sizeflag &= ~DFLAG;
11324 else if (p[4] == '3' && p[5] == '2')
11325 priv.orig_sizeflag |= DFLAG;
11327 else if (CONST_STRNEQ (p, "suffix"))
11328 priv.orig_sizeflag |= SUFFIX_ALWAYS;
11330 p = strchr (p, ',');
11337 names64 = intel_names64;
11338 names32 = intel_names32;
11339 names16 = intel_names16;
11340 names8 = intel_names8;
11341 names8rex = intel_names8rex;
11342 names_seg = intel_names_seg;
11343 names_mm = intel_names_mm;
11344 names_xmm = intel_names_xmm;
11345 names_ymm = intel_names_ymm;
11346 index64 = intel_index64;
11347 index32 = intel_index32;
11348 index16 = intel_index16;
11351 separator_char = '+';
11356 names64 = att_names64;
11357 names32 = att_names32;
11358 names16 = att_names16;
11359 names8 = att_names8;
11360 names8rex = att_names8rex;
11361 names_seg = att_names_seg;
11362 names_mm = att_names_mm;
11363 names_xmm = att_names_xmm;
11364 names_ymm = att_names_ymm;
11365 index64 = att_index64;
11366 index32 = att_index32;
11367 index16 = att_index16;
11370 separator_char = ',';
11374 /* The output looks better if we put 7 bytes on a line, since that
11375 puts most long word instructions on a single line. Use 8 bytes
11377 if (info->mach == bfd_mach_l1om
11378 || info->mach == bfd_mach_l1om_intel_syntax)
11379 info->bytes_per_line = 8;
11381 info->bytes_per_line = 7;
11383 info->private_data = &priv;
11384 priv.max_fetched = priv.the_buffer;
11385 priv.insn_start = pc;
11388 for (i = 0; i < MAX_OPERANDS; ++i)
11396 start_codep = priv.the_buffer;
11397 codep = priv.the_buffer;
11399 if (setjmp (priv.bailout) != 0)
11403 /* Getting here means we tried for data but didn't get it. That
11404 means we have an incomplete instruction of some sort. Just
11405 print the first byte as a prefix or a .byte pseudo-op. */
11406 if (codep > priv.the_buffer)
11408 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11410 (*info->fprintf_func) (info->stream, "%s", name);
11413 /* Just print the first byte as a .byte instruction. */
11414 (*info->fprintf_func) (info->stream, ".byte 0x%x",
11415 (unsigned int) priv.the_buffer[0]);
11425 sizeflag = priv.orig_sizeflag;
11427 if (!ckprefix () || rex_used)
11429 /* Too many prefixes or unused REX prefixes. */
11431 all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes);
11433 (*info->fprintf_func) (info->stream, "%s",
11434 prefix_name (all_prefixes[i], sizeflag));
11438 insn_codep = codep;
11440 FETCH_DATA (info, codep + 1);
11441 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11443 if (((prefixes & PREFIX_FWAIT)
11444 && ((*codep < 0xd8) || (*codep > 0xdf))))
11446 (*info->fprintf_func) (info->stream, "fwait");
11452 if (*codep == 0x0f)
11454 unsigned char threebyte;
11455 FETCH_DATA (info, codep + 2);
11456 threebyte = *++codep;
11457 dp = &dis386_twobyte[threebyte];
11458 need_modrm = twobyte_has_modrm[*codep];
11463 dp = &dis386[*codep];
11464 need_modrm = onebyte_has_modrm[*codep];
11468 if ((prefixes & PREFIX_REPZ))
11469 used_prefixes |= PREFIX_REPZ;
11470 if ((prefixes & PREFIX_REPNZ))
11471 used_prefixes |= PREFIX_REPNZ;
11472 if ((prefixes & PREFIX_LOCK))
11473 used_prefixes |= PREFIX_LOCK;
11475 default_prefixes = 0;
11476 if (prefixes & PREFIX_ADDR)
11479 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
11481 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11482 all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
11484 all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
11485 default_prefixes |= PREFIX_ADDR;
11489 if ((prefixes & PREFIX_DATA))
11492 if (dp->op[2].bytemode == cond_jump_mode
11493 && dp->op[0].bytemode == v_mode
11496 if (sizeflag & DFLAG)
11497 all_prefixes[last_data_prefix] = DATA32_PREFIX;
11499 all_prefixes[last_data_prefix] = DATA16_PREFIX;
11500 default_prefixes |= PREFIX_DATA;
11502 else if (rex & REX_W)
11504 /* REX_W will override PREFIX_DATA. */
11505 default_prefixes |= PREFIX_DATA;
11511 FETCH_DATA (info, codep + 1);
11512 modrm.mod = (*codep >> 6) & 3;
11513 modrm.reg = (*codep >> 3) & 7;
11514 modrm.rm = *codep & 7;
11521 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11523 dofloat (sizeflag);
11527 dp = get_valid_dis386 (dp, info);
11528 if (dp != NULL && putop (dp->name, sizeflag) == 0)
11530 for (i = 0; i < MAX_OPERANDS; ++i)
11533 op_ad = MAX_OPERANDS - 1 - i;
11535 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
11540 /* See if any prefixes were not used. If so, print the first one
11541 separately. If we don't do this, we'll wind up printing an
11542 instruction stream which does not precisely correspond to the
11543 bytes we are disassembling. */
11544 if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
11546 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11547 if (all_prefixes[i])
11550 name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
11552 name = INTERNAL_DISASSEMBLER_ERROR;
11553 (*info->fprintf_func) (info->stream, "%s", name);
11558 /* Check if the REX prefix is used. */
11559 if (rex_ignored == 0 && (rex ^ rex_used) == 0)
11560 all_prefixes[last_rex_prefix] = 0;
11562 /* Check if the SEG prefix is used. */
11563 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
11564 | PREFIX_FS | PREFIX_GS)) != 0
11566 & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
11567 all_prefixes[last_seg_prefix] = 0;
11569 /* Check if the ADDR prefix is used. */
11570 if ((prefixes & PREFIX_ADDR) != 0
11571 && (used_prefixes & PREFIX_ADDR) != 0)
11572 all_prefixes[last_addr_prefix] = 0;
11574 /* Check if the DATA prefix is used. */
11575 if ((prefixes & PREFIX_DATA) != 0
11576 && (used_prefixes & PREFIX_DATA) != 0)
11577 all_prefixes[last_data_prefix] = 0;
11580 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11581 if (all_prefixes[i])
11584 name = prefix_name (all_prefixes[i], sizeflag);
11587 prefix_length += strlen (name) + 1;
11588 (*info->fprintf_func) (info->stream, "%s ", name);
11591 /* Check maximum code length. */
11592 if ((codep - start_codep) > MAX_CODE_LENGTH)
11594 (*info->fprintf_func) (info->stream, "(bad)");
11595 return MAX_CODE_LENGTH;
11598 obufp = mnemonicendp;
11599 for (i = strlen (obuf) + prefix_length; i < 6; i++)
11602 (*info->fprintf_func) (info->stream, "%s", obuf);
11604 /* The enter and bound instructions are printed with operands in the same
11605 order as the intel book; everything else is printed in reverse order. */
11606 if (intel_syntax || two_source_ops)
11610 for (i = 0; i < MAX_OPERANDS; ++i)
11611 op_txt[i] = op_out[i];
11613 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
11615 op_ad = op_index[i];
11616 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
11617 op_index[MAX_OPERANDS - 1 - i] = op_ad;
11618 riprel = op_riprel[i];
11619 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
11620 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
11625 for (i = 0; i < MAX_OPERANDS; ++i)
11626 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
11630 for (i = 0; i < MAX_OPERANDS; ++i)
11634 (*info->fprintf_func) (info->stream, ",");
11635 if (op_index[i] != -1 && !op_riprel[i])
11636 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
11638 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
11642 for (i = 0; i < MAX_OPERANDS; i++)
11643 if (op_index[i] != -1 && op_riprel[i])
11645 (*info->fprintf_func) (info->stream, " # ");
11646 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
11647 + op_address[op_index[i]]), info);
11650 return codep - priv.the_buffer;
11653 static const char *float_mem[] = {
11728 static const unsigned char float_mem_mode[] = {
11803 #define ST { OP_ST, 0 }
11804 #define STi { OP_STi, 0 }
11806 #define FGRPd9_2 NULL, { { NULL, 0 } }
11807 #define FGRPd9_4 NULL, { { NULL, 1 } }
11808 #define FGRPd9_5 NULL, { { NULL, 2 } }
11809 #define FGRPd9_6 NULL, { { NULL, 3 } }
11810 #define FGRPd9_7 NULL, { { NULL, 4 } }
11811 #define FGRPda_5 NULL, { { NULL, 5 } }
11812 #define FGRPdb_4 NULL, { { NULL, 6 } }
11813 #define FGRPde_3 NULL, { { NULL, 7 } }
11814 #define FGRPdf_4 NULL, { { NULL, 8 } }
11816 static const struct dis386 float_reg[][8] = {
11819 { "fadd", { ST, STi } },
11820 { "fmul", { ST, STi } },
11821 { "fcom", { STi } },
11822 { "fcomp", { STi } },
11823 { "fsub", { ST, STi } },
11824 { "fsubr", { ST, STi } },
11825 { "fdiv", { ST, STi } },
11826 { "fdivr", { ST, STi } },
11830 { "fld", { STi } },
11831 { "fxch", { STi } },
11841 { "fcmovb", { ST, STi } },
11842 { "fcmove", { ST, STi } },
11843 { "fcmovbe",{ ST, STi } },
11844 { "fcmovu", { ST, STi } },
11852 { "fcmovnb",{ ST, STi } },
11853 { "fcmovne",{ ST, STi } },
11854 { "fcmovnbe",{ ST, STi } },
11855 { "fcmovnu",{ ST, STi } },
11857 { "fucomi", { ST, STi } },
11858 { "fcomi", { ST, STi } },
11863 { "fadd", { STi, ST } },
11864 { "fmul", { STi, ST } },
11867 { "fsub!M", { STi, ST } },
11868 { "fsubM", { STi, ST } },
11869 { "fdiv!M", { STi, ST } },
11870 { "fdivM", { STi, ST } },
11874 { "ffree", { STi } },
11876 { "fst", { STi } },
11877 { "fstp", { STi } },
11878 { "fucom", { STi } },
11879 { "fucomp", { STi } },
11885 { "faddp", { STi, ST } },
11886 { "fmulp", { STi, ST } },
11889 { "fsub!Mp", { STi, ST } },
11890 { "fsubMp", { STi, ST } },
11891 { "fdiv!Mp", { STi, ST } },
11892 { "fdivMp", { STi, ST } },
11896 { "ffreep", { STi } },
11901 { "fucomip", { ST, STi } },
11902 { "fcomip", { ST, STi } },
11907 static char *fgrps[][8] = {
11910 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11915 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
11920 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
11925 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
11930 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
11935 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11940 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
11941 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
11946 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11951 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11956 swap_operand (void)
11958 mnemonicendp[0] = '.';
11959 mnemonicendp[1] = 's';
11964 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
11965 int sizeflag ATTRIBUTE_UNUSED)
11967 /* Skip mod/rm byte. */
11973 dofloat (int sizeflag)
11975 const struct dis386 *dp;
11976 unsigned char floatop;
11978 floatop = codep[-1];
11980 if (modrm.mod != 3)
11982 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
11984 putop (float_mem[fp_indx], sizeflag);
11987 OP_E (float_mem_mode[fp_indx], sizeflag);
11990 /* Skip mod/rm byte. */
11994 dp = &float_reg[floatop - 0xd8][modrm.reg];
11995 if (dp->name == NULL)
11997 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
11999 /* Instruction fnstsw is only one with strange arg. */
12000 if (floatop == 0xdf && codep[-1] == 0xe0)
12001 strcpy (op_out[0], names16[0]);
12005 putop (dp->name, sizeflag);
12010 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12015 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12020 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12022 oappend ("%st" + intel_syntax);
12026 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12028 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12029 oappend (scratchbuf + intel_syntax);
12032 /* Capital letters in template are macros. */
12034 putop (const char *in_template, int sizeflag)
12039 unsigned int l = 0, len = 1;
12042 #define SAVE_LAST(c) \
12043 if (l < len && l < sizeof (last)) \
12048 for (p = in_template; *p; p++)
12065 while (*++p != '|')
12066 if (*p == '}' || *p == '\0')
12069 /* Fall through. */
12074 while (*++p != '}')
12085 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12089 if (l == 0 && len == 1)
12094 if (sizeflag & SUFFIX_ALWAYS)
12107 if (address_mode == mode_64bit
12108 && !(prefixes & PREFIX_ADDR))
12119 if (intel_syntax && !alt)
12121 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12123 if (sizeflag & DFLAG)
12124 *obufp++ = intel_syntax ? 'd' : 'l';
12126 *obufp++ = intel_syntax ? 'w' : 's';
12127 used_prefixes |= (prefixes & PREFIX_DATA);
12131 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12134 if (modrm.mod == 3)
12140 if (sizeflag & DFLAG)
12141 *obufp++ = intel_syntax ? 'd' : 'l';
12144 used_prefixes |= (prefixes & PREFIX_DATA);
12150 case 'E': /* For jcxz/jecxz */
12151 if (address_mode == mode_64bit)
12153 if (sizeflag & AFLAG)
12159 if (sizeflag & AFLAG)
12161 used_prefixes |= (prefixes & PREFIX_ADDR);
12166 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12168 if (sizeflag & AFLAG)
12169 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12171 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12172 used_prefixes |= (prefixes & PREFIX_ADDR);
12176 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12178 if ((rex & REX_W) || (sizeflag & DFLAG))
12182 if (!(rex & REX_W))
12183 used_prefixes |= (prefixes & PREFIX_DATA);
12188 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12189 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12191 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12194 if (prefixes & PREFIX_DS)
12215 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12220 /* Fall through. */
12223 if (l != 0 || len != 1)
12231 if (sizeflag & SUFFIX_ALWAYS)
12235 if (intel_mnemonic != cond)
12239 if ((prefixes & PREFIX_FWAIT) == 0)
12242 used_prefixes |= PREFIX_FWAIT;
12248 else if (intel_syntax && (sizeflag & DFLAG))
12252 if (!(rex & REX_W))
12253 used_prefixes |= (prefixes & PREFIX_DATA);
12258 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12263 /* Fall through. */
12267 if ((prefixes & PREFIX_DATA)
12269 || (sizeflag & SUFFIX_ALWAYS))
12276 if (sizeflag & DFLAG)
12280 used_prefixes |= (prefixes & PREFIX_DATA);
12287 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12289 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12293 /* Fall through. */
12296 if (l == 0 && len == 1)
12299 if (intel_syntax && !alt)
12302 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12308 if (sizeflag & DFLAG)
12309 *obufp++ = intel_syntax ? 'd' : 'l';
12312 used_prefixes |= (prefixes & PREFIX_DATA);
12318 if (l != 1 || len != 2 || last[0] != 'L')
12324 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12339 else if (sizeflag & DFLAG)
12348 if (intel_syntax && !p[1]
12349 && ((rex & REX_W) || (sizeflag & DFLAG)))
12351 if (!(rex & REX_W))
12352 used_prefixes |= (prefixes & PREFIX_DATA);
12355 if (l == 0 && len == 1)
12359 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12361 if (sizeflag & SUFFIX_ALWAYS)
12383 /* Fall through. */
12386 if (l == 0 && len == 1)
12391 if (sizeflag & SUFFIX_ALWAYS)
12397 if (sizeflag & DFLAG)
12401 used_prefixes |= (prefixes & PREFIX_DATA);
12415 if (address_mode == mode_64bit
12416 && !(prefixes & PREFIX_ADDR))
12427 if (l != 0 || len != 1)
12432 if (need_vex && vex.prefix)
12434 if (vex.prefix == DATA_PREFIX_OPCODE)
12441 if (prefixes & PREFIX_DATA)
12445 used_prefixes |= (prefixes & PREFIX_DATA);
12449 if (l == 0 && len == 1)
12451 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12462 if (l != 1 || len != 2 || last[0] != 'X')
12470 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12472 switch (vex.length)
12486 if (l == 0 && len == 1)
12488 /* operand size flag for cwtl, cbtw */
12497 else if (sizeflag & DFLAG)
12501 if (!(rex & REX_W))
12502 used_prefixes |= (prefixes & PREFIX_DATA);
12506 if (l != 1 || len != 2 || last[0] != 'X')
12513 *obufp++ = vex.w ? 'd': 's';
12520 mnemonicendp = obufp;
12525 oappend (const char *s)
12527 obufp = stpcpy (obufp, s);
12533 if (prefixes & PREFIX_CS)
12535 used_prefixes |= PREFIX_CS;
12536 oappend ("%cs:" + intel_syntax);
12538 if (prefixes & PREFIX_DS)
12540 used_prefixes |= PREFIX_DS;
12541 oappend ("%ds:" + intel_syntax);
12543 if (prefixes & PREFIX_SS)
12545 used_prefixes |= PREFIX_SS;
12546 oappend ("%ss:" + intel_syntax);
12548 if (prefixes & PREFIX_ES)
12550 used_prefixes |= PREFIX_ES;
12551 oappend ("%es:" + intel_syntax);
12553 if (prefixes & PREFIX_FS)
12555 used_prefixes |= PREFIX_FS;
12556 oappend ("%fs:" + intel_syntax);
12558 if (prefixes & PREFIX_GS)
12560 used_prefixes |= PREFIX_GS;
12561 oappend ("%gs:" + intel_syntax);
12566 OP_indirE (int bytemode, int sizeflag)
12570 OP_E (bytemode, sizeflag);
12574 print_operand_value (char *buf, int hex, bfd_vma disp)
12576 if (address_mode == mode_64bit)
12584 sprintf_vma (tmp, disp);
12585 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
12586 strcpy (buf + 2, tmp + i);
12590 bfd_signed_vma v = disp;
12597 /* Check for possible overflow on 0x8000000000000000. */
12600 strcpy (buf, "9223372036854775808");
12614 tmp[28 - i] = (v % 10) + '0';
12618 strcpy (buf, tmp + 29 - i);
12624 sprintf (buf, "0x%x", (unsigned int) disp);
12626 sprintf (buf, "%d", (int) disp);
12630 /* Put DISP in BUF as signed hex number. */
12633 print_displacement (char *buf, bfd_vma disp)
12635 bfd_signed_vma val = disp;
12644 /* Check for possible overflow. */
12647 switch (address_mode)
12650 strcpy (buf + j, "0x8000000000000000");
12653 strcpy (buf + j, "0x80000000");
12656 strcpy (buf + j, "0x8000");
12666 sprintf_vma (tmp, (bfd_vma) val);
12667 for (i = 0; tmp[i] == '0'; i++)
12669 if (tmp[i] == '\0')
12671 strcpy (buf + j, tmp + i);
12675 intel_operand_size (int bytemode, int sizeflag)
12682 oappend ("BYTE PTR ");
12686 oappend ("WORD PTR ");
12689 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12691 oappend ("QWORD PTR ");
12700 oappend ("QWORD PTR ");
12703 if ((sizeflag & DFLAG) || bytemode == dq_mode)
12704 oappend ("DWORD PTR ");
12706 oappend ("WORD PTR ");
12707 used_prefixes |= (prefixes & PREFIX_DATA);
12711 if ((rex & REX_W) || (sizeflag & DFLAG))
12713 oappend ("WORD PTR ");
12714 if (!(rex & REX_W))
12715 used_prefixes |= (prefixes & PREFIX_DATA);
12718 if (sizeflag & DFLAG)
12719 oappend ("QWORD PTR ");
12721 oappend ("DWORD PTR ");
12722 used_prefixes |= (prefixes & PREFIX_DATA);
12725 case d_scalar_mode:
12726 case d_scalar_swap_mode:
12729 oappend ("DWORD PTR ");
12732 case q_scalar_mode:
12733 case q_scalar_swap_mode:
12735 oappend ("QWORD PTR ");
12738 if (address_mode == mode_64bit)
12739 oappend ("QWORD PTR ");
12741 oappend ("DWORD PTR ");
12744 if (sizeflag & DFLAG)
12745 oappend ("FWORD PTR ");
12747 oappend ("DWORD PTR ");
12748 used_prefixes |= (prefixes & PREFIX_DATA);
12751 oappend ("TBYTE PTR ");
12757 switch (vex.length)
12760 oappend ("XMMWORD PTR ");
12763 oappend ("YMMWORD PTR ");
12770 oappend ("XMMWORD PTR ");
12773 oappend ("XMMWORD PTR ");
12779 switch (vex.length)
12782 oappend ("QWORD PTR ");
12785 oappend ("XMMWORD PTR ");
12795 switch (vex.length)
12798 oappend ("QWORD PTR ");
12801 oappend ("YMMWORD PTR ");
12808 oappend ("OWORD PTR ");
12810 case vex_w_dq_mode:
12811 case vex_scalar_w_dq_mode:
12816 oappend ("QWORD PTR ");
12818 oappend ("DWORD PTR ");
12826 OP_E_register (int bytemode, int sizeflag)
12828 int reg = modrm.rm;
12829 const char **names;
12835 if ((sizeflag & SUFFIX_ALWAYS)
12836 && (bytemode == b_swap_mode || bytemode == v_swap_mode))
12859 names = address_mode == mode_64bit ? names64 : names32;
12862 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12880 if ((sizeflag & DFLAG)
12881 || (bytemode != v_mode
12882 && bytemode != v_swap_mode))
12886 used_prefixes |= (prefixes & PREFIX_DATA);
12892 oappend (INTERNAL_DISASSEMBLER_ERROR);
12895 oappend (names[reg]);
12899 OP_E_memory (int bytemode, int sizeflag)
12902 int add = (rex & REX_B) ? 8 : 0;
12907 intel_operand_size (bytemode, sizeflag);
12910 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12912 /* 32/64 bit address mode */
12930 FETCH_DATA (the_info, codep + 1);
12931 vindex = (*codep >> 3) & 7;
12932 scale = (*codep >> 6) & 3;
12937 haveindex = vindex != 4;
12940 rbase = base + add;
12948 if (address_mode == mode_64bit && !havesib)
12954 FETCH_DATA (the_info, codep + 1);
12956 if ((disp & 0x80) != 0)
12964 /* In 32bit mode, we need index register to tell [offset] from
12965 [eiz*1 + offset]. */
12966 needindex = (havesib
12969 && address_mode == mode_32bit);
12970 havedisp = (havebase
12972 || (havesib && (haveindex || scale != 0)));
12975 if (modrm.mod != 0 || base == 5)
12977 if (havedisp || riprel)
12978 print_displacement (scratchbuf, disp);
12980 print_operand_value (scratchbuf, 1, disp);
12981 oappend (scratchbuf);
12985 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
12989 if (havebase || haveindex || riprel)
12990 used_prefixes |= PREFIX_ADDR;
12992 if (havedisp || (intel_syntax && riprel))
12994 *obufp++ = open_char;
12995 if (intel_syntax && riprel)
12998 oappend (sizeflag & AFLAG ? "rip" : "eip");
13002 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
13003 ? names64[rbase] : names32[rbase]);
13006 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
13007 print index to tell base + index from base. */
13011 || (havebase && base != ESP_REG_NUM))
13013 if (!intel_syntax || havebase)
13015 *obufp++ = separator_char;
13019 oappend (address_mode == mode_64bit
13020 && (sizeflag & AFLAG)
13021 ? names64[vindex] : names32[vindex]);
13023 oappend (address_mode == mode_64bit
13024 && (sizeflag & AFLAG)
13025 ? index64 : index32);
13027 *obufp++ = scale_char;
13029 sprintf (scratchbuf, "%d", 1 << scale);
13030 oappend (scratchbuf);
13034 && (disp || modrm.mod != 0 || base == 5))
13036 if (!havedisp || (bfd_signed_vma) disp >= 0)
13041 else if (modrm.mod != 1 && disp != -disp)
13045 disp = - (bfd_signed_vma) disp;
13049 print_displacement (scratchbuf, disp);
13051 print_operand_value (scratchbuf, 1, disp);
13052 oappend (scratchbuf);
13055 *obufp++ = close_char;
13058 else if (intel_syntax)
13060 if (modrm.mod != 0 || base == 5)
13062 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13063 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13067 oappend (names_seg[ds_reg - es_reg]);
13070 print_operand_value (scratchbuf, 1, disp);
13071 oappend (scratchbuf);
13077 /* 16 bit address mode */
13078 used_prefixes |= prefixes & PREFIX_ADDR;
13085 if ((disp & 0x8000) != 0)
13090 FETCH_DATA (the_info, codep + 1);
13092 if ((disp & 0x80) != 0)
13097 if ((disp & 0x8000) != 0)
13103 if (modrm.mod != 0 || modrm.rm == 6)
13105 print_displacement (scratchbuf, disp);
13106 oappend (scratchbuf);
13109 if (modrm.mod != 0 || modrm.rm != 6)
13111 *obufp++ = open_char;
13113 oappend (index16[modrm.rm]);
13115 && (disp || modrm.mod != 0 || modrm.rm == 6))
13117 if ((bfd_signed_vma) disp >= 0)
13122 else if (modrm.mod != 1)
13126 disp = - (bfd_signed_vma) disp;
13129 print_displacement (scratchbuf, disp);
13130 oappend (scratchbuf);
13133 *obufp++ = close_char;
13136 else if (intel_syntax)
13138 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13139 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13143 oappend (names_seg[ds_reg - es_reg]);
13146 print_operand_value (scratchbuf, 1, disp & 0xffff);
13147 oappend (scratchbuf);
13153 OP_E (int bytemode, int sizeflag)
13155 /* Skip mod/rm byte. */
13159 if (modrm.mod == 3)
13160 OP_E_register (bytemode, sizeflag);
13162 OP_E_memory (bytemode, sizeflag);
13166 OP_G (int bytemode, int sizeflag)
13177 oappend (names8rex[modrm.reg + add]);
13179 oappend (names8[modrm.reg + add]);
13182 oappend (names16[modrm.reg + add]);
13185 oappend (names32[modrm.reg + add]);
13188 oappend (names64[modrm.reg + add]);
13197 oappend (names64[modrm.reg + add]);
13200 if ((sizeflag & DFLAG) || bytemode != v_mode)
13201 oappend (names32[modrm.reg + add]);
13203 oappend (names16[modrm.reg + add]);
13204 used_prefixes |= (prefixes & PREFIX_DATA);
13208 if (address_mode == mode_64bit)
13209 oappend (names64[modrm.reg + add]);
13211 oappend (names32[modrm.reg + add]);
13214 oappend (INTERNAL_DISASSEMBLER_ERROR);
13227 FETCH_DATA (the_info, codep + 8);
13228 a = *codep++ & 0xff;
13229 a |= (*codep++ & 0xff) << 8;
13230 a |= (*codep++ & 0xff) << 16;
13231 a |= (*codep++ & 0xff) << 24;
13232 b = *codep++ & 0xff;
13233 b |= (*codep++ & 0xff) << 8;
13234 b |= (*codep++ & 0xff) << 16;
13235 b |= (*codep++ & 0xff) << 24;
13236 x = a + ((bfd_vma) b << 32);
13244 static bfd_signed_vma
13247 bfd_signed_vma x = 0;
13249 FETCH_DATA (the_info, codep + 4);
13250 x = *codep++ & (bfd_signed_vma) 0xff;
13251 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13252 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13253 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13257 static bfd_signed_vma
13260 bfd_signed_vma x = 0;
13262 FETCH_DATA (the_info, codep + 4);
13263 x = *codep++ & (bfd_signed_vma) 0xff;
13264 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13265 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13266 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13268 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
13278 FETCH_DATA (the_info, codep + 2);
13279 x = *codep++ & 0xff;
13280 x |= (*codep++ & 0xff) << 8;
13285 set_op (bfd_vma op, int riprel)
13287 op_index[op_ad] = op_ad;
13288 if (address_mode == mode_64bit)
13290 op_address[op_ad] = op;
13291 op_riprel[op_ad] = riprel;
13295 /* Mask to get a 32-bit address. */
13296 op_address[op_ad] = op & 0xffffffff;
13297 op_riprel[op_ad] = riprel & 0xffffffff;
13302 OP_REG (int code, int sizeflag)
13314 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13315 case sp_reg: case bp_reg: case si_reg: case di_reg:
13316 s = names16[code - ax_reg + add];
13318 case es_reg: case ss_reg: case cs_reg:
13319 case ds_reg: case fs_reg: case gs_reg:
13320 s = names_seg[code - es_reg + add];
13322 case al_reg: case ah_reg: case cl_reg: case ch_reg:
13323 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13326 s = names8rex[code - al_reg + add];
13328 s = names8[code - al_reg];
13330 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
13331 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
13332 if (address_mode == mode_64bit && (sizeflag & DFLAG))
13334 s = names64[code - rAX_reg + add];
13337 code += eAX_reg - rAX_reg;
13338 /* Fall through. */
13339 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13340 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13343 s = names64[code - eAX_reg + add];
13346 if (sizeflag & DFLAG)
13347 s = names32[code - eAX_reg + add];
13349 s = names16[code - eAX_reg + add];
13350 used_prefixes |= (prefixes & PREFIX_DATA);
13354 s = INTERNAL_DISASSEMBLER_ERROR;
13361 OP_IMREG (int code, int sizeflag)
13373 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13374 case sp_reg: case bp_reg: case si_reg: case di_reg:
13375 s = names16[code - ax_reg];
13377 case es_reg: case ss_reg: case cs_reg:
13378 case ds_reg: case fs_reg: case gs_reg:
13379 s = names_seg[code - es_reg];
13381 case al_reg: case ah_reg: case cl_reg: case ch_reg:
13382 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13385 s = names8rex[code - al_reg];
13387 s = names8[code - al_reg];
13389 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13390 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13393 s = names64[code - eAX_reg];
13396 if (sizeflag & DFLAG)
13397 s = names32[code - eAX_reg];
13399 s = names16[code - eAX_reg];
13400 used_prefixes |= (prefixes & PREFIX_DATA);
13403 case z_mode_ax_reg:
13404 if ((rex & REX_W) || (sizeflag & DFLAG))
13408 if (!(rex & REX_W))
13409 used_prefixes |= (prefixes & PREFIX_DATA);
13412 s = INTERNAL_DISASSEMBLER_ERROR;
13419 OP_I (int bytemode, int sizeflag)
13422 bfd_signed_vma mask = -1;
13427 FETCH_DATA (the_info, codep + 1);
13432 if (address_mode == mode_64bit)
13437 /* Fall through. */
13444 if (sizeflag & DFLAG)
13454 used_prefixes |= (prefixes & PREFIX_DATA);
13466 oappend (INTERNAL_DISASSEMBLER_ERROR);
13471 scratchbuf[0] = '$';
13472 print_operand_value (scratchbuf + 1, 1, op);
13473 oappend (scratchbuf + intel_syntax);
13474 scratchbuf[0] = '\0';
13478 OP_I64 (int bytemode, int sizeflag)
13481 bfd_signed_vma mask = -1;
13483 if (address_mode != mode_64bit)
13485 OP_I (bytemode, sizeflag);
13492 FETCH_DATA (the_info, codep + 1);
13502 if (sizeflag & DFLAG)
13512 used_prefixes |= (prefixes & PREFIX_DATA);
13520 oappend (INTERNAL_DISASSEMBLER_ERROR);
13525 scratchbuf[0] = '$';
13526 print_operand_value (scratchbuf + 1, 1, op);
13527 oappend (scratchbuf + intel_syntax);
13528 scratchbuf[0] = '\0';
13532 OP_sI (int bytemode, int sizeflag)
13535 bfd_signed_vma mask = -1;
13540 FETCH_DATA (the_info, codep + 1);
13542 if ((op & 0x80) != 0)
13552 if (sizeflag & DFLAG)
13561 if ((op & 0x8000) != 0)
13564 used_prefixes |= (prefixes & PREFIX_DATA);
13570 if ((op & 0x8000) != 0)
13574 oappend (INTERNAL_DISASSEMBLER_ERROR);
13578 scratchbuf[0] = '$';
13579 print_operand_value (scratchbuf + 1, 1, op);
13580 oappend (scratchbuf + intel_syntax);
13584 OP_J (int bytemode, int sizeflag)
13588 bfd_vma segment = 0;
13593 FETCH_DATA (the_info, codep + 1);
13595 if ((disp & 0x80) != 0)
13600 if ((sizeflag & DFLAG) || (rex & REX_W))
13605 if ((disp & 0x8000) != 0)
13607 /* In 16bit mode, address is wrapped around at 64k within
13608 the same segment. Otherwise, a data16 prefix on a jump
13609 instruction means that the pc is masked to 16 bits after
13610 the displacement is added! */
13612 if ((prefixes & PREFIX_DATA) == 0)
13613 segment = ((start_pc + codep - start_codep)
13614 & ~((bfd_vma) 0xffff));
13616 if (!(rex & REX_W))
13617 used_prefixes |= (prefixes & PREFIX_DATA);
13620 oappend (INTERNAL_DISASSEMBLER_ERROR);
13623 disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
13625 print_operand_value (scratchbuf, 1, disp);
13626 oappend (scratchbuf);
13630 OP_SEG (int bytemode, int sizeflag)
13632 if (bytemode == w_mode)
13633 oappend (names_seg[modrm.reg]);
13635 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
13639 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
13643 if (sizeflag & DFLAG)
13653 used_prefixes |= (prefixes & PREFIX_DATA);
13655 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
13657 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
13658 oappend (scratchbuf);
13662 OP_OFF (int bytemode, int sizeflag)
13666 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13667 intel_operand_size (bytemode, sizeflag);
13670 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13677 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13678 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13680 oappend (names_seg[ds_reg - es_reg]);
13684 print_operand_value (scratchbuf, 1, off);
13685 oappend (scratchbuf);
13689 OP_OFF64 (int bytemode, int sizeflag)
13693 if (address_mode != mode_64bit
13694 || (prefixes & PREFIX_ADDR))
13696 OP_OFF (bytemode, sizeflag);
13700 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13701 intel_operand_size (bytemode, sizeflag);
13708 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13709 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13711 oappend (names_seg[ds_reg - es_reg]);
13715 print_operand_value (scratchbuf, 1, off);
13716 oappend (scratchbuf);
13720 ptr_reg (int code, int sizeflag)
13724 *obufp++ = open_char;
13725 used_prefixes |= (prefixes & PREFIX_ADDR);
13726 if (address_mode == mode_64bit)
13728 if (!(sizeflag & AFLAG))
13729 s = names32[code - eAX_reg];
13731 s = names64[code - eAX_reg];
13733 else if (sizeflag & AFLAG)
13734 s = names32[code - eAX_reg];
13736 s = names16[code - eAX_reg];
13738 *obufp++ = close_char;
13743 OP_ESreg (int code, int sizeflag)
13749 case 0x6d: /* insw/insl */
13750 intel_operand_size (z_mode, sizeflag);
13752 case 0xa5: /* movsw/movsl/movsq */
13753 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13754 case 0xab: /* stosw/stosl */
13755 case 0xaf: /* scasw/scasl */
13756 intel_operand_size (v_mode, sizeflag);
13759 intel_operand_size (b_mode, sizeflag);
13762 oappend ("%es:" + intel_syntax);
13763 ptr_reg (code, sizeflag);
13767 OP_DSreg (int code, int sizeflag)
13773 case 0x6f: /* outsw/outsl */
13774 intel_operand_size (z_mode, sizeflag);
13776 case 0xa5: /* movsw/movsl/movsq */
13777 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13778 case 0xad: /* lodsw/lodsl/lodsq */
13779 intel_operand_size (v_mode, sizeflag);
13782 intel_operand_size (b_mode, sizeflag);
13791 | PREFIX_GS)) == 0)
13792 prefixes |= PREFIX_DS;
13794 ptr_reg (code, sizeflag);
13798 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13806 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
13808 all_prefixes[last_lock_prefix] = 0;
13809 used_prefixes |= PREFIX_LOCK;
13814 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
13815 oappend (scratchbuf + intel_syntax);
13819 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13828 sprintf (scratchbuf, "db%d", modrm.reg + add);
13830 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
13831 oappend (scratchbuf);
13835 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13837 sprintf (scratchbuf, "%%tr%d", modrm.reg);
13838 oappend (scratchbuf + intel_syntax);
13842 OP_R (int bytemode, int sizeflag)
13844 if (modrm.mod == 3)
13845 OP_E (bytemode, sizeflag);
13851 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13853 int reg = modrm.reg;
13854 const char **names;
13856 used_prefixes |= (prefixes & PREFIX_DATA);
13857 if (prefixes & PREFIX_DATA)
13866 oappend (names[reg]);
13870 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13872 int reg = modrm.reg;
13873 const char **names;
13879 && bytemode != xmm_mode
13880 && bytemode != scalar_mode)
13882 switch (vex.length)
13896 oappend (names[reg]);
13900 OP_EM (int bytemode, int sizeflag)
13903 const char **names;
13905 if (modrm.mod != 3)
13908 && (bytemode == v_mode || bytemode == v_swap_mode))
13910 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13911 used_prefixes |= (prefixes & PREFIX_DATA);
13913 OP_E (bytemode, sizeflag);
13917 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13920 /* Skip mod/rm byte. */
13923 used_prefixes |= (prefixes & PREFIX_DATA);
13925 if (prefixes & PREFIX_DATA)
13934 oappend (names[reg]);
13937 /* cvt* are the only instructions in sse2 which have
13938 both SSE and MMX operands and also have 0x66 prefix
13939 in their opcode. 0x66 was originally used to differentiate
13940 between SSE and MMX instruction(operands). So we have to handle the
13941 cvt* separately using OP_EMC and OP_MXC */
13943 OP_EMC (int bytemode, int sizeflag)
13945 if (modrm.mod != 3)
13947 if (intel_syntax && bytemode == v_mode)
13949 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13950 used_prefixes |= (prefixes & PREFIX_DATA);
13952 OP_E (bytemode, sizeflag);
13956 /* Skip mod/rm byte. */
13959 used_prefixes |= (prefixes & PREFIX_DATA);
13960 oappend (names_mm[modrm.rm]);
13964 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13966 used_prefixes |= (prefixes & PREFIX_DATA);
13967 oappend (names_mm[modrm.reg]);
13971 OP_EX (int bytemode, int sizeflag)
13974 const char **names;
13976 /* Skip mod/rm byte. */
13980 if (modrm.mod != 3)
13982 OP_E_memory (bytemode, sizeflag);
13991 if ((sizeflag & SUFFIX_ALWAYS)
13992 && (bytemode == x_swap_mode
13993 || bytemode == d_swap_mode
13994 || bytemode == d_scalar_swap_mode
13995 || bytemode == q_swap_mode
13996 || bytemode == q_scalar_swap_mode))
14000 && bytemode != xmm_mode
14001 && bytemode != xmmq_mode
14002 && bytemode != d_scalar_mode
14003 && bytemode != d_scalar_swap_mode
14004 && bytemode != q_scalar_mode
14005 && bytemode != q_scalar_swap_mode
14006 && bytemode != vex_scalar_w_dq_mode)
14008 switch (vex.length)
14022 oappend (names[reg]);
14026 OP_MS (int bytemode, int sizeflag)
14028 if (modrm.mod == 3)
14029 OP_EM (bytemode, sizeflag);
14035 OP_XS (int bytemode, int sizeflag)
14037 if (modrm.mod == 3)
14038 OP_EX (bytemode, sizeflag);
14044 OP_M (int bytemode, int sizeflag)
14046 if (modrm.mod == 3)
14047 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14050 OP_E (bytemode, sizeflag);
14054 OP_0f07 (int bytemode, int sizeflag)
14056 if (modrm.mod != 3 || modrm.rm != 0)
14059 OP_E (bytemode, sizeflag);
14062 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
14063 32bit mode and "xchg %rax,%rax" in 64bit mode. */
14066 NOP_Fixup1 (int bytemode, int sizeflag)
14068 if ((prefixes & PREFIX_DATA) != 0
14071 && address_mode == mode_64bit))
14072 OP_REG (bytemode, sizeflag);
14074 strcpy (obuf, "nop");
14078 NOP_Fixup2 (int bytemode, int sizeflag)
14080 if ((prefixes & PREFIX_DATA) != 0
14083 && address_mode == mode_64bit))
14084 OP_IMREG (bytemode, sizeflag);
14087 static const char *const Suffix3DNow[] = {
14088 /* 00 */ NULL, NULL, NULL, NULL,
14089 /* 04 */ NULL, NULL, NULL, NULL,
14090 /* 08 */ NULL, NULL, NULL, NULL,
14091 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
14092 /* 10 */ NULL, NULL, NULL, NULL,
14093 /* 14 */ NULL, NULL, NULL, NULL,
14094 /* 18 */ NULL, NULL, NULL, NULL,
14095 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
14096 /* 20 */ NULL, NULL, NULL, NULL,
14097 /* 24 */ NULL, NULL, NULL, NULL,
14098 /* 28 */ NULL, NULL, NULL, NULL,
14099 /* 2C */ NULL, NULL, NULL, NULL,
14100 /* 30 */ NULL, NULL, NULL, NULL,
14101 /* 34 */ NULL, NULL, NULL, NULL,
14102 /* 38 */ NULL, NULL, NULL, NULL,
14103 /* 3C */ NULL, NULL, NULL, NULL,
14104 /* 40 */ NULL, NULL, NULL, NULL,
14105 /* 44 */ NULL, NULL, NULL, NULL,
14106 /* 48 */ NULL, NULL, NULL, NULL,
14107 /* 4C */ NULL, NULL, NULL, NULL,
14108 /* 50 */ NULL, NULL, NULL, NULL,
14109 /* 54 */ NULL, NULL, NULL, NULL,
14110 /* 58 */ NULL, NULL, NULL, NULL,
14111 /* 5C */ NULL, NULL, NULL, NULL,
14112 /* 60 */ NULL, NULL, NULL, NULL,
14113 /* 64 */ NULL, NULL, NULL, NULL,
14114 /* 68 */ NULL, NULL, NULL, NULL,
14115 /* 6C */ NULL, NULL, NULL, NULL,
14116 /* 70 */ NULL, NULL, NULL, NULL,
14117 /* 74 */ NULL, NULL, NULL, NULL,
14118 /* 78 */ NULL, NULL, NULL, NULL,
14119 /* 7C */ NULL, NULL, NULL, NULL,
14120 /* 80 */ NULL, NULL, NULL, NULL,
14121 /* 84 */ NULL, NULL, NULL, NULL,
14122 /* 88 */ NULL, NULL, "pfnacc", NULL,
14123 /* 8C */ NULL, NULL, "pfpnacc", NULL,
14124 /* 90 */ "pfcmpge", NULL, NULL, NULL,
14125 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
14126 /* 98 */ NULL, NULL, "pfsub", NULL,
14127 /* 9C */ NULL, NULL, "pfadd", NULL,
14128 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
14129 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
14130 /* A8 */ NULL, NULL, "pfsubr", NULL,
14131 /* AC */ NULL, NULL, "pfacc", NULL,
14132 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
14133 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
14134 /* B8 */ NULL, NULL, NULL, "pswapd",
14135 /* BC */ NULL, NULL, NULL, "pavgusb",
14136 /* C0 */ NULL, NULL, NULL, NULL,
14137 /* C4 */ NULL, NULL, NULL, NULL,
14138 /* C8 */ NULL, NULL, NULL, NULL,
14139 /* CC */ NULL, NULL, NULL, NULL,
14140 /* D0 */ NULL, NULL, NULL, NULL,
14141 /* D4 */ NULL, NULL, NULL, NULL,
14142 /* D8 */ NULL, NULL, NULL, NULL,
14143 /* DC */ NULL, NULL, NULL, NULL,
14144 /* E0 */ NULL, NULL, NULL, NULL,
14145 /* E4 */ NULL, NULL, NULL, NULL,
14146 /* E8 */ NULL, NULL, NULL, NULL,
14147 /* EC */ NULL, NULL, NULL, NULL,
14148 /* F0 */ NULL, NULL, NULL, NULL,
14149 /* F4 */ NULL, NULL, NULL, NULL,
14150 /* F8 */ NULL, NULL, NULL, NULL,
14151 /* FC */ NULL, NULL, NULL, NULL,
14155 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14157 const char *mnemonic;
14159 FETCH_DATA (the_info, codep + 1);
14160 /* AMD 3DNow! instructions are specified by an opcode suffix in the
14161 place where an 8-bit immediate would normally go. ie. the last
14162 byte of the instruction. */
14163 obufp = mnemonicendp;
14164 mnemonic = Suffix3DNow[*codep++ & 0xff];
14166 oappend (mnemonic);
14169 /* Since a variable sized modrm/sib chunk is between the start
14170 of the opcode (0x0f0f) and the opcode suffix, we need to do
14171 all the modrm processing first, and don't know until now that
14172 we have a bad opcode. This necessitates some cleaning up. */
14173 op_out[0][0] = '\0';
14174 op_out[1][0] = '\0';
14177 mnemonicendp = obufp;
14180 static struct op simd_cmp_op[] =
14182 { STRING_COMMA_LEN ("eq") },
14183 { STRING_COMMA_LEN ("lt") },
14184 { STRING_COMMA_LEN ("le") },
14185 { STRING_COMMA_LEN ("unord") },
14186 { STRING_COMMA_LEN ("neq") },
14187 { STRING_COMMA_LEN ("nlt") },
14188 { STRING_COMMA_LEN ("nle") },
14189 { STRING_COMMA_LEN ("ord") }
14193 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14195 unsigned int cmp_type;
14197 FETCH_DATA (the_info, codep + 1);
14198 cmp_type = *codep++ & 0xff;
14199 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
14202 char *p = mnemonicendp - 2;
14206 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14207 mnemonicendp += simd_cmp_op[cmp_type].len;
14211 /* We have a reserved extension byte. Output it directly. */
14212 scratchbuf[0] = '$';
14213 print_operand_value (scratchbuf + 1, 1, cmp_type);
14214 oappend (scratchbuf + intel_syntax);
14215 scratchbuf[0] = '\0';
14220 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
14221 int sizeflag ATTRIBUTE_UNUSED)
14223 /* mwait %eax,%ecx */
14226 const char **names = (address_mode == mode_64bit
14227 ? names64 : names32);
14228 strcpy (op_out[0], names[0]);
14229 strcpy (op_out[1], names[1]);
14230 two_source_ops = 1;
14232 /* Skip mod/rm byte. */
14238 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
14239 int sizeflag ATTRIBUTE_UNUSED)
14241 /* monitor %eax,%ecx,%edx" */
14244 const char **op1_names;
14245 const char **names = (address_mode == mode_64bit
14246 ? names64 : names32);
14248 if (!(prefixes & PREFIX_ADDR))
14249 op1_names = (address_mode == mode_16bit
14250 ? names16 : names);
14253 /* Remove "addr16/addr32". */
14254 all_prefixes[last_addr_prefix] = 0;
14255 op1_names = (address_mode != mode_32bit
14256 ? names32 : names16);
14257 used_prefixes |= PREFIX_ADDR;
14259 strcpy (op_out[0], op1_names[0]);
14260 strcpy (op_out[1], names[1]);
14261 strcpy (op_out[2], names[2]);
14262 two_source_ops = 1;
14264 /* Skip mod/rm byte. */
14272 /* Throw away prefixes and 1st. opcode byte. */
14273 codep = insn_codep + 1;
14278 REP_Fixup (int bytemode, int sizeflag)
14280 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14282 if (prefixes & PREFIX_REPZ)
14283 all_prefixes[last_repz_prefix] = REP_PREFIX;
14290 OP_IMREG (bytemode, sizeflag);
14293 OP_ESreg (bytemode, sizeflag);
14296 OP_DSreg (bytemode, sizeflag);
14305 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
14310 /* Change cmpxchg8b to cmpxchg16b. */
14311 char *p = mnemonicendp - 2;
14312 mnemonicendp = stpcpy (p, "16b");
14315 OP_M (bytemode, sizeflag);
14319 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
14321 const char **names;
14325 switch (vex.length)
14339 oappend (names[reg]);
14343 CRC32_Fixup (int bytemode, int sizeflag)
14345 /* Add proper suffix to "crc32". */
14346 char *p = mnemonicendp;
14365 if (sizeflag & DFLAG)
14369 used_prefixes |= (prefixes & PREFIX_DATA);
14373 oappend (INTERNAL_DISASSEMBLER_ERROR);
14380 if (modrm.mod == 3)
14384 /* Skip mod/rm byte. */
14389 add = (rex & REX_B) ? 8 : 0;
14390 if (bytemode == b_mode)
14394 oappend (names8rex[modrm.rm + add]);
14396 oappend (names8[modrm.rm + add]);
14402 oappend (names64[modrm.rm + add]);
14403 else if ((prefixes & PREFIX_DATA))
14404 oappend (names16[modrm.rm + add]);
14406 oappend (names32[modrm.rm + add]);
14410 OP_E (bytemode, sizeflag);
14414 FXSAVE_Fixup (int bytemode, int sizeflag)
14416 /* Add proper suffix to "fxsave" and "fxrstor". */
14420 char *p = mnemonicendp;
14426 OP_M (bytemode, sizeflag);
14429 /* Display the destination register operand for instructions with
14433 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14436 const char **names;
14444 reg = vex.register_specifier;
14445 if (bytemode == vex_scalar_mode)
14447 oappend (names_xmm[reg]);
14451 switch (vex.length)
14483 oappend (names[reg]);
14486 /* Get the VEX immediate byte without moving codep. */
14488 static unsigned char
14489 get_vex_imm8 (int sizeflag, int opnum)
14491 int bytes_before_imm = 0;
14493 if (modrm.mod != 3)
14495 /* There are SIB/displacement bytes. */
14496 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14498 /* 32/64 bit address mode */
14499 int base = modrm.rm;
14501 /* Check SIB byte. */
14504 FETCH_DATA (the_info, codep + 1);
14506 /* When decoding the third source, don't increase
14507 bytes_before_imm as this has already been incremented
14508 by one in OP_E_memory while decoding the second
14511 bytes_before_imm++;
14514 /* Don't increase bytes_before_imm when decoding the third source,
14515 it has already been incremented by OP_E_memory while decoding
14516 the second source operand. */
14522 /* When modrm.rm == 5 or modrm.rm == 4 and base in
14523 SIB == 5, there is a 4 byte displacement. */
14525 /* No displacement. */
14528 /* 4 byte displacement. */
14529 bytes_before_imm += 4;
14532 /* 1 byte displacement. */
14533 bytes_before_imm++;
14540 /* 16 bit address mode */
14541 /* Don't increase bytes_before_imm when decoding the third source,
14542 it has already been incremented by OP_E_memory while decoding
14543 the second source operand. */
14549 /* When modrm.rm == 6, there is a 2 byte displacement. */
14551 /* No displacement. */
14554 /* 2 byte displacement. */
14555 bytes_before_imm += 2;
14558 /* 1 byte displacement: when decoding the third source,
14559 don't increase bytes_before_imm as this has already
14560 been incremented by one in OP_E_memory while decoding
14561 the second source operand. */
14563 bytes_before_imm++;
14571 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
14572 return codep [bytes_before_imm];
14576 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
14578 const char **names;
14580 if (reg == -1 && modrm.mod != 3)
14582 OP_E_memory (bytemode, sizeflag);
14594 else if (reg > 7 && address_mode != mode_64bit)
14598 switch (vex.length)
14609 oappend (names[reg]);
14613 OP_EX_VexImmW (int bytemode, int sizeflag)
14616 static unsigned char vex_imm8;
14618 if (vex_w_done == 0)
14622 /* Skip mod/rm byte. */
14626 vex_imm8 = get_vex_imm8 (sizeflag, 0);
14629 reg = vex_imm8 >> 4;
14631 OP_EX_VexReg (bytemode, sizeflag, reg);
14633 else if (vex_w_done == 1)
14638 reg = vex_imm8 >> 4;
14640 OP_EX_VexReg (bytemode, sizeflag, reg);
14644 /* Output the imm8 directly. */
14645 scratchbuf[0] = '$';
14646 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
14647 oappend (scratchbuf + intel_syntax);
14648 scratchbuf[0] = '\0';
14654 OP_Vex_2src (int bytemode, int sizeflag)
14656 if (modrm.mod == 3)
14658 int reg = modrm.rm;
14662 oappend (names_xmm[reg]);
14667 && (bytemode == v_mode || bytemode == v_swap_mode))
14669 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14670 used_prefixes |= (prefixes & PREFIX_DATA);
14672 OP_E (bytemode, sizeflag);
14677 OP_Vex_2src_1 (int bytemode, int sizeflag)
14679 if (modrm.mod == 3)
14681 /* Skip mod/rm byte. */
14687 oappend (names_xmm[vex.register_specifier]);
14689 OP_Vex_2src (bytemode, sizeflag);
14693 OP_Vex_2src_2 (int bytemode, int sizeflag)
14696 OP_Vex_2src (bytemode, sizeflag);
14698 oappend (names_xmm[vex.register_specifier]);
14702 OP_EX_VexW (int bytemode, int sizeflag)
14710 /* Skip mod/rm byte. */
14715 reg = get_vex_imm8 (sizeflag, 0) >> 4;
14720 reg = get_vex_imm8 (sizeflag, 1) >> 4;
14723 OP_EX_VexReg (bytemode, sizeflag, reg);
14727 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
14728 int sizeflag ATTRIBUTE_UNUSED)
14730 /* Skip the immediate byte and check for invalid bits. */
14731 FETCH_DATA (the_info, codep + 1);
14732 if (*codep++ & 0xf)
14737 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14740 const char **names;
14742 FETCH_DATA (the_info, codep + 1);
14745 if (bytemode != x_mode)
14752 if (reg > 7 && address_mode != mode_64bit)
14755 switch (vex.length)
14766 oappend (names[reg]);
14770 OP_XMM_VexW (int bytemode, int sizeflag)
14772 /* Turn off the REX.W bit since it is used for swapping operands
14775 OP_XMM (bytemode, sizeflag);
14779 OP_EX_Vex (int bytemode, int sizeflag)
14781 if (modrm.mod != 3)
14783 if (vex.register_specifier != 0)
14787 OP_EX (bytemode, sizeflag);
14791 OP_XMM_Vex (int bytemode, int sizeflag)
14793 if (modrm.mod != 3)
14795 if (vex.register_specifier != 0)
14799 OP_XMM (bytemode, sizeflag);
14803 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14805 switch (vex.length)
14808 mnemonicendp = stpcpy (obuf, "vzeroupper");
14811 mnemonicendp = stpcpy (obuf, "vzeroall");
14818 static struct op vex_cmp_op[] =
14820 { STRING_COMMA_LEN ("eq") },
14821 { STRING_COMMA_LEN ("lt") },
14822 { STRING_COMMA_LEN ("le") },
14823 { STRING_COMMA_LEN ("unord") },
14824 { STRING_COMMA_LEN ("neq") },
14825 { STRING_COMMA_LEN ("nlt") },
14826 { STRING_COMMA_LEN ("nle") },
14827 { STRING_COMMA_LEN ("ord") },
14828 { STRING_COMMA_LEN ("eq_uq") },
14829 { STRING_COMMA_LEN ("nge") },
14830 { STRING_COMMA_LEN ("ngt") },
14831 { STRING_COMMA_LEN ("false") },
14832 { STRING_COMMA_LEN ("neq_oq") },
14833 { STRING_COMMA_LEN ("ge") },
14834 { STRING_COMMA_LEN ("gt") },
14835 { STRING_COMMA_LEN ("true") },
14836 { STRING_COMMA_LEN ("eq_os") },
14837 { STRING_COMMA_LEN ("lt_oq") },
14838 { STRING_COMMA_LEN ("le_oq") },
14839 { STRING_COMMA_LEN ("unord_s") },
14840 { STRING_COMMA_LEN ("neq_us") },
14841 { STRING_COMMA_LEN ("nlt_uq") },
14842 { STRING_COMMA_LEN ("nle_uq") },
14843 { STRING_COMMA_LEN ("ord_s") },
14844 { STRING_COMMA_LEN ("eq_us") },
14845 { STRING_COMMA_LEN ("nge_uq") },
14846 { STRING_COMMA_LEN ("ngt_uq") },
14847 { STRING_COMMA_LEN ("false_os") },
14848 { STRING_COMMA_LEN ("neq_os") },
14849 { STRING_COMMA_LEN ("ge_oq") },
14850 { STRING_COMMA_LEN ("gt_oq") },
14851 { STRING_COMMA_LEN ("true_us") },
14855 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14857 unsigned int cmp_type;
14859 FETCH_DATA (the_info, codep + 1);
14860 cmp_type = *codep++ & 0xff;
14861 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
14864 char *p = mnemonicendp - 2;
14868 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
14869 mnemonicendp += vex_cmp_op[cmp_type].len;
14873 /* We have a reserved extension byte. Output it directly. */
14874 scratchbuf[0] = '$';
14875 print_operand_value (scratchbuf + 1, 1, cmp_type);
14876 oappend (scratchbuf + intel_syntax);
14877 scratchbuf[0] = '\0';
14881 static const struct op pclmul_op[] =
14883 { STRING_COMMA_LEN ("lql") },
14884 { STRING_COMMA_LEN ("hql") },
14885 { STRING_COMMA_LEN ("lqh") },
14886 { STRING_COMMA_LEN ("hqh") }
14890 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
14891 int sizeflag ATTRIBUTE_UNUSED)
14893 unsigned int pclmul_type;
14895 FETCH_DATA (the_info, codep + 1);
14896 pclmul_type = *codep++ & 0xff;
14897 switch (pclmul_type)
14908 if (pclmul_type < ARRAY_SIZE (pclmul_op))
14911 char *p = mnemonicendp - 3;
14916 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
14917 mnemonicendp += pclmul_op[pclmul_type].len;
14921 /* We have a reserved extension byte. Output it directly. */
14922 scratchbuf[0] = '$';
14923 print_operand_value (scratchbuf + 1, 1, pclmul_type);
14924 oappend (scratchbuf + intel_syntax);
14925 scratchbuf[0] = '\0';
14930 MOVBE_Fixup (int bytemode, int sizeflag)
14932 /* Add proper suffix to "movbe". */
14933 char *p = mnemonicendp;
14942 if (sizeflag & SUFFIX_ALWAYS)
14948 if (sizeflag & DFLAG)
14952 used_prefixes |= (prefixes & PREFIX_DATA);
14957 oappend (INTERNAL_DISASSEMBLER_ERROR);
14964 OP_M (bytemode, sizeflag);
14968 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14971 const char **names;
14973 /* Skip mod/rm byte. */
14987 oappend (names[reg]);
14991 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14993 const char **names;
15000 oappend (names[vex.register_specifier]);