1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2017 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma, disassemble_info *);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma get64 (void);
58 static bfd_signed_vma get32 (void);
59 static bfd_signed_vma get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void OP_Mwaitx (int, int);
106 static void NOP_Fixup1 (int, int);
107 static void NOP_Fixup2 (int, int);
108 static void OP_3DNowSuffix (int, int);
109 static void CMP_Fixup (int, int);
110 static void BadOp (void);
111 static void REP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void OP_LWPCB_E (int, int);
121 static void OP_LWP_E (int, int);
122 static void OP_Vex_2src_1 (int, int);
123 static void OP_Vex_2src_2 (int, int);
125 static void MOVBE_Fixup (int, int);
127 static void OP_Mask (int, int);
130 /* Points to first byte not fetched. */
131 bfd_byte *max_fetched;
132 bfd_byte the_buffer[MAX_MNEM_SIZE];
135 OPCODES_SIGJMP_BUF bailout;
145 enum address_mode address_mode;
147 /* Flags for the prefixes for the current instruction. See below. */
150 /* REX prefix the current instruction. See below. */
152 /* Bits of REX we've already used. */
154 /* REX bits in original REX prefix ignored. */
155 static int rex_ignored;
156 /* Mark parts used in the REX prefix. When we are testing for
157 empty prefix (for 8bit register REX extension), just mask it
158 out. Otherwise test for REX bit is excuse for existence of REX
159 only in case value is nonzero. */
160 #define USED_REX(value) \
165 rex_used |= (value) | REX_OPCODE; \
168 rex_used |= REX_OPCODE; \
171 /* Flags for prefixes which we somehow handled when printing the
172 current instruction. */
173 static int used_prefixes;
175 /* Flags stored in PREFIXES. */
176 #define PREFIX_REPZ 1
177 #define PREFIX_REPNZ 2
178 #define PREFIX_LOCK 4
180 #define PREFIX_SS 0x10
181 #define PREFIX_DS 0x20
182 #define PREFIX_ES 0x40
183 #define PREFIX_FS 0x80
184 #define PREFIX_GS 0x100
185 #define PREFIX_DATA 0x200
186 #define PREFIX_ADDR 0x400
187 #define PREFIX_FWAIT 0x800
189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
190 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
192 #define FETCH_DATA(info, addr) \
193 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
194 ? 1 : fetch_data ((info), (addr)))
197 fetch_data (struct disassemble_info *info, bfd_byte *addr)
200 struct dis_private *priv = (struct dis_private *) info->private_data;
201 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
203 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
204 status = (*info->read_memory_func) (start,
206 addr - priv->max_fetched,
212 /* If we did manage to read at least one byte, then
213 print_insn_i386 will do something sensible. Otherwise, print
214 an error. We do that here because this is where we know
216 if (priv->max_fetched == priv->the_buffer)
217 (*info->memory_error_func) (status, start, info);
218 OPCODES_SIGLONGJMP (priv->bailout, 1);
221 priv->max_fetched = addr;
225 /* Possible values for prefix requirement. */
226 #define PREFIX_IGNORED_SHIFT 16
227 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
228 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
233 /* Opcode prefixes. */
234 #define PREFIX_OPCODE (PREFIX_REPZ \
238 /* Prefixes ignored. */
239 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
240 | PREFIX_IGNORED_REPNZ \
241 | PREFIX_IGNORED_DATA)
243 #define XX { NULL, 0 }
244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
246 #define Eb { OP_E, b_mode }
247 #define Ebnd { OP_E, bnd_mode }
248 #define EbS { OP_E, b_swap_mode }
249 #define Ev { OP_E, v_mode }
250 #define Ev_bnd { OP_E, v_bnd_mode }
251 #define EvS { OP_E, v_swap_mode }
252 #define Ed { OP_E, d_mode }
253 #define Edq { OP_E, dq_mode }
254 #define Edqw { OP_E, dqw_mode }
255 #define Edqb { OP_E, dqb_mode }
256 #define Edb { OP_E, db_mode }
257 #define Edw { OP_E, dw_mode }
258 #define Edqd { OP_E, dqd_mode }
259 #define Eq { OP_E, q_mode }
260 #define indirEv { OP_indirE, indir_v_mode }
261 #define indirEp { OP_indirE, f_mode }
262 #define stackEv { OP_E, stack_v_mode }
263 #define Em { OP_E, m_mode }
264 #define Ew { OP_E, w_mode }
265 #define M { OP_M, 0 } /* lea, lgdt, etc. */
266 #define Ma { OP_M, a_mode }
267 #define Mb { OP_M, b_mode }
268 #define Md { OP_M, d_mode }
269 #define Mo { OP_M, o_mode }
270 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
271 #define Mq { OP_M, q_mode }
272 #define Mx { OP_M, x_mode }
273 #define Mxmm { OP_M, xmm_mode }
274 #define Gb { OP_G, b_mode }
275 #define Gbnd { OP_G, bnd_mode }
276 #define Gv { OP_G, v_mode }
277 #define Gd { OP_G, d_mode }
278 #define Gdq { OP_G, dq_mode }
279 #define Gm { OP_G, m_mode }
280 #define Gw { OP_G, w_mode }
281 #define Rd { OP_R, d_mode }
282 #define Rdq { OP_R, dq_mode }
283 #define Rm { OP_R, m_mode }
284 #define Ib { OP_I, b_mode }
285 #define sIb { OP_sI, b_mode } /* sign extened byte */
286 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
287 #define Iv { OP_I, v_mode }
288 #define sIv { OP_sI, v_mode }
289 #define Iq { OP_I, q_mode }
290 #define Iv64 { OP_I64, v_mode }
291 #define Iw { OP_I, w_mode }
292 #define I1 { OP_I, const_1_mode }
293 #define Jb { OP_J, b_mode }
294 #define Jv { OP_J, v_mode }
295 #define Cm { OP_C, m_mode }
296 #define Dm { OP_D, m_mode }
297 #define Td { OP_T, d_mode }
298 #define Skip_MODRM { OP_Skip_MODRM, 0 }
300 #define RMeAX { OP_REG, eAX_reg }
301 #define RMeBX { OP_REG, eBX_reg }
302 #define RMeCX { OP_REG, eCX_reg }
303 #define RMeDX { OP_REG, eDX_reg }
304 #define RMeSP { OP_REG, eSP_reg }
305 #define RMeBP { OP_REG, eBP_reg }
306 #define RMeSI { OP_REG, eSI_reg }
307 #define RMeDI { OP_REG, eDI_reg }
308 #define RMrAX { OP_REG, rAX_reg }
309 #define RMrBX { OP_REG, rBX_reg }
310 #define RMrCX { OP_REG, rCX_reg }
311 #define RMrDX { OP_REG, rDX_reg }
312 #define RMrSP { OP_REG, rSP_reg }
313 #define RMrBP { OP_REG, rBP_reg }
314 #define RMrSI { OP_REG, rSI_reg }
315 #define RMrDI { OP_REG, rDI_reg }
316 #define RMAL { OP_REG, al_reg }
317 #define RMCL { OP_REG, cl_reg }
318 #define RMDL { OP_REG, dl_reg }
319 #define RMBL { OP_REG, bl_reg }
320 #define RMAH { OP_REG, ah_reg }
321 #define RMCH { OP_REG, ch_reg }
322 #define RMDH { OP_REG, dh_reg }
323 #define RMBH { OP_REG, bh_reg }
324 #define RMAX { OP_REG, ax_reg }
325 #define RMDX { OP_REG, dx_reg }
327 #define eAX { OP_IMREG, eAX_reg }
328 #define eBX { OP_IMREG, eBX_reg }
329 #define eCX { OP_IMREG, eCX_reg }
330 #define eDX { OP_IMREG, eDX_reg }
331 #define eSP { OP_IMREG, eSP_reg }
332 #define eBP { OP_IMREG, eBP_reg }
333 #define eSI { OP_IMREG, eSI_reg }
334 #define eDI { OP_IMREG, eDI_reg }
335 #define AL { OP_IMREG, al_reg }
336 #define CL { OP_IMREG, cl_reg }
337 #define DL { OP_IMREG, dl_reg }
338 #define BL { OP_IMREG, bl_reg }
339 #define AH { OP_IMREG, ah_reg }
340 #define CH { OP_IMREG, ch_reg }
341 #define DH { OP_IMREG, dh_reg }
342 #define BH { OP_IMREG, bh_reg }
343 #define AX { OP_IMREG, ax_reg }
344 #define DX { OP_IMREG, dx_reg }
345 #define zAX { OP_IMREG, z_mode_ax_reg }
346 #define indirDX { OP_IMREG, indir_dx_reg }
348 #define Sw { OP_SEG, w_mode }
349 #define Sv { OP_SEG, v_mode }
350 #define Ap { OP_DIR, 0 }
351 #define Ob { OP_OFF64, b_mode }
352 #define Ov { OP_OFF64, v_mode }
353 #define Xb { OP_DSreg, eSI_reg }
354 #define Xv { OP_DSreg, eSI_reg }
355 #define Xz { OP_DSreg, eSI_reg }
356 #define Yb { OP_ESreg, eDI_reg }
357 #define Yv { OP_ESreg, eDI_reg }
358 #define DSBX { OP_DSreg, eBX_reg }
360 #define es { OP_REG, es_reg }
361 #define ss { OP_REG, ss_reg }
362 #define cs { OP_REG, cs_reg }
363 #define ds { OP_REG, ds_reg }
364 #define fs { OP_REG, fs_reg }
365 #define gs { OP_REG, gs_reg }
367 #define MX { OP_MMX, 0 }
368 #define XM { OP_XMM, 0 }
369 #define XMScalar { OP_XMM, scalar_mode }
370 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
371 #define XMM { OP_XMM, xmm_mode }
372 #define XMxmmq { OP_XMM, xmmq_mode }
373 #define EM { OP_EM, v_mode }
374 #define EMS { OP_EM, v_swap_mode }
375 #define EMd { OP_EM, d_mode }
376 #define EMx { OP_EM, x_mode }
377 #define EXw { OP_EX, w_mode }
378 #define EXd { OP_EX, d_mode }
379 #define EXdScalar { OP_EX, d_scalar_mode }
380 #define EXdS { OP_EX, d_swap_mode }
381 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
382 #define EXq { OP_EX, q_mode }
383 #define EXqScalar { OP_EX, q_scalar_mode }
384 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
385 #define EXqS { OP_EX, q_swap_mode }
386 #define EXx { OP_EX, x_mode }
387 #define EXxS { OP_EX, x_swap_mode }
388 #define EXxmm { OP_EX, xmm_mode }
389 #define EXymm { OP_EX, ymm_mode }
390 #define EXxmmq { OP_EX, xmmq_mode }
391 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
392 #define EXxmm_mb { OP_EX, xmm_mb_mode }
393 #define EXxmm_mw { OP_EX, xmm_mw_mode }
394 #define EXxmm_md { OP_EX, xmm_md_mode }
395 #define EXxmm_mq { OP_EX, xmm_mq_mode }
396 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
397 #define EXxmmdw { OP_EX, xmmdw_mode }
398 #define EXxmmqd { OP_EX, xmmqd_mode }
399 #define EXymmq { OP_EX, ymmq_mode }
400 #define EXVexWdq { OP_EX, vex_w_dq_mode }
401 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
402 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
403 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
404 #define MS { OP_MS, v_mode }
405 #define XS { OP_XS, v_mode }
406 #define EMCq { OP_EMC, q_mode }
407 #define MXC { OP_MXC, 0 }
408 #define OPSUF { OP_3DNowSuffix, 0 }
409 #define CMP { CMP_Fixup, 0 }
410 #define XMM0 { XMM_Fixup, 0 }
411 #define FXSAVE { FXSAVE_Fixup, 0 }
412 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
413 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
415 #define Vex { OP_VEX, vex_mode }
416 #define VexScalar { OP_VEX, vex_scalar_mode }
417 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
418 #define Vex128 { OP_VEX, vex128_mode }
419 #define Vex256 { OP_VEX, vex256_mode }
420 #define VexGdq { OP_VEX, dq_mode }
421 #define VexI4 { VEXI4_Fixup, 0}
422 #define EXdVex { OP_EX_Vex, d_mode }
423 #define EXdVexS { OP_EX_Vex, d_swap_mode }
424 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
425 #define EXqVex { OP_EX_Vex, q_mode }
426 #define EXqVexS { OP_EX_Vex, q_swap_mode }
427 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
428 #define EXVexW { OP_EX_VexW, x_mode }
429 #define EXdVexW { OP_EX_VexW, d_mode }
430 #define EXqVexW { OP_EX_VexW, q_mode }
431 #define EXVexImmW { OP_EX_VexImmW, x_mode }
432 #define XMVex { OP_XMM_Vex, 0 }
433 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
434 #define XMVexW { OP_XMM_VexW, 0 }
435 #define XMVexI4 { OP_REG_VexI4, x_mode }
436 #define PCLMUL { PCLMUL_Fixup, 0 }
437 #define VZERO { VZERO_Fixup, 0 }
438 #define VCMP { VCMP_Fixup, 0 }
439 #define VPCMP { VPCMP_Fixup, 0 }
441 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
442 #define EXxEVexS { OP_Rounding, evex_sae_mode }
444 #define XMask { OP_Mask, mask_mode }
445 #define MaskG { OP_G, mask_mode }
446 #define MaskE { OP_E, mask_mode }
447 #define MaskBDE { OP_E, mask_bd_mode }
448 #define MaskR { OP_R, mask_mode }
449 #define MaskVex { OP_VEX, mask_mode }
451 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
452 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
453 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
454 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
456 /* Used handle "rep" prefix for string instructions. */
457 #define Xbr { REP_Fixup, eSI_reg }
458 #define Xvr { REP_Fixup, eSI_reg }
459 #define Ybr { REP_Fixup, eDI_reg }
460 #define Yvr { REP_Fixup, eDI_reg }
461 #define Yzr { REP_Fixup, eDI_reg }
462 #define indirDXr { REP_Fixup, indir_dx_reg }
463 #define ALr { REP_Fixup, al_reg }
464 #define eAXr { REP_Fixup, eAX_reg }
466 /* Used handle HLE prefix for lockable instructions. */
467 #define Ebh1 { HLE_Fixup1, b_mode }
468 #define Evh1 { HLE_Fixup1, v_mode }
469 #define Ebh2 { HLE_Fixup2, b_mode }
470 #define Evh2 { HLE_Fixup2, v_mode }
471 #define Ebh3 { HLE_Fixup3, b_mode }
472 #define Evh3 { HLE_Fixup3, v_mode }
474 #define BND { BND_Fixup, 0 }
476 #define cond_jump_flag { NULL, cond_jump_mode }
477 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
479 /* bits in sizeflag */
480 #define SUFFIX_ALWAYS 4
488 /* byte operand with operand swapped */
490 /* byte operand, sign extend like 'T' suffix */
492 /* operand size depends on prefixes */
494 /* operand size depends on prefixes with operand swapped */
498 /* double word operand */
500 /* double word operand with operand swapped */
502 /* quad word operand */
504 /* quad word operand with operand swapped */
506 /* ten-byte operand */
508 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
509 broadcast enabled. */
511 /* Similar to x_mode, but with different EVEX mem shifts. */
513 /* Similar to x_mode, but with disabled broadcast. */
515 /* Similar to x_mode, but with operands swapped and disabled broadcast
518 /* 16-byte XMM operand */
520 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
521 memory operand (depending on vector length). Broadcast isn't
524 /* Same as xmmq_mode, but broadcast is allowed. */
525 evex_half_bcst_xmmq_mode,
526 /* XMM register or byte memory operand */
528 /* XMM register or word memory operand */
530 /* XMM register or double word memory operand */
532 /* XMM register or quad word memory operand */
534 /* XMM register or double/quad word memory operand, depending on
537 /* 16-byte XMM, word, double word or quad word operand. */
539 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
541 /* 32-byte YMM operand */
543 /* quad word, ymmword or zmmword memory operand. */
545 /* 32-byte YMM or 16-byte word operand */
547 /* d_mode in 32bit, q_mode in 64bit mode. */
549 /* pair of v_mode operands */
554 /* operand size depends on REX prefixes. */
556 /* registers like dq_mode, memory like w_mode. */
559 /* 4- or 6-byte pointer operand */
562 /* v_mode for indirect branch opcodes. */
564 /* v_mode for stack-related opcodes. */
566 /* non-quad operand size depends on prefixes */
568 /* 16-byte operand */
570 /* registers like dq_mode, memory like b_mode. */
572 /* registers like d_mode, memory like b_mode. */
574 /* registers like d_mode, memory like w_mode. */
576 /* registers like dq_mode, memory like d_mode. */
578 /* normal vex mode */
580 /* 128bit vex mode */
582 /* 256bit vex mode */
584 /* operand size depends on the VEX.W bit. */
587 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
588 vex_vsib_d_w_dq_mode,
589 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
591 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
592 vex_vsib_q_w_dq_mode,
593 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
596 /* scalar, ignore vector length. */
598 /* like d_mode, ignore vector length. */
600 /* like d_swap_mode, ignore vector length. */
602 /* like q_mode, ignore vector length. */
604 /* like q_swap_mode, ignore vector length. */
606 /* like vex_mode, ignore vector length. */
608 /* like vex_w_dq_mode, ignore vector length. */
609 vex_scalar_w_dq_mode,
611 /* Static rounding. */
613 /* Supress all exceptions. */
616 /* Mask register operand. */
618 /* Mask register operand. */
685 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
687 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
688 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
689 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
690 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
691 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
692 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
693 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
694 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
695 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
696 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
697 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
698 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
699 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
700 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
701 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
819 MOD_VEX_0F12_PREFIX_0,
821 MOD_VEX_0F16_PREFIX_0,
824 MOD_VEX_W_0_0F41_P_0_LEN_1,
825 MOD_VEX_W_1_0F41_P_0_LEN_1,
826 MOD_VEX_W_0_0F41_P_2_LEN_1,
827 MOD_VEX_W_1_0F41_P_2_LEN_1,
828 MOD_VEX_W_0_0F42_P_0_LEN_1,
829 MOD_VEX_W_1_0F42_P_0_LEN_1,
830 MOD_VEX_W_0_0F42_P_2_LEN_1,
831 MOD_VEX_W_1_0F42_P_2_LEN_1,
832 MOD_VEX_W_0_0F44_P_0_LEN_1,
833 MOD_VEX_W_1_0F44_P_0_LEN_1,
834 MOD_VEX_W_0_0F44_P_2_LEN_1,
835 MOD_VEX_W_1_0F44_P_2_LEN_1,
836 MOD_VEX_W_0_0F45_P_0_LEN_1,
837 MOD_VEX_W_1_0F45_P_0_LEN_1,
838 MOD_VEX_W_0_0F45_P_2_LEN_1,
839 MOD_VEX_W_1_0F45_P_2_LEN_1,
840 MOD_VEX_W_0_0F46_P_0_LEN_1,
841 MOD_VEX_W_1_0F46_P_0_LEN_1,
842 MOD_VEX_W_0_0F46_P_2_LEN_1,
843 MOD_VEX_W_1_0F46_P_2_LEN_1,
844 MOD_VEX_W_0_0F47_P_0_LEN_1,
845 MOD_VEX_W_1_0F47_P_0_LEN_1,
846 MOD_VEX_W_0_0F47_P_2_LEN_1,
847 MOD_VEX_W_1_0F47_P_2_LEN_1,
848 MOD_VEX_W_0_0F4A_P_0_LEN_1,
849 MOD_VEX_W_1_0F4A_P_0_LEN_1,
850 MOD_VEX_W_0_0F4A_P_2_LEN_1,
851 MOD_VEX_W_1_0F4A_P_2_LEN_1,
852 MOD_VEX_W_0_0F4B_P_0_LEN_1,
853 MOD_VEX_W_1_0F4B_P_0_LEN_1,
854 MOD_VEX_W_0_0F4B_P_2_LEN_1,
866 MOD_VEX_W_0_0F91_P_0_LEN_0,
867 MOD_VEX_W_1_0F91_P_0_LEN_0,
868 MOD_VEX_W_0_0F91_P_2_LEN_0,
869 MOD_VEX_W_1_0F91_P_2_LEN_0,
870 MOD_VEX_W_0_0F92_P_0_LEN_0,
871 MOD_VEX_W_0_0F92_P_2_LEN_0,
872 MOD_VEX_W_0_0F92_P_3_LEN_0,
873 MOD_VEX_W_1_0F92_P_3_LEN_0,
874 MOD_VEX_W_0_0F93_P_0_LEN_0,
875 MOD_VEX_W_0_0F93_P_2_LEN_0,
876 MOD_VEX_W_0_0F93_P_3_LEN_0,
877 MOD_VEX_W_1_0F93_P_3_LEN_0,
878 MOD_VEX_W_0_0F98_P_0_LEN_0,
879 MOD_VEX_W_1_0F98_P_0_LEN_0,
880 MOD_VEX_W_0_0F98_P_2_LEN_0,
881 MOD_VEX_W_1_0F98_P_2_LEN_0,
882 MOD_VEX_W_0_0F99_P_0_LEN_0,
883 MOD_VEX_W_1_0F99_P_0_LEN_0,
884 MOD_VEX_W_0_0F99_P_2_LEN_0,
885 MOD_VEX_W_1_0F99_P_2_LEN_0,
888 MOD_VEX_0FD7_PREFIX_2,
889 MOD_VEX_0FE7_PREFIX_2,
890 MOD_VEX_0FF0_PREFIX_3,
891 MOD_VEX_0F381A_PREFIX_2,
892 MOD_VEX_0F382A_PREFIX_2,
893 MOD_VEX_0F382C_PREFIX_2,
894 MOD_VEX_0F382D_PREFIX_2,
895 MOD_VEX_0F382E_PREFIX_2,
896 MOD_VEX_0F382F_PREFIX_2,
897 MOD_VEX_0F385A_PREFIX_2,
898 MOD_VEX_0F388C_PREFIX_2,
899 MOD_VEX_0F388E_PREFIX_2,
900 MOD_VEX_W_0_0F3A30_P_2_LEN_0,
901 MOD_VEX_W_1_0F3A30_P_2_LEN_0,
902 MOD_VEX_W_0_0F3A31_P_2_LEN_0,
903 MOD_VEX_W_1_0F3A31_P_2_LEN_0,
904 MOD_VEX_W_0_0F3A32_P_2_LEN_0,
905 MOD_VEX_W_1_0F3A32_P_2_LEN_0,
906 MOD_VEX_W_0_0F3A33_P_2_LEN_0,
907 MOD_VEX_W_1_0F3A33_P_2_LEN_0,
909 MOD_EVEX_0F10_PREFIX_1,
910 MOD_EVEX_0F10_PREFIX_3,
911 MOD_EVEX_0F11_PREFIX_1,
912 MOD_EVEX_0F11_PREFIX_3,
913 MOD_EVEX_0F12_PREFIX_0,
914 MOD_EVEX_0F16_PREFIX_0,
915 MOD_EVEX_0F38C6_REG_1,
916 MOD_EVEX_0F38C6_REG_2,
917 MOD_EVEX_0F38C6_REG_5,
918 MOD_EVEX_0F38C6_REG_6,
919 MOD_EVEX_0F38C7_REG_1,
920 MOD_EVEX_0F38C7_REG_2,
921 MOD_EVEX_0F38C7_REG_5,
922 MOD_EVEX_0F38C7_REG_6
985 PREFIX_MOD_0_0FAE_REG_4,
986 PREFIX_MOD_3_0FAE_REG_4,
994 PREFIX_MOD_0_0FC7_REG_6,
995 PREFIX_MOD_3_0FC7_REG_6,
996 PREFIX_MOD_3_0FC7_REG_7,
1120 PREFIX_VEX_0F71_REG_2,
1121 PREFIX_VEX_0F71_REG_4,
1122 PREFIX_VEX_0F71_REG_6,
1123 PREFIX_VEX_0F72_REG_2,
1124 PREFIX_VEX_0F72_REG_4,
1125 PREFIX_VEX_0F72_REG_6,
1126 PREFIX_VEX_0F73_REG_2,
1127 PREFIX_VEX_0F73_REG_3,
1128 PREFIX_VEX_0F73_REG_6,
1129 PREFIX_VEX_0F73_REG_7,
1301 PREFIX_VEX_0F38F3_REG_1,
1302 PREFIX_VEX_0F38F3_REG_2,
1303 PREFIX_VEX_0F38F3_REG_3,
1420 PREFIX_EVEX_0F71_REG_2,
1421 PREFIX_EVEX_0F71_REG_4,
1422 PREFIX_EVEX_0F71_REG_6,
1423 PREFIX_EVEX_0F72_REG_0,
1424 PREFIX_EVEX_0F72_REG_1,
1425 PREFIX_EVEX_0F72_REG_2,
1426 PREFIX_EVEX_0F72_REG_4,
1427 PREFIX_EVEX_0F72_REG_6,
1428 PREFIX_EVEX_0F73_REG_2,
1429 PREFIX_EVEX_0F73_REG_3,
1430 PREFIX_EVEX_0F73_REG_6,
1431 PREFIX_EVEX_0F73_REG_7,
1616 PREFIX_EVEX_0F38C6_REG_1,
1617 PREFIX_EVEX_0F38C6_REG_2,
1618 PREFIX_EVEX_0F38C6_REG_5,
1619 PREFIX_EVEX_0F38C6_REG_6,
1620 PREFIX_EVEX_0F38C7_REG_1,
1621 PREFIX_EVEX_0F38C7_REG_2,
1622 PREFIX_EVEX_0F38C7_REG_5,
1623 PREFIX_EVEX_0F38C7_REG_6,
1713 THREE_BYTE_0F38 = 0,
1740 VEX_LEN_0F10_P_1 = 0,
1744 VEX_LEN_0F12_P_0_M_0,
1745 VEX_LEN_0F12_P_0_M_1,
1748 VEX_LEN_0F16_P_0_M_0,
1749 VEX_LEN_0F16_P_0_M_1,
1813 VEX_LEN_0FAE_R_2_M_0,
1814 VEX_LEN_0FAE_R_3_M_0,
1823 VEX_LEN_0F381A_P_2_M_0,
1826 VEX_LEN_0F385A_P_2_M_0,
1833 VEX_LEN_0F38F3_R_1_P_0,
1834 VEX_LEN_0F38F3_R_2_P_0,
1835 VEX_LEN_0F38F3_R_3_P_0,
1881 VEX_LEN_0FXOP_08_CC,
1882 VEX_LEN_0FXOP_08_CD,
1883 VEX_LEN_0FXOP_08_CE,
1884 VEX_LEN_0FXOP_08_CF,
1885 VEX_LEN_0FXOP_08_EC,
1886 VEX_LEN_0FXOP_08_ED,
1887 VEX_LEN_0FXOP_08_EE,
1888 VEX_LEN_0FXOP_08_EF,
1889 VEX_LEN_0FXOP_09_80,
1923 VEX_W_0F41_P_0_LEN_1,
1924 VEX_W_0F41_P_2_LEN_1,
1925 VEX_W_0F42_P_0_LEN_1,
1926 VEX_W_0F42_P_2_LEN_1,
1927 VEX_W_0F44_P_0_LEN_0,
1928 VEX_W_0F44_P_2_LEN_0,
1929 VEX_W_0F45_P_0_LEN_1,
1930 VEX_W_0F45_P_2_LEN_1,
1931 VEX_W_0F46_P_0_LEN_1,
1932 VEX_W_0F46_P_2_LEN_1,
1933 VEX_W_0F47_P_0_LEN_1,
1934 VEX_W_0F47_P_2_LEN_1,
1935 VEX_W_0F4A_P_0_LEN_1,
1936 VEX_W_0F4A_P_2_LEN_1,
1937 VEX_W_0F4B_P_0_LEN_1,
1938 VEX_W_0F4B_P_2_LEN_1,
2018 VEX_W_0F90_P_0_LEN_0,
2019 VEX_W_0F90_P_2_LEN_0,
2020 VEX_W_0F91_P_0_LEN_0,
2021 VEX_W_0F91_P_2_LEN_0,
2022 VEX_W_0F92_P_0_LEN_0,
2023 VEX_W_0F92_P_2_LEN_0,
2024 VEX_W_0F92_P_3_LEN_0,
2025 VEX_W_0F93_P_0_LEN_0,
2026 VEX_W_0F93_P_2_LEN_0,
2027 VEX_W_0F93_P_3_LEN_0,
2028 VEX_W_0F98_P_0_LEN_0,
2029 VEX_W_0F98_P_2_LEN_0,
2030 VEX_W_0F99_P_0_LEN_0,
2031 VEX_W_0F99_P_2_LEN_0,
2110 VEX_W_0F381A_P_2_M_0,
2122 VEX_W_0F382A_P_2_M_0,
2124 VEX_W_0F382C_P_2_M_0,
2125 VEX_W_0F382D_P_2_M_0,
2126 VEX_W_0F382E_P_2_M_0,
2127 VEX_W_0F382F_P_2_M_0,
2149 VEX_W_0F385A_P_2_M_0,
2177 VEX_W_0F3A30_P_2_LEN_0,
2178 VEX_W_0F3A31_P_2_LEN_0,
2179 VEX_W_0F3A32_P_2_LEN_0,
2180 VEX_W_0F3A33_P_2_LEN_0,
2200 EVEX_W_0F10_P_1_M_0,
2201 EVEX_W_0F10_P_1_M_1,
2203 EVEX_W_0F10_P_3_M_0,
2204 EVEX_W_0F10_P_3_M_1,
2206 EVEX_W_0F11_P_1_M_0,
2207 EVEX_W_0F11_P_1_M_1,
2209 EVEX_W_0F11_P_3_M_0,
2210 EVEX_W_0F11_P_3_M_1,
2211 EVEX_W_0F12_P_0_M_0,
2212 EVEX_W_0F12_P_0_M_1,
2222 EVEX_W_0F16_P_0_M_0,
2223 EVEX_W_0F16_P_0_M_1,
2294 EVEX_W_0F72_R_2_P_2,
2295 EVEX_W_0F72_R_6_P_2,
2296 EVEX_W_0F73_R_2_P_2,
2297 EVEX_W_0F73_R_6_P_2,
2397 EVEX_W_0F38C7_R_1_P_2,
2398 EVEX_W_0F38C7_R_2_P_2,
2399 EVEX_W_0F38C7_R_5_P_2,
2400 EVEX_W_0F38C7_R_6_P_2,
2435 typedef void (*op_rtn) (int bytemode, int sizeflag);
2444 unsigned int prefix_requirement;
2447 /* Upper case letters in the instruction names here are macros.
2448 'A' => print 'b' if no register operands or suffix_always is true
2449 'B' => print 'b' if suffix_always is true
2450 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2452 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2453 suffix_always is true
2454 'E' => print 'e' if 32-bit form of jcxz
2455 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2456 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2457 'H' => print ",pt" or ",pn" branch hint
2458 'I' => honor following macro letter even in Intel mode (implemented only
2459 for some of the macro letters)
2461 'K' => print 'd' or 'q' if rex prefix is present.
2462 'L' => print 'l' if suffix_always is true
2463 'M' => print 'r' if intel_mnemonic is false.
2464 'N' => print 'n' if instruction has no wait "prefix"
2465 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2466 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2467 or suffix_always is true. print 'q' if rex prefix is present.
2468 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2470 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2471 'S' => print 'w', 'l' or 'q' if suffix_always is true
2472 'T' => print 'q' in 64bit mode if instruction has no operand size
2473 prefix and behave as 'P' otherwise
2474 'U' => print 'q' in 64bit mode if instruction has no operand size
2475 prefix and behave as 'Q' otherwise
2476 'V' => print 'q' in 64bit mode if instruction has no operand size
2477 prefix and behave as 'S' otherwise
2478 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2479 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2480 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2481 suffix_always is true.
2482 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2483 '!' => change condition from true to false or from false to true.
2484 '%' => add 1 upper case letter to the macro.
2485 '^' => print 'w' or 'l' depending on operand size prefix or
2486 suffix_always is true (lcall/ljmp).
2487 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2488 on operand size prefix.
2489 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2490 has no operand size prefix for AMD64 ISA, behave as 'P'
2493 2 upper case letter macros:
2494 "XY" => print 'x' or 'y' if suffix_always is true or no register
2495 operands and no broadcast.
2496 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2497 register operands and no broadcast.
2498 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2499 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2500 or suffix_always is true
2501 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2502 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2503 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2504 "LW" => print 'd', 'q' depending on the VEX.W bit
2505 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2506 an operand size prefix, or suffix_always is true. print
2507 'q' if rex prefix is present.
2509 Many of the above letters print nothing in Intel mode. See "putop"
2512 Braces '{' and '}', and vertical bars '|', indicate alternative
2513 mnemonic strings for AT&T and Intel. */
2515 static const struct dis386 dis386[] = {
2517 { "addB", { Ebh1, Gb }, 0 },
2518 { "addS", { Evh1, Gv }, 0 },
2519 { "addB", { Gb, EbS }, 0 },
2520 { "addS", { Gv, EvS }, 0 },
2521 { "addB", { AL, Ib }, 0 },
2522 { "addS", { eAX, Iv }, 0 },
2523 { X86_64_TABLE (X86_64_06) },
2524 { X86_64_TABLE (X86_64_07) },
2526 { "orB", { Ebh1, Gb }, 0 },
2527 { "orS", { Evh1, Gv }, 0 },
2528 { "orB", { Gb, EbS }, 0 },
2529 { "orS", { Gv, EvS }, 0 },
2530 { "orB", { AL, Ib }, 0 },
2531 { "orS", { eAX, Iv }, 0 },
2532 { X86_64_TABLE (X86_64_0D) },
2533 { Bad_Opcode }, /* 0x0f extended opcode escape */
2535 { "adcB", { Ebh1, Gb }, 0 },
2536 { "adcS", { Evh1, Gv }, 0 },
2537 { "adcB", { Gb, EbS }, 0 },
2538 { "adcS", { Gv, EvS }, 0 },
2539 { "adcB", { AL, Ib }, 0 },
2540 { "adcS", { eAX, Iv }, 0 },
2541 { X86_64_TABLE (X86_64_16) },
2542 { X86_64_TABLE (X86_64_17) },
2544 { "sbbB", { Ebh1, Gb }, 0 },
2545 { "sbbS", { Evh1, Gv }, 0 },
2546 { "sbbB", { Gb, EbS }, 0 },
2547 { "sbbS", { Gv, EvS }, 0 },
2548 { "sbbB", { AL, Ib }, 0 },
2549 { "sbbS", { eAX, Iv }, 0 },
2550 { X86_64_TABLE (X86_64_1E) },
2551 { X86_64_TABLE (X86_64_1F) },
2553 { "andB", { Ebh1, Gb }, 0 },
2554 { "andS", { Evh1, Gv }, 0 },
2555 { "andB", { Gb, EbS }, 0 },
2556 { "andS", { Gv, EvS }, 0 },
2557 { "andB", { AL, Ib }, 0 },
2558 { "andS", { eAX, Iv }, 0 },
2559 { Bad_Opcode }, /* SEG ES prefix */
2560 { X86_64_TABLE (X86_64_27) },
2562 { "subB", { Ebh1, Gb }, 0 },
2563 { "subS", { Evh1, Gv }, 0 },
2564 { "subB", { Gb, EbS }, 0 },
2565 { "subS", { Gv, EvS }, 0 },
2566 { "subB", { AL, Ib }, 0 },
2567 { "subS", { eAX, Iv }, 0 },
2568 { Bad_Opcode }, /* SEG CS prefix */
2569 { X86_64_TABLE (X86_64_2F) },
2571 { "xorB", { Ebh1, Gb }, 0 },
2572 { "xorS", { Evh1, Gv }, 0 },
2573 { "xorB", { Gb, EbS }, 0 },
2574 { "xorS", { Gv, EvS }, 0 },
2575 { "xorB", { AL, Ib }, 0 },
2576 { "xorS", { eAX, Iv }, 0 },
2577 { Bad_Opcode }, /* SEG SS prefix */
2578 { X86_64_TABLE (X86_64_37) },
2580 { "cmpB", { Eb, Gb }, 0 },
2581 { "cmpS", { Ev, Gv }, 0 },
2582 { "cmpB", { Gb, EbS }, 0 },
2583 { "cmpS", { Gv, EvS }, 0 },
2584 { "cmpB", { AL, Ib }, 0 },
2585 { "cmpS", { eAX, Iv }, 0 },
2586 { Bad_Opcode }, /* SEG DS prefix */
2587 { X86_64_TABLE (X86_64_3F) },
2589 { "inc{S|}", { RMeAX }, 0 },
2590 { "inc{S|}", { RMeCX }, 0 },
2591 { "inc{S|}", { RMeDX }, 0 },
2592 { "inc{S|}", { RMeBX }, 0 },
2593 { "inc{S|}", { RMeSP }, 0 },
2594 { "inc{S|}", { RMeBP }, 0 },
2595 { "inc{S|}", { RMeSI }, 0 },
2596 { "inc{S|}", { RMeDI }, 0 },
2598 { "dec{S|}", { RMeAX }, 0 },
2599 { "dec{S|}", { RMeCX }, 0 },
2600 { "dec{S|}", { RMeDX }, 0 },
2601 { "dec{S|}", { RMeBX }, 0 },
2602 { "dec{S|}", { RMeSP }, 0 },
2603 { "dec{S|}", { RMeBP }, 0 },
2604 { "dec{S|}", { RMeSI }, 0 },
2605 { "dec{S|}", { RMeDI }, 0 },
2607 { "pushV", { RMrAX }, 0 },
2608 { "pushV", { RMrCX }, 0 },
2609 { "pushV", { RMrDX }, 0 },
2610 { "pushV", { RMrBX }, 0 },
2611 { "pushV", { RMrSP }, 0 },
2612 { "pushV", { RMrBP }, 0 },
2613 { "pushV", { RMrSI }, 0 },
2614 { "pushV", { RMrDI }, 0 },
2616 { "popV", { RMrAX }, 0 },
2617 { "popV", { RMrCX }, 0 },
2618 { "popV", { RMrDX }, 0 },
2619 { "popV", { RMrBX }, 0 },
2620 { "popV", { RMrSP }, 0 },
2621 { "popV", { RMrBP }, 0 },
2622 { "popV", { RMrSI }, 0 },
2623 { "popV", { RMrDI }, 0 },
2625 { X86_64_TABLE (X86_64_60) },
2626 { X86_64_TABLE (X86_64_61) },
2627 { X86_64_TABLE (X86_64_62) },
2628 { X86_64_TABLE (X86_64_63) },
2629 { Bad_Opcode }, /* seg fs */
2630 { Bad_Opcode }, /* seg gs */
2631 { Bad_Opcode }, /* op size prefix */
2632 { Bad_Opcode }, /* adr size prefix */
2634 { "pushT", { sIv }, 0 },
2635 { "imulS", { Gv, Ev, Iv }, 0 },
2636 { "pushT", { sIbT }, 0 },
2637 { "imulS", { Gv, Ev, sIb }, 0 },
2638 { "ins{b|}", { Ybr, indirDX }, 0 },
2639 { X86_64_TABLE (X86_64_6D) },
2640 { "outs{b|}", { indirDXr, Xb }, 0 },
2641 { X86_64_TABLE (X86_64_6F) },
2643 { "joH", { Jb, BND, cond_jump_flag }, 0 },
2644 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
2645 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
2646 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
2647 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
2648 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
2649 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
2650 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
2652 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
2653 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
2654 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
2655 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
2656 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
2657 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
2658 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
2659 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
2661 { REG_TABLE (REG_80) },
2662 { REG_TABLE (REG_81) },
2663 { X86_64_TABLE (X86_64_82) },
2664 { REG_TABLE (REG_83) },
2665 { "testB", { Eb, Gb }, 0 },
2666 { "testS", { Ev, Gv }, 0 },
2667 { "xchgB", { Ebh2, Gb }, 0 },
2668 { "xchgS", { Evh2, Gv }, 0 },
2670 { "movB", { Ebh3, Gb }, 0 },
2671 { "movS", { Evh3, Gv }, 0 },
2672 { "movB", { Gb, EbS }, 0 },
2673 { "movS", { Gv, EvS }, 0 },
2674 { "movD", { Sv, Sw }, 0 },
2675 { MOD_TABLE (MOD_8D) },
2676 { "movD", { Sw, Sv }, 0 },
2677 { REG_TABLE (REG_8F) },
2679 { PREFIX_TABLE (PREFIX_90) },
2680 { "xchgS", { RMeCX, eAX }, 0 },
2681 { "xchgS", { RMeDX, eAX }, 0 },
2682 { "xchgS", { RMeBX, eAX }, 0 },
2683 { "xchgS", { RMeSP, eAX }, 0 },
2684 { "xchgS", { RMeBP, eAX }, 0 },
2685 { "xchgS", { RMeSI, eAX }, 0 },
2686 { "xchgS", { RMeDI, eAX }, 0 },
2688 { "cW{t|}R", { XX }, 0 },
2689 { "cR{t|}O", { XX }, 0 },
2690 { X86_64_TABLE (X86_64_9A) },
2691 { Bad_Opcode }, /* fwait */
2692 { "pushfT", { XX }, 0 },
2693 { "popfT", { XX }, 0 },
2694 { "sahf", { XX }, 0 },
2695 { "lahf", { XX }, 0 },
2697 { "mov%LB", { AL, Ob }, 0 },
2698 { "mov%LS", { eAX, Ov }, 0 },
2699 { "mov%LB", { Ob, AL }, 0 },
2700 { "mov%LS", { Ov, eAX }, 0 },
2701 { "movs{b|}", { Ybr, Xb }, 0 },
2702 { "movs{R|}", { Yvr, Xv }, 0 },
2703 { "cmps{b|}", { Xb, Yb }, 0 },
2704 { "cmps{R|}", { Xv, Yv }, 0 },
2706 { "testB", { AL, Ib }, 0 },
2707 { "testS", { eAX, Iv }, 0 },
2708 { "stosB", { Ybr, AL }, 0 },
2709 { "stosS", { Yvr, eAX }, 0 },
2710 { "lodsB", { ALr, Xb }, 0 },
2711 { "lodsS", { eAXr, Xv }, 0 },
2712 { "scasB", { AL, Yb }, 0 },
2713 { "scasS", { eAX, Yv }, 0 },
2715 { "movB", { RMAL, Ib }, 0 },
2716 { "movB", { RMCL, Ib }, 0 },
2717 { "movB", { RMDL, Ib }, 0 },
2718 { "movB", { RMBL, Ib }, 0 },
2719 { "movB", { RMAH, Ib }, 0 },
2720 { "movB", { RMCH, Ib }, 0 },
2721 { "movB", { RMDH, Ib }, 0 },
2722 { "movB", { RMBH, Ib }, 0 },
2724 { "mov%LV", { RMeAX, Iv64 }, 0 },
2725 { "mov%LV", { RMeCX, Iv64 }, 0 },
2726 { "mov%LV", { RMeDX, Iv64 }, 0 },
2727 { "mov%LV", { RMeBX, Iv64 }, 0 },
2728 { "mov%LV", { RMeSP, Iv64 }, 0 },
2729 { "mov%LV", { RMeBP, Iv64 }, 0 },
2730 { "mov%LV", { RMeSI, Iv64 }, 0 },
2731 { "mov%LV", { RMeDI, Iv64 }, 0 },
2733 { REG_TABLE (REG_C0) },
2734 { REG_TABLE (REG_C1) },
2735 { "retT", { Iw, BND }, 0 },
2736 { "retT", { BND }, 0 },
2737 { X86_64_TABLE (X86_64_C4) },
2738 { X86_64_TABLE (X86_64_C5) },
2739 { REG_TABLE (REG_C6) },
2740 { REG_TABLE (REG_C7) },
2742 { "enterT", { Iw, Ib }, 0 },
2743 { "leaveT", { XX }, 0 },
2744 { "Jret{|f}P", { Iw }, 0 },
2745 { "Jret{|f}P", { XX }, 0 },
2746 { "int3", { XX }, 0 },
2747 { "int", { Ib }, 0 },
2748 { X86_64_TABLE (X86_64_CE) },
2749 { "iret%LP", { XX }, 0 },
2751 { REG_TABLE (REG_D0) },
2752 { REG_TABLE (REG_D1) },
2753 { REG_TABLE (REG_D2) },
2754 { REG_TABLE (REG_D3) },
2755 { X86_64_TABLE (X86_64_D4) },
2756 { X86_64_TABLE (X86_64_D5) },
2758 { "xlat", { DSBX }, 0 },
2769 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2770 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2771 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2772 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2773 { "inB", { AL, Ib }, 0 },
2774 { "inG", { zAX, Ib }, 0 },
2775 { "outB", { Ib, AL }, 0 },
2776 { "outG", { Ib, zAX }, 0 },
2778 { X86_64_TABLE (X86_64_E8) },
2779 { X86_64_TABLE (X86_64_E9) },
2780 { X86_64_TABLE (X86_64_EA) },
2781 { "jmp", { Jb, BND }, 0 },
2782 { "inB", { AL, indirDX }, 0 },
2783 { "inG", { zAX, indirDX }, 0 },
2784 { "outB", { indirDX, AL }, 0 },
2785 { "outG", { indirDX, zAX }, 0 },
2787 { Bad_Opcode }, /* lock prefix */
2788 { "icebp", { XX }, 0 },
2789 { Bad_Opcode }, /* repne */
2790 { Bad_Opcode }, /* repz */
2791 { "hlt", { XX }, 0 },
2792 { "cmc", { XX }, 0 },
2793 { REG_TABLE (REG_F6) },
2794 { REG_TABLE (REG_F7) },
2796 { "clc", { XX }, 0 },
2797 { "stc", { XX }, 0 },
2798 { "cli", { XX }, 0 },
2799 { "sti", { XX }, 0 },
2800 { "cld", { XX }, 0 },
2801 { "std", { XX }, 0 },
2802 { REG_TABLE (REG_FE) },
2803 { REG_TABLE (REG_FF) },
2806 static const struct dis386 dis386_twobyte[] = {
2808 { REG_TABLE (REG_0F00 ) },
2809 { REG_TABLE (REG_0F01 ) },
2810 { "larS", { Gv, Ew }, 0 },
2811 { "lslS", { Gv, Ew }, 0 },
2813 { "syscall", { XX }, 0 },
2814 { "clts", { XX }, 0 },
2815 { "sysret%LP", { XX }, 0 },
2817 { "invd", { XX }, 0 },
2818 { "wbinvd", { XX }, 0 },
2820 { "ud2", { XX }, 0 },
2822 { REG_TABLE (REG_0F0D) },
2823 { "femms", { XX }, 0 },
2824 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2826 { PREFIX_TABLE (PREFIX_0F10) },
2827 { PREFIX_TABLE (PREFIX_0F11) },
2828 { PREFIX_TABLE (PREFIX_0F12) },
2829 { MOD_TABLE (MOD_0F13) },
2830 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2831 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2832 { PREFIX_TABLE (PREFIX_0F16) },
2833 { MOD_TABLE (MOD_0F17) },
2835 { REG_TABLE (REG_0F18) },
2836 { "nopQ", { Ev }, 0 },
2837 { PREFIX_TABLE (PREFIX_0F1A) },
2838 { PREFIX_TABLE (PREFIX_0F1B) },
2839 { "nopQ", { Ev }, 0 },
2840 { "nopQ", { Ev }, 0 },
2841 { "nopQ", { Ev }, 0 },
2842 { "nopQ", { Ev }, 0 },
2844 { "movZ", { Rm, Cm }, 0 },
2845 { "movZ", { Rm, Dm }, 0 },
2846 { "movZ", { Cm, Rm }, 0 },
2847 { "movZ", { Dm, Rm }, 0 },
2848 { MOD_TABLE (MOD_0F24) },
2850 { MOD_TABLE (MOD_0F26) },
2853 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2854 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2855 { PREFIX_TABLE (PREFIX_0F2A) },
2856 { PREFIX_TABLE (PREFIX_0F2B) },
2857 { PREFIX_TABLE (PREFIX_0F2C) },
2858 { PREFIX_TABLE (PREFIX_0F2D) },
2859 { PREFIX_TABLE (PREFIX_0F2E) },
2860 { PREFIX_TABLE (PREFIX_0F2F) },
2862 { "wrmsr", { XX }, 0 },
2863 { "rdtsc", { XX }, 0 },
2864 { "rdmsr", { XX }, 0 },
2865 { "rdpmc", { XX }, 0 },
2866 { "sysenter", { XX }, 0 },
2867 { "sysexit", { XX }, 0 },
2869 { "getsec", { XX }, 0 },
2871 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2873 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2880 { "cmovoS", { Gv, Ev }, 0 },
2881 { "cmovnoS", { Gv, Ev }, 0 },
2882 { "cmovbS", { Gv, Ev }, 0 },
2883 { "cmovaeS", { Gv, Ev }, 0 },
2884 { "cmoveS", { Gv, Ev }, 0 },
2885 { "cmovneS", { Gv, Ev }, 0 },
2886 { "cmovbeS", { Gv, Ev }, 0 },
2887 { "cmovaS", { Gv, Ev }, 0 },
2889 { "cmovsS", { Gv, Ev }, 0 },
2890 { "cmovnsS", { Gv, Ev }, 0 },
2891 { "cmovpS", { Gv, Ev }, 0 },
2892 { "cmovnpS", { Gv, Ev }, 0 },
2893 { "cmovlS", { Gv, Ev }, 0 },
2894 { "cmovgeS", { Gv, Ev }, 0 },
2895 { "cmovleS", { Gv, Ev }, 0 },
2896 { "cmovgS", { Gv, Ev }, 0 },
2898 { MOD_TABLE (MOD_0F51) },
2899 { PREFIX_TABLE (PREFIX_0F51) },
2900 { PREFIX_TABLE (PREFIX_0F52) },
2901 { PREFIX_TABLE (PREFIX_0F53) },
2902 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2903 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2904 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2905 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2907 { PREFIX_TABLE (PREFIX_0F58) },
2908 { PREFIX_TABLE (PREFIX_0F59) },
2909 { PREFIX_TABLE (PREFIX_0F5A) },
2910 { PREFIX_TABLE (PREFIX_0F5B) },
2911 { PREFIX_TABLE (PREFIX_0F5C) },
2912 { PREFIX_TABLE (PREFIX_0F5D) },
2913 { PREFIX_TABLE (PREFIX_0F5E) },
2914 { PREFIX_TABLE (PREFIX_0F5F) },
2916 { PREFIX_TABLE (PREFIX_0F60) },
2917 { PREFIX_TABLE (PREFIX_0F61) },
2918 { PREFIX_TABLE (PREFIX_0F62) },
2919 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2920 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2921 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2922 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2923 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2925 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2926 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2927 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2928 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2929 { PREFIX_TABLE (PREFIX_0F6C) },
2930 { PREFIX_TABLE (PREFIX_0F6D) },
2931 { "movK", { MX, Edq }, PREFIX_OPCODE },
2932 { PREFIX_TABLE (PREFIX_0F6F) },
2934 { PREFIX_TABLE (PREFIX_0F70) },
2935 { REG_TABLE (REG_0F71) },
2936 { REG_TABLE (REG_0F72) },
2937 { REG_TABLE (REG_0F73) },
2938 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2939 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2940 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2941 { "emms", { XX }, PREFIX_OPCODE },
2943 { PREFIX_TABLE (PREFIX_0F78) },
2944 { PREFIX_TABLE (PREFIX_0F79) },
2947 { PREFIX_TABLE (PREFIX_0F7C) },
2948 { PREFIX_TABLE (PREFIX_0F7D) },
2949 { PREFIX_TABLE (PREFIX_0F7E) },
2950 { PREFIX_TABLE (PREFIX_0F7F) },
2952 { "joH", { Jv, BND, cond_jump_flag }, 0 },
2953 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
2954 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
2955 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
2956 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
2957 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
2958 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
2959 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
2961 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
2962 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
2963 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
2964 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
2965 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
2966 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
2967 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
2968 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
2970 { "seto", { Eb }, 0 },
2971 { "setno", { Eb }, 0 },
2972 { "setb", { Eb }, 0 },
2973 { "setae", { Eb }, 0 },
2974 { "sete", { Eb }, 0 },
2975 { "setne", { Eb }, 0 },
2976 { "setbe", { Eb }, 0 },
2977 { "seta", { Eb }, 0 },
2979 { "sets", { Eb }, 0 },
2980 { "setns", { Eb }, 0 },
2981 { "setp", { Eb }, 0 },
2982 { "setnp", { Eb }, 0 },
2983 { "setl", { Eb }, 0 },
2984 { "setge", { Eb }, 0 },
2985 { "setle", { Eb }, 0 },
2986 { "setg", { Eb }, 0 },
2988 { "pushT", { fs }, 0 },
2989 { "popT", { fs }, 0 },
2990 { "cpuid", { XX }, 0 },
2991 { "btS", { Ev, Gv }, 0 },
2992 { "shldS", { Ev, Gv, Ib }, 0 },
2993 { "shldS", { Ev, Gv, CL }, 0 },
2994 { REG_TABLE (REG_0FA6) },
2995 { REG_TABLE (REG_0FA7) },
2997 { "pushT", { gs }, 0 },
2998 { "popT", { gs }, 0 },
2999 { "rsm", { XX }, 0 },
3000 { "btsS", { Evh1, Gv }, 0 },
3001 { "shrdS", { Ev, Gv, Ib }, 0 },
3002 { "shrdS", { Ev, Gv, CL }, 0 },
3003 { REG_TABLE (REG_0FAE) },
3004 { "imulS", { Gv, Ev }, 0 },
3006 { "cmpxchgB", { Ebh1, Gb }, 0 },
3007 { "cmpxchgS", { Evh1, Gv }, 0 },
3008 { MOD_TABLE (MOD_0FB2) },
3009 { "btrS", { Evh1, Gv }, 0 },
3010 { MOD_TABLE (MOD_0FB4) },
3011 { MOD_TABLE (MOD_0FB5) },
3012 { "movz{bR|x}", { Gv, Eb }, 0 },
3013 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3015 { PREFIX_TABLE (PREFIX_0FB8) },
3016 { "ud1", { XX }, 0 },
3017 { REG_TABLE (REG_0FBA) },
3018 { "btcS", { Evh1, Gv }, 0 },
3019 { PREFIX_TABLE (PREFIX_0FBC) },
3020 { PREFIX_TABLE (PREFIX_0FBD) },
3021 { "movs{bR|x}", { Gv, Eb }, 0 },
3022 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3024 { "xaddB", { Ebh1, Gb }, 0 },
3025 { "xaddS", { Evh1, Gv }, 0 },
3026 { PREFIX_TABLE (PREFIX_0FC2) },
3027 { MOD_TABLE (MOD_0FC3) },
3028 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
3029 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
3030 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
3031 { REG_TABLE (REG_0FC7) },
3033 { "bswap", { RMeAX }, 0 },
3034 { "bswap", { RMeCX }, 0 },
3035 { "bswap", { RMeDX }, 0 },
3036 { "bswap", { RMeBX }, 0 },
3037 { "bswap", { RMeSP }, 0 },
3038 { "bswap", { RMeBP }, 0 },
3039 { "bswap", { RMeSI }, 0 },
3040 { "bswap", { RMeDI }, 0 },
3042 { PREFIX_TABLE (PREFIX_0FD0) },
3043 { "psrlw", { MX, EM }, PREFIX_OPCODE },
3044 { "psrld", { MX, EM }, PREFIX_OPCODE },
3045 { "psrlq", { MX, EM }, PREFIX_OPCODE },
3046 { "paddq", { MX, EM }, PREFIX_OPCODE },
3047 { "pmullw", { MX, EM }, PREFIX_OPCODE },
3048 { PREFIX_TABLE (PREFIX_0FD6) },
3049 { MOD_TABLE (MOD_0FD7) },
3051 { "psubusb", { MX, EM }, PREFIX_OPCODE },
3052 { "psubusw", { MX, EM }, PREFIX_OPCODE },
3053 { "pminub", { MX, EM }, PREFIX_OPCODE },
3054 { "pand", { MX, EM }, PREFIX_OPCODE },
3055 { "paddusb", { MX, EM }, PREFIX_OPCODE },
3056 { "paddusw", { MX, EM }, PREFIX_OPCODE },
3057 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
3058 { "pandn", { MX, EM }, PREFIX_OPCODE },
3060 { "pavgb", { MX, EM }, PREFIX_OPCODE },
3061 { "psraw", { MX, EM }, PREFIX_OPCODE },
3062 { "psrad", { MX, EM }, PREFIX_OPCODE },
3063 { "pavgw", { MX, EM }, PREFIX_OPCODE },
3064 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
3065 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
3066 { PREFIX_TABLE (PREFIX_0FE6) },
3067 { PREFIX_TABLE (PREFIX_0FE7) },
3069 { "psubsb", { MX, EM }, PREFIX_OPCODE },
3070 { "psubsw", { MX, EM }, PREFIX_OPCODE },
3071 { "pminsw", { MX, EM }, PREFIX_OPCODE },
3072 { "por", { MX, EM }, PREFIX_OPCODE },
3073 { "paddsb", { MX, EM }, PREFIX_OPCODE },
3074 { "paddsw", { MX, EM }, PREFIX_OPCODE },
3075 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
3076 { "pxor", { MX, EM }, PREFIX_OPCODE },
3078 { PREFIX_TABLE (PREFIX_0FF0) },
3079 { "psllw", { MX, EM }, PREFIX_OPCODE },
3080 { "pslld", { MX, EM }, PREFIX_OPCODE },
3081 { "psllq", { MX, EM }, PREFIX_OPCODE },
3082 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
3083 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
3084 { "psadbw", { MX, EM }, PREFIX_OPCODE },
3085 { PREFIX_TABLE (PREFIX_0FF7) },
3087 { "psubb", { MX, EM }, PREFIX_OPCODE },
3088 { "psubw", { MX, EM }, PREFIX_OPCODE },
3089 { "psubd", { MX, EM }, PREFIX_OPCODE },
3090 { "psubq", { MX, EM }, PREFIX_OPCODE },
3091 { "paddb", { MX, EM }, PREFIX_OPCODE },
3092 { "paddw", { MX, EM }, PREFIX_OPCODE },
3093 { "paddd", { MX, EM }, PREFIX_OPCODE },
3097 static const unsigned char onebyte_has_modrm[256] = {
3098 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3099 /* ------------------------------- */
3100 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3101 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3102 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3103 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3104 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3105 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3106 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3107 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3108 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3109 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3110 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3111 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3112 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3113 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3114 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3115 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3116 /* ------------------------------- */
3117 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3120 static const unsigned char twobyte_has_modrm[256] = {
3121 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3122 /* ------------------------------- */
3123 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3124 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3125 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3126 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3127 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3128 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3129 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3130 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3131 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3132 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3133 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3134 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3135 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3136 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3137 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3138 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3139 /* ------------------------------- */
3140 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3143 static char obuf[100];
3145 static char *mnemonicendp;
3146 static char scratchbuf[100];
3147 static unsigned char *start_codep;
3148 static unsigned char *insn_codep;
3149 static unsigned char *codep;
3150 static unsigned char *end_codep;
3151 static int last_lock_prefix;
3152 static int last_repz_prefix;
3153 static int last_repnz_prefix;
3154 static int last_data_prefix;
3155 static int last_addr_prefix;
3156 static int last_rex_prefix;
3157 static int last_seg_prefix;
3158 static int fwait_prefix;
3159 /* The active segment register prefix. */
3160 static int active_seg_prefix;
3161 #define MAX_CODE_LENGTH 15
3162 /* We can up to 14 prefixes since the maximum instruction length is
3164 static int all_prefixes[MAX_CODE_LENGTH - 1];
3165 static disassemble_info *the_info;
3173 static unsigned char need_modrm;
3183 int register_specifier;
3190 int mask_register_specifier;
3196 static unsigned char need_vex;
3197 static unsigned char need_vex_reg;
3198 static unsigned char vex_w_done;
3206 /* If we are accessing mod/rm/reg without need_modrm set, then the
3207 values are stale. Hitting this abort likely indicates that you
3208 need to update onebyte_has_modrm or twobyte_has_modrm. */
3209 #define MODRM_CHECK if (!need_modrm) abort ()
3211 static const char **names64;
3212 static const char **names32;
3213 static const char **names16;
3214 static const char **names8;
3215 static const char **names8rex;
3216 static const char **names_seg;
3217 static const char *index64;
3218 static const char *index32;
3219 static const char **index16;
3220 static const char **names_bnd;
3222 static const char *intel_names64[] = {
3223 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3224 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3226 static const char *intel_names32[] = {
3227 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3228 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3230 static const char *intel_names16[] = {
3231 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3232 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3234 static const char *intel_names8[] = {
3235 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3237 static const char *intel_names8rex[] = {
3238 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3239 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3241 static const char *intel_names_seg[] = {
3242 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3244 static const char *intel_index64 = "riz";
3245 static const char *intel_index32 = "eiz";
3246 static const char *intel_index16[] = {
3247 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3250 static const char *att_names64[] = {
3251 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3252 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3254 static const char *att_names32[] = {
3255 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3256 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3258 static const char *att_names16[] = {
3259 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3260 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3262 static const char *att_names8[] = {
3263 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3265 static const char *att_names8rex[] = {
3266 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3267 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3269 static const char *att_names_seg[] = {
3270 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3272 static const char *att_index64 = "%riz";
3273 static const char *att_index32 = "%eiz";
3274 static const char *att_index16[] = {
3275 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3278 static const char **names_mm;
3279 static const char *intel_names_mm[] = {
3280 "mm0", "mm1", "mm2", "mm3",
3281 "mm4", "mm5", "mm6", "mm7"
3283 static const char *att_names_mm[] = {
3284 "%mm0", "%mm1", "%mm2", "%mm3",
3285 "%mm4", "%mm5", "%mm6", "%mm7"
3288 static const char *intel_names_bnd[] = {
3289 "bnd0", "bnd1", "bnd2", "bnd3"
3292 static const char *att_names_bnd[] = {
3293 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3296 static const char **names_xmm;
3297 static const char *intel_names_xmm[] = {
3298 "xmm0", "xmm1", "xmm2", "xmm3",
3299 "xmm4", "xmm5", "xmm6", "xmm7",
3300 "xmm8", "xmm9", "xmm10", "xmm11",
3301 "xmm12", "xmm13", "xmm14", "xmm15",
3302 "xmm16", "xmm17", "xmm18", "xmm19",
3303 "xmm20", "xmm21", "xmm22", "xmm23",
3304 "xmm24", "xmm25", "xmm26", "xmm27",
3305 "xmm28", "xmm29", "xmm30", "xmm31"
3307 static const char *att_names_xmm[] = {
3308 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3309 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3310 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3311 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3312 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3313 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3314 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3315 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3318 static const char **names_ymm;
3319 static const char *intel_names_ymm[] = {
3320 "ymm0", "ymm1", "ymm2", "ymm3",
3321 "ymm4", "ymm5", "ymm6", "ymm7",
3322 "ymm8", "ymm9", "ymm10", "ymm11",
3323 "ymm12", "ymm13", "ymm14", "ymm15",
3324 "ymm16", "ymm17", "ymm18", "ymm19",
3325 "ymm20", "ymm21", "ymm22", "ymm23",
3326 "ymm24", "ymm25", "ymm26", "ymm27",
3327 "ymm28", "ymm29", "ymm30", "ymm31"
3329 static const char *att_names_ymm[] = {
3330 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3331 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3332 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3333 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3334 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3335 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3336 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3337 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3340 static const char **names_zmm;
3341 static const char *intel_names_zmm[] = {
3342 "zmm0", "zmm1", "zmm2", "zmm3",
3343 "zmm4", "zmm5", "zmm6", "zmm7",
3344 "zmm8", "zmm9", "zmm10", "zmm11",
3345 "zmm12", "zmm13", "zmm14", "zmm15",
3346 "zmm16", "zmm17", "zmm18", "zmm19",
3347 "zmm20", "zmm21", "zmm22", "zmm23",
3348 "zmm24", "zmm25", "zmm26", "zmm27",
3349 "zmm28", "zmm29", "zmm30", "zmm31"
3351 static const char *att_names_zmm[] = {
3352 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3353 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3354 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3355 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3356 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3357 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3358 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3359 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3362 static const char **names_mask;
3363 static const char *intel_names_mask[] = {
3364 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3366 static const char *att_names_mask[] = {
3367 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3370 static const char *names_rounding[] =
3378 static const struct dis386 reg_table[][8] = {
3381 { "addA", { Ebh1, Ib }, 0 },
3382 { "orA", { Ebh1, Ib }, 0 },
3383 { "adcA", { Ebh1, Ib }, 0 },
3384 { "sbbA", { Ebh1, Ib }, 0 },
3385 { "andA", { Ebh1, Ib }, 0 },
3386 { "subA", { Ebh1, Ib }, 0 },
3387 { "xorA", { Ebh1, Ib }, 0 },
3388 { "cmpA", { Eb, Ib }, 0 },
3392 { "addQ", { Evh1, Iv }, 0 },
3393 { "orQ", { Evh1, Iv }, 0 },
3394 { "adcQ", { Evh1, Iv }, 0 },
3395 { "sbbQ", { Evh1, Iv }, 0 },
3396 { "andQ", { Evh1, Iv }, 0 },
3397 { "subQ", { Evh1, Iv }, 0 },
3398 { "xorQ", { Evh1, Iv }, 0 },
3399 { "cmpQ", { Ev, Iv }, 0 },
3403 { "addQ", { Evh1, sIb }, 0 },
3404 { "orQ", { Evh1, sIb }, 0 },
3405 { "adcQ", { Evh1, sIb }, 0 },
3406 { "sbbQ", { Evh1, sIb }, 0 },
3407 { "andQ", { Evh1, sIb }, 0 },
3408 { "subQ", { Evh1, sIb }, 0 },
3409 { "xorQ", { Evh1, sIb }, 0 },
3410 { "cmpQ", { Ev, sIb }, 0 },
3414 { "popU", { stackEv }, 0 },
3415 { XOP_8F_TABLE (XOP_09) },
3419 { XOP_8F_TABLE (XOP_09) },
3423 { "rolA", { Eb, Ib }, 0 },
3424 { "rorA", { Eb, Ib }, 0 },
3425 { "rclA", { Eb, Ib }, 0 },
3426 { "rcrA", { Eb, Ib }, 0 },
3427 { "shlA", { Eb, Ib }, 0 },
3428 { "shrA", { Eb, Ib }, 0 },
3430 { "sarA", { Eb, Ib }, 0 },
3434 { "rolQ", { Ev, Ib }, 0 },
3435 { "rorQ", { Ev, Ib }, 0 },
3436 { "rclQ", { Ev, Ib }, 0 },
3437 { "rcrQ", { Ev, Ib }, 0 },
3438 { "shlQ", { Ev, Ib }, 0 },
3439 { "shrQ", { Ev, Ib }, 0 },
3441 { "sarQ", { Ev, Ib }, 0 },
3445 { "movA", { Ebh3, Ib }, 0 },
3452 { MOD_TABLE (MOD_C6_REG_7) },
3456 { "movQ", { Evh3, Iv }, 0 },
3463 { MOD_TABLE (MOD_C7_REG_7) },
3467 { "rolA", { Eb, I1 }, 0 },
3468 { "rorA", { Eb, I1 }, 0 },
3469 { "rclA", { Eb, I1 }, 0 },
3470 { "rcrA", { Eb, I1 }, 0 },
3471 { "shlA", { Eb, I1 }, 0 },
3472 { "shrA", { Eb, I1 }, 0 },
3474 { "sarA", { Eb, I1 }, 0 },
3478 { "rolQ", { Ev, I1 }, 0 },
3479 { "rorQ", { Ev, I1 }, 0 },
3480 { "rclQ", { Ev, I1 }, 0 },
3481 { "rcrQ", { Ev, I1 }, 0 },
3482 { "shlQ", { Ev, I1 }, 0 },
3483 { "shrQ", { Ev, I1 }, 0 },
3485 { "sarQ", { Ev, I1 }, 0 },
3489 { "rolA", { Eb, CL }, 0 },
3490 { "rorA", { Eb, CL }, 0 },
3491 { "rclA", { Eb, CL }, 0 },
3492 { "rcrA", { Eb, CL }, 0 },
3493 { "shlA", { Eb, CL }, 0 },
3494 { "shrA", { Eb, CL }, 0 },
3496 { "sarA", { Eb, CL }, 0 },
3500 { "rolQ", { Ev, CL }, 0 },
3501 { "rorQ", { Ev, CL }, 0 },
3502 { "rclQ", { Ev, CL }, 0 },
3503 { "rcrQ", { Ev, CL }, 0 },
3504 { "shlQ", { Ev, CL }, 0 },
3505 { "shrQ", { Ev, CL }, 0 },
3507 { "sarQ", { Ev, CL }, 0 },
3511 { "testA", { Eb, Ib }, 0 },
3513 { "notA", { Ebh1 }, 0 },
3514 { "negA", { Ebh1 }, 0 },
3515 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
3516 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
3517 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
3518 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
3522 { "testQ", { Ev, Iv }, 0 },
3524 { "notQ", { Evh1 }, 0 },
3525 { "negQ", { Evh1 }, 0 },
3526 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
3527 { "imulQ", { Ev }, 0 },
3528 { "divQ", { Ev }, 0 },
3529 { "idivQ", { Ev }, 0 },
3533 { "incA", { Ebh1 }, 0 },
3534 { "decA", { Ebh1 }, 0 },
3538 { "incQ", { Evh1 }, 0 },
3539 { "decQ", { Evh1 }, 0 },
3540 { "call{&|}", { indirEv, BND }, 0 },
3541 { MOD_TABLE (MOD_FF_REG_3) },
3542 { "jmp{&|}", { indirEv, BND }, 0 },
3543 { MOD_TABLE (MOD_FF_REG_5) },
3544 { "pushU", { stackEv }, 0 },
3549 { "sldtD", { Sv }, 0 },
3550 { "strD", { Sv }, 0 },
3551 { "lldt", { Ew }, 0 },
3552 { "ltr", { Ew }, 0 },
3553 { "verr", { Ew }, 0 },
3554 { "verw", { Ew }, 0 },
3560 { MOD_TABLE (MOD_0F01_REG_0) },
3561 { MOD_TABLE (MOD_0F01_REG_1) },
3562 { MOD_TABLE (MOD_0F01_REG_2) },
3563 { MOD_TABLE (MOD_0F01_REG_3) },
3564 { "smswD", { Sv }, 0 },
3565 { MOD_TABLE (MOD_0F01_REG_5) },
3566 { "lmsw", { Ew }, 0 },
3567 { MOD_TABLE (MOD_0F01_REG_7) },
3571 { "prefetch", { Mb }, 0 },
3572 { "prefetchw", { Mb }, 0 },
3573 { "prefetchwt1", { Mb }, 0 },
3574 { "prefetch", { Mb }, 0 },
3575 { "prefetch", { Mb }, 0 },
3576 { "prefetch", { Mb }, 0 },
3577 { "prefetch", { Mb }, 0 },
3578 { "prefetch", { Mb }, 0 },
3582 { MOD_TABLE (MOD_0F18_REG_0) },
3583 { MOD_TABLE (MOD_0F18_REG_1) },
3584 { MOD_TABLE (MOD_0F18_REG_2) },
3585 { MOD_TABLE (MOD_0F18_REG_3) },
3586 { MOD_TABLE (MOD_0F18_REG_4) },
3587 { MOD_TABLE (MOD_0F18_REG_5) },
3588 { MOD_TABLE (MOD_0F18_REG_6) },
3589 { MOD_TABLE (MOD_0F18_REG_7) },
3595 { MOD_TABLE (MOD_0F71_REG_2) },
3597 { MOD_TABLE (MOD_0F71_REG_4) },
3599 { MOD_TABLE (MOD_0F71_REG_6) },
3605 { MOD_TABLE (MOD_0F72_REG_2) },
3607 { MOD_TABLE (MOD_0F72_REG_4) },
3609 { MOD_TABLE (MOD_0F72_REG_6) },
3615 { MOD_TABLE (MOD_0F73_REG_2) },
3616 { MOD_TABLE (MOD_0F73_REG_3) },
3619 { MOD_TABLE (MOD_0F73_REG_6) },
3620 { MOD_TABLE (MOD_0F73_REG_7) },
3624 { "montmul", { { OP_0f07, 0 } }, 0 },
3625 { "xsha1", { { OP_0f07, 0 } }, 0 },
3626 { "xsha256", { { OP_0f07, 0 } }, 0 },
3630 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
3631 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
3632 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
3633 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
3634 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
3635 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
3639 { MOD_TABLE (MOD_0FAE_REG_0) },
3640 { MOD_TABLE (MOD_0FAE_REG_1) },
3641 { MOD_TABLE (MOD_0FAE_REG_2) },
3642 { MOD_TABLE (MOD_0FAE_REG_3) },
3643 { MOD_TABLE (MOD_0FAE_REG_4) },
3644 { MOD_TABLE (MOD_0FAE_REG_5) },
3645 { MOD_TABLE (MOD_0FAE_REG_6) },
3646 { MOD_TABLE (MOD_0FAE_REG_7) },
3654 { "btQ", { Ev, Ib }, 0 },
3655 { "btsQ", { Evh1, Ib }, 0 },
3656 { "btrQ", { Evh1, Ib }, 0 },
3657 { "btcQ", { Evh1, Ib }, 0 },
3662 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3664 { MOD_TABLE (MOD_0FC7_REG_3) },
3665 { MOD_TABLE (MOD_0FC7_REG_4) },
3666 { MOD_TABLE (MOD_0FC7_REG_5) },
3667 { MOD_TABLE (MOD_0FC7_REG_6) },
3668 { MOD_TABLE (MOD_0FC7_REG_7) },
3674 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3676 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3678 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3684 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3686 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3688 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3694 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3695 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3698 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3699 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3705 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3706 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3708 /* REG_VEX_0F38F3 */
3711 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3712 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3713 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3717 { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3718 { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3722 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3723 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3725 /* REG_XOP_TBM_01 */
3728 { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3729 { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3730 { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 },
3731 { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3732 { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 },
3733 { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 },
3734 { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3736 /* REG_XOP_TBM_02 */
3739 { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3744 { "blci", { { OP_LWP_E, 0 }, Ev }, 0 },
3746 #define NEED_REG_TABLE
3747 #include "i386-dis-evex.h"
3748 #undef NEED_REG_TABLE
3751 static const struct dis386 prefix_table[][4] = {
3754 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3755 { "pause", { XX }, 0 },
3756 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3757 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3762 { "movups", { XM, EXx }, PREFIX_OPCODE },
3763 { "movss", { XM, EXd }, PREFIX_OPCODE },
3764 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3765 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3770 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3771 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3772 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3773 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3778 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3779 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3780 { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3781 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3786 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3787 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3788 { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3793 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3794 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3795 { "bndmov", { Gbnd, Ebnd }, 0 },
3796 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3801 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3802 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3803 { "bndmov", { Ebnd, Gbnd }, 0 },
3804 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3809 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3810 { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3811 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3812 { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3817 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3818 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3819 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3820 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3825 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3826 { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3827 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3828 { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3833 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3834 { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3835 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3836 { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3841 { "ucomiss",{ XM, EXd }, 0 },
3843 { "ucomisd",{ XM, EXq }, 0 },
3848 { "comiss", { XM, EXd }, 0 },
3850 { "comisd", { XM, EXq }, 0 },
3855 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3856 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3857 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3858 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3863 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3864 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3869 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3870 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3875 { "addps", { XM, EXx }, PREFIX_OPCODE },
3876 { "addss", { XM, EXd }, PREFIX_OPCODE },
3877 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3878 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3883 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3884 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3885 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3886 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3891 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3892 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3893 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3894 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3899 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3900 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3901 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3906 { "subps", { XM, EXx }, PREFIX_OPCODE },
3907 { "subss", { XM, EXd }, PREFIX_OPCODE },
3908 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3909 { "subsd", { XM, EXq }, PREFIX_OPCODE },
3914 { "minps", { XM, EXx }, PREFIX_OPCODE },
3915 { "minss", { XM, EXd }, PREFIX_OPCODE },
3916 { "minpd", { XM, EXx }, PREFIX_OPCODE },
3917 { "minsd", { XM, EXq }, PREFIX_OPCODE },
3922 { "divps", { XM, EXx }, PREFIX_OPCODE },
3923 { "divss", { XM, EXd }, PREFIX_OPCODE },
3924 { "divpd", { XM, EXx }, PREFIX_OPCODE },
3925 { "divsd", { XM, EXq }, PREFIX_OPCODE },
3930 { "maxps", { XM, EXx }, PREFIX_OPCODE },
3931 { "maxss", { XM, EXd }, PREFIX_OPCODE },
3932 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
3933 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
3938 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3940 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3945 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3947 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3952 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3954 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3961 { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3968 { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3973 { "movq", { MX, EM }, PREFIX_OPCODE },
3974 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3975 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3980 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3981 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3982 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3983 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3986 /* PREFIX_0F73_REG_3 */
3990 { "psrldq", { XS, Ib }, 0 },
3993 /* PREFIX_0F73_REG_7 */
3997 { "pslldq", { XS, Ib }, 0 },
4002 {"vmread", { Em, Gm }, 0 },
4004 {"extrq", { XS, Ib, Ib }, 0 },
4005 {"insertq", { XM, XS, Ib, Ib }, 0 },
4010 {"vmwrite", { Gm, Em }, 0 },
4012 {"extrq", { XM, XS }, 0 },
4013 {"insertq", { XM, XS }, 0 },
4020 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4021 { "haddps", { XM, EXx }, PREFIX_OPCODE },
4028 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4029 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4034 { "movK", { Edq, MX }, PREFIX_OPCODE },
4035 { "movq", { XM, EXq }, PREFIX_OPCODE },
4036 { "movK", { Edq, XM }, PREFIX_OPCODE },
4041 { "movq", { EMS, MX }, PREFIX_OPCODE },
4042 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4043 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4046 /* PREFIX_0FAE_REG_0 */
4049 { "rdfsbase", { Ev }, 0 },
4052 /* PREFIX_0FAE_REG_1 */
4055 { "rdgsbase", { Ev }, 0 },
4058 /* PREFIX_0FAE_REG_2 */
4061 { "wrfsbase", { Ev }, 0 },
4064 /* PREFIX_0FAE_REG_3 */
4067 { "wrgsbase", { Ev }, 0 },
4070 /* PREFIX_MOD_0_0FAE_REG_4 */
4072 { "xsave", { FXSAVE }, 0 },
4073 { "ptwrite%LQ", { Edq }, 0 },
4076 /* PREFIX_MOD_3_0FAE_REG_4 */
4079 { "ptwrite%LQ", { Edq }, 0 },
4082 /* PREFIX_0FAE_REG_6 */
4084 { "xsaveopt", { FXSAVE }, 0 },
4086 { "clwb", { Mb }, 0 },
4089 /* PREFIX_0FAE_REG_7 */
4091 { "clflush", { Mb }, 0 },
4093 { "clflushopt", { Mb }, 0 },
4099 { "popcntS", { Gv, Ev }, 0 },
4104 { "bsfS", { Gv, Ev }, 0 },
4105 { "tzcntS", { Gv, Ev }, 0 },
4106 { "bsfS", { Gv, Ev }, 0 },
4111 { "bsrS", { Gv, Ev }, 0 },
4112 { "lzcntS", { Gv, Ev }, 0 },
4113 { "bsrS", { Gv, Ev }, 0 },
4118 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
4119 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
4120 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
4121 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
4124 /* PREFIX_MOD_0_0FC3 */
4126 { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4129 /* PREFIX_MOD_0_0FC7_REG_6 */
4131 { "vmptrld",{ Mq }, 0 },
4132 { "vmxon", { Mq }, 0 },
4133 { "vmclear",{ Mq }, 0 },
4136 /* PREFIX_MOD_3_0FC7_REG_6 */
4138 { "rdrand", { Ev }, 0 },
4140 { "rdrand", { Ev }, 0 }
4143 /* PREFIX_MOD_3_0FC7_REG_7 */
4145 { "rdseed", { Ev }, 0 },
4146 { "rdpid", { Em }, 0 },
4147 { "rdseed", { Ev }, 0 },
4154 { "addsubpd", { XM, EXx }, 0 },
4155 { "addsubps", { XM, EXx }, 0 },
4161 { "movq2dq",{ XM, MS }, 0 },
4162 { "movq", { EXqS, XM }, 0 },
4163 { "movdq2q",{ MX, XS }, 0 },
4169 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4170 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4171 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4176 { "movntq", { Mq, MX }, PREFIX_OPCODE },
4178 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4186 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4191 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4193 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4200 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4207 { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4214 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4221 { "ptest", { XM, EXx }, PREFIX_OPCODE },
4228 { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4235 { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4242 { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4249 { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4256 { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4263 { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4270 { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4277 { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4284 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4291 { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4298 { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4305 { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4312 { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4319 { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4326 { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4333 { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4340 { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4347 { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4354 { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4361 { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4368 { "pminud", { XM, EXx }, PREFIX_OPCODE },
4375 { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4382 { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4389 { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4396 { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4403 { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4410 { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4417 { "invept", { Gm, Mo }, PREFIX_OPCODE },
4424 { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4431 { "invpcid", { Gm, M }, PREFIX_OPCODE },
4436 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4441 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4446 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4451 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4456 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4461 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4468 { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4475 { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4482 { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4489 { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4496 { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4501 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4503 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4504 { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4509 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4511 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4512 { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4518 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
4519 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
4527 { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4534 { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4541 { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4548 { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4555 { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4562 { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4569 { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4576 { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4583 { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4590 { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4597 { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4604 { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4611 { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4618 { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4625 { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE },
4632 { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE },
4639 { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4646 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4653 { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4660 { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE },
4667 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4674 { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4679 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4686 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4689 /* PREFIX_VEX_0F10 */
4691 { VEX_W_TABLE (VEX_W_0F10_P_0) },
4692 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4693 { VEX_W_TABLE (VEX_W_0F10_P_2) },
4694 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4697 /* PREFIX_VEX_0F11 */
4699 { VEX_W_TABLE (VEX_W_0F11_P_0) },
4700 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4701 { VEX_W_TABLE (VEX_W_0F11_P_2) },
4702 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4705 /* PREFIX_VEX_0F12 */
4707 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4708 { VEX_W_TABLE (VEX_W_0F12_P_1) },
4709 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4710 { VEX_W_TABLE (VEX_W_0F12_P_3) },
4713 /* PREFIX_VEX_0F16 */
4715 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4716 { VEX_W_TABLE (VEX_W_0F16_P_1) },
4717 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4720 /* PREFIX_VEX_0F2A */
4723 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4725 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4728 /* PREFIX_VEX_0F2C */
4731 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4733 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4736 /* PREFIX_VEX_0F2D */
4739 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4741 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4744 /* PREFIX_VEX_0F2E */
4746 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4748 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4751 /* PREFIX_VEX_0F2F */
4753 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4755 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4758 /* PREFIX_VEX_0F41 */
4760 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4762 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4765 /* PREFIX_VEX_0F42 */
4767 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4769 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4772 /* PREFIX_VEX_0F44 */
4774 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4776 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4779 /* PREFIX_VEX_0F45 */
4781 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4783 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4786 /* PREFIX_VEX_0F46 */
4788 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4790 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4793 /* PREFIX_VEX_0F47 */
4795 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4797 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4800 /* PREFIX_VEX_0F4A */
4802 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4804 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4807 /* PREFIX_VEX_0F4B */
4809 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4811 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4814 /* PREFIX_VEX_0F51 */
4816 { VEX_W_TABLE (VEX_W_0F51_P_0) },
4817 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4818 { VEX_W_TABLE (VEX_W_0F51_P_2) },
4819 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4822 /* PREFIX_VEX_0F52 */
4824 { VEX_W_TABLE (VEX_W_0F52_P_0) },
4825 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4828 /* PREFIX_VEX_0F53 */
4830 { VEX_W_TABLE (VEX_W_0F53_P_0) },
4831 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4834 /* PREFIX_VEX_0F58 */
4836 { VEX_W_TABLE (VEX_W_0F58_P_0) },
4837 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4838 { VEX_W_TABLE (VEX_W_0F58_P_2) },
4839 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4842 /* PREFIX_VEX_0F59 */
4844 { VEX_W_TABLE (VEX_W_0F59_P_0) },
4845 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4846 { VEX_W_TABLE (VEX_W_0F59_P_2) },
4847 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4850 /* PREFIX_VEX_0F5A */
4852 { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4853 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4854 { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4855 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4858 /* PREFIX_VEX_0F5B */
4860 { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4861 { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4862 { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4865 /* PREFIX_VEX_0F5C */
4867 { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4868 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4869 { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4870 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4873 /* PREFIX_VEX_0F5D */
4875 { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4876 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4877 { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4878 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4881 /* PREFIX_VEX_0F5E */
4883 { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4884 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4885 { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4886 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4889 /* PREFIX_VEX_0F5F */
4891 { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4892 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4893 { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4894 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4897 /* PREFIX_VEX_0F60 */
4901 { VEX_W_TABLE (VEX_W_0F60_P_2) },
4904 /* PREFIX_VEX_0F61 */
4908 { VEX_W_TABLE (VEX_W_0F61_P_2) },
4911 /* PREFIX_VEX_0F62 */
4915 { VEX_W_TABLE (VEX_W_0F62_P_2) },
4918 /* PREFIX_VEX_0F63 */
4922 { VEX_W_TABLE (VEX_W_0F63_P_2) },
4925 /* PREFIX_VEX_0F64 */
4929 { VEX_W_TABLE (VEX_W_0F64_P_2) },
4932 /* PREFIX_VEX_0F65 */
4936 { VEX_W_TABLE (VEX_W_0F65_P_2) },
4939 /* PREFIX_VEX_0F66 */
4943 { VEX_W_TABLE (VEX_W_0F66_P_2) },
4946 /* PREFIX_VEX_0F67 */
4950 { VEX_W_TABLE (VEX_W_0F67_P_2) },
4953 /* PREFIX_VEX_0F68 */
4957 { VEX_W_TABLE (VEX_W_0F68_P_2) },
4960 /* PREFIX_VEX_0F69 */
4964 { VEX_W_TABLE (VEX_W_0F69_P_2) },
4967 /* PREFIX_VEX_0F6A */
4971 { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4974 /* PREFIX_VEX_0F6B */
4978 { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4981 /* PREFIX_VEX_0F6C */
4985 { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4988 /* PREFIX_VEX_0F6D */
4992 { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4995 /* PREFIX_VEX_0F6E */
4999 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5002 /* PREFIX_VEX_0F6F */
5005 { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5006 { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5009 /* PREFIX_VEX_0F70 */
5012 { VEX_W_TABLE (VEX_W_0F70_P_1) },
5013 { VEX_W_TABLE (VEX_W_0F70_P_2) },
5014 { VEX_W_TABLE (VEX_W_0F70_P_3) },
5017 /* PREFIX_VEX_0F71_REG_2 */
5021 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5024 /* PREFIX_VEX_0F71_REG_4 */
5028 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5031 /* PREFIX_VEX_0F71_REG_6 */
5035 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5038 /* PREFIX_VEX_0F72_REG_2 */
5042 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5045 /* PREFIX_VEX_0F72_REG_4 */
5049 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5052 /* PREFIX_VEX_0F72_REG_6 */
5056 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5059 /* PREFIX_VEX_0F73_REG_2 */
5063 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5066 /* PREFIX_VEX_0F73_REG_3 */
5070 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5073 /* PREFIX_VEX_0F73_REG_6 */
5077 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5080 /* PREFIX_VEX_0F73_REG_7 */
5084 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5087 /* PREFIX_VEX_0F74 */
5091 { VEX_W_TABLE (VEX_W_0F74_P_2) },
5094 /* PREFIX_VEX_0F75 */
5098 { VEX_W_TABLE (VEX_W_0F75_P_2) },
5101 /* PREFIX_VEX_0F76 */
5105 { VEX_W_TABLE (VEX_W_0F76_P_2) },
5108 /* PREFIX_VEX_0F77 */
5110 { VEX_W_TABLE (VEX_W_0F77_P_0) },
5113 /* PREFIX_VEX_0F7C */
5117 { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5118 { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5121 /* PREFIX_VEX_0F7D */
5125 { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5126 { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5129 /* PREFIX_VEX_0F7E */
5132 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5133 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5136 /* PREFIX_VEX_0F7F */
5139 { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5140 { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5143 /* PREFIX_VEX_0F90 */
5145 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5147 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5150 /* PREFIX_VEX_0F91 */
5152 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5154 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5157 /* PREFIX_VEX_0F92 */
5159 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5161 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5162 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5165 /* PREFIX_VEX_0F93 */
5167 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5169 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5170 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5173 /* PREFIX_VEX_0F98 */
5175 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5177 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5180 /* PREFIX_VEX_0F99 */
5182 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5184 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5187 /* PREFIX_VEX_0FC2 */
5189 { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5190 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5191 { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5192 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5195 /* PREFIX_VEX_0FC4 */
5199 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5202 /* PREFIX_VEX_0FC5 */
5206 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5209 /* PREFIX_VEX_0FD0 */
5213 { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5214 { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5217 /* PREFIX_VEX_0FD1 */
5221 { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5224 /* PREFIX_VEX_0FD2 */
5228 { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5231 /* PREFIX_VEX_0FD3 */
5235 { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5238 /* PREFIX_VEX_0FD4 */
5242 { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5245 /* PREFIX_VEX_0FD5 */
5249 { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5252 /* PREFIX_VEX_0FD6 */
5256 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5259 /* PREFIX_VEX_0FD7 */
5263 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5266 /* PREFIX_VEX_0FD8 */
5270 { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5273 /* PREFIX_VEX_0FD9 */
5277 { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5280 /* PREFIX_VEX_0FDA */
5284 { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5287 /* PREFIX_VEX_0FDB */
5291 { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5294 /* PREFIX_VEX_0FDC */
5298 { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5301 /* PREFIX_VEX_0FDD */
5305 { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5308 /* PREFIX_VEX_0FDE */
5312 { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5315 /* PREFIX_VEX_0FDF */
5319 { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5322 /* PREFIX_VEX_0FE0 */
5326 { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5329 /* PREFIX_VEX_0FE1 */
5333 { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5336 /* PREFIX_VEX_0FE2 */
5340 { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5343 /* PREFIX_VEX_0FE3 */
5347 { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5350 /* PREFIX_VEX_0FE4 */
5354 { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5357 /* PREFIX_VEX_0FE5 */
5361 { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5364 /* PREFIX_VEX_0FE6 */
5367 { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5368 { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5369 { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5372 /* PREFIX_VEX_0FE7 */
5376 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5379 /* PREFIX_VEX_0FE8 */
5383 { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5386 /* PREFIX_VEX_0FE9 */
5390 { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5393 /* PREFIX_VEX_0FEA */
5397 { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5400 /* PREFIX_VEX_0FEB */
5404 { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5407 /* PREFIX_VEX_0FEC */
5411 { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5414 /* PREFIX_VEX_0FED */
5418 { VEX_W_TABLE (VEX_W_0FED_P_2) },
5421 /* PREFIX_VEX_0FEE */
5425 { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5428 /* PREFIX_VEX_0FEF */
5432 { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5435 /* PREFIX_VEX_0FF0 */
5440 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5443 /* PREFIX_VEX_0FF1 */
5447 { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5450 /* PREFIX_VEX_0FF2 */
5454 { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5457 /* PREFIX_VEX_0FF3 */
5461 { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5464 /* PREFIX_VEX_0FF4 */
5468 { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5471 /* PREFIX_VEX_0FF5 */
5475 { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5478 /* PREFIX_VEX_0FF6 */
5482 { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5485 /* PREFIX_VEX_0FF7 */
5489 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5492 /* PREFIX_VEX_0FF8 */
5496 { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5499 /* PREFIX_VEX_0FF9 */
5503 { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5506 /* PREFIX_VEX_0FFA */
5510 { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5513 /* PREFIX_VEX_0FFB */
5517 { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5520 /* PREFIX_VEX_0FFC */
5524 { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5527 /* PREFIX_VEX_0FFD */
5531 { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5534 /* PREFIX_VEX_0FFE */
5538 { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5541 /* PREFIX_VEX_0F3800 */
5545 { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5548 /* PREFIX_VEX_0F3801 */
5552 { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5555 /* PREFIX_VEX_0F3802 */
5559 { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5562 /* PREFIX_VEX_0F3803 */
5566 { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5569 /* PREFIX_VEX_0F3804 */
5573 { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5576 /* PREFIX_VEX_0F3805 */
5580 { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5583 /* PREFIX_VEX_0F3806 */
5587 { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5590 /* PREFIX_VEX_0F3807 */
5594 { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5597 /* PREFIX_VEX_0F3808 */
5601 { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5604 /* PREFIX_VEX_0F3809 */
5608 { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5611 /* PREFIX_VEX_0F380A */
5615 { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5618 /* PREFIX_VEX_0F380B */
5622 { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5625 /* PREFIX_VEX_0F380C */
5629 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5632 /* PREFIX_VEX_0F380D */
5636 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5639 /* PREFIX_VEX_0F380E */
5643 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5646 /* PREFIX_VEX_0F380F */
5650 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5653 /* PREFIX_VEX_0F3813 */
5657 { "vcvtph2ps", { XM, EXxmmq }, 0 },
5660 /* PREFIX_VEX_0F3816 */
5664 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5667 /* PREFIX_VEX_0F3817 */
5671 { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5674 /* PREFIX_VEX_0F3818 */
5678 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5681 /* PREFIX_VEX_0F3819 */
5685 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5688 /* PREFIX_VEX_0F381A */
5692 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5695 /* PREFIX_VEX_0F381C */
5699 { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5702 /* PREFIX_VEX_0F381D */
5706 { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5709 /* PREFIX_VEX_0F381E */
5713 { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5716 /* PREFIX_VEX_0F3820 */
5720 { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5723 /* PREFIX_VEX_0F3821 */
5727 { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5730 /* PREFIX_VEX_0F3822 */
5734 { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5737 /* PREFIX_VEX_0F3823 */
5741 { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5744 /* PREFIX_VEX_0F3824 */
5748 { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5751 /* PREFIX_VEX_0F3825 */
5755 { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5758 /* PREFIX_VEX_0F3828 */
5762 { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5765 /* PREFIX_VEX_0F3829 */
5769 { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5772 /* PREFIX_VEX_0F382A */
5776 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5779 /* PREFIX_VEX_0F382B */
5783 { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5786 /* PREFIX_VEX_0F382C */
5790 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5793 /* PREFIX_VEX_0F382D */
5797 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5800 /* PREFIX_VEX_0F382E */
5804 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5807 /* PREFIX_VEX_0F382F */
5811 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5814 /* PREFIX_VEX_0F3830 */
5818 { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5821 /* PREFIX_VEX_0F3831 */
5825 { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5828 /* PREFIX_VEX_0F3832 */
5832 { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5835 /* PREFIX_VEX_0F3833 */
5839 { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5842 /* PREFIX_VEX_0F3834 */
5846 { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5849 /* PREFIX_VEX_0F3835 */
5853 { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5856 /* PREFIX_VEX_0F3836 */
5860 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5863 /* PREFIX_VEX_0F3837 */
5867 { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5870 /* PREFIX_VEX_0F3838 */
5874 { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5877 /* PREFIX_VEX_0F3839 */
5881 { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5884 /* PREFIX_VEX_0F383A */
5888 { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5891 /* PREFIX_VEX_0F383B */
5895 { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5898 /* PREFIX_VEX_0F383C */
5902 { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5905 /* PREFIX_VEX_0F383D */
5909 { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5912 /* PREFIX_VEX_0F383E */
5916 { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5919 /* PREFIX_VEX_0F383F */
5923 { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5926 /* PREFIX_VEX_0F3840 */
5930 { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5933 /* PREFIX_VEX_0F3841 */
5937 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5940 /* PREFIX_VEX_0F3845 */
5944 { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5947 /* PREFIX_VEX_0F3846 */
5951 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5954 /* PREFIX_VEX_0F3847 */
5958 { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5961 /* PREFIX_VEX_0F3858 */
5965 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5968 /* PREFIX_VEX_0F3859 */
5972 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5975 /* PREFIX_VEX_0F385A */
5979 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5982 /* PREFIX_VEX_0F3878 */
5986 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5989 /* PREFIX_VEX_0F3879 */
5993 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5996 /* PREFIX_VEX_0F388C */
6000 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6003 /* PREFIX_VEX_0F388E */
6007 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6010 /* PREFIX_VEX_0F3890 */
6014 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6017 /* PREFIX_VEX_0F3891 */
6021 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6024 /* PREFIX_VEX_0F3892 */
6028 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6031 /* PREFIX_VEX_0F3893 */
6035 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6038 /* PREFIX_VEX_0F3896 */
6042 { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6045 /* PREFIX_VEX_0F3897 */
6049 { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6052 /* PREFIX_VEX_0F3898 */
6056 { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6059 /* PREFIX_VEX_0F3899 */
6063 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6066 /* PREFIX_VEX_0F389A */
6070 { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6073 /* PREFIX_VEX_0F389B */
6077 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6080 /* PREFIX_VEX_0F389C */
6084 { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6087 /* PREFIX_VEX_0F389D */
6091 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6094 /* PREFIX_VEX_0F389E */
6098 { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6101 /* PREFIX_VEX_0F389F */
6105 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6108 /* PREFIX_VEX_0F38A6 */
6112 { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6116 /* PREFIX_VEX_0F38A7 */
6120 { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6123 /* PREFIX_VEX_0F38A8 */
6127 { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6130 /* PREFIX_VEX_0F38A9 */
6134 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6137 /* PREFIX_VEX_0F38AA */
6141 { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6144 /* PREFIX_VEX_0F38AB */
6148 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6151 /* PREFIX_VEX_0F38AC */
6155 { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6158 /* PREFIX_VEX_0F38AD */
6162 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6165 /* PREFIX_VEX_0F38AE */
6169 { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6172 /* PREFIX_VEX_0F38AF */
6176 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6179 /* PREFIX_VEX_0F38B6 */
6183 { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6186 /* PREFIX_VEX_0F38B7 */
6190 { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6193 /* PREFIX_VEX_0F38B8 */
6197 { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6200 /* PREFIX_VEX_0F38B9 */
6204 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6207 /* PREFIX_VEX_0F38BA */
6211 { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6214 /* PREFIX_VEX_0F38BB */
6218 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6221 /* PREFIX_VEX_0F38BC */
6225 { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6228 /* PREFIX_VEX_0F38BD */
6232 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6235 /* PREFIX_VEX_0F38BE */
6239 { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6242 /* PREFIX_VEX_0F38BF */
6246 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6249 /* PREFIX_VEX_0F38DB */
6253 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6256 /* PREFIX_VEX_0F38DC */
6260 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6263 /* PREFIX_VEX_0F38DD */
6267 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6270 /* PREFIX_VEX_0F38DE */
6274 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6277 /* PREFIX_VEX_0F38DF */
6281 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6284 /* PREFIX_VEX_0F38F2 */
6286 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6289 /* PREFIX_VEX_0F38F3_REG_1 */
6291 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6294 /* PREFIX_VEX_0F38F3_REG_2 */
6296 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6299 /* PREFIX_VEX_0F38F3_REG_3 */
6301 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6304 /* PREFIX_VEX_0F38F5 */
6306 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6307 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6309 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6312 /* PREFIX_VEX_0F38F6 */
6317 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6320 /* PREFIX_VEX_0F38F7 */
6322 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6323 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6324 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6325 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6328 /* PREFIX_VEX_0F3A00 */
6332 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6335 /* PREFIX_VEX_0F3A01 */
6339 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6342 /* PREFIX_VEX_0F3A02 */
6346 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6349 /* PREFIX_VEX_0F3A04 */
6353 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6356 /* PREFIX_VEX_0F3A05 */
6360 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6363 /* PREFIX_VEX_0F3A06 */
6367 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6370 /* PREFIX_VEX_0F3A08 */
6374 { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6377 /* PREFIX_VEX_0F3A09 */
6381 { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6384 /* PREFIX_VEX_0F3A0A */
6388 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6391 /* PREFIX_VEX_0F3A0B */
6395 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6398 /* PREFIX_VEX_0F3A0C */
6402 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6405 /* PREFIX_VEX_0F3A0D */
6409 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6412 /* PREFIX_VEX_0F3A0E */
6416 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6419 /* PREFIX_VEX_0F3A0F */
6423 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6426 /* PREFIX_VEX_0F3A14 */
6430 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6433 /* PREFIX_VEX_0F3A15 */
6437 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6440 /* PREFIX_VEX_0F3A16 */
6444 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6447 /* PREFIX_VEX_0F3A17 */
6451 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6454 /* PREFIX_VEX_0F3A18 */
6458 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6461 /* PREFIX_VEX_0F3A19 */
6465 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6468 /* PREFIX_VEX_0F3A1D */
6472 { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6475 /* PREFIX_VEX_0F3A20 */
6479 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6482 /* PREFIX_VEX_0F3A21 */
6486 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6489 /* PREFIX_VEX_0F3A22 */
6493 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6496 /* PREFIX_VEX_0F3A30 */
6500 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6503 /* PREFIX_VEX_0F3A31 */
6507 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6510 /* PREFIX_VEX_0F3A32 */
6514 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6517 /* PREFIX_VEX_0F3A33 */
6521 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6524 /* PREFIX_VEX_0F3A38 */
6528 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6531 /* PREFIX_VEX_0F3A39 */
6535 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6538 /* PREFIX_VEX_0F3A40 */
6542 { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6545 /* PREFIX_VEX_0F3A41 */
6549 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6552 /* PREFIX_VEX_0F3A42 */
6556 { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6559 /* PREFIX_VEX_0F3A44 */
6563 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6566 /* PREFIX_VEX_0F3A46 */
6570 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6573 /* PREFIX_VEX_0F3A48 */
6577 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6580 /* PREFIX_VEX_0F3A49 */
6584 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6587 /* PREFIX_VEX_0F3A4A */
6591 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6594 /* PREFIX_VEX_0F3A4B */
6598 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6601 /* PREFIX_VEX_0F3A4C */
6605 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6608 /* PREFIX_VEX_0F3A5C */
6612 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6615 /* PREFIX_VEX_0F3A5D */
6619 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6622 /* PREFIX_VEX_0F3A5E */
6626 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6629 /* PREFIX_VEX_0F3A5F */
6633 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6636 /* PREFIX_VEX_0F3A60 */
6640 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6644 /* PREFIX_VEX_0F3A61 */
6648 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6651 /* PREFIX_VEX_0F3A62 */
6655 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6658 /* PREFIX_VEX_0F3A63 */
6662 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6665 /* PREFIX_VEX_0F3A68 */
6669 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6672 /* PREFIX_VEX_0F3A69 */
6676 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6679 /* PREFIX_VEX_0F3A6A */
6683 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6686 /* PREFIX_VEX_0F3A6B */
6690 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6693 /* PREFIX_VEX_0F3A6C */
6697 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6700 /* PREFIX_VEX_0F3A6D */
6704 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6707 /* PREFIX_VEX_0F3A6E */
6711 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6714 /* PREFIX_VEX_0F3A6F */
6718 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6721 /* PREFIX_VEX_0F3A78 */
6725 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6728 /* PREFIX_VEX_0F3A79 */
6732 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6735 /* PREFIX_VEX_0F3A7A */
6739 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6742 /* PREFIX_VEX_0F3A7B */
6746 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6749 /* PREFIX_VEX_0F3A7C */
6753 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6757 /* PREFIX_VEX_0F3A7D */
6761 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6764 /* PREFIX_VEX_0F3A7E */
6768 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6771 /* PREFIX_VEX_0F3A7F */
6775 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6778 /* PREFIX_VEX_0F3ADF */
6782 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6785 /* PREFIX_VEX_0F3AF0 */
6790 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6793 #define NEED_PREFIX_TABLE
6794 #include "i386-dis-evex.h"
6795 #undef NEED_PREFIX_TABLE
6798 static const struct dis386 x86_64_table[][2] = {
6801 { "pushP", { es }, 0 },
6806 { "popP", { es }, 0 },
6811 { "pushP", { cs }, 0 },
6816 { "pushP", { ss }, 0 },
6821 { "popP", { ss }, 0 },
6826 { "pushP", { ds }, 0 },
6831 { "popP", { ds }, 0 },
6836 { "daa", { XX }, 0 },
6841 { "das", { XX }, 0 },
6846 { "aaa", { XX }, 0 },
6851 { "aas", { XX }, 0 },
6856 { "pushaP", { XX }, 0 },
6861 { "popaP", { XX }, 0 },
6866 { MOD_TABLE (MOD_62_32BIT) },
6867 { EVEX_TABLE (EVEX_0F) },
6872 { "arpl", { Ew, Gw }, 0 },
6873 { "movs{lq|xd}", { Gv, Ed }, 0 },
6878 { "ins{R|}", { Yzr, indirDX }, 0 },
6879 { "ins{G|}", { Yzr, indirDX }, 0 },
6884 { "outs{R|}", { indirDXr, Xz }, 0 },
6885 { "outs{G|}", { indirDXr, Xz }, 0 },
6890 /* Opcode 0x82 is an alias of of opcode 0x80 in 32-bit mode. */
6891 { REG_TABLE (REG_80) },
6896 { "Jcall{T|}", { Ap }, 0 },
6901 { MOD_TABLE (MOD_C4_32BIT) },
6902 { VEX_C4_TABLE (VEX_0F) },
6907 { MOD_TABLE (MOD_C5_32BIT) },
6908 { VEX_C5_TABLE (VEX_0F) },
6913 { "into", { XX }, 0 },
6918 { "aam", { Ib }, 0 },
6923 { "aad", { Ib }, 0 },
6928 { "callP", { Jv, BND }, 0 },
6929 { "call@", { Jv, BND }, 0 }
6934 { "jmpP", { Jv, BND }, 0 },
6935 { "jmp@", { Jv, BND }, 0 }
6940 { "Jjmp{T|}", { Ap }, 0 },
6943 /* X86_64_0F01_REG_0 */
6945 { "sgdt{Q|IQ}", { M }, 0 },
6946 { "sgdt", { M }, 0 },
6949 /* X86_64_0F01_REG_1 */
6951 { "sidt{Q|IQ}", { M }, 0 },
6952 { "sidt", { M }, 0 },
6955 /* X86_64_0F01_REG_2 */
6957 { "lgdt{Q|Q}", { M }, 0 },
6958 { "lgdt", { M }, 0 },
6961 /* X86_64_0F01_REG_3 */
6963 { "lidt{Q|Q}", { M }, 0 },
6964 { "lidt", { M }, 0 },
6968 static const struct dis386 three_byte_table[][256] = {
6970 /* THREE_BYTE_0F38 */
6973 { "pshufb", { MX, EM }, PREFIX_OPCODE },
6974 { "phaddw", { MX, EM }, PREFIX_OPCODE },
6975 { "phaddd", { MX, EM }, PREFIX_OPCODE },
6976 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
6977 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
6978 { "phsubw", { MX, EM }, PREFIX_OPCODE },
6979 { "phsubd", { MX, EM }, PREFIX_OPCODE },
6980 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
6982 { "psignb", { MX, EM }, PREFIX_OPCODE },
6983 { "psignw", { MX, EM }, PREFIX_OPCODE },
6984 { "psignd", { MX, EM }, PREFIX_OPCODE },
6985 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
6991 { PREFIX_TABLE (PREFIX_0F3810) },
6995 { PREFIX_TABLE (PREFIX_0F3814) },
6996 { PREFIX_TABLE (PREFIX_0F3815) },
6998 { PREFIX_TABLE (PREFIX_0F3817) },
7004 { "pabsb", { MX, EM }, PREFIX_OPCODE },
7005 { "pabsw", { MX, EM }, PREFIX_OPCODE },
7006 { "pabsd", { MX, EM }, PREFIX_OPCODE },
7009 { PREFIX_TABLE (PREFIX_0F3820) },
7010 { PREFIX_TABLE (PREFIX_0F3821) },
7011 { PREFIX_TABLE (PREFIX_0F3822) },
7012 { PREFIX_TABLE (PREFIX_0F3823) },
7013 { PREFIX_TABLE (PREFIX_0F3824) },
7014 { PREFIX_TABLE (PREFIX_0F3825) },
7018 { PREFIX_TABLE (PREFIX_0F3828) },
7019 { PREFIX_TABLE (PREFIX_0F3829) },
7020 { PREFIX_TABLE (PREFIX_0F382A) },
7021 { PREFIX_TABLE (PREFIX_0F382B) },
7027 { PREFIX_TABLE (PREFIX_0F3830) },
7028 { PREFIX_TABLE (PREFIX_0F3831) },
7029 { PREFIX_TABLE (PREFIX_0F3832) },
7030 { PREFIX_TABLE (PREFIX_0F3833) },
7031 { PREFIX_TABLE (PREFIX_0F3834) },
7032 { PREFIX_TABLE (PREFIX_0F3835) },
7034 { PREFIX_TABLE (PREFIX_0F3837) },
7036 { PREFIX_TABLE (PREFIX_0F3838) },
7037 { PREFIX_TABLE (PREFIX_0F3839) },
7038 { PREFIX_TABLE (PREFIX_0F383A) },
7039 { PREFIX_TABLE (PREFIX_0F383B) },
7040 { PREFIX_TABLE (PREFIX_0F383C) },
7041 { PREFIX_TABLE (PREFIX_0F383D) },
7042 { PREFIX_TABLE (PREFIX_0F383E) },
7043 { PREFIX_TABLE (PREFIX_0F383F) },
7045 { PREFIX_TABLE (PREFIX_0F3840) },
7046 { PREFIX_TABLE (PREFIX_0F3841) },
7117 { PREFIX_TABLE (PREFIX_0F3880) },
7118 { PREFIX_TABLE (PREFIX_0F3881) },
7119 { PREFIX_TABLE (PREFIX_0F3882) },
7198 { PREFIX_TABLE (PREFIX_0F38C8) },
7199 { PREFIX_TABLE (PREFIX_0F38C9) },
7200 { PREFIX_TABLE (PREFIX_0F38CA) },
7201 { PREFIX_TABLE (PREFIX_0F38CB) },
7202 { PREFIX_TABLE (PREFIX_0F38CC) },
7203 { PREFIX_TABLE (PREFIX_0F38CD) },
7219 { PREFIX_TABLE (PREFIX_0F38DB) },
7220 { PREFIX_TABLE (PREFIX_0F38DC) },
7221 { PREFIX_TABLE (PREFIX_0F38DD) },
7222 { PREFIX_TABLE (PREFIX_0F38DE) },
7223 { PREFIX_TABLE (PREFIX_0F38DF) },
7243 { PREFIX_TABLE (PREFIX_0F38F0) },
7244 { PREFIX_TABLE (PREFIX_0F38F1) },
7249 { PREFIX_TABLE (PREFIX_0F38F6) },
7261 /* THREE_BYTE_0F3A */
7273 { PREFIX_TABLE (PREFIX_0F3A08) },
7274 { PREFIX_TABLE (PREFIX_0F3A09) },
7275 { PREFIX_TABLE (PREFIX_0F3A0A) },
7276 { PREFIX_TABLE (PREFIX_0F3A0B) },
7277 { PREFIX_TABLE (PREFIX_0F3A0C) },
7278 { PREFIX_TABLE (PREFIX_0F3A0D) },
7279 { PREFIX_TABLE (PREFIX_0F3A0E) },
7280 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
7286 { PREFIX_TABLE (PREFIX_0F3A14) },
7287 { PREFIX_TABLE (PREFIX_0F3A15) },
7288 { PREFIX_TABLE (PREFIX_0F3A16) },
7289 { PREFIX_TABLE (PREFIX_0F3A17) },
7300 { PREFIX_TABLE (PREFIX_0F3A20) },
7301 { PREFIX_TABLE (PREFIX_0F3A21) },
7302 { PREFIX_TABLE (PREFIX_0F3A22) },
7336 { PREFIX_TABLE (PREFIX_0F3A40) },
7337 { PREFIX_TABLE (PREFIX_0F3A41) },
7338 { PREFIX_TABLE (PREFIX_0F3A42) },
7340 { PREFIX_TABLE (PREFIX_0F3A44) },
7372 { PREFIX_TABLE (PREFIX_0F3A60) },
7373 { PREFIX_TABLE (PREFIX_0F3A61) },
7374 { PREFIX_TABLE (PREFIX_0F3A62) },
7375 { PREFIX_TABLE (PREFIX_0F3A63) },
7493 { PREFIX_TABLE (PREFIX_0F3ACC) },
7514 { PREFIX_TABLE (PREFIX_0F3ADF) },
7554 static const struct dis386 xop_table[][256] = {
7707 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7708 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7709 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7717 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7718 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7725 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7726 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7727 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7735 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7736 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7740 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7741 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7744 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7762 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7774 { "vprotb", { XM, Vex_2src_1, Ib }, 0 },
7775 { "vprotw", { XM, Vex_2src_1, Ib }, 0 },
7776 { "vprotd", { XM, Vex_2src_1, Ib }, 0 },
7777 { "vprotq", { XM, Vex_2src_1, Ib }, 0 },
7787 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7788 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7789 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7790 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7823 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7824 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7825 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7826 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7850 { REG_TABLE (REG_XOP_TBM_01) },
7851 { REG_TABLE (REG_XOP_TBM_02) },
7869 { REG_TABLE (REG_XOP_LWPCB) },
7993 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7994 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7995 { "vfrczss", { XM, EXd }, 0 },
7996 { "vfrczsd", { XM, EXq }, 0 },
8011 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8012 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8013 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8014 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8015 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8016 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8017 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8018 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8020 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8021 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8022 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8023 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8066 { "vphaddbw", { XM, EXxmm }, 0 },
8067 { "vphaddbd", { XM, EXxmm }, 0 },
8068 { "vphaddbq", { XM, EXxmm }, 0 },
8071 { "vphaddwd", { XM, EXxmm }, 0 },
8072 { "vphaddwq", { XM, EXxmm }, 0 },
8077 { "vphadddq", { XM, EXxmm }, 0 },
8084 { "vphaddubw", { XM, EXxmm }, 0 },
8085 { "vphaddubd", { XM, EXxmm }, 0 },
8086 { "vphaddubq", { XM, EXxmm }, 0 },
8089 { "vphadduwd", { XM, EXxmm }, 0 },
8090 { "vphadduwq", { XM, EXxmm }, 0 },
8095 { "vphaddudq", { XM, EXxmm }, 0 },
8102 { "vphsubbw", { XM, EXxmm }, 0 },
8103 { "vphsubwd", { XM, EXxmm }, 0 },
8104 { "vphsubdq", { XM, EXxmm }, 0 },
8158 { "bextr", { Gv, Ev, Iq }, 0 },
8160 { REG_TABLE (REG_XOP_LWP) },
8430 static const struct dis386 vex_table[][256] = {
8452 { PREFIX_TABLE (PREFIX_VEX_0F10) },
8453 { PREFIX_TABLE (PREFIX_VEX_0F11) },
8454 { PREFIX_TABLE (PREFIX_VEX_0F12) },
8455 { MOD_TABLE (MOD_VEX_0F13) },
8456 { VEX_W_TABLE (VEX_W_0F14) },
8457 { VEX_W_TABLE (VEX_W_0F15) },
8458 { PREFIX_TABLE (PREFIX_VEX_0F16) },
8459 { MOD_TABLE (MOD_VEX_0F17) },
8479 { VEX_W_TABLE (VEX_W_0F28) },
8480 { VEX_W_TABLE (VEX_W_0F29) },
8481 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8482 { MOD_TABLE (MOD_VEX_0F2B) },
8483 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8484 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8485 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8486 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8507 { PREFIX_TABLE (PREFIX_VEX_0F41) },
8508 { PREFIX_TABLE (PREFIX_VEX_0F42) },
8510 { PREFIX_TABLE (PREFIX_VEX_0F44) },
8511 { PREFIX_TABLE (PREFIX_VEX_0F45) },
8512 { PREFIX_TABLE (PREFIX_VEX_0F46) },
8513 { PREFIX_TABLE (PREFIX_VEX_0F47) },
8517 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8518 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8524 { MOD_TABLE (MOD_VEX_0F50) },
8525 { PREFIX_TABLE (PREFIX_VEX_0F51) },
8526 { PREFIX_TABLE (PREFIX_VEX_0F52) },
8527 { PREFIX_TABLE (PREFIX_VEX_0F53) },
8528 { "vandpX", { XM, Vex, EXx }, 0 },
8529 { "vandnpX", { XM, Vex, EXx }, 0 },
8530 { "vorpX", { XM, Vex, EXx }, 0 },
8531 { "vxorpX", { XM, Vex, EXx }, 0 },
8533 { PREFIX_TABLE (PREFIX_VEX_0F58) },
8534 { PREFIX_TABLE (PREFIX_VEX_0F59) },
8535 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8536 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8537 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8538 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8539 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8540 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8542 { PREFIX_TABLE (PREFIX_VEX_0F60) },
8543 { PREFIX_TABLE (PREFIX_VEX_0F61) },
8544 { PREFIX_TABLE (PREFIX_VEX_0F62) },
8545 { PREFIX_TABLE (PREFIX_VEX_0F63) },
8546 { PREFIX_TABLE (PREFIX_VEX_0F64) },
8547 { PREFIX_TABLE (PREFIX_VEX_0F65) },
8548 { PREFIX_TABLE (PREFIX_VEX_0F66) },
8549 { PREFIX_TABLE (PREFIX_VEX_0F67) },
8551 { PREFIX_TABLE (PREFIX_VEX_0F68) },
8552 { PREFIX_TABLE (PREFIX_VEX_0F69) },
8553 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8554 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8555 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8556 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8557 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8558 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8560 { PREFIX_TABLE (PREFIX_VEX_0F70) },
8561 { REG_TABLE (REG_VEX_0F71) },
8562 { REG_TABLE (REG_VEX_0F72) },
8563 { REG_TABLE (REG_VEX_0F73) },
8564 { PREFIX_TABLE (PREFIX_VEX_0F74) },
8565 { PREFIX_TABLE (PREFIX_VEX_0F75) },
8566 { PREFIX_TABLE (PREFIX_VEX_0F76) },
8567 { PREFIX_TABLE (PREFIX_VEX_0F77) },
8573 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8574 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8575 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8576 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8596 { PREFIX_TABLE (PREFIX_VEX_0F90) },
8597 { PREFIX_TABLE (PREFIX_VEX_0F91) },
8598 { PREFIX_TABLE (PREFIX_VEX_0F92) },
8599 { PREFIX_TABLE (PREFIX_VEX_0F93) },
8605 { PREFIX_TABLE (PREFIX_VEX_0F98) },
8606 { PREFIX_TABLE (PREFIX_VEX_0F99) },
8629 { REG_TABLE (REG_VEX_0FAE) },
8652 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8654 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8655 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8656 { "vshufpX", { XM, Vex, EXx, Ib }, 0 },
8668 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8669 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8670 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8671 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8672 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8673 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8674 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8675 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8677 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8678 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8679 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8680 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8681 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8682 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8683 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8684 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8686 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8687 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8688 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8689 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8690 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8691 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8692 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8693 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8695 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8696 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8697 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8698 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8699 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8700 { PREFIX_TABLE (PREFIX_VEX_0FED) },
8701 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8702 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8704 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8705 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8706 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8707 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8708 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8709 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8710 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8711 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8713 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8714 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8715 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8716 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8717 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8718 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8719 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8725 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8734 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8735 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8736 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8740 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8741 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8746 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8780 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8781 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8783 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8789 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8790 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8792 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8795 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8797 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8798 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8802 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8803 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8804 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8824 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8825 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8826 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8860 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8861 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8882 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8884 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8896 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8929 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8972 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8973 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8974 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8975 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8997 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8998 { REG_TABLE (REG_VEX_0F38F3) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9001 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9002 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9017 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9020 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9022 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9026 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9027 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9028 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9029 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9030 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9031 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9032 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9038 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9048 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9052 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9053 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9054 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9079 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9080 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9088 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9094 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9098 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9099 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9101 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9119 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9120 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9121 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9122 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9124 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9125 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9126 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9127 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9134 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9135 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9136 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9137 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9138 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9139 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9140 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9151 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9152 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9153 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9154 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9155 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9156 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9157 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9158 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9266 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9286 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9306 #define NEED_OPCODE_TABLE
9307 #include "i386-dis-evex.h"
9308 #undef NEED_OPCODE_TABLE
9309 static const struct dis386 vex_len_table[][2] = {
9310 /* VEX_LEN_0F10_P_1 */
9312 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9313 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9316 /* VEX_LEN_0F10_P_3 */
9318 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9319 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9322 /* VEX_LEN_0F11_P_1 */
9324 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9325 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9328 /* VEX_LEN_0F11_P_3 */
9330 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9331 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9334 /* VEX_LEN_0F12_P_0_M_0 */
9336 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9339 /* VEX_LEN_0F12_P_0_M_1 */
9341 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9344 /* VEX_LEN_0F12_P_2 */
9346 { VEX_W_TABLE (VEX_W_0F12_P_2) },
9349 /* VEX_LEN_0F13_M_0 */
9351 { VEX_W_TABLE (VEX_W_0F13_M_0) },
9354 /* VEX_LEN_0F16_P_0_M_0 */
9356 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9359 /* VEX_LEN_0F16_P_0_M_1 */
9361 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9364 /* VEX_LEN_0F16_P_2 */
9366 { VEX_W_TABLE (VEX_W_0F16_P_2) },
9369 /* VEX_LEN_0F17_M_0 */
9371 { VEX_W_TABLE (VEX_W_0F17_M_0) },
9374 /* VEX_LEN_0F2A_P_1 */
9376 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9377 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9380 /* VEX_LEN_0F2A_P_3 */
9382 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9383 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9386 /* VEX_LEN_0F2C_P_1 */
9388 { "vcvttss2siY", { Gv, EXdScalar }, 0 },
9389 { "vcvttss2siY", { Gv, EXdScalar }, 0 },
9392 /* VEX_LEN_0F2C_P_3 */
9394 { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
9395 { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
9398 /* VEX_LEN_0F2D_P_1 */
9400 { "vcvtss2siY", { Gv, EXdScalar }, 0 },
9401 { "vcvtss2siY", { Gv, EXdScalar }, 0 },
9404 /* VEX_LEN_0F2D_P_3 */
9406 { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
9407 { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
9410 /* VEX_LEN_0F2E_P_0 */
9412 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9413 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9416 /* VEX_LEN_0F2E_P_2 */
9418 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9419 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9422 /* VEX_LEN_0F2F_P_0 */
9424 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9425 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9428 /* VEX_LEN_0F2F_P_2 */
9430 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9431 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9434 /* VEX_LEN_0F41_P_0 */
9437 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9439 /* VEX_LEN_0F41_P_2 */
9442 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9444 /* VEX_LEN_0F42_P_0 */
9447 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9449 /* VEX_LEN_0F42_P_2 */
9452 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9454 /* VEX_LEN_0F44_P_0 */
9456 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9458 /* VEX_LEN_0F44_P_2 */
9460 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9462 /* VEX_LEN_0F45_P_0 */
9465 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9467 /* VEX_LEN_0F45_P_2 */
9470 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9472 /* VEX_LEN_0F46_P_0 */
9475 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9477 /* VEX_LEN_0F46_P_2 */
9480 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9482 /* VEX_LEN_0F47_P_0 */
9485 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9487 /* VEX_LEN_0F47_P_2 */
9490 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9492 /* VEX_LEN_0F4A_P_0 */
9495 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9497 /* VEX_LEN_0F4A_P_2 */
9500 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9502 /* VEX_LEN_0F4B_P_0 */
9505 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9507 /* VEX_LEN_0F4B_P_2 */
9510 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9513 /* VEX_LEN_0F51_P_1 */
9515 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9516 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9519 /* VEX_LEN_0F51_P_3 */
9521 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9522 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9525 /* VEX_LEN_0F52_P_1 */
9527 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9528 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9531 /* VEX_LEN_0F53_P_1 */
9533 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9534 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9537 /* VEX_LEN_0F58_P_1 */
9539 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9540 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9543 /* VEX_LEN_0F58_P_3 */
9545 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9546 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9549 /* VEX_LEN_0F59_P_1 */
9551 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9552 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9555 /* VEX_LEN_0F59_P_3 */
9557 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9558 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9561 /* VEX_LEN_0F5A_P_1 */
9563 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9564 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9567 /* VEX_LEN_0F5A_P_3 */
9569 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9570 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9573 /* VEX_LEN_0F5C_P_1 */
9575 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9576 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9579 /* VEX_LEN_0F5C_P_3 */
9581 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9582 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9585 /* VEX_LEN_0F5D_P_1 */
9587 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9588 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9591 /* VEX_LEN_0F5D_P_3 */
9593 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9594 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9597 /* VEX_LEN_0F5E_P_1 */
9599 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9600 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9603 /* VEX_LEN_0F5E_P_3 */
9605 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9606 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9609 /* VEX_LEN_0F5F_P_1 */
9611 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9612 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9615 /* VEX_LEN_0F5F_P_3 */
9617 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9618 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9621 /* VEX_LEN_0F6E_P_2 */
9623 { "vmovK", { XMScalar, Edq }, 0 },
9624 { "vmovK", { XMScalar, Edq }, 0 },
9627 /* VEX_LEN_0F7E_P_1 */
9629 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9630 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9633 /* VEX_LEN_0F7E_P_2 */
9635 { "vmovK", { Edq, XMScalar }, 0 },
9636 { "vmovK", { Edq, XMScalar }, 0 },
9639 /* VEX_LEN_0F90_P_0 */
9641 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9644 /* VEX_LEN_0F90_P_2 */
9646 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9649 /* VEX_LEN_0F91_P_0 */
9651 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9654 /* VEX_LEN_0F91_P_2 */
9656 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9659 /* VEX_LEN_0F92_P_0 */
9661 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9664 /* VEX_LEN_0F92_P_2 */
9666 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9669 /* VEX_LEN_0F92_P_3 */
9671 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9674 /* VEX_LEN_0F93_P_0 */
9676 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9679 /* VEX_LEN_0F93_P_2 */
9681 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9684 /* VEX_LEN_0F93_P_3 */
9686 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9689 /* VEX_LEN_0F98_P_0 */
9691 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9694 /* VEX_LEN_0F98_P_2 */
9696 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9699 /* VEX_LEN_0F99_P_0 */
9701 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9704 /* VEX_LEN_0F99_P_2 */
9706 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9709 /* VEX_LEN_0FAE_R_2_M_0 */
9711 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9714 /* VEX_LEN_0FAE_R_3_M_0 */
9716 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9719 /* VEX_LEN_0FC2_P_1 */
9721 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9722 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9725 /* VEX_LEN_0FC2_P_3 */
9727 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9728 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9731 /* VEX_LEN_0FC4_P_2 */
9733 { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9736 /* VEX_LEN_0FC5_P_2 */
9738 { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9741 /* VEX_LEN_0FD6_P_2 */
9743 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9744 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9747 /* VEX_LEN_0FF7_P_2 */
9749 { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9752 /* VEX_LEN_0F3816_P_2 */
9755 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9758 /* VEX_LEN_0F3819_P_2 */
9761 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9764 /* VEX_LEN_0F381A_P_2_M_0 */
9767 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9770 /* VEX_LEN_0F3836_P_2 */
9773 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9776 /* VEX_LEN_0F3841_P_2 */
9778 { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9781 /* VEX_LEN_0F385A_P_2_M_0 */
9784 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9787 /* VEX_LEN_0F38DB_P_2 */
9789 { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9792 /* VEX_LEN_0F38DC_P_2 */
9794 { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9797 /* VEX_LEN_0F38DD_P_2 */
9799 { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9802 /* VEX_LEN_0F38DE_P_2 */
9804 { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9807 /* VEX_LEN_0F38DF_P_2 */
9809 { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9812 /* VEX_LEN_0F38F2_P_0 */
9814 { "andnS", { Gdq, VexGdq, Edq }, 0 },
9817 /* VEX_LEN_0F38F3_R_1_P_0 */
9819 { "blsrS", { VexGdq, Edq }, 0 },
9822 /* VEX_LEN_0F38F3_R_2_P_0 */
9824 { "blsmskS", { VexGdq, Edq }, 0 },
9827 /* VEX_LEN_0F38F3_R_3_P_0 */
9829 { "blsiS", { VexGdq, Edq }, 0 },
9832 /* VEX_LEN_0F38F5_P_0 */
9834 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
9837 /* VEX_LEN_0F38F5_P_1 */
9839 { "pextS", { Gdq, VexGdq, Edq }, 0 },
9842 /* VEX_LEN_0F38F5_P_3 */
9844 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
9847 /* VEX_LEN_0F38F6_P_3 */
9849 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
9852 /* VEX_LEN_0F38F7_P_0 */
9854 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
9857 /* VEX_LEN_0F38F7_P_1 */
9859 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
9862 /* VEX_LEN_0F38F7_P_2 */
9864 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
9867 /* VEX_LEN_0F38F7_P_3 */
9869 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
9872 /* VEX_LEN_0F3A00_P_2 */
9875 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9878 /* VEX_LEN_0F3A01_P_2 */
9881 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9884 /* VEX_LEN_0F3A06_P_2 */
9887 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9890 /* VEX_LEN_0F3A0A_P_2 */
9892 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9893 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9896 /* VEX_LEN_0F3A0B_P_2 */
9898 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9899 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9902 /* VEX_LEN_0F3A14_P_2 */
9904 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9907 /* VEX_LEN_0F3A15_P_2 */
9909 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9912 /* VEX_LEN_0F3A16_P_2 */
9914 { "vpextrK", { Edq, XM, Ib }, 0 },
9917 /* VEX_LEN_0F3A17_P_2 */
9919 { "vextractps", { Edqd, XM, Ib }, 0 },
9922 /* VEX_LEN_0F3A18_P_2 */
9925 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9928 /* VEX_LEN_0F3A19_P_2 */
9931 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9934 /* VEX_LEN_0F3A20_P_2 */
9936 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
9939 /* VEX_LEN_0F3A21_P_2 */
9941 { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
9944 /* VEX_LEN_0F3A22_P_2 */
9946 { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 },
9949 /* VEX_LEN_0F3A30_P_2 */
9951 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9954 /* VEX_LEN_0F3A31_P_2 */
9956 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9959 /* VEX_LEN_0F3A32_P_2 */
9961 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9964 /* VEX_LEN_0F3A33_P_2 */
9966 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9969 /* VEX_LEN_0F3A38_P_2 */
9972 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9975 /* VEX_LEN_0F3A39_P_2 */
9978 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9981 /* VEX_LEN_0F3A41_P_2 */
9983 { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
9986 /* VEX_LEN_0F3A44_P_2 */
9988 { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
9991 /* VEX_LEN_0F3A46_P_2 */
9994 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9997 /* VEX_LEN_0F3A60_P_2 */
9999 { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10002 /* VEX_LEN_0F3A61_P_2 */
10004 { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10007 /* VEX_LEN_0F3A62_P_2 */
10009 { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10012 /* VEX_LEN_0F3A63_P_2 */
10014 { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10017 /* VEX_LEN_0F3A6A_P_2 */
10019 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10022 /* VEX_LEN_0F3A6B_P_2 */
10024 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10027 /* VEX_LEN_0F3A6E_P_2 */
10029 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10032 /* VEX_LEN_0F3A6F_P_2 */
10034 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10037 /* VEX_LEN_0F3A7A_P_2 */
10039 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10042 /* VEX_LEN_0F3A7B_P_2 */
10044 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10047 /* VEX_LEN_0F3A7E_P_2 */
10049 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10052 /* VEX_LEN_0F3A7F_P_2 */
10054 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10057 /* VEX_LEN_0F3ADF_P_2 */
10059 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10062 /* VEX_LEN_0F3AF0_P_3 */
10064 { "rorxS", { Gdq, Edq, Ib }, 0 },
10067 /* VEX_LEN_0FXOP_08_CC */
10069 { "vpcomb", { XM, Vex128, EXx, Ib }, 0 },
10072 /* VEX_LEN_0FXOP_08_CD */
10074 { "vpcomw", { XM, Vex128, EXx, Ib }, 0 },
10077 /* VEX_LEN_0FXOP_08_CE */
10079 { "vpcomd", { XM, Vex128, EXx, Ib }, 0 },
10082 /* VEX_LEN_0FXOP_08_CF */
10084 { "vpcomq", { XM, Vex128, EXx, Ib }, 0 },
10087 /* VEX_LEN_0FXOP_08_EC */
10089 { "vpcomub", { XM, Vex128, EXx, Ib }, 0 },
10092 /* VEX_LEN_0FXOP_08_ED */
10094 { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 },
10097 /* VEX_LEN_0FXOP_08_EE */
10099 { "vpcomud", { XM, Vex128, EXx, Ib }, 0 },
10102 /* VEX_LEN_0FXOP_08_EF */
10104 { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 },
10107 /* VEX_LEN_0FXOP_09_80 */
10109 { "vfrczps", { XM, EXxmm }, 0 },
10110 { "vfrczps", { XM, EXymmq }, 0 },
10113 /* VEX_LEN_0FXOP_09_81 */
10115 { "vfrczpd", { XM, EXxmm }, 0 },
10116 { "vfrczpd", { XM, EXymmq }, 0 },
10120 static const struct dis386 vex_w_table[][2] = {
10122 /* VEX_W_0F10_P_0 */
10123 { "vmovups", { XM, EXx }, 0 },
10126 /* VEX_W_0F10_P_1 */
10127 { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
10130 /* VEX_W_0F10_P_2 */
10131 { "vmovupd", { XM, EXx }, 0 },
10134 /* VEX_W_0F10_P_3 */
10135 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
10138 /* VEX_W_0F11_P_0 */
10139 { "vmovups", { EXxS, XM }, 0 },
10142 /* VEX_W_0F11_P_1 */
10143 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10146 /* VEX_W_0F11_P_2 */
10147 { "vmovupd", { EXxS, XM }, 0 },
10150 /* VEX_W_0F11_P_3 */
10151 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10154 /* VEX_W_0F12_P_0_M_0 */
10155 { "vmovlps", { XM, Vex128, EXq }, 0 },
10158 /* VEX_W_0F12_P_0_M_1 */
10159 { "vmovhlps", { XM, Vex128, EXq }, 0 },
10162 /* VEX_W_0F12_P_1 */
10163 { "vmovsldup", { XM, EXx }, 0 },
10166 /* VEX_W_0F12_P_2 */
10167 { "vmovlpd", { XM, Vex128, EXq }, 0 },
10170 /* VEX_W_0F12_P_3 */
10171 { "vmovddup", { XM, EXymmq }, 0 },
10174 /* VEX_W_0F13_M_0 */
10175 { "vmovlpX", { EXq, XM }, 0 },
10179 { "vunpcklpX", { XM, Vex, EXx }, 0 },
10183 { "vunpckhpX", { XM, Vex, EXx }, 0 },
10186 /* VEX_W_0F16_P_0_M_0 */
10187 { "vmovhps", { XM, Vex128, EXq }, 0 },
10190 /* VEX_W_0F16_P_0_M_1 */
10191 { "vmovlhps", { XM, Vex128, EXq }, 0 },
10194 /* VEX_W_0F16_P_1 */
10195 { "vmovshdup", { XM, EXx }, 0 },
10198 /* VEX_W_0F16_P_2 */
10199 { "vmovhpd", { XM, Vex128, EXq }, 0 },
10202 /* VEX_W_0F17_M_0 */
10203 { "vmovhpX", { EXq, XM }, 0 },
10207 { "vmovapX", { XM, EXx }, 0 },
10211 { "vmovapX", { EXxS, XM }, 0 },
10214 /* VEX_W_0F2B_M_0 */
10215 { "vmovntpX", { Mx, XM }, 0 },
10218 /* VEX_W_0F2E_P_0 */
10219 { "vucomiss", { XMScalar, EXdScalar }, 0 },
10222 /* VEX_W_0F2E_P_2 */
10223 { "vucomisd", { XMScalar, EXqScalar }, 0 },
10226 /* VEX_W_0F2F_P_0 */
10227 { "vcomiss", { XMScalar, EXdScalar }, 0 },
10230 /* VEX_W_0F2F_P_2 */
10231 { "vcomisd", { XMScalar, EXqScalar }, 0 },
10234 /* VEX_W_0F41_P_0_LEN_1 */
10235 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10236 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10239 /* VEX_W_0F41_P_2_LEN_1 */
10240 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10241 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10244 /* VEX_W_0F42_P_0_LEN_1 */
10245 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10246 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10249 /* VEX_W_0F42_P_2_LEN_1 */
10250 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10251 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10254 /* VEX_W_0F44_P_0_LEN_0 */
10255 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10256 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10259 /* VEX_W_0F44_P_2_LEN_0 */
10260 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10261 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10264 /* VEX_W_0F45_P_0_LEN_1 */
10265 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10266 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10269 /* VEX_W_0F45_P_2_LEN_1 */
10270 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10271 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10274 /* VEX_W_0F46_P_0_LEN_1 */
10275 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10276 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10279 /* VEX_W_0F46_P_2_LEN_1 */
10280 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10281 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10284 /* VEX_W_0F47_P_0_LEN_1 */
10285 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10286 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10289 /* VEX_W_0F47_P_2_LEN_1 */
10290 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10291 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10294 /* VEX_W_0F4A_P_0_LEN_1 */
10295 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10296 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10299 /* VEX_W_0F4A_P_2_LEN_1 */
10300 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10301 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10304 /* VEX_W_0F4B_P_0_LEN_1 */
10305 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10306 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10309 /* VEX_W_0F4B_P_2_LEN_1 */
10310 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10313 /* VEX_W_0F50_M_0 */
10314 { "vmovmskpX", { Gdq, XS }, 0 },
10317 /* VEX_W_0F51_P_0 */
10318 { "vsqrtps", { XM, EXx }, 0 },
10321 /* VEX_W_0F51_P_1 */
10322 { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10325 /* VEX_W_0F51_P_2 */
10326 { "vsqrtpd", { XM, EXx }, 0 },
10329 /* VEX_W_0F51_P_3 */
10330 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10333 /* VEX_W_0F52_P_0 */
10334 { "vrsqrtps", { XM, EXx }, 0 },
10337 /* VEX_W_0F52_P_1 */
10338 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10341 /* VEX_W_0F53_P_0 */
10342 { "vrcpps", { XM, EXx }, 0 },
10345 /* VEX_W_0F53_P_1 */
10346 { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
10349 /* VEX_W_0F58_P_0 */
10350 { "vaddps", { XM, Vex, EXx }, 0 },
10353 /* VEX_W_0F58_P_1 */
10354 { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
10357 /* VEX_W_0F58_P_2 */
10358 { "vaddpd", { XM, Vex, EXx }, 0 },
10361 /* VEX_W_0F58_P_3 */
10362 { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10365 /* VEX_W_0F59_P_0 */
10366 { "vmulps", { XM, Vex, EXx }, 0 },
10369 /* VEX_W_0F59_P_1 */
10370 { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
10373 /* VEX_W_0F59_P_2 */
10374 { "vmulpd", { XM, Vex, EXx }, 0 },
10377 /* VEX_W_0F59_P_3 */
10378 { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10381 /* VEX_W_0F5A_P_0 */
10382 { "vcvtps2pd", { XM, EXxmmq }, 0 },
10385 /* VEX_W_0F5A_P_1 */
10386 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
10389 /* VEX_W_0F5A_P_3 */
10390 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
10393 /* VEX_W_0F5B_P_0 */
10394 { "vcvtdq2ps", { XM, EXx }, 0 },
10397 /* VEX_W_0F5B_P_1 */
10398 { "vcvttps2dq", { XM, EXx }, 0 },
10401 /* VEX_W_0F5B_P_2 */
10402 { "vcvtps2dq", { XM, EXx }, 0 },
10405 /* VEX_W_0F5C_P_0 */
10406 { "vsubps", { XM, Vex, EXx }, 0 },
10409 /* VEX_W_0F5C_P_1 */
10410 { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
10413 /* VEX_W_0F5C_P_2 */
10414 { "vsubpd", { XM, Vex, EXx }, 0 },
10417 /* VEX_W_0F5C_P_3 */
10418 { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10421 /* VEX_W_0F5D_P_0 */
10422 { "vminps", { XM, Vex, EXx }, 0 },
10425 /* VEX_W_0F5D_P_1 */
10426 { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
10429 /* VEX_W_0F5D_P_2 */
10430 { "vminpd", { XM, Vex, EXx }, 0 },
10433 /* VEX_W_0F5D_P_3 */
10434 { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10437 /* VEX_W_0F5E_P_0 */
10438 { "vdivps", { XM, Vex, EXx }, 0 },
10441 /* VEX_W_0F5E_P_1 */
10442 { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
10445 /* VEX_W_0F5E_P_2 */
10446 { "vdivpd", { XM, Vex, EXx }, 0 },
10449 /* VEX_W_0F5E_P_3 */
10450 { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10453 /* VEX_W_0F5F_P_0 */
10454 { "vmaxps", { XM, Vex, EXx }, 0 },
10457 /* VEX_W_0F5F_P_1 */
10458 { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
10461 /* VEX_W_0F5F_P_2 */
10462 { "vmaxpd", { XM, Vex, EXx }, 0 },
10465 /* VEX_W_0F5F_P_3 */
10466 { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10469 /* VEX_W_0F60_P_2 */
10470 { "vpunpcklbw", { XM, Vex, EXx }, 0 },
10473 /* VEX_W_0F61_P_2 */
10474 { "vpunpcklwd", { XM, Vex, EXx }, 0 },
10477 /* VEX_W_0F62_P_2 */
10478 { "vpunpckldq", { XM, Vex, EXx }, 0 },
10481 /* VEX_W_0F63_P_2 */
10482 { "vpacksswb", { XM, Vex, EXx }, 0 },
10485 /* VEX_W_0F64_P_2 */
10486 { "vpcmpgtb", { XM, Vex, EXx }, 0 },
10489 /* VEX_W_0F65_P_2 */
10490 { "vpcmpgtw", { XM, Vex, EXx }, 0 },
10493 /* VEX_W_0F66_P_2 */
10494 { "vpcmpgtd", { XM, Vex, EXx }, 0 },
10497 /* VEX_W_0F67_P_2 */
10498 { "vpackuswb", { XM, Vex, EXx }, 0 },
10501 /* VEX_W_0F68_P_2 */
10502 { "vpunpckhbw", { XM, Vex, EXx }, 0 },
10505 /* VEX_W_0F69_P_2 */
10506 { "vpunpckhwd", { XM, Vex, EXx }, 0 },
10509 /* VEX_W_0F6A_P_2 */
10510 { "vpunpckhdq", { XM, Vex, EXx }, 0 },
10513 /* VEX_W_0F6B_P_2 */
10514 { "vpackssdw", { XM, Vex, EXx }, 0 },
10517 /* VEX_W_0F6C_P_2 */
10518 { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
10521 /* VEX_W_0F6D_P_2 */
10522 { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
10525 /* VEX_W_0F6F_P_1 */
10526 { "vmovdqu", { XM, EXx }, 0 },
10529 /* VEX_W_0F6F_P_2 */
10530 { "vmovdqa", { XM, EXx }, 0 },
10533 /* VEX_W_0F70_P_1 */
10534 { "vpshufhw", { XM, EXx, Ib }, 0 },
10537 /* VEX_W_0F70_P_2 */
10538 { "vpshufd", { XM, EXx, Ib }, 0 },
10541 /* VEX_W_0F70_P_3 */
10542 { "vpshuflw", { XM, EXx, Ib }, 0 },
10545 /* VEX_W_0F71_R_2_P_2 */
10546 { "vpsrlw", { Vex, XS, Ib }, 0 },
10549 /* VEX_W_0F71_R_4_P_2 */
10550 { "vpsraw", { Vex, XS, Ib }, 0 },
10553 /* VEX_W_0F71_R_6_P_2 */
10554 { "vpsllw", { Vex, XS, Ib }, 0 },
10557 /* VEX_W_0F72_R_2_P_2 */
10558 { "vpsrld", { Vex, XS, Ib }, 0 },
10561 /* VEX_W_0F72_R_4_P_2 */
10562 { "vpsrad", { Vex, XS, Ib }, 0 },
10565 /* VEX_W_0F72_R_6_P_2 */
10566 { "vpslld", { Vex, XS, Ib }, 0 },
10569 /* VEX_W_0F73_R_2_P_2 */
10570 { "vpsrlq", { Vex, XS, Ib }, 0 },
10573 /* VEX_W_0F73_R_3_P_2 */
10574 { "vpsrldq", { Vex, XS, Ib }, 0 },
10577 /* VEX_W_0F73_R_6_P_2 */
10578 { "vpsllq", { Vex, XS, Ib }, 0 },
10581 /* VEX_W_0F73_R_7_P_2 */
10582 { "vpslldq", { Vex, XS, Ib }, 0 },
10585 /* VEX_W_0F74_P_2 */
10586 { "vpcmpeqb", { XM, Vex, EXx }, 0 },
10589 /* VEX_W_0F75_P_2 */
10590 { "vpcmpeqw", { XM, Vex, EXx }, 0 },
10593 /* VEX_W_0F76_P_2 */
10594 { "vpcmpeqd", { XM, Vex, EXx }, 0 },
10597 /* VEX_W_0F77_P_0 */
10598 { "", { VZERO }, 0 },
10601 /* VEX_W_0F7C_P_2 */
10602 { "vhaddpd", { XM, Vex, EXx }, 0 },
10605 /* VEX_W_0F7C_P_3 */
10606 { "vhaddps", { XM, Vex, EXx }, 0 },
10609 /* VEX_W_0F7D_P_2 */
10610 { "vhsubpd", { XM, Vex, EXx }, 0 },
10613 /* VEX_W_0F7D_P_3 */
10614 { "vhsubps", { XM, Vex, EXx }, 0 },
10617 /* VEX_W_0F7E_P_1 */
10618 { "vmovq", { XMScalar, EXqScalar }, 0 },
10621 /* VEX_W_0F7F_P_1 */
10622 { "vmovdqu", { EXxS, XM }, 0 },
10625 /* VEX_W_0F7F_P_2 */
10626 { "vmovdqa", { EXxS, XM }, 0 },
10629 /* VEX_W_0F90_P_0_LEN_0 */
10630 { "kmovw", { MaskG, MaskE }, 0 },
10631 { "kmovq", { MaskG, MaskE }, 0 },
10634 /* VEX_W_0F90_P_2_LEN_0 */
10635 { "kmovb", { MaskG, MaskBDE }, 0 },
10636 { "kmovd", { MaskG, MaskBDE }, 0 },
10639 /* VEX_W_0F91_P_0_LEN_0 */
10640 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10641 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10644 /* VEX_W_0F91_P_2_LEN_0 */
10645 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10646 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10649 /* VEX_W_0F92_P_0_LEN_0 */
10650 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10653 /* VEX_W_0F92_P_2_LEN_0 */
10654 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10657 /* VEX_W_0F92_P_3_LEN_0 */
10658 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10659 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10662 /* VEX_W_0F93_P_0_LEN_0 */
10663 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10666 /* VEX_W_0F93_P_2_LEN_0 */
10667 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10670 /* VEX_W_0F93_P_3_LEN_0 */
10671 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10672 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10675 /* VEX_W_0F98_P_0_LEN_0 */
10676 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10677 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10680 /* VEX_W_0F98_P_2_LEN_0 */
10681 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10682 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10685 /* VEX_W_0F99_P_0_LEN_0 */
10686 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10687 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10690 /* VEX_W_0F99_P_2_LEN_0 */
10691 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10692 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10695 /* VEX_W_0FAE_R_2_M_0 */
10696 { "vldmxcsr", { Md }, 0 },
10699 /* VEX_W_0FAE_R_3_M_0 */
10700 { "vstmxcsr", { Md }, 0 },
10703 /* VEX_W_0FC2_P_0 */
10704 { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
10707 /* VEX_W_0FC2_P_1 */
10708 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10711 /* VEX_W_0FC2_P_2 */
10712 { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
10715 /* VEX_W_0FC2_P_3 */
10716 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10719 /* VEX_W_0FC4_P_2 */
10720 { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
10723 /* VEX_W_0FC5_P_2 */
10724 { "vpextrw", { Gdq, XS, Ib }, 0 },
10727 /* VEX_W_0FD0_P_2 */
10728 { "vaddsubpd", { XM, Vex, EXx }, 0 },
10731 /* VEX_W_0FD0_P_3 */
10732 { "vaddsubps", { XM, Vex, EXx }, 0 },
10735 /* VEX_W_0FD1_P_2 */
10736 { "vpsrlw", { XM, Vex, EXxmm }, 0 },
10739 /* VEX_W_0FD2_P_2 */
10740 { "vpsrld", { XM, Vex, EXxmm }, 0 },
10743 /* VEX_W_0FD3_P_2 */
10744 { "vpsrlq", { XM, Vex, EXxmm }, 0 },
10747 /* VEX_W_0FD4_P_2 */
10748 { "vpaddq", { XM, Vex, EXx }, 0 },
10751 /* VEX_W_0FD5_P_2 */
10752 { "vpmullw", { XM, Vex, EXx }, 0 },
10755 /* VEX_W_0FD6_P_2 */
10756 { "vmovq", { EXqScalarS, XMScalar }, 0 },
10759 /* VEX_W_0FD7_P_2_M_1 */
10760 { "vpmovmskb", { Gdq, XS }, 0 },
10763 /* VEX_W_0FD8_P_2 */
10764 { "vpsubusb", { XM, Vex, EXx }, 0 },
10767 /* VEX_W_0FD9_P_2 */
10768 { "vpsubusw", { XM, Vex, EXx }, 0 },
10771 /* VEX_W_0FDA_P_2 */
10772 { "vpminub", { XM, Vex, EXx }, 0 },
10775 /* VEX_W_0FDB_P_2 */
10776 { "vpand", { XM, Vex, EXx }, 0 },
10779 /* VEX_W_0FDC_P_2 */
10780 { "vpaddusb", { XM, Vex, EXx }, 0 },
10783 /* VEX_W_0FDD_P_2 */
10784 { "vpaddusw", { XM, Vex, EXx }, 0 },
10787 /* VEX_W_0FDE_P_2 */
10788 { "vpmaxub", { XM, Vex, EXx }, 0 },
10791 /* VEX_W_0FDF_P_2 */
10792 { "vpandn", { XM, Vex, EXx }, 0 },
10795 /* VEX_W_0FE0_P_2 */
10796 { "vpavgb", { XM, Vex, EXx }, 0 },
10799 /* VEX_W_0FE1_P_2 */
10800 { "vpsraw", { XM, Vex, EXxmm }, 0 },
10803 /* VEX_W_0FE2_P_2 */
10804 { "vpsrad", { XM, Vex, EXxmm }, 0 },
10807 /* VEX_W_0FE3_P_2 */
10808 { "vpavgw", { XM, Vex, EXx }, 0 },
10811 /* VEX_W_0FE4_P_2 */
10812 { "vpmulhuw", { XM, Vex, EXx }, 0 },
10815 /* VEX_W_0FE5_P_2 */
10816 { "vpmulhw", { XM, Vex, EXx }, 0 },
10819 /* VEX_W_0FE6_P_1 */
10820 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
10823 /* VEX_W_0FE6_P_2 */
10824 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
10827 /* VEX_W_0FE6_P_3 */
10828 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
10831 /* VEX_W_0FE7_P_2_M_0 */
10832 { "vmovntdq", { Mx, XM }, 0 },
10835 /* VEX_W_0FE8_P_2 */
10836 { "vpsubsb", { XM, Vex, EXx }, 0 },
10839 /* VEX_W_0FE9_P_2 */
10840 { "vpsubsw", { XM, Vex, EXx }, 0 },
10843 /* VEX_W_0FEA_P_2 */
10844 { "vpminsw", { XM, Vex, EXx }, 0 },
10847 /* VEX_W_0FEB_P_2 */
10848 { "vpor", { XM, Vex, EXx }, 0 },
10851 /* VEX_W_0FEC_P_2 */
10852 { "vpaddsb", { XM, Vex, EXx }, 0 },
10855 /* VEX_W_0FED_P_2 */
10856 { "vpaddsw", { XM, Vex, EXx }, 0 },
10859 /* VEX_W_0FEE_P_2 */
10860 { "vpmaxsw", { XM, Vex, EXx }, 0 },
10863 /* VEX_W_0FEF_P_2 */
10864 { "vpxor", { XM, Vex, EXx }, 0 },
10867 /* VEX_W_0FF0_P_3_M_0 */
10868 { "vlddqu", { XM, M }, 0 },
10871 /* VEX_W_0FF1_P_2 */
10872 { "vpsllw", { XM, Vex, EXxmm }, 0 },
10875 /* VEX_W_0FF2_P_2 */
10876 { "vpslld", { XM, Vex, EXxmm }, 0 },
10879 /* VEX_W_0FF3_P_2 */
10880 { "vpsllq", { XM, Vex, EXxmm }, 0 },
10883 /* VEX_W_0FF4_P_2 */
10884 { "vpmuludq", { XM, Vex, EXx }, 0 },
10887 /* VEX_W_0FF5_P_2 */
10888 { "vpmaddwd", { XM, Vex, EXx }, 0 },
10891 /* VEX_W_0FF6_P_2 */
10892 { "vpsadbw", { XM, Vex, EXx }, 0 },
10895 /* VEX_W_0FF7_P_2 */
10896 { "vmaskmovdqu", { XM, XS }, 0 },
10899 /* VEX_W_0FF8_P_2 */
10900 { "vpsubb", { XM, Vex, EXx }, 0 },
10903 /* VEX_W_0FF9_P_2 */
10904 { "vpsubw", { XM, Vex, EXx }, 0 },
10907 /* VEX_W_0FFA_P_2 */
10908 { "vpsubd", { XM, Vex, EXx }, 0 },
10911 /* VEX_W_0FFB_P_2 */
10912 { "vpsubq", { XM, Vex, EXx }, 0 },
10915 /* VEX_W_0FFC_P_2 */
10916 { "vpaddb", { XM, Vex, EXx }, 0 },
10919 /* VEX_W_0FFD_P_2 */
10920 { "vpaddw", { XM, Vex, EXx }, 0 },
10923 /* VEX_W_0FFE_P_2 */
10924 { "vpaddd", { XM, Vex, EXx }, 0 },
10927 /* VEX_W_0F3800_P_2 */
10928 { "vpshufb", { XM, Vex, EXx }, 0 },
10931 /* VEX_W_0F3801_P_2 */
10932 { "vphaddw", { XM, Vex, EXx }, 0 },
10935 /* VEX_W_0F3802_P_2 */
10936 { "vphaddd", { XM, Vex, EXx }, 0 },
10939 /* VEX_W_0F3803_P_2 */
10940 { "vphaddsw", { XM, Vex, EXx }, 0 },
10943 /* VEX_W_0F3804_P_2 */
10944 { "vpmaddubsw", { XM, Vex, EXx }, 0 },
10947 /* VEX_W_0F3805_P_2 */
10948 { "vphsubw", { XM, Vex, EXx }, 0 },
10951 /* VEX_W_0F3806_P_2 */
10952 { "vphsubd", { XM, Vex, EXx }, 0 },
10955 /* VEX_W_0F3807_P_2 */
10956 { "vphsubsw", { XM, Vex, EXx }, 0 },
10959 /* VEX_W_0F3808_P_2 */
10960 { "vpsignb", { XM, Vex, EXx }, 0 },
10963 /* VEX_W_0F3809_P_2 */
10964 { "vpsignw", { XM, Vex, EXx }, 0 },
10967 /* VEX_W_0F380A_P_2 */
10968 { "vpsignd", { XM, Vex, EXx }, 0 },
10971 /* VEX_W_0F380B_P_2 */
10972 { "vpmulhrsw", { XM, Vex, EXx }, 0 },
10975 /* VEX_W_0F380C_P_2 */
10976 { "vpermilps", { XM, Vex, EXx }, 0 },
10979 /* VEX_W_0F380D_P_2 */
10980 { "vpermilpd", { XM, Vex, EXx }, 0 },
10983 /* VEX_W_0F380E_P_2 */
10984 { "vtestps", { XM, EXx }, 0 },
10987 /* VEX_W_0F380F_P_2 */
10988 { "vtestpd", { XM, EXx }, 0 },
10991 /* VEX_W_0F3816_P_2 */
10992 { "vpermps", { XM, Vex, EXx }, 0 },
10995 /* VEX_W_0F3817_P_2 */
10996 { "vptest", { XM, EXx }, 0 },
10999 /* VEX_W_0F3818_P_2 */
11000 { "vbroadcastss", { XM, EXxmm_md }, 0 },
11003 /* VEX_W_0F3819_P_2 */
11004 { "vbroadcastsd", { XM, EXxmm_mq }, 0 },
11007 /* VEX_W_0F381A_P_2_M_0 */
11008 { "vbroadcastf128", { XM, Mxmm }, 0 },
11011 /* VEX_W_0F381C_P_2 */
11012 { "vpabsb", { XM, EXx }, 0 },
11015 /* VEX_W_0F381D_P_2 */
11016 { "vpabsw", { XM, EXx }, 0 },
11019 /* VEX_W_0F381E_P_2 */
11020 { "vpabsd", { XM, EXx }, 0 },
11023 /* VEX_W_0F3820_P_2 */
11024 { "vpmovsxbw", { XM, EXxmmq }, 0 },
11027 /* VEX_W_0F3821_P_2 */
11028 { "vpmovsxbd", { XM, EXxmmqd }, 0 },
11031 /* VEX_W_0F3822_P_2 */
11032 { "vpmovsxbq", { XM, EXxmmdw }, 0 },
11035 /* VEX_W_0F3823_P_2 */
11036 { "vpmovsxwd", { XM, EXxmmq }, 0 },
11039 /* VEX_W_0F3824_P_2 */
11040 { "vpmovsxwq", { XM, EXxmmqd }, 0 },
11043 /* VEX_W_0F3825_P_2 */
11044 { "vpmovsxdq", { XM, EXxmmq }, 0 },
11047 /* VEX_W_0F3828_P_2 */
11048 { "vpmuldq", { XM, Vex, EXx }, 0 },
11051 /* VEX_W_0F3829_P_2 */
11052 { "vpcmpeqq", { XM, Vex, EXx }, 0 },
11055 /* VEX_W_0F382A_P_2_M_0 */
11056 { "vmovntdqa", { XM, Mx }, 0 },
11059 /* VEX_W_0F382B_P_2 */
11060 { "vpackusdw", { XM, Vex, EXx }, 0 },
11063 /* VEX_W_0F382C_P_2_M_0 */
11064 { "vmaskmovps", { XM, Vex, Mx }, 0 },
11067 /* VEX_W_0F382D_P_2_M_0 */
11068 { "vmaskmovpd", { XM, Vex, Mx }, 0 },
11071 /* VEX_W_0F382E_P_2_M_0 */
11072 { "vmaskmovps", { Mx, Vex, XM }, 0 },
11075 /* VEX_W_0F382F_P_2_M_0 */
11076 { "vmaskmovpd", { Mx, Vex, XM }, 0 },
11079 /* VEX_W_0F3830_P_2 */
11080 { "vpmovzxbw", { XM, EXxmmq }, 0 },
11083 /* VEX_W_0F3831_P_2 */
11084 { "vpmovzxbd", { XM, EXxmmqd }, 0 },
11087 /* VEX_W_0F3832_P_2 */
11088 { "vpmovzxbq", { XM, EXxmmdw }, 0 },
11091 /* VEX_W_0F3833_P_2 */
11092 { "vpmovzxwd", { XM, EXxmmq }, 0 },
11095 /* VEX_W_0F3834_P_2 */
11096 { "vpmovzxwq", { XM, EXxmmqd }, 0 },
11099 /* VEX_W_0F3835_P_2 */
11100 { "vpmovzxdq", { XM, EXxmmq }, 0 },
11103 /* VEX_W_0F3836_P_2 */
11104 { "vpermd", { XM, Vex, EXx }, 0 },
11107 /* VEX_W_0F3837_P_2 */
11108 { "vpcmpgtq", { XM, Vex, EXx }, 0 },
11111 /* VEX_W_0F3838_P_2 */
11112 { "vpminsb", { XM, Vex, EXx }, 0 },
11115 /* VEX_W_0F3839_P_2 */
11116 { "vpminsd", { XM, Vex, EXx }, 0 },
11119 /* VEX_W_0F383A_P_2 */
11120 { "vpminuw", { XM, Vex, EXx }, 0 },
11123 /* VEX_W_0F383B_P_2 */
11124 { "vpminud", { XM, Vex, EXx }, 0 },
11127 /* VEX_W_0F383C_P_2 */
11128 { "vpmaxsb", { XM, Vex, EXx }, 0 },
11131 /* VEX_W_0F383D_P_2 */
11132 { "vpmaxsd", { XM, Vex, EXx }, 0 },
11135 /* VEX_W_0F383E_P_2 */
11136 { "vpmaxuw", { XM, Vex, EXx }, 0 },
11139 /* VEX_W_0F383F_P_2 */
11140 { "vpmaxud", { XM, Vex, EXx }, 0 },
11143 /* VEX_W_0F3840_P_2 */
11144 { "vpmulld", { XM, Vex, EXx }, 0 },
11147 /* VEX_W_0F3841_P_2 */
11148 { "vphminposuw", { XM, EXx }, 0 },
11151 /* VEX_W_0F3846_P_2 */
11152 { "vpsravd", { XM, Vex, EXx }, 0 },
11155 /* VEX_W_0F3858_P_2 */
11156 { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11159 /* VEX_W_0F3859_P_2 */
11160 { "vpbroadcastq", { XM, EXxmm_mq }, 0 },
11163 /* VEX_W_0F385A_P_2_M_0 */
11164 { "vbroadcasti128", { XM, Mxmm }, 0 },
11167 /* VEX_W_0F3878_P_2 */
11168 { "vpbroadcastb", { XM, EXxmm_mb }, 0 },
11171 /* VEX_W_0F3879_P_2 */
11172 { "vpbroadcastw", { XM, EXxmm_mw }, 0 },
11175 /* VEX_W_0F38DB_P_2 */
11176 { "vaesimc", { XM, EXx }, 0 },
11179 /* VEX_W_0F38DC_P_2 */
11180 { "vaesenc", { XM, Vex128, EXx }, 0 },
11183 /* VEX_W_0F38DD_P_2 */
11184 { "vaesenclast", { XM, Vex128, EXx }, 0 },
11187 /* VEX_W_0F38DE_P_2 */
11188 { "vaesdec", { XM, Vex128, EXx }, 0 },
11191 /* VEX_W_0F38DF_P_2 */
11192 { "vaesdeclast", { XM, Vex128, EXx }, 0 },
11195 /* VEX_W_0F3A00_P_2 */
11197 { "vpermq", { XM, EXx, Ib }, 0 },
11200 /* VEX_W_0F3A01_P_2 */
11202 { "vpermpd", { XM, EXx, Ib }, 0 },
11205 /* VEX_W_0F3A02_P_2 */
11206 { "vpblendd", { XM, Vex, EXx, Ib }, 0 },
11209 /* VEX_W_0F3A04_P_2 */
11210 { "vpermilps", { XM, EXx, Ib }, 0 },
11213 /* VEX_W_0F3A05_P_2 */
11214 { "vpermilpd", { XM, EXx, Ib }, 0 },
11217 /* VEX_W_0F3A06_P_2 */
11218 { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 },
11221 /* VEX_W_0F3A08_P_2 */
11222 { "vroundps", { XM, EXx, Ib }, 0 },
11225 /* VEX_W_0F3A09_P_2 */
11226 { "vroundpd", { XM, EXx, Ib }, 0 },
11229 /* VEX_W_0F3A0A_P_2 */
11230 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11233 /* VEX_W_0F3A0B_P_2 */
11234 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11237 /* VEX_W_0F3A0C_P_2 */
11238 { "vblendps", { XM, Vex, EXx, Ib }, 0 },
11241 /* VEX_W_0F3A0D_P_2 */
11242 { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
11245 /* VEX_W_0F3A0E_P_2 */
11246 { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
11249 /* VEX_W_0F3A0F_P_2 */
11250 { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
11253 /* VEX_W_0F3A14_P_2 */
11254 { "vpextrb", { Edqb, XM, Ib }, 0 },
11257 /* VEX_W_0F3A15_P_2 */
11258 { "vpextrw", { Edqw, XM, Ib }, 0 },
11261 /* VEX_W_0F3A18_P_2 */
11262 { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 },
11265 /* VEX_W_0F3A19_P_2 */
11266 { "vextractf128", { EXxmm, XM, Ib }, 0 },
11269 /* VEX_W_0F3A20_P_2 */
11270 { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
11273 /* VEX_W_0F3A21_P_2 */
11274 { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
11277 /* VEX_W_0F3A30_P_2_LEN_0 */
11278 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11279 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11282 /* VEX_W_0F3A31_P_2_LEN_0 */
11283 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11284 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11287 /* VEX_W_0F3A32_P_2_LEN_0 */
11288 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11289 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11292 /* VEX_W_0F3A33_P_2_LEN_0 */
11293 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11294 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11297 /* VEX_W_0F3A38_P_2 */
11298 { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 },
11301 /* VEX_W_0F3A39_P_2 */
11302 { "vextracti128", { EXxmm, XM, Ib }, 0 },
11305 /* VEX_W_0F3A40_P_2 */
11306 { "vdpps", { XM, Vex, EXx, Ib }, 0 },
11309 /* VEX_W_0F3A41_P_2 */
11310 { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
11313 /* VEX_W_0F3A42_P_2 */
11314 { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
11317 /* VEX_W_0F3A44_P_2 */
11318 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL }, 0 },
11321 /* VEX_W_0F3A46_P_2 */
11322 { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
11325 /* VEX_W_0F3A48_P_2 */
11326 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11327 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11330 /* VEX_W_0F3A49_P_2 */
11331 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11332 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11335 /* VEX_W_0F3A4A_P_2 */
11336 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 },
11339 /* VEX_W_0F3A4B_P_2 */
11340 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 },
11343 /* VEX_W_0F3A4C_P_2 */
11344 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
11347 /* VEX_W_0F3A60_P_2 */
11348 { "vpcmpestrm", { XM, EXx, Ib }, 0 },
11351 /* VEX_W_0F3A61_P_2 */
11352 { "vpcmpestri", { XM, EXx, Ib }, 0 },
11355 /* VEX_W_0F3A62_P_2 */
11356 { "vpcmpistrm", { XM, EXx, Ib }, 0 },
11359 /* VEX_W_0F3A63_P_2 */
11360 { "vpcmpistri", { XM, EXx, Ib }, 0 },
11363 /* VEX_W_0F3ADF_P_2 */
11364 { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11366 #define NEED_VEX_W_TABLE
11367 #include "i386-dis-evex.h"
11368 #undef NEED_VEX_W_TABLE
11371 static const struct dis386 mod_table[][2] = {
11374 { "leaS", { Gv, M }, 0 },
11379 { RM_TABLE (RM_C6_REG_7) },
11384 { RM_TABLE (RM_C7_REG_7) },
11388 { "Jcall^", { indirEp }, 0 },
11392 { "Jjmp^", { indirEp }, 0 },
11395 /* MOD_0F01_REG_0 */
11396 { X86_64_TABLE (X86_64_0F01_REG_0) },
11397 { RM_TABLE (RM_0F01_REG_0) },
11400 /* MOD_0F01_REG_1 */
11401 { X86_64_TABLE (X86_64_0F01_REG_1) },
11402 { RM_TABLE (RM_0F01_REG_1) },
11405 /* MOD_0F01_REG_2 */
11406 { X86_64_TABLE (X86_64_0F01_REG_2) },
11407 { RM_TABLE (RM_0F01_REG_2) },
11410 /* MOD_0F01_REG_3 */
11411 { X86_64_TABLE (X86_64_0F01_REG_3) },
11412 { RM_TABLE (RM_0F01_REG_3) },
11415 /* MOD_0F01_REG_5 */
11417 { RM_TABLE (RM_0F01_REG_5) },
11420 /* MOD_0F01_REG_7 */
11421 { "invlpg", { Mb }, 0 },
11422 { RM_TABLE (RM_0F01_REG_7) },
11425 /* MOD_0F12_PREFIX_0 */
11426 { "movlps", { XM, EXq }, PREFIX_OPCODE },
11427 { "movhlps", { XM, EXq }, PREFIX_OPCODE },
11431 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
11434 /* MOD_0F16_PREFIX_0 */
11435 { "movhps", { XM, EXq }, 0 },
11436 { "movlhps", { XM, EXq }, 0 },
11440 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
11443 /* MOD_0F18_REG_0 */
11444 { "prefetchnta", { Mb }, 0 },
11447 /* MOD_0F18_REG_1 */
11448 { "prefetcht0", { Mb }, 0 },
11451 /* MOD_0F18_REG_2 */
11452 { "prefetcht1", { Mb }, 0 },
11455 /* MOD_0F18_REG_3 */
11456 { "prefetcht2", { Mb }, 0 },
11459 /* MOD_0F18_REG_4 */
11460 { "nop/reserved", { Mb }, 0 },
11463 /* MOD_0F18_REG_5 */
11464 { "nop/reserved", { Mb }, 0 },
11467 /* MOD_0F18_REG_6 */
11468 { "nop/reserved", { Mb }, 0 },
11471 /* MOD_0F18_REG_7 */
11472 { "nop/reserved", { Mb }, 0 },
11475 /* MOD_0F1A_PREFIX_0 */
11476 { "bndldx", { Gbnd, Ev_bnd }, 0 },
11477 { "nopQ", { Ev }, 0 },
11480 /* MOD_0F1B_PREFIX_0 */
11481 { "bndstx", { Ev_bnd, Gbnd }, 0 },
11482 { "nopQ", { Ev }, 0 },
11485 /* MOD_0F1B_PREFIX_1 */
11486 { "bndmk", { Gbnd, Ev_bnd }, 0 },
11487 { "nopQ", { Ev }, 0 },
11492 { "movL", { Rd, Td }, 0 },
11497 { "movL", { Td, Rd }, 0 },
11500 /* MOD_0F2B_PREFIX_0 */
11501 {"movntps", { Mx, XM }, PREFIX_OPCODE },
11504 /* MOD_0F2B_PREFIX_1 */
11505 {"movntss", { Md, XM }, PREFIX_OPCODE },
11508 /* MOD_0F2B_PREFIX_2 */
11509 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
11512 /* MOD_0F2B_PREFIX_3 */
11513 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
11518 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
11521 /* MOD_0F71_REG_2 */
11523 { "psrlw", { MS, Ib }, 0 },
11526 /* MOD_0F71_REG_4 */
11528 { "psraw", { MS, Ib }, 0 },
11531 /* MOD_0F71_REG_6 */
11533 { "psllw", { MS, Ib }, 0 },
11536 /* MOD_0F72_REG_2 */
11538 { "psrld", { MS, Ib }, 0 },
11541 /* MOD_0F72_REG_4 */
11543 { "psrad", { MS, Ib }, 0 },
11546 /* MOD_0F72_REG_6 */
11548 { "pslld", { MS, Ib }, 0 },
11551 /* MOD_0F73_REG_2 */
11553 { "psrlq", { MS, Ib }, 0 },
11556 /* MOD_0F73_REG_3 */
11558 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11561 /* MOD_0F73_REG_6 */
11563 { "psllq", { MS, Ib }, 0 },
11566 /* MOD_0F73_REG_7 */
11568 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11571 /* MOD_0FAE_REG_0 */
11572 { "fxsave", { FXSAVE }, 0 },
11573 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11576 /* MOD_0FAE_REG_1 */
11577 { "fxrstor", { FXSAVE }, 0 },
11578 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11581 /* MOD_0FAE_REG_2 */
11582 { "ldmxcsr", { Md }, 0 },
11583 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11586 /* MOD_0FAE_REG_3 */
11587 { "stmxcsr", { Md }, 0 },
11588 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11591 /* MOD_0FAE_REG_4 */
11592 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11593 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11596 /* MOD_0FAE_REG_5 */
11597 { "xrstor", { FXSAVE }, 0 },
11598 { RM_TABLE (RM_0FAE_REG_5) },
11601 /* MOD_0FAE_REG_6 */
11602 { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11603 { RM_TABLE (RM_0FAE_REG_6) },
11606 /* MOD_0FAE_REG_7 */
11607 { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11608 { RM_TABLE (RM_0FAE_REG_7) },
11612 { "lssS", { Gv, Mp }, 0 },
11616 { "lfsS", { Gv, Mp }, 0 },
11620 { "lgsS", { Gv, Mp }, 0 },
11624 { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11627 /* MOD_0FC7_REG_3 */
11628 { "xrstors", { FXSAVE }, 0 },
11631 /* MOD_0FC7_REG_4 */
11632 { "xsavec", { FXSAVE }, 0 },
11635 /* MOD_0FC7_REG_5 */
11636 { "xsaves", { FXSAVE }, 0 },
11639 /* MOD_0FC7_REG_6 */
11640 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11641 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11644 /* MOD_0FC7_REG_7 */
11645 { "vmptrst", { Mq }, 0 },
11646 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11651 { "pmovmskb", { Gdq, MS }, 0 },
11654 /* MOD_0FE7_PREFIX_2 */
11655 { "movntdq", { Mx, XM }, 0 },
11658 /* MOD_0FF0_PREFIX_3 */
11659 { "lddqu", { XM, M }, 0 },
11662 /* MOD_0F382A_PREFIX_2 */
11663 { "movntdqa", { XM, Mx }, 0 },
11667 { "bound{S|}", { Gv, Ma }, 0 },
11668 { EVEX_TABLE (EVEX_0F) },
11672 { "lesS", { Gv, Mp }, 0 },
11673 { VEX_C4_TABLE (VEX_0F) },
11677 { "ldsS", { Gv, Mp }, 0 },
11678 { VEX_C5_TABLE (VEX_0F) },
11681 /* MOD_VEX_0F12_PREFIX_0 */
11682 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11683 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11687 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11690 /* MOD_VEX_0F16_PREFIX_0 */
11691 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11692 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11696 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11700 { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11703 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11705 { "kandw", { MaskG, MaskVex, MaskR }, 0 },
11708 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11710 { "kandq", { MaskG, MaskVex, MaskR }, 0 },
11713 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11715 { "kandb", { MaskG, MaskVex, MaskR }, 0 },
11718 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11720 { "kandd", { MaskG, MaskVex, MaskR }, 0 },
11723 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11725 { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
11728 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11730 { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
11733 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11735 { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
11738 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11740 { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
11743 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11745 { "knotw", { MaskG, MaskR }, 0 },
11748 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11750 { "knotq", { MaskG, MaskR }, 0 },
11753 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11755 { "knotb", { MaskG, MaskR }, 0 },
11758 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11760 { "knotd", { MaskG, MaskR }, 0 },
11763 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11765 { "korw", { MaskG, MaskVex, MaskR }, 0 },
11768 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11770 { "korq", { MaskG, MaskVex, MaskR }, 0 },
11773 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11775 { "korb", { MaskG, MaskVex, MaskR }, 0 },
11778 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11780 { "kord", { MaskG, MaskVex, MaskR }, 0 },
11783 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11785 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
11788 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11790 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
11793 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11795 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
11798 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11800 { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
11803 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11805 { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
11808 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11810 { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
11813 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11815 { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
11818 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11820 { "kxord", { MaskG, MaskVex, MaskR }, 0 },
11823 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11825 { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
11828 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11830 { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
11833 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11835 { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
11838 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11840 { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
11843 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11845 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
11848 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11850 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
11853 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11855 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
11860 { VEX_W_TABLE (VEX_W_0F50_M_0) },
11863 /* MOD_VEX_0F71_REG_2 */
11865 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11868 /* MOD_VEX_0F71_REG_4 */
11870 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11873 /* MOD_VEX_0F71_REG_6 */
11875 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11878 /* MOD_VEX_0F72_REG_2 */
11880 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11883 /* MOD_VEX_0F72_REG_4 */
11885 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11888 /* MOD_VEX_0F72_REG_6 */
11890 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11893 /* MOD_VEX_0F73_REG_2 */
11895 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11898 /* MOD_VEX_0F73_REG_3 */
11900 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11903 /* MOD_VEX_0F73_REG_6 */
11905 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11908 /* MOD_VEX_0F73_REG_7 */
11910 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11913 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11914 { "kmovw", { Ew, MaskG }, 0 },
11918 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11919 { "kmovq", { Eq, MaskG }, 0 },
11923 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11924 { "kmovb", { Eb, MaskG }, 0 },
11928 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11929 { "kmovd", { Ed, MaskG }, 0 },
11933 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
11935 { "kmovw", { MaskG, Rdq }, 0 },
11938 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
11940 { "kmovb", { MaskG, Rdq }, 0 },
11943 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
11945 { "kmovd", { MaskG, Rdq }, 0 },
11948 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
11950 { "kmovq", { MaskG, Rdq }, 0 },
11953 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
11955 { "kmovw", { Gdq, MaskR }, 0 },
11958 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
11960 { "kmovb", { Gdq, MaskR }, 0 },
11963 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
11965 { "kmovd", { Gdq, MaskR }, 0 },
11968 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
11970 { "kmovq", { Gdq, MaskR }, 0 },
11973 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
11975 { "kortestw", { MaskG, MaskR }, 0 },
11978 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
11980 { "kortestq", { MaskG, MaskR }, 0 },
11983 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
11985 { "kortestb", { MaskG, MaskR }, 0 },
11988 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
11990 { "kortestd", { MaskG, MaskR }, 0 },
11993 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
11995 { "ktestw", { MaskG, MaskR }, 0 },
11998 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12000 { "ktestq", { MaskG, MaskR }, 0 },
12003 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12005 { "ktestb", { MaskG, MaskR }, 0 },
12008 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12010 { "ktestd", { MaskG, MaskR }, 0 },
12013 /* MOD_VEX_0FAE_REG_2 */
12014 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12017 /* MOD_VEX_0FAE_REG_3 */
12018 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12021 /* MOD_VEX_0FD7_PREFIX_2 */
12023 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12026 /* MOD_VEX_0FE7_PREFIX_2 */
12027 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12030 /* MOD_VEX_0FF0_PREFIX_3 */
12031 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12034 /* MOD_VEX_0F381A_PREFIX_2 */
12035 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12038 /* MOD_VEX_0F382A_PREFIX_2 */
12039 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12042 /* MOD_VEX_0F382C_PREFIX_2 */
12043 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12046 /* MOD_VEX_0F382D_PREFIX_2 */
12047 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12050 /* MOD_VEX_0F382E_PREFIX_2 */
12051 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12054 /* MOD_VEX_0F382F_PREFIX_2 */
12055 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12058 /* MOD_VEX_0F385A_PREFIX_2 */
12059 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12062 /* MOD_VEX_0F388C_PREFIX_2 */
12063 { "vpmaskmov%LW", { XM, Vex, Mx }, 0 },
12066 /* MOD_VEX_0F388E_PREFIX_2 */
12067 { "vpmaskmov%LW", { Mx, Vex, XM }, 0 },
12070 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12072 { "kshiftrb", { MaskG, MaskR, Ib }, 0 },
12075 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12077 { "kshiftrw", { MaskG, MaskR, Ib }, 0 },
12080 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12082 { "kshiftrd", { MaskG, MaskR, Ib }, 0 },
12085 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12087 { "kshiftrq", { MaskG, MaskR, Ib }, 0 },
12090 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12092 { "kshiftlb", { MaskG, MaskR, Ib }, 0 },
12095 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12097 { "kshiftlw", { MaskG, MaskR, Ib }, 0 },
12100 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12102 { "kshiftld", { MaskG, MaskR, Ib }, 0 },
12105 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12107 { "kshiftlq", { MaskG, MaskR, Ib }, 0 },
12109 #define NEED_MOD_TABLE
12110 #include "i386-dis-evex.h"
12111 #undef NEED_MOD_TABLE
12114 static const struct dis386 rm_table[][8] = {
12117 { "xabort", { Skip_MODRM, Ib }, 0 },
12121 { "xbeginT", { Skip_MODRM, Jv }, 0 },
12124 /* RM_0F01_REG_0 */
12126 { "vmcall", { Skip_MODRM }, 0 },
12127 { "vmlaunch", { Skip_MODRM }, 0 },
12128 { "vmresume", { Skip_MODRM }, 0 },
12129 { "vmxoff", { Skip_MODRM }, 0 },
12132 /* RM_0F01_REG_1 */
12133 { "monitor", { { OP_Monitor, 0 } }, 0 },
12134 { "mwait", { { OP_Mwait, 0 } }, 0 },
12135 { "clac", { Skip_MODRM }, 0 },
12136 { "stac", { Skip_MODRM }, 0 },
12140 { "encls", { Skip_MODRM }, 0 },
12143 /* RM_0F01_REG_2 */
12144 { "xgetbv", { Skip_MODRM }, 0 },
12145 { "xsetbv", { Skip_MODRM }, 0 },
12148 { "vmfunc", { Skip_MODRM }, 0 },
12149 { "xend", { Skip_MODRM }, 0 },
12150 { "xtest", { Skip_MODRM }, 0 },
12151 { "enclu", { Skip_MODRM }, 0 },
12154 /* RM_0F01_REG_3 */
12155 { "vmrun", { Skip_MODRM }, 0 },
12156 { "vmmcall", { Skip_MODRM }, 0 },
12157 { "vmload", { Skip_MODRM }, 0 },
12158 { "vmsave", { Skip_MODRM }, 0 },
12159 { "stgi", { Skip_MODRM }, 0 },
12160 { "clgi", { Skip_MODRM }, 0 },
12161 { "skinit", { Skip_MODRM }, 0 },
12162 { "invlpga", { Skip_MODRM }, 0 },
12165 /* RM_0F01_REG_5 */
12172 { "rdpkru", { Skip_MODRM }, 0 },
12173 { "wrpkru", { Skip_MODRM }, 0 },
12176 /* RM_0F01_REG_7 */
12177 { "swapgs", { Skip_MODRM }, 0 },
12178 { "rdtscp", { Skip_MODRM }, 0 },
12179 { "monitorx", { { OP_Monitor, 0 } }, 0 },
12180 { "mwaitx", { { OP_Mwaitx, 0 } }, 0 },
12181 { "clzero", { Skip_MODRM }, 0 },
12184 /* RM_0FAE_REG_5 */
12185 { "lfence", { Skip_MODRM }, 0 },
12188 /* RM_0FAE_REG_6 */
12189 { "mfence", { Skip_MODRM }, 0 },
12192 /* RM_0FAE_REG_7 */
12193 { "sfence", { Skip_MODRM }, 0 },
12198 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12200 /* We use the high bit to indicate different name for the same
12202 #define REP_PREFIX (0xf3 | 0x100)
12203 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12204 #define XRELEASE_PREFIX (0xf3 | 0x400)
12205 #define BND_PREFIX (0xf2 | 0x400)
12210 int newrex, i, length;
12216 last_lock_prefix = -1;
12217 last_repz_prefix = -1;
12218 last_repnz_prefix = -1;
12219 last_data_prefix = -1;
12220 last_addr_prefix = -1;
12221 last_rex_prefix = -1;
12222 last_seg_prefix = -1;
12224 active_seg_prefix = 0;
12225 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12226 all_prefixes[i] = 0;
12229 /* The maximum instruction length is 15bytes. */
12230 while (length < MAX_CODE_LENGTH - 1)
12232 FETCH_DATA (the_info, codep + 1);
12236 /* REX prefixes family. */
12253 if (address_mode == mode_64bit)
12257 last_rex_prefix = i;
12260 prefixes |= PREFIX_REPZ;
12261 last_repz_prefix = i;
12264 prefixes |= PREFIX_REPNZ;
12265 last_repnz_prefix = i;
12268 prefixes |= PREFIX_LOCK;
12269 last_lock_prefix = i;
12272 prefixes |= PREFIX_CS;
12273 last_seg_prefix = i;
12274 active_seg_prefix = PREFIX_CS;
12277 prefixes |= PREFIX_SS;
12278 last_seg_prefix = i;
12279 active_seg_prefix = PREFIX_SS;
12282 prefixes |= PREFIX_DS;
12283 last_seg_prefix = i;
12284 active_seg_prefix = PREFIX_DS;
12287 prefixes |= PREFIX_ES;
12288 last_seg_prefix = i;
12289 active_seg_prefix = PREFIX_ES;
12292 prefixes |= PREFIX_FS;
12293 last_seg_prefix = i;
12294 active_seg_prefix = PREFIX_FS;
12297 prefixes |= PREFIX_GS;
12298 last_seg_prefix = i;
12299 active_seg_prefix = PREFIX_GS;
12302 prefixes |= PREFIX_DATA;
12303 last_data_prefix = i;
12306 prefixes |= PREFIX_ADDR;
12307 last_addr_prefix = i;
12310 /* fwait is really an instruction. If there are prefixes
12311 before the fwait, they belong to the fwait, *not* to the
12312 following instruction. */
12314 if (prefixes || rex)
12316 prefixes |= PREFIX_FWAIT;
12318 /* This ensures that the previous REX prefixes are noticed
12319 as unused prefixes, as in the return case below. */
12323 prefixes = PREFIX_FWAIT;
12328 /* Rex is ignored when followed by another prefix. */
12334 if (*codep != FWAIT_OPCODE)
12335 all_prefixes[i++] = *codep;
12343 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12346 static const char *
12347 prefix_name (int pref, int sizeflag)
12349 static const char *rexes [16] =
12352 "rex.B", /* 0x41 */
12353 "rex.X", /* 0x42 */
12354 "rex.XB", /* 0x43 */
12355 "rex.R", /* 0x44 */
12356 "rex.RB", /* 0x45 */
12357 "rex.RX", /* 0x46 */
12358 "rex.RXB", /* 0x47 */
12359 "rex.W", /* 0x48 */
12360 "rex.WB", /* 0x49 */
12361 "rex.WX", /* 0x4a */
12362 "rex.WXB", /* 0x4b */
12363 "rex.WR", /* 0x4c */
12364 "rex.WRB", /* 0x4d */
12365 "rex.WRX", /* 0x4e */
12366 "rex.WRXB", /* 0x4f */
12371 /* REX prefixes family. */
12388 return rexes [pref - 0x40];
12408 return (sizeflag & DFLAG) ? "data16" : "data32";
12410 if (address_mode == mode_64bit)
12411 return (sizeflag & AFLAG) ? "addr32" : "addr64";
12413 return (sizeflag & AFLAG) ? "addr16" : "addr32";
12418 case XACQUIRE_PREFIX:
12420 case XRELEASE_PREFIX:
12429 static char op_out[MAX_OPERANDS][100];
12430 static int op_ad, op_index[MAX_OPERANDS];
12431 static int two_source_ops;
12432 static bfd_vma op_address[MAX_OPERANDS];
12433 static bfd_vma op_riprel[MAX_OPERANDS];
12434 static bfd_vma start_pc;
12437 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12438 * (see topic "Redundant prefixes" in the "Differences from 8086"
12439 * section of the "Virtual 8086 Mode" chapter.)
12440 * 'pc' should be the address of this instruction, it will
12441 * be used to print the target address if this is a relative jump or call
12442 * The function returns the length of this instruction in bytes.
12445 static char intel_syntax;
12446 static char intel_mnemonic = !SYSV386_COMPAT;
12447 static char open_char;
12448 static char close_char;
12449 static char separator_char;
12450 static char scale_char;
12458 static enum x86_64_isa isa64;
12460 /* Here for backwards compatibility. When gdb stops using
12461 print_insn_i386_att and print_insn_i386_intel these functions can
12462 disappear, and print_insn_i386 be merged into print_insn. */
12464 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12468 return print_insn (pc, info);
12472 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12476 return print_insn (pc, info);
12480 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12484 return print_insn (pc, info);
12488 print_i386_disassembler_options (FILE *stream)
12490 fprintf (stream, _("\n\
12491 The following i386/x86-64 specific disassembler options are supported for use\n\
12492 with the -M switch (multiple options should be separated by commas):\n"));
12494 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
12495 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
12496 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
12497 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
12498 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
12499 fprintf (stream, _(" att-mnemonic\n"
12500 " Display instruction in AT&T mnemonic\n"));
12501 fprintf (stream, _(" intel-mnemonic\n"
12502 " Display instruction in Intel mnemonic\n"));
12503 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
12504 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
12505 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
12506 fprintf (stream, _(" data32 Assume 32bit data size\n"));
12507 fprintf (stream, _(" data16 Assume 16bit data size\n"));
12508 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12509 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
12510 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
12514 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12516 /* Get a pointer to struct dis386 with a valid name. */
12518 static const struct dis386 *
12519 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12521 int vindex, vex_table_index;
12523 if (dp->name != NULL)
12526 switch (dp->op[0].bytemode)
12528 case USE_REG_TABLE:
12529 dp = ®_table[dp->op[1].bytemode][modrm.reg];
12532 case USE_MOD_TABLE:
12533 vindex = modrm.mod == 0x3 ? 1 : 0;
12534 dp = &mod_table[dp->op[1].bytemode][vindex];
12538 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12541 case USE_PREFIX_TABLE:
12544 /* The prefix in VEX is implicit. */
12545 switch (vex.prefix)
12550 case REPE_PREFIX_OPCODE:
12553 case DATA_PREFIX_OPCODE:
12556 case REPNE_PREFIX_OPCODE:
12566 int last_prefix = -1;
12569 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12570 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12572 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12574 if (last_repz_prefix > last_repnz_prefix)
12577 prefix = PREFIX_REPZ;
12578 last_prefix = last_repz_prefix;
12583 prefix = PREFIX_REPNZ;
12584 last_prefix = last_repnz_prefix;
12587 /* Check if prefix should be ignored. */
12588 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12589 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12594 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12597 prefix = PREFIX_DATA;
12598 last_prefix = last_data_prefix;
12603 used_prefixes |= prefix;
12604 all_prefixes[last_prefix] = 0;
12607 dp = &prefix_table[dp->op[1].bytemode][vindex];
12610 case USE_X86_64_TABLE:
12611 vindex = address_mode == mode_64bit ? 1 : 0;
12612 dp = &x86_64_table[dp->op[1].bytemode][vindex];
12615 case USE_3BYTE_TABLE:
12616 FETCH_DATA (info, codep + 2);
12618 dp = &three_byte_table[dp->op[1].bytemode][vindex];
12620 modrm.mod = (*codep >> 6) & 3;
12621 modrm.reg = (*codep >> 3) & 7;
12622 modrm.rm = *codep & 7;
12625 case USE_VEX_LEN_TABLE:
12629 switch (vex.length)
12642 dp = &vex_len_table[dp->op[1].bytemode][vindex];
12645 case USE_XOP_8F_TABLE:
12646 FETCH_DATA (info, codep + 3);
12647 /* All bits in the REX prefix are ignored. */
12649 rex = ~(*codep >> 5) & 0x7;
12651 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12652 switch ((*codep & 0x1f))
12658 vex_table_index = XOP_08;
12661 vex_table_index = XOP_09;
12664 vex_table_index = XOP_0A;
12668 vex.w = *codep & 0x80;
12669 if (vex.w && address_mode == mode_64bit)
12672 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12673 if (address_mode != mode_64bit)
12675 /* In 16/32-bit mode REX_B is silently ignored. */
12677 if (vex.register_specifier > 0x7)
12684 vex.length = (*codep & 0x4) ? 256 : 128;
12685 switch ((*codep & 0x3))
12691 vex.prefix = DATA_PREFIX_OPCODE;
12694 vex.prefix = REPE_PREFIX_OPCODE;
12697 vex.prefix = REPNE_PREFIX_OPCODE;
12704 dp = &xop_table[vex_table_index][vindex];
12707 FETCH_DATA (info, codep + 1);
12708 modrm.mod = (*codep >> 6) & 3;
12709 modrm.reg = (*codep >> 3) & 7;
12710 modrm.rm = *codep & 7;
12713 case USE_VEX_C4_TABLE:
12715 FETCH_DATA (info, codep + 3);
12716 /* All bits in the REX prefix are ignored. */
12718 rex = ~(*codep >> 5) & 0x7;
12719 switch ((*codep & 0x1f))
12725 vex_table_index = VEX_0F;
12728 vex_table_index = VEX_0F38;
12731 vex_table_index = VEX_0F3A;
12735 vex.w = *codep & 0x80;
12736 if (address_mode == mode_64bit)
12740 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12744 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12745 is ignored, other REX bits are 0 and the highest bit in
12746 VEX.vvvv is also ignored. */
12748 vex.register_specifier = (~(*codep >> 3)) & 0x7;
12750 vex.length = (*codep & 0x4) ? 256 : 128;
12751 switch ((*codep & 0x3))
12757 vex.prefix = DATA_PREFIX_OPCODE;
12760 vex.prefix = REPE_PREFIX_OPCODE;
12763 vex.prefix = REPNE_PREFIX_OPCODE;
12770 dp = &vex_table[vex_table_index][vindex];
12772 /* There is no MODRM byte for VEX [82|77]. */
12773 if (vindex != 0x77 && vindex != 0x82)
12775 FETCH_DATA (info, codep + 1);
12776 modrm.mod = (*codep >> 6) & 3;
12777 modrm.reg = (*codep >> 3) & 7;
12778 modrm.rm = *codep & 7;
12782 case USE_VEX_C5_TABLE:
12784 FETCH_DATA (info, codep + 2);
12785 /* All bits in the REX prefix are ignored. */
12787 rex = (*codep & 0x80) ? 0 : REX_R;
12789 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12791 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12793 vex.length = (*codep & 0x4) ? 256 : 128;
12794 switch ((*codep & 0x3))
12800 vex.prefix = DATA_PREFIX_OPCODE;
12803 vex.prefix = REPE_PREFIX_OPCODE;
12806 vex.prefix = REPNE_PREFIX_OPCODE;
12813 dp = &vex_table[dp->op[1].bytemode][vindex];
12815 /* There is no MODRM byte for VEX [82|77]. */
12816 if (vindex != 0x77 && vindex != 0x82)
12818 FETCH_DATA (info, codep + 1);
12819 modrm.mod = (*codep >> 6) & 3;
12820 modrm.reg = (*codep >> 3) & 7;
12821 modrm.rm = *codep & 7;
12825 case USE_VEX_W_TABLE:
12829 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12832 case USE_EVEX_TABLE:
12833 two_source_ops = 0;
12836 FETCH_DATA (info, codep + 4);
12837 /* All bits in the REX prefix are ignored. */
12839 /* The first byte after 0x62. */
12840 rex = ~(*codep >> 5) & 0x7;
12841 vex.r = *codep & 0x10;
12842 switch ((*codep & 0xf))
12845 return &bad_opcode;
12847 vex_table_index = EVEX_0F;
12850 vex_table_index = EVEX_0F38;
12853 vex_table_index = EVEX_0F3A;
12857 /* The second byte after 0x62. */
12859 vex.w = *codep & 0x80;
12860 if (vex.w && address_mode == mode_64bit)
12863 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12864 if (address_mode != mode_64bit)
12866 /* In 16/32-bit mode silently ignore following bits. */
12870 vex.register_specifier &= 0x7;
12874 if (!(*codep & 0x4))
12875 return &bad_opcode;
12877 switch ((*codep & 0x3))
12883 vex.prefix = DATA_PREFIX_OPCODE;
12886 vex.prefix = REPE_PREFIX_OPCODE;
12889 vex.prefix = REPNE_PREFIX_OPCODE;
12893 /* The third byte after 0x62. */
12896 /* Remember the static rounding bits. */
12897 vex.ll = (*codep >> 5) & 3;
12898 vex.b = (*codep & 0x10) != 0;
12900 vex.v = *codep & 0x8;
12901 vex.mask_register_specifier = *codep & 0x7;
12902 vex.zeroing = *codep & 0x80;
12908 dp = &evex_table[vex_table_index][vindex];
12910 FETCH_DATA (info, codep + 1);
12911 modrm.mod = (*codep >> 6) & 3;
12912 modrm.reg = (*codep >> 3) & 7;
12913 modrm.rm = *codep & 7;
12915 /* Set vector length. */
12916 if (modrm.mod == 3 && vex.b)
12932 return &bad_opcode;
12945 if (dp->name != NULL)
12948 return get_valid_dis386 (dp, info);
12952 get_sib (disassemble_info *info, int sizeflag)
12954 /* If modrm.mod == 3, operand must be register. */
12956 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12960 FETCH_DATA (info, codep + 2);
12961 sib.index = (codep [1] >> 3) & 7;
12962 sib.scale = (codep [1] >> 6) & 3;
12963 sib.base = codep [1] & 7;
12968 print_insn (bfd_vma pc, disassemble_info *info)
12970 const struct dis386 *dp;
12972 char *op_txt[MAX_OPERANDS];
12974 int sizeflag, orig_sizeflag;
12976 struct dis_private priv;
12979 priv.orig_sizeflag = AFLAG | DFLAG;
12980 if ((info->mach & bfd_mach_i386_i386) != 0)
12981 address_mode = mode_32bit;
12982 else if (info->mach == bfd_mach_i386_i8086)
12984 address_mode = mode_16bit;
12985 priv.orig_sizeflag = 0;
12988 address_mode = mode_64bit;
12990 if (intel_syntax == (char) -1)
12991 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12993 for (p = info->disassembler_options; p != NULL; )
12995 if (CONST_STRNEQ (p, "amd64"))
12997 else if (CONST_STRNEQ (p, "intel64"))
12999 else if (CONST_STRNEQ (p, "x86-64"))
13001 address_mode = mode_64bit;
13002 priv.orig_sizeflag = AFLAG | DFLAG;
13004 else if (CONST_STRNEQ (p, "i386"))
13006 address_mode = mode_32bit;
13007 priv.orig_sizeflag = AFLAG | DFLAG;
13009 else if (CONST_STRNEQ (p, "i8086"))
13011 address_mode = mode_16bit;
13012 priv.orig_sizeflag = 0;
13014 else if (CONST_STRNEQ (p, "intel"))
13017 if (CONST_STRNEQ (p + 5, "-mnemonic"))
13018 intel_mnemonic = 1;
13020 else if (CONST_STRNEQ (p, "att"))
13023 if (CONST_STRNEQ (p + 3, "-mnemonic"))
13024 intel_mnemonic = 0;
13026 else if (CONST_STRNEQ (p, "addr"))
13028 if (address_mode == mode_64bit)
13030 if (p[4] == '3' && p[5] == '2')
13031 priv.orig_sizeflag &= ~AFLAG;
13032 else if (p[4] == '6' && p[5] == '4')
13033 priv.orig_sizeflag |= AFLAG;
13037 if (p[4] == '1' && p[5] == '6')
13038 priv.orig_sizeflag &= ~AFLAG;
13039 else if (p[4] == '3' && p[5] == '2')
13040 priv.orig_sizeflag |= AFLAG;
13043 else if (CONST_STRNEQ (p, "data"))
13045 if (p[4] == '1' && p[5] == '6')
13046 priv.orig_sizeflag &= ~DFLAG;
13047 else if (p[4] == '3' && p[5] == '2')
13048 priv.orig_sizeflag |= DFLAG;
13050 else if (CONST_STRNEQ (p, "suffix"))
13051 priv.orig_sizeflag |= SUFFIX_ALWAYS;
13053 p = strchr (p, ',');
13058 if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13060 (*info->fprintf_func) (info->stream,
13061 _("64-bit address is disabled"));
13067 names64 = intel_names64;
13068 names32 = intel_names32;
13069 names16 = intel_names16;
13070 names8 = intel_names8;
13071 names8rex = intel_names8rex;
13072 names_seg = intel_names_seg;
13073 names_mm = intel_names_mm;
13074 names_bnd = intel_names_bnd;
13075 names_xmm = intel_names_xmm;
13076 names_ymm = intel_names_ymm;
13077 names_zmm = intel_names_zmm;
13078 index64 = intel_index64;
13079 index32 = intel_index32;
13080 names_mask = intel_names_mask;
13081 index16 = intel_index16;
13084 separator_char = '+';
13089 names64 = att_names64;
13090 names32 = att_names32;
13091 names16 = att_names16;
13092 names8 = att_names8;
13093 names8rex = att_names8rex;
13094 names_seg = att_names_seg;
13095 names_mm = att_names_mm;
13096 names_bnd = att_names_bnd;
13097 names_xmm = att_names_xmm;
13098 names_ymm = att_names_ymm;
13099 names_zmm = att_names_zmm;
13100 index64 = att_index64;
13101 index32 = att_index32;
13102 names_mask = att_names_mask;
13103 index16 = att_index16;
13106 separator_char = ',';
13110 /* The output looks better if we put 7 bytes on a line, since that
13111 puts most long word instructions on a single line. Use 8 bytes
13113 if ((info->mach & bfd_mach_l1om) != 0)
13114 info->bytes_per_line = 8;
13116 info->bytes_per_line = 7;
13118 info->private_data = &priv;
13119 priv.max_fetched = priv.the_buffer;
13120 priv.insn_start = pc;
13123 for (i = 0; i < MAX_OPERANDS; ++i)
13131 start_codep = priv.the_buffer;
13132 codep = priv.the_buffer;
13134 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13138 /* Getting here means we tried for data but didn't get it. That
13139 means we have an incomplete instruction of some sort. Just
13140 print the first byte as a prefix or a .byte pseudo-op. */
13141 if (codep > priv.the_buffer)
13143 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13145 (*info->fprintf_func) (info->stream, "%s", name);
13148 /* Just print the first byte as a .byte instruction. */
13149 (*info->fprintf_func) (info->stream, ".byte 0x%x",
13150 (unsigned int) priv.the_buffer[0]);
13160 sizeflag = priv.orig_sizeflag;
13162 if (!ckprefix () || rex_used)
13164 /* Too many prefixes or unused REX prefixes. */
13166 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13168 (*info->fprintf_func) (info->stream, "%s%s",
13170 prefix_name (all_prefixes[i], sizeflag));
13174 insn_codep = codep;
13176 FETCH_DATA (info, codep + 1);
13177 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13179 if (((prefixes & PREFIX_FWAIT)
13180 && ((*codep < 0xd8) || (*codep > 0xdf))))
13182 /* Handle prefixes before fwait. */
13183 for (i = 0; i < fwait_prefix && all_prefixes[i];
13185 (*info->fprintf_func) (info->stream, "%s ",
13186 prefix_name (all_prefixes[i], sizeflag));
13187 (*info->fprintf_func) (info->stream, "fwait");
13191 if (*codep == 0x0f)
13193 unsigned char threebyte;
13196 FETCH_DATA (info, codep + 1);
13197 threebyte = *codep;
13198 dp = &dis386_twobyte[threebyte];
13199 need_modrm = twobyte_has_modrm[*codep];
13204 dp = &dis386[*codep];
13205 need_modrm = onebyte_has_modrm[*codep];
13209 /* Save sizeflag for printing the extra prefixes later before updating
13210 it for mnemonic and operand processing. The prefix names depend
13211 only on the address mode. */
13212 orig_sizeflag = sizeflag;
13213 if (prefixes & PREFIX_ADDR)
13215 if ((prefixes & PREFIX_DATA))
13221 FETCH_DATA (info, codep + 1);
13222 modrm.mod = (*codep >> 6) & 3;
13223 modrm.reg = (*codep >> 3) & 7;
13224 modrm.rm = *codep & 7;
13232 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13234 get_sib (info, sizeflag);
13235 dofloat (sizeflag);
13239 dp = get_valid_dis386 (dp, info);
13240 if (dp != NULL && putop (dp->name, sizeflag) == 0)
13242 get_sib (info, sizeflag);
13243 for (i = 0; i < MAX_OPERANDS; ++i)
13246 op_ad = MAX_OPERANDS - 1 - i;
13248 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13249 /* For EVEX instruction after the last operand masking
13250 should be printed. */
13251 if (i == 0 && vex.evex)
13253 /* Don't print {%k0}. */
13254 if (vex.mask_register_specifier)
13257 oappend (names_mask[vex.mask_register_specifier]);
13267 /* Check if the REX prefix is used. */
13268 if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13269 all_prefixes[last_rex_prefix] = 0;
13271 /* Check if the SEG prefix is used. */
13272 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13273 | PREFIX_FS | PREFIX_GS)) != 0
13274 && (used_prefixes & active_seg_prefix) != 0)
13275 all_prefixes[last_seg_prefix] = 0;
13277 /* Check if the ADDR prefix is used. */
13278 if ((prefixes & PREFIX_ADDR) != 0
13279 && (used_prefixes & PREFIX_ADDR) != 0)
13280 all_prefixes[last_addr_prefix] = 0;
13282 /* Check if the DATA prefix is used. */
13283 if ((prefixes & PREFIX_DATA) != 0
13284 && (used_prefixes & PREFIX_DATA) != 0)
13285 all_prefixes[last_data_prefix] = 0;
13287 /* Print the extra prefixes. */
13289 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13290 if (all_prefixes[i])
13293 name = prefix_name (all_prefixes[i], orig_sizeflag);
13296 prefix_length += strlen (name) + 1;
13297 (*info->fprintf_func) (info->stream, "%s ", name);
13300 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13301 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13302 used by putop and MMX/SSE operand and may be overriden by the
13303 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13305 if (dp->prefix_requirement == PREFIX_OPCODE
13306 && dp != &bad_opcode
13308 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13310 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13312 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13314 && (used_prefixes & PREFIX_DATA) == 0))))
13316 (*info->fprintf_func) (info->stream, "(bad)");
13317 return end_codep - priv.the_buffer;
13320 /* Check maximum code length. */
13321 if ((codep - start_codep) > MAX_CODE_LENGTH)
13323 (*info->fprintf_func) (info->stream, "(bad)");
13324 return MAX_CODE_LENGTH;
13327 obufp = mnemonicendp;
13328 for (i = strlen (obuf) + prefix_length; i < 6; i++)
13331 (*info->fprintf_func) (info->stream, "%s", obuf);
13333 /* The enter and bound instructions are printed with operands in the same
13334 order as the intel book; everything else is printed in reverse order. */
13335 if (intel_syntax || two_source_ops)
13339 for (i = 0; i < MAX_OPERANDS; ++i)
13340 op_txt[i] = op_out[i];
13342 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13343 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13345 op_txt[2] = op_out[3];
13346 op_txt[3] = op_out[2];
13349 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13351 op_ad = op_index[i];
13352 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13353 op_index[MAX_OPERANDS - 1 - i] = op_ad;
13354 riprel = op_riprel[i];
13355 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13356 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13361 for (i = 0; i < MAX_OPERANDS; ++i)
13362 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13366 for (i = 0; i < MAX_OPERANDS; ++i)
13370 (*info->fprintf_func) (info->stream, ",");
13371 if (op_index[i] != -1 && !op_riprel[i])
13372 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13374 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13378 for (i = 0; i < MAX_OPERANDS; i++)
13379 if (op_index[i] != -1 && op_riprel[i])
13381 (*info->fprintf_func) (info->stream, " # ");
13382 (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13383 + op_address[op_index[i]]), info);
13386 return codep - priv.the_buffer;
13389 static const char *float_mem[] = {
13464 static const unsigned char float_mem_mode[] = {
13539 #define ST { OP_ST, 0 }
13540 #define STi { OP_STi, 0 }
13542 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13543 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13544 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13545 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13546 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13547 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13548 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13549 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13550 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13552 static const struct dis386 float_reg[][8] = {
13555 { "fadd", { ST, STi }, 0 },
13556 { "fmul", { ST, STi }, 0 },
13557 { "fcom", { STi }, 0 },
13558 { "fcomp", { STi }, 0 },
13559 { "fsub", { ST, STi }, 0 },
13560 { "fsubr", { ST, STi }, 0 },
13561 { "fdiv", { ST, STi }, 0 },
13562 { "fdivr", { ST, STi }, 0 },
13566 { "fld", { STi }, 0 },
13567 { "fxch", { STi }, 0 },
13577 { "fcmovb", { ST, STi }, 0 },
13578 { "fcmove", { ST, STi }, 0 },
13579 { "fcmovbe",{ ST, STi }, 0 },
13580 { "fcmovu", { ST, STi }, 0 },
13588 { "fcmovnb",{ ST, STi }, 0 },
13589 { "fcmovne",{ ST, STi }, 0 },
13590 { "fcmovnbe",{ ST, STi }, 0 },
13591 { "fcmovnu",{ ST, STi }, 0 },
13593 { "fucomi", { ST, STi }, 0 },
13594 { "fcomi", { ST, STi }, 0 },
13599 { "fadd", { STi, ST }, 0 },
13600 { "fmul", { STi, ST }, 0 },
13603 { "fsub!M", { STi, ST }, 0 },
13604 { "fsubM", { STi, ST }, 0 },
13605 { "fdiv!M", { STi, ST }, 0 },
13606 { "fdivM", { STi, ST }, 0 },
13610 { "ffree", { STi }, 0 },
13612 { "fst", { STi }, 0 },
13613 { "fstp", { STi }, 0 },
13614 { "fucom", { STi }, 0 },
13615 { "fucomp", { STi }, 0 },
13621 { "faddp", { STi, ST }, 0 },
13622 { "fmulp", { STi, ST }, 0 },
13625 { "fsub!Mp", { STi, ST }, 0 },
13626 { "fsubMp", { STi, ST }, 0 },
13627 { "fdiv!Mp", { STi, ST }, 0 },
13628 { "fdivMp", { STi, ST }, 0 },
13632 { "ffreep", { STi }, 0 },
13637 { "fucomip", { ST, STi }, 0 },
13638 { "fcomip", { ST, STi }, 0 },
13643 static char *fgrps[][8] = {
13646 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13651 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13656 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13661 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13666 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13671 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13676 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13681 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13682 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13687 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13692 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13697 swap_operand (void)
13699 mnemonicendp[0] = '.';
13700 mnemonicendp[1] = 's';
13705 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13706 int sizeflag ATTRIBUTE_UNUSED)
13708 /* Skip mod/rm byte. */
13714 dofloat (int sizeflag)
13716 const struct dis386 *dp;
13717 unsigned char floatop;
13719 floatop = codep[-1];
13721 if (modrm.mod != 3)
13723 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13725 putop (float_mem[fp_indx], sizeflag);
13728 OP_E (float_mem_mode[fp_indx], sizeflag);
13731 /* Skip mod/rm byte. */
13735 dp = &float_reg[floatop - 0xd8][modrm.reg];
13736 if (dp->name == NULL)
13738 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13740 /* Instruction fnstsw is only one with strange arg. */
13741 if (floatop == 0xdf && codep[-1] == 0xe0)
13742 strcpy (op_out[0], names16[0]);
13746 putop (dp->name, sizeflag);
13751 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13756 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13760 /* Like oappend (below), but S is a string starting with '%'.
13761 In Intel syntax, the '%' is elided. */
13763 oappend_maybe_intel (const char *s)
13765 oappend (s + intel_syntax);
13769 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13771 oappend_maybe_intel ("%st");
13775 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13777 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13778 oappend_maybe_intel (scratchbuf);
13781 /* Capital letters in template are macros. */
13783 putop (const char *in_template, int sizeflag)
13788 unsigned int l = 0, len = 1;
13791 #define SAVE_LAST(c) \
13792 if (l < len && l < sizeof (last)) \
13797 for (p = in_template; *p; p++)
13813 while (*++p != '|')
13814 if (*p == '}' || *p == '\0')
13817 /* Fall through. */
13822 while (*++p != '}')
13833 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13837 if (l == 0 && len == 1)
13842 if (sizeflag & SUFFIX_ALWAYS)
13855 if (address_mode == mode_64bit
13856 && !(prefixes & PREFIX_ADDR))
13867 if (intel_syntax && !alt)
13869 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13871 if (sizeflag & DFLAG)
13872 *obufp++ = intel_syntax ? 'd' : 'l';
13874 *obufp++ = intel_syntax ? 'w' : 's';
13875 used_prefixes |= (prefixes & PREFIX_DATA);
13879 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13882 if (modrm.mod == 3)
13888 if (sizeflag & DFLAG)
13889 *obufp++ = intel_syntax ? 'd' : 'l';
13892 used_prefixes |= (prefixes & PREFIX_DATA);
13898 case 'E': /* For jcxz/jecxz */
13899 if (address_mode == mode_64bit)
13901 if (sizeflag & AFLAG)
13907 if (sizeflag & AFLAG)
13909 used_prefixes |= (prefixes & PREFIX_ADDR);
13914 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13916 if (sizeflag & AFLAG)
13917 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13919 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13920 used_prefixes |= (prefixes & PREFIX_ADDR);
13924 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13926 if ((rex & REX_W) || (sizeflag & DFLAG))
13930 if (!(rex & REX_W))
13931 used_prefixes |= (prefixes & PREFIX_DATA);
13936 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13937 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13939 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13942 if (prefixes & PREFIX_DS)
13961 if (l != 0 || len != 1)
13963 if (l != 1 || len != 2 || last[0] != 'X')
13968 if (!need_vex || !vex.evex)
13971 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13973 switch (vex.length)
13991 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13996 /* Fall through. */
13999 if (l != 0 || len != 1)
14007 if (sizeflag & SUFFIX_ALWAYS)
14011 if (intel_mnemonic != cond)
14015 if ((prefixes & PREFIX_FWAIT) == 0)
14018 used_prefixes |= PREFIX_FWAIT;
14024 else if (intel_syntax && (sizeflag & DFLAG))
14028 if (!(rex & REX_W))
14029 used_prefixes |= (prefixes & PREFIX_DATA);
14033 && address_mode == mode_64bit
14034 && isa64 == intel64)
14039 /* Fall through. */
14042 && address_mode == mode_64bit
14043 && ((sizeflag & DFLAG) || (rex & REX_W)))
14048 /* Fall through. */
14051 if (l == 0 && len == 1)
14056 if ((rex & REX_W) == 0
14057 && (prefixes & PREFIX_DATA))
14059 if ((sizeflag & DFLAG) == 0)
14061 used_prefixes |= (prefixes & PREFIX_DATA);
14065 if ((prefixes & PREFIX_DATA)
14067 || (sizeflag & SUFFIX_ALWAYS))
14074 if (sizeflag & DFLAG)
14078 used_prefixes |= (prefixes & PREFIX_DATA);
14084 if (l != 1 || len != 2 || last[0] != 'L')
14090 if ((prefixes & PREFIX_DATA)
14092 || (sizeflag & SUFFIX_ALWAYS))
14099 if (sizeflag & DFLAG)
14100 *obufp++ = intel_syntax ? 'd' : 'l';
14103 used_prefixes |= (prefixes & PREFIX_DATA);
14111 if (address_mode == mode_64bit
14112 && ((sizeflag & DFLAG) || (rex & REX_W)))
14114 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14118 /* Fall through. */
14121 if (l == 0 && len == 1)
14124 if (intel_syntax && !alt)
14127 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14133 if (sizeflag & DFLAG)
14134 *obufp++ = intel_syntax ? 'd' : 'l';
14137 used_prefixes |= (prefixes & PREFIX_DATA);
14143 if (l != 1 || len != 2 || last[0] != 'L')
14149 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14164 else if (sizeflag & DFLAG)
14173 if (intel_syntax && !p[1]
14174 && ((rex & REX_W) || (sizeflag & DFLAG)))
14176 if (!(rex & REX_W))
14177 used_prefixes |= (prefixes & PREFIX_DATA);
14180 if (l == 0 && len == 1)
14184 if (address_mode == mode_64bit
14185 && ((sizeflag & DFLAG) || (rex & REX_W)))
14187 if (sizeflag & SUFFIX_ALWAYS)
14209 /* Fall through. */
14212 if (l == 0 && len == 1)
14217 if (sizeflag & SUFFIX_ALWAYS)
14223 if (sizeflag & DFLAG)
14227 used_prefixes |= (prefixes & PREFIX_DATA);
14241 if (address_mode == mode_64bit
14242 && !(prefixes & PREFIX_ADDR))
14253 if (l != 0 || len != 1)
14258 if (need_vex && vex.prefix)
14260 if (vex.prefix == DATA_PREFIX_OPCODE)
14267 if (prefixes & PREFIX_DATA)
14271 used_prefixes |= (prefixes & PREFIX_DATA);
14275 if (l == 0 && len == 1)
14277 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14288 if (l != 1 || len != 2 || last[0] != 'X')
14296 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14298 switch (vex.length)
14314 if (l == 0 && len == 1)
14316 /* operand size flag for cwtl, cbtw */
14325 else if (sizeflag & DFLAG)
14329 if (!(rex & REX_W))
14330 used_prefixes |= (prefixes & PREFIX_DATA);
14337 && last[0] != 'L'))
14344 if (last[0] == 'X')
14345 *obufp++ = vex.w ? 'd': 's';
14347 *obufp++ = vex.w ? 'q': 'd';
14353 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14355 if (sizeflag & DFLAG)
14359 used_prefixes |= (prefixes & PREFIX_DATA);
14365 if (address_mode == mode_64bit
14366 && (isa64 == intel64
14367 || ((sizeflag & DFLAG) || (rex & REX_W))))
14369 else if ((prefixes & PREFIX_DATA))
14371 if (!(sizeflag & DFLAG))
14373 used_prefixes |= (prefixes & PREFIX_DATA);
14380 mnemonicendp = obufp;
14385 oappend (const char *s)
14387 obufp = stpcpy (obufp, s);
14393 /* Only print the active segment register. */
14394 if (!active_seg_prefix)
14397 used_prefixes |= active_seg_prefix;
14398 switch (active_seg_prefix)
14401 oappend_maybe_intel ("%cs:");
14404 oappend_maybe_intel ("%ds:");
14407 oappend_maybe_intel ("%ss:");
14410 oappend_maybe_intel ("%es:");
14413 oappend_maybe_intel ("%fs:");
14416 oappend_maybe_intel ("%gs:");
14424 OP_indirE (int bytemode, int sizeflag)
14428 OP_E (bytemode, sizeflag);
14432 print_operand_value (char *buf, int hex, bfd_vma disp)
14434 if (address_mode == mode_64bit)
14442 sprintf_vma (tmp, disp);
14443 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14444 strcpy (buf + 2, tmp + i);
14448 bfd_signed_vma v = disp;
14455 /* Check for possible overflow on 0x8000000000000000. */
14458 strcpy (buf, "9223372036854775808");
14472 tmp[28 - i] = (v % 10) + '0';
14476 strcpy (buf, tmp + 29 - i);
14482 sprintf (buf, "0x%x", (unsigned int) disp);
14484 sprintf (buf, "%d", (int) disp);
14488 /* Put DISP in BUF as signed hex number. */
14491 print_displacement (char *buf, bfd_vma disp)
14493 bfd_signed_vma val = disp;
14502 /* Check for possible overflow. */
14505 switch (address_mode)
14508 strcpy (buf + j, "0x8000000000000000");
14511 strcpy (buf + j, "0x80000000");
14514 strcpy (buf + j, "0x8000");
14524 sprintf_vma (tmp, (bfd_vma) val);
14525 for (i = 0; tmp[i] == '0'; i++)
14527 if (tmp[i] == '\0')
14529 strcpy (buf + j, tmp + i);
14533 intel_operand_size (int bytemode, int sizeflag)
14537 && (bytemode == x_mode
14538 || bytemode == evex_half_bcst_xmmq_mode))
14541 oappend ("QWORD PTR ");
14543 oappend ("DWORD PTR ");
14552 oappend ("BYTE PTR ");
14557 oappend ("WORD PTR ");
14560 if (address_mode == mode_64bit && isa64 == intel64)
14562 oappend ("QWORD PTR ");
14565 /* Fall through. */
14567 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14569 oappend ("QWORD PTR ");
14572 /* Fall through. */
14578 oappend ("QWORD PTR ");
14581 if ((sizeflag & DFLAG) || bytemode == dq_mode)
14582 oappend ("DWORD PTR ");
14584 oappend ("WORD PTR ");
14585 used_prefixes |= (prefixes & PREFIX_DATA);
14589 if ((rex & REX_W) || (sizeflag & DFLAG))
14591 oappend ("WORD PTR ");
14592 if (!(rex & REX_W))
14593 used_prefixes |= (prefixes & PREFIX_DATA);
14596 if (sizeflag & DFLAG)
14597 oappend ("QWORD PTR ");
14599 oappend ("DWORD PTR ");
14600 used_prefixes |= (prefixes & PREFIX_DATA);
14603 case d_scalar_mode:
14604 case d_scalar_swap_mode:
14607 oappend ("DWORD PTR ");
14610 case q_scalar_mode:
14611 case q_scalar_swap_mode:
14613 oappend ("QWORD PTR ");
14616 if (address_mode == mode_64bit)
14617 oappend ("QWORD PTR ");
14619 oappend ("DWORD PTR ");
14622 if (sizeflag & DFLAG)
14623 oappend ("FWORD PTR ");
14625 oappend ("DWORD PTR ");
14626 used_prefixes |= (prefixes & PREFIX_DATA);
14629 oappend ("TBYTE PTR ");
14633 case evex_x_gscat_mode:
14634 case evex_x_nobcst_mode:
14637 switch (vex.length)
14640 oappend ("XMMWORD PTR ");
14643 oappend ("YMMWORD PTR ");
14646 oappend ("ZMMWORD PTR ");
14653 oappend ("XMMWORD PTR ");
14656 oappend ("XMMWORD PTR ");
14659 oappend ("YMMWORD PTR ");
14662 case evex_half_bcst_xmmq_mode:
14666 switch (vex.length)
14669 oappend ("QWORD PTR ");
14672 oappend ("XMMWORD PTR ");
14675 oappend ("YMMWORD PTR ");
14685 switch (vex.length)
14690 oappend ("BYTE PTR ");
14700 switch (vex.length)
14705 oappend ("WORD PTR ");
14715 switch (vex.length)
14720 oappend ("DWORD PTR ");
14730 switch (vex.length)
14735 oappend ("QWORD PTR ");
14745 switch (vex.length)
14748 oappend ("WORD PTR ");
14751 oappend ("DWORD PTR ");
14754 oappend ("QWORD PTR ");
14764 switch (vex.length)
14767 oappend ("DWORD PTR ");
14770 oappend ("QWORD PTR ");
14773 oappend ("XMMWORD PTR ");
14783 switch (vex.length)
14786 oappend ("QWORD PTR ");
14789 oappend ("YMMWORD PTR ");
14792 oappend ("ZMMWORD PTR ");
14802 switch (vex.length)
14806 oappend ("XMMWORD PTR ");
14813 oappend ("OWORD PTR ");
14816 case vex_w_dq_mode:
14817 case vex_scalar_w_dq_mode:
14822 oappend ("QWORD PTR ");
14824 oappend ("DWORD PTR ");
14826 case vex_vsib_d_w_dq_mode:
14827 case vex_vsib_q_w_dq_mode:
14834 oappend ("QWORD PTR ");
14836 oappend ("DWORD PTR ");
14840 switch (vex.length)
14843 oappend ("XMMWORD PTR ");
14846 oappend ("YMMWORD PTR ");
14849 oappend ("ZMMWORD PTR ");
14856 case vex_vsib_q_w_d_mode:
14857 case vex_vsib_d_w_d_mode:
14858 if (!need_vex || !vex.evex)
14861 switch (vex.length)
14864 oappend ("QWORD PTR ");
14867 oappend ("XMMWORD PTR ");
14870 oappend ("YMMWORD PTR ");
14878 if (!need_vex || vex.length != 128)
14881 oappend ("DWORD PTR ");
14883 oappend ("BYTE PTR ");
14889 oappend ("QWORD PTR ");
14891 oappend ("WORD PTR ");
14900 OP_E_register (int bytemode, int sizeflag)
14902 int reg = modrm.rm;
14903 const char **names;
14909 if ((sizeflag & SUFFIX_ALWAYS)
14910 && (bytemode == b_swap_mode
14911 || bytemode == v_swap_mode))
14937 names = address_mode == mode_64bit ? names64 : names32;
14943 if (address_mode == mode_64bit && isa64 == intel64)
14948 /* Fall through. */
14950 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14956 /* Fall through. */
14968 if ((sizeflag & DFLAG)
14969 || (bytemode != v_mode
14970 && bytemode != v_swap_mode))
14974 used_prefixes |= (prefixes & PREFIX_DATA);
14984 names = names_mask;
14989 oappend (INTERNAL_DISASSEMBLER_ERROR);
14992 oappend (names[reg]);
14996 OP_E_memory (int bytemode, int sizeflag)
14999 int add = (rex & REX_B) ? 8 : 0;
15005 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
15007 && bytemode != x_mode
15008 && bytemode != xmmq_mode
15009 && bytemode != evex_half_bcst_xmmq_mode)
15024 case vex_vsib_d_w_dq_mode:
15025 case vex_vsib_d_w_d_mode:
15026 case vex_vsib_q_w_dq_mode:
15027 case vex_vsib_q_w_d_mode:
15028 case evex_x_gscat_mode:
15030 shift = vex.w ? 3 : 2;
15033 case evex_half_bcst_xmmq_mode:
15037 shift = vex.w ? 3 : 2;
15040 /* Fall through. */
15044 case evex_x_nobcst_mode:
15046 switch (vex.length)
15069 case q_scalar_mode:
15071 case q_scalar_swap_mode:
15077 case d_scalar_mode:
15079 case d_scalar_swap_mode:
15091 /* Make necessary corrections to shift for modes that need it.
15092 For these modes we currently have shift 4, 5 or 6 depending on
15093 vex.length (it corresponds to xmmword, ymmword or zmmword
15094 operand). We might want to make it 3, 4 or 5 (e.g. for
15095 xmmq_mode). In case of broadcast enabled the corrections
15096 aren't needed, as element size is always 32 or 64 bits. */
15098 && (bytemode == xmmq_mode
15099 || bytemode == evex_half_bcst_xmmq_mode))
15101 else if (bytemode == xmmqd_mode)
15103 else if (bytemode == xmmdw_mode)
15105 else if (bytemode == ymmq_mode && vex.length == 128)
15113 intel_operand_size (bytemode, sizeflag);
15116 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15118 /* 32/64 bit address mode */
15127 int addr32flag = !((sizeflag & AFLAG)
15128 || bytemode == v_bnd_mode
15129 || bytemode == bnd_mode);
15130 const char **indexes64 = names64;
15131 const char **indexes32 = names32;
15141 vindex = sib.index;
15147 case vex_vsib_d_w_dq_mode:
15148 case vex_vsib_d_w_d_mode:
15149 case vex_vsib_q_w_dq_mode:
15150 case vex_vsib_q_w_d_mode:
15160 switch (vex.length)
15163 indexes64 = indexes32 = names_xmm;
15167 || bytemode == vex_vsib_q_w_dq_mode
15168 || bytemode == vex_vsib_q_w_d_mode)
15169 indexes64 = indexes32 = names_ymm;
15171 indexes64 = indexes32 = names_xmm;
15175 || bytemode == vex_vsib_q_w_dq_mode
15176 || bytemode == vex_vsib_q_w_d_mode)
15177 indexes64 = indexes32 = names_zmm;
15179 indexes64 = indexes32 = names_ymm;
15186 haveindex = vindex != 4;
15193 rbase = base + add;
15201 if (address_mode == mode_64bit && !havesib)
15207 FETCH_DATA (the_info, codep + 1);
15209 if ((disp & 0x80) != 0)
15211 if (vex.evex && shift > 0)
15219 /* In 32bit mode, we need index register to tell [offset] from
15220 [eiz*1 + offset]. */
15221 needindex = (havesib
15224 && address_mode == mode_32bit);
15225 havedisp = (havebase
15227 || (havesib && (haveindex || scale != 0)));
15230 if (modrm.mod != 0 || base == 5)
15232 if (havedisp || riprel)
15233 print_displacement (scratchbuf, disp);
15235 print_operand_value (scratchbuf, 1, disp);
15236 oappend (scratchbuf);
15240 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15244 if ((havebase || haveindex || riprel)
15245 && (bytemode != v_bnd_mode)
15246 && (bytemode != bnd_mode))
15247 used_prefixes |= PREFIX_ADDR;
15249 if (havedisp || (intel_syntax && riprel))
15251 *obufp++ = open_char;
15252 if (intel_syntax && riprel)
15255 oappend (!addr32flag ? "rip" : "eip");
15259 oappend (address_mode == mode_64bit && !addr32flag
15260 ? names64[rbase] : names32[rbase]);
15263 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15264 print index to tell base + index from base. */
15268 || (havebase && base != ESP_REG_NUM))
15270 if (!intel_syntax || havebase)
15272 *obufp++ = separator_char;
15276 oappend (address_mode == mode_64bit && !addr32flag
15277 ? indexes64[vindex] : indexes32[vindex]);
15279 oappend (address_mode == mode_64bit && !addr32flag
15280 ? index64 : index32);
15282 *obufp++ = scale_char;
15284 sprintf (scratchbuf, "%d", 1 << scale);
15285 oappend (scratchbuf);
15289 && (disp || modrm.mod != 0 || base == 5))
15291 if (!havedisp || (bfd_signed_vma) disp >= 0)
15296 else if (modrm.mod != 1 && disp != -disp)
15300 disp = - (bfd_signed_vma) disp;
15304 print_displacement (scratchbuf, disp);
15306 print_operand_value (scratchbuf, 1, disp);
15307 oappend (scratchbuf);
15310 *obufp++ = close_char;
15313 else if (intel_syntax)
15315 if (modrm.mod != 0 || base == 5)
15317 if (!active_seg_prefix)
15319 oappend (names_seg[ds_reg - es_reg]);
15322 print_operand_value (scratchbuf, 1, disp);
15323 oappend (scratchbuf);
15329 /* 16 bit address mode */
15330 used_prefixes |= prefixes & PREFIX_ADDR;
15337 if ((disp & 0x8000) != 0)
15342 FETCH_DATA (the_info, codep + 1);
15344 if ((disp & 0x80) != 0)
15349 if ((disp & 0x8000) != 0)
15355 if (modrm.mod != 0 || modrm.rm == 6)
15357 print_displacement (scratchbuf, disp);
15358 oappend (scratchbuf);
15361 if (modrm.mod != 0 || modrm.rm != 6)
15363 *obufp++ = open_char;
15365 oappend (index16[modrm.rm]);
15367 && (disp || modrm.mod != 0 || modrm.rm == 6))
15369 if ((bfd_signed_vma) disp >= 0)
15374 else if (modrm.mod != 1)
15378 disp = - (bfd_signed_vma) disp;
15381 print_displacement (scratchbuf, disp);
15382 oappend (scratchbuf);
15385 *obufp++ = close_char;
15388 else if (intel_syntax)
15390 if (!active_seg_prefix)
15392 oappend (names_seg[ds_reg - es_reg]);
15395 print_operand_value (scratchbuf, 1, disp & 0xffff);
15396 oappend (scratchbuf);
15399 if (vex.evex && vex.b
15400 && (bytemode == x_mode
15401 || bytemode == xmmq_mode
15402 || bytemode == evex_half_bcst_xmmq_mode))
15405 || bytemode == xmmq_mode
15406 || bytemode == evex_half_bcst_xmmq_mode)
15408 switch (vex.length)
15411 oappend ("{1to2}");
15414 oappend ("{1to4}");
15417 oappend ("{1to8}");
15425 switch (vex.length)
15428 oappend ("{1to4}");
15431 oappend ("{1to8}");
15434 oappend ("{1to16}");
15444 OP_E (int bytemode, int sizeflag)
15446 /* Skip mod/rm byte. */
15450 if (modrm.mod == 3)
15451 OP_E_register (bytemode, sizeflag);
15453 OP_E_memory (bytemode, sizeflag);
15457 OP_G (int bytemode, int sizeflag)
15468 oappend (names8rex[modrm.reg + add]);
15470 oappend (names8[modrm.reg + add]);
15473 oappend (names16[modrm.reg + add]);
15478 oappend (names32[modrm.reg + add]);
15481 oappend (names64[modrm.reg + add]);
15484 oappend (names_bnd[modrm.reg]);
15493 oappend (names64[modrm.reg + add]);
15496 if ((sizeflag & DFLAG) || bytemode != v_mode)
15497 oappend (names32[modrm.reg + add]);
15499 oappend (names16[modrm.reg + add]);
15500 used_prefixes |= (prefixes & PREFIX_DATA);
15504 if (address_mode == mode_64bit)
15505 oappend (names64[modrm.reg + add]);
15507 oappend (names32[modrm.reg + add]);
15511 if ((modrm.reg + add) > 0x7)
15516 oappend (names_mask[modrm.reg + add]);
15519 oappend (INTERNAL_DISASSEMBLER_ERROR);
15532 FETCH_DATA (the_info, codep + 8);
15533 a = *codep++ & 0xff;
15534 a |= (*codep++ & 0xff) << 8;
15535 a |= (*codep++ & 0xff) << 16;
15536 a |= (*codep++ & 0xffu) << 24;
15537 b = *codep++ & 0xff;
15538 b |= (*codep++ & 0xff) << 8;
15539 b |= (*codep++ & 0xff) << 16;
15540 b |= (*codep++ & 0xffu) << 24;
15541 x = a + ((bfd_vma) b << 32);
15549 static bfd_signed_vma
15552 bfd_signed_vma x = 0;
15554 FETCH_DATA (the_info, codep + 4);
15555 x = *codep++ & (bfd_signed_vma) 0xff;
15556 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15557 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15558 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15562 static bfd_signed_vma
15565 bfd_signed_vma x = 0;
15567 FETCH_DATA (the_info, codep + 4);
15568 x = *codep++ & (bfd_signed_vma) 0xff;
15569 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15570 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15571 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15573 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15583 FETCH_DATA (the_info, codep + 2);
15584 x = *codep++ & 0xff;
15585 x |= (*codep++ & 0xff) << 8;
15590 set_op (bfd_vma op, int riprel)
15592 op_index[op_ad] = op_ad;
15593 if (address_mode == mode_64bit)
15595 op_address[op_ad] = op;
15596 op_riprel[op_ad] = riprel;
15600 /* Mask to get a 32-bit address. */
15601 op_address[op_ad] = op & 0xffffffff;
15602 op_riprel[op_ad] = riprel & 0xffffffff;
15607 OP_REG (int code, int sizeflag)
15614 case es_reg: case ss_reg: case cs_reg:
15615 case ds_reg: case fs_reg: case gs_reg:
15616 oappend (names_seg[code - es_reg]);
15628 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15629 case sp_reg: case bp_reg: case si_reg: case di_reg:
15630 s = names16[code - ax_reg + add];
15632 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15633 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15636 s = names8rex[code - al_reg + add];
15638 s = names8[code - al_reg];
15640 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15641 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15642 if (address_mode == mode_64bit
15643 && ((sizeflag & DFLAG) || (rex & REX_W)))
15645 s = names64[code - rAX_reg + add];
15648 code += eAX_reg - rAX_reg;
15649 /* Fall through. */
15650 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15651 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15654 s = names64[code - eAX_reg + add];
15657 if (sizeflag & DFLAG)
15658 s = names32[code - eAX_reg + add];
15660 s = names16[code - eAX_reg + add];
15661 used_prefixes |= (prefixes & PREFIX_DATA);
15665 s = INTERNAL_DISASSEMBLER_ERROR;
15672 OP_IMREG (int code, int sizeflag)
15684 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15685 case sp_reg: case bp_reg: case si_reg: case di_reg:
15686 s = names16[code - ax_reg];
15688 case es_reg: case ss_reg: case cs_reg:
15689 case ds_reg: case fs_reg: case gs_reg:
15690 s = names_seg[code - es_reg];
15692 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15693 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15696 s = names8rex[code - al_reg];
15698 s = names8[code - al_reg];
15700 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15701 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15704 s = names64[code - eAX_reg];
15707 if (sizeflag & DFLAG)
15708 s = names32[code - eAX_reg];
15710 s = names16[code - eAX_reg];
15711 used_prefixes |= (prefixes & PREFIX_DATA);
15714 case z_mode_ax_reg:
15715 if ((rex & REX_W) || (sizeflag & DFLAG))
15719 if (!(rex & REX_W))
15720 used_prefixes |= (prefixes & PREFIX_DATA);
15723 s = INTERNAL_DISASSEMBLER_ERROR;
15730 OP_I (int bytemode, int sizeflag)
15733 bfd_signed_vma mask = -1;
15738 FETCH_DATA (the_info, codep + 1);
15743 if (address_mode == mode_64bit)
15748 /* Fall through. */
15755 if (sizeflag & DFLAG)
15765 used_prefixes |= (prefixes & PREFIX_DATA);
15777 oappend (INTERNAL_DISASSEMBLER_ERROR);
15782 scratchbuf[0] = '$';
15783 print_operand_value (scratchbuf + 1, 1, op);
15784 oappend_maybe_intel (scratchbuf);
15785 scratchbuf[0] = '\0';
15789 OP_I64 (int bytemode, int sizeflag)
15792 bfd_signed_vma mask = -1;
15794 if (address_mode != mode_64bit)
15796 OP_I (bytemode, sizeflag);
15803 FETCH_DATA (the_info, codep + 1);
15813 if (sizeflag & DFLAG)
15823 used_prefixes |= (prefixes & PREFIX_DATA);
15831 oappend (INTERNAL_DISASSEMBLER_ERROR);
15836 scratchbuf[0] = '$';
15837 print_operand_value (scratchbuf + 1, 1, op);
15838 oappend_maybe_intel (scratchbuf);
15839 scratchbuf[0] = '\0';
15843 OP_sI (int bytemode, int sizeflag)
15851 FETCH_DATA (the_info, codep + 1);
15853 if ((op & 0x80) != 0)
15855 if (bytemode == b_T_mode)
15857 if (address_mode != mode_64bit
15858 || !((sizeflag & DFLAG) || (rex & REX_W)))
15860 /* The operand-size prefix is overridden by a REX prefix. */
15861 if ((sizeflag & DFLAG) || (rex & REX_W))
15869 if (!(rex & REX_W))
15871 if (sizeflag & DFLAG)
15879 /* The operand-size prefix is overridden by a REX prefix. */
15880 if ((sizeflag & DFLAG) || (rex & REX_W))
15886 oappend (INTERNAL_DISASSEMBLER_ERROR);
15890 scratchbuf[0] = '$';
15891 print_operand_value (scratchbuf + 1, 1, op);
15892 oappend_maybe_intel (scratchbuf);
15896 OP_J (int bytemode, int sizeflag)
15900 bfd_vma segment = 0;
15905 FETCH_DATA (the_info, codep + 1);
15907 if ((disp & 0x80) != 0)
15911 if (isa64 == amd64)
15913 if ((sizeflag & DFLAG)
15914 || (address_mode == mode_64bit
15915 && (isa64 != amd64 || (rex & REX_W))))
15920 if ((disp & 0x8000) != 0)
15922 /* In 16bit mode, address is wrapped around at 64k within
15923 the same segment. Otherwise, a data16 prefix on a jump
15924 instruction means that the pc is masked to 16 bits after
15925 the displacement is added! */
15927 if ((prefixes & PREFIX_DATA) == 0)
15928 segment = ((start_pc + (codep - start_codep))
15929 & ~((bfd_vma) 0xffff));
15931 if (address_mode != mode_64bit
15932 || (isa64 == amd64 && !(rex & REX_W)))
15933 used_prefixes |= (prefixes & PREFIX_DATA);
15936 oappend (INTERNAL_DISASSEMBLER_ERROR);
15939 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15941 print_operand_value (scratchbuf, 1, disp);
15942 oappend (scratchbuf);
15946 OP_SEG (int bytemode, int sizeflag)
15948 if (bytemode == w_mode)
15949 oappend (names_seg[modrm.reg]);
15951 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15955 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15959 if (sizeflag & DFLAG)
15969 used_prefixes |= (prefixes & PREFIX_DATA);
15971 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15973 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15974 oappend (scratchbuf);
15978 OP_OFF (int bytemode, int sizeflag)
15982 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15983 intel_operand_size (bytemode, sizeflag);
15986 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15993 if (!active_seg_prefix)
15995 oappend (names_seg[ds_reg - es_reg]);
15999 print_operand_value (scratchbuf, 1, off);
16000 oappend (scratchbuf);
16004 OP_OFF64 (int bytemode, int sizeflag)
16008 if (address_mode != mode_64bit
16009 || (prefixes & PREFIX_ADDR))
16011 OP_OFF (bytemode, sizeflag);
16015 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16016 intel_operand_size (bytemode, sizeflag);
16023 if (!active_seg_prefix)
16025 oappend (names_seg[ds_reg - es_reg]);
16029 print_operand_value (scratchbuf, 1, off);
16030 oappend (scratchbuf);
16034 ptr_reg (int code, int sizeflag)
16038 *obufp++ = open_char;
16039 used_prefixes |= (prefixes & PREFIX_ADDR);
16040 if (address_mode == mode_64bit)
16042 if (!(sizeflag & AFLAG))
16043 s = names32[code - eAX_reg];
16045 s = names64[code - eAX_reg];
16047 else if (sizeflag & AFLAG)
16048 s = names32[code - eAX_reg];
16050 s = names16[code - eAX_reg];
16052 *obufp++ = close_char;
16057 OP_ESreg (int code, int sizeflag)
16063 case 0x6d: /* insw/insl */
16064 intel_operand_size (z_mode, sizeflag);
16066 case 0xa5: /* movsw/movsl/movsq */
16067 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16068 case 0xab: /* stosw/stosl */
16069 case 0xaf: /* scasw/scasl */
16070 intel_operand_size (v_mode, sizeflag);
16073 intel_operand_size (b_mode, sizeflag);
16076 oappend_maybe_intel ("%es:");
16077 ptr_reg (code, sizeflag);
16081 OP_DSreg (int code, int sizeflag)
16087 case 0x6f: /* outsw/outsl */
16088 intel_operand_size (z_mode, sizeflag);
16090 case 0xa5: /* movsw/movsl/movsq */
16091 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16092 case 0xad: /* lodsw/lodsl/lodsq */
16093 intel_operand_size (v_mode, sizeflag);
16096 intel_operand_size (b_mode, sizeflag);
16099 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16100 default segment register DS is printed. */
16101 if (!active_seg_prefix)
16102 active_seg_prefix = PREFIX_DS;
16104 ptr_reg (code, sizeflag);
16108 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16116 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16118 all_prefixes[last_lock_prefix] = 0;
16119 used_prefixes |= PREFIX_LOCK;
16124 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16125 oappend_maybe_intel (scratchbuf);
16129 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16138 sprintf (scratchbuf, "db%d", modrm.reg + add);
16140 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16141 oappend (scratchbuf);
16145 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16147 sprintf (scratchbuf, "%%tr%d", modrm.reg);
16148 oappend_maybe_intel (scratchbuf);
16152 OP_R (int bytemode, int sizeflag)
16154 /* Skip mod/rm byte. */
16157 OP_E_register (bytemode, sizeflag);
16161 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16163 int reg = modrm.reg;
16164 const char **names;
16166 used_prefixes |= (prefixes & PREFIX_DATA);
16167 if (prefixes & PREFIX_DATA)
16176 oappend (names[reg]);
16180 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16182 int reg = modrm.reg;
16183 const char **names;
16195 && bytemode != xmm_mode
16196 && bytemode != xmmq_mode
16197 && bytemode != evex_half_bcst_xmmq_mode
16198 && bytemode != ymm_mode
16199 && bytemode != scalar_mode)
16201 switch (vex.length)
16208 || (bytemode != vex_vsib_q_w_dq_mode
16209 && bytemode != vex_vsib_q_w_d_mode))
16221 else if (bytemode == xmmq_mode
16222 || bytemode == evex_half_bcst_xmmq_mode)
16224 switch (vex.length)
16237 else if (bytemode == ymm_mode)
16241 oappend (names[reg]);
16245 OP_EM (int bytemode, int sizeflag)
16248 const char **names;
16250 if (modrm.mod != 3)
16253 && (bytemode == v_mode || bytemode == v_swap_mode))
16255 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16256 used_prefixes |= (prefixes & PREFIX_DATA);
16258 OP_E (bytemode, sizeflag);
16262 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16265 /* Skip mod/rm byte. */
16268 used_prefixes |= (prefixes & PREFIX_DATA);
16270 if (prefixes & PREFIX_DATA)
16279 oappend (names[reg]);
16282 /* cvt* are the only instructions in sse2 which have
16283 both SSE and MMX operands and also have 0x66 prefix
16284 in their opcode. 0x66 was originally used to differentiate
16285 between SSE and MMX instruction(operands). So we have to handle the
16286 cvt* separately using OP_EMC and OP_MXC */
16288 OP_EMC (int bytemode, int sizeflag)
16290 if (modrm.mod != 3)
16292 if (intel_syntax && bytemode == v_mode)
16294 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16295 used_prefixes |= (prefixes & PREFIX_DATA);
16297 OP_E (bytemode, sizeflag);
16301 /* Skip mod/rm byte. */
16304 used_prefixes |= (prefixes & PREFIX_DATA);
16305 oappend (names_mm[modrm.rm]);
16309 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16311 used_prefixes |= (prefixes & PREFIX_DATA);
16312 oappend (names_mm[modrm.reg]);
16316 OP_EX (int bytemode, int sizeflag)
16319 const char **names;
16321 /* Skip mod/rm byte. */
16325 if (modrm.mod != 3)
16327 OP_E_memory (bytemode, sizeflag);
16342 if ((sizeflag & SUFFIX_ALWAYS)
16343 && (bytemode == x_swap_mode
16344 || bytemode == d_swap_mode
16345 || bytemode == d_scalar_swap_mode
16346 || bytemode == q_swap_mode
16347 || bytemode == q_scalar_swap_mode))
16351 && bytemode != xmm_mode
16352 && bytemode != xmmdw_mode
16353 && bytemode != xmmqd_mode
16354 && bytemode != xmm_mb_mode
16355 && bytemode != xmm_mw_mode
16356 && bytemode != xmm_md_mode
16357 && bytemode != xmm_mq_mode
16358 && bytemode != xmm_mdq_mode
16359 && bytemode != xmmq_mode
16360 && bytemode != evex_half_bcst_xmmq_mode
16361 && bytemode != ymm_mode
16362 && bytemode != d_scalar_mode
16363 && bytemode != d_scalar_swap_mode
16364 && bytemode != q_scalar_mode
16365 && bytemode != q_scalar_swap_mode
16366 && bytemode != vex_scalar_w_dq_mode)
16368 switch (vex.length)
16383 else if (bytemode == xmmq_mode
16384 || bytemode == evex_half_bcst_xmmq_mode)
16386 switch (vex.length)
16399 else if (bytemode == ymm_mode)
16403 oappend (names[reg]);
16407 OP_MS (int bytemode, int sizeflag)
16409 if (modrm.mod == 3)
16410 OP_EM (bytemode, sizeflag);
16416 OP_XS (int bytemode, int sizeflag)
16418 if (modrm.mod == 3)
16419 OP_EX (bytemode, sizeflag);
16425 OP_M (int bytemode, int sizeflag)
16427 if (modrm.mod == 3)
16428 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16431 OP_E (bytemode, sizeflag);
16435 OP_0f07 (int bytemode, int sizeflag)
16437 if (modrm.mod != 3 || modrm.rm != 0)
16440 OP_E (bytemode, sizeflag);
16443 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16444 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16447 NOP_Fixup1 (int bytemode, int sizeflag)
16449 if ((prefixes & PREFIX_DATA) != 0
16452 && address_mode == mode_64bit))
16453 OP_REG (bytemode, sizeflag);
16455 strcpy (obuf, "nop");
16459 NOP_Fixup2 (int bytemode, int sizeflag)
16461 if ((prefixes & PREFIX_DATA) != 0
16464 && address_mode == mode_64bit))
16465 OP_IMREG (bytemode, sizeflag);
16468 static const char *const Suffix3DNow[] = {
16469 /* 00 */ NULL, NULL, NULL, NULL,
16470 /* 04 */ NULL, NULL, NULL, NULL,
16471 /* 08 */ NULL, NULL, NULL, NULL,
16472 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
16473 /* 10 */ NULL, NULL, NULL, NULL,
16474 /* 14 */ NULL, NULL, NULL, NULL,
16475 /* 18 */ NULL, NULL, NULL, NULL,
16476 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
16477 /* 20 */ NULL, NULL, NULL, NULL,
16478 /* 24 */ NULL, NULL, NULL, NULL,
16479 /* 28 */ NULL, NULL, NULL, NULL,
16480 /* 2C */ NULL, NULL, NULL, NULL,
16481 /* 30 */ NULL, NULL, NULL, NULL,
16482 /* 34 */ NULL, NULL, NULL, NULL,
16483 /* 38 */ NULL, NULL, NULL, NULL,
16484 /* 3C */ NULL, NULL, NULL, NULL,
16485 /* 40 */ NULL, NULL, NULL, NULL,
16486 /* 44 */ NULL, NULL, NULL, NULL,
16487 /* 48 */ NULL, NULL, NULL, NULL,
16488 /* 4C */ NULL, NULL, NULL, NULL,
16489 /* 50 */ NULL, NULL, NULL, NULL,
16490 /* 54 */ NULL, NULL, NULL, NULL,
16491 /* 58 */ NULL, NULL, NULL, NULL,
16492 /* 5C */ NULL, NULL, NULL, NULL,
16493 /* 60 */ NULL, NULL, NULL, NULL,
16494 /* 64 */ NULL, NULL, NULL, NULL,
16495 /* 68 */ NULL, NULL, NULL, NULL,
16496 /* 6C */ NULL, NULL, NULL, NULL,
16497 /* 70 */ NULL, NULL, NULL, NULL,
16498 /* 74 */ NULL, NULL, NULL, NULL,
16499 /* 78 */ NULL, NULL, NULL, NULL,
16500 /* 7C */ NULL, NULL, NULL, NULL,
16501 /* 80 */ NULL, NULL, NULL, NULL,
16502 /* 84 */ NULL, NULL, NULL, NULL,
16503 /* 88 */ NULL, NULL, "pfnacc", NULL,
16504 /* 8C */ NULL, NULL, "pfpnacc", NULL,
16505 /* 90 */ "pfcmpge", NULL, NULL, NULL,
16506 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
16507 /* 98 */ NULL, NULL, "pfsub", NULL,
16508 /* 9C */ NULL, NULL, "pfadd", NULL,
16509 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
16510 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
16511 /* A8 */ NULL, NULL, "pfsubr", NULL,
16512 /* AC */ NULL, NULL, "pfacc", NULL,
16513 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
16514 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
16515 /* B8 */ NULL, NULL, NULL, "pswapd",
16516 /* BC */ NULL, NULL, NULL, "pavgusb",
16517 /* C0 */ NULL, NULL, NULL, NULL,
16518 /* C4 */ NULL, NULL, NULL, NULL,
16519 /* C8 */ NULL, NULL, NULL, NULL,
16520 /* CC */ NULL, NULL, NULL, NULL,
16521 /* D0 */ NULL, NULL, NULL, NULL,
16522 /* D4 */ NULL, NULL, NULL, NULL,
16523 /* D8 */ NULL, NULL, NULL, NULL,
16524 /* DC */ NULL, NULL, NULL, NULL,
16525 /* E0 */ NULL, NULL, NULL, NULL,
16526 /* E4 */ NULL, NULL, NULL, NULL,
16527 /* E8 */ NULL, NULL, NULL, NULL,
16528 /* EC */ NULL, NULL, NULL, NULL,
16529 /* F0 */ NULL, NULL, NULL, NULL,
16530 /* F4 */ NULL, NULL, NULL, NULL,
16531 /* F8 */ NULL, NULL, NULL, NULL,
16532 /* FC */ NULL, NULL, NULL, NULL,
16536 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16538 const char *mnemonic;
16540 FETCH_DATA (the_info, codep + 1);
16541 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16542 place where an 8-bit immediate would normally go. ie. the last
16543 byte of the instruction. */
16544 obufp = mnemonicendp;
16545 mnemonic = Suffix3DNow[*codep++ & 0xff];
16547 oappend (mnemonic);
16550 /* Since a variable sized modrm/sib chunk is between the start
16551 of the opcode (0x0f0f) and the opcode suffix, we need to do
16552 all the modrm processing first, and don't know until now that
16553 we have a bad opcode. This necessitates some cleaning up. */
16554 op_out[0][0] = '\0';
16555 op_out[1][0] = '\0';
16558 mnemonicendp = obufp;
16561 static struct op simd_cmp_op[] =
16563 { STRING_COMMA_LEN ("eq") },
16564 { STRING_COMMA_LEN ("lt") },
16565 { STRING_COMMA_LEN ("le") },
16566 { STRING_COMMA_LEN ("unord") },
16567 { STRING_COMMA_LEN ("neq") },
16568 { STRING_COMMA_LEN ("nlt") },
16569 { STRING_COMMA_LEN ("nle") },
16570 { STRING_COMMA_LEN ("ord") }
16574 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16576 unsigned int cmp_type;
16578 FETCH_DATA (the_info, codep + 1);
16579 cmp_type = *codep++ & 0xff;
16580 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16583 char *p = mnemonicendp - 2;
16587 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16588 mnemonicendp += simd_cmp_op[cmp_type].len;
16592 /* We have a reserved extension byte. Output it directly. */
16593 scratchbuf[0] = '$';
16594 print_operand_value (scratchbuf + 1, 1, cmp_type);
16595 oappend_maybe_intel (scratchbuf);
16596 scratchbuf[0] = '\0';
16601 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16602 int sizeflag ATTRIBUTE_UNUSED)
16604 /* mwaitx %eax,%ecx,%ebx */
16607 const char **names = (address_mode == mode_64bit
16608 ? names64 : names32);
16609 strcpy (op_out[0], names[0]);
16610 strcpy (op_out[1], names[1]);
16611 strcpy (op_out[2], names[3]);
16612 two_source_ops = 1;
16614 /* Skip mod/rm byte. */
16620 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16621 int sizeflag ATTRIBUTE_UNUSED)
16623 /* mwait %eax,%ecx */
16626 const char **names = (address_mode == mode_64bit
16627 ? names64 : names32);
16628 strcpy (op_out[0], names[0]);
16629 strcpy (op_out[1], names[1]);
16630 two_source_ops = 1;
16632 /* Skip mod/rm byte. */
16638 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16639 int sizeflag ATTRIBUTE_UNUSED)
16641 /* monitor %eax,%ecx,%edx" */
16644 const char **op1_names;
16645 const char **names = (address_mode == mode_64bit
16646 ? names64 : names32);
16648 if (!(prefixes & PREFIX_ADDR))
16649 op1_names = (address_mode == mode_16bit
16650 ? names16 : names);
16653 /* Remove "addr16/addr32". */
16654 all_prefixes[last_addr_prefix] = 0;
16655 op1_names = (address_mode != mode_32bit
16656 ? names32 : names16);
16657 used_prefixes |= PREFIX_ADDR;
16659 strcpy (op_out[0], op1_names[0]);
16660 strcpy (op_out[1], names[1]);
16661 strcpy (op_out[2], names[2]);
16662 two_source_ops = 1;
16664 /* Skip mod/rm byte. */
16672 /* Throw away prefixes and 1st. opcode byte. */
16673 codep = insn_codep + 1;
16678 REP_Fixup (int bytemode, int sizeflag)
16680 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16682 if (prefixes & PREFIX_REPZ)
16683 all_prefixes[last_repz_prefix] = REP_PREFIX;
16690 OP_IMREG (bytemode, sizeflag);
16693 OP_ESreg (bytemode, sizeflag);
16696 OP_DSreg (bytemode, sizeflag);
16704 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16708 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16710 if (prefixes & PREFIX_REPNZ)
16711 all_prefixes[last_repnz_prefix] = BND_PREFIX;
16714 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16715 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16719 HLE_Fixup1 (int bytemode, int sizeflag)
16722 && (prefixes & PREFIX_LOCK) != 0)
16724 if (prefixes & PREFIX_REPZ)
16725 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16726 if (prefixes & PREFIX_REPNZ)
16727 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16730 OP_E (bytemode, sizeflag);
16733 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16734 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16738 HLE_Fixup2 (int bytemode, int sizeflag)
16740 if (modrm.mod != 3)
16742 if (prefixes & PREFIX_REPZ)
16743 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16744 if (prefixes & PREFIX_REPNZ)
16745 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16748 OP_E (bytemode, sizeflag);
16751 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16752 "xrelease" for memory operand. No check for LOCK prefix. */
16755 HLE_Fixup3 (int bytemode, int sizeflag)
16758 && last_repz_prefix > last_repnz_prefix
16759 && (prefixes & PREFIX_REPZ) != 0)
16760 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16762 OP_E (bytemode, sizeflag);
16766 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16771 /* Change cmpxchg8b to cmpxchg16b. */
16772 char *p = mnemonicendp - 2;
16773 mnemonicendp = stpcpy (p, "16b");
16776 else if ((prefixes & PREFIX_LOCK) != 0)
16778 if (prefixes & PREFIX_REPZ)
16779 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16780 if (prefixes & PREFIX_REPNZ)
16781 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16784 OP_M (bytemode, sizeflag);
16788 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16790 const char **names;
16794 switch (vex.length)
16808 oappend (names[reg]);
16812 CRC32_Fixup (int bytemode, int sizeflag)
16814 /* Add proper suffix to "crc32". */
16815 char *p = mnemonicendp;
16834 if (sizeflag & DFLAG)
16838 used_prefixes |= (prefixes & PREFIX_DATA);
16842 oappend (INTERNAL_DISASSEMBLER_ERROR);
16849 if (modrm.mod == 3)
16853 /* Skip mod/rm byte. */
16858 add = (rex & REX_B) ? 8 : 0;
16859 if (bytemode == b_mode)
16863 oappend (names8rex[modrm.rm + add]);
16865 oappend (names8[modrm.rm + add]);
16871 oappend (names64[modrm.rm + add]);
16872 else if ((prefixes & PREFIX_DATA))
16873 oappend (names16[modrm.rm + add]);
16875 oappend (names32[modrm.rm + add]);
16879 OP_E (bytemode, sizeflag);
16883 FXSAVE_Fixup (int bytemode, int sizeflag)
16885 /* Add proper suffix to "fxsave" and "fxrstor". */
16889 char *p = mnemonicendp;
16895 OP_M (bytemode, sizeflag);
16898 /* Display the destination register operand for instructions with
16902 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16905 const char **names;
16913 reg = vex.register_specifier;
16920 if (bytemode == vex_scalar_mode)
16922 oappend (names_xmm[reg]);
16926 switch (vex.length)
16933 case vex_vsib_q_w_dq_mode:
16934 case vex_vsib_q_w_d_mode:
16950 names = names_mask;
16964 case vex_vsib_q_w_dq_mode:
16965 case vex_vsib_q_w_d_mode:
16966 names = vex.w ? names_ymm : names_xmm;
16975 names = names_mask;
16978 /* See PR binutils/20893 for a reproducer. */
16990 oappend (names[reg]);
16993 /* Get the VEX immediate byte without moving codep. */
16995 static unsigned char
16996 get_vex_imm8 (int sizeflag, int opnum)
16998 int bytes_before_imm = 0;
17000 if (modrm.mod != 3)
17002 /* There are SIB/displacement bytes. */
17003 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17005 /* 32/64 bit address mode */
17006 int base = modrm.rm;
17008 /* Check SIB byte. */
17011 FETCH_DATA (the_info, codep + 1);
17013 /* When decoding the third source, don't increase
17014 bytes_before_imm as this has already been incremented
17015 by one in OP_E_memory while decoding the second
17018 bytes_before_imm++;
17021 /* Don't increase bytes_before_imm when decoding the third source,
17022 it has already been incremented by OP_E_memory while decoding
17023 the second source operand. */
17029 /* When modrm.rm == 5 or modrm.rm == 4 and base in
17030 SIB == 5, there is a 4 byte displacement. */
17032 /* No displacement. */
17034 /* Fall through. */
17036 /* 4 byte displacement. */
17037 bytes_before_imm += 4;
17040 /* 1 byte displacement. */
17041 bytes_before_imm++;
17048 /* 16 bit address mode */
17049 /* Don't increase bytes_before_imm when decoding the third source,
17050 it has already been incremented by OP_E_memory while decoding
17051 the second source operand. */
17057 /* When modrm.rm == 6, there is a 2 byte displacement. */
17059 /* No displacement. */
17061 /* Fall through. */
17063 /* 2 byte displacement. */
17064 bytes_before_imm += 2;
17067 /* 1 byte displacement: when decoding the third source,
17068 don't increase bytes_before_imm as this has already
17069 been incremented by one in OP_E_memory while decoding
17070 the second source operand. */
17072 bytes_before_imm++;
17080 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17081 return codep [bytes_before_imm];
17085 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17087 const char **names;
17089 if (reg == -1 && modrm.mod != 3)
17091 OP_E_memory (bytemode, sizeflag);
17103 else if (reg > 7 && address_mode != mode_64bit)
17107 switch (vex.length)
17118 oappend (names[reg]);
17122 OP_EX_VexImmW (int bytemode, int sizeflag)
17125 static unsigned char vex_imm8;
17127 if (vex_w_done == 0)
17131 /* Skip mod/rm byte. */
17135 vex_imm8 = get_vex_imm8 (sizeflag, 0);
17138 reg = vex_imm8 >> 4;
17140 OP_EX_VexReg (bytemode, sizeflag, reg);
17142 else if (vex_w_done == 1)
17147 reg = vex_imm8 >> 4;
17149 OP_EX_VexReg (bytemode, sizeflag, reg);
17153 /* Output the imm8 directly. */
17154 scratchbuf[0] = '$';
17155 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17156 oappend_maybe_intel (scratchbuf);
17157 scratchbuf[0] = '\0';
17163 OP_Vex_2src (int bytemode, int sizeflag)
17165 if (modrm.mod == 3)
17167 int reg = modrm.rm;
17171 oappend (names_xmm[reg]);
17176 && (bytemode == v_mode || bytemode == v_swap_mode))
17178 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17179 used_prefixes |= (prefixes & PREFIX_DATA);
17181 OP_E (bytemode, sizeflag);
17186 OP_Vex_2src_1 (int bytemode, int sizeflag)
17188 if (modrm.mod == 3)
17190 /* Skip mod/rm byte. */
17196 oappend (names_xmm[vex.register_specifier]);
17198 OP_Vex_2src (bytemode, sizeflag);
17202 OP_Vex_2src_2 (int bytemode, int sizeflag)
17205 OP_Vex_2src (bytemode, sizeflag);
17207 oappend (names_xmm[vex.register_specifier]);
17211 OP_EX_VexW (int bytemode, int sizeflag)
17219 /* Skip mod/rm byte. */
17224 reg = get_vex_imm8 (sizeflag, 0) >> 4;
17229 reg = get_vex_imm8 (sizeflag, 1) >> 4;
17232 OP_EX_VexReg (bytemode, sizeflag, reg);
17236 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17237 int sizeflag ATTRIBUTE_UNUSED)
17239 /* Skip the immediate byte and check for invalid bits. */
17240 FETCH_DATA (the_info, codep + 1);
17241 if (*codep++ & 0xf)
17246 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17249 const char **names;
17251 FETCH_DATA (the_info, codep + 1);
17254 if (bytemode != x_mode)
17261 if (reg > 7 && address_mode != mode_64bit)
17264 switch (vex.length)
17275 oappend (names[reg]);
17279 OP_XMM_VexW (int bytemode, int sizeflag)
17281 /* Turn off the REX.W bit since it is used for swapping operands
17284 OP_XMM (bytemode, sizeflag);
17288 OP_EX_Vex (int bytemode, int sizeflag)
17290 if (modrm.mod != 3)
17292 if (vex.register_specifier != 0)
17296 OP_EX (bytemode, sizeflag);
17300 OP_XMM_Vex (int bytemode, int sizeflag)
17302 if (modrm.mod != 3)
17304 if (vex.register_specifier != 0)
17308 OP_XMM (bytemode, sizeflag);
17312 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17314 switch (vex.length)
17317 mnemonicendp = stpcpy (obuf, "vzeroupper");
17320 mnemonicendp = stpcpy (obuf, "vzeroall");
17327 static struct op vex_cmp_op[] =
17329 { STRING_COMMA_LEN ("eq") },
17330 { STRING_COMMA_LEN ("lt") },
17331 { STRING_COMMA_LEN ("le") },
17332 { STRING_COMMA_LEN ("unord") },
17333 { STRING_COMMA_LEN ("neq") },
17334 { STRING_COMMA_LEN ("nlt") },
17335 { STRING_COMMA_LEN ("nle") },
17336 { STRING_COMMA_LEN ("ord") },
17337 { STRING_COMMA_LEN ("eq_uq") },
17338 { STRING_COMMA_LEN ("nge") },
17339 { STRING_COMMA_LEN ("ngt") },
17340 { STRING_COMMA_LEN ("false") },
17341 { STRING_COMMA_LEN ("neq_oq") },
17342 { STRING_COMMA_LEN ("ge") },
17343 { STRING_COMMA_LEN ("gt") },
17344 { STRING_COMMA_LEN ("true") },
17345 { STRING_COMMA_LEN ("eq_os") },
17346 { STRING_COMMA_LEN ("lt_oq") },
17347 { STRING_COMMA_LEN ("le_oq") },
17348 { STRING_COMMA_LEN ("unord_s") },
17349 { STRING_COMMA_LEN ("neq_us") },
17350 { STRING_COMMA_LEN ("nlt_uq") },
17351 { STRING_COMMA_LEN ("nle_uq") },
17352 { STRING_COMMA_LEN ("ord_s") },
17353 { STRING_COMMA_LEN ("eq_us") },
17354 { STRING_COMMA_LEN ("nge_uq") },
17355 { STRING_COMMA_LEN ("ngt_uq") },
17356 { STRING_COMMA_LEN ("false_os") },
17357 { STRING_COMMA_LEN ("neq_os") },
17358 { STRING_COMMA_LEN ("ge_oq") },
17359 { STRING_COMMA_LEN ("gt_oq") },
17360 { STRING_COMMA_LEN ("true_us") },
17364 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17366 unsigned int cmp_type;
17368 FETCH_DATA (the_info, codep + 1);
17369 cmp_type = *codep++ & 0xff;
17370 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17373 char *p = mnemonicendp - 2;
17377 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17378 mnemonicendp += vex_cmp_op[cmp_type].len;
17382 /* We have a reserved extension byte. Output it directly. */
17383 scratchbuf[0] = '$';
17384 print_operand_value (scratchbuf + 1, 1, cmp_type);
17385 oappend_maybe_intel (scratchbuf);
17386 scratchbuf[0] = '\0';
17391 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17392 int sizeflag ATTRIBUTE_UNUSED)
17394 unsigned int cmp_type;
17399 FETCH_DATA (the_info, codep + 1);
17400 cmp_type = *codep++ & 0xff;
17401 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17402 If it's the case, print suffix, otherwise - print the immediate. */
17403 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17408 char *p = mnemonicendp - 2;
17410 /* vpcmp* can have both one- and two-lettered suffix. */
17424 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17425 mnemonicendp += simd_cmp_op[cmp_type].len;
17429 /* We have a reserved extension byte. Output it directly. */
17430 scratchbuf[0] = '$';
17431 print_operand_value (scratchbuf + 1, 1, cmp_type);
17432 oappend_maybe_intel (scratchbuf);
17433 scratchbuf[0] = '\0';
17437 static const struct op pclmul_op[] =
17439 { STRING_COMMA_LEN ("lql") },
17440 { STRING_COMMA_LEN ("hql") },
17441 { STRING_COMMA_LEN ("lqh") },
17442 { STRING_COMMA_LEN ("hqh") }
17446 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17447 int sizeflag ATTRIBUTE_UNUSED)
17449 unsigned int pclmul_type;
17451 FETCH_DATA (the_info, codep + 1);
17452 pclmul_type = *codep++ & 0xff;
17453 switch (pclmul_type)
17464 if (pclmul_type < ARRAY_SIZE (pclmul_op))
17467 char *p = mnemonicendp - 3;
17472 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17473 mnemonicendp += pclmul_op[pclmul_type].len;
17477 /* We have a reserved extension byte. Output it directly. */
17478 scratchbuf[0] = '$';
17479 print_operand_value (scratchbuf + 1, 1, pclmul_type);
17480 oappend_maybe_intel (scratchbuf);
17481 scratchbuf[0] = '\0';
17486 MOVBE_Fixup (int bytemode, int sizeflag)
17488 /* Add proper suffix to "movbe". */
17489 char *p = mnemonicendp;
17498 if (sizeflag & SUFFIX_ALWAYS)
17504 if (sizeflag & DFLAG)
17508 used_prefixes |= (prefixes & PREFIX_DATA);
17513 oappend (INTERNAL_DISASSEMBLER_ERROR);
17520 OP_M (bytemode, sizeflag);
17524 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17527 const char **names;
17529 /* Skip mod/rm byte. */
17543 oappend (names[reg]);
17547 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17549 const char **names;
17556 oappend (names[vex.register_specifier]);
17560 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17563 || (bytemode != mask_mode && bytemode != mask_bd_mode))
17567 if ((rex & REX_R) != 0 || !vex.r)
17573 oappend (names_mask [modrm.reg]);
17577 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17580 || (bytemode != evex_rounding_mode
17581 && bytemode != evex_sae_mode))
17583 if (modrm.mod == 3 && vex.b)
17586 case evex_rounding_mode:
17587 oappend (names_rounding[vex.ll]);
17589 case evex_sae_mode: