1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2018 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma, disassemble_info *);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma get64 (void);
58 static bfd_signed_vma get32 (void);
59 static bfd_signed_vma get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VZERO_Fixup (int, int);
99 static void VCMP_Fixup (int, int);
100 static void VPCMP_Fixup (int, int);
101 static void VPCOM_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void OP_Mwaitx (int, int);
106 static void NOP_Fixup1 (int, int);
107 static void NOP_Fixup2 (int, int);
108 static void OP_3DNowSuffix (int, int);
109 static void CMP_Fixup (int, int);
110 static void BadOp (void);
111 static void REP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void NOTRACK_Fixup (int, int);
114 static void HLE_Fixup1 (int, int);
115 static void HLE_Fixup2 (int, int);
116 static void HLE_Fixup3 (int, int);
117 static void CMPXCHG8B_Fixup (int, int);
118 static void XMM_Fixup (int, int);
119 static void CRC32_Fixup (int, int);
120 static void FXSAVE_Fixup (int, int);
121 static void PCMPESTR_Fixup (int, int);
122 static void OP_LWPCB_E (int, int);
123 static void OP_LWP_E (int, int);
124 static void OP_Vex_2src_1 (int, int);
125 static void OP_Vex_2src_2 (int, int);
127 static void MOVBE_Fixup (int, int);
129 static void OP_Mask (int, int);
132 /* Points to first byte not fetched. */
133 bfd_byte *max_fetched;
134 bfd_byte the_buffer[MAX_MNEM_SIZE];
137 OPCODES_SIGJMP_BUF bailout;
147 enum address_mode address_mode;
149 /* Flags for the prefixes for the current instruction. See below. */
152 /* REX prefix the current instruction. See below. */
154 /* Bits of REX we've already used. */
156 /* REX bits in original REX prefix ignored. */
157 static int rex_ignored;
158 /* Mark parts used in the REX prefix. When we are testing for
159 empty prefix (for 8bit register REX extension), just mask it
160 out. Otherwise test for REX bit is excuse for existence of REX
161 only in case value is nonzero. */
162 #define USED_REX(value) \
167 rex_used |= (value) | REX_OPCODE; \
170 rex_used |= REX_OPCODE; \
173 /* Flags for prefixes which we somehow handled when printing the
174 current instruction. */
175 static int used_prefixes;
177 /* Flags stored in PREFIXES. */
178 #define PREFIX_REPZ 1
179 #define PREFIX_REPNZ 2
180 #define PREFIX_LOCK 4
182 #define PREFIX_SS 0x10
183 #define PREFIX_DS 0x20
184 #define PREFIX_ES 0x40
185 #define PREFIX_FS 0x80
186 #define PREFIX_GS 0x100
187 #define PREFIX_DATA 0x200
188 #define PREFIX_ADDR 0x400
189 #define PREFIX_FWAIT 0x800
191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
192 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
194 #define FETCH_DATA(info, addr) \
195 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
196 ? 1 : fetch_data ((info), (addr)))
199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
202 struct dis_private *priv = (struct dis_private *) info->private_data;
203 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
205 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
206 status = (*info->read_memory_func) (start,
208 addr - priv->max_fetched,
214 /* If we did manage to read at least one byte, then
215 print_insn_i386 will do something sensible. Otherwise, print
216 an error. We do that here because this is where we know
218 if (priv->max_fetched == priv->the_buffer)
219 (*info->memory_error_func) (status, start, info);
220 OPCODES_SIGLONGJMP (priv->bailout, 1);
223 priv->max_fetched = addr;
227 /* Possible values for prefix requirement. */
228 #define PREFIX_IGNORED_SHIFT 16
229 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
233 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
235 /* Opcode prefixes. */
236 #define PREFIX_OPCODE (PREFIX_REPZ \
240 /* Prefixes ignored. */
241 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
242 | PREFIX_IGNORED_REPNZ \
243 | PREFIX_IGNORED_DATA)
245 #define XX { NULL, 0 }
246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
248 #define Eb { OP_E, b_mode }
249 #define Ebnd { OP_E, bnd_mode }
250 #define EbS { OP_E, b_swap_mode }
251 #define EbndS { OP_E, bnd_swap_mode }
252 #define Ev { OP_E, v_mode }
253 #define Eva { OP_E, va_mode }
254 #define Ev_bnd { OP_E, v_bnd_mode }
255 #define EvS { OP_E, v_swap_mode }
256 #define Ed { OP_E, d_mode }
257 #define Edq { OP_E, dq_mode }
258 #define Edqw { OP_E, dqw_mode }
259 #define Edqb { OP_E, dqb_mode }
260 #define Edb { OP_E, db_mode }
261 #define Edw { OP_E, dw_mode }
262 #define Edqd { OP_E, dqd_mode }
263 #define Edqa { OP_E, dqa_mode }
264 #define Eq { OP_E, q_mode }
265 #define indirEv { OP_indirE, indir_v_mode }
266 #define indirEp { OP_indirE, f_mode }
267 #define stackEv { OP_E, stack_v_mode }
268 #define Em { OP_E, m_mode }
269 #define Ew { OP_E, w_mode }
270 #define M { OP_M, 0 } /* lea, lgdt, etc. */
271 #define Ma { OP_M, a_mode }
272 #define Mb { OP_M, b_mode }
273 #define Md { OP_M, d_mode }
274 #define Mo { OP_M, o_mode }
275 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
276 #define Mq { OP_M, q_mode }
277 #define Mv_bnd { OP_M, v_bndmk_mode }
278 #define Mx { OP_M, x_mode }
279 #define Mxmm { OP_M, xmm_mode }
280 #define Gb { OP_G, b_mode }
281 #define Gbnd { OP_G, bnd_mode }
282 #define Gv { OP_G, v_mode }
283 #define Gd { OP_G, d_mode }
284 #define Gdq { OP_G, dq_mode }
285 #define Gm { OP_G, m_mode }
286 #define Gva { OP_G, va_mode }
287 #define Gw { OP_G, w_mode }
288 #define Rd { OP_R, d_mode }
289 #define Rdq { OP_R, dq_mode }
290 #define Rm { OP_R, m_mode }
291 #define Ib { OP_I, b_mode }
292 #define sIb { OP_sI, b_mode } /* sign extened byte */
293 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
294 #define Iv { OP_I, v_mode }
295 #define sIv { OP_sI, v_mode }
296 #define Iq { OP_I, q_mode }
297 #define Iv64 { OP_I64, v_mode }
298 #define Iw { OP_I, w_mode }
299 #define I1 { OP_I, const_1_mode }
300 #define Jb { OP_J, b_mode }
301 #define Jv { OP_J, v_mode }
302 #define Cm { OP_C, m_mode }
303 #define Dm { OP_D, m_mode }
304 #define Td { OP_T, d_mode }
305 #define Skip_MODRM { OP_Skip_MODRM, 0 }
307 #define RMeAX { OP_REG, eAX_reg }
308 #define RMeBX { OP_REG, eBX_reg }
309 #define RMeCX { OP_REG, eCX_reg }
310 #define RMeDX { OP_REG, eDX_reg }
311 #define RMeSP { OP_REG, eSP_reg }
312 #define RMeBP { OP_REG, eBP_reg }
313 #define RMeSI { OP_REG, eSI_reg }
314 #define RMeDI { OP_REG, eDI_reg }
315 #define RMrAX { OP_REG, rAX_reg }
316 #define RMrBX { OP_REG, rBX_reg }
317 #define RMrCX { OP_REG, rCX_reg }
318 #define RMrDX { OP_REG, rDX_reg }
319 #define RMrSP { OP_REG, rSP_reg }
320 #define RMrBP { OP_REG, rBP_reg }
321 #define RMrSI { OP_REG, rSI_reg }
322 #define RMrDI { OP_REG, rDI_reg }
323 #define RMAL { OP_REG, al_reg }
324 #define RMCL { OP_REG, cl_reg }
325 #define RMDL { OP_REG, dl_reg }
326 #define RMBL { OP_REG, bl_reg }
327 #define RMAH { OP_REG, ah_reg }
328 #define RMCH { OP_REG, ch_reg }
329 #define RMDH { OP_REG, dh_reg }
330 #define RMBH { OP_REG, bh_reg }
331 #define RMAX { OP_REG, ax_reg }
332 #define RMDX { OP_REG, dx_reg }
334 #define eAX { OP_IMREG, eAX_reg }
335 #define eBX { OP_IMREG, eBX_reg }
336 #define eCX { OP_IMREG, eCX_reg }
337 #define eDX { OP_IMREG, eDX_reg }
338 #define eSP { OP_IMREG, eSP_reg }
339 #define eBP { OP_IMREG, eBP_reg }
340 #define eSI { OP_IMREG, eSI_reg }
341 #define eDI { OP_IMREG, eDI_reg }
342 #define AL { OP_IMREG, al_reg }
343 #define CL { OP_IMREG, cl_reg }
344 #define DL { OP_IMREG, dl_reg }
345 #define BL { OP_IMREG, bl_reg }
346 #define AH { OP_IMREG, ah_reg }
347 #define CH { OP_IMREG, ch_reg }
348 #define DH { OP_IMREG, dh_reg }
349 #define BH { OP_IMREG, bh_reg }
350 #define AX { OP_IMREG, ax_reg }
351 #define DX { OP_IMREG, dx_reg }
352 #define zAX { OP_IMREG, z_mode_ax_reg }
353 #define indirDX { OP_IMREG, indir_dx_reg }
355 #define Sw { OP_SEG, w_mode }
356 #define Sv { OP_SEG, v_mode }
357 #define Ap { OP_DIR, 0 }
358 #define Ob { OP_OFF64, b_mode }
359 #define Ov { OP_OFF64, v_mode }
360 #define Xb { OP_DSreg, eSI_reg }
361 #define Xv { OP_DSreg, eSI_reg }
362 #define Xz { OP_DSreg, eSI_reg }
363 #define Yb { OP_ESreg, eDI_reg }
364 #define Yv { OP_ESreg, eDI_reg }
365 #define DSBX { OP_DSreg, eBX_reg }
367 #define es { OP_REG, es_reg }
368 #define ss { OP_REG, ss_reg }
369 #define cs { OP_REG, cs_reg }
370 #define ds { OP_REG, ds_reg }
371 #define fs { OP_REG, fs_reg }
372 #define gs { OP_REG, gs_reg }
374 #define MX { OP_MMX, 0 }
375 #define XM { OP_XMM, 0 }
376 #define XMScalar { OP_XMM, scalar_mode }
377 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
378 #define XMM { OP_XMM, xmm_mode }
379 #define XMxmmq { OP_XMM, xmmq_mode }
380 #define EM { OP_EM, v_mode }
381 #define EMS { OP_EM, v_swap_mode }
382 #define EMd { OP_EM, d_mode }
383 #define EMx { OP_EM, x_mode }
384 #define EXbScalar { OP_EX, b_scalar_mode }
385 #define EXw { OP_EX, w_mode }
386 #define EXwScalar { OP_EX, w_scalar_mode }
387 #define EXd { OP_EX, d_mode }
388 #define EXdScalar { OP_EX, d_scalar_mode }
389 #define EXdS { OP_EX, d_swap_mode }
390 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
391 #define EXq { OP_EX, q_mode }
392 #define EXqScalar { OP_EX, q_scalar_mode }
393 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
394 #define EXqS { OP_EX, q_swap_mode }
395 #define EXx { OP_EX, x_mode }
396 #define EXxS { OP_EX, x_swap_mode }
397 #define EXxmm { OP_EX, xmm_mode }
398 #define EXymm { OP_EX, ymm_mode }
399 #define EXxmmq { OP_EX, xmmq_mode }
400 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
401 #define EXxmm_mb { OP_EX, xmm_mb_mode }
402 #define EXxmm_mw { OP_EX, xmm_mw_mode }
403 #define EXxmm_md { OP_EX, xmm_md_mode }
404 #define EXxmm_mq { OP_EX, xmm_mq_mode }
405 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
406 #define EXxmmdw { OP_EX, xmmdw_mode }
407 #define EXxmmqd { OP_EX, xmmqd_mode }
408 #define EXymmq { OP_EX, ymmq_mode }
409 #define EXVexWdq { OP_EX, vex_w_dq_mode }
410 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
411 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
412 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
413 #define MS { OP_MS, v_mode }
414 #define XS { OP_XS, v_mode }
415 #define EMCq { OP_EMC, q_mode }
416 #define MXC { OP_MXC, 0 }
417 #define OPSUF { OP_3DNowSuffix, 0 }
418 #define CMP { CMP_Fixup, 0 }
419 #define XMM0 { XMM_Fixup, 0 }
420 #define FXSAVE { FXSAVE_Fixup, 0 }
421 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
422 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
424 #define Vex { OP_VEX, vex_mode }
425 #define VexScalar { OP_VEX, vex_scalar_mode }
426 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
427 #define Vex128 { OP_VEX, vex128_mode }
428 #define Vex256 { OP_VEX, vex256_mode }
429 #define VexGdq { OP_VEX, dq_mode }
430 #define EXdVex { OP_EX_Vex, d_mode }
431 #define EXdVexS { OP_EX_Vex, d_swap_mode }
432 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
433 #define EXqVex { OP_EX_Vex, q_mode }
434 #define EXqVexS { OP_EX_Vex, q_swap_mode }
435 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
436 #define EXVexW { OP_EX_VexW, x_mode }
437 #define EXdVexW { OP_EX_VexW, d_mode }
438 #define EXqVexW { OP_EX_VexW, q_mode }
439 #define EXVexImmW { OP_EX_VexImmW, x_mode }
440 #define XMVex { OP_XMM_Vex, 0 }
441 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
442 #define XMVexW { OP_XMM_VexW, 0 }
443 #define XMVexI4 { OP_REG_VexI4, x_mode }
444 #define PCLMUL { PCLMUL_Fixup, 0 }
445 #define VZERO { VZERO_Fixup, 0 }
446 #define VCMP { VCMP_Fixup, 0 }
447 #define VPCMP { VPCMP_Fixup, 0 }
448 #define VPCOM { VPCOM_Fixup, 0 }
450 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
451 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
452 #define EXxEVexS { OP_Rounding, evex_sae_mode }
454 #define XMask { OP_Mask, mask_mode }
455 #define MaskG { OP_G, mask_mode }
456 #define MaskE { OP_E, mask_mode }
457 #define MaskBDE { OP_E, mask_bd_mode }
458 #define MaskR { OP_R, mask_mode }
459 #define MaskVex { OP_VEX, mask_mode }
461 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
462 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
463 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
464 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
466 /* Used handle "rep" prefix for string instructions. */
467 #define Xbr { REP_Fixup, eSI_reg }
468 #define Xvr { REP_Fixup, eSI_reg }
469 #define Ybr { REP_Fixup, eDI_reg }
470 #define Yvr { REP_Fixup, eDI_reg }
471 #define Yzr { REP_Fixup, eDI_reg }
472 #define indirDXr { REP_Fixup, indir_dx_reg }
473 #define ALr { REP_Fixup, al_reg }
474 #define eAXr { REP_Fixup, eAX_reg }
476 /* Used handle HLE prefix for lockable instructions. */
477 #define Ebh1 { HLE_Fixup1, b_mode }
478 #define Evh1 { HLE_Fixup1, v_mode }
479 #define Ebh2 { HLE_Fixup2, b_mode }
480 #define Evh2 { HLE_Fixup2, v_mode }
481 #define Ebh3 { HLE_Fixup3, b_mode }
482 #define Evh3 { HLE_Fixup3, v_mode }
484 #define BND { BND_Fixup, 0 }
485 #define NOTRACK { NOTRACK_Fixup, 0 }
487 #define cond_jump_flag { NULL, cond_jump_mode }
488 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
490 /* bits in sizeflag */
491 #define SUFFIX_ALWAYS 4
499 /* byte operand with operand swapped */
501 /* byte operand, sign extend like 'T' suffix */
503 /* operand size depends on prefixes */
505 /* operand size depends on prefixes with operand swapped */
507 /* operand size depends on address prefix */
511 /* double word operand */
513 /* double word operand with operand swapped */
515 /* quad word operand */
517 /* quad word operand with operand swapped */
519 /* ten-byte operand */
521 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
522 broadcast enabled. */
524 /* Similar to x_mode, but with different EVEX mem shifts. */
526 /* Similar to x_mode, but with disabled broadcast. */
528 /* Similar to x_mode, but with operands swapped and disabled broadcast
531 /* 16-byte XMM operand */
533 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
534 memory operand (depending on vector length). Broadcast isn't
537 /* Same as xmmq_mode, but broadcast is allowed. */
538 evex_half_bcst_xmmq_mode,
539 /* XMM register or byte memory operand */
541 /* XMM register or word memory operand */
543 /* XMM register or double word memory operand */
545 /* XMM register or quad word memory operand */
547 /* XMM register or double/quad word memory operand, depending on
550 /* 16-byte XMM, word, double word or quad word operand. */
552 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
554 /* 32-byte YMM operand */
556 /* quad word, ymmword or zmmword memory operand. */
558 /* 32-byte YMM or 16-byte word operand */
560 /* d_mode in 32bit, q_mode in 64bit mode. */
562 /* pair of v_mode operands */
567 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
569 /* operand size depends on REX prefixes. */
571 /* registers like dq_mode, memory like w_mode. */
575 /* bounds operand with operand swapped */
577 /* 4- or 6-byte pointer operand */
580 /* v_mode for indirect branch opcodes. */
582 /* v_mode for stack-related opcodes. */
584 /* non-quad operand size depends on prefixes */
586 /* 16-byte operand */
588 /* registers like dq_mode, memory like b_mode. */
590 /* registers like d_mode, memory like b_mode. */
592 /* registers like d_mode, memory like w_mode. */
594 /* registers like dq_mode, memory like d_mode. */
596 /* operand size depends on the W bit as well as address mode. */
598 /* normal vex mode */
600 /* 128bit vex mode */
602 /* 256bit vex mode */
604 /* operand size depends on the VEX.W bit. */
607 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
608 vex_vsib_d_w_dq_mode,
609 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
611 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
612 vex_vsib_q_w_dq_mode,
613 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
616 /* scalar, ignore vector length. */
618 /* like b_mode, ignore vector length. */
620 /* like w_mode, ignore vector length. */
622 /* like d_mode, ignore vector length. */
624 /* like d_swap_mode, ignore vector length. */
626 /* like q_mode, ignore vector length. */
628 /* like q_swap_mode, ignore vector length. */
630 /* like vex_mode, ignore vector length. */
632 /* like vex_w_dq_mode, ignore vector length. */
633 vex_scalar_w_dq_mode,
635 /* Static rounding. */
637 /* Static rounding, 64-bit mode only. */
638 evex_rounding_64_mode,
639 /* Supress all exceptions. */
642 /* Mask register operand. */
644 /* Mask register operand. */
711 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
713 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
714 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
715 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
716 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
717 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
718 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
719 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
720 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
721 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
722 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
723 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
724 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
725 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
726 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
727 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
853 MOD_VEX_0F12_PREFIX_0,
855 MOD_VEX_0F16_PREFIX_0,
858 MOD_VEX_W_0_0F41_P_0_LEN_1,
859 MOD_VEX_W_1_0F41_P_0_LEN_1,
860 MOD_VEX_W_0_0F41_P_2_LEN_1,
861 MOD_VEX_W_1_0F41_P_2_LEN_1,
862 MOD_VEX_W_0_0F42_P_0_LEN_1,
863 MOD_VEX_W_1_0F42_P_0_LEN_1,
864 MOD_VEX_W_0_0F42_P_2_LEN_1,
865 MOD_VEX_W_1_0F42_P_2_LEN_1,
866 MOD_VEX_W_0_0F44_P_0_LEN_1,
867 MOD_VEX_W_1_0F44_P_0_LEN_1,
868 MOD_VEX_W_0_0F44_P_2_LEN_1,
869 MOD_VEX_W_1_0F44_P_2_LEN_1,
870 MOD_VEX_W_0_0F45_P_0_LEN_1,
871 MOD_VEX_W_1_0F45_P_0_LEN_1,
872 MOD_VEX_W_0_0F45_P_2_LEN_1,
873 MOD_VEX_W_1_0F45_P_2_LEN_1,
874 MOD_VEX_W_0_0F46_P_0_LEN_1,
875 MOD_VEX_W_1_0F46_P_0_LEN_1,
876 MOD_VEX_W_0_0F46_P_2_LEN_1,
877 MOD_VEX_W_1_0F46_P_2_LEN_1,
878 MOD_VEX_W_0_0F47_P_0_LEN_1,
879 MOD_VEX_W_1_0F47_P_0_LEN_1,
880 MOD_VEX_W_0_0F47_P_2_LEN_1,
881 MOD_VEX_W_1_0F47_P_2_LEN_1,
882 MOD_VEX_W_0_0F4A_P_0_LEN_1,
883 MOD_VEX_W_1_0F4A_P_0_LEN_1,
884 MOD_VEX_W_0_0F4A_P_2_LEN_1,
885 MOD_VEX_W_1_0F4A_P_2_LEN_1,
886 MOD_VEX_W_0_0F4B_P_0_LEN_1,
887 MOD_VEX_W_1_0F4B_P_0_LEN_1,
888 MOD_VEX_W_0_0F4B_P_2_LEN_1,
900 MOD_VEX_W_0_0F91_P_0_LEN_0,
901 MOD_VEX_W_1_0F91_P_0_LEN_0,
902 MOD_VEX_W_0_0F91_P_2_LEN_0,
903 MOD_VEX_W_1_0F91_P_2_LEN_0,
904 MOD_VEX_W_0_0F92_P_0_LEN_0,
905 MOD_VEX_W_0_0F92_P_2_LEN_0,
906 MOD_VEX_W_0_0F92_P_3_LEN_0,
907 MOD_VEX_W_1_0F92_P_3_LEN_0,
908 MOD_VEX_W_0_0F93_P_0_LEN_0,
909 MOD_VEX_W_0_0F93_P_2_LEN_0,
910 MOD_VEX_W_0_0F93_P_3_LEN_0,
911 MOD_VEX_W_1_0F93_P_3_LEN_0,
912 MOD_VEX_W_0_0F98_P_0_LEN_0,
913 MOD_VEX_W_1_0F98_P_0_LEN_0,
914 MOD_VEX_W_0_0F98_P_2_LEN_0,
915 MOD_VEX_W_1_0F98_P_2_LEN_0,
916 MOD_VEX_W_0_0F99_P_0_LEN_0,
917 MOD_VEX_W_1_0F99_P_0_LEN_0,
918 MOD_VEX_W_0_0F99_P_2_LEN_0,
919 MOD_VEX_W_1_0F99_P_2_LEN_0,
922 MOD_VEX_0FD7_PREFIX_2,
923 MOD_VEX_0FE7_PREFIX_2,
924 MOD_VEX_0FF0_PREFIX_3,
925 MOD_VEX_0F381A_PREFIX_2,
926 MOD_VEX_0F382A_PREFIX_2,
927 MOD_VEX_0F382C_PREFIX_2,
928 MOD_VEX_0F382D_PREFIX_2,
929 MOD_VEX_0F382E_PREFIX_2,
930 MOD_VEX_0F382F_PREFIX_2,
931 MOD_VEX_0F385A_PREFIX_2,
932 MOD_VEX_0F388C_PREFIX_2,
933 MOD_VEX_0F388E_PREFIX_2,
934 MOD_VEX_W_0_0F3A30_P_2_LEN_0,
935 MOD_VEX_W_1_0F3A30_P_2_LEN_0,
936 MOD_VEX_W_0_0F3A31_P_2_LEN_0,
937 MOD_VEX_W_1_0F3A31_P_2_LEN_0,
938 MOD_VEX_W_0_0F3A32_P_2_LEN_0,
939 MOD_VEX_W_1_0F3A32_P_2_LEN_0,
940 MOD_VEX_W_0_0F3A33_P_2_LEN_0,
941 MOD_VEX_W_1_0F3A33_P_2_LEN_0,
943 MOD_EVEX_0F10_PREFIX_1,
944 MOD_EVEX_0F10_PREFIX_3,
945 MOD_EVEX_0F11_PREFIX_1,
946 MOD_EVEX_0F11_PREFIX_3,
947 MOD_EVEX_0F12_PREFIX_0,
948 MOD_EVEX_0F16_PREFIX_0,
949 MOD_EVEX_0F38C6_REG_1,
950 MOD_EVEX_0F38C6_REG_2,
951 MOD_EVEX_0F38C6_REG_5,
952 MOD_EVEX_0F38C6_REG_6,
953 MOD_EVEX_0F38C7_REG_1,
954 MOD_EVEX_0F38C7_REG_2,
955 MOD_EVEX_0F38C7_REG_5,
956 MOD_EVEX_0F38C7_REG_6
977 PREFIX_MOD_0_0F01_REG_5,
978 PREFIX_MOD_3_0F01_REG_5_RM_0,
979 PREFIX_MOD_3_0F01_REG_5_RM_2,
1025 PREFIX_MOD_0_0FAE_REG_4,
1026 PREFIX_MOD_3_0FAE_REG_4,
1027 PREFIX_MOD_0_0FAE_REG_5,
1028 PREFIX_MOD_3_0FAE_REG_5,
1029 PREFIX_MOD_0_0FAE_REG_6,
1030 PREFIX_MOD_1_0FAE_REG_6,
1037 PREFIX_MOD_0_0FC7_REG_6,
1038 PREFIX_MOD_3_0FC7_REG_6,
1039 PREFIX_MOD_3_0FC7_REG_7,
1169 PREFIX_VEX_0F71_REG_2,
1170 PREFIX_VEX_0F71_REG_4,
1171 PREFIX_VEX_0F71_REG_6,
1172 PREFIX_VEX_0F72_REG_2,
1173 PREFIX_VEX_0F72_REG_4,
1174 PREFIX_VEX_0F72_REG_6,
1175 PREFIX_VEX_0F73_REG_2,
1176 PREFIX_VEX_0F73_REG_3,
1177 PREFIX_VEX_0F73_REG_6,
1178 PREFIX_VEX_0F73_REG_7,
1351 PREFIX_VEX_0F38F3_REG_1,
1352 PREFIX_VEX_0F38F3_REG_2,
1353 PREFIX_VEX_0F38F3_REG_3,
1472 PREFIX_EVEX_0F71_REG_2,
1473 PREFIX_EVEX_0F71_REG_4,
1474 PREFIX_EVEX_0F71_REG_6,
1475 PREFIX_EVEX_0F72_REG_0,
1476 PREFIX_EVEX_0F72_REG_1,
1477 PREFIX_EVEX_0F72_REG_2,
1478 PREFIX_EVEX_0F72_REG_4,
1479 PREFIX_EVEX_0F72_REG_6,
1480 PREFIX_EVEX_0F73_REG_2,
1481 PREFIX_EVEX_0F73_REG_3,
1482 PREFIX_EVEX_0F73_REG_6,
1483 PREFIX_EVEX_0F73_REG_7,
1679 PREFIX_EVEX_0F38C6_REG_1,
1680 PREFIX_EVEX_0F38C6_REG_2,
1681 PREFIX_EVEX_0F38C6_REG_5,
1682 PREFIX_EVEX_0F38C6_REG_6,
1683 PREFIX_EVEX_0F38C7_REG_1,
1684 PREFIX_EVEX_0F38C7_REG_2,
1685 PREFIX_EVEX_0F38C7_REG_5,
1686 PREFIX_EVEX_0F38C7_REG_6,
1788 THREE_BYTE_0F38 = 0,
1815 VEX_LEN_0F10_P_1 = 0,
1819 VEX_LEN_0F12_P_0_M_0,
1820 VEX_LEN_0F12_P_0_M_1,
1823 VEX_LEN_0F16_P_0_M_0,
1824 VEX_LEN_0F16_P_0_M_1,
1888 VEX_LEN_0FAE_R_2_M_0,
1889 VEX_LEN_0FAE_R_3_M_0,
1898 VEX_LEN_0F381A_P_2_M_0,
1901 VEX_LEN_0F385A_P_2_M_0,
1904 VEX_LEN_0F38F3_R_1_P_0,
1905 VEX_LEN_0F38F3_R_2_P_0,
1906 VEX_LEN_0F38F3_R_3_P_0,
1951 VEX_LEN_0FXOP_08_CC,
1952 VEX_LEN_0FXOP_08_CD,
1953 VEX_LEN_0FXOP_08_CE,
1954 VEX_LEN_0FXOP_08_CF,
1955 VEX_LEN_0FXOP_08_EC,
1956 VEX_LEN_0FXOP_08_ED,
1957 VEX_LEN_0FXOP_08_EE,
1958 VEX_LEN_0FXOP_08_EF,
1959 VEX_LEN_0FXOP_09_80,
1993 VEX_W_0F41_P_0_LEN_1,
1994 VEX_W_0F41_P_2_LEN_1,
1995 VEX_W_0F42_P_0_LEN_1,
1996 VEX_W_0F42_P_2_LEN_1,
1997 VEX_W_0F44_P_0_LEN_0,
1998 VEX_W_0F44_P_2_LEN_0,
1999 VEX_W_0F45_P_0_LEN_1,
2000 VEX_W_0F45_P_2_LEN_1,
2001 VEX_W_0F46_P_0_LEN_1,
2002 VEX_W_0F46_P_2_LEN_1,
2003 VEX_W_0F47_P_0_LEN_1,
2004 VEX_W_0F47_P_2_LEN_1,
2005 VEX_W_0F4A_P_0_LEN_1,
2006 VEX_W_0F4A_P_2_LEN_1,
2007 VEX_W_0F4B_P_0_LEN_1,
2008 VEX_W_0F4B_P_2_LEN_1,
2088 VEX_W_0F90_P_0_LEN_0,
2089 VEX_W_0F90_P_2_LEN_0,
2090 VEX_W_0F91_P_0_LEN_0,
2091 VEX_W_0F91_P_2_LEN_0,
2092 VEX_W_0F92_P_0_LEN_0,
2093 VEX_W_0F92_P_2_LEN_0,
2094 VEX_W_0F92_P_3_LEN_0,
2095 VEX_W_0F93_P_0_LEN_0,
2096 VEX_W_0F93_P_2_LEN_0,
2097 VEX_W_0F93_P_3_LEN_0,
2098 VEX_W_0F98_P_0_LEN_0,
2099 VEX_W_0F98_P_2_LEN_0,
2100 VEX_W_0F99_P_0_LEN_0,
2101 VEX_W_0F99_P_2_LEN_0,
2180 VEX_W_0F381A_P_2_M_0,
2192 VEX_W_0F382A_P_2_M_0,
2194 VEX_W_0F382C_P_2_M_0,
2195 VEX_W_0F382D_P_2_M_0,
2196 VEX_W_0F382E_P_2_M_0,
2197 VEX_W_0F382F_P_2_M_0,
2219 VEX_W_0F385A_P_2_M_0,
2244 VEX_W_0F3A30_P_2_LEN_0,
2245 VEX_W_0F3A31_P_2_LEN_0,
2246 VEX_W_0F3A32_P_2_LEN_0,
2247 VEX_W_0F3A33_P_2_LEN_0,
2266 EVEX_W_0F10_P_1_M_0,
2267 EVEX_W_0F10_P_1_M_1,
2269 EVEX_W_0F10_P_3_M_0,
2270 EVEX_W_0F10_P_3_M_1,
2272 EVEX_W_0F11_P_1_M_0,
2273 EVEX_W_0F11_P_1_M_1,
2275 EVEX_W_0F11_P_3_M_0,
2276 EVEX_W_0F11_P_3_M_1,
2277 EVEX_W_0F12_P_0_M_0,
2278 EVEX_W_0F12_P_0_M_1,
2288 EVEX_W_0F16_P_0_M_0,
2289 EVEX_W_0F16_P_0_M_1,
2360 EVEX_W_0F72_R_2_P_2,
2361 EVEX_W_0F72_R_6_P_2,
2362 EVEX_W_0F73_R_2_P_2,
2363 EVEX_W_0F73_R_6_P_2,
2471 EVEX_W_0F38C7_R_1_P_2,
2472 EVEX_W_0F38C7_R_2_P_2,
2473 EVEX_W_0F38C7_R_5_P_2,
2474 EVEX_W_0F38C7_R_6_P_2,
2515 typedef void (*op_rtn) (int bytemode, int sizeflag);
2524 unsigned int prefix_requirement;
2527 /* Upper case letters in the instruction names here are macros.
2528 'A' => print 'b' if no register operands or suffix_always is true
2529 'B' => print 'b' if suffix_always is true
2530 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2532 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2533 suffix_always is true
2534 'E' => print 'e' if 32-bit form of jcxz
2535 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2536 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2537 'H' => print ",pt" or ",pn" branch hint
2538 'I' => honor following macro letter even in Intel mode (implemented only
2539 for some of the macro letters)
2541 'K' => print 'd' or 'q' if rex prefix is present.
2542 'L' => print 'l' if suffix_always is true
2543 'M' => print 'r' if intel_mnemonic is false.
2544 'N' => print 'n' if instruction has no wait "prefix"
2545 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2546 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2547 or suffix_always is true. print 'q' if rex prefix is present.
2548 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2550 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2551 'S' => print 'w', 'l' or 'q' if suffix_always is true
2552 'T' => print 'q' in 64bit mode if instruction has no operand size
2553 prefix and behave as 'P' otherwise
2554 'U' => print 'q' in 64bit mode if instruction has no operand size
2555 prefix and behave as 'Q' otherwise
2556 'V' => print 'q' in 64bit mode if instruction has no operand size
2557 prefix and behave as 'S' otherwise
2558 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2559 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2561 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2562 '!' => change condition from true to false or from false to true.
2563 '%' => add 1 upper case letter to the macro.
2564 '^' => print 'w' or 'l' depending on operand size prefix or
2565 suffix_always is true (lcall/ljmp).
2566 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2567 on operand size prefix.
2568 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2569 has no operand size prefix for AMD64 ISA, behave as 'P'
2572 2 upper case letter macros:
2573 "XY" => print 'x' or 'y' if suffix_always is true or no register
2574 operands and no broadcast.
2575 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2576 register operands and no broadcast.
2577 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2578 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2579 or suffix_always is true
2580 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2581 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2582 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2583 "LW" => print 'd', 'q' depending on the VEX.W bit
2584 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2585 an operand size prefix, or suffix_always is true. print
2586 'q' if rex prefix is present.
2588 Many of the above letters print nothing in Intel mode. See "putop"
2591 Braces '{' and '}', and vertical bars '|', indicate alternative
2592 mnemonic strings for AT&T and Intel. */
2594 static const struct dis386 dis386[] = {
2596 { "addB", { Ebh1, Gb }, 0 },
2597 { "addS", { Evh1, Gv }, 0 },
2598 { "addB", { Gb, EbS }, 0 },
2599 { "addS", { Gv, EvS }, 0 },
2600 { "addB", { AL, Ib }, 0 },
2601 { "addS", { eAX, Iv }, 0 },
2602 { X86_64_TABLE (X86_64_06) },
2603 { X86_64_TABLE (X86_64_07) },
2605 { "orB", { Ebh1, Gb }, 0 },
2606 { "orS", { Evh1, Gv }, 0 },
2607 { "orB", { Gb, EbS }, 0 },
2608 { "orS", { Gv, EvS }, 0 },
2609 { "orB", { AL, Ib }, 0 },
2610 { "orS", { eAX, Iv }, 0 },
2611 { X86_64_TABLE (X86_64_0D) },
2612 { Bad_Opcode }, /* 0x0f extended opcode escape */
2614 { "adcB", { Ebh1, Gb }, 0 },
2615 { "adcS", { Evh1, Gv }, 0 },
2616 { "adcB", { Gb, EbS }, 0 },
2617 { "adcS", { Gv, EvS }, 0 },
2618 { "adcB", { AL, Ib }, 0 },
2619 { "adcS", { eAX, Iv }, 0 },
2620 { X86_64_TABLE (X86_64_16) },
2621 { X86_64_TABLE (X86_64_17) },
2623 { "sbbB", { Ebh1, Gb }, 0 },
2624 { "sbbS", { Evh1, Gv }, 0 },
2625 { "sbbB", { Gb, EbS }, 0 },
2626 { "sbbS", { Gv, EvS }, 0 },
2627 { "sbbB", { AL, Ib }, 0 },
2628 { "sbbS", { eAX, Iv }, 0 },
2629 { X86_64_TABLE (X86_64_1E) },
2630 { X86_64_TABLE (X86_64_1F) },
2632 { "andB", { Ebh1, Gb }, 0 },
2633 { "andS", { Evh1, Gv }, 0 },
2634 { "andB", { Gb, EbS }, 0 },
2635 { "andS", { Gv, EvS }, 0 },
2636 { "andB", { AL, Ib }, 0 },
2637 { "andS", { eAX, Iv }, 0 },
2638 { Bad_Opcode }, /* SEG ES prefix */
2639 { X86_64_TABLE (X86_64_27) },
2641 { "subB", { Ebh1, Gb }, 0 },
2642 { "subS", { Evh1, Gv }, 0 },
2643 { "subB", { Gb, EbS }, 0 },
2644 { "subS", { Gv, EvS }, 0 },
2645 { "subB", { AL, Ib }, 0 },
2646 { "subS", { eAX, Iv }, 0 },
2647 { Bad_Opcode }, /* SEG CS prefix */
2648 { X86_64_TABLE (X86_64_2F) },
2650 { "xorB", { Ebh1, Gb }, 0 },
2651 { "xorS", { Evh1, Gv }, 0 },
2652 { "xorB", { Gb, EbS }, 0 },
2653 { "xorS", { Gv, EvS }, 0 },
2654 { "xorB", { AL, Ib }, 0 },
2655 { "xorS", { eAX, Iv }, 0 },
2656 { Bad_Opcode }, /* SEG SS prefix */
2657 { X86_64_TABLE (X86_64_37) },
2659 { "cmpB", { Eb, Gb }, 0 },
2660 { "cmpS", { Ev, Gv }, 0 },
2661 { "cmpB", { Gb, EbS }, 0 },
2662 { "cmpS", { Gv, EvS }, 0 },
2663 { "cmpB", { AL, Ib }, 0 },
2664 { "cmpS", { eAX, Iv }, 0 },
2665 { Bad_Opcode }, /* SEG DS prefix */
2666 { X86_64_TABLE (X86_64_3F) },
2668 { "inc{S|}", { RMeAX }, 0 },
2669 { "inc{S|}", { RMeCX }, 0 },
2670 { "inc{S|}", { RMeDX }, 0 },
2671 { "inc{S|}", { RMeBX }, 0 },
2672 { "inc{S|}", { RMeSP }, 0 },
2673 { "inc{S|}", { RMeBP }, 0 },
2674 { "inc{S|}", { RMeSI }, 0 },
2675 { "inc{S|}", { RMeDI }, 0 },
2677 { "dec{S|}", { RMeAX }, 0 },
2678 { "dec{S|}", { RMeCX }, 0 },
2679 { "dec{S|}", { RMeDX }, 0 },
2680 { "dec{S|}", { RMeBX }, 0 },
2681 { "dec{S|}", { RMeSP }, 0 },
2682 { "dec{S|}", { RMeBP }, 0 },
2683 { "dec{S|}", { RMeSI }, 0 },
2684 { "dec{S|}", { RMeDI }, 0 },
2686 { "pushV", { RMrAX }, 0 },
2687 { "pushV", { RMrCX }, 0 },
2688 { "pushV", { RMrDX }, 0 },
2689 { "pushV", { RMrBX }, 0 },
2690 { "pushV", { RMrSP }, 0 },
2691 { "pushV", { RMrBP }, 0 },
2692 { "pushV", { RMrSI }, 0 },
2693 { "pushV", { RMrDI }, 0 },
2695 { "popV", { RMrAX }, 0 },
2696 { "popV", { RMrCX }, 0 },
2697 { "popV", { RMrDX }, 0 },
2698 { "popV", { RMrBX }, 0 },
2699 { "popV", { RMrSP }, 0 },
2700 { "popV", { RMrBP }, 0 },
2701 { "popV", { RMrSI }, 0 },
2702 { "popV", { RMrDI }, 0 },
2704 { X86_64_TABLE (X86_64_60) },
2705 { X86_64_TABLE (X86_64_61) },
2706 { X86_64_TABLE (X86_64_62) },
2707 { X86_64_TABLE (X86_64_63) },
2708 { Bad_Opcode }, /* seg fs */
2709 { Bad_Opcode }, /* seg gs */
2710 { Bad_Opcode }, /* op size prefix */
2711 { Bad_Opcode }, /* adr size prefix */
2713 { "pushT", { sIv }, 0 },
2714 { "imulS", { Gv, Ev, Iv }, 0 },
2715 { "pushT", { sIbT }, 0 },
2716 { "imulS", { Gv, Ev, sIb }, 0 },
2717 { "ins{b|}", { Ybr, indirDX }, 0 },
2718 { X86_64_TABLE (X86_64_6D) },
2719 { "outs{b|}", { indirDXr, Xb }, 0 },
2720 { X86_64_TABLE (X86_64_6F) },
2722 { "joH", { Jb, BND, cond_jump_flag }, 0 },
2723 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
2724 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
2725 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
2726 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
2727 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
2728 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
2729 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
2731 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
2732 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
2733 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
2734 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
2735 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
2736 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
2737 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
2738 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
2740 { REG_TABLE (REG_80) },
2741 { REG_TABLE (REG_81) },
2742 { X86_64_TABLE (X86_64_82) },
2743 { REG_TABLE (REG_83) },
2744 { "testB", { Eb, Gb }, 0 },
2745 { "testS", { Ev, Gv }, 0 },
2746 { "xchgB", { Ebh2, Gb }, 0 },
2747 { "xchgS", { Evh2, Gv }, 0 },
2749 { "movB", { Ebh3, Gb }, 0 },
2750 { "movS", { Evh3, Gv }, 0 },
2751 { "movB", { Gb, EbS }, 0 },
2752 { "movS", { Gv, EvS }, 0 },
2753 { "movD", { Sv, Sw }, 0 },
2754 { MOD_TABLE (MOD_8D) },
2755 { "movD", { Sw, Sv }, 0 },
2756 { REG_TABLE (REG_8F) },
2758 { PREFIX_TABLE (PREFIX_90) },
2759 { "xchgS", { RMeCX, eAX }, 0 },
2760 { "xchgS", { RMeDX, eAX }, 0 },
2761 { "xchgS", { RMeBX, eAX }, 0 },
2762 { "xchgS", { RMeSP, eAX }, 0 },
2763 { "xchgS", { RMeBP, eAX }, 0 },
2764 { "xchgS", { RMeSI, eAX }, 0 },
2765 { "xchgS", { RMeDI, eAX }, 0 },
2767 { "cW{t|}R", { XX }, 0 },
2768 { "cR{t|}O", { XX }, 0 },
2769 { X86_64_TABLE (X86_64_9A) },
2770 { Bad_Opcode }, /* fwait */
2771 { "pushfT", { XX }, 0 },
2772 { "popfT", { XX }, 0 },
2773 { "sahf", { XX }, 0 },
2774 { "lahf", { XX }, 0 },
2776 { "mov%LB", { AL, Ob }, 0 },
2777 { "mov%LS", { eAX, Ov }, 0 },
2778 { "mov%LB", { Ob, AL }, 0 },
2779 { "mov%LS", { Ov, eAX }, 0 },
2780 { "movs{b|}", { Ybr, Xb }, 0 },
2781 { "movs{R|}", { Yvr, Xv }, 0 },
2782 { "cmps{b|}", { Xb, Yb }, 0 },
2783 { "cmps{R|}", { Xv, Yv }, 0 },
2785 { "testB", { AL, Ib }, 0 },
2786 { "testS", { eAX, Iv }, 0 },
2787 { "stosB", { Ybr, AL }, 0 },
2788 { "stosS", { Yvr, eAX }, 0 },
2789 { "lodsB", { ALr, Xb }, 0 },
2790 { "lodsS", { eAXr, Xv }, 0 },
2791 { "scasB", { AL, Yb }, 0 },
2792 { "scasS", { eAX, Yv }, 0 },
2794 { "movB", { RMAL, Ib }, 0 },
2795 { "movB", { RMCL, Ib }, 0 },
2796 { "movB", { RMDL, Ib }, 0 },
2797 { "movB", { RMBL, Ib }, 0 },
2798 { "movB", { RMAH, Ib }, 0 },
2799 { "movB", { RMCH, Ib }, 0 },
2800 { "movB", { RMDH, Ib }, 0 },
2801 { "movB", { RMBH, Ib }, 0 },
2803 { "mov%LV", { RMeAX, Iv64 }, 0 },
2804 { "mov%LV", { RMeCX, Iv64 }, 0 },
2805 { "mov%LV", { RMeDX, Iv64 }, 0 },
2806 { "mov%LV", { RMeBX, Iv64 }, 0 },
2807 { "mov%LV", { RMeSP, Iv64 }, 0 },
2808 { "mov%LV", { RMeBP, Iv64 }, 0 },
2809 { "mov%LV", { RMeSI, Iv64 }, 0 },
2810 { "mov%LV", { RMeDI, Iv64 }, 0 },
2812 { REG_TABLE (REG_C0) },
2813 { REG_TABLE (REG_C1) },
2814 { "retT", { Iw, BND }, 0 },
2815 { "retT", { BND }, 0 },
2816 { X86_64_TABLE (X86_64_C4) },
2817 { X86_64_TABLE (X86_64_C5) },
2818 { REG_TABLE (REG_C6) },
2819 { REG_TABLE (REG_C7) },
2821 { "enterT", { Iw, Ib }, 0 },
2822 { "leaveT", { XX }, 0 },
2823 { "Jret{|f}P", { Iw }, 0 },
2824 { "Jret{|f}P", { XX }, 0 },
2825 { "int3", { XX }, 0 },
2826 { "int", { Ib }, 0 },
2827 { X86_64_TABLE (X86_64_CE) },
2828 { "iret%LP", { XX }, 0 },
2830 { REG_TABLE (REG_D0) },
2831 { REG_TABLE (REG_D1) },
2832 { REG_TABLE (REG_D2) },
2833 { REG_TABLE (REG_D3) },
2834 { X86_64_TABLE (X86_64_D4) },
2835 { X86_64_TABLE (X86_64_D5) },
2837 { "xlat", { DSBX }, 0 },
2848 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2849 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2850 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2851 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2852 { "inB", { AL, Ib }, 0 },
2853 { "inG", { zAX, Ib }, 0 },
2854 { "outB", { Ib, AL }, 0 },
2855 { "outG", { Ib, zAX }, 0 },
2857 { X86_64_TABLE (X86_64_E8) },
2858 { X86_64_TABLE (X86_64_E9) },
2859 { X86_64_TABLE (X86_64_EA) },
2860 { "jmp", { Jb, BND }, 0 },
2861 { "inB", { AL, indirDX }, 0 },
2862 { "inG", { zAX, indirDX }, 0 },
2863 { "outB", { indirDX, AL }, 0 },
2864 { "outG", { indirDX, zAX }, 0 },
2866 { Bad_Opcode }, /* lock prefix */
2867 { "icebp", { XX }, 0 },
2868 { Bad_Opcode }, /* repne */
2869 { Bad_Opcode }, /* repz */
2870 { "hlt", { XX }, 0 },
2871 { "cmc", { XX }, 0 },
2872 { REG_TABLE (REG_F6) },
2873 { REG_TABLE (REG_F7) },
2875 { "clc", { XX }, 0 },
2876 { "stc", { XX }, 0 },
2877 { "cli", { XX }, 0 },
2878 { "sti", { XX }, 0 },
2879 { "cld", { XX }, 0 },
2880 { "std", { XX }, 0 },
2881 { REG_TABLE (REG_FE) },
2882 { REG_TABLE (REG_FF) },
2885 static const struct dis386 dis386_twobyte[] = {
2887 { REG_TABLE (REG_0F00 ) },
2888 { REG_TABLE (REG_0F01 ) },
2889 { "larS", { Gv, Ew }, 0 },
2890 { "lslS", { Gv, Ew }, 0 },
2892 { "syscall", { XX }, 0 },
2893 { "clts", { XX }, 0 },
2894 { "sysret%LP", { XX }, 0 },
2896 { "invd", { XX }, 0 },
2897 { PREFIX_TABLE (PREFIX_0F09) },
2899 { "ud2", { XX }, 0 },
2901 { REG_TABLE (REG_0F0D) },
2902 { "femms", { XX }, 0 },
2903 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2905 { PREFIX_TABLE (PREFIX_0F10) },
2906 { PREFIX_TABLE (PREFIX_0F11) },
2907 { PREFIX_TABLE (PREFIX_0F12) },
2908 { MOD_TABLE (MOD_0F13) },
2909 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2910 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2911 { PREFIX_TABLE (PREFIX_0F16) },
2912 { MOD_TABLE (MOD_0F17) },
2914 { REG_TABLE (REG_0F18) },
2915 { "nopQ", { Ev }, 0 },
2916 { PREFIX_TABLE (PREFIX_0F1A) },
2917 { PREFIX_TABLE (PREFIX_0F1B) },
2918 { PREFIX_TABLE (PREFIX_0F1C) },
2919 { "nopQ", { Ev }, 0 },
2920 { PREFIX_TABLE (PREFIX_0F1E) },
2921 { "nopQ", { Ev }, 0 },
2923 { "movZ", { Rm, Cm }, 0 },
2924 { "movZ", { Rm, Dm }, 0 },
2925 { "movZ", { Cm, Rm }, 0 },
2926 { "movZ", { Dm, Rm }, 0 },
2927 { MOD_TABLE (MOD_0F24) },
2929 { MOD_TABLE (MOD_0F26) },
2932 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2933 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2934 { PREFIX_TABLE (PREFIX_0F2A) },
2935 { PREFIX_TABLE (PREFIX_0F2B) },
2936 { PREFIX_TABLE (PREFIX_0F2C) },
2937 { PREFIX_TABLE (PREFIX_0F2D) },
2938 { PREFIX_TABLE (PREFIX_0F2E) },
2939 { PREFIX_TABLE (PREFIX_0F2F) },
2941 { "wrmsr", { XX }, 0 },
2942 { "rdtsc", { XX }, 0 },
2943 { "rdmsr", { XX }, 0 },
2944 { "rdpmc", { XX }, 0 },
2945 { "sysenter", { XX }, 0 },
2946 { "sysexit", { XX }, 0 },
2948 { "getsec", { XX }, 0 },
2950 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2952 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2959 { "cmovoS", { Gv, Ev }, 0 },
2960 { "cmovnoS", { Gv, Ev }, 0 },
2961 { "cmovbS", { Gv, Ev }, 0 },
2962 { "cmovaeS", { Gv, Ev }, 0 },
2963 { "cmoveS", { Gv, Ev }, 0 },
2964 { "cmovneS", { Gv, Ev }, 0 },
2965 { "cmovbeS", { Gv, Ev }, 0 },
2966 { "cmovaS", { Gv, Ev }, 0 },
2968 { "cmovsS", { Gv, Ev }, 0 },
2969 { "cmovnsS", { Gv, Ev }, 0 },
2970 { "cmovpS", { Gv, Ev }, 0 },
2971 { "cmovnpS", { Gv, Ev }, 0 },
2972 { "cmovlS", { Gv, Ev }, 0 },
2973 { "cmovgeS", { Gv, Ev }, 0 },
2974 { "cmovleS", { Gv, Ev }, 0 },
2975 { "cmovgS", { Gv, Ev }, 0 },
2977 { MOD_TABLE (MOD_0F51) },
2978 { PREFIX_TABLE (PREFIX_0F51) },
2979 { PREFIX_TABLE (PREFIX_0F52) },
2980 { PREFIX_TABLE (PREFIX_0F53) },
2981 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2982 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2983 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2984 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2986 { PREFIX_TABLE (PREFIX_0F58) },
2987 { PREFIX_TABLE (PREFIX_0F59) },
2988 { PREFIX_TABLE (PREFIX_0F5A) },
2989 { PREFIX_TABLE (PREFIX_0F5B) },
2990 { PREFIX_TABLE (PREFIX_0F5C) },
2991 { PREFIX_TABLE (PREFIX_0F5D) },
2992 { PREFIX_TABLE (PREFIX_0F5E) },
2993 { PREFIX_TABLE (PREFIX_0F5F) },
2995 { PREFIX_TABLE (PREFIX_0F60) },
2996 { PREFIX_TABLE (PREFIX_0F61) },
2997 { PREFIX_TABLE (PREFIX_0F62) },
2998 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2999 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
3000 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
3001 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
3002 { "packuswb", { MX, EM }, PREFIX_OPCODE },
3004 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
3005 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
3006 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
3007 { "packssdw", { MX, EM }, PREFIX_OPCODE },
3008 { PREFIX_TABLE (PREFIX_0F6C) },
3009 { PREFIX_TABLE (PREFIX_0F6D) },
3010 { "movK", { MX, Edq }, PREFIX_OPCODE },
3011 { PREFIX_TABLE (PREFIX_0F6F) },
3013 { PREFIX_TABLE (PREFIX_0F70) },
3014 { REG_TABLE (REG_0F71) },
3015 { REG_TABLE (REG_0F72) },
3016 { REG_TABLE (REG_0F73) },
3017 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
3018 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
3019 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
3020 { "emms", { XX }, PREFIX_OPCODE },
3022 { PREFIX_TABLE (PREFIX_0F78) },
3023 { PREFIX_TABLE (PREFIX_0F79) },
3026 { PREFIX_TABLE (PREFIX_0F7C) },
3027 { PREFIX_TABLE (PREFIX_0F7D) },
3028 { PREFIX_TABLE (PREFIX_0F7E) },
3029 { PREFIX_TABLE (PREFIX_0F7F) },
3031 { "joH", { Jv, BND, cond_jump_flag }, 0 },
3032 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
3033 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
3034 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
3035 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
3036 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
3037 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
3038 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
3040 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
3041 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
3042 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
3043 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
3044 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
3045 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
3046 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
3047 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
3049 { "seto", { Eb }, 0 },
3050 { "setno", { Eb }, 0 },
3051 { "setb", { Eb }, 0 },
3052 { "setae", { Eb }, 0 },
3053 { "sete", { Eb }, 0 },
3054 { "setne", { Eb }, 0 },
3055 { "setbe", { Eb }, 0 },
3056 { "seta", { Eb }, 0 },
3058 { "sets", { Eb }, 0 },
3059 { "setns", { Eb }, 0 },
3060 { "setp", { Eb }, 0 },
3061 { "setnp", { Eb }, 0 },
3062 { "setl", { Eb }, 0 },
3063 { "setge", { Eb }, 0 },
3064 { "setle", { Eb }, 0 },
3065 { "setg", { Eb }, 0 },
3067 { "pushT", { fs }, 0 },
3068 { "popT", { fs }, 0 },
3069 { "cpuid", { XX }, 0 },
3070 { "btS", { Ev, Gv }, 0 },
3071 { "shldS", { Ev, Gv, Ib }, 0 },
3072 { "shldS", { Ev, Gv, CL }, 0 },
3073 { REG_TABLE (REG_0FA6) },
3074 { REG_TABLE (REG_0FA7) },
3076 { "pushT", { gs }, 0 },
3077 { "popT", { gs }, 0 },
3078 { "rsm", { XX }, 0 },
3079 { "btsS", { Evh1, Gv }, 0 },
3080 { "shrdS", { Ev, Gv, Ib }, 0 },
3081 { "shrdS", { Ev, Gv, CL }, 0 },
3082 { REG_TABLE (REG_0FAE) },
3083 { "imulS", { Gv, Ev }, 0 },
3085 { "cmpxchgB", { Ebh1, Gb }, 0 },
3086 { "cmpxchgS", { Evh1, Gv }, 0 },
3087 { MOD_TABLE (MOD_0FB2) },
3088 { "btrS", { Evh1, Gv }, 0 },
3089 { MOD_TABLE (MOD_0FB4) },
3090 { MOD_TABLE (MOD_0FB5) },
3091 { "movz{bR|x}", { Gv, Eb }, 0 },
3092 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3094 { PREFIX_TABLE (PREFIX_0FB8) },
3095 { "ud1S", { Gv, Ev }, 0 },
3096 { REG_TABLE (REG_0FBA) },
3097 { "btcS", { Evh1, Gv }, 0 },
3098 { PREFIX_TABLE (PREFIX_0FBC) },
3099 { PREFIX_TABLE (PREFIX_0FBD) },
3100 { "movs{bR|x}", { Gv, Eb }, 0 },
3101 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3103 { "xaddB", { Ebh1, Gb }, 0 },
3104 { "xaddS", { Evh1, Gv }, 0 },
3105 { PREFIX_TABLE (PREFIX_0FC2) },
3106 { MOD_TABLE (MOD_0FC3) },
3107 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
3108 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
3109 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
3110 { REG_TABLE (REG_0FC7) },
3112 { "bswap", { RMeAX }, 0 },
3113 { "bswap", { RMeCX }, 0 },
3114 { "bswap", { RMeDX }, 0 },
3115 { "bswap", { RMeBX }, 0 },
3116 { "bswap", { RMeSP }, 0 },
3117 { "bswap", { RMeBP }, 0 },
3118 { "bswap", { RMeSI }, 0 },
3119 { "bswap", { RMeDI }, 0 },
3121 { PREFIX_TABLE (PREFIX_0FD0) },
3122 { "psrlw", { MX, EM }, PREFIX_OPCODE },
3123 { "psrld", { MX, EM }, PREFIX_OPCODE },
3124 { "psrlq", { MX, EM }, PREFIX_OPCODE },
3125 { "paddq", { MX, EM }, PREFIX_OPCODE },
3126 { "pmullw", { MX, EM }, PREFIX_OPCODE },
3127 { PREFIX_TABLE (PREFIX_0FD6) },
3128 { MOD_TABLE (MOD_0FD7) },
3130 { "psubusb", { MX, EM }, PREFIX_OPCODE },
3131 { "psubusw", { MX, EM }, PREFIX_OPCODE },
3132 { "pminub", { MX, EM }, PREFIX_OPCODE },
3133 { "pand", { MX, EM }, PREFIX_OPCODE },
3134 { "paddusb", { MX, EM }, PREFIX_OPCODE },
3135 { "paddusw", { MX, EM }, PREFIX_OPCODE },
3136 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
3137 { "pandn", { MX, EM }, PREFIX_OPCODE },
3139 { "pavgb", { MX, EM }, PREFIX_OPCODE },
3140 { "psraw", { MX, EM }, PREFIX_OPCODE },
3141 { "psrad", { MX, EM }, PREFIX_OPCODE },
3142 { "pavgw", { MX, EM }, PREFIX_OPCODE },
3143 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
3144 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
3145 { PREFIX_TABLE (PREFIX_0FE6) },
3146 { PREFIX_TABLE (PREFIX_0FE7) },
3148 { "psubsb", { MX, EM }, PREFIX_OPCODE },
3149 { "psubsw", { MX, EM }, PREFIX_OPCODE },
3150 { "pminsw", { MX, EM }, PREFIX_OPCODE },
3151 { "por", { MX, EM }, PREFIX_OPCODE },
3152 { "paddsb", { MX, EM }, PREFIX_OPCODE },
3153 { "paddsw", { MX, EM }, PREFIX_OPCODE },
3154 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
3155 { "pxor", { MX, EM }, PREFIX_OPCODE },
3157 { PREFIX_TABLE (PREFIX_0FF0) },
3158 { "psllw", { MX, EM }, PREFIX_OPCODE },
3159 { "pslld", { MX, EM }, PREFIX_OPCODE },
3160 { "psllq", { MX, EM }, PREFIX_OPCODE },
3161 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
3162 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
3163 { "psadbw", { MX, EM }, PREFIX_OPCODE },
3164 { PREFIX_TABLE (PREFIX_0FF7) },
3166 { "psubb", { MX, EM }, PREFIX_OPCODE },
3167 { "psubw", { MX, EM }, PREFIX_OPCODE },
3168 { "psubd", { MX, EM }, PREFIX_OPCODE },
3169 { "psubq", { MX, EM }, PREFIX_OPCODE },
3170 { "paddb", { MX, EM }, PREFIX_OPCODE },
3171 { "paddw", { MX, EM }, PREFIX_OPCODE },
3172 { "paddd", { MX, EM }, PREFIX_OPCODE },
3173 { "ud0S", { Gv, Ev }, 0 },
3176 static const unsigned char onebyte_has_modrm[256] = {
3177 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3178 /* ------------------------------- */
3179 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3180 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3181 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3182 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3183 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3184 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3185 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3186 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3187 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3188 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3189 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3190 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3191 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3192 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3193 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3194 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3195 /* ------------------------------- */
3196 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3199 static const unsigned char twobyte_has_modrm[256] = {
3200 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3201 /* ------------------------------- */
3202 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3203 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3204 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3205 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3206 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3207 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3208 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3209 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3210 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3211 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3212 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3213 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
3214 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3215 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3216 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3217 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
3218 /* ------------------------------- */
3219 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3222 static char obuf[100];
3224 static char *mnemonicendp;
3225 static char scratchbuf[100];
3226 static unsigned char *start_codep;
3227 static unsigned char *insn_codep;
3228 static unsigned char *codep;
3229 static unsigned char *end_codep;
3230 static int last_lock_prefix;
3231 static int last_repz_prefix;
3232 static int last_repnz_prefix;
3233 static int last_data_prefix;
3234 static int last_addr_prefix;
3235 static int last_rex_prefix;
3236 static int last_seg_prefix;
3237 static int fwait_prefix;
3238 /* The active segment register prefix. */
3239 static int active_seg_prefix;
3240 #define MAX_CODE_LENGTH 15
3241 /* We can up to 14 prefixes since the maximum instruction length is
3243 static int all_prefixes[MAX_CODE_LENGTH - 1];
3244 static disassemble_info *the_info;
3252 static unsigned char need_modrm;
3262 int register_specifier;
3269 int mask_register_specifier;
3275 static unsigned char need_vex;
3276 static unsigned char need_vex_reg;
3277 static unsigned char vex_w_done;
3285 /* If we are accessing mod/rm/reg without need_modrm set, then the
3286 values are stale. Hitting this abort likely indicates that you
3287 need to update onebyte_has_modrm or twobyte_has_modrm. */
3288 #define MODRM_CHECK if (!need_modrm) abort ()
3290 static const char **names64;
3291 static const char **names32;
3292 static const char **names16;
3293 static const char **names8;
3294 static const char **names8rex;
3295 static const char **names_seg;
3296 static const char *index64;
3297 static const char *index32;
3298 static const char **index16;
3299 static const char **names_bnd;
3301 static const char *intel_names64[] = {
3302 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3303 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3305 static const char *intel_names32[] = {
3306 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3307 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3309 static const char *intel_names16[] = {
3310 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3311 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3313 static const char *intel_names8[] = {
3314 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3316 static const char *intel_names8rex[] = {
3317 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3318 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3320 static const char *intel_names_seg[] = {
3321 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3323 static const char *intel_index64 = "riz";
3324 static const char *intel_index32 = "eiz";
3325 static const char *intel_index16[] = {
3326 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3329 static const char *att_names64[] = {
3330 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3331 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3333 static const char *att_names32[] = {
3334 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3335 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3337 static const char *att_names16[] = {
3338 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3339 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3341 static const char *att_names8[] = {
3342 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3344 static const char *att_names8rex[] = {
3345 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3346 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3348 static const char *att_names_seg[] = {
3349 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3351 static const char *att_index64 = "%riz";
3352 static const char *att_index32 = "%eiz";
3353 static const char *att_index16[] = {
3354 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3357 static const char **names_mm;
3358 static const char *intel_names_mm[] = {
3359 "mm0", "mm1", "mm2", "mm3",
3360 "mm4", "mm5", "mm6", "mm7"
3362 static const char *att_names_mm[] = {
3363 "%mm0", "%mm1", "%mm2", "%mm3",
3364 "%mm4", "%mm5", "%mm6", "%mm7"
3367 static const char *intel_names_bnd[] = {
3368 "bnd0", "bnd1", "bnd2", "bnd3"
3371 static const char *att_names_bnd[] = {
3372 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3375 static const char **names_xmm;
3376 static const char *intel_names_xmm[] = {
3377 "xmm0", "xmm1", "xmm2", "xmm3",
3378 "xmm4", "xmm5", "xmm6", "xmm7",
3379 "xmm8", "xmm9", "xmm10", "xmm11",
3380 "xmm12", "xmm13", "xmm14", "xmm15",
3381 "xmm16", "xmm17", "xmm18", "xmm19",
3382 "xmm20", "xmm21", "xmm22", "xmm23",
3383 "xmm24", "xmm25", "xmm26", "xmm27",
3384 "xmm28", "xmm29", "xmm30", "xmm31"
3386 static const char *att_names_xmm[] = {
3387 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3388 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3389 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3390 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3391 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3392 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3393 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3394 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3397 static const char **names_ymm;
3398 static const char *intel_names_ymm[] = {
3399 "ymm0", "ymm1", "ymm2", "ymm3",
3400 "ymm4", "ymm5", "ymm6", "ymm7",
3401 "ymm8", "ymm9", "ymm10", "ymm11",
3402 "ymm12", "ymm13", "ymm14", "ymm15",
3403 "ymm16", "ymm17", "ymm18", "ymm19",
3404 "ymm20", "ymm21", "ymm22", "ymm23",
3405 "ymm24", "ymm25", "ymm26", "ymm27",
3406 "ymm28", "ymm29", "ymm30", "ymm31"
3408 static const char *att_names_ymm[] = {
3409 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3410 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3411 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3412 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3413 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3414 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3415 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3416 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3419 static const char **names_zmm;
3420 static const char *intel_names_zmm[] = {
3421 "zmm0", "zmm1", "zmm2", "zmm3",
3422 "zmm4", "zmm5", "zmm6", "zmm7",
3423 "zmm8", "zmm9", "zmm10", "zmm11",
3424 "zmm12", "zmm13", "zmm14", "zmm15",
3425 "zmm16", "zmm17", "zmm18", "zmm19",
3426 "zmm20", "zmm21", "zmm22", "zmm23",
3427 "zmm24", "zmm25", "zmm26", "zmm27",
3428 "zmm28", "zmm29", "zmm30", "zmm31"
3430 static const char *att_names_zmm[] = {
3431 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3432 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3433 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3434 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3435 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3436 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3437 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3438 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3441 static const char **names_mask;
3442 static const char *intel_names_mask[] = {
3443 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3445 static const char *att_names_mask[] = {
3446 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3449 static const char *names_rounding[] =
3457 static const struct dis386 reg_table[][8] = {
3460 { "addA", { Ebh1, Ib }, 0 },
3461 { "orA", { Ebh1, Ib }, 0 },
3462 { "adcA", { Ebh1, Ib }, 0 },
3463 { "sbbA", { Ebh1, Ib }, 0 },
3464 { "andA", { Ebh1, Ib }, 0 },
3465 { "subA", { Ebh1, Ib }, 0 },
3466 { "xorA", { Ebh1, Ib }, 0 },
3467 { "cmpA", { Eb, Ib }, 0 },
3471 { "addQ", { Evh1, Iv }, 0 },
3472 { "orQ", { Evh1, Iv }, 0 },
3473 { "adcQ", { Evh1, Iv }, 0 },
3474 { "sbbQ", { Evh1, Iv }, 0 },
3475 { "andQ", { Evh1, Iv }, 0 },
3476 { "subQ", { Evh1, Iv }, 0 },
3477 { "xorQ", { Evh1, Iv }, 0 },
3478 { "cmpQ", { Ev, Iv }, 0 },
3482 { "addQ", { Evh1, sIb }, 0 },
3483 { "orQ", { Evh1, sIb }, 0 },
3484 { "adcQ", { Evh1, sIb }, 0 },
3485 { "sbbQ", { Evh1, sIb }, 0 },
3486 { "andQ", { Evh1, sIb }, 0 },
3487 { "subQ", { Evh1, sIb }, 0 },
3488 { "xorQ", { Evh1, sIb }, 0 },
3489 { "cmpQ", { Ev, sIb }, 0 },
3493 { "popU", { stackEv }, 0 },
3494 { XOP_8F_TABLE (XOP_09) },
3498 { XOP_8F_TABLE (XOP_09) },
3502 { "rolA", { Eb, Ib }, 0 },
3503 { "rorA", { Eb, Ib }, 0 },
3504 { "rclA", { Eb, Ib }, 0 },
3505 { "rcrA", { Eb, Ib }, 0 },
3506 { "shlA", { Eb, Ib }, 0 },
3507 { "shrA", { Eb, Ib }, 0 },
3508 { "shlA", { Eb, Ib }, 0 },
3509 { "sarA", { Eb, Ib }, 0 },
3513 { "rolQ", { Ev, Ib }, 0 },
3514 { "rorQ", { Ev, Ib }, 0 },
3515 { "rclQ", { Ev, Ib }, 0 },
3516 { "rcrQ", { Ev, Ib }, 0 },
3517 { "shlQ", { Ev, Ib }, 0 },
3518 { "shrQ", { Ev, Ib }, 0 },
3519 { "shlQ", { Ev, Ib }, 0 },
3520 { "sarQ", { Ev, Ib }, 0 },
3524 { "movA", { Ebh3, Ib }, 0 },
3531 { MOD_TABLE (MOD_C6_REG_7) },
3535 { "movQ", { Evh3, Iv }, 0 },
3542 { MOD_TABLE (MOD_C7_REG_7) },
3546 { "rolA", { Eb, I1 }, 0 },
3547 { "rorA", { Eb, I1 }, 0 },
3548 { "rclA", { Eb, I1 }, 0 },
3549 { "rcrA", { Eb, I1 }, 0 },
3550 { "shlA", { Eb, I1 }, 0 },
3551 { "shrA", { Eb, I1 }, 0 },
3552 { "shlA", { Eb, I1 }, 0 },
3553 { "sarA", { Eb, I1 }, 0 },
3557 { "rolQ", { Ev, I1 }, 0 },
3558 { "rorQ", { Ev, I1 }, 0 },
3559 { "rclQ", { Ev, I1 }, 0 },
3560 { "rcrQ", { Ev, I1 }, 0 },
3561 { "shlQ", { Ev, I1 }, 0 },
3562 { "shrQ", { Ev, I1 }, 0 },
3563 { "shlQ", { Ev, I1 }, 0 },
3564 { "sarQ", { Ev, I1 }, 0 },
3568 { "rolA", { Eb, CL }, 0 },
3569 { "rorA", { Eb, CL }, 0 },
3570 { "rclA", { Eb, CL }, 0 },
3571 { "rcrA", { Eb, CL }, 0 },
3572 { "shlA", { Eb, CL }, 0 },
3573 { "shrA", { Eb, CL }, 0 },
3574 { "shlA", { Eb, CL }, 0 },
3575 { "sarA", { Eb, CL }, 0 },
3579 { "rolQ", { Ev, CL }, 0 },
3580 { "rorQ", { Ev, CL }, 0 },
3581 { "rclQ", { Ev, CL }, 0 },
3582 { "rcrQ", { Ev, CL }, 0 },
3583 { "shlQ", { Ev, CL }, 0 },
3584 { "shrQ", { Ev, CL }, 0 },
3585 { "shlQ", { Ev, CL }, 0 },
3586 { "sarQ", { Ev, CL }, 0 },
3590 { "testA", { Eb, Ib }, 0 },
3591 { "testA", { Eb, Ib }, 0 },
3592 { "notA", { Ebh1 }, 0 },
3593 { "negA", { Ebh1 }, 0 },
3594 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
3595 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
3596 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
3597 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
3601 { "testQ", { Ev, Iv }, 0 },
3602 { "testQ", { Ev, Iv }, 0 },
3603 { "notQ", { Evh1 }, 0 },
3604 { "negQ", { Evh1 }, 0 },
3605 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
3606 { "imulQ", { Ev }, 0 },
3607 { "divQ", { Ev }, 0 },
3608 { "idivQ", { Ev }, 0 },
3612 { "incA", { Ebh1 }, 0 },
3613 { "decA", { Ebh1 }, 0 },
3617 { "incQ", { Evh1 }, 0 },
3618 { "decQ", { Evh1 }, 0 },
3619 { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3620 { MOD_TABLE (MOD_FF_REG_3) },
3621 { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3622 { MOD_TABLE (MOD_FF_REG_5) },
3623 { "pushU", { stackEv }, 0 },
3628 { "sldtD", { Sv }, 0 },
3629 { "strD", { Sv }, 0 },
3630 { "lldt", { Ew }, 0 },
3631 { "ltr", { Ew }, 0 },
3632 { "verr", { Ew }, 0 },
3633 { "verw", { Ew }, 0 },
3639 { MOD_TABLE (MOD_0F01_REG_0) },
3640 { MOD_TABLE (MOD_0F01_REG_1) },
3641 { MOD_TABLE (MOD_0F01_REG_2) },
3642 { MOD_TABLE (MOD_0F01_REG_3) },
3643 { "smswD", { Sv }, 0 },
3644 { MOD_TABLE (MOD_0F01_REG_5) },
3645 { "lmsw", { Ew }, 0 },
3646 { MOD_TABLE (MOD_0F01_REG_7) },
3650 { "prefetch", { Mb }, 0 },
3651 { "prefetchw", { Mb }, 0 },
3652 { "prefetchwt1", { Mb }, 0 },
3653 { "prefetch", { Mb }, 0 },
3654 { "prefetch", { Mb }, 0 },
3655 { "prefetch", { Mb }, 0 },
3656 { "prefetch", { Mb }, 0 },
3657 { "prefetch", { Mb }, 0 },
3661 { MOD_TABLE (MOD_0F18_REG_0) },
3662 { MOD_TABLE (MOD_0F18_REG_1) },
3663 { MOD_TABLE (MOD_0F18_REG_2) },
3664 { MOD_TABLE (MOD_0F18_REG_3) },
3665 { MOD_TABLE (MOD_0F18_REG_4) },
3666 { MOD_TABLE (MOD_0F18_REG_5) },
3667 { MOD_TABLE (MOD_0F18_REG_6) },
3668 { MOD_TABLE (MOD_0F18_REG_7) },
3670 /* REG_0F1C_MOD_0 */
3672 { "cldemote", { Mb }, 0 },
3673 { "nopQ", { Ev }, 0 },
3674 { "nopQ", { Ev }, 0 },
3675 { "nopQ", { Ev }, 0 },
3676 { "nopQ", { Ev }, 0 },
3677 { "nopQ", { Ev }, 0 },
3678 { "nopQ", { Ev }, 0 },
3679 { "nopQ", { Ev }, 0 },
3681 /* REG_0F1E_MOD_3 */
3683 { "nopQ", { Ev }, 0 },
3684 { "rdsspK", { Rdq }, PREFIX_OPCODE },
3685 { "nopQ", { Ev }, 0 },
3686 { "nopQ", { Ev }, 0 },
3687 { "nopQ", { Ev }, 0 },
3688 { "nopQ", { Ev }, 0 },
3689 { "nopQ", { Ev }, 0 },
3690 { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3696 { MOD_TABLE (MOD_0F71_REG_2) },
3698 { MOD_TABLE (MOD_0F71_REG_4) },
3700 { MOD_TABLE (MOD_0F71_REG_6) },
3706 { MOD_TABLE (MOD_0F72_REG_2) },
3708 { MOD_TABLE (MOD_0F72_REG_4) },
3710 { MOD_TABLE (MOD_0F72_REG_6) },
3716 { MOD_TABLE (MOD_0F73_REG_2) },
3717 { MOD_TABLE (MOD_0F73_REG_3) },
3720 { MOD_TABLE (MOD_0F73_REG_6) },
3721 { MOD_TABLE (MOD_0F73_REG_7) },
3725 { "montmul", { { OP_0f07, 0 } }, 0 },
3726 { "xsha1", { { OP_0f07, 0 } }, 0 },
3727 { "xsha256", { { OP_0f07, 0 } }, 0 },
3731 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
3732 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
3733 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
3734 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
3735 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
3736 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
3740 { MOD_TABLE (MOD_0FAE_REG_0) },
3741 { MOD_TABLE (MOD_0FAE_REG_1) },
3742 { MOD_TABLE (MOD_0FAE_REG_2) },
3743 { MOD_TABLE (MOD_0FAE_REG_3) },
3744 { MOD_TABLE (MOD_0FAE_REG_4) },
3745 { MOD_TABLE (MOD_0FAE_REG_5) },
3746 { MOD_TABLE (MOD_0FAE_REG_6) },
3747 { MOD_TABLE (MOD_0FAE_REG_7) },
3755 { "btQ", { Ev, Ib }, 0 },
3756 { "btsQ", { Evh1, Ib }, 0 },
3757 { "btrQ", { Evh1, Ib }, 0 },
3758 { "btcQ", { Evh1, Ib }, 0 },
3763 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3765 { MOD_TABLE (MOD_0FC7_REG_3) },
3766 { MOD_TABLE (MOD_0FC7_REG_4) },
3767 { MOD_TABLE (MOD_0FC7_REG_5) },
3768 { MOD_TABLE (MOD_0FC7_REG_6) },
3769 { MOD_TABLE (MOD_0FC7_REG_7) },
3775 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3777 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3779 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3785 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3787 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3789 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3795 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3796 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3799 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3800 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3806 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3807 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3809 /* REG_VEX_0F38F3 */
3812 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3813 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3814 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3818 { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3819 { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3823 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3824 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3826 /* REG_XOP_TBM_01 */
3829 { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3830 { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3831 { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 },
3832 { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3833 { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 },
3834 { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 },
3835 { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3837 /* REG_XOP_TBM_02 */
3840 { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3845 { "blci", { { OP_LWP_E, 0 }, Ev }, 0 },
3847 #define NEED_REG_TABLE
3848 #include "i386-dis-evex.h"
3849 #undef NEED_REG_TABLE
3852 static const struct dis386 prefix_table[][4] = {
3855 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3856 { "pause", { XX }, 0 },
3857 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3858 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3861 /* PREFIX_MOD_0_0F01_REG_5 */
3864 { "rstorssp", { Mq }, PREFIX_OPCODE },
3867 /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3870 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3873 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3876 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3881 { "wbinvd", { XX }, 0 },
3882 { "wbnoinvd", { XX }, 0 },
3887 { "movups", { XM, EXx }, PREFIX_OPCODE },
3888 { "movss", { XM, EXd }, PREFIX_OPCODE },
3889 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3890 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3895 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3896 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3897 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3898 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3903 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3904 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3905 { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3906 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3911 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3912 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3913 { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3918 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3919 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3920 { "bndmov", { Gbnd, Ebnd }, 0 },
3921 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3926 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3927 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3928 { "bndmov", { EbndS, Gbnd }, 0 },
3929 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3934 { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3935 { "nopQ", { Ev }, PREFIX_OPCODE },
3936 { "nopQ", { Ev }, PREFIX_OPCODE },
3937 { "nopQ", { Ev }, PREFIX_OPCODE },
3942 { "nopQ", { Ev }, PREFIX_OPCODE },
3943 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3944 { "nopQ", { Ev }, PREFIX_OPCODE },
3945 { "nopQ", { Ev }, PREFIX_OPCODE },
3950 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3951 { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3952 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3953 { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3958 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3959 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3960 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3961 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3966 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3967 { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE },
3968 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3969 { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE },
3974 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3975 { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE },
3976 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3977 { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE },
3982 { "ucomiss",{ XM, EXd }, 0 },
3984 { "ucomisd",{ XM, EXq }, 0 },
3989 { "comiss", { XM, EXd }, 0 },
3991 { "comisd", { XM, EXq }, 0 },
3996 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3997 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3998 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3999 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
4004 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
4005 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
4010 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
4011 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
4016 { "addps", { XM, EXx }, PREFIX_OPCODE },
4017 { "addss", { XM, EXd }, PREFIX_OPCODE },
4018 { "addpd", { XM, EXx }, PREFIX_OPCODE },
4019 { "addsd", { XM, EXq }, PREFIX_OPCODE },
4024 { "mulps", { XM, EXx }, PREFIX_OPCODE },
4025 { "mulss", { XM, EXd }, PREFIX_OPCODE },
4026 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
4027 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
4032 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
4033 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
4034 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
4035 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
4040 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
4041 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
4042 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
4047 { "subps", { XM, EXx }, PREFIX_OPCODE },
4048 { "subss", { XM, EXd }, PREFIX_OPCODE },
4049 { "subpd", { XM, EXx }, PREFIX_OPCODE },
4050 { "subsd", { XM, EXq }, PREFIX_OPCODE },
4055 { "minps", { XM, EXx }, PREFIX_OPCODE },
4056 { "minss", { XM, EXd }, PREFIX_OPCODE },
4057 { "minpd", { XM, EXx }, PREFIX_OPCODE },
4058 { "minsd", { XM, EXq }, PREFIX_OPCODE },
4063 { "divps", { XM, EXx }, PREFIX_OPCODE },
4064 { "divss", { XM, EXd }, PREFIX_OPCODE },
4065 { "divpd", { XM, EXx }, PREFIX_OPCODE },
4066 { "divsd", { XM, EXq }, PREFIX_OPCODE },
4071 { "maxps", { XM, EXx }, PREFIX_OPCODE },
4072 { "maxss", { XM, EXd }, PREFIX_OPCODE },
4073 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
4074 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
4079 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
4081 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
4086 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
4088 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
4093 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
4095 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
4102 { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
4109 { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
4114 { "movq", { MX, EM }, PREFIX_OPCODE },
4115 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
4116 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4121 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4122 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4123 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4124 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4127 /* PREFIX_0F73_REG_3 */
4131 { "psrldq", { XS, Ib }, 0 },
4134 /* PREFIX_0F73_REG_7 */
4138 { "pslldq", { XS, Ib }, 0 },
4143 {"vmread", { Em, Gm }, 0 },
4145 {"extrq", { XS, Ib, Ib }, 0 },
4146 {"insertq", { XM, XS, Ib, Ib }, 0 },
4151 {"vmwrite", { Gm, Em }, 0 },
4153 {"extrq", { XM, XS }, 0 },
4154 {"insertq", { XM, XS }, 0 },
4161 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4162 { "haddps", { XM, EXx }, PREFIX_OPCODE },
4169 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4170 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4175 { "movK", { Edq, MX }, PREFIX_OPCODE },
4176 { "movq", { XM, EXq }, PREFIX_OPCODE },
4177 { "movK", { Edq, XM }, PREFIX_OPCODE },
4182 { "movq", { EMS, MX }, PREFIX_OPCODE },
4183 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4184 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4187 /* PREFIX_0FAE_REG_0 */
4190 { "rdfsbase", { Ev }, 0 },
4193 /* PREFIX_0FAE_REG_1 */
4196 { "rdgsbase", { Ev }, 0 },
4199 /* PREFIX_0FAE_REG_2 */
4202 { "wrfsbase", { Ev }, 0 },
4205 /* PREFIX_0FAE_REG_3 */
4208 { "wrgsbase", { Ev }, 0 },
4211 /* PREFIX_MOD_0_0FAE_REG_4 */
4213 { "xsave", { FXSAVE }, 0 },
4214 { "ptwrite%LQ", { Edq }, 0 },
4217 /* PREFIX_MOD_3_0FAE_REG_4 */
4220 { "ptwrite%LQ", { Edq }, 0 },
4223 /* PREFIX_MOD_0_0FAE_REG_5 */
4225 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
4228 /* PREFIX_MOD_3_0FAE_REG_5 */
4230 { "lfence", { Skip_MODRM }, 0 },
4231 { "incsspK", { Rdq }, PREFIX_OPCODE },
4234 /* PREFIX_MOD_0_0FAE_REG_6 */
4236 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
4237 { "clrssbsy", { Mq }, PREFIX_OPCODE },
4238 { "clwb", { Mb }, PREFIX_OPCODE },
4241 /* PREFIX_MOD_1_0FAE_REG_6 */
4243 { RM_TABLE (RM_0FAE_REG_6) },
4244 { "umonitor", { Eva }, PREFIX_OPCODE },
4245 { "tpause", { Edq }, PREFIX_OPCODE },
4246 { "umwait", { Edq }, PREFIX_OPCODE },
4249 /* PREFIX_0FAE_REG_7 */
4251 { "clflush", { Mb }, 0 },
4253 { "clflushopt", { Mb }, 0 },
4259 { "popcntS", { Gv, Ev }, 0 },
4264 { "bsfS", { Gv, Ev }, 0 },
4265 { "tzcntS", { Gv, Ev }, 0 },
4266 { "bsfS", { Gv, Ev }, 0 },
4271 { "bsrS", { Gv, Ev }, 0 },
4272 { "lzcntS", { Gv, Ev }, 0 },
4273 { "bsrS", { Gv, Ev }, 0 },
4278 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
4279 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
4280 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
4281 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
4284 /* PREFIX_MOD_0_0FC3 */
4286 { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4289 /* PREFIX_MOD_0_0FC7_REG_6 */
4291 { "vmptrld",{ Mq }, 0 },
4292 { "vmxon", { Mq }, 0 },
4293 { "vmclear",{ Mq }, 0 },
4296 /* PREFIX_MOD_3_0FC7_REG_6 */
4298 { "rdrand", { Ev }, 0 },
4300 { "rdrand", { Ev }, 0 }
4303 /* PREFIX_MOD_3_0FC7_REG_7 */
4305 { "rdseed", { Ev }, 0 },
4306 { "rdpid", { Em }, 0 },
4307 { "rdseed", { Ev }, 0 },
4314 { "addsubpd", { XM, EXx }, 0 },
4315 { "addsubps", { XM, EXx }, 0 },
4321 { "movq2dq",{ XM, MS }, 0 },
4322 { "movq", { EXqS, XM }, 0 },
4323 { "movdq2q",{ MX, XS }, 0 },
4329 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4330 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4331 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4336 { "movntq", { Mq, MX }, PREFIX_OPCODE },
4338 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4346 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4351 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4353 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4360 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4367 { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4374 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4381 { "ptest", { XM, EXx }, PREFIX_OPCODE },
4388 { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4395 { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4402 { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4409 { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4416 { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4423 { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4430 { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4437 { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4444 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4451 { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4458 { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4465 { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4472 { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4479 { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4486 { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4493 { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4500 { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4507 { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4514 { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4521 { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4528 { "pminud", { XM, EXx }, PREFIX_OPCODE },
4535 { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4542 { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4549 { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4556 { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4563 { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4570 { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4577 { "invept", { Gm, Mo }, PREFIX_OPCODE },
4584 { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4591 { "invpcid", { Gm, M }, PREFIX_OPCODE },
4596 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4601 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4606 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4611 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4616 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4621 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4628 { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4635 { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4642 { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4649 { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4656 { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4663 { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4668 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4670 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4671 { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4676 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4678 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4679 { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4686 { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4691 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4692 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
4693 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
4701 { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4706 { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4713 { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4720 { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4727 { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4734 { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4741 { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4748 { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4755 { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4762 { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4769 { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4776 { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4783 { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4790 { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4797 { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4804 { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4811 { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE },
4818 { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE },
4825 { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4832 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4839 { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4846 { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4853 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4860 { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4865 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4872 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4879 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4886 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4889 /* PREFIX_VEX_0F10 */
4891 { VEX_W_TABLE (VEX_W_0F10_P_0) },
4892 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4893 { VEX_W_TABLE (VEX_W_0F10_P_2) },
4894 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4897 /* PREFIX_VEX_0F11 */
4899 { VEX_W_TABLE (VEX_W_0F11_P_0) },
4900 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4901 { VEX_W_TABLE (VEX_W_0F11_P_2) },
4902 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4905 /* PREFIX_VEX_0F12 */
4907 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4908 { VEX_W_TABLE (VEX_W_0F12_P_1) },
4909 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4910 { VEX_W_TABLE (VEX_W_0F12_P_3) },
4913 /* PREFIX_VEX_0F16 */
4915 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4916 { VEX_W_TABLE (VEX_W_0F16_P_1) },
4917 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4920 /* PREFIX_VEX_0F2A */
4923 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4925 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4928 /* PREFIX_VEX_0F2C */
4931 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4933 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4936 /* PREFIX_VEX_0F2D */
4939 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4941 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4944 /* PREFIX_VEX_0F2E */
4946 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4948 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4951 /* PREFIX_VEX_0F2F */
4953 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4955 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4958 /* PREFIX_VEX_0F41 */
4960 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4962 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4965 /* PREFIX_VEX_0F42 */
4967 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4969 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4972 /* PREFIX_VEX_0F44 */
4974 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4976 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4979 /* PREFIX_VEX_0F45 */
4981 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4983 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4986 /* PREFIX_VEX_0F46 */
4988 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4990 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4993 /* PREFIX_VEX_0F47 */
4995 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4997 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
5000 /* PREFIX_VEX_0F4A */
5002 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
5004 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
5007 /* PREFIX_VEX_0F4B */
5009 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
5011 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
5014 /* PREFIX_VEX_0F51 */
5016 { VEX_W_TABLE (VEX_W_0F51_P_0) },
5017 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
5018 { VEX_W_TABLE (VEX_W_0F51_P_2) },
5019 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
5022 /* PREFIX_VEX_0F52 */
5024 { VEX_W_TABLE (VEX_W_0F52_P_0) },
5025 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
5028 /* PREFIX_VEX_0F53 */
5030 { VEX_W_TABLE (VEX_W_0F53_P_0) },
5031 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
5034 /* PREFIX_VEX_0F58 */
5036 { VEX_W_TABLE (VEX_W_0F58_P_0) },
5037 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
5038 { VEX_W_TABLE (VEX_W_0F58_P_2) },
5039 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
5042 /* PREFIX_VEX_0F59 */
5044 { VEX_W_TABLE (VEX_W_0F59_P_0) },
5045 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
5046 { VEX_W_TABLE (VEX_W_0F59_P_2) },
5047 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
5050 /* PREFIX_VEX_0F5A */
5052 { VEX_W_TABLE (VEX_W_0F5A_P_0) },
5053 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
5054 { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
5055 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
5058 /* PREFIX_VEX_0F5B */
5060 { VEX_W_TABLE (VEX_W_0F5B_P_0) },
5061 { VEX_W_TABLE (VEX_W_0F5B_P_1) },
5062 { VEX_W_TABLE (VEX_W_0F5B_P_2) },
5065 /* PREFIX_VEX_0F5C */
5067 { VEX_W_TABLE (VEX_W_0F5C_P_0) },
5068 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
5069 { VEX_W_TABLE (VEX_W_0F5C_P_2) },
5070 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
5073 /* PREFIX_VEX_0F5D */
5075 { VEX_W_TABLE (VEX_W_0F5D_P_0) },
5076 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
5077 { VEX_W_TABLE (VEX_W_0F5D_P_2) },
5078 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
5081 /* PREFIX_VEX_0F5E */
5083 { VEX_W_TABLE (VEX_W_0F5E_P_0) },
5084 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
5085 { VEX_W_TABLE (VEX_W_0F5E_P_2) },
5086 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
5089 /* PREFIX_VEX_0F5F */
5091 { VEX_W_TABLE (VEX_W_0F5F_P_0) },
5092 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
5093 { VEX_W_TABLE (VEX_W_0F5F_P_2) },
5094 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
5097 /* PREFIX_VEX_0F60 */
5101 { VEX_W_TABLE (VEX_W_0F60_P_2) },
5104 /* PREFIX_VEX_0F61 */
5108 { VEX_W_TABLE (VEX_W_0F61_P_2) },
5111 /* PREFIX_VEX_0F62 */
5115 { VEX_W_TABLE (VEX_W_0F62_P_2) },
5118 /* PREFIX_VEX_0F63 */
5122 { VEX_W_TABLE (VEX_W_0F63_P_2) },
5125 /* PREFIX_VEX_0F64 */
5129 { VEX_W_TABLE (VEX_W_0F64_P_2) },
5132 /* PREFIX_VEX_0F65 */
5136 { VEX_W_TABLE (VEX_W_0F65_P_2) },
5139 /* PREFIX_VEX_0F66 */
5143 { VEX_W_TABLE (VEX_W_0F66_P_2) },
5146 /* PREFIX_VEX_0F67 */
5150 { VEX_W_TABLE (VEX_W_0F67_P_2) },
5153 /* PREFIX_VEX_0F68 */
5157 { VEX_W_TABLE (VEX_W_0F68_P_2) },
5160 /* PREFIX_VEX_0F69 */
5164 { VEX_W_TABLE (VEX_W_0F69_P_2) },
5167 /* PREFIX_VEX_0F6A */
5171 { VEX_W_TABLE (VEX_W_0F6A_P_2) },
5174 /* PREFIX_VEX_0F6B */
5178 { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5181 /* PREFIX_VEX_0F6C */
5185 { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5188 /* PREFIX_VEX_0F6D */
5192 { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5195 /* PREFIX_VEX_0F6E */
5199 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5202 /* PREFIX_VEX_0F6F */
5205 { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5206 { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5209 /* PREFIX_VEX_0F70 */
5212 { VEX_W_TABLE (VEX_W_0F70_P_1) },
5213 { VEX_W_TABLE (VEX_W_0F70_P_2) },
5214 { VEX_W_TABLE (VEX_W_0F70_P_3) },
5217 /* PREFIX_VEX_0F71_REG_2 */
5221 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5224 /* PREFIX_VEX_0F71_REG_4 */
5228 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5231 /* PREFIX_VEX_0F71_REG_6 */
5235 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5238 /* PREFIX_VEX_0F72_REG_2 */
5242 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5245 /* PREFIX_VEX_0F72_REG_4 */
5249 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5252 /* PREFIX_VEX_0F72_REG_6 */
5256 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5259 /* PREFIX_VEX_0F73_REG_2 */
5263 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5266 /* PREFIX_VEX_0F73_REG_3 */
5270 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5273 /* PREFIX_VEX_0F73_REG_6 */
5277 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5280 /* PREFIX_VEX_0F73_REG_7 */
5284 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5287 /* PREFIX_VEX_0F74 */
5291 { VEX_W_TABLE (VEX_W_0F74_P_2) },
5294 /* PREFIX_VEX_0F75 */
5298 { VEX_W_TABLE (VEX_W_0F75_P_2) },
5301 /* PREFIX_VEX_0F76 */
5305 { VEX_W_TABLE (VEX_W_0F76_P_2) },
5308 /* PREFIX_VEX_0F77 */
5310 { VEX_W_TABLE (VEX_W_0F77_P_0) },
5313 /* PREFIX_VEX_0F7C */
5317 { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5318 { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5321 /* PREFIX_VEX_0F7D */
5325 { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5326 { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5329 /* PREFIX_VEX_0F7E */
5332 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5333 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5336 /* PREFIX_VEX_0F7F */
5339 { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5340 { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5343 /* PREFIX_VEX_0F90 */
5345 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5347 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5350 /* PREFIX_VEX_0F91 */
5352 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5354 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5357 /* PREFIX_VEX_0F92 */
5359 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5361 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5362 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5365 /* PREFIX_VEX_0F93 */
5367 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5369 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5370 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5373 /* PREFIX_VEX_0F98 */
5375 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5377 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5380 /* PREFIX_VEX_0F99 */
5382 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5384 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5387 /* PREFIX_VEX_0FC2 */
5389 { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5390 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5391 { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5392 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5395 /* PREFIX_VEX_0FC4 */
5399 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5402 /* PREFIX_VEX_0FC5 */
5406 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5409 /* PREFIX_VEX_0FD0 */
5413 { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5414 { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5417 /* PREFIX_VEX_0FD1 */
5421 { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5424 /* PREFIX_VEX_0FD2 */
5428 { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5431 /* PREFIX_VEX_0FD3 */
5435 { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5438 /* PREFIX_VEX_0FD4 */
5442 { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5445 /* PREFIX_VEX_0FD5 */
5449 { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5452 /* PREFIX_VEX_0FD6 */
5456 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5459 /* PREFIX_VEX_0FD7 */
5463 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5466 /* PREFIX_VEX_0FD8 */
5470 { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5473 /* PREFIX_VEX_0FD9 */
5477 { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5480 /* PREFIX_VEX_0FDA */
5484 { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5487 /* PREFIX_VEX_0FDB */
5491 { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5494 /* PREFIX_VEX_0FDC */
5498 { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5501 /* PREFIX_VEX_0FDD */
5505 { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5508 /* PREFIX_VEX_0FDE */
5512 { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5515 /* PREFIX_VEX_0FDF */
5519 { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5522 /* PREFIX_VEX_0FE0 */
5526 { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5529 /* PREFIX_VEX_0FE1 */
5533 { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5536 /* PREFIX_VEX_0FE2 */
5540 { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5543 /* PREFIX_VEX_0FE3 */
5547 { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5550 /* PREFIX_VEX_0FE4 */
5554 { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5557 /* PREFIX_VEX_0FE5 */
5561 { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5564 /* PREFIX_VEX_0FE6 */
5567 { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5568 { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5569 { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5572 /* PREFIX_VEX_0FE7 */
5576 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5579 /* PREFIX_VEX_0FE8 */
5583 { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5586 /* PREFIX_VEX_0FE9 */
5590 { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5593 /* PREFIX_VEX_0FEA */
5597 { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5600 /* PREFIX_VEX_0FEB */
5604 { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5607 /* PREFIX_VEX_0FEC */
5611 { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5614 /* PREFIX_VEX_0FED */
5618 { VEX_W_TABLE (VEX_W_0FED_P_2) },
5621 /* PREFIX_VEX_0FEE */
5625 { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5628 /* PREFIX_VEX_0FEF */
5632 { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5635 /* PREFIX_VEX_0FF0 */
5640 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5643 /* PREFIX_VEX_0FF1 */
5647 { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5650 /* PREFIX_VEX_0FF2 */
5654 { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5657 /* PREFIX_VEX_0FF3 */
5661 { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5664 /* PREFIX_VEX_0FF4 */
5668 { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5671 /* PREFIX_VEX_0FF5 */
5675 { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5678 /* PREFIX_VEX_0FF6 */
5682 { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5685 /* PREFIX_VEX_0FF7 */
5689 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5692 /* PREFIX_VEX_0FF8 */
5696 { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5699 /* PREFIX_VEX_0FF9 */
5703 { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5706 /* PREFIX_VEX_0FFA */
5710 { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5713 /* PREFIX_VEX_0FFB */
5717 { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5720 /* PREFIX_VEX_0FFC */
5724 { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5727 /* PREFIX_VEX_0FFD */
5731 { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5734 /* PREFIX_VEX_0FFE */
5738 { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5741 /* PREFIX_VEX_0F3800 */
5745 { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5748 /* PREFIX_VEX_0F3801 */
5752 { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5755 /* PREFIX_VEX_0F3802 */
5759 { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5762 /* PREFIX_VEX_0F3803 */
5766 { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5769 /* PREFIX_VEX_0F3804 */
5773 { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5776 /* PREFIX_VEX_0F3805 */
5780 { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5783 /* PREFIX_VEX_0F3806 */
5787 { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5790 /* PREFIX_VEX_0F3807 */
5794 { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5797 /* PREFIX_VEX_0F3808 */
5801 { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5804 /* PREFIX_VEX_0F3809 */
5808 { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5811 /* PREFIX_VEX_0F380A */
5815 { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5818 /* PREFIX_VEX_0F380B */
5822 { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5825 /* PREFIX_VEX_0F380C */
5829 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5832 /* PREFIX_VEX_0F380D */
5836 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5839 /* PREFIX_VEX_0F380E */
5843 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5846 /* PREFIX_VEX_0F380F */
5850 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5853 /* PREFIX_VEX_0F3813 */
5857 { "vcvtph2ps", { XM, EXxmmq }, 0 },
5860 /* PREFIX_VEX_0F3816 */
5864 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5867 /* PREFIX_VEX_0F3817 */
5871 { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5874 /* PREFIX_VEX_0F3818 */
5878 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5881 /* PREFIX_VEX_0F3819 */
5885 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5888 /* PREFIX_VEX_0F381A */
5892 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5895 /* PREFIX_VEX_0F381C */
5899 { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5902 /* PREFIX_VEX_0F381D */
5906 { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5909 /* PREFIX_VEX_0F381E */
5913 { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5916 /* PREFIX_VEX_0F3820 */
5920 { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5923 /* PREFIX_VEX_0F3821 */
5927 { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5930 /* PREFIX_VEX_0F3822 */
5934 { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5937 /* PREFIX_VEX_0F3823 */
5941 { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5944 /* PREFIX_VEX_0F3824 */
5948 { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5951 /* PREFIX_VEX_0F3825 */
5955 { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5958 /* PREFIX_VEX_0F3828 */
5962 { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5965 /* PREFIX_VEX_0F3829 */
5969 { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5972 /* PREFIX_VEX_0F382A */
5976 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5979 /* PREFIX_VEX_0F382B */
5983 { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5986 /* PREFIX_VEX_0F382C */
5990 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5993 /* PREFIX_VEX_0F382D */
5997 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
6000 /* PREFIX_VEX_0F382E */
6004 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
6007 /* PREFIX_VEX_0F382F */
6011 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
6014 /* PREFIX_VEX_0F3830 */
6018 { VEX_W_TABLE (VEX_W_0F3830_P_2) },
6021 /* PREFIX_VEX_0F3831 */
6025 { VEX_W_TABLE (VEX_W_0F3831_P_2) },
6028 /* PREFIX_VEX_0F3832 */
6032 { VEX_W_TABLE (VEX_W_0F3832_P_2) },
6035 /* PREFIX_VEX_0F3833 */
6039 { VEX_W_TABLE (VEX_W_0F3833_P_2) },
6042 /* PREFIX_VEX_0F3834 */
6046 { VEX_W_TABLE (VEX_W_0F3834_P_2) },
6049 /* PREFIX_VEX_0F3835 */
6053 { VEX_W_TABLE (VEX_W_0F3835_P_2) },
6056 /* PREFIX_VEX_0F3836 */
6060 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
6063 /* PREFIX_VEX_0F3837 */
6067 { VEX_W_TABLE (VEX_W_0F3837_P_2) },
6070 /* PREFIX_VEX_0F3838 */
6074 { VEX_W_TABLE (VEX_W_0F3838_P_2) },
6077 /* PREFIX_VEX_0F3839 */
6081 { VEX_W_TABLE (VEX_W_0F3839_P_2) },
6084 /* PREFIX_VEX_0F383A */
6088 { VEX_W_TABLE (VEX_W_0F383A_P_2) },
6091 /* PREFIX_VEX_0F383B */
6095 { VEX_W_TABLE (VEX_W_0F383B_P_2) },
6098 /* PREFIX_VEX_0F383C */
6102 { VEX_W_TABLE (VEX_W_0F383C_P_2) },
6105 /* PREFIX_VEX_0F383D */
6109 { VEX_W_TABLE (VEX_W_0F383D_P_2) },
6112 /* PREFIX_VEX_0F383E */
6116 { VEX_W_TABLE (VEX_W_0F383E_P_2) },
6119 /* PREFIX_VEX_0F383F */
6123 { VEX_W_TABLE (VEX_W_0F383F_P_2) },
6126 /* PREFIX_VEX_0F3840 */
6130 { VEX_W_TABLE (VEX_W_0F3840_P_2) },
6133 /* PREFIX_VEX_0F3841 */
6137 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
6140 /* PREFIX_VEX_0F3845 */
6144 { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
6147 /* PREFIX_VEX_0F3846 */
6151 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
6154 /* PREFIX_VEX_0F3847 */
6158 { "vpsllv%LW", { XM, Vex, EXx }, 0 },
6161 /* PREFIX_VEX_0F3858 */
6165 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
6168 /* PREFIX_VEX_0F3859 */
6172 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
6175 /* PREFIX_VEX_0F385A */
6179 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6182 /* PREFIX_VEX_0F3878 */
6186 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6189 /* PREFIX_VEX_0F3879 */
6193 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6196 /* PREFIX_VEX_0F388C */
6200 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6203 /* PREFIX_VEX_0F388E */
6207 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6210 /* PREFIX_VEX_0F3890 */
6214 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6217 /* PREFIX_VEX_0F3891 */
6221 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6224 /* PREFIX_VEX_0F3892 */
6228 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6231 /* PREFIX_VEX_0F3893 */
6235 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6238 /* PREFIX_VEX_0F3896 */
6242 { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6245 /* PREFIX_VEX_0F3897 */
6249 { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6252 /* PREFIX_VEX_0F3898 */
6256 { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6259 /* PREFIX_VEX_0F3899 */
6263 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6266 /* PREFIX_VEX_0F389A */
6270 { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6273 /* PREFIX_VEX_0F389B */
6277 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6280 /* PREFIX_VEX_0F389C */
6284 { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6287 /* PREFIX_VEX_0F389D */
6291 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6294 /* PREFIX_VEX_0F389E */
6298 { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6301 /* PREFIX_VEX_0F389F */
6305 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6308 /* PREFIX_VEX_0F38A6 */
6312 { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6316 /* PREFIX_VEX_0F38A7 */
6320 { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6323 /* PREFIX_VEX_0F38A8 */
6327 { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6330 /* PREFIX_VEX_0F38A9 */
6334 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6337 /* PREFIX_VEX_0F38AA */
6341 { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6344 /* PREFIX_VEX_0F38AB */
6348 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6351 /* PREFIX_VEX_0F38AC */
6355 { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6358 /* PREFIX_VEX_0F38AD */
6362 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6365 /* PREFIX_VEX_0F38AE */
6369 { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6372 /* PREFIX_VEX_0F38AF */
6376 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6379 /* PREFIX_VEX_0F38B6 */
6383 { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6386 /* PREFIX_VEX_0F38B7 */
6390 { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6393 /* PREFIX_VEX_0F38B8 */
6397 { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6400 /* PREFIX_VEX_0F38B9 */
6404 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6407 /* PREFIX_VEX_0F38BA */
6411 { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6414 /* PREFIX_VEX_0F38BB */
6418 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6421 /* PREFIX_VEX_0F38BC */
6425 { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6428 /* PREFIX_VEX_0F38BD */
6432 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6435 /* PREFIX_VEX_0F38BE */
6439 { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6442 /* PREFIX_VEX_0F38BF */
6446 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6449 /* PREFIX_VEX_0F38CF */
6453 { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6456 /* PREFIX_VEX_0F38DB */
6460 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6463 /* PREFIX_VEX_0F38DC */
6467 { "vaesenc", { XM, Vex, EXx }, 0 },
6470 /* PREFIX_VEX_0F38DD */
6474 { "vaesenclast", { XM, Vex, EXx }, 0 },
6477 /* PREFIX_VEX_0F38DE */
6481 { "vaesdec", { XM, Vex, EXx }, 0 },
6484 /* PREFIX_VEX_0F38DF */
6488 { "vaesdeclast", { XM, Vex, EXx }, 0 },
6491 /* PREFIX_VEX_0F38F2 */
6493 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6496 /* PREFIX_VEX_0F38F3_REG_1 */
6498 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6501 /* PREFIX_VEX_0F38F3_REG_2 */
6503 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6506 /* PREFIX_VEX_0F38F3_REG_3 */
6508 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6511 /* PREFIX_VEX_0F38F5 */
6513 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6514 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6516 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6519 /* PREFIX_VEX_0F38F6 */
6524 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6527 /* PREFIX_VEX_0F38F7 */
6529 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6530 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6531 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6532 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6535 /* PREFIX_VEX_0F3A00 */
6539 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6542 /* PREFIX_VEX_0F3A01 */
6546 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6549 /* PREFIX_VEX_0F3A02 */
6553 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6556 /* PREFIX_VEX_0F3A04 */
6560 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6563 /* PREFIX_VEX_0F3A05 */
6567 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6570 /* PREFIX_VEX_0F3A06 */
6574 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6577 /* PREFIX_VEX_0F3A08 */
6581 { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6584 /* PREFIX_VEX_0F3A09 */
6588 { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6591 /* PREFIX_VEX_0F3A0A */
6595 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6598 /* PREFIX_VEX_0F3A0B */
6602 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6605 /* PREFIX_VEX_0F3A0C */
6609 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6612 /* PREFIX_VEX_0F3A0D */
6616 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6619 /* PREFIX_VEX_0F3A0E */
6623 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6626 /* PREFIX_VEX_0F3A0F */
6630 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6633 /* PREFIX_VEX_0F3A14 */
6637 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6640 /* PREFIX_VEX_0F3A15 */
6644 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6647 /* PREFIX_VEX_0F3A16 */
6651 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6654 /* PREFIX_VEX_0F3A17 */
6658 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6661 /* PREFIX_VEX_0F3A18 */
6665 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6668 /* PREFIX_VEX_0F3A19 */
6672 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6675 /* PREFIX_VEX_0F3A1D */
6679 { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6682 /* PREFIX_VEX_0F3A20 */
6686 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6689 /* PREFIX_VEX_0F3A21 */
6693 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6696 /* PREFIX_VEX_0F3A22 */
6700 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6703 /* PREFIX_VEX_0F3A30 */
6707 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6710 /* PREFIX_VEX_0F3A31 */
6714 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6717 /* PREFIX_VEX_0F3A32 */
6721 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6724 /* PREFIX_VEX_0F3A33 */
6728 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6731 /* PREFIX_VEX_0F3A38 */
6735 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6738 /* PREFIX_VEX_0F3A39 */
6742 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6745 /* PREFIX_VEX_0F3A40 */
6749 { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6752 /* PREFIX_VEX_0F3A41 */
6756 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6759 /* PREFIX_VEX_0F3A42 */
6763 { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6766 /* PREFIX_VEX_0F3A44 */
6770 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 },
6773 /* PREFIX_VEX_0F3A46 */
6777 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6780 /* PREFIX_VEX_0F3A48 */
6784 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6787 /* PREFIX_VEX_0F3A49 */
6791 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6794 /* PREFIX_VEX_0F3A4A */
6798 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6801 /* PREFIX_VEX_0F3A4B */
6805 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6808 /* PREFIX_VEX_0F3A4C */
6812 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6815 /* PREFIX_VEX_0F3A5C */
6819 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6822 /* PREFIX_VEX_0F3A5D */
6826 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6829 /* PREFIX_VEX_0F3A5E */
6833 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6836 /* PREFIX_VEX_0F3A5F */
6840 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6843 /* PREFIX_VEX_0F3A60 */
6847 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6851 /* PREFIX_VEX_0F3A61 */
6855 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6858 /* PREFIX_VEX_0F3A62 */
6862 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6865 /* PREFIX_VEX_0F3A63 */
6869 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6872 /* PREFIX_VEX_0F3A68 */
6876 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6879 /* PREFIX_VEX_0F3A69 */
6883 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6886 /* PREFIX_VEX_0F3A6A */
6890 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6893 /* PREFIX_VEX_0F3A6B */
6897 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6900 /* PREFIX_VEX_0F3A6C */
6904 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6907 /* PREFIX_VEX_0F3A6D */
6911 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6914 /* PREFIX_VEX_0F3A6E */
6918 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6921 /* PREFIX_VEX_0F3A6F */
6925 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6928 /* PREFIX_VEX_0F3A78 */
6932 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6935 /* PREFIX_VEX_0F3A79 */
6939 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6942 /* PREFIX_VEX_0F3A7A */
6946 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6949 /* PREFIX_VEX_0F3A7B */
6953 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6956 /* PREFIX_VEX_0F3A7C */
6960 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6964 /* PREFIX_VEX_0F3A7D */
6968 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6971 /* PREFIX_VEX_0F3A7E */
6975 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6978 /* PREFIX_VEX_0F3A7F */
6982 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6985 /* PREFIX_VEX_0F3ACE */
6989 { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6992 /* PREFIX_VEX_0F3ACF */
6996 { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6999 /* PREFIX_VEX_0F3ADF */
7003 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
7006 /* PREFIX_VEX_0F3AF0 */
7011 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
7014 #define NEED_PREFIX_TABLE
7015 #include "i386-dis-evex.h"
7016 #undef NEED_PREFIX_TABLE
7019 static const struct dis386 x86_64_table[][2] = {
7022 { "pushP", { es }, 0 },
7027 { "popP", { es }, 0 },
7032 { "pushP", { cs }, 0 },
7037 { "pushP", { ss }, 0 },
7042 { "popP", { ss }, 0 },
7047 { "pushP", { ds }, 0 },
7052 { "popP", { ds }, 0 },
7057 { "daa", { XX }, 0 },
7062 { "das", { XX }, 0 },
7067 { "aaa", { XX }, 0 },
7072 { "aas", { XX }, 0 },
7077 { "pushaP", { XX }, 0 },
7082 { "popaP", { XX }, 0 },
7087 { MOD_TABLE (MOD_62_32BIT) },
7088 { EVEX_TABLE (EVEX_0F) },
7093 { "arpl", { Ew, Gw }, 0 },
7094 { "movs{lq|xd}", { Gv, Ed }, 0 },
7099 { "ins{R|}", { Yzr, indirDX }, 0 },
7100 { "ins{G|}", { Yzr, indirDX }, 0 },
7105 { "outs{R|}", { indirDXr, Xz }, 0 },
7106 { "outs{G|}", { indirDXr, Xz }, 0 },
7111 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
7112 { REG_TABLE (REG_80) },
7117 { "Jcall{T|}", { Ap }, 0 },
7122 { MOD_TABLE (MOD_C4_32BIT) },
7123 { VEX_C4_TABLE (VEX_0F) },
7128 { MOD_TABLE (MOD_C5_32BIT) },
7129 { VEX_C5_TABLE (VEX_0F) },
7134 { "into", { XX }, 0 },
7139 { "aam", { Ib }, 0 },
7144 { "aad", { Ib }, 0 },
7149 { "callP", { Jv, BND }, 0 },
7150 { "call@", { Jv, BND }, 0 }
7155 { "jmpP", { Jv, BND }, 0 },
7156 { "jmp@", { Jv, BND }, 0 }
7161 { "Jjmp{T|}", { Ap }, 0 },
7164 /* X86_64_0F01_REG_0 */
7166 { "sgdt{Q|IQ}", { M }, 0 },
7167 { "sgdt", { M }, 0 },
7170 /* X86_64_0F01_REG_1 */
7172 { "sidt{Q|IQ}", { M }, 0 },
7173 { "sidt", { M }, 0 },
7176 /* X86_64_0F01_REG_2 */
7178 { "lgdt{Q|Q}", { M }, 0 },
7179 { "lgdt", { M }, 0 },
7182 /* X86_64_0F01_REG_3 */
7184 { "lidt{Q|Q}", { M }, 0 },
7185 { "lidt", { M }, 0 },
7189 static const struct dis386 three_byte_table[][256] = {
7191 /* THREE_BYTE_0F38 */
7194 { "pshufb", { MX, EM }, PREFIX_OPCODE },
7195 { "phaddw", { MX, EM }, PREFIX_OPCODE },
7196 { "phaddd", { MX, EM }, PREFIX_OPCODE },
7197 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
7198 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
7199 { "phsubw", { MX, EM }, PREFIX_OPCODE },
7200 { "phsubd", { MX, EM }, PREFIX_OPCODE },
7201 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
7203 { "psignb", { MX, EM }, PREFIX_OPCODE },
7204 { "psignw", { MX, EM }, PREFIX_OPCODE },
7205 { "psignd", { MX, EM }, PREFIX_OPCODE },
7206 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
7212 { PREFIX_TABLE (PREFIX_0F3810) },
7216 { PREFIX_TABLE (PREFIX_0F3814) },
7217 { PREFIX_TABLE (PREFIX_0F3815) },
7219 { PREFIX_TABLE (PREFIX_0F3817) },
7225 { "pabsb", { MX, EM }, PREFIX_OPCODE },
7226 { "pabsw", { MX, EM }, PREFIX_OPCODE },
7227 { "pabsd", { MX, EM }, PREFIX_OPCODE },
7230 { PREFIX_TABLE (PREFIX_0F3820) },
7231 { PREFIX_TABLE (PREFIX_0F3821) },
7232 { PREFIX_TABLE (PREFIX_0F3822) },
7233 { PREFIX_TABLE (PREFIX_0F3823) },
7234 { PREFIX_TABLE (PREFIX_0F3824) },
7235 { PREFIX_TABLE (PREFIX_0F3825) },
7239 { PREFIX_TABLE (PREFIX_0F3828) },
7240 { PREFIX_TABLE (PREFIX_0F3829) },
7241 { PREFIX_TABLE (PREFIX_0F382A) },
7242 { PREFIX_TABLE (PREFIX_0F382B) },
7248 { PREFIX_TABLE (PREFIX_0F3830) },
7249 { PREFIX_TABLE (PREFIX_0F3831) },
7250 { PREFIX_TABLE (PREFIX_0F3832) },
7251 { PREFIX_TABLE (PREFIX_0F3833) },
7252 { PREFIX_TABLE (PREFIX_0F3834) },
7253 { PREFIX_TABLE (PREFIX_0F3835) },
7255 { PREFIX_TABLE (PREFIX_0F3837) },
7257 { PREFIX_TABLE (PREFIX_0F3838) },
7258 { PREFIX_TABLE (PREFIX_0F3839) },
7259 { PREFIX_TABLE (PREFIX_0F383A) },
7260 { PREFIX_TABLE (PREFIX_0F383B) },
7261 { PREFIX_TABLE (PREFIX_0F383C) },
7262 { PREFIX_TABLE (PREFIX_0F383D) },
7263 { PREFIX_TABLE (PREFIX_0F383E) },
7264 { PREFIX_TABLE (PREFIX_0F383F) },
7266 { PREFIX_TABLE (PREFIX_0F3840) },
7267 { PREFIX_TABLE (PREFIX_0F3841) },
7338 { PREFIX_TABLE (PREFIX_0F3880) },
7339 { PREFIX_TABLE (PREFIX_0F3881) },
7340 { PREFIX_TABLE (PREFIX_0F3882) },
7419 { PREFIX_TABLE (PREFIX_0F38C8) },
7420 { PREFIX_TABLE (PREFIX_0F38C9) },
7421 { PREFIX_TABLE (PREFIX_0F38CA) },
7422 { PREFIX_TABLE (PREFIX_0F38CB) },
7423 { PREFIX_TABLE (PREFIX_0F38CC) },
7424 { PREFIX_TABLE (PREFIX_0F38CD) },
7426 { PREFIX_TABLE (PREFIX_0F38CF) },
7440 { PREFIX_TABLE (PREFIX_0F38DB) },
7441 { PREFIX_TABLE (PREFIX_0F38DC) },
7442 { PREFIX_TABLE (PREFIX_0F38DD) },
7443 { PREFIX_TABLE (PREFIX_0F38DE) },
7444 { PREFIX_TABLE (PREFIX_0F38DF) },
7464 { PREFIX_TABLE (PREFIX_0F38F0) },
7465 { PREFIX_TABLE (PREFIX_0F38F1) },
7469 { PREFIX_TABLE (PREFIX_0F38F5) },
7470 { PREFIX_TABLE (PREFIX_0F38F6) },
7473 { PREFIX_TABLE (PREFIX_0F38F8) },
7474 { PREFIX_TABLE (PREFIX_0F38F9) },
7482 /* THREE_BYTE_0F3A */
7494 { PREFIX_TABLE (PREFIX_0F3A08) },
7495 { PREFIX_TABLE (PREFIX_0F3A09) },
7496 { PREFIX_TABLE (PREFIX_0F3A0A) },
7497 { PREFIX_TABLE (PREFIX_0F3A0B) },
7498 { PREFIX_TABLE (PREFIX_0F3A0C) },
7499 { PREFIX_TABLE (PREFIX_0F3A0D) },
7500 { PREFIX_TABLE (PREFIX_0F3A0E) },
7501 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
7507 { PREFIX_TABLE (PREFIX_0F3A14) },
7508 { PREFIX_TABLE (PREFIX_0F3A15) },
7509 { PREFIX_TABLE (PREFIX_0F3A16) },
7510 { PREFIX_TABLE (PREFIX_0F3A17) },
7521 { PREFIX_TABLE (PREFIX_0F3A20) },
7522 { PREFIX_TABLE (PREFIX_0F3A21) },
7523 { PREFIX_TABLE (PREFIX_0F3A22) },
7557 { PREFIX_TABLE (PREFIX_0F3A40) },
7558 { PREFIX_TABLE (PREFIX_0F3A41) },
7559 { PREFIX_TABLE (PREFIX_0F3A42) },
7561 { PREFIX_TABLE (PREFIX_0F3A44) },
7593 { PREFIX_TABLE (PREFIX_0F3A60) },
7594 { PREFIX_TABLE (PREFIX_0F3A61) },
7595 { PREFIX_TABLE (PREFIX_0F3A62) },
7596 { PREFIX_TABLE (PREFIX_0F3A63) },
7714 { PREFIX_TABLE (PREFIX_0F3ACC) },
7716 { PREFIX_TABLE (PREFIX_0F3ACE) },
7717 { PREFIX_TABLE (PREFIX_0F3ACF) },
7735 { PREFIX_TABLE (PREFIX_0F3ADF) },
7775 static const struct dis386 xop_table[][256] = {
7928 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7929 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7930 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7938 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7939 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7946 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7947 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7948 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7956 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7957 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7961 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7962 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7965 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7983 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7995 { "vprotb", { XM, Vex_2src_1, Ib }, 0 },
7996 { "vprotw", { XM, Vex_2src_1, Ib }, 0 },
7997 { "vprotd", { XM, Vex_2src_1, Ib }, 0 },
7998 { "vprotq", { XM, Vex_2src_1, Ib }, 0 },
8008 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
8009 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
8010 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
8011 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
8044 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8045 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8046 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8047 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8071 { REG_TABLE (REG_XOP_TBM_01) },
8072 { REG_TABLE (REG_XOP_TBM_02) },
8090 { REG_TABLE (REG_XOP_LWPCB) },
8214 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8215 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8216 { "vfrczss", { XM, EXd }, 0 },
8217 { "vfrczsd", { XM, EXq }, 0 },
8232 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8233 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8234 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8235 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8236 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8237 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8238 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8239 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8241 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8242 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8243 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8244 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8287 { "vphaddbw", { XM, EXxmm }, 0 },
8288 { "vphaddbd", { XM, EXxmm }, 0 },
8289 { "vphaddbq", { XM, EXxmm }, 0 },
8292 { "vphaddwd", { XM, EXxmm }, 0 },
8293 { "vphaddwq", { XM, EXxmm }, 0 },
8298 { "vphadddq", { XM, EXxmm }, 0 },
8305 { "vphaddubw", { XM, EXxmm }, 0 },
8306 { "vphaddubd", { XM, EXxmm }, 0 },
8307 { "vphaddubq", { XM, EXxmm }, 0 },
8310 { "vphadduwd", { XM, EXxmm }, 0 },
8311 { "vphadduwq", { XM, EXxmm }, 0 },
8316 { "vphaddudq", { XM, EXxmm }, 0 },
8323 { "vphsubbw", { XM, EXxmm }, 0 },
8324 { "vphsubwd", { XM, EXxmm }, 0 },
8325 { "vphsubdq", { XM, EXxmm }, 0 },
8379 { "bextr", { Gv, Ev, Iq }, 0 },
8381 { REG_TABLE (REG_XOP_LWP) },
8651 static const struct dis386 vex_table[][256] = {
8673 { PREFIX_TABLE (PREFIX_VEX_0F10) },
8674 { PREFIX_TABLE (PREFIX_VEX_0F11) },
8675 { PREFIX_TABLE (PREFIX_VEX_0F12) },
8676 { MOD_TABLE (MOD_VEX_0F13) },
8677 { VEX_W_TABLE (VEX_W_0F14) },
8678 { VEX_W_TABLE (VEX_W_0F15) },
8679 { PREFIX_TABLE (PREFIX_VEX_0F16) },
8680 { MOD_TABLE (MOD_VEX_0F17) },
8700 { VEX_W_TABLE (VEX_W_0F28) },
8701 { VEX_W_TABLE (VEX_W_0F29) },
8702 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8703 { MOD_TABLE (MOD_VEX_0F2B) },
8704 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8705 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8706 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8707 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F41) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F42) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F44) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F45) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F46) },
8734 { PREFIX_TABLE (PREFIX_VEX_0F47) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8745 { MOD_TABLE (MOD_VEX_0F50) },
8746 { PREFIX_TABLE (PREFIX_VEX_0F51) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F52) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F53) },
8749 { "vandpX", { XM, Vex, EXx }, 0 },
8750 { "vandnpX", { XM, Vex, EXx }, 0 },
8751 { "vorpX", { XM, Vex, EXx }, 0 },
8752 { "vxorpX", { XM, Vex, EXx }, 0 },
8754 { PREFIX_TABLE (PREFIX_VEX_0F58) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F59) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F60) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F61) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F62) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F63) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F64) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F65) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F66) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F67) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F68) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F69) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8781 { PREFIX_TABLE (PREFIX_VEX_0F70) },
8782 { REG_TABLE (REG_VEX_0F71) },
8783 { REG_TABLE (REG_VEX_0F72) },
8784 { REG_TABLE (REG_VEX_0F73) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F74) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F75) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F76) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F77) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8795 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8797 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8817 { PREFIX_TABLE (PREFIX_VEX_0F90) },
8818 { PREFIX_TABLE (PREFIX_VEX_0F91) },
8819 { PREFIX_TABLE (PREFIX_VEX_0F92) },
8820 { PREFIX_TABLE (PREFIX_VEX_0F93) },
8826 { PREFIX_TABLE (PREFIX_VEX_0F98) },
8827 { PREFIX_TABLE (PREFIX_VEX_0F99) },
8850 { REG_TABLE (REG_VEX_0FAE) },
8873 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8875 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8876 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8877 { "vshufpX", { XM, Vex, EXx, Ib }, 0 },
8889 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8890 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8891 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8892 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8893 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8894 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8895 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8896 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8898 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8899 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8900 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8901 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8902 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8903 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8904 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8905 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8907 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8908 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8909 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8910 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8911 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8912 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8913 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8914 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8916 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8917 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8918 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8919 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8920 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8921 { PREFIX_TABLE (PREFIX_VEX_0FED) },
8922 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8923 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8925 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8926 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8927 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8928 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8929 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8930 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8931 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8932 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8934 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8935 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8936 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8937 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8938 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8939 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8940 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8956 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8957 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8959 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8960 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8961 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8962 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8967 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8973 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8974 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8975 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8977 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8978 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8979 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8982 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8983 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8984 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8985 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8986 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8987 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8991 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8992 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8993 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8994 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8995 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8996 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8997 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
9001 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
9002 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
9004 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
9005 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
9006 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
9009 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
9010 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
9011 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
9012 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
9013 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
9014 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
9015 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
9024 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9046 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9047 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9081 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9082 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9103 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9105 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9108 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9109 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9110 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9111 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9114 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9115 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9117 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9118 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9119 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9120 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9121 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9122 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9123 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9124 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9132 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9135 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9136 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9137 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9138 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9139 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9140 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9141 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9142 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9150 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9151 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9153 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9154 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9155 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9156 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9157 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9158 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9159 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9160 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9178 { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
9192 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9193 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9194 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9195 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9196 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9218 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9219 { REG_TABLE (REG_VEX_0F38F3) },
9221 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9222 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9223 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9237 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9238 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9239 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9241 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9242 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9243 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9246 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9247 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9248 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9249 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9250 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9251 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9252 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9253 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9259 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9260 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9261 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9262 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9264 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9265 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9269 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9273 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9274 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9275 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9291 { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9292 { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9293 { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9294 { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9300 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9301 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9309 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9310 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9311 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9313 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9315 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9318 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9319 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9320 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9321 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9322 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9340 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9341 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9342 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9343 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9345 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9346 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9347 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9348 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9354 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9355 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9356 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9357 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9358 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9359 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9360 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9361 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9372 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9373 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9374 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9375 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9376 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9377 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9378 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9379 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9468 { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9469 { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9487 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9507 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9527 #define NEED_OPCODE_TABLE
9528 #include "i386-dis-evex.h"
9529 #undef NEED_OPCODE_TABLE
9530 static const struct dis386 vex_len_table[][2] = {
9531 /* VEX_LEN_0F10_P_1 */
9533 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9534 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9537 /* VEX_LEN_0F10_P_3 */
9539 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9540 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9543 /* VEX_LEN_0F11_P_1 */
9545 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9546 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9549 /* VEX_LEN_0F11_P_3 */
9551 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9552 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9555 /* VEX_LEN_0F12_P_0_M_0 */
9557 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9560 /* VEX_LEN_0F12_P_0_M_1 */
9562 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9565 /* VEX_LEN_0F12_P_2 */
9567 { VEX_W_TABLE (VEX_W_0F12_P_2) },
9570 /* VEX_LEN_0F13_M_0 */
9572 { VEX_W_TABLE (VEX_W_0F13_M_0) },
9575 /* VEX_LEN_0F16_P_0_M_0 */
9577 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9580 /* VEX_LEN_0F16_P_0_M_1 */
9582 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9585 /* VEX_LEN_0F16_P_2 */
9587 { VEX_W_TABLE (VEX_W_0F16_P_2) },
9590 /* VEX_LEN_0F17_M_0 */
9592 { VEX_W_TABLE (VEX_W_0F17_M_0) },
9595 /* VEX_LEN_0F2A_P_1 */
9597 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9598 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9601 /* VEX_LEN_0F2A_P_3 */
9603 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9604 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9607 /* VEX_LEN_0F2C_P_1 */
9609 { "vcvttss2si", { Gv, EXdScalar }, 0 },
9610 { "vcvttss2si", { Gv, EXdScalar }, 0 },
9613 /* VEX_LEN_0F2C_P_3 */
9615 { "vcvttsd2si", { Gv, EXqScalar }, 0 },
9616 { "vcvttsd2si", { Gv, EXqScalar }, 0 },
9619 /* VEX_LEN_0F2D_P_1 */
9621 { "vcvtss2si", { Gv, EXdScalar }, 0 },
9622 { "vcvtss2si", { Gv, EXdScalar }, 0 },
9625 /* VEX_LEN_0F2D_P_3 */
9627 { "vcvtsd2si", { Gv, EXqScalar }, 0 },
9628 { "vcvtsd2si", { Gv, EXqScalar }, 0 },
9631 /* VEX_LEN_0F2E_P_0 */
9633 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9634 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9637 /* VEX_LEN_0F2E_P_2 */
9639 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9640 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9643 /* VEX_LEN_0F2F_P_0 */
9645 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9646 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9649 /* VEX_LEN_0F2F_P_2 */
9651 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9652 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9655 /* VEX_LEN_0F41_P_0 */
9658 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9660 /* VEX_LEN_0F41_P_2 */
9663 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9665 /* VEX_LEN_0F42_P_0 */
9668 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9670 /* VEX_LEN_0F42_P_2 */
9673 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9675 /* VEX_LEN_0F44_P_0 */
9677 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9679 /* VEX_LEN_0F44_P_2 */
9681 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9683 /* VEX_LEN_0F45_P_0 */
9686 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9688 /* VEX_LEN_0F45_P_2 */
9691 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9693 /* VEX_LEN_0F46_P_0 */
9696 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9698 /* VEX_LEN_0F46_P_2 */
9701 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9703 /* VEX_LEN_0F47_P_0 */
9706 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9708 /* VEX_LEN_0F47_P_2 */
9711 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9713 /* VEX_LEN_0F4A_P_0 */
9716 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9718 /* VEX_LEN_0F4A_P_2 */
9721 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9723 /* VEX_LEN_0F4B_P_0 */
9726 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9728 /* VEX_LEN_0F4B_P_2 */
9731 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9734 /* VEX_LEN_0F51_P_1 */
9736 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9737 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9740 /* VEX_LEN_0F51_P_3 */
9742 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9743 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9746 /* VEX_LEN_0F52_P_1 */
9748 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9749 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9752 /* VEX_LEN_0F53_P_1 */
9754 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9755 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9758 /* VEX_LEN_0F58_P_1 */
9760 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9761 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9764 /* VEX_LEN_0F58_P_3 */
9766 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9767 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9770 /* VEX_LEN_0F59_P_1 */
9772 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9773 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9776 /* VEX_LEN_0F59_P_3 */
9778 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9779 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9782 /* VEX_LEN_0F5A_P_1 */
9784 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9785 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9788 /* VEX_LEN_0F5A_P_3 */
9790 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9791 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9794 /* VEX_LEN_0F5C_P_1 */
9796 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9797 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9800 /* VEX_LEN_0F5C_P_3 */
9802 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9803 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9806 /* VEX_LEN_0F5D_P_1 */
9808 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9809 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9812 /* VEX_LEN_0F5D_P_3 */
9814 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9815 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9818 /* VEX_LEN_0F5E_P_1 */
9820 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9821 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9824 /* VEX_LEN_0F5E_P_3 */
9826 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9827 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9830 /* VEX_LEN_0F5F_P_1 */
9832 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9833 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9836 /* VEX_LEN_0F5F_P_3 */
9838 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9839 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9842 /* VEX_LEN_0F6E_P_2 */
9844 { "vmovK", { XMScalar, Edq }, 0 },
9845 { "vmovK", { XMScalar, Edq }, 0 },
9848 /* VEX_LEN_0F7E_P_1 */
9850 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9851 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9854 /* VEX_LEN_0F7E_P_2 */
9856 { "vmovK", { Edq, XMScalar }, 0 },
9857 { "vmovK", { Edq, XMScalar }, 0 },
9860 /* VEX_LEN_0F90_P_0 */
9862 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9865 /* VEX_LEN_0F90_P_2 */
9867 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9870 /* VEX_LEN_0F91_P_0 */
9872 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9875 /* VEX_LEN_0F91_P_2 */
9877 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9880 /* VEX_LEN_0F92_P_0 */
9882 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9885 /* VEX_LEN_0F92_P_2 */
9887 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9890 /* VEX_LEN_0F92_P_3 */
9892 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9895 /* VEX_LEN_0F93_P_0 */
9897 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9900 /* VEX_LEN_0F93_P_2 */
9902 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9905 /* VEX_LEN_0F93_P_3 */
9907 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9910 /* VEX_LEN_0F98_P_0 */
9912 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9915 /* VEX_LEN_0F98_P_2 */
9917 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9920 /* VEX_LEN_0F99_P_0 */
9922 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9925 /* VEX_LEN_0F99_P_2 */
9927 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9930 /* VEX_LEN_0FAE_R_2_M_0 */
9932 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9935 /* VEX_LEN_0FAE_R_3_M_0 */
9937 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9940 /* VEX_LEN_0FC2_P_1 */
9942 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9943 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9946 /* VEX_LEN_0FC2_P_3 */
9948 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9949 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9952 /* VEX_LEN_0FC4_P_2 */
9954 { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9957 /* VEX_LEN_0FC5_P_2 */
9959 { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9962 /* VEX_LEN_0FD6_P_2 */
9964 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9965 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9968 /* VEX_LEN_0FF7_P_2 */
9970 { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9973 /* VEX_LEN_0F3816_P_2 */
9976 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9979 /* VEX_LEN_0F3819_P_2 */
9982 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9985 /* VEX_LEN_0F381A_P_2_M_0 */
9988 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9991 /* VEX_LEN_0F3836_P_2 */
9994 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9997 /* VEX_LEN_0F3841_P_2 */
9999 { VEX_W_TABLE (VEX_W_0F3841_P_2) },
10002 /* VEX_LEN_0F385A_P_2_M_0 */
10005 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
10008 /* VEX_LEN_0F38DB_P_2 */
10010 { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
10013 /* VEX_LEN_0F38F2_P_0 */
10015 { "andnS", { Gdq, VexGdq, Edq }, 0 },
10018 /* VEX_LEN_0F38F3_R_1_P_0 */
10020 { "blsrS", { VexGdq, Edq }, 0 },
10023 /* VEX_LEN_0F38F3_R_2_P_0 */
10025 { "blsmskS", { VexGdq, Edq }, 0 },
10028 /* VEX_LEN_0F38F3_R_3_P_0 */
10030 { "blsiS", { VexGdq, Edq }, 0 },
10033 /* VEX_LEN_0F38F5_P_0 */
10035 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
10038 /* VEX_LEN_0F38F5_P_1 */
10040 { "pextS", { Gdq, VexGdq, Edq }, 0 },
10043 /* VEX_LEN_0F38F5_P_3 */
10045 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
10048 /* VEX_LEN_0F38F6_P_3 */
10050 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
10053 /* VEX_LEN_0F38F7_P_0 */
10055 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
10058 /* VEX_LEN_0F38F7_P_1 */
10060 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
10063 /* VEX_LEN_0F38F7_P_2 */
10065 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
10068 /* VEX_LEN_0F38F7_P_3 */
10070 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
10073 /* VEX_LEN_0F3A00_P_2 */
10076 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10079 /* VEX_LEN_0F3A01_P_2 */
10082 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10085 /* VEX_LEN_0F3A06_P_2 */
10088 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10091 /* VEX_LEN_0F3A0A_P_2 */
10093 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10094 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10097 /* VEX_LEN_0F3A0B_P_2 */
10099 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10100 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10103 /* VEX_LEN_0F3A14_P_2 */
10105 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10108 /* VEX_LEN_0F3A15_P_2 */
10110 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10113 /* VEX_LEN_0F3A16_P_2 */
10115 { "vpextrK", { Edq, XM, Ib }, 0 },
10118 /* VEX_LEN_0F3A17_P_2 */
10120 { "vextractps", { Edqd, XM, Ib }, 0 },
10123 /* VEX_LEN_0F3A18_P_2 */
10126 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10129 /* VEX_LEN_0F3A19_P_2 */
10132 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10135 /* VEX_LEN_0F3A20_P_2 */
10137 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10140 /* VEX_LEN_0F3A21_P_2 */
10142 { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10145 /* VEX_LEN_0F3A22_P_2 */
10147 { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 },
10150 /* VEX_LEN_0F3A30_P_2 */
10152 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10155 /* VEX_LEN_0F3A31_P_2 */
10157 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10160 /* VEX_LEN_0F3A32_P_2 */
10162 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10165 /* VEX_LEN_0F3A33_P_2 */
10167 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10170 /* VEX_LEN_0F3A38_P_2 */
10173 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10176 /* VEX_LEN_0F3A39_P_2 */
10179 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10182 /* VEX_LEN_0F3A41_P_2 */
10184 { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10187 /* VEX_LEN_0F3A46_P_2 */
10190 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10193 /* VEX_LEN_0F3A60_P_2 */
10195 { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10198 /* VEX_LEN_0F3A61_P_2 */
10200 { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10203 /* VEX_LEN_0F3A62_P_2 */
10205 { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10208 /* VEX_LEN_0F3A63_P_2 */
10210 { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10213 /* VEX_LEN_0F3A6A_P_2 */
10215 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10218 /* VEX_LEN_0F3A6B_P_2 */
10220 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10223 /* VEX_LEN_0F3A6E_P_2 */
10225 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10228 /* VEX_LEN_0F3A6F_P_2 */
10230 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10233 /* VEX_LEN_0F3A7A_P_2 */
10235 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10238 /* VEX_LEN_0F3A7B_P_2 */
10240 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10243 /* VEX_LEN_0F3A7E_P_2 */
10245 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10248 /* VEX_LEN_0F3A7F_P_2 */
10250 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10253 /* VEX_LEN_0F3ADF_P_2 */
10255 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10258 /* VEX_LEN_0F3AF0_P_3 */
10260 { "rorxS", { Gdq, Edq, Ib }, 0 },
10263 /* VEX_LEN_0FXOP_08_CC */
10265 { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 },
10268 /* VEX_LEN_0FXOP_08_CD */
10270 { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 },
10273 /* VEX_LEN_0FXOP_08_CE */
10275 { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 },
10278 /* VEX_LEN_0FXOP_08_CF */
10280 { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 },
10283 /* VEX_LEN_0FXOP_08_EC */
10285 { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 },
10288 /* VEX_LEN_0FXOP_08_ED */
10290 { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 },
10293 /* VEX_LEN_0FXOP_08_EE */
10295 { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 },
10298 /* VEX_LEN_0FXOP_08_EF */
10300 { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 },
10303 /* VEX_LEN_0FXOP_09_80 */
10305 { "vfrczps", { XM, EXxmm }, 0 },
10306 { "vfrczps", { XM, EXymmq }, 0 },
10309 /* VEX_LEN_0FXOP_09_81 */
10311 { "vfrczpd", { XM, EXxmm }, 0 },
10312 { "vfrczpd", { XM, EXymmq }, 0 },
10316 static const struct dis386 vex_w_table[][2] = {
10318 /* VEX_W_0F10_P_0 */
10319 { "vmovups", { XM, EXx }, 0 },
10322 /* VEX_W_0F10_P_1 */
10323 { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
10326 /* VEX_W_0F10_P_2 */
10327 { "vmovupd", { XM, EXx }, 0 },
10330 /* VEX_W_0F10_P_3 */
10331 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
10334 /* VEX_W_0F11_P_0 */
10335 { "vmovups", { EXxS, XM }, 0 },
10338 /* VEX_W_0F11_P_1 */
10339 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10342 /* VEX_W_0F11_P_2 */
10343 { "vmovupd", { EXxS, XM }, 0 },
10346 /* VEX_W_0F11_P_3 */
10347 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10350 /* VEX_W_0F12_P_0_M_0 */
10351 { "vmovlps", { XM, Vex128, EXq }, 0 },
10354 /* VEX_W_0F12_P_0_M_1 */
10355 { "vmovhlps", { XM, Vex128, EXq }, 0 },
10358 /* VEX_W_0F12_P_1 */
10359 { "vmovsldup", { XM, EXx }, 0 },
10362 /* VEX_W_0F12_P_2 */
10363 { "vmovlpd", { XM, Vex128, EXq }, 0 },
10366 /* VEX_W_0F12_P_3 */
10367 { "vmovddup", { XM, EXymmq }, 0 },
10370 /* VEX_W_0F13_M_0 */
10371 { "vmovlpX", { EXq, XM }, 0 },
10375 { "vunpcklpX", { XM, Vex, EXx }, 0 },
10379 { "vunpckhpX", { XM, Vex, EXx }, 0 },
10382 /* VEX_W_0F16_P_0_M_0 */
10383 { "vmovhps", { XM, Vex128, EXq }, 0 },
10386 /* VEX_W_0F16_P_0_M_1 */
10387 { "vmovlhps", { XM, Vex128, EXq }, 0 },
10390 /* VEX_W_0F16_P_1 */
10391 { "vmovshdup", { XM, EXx }, 0 },
10394 /* VEX_W_0F16_P_2 */
10395 { "vmovhpd", { XM, Vex128, EXq }, 0 },
10398 /* VEX_W_0F17_M_0 */
10399 { "vmovhpX", { EXq, XM }, 0 },
10403 { "vmovapX", { XM, EXx }, 0 },
10407 { "vmovapX", { EXxS, XM }, 0 },
10410 /* VEX_W_0F2B_M_0 */
10411 { "vmovntpX", { Mx, XM }, 0 },
10414 /* VEX_W_0F2E_P_0 */
10415 { "vucomiss", { XMScalar, EXdScalar }, 0 },
10418 /* VEX_W_0F2E_P_2 */
10419 { "vucomisd", { XMScalar, EXqScalar }, 0 },
10422 /* VEX_W_0F2F_P_0 */
10423 { "vcomiss", { XMScalar, EXdScalar }, 0 },
10426 /* VEX_W_0F2F_P_2 */
10427 { "vcomisd", { XMScalar, EXqScalar }, 0 },
10430 /* VEX_W_0F41_P_0_LEN_1 */
10431 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10432 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10435 /* VEX_W_0F41_P_2_LEN_1 */
10436 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10437 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10440 /* VEX_W_0F42_P_0_LEN_1 */
10441 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10442 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10445 /* VEX_W_0F42_P_2_LEN_1 */
10446 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10447 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10450 /* VEX_W_0F44_P_0_LEN_0 */
10451 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10452 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10455 /* VEX_W_0F44_P_2_LEN_0 */
10456 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10457 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10460 /* VEX_W_0F45_P_0_LEN_1 */
10461 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10462 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10465 /* VEX_W_0F45_P_2_LEN_1 */
10466 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10467 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10470 /* VEX_W_0F46_P_0_LEN_1 */
10471 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10472 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10475 /* VEX_W_0F46_P_2_LEN_1 */
10476 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10477 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10480 /* VEX_W_0F47_P_0_LEN_1 */
10481 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10482 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10485 /* VEX_W_0F47_P_2_LEN_1 */
10486 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10487 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10490 /* VEX_W_0F4A_P_0_LEN_1 */
10491 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10492 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10495 /* VEX_W_0F4A_P_2_LEN_1 */
10496 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10497 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10500 /* VEX_W_0F4B_P_0_LEN_1 */
10501 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10502 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10505 /* VEX_W_0F4B_P_2_LEN_1 */
10506 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10509 /* VEX_W_0F50_M_0 */
10510 { "vmovmskpX", { Gdq, XS }, 0 },
10513 /* VEX_W_0F51_P_0 */
10514 { "vsqrtps", { XM, EXx }, 0 },
10517 /* VEX_W_0F51_P_1 */
10518 { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10521 /* VEX_W_0F51_P_2 */
10522 { "vsqrtpd", { XM, EXx }, 0 },
10525 /* VEX_W_0F51_P_3 */
10526 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10529 /* VEX_W_0F52_P_0 */
10530 { "vrsqrtps", { XM, EXx }, 0 },
10533 /* VEX_W_0F52_P_1 */
10534 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10537 /* VEX_W_0F53_P_0 */
10538 { "vrcpps", { XM, EXx }, 0 },
10541 /* VEX_W_0F53_P_1 */
10542 { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
10545 /* VEX_W_0F58_P_0 */
10546 { "vaddps", { XM, Vex, EXx }, 0 },
10549 /* VEX_W_0F58_P_1 */
10550 { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
10553 /* VEX_W_0F58_P_2 */
10554 { "vaddpd", { XM, Vex, EXx }, 0 },
10557 /* VEX_W_0F58_P_3 */
10558 { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10561 /* VEX_W_0F59_P_0 */
10562 { "vmulps", { XM, Vex, EXx }, 0 },
10565 /* VEX_W_0F59_P_1 */
10566 { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
10569 /* VEX_W_0F59_P_2 */
10570 { "vmulpd", { XM, Vex, EXx }, 0 },
10573 /* VEX_W_0F59_P_3 */
10574 { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10577 /* VEX_W_0F5A_P_0 */
10578 { "vcvtps2pd", { XM, EXxmmq }, 0 },
10581 /* VEX_W_0F5A_P_1 */
10582 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
10585 /* VEX_W_0F5A_P_3 */
10586 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
10589 /* VEX_W_0F5B_P_0 */
10590 { "vcvtdq2ps", { XM, EXx }, 0 },
10593 /* VEX_W_0F5B_P_1 */
10594 { "vcvttps2dq", { XM, EXx }, 0 },
10597 /* VEX_W_0F5B_P_2 */
10598 { "vcvtps2dq", { XM, EXx }, 0 },
10601 /* VEX_W_0F5C_P_0 */
10602 { "vsubps", { XM, Vex, EXx }, 0 },
10605 /* VEX_W_0F5C_P_1 */
10606 { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
10609 /* VEX_W_0F5C_P_2 */
10610 { "vsubpd", { XM, Vex, EXx }, 0 },
10613 /* VEX_W_0F5C_P_3 */
10614 { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10617 /* VEX_W_0F5D_P_0 */
10618 { "vminps", { XM, Vex, EXx }, 0 },
10621 /* VEX_W_0F5D_P_1 */
10622 { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
10625 /* VEX_W_0F5D_P_2 */
10626 { "vminpd", { XM, Vex, EXx }, 0 },
10629 /* VEX_W_0F5D_P_3 */
10630 { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10633 /* VEX_W_0F5E_P_0 */
10634 { "vdivps", { XM, Vex, EXx }, 0 },
10637 /* VEX_W_0F5E_P_1 */
10638 { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
10641 /* VEX_W_0F5E_P_2 */
10642 { "vdivpd", { XM, Vex, EXx }, 0 },
10645 /* VEX_W_0F5E_P_3 */
10646 { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10649 /* VEX_W_0F5F_P_0 */
10650 { "vmaxps", { XM, Vex, EXx }, 0 },
10653 /* VEX_W_0F5F_P_1 */
10654 { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
10657 /* VEX_W_0F5F_P_2 */
10658 { "vmaxpd", { XM, Vex, EXx }, 0 },
10661 /* VEX_W_0F5F_P_3 */
10662 { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10665 /* VEX_W_0F60_P_2 */
10666 { "vpunpcklbw", { XM, Vex, EXx }, 0 },
10669 /* VEX_W_0F61_P_2 */
10670 { "vpunpcklwd", { XM, Vex, EXx }, 0 },
10673 /* VEX_W_0F62_P_2 */
10674 { "vpunpckldq", { XM, Vex, EXx }, 0 },
10677 /* VEX_W_0F63_P_2 */
10678 { "vpacksswb", { XM, Vex, EXx }, 0 },
10681 /* VEX_W_0F64_P_2 */
10682 { "vpcmpgtb", { XM, Vex, EXx }, 0 },
10685 /* VEX_W_0F65_P_2 */
10686 { "vpcmpgtw", { XM, Vex, EXx }, 0 },
10689 /* VEX_W_0F66_P_2 */
10690 { "vpcmpgtd", { XM, Vex, EXx }, 0 },
10693 /* VEX_W_0F67_P_2 */
10694 { "vpackuswb", { XM, Vex, EXx }, 0 },
10697 /* VEX_W_0F68_P_2 */
10698 { "vpunpckhbw", { XM, Vex, EXx }, 0 },
10701 /* VEX_W_0F69_P_2 */
10702 { "vpunpckhwd", { XM, Vex, EXx }, 0 },
10705 /* VEX_W_0F6A_P_2 */
10706 { "vpunpckhdq", { XM, Vex, EXx }, 0 },
10709 /* VEX_W_0F6B_P_2 */
10710 { "vpackssdw", { XM, Vex, EXx }, 0 },
10713 /* VEX_W_0F6C_P_2 */
10714 { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
10717 /* VEX_W_0F6D_P_2 */
10718 { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
10721 /* VEX_W_0F6F_P_1 */
10722 { "vmovdqu", { XM, EXx }, 0 },
10725 /* VEX_W_0F6F_P_2 */
10726 { "vmovdqa", { XM, EXx }, 0 },
10729 /* VEX_W_0F70_P_1 */
10730 { "vpshufhw", { XM, EXx, Ib }, 0 },
10733 /* VEX_W_0F70_P_2 */
10734 { "vpshufd", { XM, EXx, Ib }, 0 },
10737 /* VEX_W_0F70_P_3 */
10738 { "vpshuflw", { XM, EXx, Ib }, 0 },
10741 /* VEX_W_0F71_R_2_P_2 */
10742 { "vpsrlw", { Vex, XS, Ib }, 0 },
10745 /* VEX_W_0F71_R_4_P_2 */
10746 { "vpsraw", { Vex, XS, Ib }, 0 },
10749 /* VEX_W_0F71_R_6_P_2 */
10750 { "vpsllw", { Vex, XS, Ib }, 0 },
10753 /* VEX_W_0F72_R_2_P_2 */
10754 { "vpsrld", { Vex, XS, Ib }, 0 },
10757 /* VEX_W_0F72_R_4_P_2 */
10758 { "vpsrad", { Vex, XS, Ib }, 0 },
10761 /* VEX_W_0F72_R_6_P_2 */
10762 { "vpslld", { Vex, XS, Ib }, 0 },
10765 /* VEX_W_0F73_R_2_P_2 */
10766 { "vpsrlq", { Vex, XS, Ib }, 0 },
10769 /* VEX_W_0F73_R_3_P_2 */
10770 { "vpsrldq", { Vex, XS, Ib }, 0 },
10773 /* VEX_W_0F73_R_6_P_2 */
10774 { "vpsllq", { Vex, XS, Ib }, 0 },
10777 /* VEX_W_0F73_R_7_P_2 */
10778 { "vpslldq", { Vex, XS, Ib }, 0 },
10781 /* VEX_W_0F74_P_2 */
10782 { "vpcmpeqb", { XM, Vex, EXx }, 0 },
10785 /* VEX_W_0F75_P_2 */
10786 { "vpcmpeqw", { XM, Vex, EXx }, 0 },
10789 /* VEX_W_0F76_P_2 */
10790 { "vpcmpeqd", { XM, Vex, EXx }, 0 },
10793 /* VEX_W_0F77_P_0 */
10794 { "", { VZERO }, 0 },
10797 /* VEX_W_0F7C_P_2 */
10798 { "vhaddpd", { XM, Vex, EXx }, 0 },
10801 /* VEX_W_0F7C_P_3 */
10802 { "vhaddps", { XM, Vex, EXx }, 0 },
10805 /* VEX_W_0F7D_P_2 */
10806 { "vhsubpd", { XM, Vex, EXx }, 0 },
10809 /* VEX_W_0F7D_P_3 */
10810 { "vhsubps", { XM, Vex, EXx }, 0 },
10813 /* VEX_W_0F7E_P_1 */
10814 { "vmovq", { XMScalar, EXqScalar }, 0 },
10817 /* VEX_W_0F7F_P_1 */
10818 { "vmovdqu", { EXxS, XM }, 0 },
10821 /* VEX_W_0F7F_P_2 */
10822 { "vmovdqa", { EXxS, XM }, 0 },
10825 /* VEX_W_0F90_P_0_LEN_0 */
10826 { "kmovw", { MaskG, MaskE }, 0 },
10827 { "kmovq", { MaskG, MaskE }, 0 },
10830 /* VEX_W_0F90_P_2_LEN_0 */
10831 { "kmovb", { MaskG, MaskBDE }, 0 },
10832 { "kmovd", { MaskG, MaskBDE }, 0 },
10835 /* VEX_W_0F91_P_0_LEN_0 */
10836 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10837 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10840 /* VEX_W_0F91_P_2_LEN_0 */
10841 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10842 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10845 /* VEX_W_0F92_P_0_LEN_0 */
10846 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10849 /* VEX_W_0F92_P_2_LEN_0 */
10850 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10853 /* VEX_W_0F92_P_3_LEN_0 */
10854 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10855 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10858 /* VEX_W_0F93_P_0_LEN_0 */
10859 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10862 /* VEX_W_0F93_P_2_LEN_0 */
10863 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10866 /* VEX_W_0F93_P_3_LEN_0 */
10867 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10868 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10871 /* VEX_W_0F98_P_0_LEN_0 */
10872 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10873 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10876 /* VEX_W_0F98_P_2_LEN_0 */
10877 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10878 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10881 /* VEX_W_0F99_P_0_LEN_0 */
10882 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10883 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10886 /* VEX_W_0F99_P_2_LEN_0 */
10887 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10888 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10891 /* VEX_W_0FAE_R_2_M_0 */
10892 { "vldmxcsr", { Md }, 0 },
10895 /* VEX_W_0FAE_R_3_M_0 */
10896 { "vstmxcsr", { Md }, 0 },
10899 /* VEX_W_0FC2_P_0 */
10900 { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
10903 /* VEX_W_0FC2_P_1 */
10904 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10907 /* VEX_W_0FC2_P_2 */
10908 { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
10911 /* VEX_W_0FC2_P_3 */
10912 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10915 /* VEX_W_0FC4_P_2 */
10916 { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
10919 /* VEX_W_0FC5_P_2 */
10920 { "vpextrw", { Gdq, XS, Ib }, 0 },
10923 /* VEX_W_0FD0_P_2 */
10924 { "vaddsubpd", { XM, Vex, EXx }, 0 },
10927 /* VEX_W_0FD0_P_3 */
10928 { "vaddsubps", { XM, Vex, EXx }, 0 },
10931 /* VEX_W_0FD1_P_2 */
10932 { "vpsrlw", { XM, Vex, EXxmm }, 0 },
10935 /* VEX_W_0FD2_P_2 */
10936 { "vpsrld", { XM, Vex, EXxmm }, 0 },
10939 /* VEX_W_0FD3_P_2 */
10940 { "vpsrlq", { XM, Vex, EXxmm }, 0 },
10943 /* VEX_W_0FD4_P_2 */
10944 { "vpaddq", { XM, Vex, EXx }, 0 },
10947 /* VEX_W_0FD5_P_2 */
10948 { "vpmullw", { XM, Vex, EXx }, 0 },
10951 /* VEX_W_0FD6_P_2 */
10952 { "vmovq", { EXqScalarS, XMScalar }, 0 },
10955 /* VEX_W_0FD7_P_2_M_1 */
10956 { "vpmovmskb", { Gdq, XS }, 0 },
10959 /* VEX_W_0FD8_P_2 */
10960 { "vpsubusb", { XM, Vex, EXx }, 0 },
10963 /* VEX_W_0FD9_P_2 */
10964 { "vpsubusw", { XM, Vex, EXx }, 0 },
10967 /* VEX_W_0FDA_P_2 */
10968 { "vpminub", { XM, Vex, EXx }, 0 },
10971 /* VEX_W_0FDB_P_2 */
10972 { "vpand", { XM, Vex, EXx }, 0 },
10975 /* VEX_W_0FDC_P_2 */
10976 { "vpaddusb", { XM, Vex, EXx }, 0 },
10979 /* VEX_W_0FDD_P_2 */
10980 { "vpaddusw", { XM, Vex, EXx }, 0 },
10983 /* VEX_W_0FDE_P_2 */
10984 { "vpmaxub", { XM, Vex, EXx }, 0 },
10987 /* VEX_W_0FDF_P_2 */
10988 { "vpandn", { XM, Vex, EXx }, 0 },
10991 /* VEX_W_0FE0_P_2 */
10992 { "vpavgb", { XM, Vex, EXx }, 0 },
10995 /* VEX_W_0FE1_P_2 */
10996 { "vpsraw", { XM, Vex, EXxmm }, 0 },
10999 /* VEX_W_0FE2_P_2 */
11000 { "vpsrad", { XM, Vex, EXxmm }, 0 },
11003 /* VEX_W_0FE3_P_2 */
11004 { "vpavgw", { XM, Vex, EXx }, 0 },
11007 /* VEX_W_0FE4_P_2 */
11008 { "vpmulhuw", { XM, Vex, EXx }, 0 },
11011 /* VEX_W_0FE5_P_2 */
11012 { "vpmulhw", { XM, Vex, EXx }, 0 },
11015 /* VEX_W_0FE6_P_1 */
11016 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
11019 /* VEX_W_0FE6_P_2 */
11020 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
11023 /* VEX_W_0FE6_P_3 */
11024 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
11027 /* VEX_W_0FE7_P_2_M_0 */
11028 { "vmovntdq", { Mx, XM }, 0 },
11031 /* VEX_W_0FE8_P_2 */
11032 { "vpsubsb", { XM, Vex, EXx }, 0 },
11035 /* VEX_W_0FE9_P_2 */
11036 { "vpsubsw", { XM, Vex, EXx }, 0 },
11039 /* VEX_W_0FEA_P_2 */
11040 { "vpminsw", { XM, Vex, EXx }, 0 },
11043 /* VEX_W_0FEB_P_2 */
11044 { "vpor", { XM, Vex, EXx }, 0 },
11047 /* VEX_W_0FEC_P_2 */
11048 { "vpaddsb", { XM, Vex, EXx }, 0 },
11051 /* VEX_W_0FED_P_2 */
11052 { "vpaddsw", { XM, Vex, EXx }, 0 },
11055 /* VEX_W_0FEE_P_2 */
11056 { "vpmaxsw", { XM, Vex, EXx }, 0 },
11059 /* VEX_W_0FEF_P_2 */
11060 { "vpxor", { XM, Vex, EXx }, 0 },
11063 /* VEX_W_0FF0_P_3_M_0 */
11064 { "vlddqu", { XM, M }, 0 },
11067 /* VEX_W_0FF1_P_2 */
11068 { "vpsllw", { XM, Vex, EXxmm }, 0 },
11071 /* VEX_W_0FF2_P_2 */
11072 { "vpslld", { XM, Vex, EXxmm }, 0 },
11075 /* VEX_W_0FF3_P_2 */
11076 { "vpsllq", { XM, Vex, EXxmm }, 0 },
11079 /* VEX_W_0FF4_P_2 */
11080 { "vpmuludq", { XM, Vex, EXx }, 0 },
11083 /* VEX_W_0FF5_P_2 */
11084 { "vpmaddwd", { XM, Vex, EXx }, 0 },
11087 /* VEX_W_0FF6_P_2 */
11088 { "vpsadbw", { XM, Vex, EXx }, 0 },
11091 /* VEX_W_0FF7_P_2 */
11092 { "vmaskmovdqu", { XM, XS }, 0 },
11095 /* VEX_W_0FF8_P_2 */
11096 { "vpsubb", { XM, Vex, EXx }, 0 },
11099 /* VEX_W_0FF9_P_2 */
11100 { "vpsubw", { XM, Vex, EXx }, 0 },
11103 /* VEX_W_0FFA_P_2 */
11104 { "vpsubd", { XM, Vex, EXx }, 0 },
11107 /* VEX_W_0FFB_P_2 */
11108 { "vpsubq", { XM, Vex, EXx }, 0 },
11111 /* VEX_W_0FFC_P_2 */
11112 { "vpaddb", { XM, Vex, EXx }, 0 },
11115 /* VEX_W_0FFD_P_2 */
11116 { "vpaddw", { XM, Vex, EXx }, 0 },
11119 /* VEX_W_0FFE_P_2 */
11120 { "vpaddd", { XM, Vex, EXx }, 0 },
11123 /* VEX_W_0F3800_P_2 */
11124 { "vpshufb", { XM, Vex, EXx }, 0 },
11127 /* VEX_W_0F3801_P_2 */
11128 { "vphaddw", { XM, Vex, EXx }, 0 },
11131 /* VEX_W_0F3802_P_2 */
11132 { "vphaddd", { XM, Vex, EXx }, 0 },
11135 /* VEX_W_0F3803_P_2 */
11136 { "vphaddsw", { XM, Vex, EXx }, 0 },
11139 /* VEX_W_0F3804_P_2 */
11140 { "vpmaddubsw", { XM, Vex, EXx }, 0 },
11143 /* VEX_W_0F3805_P_2 */
11144 { "vphsubw", { XM, Vex, EXx }, 0 },
11147 /* VEX_W_0F3806_P_2 */
11148 { "vphsubd", { XM, Vex, EXx }, 0 },
11151 /* VEX_W_0F3807_P_2 */
11152 { "vphsubsw", { XM, Vex, EXx }, 0 },
11155 /* VEX_W_0F3808_P_2 */
11156 { "vpsignb", { XM, Vex, EXx }, 0 },
11159 /* VEX_W_0F3809_P_2 */
11160 { "vpsignw", { XM, Vex, EXx }, 0 },
11163 /* VEX_W_0F380A_P_2 */
11164 { "vpsignd", { XM, Vex, EXx }, 0 },
11167 /* VEX_W_0F380B_P_2 */
11168 { "vpmulhrsw", { XM, Vex, EXx }, 0 },
11171 /* VEX_W_0F380C_P_2 */
11172 { "vpermilps", { XM, Vex, EXx }, 0 },
11175 /* VEX_W_0F380D_P_2 */
11176 { "vpermilpd", { XM, Vex, EXx }, 0 },
11179 /* VEX_W_0F380E_P_2 */
11180 { "vtestps", { XM, EXx }, 0 },
11183 /* VEX_W_0F380F_P_2 */
11184 { "vtestpd", { XM, EXx }, 0 },
11187 /* VEX_W_0F3816_P_2 */
11188 { "vpermps", { XM, Vex, EXx }, 0 },
11191 /* VEX_W_0F3817_P_2 */
11192 { "vptest", { XM, EXx }, 0 },
11195 /* VEX_W_0F3818_P_2 */
11196 { "vbroadcastss", { XM, EXxmm_md }, 0 },
11199 /* VEX_W_0F3819_P_2 */
11200 { "vbroadcastsd", { XM, EXxmm_mq }, 0 },
11203 /* VEX_W_0F381A_P_2_M_0 */
11204 { "vbroadcastf128", { XM, Mxmm }, 0 },
11207 /* VEX_W_0F381C_P_2 */
11208 { "vpabsb", { XM, EXx }, 0 },
11211 /* VEX_W_0F381D_P_2 */
11212 { "vpabsw", { XM, EXx }, 0 },
11215 /* VEX_W_0F381E_P_2 */
11216 { "vpabsd", { XM, EXx }, 0 },
11219 /* VEX_W_0F3820_P_2 */
11220 { "vpmovsxbw", { XM, EXxmmq }, 0 },
11223 /* VEX_W_0F3821_P_2 */
11224 { "vpmovsxbd", { XM, EXxmmqd }, 0 },
11227 /* VEX_W_0F3822_P_2 */
11228 { "vpmovsxbq", { XM, EXxmmdw }, 0 },
11231 /* VEX_W_0F3823_P_2 */
11232 { "vpmovsxwd", { XM, EXxmmq }, 0 },
11235 /* VEX_W_0F3824_P_2 */
11236 { "vpmovsxwq", { XM, EXxmmqd }, 0 },
11239 /* VEX_W_0F3825_P_2 */
11240 { "vpmovsxdq", { XM, EXxmmq }, 0 },
11243 /* VEX_W_0F3828_P_2 */
11244 { "vpmuldq", { XM, Vex, EXx }, 0 },
11247 /* VEX_W_0F3829_P_2 */
11248 { "vpcmpeqq", { XM, Vex, EXx }, 0 },
11251 /* VEX_W_0F382A_P_2_M_0 */
11252 { "vmovntdqa", { XM, Mx }, 0 },
11255 /* VEX_W_0F382B_P_2 */
11256 { "vpackusdw", { XM, Vex, EXx }, 0 },
11259 /* VEX_W_0F382C_P_2_M_0 */
11260 { "vmaskmovps", { XM, Vex, Mx }, 0 },
11263 /* VEX_W_0F382D_P_2_M_0 */
11264 { "vmaskmovpd", { XM, Vex, Mx }, 0 },
11267 /* VEX_W_0F382E_P_2_M_0 */
11268 { "vmaskmovps", { Mx, Vex, XM }, 0 },
11271 /* VEX_W_0F382F_P_2_M_0 */
11272 { "vmaskmovpd", { Mx, Vex, XM }, 0 },
11275 /* VEX_W_0F3830_P_2 */
11276 { "vpmovzxbw", { XM, EXxmmq }, 0 },
11279 /* VEX_W_0F3831_P_2 */
11280 { "vpmovzxbd", { XM, EXxmmqd }, 0 },
11283 /* VEX_W_0F3832_P_2 */
11284 { "vpmovzxbq", { XM, EXxmmdw }, 0 },
11287 /* VEX_W_0F3833_P_2 */
11288 { "vpmovzxwd", { XM, EXxmmq }, 0 },
11291 /* VEX_W_0F3834_P_2 */
11292 { "vpmovzxwq", { XM, EXxmmqd }, 0 },
11295 /* VEX_W_0F3835_P_2 */
11296 { "vpmovzxdq", { XM, EXxmmq }, 0 },
11299 /* VEX_W_0F3836_P_2 */
11300 { "vpermd", { XM, Vex, EXx }, 0 },
11303 /* VEX_W_0F3837_P_2 */
11304 { "vpcmpgtq", { XM, Vex, EXx }, 0 },
11307 /* VEX_W_0F3838_P_2 */
11308 { "vpminsb", { XM, Vex, EXx }, 0 },
11311 /* VEX_W_0F3839_P_2 */
11312 { "vpminsd", { XM, Vex, EXx }, 0 },
11315 /* VEX_W_0F383A_P_2 */
11316 { "vpminuw", { XM, Vex, EXx }, 0 },
11319 /* VEX_W_0F383B_P_2 */
11320 { "vpminud", { XM, Vex, EXx }, 0 },
11323 /* VEX_W_0F383C_P_2 */
11324 { "vpmaxsb", { XM, Vex, EXx }, 0 },
11327 /* VEX_W_0F383D_P_2 */
11328 { "vpmaxsd", { XM, Vex, EXx }, 0 },
11331 /* VEX_W_0F383E_P_2 */
11332 { "vpmaxuw", { XM, Vex, EXx }, 0 },
11335 /* VEX_W_0F383F_P_2 */
11336 { "vpmaxud", { XM, Vex, EXx }, 0 },
11339 /* VEX_W_0F3840_P_2 */
11340 { "vpmulld", { XM, Vex, EXx }, 0 },
11343 /* VEX_W_0F3841_P_2 */
11344 { "vphminposuw", { XM, EXx }, 0 },
11347 /* VEX_W_0F3846_P_2 */
11348 { "vpsravd", { XM, Vex, EXx }, 0 },
11351 /* VEX_W_0F3858_P_2 */
11352 { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11355 /* VEX_W_0F3859_P_2 */
11356 { "vpbroadcastq", { XM, EXxmm_mq }, 0 },
11359 /* VEX_W_0F385A_P_2_M_0 */
11360 { "vbroadcasti128", { XM, Mxmm }, 0 },
11363 /* VEX_W_0F3878_P_2 */
11364 { "vpbroadcastb", { XM, EXxmm_mb }, 0 },
11367 /* VEX_W_0F3879_P_2 */
11368 { "vpbroadcastw", { XM, EXxmm_mw }, 0 },
11371 /* VEX_W_0F38CF_P_2 */
11372 { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
11375 /* VEX_W_0F38DB_P_2 */
11376 { "vaesimc", { XM, EXx }, 0 },
11379 /* VEX_W_0F3A00_P_2 */
11381 { "vpermq", { XM, EXx, Ib }, 0 },
11384 /* VEX_W_0F3A01_P_2 */
11386 { "vpermpd", { XM, EXx, Ib }, 0 },
11389 /* VEX_W_0F3A02_P_2 */
11390 { "vpblendd", { XM, Vex, EXx, Ib }, 0 },
11393 /* VEX_W_0F3A04_P_2 */
11394 { "vpermilps", { XM, EXx, Ib }, 0 },
11397 /* VEX_W_0F3A05_P_2 */
11398 { "vpermilpd", { XM, EXx, Ib }, 0 },
11401 /* VEX_W_0F3A06_P_2 */
11402 { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 },
11405 /* VEX_W_0F3A08_P_2 */
11406 { "vroundps", { XM, EXx, Ib }, 0 },
11409 /* VEX_W_0F3A09_P_2 */
11410 { "vroundpd", { XM, EXx, Ib }, 0 },
11413 /* VEX_W_0F3A0A_P_2 */
11414 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11417 /* VEX_W_0F3A0B_P_2 */
11418 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11421 /* VEX_W_0F3A0C_P_2 */
11422 { "vblendps", { XM, Vex, EXx, Ib }, 0 },
11425 /* VEX_W_0F3A0D_P_2 */
11426 { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
11429 /* VEX_W_0F3A0E_P_2 */
11430 { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
11433 /* VEX_W_0F3A0F_P_2 */
11434 { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
11437 /* VEX_W_0F3A14_P_2 */
11438 { "vpextrb", { Edqb, XM, Ib }, 0 },
11441 /* VEX_W_0F3A15_P_2 */
11442 { "vpextrw", { Edqw, XM, Ib }, 0 },
11445 /* VEX_W_0F3A18_P_2 */
11446 { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 },
11449 /* VEX_W_0F3A19_P_2 */
11450 { "vextractf128", { EXxmm, XM, Ib }, 0 },
11453 /* VEX_W_0F3A20_P_2 */
11454 { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
11457 /* VEX_W_0F3A21_P_2 */
11458 { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
11461 /* VEX_W_0F3A30_P_2_LEN_0 */
11462 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11463 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11466 /* VEX_W_0F3A31_P_2_LEN_0 */
11467 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11468 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11471 /* VEX_W_0F3A32_P_2_LEN_0 */
11472 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11473 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11476 /* VEX_W_0F3A33_P_2_LEN_0 */
11477 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11478 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11481 /* VEX_W_0F3A38_P_2 */
11482 { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 },
11485 /* VEX_W_0F3A39_P_2 */
11486 { "vextracti128", { EXxmm, XM, Ib }, 0 },
11489 /* VEX_W_0F3A40_P_2 */
11490 { "vdpps", { XM, Vex, EXx, Ib }, 0 },
11493 /* VEX_W_0F3A41_P_2 */
11494 { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
11497 /* VEX_W_0F3A42_P_2 */
11498 { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
11501 /* VEX_W_0F3A46_P_2 */
11502 { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
11505 /* VEX_W_0F3A48_P_2 */
11506 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11507 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11510 /* VEX_W_0F3A49_P_2 */
11511 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11512 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11515 /* VEX_W_0F3A4A_P_2 */
11516 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 },
11519 /* VEX_W_0F3A4B_P_2 */
11520 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 },
11523 /* VEX_W_0F3A4C_P_2 */
11524 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
11527 /* VEX_W_0F3A62_P_2 */
11528 { "vpcmpistrm", { XM, EXx, Ib }, 0 },
11531 /* VEX_W_0F3A63_P_2 */
11532 { "vpcmpistri", { XM, EXx, Ib }, 0 },
11535 /* VEX_W_0F3ACE_P_2 */
11537 { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
11540 /* VEX_W_0F3ACF_P_2 */
11542 { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 },
11545 /* VEX_W_0F3ADF_P_2 */
11546 { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11548 #define NEED_VEX_W_TABLE
11549 #include "i386-dis-evex.h"
11550 #undef NEED_VEX_W_TABLE
11553 static const struct dis386 mod_table[][2] = {
11556 { "leaS", { Gv, M }, 0 },
11561 { RM_TABLE (RM_C6_REG_7) },
11566 { RM_TABLE (RM_C7_REG_7) },
11570 { "Jcall^", { indirEp }, 0 },
11574 { "Jjmp^", { indirEp }, 0 },
11577 /* MOD_0F01_REG_0 */
11578 { X86_64_TABLE (X86_64_0F01_REG_0) },
11579 { RM_TABLE (RM_0F01_REG_0) },
11582 /* MOD_0F01_REG_1 */
11583 { X86_64_TABLE (X86_64_0F01_REG_1) },
11584 { RM_TABLE (RM_0F01_REG_1) },
11587 /* MOD_0F01_REG_2 */
11588 { X86_64_TABLE (X86_64_0F01_REG_2) },
11589 { RM_TABLE (RM_0F01_REG_2) },
11592 /* MOD_0F01_REG_3 */
11593 { X86_64_TABLE (X86_64_0F01_REG_3) },
11594 { RM_TABLE (RM_0F01_REG_3) },
11597 /* MOD_0F01_REG_5 */
11598 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
11599 { RM_TABLE (RM_0F01_REG_5) },
11602 /* MOD_0F01_REG_7 */
11603 { "invlpg", { Mb }, 0 },
11604 { RM_TABLE (RM_0F01_REG_7) },
11607 /* MOD_0F12_PREFIX_0 */
11608 { "movlps", { XM, EXq }, PREFIX_OPCODE },
11609 { "movhlps", { XM, EXq }, PREFIX_OPCODE },
11613 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
11616 /* MOD_0F16_PREFIX_0 */
11617 { "movhps", { XM, EXq }, 0 },
11618 { "movlhps", { XM, EXq }, 0 },
11622 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
11625 /* MOD_0F18_REG_0 */
11626 { "prefetchnta", { Mb }, 0 },
11629 /* MOD_0F18_REG_1 */
11630 { "prefetcht0", { Mb }, 0 },
11633 /* MOD_0F18_REG_2 */
11634 { "prefetcht1", { Mb }, 0 },
11637 /* MOD_0F18_REG_3 */
11638 { "prefetcht2", { Mb }, 0 },
11641 /* MOD_0F18_REG_4 */
11642 { "nop/reserved", { Mb }, 0 },
11645 /* MOD_0F18_REG_5 */
11646 { "nop/reserved", { Mb }, 0 },
11649 /* MOD_0F18_REG_6 */
11650 { "nop/reserved", { Mb }, 0 },
11653 /* MOD_0F18_REG_7 */
11654 { "nop/reserved", { Mb }, 0 },
11657 /* MOD_0F1A_PREFIX_0 */
11658 { "bndldx", { Gbnd, Mv_bnd }, 0 },
11659 { "nopQ", { Ev }, 0 },
11662 /* MOD_0F1B_PREFIX_0 */
11663 { "bndstx", { Mv_bnd, Gbnd }, 0 },
11664 { "nopQ", { Ev }, 0 },
11667 /* MOD_0F1B_PREFIX_1 */
11668 { "bndmk", { Gbnd, Mv_bnd }, 0 },
11669 { "nopQ", { Ev }, 0 },
11672 /* MOD_0F1C_PREFIX_0 */
11673 { REG_TABLE (REG_0F1C_MOD_0) },
11674 { "nopQ", { Ev }, 0 },
11677 /* MOD_0F1E_PREFIX_1 */
11678 { "nopQ", { Ev }, 0 },
11679 { REG_TABLE (REG_0F1E_MOD_3) },
11684 { "movL", { Rd, Td }, 0 },
11689 { "movL", { Td, Rd }, 0 },
11692 /* MOD_0F2B_PREFIX_0 */
11693 {"movntps", { Mx, XM }, PREFIX_OPCODE },
11696 /* MOD_0F2B_PREFIX_1 */
11697 {"movntss", { Md, XM }, PREFIX_OPCODE },
11700 /* MOD_0F2B_PREFIX_2 */
11701 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
11704 /* MOD_0F2B_PREFIX_3 */
11705 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
11710 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
11713 /* MOD_0F71_REG_2 */
11715 { "psrlw", { MS, Ib }, 0 },
11718 /* MOD_0F71_REG_4 */
11720 { "psraw", { MS, Ib }, 0 },
11723 /* MOD_0F71_REG_6 */
11725 { "psllw", { MS, Ib }, 0 },
11728 /* MOD_0F72_REG_2 */
11730 { "psrld", { MS, Ib }, 0 },
11733 /* MOD_0F72_REG_4 */
11735 { "psrad", { MS, Ib }, 0 },
11738 /* MOD_0F72_REG_6 */
11740 { "pslld", { MS, Ib }, 0 },
11743 /* MOD_0F73_REG_2 */
11745 { "psrlq", { MS, Ib }, 0 },
11748 /* MOD_0F73_REG_3 */
11750 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11753 /* MOD_0F73_REG_6 */
11755 { "psllq", { MS, Ib }, 0 },
11758 /* MOD_0F73_REG_7 */
11760 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11763 /* MOD_0FAE_REG_0 */
11764 { "fxsave", { FXSAVE }, 0 },
11765 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11768 /* MOD_0FAE_REG_1 */
11769 { "fxrstor", { FXSAVE }, 0 },
11770 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11773 /* MOD_0FAE_REG_2 */
11774 { "ldmxcsr", { Md }, 0 },
11775 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11778 /* MOD_0FAE_REG_3 */
11779 { "stmxcsr", { Md }, 0 },
11780 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11783 /* MOD_0FAE_REG_4 */
11784 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11785 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11788 /* MOD_0FAE_REG_5 */
11789 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
11790 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
11793 /* MOD_0FAE_REG_6 */
11794 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
11795 { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
11798 /* MOD_0FAE_REG_7 */
11799 { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11800 { RM_TABLE (RM_0FAE_REG_7) },
11804 { "lssS", { Gv, Mp }, 0 },
11808 { "lfsS", { Gv, Mp }, 0 },
11812 { "lgsS", { Gv, Mp }, 0 },
11816 { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11819 /* MOD_0FC7_REG_3 */
11820 { "xrstors", { FXSAVE }, 0 },
11823 /* MOD_0FC7_REG_4 */
11824 { "xsavec", { FXSAVE }, 0 },
11827 /* MOD_0FC7_REG_5 */
11828 { "xsaves", { FXSAVE }, 0 },
11831 /* MOD_0FC7_REG_6 */
11832 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11833 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11836 /* MOD_0FC7_REG_7 */
11837 { "vmptrst", { Mq }, 0 },
11838 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11843 { "pmovmskb", { Gdq, MS }, 0 },
11846 /* MOD_0FE7_PREFIX_2 */
11847 { "movntdq", { Mx, XM }, 0 },
11850 /* MOD_0FF0_PREFIX_3 */
11851 { "lddqu", { XM, M }, 0 },
11854 /* MOD_0F382A_PREFIX_2 */
11855 { "movntdqa", { XM, Mx }, 0 },
11858 /* MOD_0F38F5_PREFIX_2 */
11859 { "wrussK", { M, Gdq }, PREFIX_OPCODE },
11862 /* MOD_0F38F6_PREFIX_0 */
11863 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
11866 /* MOD_0F38F8_PREFIX_2 */
11867 { "movdir64b", { Gva, M }, PREFIX_OPCODE },
11870 /* MOD_0F38F9_PREFIX_0 */
11871 { "movdiri", { Em, Gv }, PREFIX_OPCODE },
11875 { "bound{S|}", { Gv, Ma }, 0 },
11876 { EVEX_TABLE (EVEX_0F) },
11880 { "lesS", { Gv, Mp }, 0 },
11881 { VEX_C4_TABLE (VEX_0F) },
11885 { "ldsS", { Gv, Mp }, 0 },
11886 { VEX_C5_TABLE (VEX_0F) },
11889 /* MOD_VEX_0F12_PREFIX_0 */
11890 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11891 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11895 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11898 /* MOD_VEX_0F16_PREFIX_0 */
11899 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11900 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11904 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11908 { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11911 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11913 { "kandw", { MaskG, MaskVex, MaskR }, 0 },
11916 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11918 { "kandq", { MaskG, MaskVex, MaskR }, 0 },
11921 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11923 { "kandb", { MaskG, MaskVex, MaskR }, 0 },
11926 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11928 { "kandd", { MaskG, MaskVex, MaskR }, 0 },
11931 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11933 { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
11936 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11938 { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
11941 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11943 { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
11946 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11948 { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
11951 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11953 { "knotw", { MaskG, MaskR }, 0 },
11956 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11958 { "knotq", { MaskG, MaskR }, 0 },
11961 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11963 { "knotb", { MaskG, MaskR }, 0 },
11966 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11968 { "knotd", { MaskG, MaskR }, 0 },
11971 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11973 { "korw", { MaskG, MaskVex, MaskR }, 0 },
11976 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11978 { "korq", { MaskG, MaskVex, MaskR }, 0 },
11981 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11983 { "korb", { MaskG, MaskVex, MaskR }, 0 },
11986 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11988 { "kord", { MaskG, MaskVex, MaskR }, 0 },
11991 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11993 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
11996 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11998 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
12001 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
12003 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
12006 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
12008 { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
12011 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
12013 { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
12016 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
12018 { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
12021 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
12023 { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
12026 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
12028 { "kxord", { MaskG, MaskVex, MaskR }, 0 },
12031 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
12033 { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
12036 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
12038 { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
12041 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
12043 { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
12046 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
12048 { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
12051 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
12053 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
12056 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
12058 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
12061 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
12063 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
12068 { VEX_W_TABLE (VEX_W_0F50_M_0) },
12071 /* MOD_VEX_0F71_REG_2 */
12073 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
12076 /* MOD_VEX_0F71_REG_4 */
12078 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
12081 /* MOD_VEX_0F71_REG_6 */
12083 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
12086 /* MOD_VEX_0F72_REG_2 */
12088 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12091 /* MOD_VEX_0F72_REG_4 */
12093 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12096 /* MOD_VEX_0F72_REG_6 */
12098 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12101 /* MOD_VEX_0F73_REG_2 */
12103 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12106 /* MOD_VEX_0F73_REG_3 */
12108 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12111 /* MOD_VEX_0F73_REG_6 */
12113 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12116 /* MOD_VEX_0F73_REG_7 */
12118 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12121 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12122 { "kmovw", { Ew, MaskG }, 0 },
12126 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12127 { "kmovq", { Eq, MaskG }, 0 },
12131 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12132 { "kmovb", { Eb, MaskG }, 0 },
12136 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12137 { "kmovd", { Ed, MaskG }, 0 },
12141 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12143 { "kmovw", { MaskG, Rdq }, 0 },
12146 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12148 { "kmovb", { MaskG, Rdq }, 0 },
12151 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12153 { "kmovd", { MaskG, Rdq }, 0 },
12156 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12158 { "kmovq", { MaskG, Rdq }, 0 },
12161 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12163 { "kmovw", { Gdq, MaskR }, 0 },
12166 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12168 { "kmovb", { Gdq, MaskR }, 0 },
12171 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12173 { "kmovd", { Gdq, MaskR }, 0 },
12176 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12178 { "kmovq", { Gdq, MaskR }, 0 },
12181 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12183 { "kortestw", { MaskG, MaskR }, 0 },
12186 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12188 { "kortestq", { MaskG, MaskR }, 0 },
12191 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12193 { "kortestb", { MaskG, MaskR }, 0 },
12196 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12198 { "kortestd", { MaskG, MaskR }, 0 },
12201 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12203 { "ktestw", { MaskG, MaskR }, 0 },
12206 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12208 { "ktestq", { MaskG, MaskR }, 0 },
12211 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12213 { "ktestb", { MaskG, MaskR }, 0 },
12216 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12218 { "ktestd", { MaskG, MaskR }, 0 },
12221 /* MOD_VEX_0FAE_REG_2 */
12222 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12225 /* MOD_VEX_0FAE_REG_3 */
12226 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12229 /* MOD_VEX_0FD7_PREFIX_2 */
12231 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12234 /* MOD_VEX_0FE7_PREFIX_2 */
12235 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12238 /* MOD_VEX_0FF0_PREFIX_3 */
12239 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12242 /* MOD_VEX_0F381A_PREFIX_2 */
12243 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12246 /* MOD_VEX_0F382A_PREFIX_2 */
12247 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12250 /* MOD_VEX_0F382C_PREFIX_2 */
12251 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12254 /* MOD_VEX_0F382D_PREFIX_2 */
12255 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12258 /* MOD_VEX_0F382E_PREFIX_2 */
12259 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12262 /* MOD_VEX_0F382F_PREFIX_2 */
12263 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12266 /* MOD_VEX_0F385A_PREFIX_2 */
12267 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12270 /* MOD_VEX_0F388C_PREFIX_2 */
12271 { "vpmaskmov%LW", { XM, Vex, Mx }, 0 },
12274 /* MOD_VEX_0F388E_PREFIX_2 */
12275 { "vpmaskmov%LW", { Mx, Vex, XM }, 0 },
12278 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12280 { "kshiftrb", { MaskG, MaskR, Ib }, 0 },
12283 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12285 { "kshiftrw", { MaskG, MaskR, Ib }, 0 },
12288 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12290 { "kshiftrd", { MaskG, MaskR, Ib }, 0 },
12293 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12295 { "kshiftrq", { MaskG, MaskR, Ib }, 0 },
12298 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12300 { "kshiftlb", { MaskG, MaskR, Ib }, 0 },
12303 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12305 { "kshiftlw", { MaskG, MaskR, Ib }, 0 },
12308 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12310 { "kshiftld", { MaskG, MaskR, Ib }, 0 },
12313 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12315 { "kshiftlq", { MaskG, MaskR, Ib }, 0 },
12317 #define NEED_MOD_TABLE
12318 #include "i386-dis-evex.h"
12319 #undef NEED_MOD_TABLE
12322 static const struct dis386 rm_table[][8] = {
12325 { "xabort", { Skip_MODRM, Ib }, 0 },
12329 { "xbeginT", { Skip_MODRM, Jv }, 0 },
12332 /* RM_0F01_REG_0 */
12334 { "vmcall", { Skip_MODRM }, 0 },
12335 { "vmlaunch", { Skip_MODRM }, 0 },
12336 { "vmresume", { Skip_MODRM }, 0 },
12337 { "vmxoff", { Skip_MODRM }, 0 },
12338 { "pconfig", { Skip_MODRM }, 0 },
12341 /* RM_0F01_REG_1 */
12342 { "monitor", { { OP_Monitor, 0 } }, 0 },
12343 { "mwait", { { OP_Mwait, 0 } }, 0 },
12344 { "clac", { Skip_MODRM }, 0 },
12345 { "stac", { Skip_MODRM }, 0 },
12349 { "encls", { Skip_MODRM }, 0 },
12352 /* RM_0F01_REG_2 */
12353 { "xgetbv", { Skip_MODRM }, 0 },
12354 { "xsetbv", { Skip_MODRM }, 0 },
12357 { "vmfunc", { Skip_MODRM }, 0 },
12358 { "xend", { Skip_MODRM }, 0 },
12359 { "xtest", { Skip_MODRM }, 0 },
12360 { "enclu", { Skip_MODRM }, 0 },
12363 /* RM_0F01_REG_3 */
12364 { "vmrun", { Skip_MODRM }, 0 },
12365 { "vmmcall", { Skip_MODRM }, 0 },
12366 { "vmload", { Skip_MODRM }, 0 },
12367 { "vmsave", { Skip_MODRM }, 0 },
12368 { "stgi", { Skip_MODRM }, 0 },
12369 { "clgi", { Skip_MODRM }, 0 },
12370 { "skinit", { Skip_MODRM }, 0 },
12371 { "invlpga", { Skip_MODRM }, 0 },
12374 /* RM_0F01_REG_5 */
12375 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
12377 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
12381 { "rdpkru", { Skip_MODRM }, 0 },
12382 { "wrpkru", { Skip_MODRM }, 0 },
12385 /* RM_0F01_REG_7 */
12386 { "swapgs", { Skip_MODRM }, 0 },
12387 { "rdtscp", { Skip_MODRM }, 0 },
12388 { "monitorx", { { OP_Monitor, 0 } }, 0 },
12389 { "mwaitx", { { OP_Mwaitx, 0 } }, 0 },
12390 { "clzero", { Skip_MODRM }, 0 },
12393 /* RM_0F1E_MOD_3_REG_7 */
12394 { "nopQ", { Ev }, 0 },
12395 { "nopQ", { Ev }, 0 },
12396 { "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
12397 { "endbr32", { Skip_MODRM }, PREFIX_OPCODE },
12398 { "nopQ", { Ev }, 0 },
12399 { "nopQ", { Ev }, 0 },
12400 { "nopQ", { Ev }, 0 },
12401 { "nopQ", { Ev }, 0 },
12404 /* RM_0FAE_REG_6 */
12405 { "mfence", { Skip_MODRM }, 0 },
12408 /* RM_0FAE_REG_7 */
12409 { "sfence", { Skip_MODRM }, 0 },
12414 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12416 /* We use the high bit to indicate different name for the same
12418 #define REP_PREFIX (0xf3 | 0x100)
12419 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12420 #define XRELEASE_PREFIX (0xf3 | 0x400)
12421 #define BND_PREFIX (0xf2 | 0x400)
12422 #define NOTRACK_PREFIX (0x3e | 0x100)
12427 int newrex, i, length;
12433 last_lock_prefix = -1;
12434 last_repz_prefix = -1;
12435 last_repnz_prefix = -1;
12436 last_data_prefix = -1;
12437 last_addr_prefix = -1;
12438 last_rex_prefix = -1;
12439 last_seg_prefix = -1;
12441 active_seg_prefix = 0;
12442 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12443 all_prefixes[i] = 0;
12446 /* The maximum instruction length is 15bytes. */
12447 while (length < MAX_CODE_LENGTH - 1)
12449 FETCH_DATA (the_info, codep + 1);
12453 /* REX prefixes family. */
12470 if (address_mode == mode_64bit)
12474 last_rex_prefix = i;
12477 prefixes |= PREFIX_REPZ;
12478 last_repz_prefix = i;
12481 prefixes |= PREFIX_REPNZ;
12482 last_repnz_prefix = i;
12485 prefixes |= PREFIX_LOCK;
12486 last_lock_prefix = i;
12489 prefixes |= PREFIX_CS;
12490 last_seg_prefix = i;
12491 active_seg_prefix = PREFIX_CS;
12494 prefixes |= PREFIX_SS;
12495 last_seg_prefix = i;
12496 active_seg_prefix = PREFIX_SS;
12499 prefixes |= PREFIX_DS;
12500 last_seg_prefix = i;
12501 active_seg_prefix = PREFIX_DS;
12504 prefixes |= PREFIX_ES;
12505 last_seg_prefix = i;
12506 active_seg_prefix = PREFIX_ES;
12509 prefixes |= PREFIX_FS;
12510 last_seg_prefix = i;
12511 active_seg_prefix = PREFIX_FS;
12514 prefixes |= PREFIX_GS;
12515 last_seg_prefix = i;
12516 active_seg_prefix = PREFIX_GS;
12519 prefixes |= PREFIX_DATA;
12520 last_data_prefix = i;
12523 prefixes |= PREFIX_ADDR;
12524 last_addr_prefix = i;
12527 /* fwait is really an instruction. If there are prefixes
12528 before the fwait, they belong to the fwait, *not* to the
12529 following instruction. */
12531 if (prefixes || rex)
12533 prefixes |= PREFIX_FWAIT;
12535 /* This ensures that the previous REX prefixes are noticed
12536 as unused prefixes, as in the return case below. */
12540 prefixes = PREFIX_FWAIT;
12545 /* Rex is ignored when followed by another prefix. */
12551 if (*codep != FWAIT_OPCODE)
12552 all_prefixes[i++] = *codep;
12560 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12563 static const char *
12564 prefix_name (int pref, int sizeflag)
12566 static const char *rexes [16] =
12569 "rex.B", /* 0x41 */
12570 "rex.X", /* 0x42 */
12571 "rex.XB", /* 0x43 */
12572 "rex.R", /* 0x44 */
12573 "rex.RB", /* 0x45 */
12574 "rex.RX", /* 0x46 */
12575 "rex.RXB", /* 0x47 */
12576 "rex.W", /* 0x48 */
12577 "rex.WB", /* 0x49 */
12578 "rex.WX", /* 0x4a */
12579 "rex.WXB", /* 0x4b */
12580 "rex.WR", /* 0x4c */
12581 "rex.WRB", /* 0x4d */
12582 "rex.WRX", /* 0x4e */
12583 "rex.WRXB", /* 0x4f */
12588 /* REX prefixes family. */
12605 return rexes [pref - 0x40];
12625 return (sizeflag & DFLAG) ? "data16" : "data32";
12627 if (address_mode == mode_64bit)
12628 return (sizeflag & AFLAG) ? "addr32" : "addr64";
12630 return (sizeflag & AFLAG) ? "addr16" : "addr32";
12635 case XACQUIRE_PREFIX:
12637 case XRELEASE_PREFIX:
12641 case NOTRACK_PREFIX:
12648 static char op_out[MAX_OPERANDS][100];
12649 static int op_ad, op_index[MAX_OPERANDS];
12650 static int two_source_ops;
12651 static bfd_vma op_address[MAX_OPERANDS];
12652 static bfd_vma op_riprel[MAX_OPERANDS];
12653 static bfd_vma start_pc;
12656 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12657 * (see topic "Redundant prefixes" in the "Differences from 8086"
12658 * section of the "Virtual 8086 Mode" chapter.)
12659 * 'pc' should be the address of this instruction, it will
12660 * be used to print the target address if this is a relative jump or call
12661 * The function returns the length of this instruction in bytes.
12664 static char intel_syntax;
12665 static char intel_mnemonic = !SYSV386_COMPAT;
12666 static char open_char;
12667 static char close_char;
12668 static char separator_char;
12669 static char scale_char;
12677 static enum x86_64_isa isa64;
12679 /* Here for backwards compatibility. When gdb stops using
12680 print_insn_i386_att and print_insn_i386_intel these functions can
12681 disappear, and print_insn_i386 be merged into print_insn. */
12683 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12687 return print_insn (pc, info);
12691 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12695 return print_insn (pc, info);
12699 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12703 return print_insn (pc, info);
12707 print_i386_disassembler_options (FILE *stream)
12709 fprintf (stream, _("\n\
12710 The following i386/x86-64 specific disassembler options are supported for use\n\
12711 with the -M switch (multiple options should be separated by commas):\n"));
12713 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
12714 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
12715 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
12716 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
12717 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
12718 fprintf (stream, _(" att-mnemonic\n"
12719 " Display instruction in AT&T mnemonic\n"));
12720 fprintf (stream, _(" intel-mnemonic\n"
12721 " Display instruction in Intel mnemonic\n"));
12722 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
12723 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
12724 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
12725 fprintf (stream, _(" data32 Assume 32bit data size\n"));
12726 fprintf (stream, _(" data16 Assume 16bit data size\n"));
12727 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12728 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
12729 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
12733 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12735 /* Get a pointer to struct dis386 with a valid name. */
12737 static const struct dis386 *
12738 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12740 int vindex, vex_table_index;
12742 if (dp->name != NULL)
12745 switch (dp->op[0].bytemode)
12747 case USE_REG_TABLE:
12748 dp = ®_table[dp->op[1].bytemode][modrm.reg];
12751 case USE_MOD_TABLE:
12752 vindex = modrm.mod == 0x3 ? 1 : 0;
12753 dp = &mod_table[dp->op[1].bytemode][vindex];
12757 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12760 case USE_PREFIX_TABLE:
12763 /* The prefix in VEX is implicit. */
12764 switch (vex.prefix)
12769 case REPE_PREFIX_OPCODE:
12772 case DATA_PREFIX_OPCODE:
12775 case REPNE_PREFIX_OPCODE:
12785 int last_prefix = -1;
12788 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12789 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12791 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12793 if (last_repz_prefix > last_repnz_prefix)
12796 prefix = PREFIX_REPZ;
12797 last_prefix = last_repz_prefix;
12802 prefix = PREFIX_REPNZ;
12803 last_prefix = last_repnz_prefix;
12806 /* Check if prefix should be ignored. */
12807 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12808 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12813 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12816 prefix = PREFIX_DATA;
12817 last_prefix = last_data_prefix;
12822 used_prefixes |= prefix;
12823 all_prefixes[last_prefix] = 0;
12826 dp = &prefix_table[dp->op[1].bytemode][vindex];
12829 case USE_X86_64_TABLE:
12830 vindex = address_mode == mode_64bit ? 1 : 0;
12831 dp = &x86_64_table[dp->op[1].bytemode][vindex];
12834 case USE_3BYTE_TABLE:
12835 FETCH_DATA (info, codep + 2);
12837 dp = &three_byte_table[dp->op[1].bytemode][vindex];
12839 modrm.mod = (*codep >> 6) & 3;
12840 modrm.reg = (*codep >> 3) & 7;
12841 modrm.rm = *codep & 7;
12844 case USE_VEX_LEN_TABLE:
12848 switch (vex.length)
12861 dp = &vex_len_table[dp->op[1].bytemode][vindex];
12864 case USE_XOP_8F_TABLE:
12865 FETCH_DATA (info, codep + 3);
12866 /* All bits in the REX prefix are ignored. */
12868 rex = ~(*codep >> 5) & 0x7;
12870 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12871 switch ((*codep & 0x1f))
12877 vex_table_index = XOP_08;
12880 vex_table_index = XOP_09;
12883 vex_table_index = XOP_0A;
12887 vex.w = *codep & 0x80;
12888 if (vex.w && address_mode == mode_64bit)
12891 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12892 if (address_mode != mode_64bit)
12894 /* In 16/32-bit mode REX_B is silently ignored. */
12898 vex.length = (*codep & 0x4) ? 256 : 128;
12899 switch ((*codep & 0x3))
12904 vex.prefix = DATA_PREFIX_OPCODE;
12907 vex.prefix = REPE_PREFIX_OPCODE;
12910 vex.prefix = REPNE_PREFIX_OPCODE;
12917 dp = &xop_table[vex_table_index][vindex];
12920 FETCH_DATA (info, codep + 1);
12921 modrm.mod = (*codep >> 6) & 3;
12922 modrm.reg = (*codep >> 3) & 7;
12923 modrm.rm = *codep & 7;
12926 case USE_VEX_C4_TABLE:
12928 FETCH_DATA (info, codep + 3);
12929 /* All bits in the REX prefix are ignored. */
12931 rex = ~(*codep >> 5) & 0x7;
12932 switch ((*codep & 0x1f))
12938 vex_table_index = VEX_0F;
12941 vex_table_index = VEX_0F38;
12944 vex_table_index = VEX_0F3A;
12948 vex.w = *codep & 0x80;
12949 if (address_mode == mode_64bit)
12956 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12957 is ignored, other REX bits are 0 and the highest bit in
12958 VEX.vvvv is also ignored (but we mustn't clear it here). */
12961 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12962 vex.length = (*codep & 0x4) ? 256 : 128;
12963 switch ((*codep & 0x3))
12968 vex.prefix = DATA_PREFIX_OPCODE;
12971 vex.prefix = REPE_PREFIX_OPCODE;
12974 vex.prefix = REPNE_PREFIX_OPCODE;
12981 dp = &vex_table[vex_table_index][vindex];
12983 /* There is no MODRM byte for VEX0F 77. */
12984 if (vex_table_index != VEX_0F || vindex != 0x77)
12986 FETCH_DATA (info, codep + 1);
12987 modrm.mod = (*codep >> 6) & 3;
12988 modrm.reg = (*codep >> 3) & 7;
12989 modrm.rm = *codep & 7;
12993 case USE_VEX_C5_TABLE:
12995 FETCH_DATA (info, codep + 2);
12996 /* All bits in the REX prefix are ignored. */
12998 rex = (*codep & 0x80) ? 0 : REX_R;
13000 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
13002 vex.register_specifier = (~(*codep >> 3)) & 0xf;
13003 vex.length = (*codep & 0x4) ? 256 : 128;
13004 switch ((*codep & 0x3))
13009 vex.prefix = DATA_PREFIX_OPCODE;
13012 vex.prefix = REPE_PREFIX_OPCODE;
13015 vex.prefix = REPNE_PREFIX_OPCODE;
13022 dp = &vex_table[dp->op[1].bytemode][vindex];
13024 /* There is no MODRM byte for VEX 77. */
13025 if (vindex != 0x77)
13027 FETCH_DATA (info, codep + 1);
13028 modrm.mod = (*codep >> 6) & 3;
13029 modrm.reg = (*codep >> 3) & 7;
13030 modrm.rm = *codep & 7;
13034 case USE_VEX_W_TABLE:
13038 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
13041 case USE_EVEX_TABLE:
13042 two_source_ops = 0;
13045 FETCH_DATA (info, codep + 4);
13046 /* All bits in the REX prefix are ignored. */
13048 /* The first byte after 0x62. */
13049 rex = ~(*codep >> 5) & 0x7;
13050 vex.r = *codep & 0x10;
13051 switch ((*codep & 0xf))
13054 return &bad_opcode;
13056 vex_table_index = EVEX_0F;
13059 vex_table_index = EVEX_0F38;
13062 vex_table_index = EVEX_0F3A;
13066 /* The second byte after 0x62. */
13068 vex.w = *codep & 0x80;
13069 if (vex.w && address_mode == mode_64bit)
13072 vex.register_specifier = (~(*codep >> 3)) & 0xf;
13075 if (!(*codep & 0x4))
13076 return &bad_opcode;
13078 switch ((*codep & 0x3))
13083 vex.prefix = DATA_PREFIX_OPCODE;
13086 vex.prefix = REPE_PREFIX_OPCODE;
13089 vex.prefix = REPNE_PREFIX_OPCODE;
13093 /* The third byte after 0x62. */
13096 /* Remember the static rounding bits. */
13097 vex.ll = (*codep >> 5) & 3;
13098 vex.b = (*codep & 0x10) != 0;
13100 vex.v = *codep & 0x8;
13101 vex.mask_register_specifier = *codep & 0x7;
13102 vex.zeroing = *codep & 0x80;
13104 if (address_mode != mode_64bit)
13106 /* In 16/32-bit mode silently ignore following bits. */
13116 dp = &evex_table[vex_table_index][vindex];
13118 FETCH_DATA (info, codep + 1);
13119 modrm.mod = (*codep >> 6) & 3;
13120 modrm.reg = (*codep >> 3) & 7;
13121 modrm.rm = *codep & 7;
13123 /* Set vector length. */
13124 if (modrm.mod == 3 && vex.b)
13140 return &bad_opcode;
13153 if (dp->name != NULL)
13156 return get_valid_dis386 (dp, info);
13160 get_sib (disassemble_info *info, int sizeflag)
13162 /* If modrm.mod == 3, operand must be register. */
13164 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13168 FETCH_DATA (info, codep + 2);
13169 sib.index = (codep [1] >> 3) & 7;
13170 sib.scale = (codep [1] >> 6) & 3;
13171 sib.base = codep [1] & 7;
13176 print_insn (bfd_vma pc, disassemble_info *info)
13178 const struct dis386 *dp;
13180 char *op_txt[MAX_OPERANDS];
13182 int sizeflag, orig_sizeflag;
13184 struct dis_private priv;
13187 priv.orig_sizeflag = AFLAG | DFLAG;
13188 if ((info->mach & bfd_mach_i386_i386) != 0)
13189 address_mode = mode_32bit;
13190 else if (info->mach == bfd_mach_i386_i8086)
13192 address_mode = mode_16bit;
13193 priv.orig_sizeflag = 0;
13196 address_mode = mode_64bit;
13198 if (intel_syntax == (char) -1)
13199 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13201 for (p = info->disassembler_options; p != NULL; )
13203 if (CONST_STRNEQ (p, "amd64"))
13205 else if (CONST_STRNEQ (p, "intel64"))
13207 else if (CONST_STRNEQ (p, "x86-64"))
13209 address_mode = mode_64bit;
13210 priv.orig_sizeflag = AFLAG | DFLAG;
13212 else if (CONST_STRNEQ (p, "i386"))
13214 address_mode = mode_32bit;
13215 priv.orig_sizeflag = AFLAG | DFLAG;
13217 else if (CONST_STRNEQ (p, "i8086"))
13219 address_mode = mode_16bit;
13220 priv.orig_sizeflag = 0;
13222 else if (CONST_STRNEQ (p, "intel"))
13225 if (CONST_STRNEQ (p + 5, "-mnemonic"))
13226 intel_mnemonic = 1;
13228 else if (CONST_STRNEQ (p, "att"))
13231 if (CONST_STRNEQ (p + 3, "-mnemonic"))
13232 intel_mnemonic = 0;
13234 else if (CONST_STRNEQ (p, "addr"))
13236 if (address_mode == mode_64bit)
13238 if (p[4] == '3' && p[5] == '2')
13239 priv.orig_sizeflag &= ~AFLAG;
13240 else if (p[4] == '6' && p[5] == '4')
13241 priv.orig_sizeflag |= AFLAG;
13245 if (p[4] == '1' && p[5] == '6')
13246 priv.orig_sizeflag &= ~AFLAG;
13247 else if (p[4] == '3' && p[5] == '2')
13248 priv.orig_sizeflag |= AFLAG;
13251 else if (CONST_STRNEQ (p, "data"))
13253 if (p[4] == '1' && p[5] == '6')
13254 priv.orig_sizeflag &= ~DFLAG;
13255 else if (p[4] == '3' && p[5] == '2')
13256 priv.orig_sizeflag |= DFLAG;
13258 else if (CONST_STRNEQ (p, "suffix"))
13259 priv.orig_sizeflag |= SUFFIX_ALWAYS;
13261 p = strchr (p, ',');
13266 if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13268 (*info->fprintf_func) (info->stream,
13269 _("64-bit address is disabled"));
13275 names64 = intel_names64;
13276 names32 = intel_names32;
13277 names16 = intel_names16;
13278 names8 = intel_names8;
13279 names8rex = intel_names8rex;
13280 names_seg = intel_names_seg;
13281 names_mm = intel_names_mm;
13282 names_bnd = intel_names_bnd;
13283 names_xmm = intel_names_xmm;
13284 names_ymm = intel_names_ymm;
13285 names_zmm = intel_names_zmm;
13286 index64 = intel_index64;
13287 index32 = intel_index32;
13288 names_mask = intel_names_mask;
13289 index16 = intel_index16;
13292 separator_char = '+';
13297 names64 = att_names64;
13298 names32 = att_names32;
13299 names16 = att_names16;
13300 names8 = att_names8;
13301 names8rex = att_names8rex;
13302 names_seg = att_names_seg;
13303 names_mm = att_names_mm;
13304 names_bnd = att_names_bnd;
13305 names_xmm = att_names_xmm;
13306 names_ymm = att_names_ymm;
13307 names_zmm = att_names_zmm;
13308 index64 = att_index64;
13309 index32 = att_index32;
13310 names_mask = att_names_mask;
13311 index16 = att_index16;
13314 separator_char = ',';
13318 /* The output looks better if we put 7 bytes on a line, since that
13319 puts most long word instructions on a single line. Use 8 bytes
13321 if ((info->mach & bfd_mach_l1om) != 0)
13322 info->bytes_per_line = 8;
13324 info->bytes_per_line = 7;
13326 info->private_data = &priv;
13327 priv.max_fetched = priv.the_buffer;
13328 priv.insn_start = pc;
13331 for (i = 0; i < MAX_OPERANDS; ++i)
13339 start_codep = priv.the_buffer;
13340 codep = priv.the_buffer;
13342 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13346 /* Getting here means we tried for data but didn't get it. That
13347 means we have an incomplete instruction of some sort. Just
13348 print the first byte as a prefix or a .byte pseudo-op. */
13349 if (codep > priv.the_buffer)
13351 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13353 (*info->fprintf_func) (info->stream, "%s", name);
13356 /* Just print the first byte as a .byte instruction. */
13357 (*info->fprintf_func) (info->stream, ".byte 0x%x",
13358 (unsigned int) priv.the_buffer[0]);
13368 sizeflag = priv.orig_sizeflag;
13370 if (!ckprefix () || rex_used)
13372 /* Too many prefixes or unused REX prefixes. */
13374 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13376 (*info->fprintf_func) (info->stream, "%s%s",
13378 prefix_name (all_prefixes[i], sizeflag));
13382 insn_codep = codep;
13384 FETCH_DATA (info, codep + 1);
13385 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13387 if (((prefixes & PREFIX_FWAIT)
13388 && ((*codep < 0xd8) || (*codep > 0xdf))))
13390 /* Handle prefixes before fwait. */
13391 for (i = 0; i < fwait_prefix && all_prefixes[i];
13393 (*info->fprintf_func) (info->stream, "%s ",
13394 prefix_name (all_prefixes[i], sizeflag));
13395 (*info->fprintf_func) (info->stream, "fwait");
13399 if (*codep == 0x0f)
13401 unsigned char threebyte;
13404 FETCH_DATA (info, codep + 1);
13405 threebyte = *codep;
13406 dp = &dis386_twobyte[threebyte];
13407 need_modrm = twobyte_has_modrm[*codep];
13412 dp = &dis386[*codep];
13413 need_modrm = onebyte_has_modrm[*codep];
13417 /* Save sizeflag for printing the extra prefixes later before updating
13418 it for mnemonic and operand processing. The prefix names depend
13419 only on the address mode. */
13420 orig_sizeflag = sizeflag;
13421 if (prefixes & PREFIX_ADDR)
13423 if ((prefixes & PREFIX_DATA))
13429 FETCH_DATA (info, codep + 1);
13430 modrm.mod = (*codep >> 6) & 3;
13431 modrm.reg = (*codep >> 3) & 7;
13432 modrm.rm = *codep & 7;
13438 memset (&vex, 0, sizeof (vex));
13440 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13442 get_sib (info, sizeflag);
13443 dofloat (sizeflag);
13447 dp = get_valid_dis386 (dp, info);
13448 if (dp != NULL && putop (dp->name, sizeflag) == 0)
13450 get_sib (info, sizeflag);
13451 for (i = 0; i < MAX_OPERANDS; ++i)
13454 op_ad = MAX_OPERANDS - 1 - i;
13456 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13457 /* For EVEX instruction after the last operand masking
13458 should be printed. */
13459 if (i == 0 && vex.evex)
13461 /* Don't print {%k0}. */
13462 if (vex.mask_register_specifier)
13465 oappend (names_mask[vex.mask_register_specifier]);
13475 /* Check if the REX prefix is used. */
13476 if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13477 all_prefixes[last_rex_prefix] = 0;
13479 /* Check if the SEG prefix is used. */
13480 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13481 | PREFIX_FS | PREFIX_GS)) != 0
13482 && (used_prefixes & active_seg_prefix) != 0)
13483 all_prefixes[last_seg_prefix] = 0;
13485 /* Check if the ADDR prefix is used. */
13486 if ((prefixes & PREFIX_ADDR) != 0
13487 && (used_prefixes & PREFIX_ADDR) != 0)
13488 all_prefixes[last_addr_prefix] = 0;
13490 /* Check if the DATA prefix is used. */
13491 if ((prefixes & PREFIX_DATA) != 0
13492 && (used_prefixes & PREFIX_DATA) != 0)
13493 all_prefixes[last_data_prefix] = 0;
13495 /* Print the extra prefixes. */
13497 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13498 if (all_prefixes[i])
13501 name = prefix_name (all_prefixes[i], orig_sizeflag);
13504 prefix_length += strlen (name) + 1;
13505 (*info->fprintf_func) (info->stream, "%s ", name);
13508 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13509 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13510 used by putop and MMX/SSE operand and may be overriden by the
13511 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13513 if (dp->prefix_requirement == PREFIX_OPCODE
13514 && dp != &bad_opcode
13516 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13518 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13520 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13522 && (used_prefixes & PREFIX_DATA) == 0))))
13524 (*info->fprintf_func) (info->stream, "(bad)");
13525 return end_codep - priv.the_buffer;
13528 /* Check maximum code length. */
13529 if ((codep - start_codep) > MAX_CODE_LENGTH)
13531 (*info->fprintf_func) (info->stream, "(bad)");
13532 return MAX_CODE_LENGTH;
13535 obufp = mnemonicendp;
13536 for (i = strlen (obuf) + prefix_length; i < 6; i++)
13539 (*info->fprintf_func) (info->stream, "%s", obuf);
13541 /* The enter and bound instructions are printed with operands in the same
13542 order as the intel book; everything else is printed in reverse order. */
13543 if (intel_syntax || two_source_ops)
13547 for (i = 0; i < MAX_OPERANDS; ++i)
13548 op_txt[i] = op_out[i];
13550 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13551 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13553 op_txt[2] = op_out[3];
13554 op_txt[3] = op_out[2];
13557 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13559 op_ad = op_index[i];
13560 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13561 op_index[MAX_OPERANDS - 1 - i] = op_ad;
13562 riprel = op_riprel[i];
13563 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13564 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13569 for (i = 0; i < MAX_OPERANDS; ++i)
13570 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13574 for (i = 0; i < MAX_OPERANDS; ++i)
13578 (*info->fprintf_func) (info->stream, ",");
13579 if (op_index[i] != -1 && !op_riprel[i])
13580 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13582 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13586 for (i = 0; i < MAX_OPERANDS; i++)
13587 if (op_index[i] != -1 && op_riprel[i])
13589 (*info->fprintf_func) (info->stream, " # ");
13590 (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13591 + op_address[op_index[i]]), info);
13594 return codep - priv.the_buffer;
13597 static const char *float_mem[] = {
13672 static const unsigned char float_mem_mode[] = {
13747 #define ST { OP_ST, 0 }
13748 #define STi { OP_STi, 0 }
13750 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13751 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13752 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13753 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13754 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13755 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13756 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13757 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13758 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13760 static const struct dis386 float_reg[][8] = {
13763 { "fadd", { ST, STi }, 0 },
13764 { "fmul", { ST, STi }, 0 },
13765 { "fcom", { STi }, 0 },
13766 { "fcomp", { STi }, 0 },
13767 { "fsub", { ST, STi }, 0 },
13768 { "fsubr", { ST, STi }, 0 },
13769 { "fdiv", { ST, STi }, 0 },
13770 { "fdivr", { ST, STi }, 0 },
13774 { "fld", { STi }, 0 },
13775 { "fxch", { STi }, 0 },
13785 { "fcmovb", { ST, STi }, 0 },
13786 { "fcmove", { ST, STi }, 0 },
13787 { "fcmovbe",{ ST, STi }, 0 },
13788 { "fcmovu", { ST, STi }, 0 },
13796 { "fcmovnb",{ ST, STi }, 0 },
13797 { "fcmovne",{ ST, STi }, 0 },
13798 { "fcmovnbe",{ ST, STi }, 0 },
13799 { "fcmovnu",{ ST, STi }, 0 },
13801 { "fucomi", { ST, STi }, 0 },
13802 { "fcomi", { ST, STi }, 0 },
13807 { "fadd", { STi, ST }, 0 },
13808 { "fmul", { STi, ST }, 0 },
13811 { "fsub{!M|r}", { STi, ST }, 0 },
13812 { "fsub{M|}", { STi, ST }, 0 },
13813 { "fdiv{!M|r}", { STi, ST }, 0 },
13814 { "fdiv{M|}", { STi, ST }, 0 },
13818 { "ffree", { STi }, 0 },
13820 { "fst", { STi }, 0 },
13821 { "fstp", { STi }, 0 },
13822 { "fucom", { STi }, 0 },
13823 { "fucomp", { STi }, 0 },
13829 { "faddp", { STi, ST }, 0 },
13830 { "fmulp", { STi, ST }, 0 },
13833 { "fsub{!M|r}p", { STi, ST }, 0 },
13834 { "fsub{M|}p", { STi, ST }, 0 },
13835 { "fdiv{!M|r}p", { STi, ST }, 0 },
13836 { "fdiv{M|}p", { STi, ST }, 0 },
13840 { "ffreep", { STi }, 0 },
13845 { "fucomip", { ST, STi }, 0 },
13846 { "fcomip", { ST, STi }, 0 },
13851 static char *fgrps[][8] = {
13854 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13859 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13864 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13869 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13874 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13879 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13884 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13889 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13890 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13895 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13900 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13905 swap_operand (void)
13907 mnemonicendp[0] = '.';
13908 mnemonicendp[1] = 's';
13913 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13914 int sizeflag ATTRIBUTE_UNUSED)
13916 /* Skip mod/rm byte. */
13922 dofloat (int sizeflag)
13924 const struct dis386 *dp;
13925 unsigned char floatop;
13927 floatop = codep[-1];
13929 if (modrm.mod != 3)
13931 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13933 putop (float_mem[fp_indx], sizeflag);
13936 OP_E (float_mem_mode[fp_indx], sizeflag);
13939 /* Skip mod/rm byte. */
13943 dp = &float_reg[floatop - 0xd8][modrm.reg];
13944 if (dp->name == NULL)
13946 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13948 /* Instruction fnstsw is only one with strange arg. */
13949 if (floatop == 0xdf && codep[-1] == 0xe0)
13950 strcpy (op_out[0], names16[0]);
13954 putop (dp->name, sizeflag);
13959 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13964 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13968 /* Like oappend (below), but S is a string starting with '%'.
13969 In Intel syntax, the '%' is elided. */
13971 oappend_maybe_intel (const char *s)
13973 oappend (s + intel_syntax);
13977 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13979 oappend_maybe_intel ("%st");
13983 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13985 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13986 oappend_maybe_intel (scratchbuf);
13989 /* Capital letters in template are macros. */
13991 putop (const char *in_template, int sizeflag)
13996 unsigned int l = 0, len = 1;
13999 #define SAVE_LAST(c) \
14000 if (l < len && l < sizeof (last)) \
14005 for (p = in_template; *p; p++)
14021 while (*++p != '|')
14022 if (*p == '}' || *p == '\0')
14025 /* Fall through. */
14030 while (*++p != '}')
14041 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14045 if (l == 0 && len == 1)
14050 if (sizeflag & SUFFIX_ALWAYS)
14063 if (address_mode == mode_64bit
14064 && !(prefixes & PREFIX_ADDR))
14075 if (intel_syntax && !alt)
14077 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14079 if (sizeflag & DFLAG)
14080 *obufp++ = intel_syntax ? 'd' : 'l';
14082 *obufp++ = intel_syntax ? 'w' : 's';
14083 used_prefixes |= (prefixes & PREFIX_DATA);
14087 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14090 if (modrm.mod == 3)
14096 if (sizeflag & DFLAG)
14097 *obufp++ = intel_syntax ? 'd' : 'l';
14100 used_prefixes |= (prefixes & PREFIX_DATA);
14106 case 'E': /* For jcxz/jecxz */
14107 if (address_mode == mode_64bit)
14109 if (sizeflag & AFLAG)
14115 if (sizeflag & AFLAG)
14117 used_prefixes |= (prefixes & PREFIX_ADDR);
14122 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14124 if (sizeflag & AFLAG)
14125 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14127 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14128 used_prefixes |= (prefixes & PREFIX_ADDR);
14132 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14134 if ((rex & REX_W) || (sizeflag & DFLAG))
14138 if (!(rex & REX_W))
14139 used_prefixes |= (prefixes & PREFIX_DATA);
14144 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14145 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14147 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14150 if (prefixes & PREFIX_DS)
14169 if (l != 0 || len != 1)
14171 if (l != 1 || len != 2 || last[0] != 'X')
14176 if (!need_vex || !vex.evex)
14179 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14181 switch (vex.length)
14199 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14204 /* Fall through. */
14207 if (l != 0 || len != 1)
14215 if (sizeflag & SUFFIX_ALWAYS)
14219 if (intel_mnemonic != cond)
14223 if ((prefixes & PREFIX_FWAIT) == 0)
14226 used_prefixes |= PREFIX_FWAIT;
14232 else if (intel_syntax && (sizeflag & DFLAG))
14236 if (!(rex & REX_W))
14237 used_prefixes |= (prefixes & PREFIX_DATA);
14241 && address_mode == mode_64bit
14242 && isa64 == intel64)
14247 /* Fall through. */
14250 && address_mode == mode_64bit
14251 && ((sizeflag & DFLAG) || (rex & REX_W)))
14256 /* Fall through. */
14259 if (l == 0 && len == 1)
14264 if ((rex & REX_W) == 0
14265 && (prefixes & PREFIX_DATA))
14267 if ((sizeflag & DFLAG) == 0)
14269 used_prefixes |= (prefixes & PREFIX_DATA);
14273 if ((prefixes & PREFIX_DATA)
14275 || (sizeflag & SUFFIX_ALWAYS))
14282 if (sizeflag & DFLAG)
14286 used_prefixes |= (prefixes & PREFIX_DATA);
14292 if (l != 1 || len != 2 || last[0] != 'L')
14298 if ((prefixes & PREFIX_DATA)
14300 || (sizeflag & SUFFIX_ALWAYS))
14307 if (sizeflag & DFLAG)
14308 *obufp++ = intel_syntax ? 'd' : 'l';
14311 used_prefixes |= (prefixes & PREFIX_DATA);
14319 if (address_mode == mode_64bit
14320 && ((sizeflag & DFLAG) || (rex & REX_W)))
14322 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14326 /* Fall through. */
14329 if (l == 0 && len == 1)
14332 if (intel_syntax && !alt)
14335 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14341 if (sizeflag & DFLAG)
14342 *obufp++ = intel_syntax ? 'd' : 'l';
14345 used_prefixes |= (prefixes & PREFIX_DATA);
14351 if (l != 1 || len != 2 || last[0] != 'L')
14357 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14372 else if (sizeflag & DFLAG)
14381 if (intel_syntax && !p[1]
14382 && ((rex & REX_W) || (sizeflag & DFLAG)))
14384 if (!(rex & REX_W))
14385 used_prefixes |= (prefixes & PREFIX_DATA);
14388 if (l == 0 && len == 1)
14392 if (address_mode == mode_64bit
14393 && ((sizeflag & DFLAG) || (rex & REX_W)))
14395 if (sizeflag & SUFFIX_ALWAYS)
14417 /* Fall through. */
14420 if (l == 0 && len == 1)
14425 if (sizeflag & SUFFIX_ALWAYS)
14431 if (sizeflag & DFLAG)
14435 used_prefixes |= (prefixes & PREFIX_DATA);
14449 if (address_mode == mode_64bit
14450 && !(prefixes & PREFIX_ADDR))
14461 if (l != 0 || len != 1)
14466 if (need_vex && vex.prefix)
14468 if (vex.prefix == DATA_PREFIX_OPCODE)
14475 if (prefixes & PREFIX_DATA)
14479 used_prefixes |= (prefixes & PREFIX_DATA);
14483 if (l == 0 && len == 1)
14487 if (l != 1 || len != 2 || last[0] != 'X')
14495 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14497 switch (vex.length)
14513 if (l == 0 && len == 1)
14515 /* operand size flag for cwtl, cbtw */
14524 else if (sizeflag & DFLAG)
14528 if (!(rex & REX_W))
14529 used_prefixes |= (prefixes & PREFIX_DATA);
14536 && last[0] != 'L'))
14543 if (last[0] == 'X')
14544 *obufp++ = vex.w ? 'd': 's';
14546 *obufp++ = vex.w ? 'q': 'd';
14552 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14554 if (sizeflag & DFLAG)
14558 used_prefixes |= (prefixes & PREFIX_DATA);
14564 if (address_mode == mode_64bit
14565 && (isa64 == intel64
14566 || ((sizeflag & DFLAG) || (rex & REX_W))))
14568 else if ((prefixes & PREFIX_DATA))
14570 if (!(sizeflag & DFLAG))
14572 used_prefixes |= (prefixes & PREFIX_DATA);
14579 mnemonicendp = obufp;
14584 oappend (const char *s)
14586 obufp = stpcpy (obufp, s);
14592 /* Only print the active segment register. */
14593 if (!active_seg_prefix)
14596 used_prefixes |= active_seg_prefix;
14597 switch (active_seg_prefix)
14600 oappend_maybe_intel ("%cs:");
14603 oappend_maybe_intel ("%ds:");
14606 oappend_maybe_intel ("%ss:");
14609 oappend_maybe_intel ("%es:");
14612 oappend_maybe_intel ("%fs:");
14615 oappend_maybe_intel ("%gs:");
14623 OP_indirE (int bytemode, int sizeflag)
14627 OP_E (bytemode, sizeflag);
14631 print_operand_value (char *buf, int hex, bfd_vma disp)
14633 if (address_mode == mode_64bit)
14641 sprintf_vma (tmp, disp);
14642 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14643 strcpy (buf + 2, tmp + i);
14647 bfd_signed_vma v = disp;
14654 /* Check for possible overflow on 0x8000000000000000. */
14657 strcpy (buf, "9223372036854775808");
14671 tmp[28 - i] = (v % 10) + '0';
14675 strcpy (buf, tmp + 29 - i);
14681 sprintf (buf, "0x%x", (unsigned int) disp);
14683 sprintf (buf, "%d", (int) disp);
14687 /* Put DISP in BUF as signed hex number. */
14690 print_displacement (char *buf, bfd_vma disp)
14692 bfd_signed_vma val = disp;
14701 /* Check for possible overflow. */
14704 switch (address_mode)
14707 strcpy (buf + j, "0x8000000000000000");
14710 strcpy (buf + j, "0x80000000");
14713 strcpy (buf + j, "0x8000");
14723 sprintf_vma (tmp, (bfd_vma) val);
14724 for (i = 0; tmp[i] == '0'; i++)
14726 if (tmp[i] == '\0')
14728 strcpy (buf + j, tmp + i);
14732 intel_operand_size (int bytemode, int sizeflag)
14736 && (bytemode == x_mode
14737 || bytemode == evex_half_bcst_xmmq_mode))
14740 oappend ("QWORD PTR ");
14742 oappend ("DWORD PTR ");
14751 oappend ("BYTE PTR ");
14756 oappend ("WORD PTR ");
14759 if (address_mode == mode_64bit && isa64 == intel64)
14761 oappend ("QWORD PTR ");
14764 /* Fall through. */
14766 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14768 oappend ("QWORD PTR ");
14771 /* Fall through. */
14777 oappend ("QWORD PTR ");
14780 if ((sizeflag & DFLAG) || bytemode == dq_mode)
14781 oappend ("DWORD PTR ");
14783 oappend ("WORD PTR ");
14784 used_prefixes |= (prefixes & PREFIX_DATA);
14788 if ((rex & REX_W) || (sizeflag & DFLAG))
14790 oappend ("WORD PTR ");
14791 if (!(rex & REX_W))
14792 used_prefixes |= (prefixes & PREFIX_DATA);
14795 if (sizeflag & DFLAG)
14796 oappend ("QWORD PTR ");
14798 oappend ("DWORD PTR ");
14799 used_prefixes |= (prefixes & PREFIX_DATA);
14802 case d_scalar_mode:
14803 case d_scalar_swap_mode:
14806 oappend ("DWORD PTR ");
14809 case q_scalar_mode:
14810 case q_scalar_swap_mode:
14812 oappend ("QWORD PTR ");
14816 if (address_mode == mode_64bit)
14817 oappend ("QWORD PTR ");
14819 oappend ("DWORD PTR ");
14822 if (sizeflag & DFLAG)
14823 oappend ("FWORD PTR ");
14825 oappend ("DWORD PTR ");
14826 used_prefixes |= (prefixes & PREFIX_DATA);
14829 oappend ("TBYTE PTR ");
14833 case evex_x_gscat_mode:
14834 case evex_x_nobcst_mode:
14835 case b_scalar_mode:
14836 case w_scalar_mode:
14839 switch (vex.length)
14842 oappend ("XMMWORD PTR ");
14845 oappend ("YMMWORD PTR ");
14848 oappend ("ZMMWORD PTR ");
14855 oappend ("XMMWORD PTR ");
14858 oappend ("XMMWORD PTR ");
14861 oappend ("YMMWORD PTR ");
14864 case evex_half_bcst_xmmq_mode:
14868 switch (vex.length)
14871 oappend ("QWORD PTR ");
14874 oappend ("XMMWORD PTR ");
14877 oappend ("YMMWORD PTR ");
14887 switch (vex.length)
14892 oappend ("BYTE PTR ");
14902 switch (vex.length)
14907 oappend ("WORD PTR ");
14917 switch (vex.length)
14922 oappend ("DWORD PTR ");
14932 switch (vex.length)
14937 oappend ("QWORD PTR ");
14947 switch (vex.length)
14950 oappend ("WORD PTR ");
14953 oappend ("DWORD PTR ");
14956 oappend ("QWORD PTR ");
14966 switch (vex.length)
14969 oappend ("DWORD PTR ");
14972 oappend ("QWORD PTR ");
14975 oappend ("XMMWORD PTR ");
14985 switch (vex.length)
14988 oappend ("QWORD PTR ");
14991 oappend ("YMMWORD PTR ");
14994 oappend ("ZMMWORD PTR ");
15004 switch (vex.length)
15008 oappend ("XMMWORD PTR ");
15015 oappend ("OWORD PTR ");
15018 case vex_w_dq_mode:
15019 case vex_scalar_w_dq_mode:
15024 oappend ("QWORD PTR ");
15026 oappend ("DWORD PTR ");
15028 case vex_vsib_d_w_dq_mode:
15029 case vex_vsib_q_w_dq_mode:
15036 oappend ("QWORD PTR ");
15038 oappend ("DWORD PTR ");
15042 switch (vex.length)
15045 oappend ("XMMWORD PTR ");
15048 oappend ("YMMWORD PTR ");
15051 oappend ("ZMMWORD PTR ");
15058 case vex_vsib_q_w_d_mode:
15059 case vex_vsib_d_w_d_mode:
15060 if (!need_vex || !vex.evex)
15063 switch (vex.length)
15066 oappend ("QWORD PTR ");
15069 oappend ("XMMWORD PTR ");
15072 oappend ("YMMWORD PTR ");
15080 if (!need_vex || vex.length != 128)
15083 oappend ("DWORD PTR ");
15085 oappend ("BYTE PTR ");
15091 oappend ("QWORD PTR ");
15093 oappend ("WORD PTR ");
15103 OP_E_register (int bytemode, int sizeflag)
15105 int reg = modrm.rm;
15106 const char **names;
15112 if ((sizeflag & SUFFIX_ALWAYS)
15113 && (bytemode == b_swap_mode
15114 || bytemode == bnd_swap_mode
15115 || bytemode == v_swap_mode))
15141 names = address_mode == mode_64bit ? names64 : names32;
15144 case bnd_swap_mode:
15153 if (address_mode == mode_64bit && isa64 == intel64)
15158 /* Fall through. */
15160 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15166 /* Fall through. */
15179 if ((sizeflag & DFLAG)
15180 || (bytemode != v_mode
15181 && bytemode != v_swap_mode))
15185 used_prefixes |= (prefixes & PREFIX_DATA);
15189 names = (address_mode == mode_64bit
15190 ? names64 : names32);
15191 if (!(prefixes & PREFIX_ADDR))
15192 names = (address_mode == mode_16bit
15193 ? names16 : names);
15196 /* Remove "addr16/addr32". */
15197 all_prefixes[last_addr_prefix] = 0;
15198 names = (address_mode != mode_32bit
15199 ? names32 : names16);
15200 used_prefixes |= PREFIX_ADDR;
15210 names = names_mask;
15215 oappend (INTERNAL_DISASSEMBLER_ERROR);
15218 oappend (names[reg]);
15222 OP_E_memory (int bytemode, int sizeflag)
15225 int add = (rex & REX_B) ? 8 : 0;
15231 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
15233 && bytemode != x_mode
15234 && bytemode != xmmq_mode
15235 && bytemode != evex_half_bcst_xmmq_mode)
15250 case vex_vsib_d_w_dq_mode:
15251 case vex_vsib_d_w_d_mode:
15252 case vex_vsib_q_w_dq_mode:
15253 case vex_vsib_q_w_d_mode:
15254 case evex_x_gscat_mode:
15256 shift = vex.w ? 3 : 2;
15259 case evex_half_bcst_xmmq_mode:
15263 shift = vex.w ? 3 : 2;
15266 /* Fall through. */
15270 case evex_x_nobcst_mode:
15272 switch (vex.length)
15295 case q_scalar_mode:
15297 case q_scalar_swap_mode:
15303 case d_scalar_mode:
15305 case d_scalar_swap_mode:
15308 case w_scalar_mode:
15312 case b_scalar_mode:
15317 shift = address_mode == mode_64bit ? 3 : 2;
15322 /* Make necessary corrections to shift for modes that need it.
15323 For these modes we currently have shift 4, 5 or 6 depending on
15324 vex.length (it corresponds to xmmword, ymmword or zmmword
15325 operand). We might want to make it 3, 4 or 5 (e.g. for
15326 xmmq_mode). In case of broadcast enabled the corrections
15327 aren't needed, as element size is always 32 or 64 bits. */
15329 && (bytemode == xmmq_mode
15330 || bytemode == evex_half_bcst_xmmq_mode))
15332 else if (bytemode == xmmqd_mode)
15334 else if (bytemode == xmmdw_mode)
15336 else if (bytemode == ymmq_mode && vex.length == 128)
15344 intel_operand_size (bytemode, sizeflag);
15347 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15349 /* 32/64 bit address mode */
15359 int addr32flag = !((sizeflag & AFLAG)
15360 || bytemode == v_bnd_mode
15361 || bytemode == v_bndmk_mode
15362 || bytemode == bnd_mode
15363 || bytemode == bnd_swap_mode);
15364 const char **indexes64 = names64;
15365 const char **indexes32 = names32;
15375 vindex = sib.index;
15381 case vex_vsib_d_w_dq_mode:
15382 case vex_vsib_d_w_d_mode:
15383 case vex_vsib_q_w_dq_mode:
15384 case vex_vsib_q_w_d_mode:
15394 switch (vex.length)
15397 indexes64 = indexes32 = names_xmm;
15401 || bytemode == vex_vsib_q_w_dq_mode
15402 || bytemode == vex_vsib_q_w_d_mode)
15403 indexes64 = indexes32 = names_ymm;
15405 indexes64 = indexes32 = names_xmm;
15409 || bytemode == vex_vsib_q_w_dq_mode
15410 || bytemode == vex_vsib_q_w_d_mode)
15411 indexes64 = indexes32 = names_zmm;
15413 indexes64 = indexes32 = names_ymm;
15420 haveindex = vindex != 4;
15427 rbase = base + add;
15435 if (address_mode == mode_64bit && !havesib)
15438 if (riprel && bytemode == v_bndmk_mode)
15446 FETCH_DATA (the_info, codep + 1);
15448 if ((disp & 0x80) != 0)
15450 if (vex.evex && shift > 0)
15463 && address_mode != mode_16bit)
15465 if (address_mode == mode_64bit)
15467 /* Display eiz instead of addr32. */
15468 needindex = addr32flag;
15473 /* In 32-bit mode, we need index register to tell [offset]
15474 from [eiz*1 + offset]. */
15479 havedisp = (havebase
15481 || (havesib && (haveindex || scale != 0)));
15484 if (modrm.mod != 0 || base == 5)
15486 if (havedisp || riprel)
15487 print_displacement (scratchbuf, disp);
15489 print_operand_value (scratchbuf, 1, disp);
15490 oappend (scratchbuf);
15494 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15498 if ((havebase || haveindex || needaddr32 || riprel)
15499 && (bytemode != v_bnd_mode)
15500 && (bytemode != v_bndmk_mode)
15501 && (bytemode != bnd_mode)
15502 && (bytemode != bnd_swap_mode))
15503 used_prefixes |= PREFIX_ADDR;
15505 if (havedisp || (intel_syntax && riprel))
15507 *obufp++ = open_char;
15508 if (intel_syntax && riprel)
15511 oappend (!addr32flag ? "rip" : "eip");
15515 oappend (address_mode == mode_64bit && !addr32flag
15516 ? names64[rbase] : names32[rbase]);
15519 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15520 print index to tell base + index from base. */
15524 || (havebase && base != ESP_REG_NUM))
15526 if (!intel_syntax || havebase)
15528 *obufp++ = separator_char;
15532 oappend (address_mode == mode_64bit && !addr32flag
15533 ? indexes64[vindex] : indexes32[vindex]);
15535 oappend (address_mode == mode_64bit && !addr32flag
15536 ? index64 : index32);
15538 *obufp++ = scale_char;
15540 sprintf (scratchbuf, "%d", 1 << scale);
15541 oappend (scratchbuf);
15545 && (disp || modrm.mod != 0 || base == 5))
15547 if (!havedisp || (bfd_signed_vma) disp >= 0)
15552 else if (modrm.mod != 1 && disp != -disp)
15556 disp = - (bfd_signed_vma) disp;
15560 print_displacement (scratchbuf, disp);
15562 print_operand_value (scratchbuf, 1, disp);
15563 oappend (scratchbuf);
15566 *obufp++ = close_char;
15569 else if (intel_syntax)
15571 if (modrm.mod != 0 || base == 5)
15573 if (!active_seg_prefix)
15575 oappend (names_seg[ds_reg - es_reg]);
15578 print_operand_value (scratchbuf, 1, disp);
15579 oappend (scratchbuf);
15585 /* 16 bit address mode */
15586 used_prefixes |= prefixes & PREFIX_ADDR;
15593 if ((disp & 0x8000) != 0)
15598 FETCH_DATA (the_info, codep + 1);
15600 if ((disp & 0x80) != 0)
15602 if (vex.evex && shift > 0)
15607 if ((disp & 0x8000) != 0)
15613 if (modrm.mod != 0 || modrm.rm == 6)
15615 print_displacement (scratchbuf, disp);
15616 oappend (scratchbuf);
15619 if (modrm.mod != 0 || modrm.rm != 6)
15621 *obufp++ = open_char;
15623 oappend (index16[modrm.rm]);
15625 && (disp || modrm.mod != 0 || modrm.rm == 6))
15627 if ((bfd_signed_vma) disp >= 0)
15632 else if (modrm.mod != 1)
15636 disp = - (bfd_signed_vma) disp;
15639 print_displacement (scratchbuf, disp);
15640 oappend (scratchbuf);
15643 *obufp++ = close_char;
15646 else if (intel_syntax)
15648 if (!active_seg_prefix)
15650 oappend (names_seg[ds_reg - es_reg]);
15653 print_operand_value (scratchbuf, 1, disp & 0xffff);
15654 oappend (scratchbuf);
15657 if (vex.evex && vex.b
15658 && (bytemode == x_mode
15659 || bytemode == xmmq_mode
15660 || bytemode == evex_half_bcst_xmmq_mode))
15663 || bytemode == xmmq_mode
15664 || bytemode == evex_half_bcst_xmmq_mode)
15666 switch (vex.length)
15669 oappend ("{1to2}");
15672 oappend ("{1to4}");
15675 oappend ("{1to8}");
15683 switch (vex.length)
15686 oappend ("{1to4}");
15689 oappend ("{1to8}");
15692 oappend ("{1to16}");
15702 OP_E (int bytemode, int sizeflag)
15704 /* Skip mod/rm byte. */
15708 if (modrm.mod == 3)
15709 OP_E_register (bytemode, sizeflag);
15711 OP_E_memory (bytemode, sizeflag);
15715 OP_G (int bytemode, int sizeflag)
15718 const char **names;
15727 oappend (names8rex[modrm.reg + add]);
15729 oappend (names8[modrm.reg + add]);
15732 oappend (names16[modrm.reg + add]);
15737 oappend (names32[modrm.reg + add]);
15740 oappend (names64[modrm.reg + add]);
15743 if (modrm.reg > 0x3)
15748 oappend (names_bnd[modrm.reg]);
15757 oappend (names64[modrm.reg + add]);
15760 if ((sizeflag & DFLAG) || bytemode != v_mode)
15761 oappend (names32[modrm.reg + add]);
15763 oappend (names16[modrm.reg + add]);
15764 used_prefixes |= (prefixes & PREFIX_DATA);
15768 names = (address_mode == mode_64bit
15769 ? names64 : names32);
15770 if (!(prefixes & PREFIX_ADDR))
15772 if (address_mode == mode_16bit)
15777 /* Remove "addr16/addr32". */
15778 all_prefixes[last_addr_prefix] = 0;
15779 names = (address_mode != mode_32bit
15780 ? names32 : names16);
15781 used_prefixes |= PREFIX_ADDR;
15783 oappend (names[modrm.reg + add]);
15786 if (address_mode == mode_64bit)
15787 oappend (names64[modrm.reg + add]);
15789 oappend (names32[modrm.reg + add]);
15793 if ((modrm.reg + add) > 0x7)
15798 oappend (names_mask[modrm.reg + add]);
15801 oappend (INTERNAL_DISASSEMBLER_ERROR);
15814 FETCH_DATA (the_info, codep + 8);
15815 a = *codep++ & 0xff;
15816 a |= (*codep++ & 0xff) << 8;
15817 a |= (*codep++ & 0xff) << 16;
15818 a |= (*codep++ & 0xffu) << 24;
15819 b = *codep++ & 0xff;
15820 b |= (*codep++ & 0xff) << 8;
15821 b |= (*codep++ & 0xff) << 16;
15822 b |= (*codep++ & 0xffu) << 24;
15823 x = a + ((bfd_vma) b << 32);
15831 static bfd_signed_vma
15834 bfd_signed_vma x = 0;
15836 FETCH_DATA (the_info, codep + 4);
15837 x = *codep++ & (bfd_signed_vma) 0xff;
15838 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15839 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15840 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15844 static bfd_signed_vma
15847 bfd_signed_vma x = 0;
15849 FETCH_DATA (the_info, codep + 4);
15850 x = *codep++ & (bfd_signed_vma) 0xff;
15851 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15852 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15853 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15855 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15865 FETCH_DATA (the_info, codep + 2);
15866 x = *codep++ & 0xff;
15867 x |= (*codep++ & 0xff) << 8;
15872 set_op (bfd_vma op, int riprel)
15874 op_index[op_ad] = op_ad;
15875 if (address_mode == mode_64bit)
15877 op_address[op_ad] = op;
15878 op_riprel[op_ad] = riprel;
15882 /* Mask to get a 32-bit address. */
15883 op_address[op_ad] = op & 0xffffffff;
15884 op_riprel[op_ad] = riprel & 0xffffffff;
15889 OP_REG (int code, int sizeflag)
15896 case es_reg: case ss_reg: case cs_reg:
15897 case ds_reg: case fs_reg: case gs_reg:
15898 oappend (names_seg[code - es_reg]);
15910 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15911 case sp_reg: case bp_reg: case si_reg: case di_reg:
15912 s = names16[code - ax_reg + add];
15914 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15915 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15918 s = names8rex[code - al_reg + add];
15920 s = names8[code - al_reg];
15922 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15923 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15924 if (address_mode == mode_64bit
15925 && ((sizeflag & DFLAG) || (rex & REX_W)))
15927 s = names64[code - rAX_reg + add];
15930 code += eAX_reg - rAX_reg;
15931 /* Fall through. */
15932 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15933 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15936 s = names64[code - eAX_reg + add];
15939 if (sizeflag & DFLAG)
15940 s = names32[code - eAX_reg + add];
15942 s = names16[code - eAX_reg + add];
15943 used_prefixes |= (prefixes & PREFIX_DATA);
15947 s = INTERNAL_DISASSEMBLER_ERROR;
15954 OP_IMREG (int code, int sizeflag)
15966 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15967 case sp_reg: case bp_reg: case si_reg: case di_reg:
15968 s = names16[code - ax_reg];
15970 case es_reg: case ss_reg: case cs_reg:
15971 case ds_reg: case fs_reg: case gs_reg:
15972 s = names_seg[code - es_reg];
15974 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15975 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15978 s = names8rex[code - al_reg];
15980 s = names8[code - al_reg];
15982 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15983 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15986 s = names64[code - eAX_reg];
15989 if (sizeflag & DFLAG)
15990 s = names32[code - eAX_reg];
15992 s = names16[code - eAX_reg];
15993 used_prefixes |= (prefixes & PREFIX_DATA);
15996 case z_mode_ax_reg:
15997 if ((rex & REX_W) || (sizeflag & DFLAG))
16001 if (!(rex & REX_W))
16002 used_prefixes |= (prefixes & PREFIX_DATA);
16005 s = INTERNAL_DISASSEMBLER_ERROR;
16012 OP_I (int bytemode, int sizeflag)
16015 bfd_signed_vma mask = -1;
16020 FETCH_DATA (the_info, codep + 1);
16025 if (address_mode == mode_64bit)
16030 /* Fall through. */
16037 if (sizeflag & DFLAG)
16047 used_prefixes |= (prefixes & PREFIX_DATA);
16059 oappend (INTERNAL_DISASSEMBLER_ERROR);
16064 scratchbuf[0] = '$';
16065 print_operand_value (scratchbuf + 1, 1, op);
16066 oappend_maybe_intel (scratchbuf);
16067 scratchbuf[0] = '\0';
16071 OP_I64 (int bytemode, int sizeflag)
16074 bfd_signed_vma mask = -1;
16076 if (address_mode != mode_64bit)
16078 OP_I (bytemode, sizeflag);
16085 FETCH_DATA (the_info, codep + 1);
16095 if (sizeflag & DFLAG)
16105 used_prefixes |= (prefixes & PREFIX_DATA);
16113 oappend (INTERNAL_DISASSEMBLER_ERROR);
16118 scratchbuf[0] = '$';
16119 print_operand_value (scratchbuf + 1, 1, op);
16120 oappend_maybe_intel (scratchbuf);
16121 scratchbuf[0] = '\0';
16125 OP_sI (int bytemode, int sizeflag)
16133 FETCH_DATA (the_info, codep + 1);
16135 if ((op & 0x80) != 0)
16137 if (bytemode == b_T_mode)
16139 if (address_mode != mode_64bit
16140 || !((sizeflag & DFLAG) || (rex & REX_W)))
16142 /* The operand-size prefix is overridden by a REX prefix. */
16143 if ((sizeflag & DFLAG) || (rex & REX_W))
16151 if (!(rex & REX_W))
16153 if (sizeflag & DFLAG)
16161 /* The operand-size prefix is overridden by a REX prefix. */
16162 if ((sizeflag & DFLAG) || (rex & REX_W))
16168 oappend (INTERNAL_DISASSEMBLER_ERROR);
16172 scratchbuf[0] = '$';
16173 print_operand_value (scratchbuf + 1, 1, op);
16174 oappend_maybe_intel (scratchbuf);
16178 OP_J (int bytemode, int sizeflag)
16182 bfd_vma segment = 0;
16187 FETCH_DATA (the_info, codep + 1);
16189 if ((disp & 0x80) != 0)
16193 if (isa64 == amd64)
16195 if ((sizeflag & DFLAG)
16196 || (address_mode == mode_64bit
16197 && (isa64 != amd64 || (rex & REX_W))))
16202 if ((disp & 0x8000) != 0)
16204 /* In 16bit mode, address is wrapped around at 64k within
16205 the same segment. Otherwise, a data16 prefix on a jump
16206 instruction means that the pc is masked to 16 bits after
16207 the displacement is added! */
16209 if ((prefixes & PREFIX_DATA) == 0)
16210 segment = ((start_pc + (codep - start_codep))
16211 & ~((bfd_vma) 0xffff));
16213 if (address_mode != mode_64bit
16214 || (isa64 == amd64 && !(rex & REX_W)))
16215 used_prefixes |= (prefixes & PREFIX_DATA);
16218 oappend (INTERNAL_DISASSEMBLER_ERROR);
16221 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16223 print_operand_value (scratchbuf, 1, disp);
16224 oappend (scratchbuf);
16228 OP_SEG (int bytemode, int sizeflag)
16230 if (bytemode == w_mode)
16231 oappend (names_seg[modrm.reg]);
16233 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16237 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16241 if (sizeflag & DFLAG)
16251 used_prefixes |= (prefixes & PREFIX_DATA);
16253 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16255 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16256 oappend (scratchbuf);
16260 OP_OFF (int bytemode, int sizeflag)
16264 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16265 intel_operand_size (bytemode, sizeflag);
16268 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16275 if (!active_seg_prefix)
16277 oappend (names_seg[ds_reg - es_reg]);
16281 print_operand_value (scratchbuf, 1, off);
16282 oappend (scratchbuf);
16286 OP_OFF64 (int bytemode, int sizeflag)
16290 if (address_mode != mode_64bit
16291 || (prefixes & PREFIX_ADDR))
16293 OP_OFF (bytemode, sizeflag);
16297 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16298 intel_operand_size (bytemode, sizeflag);
16305 if (!active_seg_prefix)
16307 oappend (names_seg[ds_reg - es_reg]);
16311 print_operand_value (scratchbuf, 1, off);
16312 oappend (scratchbuf);
16316 ptr_reg (int code, int sizeflag)
16320 *obufp++ = open_char;
16321 used_prefixes |= (prefixes & PREFIX_ADDR);
16322 if (address_mode == mode_64bit)
16324 if (!(sizeflag & AFLAG))
16325 s = names32[code - eAX_reg];
16327 s = names64[code - eAX_reg];
16329 else if (sizeflag & AFLAG)
16330 s = names32[code - eAX_reg];
16332 s = names16[code - eAX_reg];
16334 *obufp++ = close_char;
16339 OP_ESreg (int code, int sizeflag)
16345 case 0x6d: /* insw/insl */
16346 intel_operand_size (z_mode, sizeflag);
16348 case 0xa5: /* movsw/movsl/movsq */
16349 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16350 case 0xab: /* stosw/stosl */
16351 case 0xaf: /* scasw/scasl */
16352 intel_operand_size (v_mode, sizeflag);
16355 intel_operand_size (b_mode, sizeflag);
16358 oappend_maybe_intel ("%es:");
16359 ptr_reg (code, sizeflag);
16363 OP_DSreg (int code, int sizeflag)
16369 case 0x6f: /* outsw/outsl */
16370 intel_operand_size (z_mode, sizeflag);
16372 case 0xa5: /* movsw/movsl/movsq */
16373 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16374 case 0xad: /* lodsw/lodsl/lodsq */
16375 intel_operand_size (v_mode, sizeflag);
16378 intel_operand_size (b_mode, sizeflag);
16381 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16382 default segment register DS is printed. */
16383 if (!active_seg_prefix)
16384 active_seg_prefix = PREFIX_DS;
16386 ptr_reg (code, sizeflag);
16390 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16398 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16400 all_prefixes[last_lock_prefix] = 0;
16401 used_prefixes |= PREFIX_LOCK;
16406 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16407 oappend_maybe_intel (scratchbuf);
16411 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16420 sprintf (scratchbuf, "db%d", modrm.reg + add);
16422 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16423 oappend (scratchbuf);
16427 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16429 sprintf (scratchbuf, "%%tr%d", modrm.reg);
16430 oappend_maybe_intel (scratchbuf);
16434 OP_R (int bytemode, int sizeflag)
16436 /* Skip mod/rm byte. */
16439 OP_E_register (bytemode, sizeflag);
16443 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16445 int reg = modrm.reg;
16446 const char **names;
16448 used_prefixes |= (prefixes & PREFIX_DATA);
16449 if (prefixes & PREFIX_DATA)
16458 oappend (names[reg]);
16462 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16464 int reg = modrm.reg;
16465 const char **names;
16477 && bytemode != xmm_mode
16478 && bytemode != xmmq_mode
16479 && bytemode != evex_half_bcst_xmmq_mode
16480 && bytemode != ymm_mode
16481 && bytemode != scalar_mode)
16483 switch (vex.length)
16490 || (bytemode != vex_vsib_q_w_dq_mode
16491 && bytemode != vex_vsib_q_w_d_mode))
16503 else if (bytemode == xmmq_mode
16504 || bytemode == evex_half_bcst_xmmq_mode)
16506 switch (vex.length)
16519 else if (bytemode == ymm_mode)
16523 oappend (names[reg]);
16527 OP_EM (int bytemode, int sizeflag)
16530 const char **names;
16532 if (modrm.mod != 3)
16535 && (bytemode == v_mode || bytemode == v_swap_mode))
16537 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16538 used_prefixes |= (prefixes & PREFIX_DATA);
16540 OP_E (bytemode, sizeflag);
16544 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16547 /* Skip mod/rm byte. */
16550 used_prefixes |= (prefixes & PREFIX_DATA);
16552 if (prefixes & PREFIX_DATA)
16561 oappend (names[reg]);
16564 /* cvt* are the only instructions in sse2 which have
16565 both SSE and MMX operands and also have 0x66 prefix
16566 in their opcode. 0x66 was originally used to differentiate
16567 between SSE and MMX instruction(operands). So we have to handle the
16568 cvt* separately using OP_EMC and OP_MXC */
16570 OP_EMC (int bytemode, int sizeflag)
16572 if (modrm.mod != 3)
16574 if (intel_syntax && bytemode == v_mode)
16576 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16577 used_prefixes |= (prefixes & PREFIX_DATA);
16579 OP_E (bytemode, sizeflag);
16583 /* Skip mod/rm byte. */
16586 used_prefixes |= (prefixes & PREFIX_DATA);
16587 oappend (names_mm[modrm.rm]);
16591 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16593 used_prefixes |= (prefixes & PREFIX_DATA);
16594 oappend (names_mm[modrm.reg]);
16598 OP_EX (int bytemode, int sizeflag)
16601 const char **names;
16603 /* Skip mod/rm byte. */
16607 if (modrm.mod != 3)
16609 OP_E_memory (bytemode, sizeflag);
16624 if ((sizeflag & SUFFIX_ALWAYS)
16625 && (bytemode == x_swap_mode
16626 || bytemode == d_swap_mode
16627 || bytemode == d_scalar_swap_mode
16628 || bytemode == q_swap_mode
16629 || bytemode == q_scalar_swap_mode))
16633 && bytemode != xmm_mode
16634 && bytemode != xmmdw_mode
16635 && bytemode != xmmqd_mode
16636 && bytemode != xmm_mb_mode
16637 && bytemode != xmm_mw_mode
16638 && bytemode != xmm_md_mode
16639 && bytemode != xmm_mq_mode
16640 && bytemode != xmm_mdq_mode
16641 && bytemode != xmmq_mode
16642 && bytemode != evex_half_bcst_xmmq_mode
16643 && bytemode != ymm_mode
16644 && bytemode != d_scalar_mode
16645 && bytemode != d_scalar_swap_mode
16646 && bytemode != q_scalar_mode
16647 && bytemode != q_scalar_swap_mode
16648 && bytemode != vex_scalar_w_dq_mode)
16650 switch (vex.length)
16665 else if (bytemode == xmmq_mode
16666 || bytemode == evex_half_bcst_xmmq_mode)
16668 switch (vex.length)
16681 else if (bytemode == ymm_mode)
16685 oappend (names[reg]);
16689 OP_MS (int bytemode, int sizeflag)
16691 if (modrm.mod == 3)
16692 OP_EM (bytemode, sizeflag);
16698 OP_XS (int bytemode, int sizeflag)
16700 if (modrm.mod == 3)
16701 OP_EX (bytemode, sizeflag);
16707 OP_M (int bytemode, int sizeflag)
16709 if (modrm.mod == 3)
16710 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16713 OP_E (bytemode, sizeflag);
16717 OP_0f07 (int bytemode, int sizeflag)
16719 if (modrm.mod != 3 || modrm.rm != 0)
16722 OP_E (bytemode, sizeflag);
16725 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16726 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16729 NOP_Fixup1 (int bytemode, int sizeflag)
16731 if ((prefixes & PREFIX_DATA) != 0
16734 && address_mode == mode_64bit))
16735 OP_REG (bytemode, sizeflag);
16737 strcpy (obuf, "nop");
16741 NOP_Fixup2 (int bytemode, int sizeflag)
16743 if ((prefixes & PREFIX_DATA) != 0
16746 && address_mode == mode_64bit))
16747 OP_IMREG (bytemode, sizeflag);
16750 static const char *const Suffix3DNow[] = {
16751 /* 00 */ NULL, NULL, NULL, NULL,
16752 /* 04 */ NULL, NULL, NULL, NULL,
16753 /* 08 */ NULL, NULL, NULL, NULL,
16754 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
16755 /* 10 */ NULL, NULL, NULL, NULL,
16756 /* 14 */ NULL, NULL, NULL, NULL,
16757 /* 18 */ NULL, NULL, NULL, NULL,
16758 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
16759 /* 20 */ NULL, NULL, NULL, NULL,
16760 /* 24 */ NULL, NULL, NULL, NULL,
16761 /* 28 */ NULL, NULL, NULL, NULL,
16762 /* 2C */ NULL, NULL, NULL, NULL,
16763 /* 30 */ NULL, NULL, NULL, NULL,
16764 /* 34 */ NULL, NULL, NULL, NULL,
16765 /* 38 */ NULL, NULL, NULL, NULL,
16766 /* 3C */ NULL, NULL, NULL, NULL,
16767 /* 40 */ NULL, NULL, NULL, NULL,
16768 /* 44 */ NULL, NULL, NULL, NULL,
16769 /* 48 */ NULL, NULL, NULL, NULL,
16770 /* 4C */ NULL, NULL, NULL, NULL,
16771 /* 50 */ NULL, NULL, NULL, NULL,
16772 /* 54 */ NULL, NULL, NULL, NULL,
16773 /* 58 */ NULL, NULL, NULL, NULL,
16774 /* 5C */ NULL, NULL, NULL, NULL,
16775 /* 60 */ NULL, NULL, NULL, NULL,
16776 /* 64 */ NULL, NULL, NULL, NULL,
16777 /* 68 */ NULL, NULL, NULL, NULL,
16778 /* 6C */ NULL, NULL, NULL, NULL,
16779 /* 70 */ NULL, NULL, NULL, NULL,
16780 /* 74 */ NULL, NULL, NULL, NULL,
16781 /* 78 */ NULL, NULL, NULL, NULL,
16782 /* 7C */ NULL, NULL, NULL, NULL,
16783 /* 80 */ NULL, NULL, NULL, NULL,
16784 /* 84 */ NULL, NULL, NULL, NULL,
16785 /* 88 */ NULL, NULL, "pfnacc", NULL,
16786 /* 8C */ NULL, NULL, "pfpnacc", NULL,
16787 /* 90 */ "pfcmpge", NULL, NULL, NULL,
16788 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
16789 /* 98 */ NULL, NULL, "pfsub", NULL,
16790 /* 9C */ NULL, NULL, "pfadd", NULL,
16791 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
16792 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
16793 /* A8 */ NULL, NULL, "pfsubr", NULL,
16794 /* AC */ NULL, NULL, "pfacc", NULL,
16795 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
16796 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
16797 /* B8 */ NULL, NULL, NULL, "pswapd",
16798 /* BC */ NULL, NULL, NULL, "pavgusb",
16799 /* C0 */ NULL, NULL, NULL, NULL,
16800 /* C4 */ NULL, NULL, NULL, NULL,
16801 /* C8 */ NULL, NULL, NULL, NULL,
16802 /* CC */ NULL, NULL, NULL, NULL,
16803 /* D0 */ NULL, NULL, NULL, NULL,
16804 /* D4 */ NULL, NULL, NULL, NULL,
16805 /* D8 */ NULL, NULL, NULL, NULL,
16806 /* DC */ NULL, NULL, NULL, NULL,
16807 /* E0 */ NULL, NULL, NULL, NULL,
16808 /* E4 */ NULL, NULL, NULL, NULL,
16809 /* E8 */ NULL, NULL, NULL, NULL,
16810 /* EC */ NULL, NULL, NULL, NULL,
16811 /* F0 */ NULL, NULL, NULL, NULL,
16812 /* F4 */ NULL, NULL, NULL, NULL,
16813 /* F8 */ NULL, NULL, NULL, NULL,
16814 /* FC */ NULL, NULL, NULL, NULL,
16818 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16820 const char *mnemonic;
16822 FETCH_DATA (the_info, codep + 1);
16823 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16824 place where an 8-bit immediate would normally go. ie. the last
16825 byte of the instruction. */
16826 obufp = mnemonicendp;
16827 mnemonic = Suffix3DNow[*codep++ & 0xff];
16829 oappend (mnemonic);
16832 /* Since a variable sized modrm/sib chunk is between the start
16833 of the opcode (0x0f0f) and the opcode suffix, we need to do
16834 all the modrm processing first, and don't know until now that
16835 we have a bad opcode. This necessitates some cleaning up. */
16836 op_out[0][0] = '\0';
16837 op_out[1][0] = '\0';
16840 mnemonicendp = obufp;
16843 static struct op simd_cmp_op[] =
16845 { STRING_COMMA_LEN ("eq") },
16846 { STRING_COMMA_LEN ("lt") },
16847 { STRING_COMMA_LEN ("le") },
16848 { STRING_COMMA_LEN ("unord") },
16849 { STRING_COMMA_LEN ("neq") },
16850 { STRING_COMMA_LEN ("nlt") },
16851 { STRING_COMMA_LEN ("nle") },
16852 { STRING_COMMA_LEN ("ord") }
16856 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16858 unsigned int cmp_type;
16860 FETCH_DATA (the_info, codep + 1);
16861 cmp_type = *codep++ & 0xff;
16862 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16865 char *p = mnemonicendp - 2;
16869 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16870 mnemonicendp += simd_cmp_op[cmp_type].len;
16874 /* We have a reserved extension byte. Output it directly. */
16875 scratchbuf[0] = '$';
16876 print_operand_value (scratchbuf + 1, 1, cmp_type);
16877 oappend_maybe_intel (scratchbuf);
16878 scratchbuf[0] = '\0';
16883 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16884 int sizeflag ATTRIBUTE_UNUSED)
16886 /* mwaitx %eax,%ecx,%ebx */
16889 const char **names = (address_mode == mode_64bit
16890 ? names64 : names32);
16891 strcpy (op_out[0], names[0]);
16892 strcpy (op_out[1], names[1]);
16893 strcpy (op_out[2], names[3]);
16894 two_source_ops = 1;
16896 /* Skip mod/rm byte. */
16902 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16903 int sizeflag ATTRIBUTE_UNUSED)
16905 /* mwait %eax,%ecx */
16908 const char **names = (address_mode == mode_64bit
16909 ? names64 : names32);
16910 strcpy (op_out[0], names[0]);
16911 strcpy (op_out[1], names[1]);
16912 two_source_ops = 1;
16914 /* Skip mod/rm byte. */
16920 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16921 int sizeflag ATTRIBUTE_UNUSED)
16923 /* monitor %eax,%ecx,%edx" */
16926 const char **op1_names;
16927 const char **names = (address_mode == mode_64bit
16928 ? names64 : names32);
16930 if (!(prefixes & PREFIX_ADDR))
16931 op1_names = (address_mode == mode_16bit
16932 ? names16 : names);
16935 /* Remove "addr16/addr32". */
16936 all_prefixes[last_addr_prefix] = 0;
16937 op1_names = (address_mode != mode_32bit
16938 ? names32 : names16);
16939 used_prefixes |= PREFIX_ADDR;
16941 strcpy (op_out[0], op1_names[0]);
16942 strcpy (op_out[1], names[1]);
16943 strcpy (op_out[2], names[2]);
16944 two_source_ops = 1;
16946 /* Skip mod/rm byte. */
16954 /* Throw away prefixes and 1st. opcode byte. */
16955 codep = insn_codep + 1;
16960 REP_Fixup (int bytemode, int sizeflag)
16962 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16964 if (prefixes & PREFIX_REPZ)
16965 all_prefixes[last_repz_prefix] = REP_PREFIX;
16972 OP_IMREG (bytemode, sizeflag);
16975 OP_ESreg (bytemode, sizeflag);
16978 OP_DSreg (bytemode, sizeflag);
16986 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16990 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16992 if (prefixes & PREFIX_REPNZ)
16993 all_prefixes[last_repnz_prefix] = BND_PREFIX;
16996 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
17000 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
17001 int sizeflag ATTRIBUTE_UNUSED)
17003 if (active_seg_prefix == PREFIX_DS
17004 && (address_mode != mode_64bit || last_data_prefix < 0))
17006 /* NOTRACK prefix is only valid on indirect branch instructions.
17007 NB: DATA prefix is unsupported for Intel64. */
17008 active_seg_prefix = 0;
17009 all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
17013 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
17014 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
17018 HLE_Fixup1 (int bytemode, int sizeflag)
17021 && (prefixes & PREFIX_LOCK) != 0)
17023 if (prefixes & PREFIX_REPZ)
17024 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17025 if (prefixes & PREFIX_REPNZ)
17026 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17029 OP_E (bytemode, sizeflag);
17032 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
17033 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
17037 HLE_Fixup2 (int bytemode, int sizeflag)
17039 if (modrm.mod != 3)
17041 if (prefixes & PREFIX_REPZ)
17042 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17043 if (prefixes & PREFIX_REPNZ)
17044 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17047 OP_E (bytemode, sizeflag);
17050 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
17051 "xrelease" for memory operand. No check for LOCK prefix. */
17054 HLE_Fixup3 (int bytemode, int sizeflag)
17057 && last_repz_prefix > last_repnz_prefix
17058 && (prefixes & PREFIX_REPZ) != 0)
17059 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17061 OP_E (bytemode, sizeflag);
17065 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
17070 /* Change cmpxchg8b to cmpxchg16b. */
17071 char *p = mnemonicendp - 2;
17072 mnemonicendp = stpcpy (p, "16b");
17075 else if ((prefixes & PREFIX_LOCK) != 0)
17077 if (prefixes & PREFIX_REPZ)
17078 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17079 if (prefixes & PREFIX_REPNZ)
17080 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17083 OP_M (bytemode, sizeflag);
17087 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
17089 const char **names;
17093 switch (vex.length)
17107 oappend (names[reg]);
17111 CRC32_Fixup (int bytemode, int sizeflag)
17113 /* Add proper suffix to "crc32". */
17114 char *p = mnemonicendp;
17133 if (sizeflag & DFLAG)
17137 used_prefixes |= (prefixes & PREFIX_DATA);
17141 oappend (INTERNAL_DISASSEMBLER_ERROR);
17148 if (modrm.mod == 3)
17152 /* Skip mod/rm byte. */
17157 add = (rex & REX_B) ? 8 : 0;
17158 if (bytemode == b_mode)
17162 oappend (names8rex[modrm.rm + add]);
17164 oappend (names8[modrm.rm + add]);
17170 oappend (names64[modrm.rm + add]);
17171 else if ((prefixes & PREFIX_DATA))
17172 oappend (names16[modrm.rm + add]);
17174 oappend (names32[modrm.rm + add]);
17178 OP_E (bytemode, sizeflag);
17182 FXSAVE_Fixup (int bytemode, int sizeflag)
17184 /* Add proper suffix to "fxsave" and "fxrstor". */
17188 char *p = mnemonicendp;
17194 OP_M (bytemode, sizeflag);
17198 PCMPESTR_Fixup (int bytemode, int sizeflag)
17200 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
17203 char *p = mnemonicendp;
17208 else if (sizeflag & SUFFIX_ALWAYS)
17215 OP_EX (bytemode, sizeflag);
17218 /* Display the destination register operand for instructions with
17222 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17225 const char **names;
17233 reg = vex.register_specifier;
17234 if (address_mode != mode_64bit)
17236 else if (vex.evex && !vex.v)
17239 if (bytemode == vex_scalar_mode)
17241 oappend (names_xmm[reg]);
17245 switch (vex.length)
17252 case vex_vsib_q_w_dq_mode:
17253 case vex_vsib_q_w_d_mode:
17269 names = names_mask;
17283 case vex_vsib_q_w_dq_mode:
17284 case vex_vsib_q_w_d_mode:
17285 names = vex.w ? names_ymm : names_xmm;
17294 names = names_mask;
17297 /* See PR binutils/20893 for a reproducer. */
17309 oappend (names[reg]);
17312 /* Get the VEX immediate byte without moving codep. */
17314 static unsigned char
17315 get_vex_imm8 (int sizeflag, int opnum)
17317 int bytes_before_imm = 0;
17319 if (modrm.mod != 3)
17321 /* There are SIB/displacement bytes. */
17322 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17324 /* 32/64 bit address mode */
17325 int base = modrm.rm;
17327 /* Check SIB byte. */
17330 FETCH_DATA (the_info, codep + 1);
17332 /* When decoding the third source, don't increase
17333 bytes_before_imm as this has already been incremented
17334 by one in OP_E_memory while decoding the second
17337 bytes_before_imm++;
17340 /* Don't increase bytes_before_imm when decoding the third source,
17341 it has already been incremented by OP_E_memory while decoding
17342 the second source operand. */
17348 /* When modrm.rm == 5 or modrm.rm == 4 and base in
17349 SIB == 5, there is a 4 byte displacement. */
17351 /* No displacement. */
17353 /* Fall through. */
17355 /* 4 byte displacement. */
17356 bytes_before_imm += 4;
17359 /* 1 byte displacement. */
17360 bytes_before_imm++;
17367 /* 16 bit address mode */
17368 /* Don't increase bytes_before_imm when decoding the third source,
17369 it has already been incremented by OP_E_memory while decoding
17370 the second source operand. */
17376 /* When modrm.rm == 6, there is a 2 byte displacement. */
17378 /* No displacement. */
17380 /* Fall through. */
17382 /* 2 byte displacement. */
17383 bytes_before_imm += 2;
17386 /* 1 byte displacement: when decoding the third source,
17387 don't increase bytes_before_imm as this has already
17388 been incremented by one in OP_E_memory while decoding
17389 the second source operand. */
17391 bytes_before_imm++;
17399 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17400 return codep [bytes_before_imm];
17404 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17406 const char **names;
17408 if (reg == -1 && modrm.mod != 3)
17410 OP_E_memory (bytemode, sizeflag);
17422 if (address_mode != mode_64bit)
17426 switch (vex.length)
17437 oappend (names[reg]);
17441 OP_EX_VexImmW (int bytemode, int sizeflag)
17444 static unsigned char vex_imm8;
17446 if (vex_w_done == 0)
17450 /* Skip mod/rm byte. */
17454 vex_imm8 = get_vex_imm8 (sizeflag, 0);
17457 reg = vex_imm8 >> 4;
17459 OP_EX_VexReg (bytemode, sizeflag, reg);
17461 else if (vex_w_done == 1)
17466 reg = vex_imm8 >> 4;
17468 OP_EX_VexReg (bytemode, sizeflag, reg);
17472 /* Output the imm8 directly. */
17473 scratchbuf[0] = '$';
17474 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17475 oappend_maybe_intel (scratchbuf);
17476 scratchbuf[0] = '\0';
17482 OP_Vex_2src (int bytemode, int sizeflag)
17484 if (modrm.mod == 3)
17486 int reg = modrm.rm;
17490 oappend (names_xmm[reg]);
17495 && (bytemode == v_mode || bytemode == v_swap_mode))
17497 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17498 used_prefixes |= (prefixes & PREFIX_DATA);
17500 OP_E (bytemode, sizeflag);
17505 OP_Vex_2src_1 (int bytemode, int sizeflag)
17507 if (modrm.mod == 3)
17509 /* Skip mod/rm byte. */
17516 unsigned int reg = vex.register_specifier;
17518 if (address_mode != mode_64bit)
17520 oappend (names_xmm[reg]);
17523 OP_Vex_2src (bytemode, sizeflag);
17527 OP_Vex_2src_2 (int bytemode, int sizeflag)
17530 OP_Vex_2src (bytemode, sizeflag);
17533 unsigned int reg = vex.register_specifier;
17535 if (address_mode != mode_64bit)
17537 oappend (names_xmm[reg]);
17542 OP_EX_VexW (int bytemode, int sizeflag)
17548 /* Skip mod/rm byte. */
17553 reg = get_vex_imm8 (sizeflag, 0) >> 4;
17558 reg = get_vex_imm8 (sizeflag, 1) >> 4;
17561 OP_EX_VexReg (bytemode, sizeflag, reg);
17569 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17572 const char **names;
17574 FETCH_DATA (the_info, codep + 1);
17577 if (bytemode != x_mode)
17581 if (address_mode != mode_64bit)
17584 switch (vex.length)
17595 oappend (names[reg]);
17599 OP_XMM_VexW (int bytemode, int sizeflag)
17601 /* Turn off the REX.W bit since it is used for swapping operands
17604 OP_XMM (bytemode, sizeflag);
17608 OP_EX_Vex (int bytemode, int sizeflag)
17610 if (modrm.mod != 3)
17612 if (vex.register_specifier != 0)
17616 OP_EX (bytemode, sizeflag);
17620 OP_XMM_Vex (int bytemode, int sizeflag)
17622 if (modrm.mod != 3)
17624 if (vex.register_specifier != 0)
17628 OP_XMM (bytemode, sizeflag);
17632 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17634 switch (vex.length)
17637 mnemonicendp = stpcpy (obuf, "vzeroupper");
17640 mnemonicendp = stpcpy (obuf, "vzeroall");
17647 static struct op vex_cmp_op[] =
17649 { STRING_COMMA_LEN ("eq") },
17650 { STRING_COMMA_LEN ("lt") },
17651 { STRING_COMMA_LEN ("le") },
17652 { STRING_COMMA_LEN ("unord") },
17653 { STRING_COMMA_LEN ("neq") },
17654 { STRING_COMMA_LEN ("nlt") },
17655 { STRING_COMMA_LEN ("nle") },
17656 { STRING_COMMA_LEN ("ord") },
17657 { STRING_COMMA_LEN ("eq_uq") },
17658 { STRING_COMMA_LEN ("nge") },
17659 { STRING_COMMA_LEN ("ngt") },
17660 { STRING_COMMA_LEN ("false") },
17661 { STRING_COMMA_LEN ("neq_oq") },
17662 { STRING_COMMA_LEN ("ge") },
17663 { STRING_COMMA_LEN ("gt") },
17664 { STRING_COMMA_LEN ("true") },
17665 { STRING_COMMA_LEN ("eq_os") },
17666 { STRING_COMMA_LEN ("lt_oq") },
17667 { STRING_COMMA_LEN ("le_oq") },
17668 { STRING_COMMA_LEN ("unord_s") },
17669 { STRING_COMMA_LEN ("neq_us") },
17670 { STRING_COMMA_LEN ("nlt_uq") },
17671 { STRING_COMMA_LEN ("nle_uq") },
17672 { STRING_COMMA_LEN ("ord_s") },
17673 { STRING_COMMA_LEN ("eq_us") },
17674 { STRING_COMMA_LEN ("nge_uq") },
17675 { STRING_COMMA_LEN ("ngt_uq") },
17676 { STRING_COMMA_LEN ("false_os") },
17677 { STRING_COMMA_LEN ("neq_os") },
17678 { STRING_COMMA_LEN ("ge_oq") },
17679 { STRING_COMMA_LEN ("gt_oq") },
17680 { STRING_COMMA_LEN ("true_us") },
17684 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17686 unsigned int cmp_type;
17688 FETCH_DATA (the_info, codep + 1);
17689 cmp_type = *codep++ & 0xff;
17690 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17693 char *p = mnemonicendp - 2;
17697 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17698 mnemonicendp += vex_cmp_op[cmp_type].len;
17702 /* We have a reserved extension byte. Output it directly. */
17703 scratchbuf[0] = '$';
17704 print_operand_value (scratchbuf + 1, 1, cmp_type);
17705 oappend_maybe_intel (scratchbuf);
17706 scratchbuf[0] = '\0';
17711 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17712 int sizeflag ATTRIBUTE_UNUSED)
17714 unsigned int cmp_type;
17719 FETCH_DATA (the_info, codep + 1);
17720 cmp_type = *codep++ & 0xff;
17721 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17722 If it's the case, print suffix, otherwise - print the immediate. */
17723 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17728 char *p = mnemonicendp - 2;
17730 /* vpcmp* can have both one- and two-lettered suffix. */
17744 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17745 mnemonicendp += simd_cmp_op[cmp_type].len;
17749 /* We have a reserved extension byte. Output it directly. */
17750 scratchbuf[0] = '$';
17751 print_operand_value (scratchbuf + 1, 1, cmp_type);
17752 oappend_maybe_intel (scratchbuf);
17753 scratchbuf[0] = '\0';
17757 static const struct op xop_cmp_op[] =
17759 { STRING_COMMA_LEN ("lt") },
17760 { STRING_COMMA_LEN ("le") },
17761 { STRING_COMMA_LEN ("gt") },
17762 { STRING_COMMA_LEN ("ge") },
17763 { STRING_COMMA_LEN ("eq") },
17764 { STRING_COMMA_LEN ("neq") },
17765 { STRING_COMMA_LEN ("false") },
17766 { STRING_COMMA_LEN ("true") }
17770 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
17771 int sizeflag ATTRIBUTE_UNUSED)
17773 unsigned int cmp_type;
17775 FETCH_DATA (the_info, codep + 1);
17776 cmp_type = *codep++ & 0xff;
17777 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
17780 char *p = mnemonicendp - 2;
17782 /* vpcom* can have both one- and two-lettered suffix. */
17796 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
17797 mnemonicendp += xop_cmp_op[cmp_type].len;
17801 /* We have a reserved extension byte. Output it directly. */
17802 scratchbuf[0] = '$';
17803 print_operand_value (scratchbuf + 1, 1, cmp_type);
17804 oappend_maybe_intel (scratchbuf);
17805 scratchbuf[0] = '\0';
17809 static const struct op pclmul_op[] =
17811 { STRING_COMMA_LEN ("lql") },
17812 { STRING_COMMA_LEN ("hql") },
17813 { STRING_COMMA_LEN ("lqh") },
17814 { STRING_COMMA_LEN ("hqh") }
17818 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17819 int sizeflag ATTRIBUTE_UNUSED)
17821 unsigned int pclmul_type;
17823 FETCH_DATA (the_info, codep + 1);
17824 pclmul_type = *codep++ & 0xff;
17825 switch (pclmul_type)
17836 if (pclmul_type < ARRAY_SIZE (pclmul_op))
17839 char *p = mnemonicendp - 3;
17844 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17845 mnemonicendp += pclmul_op[pclmul_type].len;
17849 /* We have a reserved extension byte. Output it directly. */
17850 scratchbuf[0] = '$';
17851 print_operand_value (scratchbuf + 1, 1, pclmul_type);
17852 oappend_maybe_intel (scratchbuf);
17853 scratchbuf[0] = '\0';
17858 MOVBE_Fixup (int bytemode, int sizeflag)
17860 /* Add proper suffix to "movbe". */
17861 char *p = mnemonicendp;
17870 if (sizeflag & SUFFIX_ALWAYS)
17876 if (sizeflag & DFLAG)
17880 used_prefixes |= (prefixes & PREFIX_DATA);
17885 oappend (INTERNAL_DISASSEMBLER_ERROR);
17892 OP_M (bytemode, sizeflag);
17896 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17899 const char **names;
17901 /* Skip mod/rm byte. */
17915 oappend (names[reg]);
17919 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17921 const char **names;
17922 unsigned int reg = vex.register_specifier;
17929 if (address_mode != mode_64bit)
17931 oappend (names[reg]);
17935 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17938 || (bytemode != mask_mode && bytemode != mask_bd_mode))
17942 if ((rex & REX_R) != 0 || !vex.r)
17948 oappend (names_mask [modrm.reg]);
17952 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17955 || (bytemode != evex_rounding_mode
17956 && bytemode != evex_rounding_64_mode
17957 && bytemode != evex_sae_mode))
17959 if (modrm.mod == 3 && vex.b)
17962 case evex_rounding_64_mode:
17963 if (address_mode != mode_64bit)
17968 /* Fall through. */
17969 case evex_rounding_mode:
17970 oappend (names_rounding[vex.ll]);
17972 case evex_sae_mode: