1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2017 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma, disassemble_info *);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma get64 (void);
58 static bfd_signed_vma get32 (void);
59 static bfd_signed_vma get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void OP_Mwaitx (int, int);
106 static void NOP_Fixup1 (int, int);
107 static void NOP_Fixup2 (int, int);
108 static void OP_3DNowSuffix (int, int);
109 static void CMP_Fixup (int, int);
110 static void BadOp (void);
111 static void REP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void NOTRACK_Fixup (int, int);
114 static void HLE_Fixup1 (int, int);
115 static void HLE_Fixup2 (int, int);
116 static void HLE_Fixup3 (int, int);
117 static void CMPXCHG8B_Fixup (int, int);
118 static void XMM_Fixup (int, int);
119 static void CRC32_Fixup (int, int);
120 static void FXSAVE_Fixup (int, int);
121 static void PCMPESTR_Fixup (int, int);
122 static void OP_LWPCB_E (int, int);
123 static void OP_LWP_E (int, int);
124 static void OP_Vex_2src_1 (int, int);
125 static void OP_Vex_2src_2 (int, int);
127 static void MOVBE_Fixup (int, int);
129 static void OP_Mask (int, int);
132 /* Points to first byte not fetched. */
133 bfd_byte *max_fetched;
134 bfd_byte the_buffer[MAX_MNEM_SIZE];
137 OPCODES_SIGJMP_BUF bailout;
147 enum address_mode address_mode;
149 /* Flags for the prefixes for the current instruction. See below. */
152 /* REX prefix the current instruction. See below. */
154 /* Bits of REX we've already used. */
156 /* REX bits in original REX prefix ignored. */
157 static int rex_ignored;
158 /* Mark parts used in the REX prefix. When we are testing for
159 empty prefix (for 8bit register REX extension), just mask it
160 out. Otherwise test for REX bit is excuse for existence of REX
161 only in case value is nonzero. */
162 #define USED_REX(value) \
167 rex_used |= (value) | REX_OPCODE; \
170 rex_used |= REX_OPCODE; \
173 /* Flags for prefixes which we somehow handled when printing the
174 current instruction. */
175 static int used_prefixes;
177 /* Flags stored in PREFIXES. */
178 #define PREFIX_REPZ 1
179 #define PREFIX_REPNZ 2
180 #define PREFIX_LOCK 4
182 #define PREFIX_SS 0x10
183 #define PREFIX_DS 0x20
184 #define PREFIX_ES 0x40
185 #define PREFIX_FS 0x80
186 #define PREFIX_GS 0x100
187 #define PREFIX_DATA 0x200
188 #define PREFIX_ADDR 0x400
189 #define PREFIX_FWAIT 0x800
191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
192 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
194 #define FETCH_DATA(info, addr) \
195 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
196 ? 1 : fetch_data ((info), (addr)))
199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
202 struct dis_private *priv = (struct dis_private *) info->private_data;
203 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
205 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
206 status = (*info->read_memory_func) (start,
208 addr - priv->max_fetched,
214 /* If we did manage to read at least one byte, then
215 print_insn_i386 will do something sensible. Otherwise, print
216 an error. We do that here because this is where we know
218 if (priv->max_fetched == priv->the_buffer)
219 (*info->memory_error_func) (status, start, info);
220 OPCODES_SIGLONGJMP (priv->bailout, 1);
223 priv->max_fetched = addr;
227 /* Possible values for prefix requirement. */
228 #define PREFIX_IGNORED_SHIFT 16
229 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
233 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
235 /* Opcode prefixes. */
236 #define PREFIX_OPCODE (PREFIX_REPZ \
240 /* Prefixes ignored. */
241 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
242 | PREFIX_IGNORED_REPNZ \
243 | PREFIX_IGNORED_DATA)
245 #define XX { NULL, 0 }
246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
248 #define Eb { OP_E, b_mode }
249 #define Ebnd { OP_E, bnd_mode }
250 #define EbS { OP_E, b_swap_mode }
251 #define Ev { OP_E, v_mode }
252 #define Ev_bnd { OP_E, v_bnd_mode }
253 #define EvS { OP_E, v_swap_mode }
254 #define Ed { OP_E, d_mode }
255 #define Edq { OP_E, dq_mode }
256 #define Edqw { OP_E, dqw_mode }
257 #define Edqb { OP_E, dqb_mode }
258 #define Edb { OP_E, db_mode }
259 #define Edw { OP_E, dw_mode }
260 #define Edqd { OP_E, dqd_mode }
261 #define Eq { OP_E, q_mode }
262 #define indirEv { OP_indirE, indir_v_mode }
263 #define indirEp { OP_indirE, f_mode }
264 #define stackEv { OP_E, stack_v_mode }
265 #define Em { OP_E, m_mode }
266 #define Ew { OP_E, w_mode }
267 #define M { OP_M, 0 } /* lea, lgdt, etc. */
268 #define Ma { OP_M, a_mode }
269 #define Mb { OP_M, b_mode }
270 #define Md { OP_M, d_mode }
271 #define Mo { OP_M, o_mode }
272 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
273 #define Mq { OP_M, q_mode }
274 #define Mx { OP_M, x_mode }
275 #define Mxmm { OP_M, xmm_mode }
276 #define Gb { OP_G, b_mode }
277 #define Gbnd { OP_G, bnd_mode }
278 #define Gv { OP_G, v_mode }
279 #define Gd { OP_G, d_mode }
280 #define Gdq { OP_G, dq_mode }
281 #define Gm { OP_G, m_mode }
282 #define Gw { OP_G, w_mode }
283 #define Rd { OP_R, d_mode }
284 #define Rdq { OP_R, dq_mode }
285 #define Rm { OP_R, m_mode }
286 #define Ib { OP_I, b_mode }
287 #define sIb { OP_sI, b_mode } /* sign extened byte */
288 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
289 #define Iv { OP_I, v_mode }
290 #define sIv { OP_sI, v_mode }
291 #define Iq { OP_I, q_mode }
292 #define Iv64 { OP_I64, v_mode }
293 #define Iw { OP_I, w_mode }
294 #define I1 { OP_I, const_1_mode }
295 #define Jb { OP_J, b_mode }
296 #define Jv { OP_J, v_mode }
297 #define Cm { OP_C, m_mode }
298 #define Dm { OP_D, m_mode }
299 #define Td { OP_T, d_mode }
300 #define Skip_MODRM { OP_Skip_MODRM, 0 }
302 #define RMeAX { OP_REG, eAX_reg }
303 #define RMeBX { OP_REG, eBX_reg }
304 #define RMeCX { OP_REG, eCX_reg }
305 #define RMeDX { OP_REG, eDX_reg }
306 #define RMeSP { OP_REG, eSP_reg }
307 #define RMeBP { OP_REG, eBP_reg }
308 #define RMeSI { OP_REG, eSI_reg }
309 #define RMeDI { OP_REG, eDI_reg }
310 #define RMrAX { OP_REG, rAX_reg }
311 #define RMrBX { OP_REG, rBX_reg }
312 #define RMrCX { OP_REG, rCX_reg }
313 #define RMrDX { OP_REG, rDX_reg }
314 #define RMrSP { OP_REG, rSP_reg }
315 #define RMrBP { OP_REG, rBP_reg }
316 #define RMrSI { OP_REG, rSI_reg }
317 #define RMrDI { OP_REG, rDI_reg }
318 #define RMAL { OP_REG, al_reg }
319 #define RMCL { OP_REG, cl_reg }
320 #define RMDL { OP_REG, dl_reg }
321 #define RMBL { OP_REG, bl_reg }
322 #define RMAH { OP_REG, ah_reg }
323 #define RMCH { OP_REG, ch_reg }
324 #define RMDH { OP_REG, dh_reg }
325 #define RMBH { OP_REG, bh_reg }
326 #define RMAX { OP_REG, ax_reg }
327 #define RMDX { OP_REG, dx_reg }
329 #define eAX { OP_IMREG, eAX_reg }
330 #define eBX { OP_IMREG, eBX_reg }
331 #define eCX { OP_IMREG, eCX_reg }
332 #define eDX { OP_IMREG, eDX_reg }
333 #define eSP { OP_IMREG, eSP_reg }
334 #define eBP { OP_IMREG, eBP_reg }
335 #define eSI { OP_IMREG, eSI_reg }
336 #define eDI { OP_IMREG, eDI_reg }
337 #define AL { OP_IMREG, al_reg }
338 #define CL { OP_IMREG, cl_reg }
339 #define DL { OP_IMREG, dl_reg }
340 #define BL { OP_IMREG, bl_reg }
341 #define AH { OP_IMREG, ah_reg }
342 #define CH { OP_IMREG, ch_reg }
343 #define DH { OP_IMREG, dh_reg }
344 #define BH { OP_IMREG, bh_reg }
345 #define AX { OP_IMREG, ax_reg }
346 #define DX { OP_IMREG, dx_reg }
347 #define zAX { OP_IMREG, z_mode_ax_reg }
348 #define indirDX { OP_IMREG, indir_dx_reg }
350 #define Sw { OP_SEG, w_mode }
351 #define Sv { OP_SEG, v_mode }
352 #define Ap { OP_DIR, 0 }
353 #define Ob { OP_OFF64, b_mode }
354 #define Ov { OP_OFF64, v_mode }
355 #define Xb { OP_DSreg, eSI_reg }
356 #define Xv { OP_DSreg, eSI_reg }
357 #define Xz { OP_DSreg, eSI_reg }
358 #define Yb { OP_ESreg, eDI_reg }
359 #define Yv { OP_ESreg, eDI_reg }
360 #define DSBX { OP_DSreg, eBX_reg }
362 #define es { OP_REG, es_reg }
363 #define ss { OP_REG, ss_reg }
364 #define cs { OP_REG, cs_reg }
365 #define ds { OP_REG, ds_reg }
366 #define fs { OP_REG, fs_reg }
367 #define gs { OP_REG, gs_reg }
369 #define MX { OP_MMX, 0 }
370 #define XM { OP_XMM, 0 }
371 #define XMScalar { OP_XMM, scalar_mode }
372 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
373 #define XMM { OP_XMM, xmm_mode }
374 #define XMxmmq { OP_XMM, xmmq_mode }
375 #define EM { OP_EM, v_mode }
376 #define EMS { OP_EM, v_swap_mode }
377 #define EMd { OP_EM, d_mode }
378 #define EMx { OP_EM, x_mode }
379 #define EXw { OP_EX, w_mode }
380 #define EXd { OP_EX, d_mode }
381 #define EXdScalar { OP_EX, d_scalar_mode }
382 #define EXdS { OP_EX, d_swap_mode }
383 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
384 #define EXq { OP_EX, q_mode }
385 #define EXqScalar { OP_EX, q_scalar_mode }
386 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
387 #define EXqS { OP_EX, q_swap_mode }
388 #define EXx { OP_EX, x_mode }
389 #define EXxS { OP_EX, x_swap_mode }
390 #define EXxmm { OP_EX, xmm_mode }
391 #define EXymm { OP_EX, ymm_mode }
392 #define EXxmmq { OP_EX, xmmq_mode }
393 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
394 #define EXxmm_mb { OP_EX, xmm_mb_mode }
395 #define EXxmm_mw { OP_EX, xmm_mw_mode }
396 #define EXxmm_md { OP_EX, xmm_md_mode }
397 #define EXxmm_mq { OP_EX, xmm_mq_mode }
398 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
399 #define EXxmmdw { OP_EX, xmmdw_mode }
400 #define EXxmmqd { OP_EX, xmmqd_mode }
401 #define EXymmq { OP_EX, ymmq_mode }
402 #define EXVexWdq { OP_EX, vex_w_dq_mode }
403 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
404 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
405 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
406 #define MS { OP_MS, v_mode }
407 #define XS { OP_XS, v_mode }
408 #define EMCq { OP_EMC, q_mode }
409 #define MXC { OP_MXC, 0 }
410 #define OPSUF { OP_3DNowSuffix, 0 }
411 #define CMP { CMP_Fixup, 0 }
412 #define XMM0 { XMM_Fixup, 0 }
413 #define FXSAVE { FXSAVE_Fixup, 0 }
414 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
415 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
417 #define Vex { OP_VEX, vex_mode }
418 #define VexScalar { OP_VEX, vex_scalar_mode }
419 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
420 #define Vex128 { OP_VEX, vex128_mode }
421 #define Vex256 { OP_VEX, vex256_mode }
422 #define VexGdq { OP_VEX, dq_mode }
423 #define VexI4 { VEXI4_Fixup, 0}
424 #define EXdVex { OP_EX_Vex, d_mode }
425 #define EXdVexS { OP_EX_Vex, d_swap_mode }
426 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
427 #define EXqVex { OP_EX_Vex, q_mode }
428 #define EXqVexS { OP_EX_Vex, q_swap_mode }
429 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
430 #define EXVexW { OP_EX_VexW, x_mode }
431 #define EXdVexW { OP_EX_VexW, d_mode }
432 #define EXqVexW { OP_EX_VexW, q_mode }
433 #define EXVexImmW { OP_EX_VexImmW, x_mode }
434 #define XMVex { OP_XMM_Vex, 0 }
435 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
436 #define XMVexW { OP_XMM_VexW, 0 }
437 #define XMVexI4 { OP_REG_VexI4, x_mode }
438 #define PCLMUL { PCLMUL_Fixup, 0 }
439 #define VZERO { VZERO_Fixup, 0 }
440 #define VCMP { VCMP_Fixup, 0 }
441 #define VPCMP { VPCMP_Fixup, 0 }
443 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
444 #define EXxEVexS { OP_Rounding, evex_sae_mode }
446 #define XMask { OP_Mask, mask_mode }
447 #define MaskG { OP_G, mask_mode }
448 #define MaskE { OP_E, mask_mode }
449 #define MaskBDE { OP_E, mask_bd_mode }
450 #define MaskR { OP_R, mask_mode }
451 #define MaskVex { OP_VEX, mask_mode }
453 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
454 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
455 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
456 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
458 /* Used handle "rep" prefix for string instructions. */
459 #define Xbr { REP_Fixup, eSI_reg }
460 #define Xvr { REP_Fixup, eSI_reg }
461 #define Ybr { REP_Fixup, eDI_reg }
462 #define Yvr { REP_Fixup, eDI_reg }
463 #define Yzr { REP_Fixup, eDI_reg }
464 #define indirDXr { REP_Fixup, indir_dx_reg }
465 #define ALr { REP_Fixup, al_reg }
466 #define eAXr { REP_Fixup, eAX_reg }
468 /* Used handle HLE prefix for lockable instructions. */
469 #define Ebh1 { HLE_Fixup1, b_mode }
470 #define Evh1 { HLE_Fixup1, v_mode }
471 #define Ebh2 { HLE_Fixup2, b_mode }
472 #define Evh2 { HLE_Fixup2, v_mode }
473 #define Ebh3 { HLE_Fixup3, b_mode }
474 #define Evh3 { HLE_Fixup3, v_mode }
476 #define BND { BND_Fixup, 0 }
477 #define NOTRACK { NOTRACK_Fixup, 0 }
479 #define cond_jump_flag { NULL, cond_jump_mode }
480 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
482 /* bits in sizeflag */
483 #define SUFFIX_ALWAYS 4
491 /* byte operand with operand swapped */
493 /* byte operand, sign extend like 'T' suffix */
495 /* operand size depends on prefixes */
497 /* operand size depends on prefixes with operand swapped */
501 /* double word operand */
503 /* double word operand with operand swapped */
505 /* quad word operand */
507 /* quad word operand with operand swapped */
509 /* ten-byte operand */
511 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
512 broadcast enabled. */
514 /* Similar to x_mode, but with different EVEX mem shifts. */
516 /* Similar to x_mode, but with disabled broadcast. */
518 /* Similar to x_mode, but with operands swapped and disabled broadcast
521 /* 16-byte XMM operand */
523 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
524 memory operand (depending on vector length). Broadcast isn't
527 /* Same as xmmq_mode, but broadcast is allowed. */
528 evex_half_bcst_xmmq_mode,
529 /* XMM register or byte memory operand */
531 /* XMM register or word memory operand */
533 /* XMM register or double word memory operand */
535 /* XMM register or quad word memory operand */
537 /* XMM register or double/quad word memory operand, depending on
540 /* 16-byte XMM, word, double word or quad word operand. */
542 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
544 /* 32-byte YMM operand */
546 /* quad word, ymmword or zmmword memory operand. */
548 /* 32-byte YMM or 16-byte word operand */
550 /* d_mode in 32bit, q_mode in 64bit mode. */
552 /* pair of v_mode operands */
557 /* operand size depends on REX prefixes. */
559 /* registers like dq_mode, memory like w_mode. */
562 /* 4- or 6-byte pointer operand */
565 /* v_mode for indirect branch opcodes. */
567 /* v_mode for stack-related opcodes. */
569 /* non-quad operand size depends on prefixes */
571 /* 16-byte operand */
573 /* registers like dq_mode, memory like b_mode. */
575 /* registers like d_mode, memory like b_mode. */
577 /* registers like d_mode, memory like w_mode. */
579 /* registers like dq_mode, memory like d_mode. */
581 /* normal vex mode */
583 /* 128bit vex mode */
585 /* 256bit vex mode */
587 /* operand size depends on the VEX.W bit. */
590 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
591 vex_vsib_d_w_dq_mode,
592 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
594 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
595 vex_vsib_q_w_dq_mode,
596 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
599 /* scalar, ignore vector length. */
601 /* like d_mode, ignore vector length. */
603 /* like d_swap_mode, ignore vector length. */
605 /* like q_mode, ignore vector length. */
607 /* like q_swap_mode, ignore vector length. */
609 /* like vex_mode, ignore vector length. */
611 /* like vex_w_dq_mode, ignore vector length. */
612 vex_scalar_w_dq_mode,
614 /* Static rounding. */
616 /* Supress all exceptions. */
619 /* Mask register operand. */
621 /* Mask register operand. */
688 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
690 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
691 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
692 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
693 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
694 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
695 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
696 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
697 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
698 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
699 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
700 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
701 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
702 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
703 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
704 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
826 MOD_VEX_0F12_PREFIX_0,
828 MOD_VEX_0F16_PREFIX_0,
831 MOD_VEX_W_0_0F41_P_0_LEN_1,
832 MOD_VEX_W_1_0F41_P_0_LEN_1,
833 MOD_VEX_W_0_0F41_P_2_LEN_1,
834 MOD_VEX_W_1_0F41_P_2_LEN_1,
835 MOD_VEX_W_0_0F42_P_0_LEN_1,
836 MOD_VEX_W_1_0F42_P_0_LEN_1,
837 MOD_VEX_W_0_0F42_P_2_LEN_1,
838 MOD_VEX_W_1_0F42_P_2_LEN_1,
839 MOD_VEX_W_0_0F44_P_0_LEN_1,
840 MOD_VEX_W_1_0F44_P_0_LEN_1,
841 MOD_VEX_W_0_0F44_P_2_LEN_1,
842 MOD_VEX_W_1_0F44_P_2_LEN_1,
843 MOD_VEX_W_0_0F45_P_0_LEN_1,
844 MOD_VEX_W_1_0F45_P_0_LEN_1,
845 MOD_VEX_W_0_0F45_P_2_LEN_1,
846 MOD_VEX_W_1_0F45_P_2_LEN_1,
847 MOD_VEX_W_0_0F46_P_0_LEN_1,
848 MOD_VEX_W_1_0F46_P_0_LEN_1,
849 MOD_VEX_W_0_0F46_P_2_LEN_1,
850 MOD_VEX_W_1_0F46_P_2_LEN_1,
851 MOD_VEX_W_0_0F47_P_0_LEN_1,
852 MOD_VEX_W_1_0F47_P_0_LEN_1,
853 MOD_VEX_W_0_0F47_P_2_LEN_1,
854 MOD_VEX_W_1_0F47_P_2_LEN_1,
855 MOD_VEX_W_0_0F4A_P_0_LEN_1,
856 MOD_VEX_W_1_0F4A_P_0_LEN_1,
857 MOD_VEX_W_0_0F4A_P_2_LEN_1,
858 MOD_VEX_W_1_0F4A_P_2_LEN_1,
859 MOD_VEX_W_0_0F4B_P_0_LEN_1,
860 MOD_VEX_W_1_0F4B_P_0_LEN_1,
861 MOD_VEX_W_0_0F4B_P_2_LEN_1,
873 MOD_VEX_W_0_0F91_P_0_LEN_0,
874 MOD_VEX_W_1_0F91_P_0_LEN_0,
875 MOD_VEX_W_0_0F91_P_2_LEN_0,
876 MOD_VEX_W_1_0F91_P_2_LEN_0,
877 MOD_VEX_W_0_0F92_P_0_LEN_0,
878 MOD_VEX_W_0_0F92_P_2_LEN_0,
879 MOD_VEX_W_0_0F92_P_3_LEN_0,
880 MOD_VEX_W_1_0F92_P_3_LEN_0,
881 MOD_VEX_W_0_0F93_P_0_LEN_0,
882 MOD_VEX_W_0_0F93_P_2_LEN_0,
883 MOD_VEX_W_0_0F93_P_3_LEN_0,
884 MOD_VEX_W_1_0F93_P_3_LEN_0,
885 MOD_VEX_W_0_0F98_P_0_LEN_0,
886 MOD_VEX_W_1_0F98_P_0_LEN_0,
887 MOD_VEX_W_0_0F98_P_2_LEN_0,
888 MOD_VEX_W_1_0F98_P_2_LEN_0,
889 MOD_VEX_W_0_0F99_P_0_LEN_0,
890 MOD_VEX_W_1_0F99_P_0_LEN_0,
891 MOD_VEX_W_0_0F99_P_2_LEN_0,
892 MOD_VEX_W_1_0F99_P_2_LEN_0,
895 MOD_VEX_0FD7_PREFIX_2,
896 MOD_VEX_0FE7_PREFIX_2,
897 MOD_VEX_0FF0_PREFIX_3,
898 MOD_VEX_0F381A_PREFIX_2,
899 MOD_VEX_0F382A_PREFIX_2,
900 MOD_VEX_0F382C_PREFIX_2,
901 MOD_VEX_0F382D_PREFIX_2,
902 MOD_VEX_0F382E_PREFIX_2,
903 MOD_VEX_0F382F_PREFIX_2,
904 MOD_VEX_0F385A_PREFIX_2,
905 MOD_VEX_0F388C_PREFIX_2,
906 MOD_VEX_0F388E_PREFIX_2,
907 MOD_VEX_W_0_0F3A30_P_2_LEN_0,
908 MOD_VEX_W_1_0F3A30_P_2_LEN_0,
909 MOD_VEX_W_0_0F3A31_P_2_LEN_0,
910 MOD_VEX_W_1_0F3A31_P_2_LEN_0,
911 MOD_VEX_W_0_0F3A32_P_2_LEN_0,
912 MOD_VEX_W_1_0F3A32_P_2_LEN_0,
913 MOD_VEX_W_0_0F3A33_P_2_LEN_0,
914 MOD_VEX_W_1_0F3A33_P_2_LEN_0,
916 MOD_EVEX_0F10_PREFIX_1,
917 MOD_EVEX_0F10_PREFIX_3,
918 MOD_EVEX_0F11_PREFIX_1,
919 MOD_EVEX_0F11_PREFIX_3,
920 MOD_EVEX_0F12_PREFIX_0,
921 MOD_EVEX_0F16_PREFIX_0,
922 MOD_EVEX_0F38C6_REG_1,
923 MOD_EVEX_0F38C6_REG_2,
924 MOD_EVEX_0F38C6_REG_5,
925 MOD_EVEX_0F38C6_REG_6,
926 MOD_EVEX_0F38C7_REG_1,
927 MOD_EVEX_0F38C7_REG_2,
928 MOD_EVEX_0F38C7_REG_5,
929 MOD_EVEX_0F38C7_REG_6
950 PREFIX_MOD_0_0F01_REG_5,
951 PREFIX_MOD_3_0F01_REG_5_RM_0,
952 PREFIX_MOD_3_0F01_REG_5_RM_2,
996 PREFIX_MOD_0_0FAE_REG_4,
997 PREFIX_MOD_3_0FAE_REG_4,
998 PREFIX_MOD_0_0FAE_REG_5,
999 PREFIX_MOD_3_0FAE_REG_5,
1007 PREFIX_MOD_0_0FC7_REG_6,
1008 PREFIX_MOD_3_0FC7_REG_6,
1009 PREFIX_MOD_3_0FC7_REG_7,
1134 PREFIX_VEX_0F71_REG_2,
1135 PREFIX_VEX_0F71_REG_4,
1136 PREFIX_VEX_0F71_REG_6,
1137 PREFIX_VEX_0F72_REG_2,
1138 PREFIX_VEX_0F72_REG_4,
1139 PREFIX_VEX_0F72_REG_6,
1140 PREFIX_VEX_0F73_REG_2,
1141 PREFIX_VEX_0F73_REG_3,
1142 PREFIX_VEX_0F73_REG_6,
1143 PREFIX_VEX_0F73_REG_7,
1315 PREFIX_VEX_0F38F3_REG_1,
1316 PREFIX_VEX_0F38F3_REG_2,
1317 PREFIX_VEX_0F38F3_REG_3,
1434 PREFIX_EVEX_0F71_REG_2,
1435 PREFIX_EVEX_0F71_REG_4,
1436 PREFIX_EVEX_0F71_REG_6,
1437 PREFIX_EVEX_0F72_REG_0,
1438 PREFIX_EVEX_0F72_REG_1,
1439 PREFIX_EVEX_0F72_REG_2,
1440 PREFIX_EVEX_0F72_REG_4,
1441 PREFIX_EVEX_0F72_REG_6,
1442 PREFIX_EVEX_0F73_REG_2,
1443 PREFIX_EVEX_0F73_REG_3,
1444 PREFIX_EVEX_0F73_REG_6,
1445 PREFIX_EVEX_0F73_REG_7,
1631 PREFIX_EVEX_0F38C6_REG_1,
1632 PREFIX_EVEX_0F38C6_REG_2,
1633 PREFIX_EVEX_0F38C6_REG_5,
1634 PREFIX_EVEX_0F38C6_REG_6,
1635 PREFIX_EVEX_0F38C7_REG_1,
1636 PREFIX_EVEX_0F38C7_REG_2,
1637 PREFIX_EVEX_0F38C7_REG_5,
1638 PREFIX_EVEX_0F38C7_REG_6,
1728 THREE_BYTE_0F38 = 0,
1755 VEX_LEN_0F10_P_1 = 0,
1759 VEX_LEN_0F12_P_0_M_0,
1760 VEX_LEN_0F12_P_0_M_1,
1763 VEX_LEN_0F16_P_0_M_0,
1764 VEX_LEN_0F16_P_0_M_1,
1828 VEX_LEN_0FAE_R_2_M_0,
1829 VEX_LEN_0FAE_R_3_M_0,
1838 VEX_LEN_0F381A_P_2_M_0,
1841 VEX_LEN_0F385A_P_2_M_0,
1848 VEX_LEN_0F38F3_R_1_P_0,
1849 VEX_LEN_0F38F3_R_2_P_0,
1850 VEX_LEN_0F38F3_R_3_P_0,
1896 VEX_LEN_0FXOP_08_CC,
1897 VEX_LEN_0FXOP_08_CD,
1898 VEX_LEN_0FXOP_08_CE,
1899 VEX_LEN_0FXOP_08_CF,
1900 VEX_LEN_0FXOP_08_EC,
1901 VEX_LEN_0FXOP_08_ED,
1902 VEX_LEN_0FXOP_08_EE,
1903 VEX_LEN_0FXOP_08_EF,
1904 VEX_LEN_0FXOP_09_80,
1938 VEX_W_0F41_P_0_LEN_1,
1939 VEX_W_0F41_P_2_LEN_1,
1940 VEX_W_0F42_P_0_LEN_1,
1941 VEX_W_0F42_P_2_LEN_1,
1942 VEX_W_0F44_P_0_LEN_0,
1943 VEX_W_0F44_P_2_LEN_0,
1944 VEX_W_0F45_P_0_LEN_1,
1945 VEX_W_0F45_P_2_LEN_1,
1946 VEX_W_0F46_P_0_LEN_1,
1947 VEX_W_0F46_P_2_LEN_1,
1948 VEX_W_0F47_P_0_LEN_1,
1949 VEX_W_0F47_P_2_LEN_1,
1950 VEX_W_0F4A_P_0_LEN_1,
1951 VEX_W_0F4A_P_2_LEN_1,
1952 VEX_W_0F4B_P_0_LEN_1,
1953 VEX_W_0F4B_P_2_LEN_1,
2033 VEX_W_0F90_P_0_LEN_0,
2034 VEX_W_0F90_P_2_LEN_0,
2035 VEX_W_0F91_P_0_LEN_0,
2036 VEX_W_0F91_P_2_LEN_0,
2037 VEX_W_0F92_P_0_LEN_0,
2038 VEX_W_0F92_P_2_LEN_0,
2039 VEX_W_0F92_P_3_LEN_0,
2040 VEX_W_0F93_P_0_LEN_0,
2041 VEX_W_0F93_P_2_LEN_0,
2042 VEX_W_0F93_P_3_LEN_0,
2043 VEX_W_0F98_P_0_LEN_0,
2044 VEX_W_0F98_P_2_LEN_0,
2045 VEX_W_0F99_P_0_LEN_0,
2046 VEX_W_0F99_P_2_LEN_0,
2125 VEX_W_0F381A_P_2_M_0,
2137 VEX_W_0F382A_P_2_M_0,
2139 VEX_W_0F382C_P_2_M_0,
2140 VEX_W_0F382D_P_2_M_0,
2141 VEX_W_0F382E_P_2_M_0,
2142 VEX_W_0F382F_P_2_M_0,
2164 VEX_W_0F385A_P_2_M_0,
2192 VEX_W_0F3A30_P_2_LEN_0,
2193 VEX_W_0F3A31_P_2_LEN_0,
2194 VEX_W_0F3A32_P_2_LEN_0,
2195 VEX_W_0F3A33_P_2_LEN_0,
2213 EVEX_W_0F10_P_1_M_0,
2214 EVEX_W_0F10_P_1_M_1,
2216 EVEX_W_0F10_P_3_M_0,
2217 EVEX_W_0F10_P_3_M_1,
2219 EVEX_W_0F11_P_1_M_0,
2220 EVEX_W_0F11_P_1_M_1,
2222 EVEX_W_0F11_P_3_M_0,
2223 EVEX_W_0F11_P_3_M_1,
2224 EVEX_W_0F12_P_0_M_0,
2225 EVEX_W_0F12_P_0_M_1,
2235 EVEX_W_0F16_P_0_M_0,
2236 EVEX_W_0F16_P_0_M_1,
2307 EVEX_W_0F72_R_2_P_2,
2308 EVEX_W_0F72_R_6_P_2,
2309 EVEX_W_0F73_R_2_P_2,
2310 EVEX_W_0F73_R_6_P_2,
2411 EVEX_W_0F38C7_R_1_P_2,
2412 EVEX_W_0F38C7_R_2_P_2,
2413 EVEX_W_0F38C7_R_5_P_2,
2414 EVEX_W_0F38C7_R_6_P_2,
2449 typedef void (*op_rtn) (int bytemode, int sizeflag);
2458 unsigned int prefix_requirement;
2461 /* Upper case letters in the instruction names here are macros.
2462 'A' => print 'b' if no register operands or suffix_always is true
2463 'B' => print 'b' if suffix_always is true
2464 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2466 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2467 suffix_always is true
2468 'E' => print 'e' if 32-bit form of jcxz
2469 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2470 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2471 'H' => print ",pt" or ",pn" branch hint
2472 'I' => honor following macro letter even in Intel mode (implemented only
2473 for some of the macro letters)
2475 'K' => print 'd' or 'q' if rex prefix is present.
2476 'L' => print 'l' if suffix_always is true
2477 'M' => print 'r' if intel_mnemonic is false.
2478 'N' => print 'n' if instruction has no wait "prefix"
2479 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2480 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2481 or suffix_always is true. print 'q' if rex prefix is present.
2482 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2484 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2485 'S' => print 'w', 'l' or 'q' if suffix_always is true
2486 'T' => print 'q' in 64bit mode if instruction has no operand size
2487 prefix and behave as 'P' otherwise
2488 'U' => print 'q' in 64bit mode if instruction has no operand size
2489 prefix and behave as 'Q' otherwise
2490 'V' => print 'q' in 64bit mode if instruction has no operand size
2491 prefix and behave as 'S' otherwise
2492 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2493 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2494 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2495 suffix_always is true.
2496 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2497 '!' => change condition from true to false or from false to true.
2498 '%' => add 1 upper case letter to the macro.
2499 '^' => print 'w' or 'l' depending on operand size prefix or
2500 suffix_always is true (lcall/ljmp).
2501 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2502 on operand size prefix.
2503 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2504 has no operand size prefix for AMD64 ISA, behave as 'P'
2507 2 upper case letter macros:
2508 "XY" => print 'x' or 'y' if suffix_always is true or no register
2509 operands and no broadcast.
2510 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2511 register operands and no broadcast.
2512 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2513 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2514 or suffix_always is true
2515 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2516 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2517 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2518 "LW" => print 'd', 'q' depending on the VEX.W bit
2519 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2520 an operand size prefix, or suffix_always is true. print
2521 'q' if rex prefix is present.
2523 Many of the above letters print nothing in Intel mode. See "putop"
2526 Braces '{' and '}', and vertical bars '|', indicate alternative
2527 mnemonic strings for AT&T and Intel. */
2529 static const struct dis386 dis386[] = {
2531 { "addB", { Ebh1, Gb }, 0 },
2532 { "addS", { Evh1, Gv }, 0 },
2533 { "addB", { Gb, EbS }, 0 },
2534 { "addS", { Gv, EvS }, 0 },
2535 { "addB", { AL, Ib }, 0 },
2536 { "addS", { eAX, Iv }, 0 },
2537 { X86_64_TABLE (X86_64_06) },
2538 { X86_64_TABLE (X86_64_07) },
2540 { "orB", { Ebh1, Gb }, 0 },
2541 { "orS", { Evh1, Gv }, 0 },
2542 { "orB", { Gb, EbS }, 0 },
2543 { "orS", { Gv, EvS }, 0 },
2544 { "orB", { AL, Ib }, 0 },
2545 { "orS", { eAX, Iv }, 0 },
2546 { X86_64_TABLE (X86_64_0D) },
2547 { Bad_Opcode }, /* 0x0f extended opcode escape */
2549 { "adcB", { Ebh1, Gb }, 0 },
2550 { "adcS", { Evh1, Gv }, 0 },
2551 { "adcB", { Gb, EbS }, 0 },
2552 { "adcS", { Gv, EvS }, 0 },
2553 { "adcB", { AL, Ib }, 0 },
2554 { "adcS", { eAX, Iv }, 0 },
2555 { X86_64_TABLE (X86_64_16) },
2556 { X86_64_TABLE (X86_64_17) },
2558 { "sbbB", { Ebh1, Gb }, 0 },
2559 { "sbbS", { Evh1, Gv }, 0 },
2560 { "sbbB", { Gb, EbS }, 0 },
2561 { "sbbS", { Gv, EvS }, 0 },
2562 { "sbbB", { AL, Ib }, 0 },
2563 { "sbbS", { eAX, Iv }, 0 },
2564 { X86_64_TABLE (X86_64_1E) },
2565 { X86_64_TABLE (X86_64_1F) },
2567 { "andB", { Ebh1, Gb }, 0 },
2568 { "andS", { Evh1, Gv }, 0 },
2569 { "andB", { Gb, EbS }, 0 },
2570 { "andS", { Gv, EvS }, 0 },
2571 { "andB", { AL, Ib }, 0 },
2572 { "andS", { eAX, Iv }, 0 },
2573 { Bad_Opcode }, /* SEG ES prefix */
2574 { X86_64_TABLE (X86_64_27) },
2576 { "subB", { Ebh1, Gb }, 0 },
2577 { "subS", { Evh1, Gv }, 0 },
2578 { "subB", { Gb, EbS }, 0 },
2579 { "subS", { Gv, EvS }, 0 },
2580 { "subB", { AL, Ib }, 0 },
2581 { "subS", { eAX, Iv }, 0 },
2582 { Bad_Opcode }, /* SEG CS prefix */
2583 { X86_64_TABLE (X86_64_2F) },
2585 { "xorB", { Ebh1, Gb }, 0 },
2586 { "xorS", { Evh1, Gv }, 0 },
2587 { "xorB", { Gb, EbS }, 0 },
2588 { "xorS", { Gv, EvS }, 0 },
2589 { "xorB", { AL, Ib }, 0 },
2590 { "xorS", { eAX, Iv }, 0 },
2591 { Bad_Opcode }, /* SEG SS prefix */
2592 { X86_64_TABLE (X86_64_37) },
2594 { "cmpB", { Eb, Gb }, 0 },
2595 { "cmpS", { Ev, Gv }, 0 },
2596 { "cmpB", { Gb, EbS }, 0 },
2597 { "cmpS", { Gv, EvS }, 0 },
2598 { "cmpB", { AL, Ib }, 0 },
2599 { "cmpS", { eAX, Iv }, 0 },
2600 { Bad_Opcode }, /* SEG DS prefix */
2601 { X86_64_TABLE (X86_64_3F) },
2603 { "inc{S|}", { RMeAX }, 0 },
2604 { "inc{S|}", { RMeCX }, 0 },
2605 { "inc{S|}", { RMeDX }, 0 },
2606 { "inc{S|}", { RMeBX }, 0 },
2607 { "inc{S|}", { RMeSP }, 0 },
2608 { "inc{S|}", { RMeBP }, 0 },
2609 { "inc{S|}", { RMeSI }, 0 },
2610 { "inc{S|}", { RMeDI }, 0 },
2612 { "dec{S|}", { RMeAX }, 0 },
2613 { "dec{S|}", { RMeCX }, 0 },
2614 { "dec{S|}", { RMeDX }, 0 },
2615 { "dec{S|}", { RMeBX }, 0 },
2616 { "dec{S|}", { RMeSP }, 0 },
2617 { "dec{S|}", { RMeBP }, 0 },
2618 { "dec{S|}", { RMeSI }, 0 },
2619 { "dec{S|}", { RMeDI }, 0 },
2621 { "pushV", { RMrAX }, 0 },
2622 { "pushV", { RMrCX }, 0 },
2623 { "pushV", { RMrDX }, 0 },
2624 { "pushV", { RMrBX }, 0 },
2625 { "pushV", { RMrSP }, 0 },
2626 { "pushV", { RMrBP }, 0 },
2627 { "pushV", { RMrSI }, 0 },
2628 { "pushV", { RMrDI }, 0 },
2630 { "popV", { RMrAX }, 0 },
2631 { "popV", { RMrCX }, 0 },
2632 { "popV", { RMrDX }, 0 },
2633 { "popV", { RMrBX }, 0 },
2634 { "popV", { RMrSP }, 0 },
2635 { "popV", { RMrBP }, 0 },
2636 { "popV", { RMrSI }, 0 },
2637 { "popV", { RMrDI }, 0 },
2639 { X86_64_TABLE (X86_64_60) },
2640 { X86_64_TABLE (X86_64_61) },
2641 { X86_64_TABLE (X86_64_62) },
2642 { X86_64_TABLE (X86_64_63) },
2643 { Bad_Opcode }, /* seg fs */
2644 { Bad_Opcode }, /* seg gs */
2645 { Bad_Opcode }, /* op size prefix */
2646 { Bad_Opcode }, /* adr size prefix */
2648 { "pushT", { sIv }, 0 },
2649 { "imulS", { Gv, Ev, Iv }, 0 },
2650 { "pushT", { sIbT }, 0 },
2651 { "imulS", { Gv, Ev, sIb }, 0 },
2652 { "ins{b|}", { Ybr, indirDX }, 0 },
2653 { X86_64_TABLE (X86_64_6D) },
2654 { "outs{b|}", { indirDXr, Xb }, 0 },
2655 { X86_64_TABLE (X86_64_6F) },
2657 { "joH", { Jb, BND, cond_jump_flag }, 0 },
2658 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
2659 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
2660 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
2661 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
2662 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
2663 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
2664 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
2666 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
2667 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
2668 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
2669 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
2670 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
2671 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
2672 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
2673 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
2675 { REG_TABLE (REG_80) },
2676 { REG_TABLE (REG_81) },
2677 { X86_64_TABLE (X86_64_82) },
2678 { REG_TABLE (REG_83) },
2679 { "testB", { Eb, Gb }, 0 },
2680 { "testS", { Ev, Gv }, 0 },
2681 { "xchgB", { Ebh2, Gb }, 0 },
2682 { "xchgS", { Evh2, Gv }, 0 },
2684 { "movB", { Ebh3, Gb }, 0 },
2685 { "movS", { Evh3, Gv }, 0 },
2686 { "movB", { Gb, EbS }, 0 },
2687 { "movS", { Gv, EvS }, 0 },
2688 { "movD", { Sv, Sw }, 0 },
2689 { MOD_TABLE (MOD_8D) },
2690 { "movD", { Sw, Sv }, 0 },
2691 { REG_TABLE (REG_8F) },
2693 { PREFIX_TABLE (PREFIX_90) },
2694 { "xchgS", { RMeCX, eAX }, 0 },
2695 { "xchgS", { RMeDX, eAX }, 0 },
2696 { "xchgS", { RMeBX, eAX }, 0 },
2697 { "xchgS", { RMeSP, eAX }, 0 },
2698 { "xchgS", { RMeBP, eAX }, 0 },
2699 { "xchgS", { RMeSI, eAX }, 0 },
2700 { "xchgS", { RMeDI, eAX }, 0 },
2702 { "cW{t|}R", { XX }, 0 },
2703 { "cR{t|}O", { XX }, 0 },
2704 { X86_64_TABLE (X86_64_9A) },
2705 { Bad_Opcode }, /* fwait */
2706 { "pushfT", { XX }, 0 },
2707 { "popfT", { XX }, 0 },
2708 { "sahf", { XX }, 0 },
2709 { "lahf", { XX }, 0 },
2711 { "mov%LB", { AL, Ob }, 0 },
2712 { "mov%LS", { eAX, Ov }, 0 },
2713 { "mov%LB", { Ob, AL }, 0 },
2714 { "mov%LS", { Ov, eAX }, 0 },
2715 { "movs{b|}", { Ybr, Xb }, 0 },
2716 { "movs{R|}", { Yvr, Xv }, 0 },
2717 { "cmps{b|}", { Xb, Yb }, 0 },
2718 { "cmps{R|}", { Xv, Yv }, 0 },
2720 { "testB", { AL, Ib }, 0 },
2721 { "testS", { eAX, Iv }, 0 },
2722 { "stosB", { Ybr, AL }, 0 },
2723 { "stosS", { Yvr, eAX }, 0 },
2724 { "lodsB", { ALr, Xb }, 0 },
2725 { "lodsS", { eAXr, Xv }, 0 },
2726 { "scasB", { AL, Yb }, 0 },
2727 { "scasS", { eAX, Yv }, 0 },
2729 { "movB", { RMAL, Ib }, 0 },
2730 { "movB", { RMCL, Ib }, 0 },
2731 { "movB", { RMDL, Ib }, 0 },
2732 { "movB", { RMBL, Ib }, 0 },
2733 { "movB", { RMAH, Ib }, 0 },
2734 { "movB", { RMCH, Ib }, 0 },
2735 { "movB", { RMDH, Ib }, 0 },
2736 { "movB", { RMBH, Ib }, 0 },
2738 { "mov%LV", { RMeAX, Iv64 }, 0 },
2739 { "mov%LV", { RMeCX, Iv64 }, 0 },
2740 { "mov%LV", { RMeDX, Iv64 }, 0 },
2741 { "mov%LV", { RMeBX, Iv64 }, 0 },
2742 { "mov%LV", { RMeSP, Iv64 }, 0 },
2743 { "mov%LV", { RMeBP, Iv64 }, 0 },
2744 { "mov%LV", { RMeSI, Iv64 }, 0 },
2745 { "mov%LV", { RMeDI, Iv64 }, 0 },
2747 { REG_TABLE (REG_C0) },
2748 { REG_TABLE (REG_C1) },
2749 { "retT", { Iw, BND }, 0 },
2750 { "retT", { BND }, 0 },
2751 { X86_64_TABLE (X86_64_C4) },
2752 { X86_64_TABLE (X86_64_C5) },
2753 { REG_TABLE (REG_C6) },
2754 { REG_TABLE (REG_C7) },
2756 { "enterT", { Iw, Ib }, 0 },
2757 { "leaveT", { XX }, 0 },
2758 { "Jret{|f}P", { Iw }, 0 },
2759 { "Jret{|f}P", { XX }, 0 },
2760 { "int3", { XX }, 0 },
2761 { "int", { Ib }, 0 },
2762 { X86_64_TABLE (X86_64_CE) },
2763 { "iret%LP", { XX }, 0 },
2765 { REG_TABLE (REG_D0) },
2766 { REG_TABLE (REG_D1) },
2767 { REG_TABLE (REG_D2) },
2768 { REG_TABLE (REG_D3) },
2769 { X86_64_TABLE (X86_64_D4) },
2770 { X86_64_TABLE (X86_64_D5) },
2772 { "xlat", { DSBX }, 0 },
2783 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2784 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2785 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2786 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2787 { "inB", { AL, Ib }, 0 },
2788 { "inG", { zAX, Ib }, 0 },
2789 { "outB", { Ib, AL }, 0 },
2790 { "outG", { Ib, zAX }, 0 },
2792 { X86_64_TABLE (X86_64_E8) },
2793 { X86_64_TABLE (X86_64_E9) },
2794 { X86_64_TABLE (X86_64_EA) },
2795 { "jmp", { Jb, BND }, 0 },
2796 { "inB", { AL, indirDX }, 0 },
2797 { "inG", { zAX, indirDX }, 0 },
2798 { "outB", { indirDX, AL }, 0 },
2799 { "outG", { indirDX, zAX }, 0 },
2801 { Bad_Opcode }, /* lock prefix */
2802 { "icebp", { XX }, 0 },
2803 { Bad_Opcode }, /* repne */
2804 { Bad_Opcode }, /* repz */
2805 { "hlt", { XX }, 0 },
2806 { "cmc", { XX }, 0 },
2807 { REG_TABLE (REG_F6) },
2808 { REG_TABLE (REG_F7) },
2810 { "clc", { XX }, 0 },
2811 { "stc", { XX }, 0 },
2812 { "cli", { XX }, 0 },
2813 { "sti", { XX }, 0 },
2814 { "cld", { XX }, 0 },
2815 { "std", { XX }, 0 },
2816 { REG_TABLE (REG_FE) },
2817 { REG_TABLE (REG_FF) },
2820 static const struct dis386 dis386_twobyte[] = {
2822 { REG_TABLE (REG_0F00 ) },
2823 { REG_TABLE (REG_0F01 ) },
2824 { "larS", { Gv, Ew }, 0 },
2825 { "lslS", { Gv, Ew }, 0 },
2827 { "syscall", { XX }, 0 },
2828 { "clts", { XX }, 0 },
2829 { "sysret%LP", { XX }, 0 },
2831 { "invd", { XX }, 0 },
2832 { "wbinvd", { XX }, 0 },
2834 { "ud2", { XX }, 0 },
2836 { REG_TABLE (REG_0F0D) },
2837 { "femms", { XX }, 0 },
2838 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2840 { PREFIX_TABLE (PREFIX_0F10) },
2841 { PREFIX_TABLE (PREFIX_0F11) },
2842 { PREFIX_TABLE (PREFIX_0F12) },
2843 { MOD_TABLE (MOD_0F13) },
2844 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2845 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2846 { PREFIX_TABLE (PREFIX_0F16) },
2847 { MOD_TABLE (MOD_0F17) },
2849 { REG_TABLE (REG_0F18) },
2850 { "nopQ", { Ev }, 0 },
2851 { PREFIX_TABLE (PREFIX_0F1A) },
2852 { PREFIX_TABLE (PREFIX_0F1B) },
2853 { "nopQ", { Ev }, 0 },
2854 { "nopQ", { Ev }, 0 },
2855 { PREFIX_TABLE (PREFIX_0F1E) },
2856 { "nopQ", { Ev }, 0 },
2858 { "movZ", { Rm, Cm }, 0 },
2859 { "movZ", { Rm, Dm }, 0 },
2860 { "movZ", { Cm, Rm }, 0 },
2861 { "movZ", { Dm, Rm }, 0 },
2862 { MOD_TABLE (MOD_0F24) },
2864 { MOD_TABLE (MOD_0F26) },
2867 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2868 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2869 { PREFIX_TABLE (PREFIX_0F2A) },
2870 { PREFIX_TABLE (PREFIX_0F2B) },
2871 { PREFIX_TABLE (PREFIX_0F2C) },
2872 { PREFIX_TABLE (PREFIX_0F2D) },
2873 { PREFIX_TABLE (PREFIX_0F2E) },
2874 { PREFIX_TABLE (PREFIX_0F2F) },
2876 { "wrmsr", { XX }, 0 },
2877 { "rdtsc", { XX }, 0 },
2878 { "rdmsr", { XX }, 0 },
2879 { "rdpmc", { XX }, 0 },
2880 { "sysenter", { XX }, 0 },
2881 { "sysexit", { XX }, 0 },
2883 { "getsec", { XX }, 0 },
2885 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2887 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2894 { "cmovoS", { Gv, Ev }, 0 },
2895 { "cmovnoS", { Gv, Ev }, 0 },
2896 { "cmovbS", { Gv, Ev }, 0 },
2897 { "cmovaeS", { Gv, Ev }, 0 },
2898 { "cmoveS", { Gv, Ev }, 0 },
2899 { "cmovneS", { Gv, Ev }, 0 },
2900 { "cmovbeS", { Gv, Ev }, 0 },
2901 { "cmovaS", { Gv, Ev }, 0 },
2903 { "cmovsS", { Gv, Ev }, 0 },
2904 { "cmovnsS", { Gv, Ev }, 0 },
2905 { "cmovpS", { Gv, Ev }, 0 },
2906 { "cmovnpS", { Gv, Ev }, 0 },
2907 { "cmovlS", { Gv, Ev }, 0 },
2908 { "cmovgeS", { Gv, Ev }, 0 },
2909 { "cmovleS", { Gv, Ev }, 0 },
2910 { "cmovgS", { Gv, Ev }, 0 },
2912 { MOD_TABLE (MOD_0F51) },
2913 { PREFIX_TABLE (PREFIX_0F51) },
2914 { PREFIX_TABLE (PREFIX_0F52) },
2915 { PREFIX_TABLE (PREFIX_0F53) },
2916 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2917 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2918 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2919 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2921 { PREFIX_TABLE (PREFIX_0F58) },
2922 { PREFIX_TABLE (PREFIX_0F59) },
2923 { PREFIX_TABLE (PREFIX_0F5A) },
2924 { PREFIX_TABLE (PREFIX_0F5B) },
2925 { PREFIX_TABLE (PREFIX_0F5C) },
2926 { PREFIX_TABLE (PREFIX_0F5D) },
2927 { PREFIX_TABLE (PREFIX_0F5E) },
2928 { PREFIX_TABLE (PREFIX_0F5F) },
2930 { PREFIX_TABLE (PREFIX_0F60) },
2931 { PREFIX_TABLE (PREFIX_0F61) },
2932 { PREFIX_TABLE (PREFIX_0F62) },
2933 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2934 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2935 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2936 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2937 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2939 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2940 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2941 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2942 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2943 { PREFIX_TABLE (PREFIX_0F6C) },
2944 { PREFIX_TABLE (PREFIX_0F6D) },
2945 { "movK", { MX, Edq }, PREFIX_OPCODE },
2946 { PREFIX_TABLE (PREFIX_0F6F) },
2948 { PREFIX_TABLE (PREFIX_0F70) },
2949 { REG_TABLE (REG_0F71) },
2950 { REG_TABLE (REG_0F72) },
2951 { REG_TABLE (REG_0F73) },
2952 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2953 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2954 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2955 { "emms", { XX }, PREFIX_OPCODE },
2957 { PREFIX_TABLE (PREFIX_0F78) },
2958 { PREFIX_TABLE (PREFIX_0F79) },
2961 { PREFIX_TABLE (PREFIX_0F7C) },
2962 { PREFIX_TABLE (PREFIX_0F7D) },
2963 { PREFIX_TABLE (PREFIX_0F7E) },
2964 { PREFIX_TABLE (PREFIX_0F7F) },
2966 { "joH", { Jv, BND, cond_jump_flag }, 0 },
2967 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
2968 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
2969 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
2970 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
2971 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
2972 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
2973 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
2975 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
2976 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
2977 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
2978 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
2979 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
2980 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
2981 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
2982 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
2984 { "seto", { Eb }, 0 },
2985 { "setno", { Eb }, 0 },
2986 { "setb", { Eb }, 0 },
2987 { "setae", { Eb }, 0 },
2988 { "sete", { Eb }, 0 },
2989 { "setne", { Eb }, 0 },
2990 { "setbe", { Eb }, 0 },
2991 { "seta", { Eb }, 0 },
2993 { "sets", { Eb }, 0 },
2994 { "setns", { Eb }, 0 },
2995 { "setp", { Eb }, 0 },
2996 { "setnp", { Eb }, 0 },
2997 { "setl", { Eb }, 0 },
2998 { "setge", { Eb }, 0 },
2999 { "setle", { Eb }, 0 },
3000 { "setg", { Eb }, 0 },
3002 { "pushT", { fs }, 0 },
3003 { "popT", { fs }, 0 },
3004 { "cpuid", { XX }, 0 },
3005 { "btS", { Ev, Gv }, 0 },
3006 { "shldS", { Ev, Gv, Ib }, 0 },
3007 { "shldS", { Ev, Gv, CL }, 0 },
3008 { REG_TABLE (REG_0FA6) },
3009 { REG_TABLE (REG_0FA7) },
3011 { "pushT", { gs }, 0 },
3012 { "popT", { gs }, 0 },
3013 { "rsm", { XX }, 0 },
3014 { "btsS", { Evh1, Gv }, 0 },
3015 { "shrdS", { Ev, Gv, Ib }, 0 },
3016 { "shrdS", { Ev, Gv, CL }, 0 },
3017 { REG_TABLE (REG_0FAE) },
3018 { "imulS", { Gv, Ev }, 0 },
3020 { "cmpxchgB", { Ebh1, Gb }, 0 },
3021 { "cmpxchgS", { Evh1, Gv }, 0 },
3022 { MOD_TABLE (MOD_0FB2) },
3023 { "btrS", { Evh1, Gv }, 0 },
3024 { MOD_TABLE (MOD_0FB4) },
3025 { MOD_TABLE (MOD_0FB5) },
3026 { "movz{bR|x}", { Gv, Eb }, 0 },
3027 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3029 { PREFIX_TABLE (PREFIX_0FB8) },
3030 { "ud1", { XX }, 0 },
3031 { REG_TABLE (REG_0FBA) },
3032 { "btcS", { Evh1, Gv }, 0 },
3033 { PREFIX_TABLE (PREFIX_0FBC) },
3034 { PREFIX_TABLE (PREFIX_0FBD) },
3035 { "movs{bR|x}", { Gv, Eb }, 0 },
3036 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3038 { "xaddB", { Ebh1, Gb }, 0 },
3039 { "xaddS", { Evh1, Gv }, 0 },
3040 { PREFIX_TABLE (PREFIX_0FC2) },
3041 { MOD_TABLE (MOD_0FC3) },
3042 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
3043 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
3044 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
3045 { REG_TABLE (REG_0FC7) },
3047 { "bswap", { RMeAX }, 0 },
3048 { "bswap", { RMeCX }, 0 },
3049 { "bswap", { RMeDX }, 0 },
3050 { "bswap", { RMeBX }, 0 },
3051 { "bswap", { RMeSP }, 0 },
3052 { "bswap", { RMeBP }, 0 },
3053 { "bswap", { RMeSI }, 0 },
3054 { "bswap", { RMeDI }, 0 },
3056 { PREFIX_TABLE (PREFIX_0FD0) },
3057 { "psrlw", { MX, EM }, PREFIX_OPCODE },
3058 { "psrld", { MX, EM }, PREFIX_OPCODE },
3059 { "psrlq", { MX, EM }, PREFIX_OPCODE },
3060 { "paddq", { MX, EM }, PREFIX_OPCODE },
3061 { "pmullw", { MX, EM }, PREFIX_OPCODE },
3062 { PREFIX_TABLE (PREFIX_0FD6) },
3063 { MOD_TABLE (MOD_0FD7) },
3065 { "psubusb", { MX, EM }, PREFIX_OPCODE },
3066 { "psubusw", { MX, EM }, PREFIX_OPCODE },
3067 { "pminub", { MX, EM }, PREFIX_OPCODE },
3068 { "pand", { MX, EM }, PREFIX_OPCODE },
3069 { "paddusb", { MX, EM }, PREFIX_OPCODE },
3070 { "paddusw", { MX, EM }, PREFIX_OPCODE },
3071 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
3072 { "pandn", { MX, EM }, PREFIX_OPCODE },
3074 { "pavgb", { MX, EM }, PREFIX_OPCODE },
3075 { "psraw", { MX, EM }, PREFIX_OPCODE },
3076 { "psrad", { MX, EM }, PREFIX_OPCODE },
3077 { "pavgw", { MX, EM }, PREFIX_OPCODE },
3078 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
3079 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
3080 { PREFIX_TABLE (PREFIX_0FE6) },
3081 { PREFIX_TABLE (PREFIX_0FE7) },
3083 { "psubsb", { MX, EM }, PREFIX_OPCODE },
3084 { "psubsw", { MX, EM }, PREFIX_OPCODE },
3085 { "pminsw", { MX, EM }, PREFIX_OPCODE },
3086 { "por", { MX, EM }, PREFIX_OPCODE },
3087 { "paddsb", { MX, EM }, PREFIX_OPCODE },
3088 { "paddsw", { MX, EM }, PREFIX_OPCODE },
3089 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
3090 { "pxor", { MX, EM }, PREFIX_OPCODE },
3092 { PREFIX_TABLE (PREFIX_0FF0) },
3093 { "psllw", { MX, EM }, PREFIX_OPCODE },
3094 { "pslld", { MX, EM }, PREFIX_OPCODE },
3095 { "psllq", { MX, EM }, PREFIX_OPCODE },
3096 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
3097 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
3098 { "psadbw", { MX, EM }, PREFIX_OPCODE },
3099 { PREFIX_TABLE (PREFIX_0FF7) },
3101 { "psubb", { MX, EM }, PREFIX_OPCODE },
3102 { "psubw", { MX, EM }, PREFIX_OPCODE },
3103 { "psubd", { MX, EM }, PREFIX_OPCODE },
3104 { "psubq", { MX, EM }, PREFIX_OPCODE },
3105 { "paddb", { MX, EM }, PREFIX_OPCODE },
3106 { "paddw", { MX, EM }, PREFIX_OPCODE },
3107 { "paddd", { MX, EM }, PREFIX_OPCODE },
3111 static const unsigned char onebyte_has_modrm[256] = {
3112 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3113 /* ------------------------------- */
3114 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3115 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3116 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3117 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3118 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3119 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3120 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3121 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3122 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3123 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3124 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3125 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3126 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3127 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3128 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3129 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3130 /* ------------------------------- */
3131 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3134 static const unsigned char twobyte_has_modrm[256] = {
3135 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3136 /* ------------------------------- */
3137 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3138 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3139 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3140 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3141 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3142 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3143 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3144 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3145 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3146 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3147 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3148 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3149 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3150 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3151 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3152 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3153 /* ------------------------------- */
3154 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3157 static char obuf[100];
3159 static char *mnemonicendp;
3160 static char scratchbuf[100];
3161 static unsigned char *start_codep;
3162 static unsigned char *insn_codep;
3163 static unsigned char *codep;
3164 static unsigned char *end_codep;
3165 static int last_lock_prefix;
3166 static int last_repz_prefix;
3167 static int last_repnz_prefix;
3168 static int last_data_prefix;
3169 static int last_addr_prefix;
3170 static int last_rex_prefix;
3171 static int last_seg_prefix;
3172 static int last_active_prefix;
3173 static int fwait_prefix;
3174 /* The active segment register prefix. */
3175 static int active_seg_prefix;
3176 #define MAX_CODE_LENGTH 15
3177 /* We can up to 14 prefixes since the maximum instruction length is
3179 static int all_prefixes[MAX_CODE_LENGTH - 1];
3180 static disassemble_info *the_info;
3188 static unsigned char need_modrm;
3198 int register_specifier;
3205 int mask_register_specifier;
3211 static unsigned char need_vex;
3212 static unsigned char need_vex_reg;
3213 static unsigned char vex_w_done;
3221 /* If we are accessing mod/rm/reg without need_modrm set, then the
3222 values are stale. Hitting this abort likely indicates that you
3223 need to update onebyte_has_modrm or twobyte_has_modrm. */
3224 #define MODRM_CHECK if (!need_modrm) abort ()
3226 static const char **names64;
3227 static const char **names32;
3228 static const char **names16;
3229 static const char **names8;
3230 static const char **names8rex;
3231 static const char **names_seg;
3232 static const char *index64;
3233 static const char *index32;
3234 static const char **index16;
3235 static const char **names_bnd;
3237 static const char *intel_names64[] = {
3238 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3239 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3241 static const char *intel_names32[] = {
3242 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3243 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3245 static const char *intel_names16[] = {
3246 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3247 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3249 static const char *intel_names8[] = {
3250 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3252 static const char *intel_names8rex[] = {
3253 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3254 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3256 static const char *intel_names_seg[] = {
3257 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3259 static const char *intel_index64 = "riz";
3260 static const char *intel_index32 = "eiz";
3261 static const char *intel_index16[] = {
3262 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3265 static const char *att_names64[] = {
3266 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3267 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3269 static const char *att_names32[] = {
3270 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3271 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3273 static const char *att_names16[] = {
3274 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3275 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3277 static const char *att_names8[] = {
3278 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3280 static const char *att_names8rex[] = {
3281 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3282 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3284 static const char *att_names_seg[] = {
3285 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3287 static const char *att_index64 = "%riz";
3288 static const char *att_index32 = "%eiz";
3289 static const char *att_index16[] = {
3290 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3293 static const char **names_mm;
3294 static const char *intel_names_mm[] = {
3295 "mm0", "mm1", "mm2", "mm3",
3296 "mm4", "mm5", "mm6", "mm7"
3298 static const char *att_names_mm[] = {
3299 "%mm0", "%mm1", "%mm2", "%mm3",
3300 "%mm4", "%mm5", "%mm6", "%mm7"
3303 static const char *intel_names_bnd[] = {
3304 "bnd0", "bnd1", "bnd2", "bnd3"
3307 static const char *att_names_bnd[] = {
3308 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3311 static const char **names_xmm;
3312 static const char *intel_names_xmm[] = {
3313 "xmm0", "xmm1", "xmm2", "xmm3",
3314 "xmm4", "xmm5", "xmm6", "xmm7",
3315 "xmm8", "xmm9", "xmm10", "xmm11",
3316 "xmm12", "xmm13", "xmm14", "xmm15",
3317 "xmm16", "xmm17", "xmm18", "xmm19",
3318 "xmm20", "xmm21", "xmm22", "xmm23",
3319 "xmm24", "xmm25", "xmm26", "xmm27",
3320 "xmm28", "xmm29", "xmm30", "xmm31"
3322 static const char *att_names_xmm[] = {
3323 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3324 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3325 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3326 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3327 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3328 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3329 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3330 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3333 static const char **names_ymm;
3334 static const char *intel_names_ymm[] = {
3335 "ymm0", "ymm1", "ymm2", "ymm3",
3336 "ymm4", "ymm5", "ymm6", "ymm7",
3337 "ymm8", "ymm9", "ymm10", "ymm11",
3338 "ymm12", "ymm13", "ymm14", "ymm15",
3339 "ymm16", "ymm17", "ymm18", "ymm19",
3340 "ymm20", "ymm21", "ymm22", "ymm23",
3341 "ymm24", "ymm25", "ymm26", "ymm27",
3342 "ymm28", "ymm29", "ymm30", "ymm31"
3344 static const char *att_names_ymm[] = {
3345 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3346 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3347 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3348 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3349 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3350 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3351 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3352 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3355 static const char **names_zmm;
3356 static const char *intel_names_zmm[] = {
3357 "zmm0", "zmm1", "zmm2", "zmm3",
3358 "zmm4", "zmm5", "zmm6", "zmm7",
3359 "zmm8", "zmm9", "zmm10", "zmm11",
3360 "zmm12", "zmm13", "zmm14", "zmm15",
3361 "zmm16", "zmm17", "zmm18", "zmm19",
3362 "zmm20", "zmm21", "zmm22", "zmm23",
3363 "zmm24", "zmm25", "zmm26", "zmm27",
3364 "zmm28", "zmm29", "zmm30", "zmm31"
3366 static const char *att_names_zmm[] = {
3367 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3368 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3369 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3370 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3371 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3372 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3373 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3374 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3377 static const char **names_mask;
3378 static const char *intel_names_mask[] = {
3379 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3381 static const char *att_names_mask[] = {
3382 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3385 static const char *names_rounding[] =
3393 static const struct dis386 reg_table[][8] = {
3396 { "addA", { Ebh1, Ib }, 0 },
3397 { "orA", { Ebh1, Ib }, 0 },
3398 { "adcA", { Ebh1, Ib }, 0 },
3399 { "sbbA", { Ebh1, Ib }, 0 },
3400 { "andA", { Ebh1, Ib }, 0 },
3401 { "subA", { Ebh1, Ib }, 0 },
3402 { "xorA", { Ebh1, Ib }, 0 },
3403 { "cmpA", { Eb, Ib }, 0 },
3407 { "addQ", { Evh1, Iv }, 0 },
3408 { "orQ", { Evh1, Iv }, 0 },
3409 { "adcQ", { Evh1, Iv }, 0 },
3410 { "sbbQ", { Evh1, Iv }, 0 },
3411 { "andQ", { Evh1, Iv }, 0 },
3412 { "subQ", { Evh1, Iv }, 0 },
3413 { "xorQ", { Evh1, Iv }, 0 },
3414 { "cmpQ", { Ev, Iv }, 0 },
3418 { "addQ", { Evh1, sIb }, 0 },
3419 { "orQ", { Evh1, sIb }, 0 },
3420 { "adcQ", { Evh1, sIb }, 0 },
3421 { "sbbQ", { Evh1, sIb }, 0 },
3422 { "andQ", { Evh1, sIb }, 0 },
3423 { "subQ", { Evh1, sIb }, 0 },
3424 { "xorQ", { Evh1, sIb }, 0 },
3425 { "cmpQ", { Ev, sIb }, 0 },
3429 { "popU", { stackEv }, 0 },
3430 { XOP_8F_TABLE (XOP_09) },
3434 { XOP_8F_TABLE (XOP_09) },
3438 { "rolA", { Eb, Ib }, 0 },
3439 { "rorA", { Eb, Ib }, 0 },
3440 { "rclA", { Eb, Ib }, 0 },
3441 { "rcrA", { Eb, Ib }, 0 },
3442 { "shlA", { Eb, Ib }, 0 },
3443 { "shrA", { Eb, Ib }, 0 },
3445 { "sarA", { Eb, Ib }, 0 },
3449 { "rolQ", { Ev, Ib }, 0 },
3450 { "rorQ", { Ev, Ib }, 0 },
3451 { "rclQ", { Ev, Ib }, 0 },
3452 { "rcrQ", { Ev, Ib }, 0 },
3453 { "shlQ", { Ev, Ib }, 0 },
3454 { "shrQ", { Ev, Ib }, 0 },
3456 { "sarQ", { Ev, Ib }, 0 },
3460 { "movA", { Ebh3, Ib }, 0 },
3467 { MOD_TABLE (MOD_C6_REG_7) },
3471 { "movQ", { Evh3, Iv }, 0 },
3478 { MOD_TABLE (MOD_C7_REG_7) },
3482 { "rolA", { Eb, I1 }, 0 },
3483 { "rorA", { Eb, I1 }, 0 },
3484 { "rclA", { Eb, I1 }, 0 },
3485 { "rcrA", { Eb, I1 }, 0 },
3486 { "shlA", { Eb, I1 }, 0 },
3487 { "shrA", { Eb, I1 }, 0 },
3489 { "sarA", { Eb, I1 }, 0 },
3493 { "rolQ", { Ev, I1 }, 0 },
3494 { "rorQ", { Ev, I1 }, 0 },
3495 { "rclQ", { Ev, I1 }, 0 },
3496 { "rcrQ", { Ev, I1 }, 0 },
3497 { "shlQ", { Ev, I1 }, 0 },
3498 { "shrQ", { Ev, I1 }, 0 },
3500 { "sarQ", { Ev, I1 }, 0 },
3504 { "rolA", { Eb, CL }, 0 },
3505 { "rorA", { Eb, CL }, 0 },
3506 { "rclA", { Eb, CL }, 0 },
3507 { "rcrA", { Eb, CL }, 0 },
3508 { "shlA", { Eb, CL }, 0 },
3509 { "shrA", { Eb, CL }, 0 },
3511 { "sarA", { Eb, CL }, 0 },
3515 { "rolQ", { Ev, CL }, 0 },
3516 { "rorQ", { Ev, CL }, 0 },
3517 { "rclQ", { Ev, CL }, 0 },
3518 { "rcrQ", { Ev, CL }, 0 },
3519 { "shlQ", { Ev, CL }, 0 },
3520 { "shrQ", { Ev, CL }, 0 },
3522 { "sarQ", { Ev, CL }, 0 },
3526 { "testA", { Eb, Ib }, 0 },
3527 { "testA", { Eb, Ib }, 0 },
3528 { "notA", { Ebh1 }, 0 },
3529 { "negA", { Ebh1 }, 0 },
3530 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
3531 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
3532 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
3533 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
3537 { "testQ", { Ev, Iv }, 0 },
3538 { "testQ", { Ev, Iv }, 0 },
3539 { "notQ", { Evh1 }, 0 },
3540 { "negQ", { Evh1 }, 0 },
3541 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
3542 { "imulQ", { Ev }, 0 },
3543 { "divQ", { Ev }, 0 },
3544 { "idivQ", { Ev }, 0 },
3548 { "incA", { Ebh1 }, 0 },
3549 { "decA", { Ebh1 }, 0 },
3553 { "incQ", { Evh1 }, 0 },
3554 { "decQ", { Evh1 }, 0 },
3555 { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3556 { MOD_TABLE (MOD_FF_REG_3) },
3557 { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3558 { MOD_TABLE (MOD_FF_REG_5) },
3559 { "pushU", { stackEv }, 0 },
3564 { "sldtD", { Sv }, 0 },
3565 { "strD", { Sv }, 0 },
3566 { "lldt", { Ew }, 0 },
3567 { "ltr", { Ew }, 0 },
3568 { "verr", { Ew }, 0 },
3569 { "verw", { Ew }, 0 },
3575 { MOD_TABLE (MOD_0F01_REG_0) },
3576 { MOD_TABLE (MOD_0F01_REG_1) },
3577 { MOD_TABLE (MOD_0F01_REG_2) },
3578 { MOD_TABLE (MOD_0F01_REG_3) },
3579 { "smswD", { Sv }, 0 },
3580 { MOD_TABLE (MOD_0F01_REG_5) },
3581 { "lmsw", { Ew }, 0 },
3582 { MOD_TABLE (MOD_0F01_REG_7) },
3586 { "prefetch", { Mb }, 0 },
3587 { "prefetchw", { Mb }, 0 },
3588 { "prefetchwt1", { Mb }, 0 },
3589 { "prefetch", { Mb }, 0 },
3590 { "prefetch", { Mb }, 0 },
3591 { "prefetch", { Mb }, 0 },
3592 { "prefetch", { Mb }, 0 },
3593 { "prefetch", { Mb }, 0 },
3597 { MOD_TABLE (MOD_0F18_REG_0) },
3598 { MOD_TABLE (MOD_0F18_REG_1) },
3599 { MOD_TABLE (MOD_0F18_REG_2) },
3600 { MOD_TABLE (MOD_0F18_REG_3) },
3601 { MOD_TABLE (MOD_0F18_REG_4) },
3602 { MOD_TABLE (MOD_0F18_REG_5) },
3603 { MOD_TABLE (MOD_0F18_REG_6) },
3604 { MOD_TABLE (MOD_0F18_REG_7) },
3606 /* REG_0F1E_MOD_3 */
3608 { "nopQ", { Ev }, 0 },
3609 { "rdsspK", { Rdq }, PREFIX_OPCODE },
3610 { "nopQ", { Ev }, 0 },
3611 { "nopQ", { Ev }, 0 },
3612 { "nopQ", { Ev }, 0 },
3613 { "nopQ", { Ev }, 0 },
3614 { "nopQ", { Ev }, 0 },
3615 { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3621 { MOD_TABLE (MOD_0F71_REG_2) },
3623 { MOD_TABLE (MOD_0F71_REG_4) },
3625 { MOD_TABLE (MOD_0F71_REG_6) },
3631 { MOD_TABLE (MOD_0F72_REG_2) },
3633 { MOD_TABLE (MOD_0F72_REG_4) },
3635 { MOD_TABLE (MOD_0F72_REG_6) },
3641 { MOD_TABLE (MOD_0F73_REG_2) },
3642 { MOD_TABLE (MOD_0F73_REG_3) },
3645 { MOD_TABLE (MOD_0F73_REG_6) },
3646 { MOD_TABLE (MOD_0F73_REG_7) },
3650 { "montmul", { { OP_0f07, 0 } }, 0 },
3651 { "xsha1", { { OP_0f07, 0 } }, 0 },
3652 { "xsha256", { { OP_0f07, 0 } }, 0 },
3656 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
3657 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
3658 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
3659 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
3660 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
3661 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
3665 { MOD_TABLE (MOD_0FAE_REG_0) },
3666 { MOD_TABLE (MOD_0FAE_REG_1) },
3667 { MOD_TABLE (MOD_0FAE_REG_2) },
3668 { MOD_TABLE (MOD_0FAE_REG_3) },
3669 { MOD_TABLE (MOD_0FAE_REG_4) },
3670 { MOD_TABLE (MOD_0FAE_REG_5) },
3671 { MOD_TABLE (MOD_0FAE_REG_6) },
3672 { MOD_TABLE (MOD_0FAE_REG_7) },
3680 { "btQ", { Ev, Ib }, 0 },
3681 { "btsQ", { Evh1, Ib }, 0 },
3682 { "btrQ", { Evh1, Ib }, 0 },
3683 { "btcQ", { Evh1, Ib }, 0 },
3688 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3690 { MOD_TABLE (MOD_0FC7_REG_3) },
3691 { MOD_TABLE (MOD_0FC7_REG_4) },
3692 { MOD_TABLE (MOD_0FC7_REG_5) },
3693 { MOD_TABLE (MOD_0FC7_REG_6) },
3694 { MOD_TABLE (MOD_0FC7_REG_7) },
3700 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3702 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3704 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3710 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3712 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3714 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3720 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3721 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3724 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3725 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3731 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3732 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3734 /* REG_VEX_0F38F3 */
3737 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3738 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3739 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3743 { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3744 { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3748 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3749 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3751 /* REG_XOP_TBM_01 */
3754 { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3755 { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3756 { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 },
3757 { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3758 { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 },
3759 { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 },
3760 { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3762 /* REG_XOP_TBM_02 */
3765 { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3770 { "blci", { { OP_LWP_E, 0 }, Ev }, 0 },
3772 #define NEED_REG_TABLE
3773 #include "i386-dis-evex.h"
3774 #undef NEED_REG_TABLE
3777 static const struct dis386 prefix_table[][4] = {
3780 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3781 { "pause", { XX }, 0 },
3782 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3783 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3786 /* PREFIX_MOD_0_0F01_REG_5 */
3789 { "rstorssp", { Mq }, PREFIX_OPCODE },
3792 /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3795 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3798 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3801 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3806 { "movups", { XM, EXx }, PREFIX_OPCODE },
3807 { "movss", { XM, EXd }, PREFIX_OPCODE },
3808 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3809 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3814 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3815 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3816 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3817 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3822 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3823 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3824 { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3825 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3830 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3831 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3832 { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3837 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3838 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3839 { "bndmov", { Gbnd, Ebnd }, 0 },
3840 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3845 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3846 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3847 { "bndmov", { Ebnd, Gbnd }, 0 },
3848 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3853 { "nopQ", { Ev }, PREFIX_OPCODE },
3854 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3855 { "nopQ", { Ev }, PREFIX_OPCODE },
3856 { "nopQ", { Ev }, PREFIX_OPCODE },
3861 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3862 { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3863 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3864 { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3869 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3870 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3871 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3872 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3877 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3878 { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3879 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3880 { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3885 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3886 { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3887 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3888 { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3893 { "ucomiss",{ XM, EXd }, 0 },
3895 { "ucomisd",{ XM, EXq }, 0 },
3900 { "comiss", { XM, EXd }, 0 },
3902 { "comisd", { XM, EXq }, 0 },
3907 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3908 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3909 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3910 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3915 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3916 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3921 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3922 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3927 { "addps", { XM, EXx }, PREFIX_OPCODE },
3928 { "addss", { XM, EXd }, PREFIX_OPCODE },
3929 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3930 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3935 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3936 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3937 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3938 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3943 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3944 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3945 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3946 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3951 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3952 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3953 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3958 { "subps", { XM, EXx }, PREFIX_OPCODE },
3959 { "subss", { XM, EXd }, PREFIX_OPCODE },
3960 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3961 { "subsd", { XM, EXq }, PREFIX_OPCODE },
3966 { "minps", { XM, EXx }, PREFIX_OPCODE },
3967 { "minss", { XM, EXd }, PREFIX_OPCODE },
3968 { "minpd", { XM, EXx }, PREFIX_OPCODE },
3969 { "minsd", { XM, EXq }, PREFIX_OPCODE },
3974 { "divps", { XM, EXx }, PREFIX_OPCODE },
3975 { "divss", { XM, EXd }, PREFIX_OPCODE },
3976 { "divpd", { XM, EXx }, PREFIX_OPCODE },
3977 { "divsd", { XM, EXq }, PREFIX_OPCODE },
3982 { "maxps", { XM, EXx }, PREFIX_OPCODE },
3983 { "maxss", { XM, EXd }, PREFIX_OPCODE },
3984 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
3985 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
3990 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3992 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3997 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3999 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
4004 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
4006 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
4013 { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
4020 { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
4025 { "movq", { MX, EM }, PREFIX_OPCODE },
4026 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
4027 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4032 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4033 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4034 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4035 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4038 /* PREFIX_0F73_REG_3 */
4042 { "psrldq", { XS, Ib }, 0 },
4045 /* PREFIX_0F73_REG_7 */
4049 { "pslldq", { XS, Ib }, 0 },
4054 {"vmread", { Em, Gm }, 0 },
4056 {"extrq", { XS, Ib, Ib }, 0 },
4057 {"insertq", { XM, XS, Ib, Ib }, 0 },
4062 {"vmwrite", { Gm, Em }, 0 },
4064 {"extrq", { XM, XS }, 0 },
4065 {"insertq", { XM, XS }, 0 },
4072 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4073 { "haddps", { XM, EXx }, PREFIX_OPCODE },
4080 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4081 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4086 { "movK", { Edq, MX }, PREFIX_OPCODE },
4087 { "movq", { XM, EXq }, PREFIX_OPCODE },
4088 { "movK", { Edq, XM }, PREFIX_OPCODE },
4093 { "movq", { EMS, MX }, PREFIX_OPCODE },
4094 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4095 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4098 /* PREFIX_0FAE_REG_0 */
4101 { "rdfsbase", { Ev }, 0 },
4104 /* PREFIX_0FAE_REG_1 */
4107 { "rdgsbase", { Ev }, 0 },
4110 /* PREFIX_0FAE_REG_2 */
4113 { "wrfsbase", { Ev }, 0 },
4116 /* PREFIX_0FAE_REG_3 */
4119 { "wrgsbase", { Ev }, 0 },
4122 /* PREFIX_MOD_0_0FAE_REG_4 */
4124 { "xsave", { FXSAVE }, 0 },
4125 { "ptwrite%LQ", { Edq }, 0 },
4128 /* PREFIX_MOD_3_0FAE_REG_4 */
4131 { "ptwrite%LQ", { Edq }, 0 },
4134 /* PREFIX_MOD_0_0FAE_REG_5 */
4136 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
4139 /* PREFIX_MOD_3_0FAE_REG_5 */
4141 { "lfence", { Skip_MODRM }, 0 },
4142 { "incsspK", { Rdq }, PREFIX_OPCODE },
4145 /* PREFIX_0FAE_REG_6 */
4147 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
4148 { "clrssbsy", { Mq }, PREFIX_OPCODE },
4149 { "clwb", { Mb }, PREFIX_OPCODE },
4152 /* PREFIX_0FAE_REG_7 */
4154 { "clflush", { Mb }, 0 },
4156 { "clflushopt", { Mb }, 0 },
4162 { "popcntS", { Gv, Ev }, 0 },
4167 { "bsfS", { Gv, Ev }, 0 },
4168 { "tzcntS", { Gv, Ev }, 0 },
4169 { "bsfS", { Gv, Ev }, 0 },
4174 { "bsrS", { Gv, Ev }, 0 },
4175 { "lzcntS", { Gv, Ev }, 0 },
4176 { "bsrS", { Gv, Ev }, 0 },
4181 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
4182 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
4183 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
4184 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
4187 /* PREFIX_MOD_0_0FC3 */
4189 { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4192 /* PREFIX_MOD_0_0FC7_REG_6 */
4194 { "vmptrld",{ Mq }, 0 },
4195 { "vmxon", { Mq }, 0 },
4196 { "vmclear",{ Mq }, 0 },
4199 /* PREFIX_MOD_3_0FC7_REG_6 */
4201 { "rdrand", { Ev }, 0 },
4203 { "rdrand", { Ev }, 0 }
4206 /* PREFIX_MOD_3_0FC7_REG_7 */
4208 { "rdseed", { Ev }, 0 },
4209 { "rdpid", { Em }, 0 },
4210 { "rdseed", { Ev }, 0 },
4217 { "addsubpd", { XM, EXx }, 0 },
4218 { "addsubps", { XM, EXx }, 0 },
4224 { "movq2dq",{ XM, MS }, 0 },
4225 { "movq", { EXqS, XM }, 0 },
4226 { "movdq2q",{ MX, XS }, 0 },
4232 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4233 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4234 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4239 { "movntq", { Mq, MX }, PREFIX_OPCODE },
4241 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4249 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4254 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4256 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4263 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4270 { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4277 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4284 { "ptest", { XM, EXx }, PREFIX_OPCODE },
4291 { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4298 { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4305 { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4312 { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4319 { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4326 { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4333 { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4340 { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4347 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4354 { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4361 { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4368 { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4375 { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4382 { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4389 { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4396 { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4403 { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4410 { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4417 { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4424 { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4431 { "pminud", { XM, EXx }, PREFIX_OPCODE },
4438 { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4445 { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4452 { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4459 { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4466 { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4473 { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4480 { "invept", { Gm, Mo }, PREFIX_OPCODE },
4487 { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4494 { "invpcid", { Gm, M }, PREFIX_OPCODE },
4499 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4504 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4509 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4514 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4519 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4524 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4531 { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4538 { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4545 { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4552 { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4559 { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4564 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4566 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4567 { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4572 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4574 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4575 { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4582 { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4587 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4588 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
4589 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
4597 { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4604 { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4611 { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4618 { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4625 { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4632 { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4639 { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4646 { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4653 { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4660 { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4667 { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4674 { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4681 { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4688 { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4695 { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE },
4702 { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE },
4709 { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4716 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4723 { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4730 { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4737 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4744 { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4749 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4756 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4759 /* PREFIX_VEX_0F10 */
4761 { VEX_W_TABLE (VEX_W_0F10_P_0) },
4762 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4763 { VEX_W_TABLE (VEX_W_0F10_P_2) },
4764 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4767 /* PREFIX_VEX_0F11 */
4769 { VEX_W_TABLE (VEX_W_0F11_P_0) },
4770 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4771 { VEX_W_TABLE (VEX_W_0F11_P_2) },
4772 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4775 /* PREFIX_VEX_0F12 */
4777 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4778 { VEX_W_TABLE (VEX_W_0F12_P_1) },
4779 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4780 { VEX_W_TABLE (VEX_W_0F12_P_3) },
4783 /* PREFIX_VEX_0F16 */
4785 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4786 { VEX_W_TABLE (VEX_W_0F16_P_1) },
4787 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4790 /* PREFIX_VEX_0F2A */
4793 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4795 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4798 /* PREFIX_VEX_0F2C */
4801 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4803 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4806 /* PREFIX_VEX_0F2D */
4809 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4811 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4814 /* PREFIX_VEX_0F2E */
4816 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4818 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4821 /* PREFIX_VEX_0F2F */
4823 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4825 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4828 /* PREFIX_VEX_0F41 */
4830 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4832 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4835 /* PREFIX_VEX_0F42 */
4837 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4839 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4842 /* PREFIX_VEX_0F44 */
4844 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4846 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4849 /* PREFIX_VEX_0F45 */
4851 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4853 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4856 /* PREFIX_VEX_0F46 */
4858 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4860 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4863 /* PREFIX_VEX_0F47 */
4865 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4867 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4870 /* PREFIX_VEX_0F4A */
4872 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4874 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4877 /* PREFIX_VEX_0F4B */
4879 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4881 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4884 /* PREFIX_VEX_0F51 */
4886 { VEX_W_TABLE (VEX_W_0F51_P_0) },
4887 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4888 { VEX_W_TABLE (VEX_W_0F51_P_2) },
4889 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4892 /* PREFIX_VEX_0F52 */
4894 { VEX_W_TABLE (VEX_W_0F52_P_0) },
4895 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4898 /* PREFIX_VEX_0F53 */
4900 { VEX_W_TABLE (VEX_W_0F53_P_0) },
4901 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4904 /* PREFIX_VEX_0F58 */
4906 { VEX_W_TABLE (VEX_W_0F58_P_0) },
4907 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4908 { VEX_W_TABLE (VEX_W_0F58_P_2) },
4909 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4912 /* PREFIX_VEX_0F59 */
4914 { VEX_W_TABLE (VEX_W_0F59_P_0) },
4915 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4916 { VEX_W_TABLE (VEX_W_0F59_P_2) },
4917 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4920 /* PREFIX_VEX_0F5A */
4922 { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4923 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4924 { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4925 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4928 /* PREFIX_VEX_0F5B */
4930 { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4931 { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4932 { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4935 /* PREFIX_VEX_0F5C */
4937 { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4938 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4939 { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4940 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4943 /* PREFIX_VEX_0F5D */
4945 { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4946 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4947 { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4948 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4951 /* PREFIX_VEX_0F5E */
4953 { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4954 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4955 { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4956 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4959 /* PREFIX_VEX_0F5F */
4961 { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4962 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4963 { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4964 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4967 /* PREFIX_VEX_0F60 */
4971 { VEX_W_TABLE (VEX_W_0F60_P_2) },
4974 /* PREFIX_VEX_0F61 */
4978 { VEX_W_TABLE (VEX_W_0F61_P_2) },
4981 /* PREFIX_VEX_0F62 */
4985 { VEX_W_TABLE (VEX_W_0F62_P_2) },
4988 /* PREFIX_VEX_0F63 */
4992 { VEX_W_TABLE (VEX_W_0F63_P_2) },
4995 /* PREFIX_VEX_0F64 */
4999 { VEX_W_TABLE (VEX_W_0F64_P_2) },
5002 /* PREFIX_VEX_0F65 */
5006 { VEX_W_TABLE (VEX_W_0F65_P_2) },
5009 /* PREFIX_VEX_0F66 */
5013 { VEX_W_TABLE (VEX_W_0F66_P_2) },
5016 /* PREFIX_VEX_0F67 */
5020 { VEX_W_TABLE (VEX_W_0F67_P_2) },
5023 /* PREFIX_VEX_0F68 */
5027 { VEX_W_TABLE (VEX_W_0F68_P_2) },
5030 /* PREFIX_VEX_0F69 */
5034 { VEX_W_TABLE (VEX_W_0F69_P_2) },
5037 /* PREFIX_VEX_0F6A */
5041 { VEX_W_TABLE (VEX_W_0F6A_P_2) },
5044 /* PREFIX_VEX_0F6B */
5048 { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5051 /* PREFIX_VEX_0F6C */
5055 { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5058 /* PREFIX_VEX_0F6D */
5062 { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5065 /* PREFIX_VEX_0F6E */
5069 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5072 /* PREFIX_VEX_0F6F */
5075 { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5076 { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5079 /* PREFIX_VEX_0F70 */
5082 { VEX_W_TABLE (VEX_W_0F70_P_1) },
5083 { VEX_W_TABLE (VEX_W_0F70_P_2) },
5084 { VEX_W_TABLE (VEX_W_0F70_P_3) },
5087 /* PREFIX_VEX_0F71_REG_2 */
5091 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5094 /* PREFIX_VEX_0F71_REG_4 */
5098 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5101 /* PREFIX_VEX_0F71_REG_6 */
5105 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5108 /* PREFIX_VEX_0F72_REG_2 */
5112 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5115 /* PREFIX_VEX_0F72_REG_4 */
5119 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5122 /* PREFIX_VEX_0F72_REG_6 */
5126 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5129 /* PREFIX_VEX_0F73_REG_2 */
5133 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5136 /* PREFIX_VEX_0F73_REG_3 */
5140 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5143 /* PREFIX_VEX_0F73_REG_6 */
5147 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5150 /* PREFIX_VEX_0F73_REG_7 */
5154 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5157 /* PREFIX_VEX_0F74 */
5161 { VEX_W_TABLE (VEX_W_0F74_P_2) },
5164 /* PREFIX_VEX_0F75 */
5168 { VEX_W_TABLE (VEX_W_0F75_P_2) },
5171 /* PREFIX_VEX_0F76 */
5175 { VEX_W_TABLE (VEX_W_0F76_P_2) },
5178 /* PREFIX_VEX_0F77 */
5180 { VEX_W_TABLE (VEX_W_0F77_P_0) },
5183 /* PREFIX_VEX_0F7C */
5187 { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5188 { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5191 /* PREFIX_VEX_0F7D */
5195 { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5196 { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5199 /* PREFIX_VEX_0F7E */
5202 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5203 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5206 /* PREFIX_VEX_0F7F */
5209 { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5210 { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5213 /* PREFIX_VEX_0F90 */
5215 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5217 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5220 /* PREFIX_VEX_0F91 */
5222 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5224 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5227 /* PREFIX_VEX_0F92 */
5229 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5231 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5232 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5235 /* PREFIX_VEX_0F93 */
5237 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5239 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5240 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5243 /* PREFIX_VEX_0F98 */
5245 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5247 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5250 /* PREFIX_VEX_0F99 */
5252 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5254 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5257 /* PREFIX_VEX_0FC2 */
5259 { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5260 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5261 { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5262 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5265 /* PREFIX_VEX_0FC4 */
5269 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5272 /* PREFIX_VEX_0FC5 */
5276 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5279 /* PREFIX_VEX_0FD0 */
5283 { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5284 { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5287 /* PREFIX_VEX_0FD1 */
5291 { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5294 /* PREFIX_VEX_0FD2 */
5298 { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5301 /* PREFIX_VEX_0FD3 */
5305 { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5308 /* PREFIX_VEX_0FD4 */
5312 { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5315 /* PREFIX_VEX_0FD5 */
5319 { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5322 /* PREFIX_VEX_0FD6 */
5326 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5329 /* PREFIX_VEX_0FD7 */
5333 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5336 /* PREFIX_VEX_0FD8 */
5340 { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5343 /* PREFIX_VEX_0FD9 */
5347 { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5350 /* PREFIX_VEX_0FDA */
5354 { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5357 /* PREFIX_VEX_0FDB */
5361 { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5364 /* PREFIX_VEX_0FDC */
5368 { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5371 /* PREFIX_VEX_0FDD */
5375 { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5378 /* PREFIX_VEX_0FDE */
5382 { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5385 /* PREFIX_VEX_0FDF */
5389 { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5392 /* PREFIX_VEX_0FE0 */
5396 { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5399 /* PREFIX_VEX_0FE1 */
5403 { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5406 /* PREFIX_VEX_0FE2 */
5410 { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5413 /* PREFIX_VEX_0FE3 */
5417 { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5420 /* PREFIX_VEX_0FE4 */
5424 { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5427 /* PREFIX_VEX_0FE5 */
5431 { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5434 /* PREFIX_VEX_0FE6 */
5437 { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5438 { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5439 { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5442 /* PREFIX_VEX_0FE7 */
5446 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5449 /* PREFIX_VEX_0FE8 */
5453 { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5456 /* PREFIX_VEX_0FE9 */
5460 { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5463 /* PREFIX_VEX_0FEA */
5467 { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5470 /* PREFIX_VEX_0FEB */
5474 { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5477 /* PREFIX_VEX_0FEC */
5481 { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5484 /* PREFIX_VEX_0FED */
5488 { VEX_W_TABLE (VEX_W_0FED_P_2) },
5491 /* PREFIX_VEX_0FEE */
5495 { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5498 /* PREFIX_VEX_0FEF */
5502 { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5505 /* PREFIX_VEX_0FF0 */
5510 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5513 /* PREFIX_VEX_0FF1 */
5517 { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5520 /* PREFIX_VEX_0FF2 */
5524 { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5527 /* PREFIX_VEX_0FF3 */
5531 { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5534 /* PREFIX_VEX_0FF4 */
5538 { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5541 /* PREFIX_VEX_0FF5 */
5545 { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5548 /* PREFIX_VEX_0FF6 */
5552 { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5555 /* PREFIX_VEX_0FF7 */
5559 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5562 /* PREFIX_VEX_0FF8 */
5566 { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5569 /* PREFIX_VEX_0FF9 */
5573 { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5576 /* PREFIX_VEX_0FFA */
5580 { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5583 /* PREFIX_VEX_0FFB */
5587 { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5590 /* PREFIX_VEX_0FFC */
5594 { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5597 /* PREFIX_VEX_0FFD */
5601 { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5604 /* PREFIX_VEX_0FFE */
5608 { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5611 /* PREFIX_VEX_0F3800 */
5615 { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5618 /* PREFIX_VEX_0F3801 */
5622 { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5625 /* PREFIX_VEX_0F3802 */
5629 { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5632 /* PREFIX_VEX_0F3803 */
5636 { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5639 /* PREFIX_VEX_0F3804 */
5643 { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5646 /* PREFIX_VEX_0F3805 */
5650 { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5653 /* PREFIX_VEX_0F3806 */
5657 { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5660 /* PREFIX_VEX_0F3807 */
5664 { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5667 /* PREFIX_VEX_0F3808 */
5671 { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5674 /* PREFIX_VEX_0F3809 */
5678 { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5681 /* PREFIX_VEX_0F380A */
5685 { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5688 /* PREFIX_VEX_0F380B */
5692 { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5695 /* PREFIX_VEX_0F380C */
5699 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5702 /* PREFIX_VEX_0F380D */
5706 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5709 /* PREFIX_VEX_0F380E */
5713 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5716 /* PREFIX_VEX_0F380F */
5720 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5723 /* PREFIX_VEX_0F3813 */
5727 { "vcvtph2ps", { XM, EXxmmq }, 0 },
5730 /* PREFIX_VEX_0F3816 */
5734 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5737 /* PREFIX_VEX_0F3817 */
5741 { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5744 /* PREFIX_VEX_0F3818 */
5748 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5751 /* PREFIX_VEX_0F3819 */
5755 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5758 /* PREFIX_VEX_0F381A */
5762 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5765 /* PREFIX_VEX_0F381C */
5769 { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5772 /* PREFIX_VEX_0F381D */
5776 { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5779 /* PREFIX_VEX_0F381E */
5783 { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5786 /* PREFIX_VEX_0F3820 */
5790 { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5793 /* PREFIX_VEX_0F3821 */
5797 { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5800 /* PREFIX_VEX_0F3822 */
5804 { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5807 /* PREFIX_VEX_0F3823 */
5811 { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5814 /* PREFIX_VEX_0F3824 */
5818 { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5821 /* PREFIX_VEX_0F3825 */
5825 { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5828 /* PREFIX_VEX_0F3828 */
5832 { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5835 /* PREFIX_VEX_0F3829 */
5839 { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5842 /* PREFIX_VEX_0F382A */
5846 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5849 /* PREFIX_VEX_0F382B */
5853 { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5856 /* PREFIX_VEX_0F382C */
5860 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5863 /* PREFIX_VEX_0F382D */
5867 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5870 /* PREFIX_VEX_0F382E */
5874 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5877 /* PREFIX_VEX_0F382F */
5881 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5884 /* PREFIX_VEX_0F3830 */
5888 { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5891 /* PREFIX_VEX_0F3831 */
5895 { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5898 /* PREFIX_VEX_0F3832 */
5902 { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5905 /* PREFIX_VEX_0F3833 */
5909 { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5912 /* PREFIX_VEX_0F3834 */
5916 { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5919 /* PREFIX_VEX_0F3835 */
5923 { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5926 /* PREFIX_VEX_0F3836 */
5930 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5933 /* PREFIX_VEX_0F3837 */
5937 { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5940 /* PREFIX_VEX_0F3838 */
5944 { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5947 /* PREFIX_VEX_0F3839 */
5951 { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5954 /* PREFIX_VEX_0F383A */
5958 { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5961 /* PREFIX_VEX_0F383B */
5965 { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5968 /* PREFIX_VEX_0F383C */
5972 { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5975 /* PREFIX_VEX_0F383D */
5979 { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5982 /* PREFIX_VEX_0F383E */
5986 { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5989 /* PREFIX_VEX_0F383F */
5993 { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5996 /* PREFIX_VEX_0F3840 */
6000 { VEX_W_TABLE (VEX_W_0F3840_P_2) },
6003 /* PREFIX_VEX_0F3841 */
6007 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
6010 /* PREFIX_VEX_0F3845 */
6014 { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
6017 /* PREFIX_VEX_0F3846 */
6021 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
6024 /* PREFIX_VEX_0F3847 */
6028 { "vpsllv%LW", { XM, Vex, EXx }, 0 },
6031 /* PREFIX_VEX_0F3858 */
6035 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
6038 /* PREFIX_VEX_0F3859 */
6042 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
6045 /* PREFIX_VEX_0F385A */
6049 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6052 /* PREFIX_VEX_0F3878 */
6056 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6059 /* PREFIX_VEX_0F3879 */
6063 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6066 /* PREFIX_VEX_0F388C */
6070 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6073 /* PREFIX_VEX_0F388E */
6077 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6080 /* PREFIX_VEX_0F3890 */
6084 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6087 /* PREFIX_VEX_0F3891 */
6091 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6094 /* PREFIX_VEX_0F3892 */
6098 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6101 /* PREFIX_VEX_0F3893 */
6105 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6108 /* PREFIX_VEX_0F3896 */
6112 { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6115 /* PREFIX_VEX_0F3897 */
6119 { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6122 /* PREFIX_VEX_0F3898 */
6126 { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6129 /* PREFIX_VEX_0F3899 */
6133 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6136 /* PREFIX_VEX_0F389A */
6140 { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6143 /* PREFIX_VEX_0F389B */
6147 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6150 /* PREFIX_VEX_0F389C */
6154 { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6157 /* PREFIX_VEX_0F389D */
6161 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6164 /* PREFIX_VEX_0F389E */
6168 { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6171 /* PREFIX_VEX_0F389F */
6175 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6178 /* PREFIX_VEX_0F38A6 */
6182 { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6186 /* PREFIX_VEX_0F38A7 */
6190 { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6193 /* PREFIX_VEX_0F38A8 */
6197 { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6200 /* PREFIX_VEX_0F38A9 */
6204 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6207 /* PREFIX_VEX_0F38AA */
6211 { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6214 /* PREFIX_VEX_0F38AB */
6218 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6221 /* PREFIX_VEX_0F38AC */
6225 { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6228 /* PREFIX_VEX_0F38AD */
6232 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6235 /* PREFIX_VEX_0F38AE */
6239 { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6242 /* PREFIX_VEX_0F38AF */
6246 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6249 /* PREFIX_VEX_0F38B6 */
6253 { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6256 /* PREFIX_VEX_0F38B7 */
6260 { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6263 /* PREFIX_VEX_0F38B8 */
6267 { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6270 /* PREFIX_VEX_0F38B9 */
6274 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6277 /* PREFIX_VEX_0F38BA */
6281 { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6284 /* PREFIX_VEX_0F38BB */
6288 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6291 /* PREFIX_VEX_0F38BC */
6295 { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6298 /* PREFIX_VEX_0F38BD */
6302 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6305 /* PREFIX_VEX_0F38BE */
6309 { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6312 /* PREFIX_VEX_0F38BF */
6316 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6319 /* PREFIX_VEX_0F38DB */
6323 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6326 /* PREFIX_VEX_0F38DC */
6330 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6333 /* PREFIX_VEX_0F38DD */
6337 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6340 /* PREFIX_VEX_0F38DE */
6344 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6347 /* PREFIX_VEX_0F38DF */
6351 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6354 /* PREFIX_VEX_0F38F2 */
6356 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6359 /* PREFIX_VEX_0F38F3_REG_1 */
6361 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6364 /* PREFIX_VEX_0F38F3_REG_2 */
6366 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6369 /* PREFIX_VEX_0F38F3_REG_3 */
6371 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6374 /* PREFIX_VEX_0F38F5 */
6376 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6377 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6379 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6382 /* PREFIX_VEX_0F38F6 */
6387 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6390 /* PREFIX_VEX_0F38F7 */
6392 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6393 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6394 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6395 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6398 /* PREFIX_VEX_0F3A00 */
6402 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6405 /* PREFIX_VEX_0F3A01 */
6409 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6412 /* PREFIX_VEX_0F3A02 */
6416 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6419 /* PREFIX_VEX_0F3A04 */
6423 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6426 /* PREFIX_VEX_0F3A05 */
6430 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6433 /* PREFIX_VEX_0F3A06 */
6437 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6440 /* PREFIX_VEX_0F3A08 */
6444 { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6447 /* PREFIX_VEX_0F3A09 */
6451 { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6454 /* PREFIX_VEX_0F3A0A */
6458 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6461 /* PREFIX_VEX_0F3A0B */
6465 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6468 /* PREFIX_VEX_0F3A0C */
6472 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6475 /* PREFIX_VEX_0F3A0D */
6479 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6482 /* PREFIX_VEX_0F3A0E */
6486 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6489 /* PREFIX_VEX_0F3A0F */
6493 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6496 /* PREFIX_VEX_0F3A14 */
6500 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6503 /* PREFIX_VEX_0F3A15 */
6507 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6510 /* PREFIX_VEX_0F3A16 */
6514 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6517 /* PREFIX_VEX_0F3A17 */
6521 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6524 /* PREFIX_VEX_0F3A18 */
6528 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6531 /* PREFIX_VEX_0F3A19 */
6535 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6538 /* PREFIX_VEX_0F3A1D */
6542 { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6545 /* PREFIX_VEX_0F3A20 */
6549 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6552 /* PREFIX_VEX_0F3A21 */
6556 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6559 /* PREFIX_VEX_0F3A22 */
6563 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6566 /* PREFIX_VEX_0F3A30 */
6570 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6573 /* PREFIX_VEX_0F3A31 */
6577 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6580 /* PREFIX_VEX_0F3A32 */
6584 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6587 /* PREFIX_VEX_0F3A33 */
6591 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6594 /* PREFIX_VEX_0F3A38 */
6598 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6601 /* PREFIX_VEX_0F3A39 */
6605 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6608 /* PREFIX_VEX_0F3A40 */
6612 { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6615 /* PREFIX_VEX_0F3A41 */
6619 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6622 /* PREFIX_VEX_0F3A42 */
6626 { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6629 /* PREFIX_VEX_0F3A44 */
6633 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6636 /* PREFIX_VEX_0F3A46 */
6640 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6643 /* PREFIX_VEX_0F3A48 */
6647 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6650 /* PREFIX_VEX_0F3A49 */
6654 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6657 /* PREFIX_VEX_0F3A4A */
6661 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6664 /* PREFIX_VEX_0F3A4B */
6668 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6671 /* PREFIX_VEX_0F3A4C */
6675 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6678 /* PREFIX_VEX_0F3A5C */
6682 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6685 /* PREFIX_VEX_0F3A5D */
6689 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6692 /* PREFIX_VEX_0F3A5E */
6696 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6699 /* PREFIX_VEX_0F3A5F */
6703 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6706 /* PREFIX_VEX_0F3A60 */
6710 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6714 /* PREFIX_VEX_0F3A61 */
6718 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6721 /* PREFIX_VEX_0F3A62 */
6725 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6728 /* PREFIX_VEX_0F3A63 */
6732 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6735 /* PREFIX_VEX_0F3A68 */
6739 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6742 /* PREFIX_VEX_0F3A69 */
6746 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6749 /* PREFIX_VEX_0F3A6A */
6753 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6756 /* PREFIX_VEX_0F3A6B */
6760 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6763 /* PREFIX_VEX_0F3A6C */
6767 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6770 /* PREFIX_VEX_0F3A6D */
6774 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6777 /* PREFIX_VEX_0F3A6E */
6781 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6784 /* PREFIX_VEX_0F3A6F */
6788 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6791 /* PREFIX_VEX_0F3A78 */
6795 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6798 /* PREFIX_VEX_0F3A79 */
6802 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6805 /* PREFIX_VEX_0F3A7A */
6809 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6812 /* PREFIX_VEX_0F3A7B */
6816 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6819 /* PREFIX_VEX_0F3A7C */
6823 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6827 /* PREFIX_VEX_0F3A7D */
6831 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6834 /* PREFIX_VEX_0F3A7E */
6838 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6841 /* PREFIX_VEX_0F3A7F */
6845 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6848 /* PREFIX_VEX_0F3ADF */
6852 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6855 /* PREFIX_VEX_0F3AF0 */
6860 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6863 #define NEED_PREFIX_TABLE
6864 #include "i386-dis-evex.h"
6865 #undef NEED_PREFIX_TABLE
6868 static const struct dis386 x86_64_table[][2] = {
6871 { "pushP", { es }, 0 },
6876 { "popP", { es }, 0 },
6881 { "pushP", { cs }, 0 },
6886 { "pushP", { ss }, 0 },
6891 { "popP", { ss }, 0 },
6896 { "pushP", { ds }, 0 },
6901 { "popP", { ds }, 0 },
6906 { "daa", { XX }, 0 },
6911 { "das", { XX }, 0 },
6916 { "aaa", { XX }, 0 },
6921 { "aas", { XX }, 0 },
6926 { "pushaP", { XX }, 0 },
6931 { "popaP", { XX }, 0 },
6936 { MOD_TABLE (MOD_62_32BIT) },
6937 { EVEX_TABLE (EVEX_0F) },
6942 { "arpl", { Ew, Gw }, 0 },
6943 { "movs{lq|xd}", { Gv, Ed }, 0 },
6948 { "ins{R|}", { Yzr, indirDX }, 0 },
6949 { "ins{G|}", { Yzr, indirDX }, 0 },
6954 { "outs{R|}", { indirDXr, Xz }, 0 },
6955 { "outs{G|}", { indirDXr, Xz }, 0 },
6960 /* Opcode 0x82 is an alias of of opcode 0x80 in 32-bit mode. */
6961 { REG_TABLE (REG_80) },
6966 { "Jcall{T|}", { Ap }, 0 },
6971 { MOD_TABLE (MOD_C4_32BIT) },
6972 { VEX_C4_TABLE (VEX_0F) },
6977 { MOD_TABLE (MOD_C5_32BIT) },
6978 { VEX_C5_TABLE (VEX_0F) },
6983 { "into", { XX }, 0 },
6988 { "aam", { Ib }, 0 },
6993 { "aad", { Ib }, 0 },
6998 { "callP", { Jv, BND }, 0 },
6999 { "call@", { Jv, BND }, 0 }
7004 { "jmpP", { Jv, BND }, 0 },
7005 { "jmp@", { Jv, BND }, 0 }
7010 { "Jjmp{T|}", { Ap }, 0 },
7013 /* X86_64_0F01_REG_0 */
7015 { "sgdt{Q|IQ}", { M }, 0 },
7016 { "sgdt", { M }, 0 },
7019 /* X86_64_0F01_REG_1 */
7021 { "sidt{Q|IQ}", { M }, 0 },
7022 { "sidt", { M }, 0 },
7025 /* X86_64_0F01_REG_2 */
7027 { "lgdt{Q|Q}", { M }, 0 },
7028 { "lgdt", { M }, 0 },
7031 /* X86_64_0F01_REG_3 */
7033 { "lidt{Q|Q}", { M }, 0 },
7034 { "lidt", { M }, 0 },
7038 static const struct dis386 three_byte_table[][256] = {
7040 /* THREE_BYTE_0F38 */
7043 { "pshufb", { MX, EM }, PREFIX_OPCODE },
7044 { "phaddw", { MX, EM }, PREFIX_OPCODE },
7045 { "phaddd", { MX, EM }, PREFIX_OPCODE },
7046 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
7047 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
7048 { "phsubw", { MX, EM }, PREFIX_OPCODE },
7049 { "phsubd", { MX, EM }, PREFIX_OPCODE },
7050 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
7052 { "psignb", { MX, EM }, PREFIX_OPCODE },
7053 { "psignw", { MX, EM }, PREFIX_OPCODE },
7054 { "psignd", { MX, EM }, PREFIX_OPCODE },
7055 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
7061 { PREFIX_TABLE (PREFIX_0F3810) },
7065 { PREFIX_TABLE (PREFIX_0F3814) },
7066 { PREFIX_TABLE (PREFIX_0F3815) },
7068 { PREFIX_TABLE (PREFIX_0F3817) },
7074 { "pabsb", { MX, EM }, PREFIX_OPCODE },
7075 { "pabsw", { MX, EM }, PREFIX_OPCODE },
7076 { "pabsd", { MX, EM }, PREFIX_OPCODE },
7079 { PREFIX_TABLE (PREFIX_0F3820) },
7080 { PREFIX_TABLE (PREFIX_0F3821) },
7081 { PREFIX_TABLE (PREFIX_0F3822) },
7082 { PREFIX_TABLE (PREFIX_0F3823) },
7083 { PREFIX_TABLE (PREFIX_0F3824) },
7084 { PREFIX_TABLE (PREFIX_0F3825) },
7088 { PREFIX_TABLE (PREFIX_0F3828) },
7089 { PREFIX_TABLE (PREFIX_0F3829) },
7090 { PREFIX_TABLE (PREFIX_0F382A) },
7091 { PREFIX_TABLE (PREFIX_0F382B) },
7097 { PREFIX_TABLE (PREFIX_0F3830) },
7098 { PREFIX_TABLE (PREFIX_0F3831) },
7099 { PREFIX_TABLE (PREFIX_0F3832) },
7100 { PREFIX_TABLE (PREFIX_0F3833) },
7101 { PREFIX_TABLE (PREFIX_0F3834) },
7102 { PREFIX_TABLE (PREFIX_0F3835) },
7104 { PREFIX_TABLE (PREFIX_0F3837) },
7106 { PREFIX_TABLE (PREFIX_0F3838) },
7107 { PREFIX_TABLE (PREFIX_0F3839) },
7108 { PREFIX_TABLE (PREFIX_0F383A) },
7109 { PREFIX_TABLE (PREFIX_0F383B) },
7110 { PREFIX_TABLE (PREFIX_0F383C) },
7111 { PREFIX_TABLE (PREFIX_0F383D) },
7112 { PREFIX_TABLE (PREFIX_0F383E) },
7113 { PREFIX_TABLE (PREFIX_0F383F) },
7115 { PREFIX_TABLE (PREFIX_0F3840) },
7116 { PREFIX_TABLE (PREFIX_0F3841) },
7187 { PREFIX_TABLE (PREFIX_0F3880) },
7188 { PREFIX_TABLE (PREFIX_0F3881) },
7189 { PREFIX_TABLE (PREFIX_0F3882) },
7268 { PREFIX_TABLE (PREFIX_0F38C8) },
7269 { PREFIX_TABLE (PREFIX_0F38C9) },
7270 { PREFIX_TABLE (PREFIX_0F38CA) },
7271 { PREFIX_TABLE (PREFIX_0F38CB) },
7272 { PREFIX_TABLE (PREFIX_0F38CC) },
7273 { PREFIX_TABLE (PREFIX_0F38CD) },
7289 { PREFIX_TABLE (PREFIX_0F38DB) },
7290 { PREFIX_TABLE (PREFIX_0F38DC) },
7291 { PREFIX_TABLE (PREFIX_0F38DD) },
7292 { PREFIX_TABLE (PREFIX_0F38DE) },
7293 { PREFIX_TABLE (PREFIX_0F38DF) },
7313 { PREFIX_TABLE (PREFIX_0F38F0) },
7314 { PREFIX_TABLE (PREFIX_0F38F1) },
7318 { PREFIX_TABLE (PREFIX_0F38F5) },
7319 { PREFIX_TABLE (PREFIX_0F38F6) },
7331 /* THREE_BYTE_0F3A */
7343 { PREFIX_TABLE (PREFIX_0F3A08) },
7344 { PREFIX_TABLE (PREFIX_0F3A09) },
7345 { PREFIX_TABLE (PREFIX_0F3A0A) },
7346 { PREFIX_TABLE (PREFIX_0F3A0B) },
7347 { PREFIX_TABLE (PREFIX_0F3A0C) },
7348 { PREFIX_TABLE (PREFIX_0F3A0D) },
7349 { PREFIX_TABLE (PREFIX_0F3A0E) },
7350 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
7356 { PREFIX_TABLE (PREFIX_0F3A14) },
7357 { PREFIX_TABLE (PREFIX_0F3A15) },
7358 { PREFIX_TABLE (PREFIX_0F3A16) },
7359 { PREFIX_TABLE (PREFIX_0F3A17) },
7370 { PREFIX_TABLE (PREFIX_0F3A20) },
7371 { PREFIX_TABLE (PREFIX_0F3A21) },
7372 { PREFIX_TABLE (PREFIX_0F3A22) },
7406 { PREFIX_TABLE (PREFIX_0F3A40) },
7407 { PREFIX_TABLE (PREFIX_0F3A41) },
7408 { PREFIX_TABLE (PREFIX_0F3A42) },
7410 { PREFIX_TABLE (PREFIX_0F3A44) },
7442 { PREFIX_TABLE (PREFIX_0F3A60) },
7443 { PREFIX_TABLE (PREFIX_0F3A61) },
7444 { PREFIX_TABLE (PREFIX_0F3A62) },
7445 { PREFIX_TABLE (PREFIX_0F3A63) },
7563 { PREFIX_TABLE (PREFIX_0F3ACC) },
7584 { PREFIX_TABLE (PREFIX_0F3ADF) },
7624 static const struct dis386 xop_table[][256] = {
7777 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7778 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7779 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7787 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7788 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7795 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7796 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7797 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7805 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7806 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7810 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7811 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7814 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7832 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7844 { "vprotb", { XM, Vex_2src_1, Ib }, 0 },
7845 { "vprotw", { XM, Vex_2src_1, Ib }, 0 },
7846 { "vprotd", { XM, Vex_2src_1, Ib }, 0 },
7847 { "vprotq", { XM, Vex_2src_1, Ib }, 0 },
7857 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7858 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7859 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7860 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7893 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7894 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7895 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7896 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7920 { REG_TABLE (REG_XOP_TBM_01) },
7921 { REG_TABLE (REG_XOP_TBM_02) },
7939 { REG_TABLE (REG_XOP_LWPCB) },
8063 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8064 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8065 { "vfrczss", { XM, EXd }, 0 },
8066 { "vfrczsd", { XM, EXq }, 0 },
8081 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8082 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8083 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8084 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8085 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8086 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8087 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8088 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8090 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8091 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8092 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8093 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8136 { "vphaddbw", { XM, EXxmm }, 0 },
8137 { "vphaddbd", { XM, EXxmm }, 0 },
8138 { "vphaddbq", { XM, EXxmm }, 0 },
8141 { "vphaddwd", { XM, EXxmm }, 0 },
8142 { "vphaddwq", { XM, EXxmm }, 0 },
8147 { "vphadddq", { XM, EXxmm }, 0 },
8154 { "vphaddubw", { XM, EXxmm }, 0 },
8155 { "vphaddubd", { XM, EXxmm }, 0 },
8156 { "vphaddubq", { XM, EXxmm }, 0 },
8159 { "vphadduwd", { XM, EXxmm }, 0 },
8160 { "vphadduwq", { XM, EXxmm }, 0 },
8165 { "vphaddudq", { XM, EXxmm }, 0 },
8172 { "vphsubbw", { XM, EXxmm }, 0 },
8173 { "vphsubwd", { XM, EXxmm }, 0 },
8174 { "vphsubdq", { XM, EXxmm }, 0 },
8228 { "bextr", { Gv, Ev, Iq }, 0 },
8230 { REG_TABLE (REG_XOP_LWP) },
8500 static const struct dis386 vex_table[][256] = {
8522 { PREFIX_TABLE (PREFIX_VEX_0F10) },
8523 { PREFIX_TABLE (PREFIX_VEX_0F11) },
8524 { PREFIX_TABLE (PREFIX_VEX_0F12) },
8525 { MOD_TABLE (MOD_VEX_0F13) },
8526 { VEX_W_TABLE (VEX_W_0F14) },
8527 { VEX_W_TABLE (VEX_W_0F15) },
8528 { PREFIX_TABLE (PREFIX_VEX_0F16) },
8529 { MOD_TABLE (MOD_VEX_0F17) },
8549 { VEX_W_TABLE (VEX_W_0F28) },
8550 { VEX_W_TABLE (VEX_W_0F29) },
8551 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8552 { MOD_TABLE (MOD_VEX_0F2B) },
8553 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8554 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8555 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8556 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8577 { PREFIX_TABLE (PREFIX_VEX_0F41) },
8578 { PREFIX_TABLE (PREFIX_VEX_0F42) },
8580 { PREFIX_TABLE (PREFIX_VEX_0F44) },
8581 { PREFIX_TABLE (PREFIX_VEX_0F45) },
8582 { PREFIX_TABLE (PREFIX_VEX_0F46) },
8583 { PREFIX_TABLE (PREFIX_VEX_0F47) },
8587 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8588 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8594 { MOD_TABLE (MOD_VEX_0F50) },
8595 { PREFIX_TABLE (PREFIX_VEX_0F51) },
8596 { PREFIX_TABLE (PREFIX_VEX_0F52) },
8597 { PREFIX_TABLE (PREFIX_VEX_0F53) },
8598 { "vandpX", { XM, Vex, EXx }, 0 },
8599 { "vandnpX", { XM, Vex, EXx }, 0 },
8600 { "vorpX", { XM, Vex, EXx }, 0 },
8601 { "vxorpX", { XM, Vex, EXx }, 0 },
8603 { PREFIX_TABLE (PREFIX_VEX_0F58) },
8604 { PREFIX_TABLE (PREFIX_VEX_0F59) },
8605 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8606 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8607 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8608 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8609 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8610 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8612 { PREFIX_TABLE (PREFIX_VEX_0F60) },
8613 { PREFIX_TABLE (PREFIX_VEX_0F61) },
8614 { PREFIX_TABLE (PREFIX_VEX_0F62) },
8615 { PREFIX_TABLE (PREFIX_VEX_0F63) },
8616 { PREFIX_TABLE (PREFIX_VEX_0F64) },
8617 { PREFIX_TABLE (PREFIX_VEX_0F65) },
8618 { PREFIX_TABLE (PREFIX_VEX_0F66) },
8619 { PREFIX_TABLE (PREFIX_VEX_0F67) },
8621 { PREFIX_TABLE (PREFIX_VEX_0F68) },
8622 { PREFIX_TABLE (PREFIX_VEX_0F69) },
8623 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8624 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8625 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8626 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8627 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8628 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8630 { PREFIX_TABLE (PREFIX_VEX_0F70) },
8631 { REG_TABLE (REG_VEX_0F71) },
8632 { REG_TABLE (REG_VEX_0F72) },
8633 { REG_TABLE (REG_VEX_0F73) },
8634 { PREFIX_TABLE (PREFIX_VEX_0F74) },
8635 { PREFIX_TABLE (PREFIX_VEX_0F75) },
8636 { PREFIX_TABLE (PREFIX_VEX_0F76) },
8637 { PREFIX_TABLE (PREFIX_VEX_0F77) },
8643 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8644 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8645 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8646 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8666 { PREFIX_TABLE (PREFIX_VEX_0F90) },
8667 { PREFIX_TABLE (PREFIX_VEX_0F91) },
8668 { PREFIX_TABLE (PREFIX_VEX_0F92) },
8669 { PREFIX_TABLE (PREFIX_VEX_0F93) },
8675 { PREFIX_TABLE (PREFIX_VEX_0F98) },
8676 { PREFIX_TABLE (PREFIX_VEX_0F99) },
8699 { REG_TABLE (REG_VEX_0FAE) },
8722 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8724 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8725 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8726 { "vshufpX", { XM, Vex, EXx, Ib }, 0 },
8738 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8739 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8740 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8741 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8742 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8743 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8744 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8745 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8747 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8748 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8749 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8750 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8751 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8752 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8753 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8754 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8756 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8757 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8758 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8759 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8760 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8761 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8762 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8763 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8765 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8766 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8767 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8768 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8769 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8770 { PREFIX_TABLE (PREFIX_VEX_0FED) },
8771 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8772 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8774 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8775 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8776 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8777 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8778 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8779 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8780 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8781 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8783 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8784 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8785 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8786 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8787 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8788 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8789 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8795 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8797 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8798 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8799 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8800 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8802 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8804 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8806 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8807 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8808 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8809 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8810 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8811 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8816 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8819 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8820 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8822 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8823 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8824 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8826 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8827 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8828 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8831 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8832 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8833 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8834 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8835 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8836 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8840 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8841 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8842 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8843 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8844 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8845 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8846 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8847 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8849 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8850 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8851 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8852 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8853 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8854 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8855 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8856 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8858 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8859 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8860 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8861 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8862 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8863 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8864 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8865 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8867 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8868 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8872 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8873 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8874 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8895 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8896 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8954 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8957 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8959 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8960 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8963 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8964 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8966 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8967 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8968 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8969 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8972 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8973 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8981 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8982 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8984 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8985 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8986 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8987 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8988 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8989 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8990 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8991 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8999 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9002 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9004 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9005 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9006 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9008 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9009 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9067 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9068 { REG_TABLE (REG_VEX_0F38F3) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9086 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9087 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9088 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9096 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9098 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9099 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9101 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9102 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9108 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9109 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9110 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9111 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9113 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9114 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9118 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9122 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9123 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9124 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9140 { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9141 { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9142 { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9143 { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9149 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9150 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9158 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9159 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9160 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9162 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9164 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9167 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9168 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9169 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9170 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9171 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9189 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9190 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9191 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9192 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9194 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9195 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9196 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9197 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9203 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9204 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9205 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9206 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9207 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9208 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9209 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9210 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9221 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9222 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9223 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9224 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9225 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9226 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9227 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9228 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9336 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9356 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9376 #define NEED_OPCODE_TABLE
9377 #include "i386-dis-evex.h"
9378 #undef NEED_OPCODE_TABLE
9379 static const struct dis386 vex_len_table[][2] = {
9380 /* VEX_LEN_0F10_P_1 */
9382 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9383 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9386 /* VEX_LEN_0F10_P_3 */
9388 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9389 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9392 /* VEX_LEN_0F11_P_1 */
9394 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9395 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9398 /* VEX_LEN_0F11_P_3 */
9400 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9401 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9404 /* VEX_LEN_0F12_P_0_M_0 */
9406 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9409 /* VEX_LEN_0F12_P_0_M_1 */
9411 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9414 /* VEX_LEN_0F12_P_2 */
9416 { VEX_W_TABLE (VEX_W_0F12_P_2) },
9419 /* VEX_LEN_0F13_M_0 */
9421 { VEX_W_TABLE (VEX_W_0F13_M_0) },
9424 /* VEX_LEN_0F16_P_0_M_0 */
9426 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9429 /* VEX_LEN_0F16_P_0_M_1 */
9431 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9434 /* VEX_LEN_0F16_P_2 */
9436 { VEX_W_TABLE (VEX_W_0F16_P_2) },
9439 /* VEX_LEN_0F17_M_0 */
9441 { VEX_W_TABLE (VEX_W_0F17_M_0) },
9444 /* VEX_LEN_0F2A_P_1 */
9446 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9447 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9450 /* VEX_LEN_0F2A_P_3 */
9452 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9453 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9456 /* VEX_LEN_0F2C_P_1 */
9458 { "vcvttss2siY", { Gv, EXdScalar }, 0 },
9459 { "vcvttss2siY", { Gv, EXdScalar }, 0 },
9462 /* VEX_LEN_0F2C_P_3 */
9464 { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
9465 { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
9468 /* VEX_LEN_0F2D_P_1 */
9470 { "vcvtss2siY", { Gv, EXdScalar }, 0 },
9471 { "vcvtss2siY", { Gv, EXdScalar }, 0 },
9474 /* VEX_LEN_0F2D_P_3 */
9476 { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
9477 { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
9480 /* VEX_LEN_0F2E_P_0 */
9482 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9483 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9486 /* VEX_LEN_0F2E_P_2 */
9488 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9489 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9492 /* VEX_LEN_0F2F_P_0 */
9494 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9495 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9498 /* VEX_LEN_0F2F_P_2 */
9500 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9501 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9504 /* VEX_LEN_0F41_P_0 */
9507 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9509 /* VEX_LEN_0F41_P_2 */
9512 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9514 /* VEX_LEN_0F42_P_0 */
9517 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9519 /* VEX_LEN_0F42_P_2 */
9522 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9524 /* VEX_LEN_0F44_P_0 */
9526 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9528 /* VEX_LEN_0F44_P_2 */
9530 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9532 /* VEX_LEN_0F45_P_0 */
9535 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9537 /* VEX_LEN_0F45_P_2 */
9540 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9542 /* VEX_LEN_0F46_P_0 */
9545 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9547 /* VEX_LEN_0F46_P_2 */
9550 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9552 /* VEX_LEN_0F47_P_0 */
9555 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9557 /* VEX_LEN_0F47_P_2 */
9560 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9562 /* VEX_LEN_0F4A_P_0 */
9565 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9567 /* VEX_LEN_0F4A_P_2 */
9570 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9572 /* VEX_LEN_0F4B_P_0 */
9575 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9577 /* VEX_LEN_0F4B_P_2 */
9580 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9583 /* VEX_LEN_0F51_P_1 */
9585 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9586 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9589 /* VEX_LEN_0F51_P_3 */
9591 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9592 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9595 /* VEX_LEN_0F52_P_1 */
9597 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9598 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9601 /* VEX_LEN_0F53_P_1 */
9603 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9604 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9607 /* VEX_LEN_0F58_P_1 */
9609 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9610 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9613 /* VEX_LEN_0F58_P_3 */
9615 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9616 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9619 /* VEX_LEN_0F59_P_1 */
9621 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9622 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9625 /* VEX_LEN_0F59_P_3 */
9627 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9628 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9631 /* VEX_LEN_0F5A_P_1 */
9633 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9634 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9637 /* VEX_LEN_0F5A_P_3 */
9639 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9640 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9643 /* VEX_LEN_0F5C_P_1 */
9645 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9646 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9649 /* VEX_LEN_0F5C_P_3 */
9651 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9652 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9655 /* VEX_LEN_0F5D_P_1 */
9657 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9658 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9661 /* VEX_LEN_0F5D_P_3 */
9663 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9664 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9667 /* VEX_LEN_0F5E_P_1 */
9669 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9670 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9673 /* VEX_LEN_0F5E_P_3 */
9675 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9676 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9679 /* VEX_LEN_0F5F_P_1 */
9681 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9682 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9685 /* VEX_LEN_0F5F_P_3 */
9687 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9688 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9691 /* VEX_LEN_0F6E_P_2 */
9693 { "vmovK", { XMScalar, Edq }, 0 },
9694 { "vmovK", { XMScalar, Edq }, 0 },
9697 /* VEX_LEN_0F7E_P_1 */
9699 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9700 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9703 /* VEX_LEN_0F7E_P_2 */
9705 { "vmovK", { Edq, XMScalar }, 0 },
9706 { "vmovK", { Edq, XMScalar }, 0 },
9709 /* VEX_LEN_0F90_P_0 */
9711 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9714 /* VEX_LEN_0F90_P_2 */
9716 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9719 /* VEX_LEN_0F91_P_0 */
9721 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9724 /* VEX_LEN_0F91_P_2 */
9726 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9729 /* VEX_LEN_0F92_P_0 */
9731 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9734 /* VEX_LEN_0F92_P_2 */
9736 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9739 /* VEX_LEN_0F92_P_3 */
9741 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9744 /* VEX_LEN_0F93_P_0 */
9746 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9749 /* VEX_LEN_0F93_P_2 */
9751 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9754 /* VEX_LEN_0F93_P_3 */
9756 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9759 /* VEX_LEN_0F98_P_0 */
9761 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9764 /* VEX_LEN_0F98_P_2 */
9766 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9769 /* VEX_LEN_0F99_P_0 */
9771 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9774 /* VEX_LEN_0F99_P_2 */
9776 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9779 /* VEX_LEN_0FAE_R_2_M_0 */
9781 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9784 /* VEX_LEN_0FAE_R_3_M_0 */
9786 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9789 /* VEX_LEN_0FC2_P_1 */
9791 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9792 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9795 /* VEX_LEN_0FC2_P_3 */
9797 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9798 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9801 /* VEX_LEN_0FC4_P_2 */
9803 { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9806 /* VEX_LEN_0FC5_P_2 */
9808 { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9811 /* VEX_LEN_0FD6_P_2 */
9813 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9814 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9817 /* VEX_LEN_0FF7_P_2 */
9819 { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9822 /* VEX_LEN_0F3816_P_2 */
9825 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9828 /* VEX_LEN_0F3819_P_2 */
9831 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9834 /* VEX_LEN_0F381A_P_2_M_0 */
9837 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9840 /* VEX_LEN_0F3836_P_2 */
9843 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9846 /* VEX_LEN_0F3841_P_2 */
9848 { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9851 /* VEX_LEN_0F385A_P_2_M_0 */
9854 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9857 /* VEX_LEN_0F38DB_P_2 */
9859 { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9862 /* VEX_LEN_0F38DC_P_2 */
9864 { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9867 /* VEX_LEN_0F38DD_P_2 */
9869 { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9872 /* VEX_LEN_0F38DE_P_2 */
9874 { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9877 /* VEX_LEN_0F38DF_P_2 */
9879 { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9882 /* VEX_LEN_0F38F2_P_0 */
9884 { "andnS", { Gdq, VexGdq, Edq }, 0 },
9887 /* VEX_LEN_0F38F3_R_1_P_0 */
9889 { "blsrS", { VexGdq, Edq }, 0 },
9892 /* VEX_LEN_0F38F3_R_2_P_0 */
9894 { "blsmskS", { VexGdq, Edq }, 0 },
9897 /* VEX_LEN_0F38F3_R_3_P_0 */
9899 { "blsiS", { VexGdq, Edq }, 0 },
9902 /* VEX_LEN_0F38F5_P_0 */
9904 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
9907 /* VEX_LEN_0F38F5_P_1 */
9909 { "pextS", { Gdq, VexGdq, Edq }, 0 },
9912 /* VEX_LEN_0F38F5_P_3 */
9914 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
9917 /* VEX_LEN_0F38F6_P_3 */
9919 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
9922 /* VEX_LEN_0F38F7_P_0 */
9924 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
9927 /* VEX_LEN_0F38F7_P_1 */
9929 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
9932 /* VEX_LEN_0F38F7_P_2 */
9934 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
9937 /* VEX_LEN_0F38F7_P_3 */
9939 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
9942 /* VEX_LEN_0F3A00_P_2 */
9945 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9948 /* VEX_LEN_0F3A01_P_2 */
9951 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9954 /* VEX_LEN_0F3A06_P_2 */
9957 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9960 /* VEX_LEN_0F3A0A_P_2 */
9962 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9963 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9966 /* VEX_LEN_0F3A0B_P_2 */
9968 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9969 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9972 /* VEX_LEN_0F3A14_P_2 */
9974 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9977 /* VEX_LEN_0F3A15_P_2 */
9979 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9982 /* VEX_LEN_0F3A16_P_2 */
9984 { "vpextrK", { Edq, XM, Ib }, 0 },
9987 /* VEX_LEN_0F3A17_P_2 */
9989 { "vextractps", { Edqd, XM, Ib }, 0 },
9992 /* VEX_LEN_0F3A18_P_2 */
9995 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9998 /* VEX_LEN_0F3A19_P_2 */
10001 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10004 /* VEX_LEN_0F3A20_P_2 */
10006 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10009 /* VEX_LEN_0F3A21_P_2 */
10011 { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10014 /* VEX_LEN_0F3A22_P_2 */
10016 { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 },
10019 /* VEX_LEN_0F3A30_P_2 */
10021 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10024 /* VEX_LEN_0F3A31_P_2 */
10026 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10029 /* VEX_LEN_0F3A32_P_2 */
10031 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10034 /* VEX_LEN_0F3A33_P_2 */
10036 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10039 /* VEX_LEN_0F3A38_P_2 */
10042 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10045 /* VEX_LEN_0F3A39_P_2 */
10048 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10051 /* VEX_LEN_0F3A41_P_2 */
10053 { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10056 /* VEX_LEN_0F3A44_P_2 */
10058 { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10061 /* VEX_LEN_0F3A46_P_2 */
10064 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10067 /* VEX_LEN_0F3A60_P_2 */
10069 { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10072 /* VEX_LEN_0F3A61_P_2 */
10074 { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10077 /* VEX_LEN_0F3A62_P_2 */
10079 { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10082 /* VEX_LEN_0F3A63_P_2 */
10084 { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10087 /* VEX_LEN_0F3A6A_P_2 */
10089 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10092 /* VEX_LEN_0F3A6B_P_2 */
10094 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10097 /* VEX_LEN_0F3A6E_P_2 */
10099 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10102 /* VEX_LEN_0F3A6F_P_2 */
10104 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10107 /* VEX_LEN_0F3A7A_P_2 */
10109 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10112 /* VEX_LEN_0F3A7B_P_2 */
10114 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10117 /* VEX_LEN_0F3A7E_P_2 */
10119 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10122 /* VEX_LEN_0F3A7F_P_2 */
10124 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10127 /* VEX_LEN_0F3ADF_P_2 */
10129 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10132 /* VEX_LEN_0F3AF0_P_3 */
10134 { "rorxS", { Gdq, Edq, Ib }, 0 },
10137 /* VEX_LEN_0FXOP_08_CC */
10139 { "vpcomb", { XM, Vex128, EXx, Ib }, 0 },
10142 /* VEX_LEN_0FXOP_08_CD */
10144 { "vpcomw", { XM, Vex128, EXx, Ib }, 0 },
10147 /* VEX_LEN_0FXOP_08_CE */
10149 { "vpcomd", { XM, Vex128, EXx, Ib }, 0 },
10152 /* VEX_LEN_0FXOP_08_CF */
10154 { "vpcomq", { XM, Vex128, EXx, Ib }, 0 },
10157 /* VEX_LEN_0FXOP_08_EC */
10159 { "vpcomub", { XM, Vex128, EXx, Ib }, 0 },
10162 /* VEX_LEN_0FXOP_08_ED */
10164 { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 },
10167 /* VEX_LEN_0FXOP_08_EE */
10169 { "vpcomud", { XM, Vex128, EXx, Ib }, 0 },
10172 /* VEX_LEN_0FXOP_08_EF */
10174 { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 },
10177 /* VEX_LEN_0FXOP_09_80 */
10179 { "vfrczps", { XM, EXxmm }, 0 },
10180 { "vfrczps", { XM, EXymmq }, 0 },
10183 /* VEX_LEN_0FXOP_09_81 */
10185 { "vfrczpd", { XM, EXxmm }, 0 },
10186 { "vfrczpd", { XM, EXymmq }, 0 },
10190 static const struct dis386 vex_w_table[][2] = {
10192 /* VEX_W_0F10_P_0 */
10193 { "vmovups", { XM, EXx }, 0 },
10196 /* VEX_W_0F10_P_1 */
10197 { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
10200 /* VEX_W_0F10_P_2 */
10201 { "vmovupd", { XM, EXx }, 0 },
10204 /* VEX_W_0F10_P_3 */
10205 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
10208 /* VEX_W_0F11_P_0 */
10209 { "vmovups", { EXxS, XM }, 0 },
10212 /* VEX_W_0F11_P_1 */
10213 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10216 /* VEX_W_0F11_P_2 */
10217 { "vmovupd", { EXxS, XM }, 0 },
10220 /* VEX_W_0F11_P_3 */
10221 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10224 /* VEX_W_0F12_P_0_M_0 */
10225 { "vmovlps", { XM, Vex128, EXq }, 0 },
10228 /* VEX_W_0F12_P_0_M_1 */
10229 { "vmovhlps", { XM, Vex128, EXq }, 0 },
10232 /* VEX_W_0F12_P_1 */
10233 { "vmovsldup", { XM, EXx }, 0 },
10236 /* VEX_W_0F12_P_2 */
10237 { "vmovlpd", { XM, Vex128, EXq }, 0 },
10240 /* VEX_W_0F12_P_3 */
10241 { "vmovddup", { XM, EXymmq }, 0 },
10244 /* VEX_W_0F13_M_0 */
10245 { "vmovlpX", { EXq, XM }, 0 },
10249 { "vunpcklpX", { XM, Vex, EXx }, 0 },
10253 { "vunpckhpX", { XM, Vex, EXx }, 0 },
10256 /* VEX_W_0F16_P_0_M_0 */
10257 { "vmovhps", { XM, Vex128, EXq }, 0 },
10260 /* VEX_W_0F16_P_0_M_1 */
10261 { "vmovlhps", { XM, Vex128, EXq }, 0 },
10264 /* VEX_W_0F16_P_1 */
10265 { "vmovshdup", { XM, EXx }, 0 },
10268 /* VEX_W_0F16_P_2 */
10269 { "vmovhpd", { XM, Vex128, EXq }, 0 },
10272 /* VEX_W_0F17_M_0 */
10273 { "vmovhpX", { EXq, XM }, 0 },
10277 { "vmovapX", { XM, EXx }, 0 },
10281 { "vmovapX", { EXxS, XM }, 0 },
10284 /* VEX_W_0F2B_M_0 */
10285 { "vmovntpX", { Mx, XM }, 0 },
10288 /* VEX_W_0F2E_P_0 */
10289 { "vucomiss", { XMScalar, EXdScalar }, 0 },
10292 /* VEX_W_0F2E_P_2 */
10293 { "vucomisd", { XMScalar, EXqScalar }, 0 },
10296 /* VEX_W_0F2F_P_0 */
10297 { "vcomiss", { XMScalar, EXdScalar }, 0 },
10300 /* VEX_W_0F2F_P_2 */
10301 { "vcomisd", { XMScalar, EXqScalar }, 0 },
10304 /* VEX_W_0F41_P_0_LEN_1 */
10305 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10306 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10309 /* VEX_W_0F41_P_2_LEN_1 */
10310 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10311 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10314 /* VEX_W_0F42_P_0_LEN_1 */
10315 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10316 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10319 /* VEX_W_0F42_P_2_LEN_1 */
10320 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10321 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10324 /* VEX_W_0F44_P_0_LEN_0 */
10325 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10326 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10329 /* VEX_W_0F44_P_2_LEN_0 */
10330 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10331 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10334 /* VEX_W_0F45_P_0_LEN_1 */
10335 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10336 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10339 /* VEX_W_0F45_P_2_LEN_1 */
10340 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10341 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10344 /* VEX_W_0F46_P_0_LEN_1 */
10345 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10346 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10349 /* VEX_W_0F46_P_2_LEN_1 */
10350 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10351 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10354 /* VEX_W_0F47_P_0_LEN_1 */
10355 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10356 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10359 /* VEX_W_0F47_P_2_LEN_1 */
10360 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10361 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10364 /* VEX_W_0F4A_P_0_LEN_1 */
10365 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10366 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10369 /* VEX_W_0F4A_P_2_LEN_1 */
10370 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10371 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10374 /* VEX_W_0F4B_P_0_LEN_1 */
10375 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10376 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10379 /* VEX_W_0F4B_P_2_LEN_1 */
10380 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10383 /* VEX_W_0F50_M_0 */
10384 { "vmovmskpX", { Gdq, XS }, 0 },
10387 /* VEX_W_0F51_P_0 */
10388 { "vsqrtps", { XM, EXx }, 0 },
10391 /* VEX_W_0F51_P_1 */
10392 { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10395 /* VEX_W_0F51_P_2 */
10396 { "vsqrtpd", { XM, EXx }, 0 },
10399 /* VEX_W_0F51_P_3 */
10400 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10403 /* VEX_W_0F52_P_0 */
10404 { "vrsqrtps", { XM, EXx }, 0 },
10407 /* VEX_W_0F52_P_1 */
10408 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10411 /* VEX_W_0F53_P_0 */
10412 { "vrcpps", { XM, EXx }, 0 },
10415 /* VEX_W_0F53_P_1 */
10416 { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
10419 /* VEX_W_0F58_P_0 */
10420 { "vaddps", { XM, Vex, EXx }, 0 },
10423 /* VEX_W_0F58_P_1 */
10424 { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
10427 /* VEX_W_0F58_P_2 */
10428 { "vaddpd", { XM, Vex, EXx }, 0 },
10431 /* VEX_W_0F58_P_3 */
10432 { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10435 /* VEX_W_0F59_P_0 */
10436 { "vmulps", { XM, Vex, EXx }, 0 },
10439 /* VEX_W_0F59_P_1 */
10440 { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
10443 /* VEX_W_0F59_P_2 */
10444 { "vmulpd", { XM, Vex, EXx }, 0 },
10447 /* VEX_W_0F59_P_3 */
10448 { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10451 /* VEX_W_0F5A_P_0 */
10452 { "vcvtps2pd", { XM, EXxmmq }, 0 },
10455 /* VEX_W_0F5A_P_1 */
10456 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
10459 /* VEX_W_0F5A_P_3 */
10460 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
10463 /* VEX_W_0F5B_P_0 */
10464 { "vcvtdq2ps", { XM, EXx }, 0 },
10467 /* VEX_W_0F5B_P_1 */
10468 { "vcvttps2dq", { XM, EXx }, 0 },
10471 /* VEX_W_0F5B_P_2 */
10472 { "vcvtps2dq", { XM, EXx }, 0 },
10475 /* VEX_W_0F5C_P_0 */
10476 { "vsubps", { XM, Vex, EXx }, 0 },
10479 /* VEX_W_0F5C_P_1 */
10480 { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
10483 /* VEX_W_0F5C_P_2 */
10484 { "vsubpd", { XM, Vex, EXx }, 0 },
10487 /* VEX_W_0F5C_P_3 */
10488 { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10491 /* VEX_W_0F5D_P_0 */
10492 { "vminps", { XM, Vex, EXx }, 0 },
10495 /* VEX_W_0F5D_P_1 */
10496 { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
10499 /* VEX_W_0F5D_P_2 */
10500 { "vminpd", { XM, Vex, EXx }, 0 },
10503 /* VEX_W_0F5D_P_3 */
10504 { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10507 /* VEX_W_0F5E_P_0 */
10508 { "vdivps", { XM, Vex, EXx }, 0 },
10511 /* VEX_W_0F5E_P_1 */
10512 { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
10515 /* VEX_W_0F5E_P_2 */
10516 { "vdivpd", { XM, Vex, EXx }, 0 },
10519 /* VEX_W_0F5E_P_3 */
10520 { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10523 /* VEX_W_0F5F_P_0 */
10524 { "vmaxps", { XM, Vex, EXx }, 0 },
10527 /* VEX_W_0F5F_P_1 */
10528 { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
10531 /* VEX_W_0F5F_P_2 */
10532 { "vmaxpd", { XM, Vex, EXx }, 0 },
10535 /* VEX_W_0F5F_P_3 */
10536 { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10539 /* VEX_W_0F60_P_2 */
10540 { "vpunpcklbw", { XM, Vex, EXx }, 0 },
10543 /* VEX_W_0F61_P_2 */
10544 { "vpunpcklwd", { XM, Vex, EXx }, 0 },
10547 /* VEX_W_0F62_P_2 */
10548 { "vpunpckldq", { XM, Vex, EXx }, 0 },
10551 /* VEX_W_0F63_P_2 */
10552 { "vpacksswb", { XM, Vex, EXx }, 0 },
10555 /* VEX_W_0F64_P_2 */
10556 { "vpcmpgtb", { XM, Vex, EXx }, 0 },
10559 /* VEX_W_0F65_P_2 */
10560 { "vpcmpgtw", { XM, Vex, EXx }, 0 },
10563 /* VEX_W_0F66_P_2 */
10564 { "vpcmpgtd", { XM, Vex, EXx }, 0 },
10567 /* VEX_W_0F67_P_2 */
10568 { "vpackuswb", { XM, Vex, EXx }, 0 },
10571 /* VEX_W_0F68_P_2 */
10572 { "vpunpckhbw", { XM, Vex, EXx }, 0 },
10575 /* VEX_W_0F69_P_2 */
10576 { "vpunpckhwd", { XM, Vex, EXx }, 0 },
10579 /* VEX_W_0F6A_P_2 */
10580 { "vpunpckhdq", { XM, Vex, EXx }, 0 },
10583 /* VEX_W_0F6B_P_2 */
10584 { "vpackssdw", { XM, Vex, EXx }, 0 },
10587 /* VEX_W_0F6C_P_2 */
10588 { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
10591 /* VEX_W_0F6D_P_2 */
10592 { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
10595 /* VEX_W_0F6F_P_1 */
10596 { "vmovdqu", { XM, EXx }, 0 },
10599 /* VEX_W_0F6F_P_2 */
10600 { "vmovdqa", { XM, EXx }, 0 },
10603 /* VEX_W_0F70_P_1 */
10604 { "vpshufhw", { XM, EXx, Ib }, 0 },
10607 /* VEX_W_0F70_P_2 */
10608 { "vpshufd", { XM, EXx, Ib }, 0 },
10611 /* VEX_W_0F70_P_3 */
10612 { "vpshuflw", { XM, EXx, Ib }, 0 },
10615 /* VEX_W_0F71_R_2_P_2 */
10616 { "vpsrlw", { Vex, XS, Ib }, 0 },
10619 /* VEX_W_0F71_R_4_P_2 */
10620 { "vpsraw", { Vex, XS, Ib }, 0 },
10623 /* VEX_W_0F71_R_6_P_2 */
10624 { "vpsllw", { Vex, XS, Ib }, 0 },
10627 /* VEX_W_0F72_R_2_P_2 */
10628 { "vpsrld", { Vex, XS, Ib }, 0 },
10631 /* VEX_W_0F72_R_4_P_2 */
10632 { "vpsrad", { Vex, XS, Ib }, 0 },
10635 /* VEX_W_0F72_R_6_P_2 */
10636 { "vpslld", { Vex, XS, Ib }, 0 },
10639 /* VEX_W_0F73_R_2_P_2 */
10640 { "vpsrlq", { Vex, XS, Ib }, 0 },
10643 /* VEX_W_0F73_R_3_P_2 */
10644 { "vpsrldq", { Vex, XS, Ib }, 0 },
10647 /* VEX_W_0F73_R_6_P_2 */
10648 { "vpsllq", { Vex, XS, Ib }, 0 },
10651 /* VEX_W_0F73_R_7_P_2 */
10652 { "vpslldq", { Vex, XS, Ib }, 0 },
10655 /* VEX_W_0F74_P_2 */
10656 { "vpcmpeqb", { XM, Vex, EXx }, 0 },
10659 /* VEX_W_0F75_P_2 */
10660 { "vpcmpeqw", { XM, Vex, EXx }, 0 },
10663 /* VEX_W_0F76_P_2 */
10664 { "vpcmpeqd", { XM, Vex, EXx }, 0 },
10667 /* VEX_W_0F77_P_0 */
10668 { "", { VZERO }, 0 },
10671 /* VEX_W_0F7C_P_2 */
10672 { "vhaddpd", { XM, Vex, EXx }, 0 },
10675 /* VEX_W_0F7C_P_3 */
10676 { "vhaddps", { XM, Vex, EXx }, 0 },
10679 /* VEX_W_0F7D_P_2 */
10680 { "vhsubpd", { XM, Vex, EXx }, 0 },
10683 /* VEX_W_0F7D_P_3 */
10684 { "vhsubps", { XM, Vex, EXx }, 0 },
10687 /* VEX_W_0F7E_P_1 */
10688 { "vmovq", { XMScalar, EXqScalar }, 0 },
10691 /* VEX_W_0F7F_P_1 */
10692 { "vmovdqu", { EXxS, XM }, 0 },
10695 /* VEX_W_0F7F_P_2 */
10696 { "vmovdqa", { EXxS, XM }, 0 },
10699 /* VEX_W_0F90_P_0_LEN_0 */
10700 { "kmovw", { MaskG, MaskE }, 0 },
10701 { "kmovq", { MaskG, MaskE }, 0 },
10704 /* VEX_W_0F90_P_2_LEN_0 */
10705 { "kmovb", { MaskG, MaskBDE }, 0 },
10706 { "kmovd", { MaskG, MaskBDE }, 0 },
10709 /* VEX_W_0F91_P_0_LEN_0 */
10710 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10711 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10714 /* VEX_W_0F91_P_2_LEN_0 */
10715 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10716 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10719 /* VEX_W_0F92_P_0_LEN_0 */
10720 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10723 /* VEX_W_0F92_P_2_LEN_0 */
10724 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10727 /* VEX_W_0F92_P_3_LEN_0 */
10728 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10729 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10732 /* VEX_W_0F93_P_0_LEN_0 */
10733 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10736 /* VEX_W_0F93_P_2_LEN_0 */
10737 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10740 /* VEX_W_0F93_P_3_LEN_0 */
10741 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10742 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10745 /* VEX_W_0F98_P_0_LEN_0 */
10746 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10747 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10750 /* VEX_W_0F98_P_2_LEN_0 */
10751 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10752 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10755 /* VEX_W_0F99_P_0_LEN_0 */
10756 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10757 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10760 /* VEX_W_0F99_P_2_LEN_0 */
10761 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10762 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10765 /* VEX_W_0FAE_R_2_M_0 */
10766 { "vldmxcsr", { Md }, 0 },
10769 /* VEX_W_0FAE_R_3_M_0 */
10770 { "vstmxcsr", { Md }, 0 },
10773 /* VEX_W_0FC2_P_0 */
10774 { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
10777 /* VEX_W_0FC2_P_1 */
10778 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10781 /* VEX_W_0FC2_P_2 */
10782 { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
10785 /* VEX_W_0FC2_P_3 */
10786 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10789 /* VEX_W_0FC4_P_2 */
10790 { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
10793 /* VEX_W_0FC5_P_2 */
10794 { "vpextrw", { Gdq, XS, Ib }, 0 },
10797 /* VEX_W_0FD0_P_2 */
10798 { "vaddsubpd", { XM, Vex, EXx }, 0 },
10801 /* VEX_W_0FD0_P_3 */
10802 { "vaddsubps", { XM, Vex, EXx }, 0 },
10805 /* VEX_W_0FD1_P_2 */
10806 { "vpsrlw", { XM, Vex, EXxmm }, 0 },
10809 /* VEX_W_0FD2_P_2 */
10810 { "vpsrld", { XM, Vex, EXxmm }, 0 },
10813 /* VEX_W_0FD3_P_2 */
10814 { "vpsrlq", { XM, Vex, EXxmm }, 0 },
10817 /* VEX_W_0FD4_P_2 */
10818 { "vpaddq", { XM, Vex, EXx }, 0 },
10821 /* VEX_W_0FD5_P_2 */
10822 { "vpmullw", { XM, Vex, EXx }, 0 },
10825 /* VEX_W_0FD6_P_2 */
10826 { "vmovq", { EXqScalarS, XMScalar }, 0 },
10829 /* VEX_W_0FD7_P_2_M_1 */
10830 { "vpmovmskb", { Gdq, XS }, 0 },
10833 /* VEX_W_0FD8_P_2 */
10834 { "vpsubusb", { XM, Vex, EXx }, 0 },
10837 /* VEX_W_0FD9_P_2 */
10838 { "vpsubusw", { XM, Vex, EXx }, 0 },
10841 /* VEX_W_0FDA_P_2 */
10842 { "vpminub", { XM, Vex, EXx }, 0 },
10845 /* VEX_W_0FDB_P_2 */
10846 { "vpand", { XM, Vex, EXx }, 0 },
10849 /* VEX_W_0FDC_P_2 */
10850 { "vpaddusb", { XM, Vex, EXx }, 0 },
10853 /* VEX_W_0FDD_P_2 */
10854 { "vpaddusw", { XM, Vex, EXx }, 0 },
10857 /* VEX_W_0FDE_P_2 */
10858 { "vpmaxub", { XM, Vex, EXx }, 0 },
10861 /* VEX_W_0FDF_P_2 */
10862 { "vpandn", { XM, Vex, EXx }, 0 },
10865 /* VEX_W_0FE0_P_2 */
10866 { "vpavgb", { XM, Vex, EXx }, 0 },
10869 /* VEX_W_0FE1_P_2 */
10870 { "vpsraw", { XM, Vex, EXxmm }, 0 },
10873 /* VEX_W_0FE2_P_2 */
10874 { "vpsrad", { XM, Vex, EXxmm }, 0 },
10877 /* VEX_W_0FE3_P_2 */
10878 { "vpavgw", { XM, Vex, EXx }, 0 },
10881 /* VEX_W_0FE4_P_2 */
10882 { "vpmulhuw", { XM, Vex, EXx }, 0 },
10885 /* VEX_W_0FE5_P_2 */
10886 { "vpmulhw", { XM, Vex, EXx }, 0 },
10889 /* VEX_W_0FE6_P_1 */
10890 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
10893 /* VEX_W_0FE6_P_2 */
10894 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
10897 /* VEX_W_0FE6_P_3 */
10898 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
10901 /* VEX_W_0FE7_P_2_M_0 */
10902 { "vmovntdq", { Mx, XM }, 0 },
10905 /* VEX_W_0FE8_P_2 */
10906 { "vpsubsb", { XM, Vex, EXx }, 0 },
10909 /* VEX_W_0FE9_P_2 */
10910 { "vpsubsw", { XM, Vex, EXx }, 0 },
10913 /* VEX_W_0FEA_P_2 */
10914 { "vpminsw", { XM, Vex, EXx }, 0 },
10917 /* VEX_W_0FEB_P_2 */
10918 { "vpor", { XM, Vex, EXx }, 0 },
10921 /* VEX_W_0FEC_P_2 */
10922 { "vpaddsb", { XM, Vex, EXx }, 0 },
10925 /* VEX_W_0FED_P_2 */
10926 { "vpaddsw", { XM, Vex, EXx }, 0 },
10929 /* VEX_W_0FEE_P_2 */
10930 { "vpmaxsw", { XM, Vex, EXx }, 0 },
10933 /* VEX_W_0FEF_P_2 */
10934 { "vpxor", { XM, Vex, EXx }, 0 },
10937 /* VEX_W_0FF0_P_3_M_0 */
10938 { "vlddqu", { XM, M }, 0 },
10941 /* VEX_W_0FF1_P_2 */
10942 { "vpsllw", { XM, Vex, EXxmm }, 0 },
10945 /* VEX_W_0FF2_P_2 */
10946 { "vpslld", { XM, Vex, EXxmm }, 0 },
10949 /* VEX_W_0FF3_P_2 */
10950 { "vpsllq", { XM, Vex, EXxmm }, 0 },
10953 /* VEX_W_0FF4_P_2 */
10954 { "vpmuludq", { XM, Vex, EXx }, 0 },
10957 /* VEX_W_0FF5_P_2 */
10958 { "vpmaddwd", { XM, Vex, EXx }, 0 },
10961 /* VEX_W_0FF6_P_2 */
10962 { "vpsadbw", { XM, Vex, EXx }, 0 },
10965 /* VEX_W_0FF7_P_2 */
10966 { "vmaskmovdqu", { XM, XS }, 0 },
10969 /* VEX_W_0FF8_P_2 */
10970 { "vpsubb", { XM, Vex, EXx }, 0 },
10973 /* VEX_W_0FF9_P_2 */
10974 { "vpsubw", { XM, Vex, EXx }, 0 },
10977 /* VEX_W_0FFA_P_2 */
10978 { "vpsubd", { XM, Vex, EXx }, 0 },
10981 /* VEX_W_0FFB_P_2 */
10982 { "vpsubq", { XM, Vex, EXx }, 0 },
10985 /* VEX_W_0FFC_P_2 */
10986 { "vpaddb", { XM, Vex, EXx }, 0 },
10989 /* VEX_W_0FFD_P_2 */
10990 { "vpaddw", { XM, Vex, EXx }, 0 },
10993 /* VEX_W_0FFE_P_2 */
10994 { "vpaddd", { XM, Vex, EXx }, 0 },
10997 /* VEX_W_0F3800_P_2 */
10998 { "vpshufb", { XM, Vex, EXx }, 0 },
11001 /* VEX_W_0F3801_P_2 */
11002 { "vphaddw", { XM, Vex, EXx }, 0 },
11005 /* VEX_W_0F3802_P_2 */
11006 { "vphaddd", { XM, Vex, EXx }, 0 },
11009 /* VEX_W_0F3803_P_2 */
11010 { "vphaddsw", { XM, Vex, EXx }, 0 },
11013 /* VEX_W_0F3804_P_2 */
11014 { "vpmaddubsw", { XM, Vex, EXx }, 0 },
11017 /* VEX_W_0F3805_P_2 */
11018 { "vphsubw", { XM, Vex, EXx }, 0 },
11021 /* VEX_W_0F3806_P_2 */
11022 { "vphsubd", { XM, Vex, EXx }, 0 },
11025 /* VEX_W_0F3807_P_2 */
11026 { "vphsubsw", { XM, Vex, EXx }, 0 },
11029 /* VEX_W_0F3808_P_2 */
11030 { "vpsignb", { XM, Vex, EXx }, 0 },
11033 /* VEX_W_0F3809_P_2 */
11034 { "vpsignw", { XM, Vex, EXx }, 0 },
11037 /* VEX_W_0F380A_P_2 */
11038 { "vpsignd", { XM, Vex, EXx }, 0 },
11041 /* VEX_W_0F380B_P_2 */
11042 { "vpmulhrsw", { XM, Vex, EXx }, 0 },
11045 /* VEX_W_0F380C_P_2 */
11046 { "vpermilps", { XM, Vex, EXx }, 0 },
11049 /* VEX_W_0F380D_P_2 */
11050 { "vpermilpd", { XM, Vex, EXx }, 0 },
11053 /* VEX_W_0F380E_P_2 */
11054 { "vtestps", { XM, EXx }, 0 },
11057 /* VEX_W_0F380F_P_2 */
11058 { "vtestpd", { XM, EXx }, 0 },
11061 /* VEX_W_0F3816_P_2 */
11062 { "vpermps", { XM, Vex, EXx }, 0 },
11065 /* VEX_W_0F3817_P_2 */
11066 { "vptest", { XM, EXx }, 0 },
11069 /* VEX_W_0F3818_P_2 */
11070 { "vbroadcastss", { XM, EXxmm_md }, 0 },
11073 /* VEX_W_0F3819_P_2 */
11074 { "vbroadcastsd", { XM, EXxmm_mq }, 0 },
11077 /* VEX_W_0F381A_P_2_M_0 */
11078 { "vbroadcastf128", { XM, Mxmm }, 0 },
11081 /* VEX_W_0F381C_P_2 */
11082 { "vpabsb", { XM, EXx }, 0 },
11085 /* VEX_W_0F381D_P_2 */
11086 { "vpabsw", { XM, EXx }, 0 },
11089 /* VEX_W_0F381E_P_2 */
11090 { "vpabsd", { XM, EXx }, 0 },
11093 /* VEX_W_0F3820_P_2 */
11094 { "vpmovsxbw", { XM, EXxmmq }, 0 },
11097 /* VEX_W_0F3821_P_2 */
11098 { "vpmovsxbd", { XM, EXxmmqd }, 0 },
11101 /* VEX_W_0F3822_P_2 */
11102 { "vpmovsxbq", { XM, EXxmmdw }, 0 },
11105 /* VEX_W_0F3823_P_2 */
11106 { "vpmovsxwd", { XM, EXxmmq }, 0 },
11109 /* VEX_W_0F3824_P_2 */
11110 { "vpmovsxwq", { XM, EXxmmqd }, 0 },
11113 /* VEX_W_0F3825_P_2 */
11114 { "vpmovsxdq", { XM, EXxmmq }, 0 },
11117 /* VEX_W_0F3828_P_2 */
11118 { "vpmuldq", { XM, Vex, EXx }, 0 },
11121 /* VEX_W_0F3829_P_2 */
11122 { "vpcmpeqq", { XM, Vex, EXx }, 0 },
11125 /* VEX_W_0F382A_P_2_M_0 */
11126 { "vmovntdqa", { XM, Mx }, 0 },
11129 /* VEX_W_0F382B_P_2 */
11130 { "vpackusdw", { XM, Vex, EXx }, 0 },
11133 /* VEX_W_0F382C_P_2_M_0 */
11134 { "vmaskmovps", { XM, Vex, Mx }, 0 },
11137 /* VEX_W_0F382D_P_2_M_0 */
11138 { "vmaskmovpd", { XM, Vex, Mx }, 0 },
11141 /* VEX_W_0F382E_P_2_M_0 */
11142 { "vmaskmovps", { Mx, Vex, XM }, 0 },
11145 /* VEX_W_0F382F_P_2_M_0 */
11146 { "vmaskmovpd", { Mx, Vex, XM }, 0 },
11149 /* VEX_W_0F3830_P_2 */
11150 { "vpmovzxbw", { XM, EXxmmq }, 0 },
11153 /* VEX_W_0F3831_P_2 */
11154 { "vpmovzxbd", { XM, EXxmmqd }, 0 },
11157 /* VEX_W_0F3832_P_2 */
11158 { "vpmovzxbq", { XM, EXxmmdw }, 0 },
11161 /* VEX_W_0F3833_P_2 */
11162 { "vpmovzxwd", { XM, EXxmmq }, 0 },
11165 /* VEX_W_0F3834_P_2 */
11166 { "vpmovzxwq", { XM, EXxmmqd }, 0 },
11169 /* VEX_W_0F3835_P_2 */
11170 { "vpmovzxdq", { XM, EXxmmq }, 0 },
11173 /* VEX_W_0F3836_P_2 */
11174 { "vpermd", { XM, Vex, EXx }, 0 },
11177 /* VEX_W_0F3837_P_2 */
11178 { "vpcmpgtq", { XM, Vex, EXx }, 0 },
11181 /* VEX_W_0F3838_P_2 */
11182 { "vpminsb", { XM, Vex, EXx }, 0 },
11185 /* VEX_W_0F3839_P_2 */
11186 { "vpminsd", { XM, Vex, EXx }, 0 },
11189 /* VEX_W_0F383A_P_2 */
11190 { "vpminuw", { XM, Vex, EXx }, 0 },
11193 /* VEX_W_0F383B_P_2 */
11194 { "vpminud", { XM, Vex, EXx }, 0 },
11197 /* VEX_W_0F383C_P_2 */
11198 { "vpmaxsb", { XM, Vex, EXx }, 0 },
11201 /* VEX_W_0F383D_P_2 */
11202 { "vpmaxsd", { XM, Vex, EXx }, 0 },
11205 /* VEX_W_0F383E_P_2 */
11206 { "vpmaxuw", { XM, Vex, EXx }, 0 },
11209 /* VEX_W_0F383F_P_2 */
11210 { "vpmaxud", { XM, Vex, EXx }, 0 },
11213 /* VEX_W_0F3840_P_2 */
11214 { "vpmulld", { XM, Vex, EXx }, 0 },
11217 /* VEX_W_0F3841_P_2 */
11218 { "vphminposuw", { XM, EXx }, 0 },
11221 /* VEX_W_0F3846_P_2 */
11222 { "vpsravd", { XM, Vex, EXx }, 0 },
11225 /* VEX_W_0F3858_P_2 */
11226 { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11229 /* VEX_W_0F3859_P_2 */
11230 { "vpbroadcastq", { XM, EXxmm_mq }, 0 },
11233 /* VEX_W_0F385A_P_2_M_0 */
11234 { "vbroadcasti128", { XM, Mxmm }, 0 },
11237 /* VEX_W_0F3878_P_2 */
11238 { "vpbroadcastb", { XM, EXxmm_mb }, 0 },
11241 /* VEX_W_0F3879_P_2 */
11242 { "vpbroadcastw", { XM, EXxmm_mw }, 0 },
11245 /* VEX_W_0F38DB_P_2 */
11246 { "vaesimc", { XM, EXx }, 0 },
11249 /* VEX_W_0F38DC_P_2 */
11250 { "vaesenc", { XM, Vex128, EXx }, 0 },
11253 /* VEX_W_0F38DD_P_2 */
11254 { "vaesenclast", { XM, Vex128, EXx }, 0 },
11257 /* VEX_W_0F38DE_P_2 */
11258 { "vaesdec", { XM, Vex128, EXx }, 0 },
11261 /* VEX_W_0F38DF_P_2 */
11262 { "vaesdeclast", { XM, Vex128, EXx }, 0 },
11265 /* VEX_W_0F3A00_P_2 */
11267 { "vpermq", { XM, EXx, Ib }, 0 },
11270 /* VEX_W_0F3A01_P_2 */
11272 { "vpermpd", { XM, EXx, Ib }, 0 },
11275 /* VEX_W_0F3A02_P_2 */
11276 { "vpblendd", { XM, Vex, EXx, Ib }, 0 },
11279 /* VEX_W_0F3A04_P_2 */
11280 { "vpermilps", { XM, EXx, Ib }, 0 },
11283 /* VEX_W_0F3A05_P_2 */
11284 { "vpermilpd", { XM, EXx, Ib }, 0 },
11287 /* VEX_W_0F3A06_P_2 */
11288 { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 },
11291 /* VEX_W_0F3A08_P_2 */
11292 { "vroundps", { XM, EXx, Ib }, 0 },
11295 /* VEX_W_0F3A09_P_2 */
11296 { "vroundpd", { XM, EXx, Ib }, 0 },
11299 /* VEX_W_0F3A0A_P_2 */
11300 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11303 /* VEX_W_0F3A0B_P_2 */
11304 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11307 /* VEX_W_0F3A0C_P_2 */
11308 { "vblendps", { XM, Vex, EXx, Ib }, 0 },
11311 /* VEX_W_0F3A0D_P_2 */
11312 { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
11315 /* VEX_W_0F3A0E_P_2 */
11316 { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
11319 /* VEX_W_0F3A0F_P_2 */
11320 { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
11323 /* VEX_W_0F3A14_P_2 */
11324 { "vpextrb", { Edqb, XM, Ib }, 0 },
11327 /* VEX_W_0F3A15_P_2 */
11328 { "vpextrw", { Edqw, XM, Ib }, 0 },
11331 /* VEX_W_0F3A18_P_2 */
11332 { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 },
11335 /* VEX_W_0F3A19_P_2 */
11336 { "vextractf128", { EXxmm, XM, Ib }, 0 },
11339 /* VEX_W_0F3A20_P_2 */
11340 { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
11343 /* VEX_W_0F3A21_P_2 */
11344 { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
11347 /* VEX_W_0F3A30_P_2_LEN_0 */
11348 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11349 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11352 /* VEX_W_0F3A31_P_2_LEN_0 */
11353 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11354 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11357 /* VEX_W_0F3A32_P_2_LEN_0 */
11358 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11359 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11362 /* VEX_W_0F3A33_P_2_LEN_0 */
11363 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11364 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11367 /* VEX_W_0F3A38_P_2 */
11368 { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 },
11371 /* VEX_W_0F3A39_P_2 */
11372 { "vextracti128", { EXxmm, XM, Ib }, 0 },
11375 /* VEX_W_0F3A40_P_2 */
11376 { "vdpps", { XM, Vex, EXx, Ib }, 0 },
11379 /* VEX_W_0F3A41_P_2 */
11380 { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
11383 /* VEX_W_0F3A42_P_2 */
11384 { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
11387 /* VEX_W_0F3A44_P_2 */
11388 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL }, 0 },
11391 /* VEX_W_0F3A46_P_2 */
11392 { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
11395 /* VEX_W_0F3A48_P_2 */
11396 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11397 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11400 /* VEX_W_0F3A49_P_2 */
11401 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11402 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11405 /* VEX_W_0F3A4A_P_2 */
11406 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 },
11409 /* VEX_W_0F3A4B_P_2 */
11410 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 },
11413 /* VEX_W_0F3A4C_P_2 */
11414 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
11417 /* VEX_W_0F3A62_P_2 */
11418 { "vpcmpistrm", { XM, EXx, Ib }, 0 },
11421 /* VEX_W_0F3A63_P_2 */
11422 { "vpcmpistri", { XM, EXx, Ib }, 0 },
11425 /* VEX_W_0F3ADF_P_2 */
11426 { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11428 #define NEED_VEX_W_TABLE
11429 #include "i386-dis-evex.h"
11430 #undef NEED_VEX_W_TABLE
11433 static const struct dis386 mod_table[][2] = {
11436 { "leaS", { Gv, M }, 0 },
11441 { RM_TABLE (RM_C6_REG_7) },
11446 { RM_TABLE (RM_C7_REG_7) },
11450 { "Jcall^", { indirEp }, 0 },
11454 { "Jjmp^", { indirEp }, 0 },
11457 /* MOD_0F01_REG_0 */
11458 { X86_64_TABLE (X86_64_0F01_REG_0) },
11459 { RM_TABLE (RM_0F01_REG_0) },
11462 /* MOD_0F01_REG_1 */
11463 { X86_64_TABLE (X86_64_0F01_REG_1) },
11464 { RM_TABLE (RM_0F01_REG_1) },
11467 /* MOD_0F01_REG_2 */
11468 { X86_64_TABLE (X86_64_0F01_REG_2) },
11469 { RM_TABLE (RM_0F01_REG_2) },
11472 /* MOD_0F01_REG_3 */
11473 { X86_64_TABLE (X86_64_0F01_REG_3) },
11474 { RM_TABLE (RM_0F01_REG_3) },
11477 /* MOD_0F01_REG_5 */
11478 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
11479 { RM_TABLE (RM_0F01_REG_5) },
11482 /* MOD_0F01_REG_7 */
11483 { "invlpg", { Mb }, 0 },
11484 { RM_TABLE (RM_0F01_REG_7) },
11487 /* MOD_0F12_PREFIX_0 */
11488 { "movlps", { XM, EXq }, PREFIX_OPCODE },
11489 { "movhlps", { XM, EXq }, PREFIX_OPCODE },
11493 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
11496 /* MOD_0F16_PREFIX_0 */
11497 { "movhps", { XM, EXq }, 0 },
11498 { "movlhps", { XM, EXq }, 0 },
11502 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
11505 /* MOD_0F18_REG_0 */
11506 { "prefetchnta", { Mb }, 0 },
11509 /* MOD_0F18_REG_1 */
11510 { "prefetcht0", { Mb }, 0 },
11513 /* MOD_0F18_REG_2 */
11514 { "prefetcht1", { Mb }, 0 },
11517 /* MOD_0F18_REG_3 */
11518 { "prefetcht2", { Mb }, 0 },
11521 /* MOD_0F18_REG_4 */
11522 { "nop/reserved", { Mb }, 0 },
11525 /* MOD_0F18_REG_5 */
11526 { "nop/reserved", { Mb }, 0 },
11529 /* MOD_0F18_REG_6 */
11530 { "nop/reserved", { Mb }, 0 },
11533 /* MOD_0F18_REG_7 */
11534 { "nop/reserved", { Mb }, 0 },
11537 /* MOD_0F1A_PREFIX_0 */
11538 { "bndldx", { Gbnd, Ev_bnd }, 0 },
11539 { "nopQ", { Ev }, 0 },
11542 /* MOD_0F1B_PREFIX_0 */
11543 { "bndstx", { Ev_bnd, Gbnd }, 0 },
11544 { "nopQ", { Ev }, 0 },
11547 /* MOD_0F1B_PREFIX_1 */
11548 { "bndmk", { Gbnd, Ev_bnd }, 0 },
11549 { "nopQ", { Ev }, 0 },
11552 /* MOD_0F1E_PREFIX_1 */
11553 { "nopQ", { Ev }, 0 },
11554 { REG_TABLE (REG_0F1E_MOD_3) },
11559 { "movL", { Rd, Td }, 0 },
11564 { "movL", { Td, Rd }, 0 },
11567 /* MOD_0F2B_PREFIX_0 */
11568 {"movntps", { Mx, XM }, PREFIX_OPCODE },
11571 /* MOD_0F2B_PREFIX_1 */
11572 {"movntss", { Md, XM }, PREFIX_OPCODE },
11575 /* MOD_0F2B_PREFIX_2 */
11576 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
11579 /* MOD_0F2B_PREFIX_3 */
11580 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
11585 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
11588 /* MOD_0F71_REG_2 */
11590 { "psrlw", { MS, Ib }, 0 },
11593 /* MOD_0F71_REG_4 */
11595 { "psraw", { MS, Ib }, 0 },
11598 /* MOD_0F71_REG_6 */
11600 { "psllw", { MS, Ib }, 0 },
11603 /* MOD_0F72_REG_2 */
11605 { "psrld", { MS, Ib }, 0 },
11608 /* MOD_0F72_REG_4 */
11610 { "psrad", { MS, Ib }, 0 },
11613 /* MOD_0F72_REG_6 */
11615 { "pslld", { MS, Ib }, 0 },
11618 /* MOD_0F73_REG_2 */
11620 { "psrlq", { MS, Ib }, 0 },
11623 /* MOD_0F73_REG_3 */
11625 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11628 /* MOD_0F73_REG_6 */
11630 { "psllq", { MS, Ib }, 0 },
11633 /* MOD_0F73_REG_7 */
11635 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11638 /* MOD_0FAE_REG_0 */
11639 { "fxsave", { FXSAVE }, 0 },
11640 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11643 /* MOD_0FAE_REG_1 */
11644 { "fxrstor", { FXSAVE }, 0 },
11645 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11648 /* MOD_0FAE_REG_2 */
11649 { "ldmxcsr", { Md }, 0 },
11650 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11653 /* MOD_0FAE_REG_3 */
11654 { "stmxcsr", { Md }, 0 },
11655 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11658 /* MOD_0FAE_REG_4 */
11659 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11660 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11663 /* MOD_0FAE_REG_5 */
11664 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
11665 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
11668 /* MOD_0FAE_REG_6 */
11669 { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11670 { RM_TABLE (RM_0FAE_REG_6) },
11673 /* MOD_0FAE_REG_7 */
11674 { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11675 { RM_TABLE (RM_0FAE_REG_7) },
11679 { "lssS", { Gv, Mp }, 0 },
11683 { "lfsS", { Gv, Mp }, 0 },
11687 { "lgsS", { Gv, Mp }, 0 },
11691 { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11694 /* MOD_0FC7_REG_3 */
11695 { "xrstors", { FXSAVE }, 0 },
11698 /* MOD_0FC7_REG_4 */
11699 { "xsavec", { FXSAVE }, 0 },
11702 /* MOD_0FC7_REG_5 */
11703 { "xsaves", { FXSAVE }, 0 },
11706 /* MOD_0FC7_REG_6 */
11707 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11708 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11711 /* MOD_0FC7_REG_7 */
11712 { "vmptrst", { Mq }, 0 },
11713 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11718 { "pmovmskb", { Gdq, MS }, 0 },
11721 /* MOD_0FE7_PREFIX_2 */
11722 { "movntdq", { Mx, XM }, 0 },
11725 /* MOD_0FF0_PREFIX_3 */
11726 { "lddqu", { XM, M }, 0 },
11729 /* MOD_0F382A_PREFIX_2 */
11730 { "movntdqa", { XM, Mx }, 0 },
11733 /* MOD_0F38F5_PREFIX_2 */
11734 { "wrussK", { M, Gdq }, PREFIX_OPCODE },
11737 /* MOD_0F38F6_PREFIX_0 */
11738 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
11742 { "bound{S|}", { Gv, Ma }, 0 },
11743 { EVEX_TABLE (EVEX_0F) },
11747 { "lesS", { Gv, Mp }, 0 },
11748 { VEX_C4_TABLE (VEX_0F) },
11752 { "ldsS", { Gv, Mp }, 0 },
11753 { VEX_C5_TABLE (VEX_0F) },
11756 /* MOD_VEX_0F12_PREFIX_0 */
11757 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11758 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11762 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11765 /* MOD_VEX_0F16_PREFIX_0 */
11766 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11767 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11771 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11775 { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11778 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11780 { "kandw", { MaskG, MaskVex, MaskR }, 0 },
11783 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11785 { "kandq", { MaskG, MaskVex, MaskR }, 0 },
11788 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11790 { "kandb", { MaskG, MaskVex, MaskR }, 0 },
11793 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11795 { "kandd", { MaskG, MaskVex, MaskR }, 0 },
11798 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11800 { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
11803 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11805 { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
11808 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11810 { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
11813 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11815 { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
11818 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11820 { "knotw", { MaskG, MaskR }, 0 },
11823 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11825 { "knotq", { MaskG, MaskR }, 0 },
11828 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11830 { "knotb", { MaskG, MaskR }, 0 },
11833 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11835 { "knotd", { MaskG, MaskR }, 0 },
11838 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11840 { "korw", { MaskG, MaskVex, MaskR }, 0 },
11843 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11845 { "korq", { MaskG, MaskVex, MaskR }, 0 },
11848 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11850 { "korb", { MaskG, MaskVex, MaskR }, 0 },
11853 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11855 { "kord", { MaskG, MaskVex, MaskR }, 0 },
11858 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11860 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
11863 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11865 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
11868 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11870 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
11873 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11875 { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
11878 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11880 { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
11883 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11885 { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
11888 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11890 { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
11893 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11895 { "kxord", { MaskG, MaskVex, MaskR }, 0 },
11898 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11900 { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
11903 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11905 { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
11908 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11910 { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
11913 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11915 { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
11918 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11920 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
11923 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11925 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
11928 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11930 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
11935 { VEX_W_TABLE (VEX_W_0F50_M_0) },
11938 /* MOD_VEX_0F71_REG_2 */
11940 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11943 /* MOD_VEX_0F71_REG_4 */
11945 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11948 /* MOD_VEX_0F71_REG_6 */
11950 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11953 /* MOD_VEX_0F72_REG_2 */
11955 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11958 /* MOD_VEX_0F72_REG_4 */
11960 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11963 /* MOD_VEX_0F72_REG_6 */
11965 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11968 /* MOD_VEX_0F73_REG_2 */
11970 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11973 /* MOD_VEX_0F73_REG_3 */
11975 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11978 /* MOD_VEX_0F73_REG_6 */
11980 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11983 /* MOD_VEX_0F73_REG_7 */
11985 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11988 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11989 { "kmovw", { Ew, MaskG }, 0 },
11993 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11994 { "kmovq", { Eq, MaskG }, 0 },
11998 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11999 { "kmovb", { Eb, MaskG }, 0 },
12003 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12004 { "kmovd", { Ed, MaskG }, 0 },
12008 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12010 { "kmovw", { MaskG, Rdq }, 0 },
12013 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12015 { "kmovb", { MaskG, Rdq }, 0 },
12018 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12020 { "kmovd", { MaskG, Rdq }, 0 },
12023 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12025 { "kmovq", { MaskG, Rdq }, 0 },
12028 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12030 { "kmovw", { Gdq, MaskR }, 0 },
12033 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12035 { "kmovb", { Gdq, MaskR }, 0 },
12038 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12040 { "kmovd", { Gdq, MaskR }, 0 },
12043 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12045 { "kmovq", { Gdq, MaskR }, 0 },
12048 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12050 { "kortestw", { MaskG, MaskR }, 0 },
12053 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12055 { "kortestq", { MaskG, MaskR }, 0 },
12058 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12060 { "kortestb", { MaskG, MaskR }, 0 },
12063 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12065 { "kortestd", { MaskG, MaskR }, 0 },
12068 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12070 { "ktestw", { MaskG, MaskR }, 0 },
12073 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12075 { "ktestq", { MaskG, MaskR }, 0 },
12078 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12080 { "ktestb", { MaskG, MaskR }, 0 },
12083 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12085 { "ktestd", { MaskG, MaskR }, 0 },
12088 /* MOD_VEX_0FAE_REG_2 */
12089 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12092 /* MOD_VEX_0FAE_REG_3 */
12093 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12096 /* MOD_VEX_0FD7_PREFIX_2 */
12098 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12101 /* MOD_VEX_0FE7_PREFIX_2 */
12102 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12105 /* MOD_VEX_0FF0_PREFIX_3 */
12106 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12109 /* MOD_VEX_0F381A_PREFIX_2 */
12110 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12113 /* MOD_VEX_0F382A_PREFIX_2 */
12114 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12117 /* MOD_VEX_0F382C_PREFIX_2 */
12118 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12121 /* MOD_VEX_0F382D_PREFIX_2 */
12122 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12125 /* MOD_VEX_0F382E_PREFIX_2 */
12126 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12129 /* MOD_VEX_0F382F_PREFIX_2 */
12130 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12133 /* MOD_VEX_0F385A_PREFIX_2 */
12134 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12137 /* MOD_VEX_0F388C_PREFIX_2 */
12138 { "vpmaskmov%LW", { XM, Vex, Mx }, 0 },
12141 /* MOD_VEX_0F388E_PREFIX_2 */
12142 { "vpmaskmov%LW", { Mx, Vex, XM }, 0 },
12145 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12147 { "kshiftrb", { MaskG, MaskR, Ib }, 0 },
12150 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12152 { "kshiftrw", { MaskG, MaskR, Ib }, 0 },
12155 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12157 { "kshiftrd", { MaskG, MaskR, Ib }, 0 },
12160 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12162 { "kshiftrq", { MaskG, MaskR, Ib }, 0 },
12165 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12167 { "kshiftlb", { MaskG, MaskR, Ib }, 0 },
12170 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12172 { "kshiftlw", { MaskG, MaskR, Ib }, 0 },
12175 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12177 { "kshiftld", { MaskG, MaskR, Ib }, 0 },
12180 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12182 { "kshiftlq", { MaskG, MaskR, Ib }, 0 },
12184 #define NEED_MOD_TABLE
12185 #include "i386-dis-evex.h"
12186 #undef NEED_MOD_TABLE
12189 static const struct dis386 rm_table[][8] = {
12192 { "xabort", { Skip_MODRM, Ib }, 0 },
12196 { "xbeginT", { Skip_MODRM, Jv }, 0 },
12199 /* RM_0F01_REG_0 */
12201 { "vmcall", { Skip_MODRM }, 0 },
12202 { "vmlaunch", { Skip_MODRM }, 0 },
12203 { "vmresume", { Skip_MODRM }, 0 },
12204 { "vmxoff", { Skip_MODRM }, 0 },
12207 /* RM_0F01_REG_1 */
12208 { "monitor", { { OP_Monitor, 0 } }, 0 },
12209 { "mwait", { { OP_Mwait, 0 } }, 0 },
12210 { "clac", { Skip_MODRM }, 0 },
12211 { "stac", { Skip_MODRM }, 0 },
12215 { "encls", { Skip_MODRM }, 0 },
12218 /* RM_0F01_REG_2 */
12219 { "xgetbv", { Skip_MODRM }, 0 },
12220 { "xsetbv", { Skip_MODRM }, 0 },
12223 { "vmfunc", { Skip_MODRM }, 0 },
12224 { "xend", { Skip_MODRM }, 0 },
12225 { "xtest", { Skip_MODRM }, 0 },
12226 { "enclu", { Skip_MODRM }, 0 },
12229 /* RM_0F01_REG_3 */
12230 { "vmrun", { Skip_MODRM }, 0 },
12231 { "vmmcall", { Skip_MODRM }, 0 },
12232 { "vmload", { Skip_MODRM }, 0 },
12233 { "vmsave", { Skip_MODRM }, 0 },
12234 { "stgi", { Skip_MODRM }, 0 },
12235 { "clgi", { Skip_MODRM }, 0 },
12236 { "skinit", { Skip_MODRM }, 0 },
12237 { "invlpga", { Skip_MODRM }, 0 },
12240 /* RM_0F01_REG_5 */
12241 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
12243 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
12247 { "rdpkru", { Skip_MODRM }, 0 },
12248 { "wrpkru", { Skip_MODRM }, 0 },
12251 /* RM_0F01_REG_7 */
12252 { "swapgs", { Skip_MODRM }, 0 },
12253 { "rdtscp", { Skip_MODRM }, 0 },
12254 { "monitorx", { { OP_Monitor, 0 } }, 0 },
12255 { "mwaitx", { { OP_Mwaitx, 0 } }, 0 },
12256 { "clzero", { Skip_MODRM }, 0 },
12259 /* RM_0F1E_MOD_3_REG_7 */
12260 { "nopQ", { Ev }, 0 },
12261 { "nopQ", { Ev }, 0 },
12262 { "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
12263 { "endbr32", { Skip_MODRM }, PREFIX_OPCODE },
12264 { "nopQ", { Ev }, 0 },
12265 { "nopQ", { Ev }, 0 },
12266 { "nopQ", { Ev }, 0 },
12267 { "nopQ", { Ev }, 0 },
12270 /* RM_0FAE_REG_6 */
12271 { "mfence", { Skip_MODRM }, 0 },
12274 /* RM_0FAE_REG_7 */
12275 { "sfence", { Skip_MODRM }, 0 },
12280 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12282 /* We use the high bit to indicate different name for the same
12284 #define REP_PREFIX (0xf3 | 0x100)
12285 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12286 #define XRELEASE_PREFIX (0xf3 | 0x400)
12287 #define BND_PREFIX (0xf2 | 0x400)
12288 #define NOTRACK_PREFIX (0x3e | 0x100)
12293 int newrex, i, length;
12299 last_lock_prefix = -1;
12300 last_repz_prefix = -1;
12301 last_repnz_prefix = -1;
12302 last_data_prefix = -1;
12303 last_addr_prefix = -1;
12304 last_rex_prefix = -1;
12305 last_seg_prefix = -1;
12306 last_active_prefix = -1;
12308 active_seg_prefix = 0;
12309 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12310 all_prefixes[i] = 0;
12313 /* The maximum instruction length is 15bytes. */
12314 while (length < MAX_CODE_LENGTH - 1)
12316 FETCH_DATA (the_info, codep + 1);
12320 /* REX prefixes family. */
12337 if (address_mode == mode_64bit)
12341 last_rex_prefix = i;
12344 prefixes |= PREFIX_REPZ;
12345 last_repz_prefix = i;
12348 prefixes |= PREFIX_REPNZ;
12349 last_repnz_prefix = i;
12352 prefixes |= PREFIX_LOCK;
12353 last_lock_prefix = i;
12356 prefixes |= PREFIX_CS;
12357 last_seg_prefix = i;
12358 active_seg_prefix = PREFIX_CS;
12361 prefixes |= PREFIX_SS;
12362 last_seg_prefix = i;
12363 active_seg_prefix = PREFIX_SS;
12366 prefixes |= PREFIX_DS;
12367 last_seg_prefix = i;
12368 active_seg_prefix = PREFIX_DS;
12371 prefixes |= PREFIX_ES;
12372 last_seg_prefix = i;
12373 active_seg_prefix = PREFIX_ES;
12376 prefixes |= PREFIX_FS;
12377 last_seg_prefix = i;
12378 active_seg_prefix = PREFIX_FS;
12381 prefixes |= PREFIX_GS;
12382 last_seg_prefix = i;
12383 active_seg_prefix = PREFIX_GS;
12386 prefixes |= PREFIX_DATA;
12387 last_data_prefix = i;
12390 prefixes |= PREFIX_ADDR;
12391 last_addr_prefix = i;
12394 /* fwait is really an instruction. If there are prefixes
12395 before the fwait, they belong to the fwait, *not* to the
12396 following instruction. */
12398 if (prefixes || rex)
12400 prefixes |= PREFIX_FWAIT;
12402 /* This ensures that the previous REX prefixes are noticed
12403 as unused prefixes, as in the return case below. */
12407 prefixes = PREFIX_FWAIT;
12412 /* Rex is ignored when followed by another prefix. */
12418 if (*codep != FWAIT_OPCODE)
12420 last_active_prefix = i;
12421 all_prefixes[i++] = *codep;
12430 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12433 static const char *
12434 prefix_name (int pref, int sizeflag)
12436 static const char *rexes [16] =
12439 "rex.B", /* 0x41 */
12440 "rex.X", /* 0x42 */
12441 "rex.XB", /* 0x43 */
12442 "rex.R", /* 0x44 */
12443 "rex.RB", /* 0x45 */
12444 "rex.RX", /* 0x46 */
12445 "rex.RXB", /* 0x47 */
12446 "rex.W", /* 0x48 */
12447 "rex.WB", /* 0x49 */
12448 "rex.WX", /* 0x4a */
12449 "rex.WXB", /* 0x4b */
12450 "rex.WR", /* 0x4c */
12451 "rex.WRB", /* 0x4d */
12452 "rex.WRX", /* 0x4e */
12453 "rex.WRXB", /* 0x4f */
12458 /* REX prefixes family. */
12475 return rexes [pref - 0x40];
12495 return (sizeflag & DFLAG) ? "data16" : "data32";
12497 if (address_mode == mode_64bit)
12498 return (sizeflag & AFLAG) ? "addr32" : "addr64";
12500 return (sizeflag & AFLAG) ? "addr16" : "addr32";
12505 case XACQUIRE_PREFIX:
12507 case XRELEASE_PREFIX:
12511 case NOTRACK_PREFIX:
12518 static char op_out[MAX_OPERANDS][100];
12519 static int op_ad, op_index[MAX_OPERANDS];
12520 static int two_source_ops;
12521 static bfd_vma op_address[MAX_OPERANDS];
12522 static bfd_vma op_riprel[MAX_OPERANDS];
12523 static bfd_vma start_pc;
12526 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12527 * (see topic "Redundant prefixes" in the "Differences from 8086"
12528 * section of the "Virtual 8086 Mode" chapter.)
12529 * 'pc' should be the address of this instruction, it will
12530 * be used to print the target address if this is a relative jump or call
12531 * The function returns the length of this instruction in bytes.
12534 static char intel_syntax;
12535 static char intel_mnemonic = !SYSV386_COMPAT;
12536 static char open_char;
12537 static char close_char;
12538 static char separator_char;
12539 static char scale_char;
12547 static enum x86_64_isa isa64;
12549 /* Here for backwards compatibility. When gdb stops using
12550 print_insn_i386_att and print_insn_i386_intel these functions can
12551 disappear, and print_insn_i386 be merged into print_insn. */
12553 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12557 return print_insn (pc, info);
12561 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12565 return print_insn (pc, info);
12569 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12573 return print_insn (pc, info);
12577 print_i386_disassembler_options (FILE *stream)
12579 fprintf (stream, _("\n\
12580 The following i386/x86-64 specific disassembler options are supported for use\n\
12581 with the -M switch (multiple options should be separated by commas):\n"));
12583 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
12584 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
12585 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
12586 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
12587 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
12588 fprintf (stream, _(" att-mnemonic\n"
12589 " Display instruction in AT&T mnemonic\n"));
12590 fprintf (stream, _(" intel-mnemonic\n"
12591 " Display instruction in Intel mnemonic\n"));
12592 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
12593 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
12594 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
12595 fprintf (stream, _(" data32 Assume 32bit data size\n"));
12596 fprintf (stream, _(" data16 Assume 16bit data size\n"));
12597 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12598 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
12599 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
12603 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12605 /* Get a pointer to struct dis386 with a valid name. */
12607 static const struct dis386 *
12608 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12610 int vindex, vex_table_index;
12612 if (dp->name != NULL)
12615 switch (dp->op[0].bytemode)
12617 case USE_REG_TABLE:
12618 dp = ®_table[dp->op[1].bytemode][modrm.reg];
12621 case USE_MOD_TABLE:
12622 vindex = modrm.mod == 0x3 ? 1 : 0;
12623 dp = &mod_table[dp->op[1].bytemode][vindex];
12627 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12630 case USE_PREFIX_TABLE:
12633 /* The prefix in VEX is implicit. */
12634 switch (vex.prefix)
12639 case REPE_PREFIX_OPCODE:
12642 case DATA_PREFIX_OPCODE:
12645 case REPNE_PREFIX_OPCODE:
12655 int last_prefix = -1;
12658 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12659 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12661 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12663 if (last_repz_prefix > last_repnz_prefix)
12666 prefix = PREFIX_REPZ;
12667 last_prefix = last_repz_prefix;
12672 prefix = PREFIX_REPNZ;
12673 last_prefix = last_repnz_prefix;
12676 /* Check if prefix should be ignored. */
12677 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12678 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12683 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12686 prefix = PREFIX_DATA;
12687 last_prefix = last_data_prefix;
12692 used_prefixes |= prefix;
12693 all_prefixes[last_prefix] = 0;
12696 dp = &prefix_table[dp->op[1].bytemode][vindex];
12699 case USE_X86_64_TABLE:
12700 vindex = address_mode == mode_64bit ? 1 : 0;
12701 dp = &x86_64_table[dp->op[1].bytemode][vindex];
12704 case USE_3BYTE_TABLE:
12705 FETCH_DATA (info, codep + 2);
12707 dp = &three_byte_table[dp->op[1].bytemode][vindex];
12709 modrm.mod = (*codep >> 6) & 3;
12710 modrm.reg = (*codep >> 3) & 7;
12711 modrm.rm = *codep & 7;
12714 case USE_VEX_LEN_TABLE:
12718 switch (vex.length)
12731 dp = &vex_len_table[dp->op[1].bytemode][vindex];
12734 case USE_XOP_8F_TABLE:
12735 FETCH_DATA (info, codep + 3);
12736 /* All bits in the REX prefix are ignored. */
12738 rex = ~(*codep >> 5) & 0x7;
12740 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12741 switch ((*codep & 0x1f))
12747 vex_table_index = XOP_08;
12750 vex_table_index = XOP_09;
12753 vex_table_index = XOP_0A;
12757 vex.w = *codep & 0x80;
12758 if (vex.w && address_mode == mode_64bit)
12761 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12762 if (address_mode != mode_64bit)
12764 /* In 16/32-bit mode REX_B is silently ignored. */
12766 if (vex.register_specifier > 0x7)
12773 vex.length = (*codep & 0x4) ? 256 : 128;
12774 switch ((*codep & 0x3))
12780 vex.prefix = DATA_PREFIX_OPCODE;
12783 vex.prefix = REPE_PREFIX_OPCODE;
12786 vex.prefix = REPNE_PREFIX_OPCODE;
12793 dp = &xop_table[vex_table_index][vindex];
12796 FETCH_DATA (info, codep + 1);
12797 modrm.mod = (*codep >> 6) & 3;
12798 modrm.reg = (*codep >> 3) & 7;
12799 modrm.rm = *codep & 7;
12802 case USE_VEX_C4_TABLE:
12804 FETCH_DATA (info, codep + 3);
12805 /* All bits in the REX prefix are ignored. */
12807 rex = ~(*codep >> 5) & 0x7;
12808 switch ((*codep & 0x1f))
12814 vex_table_index = VEX_0F;
12817 vex_table_index = VEX_0F38;
12820 vex_table_index = VEX_0F3A;
12824 vex.w = *codep & 0x80;
12825 if (address_mode == mode_64bit)
12829 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12833 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12834 is ignored, other REX bits are 0 and the highest bit in
12835 VEX.vvvv is also ignored. */
12837 vex.register_specifier = (~(*codep >> 3)) & 0x7;
12839 vex.length = (*codep & 0x4) ? 256 : 128;
12840 switch ((*codep & 0x3))
12846 vex.prefix = DATA_PREFIX_OPCODE;
12849 vex.prefix = REPE_PREFIX_OPCODE;
12852 vex.prefix = REPNE_PREFIX_OPCODE;
12859 dp = &vex_table[vex_table_index][vindex];
12861 /* There is no MODRM byte for VEX0F 77. */
12862 if (vex_table_index != VEX_0F || vindex != 0x77)
12864 FETCH_DATA (info, codep + 1);
12865 modrm.mod = (*codep >> 6) & 3;
12866 modrm.reg = (*codep >> 3) & 7;
12867 modrm.rm = *codep & 7;
12871 case USE_VEX_C5_TABLE:
12873 FETCH_DATA (info, codep + 2);
12874 /* All bits in the REX prefix are ignored. */
12876 rex = (*codep & 0x80) ? 0 : REX_R;
12878 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12880 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12882 vex.length = (*codep & 0x4) ? 256 : 128;
12883 switch ((*codep & 0x3))
12889 vex.prefix = DATA_PREFIX_OPCODE;
12892 vex.prefix = REPE_PREFIX_OPCODE;
12895 vex.prefix = REPNE_PREFIX_OPCODE;
12902 dp = &vex_table[dp->op[1].bytemode][vindex];
12904 /* There is no MODRM byte for VEX 77. */
12905 if (vindex != 0x77)
12907 FETCH_DATA (info, codep + 1);
12908 modrm.mod = (*codep >> 6) & 3;
12909 modrm.reg = (*codep >> 3) & 7;
12910 modrm.rm = *codep & 7;
12914 case USE_VEX_W_TABLE:
12918 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12921 case USE_EVEX_TABLE:
12922 two_source_ops = 0;
12925 FETCH_DATA (info, codep + 4);
12926 /* All bits in the REX prefix are ignored. */
12928 /* The first byte after 0x62. */
12929 rex = ~(*codep >> 5) & 0x7;
12930 vex.r = *codep & 0x10;
12931 switch ((*codep & 0xf))
12934 return &bad_opcode;
12936 vex_table_index = EVEX_0F;
12939 vex_table_index = EVEX_0F38;
12942 vex_table_index = EVEX_0F3A;
12946 /* The second byte after 0x62. */
12948 vex.w = *codep & 0x80;
12949 if (vex.w && address_mode == mode_64bit)
12952 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12953 if (address_mode != mode_64bit)
12955 /* In 16/32-bit mode silently ignore following bits. */
12959 vex.register_specifier &= 0x7;
12963 if (!(*codep & 0x4))
12964 return &bad_opcode;
12966 switch ((*codep & 0x3))
12972 vex.prefix = DATA_PREFIX_OPCODE;
12975 vex.prefix = REPE_PREFIX_OPCODE;
12978 vex.prefix = REPNE_PREFIX_OPCODE;
12982 /* The third byte after 0x62. */
12985 /* Remember the static rounding bits. */
12986 vex.ll = (*codep >> 5) & 3;
12987 vex.b = (*codep & 0x10) != 0;
12989 vex.v = *codep & 0x8;
12990 vex.mask_register_specifier = *codep & 0x7;
12991 vex.zeroing = *codep & 0x80;
12997 dp = &evex_table[vex_table_index][vindex];
12999 FETCH_DATA (info, codep + 1);
13000 modrm.mod = (*codep >> 6) & 3;
13001 modrm.reg = (*codep >> 3) & 7;
13002 modrm.rm = *codep & 7;
13004 /* Set vector length. */
13005 if (modrm.mod == 3 && vex.b)
13021 return &bad_opcode;
13034 if (dp->name != NULL)
13037 return get_valid_dis386 (dp, info);
13041 get_sib (disassemble_info *info, int sizeflag)
13043 /* If modrm.mod == 3, operand must be register. */
13045 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13049 FETCH_DATA (info, codep + 2);
13050 sib.index = (codep [1] >> 3) & 7;
13051 sib.scale = (codep [1] >> 6) & 3;
13052 sib.base = codep [1] & 7;
13057 print_insn (bfd_vma pc, disassemble_info *info)
13059 const struct dis386 *dp;
13061 char *op_txt[MAX_OPERANDS];
13063 int sizeflag, orig_sizeflag;
13065 struct dis_private priv;
13068 priv.orig_sizeflag = AFLAG | DFLAG;
13069 if ((info->mach & bfd_mach_i386_i386) != 0)
13070 address_mode = mode_32bit;
13071 else if (info->mach == bfd_mach_i386_i8086)
13073 address_mode = mode_16bit;
13074 priv.orig_sizeflag = 0;
13077 address_mode = mode_64bit;
13079 if (intel_syntax == (char) -1)
13080 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13082 for (p = info->disassembler_options; p != NULL; )
13084 if (CONST_STRNEQ (p, "amd64"))
13086 else if (CONST_STRNEQ (p, "intel64"))
13088 else if (CONST_STRNEQ (p, "x86-64"))
13090 address_mode = mode_64bit;
13091 priv.orig_sizeflag = AFLAG | DFLAG;
13093 else if (CONST_STRNEQ (p, "i386"))
13095 address_mode = mode_32bit;
13096 priv.orig_sizeflag = AFLAG | DFLAG;
13098 else if (CONST_STRNEQ (p, "i8086"))
13100 address_mode = mode_16bit;
13101 priv.orig_sizeflag = 0;
13103 else if (CONST_STRNEQ (p, "intel"))
13106 if (CONST_STRNEQ (p + 5, "-mnemonic"))
13107 intel_mnemonic = 1;
13109 else if (CONST_STRNEQ (p, "att"))
13112 if (CONST_STRNEQ (p + 3, "-mnemonic"))
13113 intel_mnemonic = 0;
13115 else if (CONST_STRNEQ (p, "addr"))
13117 if (address_mode == mode_64bit)
13119 if (p[4] == '3' && p[5] == '2')
13120 priv.orig_sizeflag &= ~AFLAG;
13121 else if (p[4] == '6' && p[5] == '4')
13122 priv.orig_sizeflag |= AFLAG;
13126 if (p[4] == '1' && p[5] == '6')
13127 priv.orig_sizeflag &= ~AFLAG;
13128 else if (p[4] == '3' && p[5] == '2')
13129 priv.orig_sizeflag |= AFLAG;
13132 else if (CONST_STRNEQ (p, "data"))
13134 if (p[4] == '1' && p[5] == '6')
13135 priv.orig_sizeflag &= ~DFLAG;
13136 else if (p[4] == '3' && p[5] == '2')
13137 priv.orig_sizeflag |= DFLAG;
13139 else if (CONST_STRNEQ (p, "suffix"))
13140 priv.orig_sizeflag |= SUFFIX_ALWAYS;
13142 p = strchr (p, ',');
13147 if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13149 (*info->fprintf_func) (info->stream,
13150 _("64-bit address is disabled"));
13156 names64 = intel_names64;
13157 names32 = intel_names32;
13158 names16 = intel_names16;
13159 names8 = intel_names8;
13160 names8rex = intel_names8rex;
13161 names_seg = intel_names_seg;
13162 names_mm = intel_names_mm;
13163 names_bnd = intel_names_bnd;
13164 names_xmm = intel_names_xmm;
13165 names_ymm = intel_names_ymm;
13166 names_zmm = intel_names_zmm;
13167 index64 = intel_index64;
13168 index32 = intel_index32;
13169 names_mask = intel_names_mask;
13170 index16 = intel_index16;
13173 separator_char = '+';
13178 names64 = att_names64;
13179 names32 = att_names32;
13180 names16 = att_names16;
13181 names8 = att_names8;
13182 names8rex = att_names8rex;
13183 names_seg = att_names_seg;
13184 names_mm = att_names_mm;
13185 names_bnd = att_names_bnd;
13186 names_xmm = att_names_xmm;
13187 names_ymm = att_names_ymm;
13188 names_zmm = att_names_zmm;
13189 index64 = att_index64;
13190 index32 = att_index32;
13191 names_mask = att_names_mask;
13192 index16 = att_index16;
13195 separator_char = ',';
13199 /* The output looks better if we put 7 bytes on a line, since that
13200 puts most long word instructions on a single line. Use 8 bytes
13202 if ((info->mach & bfd_mach_l1om) != 0)
13203 info->bytes_per_line = 8;
13205 info->bytes_per_line = 7;
13207 info->private_data = &priv;
13208 priv.max_fetched = priv.the_buffer;
13209 priv.insn_start = pc;
13212 for (i = 0; i < MAX_OPERANDS; ++i)
13220 start_codep = priv.the_buffer;
13221 codep = priv.the_buffer;
13223 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13227 /* Getting here means we tried for data but didn't get it. That
13228 means we have an incomplete instruction of some sort. Just
13229 print the first byte as a prefix or a .byte pseudo-op. */
13230 if (codep > priv.the_buffer)
13232 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13234 (*info->fprintf_func) (info->stream, "%s", name);
13237 /* Just print the first byte as a .byte instruction. */
13238 (*info->fprintf_func) (info->stream, ".byte 0x%x",
13239 (unsigned int) priv.the_buffer[0]);
13249 sizeflag = priv.orig_sizeflag;
13251 if (!ckprefix () || rex_used)
13253 /* Too many prefixes or unused REX prefixes. */
13255 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13257 (*info->fprintf_func) (info->stream, "%s%s",
13259 prefix_name (all_prefixes[i], sizeflag));
13263 insn_codep = codep;
13265 FETCH_DATA (info, codep + 1);
13266 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13268 if (((prefixes & PREFIX_FWAIT)
13269 && ((*codep < 0xd8) || (*codep > 0xdf))))
13271 /* Handle prefixes before fwait. */
13272 for (i = 0; i < fwait_prefix && all_prefixes[i];
13274 (*info->fprintf_func) (info->stream, "%s ",
13275 prefix_name (all_prefixes[i], sizeflag));
13276 (*info->fprintf_func) (info->stream, "fwait");
13280 if (*codep == 0x0f)
13282 unsigned char threebyte;
13285 FETCH_DATA (info, codep + 1);
13286 threebyte = *codep;
13287 dp = &dis386_twobyte[threebyte];
13288 need_modrm = twobyte_has_modrm[*codep];
13293 dp = &dis386[*codep];
13294 need_modrm = onebyte_has_modrm[*codep];
13298 /* Save sizeflag for printing the extra prefixes later before updating
13299 it for mnemonic and operand processing. The prefix names depend
13300 only on the address mode. */
13301 orig_sizeflag = sizeflag;
13302 if (prefixes & PREFIX_ADDR)
13304 if ((prefixes & PREFIX_DATA))
13310 FETCH_DATA (info, codep + 1);
13311 modrm.mod = (*codep >> 6) & 3;
13312 modrm.reg = (*codep >> 3) & 7;
13313 modrm.rm = *codep & 7;
13321 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13323 get_sib (info, sizeflag);
13324 dofloat (sizeflag);
13328 dp = get_valid_dis386 (dp, info);
13329 if (dp != NULL && putop (dp->name, sizeflag) == 0)
13331 get_sib (info, sizeflag);
13332 for (i = 0; i < MAX_OPERANDS; ++i)
13335 op_ad = MAX_OPERANDS - 1 - i;
13337 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13338 /* For EVEX instruction after the last operand masking
13339 should be printed. */
13340 if (i == 0 && vex.evex)
13342 /* Don't print {%k0}. */
13343 if (vex.mask_register_specifier)
13346 oappend (names_mask[vex.mask_register_specifier]);
13356 /* Check if the REX prefix is used. */
13357 if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13358 all_prefixes[last_rex_prefix] = 0;
13360 /* Check if the SEG prefix is used. */
13361 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13362 | PREFIX_FS | PREFIX_GS)) != 0
13363 && (used_prefixes & active_seg_prefix) != 0)
13364 all_prefixes[last_seg_prefix] = 0;
13366 /* Check if the ADDR prefix is used. */
13367 if ((prefixes & PREFIX_ADDR) != 0
13368 && (used_prefixes & PREFIX_ADDR) != 0)
13369 all_prefixes[last_addr_prefix] = 0;
13371 /* Check if the DATA prefix is used. */
13372 if ((prefixes & PREFIX_DATA) != 0
13373 && (used_prefixes & PREFIX_DATA) != 0)
13374 all_prefixes[last_data_prefix] = 0;
13376 /* Print the extra prefixes. */
13378 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13379 if (all_prefixes[i])
13382 name = prefix_name (all_prefixes[i], orig_sizeflag);
13385 prefix_length += strlen (name) + 1;
13386 (*info->fprintf_func) (info->stream, "%s ", name);
13389 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13390 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13391 used by putop and MMX/SSE operand and may be overriden by the
13392 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13394 if (dp->prefix_requirement == PREFIX_OPCODE
13395 && dp != &bad_opcode
13397 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13399 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13401 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13403 && (used_prefixes & PREFIX_DATA) == 0))))
13405 (*info->fprintf_func) (info->stream, "(bad)");
13406 return end_codep - priv.the_buffer;
13409 /* Check maximum code length. */
13410 if ((codep - start_codep) > MAX_CODE_LENGTH)
13412 (*info->fprintf_func) (info->stream, "(bad)");
13413 return MAX_CODE_LENGTH;
13416 obufp = mnemonicendp;
13417 for (i = strlen (obuf) + prefix_length; i < 6; i++)
13420 (*info->fprintf_func) (info->stream, "%s", obuf);
13422 /* The enter and bound instructions are printed with operands in the same
13423 order as the intel book; everything else is printed in reverse order. */
13424 if (intel_syntax || two_source_ops)
13428 for (i = 0; i < MAX_OPERANDS; ++i)
13429 op_txt[i] = op_out[i];
13431 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13432 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13434 op_txt[2] = op_out[3];
13435 op_txt[3] = op_out[2];
13438 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13440 op_ad = op_index[i];
13441 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13442 op_index[MAX_OPERANDS - 1 - i] = op_ad;
13443 riprel = op_riprel[i];
13444 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13445 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13450 for (i = 0; i < MAX_OPERANDS; ++i)
13451 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13455 for (i = 0; i < MAX_OPERANDS; ++i)
13459 (*info->fprintf_func) (info->stream, ",");
13460 if (op_index[i] != -1 && !op_riprel[i])
13461 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13463 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13467 for (i = 0; i < MAX_OPERANDS; i++)
13468 if (op_index[i] != -1 && op_riprel[i])
13470 (*info->fprintf_func) (info->stream, " # ");
13471 (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13472 + op_address[op_index[i]]), info);
13475 return codep - priv.the_buffer;
13478 static const char *float_mem[] = {
13553 static const unsigned char float_mem_mode[] = {
13628 #define ST { OP_ST, 0 }
13629 #define STi { OP_STi, 0 }
13631 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13632 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13633 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13634 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13635 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13636 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13637 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13638 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13639 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13641 static const struct dis386 float_reg[][8] = {
13644 { "fadd", { ST, STi }, 0 },
13645 { "fmul", { ST, STi }, 0 },
13646 { "fcom", { STi }, 0 },
13647 { "fcomp", { STi }, 0 },
13648 { "fsub", { ST, STi }, 0 },
13649 { "fsubr", { ST, STi }, 0 },
13650 { "fdiv", { ST, STi }, 0 },
13651 { "fdivr", { ST, STi }, 0 },
13655 { "fld", { STi }, 0 },
13656 { "fxch", { STi }, 0 },
13666 { "fcmovb", { ST, STi }, 0 },
13667 { "fcmove", { ST, STi }, 0 },
13668 { "fcmovbe",{ ST, STi }, 0 },
13669 { "fcmovu", { ST, STi }, 0 },
13677 { "fcmovnb",{ ST, STi }, 0 },
13678 { "fcmovne",{ ST, STi }, 0 },
13679 { "fcmovnbe",{ ST, STi }, 0 },
13680 { "fcmovnu",{ ST, STi }, 0 },
13682 { "fucomi", { ST, STi }, 0 },
13683 { "fcomi", { ST, STi }, 0 },
13688 { "fadd", { STi, ST }, 0 },
13689 { "fmul", { STi, ST }, 0 },
13692 { "fsub!M", { STi, ST }, 0 },
13693 { "fsubM", { STi, ST }, 0 },
13694 { "fdiv!M", { STi, ST }, 0 },
13695 { "fdivM", { STi, ST }, 0 },
13699 { "ffree", { STi }, 0 },
13701 { "fst", { STi }, 0 },
13702 { "fstp", { STi }, 0 },
13703 { "fucom", { STi }, 0 },
13704 { "fucomp", { STi }, 0 },
13710 { "faddp", { STi, ST }, 0 },
13711 { "fmulp", { STi, ST }, 0 },
13714 { "fsub!Mp", { STi, ST }, 0 },
13715 { "fsubMp", { STi, ST }, 0 },
13716 { "fdiv!Mp", { STi, ST }, 0 },
13717 { "fdivMp", { STi, ST }, 0 },
13721 { "ffreep", { STi }, 0 },
13726 { "fucomip", { ST, STi }, 0 },
13727 { "fcomip", { ST, STi }, 0 },
13732 static char *fgrps[][8] = {
13735 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13740 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13745 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13750 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13755 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13760 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13765 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13770 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13771 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13776 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13781 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13786 swap_operand (void)
13788 mnemonicendp[0] = '.';
13789 mnemonicendp[1] = 's';
13794 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13795 int sizeflag ATTRIBUTE_UNUSED)
13797 /* Skip mod/rm byte. */
13803 dofloat (int sizeflag)
13805 const struct dis386 *dp;
13806 unsigned char floatop;
13808 floatop = codep[-1];
13810 if (modrm.mod != 3)
13812 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13814 putop (float_mem[fp_indx], sizeflag);
13817 OP_E (float_mem_mode[fp_indx], sizeflag);
13820 /* Skip mod/rm byte. */
13824 dp = &float_reg[floatop - 0xd8][modrm.reg];
13825 if (dp->name == NULL)
13827 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13829 /* Instruction fnstsw is only one with strange arg. */
13830 if (floatop == 0xdf && codep[-1] == 0xe0)
13831 strcpy (op_out[0], names16[0]);
13835 putop (dp->name, sizeflag);
13840 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13845 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13849 /* Like oappend (below), but S is a string starting with '%'.
13850 In Intel syntax, the '%' is elided. */
13852 oappend_maybe_intel (const char *s)
13854 oappend (s + intel_syntax);
13858 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13860 oappend_maybe_intel ("%st");
13864 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13866 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13867 oappend_maybe_intel (scratchbuf);
13870 /* Capital letters in template are macros. */
13872 putop (const char *in_template, int sizeflag)
13877 unsigned int l = 0, len = 1;
13880 #define SAVE_LAST(c) \
13881 if (l < len && l < sizeof (last)) \
13886 for (p = in_template; *p; p++)
13902 while (*++p != '|')
13903 if (*p == '}' || *p == '\0')
13906 /* Fall through. */
13911 while (*++p != '}')
13922 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13926 if (l == 0 && len == 1)
13931 if (sizeflag & SUFFIX_ALWAYS)
13944 if (address_mode == mode_64bit
13945 && !(prefixes & PREFIX_ADDR))
13956 if (intel_syntax && !alt)
13958 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13960 if (sizeflag & DFLAG)
13961 *obufp++ = intel_syntax ? 'd' : 'l';
13963 *obufp++ = intel_syntax ? 'w' : 's';
13964 used_prefixes |= (prefixes & PREFIX_DATA);
13968 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13971 if (modrm.mod == 3)
13977 if (sizeflag & DFLAG)
13978 *obufp++ = intel_syntax ? 'd' : 'l';
13981 used_prefixes |= (prefixes & PREFIX_DATA);
13987 case 'E': /* For jcxz/jecxz */
13988 if (address_mode == mode_64bit)
13990 if (sizeflag & AFLAG)
13996 if (sizeflag & AFLAG)
13998 used_prefixes |= (prefixes & PREFIX_ADDR);
14003 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14005 if (sizeflag & AFLAG)
14006 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14008 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14009 used_prefixes |= (prefixes & PREFIX_ADDR);
14013 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14015 if ((rex & REX_W) || (sizeflag & DFLAG))
14019 if (!(rex & REX_W))
14020 used_prefixes |= (prefixes & PREFIX_DATA);
14025 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14026 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14028 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14031 if (prefixes & PREFIX_DS)
14050 if (l != 0 || len != 1)
14052 if (l != 1 || len != 2 || last[0] != 'X')
14057 if (!need_vex || !vex.evex)
14060 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14062 switch (vex.length)
14080 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14085 /* Fall through. */
14088 if (l != 0 || len != 1)
14096 if (sizeflag & SUFFIX_ALWAYS)
14100 if (intel_mnemonic != cond)
14104 if ((prefixes & PREFIX_FWAIT) == 0)
14107 used_prefixes |= PREFIX_FWAIT;
14113 else if (intel_syntax && (sizeflag & DFLAG))
14117 if (!(rex & REX_W))
14118 used_prefixes |= (prefixes & PREFIX_DATA);
14122 && address_mode == mode_64bit
14123 && isa64 == intel64)
14128 /* Fall through. */
14131 && address_mode == mode_64bit
14132 && ((sizeflag & DFLAG) || (rex & REX_W)))
14137 /* Fall through. */
14140 if (l == 0 && len == 1)
14145 if ((rex & REX_W) == 0
14146 && (prefixes & PREFIX_DATA))
14148 if ((sizeflag & DFLAG) == 0)
14150 used_prefixes |= (prefixes & PREFIX_DATA);
14154 if ((prefixes & PREFIX_DATA)
14156 || (sizeflag & SUFFIX_ALWAYS))
14163 if (sizeflag & DFLAG)
14167 used_prefixes |= (prefixes & PREFIX_DATA);
14173 if (l != 1 || len != 2 || last[0] != 'L')
14179 if ((prefixes & PREFIX_DATA)
14181 || (sizeflag & SUFFIX_ALWAYS))
14188 if (sizeflag & DFLAG)
14189 *obufp++ = intel_syntax ? 'd' : 'l';
14192 used_prefixes |= (prefixes & PREFIX_DATA);
14200 if (address_mode == mode_64bit
14201 && ((sizeflag & DFLAG) || (rex & REX_W)))
14203 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14207 /* Fall through. */
14210 if (l == 0 && len == 1)
14213 if (intel_syntax && !alt)
14216 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14222 if (sizeflag & DFLAG)
14223 *obufp++ = intel_syntax ? 'd' : 'l';
14226 used_prefixes |= (prefixes & PREFIX_DATA);
14232 if (l != 1 || len != 2 || last[0] != 'L')
14238 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14253 else if (sizeflag & DFLAG)
14262 if (intel_syntax && !p[1]
14263 && ((rex & REX_W) || (sizeflag & DFLAG)))
14265 if (!(rex & REX_W))
14266 used_prefixes |= (prefixes & PREFIX_DATA);
14269 if (l == 0 && len == 1)
14273 if (address_mode == mode_64bit
14274 && ((sizeflag & DFLAG) || (rex & REX_W)))
14276 if (sizeflag & SUFFIX_ALWAYS)
14298 /* Fall through. */
14301 if (l == 0 && len == 1)
14306 if (sizeflag & SUFFIX_ALWAYS)
14312 if (sizeflag & DFLAG)
14316 used_prefixes |= (prefixes & PREFIX_DATA);
14330 if (address_mode == mode_64bit
14331 && !(prefixes & PREFIX_ADDR))
14342 if (l != 0 || len != 1)
14347 if (need_vex && vex.prefix)
14349 if (vex.prefix == DATA_PREFIX_OPCODE)
14356 if (prefixes & PREFIX_DATA)
14360 used_prefixes |= (prefixes & PREFIX_DATA);
14364 if (l == 0 && len == 1)
14366 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14377 if (l != 1 || len != 2 || last[0] != 'X')
14385 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14387 switch (vex.length)
14403 if (l == 0 && len == 1)
14405 /* operand size flag for cwtl, cbtw */
14414 else if (sizeflag & DFLAG)
14418 if (!(rex & REX_W))
14419 used_prefixes |= (prefixes & PREFIX_DATA);
14426 && last[0] != 'L'))
14433 if (last[0] == 'X')
14434 *obufp++ = vex.w ? 'd': 's';
14436 *obufp++ = vex.w ? 'q': 'd';
14442 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14444 if (sizeflag & DFLAG)
14448 used_prefixes |= (prefixes & PREFIX_DATA);
14454 if (address_mode == mode_64bit
14455 && (isa64 == intel64
14456 || ((sizeflag & DFLAG) || (rex & REX_W))))
14458 else if ((prefixes & PREFIX_DATA))
14460 if (!(sizeflag & DFLAG))
14462 used_prefixes |= (prefixes & PREFIX_DATA);
14469 mnemonicendp = obufp;
14474 oappend (const char *s)
14476 obufp = stpcpy (obufp, s);
14482 /* Only print the active segment register. */
14483 if (!active_seg_prefix)
14486 used_prefixes |= active_seg_prefix;
14487 switch (active_seg_prefix)
14490 oappend_maybe_intel ("%cs:");
14493 oappend_maybe_intel ("%ds:");
14496 oappend_maybe_intel ("%ss:");
14499 oappend_maybe_intel ("%es:");
14502 oappend_maybe_intel ("%fs:");
14505 oappend_maybe_intel ("%gs:");
14513 OP_indirE (int bytemode, int sizeflag)
14517 OP_E (bytemode, sizeflag);
14521 print_operand_value (char *buf, int hex, bfd_vma disp)
14523 if (address_mode == mode_64bit)
14531 sprintf_vma (tmp, disp);
14532 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14533 strcpy (buf + 2, tmp + i);
14537 bfd_signed_vma v = disp;
14544 /* Check for possible overflow on 0x8000000000000000. */
14547 strcpy (buf, "9223372036854775808");
14561 tmp[28 - i] = (v % 10) + '0';
14565 strcpy (buf, tmp + 29 - i);
14571 sprintf (buf, "0x%x", (unsigned int) disp);
14573 sprintf (buf, "%d", (int) disp);
14577 /* Put DISP in BUF as signed hex number. */
14580 print_displacement (char *buf, bfd_vma disp)
14582 bfd_signed_vma val = disp;
14591 /* Check for possible overflow. */
14594 switch (address_mode)
14597 strcpy (buf + j, "0x8000000000000000");
14600 strcpy (buf + j, "0x80000000");
14603 strcpy (buf + j, "0x8000");
14613 sprintf_vma (tmp, (bfd_vma) val);
14614 for (i = 0; tmp[i] == '0'; i++)
14616 if (tmp[i] == '\0')
14618 strcpy (buf + j, tmp + i);
14622 intel_operand_size (int bytemode, int sizeflag)
14626 && (bytemode == x_mode
14627 || bytemode == evex_half_bcst_xmmq_mode))
14630 oappend ("QWORD PTR ");
14632 oappend ("DWORD PTR ");
14641 oappend ("BYTE PTR ");
14646 oappend ("WORD PTR ");
14649 if (address_mode == mode_64bit && isa64 == intel64)
14651 oappend ("QWORD PTR ");
14654 /* Fall through. */
14656 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14658 oappend ("QWORD PTR ");
14661 /* Fall through. */
14667 oappend ("QWORD PTR ");
14670 if ((sizeflag & DFLAG) || bytemode == dq_mode)
14671 oappend ("DWORD PTR ");
14673 oappend ("WORD PTR ");
14674 used_prefixes |= (prefixes & PREFIX_DATA);
14678 if ((rex & REX_W) || (sizeflag & DFLAG))
14680 oappend ("WORD PTR ");
14681 if (!(rex & REX_W))
14682 used_prefixes |= (prefixes & PREFIX_DATA);
14685 if (sizeflag & DFLAG)
14686 oappend ("QWORD PTR ");
14688 oappend ("DWORD PTR ");
14689 used_prefixes |= (prefixes & PREFIX_DATA);
14692 case d_scalar_mode:
14693 case d_scalar_swap_mode:
14696 oappend ("DWORD PTR ");
14699 case q_scalar_mode:
14700 case q_scalar_swap_mode:
14702 oappend ("QWORD PTR ");
14705 if (address_mode == mode_64bit)
14706 oappend ("QWORD PTR ");
14708 oappend ("DWORD PTR ");
14711 if (sizeflag & DFLAG)
14712 oappend ("FWORD PTR ");
14714 oappend ("DWORD PTR ");
14715 used_prefixes |= (prefixes & PREFIX_DATA);
14718 oappend ("TBYTE PTR ");
14722 case evex_x_gscat_mode:
14723 case evex_x_nobcst_mode:
14726 switch (vex.length)
14729 oappend ("XMMWORD PTR ");
14732 oappend ("YMMWORD PTR ");
14735 oappend ("ZMMWORD PTR ");
14742 oappend ("XMMWORD PTR ");
14745 oappend ("XMMWORD PTR ");
14748 oappend ("YMMWORD PTR ");
14751 case evex_half_bcst_xmmq_mode:
14755 switch (vex.length)
14758 oappend ("QWORD PTR ");
14761 oappend ("XMMWORD PTR ");
14764 oappend ("YMMWORD PTR ");
14774 switch (vex.length)
14779 oappend ("BYTE PTR ");
14789 switch (vex.length)
14794 oappend ("WORD PTR ");
14804 switch (vex.length)
14809 oappend ("DWORD PTR ");
14819 switch (vex.length)
14824 oappend ("QWORD PTR ");
14834 switch (vex.length)
14837 oappend ("WORD PTR ");
14840 oappend ("DWORD PTR ");
14843 oappend ("QWORD PTR ");
14853 switch (vex.length)
14856 oappend ("DWORD PTR ");
14859 oappend ("QWORD PTR ");
14862 oappend ("XMMWORD PTR ");
14872 switch (vex.length)
14875 oappend ("QWORD PTR ");
14878 oappend ("YMMWORD PTR ");
14881 oappend ("ZMMWORD PTR ");
14891 switch (vex.length)
14895 oappend ("XMMWORD PTR ");
14902 oappend ("OWORD PTR ");
14905 case vex_w_dq_mode:
14906 case vex_scalar_w_dq_mode:
14911 oappend ("QWORD PTR ");
14913 oappend ("DWORD PTR ");
14915 case vex_vsib_d_w_dq_mode:
14916 case vex_vsib_q_w_dq_mode:
14923 oappend ("QWORD PTR ");
14925 oappend ("DWORD PTR ");
14929 switch (vex.length)
14932 oappend ("XMMWORD PTR ");
14935 oappend ("YMMWORD PTR ");
14938 oappend ("ZMMWORD PTR ");
14945 case vex_vsib_q_w_d_mode:
14946 case vex_vsib_d_w_d_mode:
14947 if (!need_vex || !vex.evex)
14950 switch (vex.length)
14953 oappend ("QWORD PTR ");
14956 oappend ("XMMWORD PTR ");
14959 oappend ("YMMWORD PTR ");
14967 if (!need_vex || vex.length != 128)
14970 oappend ("DWORD PTR ");
14972 oappend ("BYTE PTR ");
14978 oappend ("QWORD PTR ");
14980 oappend ("WORD PTR ");
14989 OP_E_register (int bytemode, int sizeflag)
14991 int reg = modrm.rm;
14992 const char **names;
14998 if ((sizeflag & SUFFIX_ALWAYS)
14999 && (bytemode == b_swap_mode
15000 || bytemode == v_swap_mode))
15026 names = address_mode == mode_64bit ? names64 : names32;
15037 if (address_mode == mode_64bit && isa64 == intel64)
15042 /* Fall through. */
15044 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15050 /* Fall through. */
15062 if ((sizeflag & DFLAG)
15063 || (bytemode != v_mode
15064 && bytemode != v_swap_mode))
15068 used_prefixes |= (prefixes & PREFIX_DATA);
15078 names = names_mask;
15083 oappend (INTERNAL_DISASSEMBLER_ERROR);
15086 oappend (names[reg]);
15090 OP_E_memory (int bytemode, int sizeflag)
15093 int add = (rex & REX_B) ? 8 : 0;
15099 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
15101 && bytemode != x_mode
15102 && bytemode != xmmq_mode
15103 && bytemode != evex_half_bcst_xmmq_mode)
15118 case vex_vsib_d_w_dq_mode:
15119 case vex_vsib_d_w_d_mode:
15120 case vex_vsib_q_w_dq_mode:
15121 case vex_vsib_q_w_d_mode:
15122 case evex_x_gscat_mode:
15124 shift = vex.w ? 3 : 2;
15127 case evex_half_bcst_xmmq_mode:
15131 shift = vex.w ? 3 : 2;
15134 /* Fall through. */
15138 case evex_x_nobcst_mode:
15140 switch (vex.length)
15163 case q_scalar_mode:
15165 case q_scalar_swap_mode:
15171 case d_scalar_mode:
15173 case d_scalar_swap_mode:
15185 /* Make necessary corrections to shift for modes that need it.
15186 For these modes we currently have shift 4, 5 or 6 depending on
15187 vex.length (it corresponds to xmmword, ymmword or zmmword
15188 operand). We might want to make it 3, 4 or 5 (e.g. for
15189 xmmq_mode). In case of broadcast enabled the corrections
15190 aren't needed, as element size is always 32 or 64 bits. */
15192 && (bytemode == xmmq_mode
15193 || bytemode == evex_half_bcst_xmmq_mode))
15195 else if (bytemode == xmmqd_mode)
15197 else if (bytemode == xmmdw_mode)
15199 else if (bytemode == ymmq_mode && vex.length == 128)
15207 intel_operand_size (bytemode, sizeflag);
15210 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15212 /* 32/64 bit address mode */
15221 int addr32flag = !((sizeflag & AFLAG)
15222 || bytemode == v_bnd_mode
15223 || bytemode == bnd_mode);
15224 const char **indexes64 = names64;
15225 const char **indexes32 = names32;
15235 vindex = sib.index;
15241 case vex_vsib_d_w_dq_mode:
15242 case vex_vsib_d_w_d_mode:
15243 case vex_vsib_q_w_dq_mode:
15244 case vex_vsib_q_w_d_mode:
15254 switch (vex.length)
15257 indexes64 = indexes32 = names_xmm;
15261 || bytemode == vex_vsib_q_w_dq_mode
15262 || bytemode == vex_vsib_q_w_d_mode)
15263 indexes64 = indexes32 = names_ymm;
15265 indexes64 = indexes32 = names_xmm;
15269 || bytemode == vex_vsib_q_w_dq_mode
15270 || bytemode == vex_vsib_q_w_d_mode)
15271 indexes64 = indexes32 = names_zmm;
15273 indexes64 = indexes32 = names_ymm;
15280 haveindex = vindex != 4;
15287 rbase = base + add;
15295 if (address_mode == mode_64bit && !havesib)
15301 FETCH_DATA (the_info, codep + 1);
15303 if ((disp & 0x80) != 0)
15305 if (vex.evex && shift > 0)
15313 /* In 32bit mode, we need index register to tell [offset] from
15314 [eiz*1 + offset]. */
15315 needindex = (havesib
15318 && address_mode == mode_32bit);
15319 havedisp = (havebase
15321 || (havesib && (haveindex || scale != 0)));
15324 if (modrm.mod != 0 || base == 5)
15326 if (havedisp || riprel)
15327 print_displacement (scratchbuf, disp);
15329 print_operand_value (scratchbuf, 1, disp);
15330 oappend (scratchbuf);
15334 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15338 if ((havebase || haveindex || riprel)
15339 && (bytemode != v_bnd_mode)
15340 && (bytemode != bnd_mode))
15341 used_prefixes |= PREFIX_ADDR;
15343 if (havedisp || (intel_syntax && riprel))
15345 *obufp++ = open_char;
15346 if (intel_syntax && riprel)
15349 oappend (!addr32flag ? "rip" : "eip");
15353 oappend (address_mode == mode_64bit && !addr32flag
15354 ? names64[rbase] : names32[rbase]);
15357 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15358 print index to tell base + index from base. */
15362 || (havebase && base != ESP_REG_NUM))
15364 if (!intel_syntax || havebase)
15366 *obufp++ = separator_char;
15370 oappend (address_mode == mode_64bit && !addr32flag
15371 ? indexes64[vindex] : indexes32[vindex]);
15373 oappend (address_mode == mode_64bit && !addr32flag
15374 ? index64 : index32);
15376 *obufp++ = scale_char;
15378 sprintf (scratchbuf, "%d", 1 << scale);
15379 oappend (scratchbuf);
15383 && (disp || modrm.mod != 0 || base == 5))
15385 if (!havedisp || (bfd_signed_vma) disp >= 0)
15390 else if (modrm.mod != 1 && disp != -disp)
15394 disp = - (bfd_signed_vma) disp;
15398 print_displacement (scratchbuf, disp);
15400 print_operand_value (scratchbuf, 1, disp);
15401 oappend (scratchbuf);
15404 *obufp++ = close_char;
15407 else if (intel_syntax)
15409 if (modrm.mod != 0 || base == 5)
15411 if (!active_seg_prefix)
15413 oappend (names_seg[ds_reg - es_reg]);
15416 print_operand_value (scratchbuf, 1, disp);
15417 oappend (scratchbuf);
15423 /* 16 bit address mode */
15424 used_prefixes |= prefixes & PREFIX_ADDR;
15431 if ((disp & 0x8000) != 0)
15436 FETCH_DATA (the_info, codep + 1);
15438 if ((disp & 0x80) != 0)
15443 if ((disp & 0x8000) != 0)
15449 if (modrm.mod != 0 || modrm.rm == 6)
15451 print_displacement (scratchbuf, disp);
15452 oappend (scratchbuf);
15455 if (modrm.mod != 0 || modrm.rm != 6)
15457 *obufp++ = open_char;
15459 oappend (index16[modrm.rm]);
15461 && (disp || modrm.mod != 0 || modrm.rm == 6))
15463 if ((bfd_signed_vma) disp >= 0)
15468 else if (modrm.mod != 1)
15472 disp = - (bfd_signed_vma) disp;
15475 print_displacement (scratchbuf, disp);
15476 oappend (scratchbuf);
15479 *obufp++ = close_char;
15482 else if (intel_syntax)
15484 if (!active_seg_prefix)
15486 oappend (names_seg[ds_reg - es_reg]);
15489 print_operand_value (scratchbuf, 1, disp & 0xffff);
15490 oappend (scratchbuf);
15493 if (vex.evex && vex.b
15494 && (bytemode == x_mode
15495 || bytemode == xmmq_mode
15496 || bytemode == evex_half_bcst_xmmq_mode))
15499 || bytemode == xmmq_mode
15500 || bytemode == evex_half_bcst_xmmq_mode)
15502 switch (vex.length)
15505 oappend ("{1to2}");
15508 oappend ("{1to4}");
15511 oappend ("{1to8}");
15519 switch (vex.length)
15522 oappend ("{1to4}");
15525 oappend ("{1to8}");
15528 oappend ("{1to16}");
15538 OP_E (int bytemode, int sizeflag)
15540 /* Skip mod/rm byte. */
15544 if (modrm.mod == 3)
15545 OP_E_register (bytemode, sizeflag);
15547 OP_E_memory (bytemode, sizeflag);
15551 OP_G (int bytemode, int sizeflag)
15562 oappend (names8rex[modrm.reg + add]);
15564 oappend (names8[modrm.reg + add]);
15567 oappend (names16[modrm.reg + add]);
15572 oappend (names32[modrm.reg + add]);
15575 oappend (names64[modrm.reg + add]);
15578 if (modrm.reg > 0x3)
15583 oappend (names_bnd[modrm.reg]);
15592 oappend (names64[modrm.reg + add]);
15595 if ((sizeflag & DFLAG) || bytemode != v_mode)
15596 oappend (names32[modrm.reg + add]);
15598 oappend (names16[modrm.reg + add]);
15599 used_prefixes |= (prefixes & PREFIX_DATA);
15603 if (address_mode == mode_64bit)
15604 oappend (names64[modrm.reg + add]);
15606 oappend (names32[modrm.reg + add]);
15610 if ((modrm.reg + add) > 0x7)
15615 oappend (names_mask[modrm.reg + add]);
15618 oappend (INTERNAL_DISASSEMBLER_ERROR);
15631 FETCH_DATA (the_info, codep + 8);
15632 a = *codep++ & 0xff;
15633 a |= (*codep++ & 0xff) << 8;
15634 a |= (*codep++ & 0xff) << 16;
15635 a |= (*codep++ & 0xffu) << 24;
15636 b = *codep++ & 0xff;
15637 b |= (*codep++ & 0xff) << 8;
15638 b |= (*codep++ & 0xff) << 16;
15639 b |= (*codep++ & 0xffu) << 24;
15640 x = a + ((bfd_vma) b << 32);
15648 static bfd_signed_vma
15651 bfd_signed_vma x = 0;
15653 FETCH_DATA (the_info, codep + 4);
15654 x = *codep++ & (bfd_signed_vma) 0xff;
15655 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15656 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15657 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15661 static bfd_signed_vma
15664 bfd_signed_vma x = 0;
15666 FETCH_DATA (the_info, codep + 4);
15667 x = *codep++ & (bfd_signed_vma) 0xff;
15668 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15669 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15670 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15672 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15682 FETCH_DATA (the_info, codep + 2);
15683 x = *codep++ & 0xff;
15684 x |= (*codep++ & 0xff) << 8;
15689 set_op (bfd_vma op, int riprel)
15691 op_index[op_ad] = op_ad;
15692 if (address_mode == mode_64bit)
15694 op_address[op_ad] = op;
15695 op_riprel[op_ad] = riprel;
15699 /* Mask to get a 32-bit address. */
15700 op_address[op_ad] = op & 0xffffffff;
15701 op_riprel[op_ad] = riprel & 0xffffffff;
15706 OP_REG (int code, int sizeflag)
15713 case es_reg: case ss_reg: case cs_reg:
15714 case ds_reg: case fs_reg: case gs_reg:
15715 oappend (names_seg[code - es_reg]);
15727 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15728 case sp_reg: case bp_reg: case si_reg: case di_reg:
15729 s = names16[code - ax_reg + add];
15731 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15732 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15735 s = names8rex[code - al_reg + add];
15737 s = names8[code - al_reg];
15739 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15740 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15741 if (address_mode == mode_64bit
15742 && ((sizeflag & DFLAG) || (rex & REX_W)))
15744 s = names64[code - rAX_reg + add];
15747 code += eAX_reg - rAX_reg;
15748 /* Fall through. */
15749 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15750 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15753 s = names64[code - eAX_reg + add];
15756 if (sizeflag & DFLAG)
15757 s = names32[code - eAX_reg + add];
15759 s = names16[code - eAX_reg + add];
15760 used_prefixes |= (prefixes & PREFIX_DATA);
15764 s = INTERNAL_DISASSEMBLER_ERROR;
15771 OP_IMREG (int code, int sizeflag)
15783 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15784 case sp_reg: case bp_reg: case si_reg: case di_reg:
15785 s = names16[code - ax_reg];
15787 case es_reg: case ss_reg: case cs_reg:
15788 case ds_reg: case fs_reg: case gs_reg:
15789 s = names_seg[code - es_reg];
15791 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15792 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15795 s = names8rex[code - al_reg];
15797 s = names8[code - al_reg];
15799 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15800 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15803 s = names64[code - eAX_reg];
15806 if (sizeflag & DFLAG)
15807 s = names32[code - eAX_reg];
15809 s = names16[code - eAX_reg];
15810 used_prefixes |= (prefixes & PREFIX_DATA);
15813 case z_mode_ax_reg:
15814 if ((rex & REX_W) || (sizeflag & DFLAG))
15818 if (!(rex & REX_W))
15819 used_prefixes |= (prefixes & PREFIX_DATA);
15822 s = INTERNAL_DISASSEMBLER_ERROR;
15829 OP_I (int bytemode, int sizeflag)
15832 bfd_signed_vma mask = -1;
15837 FETCH_DATA (the_info, codep + 1);
15842 if (address_mode == mode_64bit)
15847 /* Fall through. */
15854 if (sizeflag & DFLAG)
15864 used_prefixes |= (prefixes & PREFIX_DATA);
15876 oappend (INTERNAL_DISASSEMBLER_ERROR);
15881 scratchbuf[0] = '$';
15882 print_operand_value (scratchbuf + 1, 1, op);
15883 oappend_maybe_intel (scratchbuf);
15884 scratchbuf[0] = '\0';
15888 OP_I64 (int bytemode, int sizeflag)
15891 bfd_signed_vma mask = -1;
15893 if (address_mode != mode_64bit)
15895 OP_I (bytemode, sizeflag);
15902 FETCH_DATA (the_info, codep + 1);
15912 if (sizeflag & DFLAG)
15922 used_prefixes |= (prefixes & PREFIX_DATA);
15930 oappend (INTERNAL_DISASSEMBLER_ERROR);
15935 scratchbuf[0] = '$';
15936 print_operand_value (scratchbuf + 1, 1, op);
15937 oappend_maybe_intel (scratchbuf);
15938 scratchbuf[0] = '\0';
15942 OP_sI (int bytemode, int sizeflag)
15950 FETCH_DATA (the_info, codep + 1);
15952 if ((op & 0x80) != 0)
15954 if (bytemode == b_T_mode)
15956 if (address_mode != mode_64bit
15957 || !((sizeflag & DFLAG) || (rex & REX_W)))
15959 /* The operand-size prefix is overridden by a REX prefix. */
15960 if ((sizeflag & DFLAG) || (rex & REX_W))
15968 if (!(rex & REX_W))
15970 if (sizeflag & DFLAG)
15978 /* The operand-size prefix is overridden by a REX prefix. */
15979 if ((sizeflag & DFLAG) || (rex & REX_W))
15985 oappend (INTERNAL_DISASSEMBLER_ERROR);
15989 scratchbuf[0] = '$';
15990 print_operand_value (scratchbuf + 1, 1, op);
15991 oappend_maybe_intel (scratchbuf);
15995 OP_J (int bytemode, int sizeflag)
15999 bfd_vma segment = 0;
16004 FETCH_DATA (the_info, codep + 1);
16006 if ((disp & 0x80) != 0)
16010 if (isa64 == amd64)
16012 if ((sizeflag & DFLAG)
16013 || (address_mode == mode_64bit
16014 && (isa64 != amd64 || (rex & REX_W))))
16019 if ((disp & 0x8000) != 0)
16021 /* In 16bit mode, address is wrapped around at 64k within
16022 the same segment. Otherwise, a data16 prefix on a jump
16023 instruction means that the pc is masked to 16 bits after
16024 the displacement is added! */
16026 if ((prefixes & PREFIX_DATA) == 0)
16027 segment = ((start_pc + (codep - start_codep))
16028 & ~((bfd_vma) 0xffff));
16030 if (address_mode != mode_64bit
16031 || (isa64 == amd64 && !(rex & REX_W)))
16032 used_prefixes |= (prefixes & PREFIX_DATA);
16035 oappend (INTERNAL_DISASSEMBLER_ERROR);
16038 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16040 print_operand_value (scratchbuf, 1, disp);
16041 oappend (scratchbuf);
16045 OP_SEG (int bytemode, int sizeflag)
16047 if (bytemode == w_mode)
16048 oappend (names_seg[modrm.reg]);
16050 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16054 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16058 if (sizeflag & DFLAG)
16068 used_prefixes |= (prefixes & PREFIX_DATA);
16070 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16072 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16073 oappend (scratchbuf);
16077 OP_OFF (int bytemode, int sizeflag)
16081 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16082 intel_operand_size (bytemode, sizeflag);
16085 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16092 if (!active_seg_prefix)
16094 oappend (names_seg[ds_reg - es_reg]);
16098 print_operand_value (scratchbuf, 1, off);
16099 oappend (scratchbuf);
16103 OP_OFF64 (int bytemode, int sizeflag)
16107 if (address_mode != mode_64bit
16108 || (prefixes & PREFIX_ADDR))
16110 OP_OFF (bytemode, sizeflag);
16114 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16115 intel_operand_size (bytemode, sizeflag);
16122 if (!active_seg_prefix)
16124 oappend (names_seg[ds_reg - es_reg]);
16128 print_operand_value (scratchbuf, 1, off);
16129 oappend (scratchbuf);
16133 ptr_reg (int code, int sizeflag)
16137 *obufp++ = open_char;
16138 used_prefixes |= (prefixes & PREFIX_ADDR);
16139 if (address_mode == mode_64bit)
16141 if (!(sizeflag & AFLAG))
16142 s = names32[code - eAX_reg];
16144 s = names64[code - eAX_reg];
16146 else if (sizeflag & AFLAG)
16147 s = names32[code - eAX_reg];
16149 s = names16[code - eAX_reg];
16151 *obufp++ = close_char;
16156 OP_ESreg (int code, int sizeflag)
16162 case 0x6d: /* insw/insl */
16163 intel_operand_size (z_mode, sizeflag);
16165 case 0xa5: /* movsw/movsl/movsq */
16166 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16167 case 0xab: /* stosw/stosl */
16168 case 0xaf: /* scasw/scasl */
16169 intel_operand_size (v_mode, sizeflag);
16172 intel_operand_size (b_mode, sizeflag);
16175 oappend_maybe_intel ("%es:");
16176 ptr_reg (code, sizeflag);
16180 OP_DSreg (int code, int sizeflag)
16186 case 0x6f: /* outsw/outsl */
16187 intel_operand_size (z_mode, sizeflag);
16189 case 0xa5: /* movsw/movsl/movsq */
16190 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16191 case 0xad: /* lodsw/lodsl/lodsq */
16192 intel_operand_size (v_mode, sizeflag);
16195 intel_operand_size (b_mode, sizeflag);
16198 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16199 default segment register DS is printed. */
16200 if (!active_seg_prefix)
16201 active_seg_prefix = PREFIX_DS;
16203 ptr_reg (code, sizeflag);
16207 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16215 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16217 all_prefixes[last_lock_prefix] = 0;
16218 used_prefixes |= PREFIX_LOCK;
16223 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16224 oappend_maybe_intel (scratchbuf);
16228 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16237 sprintf (scratchbuf, "db%d", modrm.reg + add);
16239 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16240 oappend (scratchbuf);
16244 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16246 sprintf (scratchbuf, "%%tr%d", modrm.reg);
16247 oappend_maybe_intel (scratchbuf);
16251 OP_R (int bytemode, int sizeflag)
16253 /* Skip mod/rm byte. */
16256 OP_E_register (bytemode, sizeflag);
16260 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16262 int reg = modrm.reg;
16263 const char **names;
16265 used_prefixes |= (prefixes & PREFIX_DATA);
16266 if (prefixes & PREFIX_DATA)
16275 oappend (names[reg]);
16279 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16281 int reg = modrm.reg;
16282 const char **names;
16294 && bytemode != xmm_mode
16295 && bytemode != xmmq_mode
16296 && bytemode != evex_half_bcst_xmmq_mode
16297 && bytemode != ymm_mode
16298 && bytemode != scalar_mode)
16300 switch (vex.length)
16307 || (bytemode != vex_vsib_q_w_dq_mode
16308 && bytemode != vex_vsib_q_w_d_mode))
16320 else if (bytemode == xmmq_mode
16321 || bytemode == evex_half_bcst_xmmq_mode)
16323 switch (vex.length)
16336 else if (bytemode == ymm_mode)
16340 oappend (names[reg]);
16344 OP_EM (int bytemode, int sizeflag)
16347 const char **names;
16349 if (modrm.mod != 3)
16352 && (bytemode == v_mode || bytemode == v_swap_mode))
16354 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16355 used_prefixes |= (prefixes & PREFIX_DATA);
16357 OP_E (bytemode, sizeflag);
16361 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16364 /* Skip mod/rm byte. */
16367 used_prefixes |= (prefixes & PREFIX_DATA);
16369 if (prefixes & PREFIX_DATA)
16378 oappend (names[reg]);
16381 /* cvt* are the only instructions in sse2 which have
16382 both SSE and MMX operands and also have 0x66 prefix
16383 in their opcode. 0x66 was originally used to differentiate
16384 between SSE and MMX instruction(operands). So we have to handle the
16385 cvt* separately using OP_EMC and OP_MXC */
16387 OP_EMC (int bytemode, int sizeflag)
16389 if (modrm.mod != 3)
16391 if (intel_syntax && bytemode == v_mode)
16393 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16394 used_prefixes |= (prefixes & PREFIX_DATA);
16396 OP_E (bytemode, sizeflag);
16400 /* Skip mod/rm byte. */
16403 used_prefixes |= (prefixes & PREFIX_DATA);
16404 oappend (names_mm[modrm.rm]);
16408 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16410 used_prefixes |= (prefixes & PREFIX_DATA);
16411 oappend (names_mm[modrm.reg]);
16415 OP_EX (int bytemode, int sizeflag)
16418 const char **names;
16420 /* Skip mod/rm byte. */
16424 if (modrm.mod != 3)
16426 OP_E_memory (bytemode, sizeflag);
16441 if ((sizeflag & SUFFIX_ALWAYS)
16442 && (bytemode == x_swap_mode
16443 || bytemode == d_swap_mode
16444 || bytemode == d_scalar_swap_mode
16445 || bytemode == q_swap_mode
16446 || bytemode == q_scalar_swap_mode))
16450 && bytemode != xmm_mode
16451 && bytemode != xmmdw_mode
16452 && bytemode != xmmqd_mode
16453 && bytemode != xmm_mb_mode
16454 && bytemode != xmm_mw_mode
16455 && bytemode != xmm_md_mode
16456 && bytemode != xmm_mq_mode
16457 && bytemode != xmm_mdq_mode
16458 && bytemode != xmmq_mode
16459 && bytemode != evex_half_bcst_xmmq_mode
16460 && bytemode != ymm_mode
16461 && bytemode != d_scalar_mode
16462 && bytemode != d_scalar_swap_mode
16463 && bytemode != q_scalar_mode
16464 && bytemode != q_scalar_swap_mode
16465 && bytemode != vex_scalar_w_dq_mode)
16467 switch (vex.length)
16482 else if (bytemode == xmmq_mode
16483 || bytemode == evex_half_bcst_xmmq_mode)
16485 switch (vex.length)
16498 else if (bytemode == ymm_mode)
16502 oappend (names[reg]);
16506 OP_MS (int bytemode, int sizeflag)
16508 if (modrm.mod == 3)
16509 OP_EM (bytemode, sizeflag);
16515 OP_XS (int bytemode, int sizeflag)
16517 if (modrm.mod == 3)
16518 OP_EX (bytemode, sizeflag);
16524 OP_M (int bytemode, int sizeflag)
16526 if (modrm.mod == 3)
16527 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16530 OP_E (bytemode, sizeflag);
16534 OP_0f07 (int bytemode, int sizeflag)
16536 if (modrm.mod != 3 || modrm.rm != 0)
16539 OP_E (bytemode, sizeflag);
16542 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16543 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16546 NOP_Fixup1 (int bytemode, int sizeflag)
16548 if ((prefixes & PREFIX_DATA) != 0
16551 && address_mode == mode_64bit))
16552 OP_REG (bytemode, sizeflag);
16554 strcpy (obuf, "nop");
16558 NOP_Fixup2 (int bytemode, int sizeflag)
16560 if ((prefixes & PREFIX_DATA) != 0
16563 && address_mode == mode_64bit))
16564 OP_IMREG (bytemode, sizeflag);
16567 static const char *const Suffix3DNow[] = {
16568 /* 00 */ NULL, NULL, NULL, NULL,
16569 /* 04 */ NULL, NULL, NULL, NULL,
16570 /* 08 */ NULL, NULL, NULL, NULL,
16571 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
16572 /* 10 */ NULL, NULL, NULL, NULL,
16573 /* 14 */ NULL, NULL, NULL, NULL,
16574 /* 18 */ NULL, NULL, NULL, NULL,
16575 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
16576 /* 20 */ NULL, NULL, NULL, NULL,
16577 /* 24 */ NULL, NULL, NULL, NULL,
16578 /* 28 */ NULL, NULL, NULL, NULL,
16579 /* 2C */ NULL, NULL, NULL, NULL,
16580 /* 30 */ NULL, NULL, NULL, NULL,
16581 /* 34 */ NULL, NULL, NULL, NULL,
16582 /* 38 */ NULL, NULL, NULL, NULL,
16583 /* 3C */ NULL, NULL, NULL, NULL,
16584 /* 40 */ NULL, NULL, NULL, NULL,
16585 /* 44 */ NULL, NULL, NULL, NULL,
16586 /* 48 */ NULL, NULL, NULL, NULL,
16587 /* 4C */ NULL, NULL, NULL, NULL,
16588 /* 50 */ NULL, NULL, NULL, NULL,
16589 /* 54 */ NULL, NULL, NULL, NULL,
16590 /* 58 */ NULL, NULL, NULL, NULL,
16591 /* 5C */ NULL, NULL, NULL, NULL,
16592 /* 60 */ NULL, NULL, NULL, NULL,
16593 /* 64 */ NULL, NULL, NULL, NULL,
16594 /* 68 */ NULL, NULL, NULL, NULL,
16595 /* 6C */ NULL, NULL, NULL, NULL,
16596 /* 70 */ NULL, NULL, NULL, NULL,
16597 /* 74 */ NULL, NULL, NULL, NULL,
16598 /* 78 */ NULL, NULL, NULL, NULL,
16599 /* 7C */ NULL, NULL, NULL, NULL,
16600 /* 80 */ NULL, NULL, NULL, NULL,
16601 /* 84 */ NULL, NULL, NULL, NULL,
16602 /* 88 */ NULL, NULL, "pfnacc", NULL,
16603 /* 8C */ NULL, NULL, "pfpnacc", NULL,
16604 /* 90 */ "pfcmpge", NULL, NULL, NULL,
16605 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
16606 /* 98 */ NULL, NULL, "pfsub", NULL,
16607 /* 9C */ NULL, NULL, "pfadd", NULL,
16608 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
16609 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
16610 /* A8 */ NULL, NULL, "pfsubr", NULL,
16611 /* AC */ NULL, NULL, "pfacc", NULL,
16612 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
16613 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
16614 /* B8 */ NULL, NULL, NULL, "pswapd",
16615 /* BC */ NULL, NULL, NULL, "pavgusb",
16616 /* C0 */ NULL, NULL, NULL, NULL,
16617 /* C4 */ NULL, NULL, NULL, NULL,
16618 /* C8 */ NULL, NULL, NULL, NULL,
16619 /* CC */ NULL, NULL, NULL, NULL,
16620 /* D0 */ NULL, NULL, NULL, NULL,
16621 /* D4 */ NULL, NULL, NULL, NULL,
16622 /* D8 */ NULL, NULL, NULL, NULL,
16623 /* DC */ NULL, NULL, NULL, NULL,
16624 /* E0 */ NULL, NULL, NULL, NULL,
16625 /* E4 */ NULL, NULL, NULL, NULL,
16626 /* E8 */ NULL, NULL, NULL, NULL,
16627 /* EC */ NULL, NULL, NULL, NULL,
16628 /* F0 */ NULL, NULL, NULL, NULL,
16629 /* F4 */ NULL, NULL, NULL, NULL,
16630 /* F8 */ NULL, NULL, NULL, NULL,
16631 /* FC */ NULL, NULL, NULL, NULL,
16635 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16637 const char *mnemonic;
16639 FETCH_DATA (the_info, codep + 1);
16640 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16641 place where an 8-bit immediate would normally go. ie. the last
16642 byte of the instruction. */
16643 obufp = mnemonicendp;
16644 mnemonic = Suffix3DNow[*codep++ & 0xff];
16646 oappend (mnemonic);
16649 /* Since a variable sized modrm/sib chunk is between the start
16650 of the opcode (0x0f0f) and the opcode suffix, we need to do
16651 all the modrm processing first, and don't know until now that
16652 we have a bad opcode. This necessitates some cleaning up. */
16653 op_out[0][0] = '\0';
16654 op_out[1][0] = '\0';
16657 mnemonicendp = obufp;
16660 static struct op simd_cmp_op[] =
16662 { STRING_COMMA_LEN ("eq") },
16663 { STRING_COMMA_LEN ("lt") },
16664 { STRING_COMMA_LEN ("le") },
16665 { STRING_COMMA_LEN ("unord") },
16666 { STRING_COMMA_LEN ("neq") },
16667 { STRING_COMMA_LEN ("nlt") },
16668 { STRING_COMMA_LEN ("nle") },
16669 { STRING_COMMA_LEN ("ord") }
16673 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16675 unsigned int cmp_type;
16677 FETCH_DATA (the_info, codep + 1);
16678 cmp_type = *codep++ & 0xff;
16679 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16682 char *p = mnemonicendp - 2;
16686 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16687 mnemonicendp += simd_cmp_op[cmp_type].len;
16691 /* We have a reserved extension byte. Output it directly. */
16692 scratchbuf[0] = '$';
16693 print_operand_value (scratchbuf + 1, 1, cmp_type);
16694 oappend_maybe_intel (scratchbuf);
16695 scratchbuf[0] = '\0';
16700 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16701 int sizeflag ATTRIBUTE_UNUSED)
16703 /* mwaitx %eax,%ecx,%ebx */
16706 const char **names = (address_mode == mode_64bit
16707 ? names64 : names32);
16708 strcpy (op_out[0], names[0]);
16709 strcpy (op_out[1], names[1]);
16710 strcpy (op_out[2], names[3]);
16711 two_source_ops = 1;
16713 /* Skip mod/rm byte. */
16719 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16720 int sizeflag ATTRIBUTE_UNUSED)
16722 /* mwait %eax,%ecx */
16725 const char **names = (address_mode == mode_64bit
16726 ? names64 : names32);
16727 strcpy (op_out[0], names[0]);
16728 strcpy (op_out[1], names[1]);
16729 two_source_ops = 1;
16731 /* Skip mod/rm byte. */
16737 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16738 int sizeflag ATTRIBUTE_UNUSED)
16740 /* monitor %eax,%ecx,%edx" */
16743 const char **op1_names;
16744 const char **names = (address_mode == mode_64bit
16745 ? names64 : names32);
16747 if (!(prefixes & PREFIX_ADDR))
16748 op1_names = (address_mode == mode_16bit
16749 ? names16 : names);
16752 /* Remove "addr16/addr32". */
16753 all_prefixes[last_addr_prefix] = 0;
16754 op1_names = (address_mode != mode_32bit
16755 ? names32 : names16);
16756 used_prefixes |= PREFIX_ADDR;
16758 strcpy (op_out[0], op1_names[0]);
16759 strcpy (op_out[1], names[1]);
16760 strcpy (op_out[2], names[2]);
16761 two_source_ops = 1;
16763 /* Skip mod/rm byte. */
16771 /* Throw away prefixes and 1st. opcode byte. */
16772 codep = insn_codep + 1;
16777 REP_Fixup (int bytemode, int sizeflag)
16779 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16781 if (prefixes & PREFIX_REPZ)
16782 all_prefixes[last_repz_prefix] = REP_PREFIX;
16789 OP_IMREG (bytemode, sizeflag);
16792 OP_ESreg (bytemode, sizeflag);
16795 OP_DSreg (bytemode, sizeflag);
16803 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16807 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16809 if (prefixes & PREFIX_REPNZ)
16810 all_prefixes[last_repnz_prefix] = BND_PREFIX;
16813 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16817 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16818 int sizeflag ATTRIBUTE_UNUSED)
16820 if (active_seg_prefix == PREFIX_DS
16821 && (address_mode != mode_64bit || last_data_prefix < 0))
16823 /* NOTRACK prefix is only valid on indirect branch instructions
16824 and it must be the last prefix before REX prefix and opcode.
16825 NB: DATA prefix is unsupported for Intel64. */
16826 if (last_active_prefix >= 0)
16828 int notrack_prefix = last_active_prefix;
16829 if (last_rex_prefix == last_active_prefix)
16831 if (all_prefixes[notrack_prefix] != NOTRACK_PREFIX_OPCODE)
16834 active_seg_prefix = 0;
16835 all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
16839 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16840 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16844 HLE_Fixup1 (int bytemode, int sizeflag)
16847 && (prefixes & PREFIX_LOCK) != 0)
16849 if (prefixes & PREFIX_REPZ)
16850 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16851 if (prefixes & PREFIX_REPNZ)
16852 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16855 OP_E (bytemode, sizeflag);
16858 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16859 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16863 HLE_Fixup2 (int bytemode, int sizeflag)
16865 if (modrm.mod != 3)
16867 if (prefixes & PREFIX_REPZ)
16868 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16869 if (prefixes & PREFIX_REPNZ)
16870 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16873 OP_E (bytemode, sizeflag);
16876 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16877 "xrelease" for memory operand. No check for LOCK prefix. */
16880 HLE_Fixup3 (int bytemode, int sizeflag)
16883 && last_repz_prefix > last_repnz_prefix
16884 && (prefixes & PREFIX_REPZ) != 0)
16885 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16887 OP_E (bytemode, sizeflag);
16891 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16896 /* Change cmpxchg8b to cmpxchg16b. */
16897 char *p = mnemonicendp - 2;
16898 mnemonicendp = stpcpy (p, "16b");
16901 else if ((prefixes & PREFIX_LOCK) != 0)
16903 if (prefixes & PREFIX_REPZ)
16904 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16905 if (prefixes & PREFIX_REPNZ)
16906 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16909 OP_M (bytemode, sizeflag);
16913 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16915 const char **names;
16919 switch (vex.length)
16933 oappend (names[reg]);
16937 CRC32_Fixup (int bytemode, int sizeflag)
16939 /* Add proper suffix to "crc32". */
16940 char *p = mnemonicendp;
16959 if (sizeflag & DFLAG)
16963 used_prefixes |= (prefixes & PREFIX_DATA);
16967 oappend (INTERNAL_DISASSEMBLER_ERROR);
16974 if (modrm.mod == 3)
16978 /* Skip mod/rm byte. */
16983 add = (rex & REX_B) ? 8 : 0;
16984 if (bytemode == b_mode)
16988 oappend (names8rex[modrm.rm + add]);
16990 oappend (names8[modrm.rm + add]);
16996 oappend (names64[modrm.rm + add]);
16997 else if ((prefixes & PREFIX_DATA))
16998 oappend (names16[modrm.rm + add]);
17000 oappend (names32[modrm.rm + add]);
17004 OP_E (bytemode, sizeflag);
17008 FXSAVE_Fixup (int bytemode, int sizeflag)
17010 /* Add proper suffix to "fxsave" and "fxrstor". */
17014 char *p = mnemonicendp;
17020 OP_M (bytemode, sizeflag);
17024 PCMPESTR_Fixup (int bytemode, int sizeflag)
17026 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
17029 char *p = mnemonicendp;
17034 else if (sizeflag & SUFFIX_ALWAYS)
17041 OP_EX (bytemode, sizeflag);
17044 /* Display the destination register operand for instructions with
17048 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17051 const char **names;
17059 reg = vex.register_specifier;
17066 if (bytemode == vex_scalar_mode)
17068 oappend (names_xmm[reg]);
17072 switch (vex.length)
17079 case vex_vsib_q_w_dq_mode:
17080 case vex_vsib_q_w_d_mode:
17096 names = names_mask;
17110 case vex_vsib_q_w_dq_mode:
17111 case vex_vsib_q_w_d_mode:
17112 names = vex.w ? names_ymm : names_xmm;
17121 names = names_mask;
17124 /* See PR binutils/20893 for a reproducer. */
17136 oappend (names[reg]);
17139 /* Get the VEX immediate byte without moving codep. */
17141 static unsigned char
17142 get_vex_imm8 (int sizeflag, int opnum)
17144 int bytes_before_imm = 0;
17146 if (modrm.mod != 3)
17148 /* There are SIB/displacement bytes. */
17149 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17151 /* 32/64 bit address mode */
17152 int base = modrm.rm;
17154 /* Check SIB byte. */
17157 FETCH_DATA (the_info, codep + 1);
17159 /* When decoding the third source, don't increase
17160 bytes_before_imm as this has already been incremented
17161 by one in OP_E_memory while decoding the second
17164 bytes_before_imm++;
17167 /* Don't increase bytes_before_imm when decoding the third source,
17168 it has already been incremented by OP_E_memory while decoding
17169 the second source operand. */
17175 /* When modrm.rm == 5 or modrm.rm == 4 and base in
17176 SIB == 5, there is a 4 byte displacement. */
17178 /* No displacement. */
17180 /* Fall through. */
17182 /* 4 byte displacement. */
17183 bytes_before_imm += 4;
17186 /* 1 byte displacement. */
17187 bytes_before_imm++;
17194 /* 16 bit address mode */
17195 /* Don't increase bytes_before_imm when decoding the third source,
17196 it has already been incremented by OP_E_memory while decoding
17197 the second source operand. */
17203 /* When modrm.rm == 6, there is a 2 byte displacement. */
17205 /* No displacement. */
17207 /* Fall through. */
17209 /* 2 byte displacement. */
17210 bytes_before_imm += 2;
17213 /* 1 byte displacement: when decoding the third source,
17214 don't increase bytes_before_imm as this has already
17215 been incremented by one in OP_E_memory while decoding
17216 the second source operand. */
17218 bytes_before_imm++;
17226 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17227 return codep [bytes_before_imm];
17231 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17233 const char **names;
17235 if (reg == -1 && modrm.mod != 3)
17237 OP_E_memory (bytemode, sizeflag);
17249 else if (reg > 7 && address_mode != mode_64bit)
17253 switch (vex.length)
17264 oappend (names[reg]);
17268 OP_EX_VexImmW (int bytemode, int sizeflag)
17271 static unsigned char vex_imm8;
17273 if (vex_w_done == 0)
17277 /* Skip mod/rm byte. */
17281 vex_imm8 = get_vex_imm8 (sizeflag, 0);
17284 reg = vex_imm8 >> 4;
17286 OP_EX_VexReg (bytemode, sizeflag, reg);
17288 else if (vex_w_done == 1)
17293 reg = vex_imm8 >> 4;
17295 OP_EX_VexReg (bytemode, sizeflag, reg);
17299 /* Output the imm8 directly. */
17300 scratchbuf[0] = '$';
17301 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17302 oappend_maybe_intel (scratchbuf);
17303 scratchbuf[0] = '\0';
17309 OP_Vex_2src (int bytemode, int sizeflag)
17311 if (modrm.mod == 3)
17313 int reg = modrm.rm;
17317 oappend (names_xmm[reg]);
17322 && (bytemode == v_mode || bytemode == v_swap_mode))
17324 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17325 used_prefixes |= (prefixes & PREFIX_DATA);
17327 OP_E (bytemode, sizeflag);
17332 OP_Vex_2src_1 (int bytemode, int sizeflag)
17334 if (modrm.mod == 3)
17336 /* Skip mod/rm byte. */
17342 oappend (names_xmm[vex.register_specifier]);
17344 OP_Vex_2src (bytemode, sizeflag);
17348 OP_Vex_2src_2 (int bytemode, int sizeflag)
17351 OP_Vex_2src (bytemode, sizeflag);
17353 oappend (names_xmm[vex.register_specifier]);
17357 OP_EX_VexW (int bytemode, int sizeflag)
17365 /* Skip mod/rm byte. */
17370 reg = get_vex_imm8 (sizeflag, 0) >> 4;
17375 reg = get_vex_imm8 (sizeflag, 1) >> 4;
17378 OP_EX_VexReg (bytemode, sizeflag, reg);
17382 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17383 int sizeflag ATTRIBUTE_UNUSED)
17385 /* Skip the immediate byte and check for invalid bits. */
17386 FETCH_DATA (the_info, codep + 1);
17387 if (*codep++ & 0xf)
17392 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17395 const char **names;
17397 FETCH_DATA (the_info, codep + 1);
17400 if (bytemode != x_mode)
17407 if (reg > 7 && address_mode != mode_64bit)
17410 switch (vex.length)
17421 oappend (names[reg]);
17425 OP_XMM_VexW (int bytemode, int sizeflag)
17427 /* Turn off the REX.W bit since it is used for swapping operands
17430 OP_XMM (bytemode, sizeflag);
17434 OP_EX_Vex (int bytemode, int sizeflag)
17436 if (modrm.mod != 3)
17438 if (vex.register_specifier != 0)
17442 OP_EX (bytemode, sizeflag);
17446 OP_XMM_Vex (int bytemode, int sizeflag)
17448 if (modrm.mod != 3)
17450 if (vex.register_specifier != 0)
17454 OP_XMM (bytemode, sizeflag);
17458 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17460 switch (vex.length)
17463 mnemonicendp = stpcpy (obuf, "vzeroupper");
17466 mnemonicendp = stpcpy (obuf, "vzeroall");
17473 static struct op vex_cmp_op[] =
17475 { STRING_COMMA_LEN ("eq") },
17476 { STRING_COMMA_LEN ("lt") },
17477 { STRING_COMMA_LEN ("le") },
17478 { STRING_COMMA_LEN ("unord") },
17479 { STRING_COMMA_LEN ("neq") },
17480 { STRING_COMMA_LEN ("nlt") },
17481 { STRING_COMMA_LEN ("nle") },
17482 { STRING_COMMA_LEN ("ord") },
17483 { STRING_COMMA_LEN ("eq_uq") },
17484 { STRING_COMMA_LEN ("nge") },
17485 { STRING_COMMA_LEN ("ngt") },
17486 { STRING_COMMA_LEN ("false") },
17487 { STRING_COMMA_LEN ("neq_oq") },
17488 { STRING_COMMA_LEN ("ge") },
17489 { STRING_COMMA_LEN ("gt") },
17490 { STRING_COMMA_LEN ("true") },
17491 { STRING_COMMA_LEN ("eq_os") },
17492 { STRING_COMMA_LEN ("lt_oq") },
17493 { STRING_COMMA_LEN ("le_oq") },
17494 { STRING_COMMA_LEN ("unord_s") },
17495 { STRING_COMMA_LEN ("neq_us") },
17496 { STRING_COMMA_LEN ("nlt_uq") },
17497 { STRING_COMMA_LEN ("nle_uq") },
17498 { STRING_COMMA_LEN ("ord_s") },
17499 { STRING_COMMA_LEN ("eq_us") },
17500 { STRING_COMMA_LEN ("nge_uq") },
17501 { STRING_COMMA_LEN ("ngt_uq") },
17502 { STRING_COMMA_LEN ("false_os") },
17503 { STRING_COMMA_LEN ("neq_os") },
17504 { STRING_COMMA_LEN ("ge_oq") },
17505 { STRING_COMMA_LEN ("gt_oq") },
17506 { STRING_COMMA_LEN ("true_us") },
17510 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17512 unsigned int cmp_type;
17514 FETCH_DATA (the_info, codep + 1);
17515 cmp_type = *codep++ & 0xff;
17516 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17519 char *p = mnemonicendp - 2;
17523 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17524 mnemonicendp += vex_cmp_op[cmp_type].len;
17528 /* We have a reserved extension byte. Output it directly. */
17529 scratchbuf[0] = '$';
17530 print_operand_value (scratchbuf + 1, 1, cmp_type);
17531 oappend_maybe_intel (scratchbuf);
17532 scratchbuf[0] = '\0';
17537 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17538 int sizeflag ATTRIBUTE_UNUSED)
17540 unsigned int cmp_type;
17545 FETCH_DATA (the_info, codep + 1);
17546 cmp_type = *codep++ & 0xff;
17547 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17548 If it's the case, print suffix, otherwise - print the immediate. */
17549 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17554 char *p = mnemonicendp - 2;
17556 /* vpcmp* can have both one- and two-lettered suffix. */
17570 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17571 mnemonicendp += simd_cmp_op[cmp_type].len;
17575 /* We have a reserved extension byte. Output it directly. */
17576 scratchbuf[0] = '$';
17577 print_operand_value (scratchbuf + 1, 1, cmp_type);
17578 oappend_maybe_intel (scratchbuf);
17579 scratchbuf[0] = '\0';
17583 static const struct op pclmul_op[] =
17585 { STRING_COMMA_LEN ("lql") },
17586 { STRING_COMMA_LEN ("hql") },
17587 { STRING_COMMA_LEN ("lqh") },
17588 { STRING_COMMA_LEN ("hqh") }
17592 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17593 int sizeflag ATTRIBUTE_UNUSED)
17595 unsigned int pclmul_type;
17597 FETCH_DATA (the_info, codep + 1);
17598 pclmul_type = *codep++ & 0xff;
17599 switch (pclmul_type)
17610 if (pclmul_type < ARRAY_SIZE (pclmul_op))
17613 char *p = mnemonicendp - 3;
17618 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17619 mnemonicendp += pclmul_op[pclmul_type].len;
17623 /* We have a reserved extension byte. Output it directly. */
17624 scratchbuf[0] = '$';
17625 print_operand_value (scratchbuf + 1, 1, pclmul_type);
17626 oappend_maybe_intel (scratchbuf);
17627 scratchbuf[0] = '\0';
17632 MOVBE_Fixup (int bytemode, int sizeflag)
17634 /* Add proper suffix to "movbe". */
17635 char *p = mnemonicendp;
17644 if (sizeflag & SUFFIX_ALWAYS)
17650 if (sizeflag & DFLAG)
17654 used_prefixes |= (prefixes & PREFIX_DATA);
17659 oappend (INTERNAL_DISASSEMBLER_ERROR);
17666 OP_M (bytemode, sizeflag);
17670 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17673 const char **names;
17675 /* Skip mod/rm byte. */
17689 oappend (names[reg]);
17693 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17695 const char **names;
17702 oappend (names[vex.register_specifier]);
17706 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17709 || (bytemode != mask_mode && bytemode != mask_bd_mode))
17713 if ((rex & REX_R) != 0 || !vex.r)
17719 oappend (names_mask [modrm.reg]);
17723 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17726 || (bytemode != evex_rounding_mode
17727 && bytemode != evex_sae_mode))
17729 if (modrm.mod == 3 && vex.b)
17732 case evex_rounding_mode:
17733 oappend (names_rounding[vex.ll]);
17735 case evex_sae_mode: