1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
30 /* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
40 #include "opcode/i386.h"
41 #include "libiberty.h"
45 static int print_insn (bfd_vma, disassemble_info *);
46 static void dofloat (int);
47 static void OP_ST (int, int);
48 static void OP_STi (int, int);
49 static int putop (const char *, int);
50 static void oappend (const char *);
51 static void append_seg (void);
52 static void OP_indirE (int, int);
53 static void print_operand_value (char *, int, bfd_vma);
54 static void OP_E_register (int, int);
55 static void OP_E_memory (int, int);
56 static void print_displacement (char *, bfd_vma);
57 static void OP_E (int, int);
58 static void OP_G (int, int);
59 static bfd_vma get64 (void);
60 static bfd_signed_vma get32 (void);
61 static bfd_signed_vma get32s (void);
62 static int get16 (void);
63 static void set_op (bfd_vma, int);
64 static void OP_Skip_MODRM (int, int);
65 static void OP_REG (int, int);
66 static void OP_IMREG (int, int);
67 static void OP_I (int, int);
68 static void OP_I64 (int, int);
69 static void OP_sI (int, int);
70 static void OP_J (int, int);
71 static void OP_SEG (int, int);
72 static void OP_DIR (int, int);
73 static void OP_OFF (int, int);
74 static void OP_OFF64 (int, int);
75 static void ptr_reg (int, int);
76 static void OP_ESreg (int, int);
77 static void OP_DSreg (int, int);
78 static void OP_C (int, int);
79 static void OP_D (int, int);
80 static void OP_T (int, int);
81 static void OP_R (int, int);
82 static void OP_MMX (int, int);
83 static void OP_XMM (int, int);
84 static void OP_EM (int, int);
85 static void OP_EX (int, int);
86 static void OP_EMC (int,int);
87 static void OP_MXC (int,int);
88 static void OP_MS (int, int);
89 static void OP_XS (int, int);
90 static void OP_M (int, int);
91 static void OP_VEX (int, int);
92 static void OP_EX_Vex (int, int);
93 static void OP_EX_VexW (int, int);
94 static void OP_EX_VexImmW (int, int);
95 static void OP_XMM_Vex (int, int);
96 static void OP_XMM_VexW (int, int);
97 static void OP_Rounding (int, int);
98 static void OP_REG_VexI4 (int, int);
99 static void PCLMUL_Fixup (int, int);
100 static void VEXI4_Fixup (int, int);
101 static void VZERO_Fixup (int, int);
102 static void VCMP_Fixup (int, int);
103 static void VPCMP_Fixup (int, int);
104 static void OP_0f07 (int, int);
105 static void OP_Monitor (int, int);
106 static void OP_Mwait (int, int);
107 static void NOP_Fixup1 (int, int);
108 static void NOP_Fixup2 (int, int);
109 static void OP_3DNowSuffix (int, int);
110 static void CMP_Fixup (int, int);
111 static void BadOp (void);
112 static void REP_Fixup (int, int);
113 static void BND_Fixup (int, int);
114 static void HLE_Fixup1 (int, int);
115 static void HLE_Fixup2 (int, int);
116 static void HLE_Fixup3 (int, int);
117 static void CMPXCHG8B_Fixup (int, int);
118 static void XMM_Fixup (int, int);
119 static void CRC32_Fixup (int, int);
120 static void FXSAVE_Fixup (int, int);
121 static void OP_LWPCB_E (int, int);
122 static void OP_LWP_E (int, int);
123 static void OP_Vex_2src_1 (int, int);
124 static void OP_Vex_2src_2 (int, int);
126 static void MOVBE_Fixup (int, int);
128 static void OP_Mask (int, int);
131 /* Points to first byte not fetched. */
132 bfd_byte *max_fetched;
133 bfd_byte the_buffer[MAX_MNEM_SIZE];
146 enum address_mode address_mode;
148 /* Flags for the prefixes for the current instruction. See below. */
151 /* REX prefix the current instruction. See below. */
153 /* Bits of REX we've already used. */
155 /* REX bits in original REX prefix ignored. */
156 static int rex_ignored;
157 /* Mark parts used in the REX prefix. When we are testing for
158 empty prefix (for 8bit register REX extension), just mask it
159 out. Otherwise test for REX bit is excuse for existence of REX
160 only in case value is nonzero. */
161 #define USED_REX(value) \
166 rex_used |= (value) | REX_OPCODE; \
169 rex_used |= REX_OPCODE; \
172 /* Flags for prefixes which we somehow handled when printing the
173 current instruction. */
174 static int used_prefixes;
176 /* Flags stored in PREFIXES. */
177 #define PREFIX_REPZ 1
178 #define PREFIX_REPNZ 2
179 #define PREFIX_LOCK 4
181 #define PREFIX_SS 0x10
182 #define PREFIX_DS 0x20
183 #define PREFIX_ES 0x40
184 #define PREFIX_FS 0x80
185 #define PREFIX_GS 0x100
186 #define PREFIX_DATA 0x200
187 #define PREFIX_ADDR 0x400
188 #define PREFIX_FWAIT 0x800
190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
191 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
193 #define FETCH_DATA(info, addr) \
194 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
195 ? 1 : fetch_data ((info), (addr)))
198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
201 struct dis_private *priv = (struct dis_private *) info->private_data;
202 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
204 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
205 status = (*info->read_memory_func) (start,
207 addr - priv->max_fetched,
213 /* If we did manage to read at least one byte, then
214 print_insn_i386 will do something sensible. Otherwise, print
215 an error. We do that here because this is where we know
217 if (priv->max_fetched == priv->the_buffer)
218 (*info->memory_error_func) (status, start, info);
219 longjmp (priv->bailout, 1);
222 priv->max_fetched = addr;
226 #define XX { NULL, 0 }
227 #define Bad_Opcode NULL, { { NULL, 0 } }
229 #define Eb { OP_E, b_mode }
230 #define Ebnd { OP_E, bnd_mode }
231 #define EbS { OP_E, b_swap_mode }
232 #define Ev { OP_E, v_mode }
233 #define Ev_bnd { OP_E, v_bnd_mode }
234 #define EvS { OP_E, v_swap_mode }
235 #define Ed { OP_E, d_mode }
236 #define Edq { OP_E, dq_mode }
237 #define Edqw { OP_E, dqw_mode }
238 #define Edqb { OP_E, dqb_mode }
239 #define Edqd { OP_E, dqd_mode }
240 #define Eq { OP_E, q_mode }
241 #define indirEv { OP_indirE, stack_v_mode }
242 #define indirEp { OP_indirE, f_mode }
243 #define stackEv { OP_E, stack_v_mode }
244 #define Em { OP_E, m_mode }
245 #define Ew { OP_E, w_mode }
246 #define M { OP_M, 0 } /* lea, lgdt, etc. */
247 #define Ma { OP_M, a_mode }
248 #define Mb { OP_M, b_mode }
249 #define Md { OP_M, d_mode }
250 #define Mo { OP_M, o_mode }
251 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
252 #define Mq { OP_M, q_mode }
253 #define Mx { OP_M, x_mode }
254 #define Mxmm { OP_M, xmm_mode }
255 #define Gb { OP_G, b_mode }
256 #define Gbnd { OP_G, bnd_mode }
257 #define Gv { OP_G, v_mode }
258 #define Gd { OP_G, d_mode }
259 #define Gdq { OP_G, dq_mode }
260 #define Gm { OP_G, m_mode }
261 #define Gw { OP_G, w_mode }
262 #define Rd { OP_R, d_mode }
263 #define Rdq { OP_R, dq_mode }
264 #define Rm { OP_R, m_mode }
265 #define Ib { OP_I, b_mode }
266 #define sIb { OP_sI, b_mode } /* sign extened byte */
267 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
268 #define Iv { OP_I, v_mode }
269 #define sIv { OP_sI, v_mode }
270 #define Iq { OP_I, q_mode }
271 #define Iv64 { OP_I64, v_mode }
272 #define Iw { OP_I, w_mode }
273 #define I1 { OP_I, const_1_mode }
274 #define Jb { OP_J, b_mode }
275 #define Jv { OP_J, v_mode }
276 #define Cm { OP_C, m_mode }
277 #define Dm { OP_D, m_mode }
278 #define Td { OP_T, d_mode }
279 #define Skip_MODRM { OP_Skip_MODRM, 0 }
281 #define RMeAX { OP_REG, eAX_reg }
282 #define RMeBX { OP_REG, eBX_reg }
283 #define RMeCX { OP_REG, eCX_reg }
284 #define RMeDX { OP_REG, eDX_reg }
285 #define RMeSP { OP_REG, eSP_reg }
286 #define RMeBP { OP_REG, eBP_reg }
287 #define RMeSI { OP_REG, eSI_reg }
288 #define RMeDI { OP_REG, eDI_reg }
289 #define RMrAX { OP_REG, rAX_reg }
290 #define RMrBX { OP_REG, rBX_reg }
291 #define RMrCX { OP_REG, rCX_reg }
292 #define RMrDX { OP_REG, rDX_reg }
293 #define RMrSP { OP_REG, rSP_reg }
294 #define RMrBP { OP_REG, rBP_reg }
295 #define RMrSI { OP_REG, rSI_reg }
296 #define RMrDI { OP_REG, rDI_reg }
297 #define RMAL { OP_REG, al_reg }
298 #define RMCL { OP_REG, cl_reg }
299 #define RMDL { OP_REG, dl_reg }
300 #define RMBL { OP_REG, bl_reg }
301 #define RMAH { OP_REG, ah_reg }
302 #define RMCH { OP_REG, ch_reg }
303 #define RMDH { OP_REG, dh_reg }
304 #define RMBH { OP_REG, bh_reg }
305 #define RMAX { OP_REG, ax_reg }
306 #define RMDX { OP_REG, dx_reg }
308 #define eAX { OP_IMREG, eAX_reg }
309 #define eBX { OP_IMREG, eBX_reg }
310 #define eCX { OP_IMREG, eCX_reg }
311 #define eDX { OP_IMREG, eDX_reg }
312 #define eSP { OP_IMREG, eSP_reg }
313 #define eBP { OP_IMREG, eBP_reg }
314 #define eSI { OP_IMREG, eSI_reg }
315 #define eDI { OP_IMREG, eDI_reg }
316 #define AL { OP_IMREG, al_reg }
317 #define CL { OP_IMREG, cl_reg }
318 #define DL { OP_IMREG, dl_reg }
319 #define BL { OP_IMREG, bl_reg }
320 #define AH { OP_IMREG, ah_reg }
321 #define CH { OP_IMREG, ch_reg }
322 #define DH { OP_IMREG, dh_reg }
323 #define BH { OP_IMREG, bh_reg }
324 #define AX { OP_IMREG, ax_reg }
325 #define DX { OP_IMREG, dx_reg }
326 #define zAX { OP_IMREG, z_mode_ax_reg }
327 #define indirDX { OP_IMREG, indir_dx_reg }
329 #define Sw { OP_SEG, w_mode }
330 #define Sv { OP_SEG, v_mode }
331 #define Ap { OP_DIR, 0 }
332 #define Ob { OP_OFF64, b_mode }
333 #define Ov { OP_OFF64, v_mode }
334 #define Xb { OP_DSreg, eSI_reg }
335 #define Xv { OP_DSreg, eSI_reg }
336 #define Xz { OP_DSreg, eSI_reg }
337 #define Yb { OP_ESreg, eDI_reg }
338 #define Yv { OP_ESreg, eDI_reg }
339 #define DSBX { OP_DSreg, eBX_reg }
341 #define es { OP_REG, es_reg }
342 #define ss { OP_REG, ss_reg }
343 #define cs { OP_REG, cs_reg }
344 #define ds { OP_REG, ds_reg }
345 #define fs { OP_REG, fs_reg }
346 #define gs { OP_REG, gs_reg }
348 #define MX { OP_MMX, 0 }
349 #define XM { OP_XMM, 0 }
350 #define XMScalar { OP_XMM, scalar_mode }
351 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
352 #define XMM { OP_XMM, xmm_mode }
353 #define XMxmmq { OP_XMM, xmmq_mode }
354 #define EM { OP_EM, v_mode }
355 #define EMS { OP_EM, v_swap_mode }
356 #define EMd { OP_EM, d_mode }
357 #define EMx { OP_EM, x_mode }
358 #define EXw { OP_EX, w_mode }
359 #define EXd { OP_EX, d_mode }
360 #define EXdScalar { OP_EX, d_scalar_mode }
361 #define EXdS { OP_EX, d_swap_mode }
362 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
363 #define EXq { OP_EX, q_mode }
364 #define EXqScalar { OP_EX, q_scalar_mode }
365 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
366 #define EXqS { OP_EX, q_swap_mode }
367 #define EXx { OP_EX, x_mode }
368 #define EXxS { OP_EX, x_swap_mode }
369 #define EXxmm { OP_EX, xmm_mode }
370 #define EXymm { OP_EX, ymm_mode }
371 #define EXxmmq { OP_EX, xmmq_mode }
372 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
373 #define EXxmm_mb { OP_EX, xmm_mb_mode }
374 #define EXxmm_mw { OP_EX, xmm_mw_mode }
375 #define EXxmm_md { OP_EX, xmm_md_mode }
376 #define EXxmm_mq { OP_EX, xmm_mq_mode }
377 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
378 #define EXxmmdw { OP_EX, xmmdw_mode }
379 #define EXxmmqd { OP_EX, xmmqd_mode }
380 #define EXymmq { OP_EX, ymmq_mode }
381 #define EXVexWdq { OP_EX, vex_w_dq_mode }
382 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
383 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
384 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
385 #define MS { OP_MS, v_mode }
386 #define XS { OP_XS, v_mode }
387 #define EMCq { OP_EMC, q_mode }
388 #define MXC { OP_MXC, 0 }
389 #define OPSUF { OP_3DNowSuffix, 0 }
390 #define CMP { CMP_Fixup, 0 }
391 #define XMM0 { XMM_Fixup, 0 }
392 #define FXSAVE { FXSAVE_Fixup, 0 }
393 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
394 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
396 #define Vex { OP_VEX, vex_mode }
397 #define VexScalar { OP_VEX, vex_scalar_mode }
398 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
399 #define Vex128 { OP_VEX, vex128_mode }
400 #define Vex256 { OP_VEX, vex256_mode }
401 #define VexGdq { OP_VEX, dq_mode }
402 #define VexI4 { VEXI4_Fixup, 0}
403 #define EXdVex { OP_EX_Vex, d_mode }
404 #define EXdVexS { OP_EX_Vex, d_swap_mode }
405 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
406 #define EXqVex { OP_EX_Vex, q_mode }
407 #define EXqVexS { OP_EX_Vex, q_swap_mode }
408 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
409 #define EXVexW { OP_EX_VexW, x_mode }
410 #define EXdVexW { OP_EX_VexW, d_mode }
411 #define EXqVexW { OP_EX_VexW, q_mode }
412 #define EXVexImmW { OP_EX_VexImmW, x_mode }
413 #define XMVex { OP_XMM_Vex, 0 }
414 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
415 #define XMVexW { OP_XMM_VexW, 0 }
416 #define XMVexI4 { OP_REG_VexI4, x_mode }
417 #define PCLMUL { PCLMUL_Fixup, 0 }
418 #define VZERO { VZERO_Fixup, 0 }
419 #define VCMP { VCMP_Fixup, 0 }
420 #define VPCMP { VPCMP_Fixup, 0 }
422 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
423 #define EXxEVexS { OP_Rounding, evex_sae_mode }
425 #define XMask { OP_Mask, mask_mode }
426 #define MaskG { OP_G, mask_mode }
427 #define MaskE { OP_E, mask_mode }
428 #define MaskR { OP_R, mask_mode }
429 #define MaskVex { OP_VEX, mask_mode }
431 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
432 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
434 /* Used handle "rep" prefix for string instructions. */
435 #define Xbr { REP_Fixup, eSI_reg }
436 #define Xvr { REP_Fixup, eSI_reg }
437 #define Ybr { REP_Fixup, eDI_reg }
438 #define Yvr { REP_Fixup, eDI_reg }
439 #define Yzr { REP_Fixup, eDI_reg }
440 #define indirDXr { REP_Fixup, indir_dx_reg }
441 #define ALr { REP_Fixup, al_reg }
442 #define eAXr { REP_Fixup, eAX_reg }
444 /* Used handle HLE prefix for lockable instructions. */
445 #define Ebh1 { HLE_Fixup1, b_mode }
446 #define Evh1 { HLE_Fixup1, v_mode }
447 #define Ebh2 { HLE_Fixup2, b_mode }
448 #define Evh2 { HLE_Fixup2, v_mode }
449 #define Ebh3 { HLE_Fixup3, b_mode }
450 #define Evh3 { HLE_Fixup3, v_mode }
452 #define BND { BND_Fixup, 0 }
454 #define cond_jump_flag { NULL, cond_jump_mode }
455 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
457 /* bits in sizeflag */
458 #define SUFFIX_ALWAYS 4
466 /* byte operand with operand swapped */
468 /* byte operand, sign extend like 'T' suffix */
470 /* operand size depends on prefixes */
472 /* operand size depends on prefixes with operand swapped */
476 /* double word operand */
478 /* double word operand with operand swapped */
480 /* quad word operand */
482 /* quad word operand with operand swapped */
484 /* ten-byte operand */
486 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
487 broadcast enabled. */
489 /* Similar to x_mode, but with different EVEX mem shifts. */
491 /* Similar to x_mode, but with disabled broadcast. */
493 /* Similar to x_mode, but with operands swapped and disabled broadcast
496 /* 16-byte XMM operand */
498 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
499 memory operand (depending on vector length). Broadcast isn't
502 /* Same as xmmq_mode, but broadcast is allowed. */
503 evex_half_bcst_xmmq_mode,
504 /* XMM register or byte memory operand */
506 /* XMM register or word memory operand */
508 /* XMM register or double word memory operand */
510 /* XMM register or quad word memory operand */
512 /* XMM register or double/quad word memory operand, depending on
515 /* 16-byte XMM, word, double word or quad word operand. */
517 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
519 /* 32-byte YMM operand */
521 /* quad word, ymmword or zmmword memory operand. */
523 /* 32-byte YMM or 16-byte word operand */
525 /* d_mode in 32bit, q_mode in 64bit mode. */
527 /* pair of v_mode operands */
532 /* operand size depends on REX prefixes. */
534 /* registers like dq_mode, memory like w_mode. */
537 /* 4- or 6-byte pointer operand */
540 /* v_mode for stack-related opcodes. */
542 /* non-quad operand size depends on prefixes */
544 /* 16-byte operand */
546 /* registers like dq_mode, memory like b_mode. */
548 /* registers like dq_mode, memory like d_mode. */
550 /* normal vex mode */
552 /* 128bit vex mode */
554 /* 256bit vex mode */
556 /* operand size depends on the VEX.W bit. */
559 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
560 vex_vsib_d_w_dq_mode,
561 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
562 vex_vsib_q_w_dq_mode,
564 /* scalar, ignore vector length. */
566 /* like d_mode, ignore vector length. */
568 /* like d_swap_mode, ignore vector length. */
570 /* like q_mode, ignore vector length. */
572 /* like q_swap_mode, ignore vector length. */
574 /* like vex_mode, ignore vector length. */
576 /* like vex_w_dq_mode, ignore vector length. */
577 vex_scalar_w_dq_mode,
579 /* Static rounding. */
581 /* Supress all exceptions. */
584 /* Mask register operand. */
651 #define FLOAT NULL, { { NULL, FLOATCODE } }
653 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
654 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
655 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
656 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
657 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
658 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
659 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
660 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
661 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
662 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
663 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
664 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
665 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
779 MOD_VEX_0F12_PREFIX_0,
781 MOD_VEX_0F16_PREFIX_0,
797 MOD_VEX_0FD7_PREFIX_2,
798 MOD_VEX_0FE7_PREFIX_2,
799 MOD_VEX_0FF0_PREFIX_3,
800 MOD_VEX_0F381A_PREFIX_2,
801 MOD_VEX_0F382A_PREFIX_2,
802 MOD_VEX_0F382C_PREFIX_2,
803 MOD_VEX_0F382D_PREFIX_2,
804 MOD_VEX_0F382E_PREFIX_2,
805 MOD_VEX_0F382F_PREFIX_2,
806 MOD_VEX_0F385A_PREFIX_2,
807 MOD_VEX_0F388C_PREFIX_2,
808 MOD_VEX_0F388E_PREFIX_2,
810 MOD_EVEX_0F10_PREFIX_1,
811 MOD_EVEX_0F10_PREFIX_3,
812 MOD_EVEX_0F11_PREFIX_1,
813 MOD_EVEX_0F11_PREFIX_3,
814 MOD_EVEX_0F12_PREFIX_0,
815 MOD_EVEX_0F16_PREFIX_0,
816 MOD_EVEX_0F38C6_REG_1,
817 MOD_EVEX_0F38C6_REG_2,
818 MOD_EVEX_0F38C6_REG_5,
819 MOD_EVEX_0F38C6_REG_6,
820 MOD_EVEX_0F38C7_REG_1,
821 MOD_EVEX_0F38C7_REG_2,
822 MOD_EVEX_0F38C7_REG_5,
823 MOD_EVEX_0F38C7_REG_6
1013 PREFIX_VEX_0F71_REG_2,
1014 PREFIX_VEX_0F71_REG_4,
1015 PREFIX_VEX_0F71_REG_6,
1016 PREFIX_VEX_0F72_REG_2,
1017 PREFIX_VEX_0F72_REG_4,
1018 PREFIX_VEX_0F72_REG_6,
1019 PREFIX_VEX_0F73_REG_2,
1020 PREFIX_VEX_0F73_REG_3,
1021 PREFIX_VEX_0F73_REG_6,
1022 PREFIX_VEX_0F73_REG_7,
1193 PREFIX_VEX_0F38F3_REG_1,
1194 PREFIX_VEX_0F38F3_REG_2,
1195 PREFIX_VEX_0F38F3_REG_3,
1297 PREFIX_EVEX_0F72_REG_0,
1298 PREFIX_EVEX_0F72_REG_1,
1299 PREFIX_EVEX_0F72_REG_2,
1300 PREFIX_EVEX_0F72_REG_4,
1301 PREFIX_EVEX_0F72_REG_6,
1302 PREFIX_EVEX_0F73_REG_2,
1303 PREFIX_EVEX_0F73_REG_6,
1432 PREFIX_EVEX_0F38C6_REG_1,
1433 PREFIX_EVEX_0F38C6_REG_2,
1434 PREFIX_EVEX_0F38C6_REG_5,
1435 PREFIX_EVEX_0F38C6_REG_6,
1436 PREFIX_EVEX_0F38C7_REG_1,
1437 PREFIX_EVEX_0F38C7_REG_2,
1438 PREFIX_EVEX_0F38C7_REG_5,
1439 PREFIX_EVEX_0F38C7_REG_6,
1511 THREE_BYTE_0F38 = 0,
1539 VEX_LEN_0F10_P_1 = 0,
1543 VEX_LEN_0F12_P_0_M_0,
1544 VEX_LEN_0F12_P_0_M_1,
1547 VEX_LEN_0F16_P_0_M_0,
1548 VEX_LEN_0F16_P_0_M_1,
1594 VEX_LEN_0FAE_R_2_M_0,
1595 VEX_LEN_0FAE_R_3_M_0,
1604 VEX_LEN_0F381A_P_2_M_0,
1607 VEX_LEN_0F385A_P_2_M_0,
1614 VEX_LEN_0F38F3_R_1_P_0,
1615 VEX_LEN_0F38F3_R_2_P_0,
1616 VEX_LEN_0F38F3_R_3_P_0,
1660 VEX_LEN_0FXOP_08_CC,
1661 VEX_LEN_0FXOP_08_CD,
1662 VEX_LEN_0FXOP_08_CE,
1663 VEX_LEN_0FXOP_08_CF,
1664 VEX_LEN_0FXOP_08_EC,
1665 VEX_LEN_0FXOP_08_ED,
1666 VEX_LEN_0FXOP_08_EE,
1667 VEX_LEN_0FXOP_08_EF,
1668 VEX_LEN_0FXOP_09_80,
1702 VEX_W_0F41_P_0_LEN_1,
1703 VEX_W_0F42_P_0_LEN_1,
1704 VEX_W_0F44_P_0_LEN_0,
1705 VEX_W_0F45_P_0_LEN_1,
1706 VEX_W_0F46_P_0_LEN_1,
1707 VEX_W_0F47_P_0_LEN_1,
1708 VEX_W_0F4B_P_2_LEN_1,
1788 VEX_W_0F90_P_0_LEN_0,
1789 VEX_W_0F91_P_0_LEN_0,
1790 VEX_W_0F92_P_0_LEN_0,
1791 VEX_W_0F93_P_0_LEN_0,
1792 VEX_W_0F98_P_0_LEN_0,
1871 VEX_W_0F381A_P_2_M_0,
1883 VEX_W_0F382A_P_2_M_0,
1885 VEX_W_0F382C_P_2_M_0,
1886 VEX_W_0F382D_P_2_M_0,
1887 VEX_W_0F382E_P_2_M_0,
1888 VEX_W_0F382F_P_2_M_0,
1910 VEX_W_0F385A_P_2_M_0,
1938 VEX_W_0F3A30_P_2_LEN_0,
1939 VEX_W_0F3A32_P_2_LEN_0,
1959 EVEX_W_0F10_P_1_M_0,
1960 EVEX_W_0F10_P_1_M_1,
1962 EVEX_W_0F10_P_3_M_0,
1963 EVEX_W_0F10_P_3_M_1,
1965 EVEX_W_0F11_P_1_M_0,
1966 EVEX_W_0F11_P_1_M_1,
1968 EVEX_W_0F11_P_3_M_0,
1969 EVEX_W_0F11_P_3_M_1,
1970 EVEX_W_0F12_P_0_M_0,
1971 EVEX_W_0F12_P_0_M_1,
1981 EVEX_W_0F16_P_0_M_0,
1982 EVEX_W_0F16_P_0_M_1,
2043 EVEX_W_0F72_R_2_P_2,
2044 EVEX_W_0F72_R_6_P_2,
2045 EVEX_W_0F73_R_2_P_2,
2046 EVEX_W_0F73_R_6_P_2,
2119 EVEX_W_0F38C7_R_1_P_2,
2120 EVEX_W_0F38C7_R_2_P_2,
2121 EVEX_W_0F38C7_R_5_P_2,
2122 EVEX_W_0F38C7_R_6_P_2,
2146 typedef void (*op_rtn) (int bytemode, int sizeflag);
2157 /* Upper case letters in the instruction names here are macros.
2158 'A' => print 'b' if no register operands or suffix_always is true
2159 'B' => print 'b' if suffix_always is true
2160 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2162 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2163 suffix_always is true
2164 'E' => print 'e' if 32-bit form of jcxz
2165 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2166 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2167 'H' => print ",pt" or ",pn" branch hint
2168 'I' => honor following macro letter even in Intel mode (implemented only
2169 for some of the macro letters)
2171 'K' => print 'd' or 'q' if rex prefix is present.
2172 'L' => print 'l' if suffix_always is true
2173 'M' => print 'r' if intel_mnemonic is false.
2174 'N' => print 'n' if instruction has no wait "prefix"
2175 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2176 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2177 or suffix_always is true. print 'q' if rex prefix is present.
2178 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2180 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2181 'S' => print 'w', 'l' or 'q' if suffix_always is true
2182 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2183 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2184 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2185 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2186 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2187 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2188 suffix_always is true.
2189 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2190 '!' => change condition from true to false or from false to true.
2191 '%' => add 1 upper case letter to the macro.
2193 2 upper case letter macros:
2194 "XY" => print 'x' or 'y' if no register operands or suffix_always
2196 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2197 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2198 or suffix_always is true
2199 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2200 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2201 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2202 "LW" => print 'd', 'q' depending on the VEX.W bit
2204 Many of the above letters print nothing in Intel mode. See "putop"
2207 Braces '{' and '}', and vertical bars '|', indicate alternative
2208 mnemonic strings for AT&T and Intel. */
2210 static const struct dis386 dis386[] = {
2212 { "addB", { Ebh1, Gb } },
2213 { "addS", { Evh1, Gv } },
2214 { "addB", { Gb, EbS } },
2215 { "addS", { Gv, EvS } },
2216 { "addB", { AL, Ib } },
2217 { "addS", { eAX, Iv } },
2218 { X86_64_TABLE (X86_64_06) },
2219 { X86_64_TABLE (X86_64_07) },
2221 { "orB", { Ebh1, Gb } },
2222 { "orS", { Evh1, Gv } },
2223 { "orB", { Gb, EbS } },
2224 { "orS", { Gv, EvS } },
2225 { "orB", { AL, Ib } },
2226 { "orS", { eAX, Iv } },
2227 { X86_64_TABLE (X86_64_0D) },
2228 { Bad_Opcode }, /* 0x0f extended opcode escape */
2230 { "adcB", { Ebh1, Gb } },
2231 { "adcS", { Evh1, Gv } },
2232 { "adcB", { Gb, EbS } },
2233 { "adcS", { Gv, EvS } },
2234 { "adcB", { AL, Ib } },
2235 { "adcS", { eAX, Iv } },
2236 { X86_64_TABLE (X86_64_16) },
2237 { X86_64_TABLE (X86_64_17) },
2239 { "sbbB", { Ebh1, Gb } },
2240 { "sbbS", { Evh1, Gv } },
2241 { "sbbB", { Gb, EbS } },
2242 { "sbbS", { Gv, EvS } },
2243 { "sbbB", { AL, Ib } },
2244 { "sbbS", { eAX, Iv } },
2245 { X86_64_TABLE (X86_64_1E) },
2246 { X86_64_TABLE (X86_64_1F) },
2248 { "andB", { Ebh1, Gb } },
2249 { "andS", { Evh1, Gv } },
2250 { "andB", { Gb, EbS } },
2251 { "andS", { Gv, EvS } },
2252 { "andB", { AL, Ib } },
2253 { "andS", { eAX, Iv } },
2254 { Bad_Opcode }, /* SEG ES prefix */
2255 { X86_64_TABLE (X86_64_27) },
2257 { "subB", { Ebh1, Gb } },
2258 { "subS", { Evh1, Gv } },
2259 { "subB", { Gb, EbS } },
2260 { "subS", { Gv, EvS } },
2261 { "subB", { AL, Ib } },
2262 { "subS", { eAX, Iv } },
2263 { Bad_Opcode }, /* SEG CS prefix */
2264 { X86_64_TABLE (X86_64_2F) },
2266 { "xorB", { Ebh1, Gb } },
2267 { "xorS", { Evh1, Gv } },
2268 { "xorB", { Gb, EbS } },
2269 { "xorS", { Gv, EvS } },
2270 { "xorB", { AL, Ib } },
2271 { "xorS", { eAX, Iv } },
2272 { Bad_Opcode }, /* SEG SS prefix */
2273 { X86_64_TABLE (X86_64_37) },
2275 { "cmpB", { Eb, Gb } },
2276 { "cmpS", { Ev, Gv } },
2277 { "cmpB", { Gb, EbS } },
2278 { "cmpS", { Gv, EvS } },
2279 { "cmpB", { AL, Ib } },
2280 { "cmpS", { eAX, Iv } },
2281 { Bad_Opcode }, /* SEG DS prefix */
2282 { X86_64_TABLE (X86_64_3F) },
2284 { "inc{S|}", { RMeAX } },
2285 { "inc{S|}", { RMeCX } },
2286 { "inc{S|}", { RMeDX } },
2287 { "inc{S|}", { RMeBX } },
2288 { "inc{S|}", { RMeSP } },
2289 { "inc{S|}", { RMeBP } },
2290 { "inc{S|}", { RMeSI } },
2291 { "inc{S|}", { RMeDI } },
2293 { "dec{S|}", { RMeAX } },
2294 { "dec{S|}", { RMeCX } },
2295 { "dec{S|}", { RMeDX } },
2296 { "dec{S|}", { RMeBX } },
2297 { "dec{S|}", { RMeSP } },
2298 { "dec{S|}", { RMeBP } },
2299 { "dec{S|}", { RMeSI } },
2300 { "dec{S|}", { RMeDI } },
2302 { "pushV", { RMrAX } },
2303 { "pushV", { RMrCX } },
2304 { "pushV", { RMrDX } },
2305 { "pushV", { RMrBX } },
2306 { "pushV", { RMrSP } },
2307 { "pushV", { RMrBP } },
2308 { "pushV", { RMrSI } },
2309 { "pushV", { RMrDI } },
2311 { "popV", { RMrAX } },
2312 { "popV", { RMrCX } },
2313 { "popV", { RMrDX } },
2314 { "popV", { RMrBX } },
2315 { "popV", { RMrSP } },
2316 { "popV", { RMrBP } },
2317 { "popV", { RMrSI } },
2318 { "popV", { RMrDI } },
2320 { X86_64_TABLE (X86_64_60) },
2321 { X86_64_TABLE (X86_64_61) },
2322 { X86_64_TABLE (X86_64_62) },
2323 { X86_64_TABLE (X86_64_63) },
2324 { Bad_Opcode }, /* seg fs */
2325 { Bad_Opcode }, /* seg gs */
2326 { Bad_Opcode }, /* op size prefix */
2327 { Bad_Opcode }, /* adr size prefix */
2329 { "pushT", { sIv } },
2330 { "imulS", { Gv, Ev, Iv } },
2331 { "pushT", { sIbT } },
2332 { "imulS", { Gv, Ev, sIb } },
2333 { "ins{b|}", { Ybr, indirDX } },
2334 { X86_64_TABLE (X86_64_6D) },
2335 { "outs{b|}", { indirDXr, Xb } },
2336 { X86_64_TABLE (X86_64_6F) },
2338 { "joH", { Jb, BND, cond_jump_flag } },
2339 { "jnoH", { Jb, BND, cond_jump_flag } },
2340 { "jbH", { Jb, BND, cond_jump_flag } },
2341 { "jaeH", { Jb, BND, cond_jump_flag } },
2342 { "jeH", { Jb, BND, cond_jump_flag } },
2343 { "jneH", { Jb, BND, cond_jump_flag } },
2344 { "jbeH", { Jb, BND, cond_jump_flag } },
2345 { "jaH", { Jb, BND, cond_jump_flag } },
2347 { "jsH", { Jb, BND, cond_jump_flag } },
2348 { "jnsH", { Jb, BND, cond_jump_flag } },
2349 { "jpH", { Jb, BND, cond_jump_flag } },
2350 { "jnpH", { Jb, BND, cond_jump_flag } },
2351 { "jlH", { Jb, BND, cond_jump_flag } },
2352 { "jgeH", { Jb, BND, cond_jump_flag } },
2353 { "jleH", { Jb, BND, cond_jump_flag } },
2354 { "jgH", { Jb, BND, cond_jump_flag } },
2356 { REG_TABLE (REG_80) },
2357 { REG_TABLE (REG_81) },
2359 { REG_TABLE (REG_82) },
2360 { "testB", { Eb, Gb } },
2361 { "testS", { Ev, Gv } },
2362 { "xchgB", { Ebh2, Gb } },
2363 { "xchgS", { Evh2, Gv } },
2365 { "movB", { Ebh3, Gb } },
2366 { "movS", { Evh3, Gv } },
2367 { "movB", { Gb, EbS } },
2368 { "movS", { Gv, EvS } },
2369 { "movD", { Sv, Sw } },
2370 { MOD_TABLE (MOD_8D) },
2371 { "movD", { Sw, Sv } },
2372 { REG_TABLE (REG_8F) },
2374 { PREFIX_TABLE (PREFIX_90) },
2375 { "xchgS", { RMeCX, eAX } },
2376 { "xchgS", { RMeDX, eAX } },
2377 { "xchgS", { RMeBX, eAX } },
2378 { "xchgS", { RMeSP, eAX } },
2379 { "xchgS", { RMeBP, eAX } },
2380 { "xchgS", { RMeSI, eAX } },
2381 { "xchgS", { RMeDI, eAX } },
2383 { "cW{t|}R", { XX } },
2384 { "cR{t|}O", { XX } },
2385 { X86_64_TABLE (X86_64_9A) },
2386 { Bad_Opcode }, /* fwait */
2387 { "pushfT", { XX } },
2388 { "popfT", { XX } },
2392 { "mov%LB", { AL, Ob } },
2393 { "mov%LS", { eAX, Ov } },
2394 { "mov%LB", { Ob, AL } },
2395 { "mov%LS", { Ov, eAX } },
2396 { "movs{b|}", { Ybr, Xb } },
2397 { "movs{R|}", { Yvr, Xv } },
2398 { "cmps{b|}", { Xb, Yb } },
2399 { "cmps{R|}", { Xv, Yv } },
2401 { "testB", { AL, Ib } },
2402 { "testS", { eAX, Iv } },
2403 { "stosB", { Ybr, AL } },
2404 { "stosS", { Yvr, eAX } },
2405 { "lodsB", { ALr, Xb } },
2406 { "lodsS", { eAXr, Xv } },
2407 { "scasB", { AL, Yb } },
2408 { "scasS", { eAX, Yv } },
2410 { "movB", { RMAL, Ib } },
2411 { "movB", { RMCL, Ib } },
2412 { "movB", { RMDL, Ib } },
2413 { "movB", { RMBL, Ib } },
2414 { "movB", { RMAH, Ib } },
2415 { "movB", { RMCH, Ib } },
2416 { "movB", { RMDH, Ib } },
2417 { "movB", { RMBH, Ib } },
2419 { "mov%LV", { RMeAX, Iv64 } },
2420 { "mov%LV", { RMeCX, Iv64 } },
2421 { "mov%LV", { RMeDX, Iv64 } },
2422 { "mov%LV", { RMeBX, Iv64 } },
2423 { "mov%LV", { RMeSP, Iv64 } },
2424 { "mov%LV", { RMeBP, Iv64 } },
2425 { "mov%LV", { RMeSI, Iv64 } },
2426 { "mov%LV", { RMeDI, Iv64 } },
2428 { REG_TABLE (REG_C0) },
2429 { REG_TABLE (REG_C1) },
2430 { "retT", { Iw, BND } },
2431 { "retT", { BND } },
2432 { X86_64_TABLE (X86_64_C4) },
2433 { X86_64_TABLE (X86_64_C5) },
2434 { REG_TABLE (REG_C6) },
2435 { REG_TABLE (REG_C7) },
2437 { "enterT", { Iw, Ib } },
2438 { "leaveT", { XX } },
2439 { "Jret{|f}P", { Iw } },
2440 { "Jret{|f}P", { XX } },
2443 { X86_64_TABLE (X86_64_CE) },
2444 { "iretP", { XX } },
2446 { REG_TABLE (REG_D0) },
2447 { REG_TABLE (REG_D1) },
2448 { REG_TABLE (REG_D2) },
2449 { REG_TABLE (REG_D3) },
2450 { X86_64_TABLE (X86_64_D4) },
2451 { X86_64_TABLE (X86_64_D5) },
2453 { "xlat", { DSBX } },
2464 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
2465 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
2466 { "loopFH", { Jb, XX, loop_jcxz_flag } },
2467 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
2468 { "inB", { AL, Ib } },
2469 { "inG", { zAX, Ib } },
2470 { "outB", { Ib, AL } },
2471 { "outG", { Ib, zAX } },
2473 { "callT", { Jv, BND } },
2474 { "jmpT", { Jv, BND } },
2475 { X86_64_TABLE (X86_64_EA) },
2476 { "jmp", { Jb, BND } },
2477 { "inB", { AL, indirDX } },
2478 { "inG", { zAX, indirDX } },
2479 { "outB", { indirDX, AL } },
2480 { "outG", { indirDX, zAX } },
2482 { Bad_Opcode }, /* lock prefix */
2483 { "icebp", { XX } },
2484 { Bad_Opcode }, /* repne */
2485 { Bad_Opcode }, /* repz */
2488 { REG_TABLE (REG_F6) },
2489 { REG_TABLE (REG_F7) },
2497 { REG_TABLE (REG_FE) },
2498 { REG_TABLE (REG_FF) },
2501 static const struct dis386 dis386_twobyte[] = {
2503 { REG_TABLE (REG_0F00 ) },
2504 { REG_TABLE (REG_0F01 ) },
2505 { "larS", { Gv, Ew } },
2506 { "lslS", { Gv, Ew } },
2508 { "syscall", { XX } },
2510 { "sysretP", { XX } },
2513 { "wbinvd", { XX } },
2517 { REG_TABLE (REG_0F0D) },
2518 { "femms", { XX } },
2519 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
2521 { PREFIX_TABLE (PREFIX_0F10) },
2522 { PREFIX_TABLE (PREFIX_0F11) },
2523 { PREFIX_TABLE (PREFIX_0F12) },
2524 { MOD_TABLE (MOD_0F13) },
2525 { "unpcklpX", { XM, EXx } },
2526 { "unpckhpX", { XM, EXx } },
2527 { PREFIX_TABLE (PREFIX_0F16) },
2528 { MOD_TABLE (MOD_0F17) },
2530 { REG_TABLE (REG_0F18) },
2532 { PREFIX_TABLE (PREFIX_0F1A) },
2533 { PREFIX_TABLE (PREFIX_0F1B) },
2539 { MOD_TABLE (MOD_0F20) },
2540 { MOD_TABLE (MOD_0F21) },
2541 { MOD_TABLE (MOD_0F22) },
2542 { MOD_TABLE (MOD_0F23) },
2543 { MOD_TABLE (MOD_0F24) },
2545 { MOD_TABLE (MOD_0F26) },
2548 { "movapX", { XM, EXx } },
2549 { "movapX", { EXxS, XM } },
2550 { PREFIX_TABLE (PREFIX_0F2A) },
2551 { PREFIX_TABLE (PREFIX_0F2B) },
2552 { PREFIX_TABLE (PREFIX_0F2C) },
2553 { PREFIX_TABLE (PREFIX_0F2D) },
2554 { PREFIX_TABLE (PREFIX_0F2E) },
2555 { PREFIX_TABLE (PREFIX_0F2F) },
2557 { "wrmsr", { XX } },
2558 { "rdtsc", { XX } },
2559 { "rdmsr", { XX } },
2560 { "rdpmc", { XX } },
2561 { "sysenter", { XX } },
2562 { "sysexit", { XX } },
2564 { "getsec", { XX } },
2566 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2568 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2575 { "cmovoS", { Gv, Ev } },
2576 { "cmovnoS", { Gv, Ev } },
2577 { "cmovbS", { Gv, Ev } },
2578 { "cmovaeS", { Gv, Ev } },
2579 { "cmoveS", { Gv, Ev } },
2580 { "cmovneS", { Gv, Ev } },
2581 { "cmovbeS", { Gv, Ev } },
2582 { "cmovaS", { Gv, Ev } },
2584 { "cmovsS", { Gv, Ev } },
2585 { "cmovnsS", { Gv, Ev } },
2586 { "cmovpS", { Gv, Ev } },
2587 { "cmovnpS", { Gv, Ev } },
2588 { "cmovlS", { Gv, Ev } },
2589 { "cmovgeS", { Gv, Ev } },
2590 { "cmovleS", { Gv, Ev } },
2591 { "cmovgS", { Gv, Ev } },
2593 { MOD_TABLE (MOD_0F51) },
2594 { PREFIX_TABLE (PREFIX_0F51) },
2595 { PREFIX_TABLE (PREFIX_0F52) },
2596 { PREFIX_TABLE (PREFIX_0F53) },
2597 { "andpX", { XM, EXx } },
2598 { "andnpX", { XM, EXx } },
2599 { "orpX", { XM, EXx } },
2600 { "xorpX", { XM, EXx } },
2602 { PREFIX_TABLE (PREFIX_0F58) },
2603 { PREFIX_TABLE (PREFIX_0F59) },
2604 { PREFIX_TABLE (PREFIX_0F5A) },
2605 { PREFIX_TABLE (PREFIX_0F5B) },
2606 { PREFIX_TABLE (PREFIX_0F5C) },
2607 { PREFIX_TABLE (PREFIX_0F5D) },
2608 { PREFIX_TABLE (PREFIX_0F5E) },
2609 { PREFIX_TABLE (PREFIX_0F5F) },
2611 { PREFIX_TABLE (PREFIX_0F60) },
2612 { PREFIX_TABLE (PREFIX_0F61) },
2613 { PREFIX_TABLE (PREFIX_0F62) },
2614 { "packsswb", { MX, EM } },
2615 { "pcmpgtb", { MX, EM } },
2616 { "pcmpgtw", { MX, EM } },
2617 { "pcmpgtd", { MX, EM } },
2618 { "packuswb", { MX, EM } },
2620 { "punpckhbw", { MX, EM } },
2621 { "punpckhwd", { MX, EM } },
2622 { "punpckhdq", { MX, EM } },
2623 { "packssdw", { MX, EM } },
2624 { PREFIX_TABLE (PREFIX_0F6C) },
2625 { PREFIX_TABLE (PREFIX_0F6D) },
2626 { "movK", { MX, Edq } },
2627 { PREFIX_TABLE (PREFIX_0F6F) },
2629 { PREFIX_TABLE (PREFIX_0F70) },
2630 { REG_TABLE (REG_0F71) },
2631 { REG_TABLE (REG_0F72) },
2632 { REG_TABLE (REG_0F73) },
2633 { "pcmpeqb", { MX, EM } },
2634 { "pcmpeqw", { MX, EM } },
2635 { "pcmpeqd", { MX, EM } },
2638 { PREFIX_TABLE (PREFIX_0F78) },
2639 { PREFIX_TABLE (PREFIX_0F79) },
2640 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2642 { PREFIX_TABLE (PREFIX_0F7C) },
2643 { PREFIX_TABLE (PREFIX_0F7D) },
2644 { PREFIX_TABLE (PREFIX_0F7E) },
2645 { PREFIX_TABLE (PREFIX_0F7F) },
2647 { "joH", { Jv, BND, cond_jump_flag } },
2648 { "jnoH", { Jv, BND, cond_jump_flag } },
2649 { "jbH", { Jv, BND, cond_jump_flag } },
2650 { "jaeH", { Jv, BND, cond_jump_flag } },
2651 { "jeH", { Jv, BND, cond_jump_flag } },
2652 { "jneH", { Jv, BND, cond_jump_flag } },
2653 { "jbeH", { Jv, BND, cond_jump_flag } },
2654 { "jaH", { Jv, BND, cond_jump_flag } },
2656 { "jsH", { Jv, BND, cond_jump_flag } },
2657 { "jnsH", { Jv, BND, cond_jump_flag } },
2658 { "jpH", { Jv, BND, cond_jump_flag } },
2659 { "jnpH", { Jv, BND, cond_jump_flag } },
2660 { "jlH", { Jv, BND, cond_jump_flag } },
2661 { "jgeH", { Jv, BND, cond_jump_flag } },
2662 { "jleH", { Jv, BND, cond_jump_flag } },
2663 { "jgH", { Jv, BND, cond_jump_flag } },
2666 { "setno", { Eb } },
2668 { "setae", { Eb } },
2670 { "setne", { Eb } },
2671 { "setbe", { Eb } },
2675 { "setns", { Eb } },
2677 { "setnp", { Eb } },
2679 { "setge", { Eb } },
2680 { "setle", { Eb } },
2683 { "pushT", { fs } },
2685 { "cpuid", { XX } },
2686 { "btS", { Ev, Gv } },
2687 { "shldS", { Ev, Gv, Ib } },
2688 { "shldS", { Ev, Gv, CL } },
2689 { REG_TABLE (REG_0FA6) },
2690 { REG_TABLE (REG_0FA7) },
2692 { "pushT", { gs } },
2695 { "btsS", { Evh1, Gv } },
2696 { "shrdS", { Ev, Gv, Ib } },
2697 { "shrdS", { Ev, Gv, CL } },
2698 { REG_TABLE (REG_0FAE) },
2699 { "imulS", { Gv, Ev } },
2701 { "cmpxchgB", { Ebh1, Gb } },
2702 { "cmpxchgS", { Evh1, Gv } },
2703 { MOD_TABLE (MOD_0FB2) },
2704 { "btrS", { Evh1, Gv } },
2705 { MOD_TABLE (MOD_0FB4) },
2706 { MOD_TABLE (MOD_0FB5) },
2707 { "movz{bR|x}", { Gv, Eb } },
2708 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
2710 { PREFIX_TABLE (PREFIX_0FB8) },
2712 { REG_TABLE (REG_0FBA) },
2713 { "btcS", { Evh1, Gv } },
2714 { PREFIX_TABLE (PREFIX_0FBC) },
2715 { PREFIX_TABLE (PREFIX_0FBD) },
2716 { "movs{bR|x}", { Gv, Eb } },
2717 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
2719 { "xaddB", { Ebh1, Gb } },
2720 { "xaddS", { Evh1, Gv } },
2721 { PREFIX_TABLE (PREFIX_0FC2) },
2722 { PREFIX_TABLE (PREFIX_0FC3) },
2723 { "pinsrw", { MX, Edqw, Ib } },
2724 { "pextrw", { Gdq, MS, Ib } },
2725 { "shufpX", { XM, EXx, Ib } },
2726 { REG_TABLE (REG_0FC7) },
2728 { "bswap", { RMeAX } },
2729 { "bswap", { RMeCX } },
2730 { "bswap", { RMeDX } },
2731 { "bswap", { RMeBX } },
2732 { "bswap", { RMeSP } },
2733 { "bswap", { RMeBP } },
2734 { "bswap", { RMeSI } },
2735 { "bswap", { RMeDI } },
2737 { PREFIX_TABLE (PREFIX_0FD0) },
2738 { "psrlw", { MX, EM } },
2739 { "psrld", { MX, EM } },
2740 { "psrlq", { MX, EM } },
2741 { "paddq", { MX, EM } },
2742 { "pmullw", { MX, EM } },
2743 { PREFIX_TABLE (PREFIX_0FD6) },
2744 { MOD_TABLE (MOD_0FD7) },
2746 { "psubusb", { MX, EM } },
2747 { "psubusw", { MX, EM } },
2748 { "pminub", { MX, EM } },
2749 { "pand", { MX, EM } },
2750 { "paddusb", { MX, EM } },
2751 { "paddusw", { MX, EM } },
2752 { "pmaxub", { MX, EM } },
2753 { "pandn", { MX, EM } },
2755 { "pavgb", { MX, EM } },
2756 { "psraw", { MX, EM } },
2757 { "psrad", { MX, EM } },
2758 { "pavgw", { MX, EM } },
2759 { "pmulhuw", { MX, EM } },
2760 { "pmulhw", { MX, EM } },
2761 { PREFIX_TABLE (PREFIX_0FE6) },
2762 { PREFIX_TABLE (PREFIX_0FE7) },
2764 { "psubsb", { MX, EM } },
2765 { "psubsw", { MX, EM } },
2766 { "pminsw", { MX, EM } },
2767 { "por", { MX, EM } },
2768 { "paddsb", { MX, EM } },
2769 { "paddsw", { MX, EM } },
2770 { "pmaxsw", { MX, EM } },
2771 { "pxor", { MX, EM } },
2773 { PREFIX_TABLE (PREFIX_0FF0) },
2774 { "psllw", { MX, EM } },
2775 { "pslld", { MX, EM } },
2776 { "psllq", { MX, EM } },
2777 { "pmuludq", { MX, EM } },
2778 { "pmaddwd", { MX, EM } },
2779 { "psadbw", { MX, EM } },
2780 { PREFIX_TABLE (PREFIX_0FF7) },
2782 { "psubb", { MX, EM } },
2783 { "psubw", { MX, EM } },
2784 { "psubd", { MX, EM } },
2785 { "psubq", { MX, EM } },
2786 { "paddb", { MX, EM } },
2787 { "paddw", { MX, EM } },
2788 { "paddd", { MX, EM } },
2792 static const unsigned char onebyte_has_modrm[256] = {
2793 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2794 /* ------------------------------- */
2795 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2796 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2797 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2798 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2799 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2800 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2801 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2802 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2803 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2804 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2805 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2806 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2807 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2808 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2809 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2810 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2811 /* ------------------------------- */
2812 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2815 static const unsigned char twobyte_has_modrm[256] = {
2816 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2817 /* ------------------------------- */
2818 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2819 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2820 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2821 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2822 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2823 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2824 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2825 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2826 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2827 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2828 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2829 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2830 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2831 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2832 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2833 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
2834 /* ------------------------------- */
2835 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2838 static char obuf[100];
2840 static char *mnemonicendp;
2841 static char scratchbuf[100];
2842 static unsigned char *start_codep;
2843 static unsigned char *insn_codep;
2844 static unsigned char *codep;
2845 static int last_lock_prefix;
2846 static int last_repz_prefix;
2847 static int last_repnz_prefix;
2848 static int last_data_prefix;
2849 static int last_addr_prefix;
2850 static int last_rex_prefix;
2851 static int last_seg_prefix;
2852 #define MAX_CODE_LENGTH 15
2853 /* We can up to 14 prefixes since the maximum instruction length is
2855 static int all_prefixes[MAX_CODE_LENGTH - 1];
2856 static disassemble_info *the_info;
2864 static unsigned char need_modrm;
2874 int register_specifier;
2881 int mask_register_specifier;
2887 static unsigned char need_vex;
2888 static unsigned char need_vex_reg;
2889 static unsigned char vex_w_done;
2897 /* If we are accessing mod/rm/reg without need_modrm set, then the
2898 values are stale. Hitting this abort likely indicates that you
2899 need to update onebyte_has_modrm or twobyte_has_modrm. */
2900 #define MODRM_CHECK if (!need_modrm) abort ()
2902 static const char **names64;
2903 static const char **names32;
2904 static const char **names16;
2905 static const char **names8;
2906 static const char **names8rex;
2907 static const char **names_seg;
2908 static const char *index64;
2909 static const char *index32;
2910 static const char **index16;
2911 static const char **names_bnd;
2913 static const char *intel_names64[] = {
2914 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2915 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2917 static const char *intel_names32[] = {
2918 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2919 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2921 static const char *intel_names16[] = {
2922 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2923 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2925 static const char *intel_names8[] = {
2926 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2928 static const char *intel_names8rex[] = {
2929 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2930 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2932 static const char *intel_names_seg[] = {
2933 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2935 static const char *intel_index64 = "riz";
2936 static const char *intel_index32 = "eiz";
2937 static const char *intel_index16[] = {
2938 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2941 static const char *att_names64[] = {
2942 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2943 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2945 static const char *att_names32[] = {
2946 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2947 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2949 static const char *att_names16[] = {
2950 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2951 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2953 static const char *att_names8[] = {
2954 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2956 static const char *att_names8rex[] = {
2957 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2958 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2960 static const char *att_names_seg[] = {
2961 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2963 static const char *att_index64 = "%riz";
2964 static const char *att_index32 = "%eiz";
2965 static const char *att_index16[] = {
2966 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2969 static const char **names_mm;
2970 static const char *intel_names_mm[] = {
2971 "mm0", "mm1", "mm2", "mm3",
2972 "mm4", "mm5", "mm6", "mm7"
2974 static const char *att_names_mm[] = {
2975 "%mm0", "%mm1", "%mm2", "%mm3",
2976 "%mm4", "%mm5", "%mm6", "%mm7"
2979 static const char *intel_names_bnd[] = {
2980 "bnd0", "bnd1", "bnd2", "bnd3"
2983 static const char *att_names_bnd[] = {
2984 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2987 static const char **names_xmm;
2988 static const char *intel_names_xmm[] = {
2989 "xmm0", "xmm1", "xmm2", "xmm3",
2990 "xmm4", "xmm5", "xmm6", "xmm7",
2991 "xmm8", "xmm9", "xmm10", "xmm11",
2992 "xmm12", "xmm13", "xmm14", "xmm15",
2993 "xmm16", "xmm17", "xmm18", "xmm19",
2994 "xmm20", "xmm21", "xmm22", "xmm23",
2995 "xmm24", "xmm25", "xmm26", "xmm27",
2996 "xmm28", "xmm29", "xmm30", "xmm31"
2998 static const char *att_names_xmm[] = {
2999 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3000 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3001 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3002 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3003 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3004 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3005 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3006 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3009 static const char **names_ymm;
3010 static const char *intel_names_ymm[] = {
3011 "ymm0", "ymm1", "ymm2", "ymm3",
3012 "ymm4", "ymm5", "ymm6", "ymm7",
3013 "ymm8", "ymm9", "ymm10", "ymm11",
3014 "ymm12", "ymm13", "ymm14", "ymm15",
3015 "ymm16", "ymm17", "ymm18", "ymm19",
3016 "ymm20", "ymm21", "ymm22", "ymm23",
3017 "ymm24", "ymm25", "ymm26", "ymm27",
3018 "ymm28", "ymm29", "ymm30", "ymm31"
3020 static const char *att_names_ymm[] = {
3021 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3022 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3023 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3024 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3025 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3026 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3027 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3028 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3031 static const char **names_zmm;
3032 static const char *intel_names_zmm[] = {
3033 "zmm0", "zmm1", "zmm2", "zmm3",
3034 "zmm4", "zmm5", "zmm6", "zmm7",
3035 "zmm8", "zmm9", "zmm10", "zmm11",
3036 "zmm12", "zmm13", "zmm14", "zmm15",
3037 "zmm16", "zmm17", "zmm18", "zmm19",
3038 "zmm20", "zmm21", "zmm22", "zmm23",
3039 "zmm24", "zmm25", "zmm26", "zmm27",
3040 "zmm28", "zmm29", "zmm30", "zmm31"
3042 static const char *att_names_zmm[] = {
3043 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3044 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3045 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3046 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3047 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3048 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3049 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3050 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3053 static const char **names_mask;
3054 static const char *intel_names_mask[] = {
3055 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3057 static const char *att_names_mask[] = {
3058 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3061 static const char *names_rounding[] =
3069 static const struct dis386 reg_table[][8] = {
3072 { "addA", { Ebh1, Ib } },
3073 { "orA", { Ebh1, Ib } },
3074 { "adcA", { Ebh1, Ib } },
3075 { "sbbA", { Ebh1, Ib } },
3076 { "andA", { Ebh1, Ib } },
3077 { "subA", { Ebh1, Ib } },
3078 { "xorA", { Ebh1, Ib } },
3079 { "cmpA", { Eb, Ib } },
3083 { "addQ", { Evh1, Iv } },
3084 { "orQ", { Evh1, Iv } },
3085 { "adcQ", { Evh1, Iv } },
3086 { "sbbQ", { Evh1, Iv } },
3087 { "andQ", { Evh1, Iv } },
3088 { "subQ", { Evh1, Iv } },
3089 { "xorQ", { Evh1, Iv } },
3090 { "cmpQ", { Ev, Iv } },
3094 { "addQ", { Evh1, sIb } },
3095 { "orQ", { Evh1, sIb } },
3096 { "adcQ", { Evh1, sIb } },
3097 { "sbbQ", { Evh1, sIb } },
3098 { "andQ", { Evh1, sIb } },
3099 { "subQ", { Evh1, sIb } },
3100 { "xorQ", { Evh1, sIb } },
3101 { "cmpQ", { Ev, sIb } },
3105 { "popU", { stackEv } },
3106 { XOP_8F_TABLE (XOP_09) },
3110 { XOP_8F_TABLE (XOP_09) },
3114 { "rolA", { Eb, Ib } },
3115 { "rorA", { Eb, Ib } },
3116 { "rclA", { Eb, Ib } },
3117 { "rcrA", { Eb, Ib } },
3118 { "shlA", { Eb, Ib } },
3119 { "shrA", { Eb, Ib } },
3121 { "sarA", { Eb, Ib } },
3125 { "rolQ", { Ev, Ib } },
3126 { "rorQ", { Ev, Ib } },
3127 { "rclQ", { Ev, Ib } },
3128 { "rcrQ", { Ev, Ib } },
3129 { "shlQ", { Ev, Ib } },
3130 { "shrQ", { Ev, Ib } },
3132 { "sarQ", { Ev, Ib } },
3136 { "movA", { Ebh3, Ib } },
3143 { MOD_TABLE (MOD_C6_REG_7) },
3147 { "movQ", { Evh3, Iv } },
3154 { MOD_TABLE (MOD_C7_REG_7) },
3158 { "rolA", { Eb, I1 } },
3159 { "rorA", { Eb, I1 } },
3160 { "rclA", { Eb, I1 } },
3161 { "rcrA", { Eb, I1 } },
3162 { "shlA", { Eb, I1 } },
3163 { "shrA", { Eb, I1 } },
3165 { "sarA", { Eb, I1 } },
3169 { "rolQ", { Ev, I1 } },
3170 { "rorQ", { Ev, I1 } },
3171 { "rclQ", { Ev, I1 } },
3172 { "rcrQ", { Ev, I1 } },
3173 { "shlQ", { Ev, I1 } },
3174 { "shrQ", { Ev, I1 } },
3176 { "sarQ", { Ev, I1 } },
3180 { "rolA", { Eb, CL } },
3181 { "rorA", { Eb, CL } },
3182 { "rclA", { Eb, CL } },
3183 { "rcrA", { Eb, CL } },
3184 { "shlA", { Eb, CL } },
3185 { "shrA", { Eb, CL } },
3187 { "sarA", { Eb, CL } },
3191 { "rolQ", { Ev, CL } },
3192 { "rorQ", { Ev, CL } },
3193 { "rclQ", { Ev, CL } },
3194 { "rcrQ", { Ev, CL } },
3195 { "shlQ", { Ev, CL } },
3196 { "shrQ", { Ev, CL } },
3198 { "sarQ", { Ev, CL } },
3202 { "testA", { Eb, Ib } },
3204 { "notA", { Ebh1 } },
3205 { "negA", { Ebh1 } },
3206 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
3207 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
3208 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
3209 { "idivA", { Eb } }, /* and idiv for consistency. */
3213 { "testQ", { Ev, Iv } },
3215 { "notQ", { Evh1 } },
3216 { "negQ", { Evh1 } },
3217 { "mulQ", { Ev } }, /* Don't print the implicit register. */
3218 { "imulQ", { Ev } },
3220 { "idivQ", { Ev } },
3224 { "incA", { Ebh1 } },
3225 { "decA", { Ebh1 } },
3229 { "incQ", { Evh1 } },
3230 { "decQ", { Evh1 } },
3231 { "call{T|}", { indirEv, BND } },
3232 { "Jcall{T|}", { indirEp } },
3233 { "jmp{T|}", { indirEv, BND } },
3234 { "Jjmp{T|}", { indirEp } },
3235 { "pushU", { stackEv } },
3240 { "sldtD", { Sv } },
3251 { MOD_TABLE (MOD_0F01_REG_0) },
3252 { MOD_TABLE (MOD_0F01_REG_1) },
3253 { MOD_TABLE (MOD_0F01_REG_2) },
3254 { MOD_TABLE (MOD_0F01_REG_3) },
3255 { "smswD", { Sv } },
3258 { MOD_TABLE (MOD_0F01_REG_7) },
3262 { "prefetch", { Mb } },
3263 { "prefetchw", { Mb } },
3264 { "prefetchwt1", { Mb } },
3265 { "prefetch", { Mb } },
3266 { "prefetch", { Mb } },
3267 { "prefetch", { Mb } },
3268 { "prefetch", { Mb } },
3269 { "prefetch", { Mb } },
3273 { MOD_TABLE (MOD_0F18_REG_0) },
3274 { MOD_TABLE (MOD_0F18_REG_1) },
3275 { MOD_TABLE (MOD_0F18_REG_2) },
3276 { MOD_TABLE (MOD_0F18_REG_3) },
3277 { MOD_TABLE (MOD_0F18_REG_4) },
3278 { MOD_TABLE (MOD_0F18_REG_5) },
3279 { MOD_TABLE (MOD_0F18_REG_6) },
3280 { MOD_TABLE (MOD_0F18_REG_7) },
3286 { MOD_TABLE (MOD_0F71_REG_2) },
3288 { MOD_TABLE (MOD_0F71_REG_4) },
3290 { MOD_TABLE (MOD_0F71_REG_6) },
3296 { MOD_TABLE (MOD_0F72_REG_2) },
3298 { MOD_TABLE (MOD_0F72_REG_4) },
3300 { MOD_TABLE (MOD_0F72_REG_6) },
3306 { MOD_TABLE (MOD_0F73_REG_2) },
3307 { MOD_TABLE (MOD_0F73_REG_3) },
3310 { MOD_TABLE (MOD_0F73_REG_6) },
3311 { MOD_TABLE (MOD_0F73_REG_7) },
3315 { "montmul", { { OP_0f07, 0 } } },
3316 { "xsha1", { { OP_0f07, 0 } } },
3317 { "xsha256", { { OP_0f07, 0 } } },
3321 { "xstore-rng", { { OP_0f07, 0 } } },
3322 { "xcrypt-ecb", { { OP_0f07, 0 } } },
3323 { "xcrypt-cbc", { { OP_0f07, 0 } } },
3324 { "xcrypt-ctr", { { OP_0f07, 0 } } },
3325 { "xcrypt-cfb", { { OP_0f07, 0 } } },
3326 { "xcrypt-ofb", { { OP_0f07, 0 } } },
3330 { MOD_TABLE (MOD_0FAE_REG_0) },
3331 { MOD_TABLE (MOD_0FAE_REG_1) },
3332 { MOD_TABLE (MOD_0FAE_REG_2) },
3333 { MOD_TABLE (MOD_0FAE_REG_3) },
3334 { MOD_TABLE (MOD_0FAE_REG_4) },
3335 { MOD_TABLE (MOD_0FAE_REG_5) },
3336 { MOD_TABLE (MOD_0FAE_REG_6) },
3337 { MOD_TABLE (MOD_0FAE_REG_7) },
3345 { "btQ", { Ev, Ib } },
3346 { "btsQ", { Evh1, Ib } },
3347 { "btrQ", { Evh1, Ib } },
3348 { "btcQ", { Evh1, Ib } },
3353 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
3358 { MOD_TABLE (MOD_0FC7_REG_6) },
3359 { MOD_TABLE (MOD_0FC7_REG_7) },
3365 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3367 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3369 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3375 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3377 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3379 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3385 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3386 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3389 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3390 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3396 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3397 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3399 /* REG_VEX_0F38F3 */
3402 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3403 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3404 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3408 { "llwpcb", { { OP_LWPCB_E, 0 } } },
3409 { "slwpcb", { { OP_LWPCB_E, 0 } } },
3413 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
3414 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
3416 /* REG_XOP_TBM_01 */
3419 { "blcfill", { { OP_LWP_E, 0 }, Ev } },
3420 { "blsfill", { { OP_LWP_E, 0 }, Ev } },
3421 { "blcs", { { OP_LWP_E, 0 }, Ev } },
3422 { "tzmsk", { { OP_LWP_E, 0 }, Ev } },
3423 { "blcic", { { OP_LWP_E, 0 }, Ev } },
3424 { "blsic", { { OP_LWP_E, 0 }, Ev } },
3425 { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
3427 /* REG_XOP_TBM_02 */
3430 { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
3435 { "blci", { { OP_LWP_E, 0 }, Ev } },
3437 #define NEED_REG_TABLE
3438 #include "i386-dis-evex.h"
3439 #undef NEED_REG_TABLE
3442 static const struct dis386 prefix_table[][4] = {
3445 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3446 { "pause", { XX } },
3447 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3452 { "movups", { XM, EXx } },
3453 { "movss", { XM, EXd } },
3454 { "movupd", { XM, EXx } },
3455 { "movsd", { XM, EXq } },
3460 { "movups", { EXxS, XM } },
3461 { "movss", { EXdS, XM } },
3462 { "movupd", { EXxS, XM } },
3463 { "movsd", { EXqS, XM } },
3468 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3469 { "movsldup", { XM, EXx } },
3470 { "movlpd", { XM, EXq } },
3471 { "movddup", { XM, EXq } },
3476 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3477 { "movshdup", { XM, EXx } },
3478 { "movhpd", { XM, EXq } },
3483 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3484 { "bndcl", { Gbnd, Ev_bnd } },
3485 { "bndmov", { Gbnd, Ebnd } },
3486 { "bndcu", { Gbnd, Ev_bnd } },
3491 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3492 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3493 { "bndmov", { Ebnd, Gbnd } },
3494 { "bndcn", { Gbnd, Ev_bnd } },
3499 { "cvtpi2ps", { XM, EMCq } },
3500 { "cvtsi2ss%LQ", { XM, Ev } },
3501 { "cvtpi2pd", { XM, EMCq } },
3502 { "cvtsi2sd%LQ", { XM, Ev } },
3507 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3508 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3509 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3510 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3515 { "cvttps2pi", { MXC, EXq } },
3516 { "cvttss2siY", { Gv, EXd } },
3517 { "cvttpd2pi", { MXC, EXx } },
3518 { "cvttsd2siY", { Gv, EXq } },
3523 { "cvtps2pi", { MXC, EXq } },
3524 { "cvtss2siY", { Gv, EXd } },
3525 { "cvtpd2pi", { MXC, EXx } },
3526 { "cvtsd2siY", { Gv, EXq } },
3531 { "ucomiss",{ XM, EXd } },
3533 { "ucomisd",{ XM, EXq } },
3538 { "comiss", { XM, EXd } },
3540 { "comisd", { XM, EXq } },
3545 { "sqrtps", { XM, EXx } },
3546 { "sqrtss", { XM, EXd } },
3547 { "sqrtpd", { XM, EXx } },
3548 { "sqrtsd", { XM, EXq } },
3553 { "rsqrtps",{ XM, EXx } },
3554 { "rsqrtss",{ XM, EXd } },
3559 { "rcpps", { XM, EXx } },
3560 { "rcpss", { XM, EXd } },
3565 { "addps", { XM, EXx } },
3566 { "addss", { XM, EXd } },
3567 { "addpd", { XM, EXx } },
3568 { "addsd", { XM, EXq } },
3573 { "mulps", { XM, EXx } },
3574 { "mulss", { XM, EXd } },
3575 { "mulpd", { XM, EXx } },
3576 { "mulsd", { XM, EXq } },
3581 { "cvtps2pd", { XM, EXq } },
3582 { "cvtss2sd", { XM, EXd } },
3583 { "cvtpd2ps", { XM, EXx } },
3584 { "cvtsd2ss", { XM, EXq } },
3589 { "cvtdq2ps", { XM, EXx } },
3590 { "cvttps2dq", { XM, EXx } },
3591 { "cvtps2dq", { XM, EXx } },
3596 { "subps", { XM, EXx } },
3597 { "subss", { XM, EXd } },
3598 { "subpd", { XM, EXx } },
3599 { "subsd", { XM, EXq } },
3604 { "minps", { XM, EXx } },
3605 { "minss", { XM, EXd } },
3606 { "minpd", { XM, EXx } },
3607 { "minsd", { XM, EXq } },
3612 { "divps", { XM, EXx } },
3613 { "divss", { XM, EXd } },
3614 { "divpd", { XM, EXx } },
3615 { "divsd", { XM, EXq } },
3620 { "maxps", { XM, EXx } },
3621 { "maxss", { XM, EXd } },
3622 { "maxpd", { XM, EXx } },
3623 { "maxsd", { XM, EXq } },
3628 { "punpcklbw",{ MX, EMd } },
3630 { "punpcklbw",{ MX, EMx } },
3635 { "punpcklwd",{ MX, EMd } },
3637 { "punpcklwd",{ MX, EMx } },
3642 { "punpckldq",{ MX, EMd } },
3644 { "punpckldq",{ MX, EMx } },
3651 { "punpcklqdq", { XM, EXx } },
3658 { "punpckhqdq", { XM, EXx } },
3663 { "movq", { MX, EM } },
3664 { "movdqu", { XM, EXx } },
3665 { "movdqa", { XM, EXx } },
3670 { "pshufw", { MX, EM, Ib } },
3671 { "pshufhw",{ XM, EXx, Ib } },
3672 { "pshufd", { XM, EXx, Ib } },
3673 { "pshuflw",{ XM, EXx, Ib } },
3676 /* PREFIX_0F73_REG_3 */
3680 { "psrldq", { XS, Ib } },
3683 /* PREFIX_0F73_REG_7 */
3687 { "pslldq", { XS, Ib } },
3692 {"vmread", { Em, Gm } },
3694 {"extrq", { XS, Ib, Ib } },
3695 {"insertq", { XM, XS, Ib, Ib } },
3700 {"vmwrite", { Gm, Em } },
3702 {"extrq", { XM, XS } },
3703 {"insertq", { XM, XS } },
3710 { "haddpd", { XM, EXx } },
3711 { "haddps", { XM, EXx } },
3718 { "hsubpd", { XM, EXx } },
3719 { "hsubps", { XM, EXx } },
3724 { "movK", { Edq, MX } },
3725 { "movq", { XM, EXq } },
3726 { "movK", { Edq, XM } },
3731 { "movq", { EMS, MX } },
3732 { "movdqu", { EXxS, XM } },
3733 { "movdqa", { EXxS, XM } },
3736 /* PREFIX_0FAE_REG_0 */
3739 { "rdfsbase", { Ev } },
3742 /* PREFIX_0FAE_REG_1 */
3745 { "rdgsbase", { Ev } },
3748 /* PREFIX_0FAE_REG_2 */
3751 { "wrfsbase", { Ev } },
3754 /* PREFIX_0FAE_REG_3 */
3757 { "wrgsbase", { Ev } },
3763 { "popcntS", { Gv, Ev } },
3768 { "bsfS", { Gv, Ev } },
3769 { "tzcntS", { Gv, Ev } },
3770 { "bsfS", { Gv, Ev } },
3775 { "bsrS", { Gv, Ev } },
3776 { "lzcntS", { Gv, Ev } },
3777 { "bsrS", { Gv, Ev } },
3782 { "cmpps", { XM, EXx, CMP } },
3783 { "cmpss", { XM, EXd, CMP } },
3784 { "cmppd", { XM, EXx, CMP } },
3785 { "cmpsd", { XM, EXq, CMP } },
3790 { "movntiS", { Ma, Gv } },
3793 /* PREFIX_0FC7_REG_6 */
3795 { "vmptrld",{ Mq } },
3796 { "vmxon", { Mq } },
3797 { "vmclear",{ Mq } },
3804 { "addsubpd", { XM, EXx } },
3805 { "addsubps", { XM, EXx } },
3811 { "movq2dq",{ XM, MS } },
3812 { "movq", { EXqS, XM } },
3813 { "movdq2q",{ MX, XS } },
3819 { "cvtdq2pd", { XM, EXq } },
3820 { "cvttpd2dq", { XM, EXx } },
3821 { "cvtpd2dq", { XM, EXx } },
3826 { "movntq", { Mq, MX } },
3828 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3836 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3841 { "maskmovq", { MX, MS } },
3843 { "maskmovdqu", { XM, XS } },
3850 { "pblendvb", { XM, EXx, XMM0 } },
3857 { "blendvps", { XM, EXx, XMM0 } },
3864 { "blendvpd", { XM, EXx, XMM0 } },
3871 { "ptest", { XM, EXx } },
3878 { "pmovsxbw", { XM, EXq } },
3885 { "pmovsxbd", { XM, EXd } },
3892 { "pmovsxbq", { XM, EXw } },
3899 { "pmovsxwd", { XM, EXq } },
3906 { "pmovsxwq", { XM, EXd } },
3913 { "pmovsxdq", { XM, EXq } },
3920 { "pmuldq", { XM, EXx } },
3927 { "pcmpeqq", { XM, EXx } },
3934 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3941 { "packusdw", { XM, EXx } },
3948 { "pmovzxbw", { XM, EXq } },
3955 { "pmovzxbd", { XM, EXd } },
3962 { "pmovzxbq", { XM, EXw } },
3969 { "pmovzxwd", { XM, EXq } },
3976 { "pmovzxwq", { XM, EXd } },
3983 { "pmovzxdq", { XM, EXq } },
3990 { "pcmpgtq", { XM, EXx } },
3997 { "pminsb", { XM, EXx } },
4004 { "pminsd", { XM, EXx } },
4011 { "pminuw", { XM, EXx } },
4018 { "pminud", { XM, EXx } },
4025 { "pmaxsb", { XM, EXx } },
4032 { "pmaxsd", { XM, EXx } },
4039 { "pmaxuw", { XM, EXx } },
4046 { "pmaxud", { XM, EXx } },
4053 { "pmulld", { XM, EXx } },
4060 { "phminposuw", { XM, EXx } },
4067 { "invept", { Gm, Mo } },
4074 { "invvpid", { Gm, Mo } },
4081 { "invpcid", { Gm, M } },
4086 { "sha1nexte", { XM, EXxmm } },
4091 { "sha1msg1", { XM, EXxmm } },
4096 { "sha1msg2", { XM, EXxmm } },
4101 { "sha256rnds2", { XM, EXxmm, XMM0 } },
4106 { "sha256msg1", { XM, EXxmm } },
4111 { "sha256msg2", { XM, EXxmm } },
4118 { "aesimc", { XM, EXx } },
4125 { "aesenc", { XM, EXx } },
4132 { "aesenclast", { XM, EXx } },
4139 { "aesdec", { XM, EXx } },
4146 { "aesdeclast", { XM, EXx } },
4151 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4153 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4154 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
4159 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4161 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4162 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
4168 { "adoxS", { Gdq, Edq} },
4169 { "adcxS", { Gdq, Edq} },
4177 { "roundps", { XM, EXx, Ib } },
4184 { "roundpd", { XM, EXx, Ib } },
4191 { "roundss", { XM, EXd, Ib } },
4198 { "roundsd", { XM, EXq, Ib } },
4205 { "blendps", { XM, EXx, Ib } },
4212 { "blendpd", { XM, EXx, Ib } },
4219 { "pblendw", { XM, EXx, Ib } },
4226 { "pextrb", { Edqb, XM, Ib } },
4233 { "pextrw", { Edqw, XM, Ib } },
4240 { "pextrK", { Edq, XM, Ib } },
4247 { "extractps", { Edqd, XM, Ib } },
4254 { "pinsrb", { XM, Edqb, Ib } },
4261 { "insertps", { XM, EXd, Ib } },
4268 { "pinsrK", { XM, Edq, Ib } },
4275 { "dpps", { XM, EXx, Ib } },
4282 { "dppd", { XM, EXx, Ib } },
4289 { "mpsadbw", { XM, EXx, Ib } },
4296 { "pclmulqdq", { XM, EXx, PCLMUL } },
4303 { "pcmpestrm", { XM, EXx, Ib } },
4310 { "pcmpestri", { XM, EXx, Ib } },
4317 { "pcmpistrm", { XM, EXx, Ib } },
4324 { "pcmpistri", { XM, EXx, Ib } },
4329 { "sha1rnds4", { XM, EXxmm, Ib } },
4336 { "aeskeygenassist", { XM, EXx, Ib } },
4339 /* PREFIX_VEX_0F10 */
4341 { VEX_W_TABLE (VEX_W_0F10_P_0) },
4342 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4343 { VEX_W_TABLE (VEX_W_0F10_P_2) },
4344 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4347 /* PREFIX_VEX_0F11 */
4349 { VEX_W_TABLE (VEX_W_0F11_P_0) },
4350 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4351 { VEX_W_TABLE (VEX_W_0F11_P_2) },
4352 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4355 /* PREFIX_VEX_0F12 */
4357 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4358 { VEX_W_TABLE (VEX_W_0F12_P_1) },
4359 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4360 { VEX_W_TABLE (VEX_W_0F12_P_3) },
4363 /* PREFIX_VEX_0F16 */
4365 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4366 { VEX_W_TABLE (VEX_W_0F16_P_1) },
4367 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4370 /* PREFIX_VEX_0F2A */
4373 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4375 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4378 /* PREFIX_VEX_0F2C */
4381 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4383 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4386 /* PREFIX_VEX_0F2D */
4389 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4391 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4394 /* PREFIX_VEX_0F2E */
4396 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4398 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4401 /* PREFIX_VEX_0F2F */
4403 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4405 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4408 /* PREFIX_VEX_0F41 */
4410 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4413 /* PREFIX_VEX_0F42 */
4415 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4418 /* PREFIX_VEX_0F44 */
4420 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4423 /* PREFIX_VEX_0F45 */
4425 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4428 /* PREFIX_VEX_0F46 */
4430 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4433 /* PREFIX_VEX_0F47 */
4435 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4438 /* PREFIX_VEX_0F4B */
4442 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4445 /* PREFIX_VEX_0F51 */
4447 { VEX_W_TABLE (VEX_W_0F51_P_0) },
4448 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4449 { VEX_W_TABLE (VEX_W_0F51_P_2) },
4450 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4453 /* PREFIX_VEX_0F52 */
4455 { VEX_W_TABLE (VEX_W_0F52_P_0) },
4456 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4459 /* PREFIX_VEX_0F53 */
4461 { VEX_W_TABLE (VEX_W_0F53_P_0) },
4462 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4465 /* PREFIX_VEX_0F58 */
4467 { VEX_W_TABLE (VEX_W_0F58_P_0) },
4468 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4469 { VEX_W_TABLE (VEX_W_0F58_P_2) },
4470 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4473 /* PREFIX_VEX_0F59 */
4475 { VEX_W_TABLE (VEX_W_0F59_P_0) },
4476 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4477 { VEX_W_TABLE (VEX_W_0F59_P_2) },
4478 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4481 /* PREFIX_VEX_0F5A */
4483 { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4484 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4485 { "vcvtpd2ps%XY", { XMM, EXx } },
4486 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4489 /* PREFIX_VEX_0F5B */
4491 { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4492 { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4493 { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4496 /* PREFIX_VEX_0F5C */
4498 { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4499 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4500 { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4501 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4504 /* PREFIX_VEX_0F5D */
4506 { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4507 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4508 { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4509 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4512 /* PREFIX_VEX_0F5E */
4514 { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4515 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4516 { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4517 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4520 /* PREFIX_VEX_0F5F */
4522 { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4523 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4524 { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4525 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4528 /* PREFIX_VEX_0F60 */
4532 { VEX_W_TABLE (VEX_W_0F60_P_2) },
4535 /* PREFIX_VEX_0F61 */
4539 { VEX_W_TABLE (VEX_W_0F61_P_2) },
4542 /* PREFIX_VEX_0F62 */
4546 { VEX_W_TABLE (VEX_W_0F62_P_2) },
4549 /* PREFIX_VEX_0F63 */
4553 { VEX_W_TABLE (VEX_W_0F63_P_2) },
4556 /* PREFIX_VEX_0F64 */
4560 { VEX_W_TABLE (VEX_W_0F64_P_2) },
4563 /* PREFIX_VEX_0F65 */
4567 { VEX_W_TABLE (VEX_W_0F65_P_2) },
4570 /* PREFIX_VEX_0F66 */
4574 { VEX_W_TABLE (VEX_W_0F66_P_2) },
4577 /* PREFIX_VEX_0F67 */
4581 { VEX_W_TABLE (VEX_W_0F67_P_2) },
4584 /* PREFIX_VEX_0F68 */
4588 { VEX_W_TABLE (VEX_W_0F68_P_2) },
4591 /* PREFIX_VEX_0F69 */
4595 { VEX_W_TABLE (VEX_W_0F69_P_2) },
4598 /* PREFIX_VEX_0F6A */
4602 { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4605 /* PREFIX_VEX_0F6B */
4609 { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4612 /* PREFIX_VEX_0F6C */
4616 { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4619 /* PREFIX_VEX_0F6D */
4623 { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4626 /* PREFIX_VEX_0F6E */
4630 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4633 /* PREFIX_VEX_0F6F */
4636 { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4637 { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4640 /* PREFIX_VEX_0F70 */
4643 { VEX_W_TABLE (VEX_W_0F70_P_1) },
4644 { VEX_W_TABLE (VEX_W_0F70_P_2) },
4645 { VEX_W_TABLE (VEX_W_0F70_P_3) },
4648 /* PREFIX_VEX_0F71_REG_2 */
4652 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4655 /* PREFIX_VEX_0F71_REG_4 */
4659 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4662 /* PREFIX_VEX_0F71_REG_6 */
4666 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4669 /* PREFIX_VEX_0F72_REG_2 */
4673 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4676 /* PREFIX_VEX_0F72_REG_4 */
4680 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4683 /* PREFIX_VEX_0F72_REG_6 */
4687 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4690 /* PREFIX_VEX_0F73_REG_2 */
4694 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4697 /* PREFIX_VEX_0F73_REG_3 */
4701 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4704 /* PREFIX_VEX_0F73_REG_6 */
4708 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4711 /* PREFIX_VEX_0F73_REG_7 */
4715 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4718 /* PREFIX_VEX_0F74 */
4722 { VEX_W_TABLE (VEX_W_0F74_P_2) },
4725 /* PREFIX_VEX_0F75 */
4729 { VEX_W_TABLE (VEX_W_0F75_P_2) },
4732 /* PREFIX_VEX_0F76 */
4736 { VEX_W_TABLE (VEX_W_0F76_P_2) },
4739 /* PREFIX_VEX_0F77 */
4741 { VEX_W_TABLE (VEX_W_0F77_P_0) },
4744 /* PREFIX_VEX_0F7C */
4748 { VEX_W_TABLE (VEX_W_0F7C_P_2) },
4749 { VEX_W_TABLE (VEX_W_0F7C_P_3) },
4752 /* PREFIX_VEX_0F7D */
4756 { VEX_W_TABLE (VEX_W_0F7D_P_2) },
4757 { VEX_W_TABLE (VEX_W_0F7D_P_3) },
4760 /* PREFIX_VEX_0F7E */
4763 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4764 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4767 /* PREFIX_VEX_0F7F */
4770 { VEX_W_TABLE (VEX_W_0F7F_P_1) },
4771 { VEX_W_TABLE (VEX_W_0F7F_P_2) },
4774 /* PREFIX_VEX_0F90 */
4776 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
4779 /* PREFIX_VEX_0F91 */
4781 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
4784 /* PREFIX_VEX_0F92 */
4786 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
4789 /* PREFIX_VEX_0F93 */
4791 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
4794 /* PREFIX_VEX_0F98 */
4796 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
4799 /* PREFIX_VEX_0FC2 */
4801 { VEX_W_TABLE (VEX_W_0FC2_P_0) },
4802 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
4803 { VEX_W_TABLE (VEX_W_0FC2_P_2) },
4804 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
4807 /* PREFIX_VEX_0FC4 */
4811 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
4814 /* PREFIX_VEX_0FC5 */
4818 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
4821 /* PREFIX_VEX_0FD0 */
4825 { VEX_W_TABLE (VEX_W_0FD0_P_2) },
4826 { VEX_W_TABLE (VEX_W_0FD0_P_3) },
4829 /* PREFIX_VEX_0FD1 */
4833 { VEX_W_TABLE (VEX_W_0FD1_P_2) },
4836 /* PREFIX_VEX_0FD2 */
4840 { VEX_W_TABLE (VEX_W_0FD2_P_2) },
4843 /* PREFIX_VEX_0FD3 */
4847 { VEX_W_TABLE (VEX_W_0FD3_P_2) },
4850 /* PREFIX_VEX_0FD4 */
4854 { VEX_W_TABLE (VEX_W_0FD4_P_2) },
4857 /* PREFIX_VEX_0FD5 */
4861 { VEX_W_TABLE (VEX_W_0FD5_P_2) },
4864 /* PREFIX_VEX_0FD6 */
4868 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
4871 /* PREFIX_VEX_0FD7 */
4875 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
4878 /* PREFIX_VEX_0FD8 */
4882 { VEX_W_TABLE (VEX_W_0FD8_P_2) },
4885 /* PREFIX_VEX_0FD9 */
4889 { VEX_W_TABLE (VEX_W_0FD9_P_2) },
4892 /* PREFIX_VEX_0FDA */
4896 { VEX_W_TABLE (VEX_W_0FDA_P_2) },
4899 /* PREFIX_VEX_0FDB */
4903 { VEX_W_TABLE (VEX_W_0FDB_P_2) },
4906 /* PREFIX_VEX_0FDC */
4910 { VEX_W_TABLE (VEX_W_0FDC_P_2) },
4913 /* PREFIX_VEX_0FDD */
4917 { VEX_W_TABLE (VEX_W_0FDD_P_2) },
4920 /* PREFIX_VEX_0FDE */
4924 { VEX_W_TABLE (VEX_W_0FDE_P_2) },
4927 /* PREFIX_VEX_0FDF */
4931 { VEX_W_TABLE (VEX_W_0FDF_P_2) },
4934 /* PREFIX_VEX_0FE0 */
4938 { VEX_W_TABLE (VEX_W_0FE0_P_2) },
4941 /* PREFIX_VEX_0FE1 */
4945 { VEX_W_TABLE (VEX_W_0FE1_P_2) },
4948 /* PREFIX_VEX_0FE2 */
4952 { VEX_W_TABLE (VEX_W_0FE2_P_2) },
4955 /* PREFIX_VEX_0FE3 */
4959 { VEX_W_TABLE (VEX_W_0FE3_P_2) },
4962 /* PREFIX_VEX_0FE4 */
4966 { VEX_W_TABLE (VEX_W_0FE4_P_2) },
4969 /* PREFIX_VEX_0FE5 */
4973 { VEX_W_TABLE (VEX_W_0FE5_P_2) },
4976 /* PREFIX_VEX_0FE6 */
4979 { VEX_W_TABLE (VEX_W_0FE6_P_1) },
4980 { VEX_W_TABLE (VEX_W_0FE6_P_2) },
4981 { VEX_W_TABLE (VEX_W_0FE6_P_3) },
4984 /* PREFIX_VEX_0FE7 */
4988 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
4991 /* PREFIX_VEX_0FE8 */
4995 { VEX_W_TABLE (VEX_W_0FE8_P_2) },
4998 /* PREFIX_VEX_0FE9 */
5002 { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5005 /* PREFIX_VEX_0FEA */
5009 { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5012 /* PREFIX_VEX_0FEB */
5016 { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5019 /* PREFIX_VEX_0FEC */
5023 { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5026 /* PREFIX_VEX_0FED */
5030 { VEX_W_TABLE (VEX_W_0FED_P_2) },
5033 /* PREFIX_VEX_0FEE */
5037 { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5040 /* PREFIX_VEX_0FEF */
5044 { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5047 /* PREFIX_VEX_0FF0 */
5052 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5055 /* PREFIX_VEX_0FF1 */
5059 { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5062 /* PREFIX_VEX_0FF2 */
5066 { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5069 /* PREFIX_VEX_0FF3 */
5073 { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5076 /* PREFIX_VEX_0FF4 */
5080 { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5083 /* PREFIX_VEX_0FF5 */
5087 { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5090 /* PREFIX_VEX_0FF6 */
5094 { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5097 /* PREFIX_VEX_0FF7 */
5101 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5104 /* PREFIX_VEX_0FF8 */
5108 { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5111 /* PREFIX_VEX_0FF9 */
5115 { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5118 /* PREFIX_VEX_0FFA */
5122 { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5125 /* PREFIX_VEX_0FFB */
5129 { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5132 /* PREFIX_VEX_0FFC */
5136 { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5139 /* PREFIX_VEX_0FFD */
5143 { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5146 /* PREFIX_VEX_0FFE */
5150 { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5153 /* PREFIX_VEX_0F3800 */
5157 { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5160 /* PREFIX_VEX_0F3801 */
5164 { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5167 /* PREFIX_VEX_0F3802 */
5171 { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5174 /* PREFIX_VEX_0F3803 */
5178 { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5181 /* PREFIX_VEX_0F3804 */
5185 { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5188 /* PREFIX_VEX_0F3805 */
5192 { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5195 /* PREFIX_VEX_0F3806 */
5199 { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5202 /* PREFIX_VEX_0F3807 */
5206 { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5209 /* PREFIX_VEX_0F3808 */
5213 { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5216 /* PREFIX_VEX_0F3809 */
5220 { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5223 /* PREFIX_VEX_0F380A */
5227 { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5230 /* PREFIX_VEX_0F380B */
5234 { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5237 /* PREFIX_VEX_0F380C */
5241 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5244 /* PREFIX_VEX_0F380D */
5248 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5251 /* PREFIX_VEX_0F380E */
5255 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5258 /* PREFIX_VEX_0F380F */
5262 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5265 /* PREFIX_VEX_0F3813 */
5269 { "vcvtph2ps", { XM, EXxmmq } },
5272 /* PREFIX_VEX_0F3816 */
5276 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5279 /* PREFIX_VEX_0F3817 */
5283 { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5286 /* PREFIX_VEX_0F3818 */
5290 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5293 /* PREFIX_VEX_0F3819 */
5297 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5300 /* PREFIX_VEX_0F381A */
5304 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5307 /* PREFIX_VEX_0F381C */
5311 { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5314 /* PREFIX_VEX_0F381D */
5318 { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5321 /* PREFIX_VEX_0F381E */
5325 { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5328 /* PREFIX_VEX_0F3820 */
5332 { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5335 /* PREFIX_VEX_0F3821 */
5339 { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5342 /* PREFIX_VEX_0F3822 */
5346 { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5349 /* PREFIX_VEX_0F3823 */
5353 { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5356 /* PREFIX_VEX_0F3824 */
5360 { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5363 /* PREFIX_VEX_0F3825 */
5367 { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5370 /* PREFIX_VEX_0F3828 */
5374 { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5377 /* PREFIX_VEX_0F3829 */
5381 { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5384 /* PREFIX_VEX_0F382A */
5388 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5391 /* PREFIX_VEX_0F382B */
5395 { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5398 /* PREFIX_VEX_0F382C */
5402 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5405 /* PREFIX_VEX_0F382D */
5409 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5412 /* PREFIX_VEX_0F382E */
5416 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5419 /* PREFIX_VEX_0F382F */
5423 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5426 /* PREFIX_VEX_0F3830 */
5430 { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5433 /* PREFIX_VEX_0F3831 */
5437 { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5440 /* PREFIX_VEX_0F3832 */
5444 { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5447 /* PREFIX_VEX_0F3833 */
5451 { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5454 /* PREFIX_VEX_0F3834 */
5458 { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5461 /* PREFIX_VEX_0F3835 */
5465 { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5468 /* PREFIX_VEX_0F3836 */
5472 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5475 /* PREFIX_VEX_0F3837 */
5479 { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5482 /* PREFIX_VEX_0F3838 */
5486 { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5489 /* PREFIX_VEX_0F3839 */
5493 { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5496 /* PREFIX_VEX_0F383A */
5500 { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5503 /* PREFIX_VEX_0F383B */
5507 { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5510 /* PREFIX_VEX_0F383C */
5514 { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5517 /* PREFIX_VEX_0F383D */
5521 { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5524 /* PREFIX_VEX_0F383E */
5528 { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5531 /* PREFIX_VEX_0F383F */
5535 { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5538 /* PREFIX_VEX_0F3840 */
5542 { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5545 /* PREFIX_VEX_0F3841 */
5549 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5552 /* PREFIX_VEX_0F3845 */
5556 { "vpsrlv%LW", { XM, Vex, EXx } },
5559 /* PREFIX_VEX_0F3846 */
5563 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5566 /* PREFIX_VEX_0F3847 */
5570 { "vpsllv%LW", { XM, Vex, EXx } },
5573 /* PREFIX_VEX_0F3858 */
5577 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5580 /* PREFIX_VEX_0F3859 */
5584 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5587 /* PREFIX_VEX_0F385A */
5591 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5594 /* PREFIX_VEX_0F3878 */
5598 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5601 /* PREFIX_VEX_0F3879 */
5605 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5608 /* PREFIX_VEX_0F388C */
5612 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5615 /* PREFIX_VEX_0F388E */
5619 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5622 /* PREFIX_VEX_0F3890 */
5626 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
5629 /* PREFIX_VEX_0F3891 */
5633 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5636 /* PREFIX_VEX_0F3892 */
5640 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
5643 /* PREFIX_VEX_0F3893 */
5647 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5650 /* PREFIX_VEX_0F3896 */
5654 { "vfmaddsub132p%XW", { XM, Vex, EXx } },
5657 /* PREFIX_VEX_0F3897 */
5661 { "vfmsubadd132p%XW", { XM, Vex, EXx } },
5664 /* PREFIX_VEX_0F3898 */
5668 { "vfmadd132p%XW", { XM, Vex, EXx } },
5671 /* PREFIX_VEX_0F3899 */
5675 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5678 /* PREFIX_VEX_0F389A */
5682 { "vfmsub132p%XW", { XM, Vex, EXx } },
5685 /* PREFIX_VEX_0F389B */
5689 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5692 /* PREFIX_VEX_0F389C */
5696 { "vfnmadd132p%XW", { XM, Vex, EXx } },
5699 /* PREFIX_VEX_0F389D */
5703 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5706 /* PREFIX_VEX_0F389E */
5710 { "vfnmsub132p%XW", { XM, Vex, EXx } },
5713 /* PREFIX_VEX_0F389F */
5717 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5720 /* PREFIX_VEX_0F38A6 */
5724 { "vfmaddsub213p%XW", { XM, Vex, EXx } },
5728 /* PREFIX_VEX_0F38A7 */
5732 { "vfmsubadd213p%XW", { XM, Vex, EXx } },
5735 /* PREFIX_VEX_0F38A8 */
5739 { "vfmadd213p%XW", { XM, Vex, EXx } },
5742 /* PREFIX_VEX_0F38A9 */
5746 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5749 /* PREFIX_VEX_0F38AA */
5753 { "vfmsub213p%XW", { XM, Vex, EXx } },
5756 /* PREFIX_VEX_0F38AB */
5760 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5763 /* PREFIX_VEX_0F38AC */
5767 { "vfnmadd213p%XW", { XM, Vex, EXx } },
5770 /* PREFIX_VEX_0F38AD */
5774 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5777 /* PREFIX_VEX_0F38AE */
5781 { "vfnmsub213p%XW", { XM, Vex, EXx } },
5784 /* PREFIX_VEX_0F38AF */
5788 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5791 /* PREFIX_VEX_0F38B6 */
5795 { "vfmaddsub231p%XW", { XM, Vex, EXx } },
5798 /* PREFIX_VEX_0F38B7 */
5802 { "vfmsubadd231p%XW", { XM, Vex, EXx } },
5805 /* PREFIX_VEX_0F38B8 */
5809 { "vfmadd231p%XW", { XM, Vex, EXx } },
5812 /* PREFIX_VEX_0F38B9 */
5816 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5819 /* PREFIX_VEX_0F38BA */
5823 { "vfmsub231p%XW", { XM, Vex, EXx } },
5826 /* PREFIX_VEX_0F38BB */
5830 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5833 /* PREFIX_VEX_0F38BC */
5837 { "vfnmadd231p%XW", { XM, Vex, EXx } },
5840 /* PREFIX_VEX_0F38BD */
5844 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5847 /* PREFIX_VEX_0F38BE */
5851 { "vfnmsub231p%XW", { XM, Vex, EXx } },
5854 /* PREFIX_VEX_0F38BF */
5858 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5861 /* PREFIX_VEX_0F38DB */
5865 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
5868 /* PREFIX_VEX_0F38DC */
5872 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
5875 /* PREFIX_VEX_0F38DD */
5879 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
5882 /* PREFIX_VEX_0F38DE */
5886 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
5889 /* PREFIX_VEX_0F38DF */
5893 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
5896 /* PREFIX_VEX_0F38F2 */
5898 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
5901 /* PREFIX_VEX_0F38F3_REG_1 */
5903 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
5906 /* PREFIX_VEX_0F38F3_REG_2 */
5908 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
5911 /* PREFIX_VEX_0F38F3_REG_3 */
5913 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
5916 /* PREFIX_VEX_0F38F5 */
5918 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
5919 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
5921 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
5924 /* PREFIX_VEX_0F38F6 */
5929 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
5932 /* PREFIX_VEX_0F38F7 */
5934 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
5935 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
5936 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
5937 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
5940 /* PREFIX_VEX_0F3A00 */
5944 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
5947 /* PREFIX_VEX_0F3A01 */
5951 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
5954 /* PREFIX_VEX_0F3A02 */
5958 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
5961 /* PREFIX_VEX_0F3A04 */
5965 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
5968 /* PREFIX_VEX_0F3A05 */
5972 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
5975 /* PREFIX_VEX_0F3A06 */
5979 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
5982 /* PREFIX_VEX_0F3A08 */
5986 { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
5989 /* PREFIX_VEX_0F3A09 */
5993 { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
5996 /* PREFIX_VEX_0F3A0A */
6000 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6003 /* PREFIX_VEX_0F3A0B */
6007 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6010 /* PREFIX_VEX_0F3A0C */
6014 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6017 /* PREFIX_VEX_0F3A0D */
6021 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6024 /* PREFIX_VEX_0F3A0E */
6028 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6031 /* PREFIX_VEX_0F3A0F */
6035 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6038 /* PREFIX_VEX_0F3A14 */
6042 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6045 /* PREFIX_VEX_0F3A15 */
6049 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6052 /* PREFIX_VEX_0F3A16 */
6056 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6059 /* PREFIX_VEX_0F3A17 */
6063 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6066 /* PREFIX_VEX_0F3A18 */
6070 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6073 /* PREFIX_VEX_0F3A19 */
6077 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6080 /* PREFIX_VEX_0F3A1D */
6084 { "vcvtps2ph", { EXxmmq, XM, Ib } },
6087 /* PREFIX_VEX_0F3A20 */
6091 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6094 /* PREFIX_VEX_0F3A21 */
6098 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6101 /* PREFIX_VEX_0F3A22 */
6105 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6108 /* PREFIX_VEX_0F3A30 */
6112 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6115 /* PREFIX_VEX_0F3A32 */
6119 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6122 /* PREFIX_VEX_0F3A38 */
6126 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6129 /* PREFIX_VEX_0F3A39 */
6133 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6136 /* PREFIX_VEX_0F3A40 */
6140 { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6143 /* PREFIX_VEX_0F3A41 */
6147 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6150 /* PREFIX_VEX_0F3A42 */
6154 { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6157 /* PREFIX_VEX_0F3A44 */
6161 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6164 /* PREFIX_VEX_0F3A46 */
6168 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6171 /* PREFIX_VEX_0F3A48 */
6175 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6178 /* PREFIX_VEX_0F3A49 */
6182 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6185 /* PREFIX_VEX_0F3A4A */
6189 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6192 /* PREFIX_VEX_0F3A4B */
6196 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6199 /* PREFIX_VEX_0F3A4C */
6203 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6206 /* PREFIX_VEX_0F3A5C */
6210 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6213 /* PREFIX_VEX_0F3A5D */
6217 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6220 /* PREFIX_VEX_0F3A5E */
6224 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6227 /* PREFIX_VEX_0F3A5F */
6231 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6234 /* PREFIX_VEX_0F3A60 */
6238 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6242 /* PREFIX_VEX_0F3A61 */
6246 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6249 /* PREFIX_VEX_0F3A62 */
6253 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6256 /* PREFIX_VEX_0F3A63 */
6260 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6263 /* PREFIX_VEX_0F3A68 */
6267 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6270 /* PREFIX_VEX_0F3A69 */
6274 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6277 /* PREFIX_VEX_0F3A6A */
6281 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6284 /* PREFIX_VEX_0F3A6B */
6288 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6291 /* PREFIX_VEX_0F3A6C */
6295 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6298 /* PREFIX_VEX_0F3A6D */
6302 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6305 /* PREFIX_VEX_0F3A6E */
6309 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6312 /* PREFIX_VEX_0F3A6F */
6316 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6319 /* PREFIX_VEX_0F3A78 */
6323 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6326 /* PREFIX_VEX_0F3A79 */
6330 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6333 /* PREFIX_VEX_0F3A7A */
6337 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6340 /* PREFIX_VEX_0F3A7B */
6344 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6347 /* PREFIX_VEX_0F3A7C */
6351 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6355 /* PREFIX_VEX_0F3A7D */
6359 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6362 /* PREFIX_VEX_0F3A7E */
6366 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6369 /* PREFIX_VEX_0F3A7F */
6373 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6376 /* PREFIX_VEX_0F3ADF */
6380 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6383 /* PREFIX_VEX_0F3AF0 */
6388 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6391 #define NEED_PREFIX_TABLE
6392 #include "i386-dis-evex.h"
6393 #undef NEED_PREFIX_TABLE
6396 static const struct dis386 x86_64_table[][2] = {
6399 { "pushP", { es } },
6409 { "pushP", { cs } },
6414 { "pushP", { ss } },
6424 { "pushP", { ds } },
6454 { "pushaP", { XX } },
6459 { "popaP", { XX } },
6464 { MOD_TABLE (MOD_62_32BIT) },
6465 { EVEX_TABLE (EVEX_0F) },
6470 { "arpl", { Ew, Gw } },
6471 { "movs{lq|xd}", { Gv, Ed } },
6476 { "ins{R|}", { Yzr, indirDX } },
6477 { "ins{G|}", { Yzr, indirDX } },
6482 { "outs{R|}", { indirDXr, Xz } },
6483 { "outs{G|}", { indirDXr, Xz } },
6488 { "Jcall{T|}", { Ap } },
6493 { MOD_TABLE (MOD_C4_32BIT) },
6494 { VEX_C4_TABLE (VEX_0F) },
6499 { MOD_TABLE (MOD_C5_32BIT) },
6500 { VEX_C5_TABLE (VEX_0F) },
6520 { "Jjmp{T|}", { Ap } },
6523 /* X86_64_0F01_REG_0 */
6525 { "sgdt{Q|IQ}", { M } },
6529 /* X86_64_0F01_REG_1 */
6531 { "sidt{Q|IQ}", { M } },
6535 /* X86_64_0F01_REG_2 */
6537 { "lgdt{Q|Q}", { M } },
6541 /* X86_64_0F01_REG_3 */
6543 { "lidt{Q|Q}", { M } },
6548 static const struct dis386 three_byte_table[][256] = {
6550 /* THREE_BYTE_0F38 */
6553 { "pshufb", { MX, EM } },
6554 { "phaddw", { MX, EM } },
6555 { "phaddd", { MX, EM } },
6556 { "phaddsw", { MX, EM } },
6557 { "pmaddubsw", { MX, EM } },
6558 { "phsubw", { MX, EM } },
6559 { "phsubd", { MX, EM } },
6560 { "phsubsw", { MX, EM } },
6562 { "psignb", { MX, EM } },
6563 { "psignw", { MX, EM } },
6564 { "psignd", { MX, EM } },
6565 { "pmulhrsw", { MX, EM } },
6571 { PREFIX_TABLE (PREFIX_0F3810) },
6575 { PREFIX_TABLE (PREFIX_0F3814) },
6576 { PREFIX_TABLE (PREFIX_0F3815) },
6578 { PREFIX_TABLE (PREFIX_0F3817) },
6584 { "pabsb", { MX, EM } },
6585 { "pabsw", { MX, EM } },
6586 { "pabsd", { MX, EM } },
6589 { PREFIX_TABLE (PREFIX_0F3820) },
6590 { PREFIX_TABLE (PREFIX_0F3821) },
6591 { PREFIX_TABLE (PREFIX_0F3822) },
6592 { PREFIX_TABLE (PREFIX_0F3823) },
6593 { PREFIX_TABLE (PREFIX_0F3824) },
6594 { PREFIX_TABLE (PREFIX_0F3825) },
6598 { PREFIX_TABLE (PREFIX_0F3828) },
6599 { PREFIX_TABLE (PREFIX_0F3829) },
6600 { PREFIX_TABLE (PREFIX_0F382A) },
6601 { PREFIX_TABLE (PREFIX_0F382B) },
6607 { PREFIX_TABLE (PREFIX_0F3830) },
6608 { PREFIX_TABLE (PREFIX_0F3831) },
6609 { PREFIX_TABLE (PREFIX_0F3832) },
6610 { PREFIX_TABLE (PREFIX_0F3833) },
6611 { PREFIX_TABLE (PREFIX_0F3834) },
6612 { PREFIX_TABLE (PREFIX_0F3835) },
6614 { PREFIX_TABLE (PREFIX_0F3837) },
6616 { PREFIX_TABLE (PREFIX_0F3838) },
6617 { PREFIX_TABLE (PREFIX_0F3839) },
6618 { PREFIX_TABLE (PREFIX_0F383A) },
6619 { PREFIX_TABLE (PREFIX_0F383B) },
6620 { PREFIX_TABLE (PREFIX_0F383C) },
6621 { PREFIX_TABLE (PREFIX_0F383D) },
6622 { PREFIX_TABLE (PREFIX_0F383E) },
6623 { PREFIX_TABLE (PREFIX_0F383F) },
6625 { PREFIX_TABLE (PREFIX_0F3840) },
6626 { PREFIX_TABLE (PREFIX_0F3841) },
6697 { PREFIX_TABLE (PREFIX_0F3880) },
6698 { PREFIX_TABLE (PREFIX_0F3881) },
6699 { PREFIX_TABLE (PREFIX_0F3882) },
6778 { PREFIX_TABLE (PREFIX_0F38C8) },
6779 { PREFIX_TABLE (PREFIX_0F38C9) },
6780 { PREFIX_TABLE (PREFIX_0F38CA) },
6781 { PREFIX_TABLE (PREFIX_0F38CB) },
6782 { PREFIX_TABLE (PREFIX_0F38CC) },
6783 { PREFIX_TABLE (PREFIX_0F38CD) },
6799 { PREFIX_TABLE (PREFIX_0F38DB) },
6800 { PREFIX_TABLE (PREFIX_0F38DC) },
6801 { PREFIX_TABLE (PREFIX_0F38DD) },
6802 { PREFIX_TABLE (PREFIX_0F38DE) },
6803 { PREFIX_TABLE (PREFIX_0F38DF) },
6823 { PREFIX_TABLE (PREFIX_0F38F0) },
6824 { PREFIX_TABLE (PREFIX_0F38F1) },
6829 { PREFIX_TABLE (PREFIX_0F38F6) },
6841 /* THREE_BYTE_0F3A */
6853 { PREFIX_TABLE (PREFIX_0F3A08) },
6854 { PREFIX_TABLE (PREFIX_0F3A09) },
6855 { PREFIX_TABLE (PREFIX_0F3A0A) },
6856 { PREFIX_TABLE (PREFIX_0F3A0B) },
6857 { PREFIX_TABLE (PREFIX_0F3A0C) },
6858 { PREFIX_TABLE (PREFIX_0F3A0D) },
6859 { PREFIX_TABLE (PREFIX_0F3A0E) },
6860 { "palignr", { MX, EM, Ib } },
6866 { PREFIX_TABLE (PREFIX_0F3A14) },
6867 { PREFIX_TABLE (PREFIX_0F3A15) },
6868 { PREFIX_TABLE (PREFIX_0F3A16) },
6869 { PREFIX_TABLE (PREFIX_0F3A17) },
6880 { PREFIX_TABLE (PREFIX_0F3A20) },
6881 { PREFIX_TABLE (PREFIX_0F3A21) },
6882 { PREFIX_TABLE (PREFIX_0F3A22) },
6916 { PREFIX_TABLE (PREFIX_0F3A40) },
6917 { PREFIX_TABLE (PREFIX_0F3A41) },
6918 { PREFIX_TABLE (PREFIX_0F3A42) },
6920 { PREFIX_TABLE (PREFIX_0F3A44) },
6952 { PREFIX_TABLE (PREFIX_0F3A60) },
6953 { PREFIX_TABLE (PREFIX_0F3A61) },
6954 { PREFIX_TABLE (PREFIX_0F3A62) },
6955 { PREFIX_TABLE (PREFIX_0F3A63) },
7073 { PREFIX_TABLE (PREFIX_0F3ACC) },
7094 { PREFIX_TABLE (PREFIX_0F3ADF) },
7133 /* THREE_BYTE_0F7A */
7172 { "ptest", { XX } },
7209 { "phaddbw", { XM, EXq } },
7210 { "phaddbd", { XM, EXq } },
7211 { "phaddbq", { XM, EXq } },
7214 { "phaddwd", { XM, EXq } },
7215 { "phaddwq", { XM, EXq } },
7220 { "phadddq", { XM, EXq } },
7227 { "phaddubw", { XM, EXq } },
7228 { "phaddubd", { XM, EXq } },
7229 { "phaddubq", { XM, EXq } },
7232 { "phadduwd", { XM, EXq } },
7233 { "phadduwq", { XM, EXq } },
7238 { "phaddudq", { XM, EXq } },
7245 { "phsubbw", { XM, EXq } },
7246 { "phsubbd", { XM, EXq } },
7247 { "phsubbq", { XM, EXq } },
7426 static const struct dis386 xop_table[][256] = {
7579 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7580 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7581 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7589 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7590 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7597 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7598 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7599 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7607 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7608 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7612 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7613 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7616 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7634 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7646 { "vprotb", { XM, Vex_2src_1, Ib } },
7647 { "vprotw", { XM, Vex_2src_1, Ib } },
7648 { "vprotd", { XM, Vex_2src_1, Ib } },
7649 { "vprotq", { XM, Vex_2src_1, Ib } },
7659 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7660 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7661 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7662 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7695 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7696 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7697 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7698 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7722 { REG_TABLE (REG_XOP_TBM_01) },
7723 { REG_TABLE (REG_XOP_TBM_02) },
7741 { REG_TABLE (REG_XOP_LWPCB) },
7865 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7866 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7867 { "vfrczss", { XM, EXd } },
7868 { "vfrczsd", { XM, EXq } },
7883 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } },
7884 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } },
7885 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } },
7886 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } },
7887 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } },
7888 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } },
7889 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } },
7890 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } },
7892 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } },
7893 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } },
7894 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } },
7895 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } },
7938 { "vphaddbw", { XM, EXxmm } },
7939 { "vphaddbd", { XM, EXxmm } },
7940 { "vphaddbq", { XM, EXxmm } },
7943 { "vphaddwd", { XM, EXxmm } },
7944 { "vphaddwq", { XM, EXxmm } },
7949 { "vphadddq", { XM, EXxmm } },
7956 { "vphaddubw", { XM, EXxmm } },
7957 { "vphaddubd", { XM, EXxmm } },
7958 { "vphaddubq", { XM, EXxmm } },
7961 { "vphadduwd", { XM, EXxmm } },
7962 { "vphadduwq", { XM, EXxmm } },
7967 { "vphaddudq", { XM, EXxmm } },
7974 { "vphsubbw", { XM, EXxmm } },
7975 { "vphsubwd", { XM, EXxmm } },
7976 { "vphsubdq", { XM, EXxmm } },
8030 { "bextr", { Gv, Ev, Iq } },
8032 { REG_TABLE (REG_XOP_LWP) },
8302 static const struct dis386 vex_table[][256] = {
8324 { PREFIX_TABLE (PREFIX_VEX_0F10) },
8325 { PREFIX_TABLE (PREFIX_VEX_0F11) },
8326 { PREFIX_TABLE (PREFIX_VEX_0F12) },
8327 { MOD_TABLE (MOD_VEX_0F13) },
8328 { VEX_W_TABLE (VEX_W_0F14) },
8329 { VEX_W_TABLE (VEX_W_0F15) },
8330 { PREFIX_TABLE (PREFIX_VEX_0F16) },
8331 { MOD_TABLE (MOD_VEX_0F17) },
8351 { VEX_W_TABLE (VEX_W_0F28) },
8352 { VEX_W_TABLE (VEX_W_0F29) },
8353 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8354 { MOD_TABLE (MOD_VEX_0F2B) },
8355 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8356 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8357 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8358 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8379 { PREFIX_TABLE (PREFIX_VEX_0F41) },
8380 { PREFIX_TABLE (PREFIX_VEX_0F42) },
8382 { PREFIX_TABLE (PREFIX_VEX_0F44) },
8383 { PREFIX_TABLE (PREFIX_VEX_0F45) },
8384 { PREFIX_TABLE (PREFIX_VEX_0F46) },
8385 { PREFIX_TABLE (PREFIX_VEX_0F47) },
8390 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8396 { MOD_TABLE (MOD_VEX_0F50) },
8397 { PREFIX_TABLE (PREFIX_VEX_0F51) },
8398 { PREFIX_TABLE (PREFIX_VEX_0F52) },
8399 { PREFIX_TABLE (PREFIX_VEX_0F53) },
8400 { "vandpX", { XM, Vex, EXx } },
8401 { "vandnpX", { XM, Vex, EXx } },
8402 { "vorpX", { XM, Vex, EXx } },
8403 { "vxorpX", { XM, Vex, EXx } },
8405 { PREFIX_TABLE (PREFIX_VEX_0F58) },
8406 { PREFIX_TABLE (PREFIX_VEX_0F59) },
8407 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8408 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8409 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8410 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8411 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8412 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8414 { PREFIX_TABLE (PREFIX_VEX_0F60) },
8415 { PREFIX_TABLE (PREFIX_VEX_0F61) },
8416 { PREFIX_TABLE (PREFIX_VEX_0F62) },
8417 { PREFIX_TABLE (PREFIX_VEX_0F63) },
8418 { PREFIX_TABLE (PREFIX_VEX_0F64) },
8419 { PREFIX_TABLE (PREFIX_VEX_0F65) },
8420 { PREFIX_TABLE (PREFIX_VEX_0F66) },
8421 { PREFIX_TABLE (PREFIX_VEX_0F67) },
8423 { PREFIX_TABLE (PREFIX_VEX_0F68) },
8424 { PREFIX_TABLE (PREFIX_VEX_0F69) },
8425 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8426 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8427 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8428 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8429 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8430 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8432 { PREFIX_TABLE (PREFIX_VEX_0F70) },
8433 { REG_TABLE (REG_VEX_0F71) },
8434 { REG_TABLE (REG_VEX_0F72) },
8435 { REG_TABLE (REG_VEX_0F73) },
8436 { PREFIX_TABLE (PREFIX_VEX_0F74) },
8437 { PREFIX_TABLE (PREFIX_VEX_0F75) },
8438 { PREFIX_TABLE (PREFIX_VEX_0F76) },
8439 { PREFIX_TABLE (PREFIX_VEX_0F77) },
8445 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8446 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8447 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8448 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8468 { PREFIX_TABLE (PREFIX_VEX_0F90) },
8469 { PREFIX_TABLE (PREFIX_VEX_0F91) },
8470 { PREFIX_TABLE (PREFIX_VEX_0F92) },
8471 { PREFIX_TABLE (PREFIX_VEX_0F93) },
8477 { PREFIX_TABLE (PREFIX_VEX_0F98) },
8501 { REG_TABLE (REG_VEX_0FAE) },
8524 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8526 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8527 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8528 { "vshufpX", { XM, Vex, EXx, Ib } },
8540 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8541 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8542 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8543 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8544 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8545 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8546 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8547 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8549 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8550 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8551 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8552 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8553 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8554 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8555 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8556 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8558 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8559 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8560 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8561 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8562 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8563 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8564 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8565 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8567 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8568 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8569 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8570 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8571 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8572 { PREFIX_TABLE (PREFIX_VEX_0FED) },
8573 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8574 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8576 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8577 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8578 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8579 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8580 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8581 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8582 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8583 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8585 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8586 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8587 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8588 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8589 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8590 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8591 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8597 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8598 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8599 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8600 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8601 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8602 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8603 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8604 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8606 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8607 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8608 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8609 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8610 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8611 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8612 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8613 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8618 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8621 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8622 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8624 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8625 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8626 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8628 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8629 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8630 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8633 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8634 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8635 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8636 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8637 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8638 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8642 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8643 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8644 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8645 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8646 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8647 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8648 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8649 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8651 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8652 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8653 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8654 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8655 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8656 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8657 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8658 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8660 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8661 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8662 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8663 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8664 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8665 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8666 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8667 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8669 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8670 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8674 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8675 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8676 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8696 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8697 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8698 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8783 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8789 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8790 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8792 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8802 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8804 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8806 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8807 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8808 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8809 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8810 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8811 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8843 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8844 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8845 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8846 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8847 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8869 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8870 { REG_TABLE (REG_VEX_0F38F3) },
8872 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8873 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8874 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8924 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8925 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8926 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8960 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8961 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8962 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8964 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8966 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8969 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8972 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8973 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8991 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
8992 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
8993 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
8994 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
8996 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
8997 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
8999 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9005 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9006 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9008 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9009 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9010 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9011 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9012 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9024 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9026 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9027 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9028 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9029 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9030 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9138 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9158 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9178 #define NEED_OPCODE_TABLE
9179 #include "i386-dis-evex.h"
9180 #undef NEED_OPCODE_TABLE
9181 static const struct dis386 vex_len_table[][2] = {
9182 /* VEX_LEN_0F10_P_1 */
9184 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9185 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9188 /* VEX_LEN_0F10_P_3 */
9190 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9191 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9194 /* VEX_LEN_0F11_P_1 */
9196 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9197 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9200 /* VEX_LEN_0F11_P_3 */
9202 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9203 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9206 /* VEX_LEN_0F12_P_0_M_0 */
9208 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9211 /* VEX_LEN_0F12_P_0_M_1 */
9213 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9216 /* VEX_LEN_0F12_P_2 */
9218 { VEX_W_TABLE (VEX_W_0F12_P_2) },
9221 /* VEX_LEN_0F13_M_0 */
9223 { VEX_W_TABLE (VEX_W_0F13_M_0) },
9226 /* VEX_LEN_0F16_P_0_M_0 */
9228 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9231 /* VEX_LEN_0F16_P_0_M_1 */
9233 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9236 /* VEX_LEN_0F16_P_2 */
9238 { VEX_W_TABLE (VEX_W_0F16_P_2) },
9241 /* VEX_LEN_0F17_M_0 */
9243 { VEX_W_TABLE (VEX_W_0F17_M_0) },
9246 /* VEX_LEN_0F2A_P_1 */
9248 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
9249 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
9252 /* VEX_LEN_0F2A_P_3 */
9254 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
9255 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
9258 /* VEX_LEN_0F2C_P_1 */
9260 { "vcvttss2siY", { Gv, EXdScalar } },
9261 { "vcvttss2siY", { Gv, EXdScalar } },
9264 /* VEX_LEN_0F2C_P_3 */
9266 { "vcvttsd2siY", { Gv, EXqScalar } },
9267 { "vcvttsd2siY", { Gv, EXqScalar } },
9270 /* VEX_LEN_0F2D_P_1 */
9272 { "vcvtss2siY", { Gv, EXdScalar } },
9273 { "vcvtss2siY", { Gv, EXdScalar } },
9276 /* VEX_LEN_0F2D_P_3 */
9278 { "vcvtsd2siY", { Gv, EXqScalar } },
9279 { "vcvtsd2siY", { Gv, EXqScalar } },
9282 /* VEX_LEN_0F2E_P_0 */
9284 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9285 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9288 /* VEX_LEN_0F2E_P_2 */
9290 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9291 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9294 /* VEX_LEN_0F2F_P_0 */
9296 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9297 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9300 /* VEX_LEN_0F2F_P_2 */
9302 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9303 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9306 /* VEX_LEN_0F41_P_0 */
9309 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9311 /* VEX_LEN_0F42_P_0 */
9314 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9316 /* VEX_LEN_0F44_P_0 */
9318 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9320 /* VEX_LEN_0F45_P_0 */
9323 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9325 /* VEX_LEN_0F46_P_0 */
9328 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9330 /* VEX_LEN_0F47_P_0 */
9333 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9335 /* VEX_LEN_0F4B_P_2 */
9338 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9341 /* VEX_LEN_0F51_P_1 */
9343 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9344 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9347 /* VEX_LEN_0F51_P_3 */
9349 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9350 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9353 /* VEX_LEN_0F52_P_1 */
9355 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9356 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9359 /* VEX_LEN_0F53_P_1 */
9361 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9362 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9365 /* VEX_LEN_0F58_P_1 */
9367 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9368 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9371 /* VEX_LEN_0F58_P_3 */
9373 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9374 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9377 /* VEX_LEN_0F59_P_1 */
9379 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9380 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9383 /* VEX_LEN_0F59_P_3 */
9385 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9386 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9389 /* VEX_LEN_0F5A_P_1 */
9391 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9392 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9395 /* VEX_LEN_0F5A_P_3 */
9397 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9398 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9401 /* VEX_LEN_0F5C_P_1 */
9403 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9404 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9407 /* VEX_LEN_0F5C_P_3 */
9409 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9410 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9413 /* VEX_LEN_0F5D_P_1 */
9415 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9416 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9419 /* VEX_LEN_0F5D_P_3 */
9421 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9422 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9425 /* VEX_LEN_0F5E_P_1 */
9427 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9428 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9431 /* VEX_LEN_0F5E_P_3 */
9433 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9434 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9437 /* VEX_LEN_0F5F_P_1 */
9439 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9440 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9443 /* VEX_LEN_0F5F_P_3 */
9445 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9446 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9449 /* VEX_LEN_0F6E_P_2 */
9451 { "vmovK", { XMScalar, Edq } },
9452 { "vmovK", { XMScalar, Edq } },
9455 /* VEX_LEN_0F7E_P_1 */
9457 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9458 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9461 /* VEX_LEN_0F7E_P_2 */
9463 { "vmovK", { Edq, XMScalar } },
9464 { "vmovK", { Edq, XMScalar } },
9467 /* VEX_LEN_0F90_P_0 */
9469 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9472 /* VEX_LEN_0F91_P_0 */
9474 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9477 /* VEX_LEN_0F92_P_0 */
9479 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9482 /* VEX_LEN_0F93_P_0 */
9484 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9487 /* VEX_LEN_0F98_P_0 */
9489 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9492 /* VEX_LEN_0FAE_R_2_M_0 */
9494 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9497 /* VEX_LEN_0FAE_R_3_M_0 */
9499 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9502 /* VEX_LEN_0FC2_P_1 */
9504 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9505 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9508 /* VEX_LEN_0FC2_P_3 */
9510 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9511 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9514 /* VEX_LEN_0FC4_P_2 */
9516 { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9519 /* VEX_LEN_0FC5_P_2 */
9521 { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9524 /* VEX_LEN_0FD6_P_2 */
9526 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9527 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9530 /* VEX_LEN_0FF7_P_2 */
9532 { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9535 /* VEX_LEN_0F3816_P_2 */
9538 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9541 /* VEX_LEN_0F3819_P_2 */
9544 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9547 /* VEX_LEN_0F381A_P_2_M_0 */
9550 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9553 /* VEX_LEN_0F3836_P_2 */
9556 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9559 /* VEX_LEN_0F3841_P_2 */
9561 { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9564 /* VEX_LEN_0F385A_P_2_M_0 */
9567 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9570 /* VEX_LEN_0F38DB_P_2 */
9572 { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9575 /* VEX_LEN_0F38DC_P_2 */
9577 { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9580 /* VEX_LEN_0F38DD_P_2 */
9582 { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9585 /* VEX_LEN_0F38DE_P_2 */
9587 { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9590 /* VEX_LEN_0F38DF_P_2 */
9592 { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9595 /* VEX_LEN_0F38F2_P_0 */
9597 { "andnS", { Gdq, VexGdq, Edq } },
9600 /* VEX_LEN_0F38F3_R_1_P_0 */
9602 { "blsrS", { VexGdq, Edq } },
9605 /* VEX_LEN_0F38F3_R_2_P_0 */
9607 { "blsmskS", { VexGdq, Edq } },
9610 /* VEX_LEN_0F38F3_R_3_P_0 */
9612 { "blsiS", { VexGdq, Edq } },
9615 /* VEX_LEN_0F38F5_P_0 */
9617 { "bzhiS", { Gdq, Edq, VexGdq } },
9620 /* VEX_LEN_0F38F5_P_1 */
9622 { "pextS", { Gdq, VexGdq, Edq } },
9625 /* VEX_LEN_0F38F5_P_3 */
9627 { "pdepS", { Gdq, VexGdq, Edq } },
9630 /* VEX_LEN_0F38F6_P_3 */
9632 { "mulxS", { Gdq, VexGdq, Edq } },
9635 /* VEX_LEN_0F38F7_P_0 */
9637 { "bextrS", { Gdq, Edq, VexGdq } },
9640 /* VEX_LEN_0F38F7_P_1 */
9642 { "sarxS", { Gdq, Edq, VexGdq } },
9645 /* VEX_LEN_0F38F7_P_2 */
9647 { "shlxS", { Gdq, Edq, VexGdq } },
9650 /* VEX_LEN_0F38F7_P_3 */
9652 { "shrxS", { Gdq, Edq, VexGdq } },
9655 /* VEX_LEN_0F3A00_P_2 */
9658 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9661 /* VEX_LEN_0F3A01_P_2 */
9664 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9667 /* VEX_LEN_0F3A06_P_2 */
9670 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9673 /* VEX_LEN_0F3A0A_P_2 */
9675 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9676 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9679 /* VEX_LEN_0F3A0B_P_2 */
9681 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9682 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9685 /* VEX_LEN_0F3A14_P_2 */
9687 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9690 /* VEX_LEN_0F3A15_P_2 */
9692 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9695 /* VEX_LEN_0F3A16_P_2 */
9697 { "vpextrK", { Edq, XM, Ib } },
9700 /* VEX_LEN_0F3A17_P_2 */
9702 { "vextractps", { Edqd, XM, Ib } },
9705 /* VEX_LEN_0F3A18_P_2 */
9708 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9711 /* VEX_LEN_0F3A19_P_2 */
9714 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9717 /* VEX_LEN_0F3A20_P_2 */
9719 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
9722 /* VEX_LEN_0F3A21_P_2 */
9724 { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
9727 /* VEX_LEN_0F3A22_P_2 */
9729 { "vpinsrK", { XM, Vex128, Edq, Ib } },
9732 /* VEX_LEN_0F3A30_P_2 */
9734 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9737 /* VEX_LEN_0F3A32_P_2 */
9739 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9742 /* VEX_LEN_0F3A38_P_2 */
9745 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9748 /* VEX_LEN_0F3A39_P_2 */
9751 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9754 /* VEX_LEN_0F3A41_P_2 */
9756 { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
9759 /* VEX_LEN_0F3A44_P_2 */
9761 { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
9764 /* VEX_LEN_0F3A46_P_2 */
9767 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9770 /* VEX_LEN_0F3A60_P_2 */
9772 { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
9775 /* VEX_LEN_0F3A61_P_2 */
9777 { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
9780 /* VEX_LEN_0F3A62_P_2 */
9782 { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
9785 /* VEX_LEN_0F3A63_P_2 */
9787 { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
9790 /* VEX_LEN_0F3A6A_P_2 */
9792 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9795 /* VEX_LEN_0F3A6B_P_2 */
9797 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9800 /* VEX_LEN_0F3A6E_P_2 */
9802 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9805 /* VEX_LEN_0F3A6F_P_2 */
9807 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9810 /* VEX_LEN_0F3A7A_P_2 */
9812 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9815 /* VEX_LEN_0F3A7B_P_2 */
9817 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9820 /* VEX_LEN_0F3A7E_P_2 */
9822 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9825 /* VEX_LEN_0F3A7F_P_2 */
9827 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9830 /* VEX_LEN_0F3ADF_P_2 */
9832 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
9835 /* VEX_LEN_0F3AF0_P_3 */
9837 { "rorxS", { Gdq, Edq, Ib } },
9840 /* VEX_LEN_0FXOP_08_CC */
9842 { "vpcomb", { XM, Vex128, EXx, Ib } },
9845 /* VEX_LEN_0FXOP_08_CD */
9847 { "vpcomw", { XM, Vex128, EXx, Ib } },
9850 /* VEX_LEN_0FXOP_08_CE */
9852 { "vpcomd", { XM, Vex128, EXx, Ib } },
9855 /* VEX_LEN_0FXOP_08_CF */
9857 { "vpcomq", { XM, Vex128, EXx, Ib } },
9860 /* VEX_LEN_0FXOP_08_EC */
9862 { "vpcomub", { XM, Vex128, EXx, Ib } },
9865 /* VEX_LEN_0FXOP_08_ED */
9867 { "vpcomuw", { XM, Vex128, EXx, Ib } },
9870 /* VEX_LEN_0FXOP_08_EE */
9872 { "vpcomud", { XM, Vex128, EXx, Ib } },
9875 /* VEX_LEN_0FXOP_08_EF */
9877 { "vpcomuq", { XM, Vex128, EXx, Ib } },
9880 /* VEX_LEN_0FXOP_09_80 */
9882 { "vfrczps", { XM, EXxmm } },
9883 { "vfrczps", { XM, EXymmq } },
9886 /* VEX_LEN_0FXOP_09_81 */
9888 { "vfrczpd", { XM, EXxmm } },
9889 { "vfrczpd", { XM, EXymmq } },
9893 static const struct dis386 vex_w_table[][2] = {
9895 /* VEX_W_0F10_P_0 */
9896 { "vmovups", { XM, EXx } },
9899 /* VEX_W_0F10_P_1 */
9900 { "vmovss", { XMVexScalar, VexScalar, EXdScalar } },
9903 /* VEX_W_0F10_P_2 */
9904 { "vmovupd", { XM, EXx } },
9907 /* VEX_W_0F10_P_3 */
9908 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } },
9911 /* VEX_W_0F11_P_0 */
9912 { "vmovups", { EXxS, XM } },
9915 /* VEX_W_0F11_P_1 */
9916 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } },
9919 /* VEX_W_0F11_P_2 */
9920 { "vmovupd", { EXxS, XM } },
9923 /* VEX_W_0F11_P_3 */
9924 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } },
9927 /* VEX_W_0F12_P_0_M_0 */
9928 { "vmovlps", { XM, Vex128, EXq } },
9931 /* VEX_W_0F12_P_0_M_1 */
9932 { "vmovhlps", { XM, Vex128, EXq } },
9935 /* VEX_W_0F12_P_1 */
9936 { "vmovsldup", { XM, EXx } },
9939 /* VEX_W_0F12_P_2 */
9940 { "vmovlpd", { XM, Vex128, EXq } },
9943 /* VEX_W_0F12_P_3 */
9944 { "vmovddup", { XM, EXymmq } },
9947 /* VEX_W_0F13_M_0 */
9948 { "vmovlpX", { EXq, XM } },
9952 { "vunpcklpX", { XM, Vex, EXx } },
9956 { "vunpckhpX", { XM, Vex, EXx } },
9959 /* VEX_W_0F16_P_0_M_0 */
9960 { "vmovhps", { XM, Vex128, EXq } },
9963 /* VEX_W_0F16_P_0_M_1 */
9964 { "vmovlhps", { XM, Vex128, EXq } },
9967 /* VEX_W_0F16_P_1 */
9968 { "vmovshdup", { XM, EXx } },
9971 /* VEX_W_0F16_P_2 */
9972 { "vmovhpd", { XM, Vex128, EXq } },
9975 /* VEX_W_0F17_M_0 */
9976 { "vmovhpX", { EXq, XM } },
9980 { "vmovapX", { XM, EXx } },
9984 { "vmovapX", { EXxS, XM } },
9987 /* VEX_W_0F2B_M_0 */
9988 { "vmovntpX", { Mx, XM } },
9991 /* VEX_W_0F2E_P_0 */
9992 { "vucomiss", { XMScalar, EXdScalar } },
9995 /* VEX_W_0F2E_P_2 */
9996 { "vucomisd", { XMScalar, EXqScalar } },
9999 /* VEX_W_0F2F_P_0 */
10000 { "vcomiss", { XMScalar, EXdScalar } },
10003 /* VEX_W_0F2F_P_2 */
10004 { "vcomisd", { XMScalar, EXqScalar } },
10007 /* VEX_W_0F41_P_0_LEN_1 */
10008 { "kandw", { MaskG, MaskVex, MaskR } },
10011 /* VEX_W_0F42_P_0_LEN_1 */
10012 { "kandnw", { MaskG, MaskVex, MaskR } },
10015 /* VEX_W_0F44_P_0_LEN_0 */
10016 { "knotw", { MaskG, MaskR } },
10019 /* VEX_W_0F45_P_0_LEN_1 */
10020 { "korw", { MaskG, MaskVex, MaskR } },
10023 /* VEX_W_0F46_P_0_LEN_1 */
10024 { "kxnorw", { MaskG, MaskVex, MaskR } },
10027 /* VEX_W_0F47_P_0_LEN_1 */
10028 { "kxorw", { MaskG, MaskVex, MaskR } },
10031 /* VEX_W_0F4B_P_2_LEN_1 */
10032 { "kunpckbw", { MaskG, MaskVex, MaskR } },
10035 /* VEX_W_0F50_M_0 */
10036 { "vmovmskpX", { Gdq, XS } },
10039 /* VEX_W_0F51_P_0 */
10040 { "vsqrtps", { XM, EXx } },
10043 /* VEX_W_0F51_P_1 */
10044 { "vsqrtss", { XMScalar, VexScalar, EXdScalar } },
10047 /* VEX_W_0F51_P_2 */
10048 { "vsqrtpd", { XM, EXx } },
10051 /* VEX_W_0F51_P_3 */
10052 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar } },
10055 /* VEX_W_0F52_P_0 */
10056 { "vrsqrtps", { XM, EXx } },
10059 /* VEX_W_0F52_P_1 */
10060 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar } },
10063 /* VEX_W_0F53_P_0 */
10064 { "vrcpps", { XM, EXx } },
10067 /* VEX_W_0F53_P_1 */
10068 { "vrcpss", { XMScalar, VexScalar, EXdScalar } },
10071 /* VEX_W_0F58_P_0 */
10072 { "vaddps", { XM, Vex, EXx } },
10075 /* VEX_W_0F58_P_1 */
10076 { "vaddss", { XMScalar, VexScalar, EXdScalar } },
10079 /* VEX_W_0F58_P_2 */
10080 { "vaddpd", { XM, Vex, EXx } },
10083 /* VEX_W_0F58_P_3 */
10084 { "vaddsd", { XMScalar, VexScalar, EXqScalar } },
10087 /* VEX_W_0F59_P_0 */
10088 { "vmulps", { XM, Vex, EXx } },
10091 /* VEX_W_0F59_P_1 */
10092 { "vmulss", { XMScalar, VexScalar, EXdScalar } },
10095 /* VEX_W_0F59_P_2 */
10096 { "vmulpd", { XM, Vex, EXx } },
10099 /* VEX_W_0F59_P_3 */
10100 { "vmulsd", { XMScalar, VexScalar, EXqScalar } },
10103 /* VEX_W_0F5A_P_0 */
10104 { "vcvtps2pd", { XM, EXxmmq } },
10107 /* VEX_W_0F5A_P_1 */
10108 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar } },
10111 /* VEX_W_0F5A_P_3 */
10112 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar } },
10115 /* VEX_W_0F5B_P_0 */
10116 { "vcvtdq2ps", { XM, EXx } },
10119 /* VEX_W_0F5B_P_1 */
10120 { "vcvttps2dq", { XM, EXx } },
10123 /* VEX_W_0F5B_P_2 */
10124 { "vcvtps2dq", { XM, EXx } },
10127 /* VEX_W_0F5C_P_0 */
10128 { "vsubps", { XM, Vex, EXx } },
10131 /* VEX_W_0F5C_P_1 */
10132 { "vsubss", { XMScalar, VexScalar, EXdScalar } },
10135 /* VEX_W_0F5C_P_2 */
10136 { "vsubpd", { XM, Vex, EXx } },
10139 /* VEX_W_0F5C_P_3 */
10140 { "vsubsd", { XMScalar, VexScalar, EXqScalar } },
10143 /* VEX_W_0F5D_P_0 */
10144 { "vminps", { XM, Vex, EXx } },
10147 /* VEX_W_0F5D_P_1 */
10148 { "vminss", { XMScalar, VexScalar, EXdScalar } },
10151 /* VEX_W_0F5D_P_2 */
10152 { "vminpd", { XM, Vex, EXx } },
10155 /* VEX_W_0F5D_P_3 */
10156 { "vminsd", { XMScalar, VexScalar, EXqScalar } },
10159 /* VEX_W_0F5E_P_0 */
10160 { "vdivps", { XM, Vex, EXx } },
10163 /* VEX_W_0F5E_P_1 */
10164 { "vdivss", { XMScalar, VexScalar, EXdScalar } },
10167 /* VEX_W_0F5E_P_2 */
10168 { "vdivpd", { XM, Vex, EXx } },
10171 /* VEX_W_0F5E_P_3 */
10172 { "vdivsd", { XMScalar, VexScalar, EXqScalar } },
10175 /* VEX_W_0F5F_P_0 */
10176 { "vmaxps", { XM, Vex, EXx } },
10179 /* VEX_W_0F5F_P_1 */
10180 { "vmaxss", { XMScalar, VexScalar, EXdScalar } },
10183 /* VEX_W_0F5F_P_2 */
10184 { "vmaxpd", { XM, Vex, EXx } },
10187 /* VEX_W_0F5F_P_3 */
10188 { "vmaxsd", { XMScalar, VexScalar, EXqScalar } },
10191 /* VEX_W_0F60_P_2 */
10192 { "vpunpcklbw", { XM, Vex, EXx } },
10195 /* VEX_W_0F61_P_2 */
10196 { "vpunpcklwd", { XM, Vex, EXx } },
10199 /* VEX_W_0F62_P_2 */
10200 { "vpunpckldq", { XM, Vex, EXx } },
10203 /* VEX_W_0F63_P_2 */
10204 { "vpacksswb", { XM, Vex, EXx } },
10207 /* VEX_W_0F64_P_2 */
10208 { "vpcmpgtb", { XM, Vex, EXx } },
10211 /* VEX_W_0F65_P_2 */
10212 { "vpcmpgtw", { XM, Vex, EXx } },
10215 /* VEX_W_0F66_P_2 */
10216 { "vpcmpgtd", { XM, Vex, EXx } },
10219 /* VEX_W_0F67_P_2 */
10220 { "vpackuswb", { XM, Vex, EXx } },
10223 /* VEX_W_0F68_P_2 */
10224 { "vpunpckhbw", { XM, Vex, EXx } },
10227 /* VEX_W_0F69_P_2 */
10228 { "vpunpckhwd", { XM, Vex, EXx } },
10231 /* VEX_W_0F6A_P_2 */
10232 { "vpunpckhdq", { XM, Vex, EXx } },
10235 /* VEX_W_0F6B_P_2 */
10236 { "vpackssdw", { XM, Vex, EXx } },
10239 /* VEX_W_0F6C_P_2 */
10240 { "vpunpcklqdq", { XM, Vex, EXx } },
10243 /* VEX_W_0F6D_P_2 */
10244 { "vpunpckhqdq", { XM, Vex, EXx } },
10247 /* VEX_W_0F6F_P_1 */
10248 { "vmovdqu", { XM, EXx } },
10251 /* VEX_W_0F6F_P_2 */
10252 { "vmovdqa", { XM, EXx } },
10255 /* VEX_W_0F70_P_1 */
10256 { "vpshufhw", { XM, EXx, Ib } },
10259 /* VEX_W_0F70_P_2 */
10260 { "vpshufd", { XM, EXx, Ib } },
10263 /* VEX_W_0F70_P_3 */
10264 { "vpshuflw", { XM, EXx, Ib } },
10267 /* VEX_W_0F71_R_2_P_2 */
10268 { "vpsrlw", { Vex, XS, Ib } },
10271 /* VEX_W_0F71_R_4_P_2 */
10272 { "vpsraw", { Vex, XS, Ib } },
10275 /* VEX_W_0F71_R_6_P_2 */
10276 { "vpsllw", { Vex, XS, Ib } },
10279 /* VEX_W_0F72_R_2_P_2 */
10280 { "vpsrld", { Vex, XS, Ib } },
10283 /* VEX_W_0F72_R_4_P_2 */
10284 { "vpsrad", { Vex, XS, Ib } },
10287 /* VEX_W_0F72_R_6_P_2 */
10288 { "vpslld", { Vex, XS, Ib } },
10291 /* VEX_W_0F73_R_2_P_2 */
10292 { "vpsrlq", { Vex, XS, Ib } },
10295 /* VEX_W_0F73_R_3_P_2 */
10296 { "vpsrldq", { Vex, XS, Ib } },
10299 /* VEX_W_0F73_R_6_P_2 */
10300 { "vpsllq", { Vex, XS, Ib } },
10303 /* VEX_W_0F73_R_7_P_2 */
10304 { "vpslldq", { Vex, XS, Ib } },
10307 /* VEX_W_0F74_P_2 */
10308 { "vpcmpeqb", { XM, Vex, EXx } },
10311 /* VEX_W_0F75_P_2 */
10312 { "vpcmpeqw", { XM, Vex, EXx } },
10315 /* VEX_W_0F76_P_2 */
10316 { "vpcmpeqd", { XM, Vex, EXx } },
10319 /* VEX_W_0F77_P_0 */
10323 /* VEX_W_0F7C_P_2 */
10324 { "vhaddpd", { XM, Vex, EXx } },
10327 /* VEX_W_0F7C_P_3 */
10328 { "vhaddps", { XM, Vex, EXx } },
10331 /* VEX_W_0F7D_P_2 */
10332 { "vhsubpd", { XM, Vex, EXx } },
10335 /* VEX_W_0F7D_P_3 */
10336 { "vhsubps", { XM, Vex, EXx } },
10339 /* VEX_W_0F7E_P_1 */
10340 { "vmovq", { XMScalar, EXqScalar } },
10343 /* VEX_W_0F7F_P_1 */
10344 { "vmovdqu", { EXxS, XM } },
10347 /* VEX_W_0F7F_P_2 */
10348 { "vmovdqa", { EXxS, XM } },
10351 /* VEX_W_0F90_P_0_LEN_0 */
10352 { "kmovw", { MaskG, MaskE } },
10355 /* VEX_W_0F91_P_0_LEN_0 */
10356 { "kmovw", { Ew, MaskG } },
10359 /* VEX_W_0F92_P_0_LEN_0 */
10360 { "kmovw", { MaskG, Rdq } },
10363 /* VEX_W_0F93_P_0_LEN_0 */
10364 { "kmovw", { Gdq, MaskR } },
10367 /* VEX_W_0F98_P_0_LEN_0 */
10368 { "kortestw", { MaskG, MaskR } },
10371 /* VEX_W_0FAE_R_2_M_0 */
10372 { "vldmxcsr", { Md } },
10375 /* VEX_W_0FAE_R_3_M_0 */
10376 { "vstmxcsr", { Md } },
10379 /* VEX_W_0FC2_P_0 */
10380 { "vcmpps", { XM, Vex, EXx, VCMP } },
10383 /* VEX_W_0FC2_P_1 */
10384 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP } },
10387 /* VEX_W_0FC2_P_2 */
10388 { "vcmppd", { XM, Vex, EXx, VCMP } },
10391 /* VEX_W_0FC2_P_3 */
10392 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP } },
10395 /* VEX_W_0FC4_P_2 */
10396 { "vpinsrw", { XM, Vex128, Edqw, Ib } },
10399 /* VEX_W_0FC5_P_2 */
10400 { "vpextrw", { Gdq, XS, Ib } },
10403 /* VEX_W_0FD0_P_2 */
10404 { "vaddsubpd", { XM, Vex, EXx } },
10407 /* VEX_W_0FD0_P_3 */
10408 { "vaddsubps", { XM, Vex, EXx } },
10411 /* VEX_W_0FD1_P_2 */
10412 { "vpsrlw", { XM, Vex, EXxmm } },
10415 /* VEX_W_0FD2_P_2 */
10416 { "vpsrld", { XM, Vex, EXxmm } },
10419 /* VEX_W_0FD3_P_2 */
10420 { "vpsrlq", { XM, Vex, EXxmm } },
10423 /* VEX_W_0FD4_P_2 */
10424 { "vpaddq", { XM, Vex, EXx } },
10427 /* VEX_W_0FD5_P_2 */
10428 { "vpmullw", { XM, Vex, EXx } },
10431 /* VEX_W_0FD6_P_2 */
10432 { "vmovq", { EXqScalarS, XMScalar } },
10435 /* VEX_W_0FD7_P_2_M_1 */
10436 { "vpmovmskb", { Gdq, XS } },
10439 /* VEX_W_0FD8_P_2 */
10440 { "vpsubusb", { XM, Vex, EXx } },
10443 /* VEX_W_0FD9_P_2 */
10444 { "vpsubusw", { XM, Vex, EXx } },
10447 /* VEX_W_0FDA_P_2 */
10448 { "vpminub", { XM, Vex, EXx } },
10451 /* VEX_W_0FDB_P_2 */
10452 { "vpand", { XM, Vex, EXx } },
10455 /* VEX_W_0FDC_P_2 */
10456 { "vpaddusb", { XM, Vex, EXx } },
10459 /* VEX_W_0FDD_P_2 */
10460 { "vpaddusw", { XM, Vex, EXx } },
10463 /* VEX_W_0FDE_P_2 */
10464 { "vpmaxub", { XM, Vex, EXx } },
10467 /* VEX_W_0FDF_P_2 */
10468 { "vpandn", { XM, Vex, EXx } },
10471 /* VEX_W_0FE0_P_2 */
10472 { "vpavgb", { XM, Vex, EXx } },
10475 /* VEX_W_0FE1_P_2 */
10476 { "vpsraw", { XM, Vex, EXxmm } },
10479 /* VEX_W_0FE2_P_2 */
10480 { "vpsrad", { XM, Vex, EXxmm } },
10483 /* VEX_W_0FE3_P_2 */
10484 { "vpavgw", { XM, Vex, EXx } },
10487 /* VEX_W_0FE4_P_2 */
10488 { "vpmulhuw", { XM, Vex, EXx } },
10491 /* VEX_W_0FE5_P_2 */
10492 { "vpmulhw", { XM, Vex, EXx } },
10495 /* VEX_W_0FE6_P_1 */
10496 { "vcvtdq2pd", { XM, EXxmmq } },
10499 /* VEX_W_0FE6_P_2 */
10500 { "vcvttpd2dq%XY", { XMM, EXx } },
10503 /* VEX_W_0FE6_P_3 */
10504 { "vcvtpd2dq%XY", { XMM, EXx } },
10507 /* VEX_W_0FE7_P_2_M_0 */
10508 { "vmovntdq", { Mx, XM } },
10511 /* VEX_W_0FE8_P_2 */
10512 { "vpsubsb", { XM, Vex, EXx } },
10515 /* VEX_W_0FE9_P_2 */
10516 { "vpsubsw", { XM, Vex, EXx } },
10519 /* VEX_W_0FEA_P_2 */
10520 { "vpminsw", { XM, Vex, EXx } },
10523 /* VEX_W_0FEB_P_2 */
10524 { "vpor", { XM, Vex, EXx } },
10527 /* VEX_W_0FEC_P_2 */
10528 { "vpaddsb", { XM, Vex, EXx } },
10531 /* VEX_W_0FED_P_2 */
10532 { "vpaddsw", { XM, Vex, EXx } },
10535 /* VEX_W_0FEE_P_2 */
10536 { "vpmaxsw", { XM, Vex, EXx } },
10539 /* VEX_W_0FEF_P_2 */
10540 { "vpxor", { XM, Vex, EXx } },
10543 /* VEX_W_0FF0_P_3_M_0 */
10544 { "vlddqu", { XM, M } },
10547 /* VEX_W_0FF1_P_2 */
10548 { "vpsllw", { XM, Vex, EXxmm } },
10551 /* VEX_W_0FF2_P_2 */
10552 { "vpslld", { XM, Vex, EXxmm } },
10555 /* VEX_W_0FF3_P_2 */
10556 { "vpsllq", { XM, Vex, EXxmm } },
10559 /* VEX_W_0FF4_P_2 */
10560 { "vpmuludq", { XM, Vex, EXx } },
10563 /* VEX_W_0FF5_P_2 */
10564 { "vpmaddwd", { XM, Vex, EXx } },
10567 /* VEX_W_0FF6_P_2 */
10568 { "vpsadbw", { XM, Vex, EXx } },
10571 /* VEX_W_0FF7_P_2 */
10572 { "vmaskmovdqu", { XM, XS } },
10575 /* VEX_W_0FF8_P_2 */
10576 { "vpsubb", { XM, Vex, EXx } },
10579 /* VEX_W_0FF9_P_2 */
10580 { "vpsubw", { XM, Vex, EXx } },
10583 /* VEX_W_0FFA_P_2 */
10584 { "vpsubd", { XM, Vex, EXx } },
10587 /* VEX_W_0FFB_P_2 */
10588 { "vpsubq", { XM, Vex, EXx } },
10591 /* VEX_W_0FFC_P_2 */
10592 { "vpaddb", { XM, Vex, EXx } },
10595 /* VEX_W_0FFD_P_2 */
10596 { "vpaddw", { XM, Vex, EXx } },
10599 /* VEX_W_0FFE_P_2 */
10600 { "vpaddd", { XM, Vex, EXx } },
10603 /* VEX_W_0F3800_P_2 */
10604 { "vpshufb", { XM, Vex, EXx } },
10607 /* VEX_W_0F3801_P_2 */
10608 { "vphaddw", { XM, Vex, EXx } },
10611 /* VEX_W_0F3802_P_2 */
10612 { "vphaddd", { XM, Vex, EXx } },
10615 /* VEX_W_0F3803_P_2 */
10616 { "vphaddsw", { XM, Vex, EXx } },
10619 /* VEX_W_0F3804_P_2 */
10620 { "vpmaddubsw", { XM, Vex, EXx } },
10623 /* VEX_W_0F3805_P_2 */
10624 { "vphsubw", { XM, Vex, EXx } },
10627 /* VEX_W_0F3806_P_2 */
10628 { "vphsubd", { XM, Vex, EXx } },
10631 /* VEX_W_0F3807_P_2 */
10632 { "vphsubsw", { XM, Vex, EXx } },
10635 /* VEX_W_0F3808_P_2 */
10636 { "vpsignb", { XM, Vex, EXx } },
10639 /* VEX_W_0F3809_P_2 */
10640 { "vpsignw", { XM, Vex, EXx } },
10643 /* VEX_W_0F380A_P_2 */
10644 { "vpsignd", { XM, Vex, EXx } },
10647 /* VEX_W_0F380B_P_2 */
10648 { "vpmulhrsw", { XM, Vex, EXx } },
10651 /* VEX_W_0F380C_P_2 */
10652 { "vpermilps", { XM, Vex, EXx } },
10655 /* VEX_W_0F380D_P_2 */
10656 { "vpermilpd", { XM, Vex, EXx } },
10659 /* VEX_W_0F380E_P_2 */
10660 { "vtestps", { XM, EXx } },
10663 /* VEX_W_0F380F_P_2 */
10664 { "vtestpd", { XM, EXx } },
10667 /* VEX_W_0F3816_P_2 */
10668 { "vpermps", { XM, Vex, EXx } },
10671 /* VEX_W_0F3817_P_2 */
10672 { "vptest", { XM, EXx } },
10675 /* VEX_W_0F3818_P_2 */
10676 { "vbroadcastss", { XM, EXxmm_md } },
10679 /* VEX_W_0F3819_P_2 */
10680 { "vbroadcastsd", { XM, EXxmm_mq } },
10683 /* VEX_W_0F381A_P_2_M_0 */
10684 { "vbroadcastf128", { XM, Mxmm } },
10687 /* VEX_W_0F381C_P_2 */
10688 { "vpabsb", { XM, EXx } },
10691 /* VEX_W_0F381D_P_2 */
10692 { "vpabsw", { XM, EXx } },
10695 /* VEX_W_0F381E_P_2 */
10696 { "vpabsd", { XM, EXx } },
10699 /* VEX_W_0F3820_P_2 */
10700 { "vpmovsxbw", { XM, EXxmmq } },
10703 /* VEX_W_0F3821_P_2 */
10704 { "vpmovsxbd", { XM, EXxmmqd } },
10707 /* VEX_W_0F3822_P_2 */
10708 { "vpmovsxbq", { XM, EXxmmdw } },
10711 /* VEX_W_0F3823_P_2 */
10712 { "vpmovsxwd", { XM, EXxmmq } },
10715 /* VEX_W_0F3824_P_2 */
10716 { "vpmovsxwq", { XM, EXxmmqd } },
10719 /* VEX_W_0F3825_P_2 */
10720 { "vpmovsxdq", { XM, EXxmmq } },
10723 /* VEX_W_0F3828_P_2 */
10724 { "vpmuldq", { XM, Vex, EXx } },
10727 /* VEX_W_0F3829_P_2 */
10728 { "vpcmpeqq", { XM, Vex, EXx } },
10731 /* VEX_W_0F382A_P_2_M_0 */
10732 { "vmovntdqa", { XM, Mx } },
10735 /* VEX_W_0F382B_P_2 */
10736 { "vpackusdw", { XM, Vex, EXx } },
10739 /* VEX_W_0F382C_P_2_M_0 */
10740 { "vmaskmovps", { XM, Vex, Mx } },
10743 /* VEX_W_0F382D_P_2_M_0 */
10744 { "vmaskmovpd", { XM, Vex, Mx } },
10747 /* VEX_W_0F382E_P_2_M_0 */
10748 { "vmaskmovps", { Mx, Vex, XM } },
10751 /* VEX_W_0F382F_P_2_M_0 */
10752 { "vmaskmovpd", { Mx, Vex, XM } },
10755 /* VEX_W_0F3830_P_2 */
10756 { "vpmovzxbw", { XM, EXxmmq } },
10759 /* VEX_W_0F3831_P_2 */
10760 { "vpmovzxbd", { XM, EXxmmqd } },
10763 /* VEX_W_0F3832_P_2 */
10764 { "vpmovzxbq", { XM, EXxmmdw } },
10767 /* VEX_W_0F3833_P_2 */
10768 { "vpmovzxwd", { XM, EXxmmq } },
10771 /* VEX_W_0F3834_P_2 */
10772 { "vpmovzxwq", { XM, EXxmmqd } },
10775 /* VEX_W_0F3835_P_2 */
10776 { "vpmovzxdq", { XM, EXxmmq } },
10779 /* VEX_W_0F3836_P_2 */
10780 { "vpermd", { XM, Vex, EXx } },
10783 /* VEX_W_0F3837_P_2 */
10784 { "vpcmpgtq", { XM, Vex, EXx } },
10787 /* VEX_W_0F3838_P_2 */
10788 { "vpminsb", { XM, Vex, EXx } },
10791 /* VEX_W_0F3839_P_2 */
10792 { "vpminsd", { XM, Vex, EXx } },
10795 /* VEX_W_0F383A_P_2 */
10796 { "vpminuw", { XM, Vex, EXx } },
10799 /* VEX_W_0F383B_P_2 */
10800 { "vpminud", { XM, Vex, EXx } },
10803 /* VEX_W_0F383C_P_2 */
10804 { "vpmaxsb", { XM, Vex, EXx } },
10807 /* VEX_W_0F383D_P_2 */
10808 { "vpmaxsd", { XM, Vex, EXx } },
10811 /* VEX_W_0F383E_P_2 */
10812 { "vpmaxuw", { XM, Vex, EXx } },
10815 /* VEX_W_0F383F_P_2 */
10816 { "vpmaxud", { XM, Vex, EXx } },
10819 /* VEX_W_0F3840_P_2 */
10820 { "vpmulld", { XM, Vex, EXx } },
10823 /* VEX_W_0F3841_P_2 */
10824 { "vphminposuw", { XM, EXx } },
10827 /* VEX_W_0F3846_P_2 */
10828 { "vpsravd", { XM, Vex, EXx } },
10831 /* VEX_W_0F3858_P_2 */
10832 { "vpbroadcastd", { XM, EXxmm_md } },
10835 /* VEX_W_0F3859_P_2 */
10836 { "vpbroadcastq", { XM, EXxmm_mq } },
10839 /* VEX_W_0F385A_P_2_M_0 */
10840 { "vbroadcasti128", { XM, Mxmm } },
10843 /* VEX_W_0F3878_P_2 */
10844 { "vpbroadcastb", { XM, EXxmm_mb } },
10847 /* VEX_W_0F3879_P_2 */
10848 { "vpbroadcastw", { XM, EXxmm_mw } },
10851 /* VEX_W_0F38DB_P_2 */
10852 { "vaesimc", { XM, EXx } },
10855 /* VEX_W_0F38DC_P_2 */
10856 { "vaesenc", { XM, Vex128, EXx } },
10859 /* VEX_W_0F38DD_P_2 */
10860 { "vaesenclast", { XM, Vex128, EXx } },
10863 /* VEX_W_0F38DE_P_2 */
10864 { "vaesdec", { XM, Vex128, EXx } },
10867 /* VEX_W_0F38DF_P_2 */
10868 { "vaesdeclast", { XM, Vex128, EXx } },
10871 /* VEX_W_0F3A00_P_2 */
10873 { "vpermq", { XM, EXx, Ib } },
10876 /* VEX_W_0F3A01_P_2 */
10878 { "vpermpd", { XM, EXx, Ib } },
10881 /* VEX_W_0F3A02_P_2 */
10882 { "vpblendd", { XM, Vex, EXx, Ib } },
10885 /* VEX_W_0F3A04_P_2 */
10886 { "vpermilps", { XM, EXx, Ib } },
10889 /* VEX_W_0F3A05_P_2 */
10890 { "vpermilpd", { XM, EXx, Ib } },
10893 /* VEX_W_0F3A06_P_2 */
10894 { "vperm2f128", { XM, Vex256, EXx, Ib } },
10897 /* VEX_W_0F3A08_P_2 */
10898 { "vroundps", { XM, EXx, Ib } },
10901 /* VEX_W_0F3A09_P_2 */
10902 { "vroundpd", { XM, EXx, Ib } },
10905 /* VEX_W_0F3A0A_P_2 */
10906 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib } },
10909 /* VEX_W_0F3A0B_P_2 */
10910 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib } },
10913 /* VEX_W_0F3A0C_P_2 */
10914 { "vblendps", { XM, Vex, EXx, Ib } },
10917 /* VEX_W_0F3A0D_P_2 */
10918 { "vblendpd", { XM, Vex, EXx, Ib } },
10921 /* VEX_W_0F3A0E_P_2 */
10922 { "vpblendw", { XM, Vex, EXx, Ib } },
10925 /* VEX_W_0F3A0F_P_2 */
10926 { "vpalignr", { XM, Vex, EXx, Ib } },
10929 /* VEX_W_0F3A14_P_2 */
10930 { "vpextrb", { Edqb, XM, Ib } },
10933 /* VEX_W_0F3A15_P_2 */
10934 { "vpextrw", { Edqw, XM, Ib } },
10937 /* VEX_W_0F3A18_P_2 */
10938 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },
10941 /* VEX_W_0F3A19_P_2 */
10942 { "vextractf128", { EXxmm, XM, Ib } },
10945 /* VEX_W_0F3A20_P_2 */
10946 { "vpinsrb", { XM, Vex128, Edqb, Ib } },
10949 /* VEX_W_0F3A21_P_2 */
10950 { "vinsertps", { XM, Vex128, EXd, Ib } },
10953 /* VEX_W_0F3A30_P_2 */
10955 { "kshiftrw", { MaskG, MaskR, Ib } },
10958 /* VEX_W_0F3A32_P_2 */
10960 { "kshiftlw", { MaskG, MaskR, Ib } },
10963 /* VEX_W_0F3A38_P_2 */
10964 { "vinserti128", { XM, Vex256, EXxmm, Ib } },
10967 /* VEX_W_0F3A39_P_2 */
10968 { "vextracti128", { EXxmm, XM, Ib } },
10971 /* VEX_W_0F3A40_P_2 */
10972 { "vdpps", { XM, Vex, EXx, Ib } },
10975 /* VEX_W_0F3A41_P_2 */
10976 { "vdppd", { XM, Vex128, EXx, Ib } },
10979 /* VEX_W_0F3A42_P_2 */
10980 { "vmpsadbw", { XM, Vex, EXx, Ib } },
10983 /* VEX_W_0F3A44_P_2 */
10984 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } },
10987 /* VEX_W_0F3A46_P_2 */
10988 { "vperm2i128", { XM, Vex256, EXx, Ib } },
10991 /* VEX_W_0F3A48_P_2 */
10992 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10993 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10996 /* VEX_W_0F3A49_P_2 */
10997 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10998 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11001 /* VEX_W_0F3A4A_P_2 */
11002 { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
11005 /* VEX_W_0F3A4B_P_2 */
11006 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
11009 /* VEX_W_0F3A4C_P_2 */
11010 { "vpblendvb", { XM, Vex, EXx, XMVexI4 } },
11013 /* VEX_W_0F3A60_P_2 */
11014 { "vpcmpestrm", { XM, EXx, Ib } },
11017 /* VEX_W_0F3A61_P_2 */
11018 { "vpcmpestri", { XM, EXx, Ib } },
11021 /* VEX_W_0F3A62_P_2 */
11022 { "vpcmpistrm", { XM, EXx, Ib } },
11025 /* VEX_W_0F3A63_P_2 */
11026 { "vpcmpistri", { XM, EXx, Ib } },
11029 /* VEX_W_0F3ADF_P_2 */
11030 { "vaeskeygenassist", { XM, EXx, Ib } },
11032 #define NEED_VEX_W_TABLE
11033 #include "i386-dis-evex.h"
11034 #undef NEED_VEX_W_TABLE
11037 static const struct dis386 mod_table[][2] = {
11040 { "leaS", { Gv, M } },
11045 { RM_TABLE (RM_C6_REG_7) },
11050 { RM_TABLE (RM_C7_REG_7) },
11053 /* MOD_0F01_REG_0 */
11054 { X86_64_TABLE (X86_64_0F01_REG_0) },
11055 { RM_TABLE (RM_0F01_REG_0) },
11058 /* MOD_0F01_REG_1 */
11059 { X86_64_TABLE (X86_64_0F01_REG_1) },
11060 { RM_TABLE (RM_0F01_REG_1) },
11063 /* MOD_0F01_REG_2 */
11064 { X86_64_TABLE (X86_64_0F01_REG_2) },
11065 { RM_TABLE (RM_0F01_REG_2) },
11068 /* MOD_0F01_REG_3 */
11069 { X86_64_TABLE (X86_64_0F01_REG_3) },
11070 { RM_TABLE (RM_0F01_REG_3) },
11073 /* MOD_0F01_REG_7 */
11074 { "invlpg", { Mb } },
11075 { RM_TABLE (RM_0F01_REG_7) },
11078 /* MOD_0F12_PREFIX_0 */
11079 { "movlps", { XM, EXq } },
11080 { "movhlps", { XM, EXq } },
11084 { "movlpX", { EXq, XM } },
11087 /* MOD_0F16_PREFIX_0 */
11088 { "movhps", { XM, EXq } },
11089 { "movlhps", { XM, EXq } },
11093 { "movhpX", { EXq, XM } },
11096 /* MOD_0F18_REG_0 */
11097 { "prefetchnta", { Mb } },
11100 /* MOD_0F18_REG_1 */
11101 { "prefetcht0", { Mb } },
11104 /* MOD_0F18_REG_2 */
11105 { "prefetcht1", { Mb } },
11108 /* MOD_0F18_REG_3 */
11109 { "prefetcht2", { Mb } },
11112 /* MOD_0F18_REG_4 */
11113 { "nop/reserved", { Mb } },
11116 /* MOD_0F18_REG_5 */
11117 { "nop/reserved", { Mb } },
11120 /* MOD_0F18_REG_6 */
11121 { "nop/reserved", { Mb } },
11124 /* MOD_0F18_REG_7 */
11125 { "nop/reserved", { Mb } },
11128 /* MOD_0F1A_PREFIX_0 */
11129 { "bndldx", { Gbnd, Ev_bnd } },
11130 { "nopQ", { Ev } },
11133 /* MOD_0F1B_PREFIX_0 */
11134 { "bndstx", { Ev_bnd, Gbnd } },
11135 { "nopQ", { Ev } },
11138 /* MOD_0F1B_PREFIX_1 */
11139 { "bndmk", { Gbnd, Ev_bnd } },
11140 { "nopQ", { Ev } },
11145 { "movZ", { Rm, Cm } },
11150 { "movZ", { Rm, Dm } },
11155 { "movZ", { Cm, Rm } },
11160 { "movZ", { Dm, Rm } },
11165 { "movL", { Rd, Td } },
11170 { "movL", { Td, Rd } },
11173 /* MOD_0F2B_PREFIX_0 */
11174 {"movntps", { Mx, XM } },
11177 /* MOD_0F2B_PREFIX_1 */
11178 {"movntss", { Md, XM } },
11181 /* MOD_0F2B_PREFIX_2 */
11182 {"movntpd", { Mx, XM } },
11185 /* MOD_0F2B_PREFIX_3 */
11186 {"movntsd", { Mq, XM } },
11191 { "movmskpX", { Gdq, XS } },
11194 /* MOD_0F71_REG_2 */
11196 { "psrlw", { MS, Ib } },
11199 /* MOD_0F71_REG_4 */
11201 { "psraw", { MS, Ib } },
11204 /* MOD_0F71_REG_6 */
11206 { "psllw", { MS, Ib } },
11209 /* MOD_0F72_REG_2 */
11211 { "psrld", { MS, Ib } },
11214 /* MOD_0F72_REG_4 */
11216 { "psrad", { MS, Ib } },
11219 /* MOD_0F72_REG_6 */
11221 { "pslld", { MS, Ib } },
11224 /* MOD_0F73_REG_2 */
11226 { "psrlq", { MS, Ib } },
11229 /* MOD_0F73_REG_3 */
11231 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11234 /* MOD_0F73_REG_6 */
11236 { "psllq", { MS, Ib } },
11239 /* MOD_0F73_REG_7 */
11241 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11244 /* MOD_0FAE_REG_0 */
11245 { "fxsave", { FXSAVE } },
11246 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11249 /* MOD_0FAE_REG_1 */
11250 { "fxrstor", { FXSAVE } },
11251 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11254 /* MOD_0FAE_REG_2 */
11255 { "ldmxcsr", { Md } },
11256 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11259 /* MOD_0FAE_REG_3 */
11260 { "stmxcsr", { Md } },
11261 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11264 /* MOD_0FAE_REG_4 */
11265 { "xsave", { FXSAVE } },
11268 /* MOD_0FAE_REG_5 */
11269 { "xrstor", { FXSAVE } },
11270 { RM_TABLE (RM_0FAE_REG_5) },
11273 /* MOD_0FAE_REG_6 */
11274 { "xsaveopt", { FXSAVE } },
11275 { RM_TABLE (RM_0FAE_REG_6) },
11278 /* MOD_0FAE_REG_7 */
11279 { "clflush", { Mb } },
11280 { RM_TABLE (RM_0FAE_REG_7) },
11284 { "lssS", { Gv, Mp } },
11288 { "lfsS", { Gv, Mp } },
11292 { "lgsS", { Gv, Mp } },
11295 /* MOD_0FC7_REG_6 */
11296 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
11297 { "rdrand", { Ev } },
11300 /* MOD_0FC7_REG_7 */
11301 { "vmptrst", { Mq } },
11302 { "rdseed", { Ev } },
11307 { "pmovmskb", { Gdq, MS } },
11310 /* MOD_0FE7_PREFIX_2 */
11311 { "movntdq", { Mx, XM } },
11314 /* MOD_0FF0_PREFIX_3 */
11315 { "lddqu", { XM, M } },
11318 /* MOD_0F382A_PREFIX_2 */
11319 { "movntdqa", { XM, Mx } },
11323 { "bound{S|}", { Gv, Ma } },
11324 { EVEX_TABLE (EVEX_0F) },
11328 { "lesS", { Gv, Mp } },
11329 { VEX_C4_TABLE (VEX_0F) },
11333 { "ldsS", { Gv, Mp } },
11334 { VEX_C5_TABLE (VEX_0F) },
11337 /* MOD_VEX_0F12_PREFIX_0 */
11338 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11339 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11343 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11346 /* MOD_VEX_0F16_PREFIX_0 */
11347 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11348 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11352 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11356 { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11361 { VEX_W_TABLE (VEX_W_0F50_M_0) },
11364 /* MOD_VEX_0F71_REG_2 */
11366 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11369 /* MOD_VEX_0F71_REG_4 */
11371 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11374 /* MOD_VEX_0F71_REG_6 */
11376 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11379 /* MOD_VEX_0F72_REG_2 */
11381 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11384 /* MOD_VEX_0F72_REG_4 */
11386 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11389 /* MOD_VEX_0F72_REG_6 */
11391 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11394 /* MOD_VEX_0F73_REG_2 */
11396 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11399 /* MOD_VEX_0F73_REG_3 */
11401 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11404 /* MOD_VEX_0F73_REG_6 */
11406 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11409 /* MOD_VEX_0F73_REG_7 */
11411 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11414 /* MOD_VEX_0FAE_REG_2 */
11415 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11418 /* MOD_VEX_0FAE_REG_3 */
11419 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11422 /* MOD_VEX_0FD7_PREFIX_2 */
11424 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11427 /* MOD_VEX_0FE7_PREFIX_2 */
11428 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11431 /* MOD_VEX_0FF0_PREFIX_3 */
11432 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11435 /* MOD_VEX_0F381A_PREFIX_2 */
11436 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11439 /* MOD_VEX_0F382A_PREFIX_2 */
11440 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11443 /* MOD_VEX_0F382C_PREFIX_2 */
11444 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11447 /* MOD_VEX_0F382D_PREFIX_2 */
11448 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11451 /* MOD_VEX_0F382E_PREFIX_2 */
11452 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11455 /* MOD_VEX_0F382F_PREFIX_2 */
11456 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11459 /* MOD_VEX_0F385A_PREFIX_2 */
11460 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11463 /* MOD_VEX_0F388C_PREFIX_2 */
11464 { "vpmaskmov%LW", { XM, Vex, Mx } },
11467 /* MOD_VEX_0F388E_PREFIX_2 */
11468 { "vpmaskmov%LW", { Mx, Vex, XM } },
11470 #define NEED_MOD_TABLE
11471 #include "i386-dis-evex.h"
11472 #undef NEED_MOD_TABLE
11475 static const struct dis386 rm_table[][8] = {
11478 { "xabort", { Skip_MODRM, Ib } },
11482 { "xbeginT", { Skip_MODRM, Jv } },
11485 /* RM_0F01_REG_0 */
11487 { "vmcall", { Skip_MODRM } },
11488 { "vmlaunch", { Skip_MODRM } },
11489 { "vmresume", { Skip_MODRM } },
11490 { "vmxoff", { Skip_MODRM } },
11493 /* RM_0F01_REG_1 */
11494 { "monitor", { { OP_Monitor, 0 } } },
11495 { "mwait", { { OP_Mwait, 0 } } },
11496 { "clac", { Skip_MODRM } },
11497 { "stac", { Skip_MODRM } },
11500 /* RM_0F01_REG_2 */
11501 { "xgetbv", { Skip_MODRM } },
11502 { "xsetbv", { Skip_MODRM } },
11505 { "vmfunc", { Skip_MODRM } },
11506 { "xend", { Skip_MODRM } },
11507 { "xtest", { Skip_MODRM } },
11511 /* RM_0F01_REG_3 */
11512 { "vmrun", { Skip_MODRM } },
11513 { "vmmcall", { Skip_MODRM } },
11514 { "vmload", { Skip_MODRM } },
11515 { "vmsave", { Skip_MODRM } },
11516 { "stgi", { Skip_MODRM } },
11517 { "clgi", { Skip_MODRM } },
11518 { "skinit", { Skip_MODRM } },
11519 { "invlpga", { Skip_MODRM } },
11522 /* RM_0F01_REG_7 */
11523 { "swapgs", { Skip_MODRM } },
11524 { "rdtscp", { Skip_MODRM } },
11527 /* RM_0FAE_REG_5 */
11528 { "lfence", { Skip_MODRM } },
11531 /* RM_0FAE_REG_6 */
11532 { "mfence", { Skip_MODRM } },
11535 /* RM_0FAE_REG_7 */
11536 { "sfence", { Skip_MODRM } },
11540 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11542 /* We use the high bit to indicate different name for the same
11544 #define ADDR16_PREFIX (0x67 | 0x100)
11545 #define ADDR32_PREFIX (0x67 | 0x200)
11546 #define DATA16_PREFIX (0x66 | 0x100)
11547 #define DATA32_PREFIX (0x66 | 0x200)
11548 #define REP_PREFIX (0xf3 | 0x100)
11549 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11550 #define XRELEASE_PREFIX (0xf3 | 0x400)
11551 #define BND_PREFIX (0xf2 | 0x400)
11556 int newrex, i, length;
11562 last_lock_prefix = -1;
11563 last_repz_prefix = -1;
11564 last_repnz_prefix = -1;
11565 last_data_prefix = -1;
11566 last_addr_prefix = -1;
11567 last_rex_prefix = -1;
11568 last_seg_prefix = -1;
11569 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11570 all_prefixes[i] = 0;
11573 /* The maximum instruction length is 15bytes. */
11574 while (length < MAX_CODE_LENGTH - 1)
11576 FETCH_DATA (the_info, codep + 1);
11580 /* REX prefixes family. */
11597 if (address_mode == mode_64bit)
11601 last_rex_prefix = i;
11604 prefixes |= PREFIX_REPZ;
11605 last_repz_prefix = i;
11608 prefixes |= PREFIX_REPNZ;
11609 last_repnz_prefix = i;
11612 prefixes |= PREFIX_LOCK;
11613 last_lock_prefix = i;
11616 prefixes |= PREFIX_CS;
11617 last_seg_prefix = i;
11620 prefixes |= PREFIX_SS;
11621 last_seg_prefix = i;
11624 prefixes |= PREFIX_DS;
11625 last_seg_prefix = i;
11628 prefixes |= PREFIX_ES;
11629 last_seg_prefix = i;
11632 prefixes |= PREFIX_FS;
11633 last_seg_prefix = i;
11636 prefixes |= PREFIX_GS;
11637 last_seg_prefix = i;
11640 prefixes |= PREFIX_DATA;
11641 last_data_prefix = i;
11644 prefixes |= PREFIX_ADDR;
11645 last_addr_prefix = i;
11648 /* fwait is really an instruction. If there are prefixes
11649 before the fwait, they belong to the fwait, *not* to the
11650 following instruction. */
11651 if (prefixes || rex)
11653 prefixes |= PREFIX_FWAIT;
11655 /* This ensures that the previous REX prefixes are noticed
11656 as unused prefixes, as in the return case below. */
11660 prefixes = PREFIX_FWAIT;
11665 /* Rex is ignored when followed by another prefix. */
11671 if (*codep != FWAIT_OPCODE)
11672 all_prefixes[i++] = *codep;
11681 seg_prefix (int pref)
11702 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11705 static const char *
11706 prefix_name (int pref, int sizeflag)
11708 static const char *rexes [16] =
11711 "rex.B", /* 0x41 */
11712 "rex.X", /* 0x42 */
11713 "rex.XB", /* 0x43 */
11714 "rex.R", /* 0x44 */
11715 "rex.RB", /* 0x45 */
11716 "rex.RX", /* 0x46 */
11717 "rex.RXB", /* 0x47 */
11718 "rex.W", /* 0x48 */
11719 "rex.WB", /* 0x49 */
11720 "rex.WX", /* 0x4a */
11721 "rex.WXB", /* 0x4b */
11722 "rex.WR", /* 0x4c */
11723 "rex.WRB", /* 0x4d */
11724 "rex.WRX", /* 0x4e */
11725 "rex.WRXB", /* 0x4f */
11730 /* REX prefixes family. */
11747 return rexes [pref - 0x40];
11767 return (sizeflag & DFLAG) ? "data16" : "data32";
11769 if (address_mode == mode_64bit)
11770 return (sizeflag & AFLAG) ? "addr32" : "addr64";
11772 return (sizeflag & AFLAG) ? "addr16" : "addr32";
11775 case ADDR16_PREFIX:
11777 case ADDR32_PREFIX:
11779 case DATA16_PREFIX:
11781 case DATA32_PREFIX:
11785 case XACQUIRE_PREFIX:
11787 case XRELEASE_PREFIX:
11796 static char op_out[MAX_OPERANDS][100];
11797 static int op_ad, op_index[MAX_OPERANDS];
11798 static int two_source_ops;
11799 static bfd_vma op_address[MAX_OPERANDS];
11800 static bfd_vma op_riprel[MAX_OPERANDS];
11801 static bfd_vma start_pc;
11804 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11805 * (see topic "Redundant prefixes" in the "Differences from 8086"
11806 * section of the "Virtual 8086 Mode" chapter.)
11807 * 'pc' should be the address of this instruction, it will
11808 * be used to print the target address if this is a relative jump or call
11809 * The function returns the length of this instruction in bytes.
11812 static char intel_syntax;
11813 static char intel_mnemonic = !SYSV386_COMPAT;
11814 static char open_char;
11815 static char close_char;
11816 static char separator_char;
11817 static char scale_char;
11819 /* Here for backwards compatibility. When gdb stops using
11820 print_insn_i386_att and print_insn_i386_intel these functions can
11821 disappear, and print_insn_i386 be merged into print_insn. */
11823 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11827 return print_insn (pc, info);
11831 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11835 return print_insn (pc, info);
11839 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11843 return print_insn (pc, info);
11847 print_i386_disassembler_options (FILE *stream)
11849 fprintf (stream, _("\n\
11850 The following i386/x86-64 specific disassembler options are supported for use\n\
11851 with the -M switch (multiple options should be separated by commas):\n"));
11853 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
11854 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
11855 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
11856 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
11857 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
11858 fprintf (stream, _(" att-mnemonic\n"
11859 " Display instruction in AT&T mnemonic\n"));
11860 fprintf (stream, _(" intel-mnemonic\n"
11861 " Display instruction in Intel mnemonic\n"));
11862 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
11863 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
11864 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
11865 fprintf (stream, _(" data32 Assume 32bit data size\n"));
11866 fprintf (stream, _(" data16 Assume 16bit data size\n"));
11867 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11871 static const struct dis386 bad_opcode = { "(bad)", { XX } };
11873 /* Get a pointer to struct dis386 with a valid name. */
11875 static const struct dis386 *
11876 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11878 int vindex, vex_table_index;
11880 if (dp->name != NULL)
11883 switch (dp->op[0].bytemode)
11885 case USE_REG_TABLE:
11886 dp = ®_table[dp->op[1].bytemode][modrm.reg];
11889 case USE_MOD_TABLE:
11890 vindex = modrm.mod == 0x3 ? 1 : 0;
11891 dp = &mod_table[dp->op[1].bytemode][vindex];
11895 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11898 case USE_PREFIX_TABLE:
11901 /* The prefix in VEX is implicit. */
11902 switch (vex.prefix)
11907 case REPE_PREFIX_OPCODE:
11910 case DATA_PREFIX_OPCODE:
11913 case REPNE_PREFIX_OPCODE:
11924 used_prefixes |= (prefixes & PREFIX_REPZ);
11925 if (prefixes & PREFIX_REPZ)
11928 all_prefixes[last_repz_prefix] = 0;
11932 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11934 used_prefixes |= (prefixes & PREFIX_REPNZ);
11935 if (prefixes & PREFIX_REPNZ)
11938 all_prefixes[last_repnz_prefix] = 0;
11942 used_prefixes |= (prefixes & PREFIX_DATA);
11943 if (prefixes & PREFIX_DATA)
11946 all_prefixes[last_data_prefix] = 0;
11951 dp = &prefix_table[dp->op[1].bytemode][vindex];
11954 case USE_X86_64_TABLE:
11955 vindex = address_mode == mode_64bit ? 1 : 0;
11956 dp = &x86_64_table[dp->op[1].bytemode][vindex];
11959 case USE_3BYTE_TABLE:
11960 FETCH_DATA (info, codep + 2);
11962 dp = &three_byte_table[dp->op[1].bytemode][vindex];
11963 modrm.mod = (*codep >> 6) & 3;
11964 modrm.reg = (*codep >> 3) & 7;
11965 modrm.rm = *codep & 7;
11968 case USE_VEX_LEN_TABLE:
11972 switch (vex.length)
11985 dp = &vex_len_table[dp->op[1].bytemode][vindex];
11988 case USE_XOP_8F_TABLE:
11989 FETCH_DATA (info, codep + 3);
11990 /* All bits in the REX prefix are ignored. */
11992 rex = ~(*codep >> 5) & 0x7;
11994 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11995 switch ((*codep & 0x1f))
12001 vex_table_index = XOP_08;
12004 vex_table_index = XOP_09;
12007 vex_table_index = XOP_0A;
12011 vex.w = *codep & 0x80;
12012 if (vex.w && address_mode == mode_64bit)
12015 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12016 if (address_mode != mode_64bit
12017 && vex.register_specifier > 0x7)
12023 vex.length = (*codep & 0x4) ? 256 : 128;
12024 switch ((*codep & 0x3))
12030 vex.prefix = DATA_PREFIX_OPCODE;
12033 vex.prefix = REPE_PREFIX_OPCODE;
12036 vex.prefix = REPNE_PREFIX_OPCODE;
12043 dp = &xop_table[vex_table_index][vindex];
12045 FETCH_DATA (info, codep + 1);
12046 modrm.mod = (*codep >> 6) & 3;
12047 modrm.reg = (*codep >> 3) & 7;
12048 modrm.rm = *codep & 7;
12051 case USE_VEX_C4_TABLE:
12053 FETCH_DATA (info, codep + 3);
12054 /* All bits in the REX prefix are ignored. */
12056 rex = ~(*codep >> 5) & 0x7;
12057 switch ((*codep & 0x1f))
12063 vex_table_index = VEX_0F;
12066 vex_table_index = VEX_0F38;
12069 vex_table_index = VEX_0F3A;
12073 vex.w = *codep & 0x80;
12074 if (vex.w && address_mode == mode_64bit)
12077 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12078 if (address_mode != mode_64bit
12079 && vex.register_specifier > 0x7)
12085 vex.length = (*codep & 0x4) ? 256 : 128;
12086 switch ((*codep & 0x3))
12092 vex.prefix = DATA_PREFIX_OPCODE;
12095 vex.prefix = REPE_PREFIX_OPCODE;
12098 vex.prefix = REPNE_PREFIX_OPCODE;
12105 dp = &vex_table[vex_table_index][vindex];
12106 /* There is no MODRM byte for VEX [82|77]. */
12107 if (vindex != 0x77 && vindex != 0x82)
12109 FETCH_DATA (info, codep + 1);
12110 modrm.mod = (*codep >> 6) & 3;
12111 modrm.reg = (*codep >> 3) & 7;
12112 modrm.rm = *codep & 7;
12116 case USE_VEX_C5_TABLE:
12118 FETCH_DATA (info, codep + 2);
12119 /* All bits in the REX prefix are ignored. */
12121 rex = (*codep & 0x80) ? 0 : REX_R;
12123 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12124 if (address_mode != mode_64bit
12125 && vex.register_specifier > 0x7)
12133 vex.length = (*codep & 0x4) ? 256 : 128;
12134 switch ((*codep & 0x3))
12140 vex.prefix = DATA_PREFIX_OPCODE;
12143 vex.prefix = REPE_PREFIX_OPCODE;
12146 vex.prefix = REPNE_PREFIX_OPCODE;
12153 dp = &vex_table[dp->op[1].bytemode][vindex];
12154 /* There is no MODRM byte for VEX [82|77]. */
12155 if (vindex != 0x77 && vindex != 0x82)
12157 FETCH_DATA (info, codep + 1);
12158 modrm.mod = (*codep >> 6) & 3;
12159 modrm.reg = (*codep >> 3) & 7;
12160 modrm.rm = *codep & 7;
12164 case USE_VEX_W_TABLE:
12168 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12171 case USE_EVEX_TABLE:
12172 two_source_ops = 0;
12175 FETCH_DATA (info, codep + 4);
12176 /* All bits in the REX prefix are ignored. */
12178 /* The first byte after 0x62. */
12179 rex = ~(*codep >> 5) & 0x7;
12180 vex.r = *codep & 0x10;
12181 switch ((*codep & 0xf))
12184 return &bad_opcode;
12186 vex_table_index = EVEX_0F;
12189 vex_table_index = EVEX_0F38;
12192 vex_table_index = EVEX_0F3A;
12196 /* The second byte after 0x62. */
12198 vex.w = *codep & 0x80;
12199 if (vex.w && address_mode == mode_64bit)
12202 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12203 if (address_mode != mode_64bit)
12205 /* In 16/32-bit mode silently ignore following bits. */
12209 vex.register_specifier &= 0x7;
12213 if (!(*codep & 0x4))
12214 return &bad_opcode;
12216 switch ((*codep & 0x3))
12222 vex.prefix = DATA_PREFIX_OPCODE;
12225 vex.prefix = REPE_PREFIX_OPCODE;
12228 vex.prefix = REPNE_PREFIX_OPCODE;
12232 /* The third byte after 0x62. */
12235 /* Remember the static rounding bits. */
12236 vex.ll = (*codep >> 5) & 3;
12237 vex.b = (*codep & 0x10) != 0;
12239 vex.v = *codep & 0x8;
12240 vex.mask_register_specifier = *codep & 0x7;
12241 vex.zeroing = *codep & 0x80;
12247 dp = &evex_table[vex_table_index][vindex];
12248 FETCH_DATA (info, codep + 1);
12249 modrm.mod = (*codep >> 6) & 3;
12250 modrm.reg = (*codep >> 3) & 7;
12251 modrm.rm = *codep & 7;
12253 /* Set vector length. */
12254 if (modrm.mod == 3 && vex.b)
12270 return &bad_opcode;
12283 if (dp->name != NULL)
12286 return get_valid_dis386 (dp, info);
12290 get_sib (disassemble_info *info, int sizeflag)
12292 /* If modrm.mod == 3, operand must be register. */
12294 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12298 FETCH_DATA (info, codep + 2);
12299 sib.index = (codep [1] >> 3) & 7;
12300 sib.scale = (codep [1] >> 6) & 3;
12301 sib.base = codep [1] & 7;
12306 print_insn (bfd_vma pc, disassemble_info *info)
12308 const struct dis386 *dp;
12310 char *op_txt[MAX_OPERANDS];
12314 struct dis_private priv;
12316 int default_prefixes;
12318 priv.orig_sizeflag = AFLAG | DFLAG;
12319 if ((info->mach & bfd_mach_i386_i386) != 0)
12320 address_mode = mode_32bit;
12321 else if (info->mach == bfd_mach_i386_i8086)
12323 address_mode = mode_16bit;
12324 priv.orig_sizeflag = 0;
12327 address_mode = mode_64bit;
12329 if (intel_syntax == (char) -1)
12330 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12332 for (p = info->disassembler_options; p != NULL; )
12334 if (CONST_STRNEQ (p, "x86-64"))
12336 address_mode = mode_64bit;
12337 priv.orig_sizeflag = AFLAG | DFLAG;
12339 else if (CONST_STRNEQ (p, "i386"))
12341 address_mode = mode_32bit;
12342 priv.orig_sizeflag = AFLAG | DFLAG;
12344 else if (CONST_STRNEQ (p, "i8086"))
12346 address_mode = mode_16bit;
12347 priv.orig_sizeflag = 0;
12349 else if (CONST_STRNEQ (p, "intel"))
12352 if (CONST_STRNEQ (p + 5, "-mnemonic"))
12353 intel_mnemonic = 1;
12355 else if (CONST_STRNEQ (p, "att"))
12358 if (CONST_STRNEQ (p + 3, "-mnemonic"))
12359 intel_mnemonic = 0;
12361 else if (CONST_STRNEQ (p, "addr"))
12363 if (address_mode == mode_64bit)
12365 if (p[4] == '3' && p[5] == '2')
12366 priv.orig_sizeflag &= ~AFLAG;
12367 else if (p[4] == '6' && p[5] == '4')
12368 priv.orig_sizeflag |= AFLAG;
12372 if (p[4] == '1' && p[5] == '6')
12373 priv.orig_sizeflag &= ~AFLAG;
12374 else if (p[4] == '3' && p[5] == '2')
12375 priv.orig_sizeflag |= AFLAG;
12378 else if (CONST_STRNEQ (p, "data"))
12380 if (p[4] == '1' && p[5] == '6')
12381 priv.orig_sizeflag &= ~DFLAG;
12382 else if (p[4] == '3' && p[5] == '2')
12383 priv.orig_sizeflag |= DFLAG;
12385 else if (CONST_STRNEQ (p, "suffix"))
12386 priv.orig_sizeflag |= SUFFIX_ALWAYS;
12388 p = strchr (p, ',');
12395 names64 = intel_names64;
12396 names32 = intel_names32;
12397 names16 = intel_names16;
12398 names8 = intel_names8;
12399 names8rex = intel_names8rex;
12400 names_seg = intel_names_seg;
12401 names_mm = intel_names_mm;
12402 names_bnd = intel_names_bnd;
12403 names_xmm = intel_names_xmm;
12404 names_ymm = intel_names_ymm;
12405 names_zmm = intel_names_zmm;
12406 index64 = intel_index64;
12407 index32 = intel_index32;
12408 names_mask = intel_names_mask;
12409 index16 = intel_index16;
12412 separator_char = '+';
12417 names64 = att_names64;
12418 names32 = att_names32;
12419 names16 = att_names16;
12420 names8 = att_names8;
12421 names8rex = att_names8rex;
12422 names_seg = att_names_seg;
12423 names_mm = att_names_mm;
12424 names_bnd = att_names_bnd;
12425 names_xmm = att_names_xmm;
12426 names_ymm = att_names_ymm;
12427 names_zmm = att_names_zmm;
12428 index64 = att_index64;
12429 index32 = att_index32;
12430 names_mask = att_names_mask;
12431 index16 = att_index16;
12434 separator_char = ',';
12438 /* The output looks better if we put 7 bytes on a line, since that
12439 puts most long word instructions on a single line. Use 8 bytes
12441 if ((info->mach & bfd_mach_l1om) != 0)
12442 info->bytes_per_line = 8;
12444 info->bytes_per_line = 7;
12446 info->private_data = &priv;
12447 priv.max_fetched = priv.the_buffer;
12448 priv.insn_start = pc;
12451 for (i = 0; i < MAX_OPERANDS; ++i)
12459 start_codep = priv.the_buffer;
12460 codep = priv.the_buffer;
12462 if (setjmp (priv.bailout) != 0)
12466 /* Getting here means we tried for data but didn't get it. That
12467 means we have an incomplete instruction of some sort. Just
12468 print the first byte as a prefix or a .byte pseudo-op. */
12469 if (codep > priv.the_buffer)
12471 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12473 (*info->fprintf_func) (info->stream, "%s", name);
12476 /* Just print the first byte as a .byte instruction. */
12477 (*info->fprintf_func) (info->stream, ".byte 0x%x",
12478 (unsigned int) priv.the_buffer[0]);
12488 sizeflag = priv.orig_sizeflag;
12490 if (!ckprefix () || rex_used)
12492 /* Too many prefixes or unused REX prefixes. */
12494 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12496 (*info->fprintf_func) (info->stream, "%s%s",
12498 prefix_name (all_prefixes[i], sizeflag));
12502 insn_codep = codep;
12504 FETCH_DATA (info, codep + 1);
12505 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12507 if (((prefixes & PREFIX_FWAIT)
12508 && ((*codep < 0xd8) || (*codep > 0xdf))))
12510 (*info->fprintf_func) (info->stream, "fwait");
12514 if (*codep == 0x0f)
12516 unsigned char threebyte;
12517 FETCH_DATA (info, codep + 2);
12518 threebyte = *++codep;
12519 dp = &dis386_twobyte[threebyte];
12520 need_modrm = twobyte_has_modrm[*codep];
12525 dp = &dis386[*codep];
12526 need_modrm = onebyte_has_modrm[*codep];
12530 if ((prefixes & PREFIX_REPZ))
12531 used_prefixes |= PREFIX_REPZ;
12532 if ((prefixes & PREFIX_REPNZ))
12533 used_prefixes |= PREFIX_REPNZ;
12534 if ((prefixes & PREFIX_LOCK))
12535 used_prefixes |= PREFIX_LOCK;
12537 default_prefixes = 0;
12538 if (prefixes & PREFIX_ADDR)
12541 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
12543 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12544 all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
12546 all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
12547 default_prefixes |= PREFIX_ADDR;
12551 if ((prefixes & PREFIX_DATA))
12554 if (dp->op[2].bytemode == cond_jump_mode
12555 && dp->op[0].bytemode == v_mode
12558 if (sizeflag & DFLAG)
12559 all_prefixes[last_data_prefix] = DATA32_PREFIX;
12561 all_prefixes[last_data_prefix] = DATA16_PREFIX;
12562 default_prefixes |= PREFIX_DATA;
12564 else if (rex & REX_W)
12566 /* REX_W will override PREFIX_DATA. */
12567 default_prefixes |= PREFIX_DATA;
12573 FETCH_DATA (info, codep + 1);
12574 modrm.mod = (*codep >> 6) & 3;
12575 modrm.reg = (*codep >> 3) & 7;
12576 modrm.rm = *codep & 7;
12584 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12586 get_sib (info, sizeflag);
12587 dofloat (sizeflag);
12591 dp = get_valid_dis386 (dp, info);
12592 if (dp != NULL && putop (dp->name, sizeflag) == 0)
12594 get_sib (info, sizeflag);
12595 for (i = 0; i < MAX_OPERANDS; ++i)
12598 op_ad = MAX_OPERANDS - 1 - i;
12600 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12601 /* For EVEX instruction after the last operand masking
12602 should be printed. */
12603 if (i == 0 && vex.evex)
12605 /* Don't print {%k0}. */
12606 if (vex.mask_register_specifier)
12609 oappend (names_mask[vex.mask_register_specifier]);
12619 /* See if any prefixes were not used. If so, print the first one
12620 separately. If we don't do this, we'll wind up printing an
12621 instruction stream which does not precisely correspond to the
12622 bytes we are disassembling. */
12623 if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
12625 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12626 if (all_prefixes[i])
12629 name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
12631 name = INTERNAL_DISASSEMBLER_ERROR;
12632 (*info->fprintf_func) (info->stream, "%s", name);
12637 /* Check if the REX prefix is used. */
12638 if (rex_ignored == 0 && (rex ^ rex_used) == 0)
12639 all_prefixes[last_rex_prefix] = 0;
12641 /* Check if the SEG prefix is used. */
12642 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12643 | PREFIX_FS | PREFIX_GS)) != 0
12645 & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
12646 all_prefixes[last_seg_prefix] = 0;
12648 /* Check if the ADDR prefix is used. */
12649 if ((prefixes & PREFIX_ADDR) != 0
12650 && (used_prefixes & PREFIX_ADDR) != 0)
12651 all_prefixes[last_addr_prefix] = 0;
12653 /* Check if the DATA prefix is used. */
12654 if ((prefixes & PREFIX_DATA) != 0
12655 && (used_prefixes & PREFIX_DATA) != 0)
12656 all_prefixes[last_data_prefix] = 0;
12659 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12660 if (all_prefixes[i])
12663 name = prefix_name (all_prefixes[i], sizeflag);
12666 prefix_length += strlen (name) + 1;
12667 (*info->fprintf_func) (info->stream, "%s ", name);
12670 /* Check maximum code length. */
12671 if ((codep - start_codep) > MAX_CODE_LENGTH)
12673 (*info->fprintf_func) (info->stream, "(bad)");
12674 return MAX_CODE_LENGTH;
12677 obufp = mnemonicendp;
12678 for (i = strlen (obuf) + prefix_length; i < 6; i++)
12681 (*info->fprintf_func) (info->stream, "%s", obuf);
12683 /* The enter and bound instructions are printed with operands in the same
12684 order as the intel book; everything else is printed in reverse order. */
12685 if (intel_syntax || two_source_ops)
12689 for (i = 0; i < MAX_OPERANDS; ++i)
12690 op_txt[i] = op_out[i];
12692 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12694 op_ad = op_index[i];
12695 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12696 op_index[MAX_OPERANDS - 1 - i] = op_ad;
12697 riprel = op_riprel[i];
12698 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12699 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12704 for (i = 0; i < MAX_OPERANDS; ++i)
12705 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12709 for (i = 0; i < MAX_OPERANDS; ++i)
12713 (*info->fprintf_func) (info->stream, ",");
12714 if (op_index[i] != -1 && !op_riprel[i])
12715 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12717 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12721 for (i = 0; i < MAX_OPERANDS; i++)
12722 if (op_index[i] != -1 && op_riprel[i])
12724 (*info->fprintf_func) (info->stream, " # ");
12725 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
12726 + op_address[op_index[i]]), info);
12729 return codep - priv.the_buffer;
12732 static const char *float_mem[] = {
12807 static const unsigned char float_mem_mode[] = {
12882 #define ST { OP_ST, 0 }
12883 #define STi { OP_STi, 0 }
12885 #define FGRPd9_2 NULL, { { NULL, 0 } }
12886 #define FGRPd9_4 NULL, { { NULL, 1 } }
12887 #define FGRPd9_5 NULL, { { NULL, 2 } }
12888 #define FGRPd9_6 NULL, { { NULL, 3 } }
12889 #define FGRPd9_7 NULL, { { NULL, 4 } }
12890 #define FGRPda_5 NULL, { { NULL, 5 } }
12891 #define FGRPdb_4 NULL, { { NULL, 6 } }
12892 #define FGRPde_3 NULL, { { NULL, 7 } }
12893 #define FGRPdf_4 NULL, { { NULL, 8 } }
12895 static const struct dis386 float_reg[][8] = {
12898 { "fadd", { ST, STi } },
12899 { "fmul", { ST, STi } },
12900 { "fcom", { STi } },
12901 { "fcomp", { STi } },
12902 { "fsub", { ST, STi } },
12903 { "fsubr", { ST, STi } },
12904 { "fdiv", { ST, STi } },
12905 { "fdivr", { ST, STi } },
12909 { "fld", { STi } },
12910 { "fxch", { STi } },
12920 { "fcmovb", { ST, STi } },
12921 { "fcmove", { ST, STi } },
12922 { "fcmovbe",{ ST, STi } },
12923 { "fcmovu", { ST, STi } },
12931 { "fcmovnb",{ ST, STi } },
12932 { "fcmovne",{ ST, STi } },
12933 { "fcmovnbe",{ ST, STi } },
12934 { "fcmovnu",{ ST, STi } },
12936 { "fucomi", { ST, STi } },
12937 { "fcomi", { ST, STi } },
12942 { "fadd", { STi, ST } },
12943 { "fmul", { STi, ST } },
12946 { "fsub!M", { STi, ST } },
12947 { "fsubM", { STi, ST } },
12948 { "fdiv!M", { STi, ST } },
12949 { "fdivM", { STi, ST } },
12953 { "ffree", { STi } },
12955 { "fst", { STi } },
12956 { "fstp", { STi } },
12957 { "fucom", { STi } },
12958 { "fucomp", { STi } },
12964 { "faddp", { STi, ST } },
12965 { "fmulp", { STi, ST } },
12968 { "fsub!Mp", { STi, ST } },
12969 { "fsubMp", { STi, ST } },
12970 { "fdiv!Mp", { STi, ST } },
12971 { "fdivMp", { STi, ST } },
12975 { "ffreep", { STi } },
12980 { "fucomip", { ST, STi } },
12981 { "fcomip", { ST, STi } },
12986 static char *fgrps[][8] = {
12989 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12994 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12999 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13004 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13009 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13014 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13019 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13020 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13025 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13030 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13035 swap_operand (void)
13037 mnemonicendp[0] = '.';
13038 mnemonicendp[1] = 's';
13043 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13044 int sizeflag ATTRIBUTE_UNUSED)
13046 /* Skip mod/rm byte. */
13052 dofloat (int sizeflag)
13054 const struct dis386 *dp;
13055 unsigned char floatop;
13057 floatop = codep[-1];
13059 if (modrm.mod != 3)
13061 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13063 putop (float_mem[fp_indx], sizeflag);
13066 OP_E (float_mem_mode[fp_indx], sizeflag);
13069 /* Skip mod/rm byte. */
13073 dp = &float_reg[floatop - 0xd8][modrm.reg];
13074 if (dp->name == NULL)
13076 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13078 /* Instruction fnstsw is only one with strange arg. */
13079 if (floatop == 0xdf && codep[-1] == 0xe0)
13080 strcpy (op_out[0], names16[0]);
13084 putop (dp->name, sizeflag);
13089 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13094 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13099 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13101 oappend ("%st" + intel_syntax);
13105 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13107 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13108 oappend (scratchbuf + intel_syntax);
13111 /* Capital letters in template are macros. */
13113 putop (const char *in_template, int sizeflag)
13118 unsigned int l = 0, len = 1;
13121 #define SAVE_LAST(c) \
13122 if (l < len && l < sizeof (last)) \
13127 for (p = in_template; *p; p++)
13144 while (*++p != '|')
13145 if (*p == '}' || *p == '\0')
13148 /* Fall through. */
13153 while (*++p != '}')
13164 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13168 if (l == 0 && len == 1)
13173 if (sizeflag & SUFFIX_ALWAYS)
13186 if (address_mode == mode_64bit
13187 && !(prefixes & PREFIX_ADDR))
13198 if (intel_syntax && !alt)
13200 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13202 if (sizeflag & DFLAG)
13203 *obufp++ = intel_syntax ? 'd' : 'l';
13205 *obufp++ = intel_syntax ? 'w' : 's';
13206 used_prefixes |= (prefixes & PREFIX_DATA);
13210 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13213 if (modrm.mod == 3)
13219 if (sizeflag & DFLAG)
13220 *obufp++ = intel_syntax ? 'd' : 'l';
13223 used_prefixes |= (prefixes & PREFIX_DATA);
13229 case 'E': /* For jcxz/jecxz */
13230 if (address_mode == mode_64bit)
13232 if (sizeflag & AFLAG)
13238 if (sizeflag & AFLAG)
13240 used_prefixes |= (prefixes & PREFIX_ADDR);
13245 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13247 if (sizeflag & AFLAG)
13248 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13250 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13251 used_prefixes |= (prefixes & PREFIX_ADDR);
13255 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13257 if ((rex & REX_W) || (sizeflag & DFLAG))
13261 if (!(rex & REX_W))
13262 used_prefixes |= (prefixes & PREFIX_DATA);
13267 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13268 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13270 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13273 if (prefixes & PREFIX_DS)
13294 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13299 /* Fall through. */
13302 if (l != 0 || len != 1)
13310 if (sizeflag & SUFFIX_ALWAYS)
13314 if (intel_mnemonic != cond)
13318 if ((prefixes & PREFIX_FWAIT) == 0)
13321 used_prefixes |= PREFIX_FWAIT;
13327 else if (intel_syntax && (sizeflag & DFLAG))
13331 if (!(rex & REX_W))
13332 used_prefixes |= (prefixes & PREFIX_DATA);
13336 && address_mode == mode_64bit
13337 && ((sizeflag & DFLAG) || (rex & REX_W)))
13342 /* Fall through. */
13346 if ((rex & REX_W) == 0
13347 && (prefixes & PREFIX_DATA))
13349 if ((sizeflag & DFLAG) == 0)
13351 used_prefixes |= (prefixes & PREFIX_DATA);
13355 if ((prefixes & PREFIX_DATA)
13357 || (sizeflag & SUFFIX_ALWAYS))
13364 if (sizeflag & DFLAG)
13368 used_prefixes |= (prefixes & PREFIX_DATA);
13375 if (address_mode == mode_64bit
13376 && ((sizeflag & DFLAG) || (rex & REX_W)))
13378 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13382 /* Fall through. */
13385 if (l == 0 && len == 1)
13388 if (intel_syntax && !alt)
13391 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13397 if (sizeflag & DFLAG)
13398 *obufp++ = intel_syntax ? 'd' : 'l';
13401 used_prefixes |= (prefixes & PREFIX_DATA);
13407 if (l != 1 || len != 2 || last[0] != 'L')
13413 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13428 else if (sizeflag & DFLAG)
13437 if (intel_syntax && !p[1]
13438 && ((rex & REX_W) || (sizeflag & DFLAG)))
13440 if (!(rex & REX_W))
13441 used_prefixes |= (prefixes & PREFIX_DATA);
13444 if (l == 0 && len == 1)
13448 if (address_mode == mode_64bit
13449 && ((sizeflag & DFLAG) || (rex & REX_W)))
13451 if (sizeflag & SUFFIX_ALWAYS)
13473 /* Fall through. */
13476 if (l == 0 && len == 1)
13481 if (sizeflag & SUFFIX_ALWAYS)
13487 if (sizeflag & DFLAG)
13491 used_prefixes |= (prefixes & PREFIX_DATA);
13505 if (address_mode == mode_64bit
13506 && !(prefixes & PREFIX_ADDR))
13517 if (l != 0 || len != 1)
13522 if (need_vex && vex.prefix)
13524 if (vex.prefix == DATA_PREFIX_OPCODE)
13531 if (prefixes & PREFIX_DATA)
13535 used_prefixes |= (prefixes & PREFIX_DATA);
13539 if (l == 0 && len == 1)
13541 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13552 if (l != 1 || len != 2 || last[0] != 'X')
13560 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13562 switch (vex.length)
13576 if (l == 0 && len == 1)
13578 /* operand size flag for cwtl, cbtw */
13587 else if (sizeflag & DFLAG)
13591 if (!(rex & REX_W))
13592 used_prefixes |= (prefixes & PREFIX_DATA);
13599 && last[0] != 'L'))
13606 if (last[0] == 'X')
13607 *obufp++ = vex.w ? 'd': 's';
13609 *obufp++ = vex.w ? 'q': 'd';
13616 mnemonicendp = obufp;
13621 oappend (const char *s)
13623 obufp = stpcpy (obufp, s);
13629 if (prefixes & PREFIX_CS)
13631 used_prefixes |= PREFIX_CS;
13632 oappend ("%cs:" + intel_syntax);
13634 if (prefixes & PREFIX_DS)
13636 used_prefixes |= PREFIX_DS;
13637 oappend ("%ds:" + intel_syntax);
13639 if (prefixes & PREFIX_SS)
13641 used_prefixes |= PREFIX_SS;
13642 oappend ("%ss:" + intel_syntax);
13644 if (prefixes & PREFIX_ES)
13646 used_prefixes |= PREFIX_ES;
13647 oappend ("%es:" + intel_syntax);
13649 if (prefixes & PREFIX_FS)
13651 used_prefixes |= PREFIX_FS;
13652 oappend ("%fs:" + intel_syntax);
13654 if (prefixes & PREFIX_GS)
13656 used_prefixes |= PREFIX_GS;
13657 oappend ("%gs:" + intel_syntax);
13662 OP_indirE (int bytemode, int sizeflag)
13666 OP_E (bytemode, sizeflag);
13670 print_operand_value (char *buf, int hex, bfd_vma disp)
13672 if (address_mode == mode_64bit)
13680 sprintf_vma (tmp, disp);
13681 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13682 strcpy (buf + 2, tmp + i);
13686 bfd_signed_vma v = disp;
13693 /* Check for possible overflow on 0x8000000000000000. */
13696 strcpy (buf, "9223372036854775808");
13710 tmp[28 - i] = (v % 10) + '0';
13714 strcpy (buf, tmp + 29 - i);
13720 sprintf (buf, "0x%x", (unsigned int) disp);
13722 sprintf (buf, "%d", (int) disp);
13726 /* Put DISP in BUF as signed hex number. */
13729 print_displacement (char *buf, bfd_vma disp)
13731 bfd_signed_vma val = disp;
13740 /* Check for possible overflow. */
13743 switch (address_mode)
13746 strcpy (buf + j, "0x8000000000000000");
13749 strcpy (buf + j, "0x80000000");
13752 strcpy (buf + j, "0x8000");
13762 sprintf_vma (tmp, (bfd_vma) val);
13763 for (i = 0; tmp[i] == '0'; i++)
13765 if (tmp[i] == '\0')
13767 strcpy (buf + j, tmp + i);
13771 intel_operand_size (int bytemode, int sizeflag)
13775 && (bytemode == x_mode
13776 || bytemode == evex_half_bcst_xmmq_mode))
13779 oappend ("QWORD PTR ");
13781 oappend ("DWORD PTR ");
13789 oappend ("BYTE PTR ");
13793 oappend ("WORD PTR ");
13796 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13798 oappend ("QWORD PTR ");
13808 oappend ("QWORD PTR ");
13811 if ((sizeflag & DFLAG) || bytemode == dq_mode)
13812 oappend ("DWORD PTR ");
13814 oappend ("WORD PTR ");
13815 used_prefixes |= (prefixes & PREFIX_DATA);
13819 if ((rex & REX_W) || (sizeflag & DFLAG))
13821 oappend ("WORD PTR ");
13822 if (!(rex & REX_W))
13823 used_prefixes |= (prefixes & PREFIX_DATA);
13826 if (sizeflag & DFLAG)
13827 oappend ("QWORD PTR ");
13829 oappend ("DWORD PTR ");
13830 used_prefixes |= (prefixes & PREFIX_DATA);
13833 case d_scalar_mode:
13834 case d_scalar_swap_mode:
13837 oappend ("DWORD PTR ");
13840 case q_scalar_mode:
13841 case q_scalar_swap_mode:
13843 oappend ("QWORD PTR ");
13846 if (address_mode == mode_64bit)
13847 oappend ("QWORD PTR ");
13849 oappend ("DWORD PTR ");
13852 if (sizeflag & DFLAG)
13853 oappend ("FWORD PTR ");
13855 oappend ("DWORD PTR ");
13856 used_prefixes |= (prefixes & PREFIX_DATA);
13859 oappend ("TBYTE PTR ");
13863 case evex_x_gscat_mode:
13864 case evex_x_nobcst_mode:
13867 switch (vex.length)
13870 oappend ("XMMWORD PTR ");
13873 oappend ("YMMWORD PTR ");
13876 oappend ("ZMMWORD PTR ");
13883 oappend ("XMMWORD PTR ");
13886 oappend ("XMMWORD PTR ");
13889 oappend ("YMMWORD PTR ");
13892 case evex_half_bcst_xmmq_mode:
13896 switch (vex.length)
13899 oappend ("QWORD PTR ");
13902 oappend ("XMMWORD PTR ");
13905 oappend ("YMMWORD PTR ");
13915 switch (vex.length)
13920 oappend ("BYTE PTR ");
13930 switch (vex.length)
13935 oappend ("WORD PTR ");
13945 switch (vex.length)
13950 oappend ("DWORD PTR ");
13960 switch (vex.length)
13965 oappend ("QWORD PTR ");
13975 switch (vex.length)
13978 oappend ("WORD PTR ");
13981 oappend ("DWORD PTR ");
13984 oappend ("QWORD PTR ");
13994 switch (vex.length)
13997 oappend ("DWORD PTR ");
14000 oappend ("QWORD PTR ");
14003 oappend ("XMMWORD PTR ");
14013 switch (vex.length)
14016 oappend ("QWORD PTR ");
14019 oappend ("YMMWORD PTR ");
14022 oappend ("ZMMWORD PTR ");
14032 switch (vex.length)
14036 oappend ("XMMWORD PTR ");
14043 oappend ("OWORD PTR ");
14046 case vex_w_dq_mode:
14047 case vex_scalar_w_dq_mode:
14052 oappend ("QWORD PTR ");
14054 oappend ("DWORD PTR ");
14056 case vex_vsib_d_w_dq_mode:
14057 case vex_vsib_q_w_dq_mode:
14064 oappend ("QWORD PTR ");
14066 oappend ("DWORD PTR ");
14070 if (vex.length != 512)
14072 oappend ("ZMMWORD PTR ");
14078 /* Currently the only instructions, which allows either mask or
14079 memory operand, are AVX512's KMOVW instructions. They need
14080 Word-sized operand. */
14081 if (vex.w || vex.length != 128)
14083 oappend ("WORD PTR ");
14091 OP_E_register (int bytemode, int sizeflag)
14093 int reg = modrm.rm;
14094 const char **names;
14100 if ((sizeflag & SUFFIX_ALWAYS)
14101 && (bytemode == b_swap_mode || bytemode == v_swap_mode))
14124 names = address_mode == mode_64bit ? names64 : names32;
14130 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14149 if ((sizeflag & DFLAG)
14150 || (bytemode != v_mode
14151 && bytemode != v_swap_mode))
14155 used_prefixes |= (prefixes & PREFIX_DATA);
14159 names = names_mask;
14164 oappend (INTERNAL_DISASSEMBLER_ERROR);
14167 oappend (names[reg]);
14171 OP_E_memory (int bytemode, int sizeflag)
14174 int add = (rex & REX_B) ? 8 : 0;
14180 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
14182 && bytemode != x_mode
14183 && bytemode != evex_half_bcst_xmmq_mode)
14190 case vex_vsib_d_w_dq_mode:
14191 case evex_x_gscat_mode:
14193 shift = vex.w ? 3 : 2;
14195 case vex_vsib_q_w_dq_mode:
14199 case evex_half_bcst_xmmq_mode:
14202 shift = vex.w ? 3 : 2;
14205 /* Fall through if vex.b == 0. */
14210 case evex_x_nobcst_mode:
14212 switch (vex.length)
14235 case q_scalar_mode:
14237 case q_scalar_swap_mode:
14243 case d_scalar_mode:
14245 case d_scalar_swap_mode:
14257 /* Make necessary corrections to shift for modes that need it.
14258 For these modes we currently have shift 4, 5 or 6 depending on
14259 vex.length (it corresponds to xmmword, ymmword or zmmword
14260 operand). We might want to make it 3, 4 or 5 (e.g. for
14261 xmmq_mode). In case of broadcast enabled the corrections
14262 aren't needed, as element size is always 32 or 64 bits. */
14263 if (bytemode == xmmq_mode
14264 || (bytemode == evex_half_bcst_xmmq_mode
14267 else if (bytemode == xmmqd_mode)
14269 else if (bytemode == xmmdw_mode)
14277 intel_operand_size (bytemode, sizeflag);
14280 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14282 /* 32/64 bit address mode */
14291 int addr32flag = !((sizeflag & AFLAG)
14292 || bytemode == v_bnd_mode
14293 || bytemode == bnd_mode);
14294 const char **indexes64 = names64;
14295 const char **indexes32 = names32;
14305 vindex = sib.index;
14311 case vex_vsib_d_w_dq_mode:
14312 case vex_vsib_q_w_dq_mode:
14322 switch (vex.length)
14325 indexes64 = indexes32 = names_xmm;
14328 if (!vex.w || bytemode == vex_vsib_q_w_dq_mode)
14329 indexes64 = indexes32 = names_ymm;
14331 indexes64 = indexes32 = names_xmm;
14334 if (!vex.w || bytemode == vex_vsib_q_w_dq_mode)
14335 indexes64 = indexes32 = names_zmm;
14337 indexes64 = indexes32 = names_ymm;
14344 haveindex = vindex != 4;
14351 rbase = base + add;
14359 if (address_mode == mode_64bit && !havesib)
14365 FETCH_DATA (the_info, codep + 1);
14367 if ((disp & 0x80) != 0)
14369 if (vex.evex && shift > 0)
14377 /* In 32bit mode, we need index register to tell [offset] from
14378 [eiz*1 + offset]. */
14379 needindex = (havesib
14382 && address_mode == mode_32bit);
14383 havedisp = (havebase
14385 || (havesib && (haveindex || scale != 0)));
14388 if (modrm.mod != 0 || base == 5)
14390 if (havedisp || riprel)
14391 print_displacement (scratchbuf, disp);
14393 print_operand_value (scratchbuf, 1, disp);
14394 oappend (scratchbuf);
14398 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
14402 if ((havebase || haveindex || riprel)
14403 && (bytemode != v_bnd_mode)
14404 && (bytemode != bnd_mode))
14405 used_prefixes |= PREFIX_ADDR;
14407 if (havedisp || (intel_syntax && riprel))
14409 *obufp++ = open_char;
14410 if (intel_syntax && riprel)
14413 oappend (sizeflag & AFLAG ? "rip" : "eip");
14417 oappend (address_mode == mode_64bit && !addr32flag
14418 ? names64[rbase] : names32[rbase]);
14421 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14422 print index to tell base + index from base. */
14426 || (havebase && base != ESP_REG_NUM))
14428 if (!intel_syntax || havebase)
14430 *obufp++ = separator_char;
14434 oappend (address_mode == mode_64bit && !addr32flag
14435 ? indexes64[vindex] : indexes32[vindex]);
14437 oappend (address_mode == mode_64bit && !addr32flag
14438 ? index64 : index32);
14440 *obufp++ = scale_char;
14442 sprintf (scratchbuf, "%d", 1 << scale);
14443 oappend (scratchbuf);
14447 && (disp || modrm.mod != 0 || base == 5))
14449 if (!havedisp || (bfd_signed_vma) disp >= 0)
14454 else if (modrm.mod != 1 && disp != -disp)
14458 disp = - (bfd_signed_vma) disp;
14462 print_displacement (scratchbuf, disp);
14464 print_operand_value (scratchbuf, 1, disp);
14465 oappend (scratchbuf);
14468 *obufp++ = close_char;
14471 else if (intel_syntax)
14473 if (modrm.mod != 0 || base == 5)
14475 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
14476 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
14480 oappend (names_seg[ds_reg - es_reg]);
14483 print_operand_value (scratchbuf, 1, disp);
14484 oappend (scratchbuf);
14490 /* 16 bit address mode */
14491 used_prefixes |= prefixes & PREFIX_ADDR;
14498 if ((disp & 0x8000) != 0)
14503 FETCH_DATA (the_info, codep + 1);
14505 if ((disp & 0x80) != 0)
14510 if ((disp & 0x8000) != 0)
14516 if (modrm.mod != 0 || modrm.rm == 6)
14518 print_displacement (scratchbuf, disp);
14519 oappend (scratchbuf);
14522 if (modrm.mod != 0 || modrm.rm != 6)
14524 *obufp++ = open_char;
14526 oappend (index16[modrm.rm]);
14528 && (disp || modrm.mod != 0 || modrm.rm == 6))
14530 if ((bfd_signed_vma) disp >= 0)
14535 else if (modrm.mod != 1)
14539 disp = - (bfd_signed_vma) disp;
14542 print_displacement (scratchbuf, disp);
14543 oappend (scratchbuf);
14546 *obufp++ = close_char;
14549 else if (intel_syntax)
14551 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
14552 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
14556 oappend (names_seg[ds_reg - es_reg]);
14559 print_operand_value (scratchbuf, 1, disp & 0xffff);
14560 oappend (scratchbuf);
14563 if (vex.evex && vex.b
14564 && (bytemode == x_mode
14565 || bytemode == evex_half_bcst_xmmq_mode))
14567 if (vex.w || bytemode == evex_half_bcst_xmmq_mode)
14568 oappend ("{1to8}");
14570 oappend ("{1to16}");
14575 OP_E (int bytemode, int sizeflag)
14577 /* Skip mod/rm byte. */
14581 if (modrm.mod == 3)
14582 OP_E_register (bytemode, sizeflag);
14584 OP_E_memory (bytemode, sizeflag);
14588 OP_G (int bytemode, int sizeflag)
14599 oappend (names8rex[modrm.reg + add]);
14601 oappend (names8[modrm.reg + add]);
14604 oappend (names16[modrm.reg + add]);
14607 oappend (names32[modrm.reg + add]);
14610 oappend (names64[modrm.reg + add]);
14613 oappend (names_bnd[modrm.reg]);
14622 oappend (names64[modrm.reg + add]);
14625 if ((sizeflag & DFLAG) || bytemode != v_mode)
14626 oappend (names32[modrm.reg + add]);
14628 oappend (names16[modrm.reg + add]);
14629 used_prefixes |= (prefixes & PREFIX_DATA);
14633 if (address_mode == mode_64bit)
14634 oappend (names64[modrm.reg + add]);
14636 oappend (names32[modrm.reg + add]);
14639 oappend (names_mask[modrm.reg + add]);
14642 oappend (INTERNAL_DISASSEMBLER_ERROR);
14655 FETCH_DATA (the_info, codep + 8);
14656 a = *codep++ & 0xff;
14657 a |= (*codep++ & 0xff) << 8;
14658 a |= (*codep++ & 0xff) << 16;
14659 a |= (*codep++ & 0xff) << 24;
14660 b = *codep++ & 0xff;
14661 b |= (*codep++ & 0xff) << 8;
14662 b |= (*codep++ & 0xff) << 16;
14663 b |= (*codep++ & 0xff) << 24;
14664 x = a + ((bfd_vma) b << 32);
14672 static bfd_signed_vma
14675 bfd_signed_vma x = 0;
14677 FETCH_DATA (the_info, codep + 4);
14678 x = *codep++ & (bfd_signed_vma) 0xff;
14679 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14680 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14681 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14685 static bfd_signed_vma
14688 bfd_signed_vma x = 0;
14690 FETCH_DATA (the_info, codep + 4);
14691 x = *codep++ & (bfd_signed_vma) 0xff;
14692 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14693 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14694 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14696 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14706 FETCH_DATA (the_info, codep + 2);
14707 x = *codep++ & 0xff;
14708 x |= (*codep++ & 0xff) << 8;
14713 set_op (bfd_vma op, int riprel)
14715 op_index[op_ad] = op_ad;
14716 if (address_mode == mode_64bit)
14718 op_address[op_ad] = op;
14719 op_riprel[op_ad] = riprel;
14723 /* Mask to get a 32-bit address. */
14724 op_address[op_ad] = op & 0xffffffff;
14725 op_riprel[op_ad] = riprel & 0xffffffff;
14730 OP_REG (int code, int sizeflag)
14737 case es_reg: case ss_reg: case cs_reg:
14738 case ds_reg: case fs_reg: case gs_reg:
14739 oappend (names_seg[code - es_reg]);
14751 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14752 case sp_reg: case bp_reg: case si_reg: case di_reg:
14753 s = names16[code - ax_reg + add];
14755 case al_reg: case ah_reg: case cl_reg: case ch_reg:
14756 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14759 s = names8rex[code - al_reg + add];
14761 s = names8[code - al_reg];
14763 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14764 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14765 if (address_mode == mode_64bit
14766 && ((sizeflag & DFLAG) || (rex & REX_W)))
14768 s = names64[code - rAX_reg + add];
14771 code += eAX_reg - rAX_reg;
14772 /* Fall through. */
14773 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14774 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14777 s = names64[code - eAX_reg + add];
14780 if (sizeflag & DFLAG)
14781 s = names32[code - eAX_reg + add];
14783 s = names16[code - eAX_reg + add];
14784 used_prefixes |= (prefixes & PREFIX_DATA);
14788 s = INTERNAL_DISASSEMBLER_ERROR;
14795 OP_IMREG (int code, int sizeflag)
14807 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14808 case sp_reg: case bp_reg: case si_reg: case di_reg:
14809 s = names16[code - ax_reg];
14811 case es_reg: case ss_reg: case cs_reg:
14812 case ds_reg: case fs_reg: case gs_reg:
14813 s = names_seg[code - es_reg];
14815 case al_reg: case ah_reg: case cl_reg: case ch_reg:
14816 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14819 s = names8rex[code - al_reg];
14821 s = names8[code - al_reg];
14823 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14824 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14827 s = names64[code - eAX_reg];
14830 if (sizeflag & DFLAG)
14831 s = names32[code - eAX_reg];
14833 s = names16[code - eAX_reg];
14834 used_prefixes |= (prefixes & PREFIX_DATA);
14837 case z_mode_ax_reg:
14838 if ((rex & REX_W) || (sizeflag & DFLAG))
14842 if (!(rex & REX_W))
14843 used_prefixes |= (prefixes & PREFIX_DATA);
14846 s = INTERNAL_DISASSEMBLER_ERROR;
14853 OP_I (int bytemode, int sizeflag)
14856 bfd_signed_vma mask = -1;
14861 FETCH_DATA (the_info, codep + 1);
14866 if (address_mode == mode_64bit)
14871 /* Fall through. */
14878 if (sizeflag & DFLAG)
14888 used_prefixes |= (prefixes & PREFIX_DATA);
14900 oappend (INTERNAL_DISASSEMBLER_ERROR);
14905 scratchbuf[0] = '$';
14906 print_operand_value (scratchbuf + 1, 1, op);
14907 oappend (scratchbuf + intel_syntax);
14908 scratchbuf[0] = '\0';
14912 OP_I64 (int bytemode, int sizeflag)
14915 bfd_signed_vma mask = -1;
14917 if (address_mode != mode_64bit)
14919 OP_I (bytemode, sizeflag);
14926 FETCH_DATA (the_info, codep + 1);
14936 if (sizeflag & DFLAG)
14946 used_prefixes |= (prefixes & PREFIX_DATA);
14954 oappend (INTERNAL_DISASSEMBLER_ERROR);
14959 scratchbuf[0] = '$';
14960 print_operand_value (scratchbuf + 1, 1, op);
14961 oappend (scratchbuf + intel_syntax);
14962 scratchbuf[0] = '\0';
14966 OP_sI (int bytemode, int sizeflag)
14974 FETCH_DATA (the_info, codep + 1);
14976 if ((op & 0x80) != 0)
14978 if (bytemode == b_T_mode)
14980 if (address_mode != mode_64bit
14981 || !((sizeflag & DFLAG) || (rex & REX_W)))
14983 /* The operand-size prefix is overridden by a REX prefix. */
14984 if ((sizeflag & DFLAG) || (rex & REX_W))
14992 if (!(rex & REX_W))
14994 if (sizeflag & DFLAG)
15002 /* The operand-size prefix is overridden by a REX prefix. */
15003 if ((sizeflag & DFLAG) || (rex & REX_W))
15009 oappend (INTERNAL_DISASSEMBLER_ERROR);
15013 scratchbuf[0] = '$';
15014 print_operand_value (scratchbuf + 1, 1, op);
15015 oappend (scratchbuf + intel_syntax);
15019 OP_J (int bytemode, int sizeflag)
15023 bfd_vma segment = 0;
15028 FETCH_DATA (the_info, codep + 1);
15030 if ((disp & 0x80) != 0)
15035 if ((sizeflag & DFLAG) || (rex & REX_W))
15040 if ((disp & 0x8000) != 0)
15042 /* In 16bit mode, address is wrapped around at 64k within
15043 the same segment. Otherwise, a data16 prefix on a jump
15044 instruction means that the pc is masked to 16 bits after
15045 the displacement is added! */
15047 if ((prefixes & PREFIX_DATA) == 0)
15048 segment = ((start_pc + codep - start_codep)
15049 & ~((bfd_vma) 0xffff));
15051 if (!(rex & REX_W))
15052 used_prefixes |= (prefixes & PREFIX_DATA);
15055 oappend (INTERNAL_DISASSEMBLER_ERROR);
15058 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15060 print_operand_value (scratchbuf, 1, disp);
15061 oappend (scratchbuf);
15065 OP_SEG (int bytemode, int sizeflag)
15067 if (bytemode == w_mode)
15068 oappend (names_seg[modrm.reg]);
15070 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15074 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15078 if (sizeflag & DFLAG)
15088 used_prefixes |= (prefixes & PREFIX_DATA);
15090 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15092 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15093 oappend (scratchbuf);
15097 OP_OFF (int bytemode, int sizeflag)
15101 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15102 intel_operand_size (bytemode, sizeflag);
15105 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15112 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
15113 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
15115 oappend (names_seg[ds_reg - es_reg]);
15119 print_operand_value (scratchbuf, 1, off);
15120 oappend (scratchbuf);
15124 OP_OFF64 (int bytemode, int sizeflag)
15128 if (address_mode != mode_64bit
15129 || (prefixes & PREFIX_ADDR))
15131 OP_OFF (bytemode, sizeflag);
15135 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15136 intel_operand_size (bytemode, sizeflag);
15143 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
15144 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
15146 oappend (names_seg[ds_reg - es_reg]);
15150 print_operand_value (scratchbuf, 1, off);
15151 oappend (scratchbuf);
15155 ptr_reg (int code, int sizeflag)
15159 *obufp++ = open_char;
15160 used_prefixes |= (prefixes & PREFIX_ADDR);
15161 if (address_mode == mode_64bit)
15163 if (!(sizeflag & AFLAG))
15164 s = names32[code - eAX_reg];
15166 s = names64[code - eAX_reg];
15168 else if (sizeflag & AFLAG)
15169 s = names32[code - eAX_reg];
15171 s = names16[code - eAX_reg];
15173 *obufp++ = close_char;
15178 OP_ESreg (int code, int sizeflag)
15184 case 0x6d: /* insw/insl */
15185 intel_operand_size (z_mode, sizeflag);
15187 case 0xa5: /* movsw/movsl/movsq */
15188 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15189 case 0xab: /* stosw/stosl */
15190 case 0xaf: /* scasw/scasl */
15191 intel_operand_size (v_mode, sizeflag);
15194 intel_operand_size (b_mode, sizeflag);
15197 oappend ("%es:" + intel_syntax);
15198 ptr_reg (code, sizeflag);
15202 OP_DSreg (int code, int sizeflag)
15208 case 0x6f: /* outsw/outsl */
15209 intel_operand_size (z_mode, sizeflag);
15211 case 0xa5: /* movsw/movsl/movsq */
15212 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15213 case 0xad: /* lodsw/lodsl/lodsq */
15214 intel_operand_size (v_mode, sizeflag);
15217 intel_operand_size (b_mode, sizeflag);
15226 | PREFIX_GS)) == 0)
15227 prefixes |= PREFIX_DS;
15229 ptr_reg (code, sizeflag);
15233 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15241 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15243 all_prefixes[last_lock_prefix] = 0;
15244 used_prefixes |= PREFIX_LOCK;
15249 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15250 oappend (scratchbuf + intel_syntax);
15254 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15263 sprintf (scratchbuf, "db%d", modrm.reg + add);
15265 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15266 oappend (scratchbuf);
15270 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15272 sprintf (scratchbuf, "%%tr%d", modrm.reg);
15273 oappend (scratchbuf + intel_syntax);
15277 OP_R (int bytemode, int sizeflag)
15279 if (modrm.mod == 3)
15280 OP_E (bytemode, sizeflag);
15286 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15288 int reg = modrm.reg;
15289 const char **names;
15291 used_prefixes |= (prefixes & PREFIX_DATA);
15292 if (prefixes & PREFIX_DATA)
15301 oappend (names[reg]);
15305 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15307 int reg = modrm.reg;
15308 const char **names;
15320 && bytemode != xmm_mode
15321 && bytemode != xmmq_mode
15322 && bytemode != evex_half_bcst_xmmq_mode
15323 && bytemode != ymm_mode
15324 && bytemode != scalar_mode)
15326 switch (vex.length)
15332 if (vex.w || bytemode != vex_vsib_q_w_dq_mode)
15344 else if (bytemode == xmmq_mode
15345 || bytemode == evex_half_bcst_xmmq_mode)
15347 switch (vex.length)
15360 else if (bytemode == ymm_mode)
15364 oappend (names[reg]);
15368 OP_EM (int bytemode, int sizeflag)
15371 const char **names;
15373 if (modrm.mod != 3)
15376 && (bytemode == v_mode || bytemode == v_swap_mode))
15378 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15379 used_prefixes |= (prefixes & PREFIX_DATA);
15381 OP_E (bytemode, sizeflag);
15385 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15388 /* Skip mod/rm byte. */
15391 used_prefixes |= (prefixes & PREFIX_DATA);
15393 if (prefixes & PREFIX_DATA)
15402 oappend (names[reg]);
15405 /* cvt* are the only instructions in sse2 which have
15406 both SSE and MMX operands and also have 0x66 prefix
15407 in their opcode. 0x66 was originally used to differentiate
15408 between SSE and MMX instruction(operands). So we have to handle the
15409 cvt* separately using OP_EMC and OP_MXC */
15411 OP_EMC (int bytemode, int sizeflag)
15413 if (modrm.mod != 3)
15415 if (intel_syntax && bytemode == v_mode)
15417 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15418 used_prefixes |= (prefixes & PREFIX_DATA);
15420 OP_E (bytemode, sizeflag);
15424 /* Skip mod/rm byte. */
15427 used_prefixes |= (prefixes & PREFIX_DATA);
15428 oappend (names_mm[modrm.rm]);
15432 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15434 used_prefixes |= (prefixes & PREFIX_DATA);
15435 oappend (names_mm[modrm.reg]);
15439 OP_EX (int bytemode, int sizeflag)
15442 const char **names;
15444 /* Skip mod/rm byte. */
15448 if (modrm.mod != 3)
15450 OP_E_memory (bytemode, sizeflag);
15465 if ((sizeflag & SUFFIX_ALWAYS)
15466 && (bytemode == x_swap_mode
15467 || bytemode == d_swap_mode
15468 || bytemode == d_scalar_swap_mode
15469 || bytemode == q_swap_mode
15470 || bytemode == q_scalar_swap_mode))
15474 && bytemode != xmm_mode
15475 && bytemode != xmmdw_mode
15476 && bytemode != xmmqd_mode
15477 && bytemode != xmm_mb_mode
15478 && bytemode != xmm_mw_mode
15479 && bytemode != xmm_md_mode
15480 && bytemode != xmm_mq_mode
15481 && bytemode != xmm_mdq_mode
15482 && bytemode != xmmq_mode
15483 && bytemode != evex_half_bcst_xmmq_mode
15484 && bytemode != ymm_mode
15485 && bytemode != d_scalar_mode
15486 && bytemode != d_scalar_swap_mode
15487 && bytemode != q_scalar_mode
15488 && bytemode != q_scalar_swap_mode
15489 && bytemode != vex_scalar_w_dq_mode)
15491 switch (vex.length)
15506 else if (bytemode == xmmq_mode
15507 || bytemode == evex_half_bcst_xmmq_mode)
15509 switch (vex.length)
15522 else if (bytemode == ymm_mode)
15526 oappend (names[reg]);
15530 OP_MS (int bytemode, int sizeflag)
15532 if (modrm.mod == 3)
15533 OP_EM (bytemode, sizeflag);
15539 OP_XS (int bytemode, int sizeflag)
15541 if (modrm.mod == 3)
15542 OP_EX (bytemode, sizeflag);
15548 OP_M (int bytemode, int sizeflag)
15550 if (modrm.mod == 3)
15551 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15554 OP_E (bytemode, sizeflag);
15558 OP_0f07 (int bytemode, int sizeflag)
15560 if (modrm.mod != 3 || modrm.rm != 0)
15563 OP_E (bytemode, sizeflag);
15566 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15567 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15570 NOP_Fixup1 (int bytemode, int sizeflag)
15572 if ((prefixes & PREFIX_DATA) != 0
15575 && address_mode == mode_64bit))
15576 OP_REG (bytemode, sizeflag);
15578 strcpy (obuf, "nop");
15582 NOP_Fixup2 (int bytemode, int sizeflag)
15584 if ((prefixes & PREFIX_DATA) != 0
15587 && address_mode == mode_64bit))
15588 OP_IMREG (bytemode, sizeflag);
15591 static const char *const Suffix3DNow[] = {
15592 /* 00 */ NULL, NULL, NULL, NULL,
15593 /* 04 */ NULL, NULL, NULL, NULL,
15594 /* 08 */ NULL, NULL, NULL, NULL,
15595 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
15596 /* 10 */ NULL, NULL, NULL, NULL,
15597 /* 14 */ NULL, NULL, NULL, NULL,
15598 /* 18 */ NULL, NULL, NULL, NULL,
15599 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
15600 /* 20 */ NULL, NULL, NULL, NULL,
15601 /* 24 */ NULL, NULL, NULL, NULL,
15602 /* 28 */ NULL, NULL, NULL, NULL,
15603 /* 2C */ NULL, NULL, NULL, NULL,
15604 /* 30 */ NULL, NULL, NULL, NULL,
15605 /* 34 */ NULL, NULL, NULL, NULL,
15606 /* 38 */ NULL, NULL, NULL, NULL,
15607 /* 3C */ NULL, NULL, NULL, NULL,
15608 /* 40 */ NULL, NULL, NULL, NULL,
15609 /* 44 */ NULL, NULL, NULL, NULL,
15610 /* 48 */ NULL, NULL, NULL, NULL,
15611 /* 4C */ NULL, NULL, NULL, NULL,
15612 /* 50 */ NULL, NULL, NULL, NULL,
15613 /* 54 */ NULL, NULL, NULL, NULL,
15614 /* 58 */ NULL, NULL, NULL, NULL,
15615 /* 5C */ NULL, NULL, NULL, NULL,
15616 /* 60 */ NULL, NULL, NULL, NULL,
15617 /* 64 */ NULL, NULL, NULL, NULL,
15618 /* 68 */ NULL, NULL, NULL, NULL,
15619 /* 6C */ NULL, NULL, NULL, NULL,
15620 /* 70 */ NULL, NULL, NULL, NULL,
15621 /* 74 */ NULL, NULL, NULL, NULL,
15622 /* 78 */ NULL, NULL, NULL, NULL,
15623 /* 7C */ NULL, NULL, NULL, NULL,
15624 /* 80 */ NULL, NULL, NULL, NULL,
15625 /* 84 */ NULL, NULL, NULL, NULL,
15626 /* 88 */ NULL, NULL, "pfnacc", NULL,
15627 /* 8C */ NULL, NULL, "pfpnacc", NULL,
15628 /* 90 */ "pfcmpge", NULL, NULL, NULL,
15629 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
15630 /* 98 */ NULL, NULL, "pfsub", NULL,
15631 /* 9C */ NULL, NULL, "pfadd", NULL,
15632 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
15633 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
15634 /* A8 */ NULL, NULL, "pfsubr", NULL,
15635 /* AC */ NULL, NULL, "pfacc", NULL,
15636 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
15637 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
15638 /* B8 */ NULL, NULL, NULL, "pswapd",
15639 /* BC */ NULL, NULL, NULL, "pavgusb",
15640 /* C0 */ NULL, NULL, NULL, NULL,
15641 /* C4 */ NULL, NULL, NULL, NULL,
15642 /* C8 */ NULL, NULL, NULL, NULL,
15643 /* CC */ NULL, NULL, NULL, NULL,
15644 /* D0 */ NULL, NULL, NULL, NULL,
15645 /* D4 */ NULL, NULL, NULL, NULL,
15646 /* D8 */ NULL, NULL, NULL, NULL,
15647 /* DC */ NULL, NULL, NULL, NULL,
15648 /* E0 */ NULL, NULL, NULL, NULL,
15649 /* E4 */ NULL, NULL, NULL, NULL,
15650 /* E8 */ NULL, NULL, NULL, NULL,
15651 /* EC */ NULL, NULL, NULL, NULL,
15652 /* F0 */ NULL, NULL, NULL, NULL,
15653 /* F4 */ NULL, NULL, NULL, NULL,
15654 /* F8 */ NULL, NULL, NULL, NULL,
15655 /* FC */ NULL, NULL, NULL, NULL,
15659 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15661 const char *mnemonic;
15663 FETCH_DATA (the_info, codep + 1);
15664 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15665 place where an 8-bit immediate would normally go. ie. the last
15666 byte of the instruction. */
15667 obufp = mnemonicendp;
15668 mnemonic = Suffix3DNow[*codep++ & 0xff];
15670 oappend (mnemonic);
15673 /* Since a variable sized modrm/sib chunk is between the start
15674 of the opcode (0x0f0f) and the opcode suffix, we need to do
15675 all the modrm processing first, and don't know until now that
15676 we have a bad opcode. This necessitates some cleaning up. */
15677 op_out[0][0] = '\0';
15678 op_out[1][0] = '\0';
15681 mnemonicendp = obufp;
15684 static struct op simd_cmp_op[] =
15686 { STRING_COMMA_LEN ("eq") },
15687 { STRING_COMMA_LEN ("lt") },
15688 { STRING_COMMA_LEN ("le") },
15689 { STRING_COMMA_LEN ("unord") },
15690 { STRING_COMMA_LEN ("neq") },
15691 { STRING_COMMA_LEN ("nlt") },
15692 { STRING_COMMA_LEN ("nle") },
15693 { STRING_COMMA_LEN ("ord") }
15697 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15699 unsigned int cmp_type;
15701 FETCH_DATA (the_info, codep + 1);
15702 cmp_type = *codep++ & 0xff;
15703 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15706 char *p = mnemonicendp - 2;
15710 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15711 mnemonicendp += simd_cmp_op[cmp_type].len;
15715 /* We have a reserved extension byte. Output it directly. */
15716 scratchbuf[0] = '$';
15717 print_operand_value (scratchbuf + 1, 1, cmp_type);
15718 oappend (scratchbuf + intel_syntax);
15719 scratchbuf[0] = '\0';
15724 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15725 int sizeflag ATTRIBUTE_UNUSED)
15727 /* mwait %eax,%ecx */
15730 const char **names = (address_mode == mode_64bit
15731 ? names64 : names32);
15732 strcpy (op_out[0], names[0]);
15733 strcpy (op_out[1], names[1]);
15734 two_source_ops = 1;
15736 /* Skip mod/rm byte. */
15742 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15743 int sizeflag ATTRIBUTE_UNUSED)
15745 /* monitor %eax,%ecx,%edx" */
15748 const char **op1_names;
15749 const char **names = (address_mode == mode_64bit
15750 ? names64 : names32);
15752 if (!(prefixes & PREFIX_ADDR))
15753 op1_names = (address_mode == mode_16bit
15754 ? names16 : names);
15757 /* Remove "addr16/addr32". */
15758 all_prefixes[last_addr_prefix] = 0;
15759 op1_names = (address_mode != mode_32bit
15760 ? names32 : names16);
15761 used_prefixes |= PREFIX_ADDR;
15763 strcpy (op_out[0], op1_names[0]);
15764 strcpy (op_out[1], names[1]);
15765 strcpy (op_out[2], names[2]);
15766 two_source_ops = 1;
15768 /* Skip mod/rm byte. */
15776 /* Throw away prefixes and 1st. opcode byte. */
15777 codep = insn_codep + 1;
15782 REP_Fixup (int bytemode, int sizeflag)
15784 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15786 if (prefixes & PREFIX_REPZ)
15787 all_prefixes[last_repz_prefix] = REP_PREFIX;
15794 OP_IMREG (bytemode, sizeflag);
15797 OP_ESreg (bytemode, sizeflag);
15800 OP_DSreg (bytemode, sizeflag);
15808 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15812 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15814 if (prefixes & PREFIX_REPNZ)
15815 all_prefixes[last_repnz_prefix] = BND_PREFIX;
15818 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15819 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15823 HLE_Fixup1 (int bytemode, int sizeflag)
15826 && (prefixes & PREFIX_LOCK) != 0)
15828 if (prefixes & PREFIX_REPZ)
15829 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15830 if (prefixes & PREFIX_REPNZ)
15831 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15834 OP_E (bytemode, sizeflag);
15837 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15838 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15842 HLE_Fixup2 (int bytemode, int sizeflag)
15844 if (modrm.mod != 3)
15846 if (prefixes & PREFIX_REPZ)
15847 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15848 if (prefixes & PREFIX_REPNZ)
15849 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15852 OP_E (bytemode, sizeflag);
15855 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15856 "xrelease" for memory operand. No check for LOCK prefix. */
15859 HLE_Fixup3 (int bytemode, int sizeflag)
15862 && last_repz_prefix > last_repnz_prefix
15863 && (prefixes & PREFIX_REPZ) != 0)
15864 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15866 OP_E (bytemode, sizeflag);
15870 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15875 /* Change cmpxchg8b to cmpxchg16b. */
15876 char *p = mnemonicendp - 2;
15877 mnemonicendp = stpcpy (p, "16b");
15880 else if ((prefixes & PREFIX_LOCK) != 0)
15882 if (prefixes & PREFIX_REPZ)
15883 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15884 if (prefixes & PREFIX_REPNZ)
15885 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15888 OP_M (bytemode, sizeflag);
15892 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15894 const char **names;
15898 switch (vex.length)
15912 oappend (names[reg]);
15916 CRC32_Fixup (int bytemode, int sizeflag)
15918 /* Add proper suffix to "crc32". */
15919 char *p = mnemonicendp;
15938 if (sizeflag & DFLAG)
15942 used_prefixes |= (prefixes & PREFIX_DATA);
15946 oappend (INTERNAL_DISASSEMBLER_ERROR);
15953 if (modrm.mod == 3)
15957 /* Skip mod/rm byte. */
15962 add = (rex & REX_B) ? 8 : 0;
15963 if (bytemode == b_mode)
15967 oappend (names8rex[modrm.rm + add]);
15969 oappend (names8[modrm.rm + add]);
15975 oappend (names64[modrm.rm + add]);
15976 else if ((prefixes & PREFIX_DATA))
15977 oappend (names16[modrm.rm + add]);
15979 oappend (names32[modrm.rm + add]);
15983 OP_E (bytemode, sizeflag);
15987 FXSAVE_Fixup (int bytemode, int sizeflag)
15989 /* Add proper suffix to "fxsave" and "fxrstor". */
15993 char *p = mnemonicendp;
15999 OP_M (bytemode, sizeflag);
16002 /* Display the destination register operand for instructions with
16006 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16009 const char **names;
16017 reg = vex.register_specifier;
16024 if (bytemode == vex_scalar_mode)
16026 oappend (names_xmm[reg]);
16030 switch (vex.length)
16037 case vex_vsib_q_w_dq_mode:
16047 names = names_mask;
16061 case vex_vsib_q_w_dq_mode:
16062 names = vex.w ? names_ymm : names_xmm;
16065 names = names_mask;
16079 oappend (names[reg]);
16082 /* Get the VEX immediate byte without moving codep. */
16084 static unsigned char
16085 get_vex_imm8 (int sizeflag, int opnum)
16087 int bytes_before_imm = 0;
16089 if (modrm.mod != 3)
16091 /* There are SIB/displacement bytes. */
16092 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16094 /* 32/64 bit address mode */
16095 int base = modrm.rm;
16097 /* Check SIB byte. */
16100 FETCH_DATA (the_info, codep + 1);
16102 /* When decoding the third source, don't increase
16103 bytes_before_imm as this has already been incremented
16104 by one in OP_E_memory while decoding the second
16107 bytes_before_imm++;
16110 /* Don't increase bytes_before_imm when decoding the third source,
16111 it has already been incremented by OP_E_memory while decoding
16112 the second source operand. */
16118 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16119 SIB == 5, there is a 4 byte displacement. */
16121 /* No displacement. */
16124 /* 4 byte displacement. */
16125 bytes_before_imm += 4;
16128 /* 1 byte displacement. */
16129 bytes_before_imm++;
16136 /* 16 bit address mode */
16137 /* Don't increase bytes_before_imm when decoding the third source,
16138 it has already been incremented by OP_E_memory while decoding
16139 the second source operand. */
16145 /* When modrm.rm == 6, there is a 2 byte displacement. */
16147 /* No displacement. */
16150 /* 2 byte displacement. */
16151 bytes_before_imm += 2;
16154 /* 1 byte displacement: when decoding the third source,
16155 don't increase bytes_before_imm as this has already
16156 been incremented by one in OP_E_memory while decoding
16157 the second source operand. */
16159 bytes_before_imm++;
16167 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16168 return codep [bytes_before_imm];
16172 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16174 const char **names;
16176 if (reg == -1 && modrm.mod != 3)
16178 OP_E_memory (bytemode, sizeflag);
16190 else if (reg > 7 && address_mode != mode_64bit)
16194 switch (vex.length)
16205 oappend (names[reg]);
16209 OP_EX_VexImmW (int bytemode, int sizeflag)
16212 static unsigned char vex_imm8;
16214 if (vex_w_done == 0)
16218 /* Skip mod/rm byte. */
16222 vex_imm8 = get_vex_imm8 (sizeflag, 0);
16225 reg = vex_imm8 >> 4;
16227 OP_EX_VexReg (bytemode, sizeflag, reg);
16229 else if (vex_w_done == 1)
16234 reg = vex_imm8 >> 4;
16236 OP_EX_VexReg (bytemode, sizeflag, reg);
16240 /* Output the imm8 directly. */
16241 scratchbuf[0] = '$';
16242 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16243 oappend (scratchbuf + intel_syntax);
16244 scratchbuf[0] = '\0';
16250 OP_Vex_2src (int bytemode, int sizeflag)
16252 if (modrm.mod == 3)
16254 int reg = modrm.rm;
16258 oappend (names_xmm[reg]);
16263 && (bytemode == v_mode || bytemode == v_swap_mode))
16265 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16266 used_prefixes |= (prefixes & PREFIX_DATA);
16268 OP_E (bytemode, sizeflag);
16273 OP_Vex_2src_1 (int bytemode, int sizeflag)
16275 if (modrm.mod == 3)
16277 /* Skip mod/rm byte. */
16283 oappend (names_xmm[vex.register_specifier]);
16285 OP_Vex_2src (bytemode, sizeflag);
16289 OP_Vex_2src_2 (int bytemode, int sizeflag)
16292 OP_Vex_2src (bytemode, sizeflag);
16294 oappend (names_xmm[vex.register_specifier]);
16298 OP_EX_VexW (int bytemode, int sizeflag)
16306 /* Skip mod/rm byte. */
16311 reg = get_vex_imm8 (sizeflag, 0) >> 4;
16316 reg = get_vex_imm8 (sizeflag, 1) >> 4;
16319 OP_EX_VexReg (bytemode, sizeflag, reg);
16323 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16324 int sizeflag ATTRIBUTE_UNUSED)
16326 /* Skip the immediate byte and check for invalid bits. */
16327 FETCH_DATA (the_info, codep + 1);
16328 if (*codep++ & 0xf)
16333 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16336 const char **names;
16338 FETCH_DATA (the_info, codep + 1);
16341 if (bytemode != x_mode)
16348 if (reg > 7 && address_mode != mode_64bit)
16351 switch (vex.length)
16362 oappend (names[reg]);
16366 OP_XMM_VexW (int bytemode, int sizeflag)
16368 /* Turn off the REX.W bit since it is used for swapping operands
16371 OP_XMM (bytemode, sizeflag);
16375 OP_EX_Vex (int bytemode, int sizeflag)
16377 if (modrm.mod != 3)
16379 if (vex.register_specifier != 0)
16383 OP_EX (bytemode, sizeflag);
16387 OP_XMM_Vex (int bytemode, int sizeflag)
16389 if (modrm.mod != 3)
16391 if (vex.register_specifier != 0)
16395 OP_XMM (bytemode, sizeflag);
16399 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16401 switch (vex.length)
16404 mnemonicendp = stpcpy (obuf, "vzeroupper");
16407 mnemonicendp = stpcpy (obuf, "vzeroall");
16414 static struct op vex_cmp_op[] =
16416 { STRING_COMMA_LEN ("eq") },
16417 { STRING_COMMA_LEN ("lt") },
16418 { STRING_COMMA_LEN ("le") },
16419 { STRING_COMMA_LEN ("unord") },
16420 { STRING_COMMA_LEN ("neq") },
16421 { STRING_COMMA_LEN ("nlt") },
16422 { STRING_COMMA_LEN ("nle") },
16423 { STRING_COMMA_LEN ("ord") },
16424 { STRING_COMMA_LEN ("eq_uq") },
16425 { STRING_COMMA_LEN ("nge") },
16426 { STRING_COMMA_LEN ("ngt") },
16427 { STRING_COMMA_LEN ("false") },
16428 { STRING_COMMA_LEN ("neq_oq") },
16429 { STRING_COMMA_LEN ("ge") },
16430 { STRING_COMMA_LEN ("gt") },
16431 { STRING_COMMA_LEN ("true") },
16432 { STRING_COMMA_LEN ("eq_os") },
16433 { STRING_COMMA_LEN ("lt_oq") },
16434 { STRING_COMMA_LEN ("le_oq") },
16435 { STRING_COMMA_LEN ("unord_s") },
16436 { STRING_COMMA_LEN ("neq_us") },
16437 { STRING_COMMA_LEN ("nlt_uq") },
16438 { STRING_COMMA_LEN ("nle_uq") },
16439 { STRING_COMMA_LEN ("ord_s") },
16440 { STRING_COMMA_LEN ("eq_us") },
16441 { STRING_COMMA_LEN ("nge_uq") },
16442 { STRING_COMMA_LEN ("ngt_uq") },
16443 { STRING_COMMA_LEN ("false_os") },
16444 { STRING_COMMA_LEN ("neq_os") },
16445 { STRING_COMMA_LEN ("ge_oq") },
16446 { STRING_COMMA_LEN ("gt_oq") },
16447 { STRING_COMMA_LEN ("true_us") },
16451 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16453 unsigned int cmp_type;
16455 FETCH_DATA (the_info, codep + 1);
16456 cmp_type = *codep++ & 0xff;
16457 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16460 char *p = mnemonicendp - 2;
16464 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16465 mnemonicendp += vex_cmp_op[cmp_type].len;
16469 /* We have a reserved extension byte. Output it directly. */
16470 scratchbuf[0] = '$';
16471 print_operand_value (scratchbuf + 1, 1, cmp_type);
16472 oappend (scratchbuf + intel_syntax);
16473 scratchbuf[0] = '\0';
16478 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16479 int sizeflag ATTRIBUTE_UNUSED)
16481 unsigned int cmp_type;
16486 FETCH_DATA (the_info, codep + 1);
16487 cmp_type = *codep++ & 0xff;
16488 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16489 If it's the case, print suffix, otherwise - print the immediate. */
16490 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16495 char *p = mnemonicendp - 2;
16497 /* vpcmp* can have both one- and two-lettered suffix. */
16511 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16512 mnemonicendp += simd_cmp_op[cmp_type].len;
16516 /* We have a reserved extension byte. Output it directly. */
16517 scratchbuf[0] = '$';
16518 print_operand_value (scratchbuf + 1, 1, cmp_type);
16519 oappend (scratchbuf + intel_syntax);
16520 scratchbuf[0] = '\0';
16524 static const struct op pclmul_op[] =
16526 { STRING_COMMA_LEN ("lql") },
16527 { STRING_COMMA_LEN ("hql") },
16528 { STRING_COMMA_LEN ("lqh") },
16529 { STRING_COMMA_LEN ("hqh") }
16533 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16534 int sizeflag ATTRIBUTE_UNUSED)
16536 unsigned int pclmul_type;
16538 FETCH_DATA (the_info, codep + 1);
16539 pclmul_type = *codep++ & 0xff;
16540 switch (pclmul_type)
16551 if (pclmul_type < ARRAY_SIZE (pclmul_op))
16554 char *p = mnemonicendp - 3;
16559 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16560 mnemonicendp += pclmul_op[pclmul_type].len;
16564 /* We have a reserved extension byte. Output it directly. */
16565 scratchbuf[0] = '$';
16566 print_operand_value (scratchbuf + 1, 1, pclmul_type);
16567 oappend (scratchbuf + intel_syntax);
16568 scratchbuf[0] = '\0';
16573 MOVBE_Fixup (int bytemode, int sizeflag)
16575 /* Add proper suffix to "movbe". */
16576 char *p = mnemonicendp;
16585 if (sizeflag & SUFFIX_ALWAYS)
16591 if (sizeflag & DFLAG)
16595 used_prefixes |= (prefixes & PREFIX_DATA);
16600 oappend (INTERNAL_DISASSEMBLER_ERROR);
16607 OP_M (bytemode, sizeflag);
16611 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16614 const char **names;
16616 /* Skip mod/rm byte. */
16630 oappend (names[reg]);
16634 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16636 const char **names;
16643 oappend (names[vex.register_specifier]);
16647 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16650 || bytemode != mask_mode)
16654 if ((rex & REX_R) != 0 || !vex.r)
16660 oappend (names_mask [modrm.reg]);
16664 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16667 || (bytemode != evex_rounding_mode
16668 && bytemode != evex_sae_mode))
16670 if (modrm.mod == 3 && vex.b)
16673 case evex_rounding_mode:
16674 oappend (names_rounding[vex.ll]);
16676 case evex_sae_mode: