1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
30 /* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
40 #include "opcode/i386.h"
41 #include "libiberty.h"
45 static int print_insn (bfd_vma, disassemble_info *);
46 static void dofloat (int);
47 static void OP_ST (int, int);
48 static void OP_STi (int, int);
49 static int putop (const char *, int);
50 static void oappend (const char *);
51 static void append_seg (void);
52 static void OP_indirE (int, int);
53 static void print_operand_value (char *, int, bfd_vma);
54 static void OP_E_register (int, int);
55 static void OP_E_memory (int, int);
56 static void print_displacement (char *, bfd_vma);
57 static void OP_E (int, int);
58 static void OP_G (int, int);
59 static bfd_vma get64 (void);
60 static bfd_signed_vma get32 (void);
61 static bfd_signed_vma get32s (void);
62 static int get16 (void);
63 static void set_op (bfd_vma, int);
64 static void OP_Skip_MODRM (int, int);
65 static void OP_REG (int, int);
66 static void OP_IMREG (int, int);
67 static void OP_I (int, int);
68 static void OP_I64 (int, int);
69 static void OP_sI (int, int);
70 static void OP_J (int, int);
71 static void OP_SEG (int, int);
72 static void OP_DIR (int, int);
73 static void OP_OFF (int, int);
74 static void OP_OFF64 (int, int);
75 static void ptr_reg (int, int);
76 static void OP_ESreg (int, int);
77 static void OP_DSreg (int, int);
78 static void OP_C (int, int);
79 static void OP_D (int, int);
80 static void OP_T (int, int);
81 static void OP_R (int, int);
82 static void OP_MMX (int, int);
83 static void OP_XMM (int, int);
84 static void OP_EM (int, int);
85 static void OP_EX (int, int);
86 static void OP_EMC (int,int);
87 static void OP_MXC (int,int);
88 static void OP_MS (int, int);
89 static void OP_XS (int, int);
90 static void OP_M (int, int);
91 static void OP_VEX (int, int);
92 static void OP_EX_Vex (int, int);
93 static void OP_EX_VexW (int, int);
94 static void OP_EX_VexImmW (int, int);
95 static void OP_XMM_Vex (int, int);
96 static void OP_XMM_VexW (int, int);
97 static void OP_Rounding (int, int);
98 static void OP_REG_VexI4 (int, int);
99 static void PCLMUL_Fixup (int, int);
100 static void VEXI4_Fixup (int, int);
101 static void VZERO_Fixup (int, int);
102 static void VCMP_Fixup (int, int);
103 static void VPCMP_Fixup (int, int);
104 static void OP_0f07 (int, int);
105 static void OP_Monitor (int, int);
106 static void OP_Mwait (int, int);
107 static void NOP_Fixup1 (int, int);
108 static void NOP_Fixup2 (int, int);
109 static void OP_3DNowSuffix (int, int);
110 static void CMP_Fixup (int, int);
111 static void BadOp (void);
112 static void REP_Fixup (int, int);
113 static void BND_Fixup (int, int);
114 static void HLE_Fixup1 (int, int);
115 static void HLE_Fixup2 (int, int);
116 static void HLE_Fixup3 (int, int);
117 static void CMPXCHG8B_Fixup (int, int);
118 static void XMM_Fixup (int, int);
119 static void CRC32_Fixup (int, int);
120 static void FXSAVE_Fixup (int, int);
121 static void OP_LWPCB_E (int, int);
122 static void OP_LWP_E (int, int);
123 static void OP_Vex_2src_1 (int, int);
124 static void OP_Vex_2src_2 (int, int);
126 static void MOVBE_Fixup (int, int);
128 static void OP_Mask (int, int);
131 /* Points to first byte not fetched. */
132 bfd_byte *max_fetched;
133 bfd_byte the_buffer[MAX_MNEM_SIZE];
146 enum address_mode address_mode;
148 /* Flags for the prefixes for the current instruction. See below. */
151 /* REX prefix the current instruction. See below. */
153 /* Bits of REX we've already used. */
155 /* REX bits in original REX prefix ignored. */
156 static int rex_ignored;
157 /* Mark parts used in the REX prefix. When we are testing for
158 empty prefix (for 8bit register REX extension), just mask it
159 out. Otherwise test for REX bit is excuse for existence of REX
160 only in case value is nonzero. */
161 #define USED_REX(value) \
166 rex_used |= (value) | REX_OPCODE; \
169 rex_used |= REX_OPCODE; \
172 /* Flags for prefixes which we somehow handled when printing the
173 current instruction. */
174 static int used_prefixes;
176 /* Flags stored in PREFIXES. */
177 #define PREFIX_REPZ 1
178 #define PREFIX_REPNZ 2
179 #define PREFIX_LOCK 4
181 #define PREFIX_SS 0x10
182 #define PREFIX_DS 0x20
183 #define PREFIX_ES 0x40
184 #define PREFIX_FS 0x80
185 #define PREFIX_GS 0x100
186 #define PREFIX_DATA 0x200
187 #define PREFIX_ADDR 0x400
188 #define PREFIX_FWAIT 0x800
190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
191 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
193 #define FETCH_DATA(info, addr) \
194 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
195 ? 1 : fetch_data ((info), (addr)))
198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
201 struct dis_private *priv = (struct dis_private *) info->private_data;
202 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
204 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
205 status = (*info->read_memory_func) (start,
207 addr - priv->max_fetched,
213 /* If we did manage to read at least one byte, then
214 print_insn_i386 will do something sensible. Otherwise, print
215 an error. We do that here because this is where we know
217 if (priv->max_fetched == priv->the_buffer)
218 (*info->memory_error_func) (status, start, info);
219 longjmp (priv->bailout, 1);
222 priv->max_fetched = addr;
226 #define XX { NULL, 0 }
227 #define Bad_Opcode NULL, { { NULL, 0 } }
229 #define Eb { OP_E, b_mode }
230 #define Ebnd { OP_E, bnd_mode }
231 #define EbS { OP_E, b_swap_mode }
232 #define Ev { OP_E, v_mode }
233 #define Ev_bnd { OP_E, v_bnd_mode }
234 #define EvS { OP_E, v_swap_mode }
235 #define Ed { OP_E, d_mode }
236 #define Edq { OP_E, dq_mode }
237 #define Edqw { OP_E, dqw_mode }
238 #define Edqb { OP_E, dqb_mode }
239 #define Edqd { OP_E, dqd_mode }
240 #define Eq { OP_E, q_mode }
241 #define indirEv { OP_indirE, stack_v_mode }
242 #define indirEp { OP_indirE, f_mode }
243 #define stackEv { OP_E, stack_v_mode }
244 #define Em { OP_E, m_mode }
245 #define Ew { OP_E, w_mode }
246 #define M { OP_M, 0 } /* lea, lgdt, etc. */
247 #define Ma { OP_M, a_mode }
248 #define Mb { OP_M, b_mode }
249 #define Md { OP_M, d_mode }
250 #define Mo { OP_M, o_mode }
251 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
252 #define Mq { OP_M, q_mode }
253 #define Mx { OP_M, x_mode }
254 #define Mxmm { OP_M, xmm_mode }
255 #define Gb { OP_G, b_mode }
256 #define Gbnd { OP_G, bnd_mode }
257 #define Gv { OP_G, v_mode }
258 #define Gd { OP_G, d_mode }
259 #define Gdq { OP_G, dq_mode }
260 #define Gm { OP_G, m_mode }
261 #define Gw { OP_G, w_mode }
262 #define Rd { OP_R, d_mode }
263 #define Rdq { OP_R, dq_mode }
264 #define Rm { OP_R, m_mode }
265 #define Ib { OP_I, b_mode }
266 #define sIb { OP_sI, b_mode } /* sign extened byte */
267 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
268 #define Iv { OP_I, v_mode }
269 #define sIv { OP_sI, v_mode }
270 #define Iq { OP_I, q_mode }
271 #define Iv64 { OP_I64, v_mode }
272 #define Iw { OP_I, w_mode }
273 #define I1 { OP_I, const_1_mode }
274 #define Jb { OP_J, b_mode }
275 #define Jv { OP_J, v_mode }
276 #define Cm { OP_C, m_mode }
277 #define Dm { OP_D, m_mode }
278 #define Td { OP_T, d_mode }
279 #define Skip_MODRM { OP_Skip_MODRM, 0 }
281 #define RMeAX { OP_REG, eAX_reg }
282 #define RMeBX { OP_REG, eBX_reg }
283 #define RMeCX { OP_REG, eCX_reg }
284 #define RMeDX { OP_REG, eDX_reg }
285 #define RMeSP { OP_REG, eSP_reg }
286 #define RMeBP { OP_REG, eBP_reg }
287 #define RMeSI { OP_REG, eSI_reg }
288 #define RMeDI { OP_REG, eDI_reg }
289 #define RMrAX { OP_REG, rAX_reg }
290 #define RMrBX { OP_REG, rBX_reg }
291 #define RMrCX { OP_REG, rCX_reg }
292 #define RMrDX { OP_REG, rDX_reg }
293 #define RMrSP { OP_REG, rSP_reg }
294 #define RMrBP { OP_REG, rBP_reg }
295 #define RMrSI { OP_REG, rSI_reg }
296 #define RMrDI { OP_REG, rDI_reg }
297 #define RMAL { OP_REG, al_reg }
298 #define RMCL { OP_REG, cl_reg }
299 #define RMDL { OP_REG, dl_reg }
300 #define RMBL { OP_REG, bl_reg }
301 #define RMAH { OP_REG, ah_reg }
302 #define RMCH { OP_REG, ch_reg }
303 #define RMDH { OP_REG, dh_reg }
304 #define RMBH { OP_REG, bh_reg }
305 #define RMAX { OP_REG, ax_reg }
306 #define RMDX { OP_REG, dx_reg }
308 #define eAX { OP_IMREG, eAX_reg }
309 #define eBX { OP_IMREG, eBX_reg }
310 #define eCX { OP_IMREG, eCX_reg }
311 #define eDX { OP_IMREG, eDX_reg }
312 #define eSP { OP_IMREG, eSP_reg }
313 #define eBP { OP_IMREG, eBP_reg }
314 #define eSI { OP_IMREG, eSI_reg }
315 #define eDI { OP_IMREG, eDI_reg }
316 #define AL { OP_IMREG, al_reg }
317 #define CL { OP_IMREG, cl_reg }
318 #define DL { OP_IMREG, dl_reg }
319 #define BL { OP_IMREG, bl_reg }
320 #define AH { OP_IMREG, ah_reg }
321 #define CH { OP_IMREG, ch_reg }
322 #define DH { OP_IMREG, dh_reg }
323 #define BH { OP_IMREG, bh_reg }
324 #define AX { OP_IMREG, ax_reg }
325 #define DX { OP_IMREG, dx_reg }
326 #define zAX { OP_IMREG, z_mode_ax_reg }
327 #define indirDX { OP_IMREG, indir_dx_reg }
329 #define Sw { OP_SEG, w_mode }
330 #define Sv { OP_SEG, v_mode }
331 #define Ap { OP_DIR, 0 }
332 #define Ob { OP_OFF64, b_mode }
333 #define Ov { OP_OFF64, v_mode }
334 #define Xb { OP_DSreg, eSI_reg }
335 #define Xv { OP_DSreg, eSI_reg }
336 #define Xz { OP_DSreg, eSI_reg }
337 #define Yb { OP_ESreg, eDI_reg }
338 #define Yv { OP_ESreg, eDI_reg }
339 #define DSBX { OP_DSreg, eBX_reg }
341 #define es { OP_REG, es_reg }
342 #define ss { OP_REG, ss_reg }
343 #define cs { OP_REG, cs_reg }
344 #define ds { OP_REG, ds_reg }
345 #define fs { OP_REG, fs_reg }
346 #define gs { OP_REG, gs_reg }
348 #define MX { OP_MMX, 0 }
349 #define XM { OP_XMM, 0 }
350 #define XMScalar { OP_XMM, scalar_mode }
351 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
352 #define XMM { OP_XMM, xmm_mode }
353 #define XMxmmq { OP_XMM, xmmq_mode }
354 #define EM { OP_EM, v_mode }
355 #define EMS { OP_EM, v_swap_mode }
356 #define EMd { OP_EM, d_mode }
357 #define EMx { OP_EM, x_mode }
358 #define EXw { OP_EX, w_mode }
359 #define EXd { OP_EX, d_mode }
360 #define EXdScalar { OP_EX, d_scalar_mode }
361 #define EXdS { OP_EX, d_swap_mode }
362 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
363 #define EXq { OP_EX, q_mode }
364 #define EXqScalar { OP_EX, q_scalar_mode }
365 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
366 #define EXqS { OP_EX, q_swap_mode }
367 #define EXx { OP_EX, x_mode }
368 #define EXxS { OP_EX, x_swap_mode }
369 #define EXxmm { OP_EX, xmm_mode }
370 #define EXymm { OP_EX, ymm_mode }
371 #define EXxmmq { OP_EX, xmmq_mode }
372 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
373 #define EXxmm_mb { OP_EX, xmm_mb_mode }
374 #define EXxmm_mw { OP_EX, xmm_mw_mode }
375 #define EXxmm_md { OP_EX, xmm_md_mode }
376 #define EXxmm_mq { OP_EX, xmm_mq_mode }
377 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
378 #define EXxmmdw { OP_EX, xmmdw_mode }
379 #define EXxmmqd { OP_EX, xmmqd_mode }
380 #define EXymmq { OP_EX, ymmq_mode }
381 #define EXVexWdq { OP_EX, vex_w_dq_mode }
382 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
383 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
384 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
385 #define MS { OP_MS, v_mode }
386 #define XS { OP_XS, v_mode }
387 #define EMCq { OP_EMC, q_mode }
388 #define MXC { OP_MXC, 0 }
389 #define OPSUF { OP_3DNowSuffix, 0 }
390 #define CMP { CMP_Fixup, 0 }
391 #define XMM0 { XMM_Fixup, 0 }
392 #define FXSAVE { FXSAVE_Fixup, 0 }
393 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
394 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
396 #define Vex { OP_VEX, vex_mode }
397 #define VexScalar { OP_VEX, vex_scalar_mode }
398 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
399 #define Vex128 { OP_VEX, vex128_mode }
400 #define Vex256 { OP_VEX, vex256_mode }
401 #define VexGdq { OP_VEX, dq_mode }
402 #define VexI4 { VEXI4_Fixup, 0}
403 #define EXdVex { OP_EX_Vex, d_mode }
404 #define EXdVexS { OP_EX_Vex, d_swap_mode }
405 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
406 #define EXqVex { OP_EX_Vex, q_mode }
407 #define EXqVexS { OP_EX_Vex, q_swap_mode }
408 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
409 #define EXVexW { OP_EX_VexW, x_mode }
410 #define EXdVexW { OP_EX_VexW, d_mode }
411 #define EXqVexW { OP_EX_VexW, q_mode }
412 #define EXVexImmW { OP_EX_VexImmW, x_mode }
413 #define XMVex { OP_XMM_Vex, 0 }
414 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
415 #define XMVexW { OP_XMM_VexW, 0 }
416 #define XMVexI4 { OP_REG_VexI4, x_mode }
417 #define PCLMUL { PCLMUL_Fixup, 0 }
418 #define VZERO { VZERO_Fixup, 0 }
419 #define VCMP { VCMP_Fixup, 0 }
420 #define VPCMP { VPCMP_Fixup, 0 }
422 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
423 #define EXxEVexS { OP_Rounding, evex_sae_mode }
425 #define XMask { OP_Mask, mask_mode }
426 #define MaskG { OP_G, mask_mode }
427 #define MaskE { OP_E, mask_mode }
428 #define MaskR { OP_R, mask_mode }
429 #define MaskVex { OP_VEX, mask_mode }
431 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
432 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
434 /* Used handle "rep" prefix for string instructions. */
435 #define Xbr { REP_Fixup, eSI_reg }
436 #define Xvr { REP_Fixup, eSI_reg }
437 #define Ybr { REP_Fixup, eDI_reg }
438 #define Yvr { REP_Fixup, eDI_reg }
439 #define Yzr { REP_Fixup, eDI_reg }
440 #define indirDXr { REP_Fixup, indir_dx_reg }
441 #define ALr { REP_Fixup, al_reg }
442 #define eAXr { REP_Fixup, eAX_reg }
444 /* Used handle HLE prefix for lockable instructions. */
445 #define Ebh1 { HLE_Fixup1, b_mode }
446 #define Evh1 { HLE_Fixup1, v_mode }
447 #define Ebh2 { HLE_Fixup2, b_mode }
448 #define Evh2 { HLE_Fixup2, v_mode }
449 #define Ebh3 { HLE_Fixup3, b_mode }
450 #define Evh3 { HLE_Fixup3, v_mode }
452 #define BND { BND_Fixup, 0 }
454 #define cond_jump_flag { NULL, cond_jump_mode }
455 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
457 /* bits in sizeflag */
458 #define SUFFIX_ALWAYS 4
466 /* byte operand with operand swapped */
468 /* byte operand, sign extend like 'T' suffix */
470 /* operand size depends on prefixes */
472 /* operand size depends on prefixes with operand swapped */
476 /* double word operand */
478 /* double word operand with operand swapped */
480 /* quad word operand */
482 /* quad word operand with operand swapped */
484 /* ten-byte operand */
486 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
487 broadcast enabled. */
489 /* Similar to x_mode, but with different EVEX mem shifts. */
491 /* Similar to x_mode, but with disabled broadcast. */
493 /* Similar to x_mode, but with operands swapped and disabled broadcast
496 /* 16-byte XMM operand */
498 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
499 memory operand (depending on vector length). Broadcast isn't
502 /* Same as xmmq_mode, but broadcast is allowed. */
503 evex_half_bcst_xmmq_mode,
504 /* XMM register or byte memory operand */
506 /* XMM register or word memory operand */
508 /* XMM register or double word memory operand */
510 /* XMM register or quad word memory operand */
512 /* XMM register or double/quad word memory operand, depending on
515 /* 16-byte XMM, word, double word or quad word operand. */
517 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
519 /* 32-byte YMM operand */
521 /* quad word, ymmword or zmmword memory operand. */
523 /* 32-byte YMM or 16-byte word operand */
525 /* d_mode in 32bit, q_mode in 64bit mode. */
527 /* pair of v_mode operands */
532 /* operand size depends on REX prefixes. */
534 /* registers like dq_mode, memory like w_mode. */
537 /* 4- or 6-byte pointer operand */
540 /* v_mode for stack-related opcodes. */
542 /* non-quad operand size depends on prefixes */
544 /* 16-byte operand */
546 /* registers like dq_mode, memory like b_mode. */
548 /* registers like dq_mode, memory like d_mode. */
550 /* normal vex mode */
552 /* 128bit vex mode */
554 /* 256bit vex mode */
556 /* operand size depends on the VEX.W bit. */
559 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
560 vex_vsib_d_w_dq_mode,
561 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
562 vex_vsib_q_w_dq_mode,
564 /* scalar, ignore vector length. */
566 /* like d_mode, ignore vector length. */
568 /* like d_swap_mode, ignore vector length. */
570 /* like q_mode, ignore vector length. */
572 /* like q_swap_mode, ignore vector length. */
574 /* like vex_mode, ignore vector length. */
576 /* like vex_w_dq_mode, ignore vector length. */
577 vex_scalar_w_dq_mode,
579 /* Static rounding. */
581 /* Supress all exceptions. */
584 /* Mask register operand. */
651 #define FLOAT NULL, { { NULL, FLOATCODE } }
653 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
654 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
655 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
656 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
657 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
658 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
659 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
660 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
661 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
662 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
663 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
664 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
665 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
781 MOD_VEX_0F12_PREFIX_0,
783 MOD_VEX_0F16_PREFIX_0,
799 MOD_VEX_0FD7_PREFIX_2,
800 MOD_VEX_0FE7_PREFIX_2,
801 MOD_VEX_0FF0_PREFIX_3,
802 MOD_VEX_0F381A_PREFIX_2,
803 MOD_VEX_0F382A_PREFIX_2,
804 MOD_VEX_0F382C_PREFIX_2,
805 MOD_VEX_0F382D_PREFIX_2,
806 MOD_VEX_0F382E_PREFIX_2,
807 MOD_VEX_0F382F_PREFIX_2,
808 MOD_VEX_0F385A_PREFIX_2,
809 MOD_VEX_0F388C_PREFIX_2,
810 MOD_VEX_0F388E_PREFIX_2,
812 MOD_EVEX_0F10_PREFIX_1,
813 MOD_EVEX_0F10_PREFIX_3,
814 MOD_EVEX_0F11_PREFIX_1,
815 MOD_EVEX_0F11_PREFIX_3,
816 MOD_EVEX_0F12_PREFIX_0,
817 MOD_EVEX_0F16_PREFIX_0,
818 MOD_EVEX_0F38C6_REG_1,
819 MOD_EVEX_0F38C6_REG_2,
820 MOD_EVEX_0F38C6_REG_5,
821 MOD_EVEX_0F38C6_REG_6,
822 MOD_EVEX_0F38C7_REG_1,
823 MOD_EVEX_0F38C7_REG_2,
824 MOD_EVEX_0F38C7_REG_5,
825 MOD_EVEX_0F38C7_REG_6
1015 PREFIX_VEX_0F71_REG_2,
1016 PREFIX_VEX_0F71_REG_4,
1017 PREFIX_VEX_0F71_REG_6,
1018 PREFIX_VEX_0F72_REG_2,
1019 PREFIX_VEX_0F72_REG_4,
1020 PREFIX_VEX_0F72_REG_6,
1021 PREFIX_VEX_0F73_REG_2,
1022 PREFIX_VEX_0F73_REG_3,
1023 PREFIX_VEX_0F73_REG_6,
1024 PREFIX_VEX_0F73_REG_7,
1195 PREFIX_VEX_0F38F3_REG_1,
1196 PREFIX_VEX_0F38F3_REG_2,
1197 PREFIX_VEX_0F38F3_REG_3,
1299 PREFIX_EVEX_0F72_REG_0,
1300 PREFIX_EVEX_0F72_REG_1,
1301 PREFIX_EVEX_0F72_REG_2,
1302 PREFIX_EVEX_0F72_REG_4,
1303 PREFIX_EVEX_0F72_REG_6,
1304 PREFIX_EVEX_0F73_REG_2,
1305 PREFIX_EVEX_0F73_REG_6,
1434 PREFIX_EVEX_0F38C6_REG_1,
1435 PREFIX_EVEX_0F38C6_REG_2,
1436 PREFIX_EVEX_0F38C6_REG_5,
1437 PREFIX_EVEX_0F38C6_REG_6,
1438 PREFIX_EVEX_0F38C7_REG_1,
1439 PREFIX_EVEX_0F38C7_REG_2,
1440 PREFIX_EVEX_0F38C7_REG_5,
1441 PREFIX_EVEX_0F38C7_REG_6,
1513 THREE_BYTE_0F38 = 0,
1541 VEX_LEN_0F10_P_1 = 0,
1545 VEX_LEN_0F12_P_0_M_0,
1546 VEX_LEN_0F12_P_0_M_1,
1549 VEX_LEN_0F16_P_0_M_0,
1550 VEX_LEN_0F16_P_0_M_1,
1596 VEX_LEN_0FAE_R_2_M_0,
1597 VEX_LEN_0FAE_R_3_M_0,
1606 VEX_LEN_0F381A_P_2_M_0,
1609 VEX_LEN_0F385A_P_2_M_0,
1616 VEX_LEN_0F38F3_R_1_P_0,
1617 VEX_LEN_0F38F3_R_2_P_0,
1618 VEX_LEN_0F38F3_R_3_P_0,
1662 VEX_LEN_0FXOP_08_CC,
1663 VEX_LEN_0FXOP_08_CD,
1664 VEX_LEN_0FXOP_08_CE,
1665 VEX_LEN_0FXOP_08_CF,
1666 VEX_LEN_0FXOP_08_EC,
1667 VEX_LEN_0FXOP_08_ED,
1668 VEX_LEN_0FXOP_08_EE,
1669 VEX_LEN_0FXOP_08_EF,
1670 VEX_LEN_0FXOP_09_80,
1704 VEX_W_0F41_P_0_LEN_1,
1705 VEX_W_0F42_P_0_LEN_1,
1706 VEX_W_0F44_P_0_LEN_0,
1707 VEX_W_0F45_P_0_LEN_1,
1708 VEX_W_0F46_P_0_LEN_1,
1709 VEX_W_0F47_P_0_LEN_1,
1710 VEX_W_0F4B_P_2_LEN_1,
1790 VEX_W_0F90_P_0_LEN_0,
1791 VEX_W_0F91_P_0_LEN_0,
1792 VEX_W_0F92_P_0_LEN_0,
1793 VEX_W_0F93_P_0_LEN_0,
1794 VEX_W_0F98_P_0_LEN_0,
1873 VEX_W_0F381A_P_2_M_0,
1885 VEX_W_0F382A_P_2_M_0,
1887 VEX_W_0F382C_P_2_M_0,
1888 VEX_W_0F382D_P_2_M_0,
1889 VEX_W_0F382E_P_2_M_0,
1890 VEX_W_0F382F_P_2_M_0,
1912 VEX_W_0F385A_P_2_M_0,
1940 VEX_W_0F3A30_P_2_LEN_0,
1941 VEX_W_0F3A32_P_2_LEN_0,
1961 EVEX_W_0F10_P_1_M_0,
1962 EVEX_W_0F10_P_1_M_1,
1964 EVEX_W_0F10_P_3_M_0,
1965 EVEX_W_0F10_P_3_M_1,
1967 EVEX_W_0F11_P_1_M_0,
1968 EVEX_W_0F11_P_1_M_1,
1970 EVEX_W_0F11_P_3_M_0,
1971 EVEX_W_0F11_P_3_M_1,
1972 EVEX_W_0F12_P_0_M_0,
1973 EVEX_W_0F12_P_0_M_1,
1983 EVEX_W_0F16_P_0_M_0,
1984 EVEX_W_0F16_P_0_M_1,
2045 EVEX_W_0F72_R_2_P_2,
2046 EVEX_W_0F72_R_6_P_2,
2047 EVEX_W_0F73_R_2_P_2,
2048 EVEX_W_0F73_R_6_P_2,
2121 EVEX_W_0F38C7_R_1_P_2,
2122 EVEX_W_0F38C7_R_2_P_2,
2123 EVEX_W_0F38C7_R_5_P_2,
2124 EVEX_W_0F38C7_R_6_P_2,
2148 typedef void (*op_rtn) (int bytemode, int sizeflag);
2159 /* Upper case letters in the instruction names here are macros.
2160 'A' => print 'b' if no register operands or suffix_always is true
2161 'B' => print 'b' if suffix_always is true
2162 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2164 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2165 suffix_always is true
2166 'E' => print 'e' if 32-bit form of jcxz
2167 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2168 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2169 'H' => print ",pt" or ",pn" branch hint
2170 'I' => honor following macro letter even in Intel mode (implemented only
2171 for some of the macro letters)
2173 'K' => print 'd' or 'q' if rex prefix is present.
2174 'L' => print 'l' if suffix_always is true
2175 'M' => print 'r' if intel_mnemonic is false.
2176 'N' => print 'n' if instruction has no wait "prefix"
2177 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2178 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2179 or suffix_always is true. print 'q' if rex prefix is present.
2180 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2182 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2183 'S' => print 'w', 'l' or 'q' if suffix_always is true
2184 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2185 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2186 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2187 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2188 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2189 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2190 suffix_always is true.
2191 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2192 '!' => change condition from true to false or from false to true.
2193 '%' => add 1 upper case letter to the macro.
2195 2 upper case letter macros:
2196 "XY" => print 'x' or 'y' if no register operands or suffix_always
2198 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2199 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2200 or suffix_always is true
2201 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2202 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2203 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2204 "LW" => print 'd', 'q' depending on the VEX.W bit
2206 Many of the above letters print nothing in Intel mode. See "putop"
2209 Braces '{' and '}', and vertical bars '|', indicate alternative
2210 mnemonic strings for AT&T and Intel. */
2212 static const struct dis386 dis386[] = {
2214 { "addB", { Ebh1, Gb } },
2215 { "addS", { Evh1, Gv } },
2216 { "addB", { Gb, EbS } },
2217 { "addS", { Gv, EvS } },
2218 { "addB", { AL, Ib } },
2219 { "addS", { eAX, Iv } },
2220 { X86_64_TABLE (X86_64_06) },
2221 { X86_64_TABLE (X86_64_07) },
2223 { "orB", { Ebh1, Gb } },
2224 { "orS", { Evh1, Gv } },
2225 { "orB", { Gb, EbS } },
2226 { "orS", { Gv, EvS } },
2227 { "orB", { AL, Ib } },
2228 { "orS", { eAX, Iv } },
2229 { X86_64_TABLE (X86_64_0D) },
2230 { Bad_Opcode }, /* 0x0f extended opcode escape */
2232 { "adcB", { Ebh1, Gb } },
2233 { "adcS", { Evh1, Gv } },
2234 { "adcB", { Gb, EbS } },
2235 { "adcS", { Gv, EvS } },
2236 { "adcB", { AL, Ib } },
2237 { "adcS", { eAX, Iv } },
2238 { X86_64_TABLE (X86_64_16) },
2239 { X86_64_TABLE (X86_64_17) },
2241 { "sbbB", { Ebh1, Gb } },
2242 { "sbbS", { Evh1, Gv } },
2243 { "sbbB", { Gb, EbS } },
2244 { "sbbS", { Gv, EvS } },
2245 { "sbbB", { AL, Ib } },
2246 { "sbbS", { eAX, Iv } },
2247 { X86_64_TABLE (X86_64_1E) },
2248 { X86_64_TABLE (X86_64_1F) },
2250 { "andB", { Ebh1, Gb } },
2251 { "andS", { Evh1, Gv } },
2252 { "andB", { Gb, EbS } },
2253 { "andS", { Gv, EvS } },
2254 { "andB", { AL, Ib } },
2255 { "andS", { eAX, Iv } },
2256 { Bad_Opcode }, /* SEG ES prefix */
2257 { X86_64_TABLE (X86_64_27) },
2259 { "subB", { Ebh1, Gb } },
2260 { "subS", { Evh1, Gv } },
2261 { "subB", { Gb, EbS } },
2262 { "subS", { Gv, EvS } },
2263 { "subB", { AL, Ib } },
2264 { "subS", { eAX, Iv } },
2265 { Bad_Opcode }, /* SEG CS prefix */
2266 { X86_64_TABLE (X86_64_2F) },
2268 { "xorB", { Ebh1, Gb } },
2269 { "xorS", { Evh1, Gv } },
2270 { "xorB", { Gb, EbS } },
2271 { "xorS", { Gv, EvS } },
2272 { "xorB", { AL, Ib } },
2273 { "xorS", { eAX, Iv } },
2274 { Bad_Opcode }, /* SEG SS prefix */
2275 { X86_64_TABLE (X86_64_37) },
2277 { "cmpB", { Eb, Gb } },
2278 { "cmpS", { Ev, Gv } },
2279 { "cmpB", { Gb, EbS } },
2280 { "cmpS", { Gv, EvS } },
2281 { "cmpB", { AL, Ib } },
2282 { "cmpS", { eAX, Iv } },
2283 { Bad_Opcode }, /* SEG DS prefix */
2284 { X86_64_TABLE (X86_64_3F) },
2286 { "inc{S|}", { RMeAX } },
2287 { "inc{S|}", { RMeCX } },
2288 { "inc{S|}", { RMeDX } },
2289 { "inc{S|}", { RMeBX } },
2290 { "inc{S|}", { RMeSP } },
2291 { "inc{S|}", { RMeBP } },
2292 { "inc{S|}", { RMeSI } },
2293 { "inc{S|}", { RMeDI } },
2295 { "dec{S|}", { RMeAX } },
2296 { "dec{S|}", { RMeCX } },
2297 { "dec{S|}", { RMeDX } },
2298 { "dec{S|}", { RMeBX } },
2299 { "dec{S|}", { RMeSP } },
2300 { "dec{S|}", { RMeBP } },
2301 { "dec{S|}", { RMeSI } },
2302 { "dec{S|}", { RMeDI } },
2304 { "pushV", { RMrAX } },
2305 { "pushV", { RMrCX } },
2306 { "pushV", { RMrDX } },
2307 { "pushV", { RMrBX } },
2308 { "pushV", { RMrSP } },
2309 { "pushV", { RMrBP } },
2310 { "pushV", { RMrSI } },
2311 { "pushV", { RMrDI } },
2313 { "popV", { RMrAX } },
2314 { "popV", { RMrCX } },
2315 { "popV", { RMrDX } },
2316 { "popV", { RMrBX } },
2317 { "popV", { RMrSP } },
2318 { "popV", { RMrBP } },
2319 { "popV", { RMrSI } },
2320 { "popV", { RMrDI } },
2322 { X86_64_TABLE (X86_64_60) },
2323 { X86_64_TABLE (X86_64_61) },
2324 { X86_64_TABLE (X86_64_62) },
2325 { X86_64_TABLE (X86_64_63) },
2326 { Bad_Opcode }, /* seg fs */
2327 { Bad_Opcode }, /* seg gs */
2328 { Bad_Opcode }, /* op size prefix */
2329 { Bad_Opcode }, /* adr size prefix */
2331 { "pushT", { sIv } },
2332 { "imulS", { Gv, Ev, Iv } },
2333 { "pushT", { sIbT } },
2334 { "imulS", { Gv, Ev, sIb } },
2335 { "ins{b|}", { Ybr, indirDX } },
2336 { X86_64_TABLE (X86_64_6D) },
2337 { "outs{b|}", { indirDXr, Xb } },
2338 { X86_64_TABLE (X86_64_6F) },
2340 { "joH", { Jb, BND, cond_jump_flag } },
2341 { "jnoH", { Jb, BND, cond_jump_flag } },
2342 { "jbH", { Jb, BND, cond_jump_flag } },
2343 { "jaeH", { Jb, BND, cond_jump_flag } },
2344 { "jeH", { Jb, BND, cond_jump_flag } },
2345 { "jneH", { Jb, BND, cond_jump_flag } },
2346 { "jbeH", { Jb, BND, cond_jump_flag } },
2347 { "jaH", { Jb, BND, cond_jump_flag } },
2349 { "jsH", { Jb, BND, cond_jump_flag } },
2350 { "jnsH", { Jb, BND, cond_jump_flag } },
2351 { "jpH", { Jb, BND, cond_jump_flag } },
2352 { "jnpH", { Jb, BND, cond_jump_flag } },
2353 { "jlH", { Jb, BND, cond_jump_flag } },
2354 { "jgeH", { Jb, BND, cond_jump_flag } },
2355 { "jleH", { Jb, BND, cond_jump_flag } },
2356 { "jgH", { Jb, BND, cond_jump_flag } },
2358 { REG_TABLE (REG_80) },
2359 { REG_TABLE (REG_81) },
2361 { REG_TABLE (REG_82) },
2362 { "testB", { Eb, Gb } },
2363 { "testS", { Ev, Gv } },
2364 { "xchgB", { Ebh2, Gb } },
2365 { "xchgS", { Evh2, Gv } },
2367 { "movB", { Ebh3, Gb } },
2368 { "movS", { Evh3, Gv } },
2369 { "movB", { Gb, EbS } },
2370 { "movS", { Gv, EvS } },
2371 { "movD", { Sv, Sw } },
2372 { MOD_TABLE (MOD_8D) },
2373 { "movD", { Sw, Sv } },
2374 { REG_TABLE (REG_8F) },
2376 { PREFIX_TABLE (PREFIX_90) },
2377 { "xchgS", { RMeCX, eAX } },
2378 { "xchgS", { RMeDX, eAX } },
2379 { "xchgS", { RMeBX, eAX } },
2380 { "xchgS", { RMeSP, eAX } },
2381 { "xchgS", { RMeBP, eAX } },
2382 { "xchgS", { RMeSI, eAX } },
2383 { "xchgS", { RMeDI, eAX } },
2385 { "cW{t|}R", { XX } },
2386 { "cR{t|}O", { XX } },
2387 { X86_64_TABLE (X86_64_9A) },
2388 { Bad_Opcode }, /* fwait */
2389 { "pushfT", { XX } },
2390 { "popfT", { XX } },
2394 { "mov%LB", { AL, Ob } },
2395 { "mov%LS", { eAX, Ov } },
2396 { "mov%LB", { Ob, AL } },
2397 { "mov%LS", { Ov, eAX } },
2398 { "movs{b|}", { Ybr, Xb } },
2399 { "movs{R|}", { Yvr, Xv } },
2400 { "cmps{b|}", { Xb, Yb } },
2401 { "cmps{R|}", { Xv, Yv } },
2403 { "testB", { AL, Ib } },
2404 { "testS", { eAX, Iv } },
2405 { "stosB", { Ybr, AL } },
2406 { "stosS", { Yvr, eAX } },
2407 { "lodsB", { ALr, Xb } },
2408 { "lodsS", { eAXr, Xv } },
2409 { "scasB", { AL, Yb } },
2410 { "scasS", { eAX, Yv } },
2412 { "movB", { RMAL, Ib } },
2413 { "movB", { RMCL, Ib } },
2414 { "movB", { RMDL, Ib } },
2415 { "movB", { RMBL, Ib } },
2416 { "movB", { RMAH, Ib } },
2417 { "movB", { RMCH, Ib } },
2418 { "movB", { RMDH, Ib } },
2419 { "movB", { RMBH, Ib } },
2421 { "mov%LV", { RMeAX, Iv64 } },
2422 { "mov%LV", { RMeCX, Iv64 } },
2423 { "mov%LV", { RMeDX, Iv64 } },
2424 { "mov%LV", { RMeBX, Iv64 } },
2425 { "mov%LV", { RMeSP, Iv64 } },
2426 { "mov%LV", { RMeBP, Iv64 } },
2427 { "mov%LV", { RMeSI, Iv64 } },
2428 { "mov%LV", { RMeDI, Iv64 } },
2430 { REG_TABLE (REG_C0) },
2431 { REG_TABLE (REG_C1) },
2432 { "retT", { Iw, BND } },
2433 { "retT", { BND } },
2434 { X86_64_TABLE (X86_64_C4) },
2435 { X86_64_TABLE (X86_64_C5) },
2436 { REG_TABLE (REG_C6) },
2437 { REG_TABLE (REG_C7) },
2439 { "enterT", { Iw, Ib } },
2440 { "leaveT", { XX } },
2441 { "Jret{|f}P", { Iw } },
2442 { "Jret{|f}P", { XX } },
2445 { X86_64_TABLE (X86_64_CE) },
2446 { "iretP", { XX } },
2448 { REG_TABLE (REG_D0) },
2449 { REG_TABLE (REG_D1) },
2450 { REG_TABLE (REG_D2) },
2451 { REG_TABLE (REG_D3) },
2452 { X86_64_TABLE (X86_64_D4) },
2453 { X86_64_TABLE (X86_64_D5) },
2455 { "xlat", { DSBX } },
2466 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
2467 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
2468 { "loopFH", { Jb, XX, loop_jcxz_flag } },
2469 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
2470 { "inB", { AL, Ib } },
2471 { "inG", { zAX, Ib } },
2472 { "outB", { Ib, AL } },
2473 { "outG", { Ib, zAX } },
2475 { "callT", { Jv, BND } },
2476 { "jmpT", { Jv, BND } },
2477 { X86_64_TABLE (X86_64_EA) },
2478 { "jmp", { Jb, BND } },
2479 { "inB", { AL, indirDX } },
2480 { "inG", { zAX, indirDX } },
2481 { "outB", { indirDX, AL } },
2482 { "outG", { indirDX, zAX } },
2484 { Bad_Opcode }, /* lock prefix */
2485 { "icebp", { XX } },
2486 { Bad_Opcode }, /* repne */
2487 { Bad_Opcode }, /* repz */
2490 { REG_TABLE (REG_F6) },
2491 { REG_TABLE (REG_F7) },
2499 { REG_TABLE (REG_FE) },
2500 { REG_TABLE (REG_FF) },
2503 static const struct dis386 dis386_twobyte[] = {
2505 { REG_TABLE (REG_0F00 ) },
2506 { REG_TABLE (REG_0F01 ) },
2507 { "larS", { Gv, Ew } },
2508 { "lslS", { Gv, Ew } },
2510 { "syscall", { XX } },
2512 { "sysretP", { XX } },
2515 { "wbinvd", { XX } },
2519 { REG_TABLE (REG_0F0D) },
2520 { "femms", { XX } },
2521 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
2523 { PREFIX_TABLE (PREFIX_0F10) },
2524 { PREFIX_TABLE (PREFIX_0F11) },
2525 { PREFIX_TABLE (PREFIX_0F12) },
2526 { MOD_TABLE (MOD_0F13) },
2527 { "unpcklpX", { XM, EXx } },
2528 { "unpckhpX", { XM, EXx } },
2529 { PREFIX_TABLE (PREFIX_0F16) },
2530 { MOD_TABLE (MOD_0F17) },
2532 { REG_TABLE (REG_0F18) },
2534 { PREFIX_TABLE (PREFIX_0F1A) },
2535 { PREFIX_TABLE (PREFIX_0F1B) },
2541 { MOD_TABLE (MOD_0F20) },
2542 { MOD_TABLE (MOD_0F21) },
2543 { MOD_TABLE (MOD_0F22) },
2544 { MOD_TABLE (MOD_0F23) },
2545 { MOD_TABLE (MOD_0F24) },
2547 { MOD_TABLE (MOD_0F26) },
2550 { "movapX", { XM, EXx } },
2551 { "movapX", { EXxS, XM } },
2552 { PREFIX_TABLE (PREFIX_0F2A) },
2553 { PREFIX_TABLE (PREFIX_0F2B) },
2554 { PREFIX_TABLE (PREFIX_0F2C) },
2555 { PREFIX_TABLE (PREFIX_0F2D) },
2556 { PREFIX_TABLE (PREFIX_0F2E) },
2557 { PREFIX_TABLE (PREFIX_0F2F) },
2559 { "wrmsr", { XX } },
2560 { "rdtsc", { XX } },
2561 { "rdmsr", { XX } },
2562 { "rdpmc", { XX } },
2563 { "sysenter", { XX } },
2564 { "sysexit", { XX } },
2566 { "getsec", { XX } },
2568 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2570 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2577 { "cmovoS", { Gv, Ev } },
2578 { "cmovnoS", { Gv, Ev } },
2579 { "cmovbS", { Gv, Ev } },
2580 { "cmovaeS", { Gv, Ev } },
2581 { "cmoveS", { Gv, Ev } },
2582 { "cmovneS", { Gv, Ev } },
2583 { "cmovbeS", { Gv, Ev } },
2584 { "cmovaS", { Gv, Ev } },
2586 { "cmovsS", { Gv, Ev } },
2587 { "cmovnsS", { Gv, Ev } },
2588 { "cmovpS", { Gv, Ev } },
2589 { "cmovnpS", { Gv, Ev } },
2590 { "cmovlS", { Gv, Ev } },
2591 { "cmovgeS", { Gv, Ev } },
2592 { "cmovleS", { Gv, Ev } },
2593 { "cmovgS", { Gv, Ev } },
2595 { MOD_TABLE (MOD_0F51) },
2596 { PREFIX_TABLE (PREFIX_0F51) },
2597 { PREFIX_TABLE (PREFIX_0F52) },
2598 { PREFIX_TABLE (PREFIX_0F53) },
2599 { "andpX", { XM, EXx } },
2600 { "andnpX", { XM, EXx } },
2601 { "orpX", { XM, EXx } },
2602 { "xorpX", { XM, EXx } },
2604 { PREFIX_TABLE (PREFIX_0F58) },
2605 { PREFIX_TABLE (PREFIX_0F59) },
2606 { PREFIX_TABLE (PREFIX_0F5A) },
2607 { PREFIX_TABLE (PREFIX_0F5B) },
2608 { PREFIX_TABLE (PREFIX_0F5C) },
2609 { PREFIX_TABLE (PREFIX_0F5D) },
2610 { PREFIX_TABLE (PREFIX_0F5E) },
2611 { PREFIX_TABLE (PREFIX_0F5F) },
2613 { PREFIX_TABLE (PREFIX_0F60) },
2614 { PREFIX_TABLE (PREFIX_0F61) },
2615 { PREFIX_TABLE (PREFIX_0F62) },
2616 { "packsswb", { MX, EM } },
2617 { "pcmpgtb", { MX, EM } },
2618 { "pcmpgtw", { MX, EM } },
2619 { "pcmpgtd", { MX, EM } },
2620 { "packuswb", { MX, EM } },
2622 { "punpckhbw", { MX, EM } },
2623 { "punpckhwd", { MX, EM } },
2624 { "punpckhdq", { MX, EM } },
2625 { "packssdw", { MX, EM } },
2626 { PREFIX_TABLE (PREFIX_0F6C) },
2627 { PREFIX_TABLE (PREFIX_0F6D) },
2628 { "movK", { MX, Edq } },
2629 { PREFIX_TABLE (PREFIX_0F6F) },
2631 { PREFIX_TABLE (PREFIX_0F70) },
2632 { REG_TABLE (REG_0F71) },
2633 { REG_TABLE (REG_0F72) },
2634 { REG_TABLE (REG_0F73) },
2635 { "pcmpeqb", { MX, EM } },
2636 { "pcmpeqw", { MX, EM } },
2637 { "pcmpeqd", { MX, EM } },
2640 { PREFIX_TABLE (PREFIX_0F78) },
2641 { PREFIX_TABLE (PREFIX_0F79) },
2642 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2644 { PREFIX_TABLE (PREFIX_0F7C) },
2645 { PREFIX_TABLE (PREFIX_0F7D) },
2646 { PREFIX_TABLE (PREFIX_0F7E) },
2647 { PREFIX_TABLE (PREFIX_0F7F) },
2649 { "joH", { Jv, BND, cond_jump_flag } },
2650 { "jnoH", { Jv, BND, cond_jump_flag } },
2651 { "jbH", { Jv, BND, cond_jump_flag } },
2652 { "jaeH", { Jv, BND, cond_jump_flag } },
2653 { "jeH", { Jv, BND, cond_jump_flag } },
2654 { "jneH", { Jv, BND, cond_jump_flag } },
2655 { "jbeH", { Jv, BND, cond_jump_flag } },
2656 { "jaH", { Jv, BND, cond_jump_flag } },
2658 { "jsH", { Jv, BND, cond_jump_flag } },
2659 { "jnsH", { Jv, BND, cond_jump_flag } },
2660 { "jpH", { Jv, BND, cond_jump_flag } },
2661 { "jnpH", { Jv, BND, cond_jump_flag } },
2662 { "jlH", { Jv, BND, cond_jump_flag } },
2663 { "jgeH", { Jv, BND, cond_jump_flag } },
2664 { "jleH", { Jv, BND, cond_jump_flag } },
2665 { "jgH", { Jv, BND, cond_jump_flag } },
2668 { "setno", { Eb } },
2670 { "setae", { Eb } },
2672 { "setne", { Eb } },
2673 { "setbe", { Eb } },
2677 { "setns", { Eb } },
2679 { "setnp", { Eb } },
2681 { "setge", { Eb } },
2682 { "setle", { Eb } },
2685 { "pushT", { fs } },
2687 { "cpuid", { XX } },
2688 { "btS", { Ev, Gv } },
2689 { "shldS", { Ev, Gv, Ib } },
2690 { "shldS", { Ev, Gv, CL } },
2691 { REG_TABLE (REG_0FA6) },
2692 { REG_TABLE (REG_0FA7) },
2694 { "pushT", { gs } },
2697 { "btsS", { Evh1, Gv } },
2698 { "shrdS", { Ev, Gv, Ib } },
2699 { "shrdS", { Ev, Gv, CL } },
2700 { REG_TABLE (REG_0FAE) },
2701 { "imulS", { Gv, Ev } },
2703 { "cmpxchgB", { Ebh1, Gb } },
2704 { "cmpxchgS", { Evh1, Gv } },
2705 { MOD_TABLE (MOD_0FB2) },
2706 { "btrS", { Evh1, Gv } },
2707 { MOD_TABLE (MOD_0FB4) },
2708 { MOD_TABLE (MOD_0FB5) },
2709 { "movz{bR|x}", { Gv, Eb } },
2710 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
2712 { PREFIX_TABLE (PREFIX_0FB8) },
2714 { REG_TABLE (REG_0FBA) },
2715 { "btcS", { Evh1, Gv } },
2716 { PREFIX_TABLE (PREFIX_0FBC) },
2717 { PREFIX_TABLE (PREFIX_0FBD) },
2718 { "movs{bR|x}", { Gv, Eb } },
2719 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
2721 { "xaddB", { Ebh1, Gb } },
2722 { "xaddS", { Evh1, Gv } },
2723 { PREFIX_TABLE (PREFIX_0FC2) },
2724 { PREFIX_TABLE (PREFIX_0FC3) },
2725 { "pinsrw", { MX, Edqw, Ib } },
2726 { "pextrw", { Gdq, MS, Ib } },
2727 { "shufpX", { XM, EXx, Ib } },
2728 { REG_TABLE (REG_0FC7) },
2730 { "bswap", { RMeAX } },
2731 { "bswap", { RMeCX } },
2732 { "bswap", { RMeDX } },
2733 { "bswap", { RMeBX } },
2734 { "bswap", { RMeSP } },
2735 { "bswap", { RMeBP } },
2736 { "bswap", { RMeSI } },
2737 { "bswap", { RMeDI } },
2739 { PREFIX_TABLE (PREFIX_0FD0) },
2740 { "psrlw", { MX, EM } },
2741 { "psrld", { MX, EM } },
2742 { "psrlq", { MX, EM } },
2743 { "paddq", { MX, EM } },
2744 { "pmullw", { MX, EM } },
2745 { PREFIX_TABLE (PREFIX_0FD6) },
2746 { MOD_TABLE (MOD_0FD7) },
2748 { "psubusb", { MX, EM } },
2749 { "psubusw", { MX, EM } },
2750 { "pminub", { MX, EM } },
2751 { "pand", { MX, EM } },
2752 { "paddusb", { MX, EM } },
2753 { "paddusw", { MX, EM } },
2754 { "pmaxub", { MX, EM } },
2755 { "pandn", { MX, EM } },
2757 { "pavgb", { MX, EM } },
2758 { "psraw", { MX, EM } },
2759 { "psrad", { MX, EM } },
2760 { "pavgw", { MX, EM } },
2761 { "pmulhuw", { MX, EM } },
2762 { "pmulhw", { MX, EM } },
2763 { PREFIX_TABLE (PREFIX_0FE6) },
2764 { PREFIX_TABLE (PREFIX_0FE7) },
2766 { "psubsb", { MX, EM } },
2767 { "psubsw", { MX, EM } },
2768 { "pminsw", { MX, EM } },
2769 { "por", { MX, EM } },
2770 { "paddsb", { MX, EM } },
2771 { "paddsw", { MX, EM } },
2772 { "pmaxsw", { MX, EM } },
2773 { "pxor", { MX, EM } },
2775 { PREFIX_TABLE (PREFIX_0FF0) },
2776 { "psllw", { MX, EM } },
2777 { "pslld", { MX, EM } },
2778 { "psllq", { MX, EM } },
2779 { "pmuludq", { MX, EM } },
2780 { "pmaddwd", { MX, EM } },
2781 { "psadbw", { MX, EM } },
2782 { PREFIX_TABLE (PREFIX_0FF7) },
2784 { "psubb", { MX, EM } },
2785 { "psubw", { MX, EM } },
2786 { "psubd", { MX, EM } },
2787 { "psubq", { MX, EM } },
2788 { "paddb", { MX, EM } },
2789 { "paddw", { MX, EM } },
2790 { "paddd", { MX, EM } },
2794 static const unsigned char onebyte_has_modrm[256] = {
2795 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2796 /* ------------------------------- */
2797 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2798 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2799 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2800 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2801 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2802 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2803 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2804 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2805 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2806 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2807 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2808 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2809 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2810 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2811 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2812 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2813 /* ------------------------------- */
2814 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2817 static const unsigned char twobyte_has_modrm[256] = {
2818 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2819 /* ------------------------------- */
2820 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2821 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2822 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2823 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2824 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2825 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2826 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2827 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2828 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2829 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2830 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2831 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2832 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2833 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2834 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2835 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
2836 /* ------------------------------- */
2837 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2840 static char obuf[100];
2842 static char *mnemonicendp;
2843 static char scratchbuf[100];
2844 static unsigned char *start_codep;
2845 static unsigned char *insn_codep;
2846 static unsigned char *codep;
2847 static int last_lock_prefix;
2848 static int last_repz_prefix;
2849 static int last_repnz_prefix;
2850 static int last_data_prefix;
2851 static int last_addr_prefix;
2852 static int last_rex_prefix;
2853 static int last_seg_prefix;
2854 #define MAX_CODE_LENGTH 15
2855 /* We can up to 14 prefixes since the maximum instruction length is
2857 static int all_prefixes[MAX_CODE_LENGTH - 1];
2858 static disassemble_info *the_info;
2866 static unsigned char need_modrm;
2876 int register_specifier;
2883 int mask_register_specifier;
2889 static unsigned char need_vex;
2890 static unsigned char need_vex_reg;
2891 static unsigned char vex_w_done;
2899 /* If we are accessing mod/rm/reg without need_modrm set, then the
2900 values are stale. Hitting this abort likely indicates that you
2901 need to update onebyte_has_modrm or twobyte_has_modrm. */
2902 #define MODRM_CHECK if (!need_modrm) abort ()
2904 static const char **names64;
2905 static const char **names32;
2906 static const char **names16;
2907 static const char **names8;
2908 static const char **names8rex;
2909 static const char **names_seg;
2910 static const char *index64;
2911 static const char *index32;
2912 static const char **index16;
2913 static const char **names_bnd;
2915 static const char *intel_names64[] = {
2916 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2917 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2919 static const char *intel_names32[] = {
2920 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2921 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2923 static const char *intel_names16[] = {
2924 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2925 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2927 static const char *intel_names8[] = {
2928 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2930 static const char *intel_names8rex[] = {
2931 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2932 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2934 static const char *intel_names_seg[] = {
2935 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2937 static const char *intel_index64 = "riz";
2938 static const char *intel_index32 = "eiz";
2939 static const char *intel_index16[] = {
2940 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2943 static const char *att_names64[] = {
2944 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2945 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2947 static const char *att_names32[] = {
2948 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2949 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2951 static const char *att_names16[] = {
2952 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2953 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2955 static const char *att_names8[] = {
2956 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2958 static const char *att_names8rex[] = {
2959 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2960 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2962 static const char *att_names_seg[] = {
2963 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2965 static const char *att_index64 = "%riz";
2966 static const char *att_index32 = "%eiz";
2967 static const char *att_index16[] = {
2968 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2971 static const char **names_mm;
2972 static const char *intel_names_mm[] = {
2973 "mm0", "mm1", "mm2", "mm3",
2974 "mm4", "mm5", "mm6", "mm7"
2976 static const char *att_names_mm[] = {
2977 "%mm0", "%mm1", "%mm2", "%mm3",
2978 "%mm4", "%mm5", "%mm6", "%mm7"
2981 static const char *intel_names_bnd[] = {
2982 "bnd0", "bnd1", "bnd2", "bnd3"
2985 static const char *att_names_bnd[] = {
2986 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2989 static const char **names_xmm;
2990 static const char *intel_names_xmm[] = {
2991 "xmm0", "xmm1", "xmm2", "xmm3",
2992 "xmm4", "xmm5", "xmm6", "xmm7",
2993 "xmm8", "xmm9", "xmm10", "xmm11",
2994 "xmm12", "xmm13", "xmm14", "xmm15",
2995 "xmm16", "xmm17", "xmm18", "xmm19",
2996 "xmm20", "xmm21", "xmm22", "xmm23",
2997 "xmm24", "xmm25", "xmm26", "xmm27",
2998 "xmm28", "xmm29", "xmm30", "xmm31"
3000 static const char *att_names_xmm[] = {
3001 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3002 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3003 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3004 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3005 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3006 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3007 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3008 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3011 static const char **names_ymm;
3012 static const char *intel_names_ymm[] = {
3013 "ymm0", "ymm1", "ymm2", "ymm3",
3014 "ymm4", "ymm5", "ymm6", "ymm7",
3015 "ymm8", "ymm9", "ymm10", "ymm11",
3016 "ymm12", "ymm13", "ymm14", "ymm15",
3017 "ymm16", "ymm17", "ymm18", "ymm19",
3018 "ymm20", "ymm21", "ymm22", "ymm23",
3019 "ymm24", "ymm25", "ymm26", "ymm27",
3020 "ymm28", "ymm29", "ymm30", "ymm31"
3022 static const char *att_names_ymm[] = {
3023 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3024 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3025 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3026 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3027 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3028 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3029 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3030 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3033 static const char **names_zmm;
3034 static const char *intel_names_zmm[] = {
3035 "zmm0", "zmm1", "zmm2", "zmm3",
3036 "zmm4", "zmm5", "zmm6", "zmm7",
3037 "zmm8", "zmm9", "zmm10", "zmm11",
3038 "zmm12", "zmm13", "zmm14", "zmm15",
3039 "zmm16", "zmm17", "zmm18", "zmm19",
3040 "zmm20", "zmm21", "zmm22", "zmm23",
3041 "zmm24", "zmm25", "zmm26", "zmm27",
3042 "zmm28", "zmm29", "zmm30", "zmm31"
3044 static const char *att_names_zmm[] = {
3045 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3046 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3047 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3048 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3049 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3050 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3051 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3052 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3055 static const char **names_mask;
3056 static const char *intel_names_mask[] = {
3057 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3059 static const char *att_names_mask[] = {
3060 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3063 static const char *names_rounding[] =
3071 static const struct dis386 reg_table[][8] = {
3074 { "addA", { Ebh1, Ib } },
3075 { "orA", { Ebh1, Ib } },
3076 { "adcA", { Ebh1, Ib } },
3077 { "sbbA", { Ebh1, Ib } },
3078 { "andA", { Ebh1, Ib } },
3079 { "subA", { Ebh1, Ib } },
3080 { "xorA", { Ebh1, Ib } },
3081 { "cmpA", { Eb, Ib } },
3085 { "addQ", { Evh1, Iv } },
3086 { "orQ", { Evh1, Iv } },
3087 { "adcQ", { Evh1, Iv } },
3088 { "sbbQ", { Evh1, Iv } },
3089 { "andQ", { Evh1, Iv } },
3090 { "subQ", { Evh1, Iv } },
3091 { "xorQ", { Evh1, Iv } },
3092 { "cmpQ", { Ev, Iv } },
3096 { "addQ", { Evh1, sIb } },
3097 { "orQ", { Evh1, sIb } },
3098 { "adcQ", { Evh1, sIb } },
3099 { "sbbQ", { Evh1, sIb } },
3100 { "andQ", { Evh1, sIb } },
3101 { "subQ", { Evh1, sIb } },
3102 { "xorQ", { Evh1, sIb } },
3103 { "cmpQ", { Ev, sIb } },
3107 { "popU", { stackEv } },
3108 { XOP_8F_TABLE (XOP_09) },
3112 { XOP_8F_TABLE (XOP_09) },
3116 { "rolA", { Eb, Ib } },
3117 { "rorA", { Eb, Ib } },
3118 { "rclA", { Eb, Ib } },
3119 { "rcrA", { Eb, Ib } },
3120 { "shlA", { Eb, Ib } },
3121 { "shrA", { Eb, Ib } },
3123 { "sarA", { Eb, Ib } },
3127 { "rolQ", { Ev, Ib } },
3128 { "rorQ", { Ev, Ib } },
3129 { "rclQ", { Ev, Ib } },
3130 { "rcrQ", { Ev, Ib } },
3131 { "shlQ", { Ev, Ib } },
3132 { "shrQ", { Ev, Ib } },
3134 { "sarQ", { Ev, Ib } },
3138 { "movA", { Ebh3, Ib } },
3145 { MOD_TABLE (MOD_C6_REG_7) },
3149 { "movQ", { Evh3, Iv } },
3156 { MOD_TABLE (MOD_C7_REG_7) },
3160 { "rolA", { Eb, I1 } },
3161 { "rorA", { Eb, I1 } },
3162 { "rclA", { Eb, I1 } },
3163 { "rcrA", { Eb, I1 } },
3164 { "shlA", { Eb, I1 } },
3165 { "shrA", { Eb, I1 } },
3167 { "sarA", { Eb, I1 } },
3171 { "rolQ", { Ev, I1 } },
3172 { "rorQ", { Ev, I1 } },
3173 { "rclQ", { Ev, I1 } },
3174 { "rcrQ", { Ev, I1 } },
3175 { "shlQ", { Ev, I1 } },
3176 { "shrQ", { Ev, I1 } },
3178 { "sarQ", { Ev, I1 } },
3182 { "rolA", { Eb, CL } },
3183 { "rorA", { Eb, CL } },
3184 { "rclA", { Eb, CL } },
3185 { "rcrA", { Eb, CL } },
3186 { "shlA", { Eb, CL } },
3187 { "shrA", { Eb, CL } },
3189 { "sarA", { Eb, CL } },
3193 { "rolQ", { Ev, CL } },
3194 { "rorQ", { Ev, CL } },
3195 { "rclQ", { Ev, CL } },
3196 { "rcrQ", { Ev, CL } },
3197 { "shlQ", { Ev, CL } },
3198 { "shrQ", { Ev, CL } },
3200 { "sarQ", { Ev, CL } },
3204 { "testA", { Eb, Ib } },
3206 { "notA", { Ebh1 } },
3207 { "negA", { Ebh1 } },
3208 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
3209 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
3210 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
3211 { "idivA", { Eb } }, /* and idiv for consistency. */
3215 { "testQ", { Ev, Iv } },
3217 { "notQ", { Evh1 } },
3218 { "negQ", { Evh1 } },
3219 { "mulQ", { Ev } }, /* Don't print the implicit register. */
3220 { "imulQ", { Ev } },
3222 { "idivQ", { Ev } },
3226 { "incA", { Ebh1 } },
3227 { "decA", { Ebh1 } },
3231 { "incQ", { Evh1 } },
3232 { "decQ", { Evh1 } },
3233 { "call{T|}", { indirEv, BND } },
3234 { MOD_TABLE (MOD_FF_REG_3) },
3235 { "jmp{T|}", { indirEv, BND } },
3236 { MOD_TABLE (MOD_FF_REG_5) },
3237 { "pushU", { stackEv } },
3242 { "sldtD", { Sv } },
3253 { MOD_TABLE (MOD_0F01_REG_0) },
3254 { MOD_TABLE (MOD_0F01_REG_1) },
3255 { MOD_TABLE (MOD_0F01_REG_2) },
3256 { MOD_TABLE (MOD_0F01_REG_3) },
3257 { "smswD", { Sv } },
3260 { MOD_TABLE (MOD_0F01_REG_7) },
3264 { "prefetch", { Mb } },
3265 { "prefetchw", { Mb } },
3266 { "prefetchwt1", { Mb } },
3267 { "prefetch", { Mb } },
3268 { "prefetch", { Mb } },
3269 { "prefetch", { Mb } },
3270 { "prefetch", { Mb } },
3271 { "prefetch", { Mb } },
3275 { MOD_TABLE (MOD_0F18_REG_0) },
3276 { MOD_TABLE (MOD_0F18_REG_1) },
3277 { MOD_TABLE (MOD_0F18_REG_2) },
3278 { MOD_TABLE (MOD_0F18_REG_3) },
3279 { MOD_TABLE (MOD_0F18_REG_4) },
3280 { MOD_TABLE (MOD_0F18_REG_5) },
3281 { MOD_TABLE (MOD_0F18_REG_6) },
3282 { MOD_TABLE (MOD_0F18_REG_7) },
3288 { MOD_TABLE (MOD_0F71_REG_2) },
3290 { MOD_TABLE (MOD_0F71_REG_4) },
3292 { MOD_TABLE (MOD_0F71_REG_6) },
3298 { MOD_TABLE (MOD_0F72_REG_2) },
3300 { MOD_TABLE (MOD_0F72_REG_4) },
3302 { MOD_TABLE (MOD_0F72_REG_6) },
3308 { MOD_TABLE (MOD_0F73_REG_2) },
3309 { MOD_TABLE (MOD_0F73_REG_3) },
3312 { MOD_TABLE (MOD_0F73_REG_6) },
3313 { MOD_TABLE (MOD_0F73_REG_7) },
3317 { "montmul", { { OP_0f07, 0 } } },
3318 { "xsha1", { { OP_0f07, 0 } } },
3319 { "xsha256", { { OP_0f07, 0 } } },
3323 { "xstore-rng", { { OP_0f07, 0 } } },
3324 { "xcrypt-ecb", { { OP_0f07, 0 } } },
3325 { "xcrypt-cbc", { { OP_0f07, 0 } } },
3326 { "xcrypt-ctr", { { OP_0f07, 0 } } },
3327 { "xcrypt-cfb", { { OP_0f07, 0 } } },
3328 { "xcrypt-ofb", { { OP_0f07, 0 } } },
3332 { MOD_TABLE (MOD_0FAE_REG_0) },
3333 { MOD_TABLE (MOD_0FAE_REG_1) },
3334 { MOD_TABLE (MOD_0FAE_REG_2) },
3335 { MOD_TABLE (MOD_0FAE_REG_3) },
3336 { MOD_TABLE (MOD_0FAE_REG_4) },
3337 { MOD_TABLE (MOD_0FAE_REG_5) },
3338 { MOD_TABLE (MOD_0FAE_REG_6) },
3339 { MOD_TABLE (MOD_0FAE_REG_7) },
3347 { "btQ", { Ev, Ib } },
3348 { "btsQ", { Evh1, Ib } },
3349 { "btrQ", { Evh1, Ib } },
3350 { "btcQ", { Evh1, Ib } },
3355 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
3360 { MOD_TABLE (MOD_0FC7_REG_6) },
3361 { MOD_TABLE (MOD_0FC7_REG_7) },
3367 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3369 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3371 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3377 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3379 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3381 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3387 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3388 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3391 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3392 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3398 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3399 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3401 /* REG_VEX_0F38F3 */
3404 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3405 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3406 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3410 { "llwpcb", { { OP_LWPCB_E, 0 } } },
3411 { "slwpcb", { { OP_LWPCB_E, 0 } } },
3415 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
3416 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
3418 /* REG_XOP_TBM_01 */
3421 { "blcfill", { { OP_LWP_E, 0 }, Ev } },
3422 { "blsfill", { { OP_LWP_E, 0 }, Ev } },
3423 { "blcs", { { OP_LWP_E, 0 }, Ev } },
3424 { "tzmsk", { { OP_LWP_E, 0 }, Ev } },
3425 { "blcic", { { OP_LWP_E, 0 }, Ev } },
3426 { "blsic", { { OP_LWP_E, 0 }, Ev } },
3427 { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
3429 /* REG_XOP_TBM_02 */
3432 { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
3437 { "blci", { { OP_LWP_E, 0 }, Ev } },
3439 #define NEED_REG_TABLE
3440 #include "i386-dis-evex.h"
3441 #undef NEED_REG_TABLE
3444 static const struct dis386 prefix_table[][4] = {
3447 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3448 { "pause", { XX } },
3449 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3454 { "movups", { XM, EXx } },
3455 { "movss", { XM, EXd } },
3456 { "movupd", { XM, EXx } },
3457 { "movsd", { XM, EXq } },
3462 { "movups", { EXxS, XM } },
3463 { "movss", { EXdS, XM } },
3464 { "movupd", { EXxS, XM } },
3465 { "movsd", { EXqS, XM } },
3470 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3471 { "movsldup", { XM, EXx } },
3472 { "movlpd", { XM, EXq } },
3473 { "movddup", { XM, EXq } },
3478 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3479 { "movshdup", { XM, EXx } },
3480 { "movhpd", { XM, EXq } },
3485 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3486 { "bndcl", { Gbnd, Ev_bnd } },
3487 { "bndmov", { Gbnd, Ebnd } },
3488 { "bndcu", { Gbnd, Ev_bnd } },
3493 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3494 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3495 { "bndmov", { Ebnd, Gbnd } },
3496 { "bndcn", { Gbnd, Ev_bnd } },
3501 { "cvtpi2ps", { XM, EMCq } },
3502 { "cvtsi2ss%LQ", { XM, Ev } },
3503 { "cvtpi2pd", { XM, EMCq } },
3504 { "cvtsi2sd%LQ", { XM, Ev } },
3509 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3510 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3511 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3512 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3517 { "cvttps2pi", { MXC, EXq } },
3518 { "cvttss2siY", { Gv, EXd } },
3519 { "cvttpd2pi", { MXC, EXx } },
3520 { "cvttsd2siY", { Gv, EXq } },
3525 { "cvtps2pi", { MXC, EXq } },
3526 { "cvtss2siY", { Gv, EXd } },
3527 { "cvtpd2pi", { MXC, EXx } },
3528 { "cvtsd2siY", { Gv, EXq } },
3533 { "ucomiss",{ XM, EXd } },
3535 { "ucomisd",{ XM, EXq } },
3540 { "comiss", { XM, EXd } },
3542 { "comisd", { XM, EXq } },
3547 { "sqrtps", { XM, EXx } },
3548 { "sqrtss", { XM, EXd } },
3549 { "sqrtpd", { XM, EXx } },
3550 { "sqrtsd", { XM, EXq } },
3555 { "rsqrtps",{ XM, EXx } },
3556 { "rsqrtss",{ XM, EXd } },
3561 { "rcpps", { XM, EXx } },
3562 { "rcpss", { XM, EXd } },
3567 { "addps", { XM, EXx } },
3568 { "addss", { XM, EXd } },
3569 { "addpd", { XM, EXx } },
3570 { "addsd", { XM, EXq } },
3575 { "mulps", { XM, EXx } },
3576 { "mulss", { XM, EXd } },
3577 { "mulpd", { XM, EXx } },
3578 { "mulsd", { XM, EXq } },
3583 { "cvtps2pd", { XM, EXq } },
3584 { "cvtss2sd", { XM, EXd } },
3585 { "cvtpd2ps", { XM, EXx } },
3586 { "cvtsd2ss", { XM, EXq } },
3591 { "cvtdq2ps", { XM, EXx } },
3592 { "cvttps2dq", { XM, EXx } },
3593 { "cvtps2dq", { XM, EXx } },
3598 { "subps", { XM, EXx } },
3599 { "subss", { XM, EXd } },
3600 { "subpd", { XM, EXx } },
3601 { "subsd", { XM, EXq } },
3606 { "minps", { XM, EXx } },
3607 { "minss", { XM, EXd } },
3608 { "minpd", { XM, EXx } },
3609 { "minsd", { XM, EXq } },
3614 { "divps", { XM, EXx } },
3615 { "divss", { XM, EXd } },
3616 { "divpd", { XM, EXx } },
3617 { "divsd", { XM, EXq } },
3622 { "maxps", { XM, EXx } },
3623 { "maxss", { XM, EXd } },
3624 { "maxpd", { XM, EXx } },
3625 { "maxsd", { XM, EXq } },
3630 { "punpcklbw",{ MX, EMd } },
3632 { "punpcklbw",{ MX, EMx } },
3637 { "punpcklwd",{ MX, EMd } },
3639 { "punpcklwd",{ MX, EMx } },
3644 { "punpckldq",{ MX, EMd } },
3646 { "punpckldq",{ MX, EMx } },
3653 { "punpcklqdq", { XM, EXx } },
3660 { "punpckhqdq", { XM, EXx } },
3665 { "movq", { MX, EM } },
3666 { "movdqu", { XM, EXx } },
3667 { "movdqa", { XM, EXx } },
3672 { "pshufw", { MX, EM, Ib } },
3673 { "pshufhw",{ XM, EXx, Ib } },
3674 { "pshufd", { XM, EXx, Ib } },
3675 { "pshuflw",{ XM, EXx, Ib } },
3678 /* PREFIX_0F73_REG_3 */
3682 { "psrldq", { XS, Ib } },
3685 /* PREFIX_0F73_REG_7 */
3689 { "pslldq", { XS, Ib } },
3694 {"vmread", { Em, Gm } },
3696 {"extrq", { XS, Ib, Ib } },
3697 {"insertq", { XM, XS, Ib, Ib } },
3702 {"vmwrite", { Gm, Em } },
3704 {"extrq", { XM, XS } },
3705 {"insertq", { XM, XS } },
3712 { "haddpd", { XM, EXx } },
3713 { "haddps", { XM, EXx } },
3720 { "hsubpd", { XM, EXx } },
3721 { "hsubps", { XM, EXx } },
3726 { "movK", { Edq, MX } },
3727 { "movq", { XM, EXq } },
3728 { "movK", { Edq, XM } },
3733 { "movq", { EMS, MX } },
3734 { "movdqu", { EXxS, XM } },
3735 { "movdqa", { EXxS, XM } },
3738 /* PREFIX_0FAE_REG_0 */
3741 { "rdfsbase", { Ev } },
3744 /* PREFIX_0FAE_REG_1 */
3747 { "rdgsbase", { Ev } },
3750 /* PREFIX_0FAE_REG_2 */
3753 { "wrfsbase", { Ev } },
3756 /* PREFIX_0FAE_REG_3 */
3759 { "wrgsbase", { Ev } },
3765 { "popcntS", { Gv, Ev } },
3770 { "bsfS", { Gv, Ev } },
3771 { "tzcntS", { Gv, Ev } },
3772 { "bsfS", { Gv, Ev } },
3777 { "bsrS", { Gv, Ev } },
3778 { "lzcntS", { Gv, Ev } },
3779 { "bsrS", { Gv, Ev } },
3784 { "cmpps", { XM, EXx, CMP } },
3785 { "cmpss", { XM, EXd, CMP } },
3786 { "cmppd", { XM, EXx, CMP } },
3787 { "cmpsd", { XM, EXq, CMP } },
3792 { "movntiS", { Ma, Gv } },
3795 /* PREFIX_0FC7_REG_6 */
3797 { "vmptrld",{ Mq } },
3798 { "vmxon", { Mq } },
3799 { "vmclear",{ Mq } },
3806 { "addsubpd", { XM, EXx } },
3807 { "addsubps", { XM, EXx } },
3813 { "movq2dq",{ XM, MS } },
3814 { "movq", { EXqS, XM } },
3815 { "movdq2q",{ MX, XS } },
3821 { "cvtdq2pd", { XM, EXq } },
3822 { "cvttpd2dq", { XM, EXx } },
3823 { "cvtpd2dq", { XM, EXx } },
3828 { "movntq", { Mq, MX } },
3830 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3838 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3843 { "maskmovq", { MX, MS } },
3845 { "maskmovdqu", { XM, XS } },
3852 { "pblendvb", { XM, EXx, XMM0 } },
3859 { "blendvps", { XM, EXx, XMM0 } },
3866 { "blendvpd", { XM, EXx, XMM0 } },
3873 { "ptest", { XM, EXx } },
3880 { "pmovsxbw", { XM, EXq } },
3887 { "pmovsxbd", { XM, EXd } },
3894 { "pmovsxbq", { XM, EXw } },
3901 { "pmovsxwd", { XM, EXq } },
3908 { "pmovsxwq", { XM, EXd } },
3915 { "pmovsxdq", { XM, EXq } },
3922 { "pmuldq", { XM, EXx } },
3929 { "pcmpeqq", { XM, EXx } },
3936 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3943 { "packusdw", { XM, EXx } },
3950 { "pmovzxbw", { XM, EXq } },
3957 { "pmovzxbd", { XM, EXd } },
3964 { "pmovzxbq", { XM, EXw } },
3971 { "pmovzxwd", { XM, EXq } },
3978 { "pmovzxwq", { XM, EXd } },
3985 { "pmovzxdq", { XM, EXq } },
3992 { "pcmpgtq", { XM, EXx } },
3999 { "pminsb", { XM, EXx } },
4006 { "pminsd", { XM, EXx } },
4013 { "pminuw", { XM, EXx } },
4020 { "pminud", { XM, EXx } },
4027 { "pmaxsb", { XM, EXx } },
4034 { "pmaxsd", { XM, EXx } },
4041 { "pmaxuw", { XM, EXx } },
4048 { "pmaxud", { XM, EXx } },
4055 { "pmulld", { XM, EXx } },
4062 { "phminposuw", { XM, EXx } },
4069 { "invept", { Gm, Mo } },
4076 { "invvpid", { Gm, Mo } },
4083 { "invpcid", { Gm, M } },
4088 { "sha1nexte", { XM, EXxmm } },
4093 { "sha1msg1", { XM, EXxmm } },
4098 { "sha1msg2", { XM, EXxmm } },
4103 { "sha256rnds2", { XM, EXxmm, XMM0 } },
4108 { "sha256msg1", { XM, EXxmm } },
4113 { "sha256msg2", { XM, EXxmm } },
4120 { "aesimc", { XM, EXx } },
4127 { "aesenc", { XM, EXx } },
4134 { "aesenclast", { XM, EXx } },
4141 { "aesdec", { XM, EXx } },
4148 { "aesdeclast", { XM, EXx } },
4153 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4155 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4156 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
4161 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4163 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4164 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
4170 { "adoxS", { Gdq, Edq} },
4171 { "adcxS", { Gdq, Edq} },
4179 { "roundps", { XM, EXx, Ib } },
4186 { "roundpd", { XM, EXx, Ib } },
4193 { "roundss", { XM, EXd, Ib } },
4200 { "roundsd", { XM, EXq, Ib } },
4207 { "blendps", { XM, EXx, Ib } },
4214 { "blendpd", { XM, EXx, Ib } },
4221 { "pblendw", { XM, EXx, Ib } },
4228 { "pextrb", { Edqb, XM, Ib } },
4235 { "pextrw", { Edqw, XM, Ib } },
4242 { "pextrK", { Edq, XM, Ib } },
4249 { "extractps", { Edqd, XM, Ib } },
4256 { "pinsrb", { XM, Edqb, Ib } },
4263 { "insertps", { XM, EXd, Ib } },
4270 { "pinsrK", { XM, Edq, Ib } },
4277 { "dpps", { XM, EXx, Ib } },
4284 { "dppd", { XM, EXx, Ib } },
4291 { "mpsadbw", { XM, EXx, Ib } },
4298 { "pclmulqdq", { XM, EXx, PCLMUL } },
4305 { "pcmpestrm", { XM, EXx, Ib } },
4312 { "pcmpestri", { XM, EXx, Ib } },
4319 { "pcmpistrm", { XM, EXx, Ib } },
4326 { "pcmpistri", { XM, EXx, Ib } },
4331 { "sha1rnds4", { XM, EXxmm, Ib } },
4338 { "aeskeygenassist", { XM, EXx, Ib } },
4341 /* PREFIX_VEX_0F10 */
4343 { VEX_W_TABLE (VEX_W_0F10_P_0) },
4344 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4345 { VEX_W_TABLE (VEX_W_0F10_P_2) },
4346 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4349 /* PREFIX_VEX_0F11 */
4351 { VEX_W_TABLE (VEX_W_0F11_P_0) },
4352 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4353 { VEX_W_TABLE (VEX_W_0F11_P_2) },
4354 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4357 /* PREFIX_VEX_0F12 */
4359 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4360 { VEX_W_TABLE (VEX_W_0F12_P_1) },
4361 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4362 { VEX_W_TABLE (VEX_W_0F12_P_3) },
4365 /* PREFIX_VEX_0F16 */
4367 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4368 { VEX_W_TABLE (VEX_W_0F16_P_1) },
4369 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4372 /* PREFIX_VEX_0F2A */
4375 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4377 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4380 /* PREFIX_VEX_0F2C */
4383 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4385 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4388 /* PREFIX_VEX_0F2D */
4391 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4393 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4396 /* PREFIX_VEX_0F2E */
4398 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4400 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4403 /* PREFIX_VEX_0F2F */
4405 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4407 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4410 /* PREFIX_VEX_0F41 */
4412 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4415 /* PREFIX_VEX_0F42 */
4417 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4420 /* PREFIX_VEX_0F44 */
4422 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4425 /* PREFIX_VEX_0F45 */
4427 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4430 /* PREFIX_VEX_0F46 */
4432 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4435 /* PREFIX_VEX_0F47 */
4437 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4440 /* PREFIX_VEX_0F4B */
4444 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4447 /* PREFIX_VEX_0F51 */
4449 { VEX_W_TABLE (VEX_W_0F51_P_0) },
4450 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4451 { VEX_W_TABLE (VEX_W_0F51_P_2) },
4452 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4455 /* PREFIX_VEX_0F52 */
4457 { VEX_W_TABLE (VEX_W_0F52_P_0) },
4458 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4461 /* PREFIX_VEX_0F53 */
4463 { VEX_W_TABLE (VEX_W_0F53_P_0) },
4464 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4467 /* PREFIX_VEX_0F58 */
4469 { VEX_W_TABLE (VEX_W_0F58_P_0) },
4470 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4471 { VEX_W_TABLE (VEX_W_0F58_P_2) },
4472 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4475 /* PREFIX_VEX_0F59 */
4477 { VEX_W_TABLE (VEX_W_0F59_P_0) },
4478 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4479 { VEX_W_TABLE (VEX_W_0F59_P_2) },
4480 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4483 /* PREFIX_VEX_0F5A */
4485 { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4486 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4487 { "vcvtpd2ps%XY", { XMM, EXx } },
4488 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4491 /* PREFIX_VEX_0F5B */
4493 { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4494 { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4495 { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4498 /* PREFIX_VEX_0F5C */
4500 { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4501 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4502 { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4503 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4506 /* PREFIX_VEX_0F5D */
4508 { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4509 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4510 { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4511 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4514 /* PREFIX_VEX_0F5E */
4516 { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4517 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4518 { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4519 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4522 /* PREFIX_VEX_0F5F */
4524 { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4525 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4526 { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4527 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4530 /* PREFIX_VEX_0F60 */
4534 { VEX_W_TABLE (VEX_W_0F60_P_2) },
4537 /* PREFIX_VEX_0F61 */
4541 { VEX_W_TABLE (VEX_W_0F61_P_2) },
4544 /* PREFIX_VEX_0F62 */
4548 { VEX_W_TABLE (VEX_W_0F62_P_2) },
4551 /* PREFIX_VEX_0F63 */
4555 { VEX_W_TABLE (VEX_W_0F63_P_2) },
4558 /* PREFIX_VEX_0F64 */
4562 { VEX_W_TABLE (VEX_W_0F64_P_2) },
4565 /* PREFIX_VEX_0F65 */
4569 { VEX_W_TABLE (VEX_W_0F65_P_2) },
4572 /* PREFIX_VEX_0F66 */
4576 { VEX_W_TABLE (VEX_W_0F66_P_2) },
4579 /* PREFIX_VEX_0F67 */
4583 { VEX_W_TABLE (VEX_W_0F67_P_2) },
4586 /* PREFIX_VEX_0F68 */
4590 { VEX_W_TABLE (VEX_W_0F68_P_2) },
4593 /* PREFIX_VEX_0F69 */
4597 { VEX_W_TABLE (VEX_W_0F69_P_2) },
4600 /* PREFIX_VEX_0F6A */
4604 { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4607 /* PREFIX_VEX_0F6B */
4611 { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4614 /* PREFIX_VEX_0F6C */
4618 { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4621 /* PREFIX_VEX_0F6D */
4625 { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4628 /* PREFIX_VEX_0F6E */
4632 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4635 /* PREFIX_VEX_0F6F */
4638 { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4639 { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4642 /* PREFIX_VEX_0F70 */
4645 { VEX_W_TABLE (VEX_W_0F70_P_1) },
4646 { VEX_W_TABLE (VEX_W_0F70_P_2) },
4647 { VEX_W_TABLE (VEX_W_0F70_P_3) },
4650 /* PREFIX_VEX_0F71_REG_2 */
4654 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4657 /* PREFIX_VEX_0F71_REG_4 */
4661 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4664 /* PREFIX_VEX_0F71_REG_6 */
4668 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4671 /* PREFIX_VEX_0F72_REG_2 */
4675 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4678 /* PREFIX_VEX_0F72_REG_4 */
4682 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4685 /* PREFIX_VEX_0F72_REG_6 */
4689 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4692 /* PREFIX_VEX_0F73_REG_2 */
4696 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4699 /* PREFIX_VEX_0F73_REG_3 */
4703 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4706 /* PREFIX_VEX_0F73_REG_6 */
4710 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4713 /* PREFIX_VEX_0F73_REG_7 */
4717 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4720 /* PREFIX_VEX_0F74 */
4724 { VEX_W_TABLE (VEX_W_0F74_P_2) },
4727 /* PREFIX_VEX_0F75 */
4731 { VEX_W_TABLE (VEX_W_0F75_P_2) },
4734 /* PREFIX_VEX_0F76 */
4738 { VEX_W_TABLE (VEX_W_0F76_P_2) },
4741 /* PREFIX_VEX_0F77 */
4743 { VEX_W_TABLE (VEX_W_0F77_P_0) },
4746 /* PREFIX_VEX_0F7C */
4750 { VEX_W_TABLE (VEX_W_0F7C_P_2) },
4751 { VEX_W_TABLE (VEX_W_0F7C_P_3) },
4754 /* PREFIX_VEX_0F7D */
4758 { VEX_W_TABLE (VEX_W_0F7D_P_2) },
4759 { VEX_W_TABLE (VEX_W_0F7D_P_3) },
4762 /* PREFIX_VEX_0F7E */
4765 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4766 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4769 /* PREFIX_VEX_0F7F */
4772 { VEX_W_TABLE (VEX_W_0F7F_P_1) },
4773 { VEX_W_TABLE (VEX_W_0F7F_P_2) },
4776 /* PREFIX_VEX_0F90 */
4778 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
4781 /* PREFIX_VEX_0F91 */
4783 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
4786 /* PREFIX_VEX_0F92 */
4788 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
4791 /* PREFIX_VEX_0F93 */
4793 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
4796 /* PREFIX_VEX_0F98 */
4798 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
4801 /* PREFIX_VEX_0FC2 */
4803 { VEX_W_TABLE (VEX_W_0FC2_P_0) },
4804 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
4805 { VEX_W_TABLE (VEX_W_0FC2_P_2) },
4806 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
4809 /* PREFIX_VEX_0FC4 */
4813 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
4816 /* PREFIX_VEX_0FC5 */
4820 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
4823 /* PREFIX_VEX_0FD0 */
4827 { VEX_W_TABLE (VEX_W_0FD0_P_2) },
4828 { VEX_W_TABLE (VEX_W_0FD0_P_3) },
4831 /* PREFIX_VEX_0FD1 */
4835 { VEX_W_TABLE (VEX_W_0FD1_P_2) },
4838 /* PREFIX_VEX_0FD2 */
4842 { VEX_W_TABLE (VEX_W_0FD2_P_2) },
4845 /* PREFIX_VEX_0FD3 */
4849 { VEX_W_TABLE (VEX_W_0FD3_P_2) },
4852 /* PREFIX_VEX_0FD4 */
4856 { VEX_W_TABLE (VEX_W_0FD4_P_2) },
4859 /* PREFIX_VEX_0FD5 */
4863 { VEX_W_TABLE (VEX_W_0FD5_P_2) },
4866 /* PREFIX_VEX_0FD6 */
4870 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
4873 /* PREFIX_VEX_0FD7 */
4877 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
4880 /* PREFIX_VEX_0FD8 */
4884 { VEX_W_TABLE (VEX_W_0FD8_P_2) },
4887 /* PREFIX_VEX_0FD9 */
4891 { VEX_W_TABLE (VEX_W_0FD9_P_2) },
4894 /* PREFIX_VEX_0FDA */
4898 { VEX_W_TABLE (VEX_W_0FDA_P_2) },
4901 /* PREFIX_VEX_0FDB */
4905 { VEX_W_TABLE (VEX_W_0FDB_P_2) },
4908 /* PREFIX_VEX_0FDC */
4912 { VEX_W_TABLE (VEX_W_0FDC_P_2) },
4915 /* PREFIX_VEX_0FDD */
4919 { VEX_W_TABLE (VEX_W_0FDD_P_2) },
4922 /* PREFIX_VEX_0FDE */
4926 { VEX_W_TABLE (VEX_W_0FDE_P_2) },
4929 /* PREFIX_VEX_0FDF */
4933 { VEX_W_TABLE (VEX_W_0FDF_P_2) },
4936 /* PREFIX_VEX_0FE0 */
4940 { VEX_W_TABLE (VEX_W_0FE0_P_2) },
4943 /* PREFIX_VEX_0FE1 */
4947 { VEX_W_TABLE (VEX_W_0FE1_P_2) },
4950 /* PREFIX_VEX_0FE2 */
4954 { VEX_W_TABLE (VEX_W_0FE2_P_2) },
4957 /* PREFIX_VEX_0FE3 */
4961 { VEX_W_TABLE (VEX_W_0FE3_P_2) },
4964 /* PREFIX_VEX_0FE4 */
4968 { VEX_W_TABLE (VEX_W_0FE4_P_2) },
4971 /* PREFIX_VEX_0FE5 */
4975 { VEX_W_TABLE (VEX_W_0FE5_P_2) },
4978 /* PREFIX_VEX_0FE6 */
4981 { VEX_W_TABLE (VEX_W_0FE6_P_1) },
4982 { VEX_W_TABLE (VEX_W_0FE6_P_2) },
4983 { VEX_W_TABLE (VEX_W_0FE6_P_3) },
4986 /* PREFIX_VEX_0FE7 */
4990 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
4993 /* PREFIX_VEX_0FE8 */
4997 { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5000 /* PREFIX_VEX_0FE9 */
5004 { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5007 /* PREFIX_VEX_0FEA */
5011 { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5014 /* PREFIX_VEX_0FEB */
5018 { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5021 /* PREFIX_VEX_0FEC */
5025 { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5028 /* PREFIX_VEX_0FED */
5032 { VEX_W_TABLE (VEX_W_0FED_P_2) },
5035 /* PREFIX_VEX_0FEE */
5039 { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5042 /* PREFIX_VEX_0FEF */
5046 { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5049 /* PREFIX_VEX_0FF0 */
5054 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5057 /* PREFIX_VEX_0FF1 */
5061 { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5064 /* PREFIX_VEX_0FF2 */
5068 { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5071 /* PREFIX_VEX_0FF3 */
5075 { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5078 /* PREFIX_VEX_0FF4 */
5082 { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5085 /* PREFIX_VEX_0FF5 */
5089 { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5092 /* PREFIX_VEX_0FF6 */
5096 { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5099 /* PREFIX_VEX_0FF7 */
5103 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5106 /* PREFIX_VEX_0FF8 */
5110 { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5113 /* PREFIX_VEX_0FF9 */
5117 { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5120 /* PREFIX_VEX_0FFA */
5124 { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5127 /* PREFIX_VEX_0FFB */
5131 { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5134 /* PREFIX_VEX_0FFC */
5138 { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5141 /* PREFIX_VEX_0FFD */
5145 { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5148 /* PREFIX_VEX_0FFE */
5152 { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5155 /* PREFIX_VEX_0F3800 */
5159 { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5162 /* PREFIX_VEX_0F3801 */
5166 { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5169 /* PREFIX_VEX_0F3802 */
5173 { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5176 /* PREFIX_VEX_0F3803 */
5180 { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5183 /* PREFIX_VEX_0F3804 */
5187 { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5190 /* PREFIX_VEX_0F3805 */
5194 { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5197 /* PREFIX_VEX_0F3806 */
5201 { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5204 /* PREFIX_VEX_0F3807 */
5208 { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5211 /* PREFIX_VEX_0F3808 */
5215 { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5218 /* PREFIX_VEX_0F3809 */
5222 { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5225 /* PREFIX_VEX_0F380A */
5229 { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5232 /* PREFIX_VEX_0F380B */
5236 { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5239 /* PREFIX_VEX_0F380C */
5243 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5246 /* PREFIX_VEX_0F380D */
5250 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5253 /* PREFIX_VEX_0F380E */
5257 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5260 /* PREFIX_VEX_0F380F */
5264 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5267 /* PREFIX_VEX_0F3813 */
5271 { "vcvtph2ps", { XM, EXxmmq } },
5274 /* PREFIX_VEX_0F3816 */
5278 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5281 /* PREFIX_VEX_0F3817 */
5285 { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5288 /* PREFIX_VEX_0F3818 */
5292 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5295 /* PREFIX_VEX_0F3819 */
5299 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5302 /* PREFIX_VEX_0F381A */
5306 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5309 /* PREFIX_VEX_0F381C */
5313 { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5316 /* PREFIX_VEX_0F381D */
5320 { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5323 /* PREFIX_VEX_0F381E */
5327 { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5330 /* PREFIX_VEX_0F3820 */
5334 { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5337 /* PREFIX_VEX_0F3821 */
5341 { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5344 /* PREFIX_VEX_0F3822 */
5348 { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5351 /* PREFIX_VEX_0F3823 */
5355 { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5358 /* PREFIX_VEX_0F3824 */
5362 { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5365 /* PREFIX_VEX_0F3825 */
5369 { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5372 /* PREFIX_VEX_0F3828 */
5376 { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5379 /* PREFIX_VEX_0F3829 */
5383 { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5386 /* PREFIX_VEX_0F382A */
5390 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5393 /* PREFIX_VEX_0F382B */
5397 { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5400 /* PREFIX_VEX_0F382C */
5404 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5407 /* PREFIX_VEX_0F382D */
5411 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5414 /* PREFIX_VEX_0F382E */
5418 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5421 /* PREFIX_VEX_0F382F */
5425 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5428 /* PREFIX_VEX_0F3830 */
5432 { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5435 /* PREFIX_VEX_0F3831 */
5439 { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5442 /* PREFIX_VEX_0F3832 */
5446 { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5449 /* PREFIX_VEX_0F3833 */
5453 { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5456 /* PREFIX_VEX_0F3834 */
5460 { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5463 /* PREFIX_VEX_0F3835 */
5467 { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5470 /* PREFIX_VEX_0F3836 */
5474 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5477 /* PREFIX_VEX_0F3837 */
5481 { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5484 /* PREFIX_VEX_0F3838 */
5488 { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5491 /* PREFIX_VEX_0F3839 */
5495 { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5498 /* PREFIX_VEX_0F383A */
5502 { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5505 /* PREFIX_VEX_0F383B */
5509 { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5512 /* PREFIX_VEX_0F383C */
5516 { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5519 /* PREFIX_VEX_0F383D */
5523 { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5526 /* PREFIX_VEX_0F383E */
5530 { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5533 /* PREFIX_VEX_0F383F */
5537 { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5540 /* PREFIX_VEX_0F3840 */
5544 { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5547 /* PREFIX_VEX_0F3841 */
5551 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5554 /* PREFIX_VEX_0F3845 */
5558 { "vpsrlv%LW", { XM, Vex, EXx } },
5561 /* PREFIX_VEX_0F3846 */
5565 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5568 /* PREFIX_VEX_0F3847 */
5572 { "vpsllv%LW", { XM, Vex, EXx } },
5575 /* PREFIX_VEX_0F3858 */
5579 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5582 /* PREFIX_VEX_0F3859 */
5586 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5589 /* PREFIX_VEX_0F385A */
5593 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5596 /* PREFIX_VEX_0F3878 */
5600 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5603 /* PREFIX_VEX_0F3879 */
5607 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5610 /* PREFIX_VEX_0F388C */
5614 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5617 /* PREFIX_VEX_0F388E */
5621 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5624 /* PREFIX_VEX_0F3890 */
5628 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
5631 /* PREFIX_VEX_0F3891 */
5635 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5638 /* PREFIX_VEX_0F3892 */
5642 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
5645 /* PREFIX_VEX_0F3893 */
5649 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5652 /* PREFIX_VEX_0F3896 */
5656 { "vfmaddsub132p%XW", { XM, Vex, EXx } },
5659 /* PREFIX_VEX_0F3897 */
5663 { "vfmsubadd132p%XW", { XM, Vex, EXx } },
5666 /* PREFIX_VEX_0F3898 */
5670 { "vfmadd132p%XW", { XM, Vex, EXx } },
5673 /* PREFIX_VEX_0F3899 */
5677 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5680 /* PREFIX_VEX_0F389A */
5684 { "vfmsub132p%XW", { XM, Vex, EXx } },
5687 /* PREFIX_VEX_0F389B */
5691 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5694 /* PREFIX_VEX_0F389C */
5698 { "vfnmadd132p%XW", { XM, Vex, EXx } },
5701 /* PREFIX_VEX_0F389D */
5705 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5708 /* PREFIX_VEX_0F389E */
5712 { "vfnmsub132p%XW", { XM, Vex, EXx } },
5715 /* PREFIX_VEX_0F389F */
5719 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5722 /* PREFIX_VEX_0F38A6 */
5726 { "vfmaddsub213p%XW", { XM, Vex, EXx } },
5730 /* PREFIX_VEX_0F38A7 */
5734 { "vfmsubadd213p%XW", { XM, Vex, EXx } },
5737 /* PREFIX_VEX_0F38A8 */
5741 { "vfmadd213p%XW", { XM, Vex, EXx } },
5744 /* PREFIX_VEX_0F38A9 */
5748 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5751 /* PREFIX_VEX_0F38AA */
5755 { "vfmsub213p%XW", { XM, Vex, EXx } },
5758 /* PREFIX_VEX_0F38AB */
5762 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5765 /* PREFIX_VEX_0F38AC */
5769 { "vfnmadd213p%XW", { XM, Vex, EXx } },
5772 /* PREFIX_VEX_0F38AD */
5776 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5779 /* PREFIX_VEX_0F38AE */
5783 { "vfnmsub213p%XW", { XM, Vex, EXx } },
5786 /* PREFIX_VEX_0F38AF */
5790 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5793 /* PREFIX_VEX_0F38B6 */
5797 { "vfmaddsub231p%XW", { XM, Vex, EXx } },
5800 /* PREFIX_VEX_0F38B7 */
5804 { "vfmsubadd231p%XW", { XM, Vex, EXx } },
5807 /* PREFIX_VEX_0F38B8 */
5811 { "vfmadd231p%XW", { XM, Vex, EXx } },
5814 /* PREFIX_VEX_0F38B9 */
5818 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5821 /* PREFIX_VEX_0F38BA */
5825 { "vfmsub231p%XW", { XM, Vex, EXx } },
5828 /* PREFIX_VEX_0F38BB */
5832 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5835 /* PREFIX_VEX_0F38BC */
5839 { "vfnmadd231p%XW", { XM, Vex, EXx } },
5842 /* PREFIX_VEX_0F38BD */
5846 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5849 /* PREFIX_VEX_0F38BE */
5853 { "vfnmsub231p%XW", { XM, Vex, EXx } },
5856 /* PREFIX_VEX_0F38BF */
5860 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5863 /* PREFIX_VEX_0F38DB */
5867 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
5870 /* PREFIX_VEX_0F38DC */
5874 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
5877 /* PREFIX_VEX_0F38DD */
5881 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
5884 /* PREFIX_VEX_0F38DE */
5888 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
5891 /* PREFIX_VEX_0F38DF */
5895 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
5898 /* PREFIX_VEX_0F38F2 */
5900 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
5903 /* PREFIX_VEX_0F38F3_REG_1 */
5905 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
5908 /* PREFIX_VEX_0F38F3_REG_2 */
5910 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
5913 /* PREFIX_VEX_0F38F3_REG_3 */
5915 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
5918 /* PREFIX_VEX_0F38F5 */
5920 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
5921 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
5923 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
5926 /* PREFIX_VEX_0F38F6 */
5931 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
5934 /* PREFIX_VEX_0F38F7 */
5936 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
5937 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
5938 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
5939 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
5942 /* PREFIX_VEX_0F3A00 */
5946 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
5949 /* PREFIX_VEX_0F3A01 */
5953 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
5956 /* PREFIX_VEX_0F3A02 */
5960 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
5963 /* PREFIX_VEX_0F3A04 */
5967 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
5970 /* PREFIX_VEX_0F3A05 */
5974 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
5977 /* PREFIX_VEX_0F3A06 */
5981 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
5984 /* PREFIX_VEX_0F3A08 */
5988 { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
5991 /* PREFIX_VEX_0F3A09 */
5995 { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
5998 /* PREFIX_VEX_0F3A0A */
6002 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6005 /* PREFIX_VEX_0F3A0B */
6009 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6012 /* PREFIX_VEX_0F3A0C */
6016 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6019 /* PREFIX_VEX_0F3A0D */
6023 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6026 /* PREFIX_VEX_0F3A0E */
6030 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6033 /* PREFIX_VEX_0F3A0F */
6037 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6040 /* PREFIX_VEX_0F3A14 */
6044 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6047 /* PREFIX_VEX_0F3A15 */
6051 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6054 /* PREFIX_VEX_0F3A16 */
6058 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6061 /* PREFIX_VEX_0F3A17 */
6065 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6068 /* PREFIX_VEX_0F3A18 */
6072 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6075 /* PREFIX_VEX_0F3A19 */
6079 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6082 /* PREFIX_VEX_0F3A1D */
6086 { "vcvtps2ph", { EXxmmq, XM, Ib } },
6089 /* PREFIX_VEX_0F3A20 */
6093 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6096 /* PREFIX_VEX_0F3A21 */
6100 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6103 /* PREFIX_VEX_0F3A22 */
6107 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6110 /* PREFIX_VEX_0F3A30 */
6114 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6117 /* PREFIX_VEX_0F3A32 */
6121 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6124 /* PREFIX_VEX_0F3A38 */
6128 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6131 /* PREFIX_VEX_0F3A39 */
6135 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6138 /* PREFIX_VEX_0F3A40 */
6142 { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6145 /* PREFIX_VEX_0F3A41 */
6149 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6152 /* PREFIX_VEX_0F3A42 */
6156 { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6159 /* PREFIX_VEX_0F3A44 */
6163 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6166 /* PREFIX_VEX_0F3A46 */
6170 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6173 /* PREFIX_VEX_0F3A48 */
6177 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6180 /* PREFIX_VEX_0F3A49 */
6184 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6187 /* PREFIX_VEX_0F3A4A */
6191 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6194 /* PREFIX_VEX_0F3A4B */
6198 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6201 /* PREFIX_VEX_0F3A4C */
6205 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6208 /* PREFIX_VEX_0F3A5C */
6212 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6215 /* PREFIX_VEX_0F3A5D */
6219 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6222 /* PREFIX_VEX_0F3A5E */
6226 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6229 /* PREFIX_VEX_0F3A5F */
6233 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6236 /* PREFIX_VEX_0F3A60 */
6240 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6244 /* PREFIX_VEX_0F3A61 */
6248 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6251 /* PREFIX_VEX_0F3A62 */
6255 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6258 /* PREFIX_VEX_0F3A63 */
6262 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6265 /* PREFIX_VEX_0F3A68 */
6269 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6272 /* PREFIX_VEX_0F3A69 */
6276 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6279 /* PREFIX_VEX_0F3A6A */
6283 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6286 /* PREFIX_VEX_0F3A6B */
6290 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6293 /* PREFIX_VEX_0F3A6C */
6297 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6300 /* PREFIX_VEX_0F3A6D */
6304 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6307 /* PREFIX_VEX_0F3A6E */
6311 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6314 /* PREFIX_VEX_0F3A6F */
6318 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6321 /* PREFIX_VEX_0F3A78 */
6325 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6328 /* PREFIX_VEX_0F3A79 */
6332 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6335 /* PREFIX_VEX_0F3A7A */
6339 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6342 /* PREFIX_VEX_0F3A7B */
6346 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6349 /* PREFIX_VEX_0F3A7C */
6353 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6357 /* PREFIX_VEX_0F3A7D */
6361 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6364 /* PREFIX_VEX_0F3A7E */
6368 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6371 /* PREFIX_VEX_0F3A7F */
6375 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6378 /* PREFIX_VEX_0F3ADF */
6382 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6385 /* PREFIX_VEX_0F3AF0 */
6390 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6393 #define NEED_PREFIX_TABLE
6394 #include "i386-dis-evex.h"
6395 #undef NEED_PREFIX_TABLE
6398 static const struct dis386 x86_64_table[][2] = {
6401 { "pushP", { es } },
6411 { "pushP", { cs } },
6416 { "pushP", { ss } },
6426 { "pushP", { ds } },
6456 { "pushaP", { XX } },
6461 { "popaP", { XX } },
6466 { MOD_TABLE (MOD_62_32BIT) },
6467 { EVEX_TABLE (EVEX_0F) },
6472 { "arpl", { Ew, Gw } },
6473 { "movs{lq|xd}", { Gv, Ed } },
6478 { "ins{R|}", { Yzr, indirDX } },
6479 { "ins{G|}", { Yzr, indirDX } },
6484 { "outs{R|}", { indirDXr, Xz } },
6485 { "outs{G|}", { indirDXr, Xz } },
6490 { "Jcall{T|}", { Ap } },
6495 { MOD_TABLE (MOD_C4_32BIT) },
6496 { VEX_C4_TABLE (VEX_0F) },
6501 { MOD_TABLE (MOD_C5_32BIT) },
6502 { VEX_C5_TABLE (VEX_0F) },
6522 { "Jjmp{T|}", { Ap } },
6525 /* X86_64_0F01_REG_0 */
6527 { "sgdt{Q|IQ}", { M } },
6531 /* X86_64_0F01_REG_1 */
6533 { "sidt{Q|IQ}", { M } },
6537 /* X86_64_0F01_REG_2 */
6539 { "lgdt{Q|Q}", { M } },
6543 /* X86_64_0F01_REG_3 */
6545 { "lidt{Q|Q}", { M } },
6550 static const struct dis386 three_byte_table[][256] = {
6552 /* THREE_BYTE_0F38 */
6555 { "pshufb", { MX, EM } },
6556 { "phaddw", { MX, EM } },
6557 { "phaddd", { MX, EM } },
6558 { "phaddsw", { MX, EM } },
6559 { "pmaddubsw", { MX, EM } },
6560 { "phsubw", { MX, EM } },
6561 { "phsubd", { MX, EM } },
6562 { "phsubsw", { MX, EM } },
6564 { "psignb", { MX, EM } },
6565 { "psignw", { MX, EM } },
6566 { "psignd", { MX, EM } },
6567 { "pmulhrsw", { MX, EM } },
6573 { PREFIX_TABLE (PREFIX_0F3810) },
6577 { PREFIX_TABLE (PREFIX_0F3814) },
6578 { PREFIX_TABLE (PREFIX_0F3815) },
6580 { PREFIX_TABLE (PREFIX_0F3817) },
6586 { "pabsb", { MX, EM } },
6587 { "pabsw", { MX, EM } },
6588 { "pabsd", { MX, EM } },
6591 { PREFIX_TABLE (PREFIX_0F3820) },
6592 { PREFIX_TABLE (PREFIX_0F3821) },
6593 { PREFIX_TABLE (PREFIX_0F3822) },
6594 { PREFIX_TABLE (PREFIX_0F3823) },
6595 { PREFIX_TABLE (PREFIX_0F3824) },
6596 { PREFIX_TABLE (PREFIX_0F3825) },
6600 { PREFIX_TABLE (PREFIX_0F3828) },
6601 { PREFIX_TABLE (PREFIX_0F3829) },
6602 { PREFIX_TABLE (PREFIX_0F382A) },
6603 { PREFIX_TABLE (PREFIX_0F382B) },
6609 { PREFIX_TABLE (PREFIX_0F3830) },
6610 { PREFIX_TABLE (PREFIX_0F3831) },
6611 { PREFIX_TABLE (PREFIX_0F3832) },
6612 { PREFIX_TABLE (PREFIX_0F3833) },
6613 { PREFIX_TABLE (PREFIX_0F3834) },
6614 { PREFIX_TABLE (PREFIX_0F3835) },
6616 { PREFIX_TABLE (PREFIX_0F3837) },
6618 { PREFIX_TABLE (PREFIX_0F3838) },
6619 { PREFIX_TABLE (PREFIX_0F3839) },
6620 { PREFIX_TABLE (PREFIX_0F383A) },
6621 { PREFIX_TABLE (PREFIX_0F383B) },
6622 { PREFIX_TABLE (PREFIX_0F383C) },
6623 { PREFIX_TABLE (PREFIX_0F383D) },
6624 { PREFIX_TABLE (PREFIX_0F383E) },
6625 { PREFIX_TABLE (PREFIX_0F383F) },
6627 { PREFIX_TABLE (PREFIX_0F3840) },
6628 { PREFIX_TABLE (PREFIX_0F3841) },
6699 { PREFIX_TABLE (PREFIX_0F3880) },
6700 { PREFIX_TABLE (PREFIX_0F3881) },
6701 { PREFIX_TABLE (PREFIX_0F3882) },
6780 { PREFIX_TABLE (PREFIX_0F38C8) },
6781 { PREFIX_TABLE (PREFIX_0F38C9) },
6782 { PREFIX_TABLE (PREFIX_0F38CA) },
6783 { PREFIX_TABLE (PREFIX_0F38CB) },
6784 { PREFIX_TABLE (PREFIX_0F38CC) },
6785 { PREFIX_TABLE (PREFIX_0F38CD) },
6801 { PREFIX_TABLE (PREFIX_0F38DB) },
6802 { PREFIX_TABLE (PREFIX_0F38DC) },
6803 { PREFIX_TABLE (PREFIX_0F38DD) },
6804 { PREFIX_TABLE (PREFIX_0F38DE) },
6805 { PREFIX_TABLE (PREFIX_0F38DF) },
6825 { PREFIX_TABLE (PREFIX_0F38F0) },
6826 { PREFIX_TABLE (PREFIX_0F38F1) },
6831 { PREFIX_TABLE (PREFIX_0F38F6) },
6843 /* THREE_BYTE_0F3A */
6855 { PREFIX_TABLE (PREFIX_0F3A08) },
6856 { PREFIX_TABLE (PREFIX_0F3A09) },
6857 { PREFIX_TABLE (PREFIX_0F3A0A) },
6858 { PREFIX_TABLE (PREFIX_0F3A0B) },
6859 { PREFIX_TABLE (PREFIX_0F3A0C) },
6860 { PREFIX_TABLE (PREFIX_0F3A0D) },
6861 { PREFIX_TABLE (PREFIX_0F3A0E) },
6862 { "palignr", { MX, EM, Ib } },
6868 { PREFIX_TABLE (PREFIX_0F3A14) },
6869 { PREFIX_TABLE (PREFIX_0F3A15) },
6870 { PREFIX_TABLE (PREFIX_0F3A16) },
6871 { PREFIX_TABLE (PREFIX_0F3A17) },
6882 { PREFIX_TABLE (PREFIX_0F3A20) },
6883 { PREFIX_TABLE (PREFIX_0F3A21) },
6884 { PREFIX_TABLE (PREFIX_0F3A22) },
6918 { PREFIX_TABLE (PREFIX_0F3A40) },
6919 { PREFIX_TABLE (PREFIX_0F3A41) },
6920 { PREFIX_TABLE (PREFIX_0F3A42) },
6922 { PREFIX_TABLE (PREFIX_0F3A44) },
6954 { PREFIX_TABLE (PREFIX_0F3A60) },
6955 { PREFIX_TABLE (PREFIX_0F3A61) },
6956 { PREFIX_TABLE (PREFIX_0F3A62) },
6957 { PREFIX_TABLE (PREFIX_0F3A63) },
7075 { PREFIX_TABLE (PREFIX_0F3ACC) },
7096 { PREFIX_TABLE (PREFIX_0F3ADF) },
7135 /* THREE_BYTE_0F7A */
7174 { "ptest", { XX } },
7211 { "phaddbw", { XM, EXq } },
7212 { "phaddbd", { XM, EXq } },
7213 { "phaddbq", { XM, EXq } },
7216 { "phaddwd", { XM, EXq } },
7217 { "phaddwq", { XM, EXq } },
7222 { "phadddq", { XM, EXq } },
7229 { "phaddubw", { XM, EXq } },
7230 { "phaddubd", { XM, EXq } },
7231 { "phaddubq", { XM, EXq } },
7234 { "phadduwd", { XM, EXq } },
7235 { "phadduwq", { XM, EXq } },
7240 { "phaddudq", { XM, EXq } },
7247 { "phsubbw", { XM, EXq } },
7248 { "phsubbd", { XM, EXq } },
7249 { "phsubbq", { XM, EXq } },
7428 static const struct dis386 xop_table[][256] = {
7581 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7582 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7583 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7591 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7592 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7599 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7600 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7601 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7609 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7610 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7614 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7615 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7618 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7636 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7648 { "vprotb", { XM, Vex_2src_1, Ib } },
7649 { "vprotw", { XM, Vex_2src_1, Ib } },
7650 { "vprotd", { XM, Vex_2src_1, Ib } },
7651 { "vprotq", { XM, Vex_2src_1, Ib } },
7661 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7662 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7663 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7664 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7697 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7698 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7699 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7700 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7724 { REG_TABLE (REG_XOP_TBM_01) },
7725 { REG_TABLE (REG_XOP_TBM_02) },
7743 { REG_TABLE (REG_XOP_LWPCB) },
7867 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7868 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7869 { "vfrczss", { XM, EXd } },
7870 { "vfrczsd", { XM, EXq } },
7885 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } },
7886 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } },
7887 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } },
7888 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } },
7889 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } },
7890 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } },
7891 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } },
7892 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } },
7894 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } },
7895 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } },
7896 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } },
7897 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } },
7940 { "vphaddbw", { XM, EXxmm } },
7941 { "vphaddbd", { XM, EXxmm } },
7942 { "vphaddbq", { XM, EXxmm } },
7945 { "vphaddwd", { XM, EXxmm } },
7946 { "vphaddwq", { XM, EXxmm } },
7951 { "vphadddq", { XM, EXxmm } },
7958 { "vphaddubw", { XM, EXxmm } },
7959 { "vphaddubd", { XM, EXxmm } },
7960 { "vphaddubq", { XM, EXxmm } },
7963 { "vphadduwd", { XM, EXxmm } },
7964 { "vphadduwq", { XM, EXxmm } },
7969 { "vphaddudq", { XM, EXxmm } },
7976 { "vphsubbw", { XM, EXxmm } },
7977 { "vphsubwd", { XM, EXxmm } },
7978 { "vphsubdq", { XM, EXxmm } },
8032 { "bextr", { Gv, Ev, Iq } },
8034 { REG_TABLE (REG_XOP_LWP) },
8304 static const struct dis386 vex_table[][256] = {
8326 { PREFIX_TABLE (PREFIX_VEX_0F10) },
8327 { PREFIX_TABLE (PREFIX_VEX_0F11) },
8328 { PREFIX_TABLE (PREFIX_VEX_0F12) },
8329 { MOD_TABLE (MOD_VEX_0F13) },
8330 { VEX_W_TABLE (VEX_W_0F14) },
8331 { VEX_W_TABLE (VEX_W_0F15) },
8332 { PREFIX_TABLE (PREFIX_VEX_0F16) },
8333 { MOD_TABLE (MOD_VEX_0F17) },
8353 { VEX_W_TABLE (VEX_W_0F28) },
8354 { VEX_W_TABLE (VEX_W_0F29) },
8355 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8356 { MOD_TABLE (MOD_VEX_0F2B) },
8357 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8358 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8359 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8360 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8381 { PREFIX_TABLE (PREFIX_VEX_0F41) },
8382 { PREFIX_TABLE (PREFIX_VEX_0F42) },
8384 { PREFIX_TABLE (PREFIX_VEX_0F44) },
8385 { PREFIX_TABLE (PREFIX_VEX_0F45) },
8386 { PREFIX_TABLE (PREFIX_VEX_0F46) },
8387 { PREFIX_TABLE (PREFIX_VEX_0F47) },
8392 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8398 { MOD_TABLE (MOD_VEX_0F50) },
8399 { PREFIX_TABLE (PREFIX_VEX_0F51) },
8400 { PREFIX_TABLE (PREFIX_VEX_0F52) },
8401 { PREFIX_TABLE (PREFIX_VEX_0F53) },
8402 { "vandpX", { XM, Vex, EXx } },
8403 { "vandnpX", { XM, Vex, EXx } },
8404 { "vorpX", { XM, Vex, EXx } },
8405 { "vxorpX", { XM, Vex, EXx } },
8407 { PREFIX_TABLE (PREFIX_VEX_0F58) },
8408 { PREFIX_TABLE (PREFIX_VEX_0F59) },
8409 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8410 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8411 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8412 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8413 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8414 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8416 { PREFIX_TABLE (PREFIX_VEX_0F60) },
8417 { PREFIX_TABLE (PREFIX_VEX_0F61) },
8418 { PREFIX_TABLE (PREFIX_VEX_0F62) },
8419 { PREFIX_TABLE (PREFIX_VEX_0F63) },
8420 { PREFIX_TABLE (PREFIX_VEX_0F64) },
8421 { PREFIX_TABLE (PREFIX_VEX_0F65) },
8422 { PREFIX_TABLE (PREFIX_VEX_0F66) },
8423 { PREFIX_TABLE (PREFIX_VEX_0F67) },
8425 { PREFIX_TABLE (PREFIX_VEX_0F68) },
8426 { PREFIX_TABLE (PREFIX_VEX_0F69) },
8427 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8428 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8429 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8430 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8431 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8432 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8434 { PREFIX_TABLE (PREFIX_VEX_0F70) },
8435 { REG_TABLE (REG_VEX_0F71) },
8436 { REG_TABLE (REG_VEX_0F72) },
8437 { REG_TABLE (REG_VEX_0F73) },
8438 { PREFIX_TABLE (PREFIX_VEX_0F74) },
8439 { PREFIX_TABLE (PREFIX_VEX_0F75) },
8440 { PREFIX_TABLE (PREFIX_VEX_0F76) },
8441 { PREFIX_TABLE (PREFIX_VEX_0F77) },
8447 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8448 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8449 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8450 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8470 { PREFIX_TABLE (PREFIX_VEX_0F90) },
8471 { PREFIX_TABLE (PREFIX_VEX_0F91) },
8472 { PREFIX_TABLE (PREFIX_VEX_0F92) },
8473 { PREFIX_TABLE (PREFIX_VEX_0F93) },
8479 { PREFIX_TABLE (PREFIX_VEX_0F98) },
8503 { REG_TABLE (REG_VEX_0FAE) },
8526 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8528 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8529 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8530 { "vshufpX", { XM, Vex, EXx, Ib } },
8542 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8543 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8544 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8545 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8546 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8547 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8548 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8549 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8551 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8552 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8553 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8554 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8555 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8556 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8557 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8558 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8560 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8561 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8562 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8563 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8564 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8565 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8566 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8567 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8569 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8570 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8571 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8572 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8573 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8574 { PREFIX_TABLE (PREFIX_VEX_0FED) },
8575 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8576 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8578 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8579 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8580 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8581 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8582 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8583 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8584 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8585 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8587 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8588 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8589 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8590 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8591 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8592 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8593 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8599 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8600 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8601 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8602 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8603 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8604 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8605 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8606 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8608 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8609 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8610 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8611 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8612 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8613 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8614 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8615 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8620 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8623 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8624 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8626 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8627 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8628 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8630 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8631 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8632 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8635 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8636 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8637 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8638 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8639 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8640 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8644 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8645 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8646 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8647 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8648 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8649 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8650 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8651 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8653 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8654 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8655 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8656 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8657 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8658 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8659 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8660 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8662 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8663 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8664 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8665 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8666 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8667 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8668 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8669 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8671 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8672 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8676 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8677 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8678 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8698 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8699 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8700 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8734 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8735 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8789 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8790 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8792 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8795 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8803 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8804 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8806 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8807 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8808 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8809 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8810 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8811 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8812 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8813 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8845 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8846 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8847 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8848 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8849 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8871 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8872 { REG_TABLE (REG_VEX_0F38F3) },
8874 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8875 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8876 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8895 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8896 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8905 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8926 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8927 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8928 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8954 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8962 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8963 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8964 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8966 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8968 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8972 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8973 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8974 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8975 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8993 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
8994 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
8995 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
8996 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
8999 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9001 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9008 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9009 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9010 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9011 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9012 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9013 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9014 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9026 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9027 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9028 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9029 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9030 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9031 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9032 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9140 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9160 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9180 #define NEED_OPCODE_TABLE
9181 #include "i386-dis-evex.h"
9182 #undef NEED_OPCODE_TABLE
9183 static const struct dis386 vex_len_table[][2] = {
9184 /* VEX_LEN_0F10_P_1 */
9186 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9187 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9190 /* VEX_LEN_0F10_P_3 */
9192 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9193 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9196 /* VEX_LEN_0F11_P_1 */
9198 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9199 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9202 /* VEX_LEN_0F11_P_3 */
9204 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9205 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9208 /* VEX_LEN_0F12_P_0_M_0 */
9210 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9213 /* VEX_LEN_0F12_P_0_M_1 */
9215 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9218 /* VEX_LEN_0F12_P_2 */
9220 { VEX_W_TABLE (VEX_W_0F12_P_2) },
9223 /* VEX_LEN_0F13_M_0 */
9225 { VEX_W_TABLE (VEX_W_0F13_M_0) },
9228 /* VEX_LEN_0F16_P_0_M_0 */
9230 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9233 /* VEX_LEN_0F16_P_0_M_1 */
9235 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9238 /* VEX_LEN_0F16_P_2 */
9240 { VEX_W_TABLE (VEX_W_0F16_P_2) },
9243 /* VEX_LEN_0F17_M_0 */
9245 { VEX_W_TABLE (VEX_W_0F17_M_0) },
9248 /* VEX_LEN_0F2A_P_1 */
9250 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
9251 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
9254 /* VEX_LEN_0F2A_P_3 */
9256 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
9257 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
9260 /* VEX_LEN_0F2C_P_1 */
9262 { "vcvttss2siY", { Gv, EXdScalar } },
9263 { "vcvttss2siY", { Gv, EXdScalar } },
9266 /* VEX_LEN_0F2C_P_3 */
9268 { "vcvttsd2siY", { Gv, EXqScalar } },
9269 { "vcvttsd2siY", { Gv, EXqScalar } },
9272 /* VEX_LEN_0F2D_P_1 */
9274 { "vcvtss2siY", { Gv, EXdScalar } },
9275 { "vcvtss2siY", { Gv, EXdScalar } },
9278 /* VEX_LEN_0F2D_P_3 */
9280 { "vcvtsd2siY", { Gv, EXqScalar } },
9281 { "vcvtsd2siY", { Gv, EXqScalar } },
9284 /* VEX_LEN_0F2E_P_0 */
9286 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9287 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9290 /* VEX_LEN_0F2E_P_2 */
9292 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9293 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9296 /* VEX_LEN_0F2F_P_0 */
9298 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9299 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9302 /* VEX_LEN_0F2F_P_2 */
9304 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9305 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9308 /* VEX_LEN_0F41_P_0 */
9311 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9313 /* VEX_LEN_0F42_P_0 */
9316 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9318 /* VEX_LEN_0F44_P_0 */
9320 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9322 /* VEX_LEN_0F45_P_0 */
9325 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9327 /* VEX_LEN_0F46_P_0 */
9330 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9332 /* VEX_LEN_0F47_P_0 */
9335 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9337 /* VEX_LEN_0F4B_P_2 */
9340 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9343 /* VEX_LEN_0F51_P_1 */
9345 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9346 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9349 /* VEX_LEN_0F51_P_3 */
9351 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9352 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9355 /* VEX_LEN_0F52_P_1 */
9357 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9358 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9361 /* VEX_LEN_0F53_P_1 */
9363 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9364 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9367 /* VEX_LEN_0F58_P_1 */
9369 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9370 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9373 /* VEX_LEN_0F58_P_3 */
9375 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9376 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9379 /* VEX_LEN_0F59_P_1 */
9381 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9382 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9385 /* VEX_LEN_0F59_P_3 */
9387 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9388 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9391 /* VEX_LEN_0F5A_P_1 */
9393 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9394 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9397 /* VEX_LEN_0F5A_P_3 */
9399 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9400 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9403 /* VEX_LEN_0F5C_P_1 */
9405 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9406 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9409 /* VEX_LEN_0F5C_P_3 */
9411 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9412 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9415 /* VEX_LEN_0F5D_P_1 */
9417 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9418 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9421 /* VEX_LEN_0F5D_P_3 */
9423 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9424 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9427 /* VEX_LEN_0F5E_P_1 */
9429 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9430 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9433 /* VEX_LEN_0F5E_P_3 */
9435 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9436 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9439 /* VEX_LEN_0F5F_P_1 */
9441 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9442 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9445 /* VEX_LEN_0F5F_P_3 */
9447 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9448 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9451 /* VEX_LEN_0F6E_P_2 */
9453 { "vmovK", { XMScalar, Edq } },
9454 { "vmovK", { XMScalar, Edq } },
9457 /* VEX_LEN_0F7E_P_1 */
9459 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9460 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9463 /* VEX_LEN_0F7E_P_2 */
9465 { "vmovK", { Edq, XMScalar } },
9466 { "vmovK", { Edq, XMScalar } },
9469 /* VEX_LEN_0F90_P_0 */
9471 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9474 /* VEX_LEN_0F91_P_0 */
9476 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9479 /* VEX_LEN_0F92_P_0 */
9481 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9484 /* VEX_LEN_0F93_P_0 */
9486 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9489 /* VEX_LEN_0F98_P_0 */
9491 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9494 /* VEX_LEN_0FAE_R_2_M_0 */
9496 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9499 /* VEX_LEN_0FAE_R_3_M_0 */
9501 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9504 /* VEX_LEN_0FC2_P_1 */
9506 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9507 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9510 /* VEX_LEN_0FC2_P_3 */
9512 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9513 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9516 /* VEX_LEN_0FC4_P_2 */
9518 { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9521 /* VEX_LEN_0FC5_P_2 */
9523 { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9526 /* VEX_LEN_0FD6_P_2 */
9528 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9529 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9532 /* VEX_LEN_0FF7_P_2 */
9534 { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9537 /* VEX_LEN_0F3816_P_2 */
9540 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9543 /* VEX_LEN_0F3819_P_2 */
9546 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9549 /* VEX_LEN_0F381A_P_2_M_0 */
9552 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9555 /* VEX_LEN_0F3836_P_2 */
9558 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9561 /* VEX_LEN_0F3841_P_2 */
9563 { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9566 /* VEX_LEN_0F385A_P_2_M_0 */
9569 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9572 /* VEX_LEN_0F38DB_P_2 */
9574 { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9577 /* VEX_LEN_0F38DC_P_2 */
9579 { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9582 /* VEX_LEN_0F38DD_P_2 */
9584 { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9587 /* VEX_LEN_0F38DE_P_2 */
9589 { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9592 /* VEX_LEN_0F38DF_P_2 */
9594 { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9597 /* VEX_LEN_0F38F2_P_0 */
9599 { "andnS", { Gdq, VexGdq, Edq } },
9602 /* VEX_LEN_0F38F3_R_1_P_0 */
9604 { "blsrS", { VexGdq, Edq } },
9607 /* VEX_LEN_0F38F3_R_2_P_0 */
9609 { "blsmskS", { VexGdq, Edq } },
9612 /* VEX_LEN_0F38F3_R_3_P_0 */
9614 { "blsiS", { VexGdq, Edq } },
9617 /* VEX_LEN_0F38F5_P_0 */
9619 { "bzhiS", { Gdq, Edq, VexGdq } },
9622 /* VEX_LEN_0F38F5_P_1 */
9624 { "pextS", { Gdq, VexGdq, Edq } },
9627 /* VEX_LEN_0F38F5_P_3 */
9629 { "pdepS", { Gdq, VexGdq, Edq } },
9632 /* VEX_LEN_0F38F6_P_3 */
9634 { "mulxS", { Gdq, VexGdq, Edq } },
9637 /* VEX_LEN_0F38F7_P_0 */
9639 { "bextrS", { Gdq, Edq, VexGdq } },
9642 /* VEX_LEN_0F38F7_P_1 */
9644 { "sarxS", { Gdq, Edq, VexGdq } },
9647 /* VEX_LEN_0F38F7_P_2 */
9649 { "shlxS", { Gdq, Edq, VexGdq } },
9652 /* VEX_LEN_0F38F7_P_3 */
9654 { "shrxS", { Gdq, Edq, VexGdq } },
9657 /* VEX_LEN_0F3A00_P_2 */
9660 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9663 /* VEX_LEN_0F3A01_P_2 */
9666 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9669 /* VEX_LEN_0F3A06_P_2 */
9672 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9675 /* VEX_LEN_0F3A0A_P_2 */
9677 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9678 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9681 /* VEX_LEN_0F3A0B_P_2 */
9683 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9684 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9687 /* VEX_LEN_0F3A14_P_2 */
9689 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9692 /* VEX_LEN_0F3A15_P_2 */
9694 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9697 /* VEX_LEN_0F3A16_P_2 */
9699 { "vpextrK", { Edq, XM, Ib } },
9702 /* VEX_LEN_0F3A17_P_2 */
9704 { "vextractps", { Edqd, XM, Ib } },
9707 /* VEX_LEN_0F3A18_P_2 */
9710 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9713 /* VEX_LEN_0F3A19_P_2 */
9716 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9719 /* VEX_LEN_0F3A20_P_2 */
9721 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
9724 /* VEX_LEN_0F3A21_P_2 */
9726 { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
9729 /* VEX_LEN_0F3A22_P_2 */
9731 { "vpinsrK", { XM, Vex128, Edq, Ib } },
9734 /* VEX_LEN_0F3A30_P_2 */
9736 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9739 /* VEX_LEN_0F3A32_P_2 */
9741 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9744 /* VEX_LEN_0F3A38_P_2 */
9747 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9750 /* VEX_LEN_0F3A39_P_2 */
9753 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9756 /* VEX_LEN_0F3A41_P_2 */
9758 { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
9761 /* VEX_LEN_0F3A44_P_2 */
9763 { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
9766 /* VEX_LEN_0F3A46_P_2 */
9769 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9772 /* VEX_LEN_0F3A60_P_2 */
9774 { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
9777 /* VEX_LEN_0F3A61_P_2 */
9779 { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
9782 /* VEX_LEN_0F3A62_P_2 */
9784 { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
9787 /* VEX_LEN_0F3A63_P_2 */
9789 { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
9792 /* VEX_LEN_0F3A6A_P_2 */
9794 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9797 /* VEX_LEN_0F3A6B_P_2 */
9799 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9802 /* VEX_LEN_0F3A6E_P_2 */
9804 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9807 /* VEX_LEN_0F3A6F_P_2 */
9809 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9812 /* VEX_LEN_0F3A7A_P_2 */
9814 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9817 /* VEX_LEN_0F3A7B_P_2 */
9819 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9822 /* VEX_LEN_0F3A7E_P_2 */
9824 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9827 /* VEX_LEN_0F3A7F_P_2 */
9829 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9832 /* VEX_LEN_0F3ADF_P_2 */
9834 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
9837 /* VEX_LEN_0F3AF0_P_3 */
9839 { "rorxS", { Gdq, Edq, Ib } },
9842 /* VEX_LEN_0FXOP_08_CC */
9844 { "vpcomb", { XM, Vex128, EXx, Ib } },
9847 /* VEX_LEN_0FXOP_08_CD */
9849 { "vpcomw", { XM, Vex128, EXx, Ib } },
9852 /* VEX_LEN_0FXOP_08_CE */
9854 { "vpcomd", { XM, Vex128, EXx, Ib } },
9857 /* VEX_LEN_0FXOP_08_CF */
9859 { "vpcomq", { XM, Vex128, EXx, Ib } },
9862 /* VEX_LEN_0FXOP_08_EC */
9864 { "vpcomub", { XM, Vex128, EXx, Ib } },
9867 /* VEX_LEN_0FXOP_08_ED */
9869 { "vpcomuw", { XM, Vex128, EXx, Ib } },
9872 /* VEX_LEN_0FXOP_08_EE */
9874 { "vpcomud", { XM, Vex128, EXx, Ib } },
9877 /* VEX_LEN_0FXOP_08_EF */
9879 { "vpcomuq", { XM, Vex128, EXx, Ib } },
9882 /* VEX_LEN_0FXOP_09_80 */
9884 { "vfrczps", { XM, EXxmm } },
9885 { "vfrczps", { XM, EXymmq } },
9888 /* VEX_LEN_0FXOP_09_81 */
9890 { "vfrczpd", { XM, EXxmm } },
9891 { "vfrczpd", { XM, EXymmq } },
9895 static const struct dis386 vex_w_table[][2] = {
9897 /* VEX_W_0F10_P_0 */
9898 { "vmovups", { XM, EXx } },
9901 /* VEX_W_0F10_P_1 */
9902 { "vmovss", { XMVexScalar, VexScalar, EXdScalar } },
9905 /* VEX_W_0F10_P_2 */
9906 { "vmovupd", { XM, EXx } },
9909 /* VEX_W_0F10_P_3 */
9910 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } },
9913 /* VEX_W_0F11_P_0 */
9914 { "vmovups", { EXxS, XM } },
9917 /* VEX_W_0F11_P_1 */
9918 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } },
9921 /* VEX_W_0F11_P_2 */
9922 { "vmovupd", { EXxS, XM } },
9925 /* VEX_W_0F11_P_3 */
9926 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } },
9929 /* VEX_W_0F12_P_0_M_0 */
9930 { "vmovlps", { XM, Vex128, EXq } },
9933 /* VEX_W_0F12_P_0_M_1 */
9934 { "vmovhlps", { XM, Vex128, EXq } },
9937 /* VEX_W_0F12_P_1 */
9938 { "vmovsldup", { XM, EXx } },
9941 /* VEX_W_0F12_P_2 */
9942 { "vmovlpd", { XM, Vex128, EXq } },
9945 /* VEX_W_0F12_P_3 */
9946 { "vmovddup", { XM, EXymmq } },
9949 /* VEX_W_0F13_M_0 */
9950 { "vmovlpX", { EXq, XM } },
9954 { "vunpcklpX", { XM, Vex, EXx } },
9958 { "vunpckhpX", { XM, Vex, EXx } },
9961 /* VEX_W_0F16_P_0_M_0 */
9962 { "vmovhps", { XM, Vex128, EXq } },
9965 /* VEX_W_0F16_P_0_M_1 */
9966 { "vmovlhps", { XM, Vex128, EXq } },
9969 /* VEX_W_0F16_P_1 */
9970 { "vmovshdup", { XM, EXx } },
9973 /* VEX_W_0F16_P_2 */
9974 { "vmovhpd", { XM, Vex128, EXq } },
9977 /* VEX_W_0F17_M_0 */
9978 { "vmovhpX", { EXq, XM } },
9982 { "vmovapX", { XM, EXx } },
9986 { "vmovapX", { EXxS, XM } },
9989 /* VEX_W_0F2B_M_0 */
9990 { "vmovntpX", { Mx, XM } },
9993 /* VEX_W_0F2E_P_0 */
9994 { "vucomiss", { XMScalar, EXdScalar } },
9997 /* VEX_W_0F2E_P_2 */
9998 { "vucomisd", { XMScalar, EXqScalar } },
10001 /* VEX_W_0F2F_P_0 */
10002 { "vcomiss", { XMScalar, EXdScalar } },
10005 /* VEX_W_0F2F_P_2 */
10006 { "vcomisd", { XMScalar, EXqScalar } },
10009 /* VEX_W_0F41_P_0_LEN_1 */
10010 { "kandw", { MaskG, MaskVex, MaskR } },
10013 /* VEX_W_0F42_P_0_LEN_1 */
10014 { "kandnw", { MaskG, MaskVex, MaskR } },
10017 /* VEX_W_0F44_P_0_LEN_0 */
10018 { "knotw", { MaskG, MaskR } },
10021 /* VEX_W_0F45_P_0_LEN_1 */
10022 { "korw", { MaskG, MaskVex, MaskR } },
10025 /* VEX_W_0F46_P_0_LEN_1 */
10026 { "kxnorw", { MaskG, MaskVex, MaskR } },
10029 /* VEX_W_0F47_P_0_LEN_1 */
10030 { "kxorw", { MaskG, MaskVex, MaskR } },
10033 /* VEX_W_0F4B_P_2_LEN_1 */
10034 { "kunpckbw", { MaskG, MaskVex, MaskR } },
10037 /* VEX_W_0F50_M_0 */
10038 { "vmovmskpX", { Gdq, XS } },
10041 /* VEX_W_0F51_P_0 */
10042 { "vsqrtps", { XM, EXx } },
10045 /* VEX_W_0F51_P_1 */
10046 { "vsqrtss", { XMScalar, VexScalar, EXdScalar } },
10049 /* VEX_W_0F51_P_2 */
10050 { "vsqrtpd", { XM, EXx } },
10053 /* VEX_W_0F51_P_3 */
10054 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar } },
10057 /* VEX_W_0F52_P_0 */
10058 { "vrsqrtps", { XM, EXx } },
10061 /* VEX_W_0F52_P_1 */
10062 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar } },
10065 /* VEX_W_0F53_P_0 */
10066 { "vrcpps", { XM, EXx } },
10069 /* VEX_W_0F53_P_1 */
10070 { "vrcpss", { XMScalar, VexScalar, EXdScalar } },
10073 /* VEX_W_0F58_P_0 */
10074 { "vaddps", { XM, Vex, EXx } },
10077 /* VEX_W_0F58_P_1 */
10078 { "vaddss", { XMScalar, VexScalar, EXdScalar } },
10081 /* VEX_W_0F58_P_2 */
10082 { "vaddpd", { XM, Vex, EXx } },
10085 /* VEX_W_0F58_P_3 */
10086 { "vaddsd", { XMScalar, VexScalar, EXqScalar } },
10089 /* VEX_W_0F59_P_0 */
10090 { "vmulps", { XM, Vex, EXx } },
10093 /* VEX_W_0F59_P_1 */
10094 { "vmulss", { XMScalar, VexScalar, EXdScalar } },
10097 /* VEX_W_0F59_P_2 */
10098 { "vmulpd", { XM, Vex, EXx } },
10101 /* VEX_W_0F59_P_3 */
10102 { "vmulsd", { XMScalar, VexScalar, EXqScalar } },
10105 /* VEX_W_0F5A_P_0 */
10106 { "vcvtps2pd", { XM, EXxmmq } },
10109 /* VEX_W_0F5A_P_1 */
10110 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar } },
10113 /* VEX_W_0F5A_P_3 */
10114 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar } },
10117 /* VEX_W_0F5B_P_0 */
10118 { "vcvtdq2ps", { XM, EXx } },
10121 /* VEX_W_0F5B_P_1 */
10122 { "vcvttps2dq", { XM, EXx } },
10125 /* VEX_W_0F5B_P_2 */
10126 { "vcvtps2dq", { XM, EXx } },
10129 /* VEX_W_0F5C_P_0 */
10130 { "vsubps", { XM, Vex, EXx } },
10133 /* VEX_W_0F5C_P_1 */
10134 { "vsubss", { XMScalar, VexScalar, EXdScalar } },
10137 /* VEX_W_0F5C_P_2 */
10138 { "vsubpd", { XM, Vex, EXx } },
10141 /* VEX_W_0F5C_P_3 */
10142 { "vsubsd", { XMScalar, VexScalar, EXqScalar } },
10145 /* VEX_W_0F5D_P_0 */
10146 { "vminps", { XM, Vex, EXx } },
10149 /* VEX_W_0F5D_P_1 */
10150 { "vminss", { XMScalar, VexScalar, EXdScalar } },
10153 /* VEX_W_0F5D_P_2 */
10154 { "vminpd", { XM, Vex, EXx } },
10157 /* VEX_W_0F5D_P_3 */
10158 { "vminsd", { XMScalar, VexScalar, EXqScalar } },
10161 /* VEX_W_0F5E_P_0 */
10162 { "vdivps", { XM, Vex, EXx } },
10165 /* VEX_W_0F5E_P_1 */
10166 { "vdivss", { XMScalar, VexScalar, EXdScalar } },
10169 /* VEX_W_0F5E_P_2 */
10170 { "vdivpd", { XM, Vex, EXx } },
10173 /* VEX_W_0F5E_P_3 */
10174 { "vdivsd", { XMScalar, VexScalar, EXqScalar } },
10177 /* VEX_W_0F5F_P_0 */
10178 { "vmaxps", { XM, Vex, EXx } },
10181 /* VEX_W_0F5F_P_1 */
10182 { "vmaxss", { XMScalar, VexScalar, EXdScalar } },
10185 /* VEX_W_0F5F_P_2 */
10186 { "vmaxpd", { XM, Vex, EXx } },
10189 /* VEX_W_0F5F_P_3 */
10190 { "vmaxsd", { XMScalar, VexScalar, EXqScalar } },
10193 /* VEX_W_0F60_P_2 */
10194 { "vpunpcklbw", { XM, Vex, EXx } },
10197 /* VEX_W_0F61_P_2 */
10198 { "vpunpcklwd", { XM, Vex, EXx } },
10201 /* VEX_W_0F62_P_2 */
10202 { "vpunpckldq", { XM, Vex, EXx } },
10205 /* VEX_W_0F63_P_2 */
10206 { "vpacksswb", { XM, Vex, EXx } },
10209 /* VEX_W_0F64_P_2 */
10210 { "vpcmpgtb", { XM, Vex, EXx } },
10213 /* VEX_W_0F65_P_2 */
10214 { "vpcmpgtw", { XM, Vex, EXx } },
10217 /* VEX_W_0F66_P_2 */
10218 { "vpcmpgtd", { XM, Vex, EXx } },
10221 /* VEX_W_0F67_P_2 */
10222 { "vpackuswb", { XM, Vex, EXx } },
10225 /* VEX_W_0F68_P_2 */
10226 { "vpunpckhbw", { XM, Vex, EXx } },
10229 /* VEX_W_0F69_P_2 */
10230 { "vpunpckhwd", { XM, Vex, EXx } },
10233 /* VEX_W_0F6A_P_2 */
10234 { "vpunpckhdq", { XM, Vex, EXx } },
10237 /* VEX_W_0F6B_P_2 */
10238 { "vpackssdw", { XM, Vex, EXx } },
10241 /* VEX_W_0F6C_P_2 */
10242 { "vpunpcklqdq", { XM, Vex, EXx } },
10245 /* VEX_W_0F6D_P_2 */
10246 { "vpunpckhqdq", { XM, Vex, EXx } },
10249 /* VEX_W_0F6F_P_1 */
10250 { "vmovdqu", { XM, EXx } },
10253 /* VEX_W_0F6F_P_2 */
10254 { "vmovdqa", { XM, EXx } },
10257 /* VEX_W_0F70_P_1 */
10258 { "vpshufhw", { XM, EXx, Ib } },
10261 /* VEX_W_0F70_P_2 */
10262 { "vpshufd", { XM, EXx, Ib } },
10265 /* VEX_W_0F70_P_3 */
10266 { "vpshuflw", { XM, EXx, Ib } },
10269 /* VEX_W_0F71_R_2_P_2 */
10270 { "vpsrlw", { Vex, XS, Ib } },
10273 /* VEX_W_0F71_R_4_P_2 */
10274 { "vpsraw", { Vex, XS, Ib } },
10277 /* VEX_W_0F71_R_6_P_2 */
10278 { "vpsllw", { Vex, XS, Ib } },
10281 /* VEX_W_0F72_R_2_P_2 */
10282 { "vpsrld", { Vex, XS, Ib } },
10285 /* VEX_W_0F72_R_4_P_2 */
10286 { "vpsrad", { Vex, XS, Ib } },
10289 /* VEX_W_0F72_R_6_P_2 */
10290 { "vpslld", { Vex, XS, Ib } },
10293 /* VEX_W_0F73_R_2_P_2 */
10294 { "vpsrlq", { Vex, XS, Ib } },
10297 /* VEX_W_0F73_R_3_P_2 */
10298 { "vpsrldq", { Vex, XS, Ib } },
10301 /* VEX_W_0F73_R_6_P_2 */
10302 { "vpsllq", { Vex, XS, Ib } },
10305 /* VEX_W_0F73_R_7_P_2 */
10306 { "vpslldq", { Vex, XS, Ib } },
10309 /* VEX_W_0F74_P_2 */
10310 { "vpcmpeqb", { XM, Vex, EXx } },
10313 /* VEX_W_0F75_P_2 */
10314 { "vpcmpeqw", { XM, Vex, EXx } },
10317 /* VEX_W_0F76_P_2 */
10318 { "vpcmpeqd", { XM, Vex, EXx } },
10321 /* VEX_W_0F77_P_0 */
10325 /* VEX_W_0F7C_P_2 */
10326 { "vhaddpd", { XM, Vex, EXx } },
10329 /* VEX_W_0F7C_P_3 */
10330 { "vhaddps", { XM, Vex, EXx } },
10333 /* VEX_W_0F7D_P_2 */
10334 { "vhsubpd", { XM, Vex, EXx } },
10337 /* VEX_W_0F7D_P_3 */
10338 { "vhsubps", { XM, Vex, EXx } },
10341 /* VEX_W_0F7E_P_1 */
10342 { "vmovq", { XMScalar, EXqScalar } },
10345 /* VEX_W_0F7F_P_1 */
10346 { "vmovdqu", { EXxS, XM } },
10349 /* VEX_W_0F7F_P_2 */
10350 { "vmovdqa", { EXxS, XM } },
10353 /* VEX_W_0F90_P_0_LEN_0 */
10354 { "kmovw", { MaskG, MaskE } },
10357 /* VEX_W_0F91_P_0_LEN_0 */
10358 { "kmovw", { Ew, MaskG } },
10361 /* VEX_W_0F92_P_0_LEN_0 */
10362 { "kmovw", { MaskG, Rdq } },
10365 /* VEX_W_0F93_P_0_LEN_0 */
10366 { "kmovw", { Gdq, MaskR } },
10369 /* VEX_W_0F98_P_0_LEN_0 */
10370 { "kortestw", { MaskG, MaskR } },
10373 /* VEX_W_0FAE_R_2_M_0 */
10374 { "vldmxcsr", { Md } },
10377 /* VEX_W_0FAE_R_3_M_0 */
10378 { "vstmxcsr", { Md } },
10381 /* VEX_W_0FC2_P_0 */
10382 { "vcmpps", { XM, Vex, EXx, VCMP } },
10385 /* VEX_W_0FC2_P_1 */
10386 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP } },
10389 /* VEX_W_0FC2_P_2 */
10390 { "vcmppd", { XM, Vex, EXx, VCMP } },
10393 /* VEX_W_0FC2_P_3 */
10394 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP } },
10397 /* VEX_W_0FC4_P_2 */
10398 { "vpinsrw", { XM, Vex128, Edqw, Ib } },
10401 /* VEX_W_0FC5_P_2 */
10402 { "vpextrw", { Gdq, XS, Ib } },
10405 /* VEX_W_0FD0_P_2 */
10406 { "vaddsubpd", { XM, Vex, EXx } },
10409 /* VEX_W_0FD0_P_3 */
10410 { "vaddsubps", { XM, Vex, EXx } },
10413 /* VEX_W_0FD1_P_2 */
10414 { "vpsrlw", { XM, Vex, EXxmm } },
10417 /* VEX_W_0FD2_P_2 */
10418 { "vpsrld", { XM, Vex, EXxmm } },
10421 /* VEX_W_0FD3_P_2 */
10422 { "vpsrlq", { XM, Vex, EXxmm } },
10425 /* VEX_W_0FD4_P_2 */
10426 { "vpaddq", { XM, Vex, EXx } },
10429 /* VEX_W_0FD5_P_2 */
10430 { "vpmullw", { XM, Vex, EXx } },
10433 /* VEX_W_0FD6_P_2 */
10434 { "vmovq", { EXqScalarS, XMScalar } },
10437 /* VEX_W_0FD7_P_2_M_1 */
10438 { "vpmovmskb", { Gdq, XS } },
10441 /* VEX_W_0FD8_P_2 */
10442 { "vpsubusb", { XM, Vex, EXx } },
10445 /* VEX_W_0FD9_P_2 */
10446 { "vpsubusw", { XM, Vex, EXx } },
10449 /* VEX_W_0FDA_P_2 */
10450 { "vpminub", { XM, Vex, EXx } },
10453 /* VEX_W_0FDB_P_2 */
10454 { "vpand", { XM, Vex, EXx } },
10457 /* VEX_W_0FDC_P_2 */
10458 { "vpaddusb", { XM, Vex, EXx } },
10461 /* VEX_W_0FDD_P_2 */
10462 { "vpaddusw", { XM, Vex, EXx } },
10465 /* VEX_W_0FDE_P_2 */
10466 { "vpmaxub", { XM, Vex, EXx } },
10469 /* VEX_W_0FDF_P_2 */
10470 { "vpandn", { XM, Vex, EXx } },
10473 /* VEX_W_0FE0_P_2 */
10474 { "vpavgb", { XM, Vex, EXx } },
10477 /* VEX_W_0FE1_P_2 */
10478 { "vpsraw", { XM, Vex, EXxmm } },
10481 /* VEX_W_0FE2_P_2 */
10482 { "vpsrad", { XM, Vex, EXxmm } },
10485 /* VEX_W_0FE3_P_2 */
10486 { "vpavgw", { XM, Vex, EXx } },
10489 /* VEX_W_0FE4_P_2 */
10490 { "vpmulhuw", { XM, Vex, EXx } },
10493 /* VEX_W_0FE5_P_2 */
10494 { "vpmulhw", { XM, Vex, EXx } },
10497 /* VEX_W_0FE6_P_1 */
10498 { "vcvtdq2pd", { XM, EXxmmq } },
10501 /* VEX_W_0FE6_P_2 */
10502 { "vcvttpd2dq%XY", { XMM, EXx } },
10505 /* VEX_W_0FE6_P_3 */
10506 { "vcvtpd2dq%XY", { XMM, EXx } },
10509 /* VEX_W_0FE7_P_2_M_0 */
10510 { "vmovntdq", { Mx, XM } },
10513 /* VEX_W_0FE8_P_2 */
10514 { "vpsubsb", { XM, Vex, EXx } },
10517 /* VEX_W_0FE9_P_2 */
10518 { "vpsubsw", { XM, Vex, EXx } },
10521 /* VEX_W_0FEA_P_2 */
10522 { "vpminsw", { XM, Vex, EXx } },
10525 /* VEX_W_0FEB_P_2 */
10526 { "vpor", { XM, Vex, EXx } },
10529 /* VEX_W_0FEC_P_2 */
10530 { "vpaddsb", { XM, Vex, EXx } },
10533 /* VEX_W_0FED_P_2 */
10534 { "vpaddsw", { XM, Vex, EXx } },
10537 /* VEX_W_0FEE_P_2 */
10538 { "vpmaxsw", { XM, Vex, EXx } },
10541 /* VEX_W_0FEF_P_2 */
10542 { "vpxor", { XM, Vex, EXx } },
10545 /* VEX_W_0FF0_P_3_M_0 */
10546 { "vlddqu", { XM, M } },
10549 /* VEX_W_0FF1_P_2 */
10550 { "vpsllw", { XM, Vex, EXxmm } },
10553 /* VEX_W_0FF2_P_2 */
10554 { "vpslld", { XM, Vex, EXxmm } },
10557 /* VEX_W_0FF3_P_2 */
10558 { "vpsllq", { XM, Vex, EXxmm } },
10561 /* VEX_W_0FF4_P_2 */
10562 { "vpmuludq", { XM, Vex, EXx } },
10565 /* VEX_W_0FF5_P_2 */
10566 { "vpmaddwd", { XM, Vex, EXx } },
10569 /* VEX_W_0FF6_P_2 */
10570 { "vpsadbw", { XM, Vex, EXx } },
10573 /* VEX_W_0FF7_P_2 */
10574 { "vmaskmovdqu", { XM, XS } },
10577 /* VEX_W_0FF8_P_2 */
10578 { "vpsubb", { XM, Vex, EXx } },
10581 /* VEX_W_0FF9_P_2 */
10582 { "vpsubw", { XM, Vex, EXx } },
10585 /* VEX_W_0FFA_P_2 */
10586 { "vpsubd", { XM, Vex, EXx } },
10589 /* VEX_W_0FFB_P_2 */
10590 { "vpsubq", { XM, Vex, EXx } },
10593 /* VEX_W_0FFC_P_2 */
10594 { "vpaddb", { XM, Vex, EXx } },
10597 /* VEX_W_0FFD_P_2 */
10598 { "vpaddw", { XM, Vex, EXx } },
10601 /* VEX_W_0FFE_P_2 */
10602 { "vpaddd", { XM, Vex, EXx } },
10605 /* VEX_W_0F3800_P_2 */
10606 { "vpshufb", { XM, Vex, EXx } },
10609 /* VEX_W_0F3801_P_2 */
10610 { "vphaddw", { XM, Vex, EXx } },
10613 /* VEX_W_0F3802_P_2 */
10614 { "vphaddd", { XM, Vex, EXx } },
10617 /* VEX_W_0F3803_P_2 */
10618 { "vphaddsw", { XM, Vex, EXx } },
10621 /* VEX_W_0F3804_P_2 */
10622 { "vpmaddubsw", { XM, Vex, EXx } },
10625 /* VEX_W_0F3805_P_2 */
10626 { "vphsubw", { XM, Vex, EXx } },
10629 /* VEX_W_0F3806_P_2 */
10630 { "vphsubd", { XM, Vex, EXx } },
10633 /* VEX_W_0F3807_P_2 */
10634 { "vphsubsw", { XM, Vex, EXx } },
10637 /* VEX_W_0F3808_P_2 */
10638 { "vpsignb", { XM, Vex, EXx } },
10641 /* VEX_W_0F3809_P_2 */
10642 { "vpsignw", { XM, Vex, EXx } },
10645 /* VEX_W_0F380A_P_2 */
10646 { "vpsignd", { XM, Vex, EXx } },
10649 /* VEX_W_0F380B_P_2 */
10650 { "vpmulhrsw", { XM, Vex, EXx } },
10653 /* VEX_W_0F380C_P_2 */
10654 { "vpermilps", { XM, Vex, EXx } },
10657 /* VEX_W_0F380D_P_2 */
10658 { "vpermilpd", { XM, Vex, EXx } },
10661 /* VEX_W_0F380E_P_2 */
10662 { "vtestps", { XM, EXx } },
10665 /* VEX_W_0F380F_P_2 */
10666 { "vtestpd", { XM, EXx } },
10669 /* VEX_W_0F3816_P_2 */
10670 { "vpermps", { XM, Vex, EXx } },
10673 /* VEX_W_0F3817_P_2 */
10674 { "vptest", { XM, EXx } },
10677 /* VEX_W_0F3818_P_2 */
10678 { "vbroadcastss", { XM, EXxmm_md } },
10681 /* VEX_W_0F3819_P_2 */
10682 { "vbroadcastsd", { XM, EXxmm_mq } },
10685 /* VEX_W_0F381A_P_2_M_0 */
10686 { "vbroadcastf128", { XM, Mxmm } },
10689 /* VEX_W_0F381C_P_2 */
10690 { "vpabsb", { XM, EXx } },
10693 /* VEX_W_0F381D_P_2 */
10694 { "vpabsw", { XM, EXx } },
10697 /* VEX_W_0F381E_P_2 */
10698 { "vpabsd", { XM, EXx } },
10701 /* VEX_W_0F3820_P_2 */
10702 { "vpmovsxbw", { XM, EXxmmq } },
10705 /* VEX_W_0F3821_P_2 */
10706 { "vpmovsxbd", { XM, EXxmmqd } },
10709 /* VEX_W_0F3822_P_2 */
10710 { "vpmovsxbq", { XM, EXxmmdw } },
10713 /* VEX_W_0F3823_P_2 */
10714 { "vpmovsxwd", { XM, EXxmmq } },
10717 /* VEX_W_0F3824_P_2 */
10718 { "vpmovsxwq", { XM, EXxmmqd } },
10721 /* VEX_W_0F3825_P_2 */
10722 { "vpmovsxdq", { XM, EXxmmq } },
10725 /* VEX_W_0F3828_P_2 */
10726 { "vpmuldq", { XM, Vex, EXx } },
10729 /* VEX_W_0F3829_P_2 */
10730 { "vpcmpeqq", { XM, Vex, EXx } },
10733 /* VEX_W_0F382A_P_2_M_0 */
10734 { "vmovntdqa", { XM, Mx } },
10737 /* VEX_W_0F382B_P_2 */
10738 { "vpackusdw", { XM, Vex, EXx } },
10741 /* VEX_W_0F382C_P_2_M_0 */
10742 { "vmaskmovps", { XM, Vex, Mx } },
10745 /* VEX_W_0F382D_P_2_M_0 */
10746 { "vmaskmovpd", { XM, Vex, Mx } },
10749 /* VEX_W_0F382E_P_2_M_0 */
10750 { "vmaskmovps", { Mx, Vex, XM } },
10753 /* VEX_W_0F382F_P_2_M_0 */
10754 { "vmaskmovpd", { Mx, Vex, XM } },
10757 /* VEX_W_0F3830_P_2 */
10758 { "vpmovzxbw", { XM, EXxmmq } },
10761 /* VEX_W_0F3831_P_2 */
10762 { "vpmovzxbd", { XM, EXxmmqd } },
10765 /* VEX_W_0F3832_P_2 */
10766 { "vpmovzxbq", { XM, EXxmmdw } },
10769 /* VEX_W_0F3833_P_2 */
10770 { "vpmovzxwd", { XM, EXxmmq } },
10773 /* VEX_W_0F3834_P_2 */
10774 { "vpmovzxwq", { XM, EXxmmqd } },
10777 /* VEX_W_0F3835_P_2 */
10778 { "vpmovzxdq", { XM, EXxmmq } },
10781 /* VEX_W_0F3836_P_2 */
10782 { "vpermd", { XM, Vex, EXx } },
10785 /* VEX_W_0F3837_P_2 */
10786 { "vpcmpgtq", { XM, Vex, EXx } },
10789 /* VEX_W_0F3838_P_2 */
10790 { "vpminsb", { XM, Vex, EXx } },
10793 /* VEX_W_0F3839_P_2 */
10794 { "vpminsd", { XM, Vex, EXx } },
10797 /* VEX_W_0F383A_P_2 */
10798 { "vpminuw", { XM, Vex, EXx } },
10801 /* VEX_W_0F383B_P_2 */
10802 { "vpminud", { XM, Vex, EXx } },
10805 /* VEX_W_0F383C_P_2 */
10806 { "vpmaxsb", { XM, Vex, EXx } },
10809 /* VEX_W_0F383D_P_2 */
10810 { "vpmaxsd", { XM, Vex, EXx } },
10813 /* VEX_W_0F383E_P_2 */
10814 { "vpmaxuw", { XM, Vex, EXx } },
10817 /* VEX_W_0F383F_P_2 */
10818 { "vpmaxud", { XM, Vex, EXx } },
10821 /* VEX_W_0F3840_P_2 */
10822 { "vpmulld", { XM, Vex, EXx } },
10825 /* VEX_W_0F3841_P_2 */
10826 { "vphminposuw", { XM, EXx } },
10829 /* VEX_W_0F3846_P_2 */
10830 { "vpsravd", { XM, Vex, EXx } },
10833 /* VEX_W_0F3858_P_2 */
10834 { "vpbroadcastd", { XM, EXxmm_md } },
10837 /* VEX_W_0F3859_P_2 */
10838 { "vpbroadcastq", { XM, EXxmm_mq } },
10841 /* VEX_W_0F385A_P_2_M_0 */
10842 { "vbroadcasti128", { XM, Mxmm } },
10845 /* VEX_W_0F3878_P_2 */
10846 { "vpbroadcastb", { XM, EXxmm_mb } },
10849 /* VEX_W_0F3879_P_2 */
10850 { "vpbroadcastw", { XM, EXxmm_mw } },
10853 /* VEX_W_0F38DB_P_2 */
10854 { "vaesimc", { XM, EXx } },
10857 /* VEX_W_0F38DC_P_2 */
10858 { "vaesenc", { XM, Vex128, EXx } },
10861 /* VEX_W_0F38DD_P_2 */
10862 { "vaesenclast", { XM, Vex128, EXx } },
10865 /* VEX_W_0F38DE_P_2 */
10866 { "vaesdec", { XM, Vex128, EXx } },
10869 /* VEX_W_0F38DF_P_2 */
10870 { "vaesdeclast", { XM, Vex128, EXx } },
10873 /* VEX_W_0F3A00_P_2 */
10875 { "vpermq", { XM, EXx, Ib } },
10878 /* VEX_W_0F3A01_P_2 */
10880 { "vpermpd", { XM, EXx, Ib } },
10883 /* VEX_W_0F3A02_P_2 */
10884 { "vpblendd", { XM, Vex, EXx, Ib } },
10887 /* VEX_W_0F3A04_P_2 */
10888 { "vpermilps", { XM, EXx, Ib } },
10891 /* VEX_W_0F3A05_P_2 */
10892 { "vpermilpd", { XM, EXx, Ib } },
10895 /* VEX_W_0F3A06_P_2 */
10896 { "vperm2f128", { XM, Vex256, EXx, Ib } },
10899 /* VEX_W_0F3A08_P_2 */
10900 { "vroundps", { XM, EXx, Ib } },
10903 /* VEX_W_0F3A09_P_2 */
10904 { "vroundpd", { XM, EXx, Ib } },
10907 /* VEX_W_0F3A0A_P_2 */
10908 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib } },
10911 /* VEX_W_0F3A0B_P_2 */
10912 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib } },
10915 /* VEX_W_0F3A0C_P_2 */
10916 { "vblendps", { XM, Vex, EXx, Ib } },
10919 /* VEX_W_0F3A0D_P_2 */
10920 { "vblendpd", { XM, Vex, EXx, Ib } },
10923 /* VEX_W_0F3A0E_P_2 */
10924 { "vpblendw", { XM, Vex, EXx, Ib } },
10927 /* VEX_W_0F3A0F_P_2 */
10928 { "vpalignr", { XM, Vex, EXx, Ib } },
10931 /* VEX_W_0F3A14_P_2 */
10932 { "vpextrb", { Edqb, XM, Ib } },
10935 /* VEX_W_0F3A15_P_2 */
10936 { "vpextrw", { Edqw, XM, Ib } },
10939 /* VEX_W_0F3A18_P_2 */
10940 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },
10943 /* VEX_W_0F3A19_P_2 */
10944 { "vextractf128", { EXxmm, XM, Ib } },
10947 /* VEX_W_0F3A20_P_2 */
10948 { "vpinsrb", { XM, Vex128, Edqb, Ib } },
10951 /* VEX_W_0F3A21_P_2 */
10952 { "vinsertps", { XM, Vex128, EXd, Ib } },
10955 /* VEX_W_0F3A30_P_2 */
10957 { "kshiftrw", { MaskG, MaskR, Ib } },
10960 /* VEX_W_0F3A32_P_2 */
10962 { "kshiftlw", { MaskG, MaskR, Ib } },
10965 /* VEX_W_0F3A38_P_2 */
10966 { "vinserti128", { XM, Vex256, EXxmm, Ib } },
10969 /* VEX_W_0F3A39_P_2 */
10970 { "vextracti128", { EXxmm, XM, Ib } },
10973 /* VEX_W_0F3A40_P_2 */
10974 { "vdpps", { XM, Vex, EXx, Ib } },
10977 /* VEX_W_0F3A41_P_2 */
10978 { "vdppd", { XM, Vex128, EXx, Ib } },
10981 /* VEX_W_0F3A42_P_2 */
10982 { "vmpsadbw", { XM, Vex, EXx, Ib } },
10985 /* VEX_W_0F3A44_P_2 */
10986 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } },
10989 /* VEX_W_0F3A46_P_2 */
10990 { "vperm2i128", { XM, Vex256, EXx, Ib } },
10993 /* VEX_W_0F3A48_P_2 */
10994 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10995 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10998 /* VEX_W_0F3A49_P_2 */
10999 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11000 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11003 /* VEX_W_0F3A4A_P_2 */
11004 { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
11007 /* VEX_W_0F3A4B_P_2 */
11008 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
11011 /* VEX_W_0F3A4C_P_2 */
11012 { "vpblendvb", { XM, Vex, EXx, XMVexI4 } },
11015 /* VEX_W_0F3A60_P_2 */
11016 { "vpcmpestrm", { XM, EXx, Ib } },
11019 /* VEX_W_0F3A61_P_2 */
11020 { "vpcmpestri", { XM, EXx, Ib } },
11023 /* VEX_W_0F3A62_P_2 */
11024 { "vpcmpistrm", { XM, EXx, Ib } },
11027 /* VEX_W_0F3A63_P_2 */
11028 { "vpcmpistri", { XM, EXx, Ib } },
11031 /* VEX_W_0F3ADF_P_2 */
11032 { "vaeskeygenassist", { XM, EXx, Ib } },
11034 #define NEED_VEX_W_TABLE
11035 #include "i386-dis-evex.h"
11036 #undef NEED_VEX_W_TABLE
11039 static const struct dis386 mod_table[][2] = {
11042 { "leaS", { Gv, M } },
11047 { RM_TABLE (RM_C6_REG_7) },
11052 { RM_TABLE (RM_C7_REG_7) },
11056 { "Jcall{T|}", { indirEp } },
11060 { "Jjmp{T|}", { indirEp } },
11063 /* MOD_0F01_REG_0 */
11064 { X86_64_TABLE (X86_64_0F01_REG_0) },
11065 { RM_TABLE (RM_0F01_REG_0) },
11068 /* MOD_0F01_REG_1 */
11069 { X86_64_TABLE (X86_64_0F01_REG_1) },
11070 { RM_TABLE (RM_0F01_REG_1) },
11073 /* MOD_0F01_REG_2 */
11074 { X86_64_TABLE (X86_64_0F01_REG_2) },
11075 { RM_TABLE (RM_0F01_REG_2) },
11078 /* MOD_0F01_REG_3 */
11079 { X86_64_TABLE (X86_64_0F01_REG_3) },
11080 { RM_TABLE (RM_0F01_REG_3) },
11083 /* MOD_0F01_REG_7 */
11084 { "invlpg", { Mb } },
11085 { RM_TABLE (RM_0F01_REG_7) },
11088 /* MOD_0F12_PREFIX_0 */
11089 { "movlps", { XM, EXq } },
11090 { "movhlps", { XM, EXq } },
11094 { "movlpX", { EXq, XM } },
11097 /* MOD_0F16_PREFIX_0 */
11098 { "movhps", { XM, EXq } },
11099 { "movlhps", { XM, EXq } },
11103 { "movhpX", { EXq, XM } },
11106 /* MOD_0F18_REG_0 */
11107 { "prefetchnta", { Mb } },
11110 /* MOD_0F18_REG_1 */
11111 { "prefetcht0", { Mb } },
11114 /* MOD_0F18_REG_2 */
11115 { "prefetcht1", { Mb } },
11118 /* MOD_0F18_REG_3 */
11119 { "prefetcht2", { Mb } },
11122 /* MOD_0F18_REG_4 */
11123 { "nop/reserved", { Mb } },
11126 /* MOD_0F18_REG_5 */
11127 { "nop/reserved", { Mb } },
11130 /* MOD_0F18_REG_6 */
11131 { "nop/reserved", { Mb } },
11134 /* MOD_0F18_REG_7 */
11135 { "nop/reserved", { Mb } },
11138 /* MOD_0F1A_PREFIX_0 */
11139 { "bndldx", { Gbnd, Ev_bnd } },
11140 { "nopQ", { Ev } },
11143 /* MOD_0F1B_PREFIX_0 */
11144 { "bndstx", { Ev_bnd, Gbnd } },
11145 { "nopQ", { Ev } },
11148 /* MOD_0F1B_PREFIX_1 */
11149 { "bndmk", { Gbnd, Ev_bnd } },
11150 { "nopQ", { Ev } },
11155 { "movZ", { Rm, Cm } },
11160 { "movZ", { Rm, Dm } },
11165 { "movZ", { Cm, Rm } },
11170 { "movZ", { Dm, Rm } },
11175 { "movL", { Rd, Td } },
11180 { "movL", { Td, Rd } },
11183 /* MOD_0F2B_PREFIX_0 */
11184 {"movntps", { Mx, XM } },
11187 /* MOD_0F2B_PREFIX_1 */
11188 {"movntss", { Md, XM } },
11191 /* MOD_0F2B_PREFIX_2 */
11192 {"movntpd", { Mx, XM } },
11195 /* MOD_0F2B_PREFIX_3 */
11196 {"movntsd", { Mq, XM } },
11201 { "movmskpX", { Gdq, XS } },
11204 /* MOD_0F71_REG_2 */
11206 { "psrlw", { MS, Ib } },
11209 /* MOD_0F71_REG_4 */
11211 { "psraw", { MS, Ib } },
11214 /* MOD_0F71_REG_6 */
11216 { "psllw", { MS, Ib } },
11219 /* MOD_0F72_REG_2 */
11221 { "psrld", { MS, Ib } },
11224 /* MOD_0F72_REG_4 */
11226 { "psrad", { MS, Ib } },
11229 /* MOD_0F72_REG_6 */
11231 { "pslld", { MS, Ib } },
11234 /* MOD_0F73_REG_2 */
11236 { "psrlq", { MS, Ib } },
11239 /* MOD_0F73_REG_3 */
11241 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11244 /* MOD_0F73_REG_6 */
11246 { "psllq", { MS, Ib } },
11249 /* MOD_0F73_REG_7 */
11251 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11254 /* MOD_0FAE_REG_0 */
11255 { "fxsave", { FXSAVE } },
11256 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11259 /* MOD_0FAE_REG_1 */
11260 { "fxrstor", { FXSAVE } },
11261 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11264 /* MOD_0FAE_REG_2 */
11265 { "ldmxcsr", { Md } },
11266 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11269 /* MOD_0FAE_REG_3 */
11270 { "stmxcsr", { Md } },
11271 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11274 /* MOD_0FAE_REG_4 */
11275 { "xsave", { FXSAVE } },
11278 /* MOD_0FAE_REG_5 */
11279 { "xrstor", { FXSAVE } },
11280 { RM_TABLE (RM_0FAE_REG_5) },
11283 /* MOD_0FAE_REG_6 */
11284 { "xsaveopt", { FXSAVE } },
11285 { RM_TABLE (RM_0FAE_REG_6) },
11288 /* MOD_0FAE_REG_7 */
11289 { "clflush", { Mb } },
11290 { RM_TABLE (RM_0FAE_REG_7) },
11294 { "lssS", { Gv, Mp } },
11298 { "lfsS", { Gv, Mp } },
11302 { "lgsS", { Gv, Mp } },
11305 /* MOD_0FC7_REG_6 */
11306 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
11307 { "rdrand", { Ev } },
11310 /* MOD_0FC7_REG_7 */
11311 { "vmptrst", { Mq } },
11312 { "rdseed", { Ev } },
11317 { "pmovmskb", { Gdq, MS } },
11320 /* MOD_0FE7_PREFIX_2 */
11321 { "movntdq", { Mx, XM } },
11324 /* MOD_0FF0_PREFIX_3 */
11325 { "lddqu", { XM, M } },
11328 /* MOD_0F382A_PREFIX_2 */
11329 { "movntdqa", { XM, Mx } },
11333 { "bound{S|}", { Gv, Ma } },
11334 { EVEX_TABLE (EVEX_0F) },
11338 { "lesS", { Gv, Mp } },
11339 { VEX_C4_TABLE (VEX_0F) },
11343 { "ldsS", { Gv, Mp } },
11344 { VEX_C5_TABLE (VEX_0F) },
11347 /* MOD_VEX_0F12_PREFIX_0 */
11348 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11349 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11353 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11356 /* MOD_VEX_0F16_PREFIX_0 */
11357 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11358 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11362 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11366 { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11371 { VEX_W_TABLE (VEX_W_0F50_M_0) },
11374 /* MOD_VEX_0F71_REG_2 */
11376 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11379 /* MOD_VEX_0F71_REG_4 */
11381 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11384 /* MOD_VEX_0F71_REG_6 */
11386 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11389 /* MOD_VEX_0F72_REG_2 */
11391 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11394 /* MOD_VEX_0F72_REG_4 */
11396 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11399 /* MOD_VEX_0F72_REG_6 */
11401 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11404 /* MOD_VEX_0F73_REG_2 */
11406 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11409 /* MOD_VEX_0F73_REG_3 */
11411 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11414 /* MOD_VEX_0F73_REG_6 */
11416 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11419 /* MOD_VEX_0F73_REG_7 */
11421 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11424 /* MOD_VEX_0FAE_REG_2 */
11425 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11428 /* MOD_VEX_0FAE_REG_3 */
11429 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11432 /* MOD_VEX_0FD7_PREFIX_2 */
11434 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11437 /* MOD_VEX_0FE7_PREFIX_2 */
11438 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11441 /* MOD_VEX_0FF0_PREFIX_3 */
11442 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11445 /* MOD_VEX_0F381A_PREFIX_2 */
11446 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11449 /* MOD_VEX_0F382A_PREFIX_2 */
11450 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11453 /* MOD_VEX_0F382C_PREFIX_2 */
11454 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11457 /* MOD_VEX_0F382D_PREFIX_2 */
11458 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11461 /* MOD_VEX_0F382E_PREFIX_2 */
11462 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11465 /* MOD_VEX_0F382F_PREFIX_2 */
11466 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11469 /* MOD_VEX_0F385A_PREFIX_2 */
11470 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11473 /* MOD_VEX_0F388C_PREFIX_2 */
11474 { "vpmaskmov%LW", { XM, Vex, Mx } },
11477 /* MOD_VEX_0F388E_PREFIX_2 */
11478 { "vpmaskmov%LW", { Mx, Vex, XM } },
11480 #define NEED_MOD_TABLE
11481 #include "i386-dis-evex.h"
11482 #undef NEED_MOD_TABLE
11485 static const struct dis386 rm_table[][8] = {
11488 { "xabort", { Skip_MODRM, Ib } },
11492 { "xbeginT", { Skip_MODRM, Jv } },
11495 /* RM_0F01_REG_0 */
11497 { "vmcall", { Skip_MODRM } },
11498 { "vmlaunch", { Skip_MODRM } },
11499 { "vmresume", { Skip_MODRM } },
11500 { "vmxoff", { Skip_MODRM } },
11503 /* RM_0F01_REG_1 */
11504 { "monitor", { { OP_Monitor, 0 } } },
11505 { "mwait", { { OP_Mwait, 0 } } },
11506 { "clac", { Skip_MODRM } },
11507 { "stac", { Skip_MODRM } },
11510 /* RM_0F01_REG_2 */
11511 { "xgetbv", { Skip_MODRM } },
11512 { "xsetbv", { Skip_MODRM } },
11515 { "vmfunc", { Skip_MODRM } },
11516 { "xend", { Skip_MODRM } },
11517 { "xtest", { Skip_MODRM } },
11521 /* RM_0F01_REG_3 */
11522 { "vmrun", { Skip_MODRM } },
11523 { "vmmcall", { Skip_MODRM } },
11524 { "vmload", { Skip_MODRM } },
11525 { "vmsave", { Skip_MODRM } },
11526 { "stgi", { Skip_MODRM } },
11527 { "clgi", { Skip_MODRM } },
11528 { "skinit", { Skip_MODRM } },
11529 { "invlpga", { Skip_MODRM } },
11532 /* RM_0F01_REG_7 */
11533 { "swapgs", { Skip_MODRM } },
11534 { "rdtscp", { Skip_MODRM } },
11537 /* RM_0FAE_REG_5 */
11538 { "lfence", { Skip_MODRM } },
11541 /* RM_0FAE_REG_6 */
11542 { "mfence", { Skip_MODRM } },
11545 /* RM_0FAE_REG_7 */
11546 { "sfence", { Skip_MODRM } },
11550 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11552 /* We use the high bit to indicate different name for the same
11554 #define ADDR16_PREFIX (0x67 | 0x100)
11555 #define ADDR32_PREFIX (0x67 | 0x200)
11556 #define DATA16_PREFIX (0x66 | 0x100)
11557 #define DATA32_PREFIX (0x66 | 0x200)
11558 #define REP_PREFIX (0xf3 | 0x100)
11559 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11560 #define XRELEASE_PREFIX (0xf3 | 0x400)
11561 #define BND_PREFIX (0xf2 | 0x400)
11566 int newrex, i, length;
11572 last_lock_prefix = -1;
11573 last_repz_prefix = -1;
11574 last_repnz_prefix = -1;
11575 last_data_prefix = -1;
11576 last_addr_prefix = -1;
11577 last_rex_prefix = -1;
11578 last_seg_prefix = -1;
11579 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11580 all_prefixes[i] = 0;
11583 /* The maximum instruction length is 15bytes. */
11584 while (length < MAX_CODE_LENGTH - 1)
11586 FETCH_DATA (the_info, codep + 1);
11590 /* REX prefixes family. */
11607 if (address_mode == mode_64bit)
11611 last_rex_prefix = i;
11614 prefixes |= PREFIX_REPZ;
11615 last_repz_prefix = i;
11618 prefixes |= PREFIX_REPNZ;
11619 last_repnz_prefix = i;
11622 prefixes |= PREFIX_LOCK;
11623 last_lock_prefix = i;
11626 prefixes |= PREFIX_CS;
11627 last_seg_prefix = i;
11630 prefixes |= PREFIX_SS;
11631 last_seg_prefix = i;
11634 prefixes |= PREFIX_DS;
11635 last_seg_prefix = i;
11638 prefixes |= PREFIX_ES;
11639 last_seg_prefix = i;
11642 prefixes |= PREFIX_FS;
11643 last_seg_prefix = i;
11646 prefixes |= PREFIX_GS;
11647 last_seg_prefix = i;
11650 prefixes |= PREFIX_DATA;
11651 last_data_prefix = i;
11654 prefixes |= PREFIX_ADDR;
11655 last_addr_prefix = i;
11658 /* fwait is really an instruction. If there are prefixes
11659 before the fwait, they belong to the fwait, *not* to the
11660 following instruction. */
11661 if (prefixes || rex)
11663 prefixes |= PREFIX_FWAIT;
11665 /* This ensures that the previous REX prefixes are noticed
11666 as unused prefixes, as in the return case below. */
11670 prefixes = PREFIX_FWAIT;
11675 /* Rex is ignored when followed by another prefix. */
11681 if (*codep != FWAIT_OPCODE)
11682 all_prefixes[i++] = *codep;
11691 seg_prefix (int pref)
11712 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11715 static const char *
11716 prefix_name (int pref, int sizeflag)
11718 static const char *rexes [16] =
11721 "rex.B", /* 0x41 */
11722 "rex.X", /* 0x42 */
11723 "rex.XB", /* 0x43 */
11724 "rex.R", /* 0x44 */
11725 "rex.RB", /* 0x45 */
11726 "rex.RX", /* 0x46 */
11727 "rex.RXB", /* 0x47 */
11728 "rex.W", /* 0x48 */
11729 "rex.WB", /* 0x49 */
11730 "rex.WX", /* 0x4a */
11731 "rex.WXB", /* 0x4b */
11732 "rex.WR", /* 0x4c */
11733 "rex.WRB", /* 0x4d */
11734 "rex.WRX", /* 0x4e */
11735 "rex.WRXB", /* 0x4f */
11740 /* REX prefixes family. */
11757 return rexes [pref - 0x40];
11777 return (sizeflag & DFLAG) ? "data16" : "data32";
11779 if (address_mode == mode_64bit)
11780 return (sizeflag & AFLAG) ? "addr32" : "addr64";
11782 return (sizeflag & AFLAG) ? "addr16" : "addr32";
11785 case ADDR16_PREFIX:
11787 case ADDR32_PREFIX:
11789 case DATA16_PREFIX:
11791 case DATA32_PREFIX:
11795 case XACQUIRE_PREFIX:
11797 case XRELEASE_PREFIX:
11806 static char op_out[MAX_OPERANDS][100];
11807 static int op_ad, op_index[MAX_OPERANDS];
11808 static int two_source_ops;
11809 static bfd_vma op_address[MAX_OPERANDS];
11810 static bfd_vma op_riprel[MAX_OPERANDS];
11811 static bfd_vma start_pc;
11814 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11815 * (see topic "Redundant prefixes" in the "Differences from 8086"
11816 * section of the "Virtual 8086 Mode" chapter.)
11817 * 'pc' should be the address of this instruction, it will
11818 * be used to print the target address if this is a relative jump or call
11819 * The function returns the length of this instruction in bytes.
11822 static char intel_syntax;
11823 static char intel_mnemonic = !SYSV386_COMPAT;
11824 static char open_char;
11825 static char close_char;
11826 static char separator_char;
11827 static char scale_char;
11829 /* Here for backwards compatibility. When gdb stops using
11830 print_insn_i386_att and print_insn_i386_intel these functions can
11831 disappear, and print_insn_i386 be merged into print_insn. */
11833 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11837 return print_insn (pc, info);
11841 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11845 return print_insn (pc, info);
11849 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11853 return print_insn (pc, info);
11857 print_i386_disassembler_options (FILE *stream)
11859 fprintf (stream, _("\n\
11860 The following i386/x86-64 specific disassembler options are supported for use\n\
11861 with the -M switch (multiple options should be separated by commas):\n"));
11863 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
11864 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
11865 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
11866 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
11867 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
11868 fprintf (stream, _(" att-mnemonic\n"
11869 " Display instruction in AT&T mnemonic\n"));
11870 fprintf (stream, _(" intel-mnemonic\n"
11871 " Display instruction in Intel mnemonic\n"));
11872 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
11873 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
11874 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
11875 fprintf (stream, _(" data32 Assume 32bit data size\n"));
11876 fprintf (stream, _(" data16 Assume 16bit data size\n"));
11877 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11881 static const struct dis386 bad_opcode = { "(bad)", { XX } };
11883 /* Get a pointer to struct dis386 with a valid name. */
11885 static const struct dis386 *
11886 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11888 int vindex, vex_table_index;
11890 if (dp->name != NULL)
11893 switch (dp->op[0].bytemode)
11895 case USE_REG_TABLE:
11896 dp = ®_table[dp->op[1].bytemode][modrm.reg];
11899 case USE_MOD_TABLE:
11900 vindex = modrm.mod == 0x3 ? 1 : 0;
11901 dp = &mod_table[dp->op[1].bytemode][vindex];
11905 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11908 case USE_PREFIX_TABLE:
11911 /* The prefix in VEX is implicit. */
11912 switch (vex.prefix)
11917 case REPE_PREFIX_OPCODE:
11920 case DATA_PREFIX_OPCODE:
11923 case REPNE_PREFIX_OPCODE:
11934 used_prefixes |= (prefixes & PREFIX_REPZ);
11935 if (prefixes & PREFIX_REPZ)
11938 all_prefixes[last_repz_prefix] = 0;
11942 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11944 used_prefixes |= (prefixes & PREFIX_REPNZ);
11945 if (prefixes & PREFIX_REPNZ)
11948 all_prefixes[last_repnz_prefix] = 0;
11952 used_prefixes |= (prefixes & PREFIX_DATA);
11953 if (prefixes & PREFIX_DATA)
11956 all_prefixes[last_data_prefix] = 0;
11961 dp = &prefix_table[dp->op[1].bytemode][vindex];
11964 case USE_X86_64_TABLE:
11965 vindex = address_mode == mode_64bit ? 1 : 0;
11966 dp = &x86_64_table[dp->op[1].bytemode][vindex];
11969 case USE_3BYTE_TABLE:
11970 FETCH_DATA (info, codep + 2);
11972 dp = &three_byte_table[dp->op[1].bytemode][vindex];
11973 modrm.mod = (*codep >> 6) & 3;
11974 modrm.reg = (*codep >> 3) & 7;
11975 modrm.rm = *codep & 7;
11978 case USE_VEX_LEN_TABLE:
11982 switch (vex.length)
11995 dp = &vex_len_table[dp->op[1].bytemode][vindex];
11998 case USE_XOP_8F_TABLE:
11999 FETCH_DATA (info, codep + 3);
12000 /* All bits in the REX prefix are ignored. */
12002 rex = ~(*codep >> 5) & 0x7;
12004 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12005 switch ((*codep & 0x1f))
12011 vex_table_index = XOP_08;
12014 vex_table_index = XOP_09;
12017 vex_table_index = XOP_0A;
12021 vex.w = *codep & 0x80;
12022 if (vex.w && address_mode == mode_64bit)
12025 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12026 if (address_mode != mode_64bit
12027 && vex.register_specifier > 0x7)
12033 vex.length = (*codep & 0x4) ? 256 : 128;
12034 switch ((*codep & 0x3))
12040 vex.prefix = DATA_PREFIX_OPCODE;
12043 vex.prefix = REPE_PREFIX_OPCODE;
12046 vex.prefix = REPNE_PREFIX_OPCODE;
12053 dp = &xop_table[vex_table_index][vindex];
12055 FETCH_DATA (info, codep + 1);
12056 modrm.mod = (*codep >> 6) & 3;
12057 modrm.reg = (*codep >> 3) & 7;
12058 modrm.rm = *codep & 7;
12061 case USE_VEX_C4_TABLE:
12063 FETCH_DATA (info, codep + 3);
12064 /* All bits in the REX prefix are ignored. */
12066 rex = ~(*codep >> 5) & 0x7;
12067 switch ((*codep & 0x1f))
12073 vex_table_index = VEX_0F;
12076 vex_table_index = VEX_0F38;
12079 vex_table_index = VEX_0F3A;
12083 vex.w = *codep & 0x80;
12084 if (vex.w && address_mode == mode_64bit)
12087 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12088 if (address_mode != mode_64bit
12089 && vex.register_specifier > 0x7)
12095 vex.length = (*codep & 0x4) ? 256 : 128;
12096 switch ((*codep & 0x3))
12102 vex.prefix = DATA_PREFIX_OPCODE;
12105 vex.prefix = REPE_PREFIX_OPCODE;
12108 vex.prefix = REPNE_PREFIX_OPCODE;
12115 dp = &vex_table[vex_table_index][vindex];
12116 /* There is no MODRM byte for VEX [82|77]. */
12117 if (vindex != 0x77 && vindex != 0x82)
12119 FETCH_DATA (info, codep + 1);
12120 modrm.mod = (*codep >> 6) & 3;
12121 modrm.reg = (*codep >> 3) & 7;
12122 modrm.rm = *codep & 7;
12126 case USE_VEX_C5_TABLE:
12128 FETCH_DATA (info, codep + 2);
12129 /* All bits in the REX prefix are ignored. */
12131 rex = (*codep & 0x80) ? 0 : REX_R;
12133 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12134 if (address_mode != mode_64bit
12135 && vex.register_specifier > 0x7)
12143 vex.length = (*codep & 0x4) ? 256 : 128;
12144 switch ((*codep & 0x3))
12150 vex.prefix = DATA_PREFIX_OPCODE;
12153 vex.prefix = REPE_PREFIX_OPCODE;
12156 vex.prefix = REPNE_PREFIX_OPCODE;
12163 dp = &vex_table[dp->op[1].bytemode][vindex];
12164 /* There is no MODRM byte for VEX [82|77]. */
12165 if (vindex != 0x77 && vindex != 0x82)
12167 FETCH_DATA (info, codep + 1);
12168 modrm.mod = (*codep >> 6) & 3;
12169 modrm.reg = (*codep >> 3) & 7;
12170 modrm.rm = *codep & 7;
12174 case USE_VEX_W_TABLE:
12178 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12181 case USE_EVEX_TABLE:
12182 two_source_ops = 0;
12185 FETCH_DATA (info, codep + 4);
12186 /* All bits in the REX prefix are ignored. */
12188 /* The first byte after 0x62. */
12189 rex = ~(*codep >> 5) & 0x7;
12190 vex.r = *codep & 0x10;
12191 switch ((*codep & 0xf))
12194 return &bad_opcode;
12196 vex_table_index = EVEX_0F;
12199 vex_table_index = EVEX_0F38;
12202 vex_table_index = EVEX_0F3A;
12206 /* The second byte after 0x62. */
12208 vex.w = *codep & 0x80;
12209 if (vex.w && address_mode == mode_64bit)
12212 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12213 if (address_mode != mode_64bit)
12215 /* In 16/32-bit mode silently ignore following bits. */
12219 vex.register_specifier &= 0x7;
12223 if (!(*codep & 0x4))
12224 return &bad_opcode;
12226 switch ((*codep & 0x3))
12232 vex.prefix = DATA_PREFIX_OPCODE;
12235 vex.prefix = REPE_PREFIX_OPCODE;
12238 vex.prefix = REPNE_PREFIX_OPCODE;
12242 /* The third byte after 0x62. */
12245 /* Remember the static rounding bits. */
12246 vex.ll = (*codep >> 5) & 3;
12247 vex.b = (*codep & 0x10) != 0;
12249 vex.v = *codep & 0x8;
12250 vex.mask_register_specifier = *codep & 0x7;
12251 vex.zeroing = *codep & 0x80;
12257 dp = &evex_table[vex_table_index][vindex];
12258 FETCH_DATA (info, codep + 1);
12259 modrm.mod = (*codep >> 6) & 3;
12260 modrm.reg = (*codep >> 3) & 7;
12261 modrm.rm = *codep & 7;
12263 /* Set vector length. */
12264 if (modrm.mod == 3 && vex.b)
12280 return &bad_opcode;
12293 if (dp->name != NULL)
12296 return get_valid_dis386 (dp, info);
12300 get_sib (disassemble_info *info, int sizeflag)
12302 /* If modrm.mod == 3, operand must be register. */
12304 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12308 FETCH_DATA (info, codep + 2);
12309 sib.index = (codep [1] >> 3) & 7;
12310 sib.scale = (codep [1] >> 6) & 3;
12311 sib.base = codep [1] & 7;
12316 print_insn (bfd_vma pc, disassemble_info *info)
12318 const struct dis386 *dp;
12320 char *op_txt[MAX_OPERANDS];
12324 struct dis_private priv;
12326 int default_prefixes;
12328 priv.orig_sizeflag = AFLAG | DFLAG;
12329 if ((info->mach & bfd_mach_i386_i386) != 0)
12330 address_mode = mode_32bit;
12331 else if (info->mach == bfd_mach_i386_i8086)
12333 address_mode = mode_16bit;
12334 priv.orig_sizeflag = 0;
12337 address_mode = mode_64bit;
12339 if (intel_syntax == (char) -1)
12340 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12342 for (p = info->disassembler_options; p != NULL; )
12344 if (CONST_STRNEQ (p, "x86-64"))
12346 address_mode = mode_64bit;
12347 priv.orig_sizeflag = AFLAG | DFLAG;
12349 else if (CONST_STRNEQ (p, "i386"))
12351 address_mode = mode_32bit;
12352 priv.orig_sizeflag = AFLAG | DFLAG;
12354 else if (CONST_STRNEQ (p, "i8086"))
12356 address_mode = mode_16bit;
12357 priv.orig_sizeflag = 0;
12359 else if (CONST_STRNEQ (p, "intel"))
12362 if (CONST_STRNEQ (p + 5, "-mnemonic"))
12363 intel_mnemonic = 1;
12365 else if (CONST_STRNEQ (p, "att"))
12368 if (CONST_STRNEQ (p + 3, "-mnemonic"))
12369 intel_mnemonic = 0;
12371 else if (CONST_STRNEQ (p, "addr"))
12373 if (address_mode == mode_64bit)
12375 if (p[4] == '3' && p[5] == '2')
12376 priv.orig_sizeflag &= ~AFLAG;
12377 else if (p[4] == '6' && p[5] == '4')
12378 priv.orig_sizeflag |= AFLAG;
12382 if (p[4] == '1' && p[5] == '6')
12383 priv.orig_sizeflag &= ~AFLAG;
12384 else if (p[4] == '3' && p[5] == '2')
12385 priv.orig_sizeflag |= AFLAG;
12388 else if (CONST_STRNEQ (p, "data"))
12390 if (p[4] == '1' && p[5] == '6')
12391 priv.orig_sizeflag &= ~DFLAG;
12392 else if (p[4] == '3' && p[5] == '2')
12393 priv.orig_sizeflag |= DFLAG;
12395 else if (CONST_STRNEQ (p, "suffix"))
12396 priv.orig_sizeflag |= SUFFIX_ALWAYS;
12398 p = strchr (p, ',');
12405 names64 = intel_names64;
12406 names32 = intel_names32;
12407 names16 = intel_names16;
12408 names8 = intel_names8;
12409 names8rex = intel_names8rex;
12410 names_seg = intel_names_seg;
12411 names_mm = intel_names_mm;
12412 names_bnd = intel_names_bnd;
12413 names_xmm = intel_names_xmm;
12414 names_ymm = intel_names_ymm;
12415 names_zmm = intel_names_zmm;
12416 index64 = intel_index64;
12417 index32 = intel_index32;
12418 names_mask = intel_names_mask;
12419 index16 = intel_index16;
12422 separator_char = '+';
12427 names64 = att_names64;
12428 names32 = att_names32;
12429 names16 = att_names16;
12430 names8 = att_names8;
12431 names8rex = att_names8rex;
12432 names_seg = att_names_seg;
12433 names_mm = att_names_mm;
12434 names_bnd = att_names_bnd;
12435 names_xmm = att_names_xmm;
12436 names_ymm = att_names_ymm;
12437 names_zmm = att_names_zmm;
12438 index64 = att_index64;
12439 index32 = att_index32;
12440 names_mask = att_names_mask;
12441 index16 = att_index16;
12444 separator_char = ',';
12448 /* The output looks better if we put 7 bytes on a line, since that
12449 puts most long word instructions on a single line. Use 8 bytes
12451 if ((info->mach & bfd_mach_l1om) != 0)
12452 info->bytes_per_line = 8;
12454 info->bytes_per_line = 7;
12456 info->private_data = &priv;
12457 priv.max_fetched = priv.the_buffer;
12458 priv.insn_start = pc;
12461 for (i = 0; i < MAX_OPERANDS; ++i)
12469 start_codep = priv.the_buffer;
12470 codep = priv.the_buffer;
12472 if (setjmp (priv.bailout) != 0)
12476 /* Getting here means we tried for data but didn't get it. That
12477 means we have an incomplete instruction of some sort. Just
12478 print the first byte as a prefix or a .byte pseudo-op. */
12479 if (codep > priv.the_buffer)
12481 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12483 (*info->fprintf_func) (info->stream, "%s", name);
12486 /* Just print the first byte as a .byte instruction. */
12487 (*info->fprintf_func) (info->stream, ".byte 0x%x",
12488 (unsigned int) priv.the_buffer[0]);
12498 sizeflag = priv.orig_sizeflag;
12500 if (!ckprefix () || rex_used)
12502 /* Too many prefixes or unused REX prefixes. */
12504 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12506 (*info->fprintf_func) (info->stream, "%s%s",
12508 prefix_name (all_prefixes[i], sizeflag));
12512 insn_codep = codep;
12514 FETCH_DATA (info, codep + 1);
12515 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12517 if (((prefixes & PREFIX_FWAIT)
12518 && ((*codep < 0xd8) || (*codep > 0xdf))))
12520 (*info->fprintf_func) (info->stream, "fwait");
12524 if (*codep == 0x0f)
12526 unsigned char threebyte;
12527 FETCH_DATA (info, codep + 2);
12528 threebyte = *++codep;
12529 dp = &dis386_twobyte[threebyte];
12530 need_modrm = twobyte_has_modrm[*codep];
12535 dp = &dis386[*codep];
12536 need_modrm = onebyte_has_modrm[*codep];
12540 if ((prefixes & PREFIX_REPZ))
12541 used_prefixes |= PREFIX_REPZ;
12542 if ((prefixes & PREFIX_REPNZ))
12543 used_prefixes |= PREFIX_REPNZ;
12544 if ((prefixes & PREFIX_LOCK))
12545 used_prefixes |= PREFIX_LOCK;
12547 default_prefixes = 0;
12548 if (prefixes & PREFIX_ADDR)
12551 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
12553 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12554 all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
12556 all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
12557 default_prefixes |= PREFIX_ADDR;
12561 if ((prefixes & PREFIX_DATA))
12564 if (dp->op[2].bytemode == cond_jump_mode
12565 && dp->op[0].bytemode == v_mode
12568 if (sizeflag & DFLAG)
12569 all_prefixes[last_data_prefix] = DATA32_PREFIX;
12571 all_prefixes[last_data_prefix] = DATA16_PREFIX;
12572 default_prefixes |= PREFIX_DATA;
12574 else if (rex & REX_W)
12576 /* REX_W will override PREFIX_DATA. */
12577 default_prefixes |= PREFIX_DATA;
12583 FETCH_DATA (info, codep + 1);
12584 modrm.mod = (*codep >> 6) & 3;
12585 modrm.reg = (*codep >> 3) & 7;
12586 modrm.rm = *codep & 7;
12594 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12596 get_sib (info, sizeflag);
12597 dofloat (sizeflag);
12601 dp = get_valid_dis386 (dp, info);
12602 if (dp != NULL && putop (dp->name, sizeflag) == 0)
12604 get_sib (info, sizeflag);
12605 for (i = 0; i < MAX_OPERANDS; ++i)
12608 op_ad = MAX_OPERANDS - 1 - i;
12610 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12611 /* For EVEX instruction after the last operand masking
12612 should be printed. */
12613 if (i == 0 && vex.evex)
12615 /* Don't print {%k0}. */
12616 if (vex.mask_register_specifier)
12619 oappend (names_mask[vex.mask_register_specifier]);
12629 /* See if any prefixes were not used. If so, print the first one
12630 separately. If we don't do this, we'll wind up printing an
12631 instruction stream which does not precisely correspond to the
12632 bytes we are disassembling. */
12633 if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
12635 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12636 if (all_prefixes[i])
12639 name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
12641 name = INTERNAL_DISASSEMBLER_ERROR;
12642 (*info->fprintf_func) (info->stream, "%s", name);
12647 /* Check if the REX prefix is used. */
12648 if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12649 all_prefixes[last_rex_prefix] = 0;
12651 /* Check if the SEG prefix is used. */
12652 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12653 | PREFIX_FS | PREFIX_GS)) != 0
12655 & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
12656 all_prefixes[last_seg_prefix] = 0;
12658 /* Check if the ADDR prefix is used. */
12659 if ((prefixes & PREFIX_ADDR) != 0
12660 && (used_prefixes & PREFIX_ADDR) != 0)
12661 all_prefixes[last_addr_prefix] = 0;
12663 /* Check if the DATA prefix is used. */
12664 if ((prefixes & PREFIX_DATA) != 0
12665 && (used_prefixes & PREFIX_DATA) != 0)
12666 all_prefixes[last_data_prefix] = 0;
12669 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12670 if (all_prefixes[i])
12673 name = prefix_name (all_prefixes[i], sizeflag);
12676 prefix_length += strlen (name) + 1;
12677 (*info->fprintf_func) (info->stream, "%s ", name);
12680 /* Check maximum code length. */
12681 if ((codep - start_codep) > MAX_CODE_LENGTH)
12683 (*info->fprintf_func) (info->stream, "(bad)");
12684 return MAX_CODE_LENGTH;
12687 obufp = mnemonicendp;
12688 for (i = strlen (obuf) + prefix_length; i < 6; i++)
12691 (*info->fprintf_func) (info->stream, "%s", obuf);
12693 /* The enter and bound instructions are printed with operands in the same
12694 order as the intel book; everything else is printed in reverse order. */
12695 if (intel_syntax || two_source_ops)
12699 for (i = 0; i < MAX_OPERANDS; ++i)
12700 op_txt[i] = op_out[i];
12702 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12704 op_ad = op_index[i];
12705 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12706 op_index[MAX_OPERANDS - 1 - i] = op_ad;
12707 riprel = op_riprel[i];
12708 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12709 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12714 for (i = 0; i < MAX_OPERANDS; ++i)
12715 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12719 for (i = 0; i < MAX_OPERANDS; ++i)
12723 (*info->fprintf_func) (info->stream, ",");
12724 if (op_index[i] != -1 && !op_riprel[i])
12725 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12727 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12731 for (i = 0; i < MAX_OPERANDS; i++)
12732 if (op_index[i] != -1 && op_riprel[i])
12734 (*info->fprintf_func) (info->stream, " # ");
12735 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
12736 + op_address[op_index[i]]), info);
12739 return codep - priv.the_buffer;
12742 static const char *float_mem[] = {
12817 static const unsigned char float_mem_mode[] = {
12892 #define ST { OP_ST, 0 }
12893 #define STi { OP_STi, 0 }
12895 #define FGRPd9_2 NULL, { { NULL, 0 } }
12896 #define FGRPd9_4 NULL, { { NULL, 1 } }
12897 #define FGRPd9_5 NULL, { { NULL, 2 } }
12898 #define FGRPd9_6 NULL, { { NULL, 3 } }
12899 #define FGRPd9_7 NULL, { { NULL, 4 } }
12900 #define FGRPda_5 NULL, { { NULL, 5 } }
12901 #define FGRPdb_4 NULL, { { NULL, 6 } }
12902 #define FGRPde_3 NULL, { { NULL, 7 } }
12903 #define FGRPdf_4 NULL, { { NULL, 8 } }
12905 static const struct dis386 float_reg[][8] = {
12908 { "fadd", { ST, STi } },
12909 { "fmul", { ST, STi } },
12910 { "fcom", { STi } },
12911 { "fcomp", { STi } },
12912 { "fsub", { ST, STi } },
12913 { "fsubr", { ST, STi } },
12914 { "fdiv", { ST, STi } },
12915 { "fdivr", { ST, STi } },
12919 { "fld", { STi } },
12920 { "fxch", { STi } },
12930 { "fcmovb", { ST, STi } },
12931 { "fcmove", { ST, STi } },
12932 { "fcmovbe",{ ST, STi } },
12933 { "fcmovu", { ST, STi } },
12941 { "fcmovnb",{ ST, STi } },
12942 { "fcmovne",{ ST, STi } },
12943 { "fcmovnbe",{ ST, STi } },
12944 { "fcmovnu",{ ST, STi } },
12946 { "fucomi", { ST, STi } },
12947 { "fcomi", { ST, STi } },
12952 { "fadd", { STi, ST } },
12953 { "fmul", { STi, ST } },
12956 { "fsub!M", { STi, ST } },
12957 { "fsubM", { STi, ST } },
12958 { "fdiv!M", { STi, ST } },
12959 { "fdivM", { STi, ST } },
12963 { "ffree", { STi } },
12965 { "fst", { STi } },
12966 { "fstp", { STi } },
12967 { "fucom", { STi } },
12968 { "fucomp", { STi } },
12974 { "faddp", { STi, ST } },
12975 { "fmulp", { STi, ST } },
12978 { "fsub!Mp", { STi, ST } },
12979 { "fsubMp", { STi, ST } },
12980 { "fdiv!Mp", { STi, ST } },
12981 { "fdivMp", { STi, ST } },
12985 { "ffreep", { STi } },
12990 { "fucomip", { ST, STi } },
12991 { "fcomip", { ST, STi } },
12996 static char *fgrps[][8] = {
12999 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13004 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13009 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13014 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13019 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13024 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13029 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13030 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13035 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13040 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13045 swap_operand (void)
13047 mnemonicendp[0] = '.';
13048 mnemonicendp[1] = 's';
13053 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13054 int sizeflag ATTRIBUTE_UNUSED)
13056 /* Skip mod/rm byte. */
13062 dofloat (int sizeflag)
13064 const struct dis386 *dp;
13065 unsigned char floatop;
13067 floatop = codep[-1];
13069 if (modrm.mod != 3)
13071 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13073 putop (float_mem[fp_indx], sizeflag);
13076 OP_E (float_mem_mode[fp_indx], sizeflag);
13079 /* Skip mod/rm byte. */
13083 dp = &float_reg[floatop - 0xd8][modrm.reg];
13084 if (dp->name == NULL)
13086 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13088 /* Instruction fnstsw is only one with strange arg. */
13089 if (floatop == 0xdf && codep[-1] == 0xe0)
13090 strcpy (op_out[0], names16[0]);
13094 putop (dp->name, sizeflag);
13099 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13104 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13108 /* Like oappend (below), but S is a string starting with '%'.
13109 In Intel syntax, the '%' is elided. */
13111 oappend_maybe_intel (const char *s)
13113 oappend (s + intel_syntax);
13117 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13119 oappend_maybe_intel ("%st");
13123 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13125 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13126 oappend_maybe_intel (scratchbuf);
13129 /* Capital letters in template are macros. */
13131 putop (const char *in_template, int sizeflag)
13136 unsigned int l = 0, len = 1;
13139 #define SAVE_LAST(c) \
13140 if (l < len && l < sizeof (last)) \
13145 for (p = in_template; *p; p++)
13162 while (*++p != '|')
13163 if (*p == '}' || *p == '\0')
13166 /* Fall through. */
13171 while (*++p != '}')
13182 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13186 if (l == 0 && len == 1)
13191 if (sizeflag & SUFFIX_ALWAYS)
13204 if (address_mode == mode_64bit
13205 && !(prefixes & PREFIX_ADDR))
13216 if (intel_syntax && !alt)
13218 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13220 if (sizeflag & DFLAG)
13221 *obufp++ = intel_syntax ? 'd' : 'l';
13223 *obufp++ = intel_syntax ? 'w' : 's';
13224 used_prefixes |= (prefixes & PREFIX_DATA);
13228 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13231 if (modrm.mod == 3)
13237 if (sizeflag & DFLAG)
13238 *obufp++ = intel_syntax ? 'd' : 'l';
13241 used_prefixes |= (prefixes & PREFIX_DATA);
13247 case 'E': /* For jcxz/jecxz */
13248 if (address_mode == mode_64bit)
13250 if (sizeflag & AFLAG)
13256 if (sizeflag & AFLAG)
13258 used_prefixes |= (prefixes & PREFIX_ADDR);
13263 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13265 if (sizeflag & AFLAG)
13266 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13268 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13269 used_prefixes |= (prefixes & PREFIX_ADDR);
13273 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13275 if ((rex & REX_W) || (sizeflag & DFLAG))
13279 if (!(rex & REX_W))
13280 used_prefixes |= (prefixes & PREFIX_DATA);
13285 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13286 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13288 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13291 if (prefixes & PREFIX_DS)
13312 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13317 /* Fall through. */
13320 if (l != 0 || len != 1)
13328 if (sizeflag & SUFFIX_ALWAYS)
13332 if (intel_mnemonic != cond)
13336 if ((prefixes & PREFIX_FWAIT) == 0)
13339 used_prefixes |= PREFIX_FWAIT;
13345 else if (intel_syntax && (sizeflag & DFLAG))
13349 if (!(rex & REX_W))
13350 used_prefixes |= (prefixes & PREFIX_DATA);
13354 && address_mode == mode_64bit
13355 && ((sizeflag & DFLAG) || (rex & REX_W)))
13360 /* Fall through. */
13364 if ((rex & REX_W) == 0
13365 && (prefixes & PREFIX_DATA))
13367 if ((sizeflag & DFLAG) == 0)
13369 used_prefixes |= (prefixes & PREFIX_DATA);
13373 if ((prefixes & PREFIX_DATA)
13375 || (sizeflag & SUFFIX_ALWAYS))
13382 if (sizeflag & DFLAG)
13386 used_prefixes |= (prefixes & PREFIX_DATA);
13393 if (address_mode == mode_64bit
13394 && ((sizeflag & DFLAG) || (rex & REX_W)))
13396 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13400 /* Fall through. */
13403 if (l == 0 && len == 1)
13406 if (intel_syntax && !alt)
13409 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13415 if (sizeflag & DFLAG)
13416 *obufp++ = intel_syntax ? 'd' : 'l';
13419 used_prefixes |= (prefixes & PREFIX_DATA);
13425 if (l != 1 || len != 2 || last[0] != 'L')
13431 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13446 else if (sizeflag & DFLAG)
13455 if (intel_syntax && !p[1]
13456 && ((rex & REX_W) || (sizeflag & DFLAG)))
13458 if (!(rex & REX_W))
13459 used_prefixes |= (prefixes & PREFIX_DATA);
13462 if (l == 0 && len == 1)
13466 if (address_mode == mode_64bit
13467 && ((sizeflag & DFLAG) || (rex & REX_W)))
13469 if (sizeflag & SUFFIX_ALWAYS)
13491 /* Fall through. */
13494 if (l == 0 && len == 1)
13499 if (sizeflag & SUFFIX_ALWAYS)
13505 if (sizeflag & DFLAG)
13509 used_prefixes |= (prefixes & PREFIX_DATA);
13523 if (address_mode == mode_64bit
13524 && !(prefixes & PREFIX_ADDR))
13535 if (l != 0 || len != 1)
13540 if (need_vex && vex.prefix)
13542 if (vex.prefix == DATA_PREFIX_OPCODE)
13549 if (prefixes & PREFIX_DATA)
13553 used_prefixes |= (prefixes & PREFIX_DATA);
13557 if (l == 0 && len == 1)
13559 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13570 if (l != 1 || len != 2 || last[0] != 'X')
13578 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13580 switch (vex.length)
13594 if (l == 0 && len == 1)
13596 /* operand size flag for cwtl, cbtw */
13605 else if (sizeflag & DFLAG)
13609 if (!(rex & REX_W))
13610 used_prefixes |= (prefixes & PREFIX_DATA);
13617 && last[0] != 'L'))
13624 if (last[0] == 'X')
13625 *obufp++ = vex.w ? 'd': 's';
13627 *obufp++ = vex.w ? 'q': 'd';
13634 mnemonicendp = obufp;
13639 oappend (const char *s)
13641 obufp = stpcpy (obufp, s);
13647 if (prefixes & PREFIX_CS)
13649 used_prefixes |= PREFIX_CS;
13650 oappend_maybe_intel ("%cs:");
13652 if (prefixes & PREFIX_DS)
13654 used_prefixes |= PREFIX_DS;
13655 oappend_maybe_intel ("%ds:");
13657 if (prefixes & PREFIX_SS)
13659 used_prefixes |= PREFIX_SS;
13660 oappend_maybe_intel ("%ss:");
13662 if (prefixes & PREFIX_ES)
13664 used_prefixes |= PREFIX_ES;
13665 oappend_maybe_intel ("%es:");
13667 if (prefixes & PREFIX_FS)
13669 used_prefixes |= PREFIX_FS;
13670 oappend_maybe_intel ("%fs:");
13672 if (prefixes & PREFIX_GS)
13674 used_prefixes |= PREFIX_GS;
13675 oappend_maybe_intel ("%gs:");
13680 OP_indirE (int bytemode, int sizeflag)
13684 OP_E (bytemode, sizeflag);
13688 print_operand_value (char *buf, int hex, bfd_vma disp)
13690 if (address_mode == mode_64bit)
13698 sprintf_vma (tmp, disp);
13699 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13700 strcpy (buf + 2, tmp + i);
13704 bfd_signed_vma v = disp;
13711 /* Check for possible overflow on 0x8000000000000000. */
13714 strcpy (buf, "9223372036854775808");
13728 tmp[28 - i] = (v % 10) + '0';
13732 strcpy (buf, tmp + 29 - i);
13738 sprintf (buf, "0x%x", (unsigned int) disp);
13740 sprintf (buf, "%d", (int) disp);
13744 /* Put DISP in BUF as signed hex number. */
13747 print_displacement (char *buf, bfd_vma disp)
13749 bfd_signed_vma val = disp;
13758 /* Check for possible overflow. */
13761 switch (address_mode)
13764 strcpy (buf + j, "0x8000000000000000");
13767 strcpy (buf + j, "0x80000000");
13770 strcpy (buf + j, "0x8000");
13780 sprintf_vma (tmp, (bfd_vma) val);
13781 for (i = 0; tmp[i] == '0'; i++)
13783 if (tmp[i] == '\0')
13785 strcpy (buf + j, tmp + i);
13789 intel_operand_size (int bytemode, int sizeflag)
13793 && (bytemode == x_mode
13794 || bytemode == evex_half_bcst_xmmq_mode))
13797 oappend ("QWORD PTR ");
13799 oappend ("DWORD PTR ");
13807 oappend ("BYTE PTR ");
13811 oappend ("WORD PTR ");
13814 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13816 oappend ("QWORD PTR ");
13825 oappend ("QWORD PTR ");
13828 if ((sizeflag & DFLAG) || bytemode == dq_mode)
13829 oappend ("DWORD PTR ");
13831 oappend ("WORD PTR ");
13832 used_prefixes |= (prefixes & PREFIX_DATA);
13836 if ((rex & REX_W) || (sizeflag & DFLAG))
13838 oappend ("WORD PTR ");
13839 if (!(rex & REX_W))
13840 used_prefixes |= (prefixes & PREFIX_DATA);
13843 if (sizeflag & DFLAG)
13844 oappend ("QWORD PTR ");
13846 oappend ("DWORD PTR ");
13847 used_prefixes |= (prefixes & PREFIX_DATA);
13850 case d_scalar_mode:
13851 case d_scalar_swap_mode:
13854 oappend ("DWORD PTR ");
13857 case q_scalar_mode:
13858 case q_scalar_swap_mode:
13860 oappend ("QWORD PTR ");
13863 if (address_mode == mode_64bit)
13864 oappend ("QWORD PTR ");
13866 oappend ("DWORD PTR ");
13869 if (sizeflag & DFLAG)
13870 oappend ("FWORD PTR ");
13872 oappend ("DWORD PTR ");
13873 used_prefixes |= (prefixes & PREFIX_DATA);
13876 oappend ("TBYTE PTR ");
13880 case evex_x_gscat_mode:
13881 case evex_x_nobcst_mode:
13884 switch (vex.length)
13887 oappend ("XMMWORD PTR ");
13890 oappend ("YMMWORD PTR ");
13893 oappend ("ZMMWORD PTR ");
13900 oappend ("XMMWORD PTR ");
13903 oappend ("XMMWORD PTR ");
13906 oappend ("YMMWORD PTR ");
13909 case evex_half_bcst_xmmq_mode:
13913 switch (vex.length)
13916 oappend ("QWORD PTR ");
13919 oappend ("XMMWORD PTR ");
13922 oappend ("YMMWORD PTR ");
13932 switch (vex.length)
13937 oappend ("BYTE PTR ");
13947 switch (vex.length)
13952 oappend ("WORD PTR ");
13962 switch (vex.length)
13967 oappend ("DWORD PTR ");
13977 switch (vex.length)
13982 oappend ("QWORD PTR ");
13992 switch (vex.length)
13995 oappend ("WORD PTR ");
13998 oappend ("DWORD PTR ");
14001 oappend ("QWORD PTR ");
14011 switch (vex.length)
14014 oappend ("DWORD PTR ");
14017 oappend ("QWORD PTR ");
14020 oappend ("XMMWORD PTR ");
14030 switch (vex.length)
14033 oappend ("QWORD PTR ");
14036 oappend ("YMMWORD PTR ");
14039 oappend ("ZMMWORD PTR ");
14049 switch (vex.length)
14053 oappend ("XMMWORD PTR ");
14060 oappend ("OWORD PTR ");
14063 case vex_w_dq_mode:
14064 case vex_scalar_w_dq_mode:
14069 oappend ("QWORD PTR ");
14071 oappend ("DWORD PTR ");
14073 case vex_vsib_d_w_dq_mode:
14074 case vex_vsib_q_w_dq_mode:
14081 oappend ("QWORD PTR ");
14083 oappend ("DWORD PTR ");
14087 if (vex.length != 512)
14089 oappend ("ZMMWORD PTR ");
14095 /* Currently the only instructions, which allows either mask or
14096 memory operand, are AVX512's KMOVW instructions. They need
14097 Word-sized operand. */
14098 if (vex.w || vex.length != 128)
14100 oappend ("WORD PTR ");
14109 OP_E_register (int bytemode, int sizeflag)
14111 int reg = modrm.rm;
14112 const char **names;
14118 if ((sizeflag & SUFFIX_ALWAYS)
14119 && (bytemode == b_swap_mode || bytemode == v_swap_mode))
14143 names = address_mode == mode_64bit ? names64 : names32;
14149 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14167 if ((sizeflag & DFLAG)
14168 || (bytemode != v_mode
14169 && bytemode != v_swap_mode))
14173 used_prefixes |= (prefixes & PREFIX_DATA);
14177 names = names_mask;
14182 oappend (INTERNAL_DISASSEMBLER_ERROR);
14185 oappend (names[reg]);
14189 OP_E_memory (int bytemode, int sizeflag)
14192 int add = (rex & REX_B) ? 8 : 0;
14198 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
14200 && bytemode != x_mode
14201 && bytemode != evex_half_bcst_xmmq_mode)
14208 case vex_vsib_d_w_dq_mode:
14209 case vex_vsib_q_w_dq_mode:
14210 case evex_x_gscat_mode:
14212 shift = vex.w ? 3 : 2;
14215 case evex_half_bcst_xmmq_mode:
14218 shift = vex.w ? 3 : 2;
14221 /* Fall through if vex.b == 0. */
14226 case evex_x_nobcst_mode:
14228 switch (vex.length)
14251 case q_scalar_mode:
14253 case q_scalar_swap_mode:
14259 case d_scalar_mode:
14261 case d_scalar_swap_mode:
14273 /* Make necessary corrections to shift for modes that need it.
14274 For these modes we currently have shift 4, 5 or 6 depending on
14275 vex.length (it corresponds to xmmword, ymmword or zmmword
14276 operand). We might want to make it 3, 4 or 5 (e.g. for
14277 xmmq_mode). In case of broadcast enabled the corrections
14278 aren't needed, as element size is always 32 or 64 bits. */
14279 if (bytemode == xmmq_mode
14280 || (bytemode == evex_half_bcst_xmmq_mode
14283 else if (bytemode == xmmqd_mode)
14285 else if (bytemode == xmmdw_mode)
14293 intel_operand_size (bytemode, sizeflag);
14296 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14298 /* 32/64 bit address mode */
14307 int addr32flag = !((sizeflag & AFLAG)
14308 || bytemode == v_bnd_mode
14309 || bytemode == bnd_mode);
14310 const char **indexes64 = names64;
14311 const char **indexes32 = names32;
14321 vindex = sib.index;
14327 case vex_vsib_d_w_dq_mode:
14328 case vex_vsib_q_w_dq_mode:
14338 switch (vex.length)
14341 indexes64 = indexes32 = names_xmm;
14344 if (!vex.w || bytemode == vex_vsib_q_w_dq_mode)
14345 indexes64 = indexes32 = names_ymm;
14347 indexes64 = indexes32 = names_xmm;
14350 if (!vex.w || bytemode == vex_vsib_q_w_dq_mode)
14351 indexes64 = indexes32 = names_zmm;
14353 indexes64 = indexes32 = names_ymm;
14360 haveindex = vindex != 4;
14367 rbase = base + add;
14375 if (address_mode == mode_64bit && !havesib)
14381 FETCH_DATA (the_info, codep + 1);
14383 if ((disp & 0x80) != 0)
14385 if (vex.evex && shift > 0)
14393 /* In 32bit mode, we need index register to tell [offset] from
14394 [eiz*1 + offset]. */
14395 needindex = (havesib
14398 && address_mode == mode_32bit);
14399 havedisp = (havebase
14401 || (havesib && (haveindex || scale != 0)));
14404 if (modrm.mod != 0 || base == 5)
14406 if (havedisp || riprel)
14407 print_displacement (scratchbuf, disp);
14409 print_operand_value (scratchbuf, 1, disp);
14410 oappend (scratchbuf);
14414 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
14418 if ((havebase || haveindex || riprel)
14419 && (bytemode != v_bnd_mode)
14420 && (bytemode != bnd_mode))
14421 used_prefixes |= PREFIX_ADDR;
14423 if (havedisp || (intel_syntax && riprel))
14425 *obufp++ = open_char;
14426 if (intel_syntax && riprel)
14429 oappend (sizeflag & AFLAG ? "rip" : "eip");
14433 oappend (address_mode == mode_64bit && !addr32flag
14434 ? names64[rbase] : names32[rbase]);
14437 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14438 print index to tell base + index from base. */
14442 || (havebase && base != ESP_REG_NUM))
14444 if (!intel_syntax || havebase)
14446 *obufp++ = separator_char;
14450 oappend (address_mode == mode_64bit && !addr32flag
14451 ? indexes64[vindex] : indexes32[vindex]);
14453 oappend (address_mode == mode_64bit && !addr32flag
14454 ? index64 : index32);
14456 *obufp++ = scale_char;
14458 sprintf (scratchbuf, "%d", 1 << scale);
14459 oappend (scratchbuf);
14463 && (disp || modrm.mod != 0 || base == 5))
14465 if (!havedisp || (bfd_signed_vma) disp >= 0)
14470 else if (modrm.mod != 1 && disp != -disp)
14474 disp = - (bfd_signed_vma) disp;
14478 print_displacement (scratchbuf, disp);
14480 print_operand_value (scratchbuf, 1, disp);
14481 oappend (scratchbuf);
14484 *obufp++ = close_char;
14487 else if (intel_syntax)
14489 if (modrm.mod != 0 || base == 5)
14491 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
14492 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
14496 oappend (names_seg[ds_reg - es_reg]);
14499 print_operand_value (scratchbuf, 1, disp);
14500 oappend (scratchbuf);
14506 /* 16 bit address mode */
14507 used_prefixes |= prefixes & PREFIX_ADDR;
14514 if ((disp & 0x8000) != 0)
14519 FETCH_DATA (the_info, codep + 1);
14521 if ((disp & 0x80) != 0)
14526 if ((disp & 0x8000) != 0)
14532 if (modrm.mod != 0 || modrm.rm == 6)
14534 print_displacement (scratchbuf, disp);
14535 oappend (scratchbuf);
14538 if (modrm.mod != 0 || modrm.rm != 6)
14540 *obufp++ = open_char;
14542 oappend (index16[modrm.rm]);
14544 && (disp || modrm.mod != 0 || modrm.rm == 6))
14546 if ((bfd_signed_vma) disp >= 0)
14551 else if (modrm.mod != 1)
14555 disp = - (bfd_signed_vma) disp;
14558 print_displacement (scratchbuf, disp);
14559 oappend (scratchbuf);
14562 *obufp++ = close_char;
14565 else if (intel_syntax)
14567 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
14568 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
14572 oappend (names_seg[ds_reg - es_reg]);
14575 print_operand_value (scratchbuf, 1, disp & 0xffff);
14576 oappend (scratchbuf);
14579 if (vex.evex && vex.b
14580 && (bytemode == x_mode
14581 || bytemode == evex_half_bcst_xmmq_mode))
14583 if (vex.w || bytemode == evex_half_bcst_xmmq_mode)
14584 oappend ("{1to8}");
14586 oappend ("{1to16}");
14591 OP_E (int bytemode, int sizeflag)
14593 /* Skip mod/rm byte. */
14597 if (modrm.mod == 3)
14598 OP_E_register (bytemode, sizeflag);
14600 OP_E_memory (bytemode, sizeflag);
14604 OP_G (int bytemode, int sizeflag)
14615 oappend (names8rex[modrm.reg + add]);
14617 oappend (names8[modrm.reg + add]);
14620 oappend (names16[modrm.reg + add]);
14623 oappend (names32[modrm.reg + add]);
14626 oappend (names64[modrm.reg + add]);
14629 oappend (names_bnd[modrm.reg]);
14638 oappend (names64[modrm.reg + add]);
14641 if ((sizeflag & DFLAG) || bytemode != v_mode)
14642 oappend (names32[modrm.reg + add]);
14644 oappend (names16[modrm.reg + add]);
14645 used_prefixes |= (prefixes & PREFIX_DATA);
14649 if (address_mode == mode_64bit)
14650 oappend (names64[modrm.reg + add]);
14652 oappend (names32[modrm.reg + add]);
14655 oappend (names_mask[modrm.reg + add]);
14658 oappend (INTERNAL_DISASSEMBLER_ERROR);
14671 FETCH_DATA (the_info, codep + 8);
14672 a = *codep++ & 0xff;
14673 a |= (*codep++ & 0xff) << 8;
14674 a |= (*codep++ & 0xff) << 16;
14675 a |= (*codep++ & 0xff) << 24;
14676 b = *codep++ & 0xff;
14677 b |= (*codep++ & 0xff) << 8;
14678 b |= (*codep++ & 0xff) << 16;
14679 b |= (*codep++ & 0xff) << 24;
14680 x = a + ((bfd_vma) b << 32);
14688 static bfd_signed_vma
14691 bfd_signed_vma x = 0;
14693 FETCH_DATA (the_info, codep + 4);
14694 x = *codep++ & (bfd_signed_vma) 0xff;
14695 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14696 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14697 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14701 static bfd_signed_vma
14704 bfd_signed_vma x = 0;
14706 FETCH_DATA (the_info, codep + 4);
14707 x = *codep++ & (bfd_signed_vma) 0xff;
14708 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14709 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14710 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14712 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14722 FETCH_DATA (the_info, codep + 2);
14723 x = *codep++ & 0xff;
14724 x |= (*codep++ & 0xff) << 8;
14729 set_op (bfd_vma op, int riprel)
14731 op_index[op_ad] = op_ad;
14732 if (address_mode == mode_64bit)
14734 op_address[op_ad] = op;
14735 op_riprel[op_ad] = riprel;
14739 /* Mask to get a 32-bit address. */
14740 op_address[op_ad] = op & 0xffffffff;
14741 op_riprel[op_ad] = riprel & 0xffffffff;
14746 OP_REG (int code, int sizeflag)
14753 case es_reg: case ss_reg: case cs_reg:
14754 case ds_reg: case fs_reg: case gs_reg:
14755 oappend (names_seg[code - es_reg]);
14767 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14768 case sp_reg: case bp_reg: case si_reg: case di_reg:
14769 s = names16[code - ax_reg + add];
14771 case al_reg: case ah_reg: case cl_reg: case ch_reg:
14772 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14775 s = names8rex[code - al_reg + add];
14777 s = names8[code - al_reg];
14779 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14780 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14781 if (address_mode == mode_64bit
14782 && ((sizeflag & DFLAG) || (rex & REX_W)))
14784 s = names64[code - rAX_reg + add];
14787 code += eAX_reg - rAX_reg;
14788 /* Fall through. */
14789 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14790 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14793 s = names64[code - eAX_reg + add];
14796 if (sizeflag & DFLAG)
14797 s = names32[code - eAX_reg + add];
14799 s = names16[code - eAX_reg + add];
14800 used_prefixes |= (prefixes & PREFIX_DATA);
14804 s = INTERNAL_DISASSEMBLER_ERROR;
14811 OP_IMREG (int code, int sizeflag)
14823 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14824 case sp_reg: case bp_reg: case si_reg: case di_reg:
14825 s = names16[code - ax_reg];
14827 case es_reg: case ss_reg: case cs_reg:
14828 case ds_reg: case fs_reg: case gs_reg:
14829 s = names_seg[code - es_reg];
14831 case al_reg: case ah_reg: case cl_reg: case ch_reg:
14832 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14835 s = names8rex[code - al_reg];
14837 s = names8[code - al_reg];
14839 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14840 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14843 s = names64[code - eAX_reg];
14846 if (sizeflag & DFLAG)
14847 s = names32[code - eAX_reg];
14849 s = names16[code - eAX_reg];
14850 used_prefixes |= (prefixes & PREFIX_DATA);
14853 case z_mode_ax_reg:
14854 if ((rex & REX_W) || (sizeflag & DFLAG))
14858 if (!(rex & REX_W))
14859 used_prefixes |= (prefixes & PREFIX_DATA);
14862 s = INTERNAL_DISASSEMBLER_ERROR;
14869 OP_I (int bytemode, int sizeflag)
14872 bfd_signed_vma mask = -1;
14877 FETCH_DATA (the_info, codep + 1);
14882 if (address_mode == mode_64bit)
14887 /* Fall through. */
14894 if (sizeflag & DFLAG)
14904 used_prefixes |= (prefixes & PREFIX_DATA);
14916 oappend (INTERNAL_DISASSEMBLER_ERROR);
14921 scratchbuf[0] = '$';
14922 print_operand_value (scratchbuf + 1, 1, op);
14923 oappend_maybe_intel (scratchbuf);
14924 scratchbuf[0] = '\0';
14928 OP_I64 (int bytemode, int sizeflag)
14931 bfd_signed_vma mask = -1;
14933 if (address_mode != mode_64bit)
14935 OP_I (bytemode, sizeflag);
14942 FETCH_DATA (the_info, codep + 1);
14952 if (sizeflag & DFLAG)
14962 used_prefixes |= (prefixes & PREFIX_DATA);
14970 oappend (INTERNAL_DISASSEMBLER_ERROR);
14975 scratchbuf[0] = '$';
14976 print_operand_value (scratchbuf + 1, 1, op);
14977 oappend_maybe_intel (scratchbuf);
14978 scratchbuf[0] = '\0';
14982 OP_sI (int bytemode, int sizeflag)
14990 FETCH_DATA (the_info, codep + 1);
14992 if ((op & 0x80) != 0)
14994 if (bytemode == b_T_mode)
14996 if (address_mode != mode_64bit
14997 || !((sizeflag & DFLAG) || (rex & REX_W)))
14999 /* The operand-size prefix is overridden by a REX prefix. */
15000 if ((sizeflag & DFLAG) || (rex & REX_W))
15008 if (!(rex & REX_W))
15010 if (sizeflag & DFLAG)
15018 /* The operand-size prefix is overridden by a REX prefix. */
15019 if ((sizeflag & DFLAG) || (rex & REX_W))
15025 oappend (INTERNAL_DISASSEMBLER_ERROR);
15029 scratchbuf[0] = '$';
15030 print_operand_value (scratchbuf + 1, 1, op);
15031 oappend_maybe_intel (scratchbuf);
15035 OP_J (int bytemode, int sizeflag)
15039 bfd_vma segment = 0;
15044 FETCH_DATA (the_info, codep + 1);
15046 if ((disp & 0x80) != 0)
15051 if ((sizeflag & DFLAG) || (rex & REX_W))
15056 if ((disp & 0x8000) != 0)
15058 /* In 16bit mode, address is wrapped around at 64k within
15059 the same segment. Otherwise, a data16 prefix on a jump
15060 instruction means that the pc is masked to 16 bits after
15061 the displacement is added! */
15063 if ((prefixes & PREFIX_DATA) == 0)
15064 segment = ((start_pc + codep - start_codep)
15065 & ~((bfd_vma) 0xffff));
15067 if (!(rex & REX_W))
15068 used_prefixes |= (prefixes & PREFIX_DATA);
15071 oappend (INTERNAL_DISASSEMBLER_ERROR);
15074 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15076 print_operand_value (scratchbuf, 1, disp);
15077 oappend (scratchbuf);
15081 OP_SEG (int bytemode, int sizeflag)
15083 if (bytemode == w_mode)
15084 oappend (names_seg[modrm.reg]);
15086 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15090 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15094 if (sizeflag & DFLAG)
15104 used_prefixes |= (prefixes & PREFIX_DATA);
15106 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15108 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15109 oappend (scratchbuf);
15113 OP_OFF (int bytemode, int sizeflag)
15117 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15118 intel_operand_size (bytemode, sizeflag);
15121 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15128 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
15129 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
15131 oappend (names_seg[ds_reg - es_reg]);
15135 print_operand_value (scratchbuf, 1, off);
15136 oappend (scratchbuf);
15140 OP_OFF64 (int bytemode, int sizeflag)
15144 if (address_mode != mode_64bit
15145 || (prefixes & PREFIX_ADDR))
15147 OP_OFF (bytemode, sizeflag);
15151 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15152 intel_operand_size (bytemode, sizeflag);
15159 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
15160 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
15162 oappend (names_seg[ds_reg - es_reg]);
15166 print_operand_value (scratchbuf, 1, off);
15167 oappend (scratchbuf);
15171 ptr_reg (int code, int sizeflag)
15175 *obufp++ = open_char;
15176 used_prefixes |= (prefixes & PREFIX_ADDR);
15177 if (address_mode == mode_64bit)
15179 if (!(sizeflag & AFLAG))
15180 s = names32[code - eAX_reg];
15182 s = names64[code - eAX_reg];
15184 else if (sizeflag & AFLAG)
15185 s = names32[code - eAX_reg];
15187 s = names16[code - eAX_reg];
15189 *obufp++ = close_char;
15194 OP_ESreg (int code, int sizeflag)
15200 case 0x6d: /* insw/insl */
15201 intel_operand_size (z_mode, sizeflag);
15203 case 0xa5: /* movsw/movsl/movsq */
15204 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15205 case 0xab: /* stosw/stosl */
15206 case 0xaf: /* scasw/scasl */
15207 intel_operand_size (v_mode, sizeflag);
15210 intel_operand_size (b_mode, sizeflag);
15213 oappend_maybe_intel ("%es:");
15214 ptr_reg (code, sizeflag);
15218 OP_DSreg (int code, int sizeflag)
15224 case 0x6f: /* outsw/outsl */
15225 intel_operand_size (z_mode, sizeflag);
15227 case 0xa5: /* movsw/movsl/movsq */
15228 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15229 case 0xad: /* lodsw/lodsl/lodsq */
15230 intel_operand_size (v_mode, sizeflag);
15233 intel_operand_size (b_mode, sizeflag);
15242 | PREFIX_GS)) == 0)
15243 prefixes |= PREFIX_DS;
15245 ptr_reg (code, sizeflag);
15249 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15257 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15259 all_prefixes[last_lock_prefix] = 0;
15260 used_prefixes |= PREFIX_LOCK;
15265 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15266 oappend_maybe_intel (scratchbuf);
15270 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15279 sprintf (scratchbuf, "db%d", modrm.reg + add);
15281 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15282 oappend (scratchbuf);
15286 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15288 sprintf (scratchbuf, "%%tr%d", modrm.reg);
15289 oappend_maybe_intel (scratchbuf);
15293 OP_R (int bytemode, int sizeflag)
15295 if (modrm.mod == 3)
15296 OP_E (bytemode, sizeflag);
15302 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15304 int reg = modrm.reg;
15305 const char **names;
15307 used_prefixes |= (prefixes & PREFIX_DATA);
15308 if (prefixes & PREFIX_DATA)
15317 oappend (names[reg]);
15321 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15323 int reg = modrm.reg;
15324 const char **names;
15336 && bytemode != xmm_mode
15337 && bytemode != xmmq_mode
15338 && bytemode != evex_half_bcst_xmmq_mode
15339 && bytemode != ymm_mode
15340 && bytemode != scalar_mode)
15342 switch (vex.length)
15348 if (vex.w || bytemode != vex_vsib_q_w_dq_mode)
15360 else if (bytemode == xmmq_mode
15361 || bytemode == evex_half_bcst_xmmq_mode)
15363 switch (vex.length)
15376 else if (bytemode == ymm_mode)
15380 oappend (names[reg]);
15384 OP_EM (int bytemode, int sizeflag)
15387 const char **names;
15389 if (modrm.mod != 3)
15392 && (bytemode == v_mode || bytemode == v_swap_mode))
15394 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15395 used_prefixes |= (prefixes & PREFIX_DATA);
15397 OP_E (bytemode, sizeflag);
15401 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15404 /* Skip mod/rm byte. */
15407 used_prefixes |= (prefixes & PREFIX_DATA);
15409 if (prefixes & PREFIX_DATA)
15418 oappend (names[reg]);
15421 /* cvt* are the only instructions in sse2 which have
15422 both SSE and MMX operands and also have 0x66 prefix
15423 in their opcode. 0x66 was originally used to differentiate
15424 between SSE and MMX instruction(operands). So we have to handle the
15425 cvt* separately using OP_EMC and OP_MXC */
15427 OP_EMC (int bytemode, int sizeflag)
15429 if (modrm.mod != 3)
15431 if (intel_syntax && bytemode == v_mode)
15433 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15434 used_prefixes |= (prefixes & PREFIX_DATA);
15436 OP_E (bytemode, sizeflag);
15440 /* Skip mod/rm byte. */
15443 used_prefixes |= (prefixes & PREFIX_DATA);
15444 oappend (names_mm[modrm.rm]);
15448 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15450 used_prefixes |= (prefixes & PREFIX_DATA);
15451 oappend (names_mm[modrm.reg]);
15455 OP_EX (int bytemode, int sizeflag)
15458 const char **names;
15460 /* Skip mod/rm byte. */
15464 if (modrm.mod != 3)
15466 OP_E_memory (bytemode, sizeflag);
15481 if ((sizeflag & SUFFIX_ALWAYS)
15482 && (bytemode == x_swap_mode
15483 || bytemode == d_swap_mode
15484 || bytemode == d_scalar_swap_mode
15485 || bytemode == q_swap_mode
15486 || bytemode == q_scalar_swap_mode))
15490 && bytemode != xmm_mode
15491 && bytemode != xmmdw_mode
15492 && bytemode != xmmqd_mode
15493 && bytemode != xmm_mb_mode
15494 && bytemode != xmm_mw_mode
15495 && bytemode != xmm_md_mode
15496 && bytemode != xmm_mq_mode
15497 && bytemode != xmm_mdq_mode
15498 && bytemode != xmmq_mode
15499 && bytemode != evex_half_bcst_xmmq_mode
15500 && bytemode != ymm_mode
15501 && bytemode != d_scalar_mode
15502 && bytemode != d_scalar_swap_mode
15503 && bytemode != q_scalar_mode
15504 && bytemode != q_scalar_swap_mode
15505 && bytemode != vex_scalar_w_dq_mode)
15507 switch (vex.length)
15522 else if (bytemode == xmmq_mode
15523 || bytemode == evex_half_bcst_xmmq_mode)
15525 switch (vex.length)
15538 else if (bytemode == ymm_mode)
15542 oappend (names[reg]);
15546 OP_MS (int bytemode, int sizeflag)
15548 if (modrm.mod == 3)
15549 OP_EM (bytemode, sizeflag);
15555 OP_XS (int bytemode, int sizeflag)
15557 if (modrm.mod == 3)
15558 OP_EX (bytemode, sizeflag);
15564 OP_M (int bytemode, int sizeflag)
15566 if (modrm.mod == 3)
15567 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15570 OP_E (bytemode, sizeflag);
15574 OP_0f07 (int bytemode, int sizeflag)
15576 if (modrm.mod != 3 || modrm.rm != 0)
15579 OP_E (bytemode, sizeflag);
15582 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15583 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15586 NOP_Fixup1 (int bytemode, int sizeflag)
15588 if ((prefixes & PREFIX_DATA) != 0
15591 && address_mode == mode_64bit))
15592 OP_REG (bytemode, sizeflag);
15594 strcpy (obuf, "nop");
15598 NOP_Fixup2 (int bytemode, int sizeflag)
15600 if ((prefixes & PREFIX_DATA) != 0
15603 && address_mode == mode_64bit))
15604 OP_IMREG (bytemode, sizeflag);
15607 static const char *const Suffix3DNow[] = {
15608 /* 00 */ NULL, NULL, NULL, NULL,
15609 /* 04 */ NULL, NULL, NULL, NULL,
15610 /* 08 */ NULL, NULL, NULL, NULL,
15611 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
15612 /* 10 */ NULL, NULL, NULL, NULL,
15613 /* 14 */ NULL, NULL, NULL, NULL,
15614 /* 18 */ NULL, NULL, NULL, NULL,
15615 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
15616 /* 20 */ NULL, NULL, NULL, NULL,
15617 /* 24 */ NULL, NULL, NULL, NULL,
15618 /* 28 */ NULL, NULL, NULL, NULL,
15619 /* 2C */ NULL, NULL, NULL, NULL,
15620 /* 30 */ NULL, NULL, NULL, NULL,
15621 /* 34 */ NULL, NULL, NULL, NULL,
15622 /* 38 */ NULL, NULL, NULL, NULL,
15623 /* 3C */ NULL, NULL, NULL, NULL,
15624 /* 40 */ NULL, NULL, NULL, NULL,
15625 /* 44 */ NULL, NULL, NULL, NULL,
15626 /* 48 */ NULL, NULL, NULL, NULL,
15627 /* 4C */ NULL, NULL, NULL, NULL,
15628 /* 50 */ NULL, NULL, NULL, NULL,
15629 /* 54 */ NULL, NULL, NULL, NULL,
15630 /* 58 */ NULL, NULL, NULL, NULL,
15631 /* 5C */ NULL, NULL, NULL, NULL,
15632 /* 60 */ NULL, NULL, NULL, NULL,
15633 /* 64 */ NULL, NULL, NULL, NULL,
15634 /* 68 */ NULL, NULL, NULL, NULL,
15635 /* 6C */ NULL, NULL, NULL, NULL,
15636 /* 70 */ NULL, NULL, NULL, NULL,
15637 /* 74 */ NULL, NULL, NULL, NULL,
15638 /* 78 */ NULL, NULL, NULL, NULL,
15639 /* 7C */ NULL, NULL, NULL, NULL,
15640 /* 80 */ NULL, NULL, NULL, NULL,
15641 /* 84 */ NULL, NULL, NULL, NULL,
15642 /* 88 */ NULL, NULL, "pfnacc", NULL,
15643 /* 8C */ NULL, NULL, "pfpnacc", NULL,
15644 /* 90 */ "pfcmpge", NULL, NULL, NULL,
15645 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
15646 /* 98 */ NULL, NULL, "pfsub", NULL,
15647 /* 9C */ NULL, NULL, "pfadd", NULL,
15648 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
15649 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
15650 /* A8 */ NULL, NULL, "pfsubr", NULL,
15651 /* AC */ NULL, NULL, "pfacc", NULL,
15652 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
15653 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
15654 /* B8 */ NULL, NULL, NULL, "pswapd",
15655 /* BC */ NULL, NULL, NULL, "pavgusb",
15656 /* C0 */ NULL, NULL, NULL, NULL,
15657 /* C4 */ NULL, NULL, NULL, NULL,
15658 /* C8 */ NULL, NULL, NULL, NULL,
15659 /* CC */ NULL, NULL, NULL, NULL,
15660 /* D0 */ NULL, NULL, NULL, NULL,
15661 /* D4 */ NULL, NULL, NULL, NULL,
15662 /* D8 */ NULL, NULL, NULL, NULL,
15663 /* DC */ NULL, NULL, NULL, NULL,
15664 /* E0 */ NULL, NULL, NULL, NULL,
15665 /* E4 */ NULL, NULL, NULL, NULL,
15666 /* E8 */ NULL, NULL, NULL, NULL,
15667 /* EC */ NULL, NULL, NULL, NULL,
15668 /* F0 */ NULL, NULL, NULL, NULL,
15669 /* F4 */ NULL, NULL, NULL, NULL,
15670 /* F8 */ NULL, NULL, NULL, NULL,
15671 /* FC */ NULL, NULL, NULL, NULL,
15675 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15677 const char *mnemonic;
15679 FETCH_DATA (the_info, codep + 1);
15680 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15681 place where an 8-bit immediate would normally go. ie. the last
15682 byte of the instruction. */
15683 obufp = mnemonicendp;
15684 mnemonic = Suffix3DNow[*codep++ & 0xff];
15686 oappend (mnemonic);
15689 /* Since a variable sized modrm/sib chunk is between the start
15690 of the opcode (0x0f0f) and the opcode suffix, we need to do
15691 all the modrm processing first, and don't know until now that
15692 we have a bad opcode. This necessitates some cleaning up. */
15693 op_out[0][0] = '\0';
15694 op_out[1][0] = '\0';
15697 mnemonicendp = obufp;
15700 static struct op simd_cmp_op[] =
15702 { STRING_COMMA_LEN ("eq") },
15703 { STRING_COMMA_LEN ("lt") },
15704 { STRING_COMMA_LEN ("le") },
15705 { STRING_COMMA_LEN ("unord") },
15706 { STRING_COMMA_LEN ("neq") },
15707 { STRING_COMMA_LEN ("nlt") },
15708 { STRING_COMMA_LEN ("nle") },
15709 { STRING_COMMA_LEN ("ord") }
15713 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15715 unsigned int cmp_type;
15717 FETCH_DATA (the_info, codep + 1);
15718 cmp_type = *codep++ & 0xff;
15719 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15722 char *p = mnemonicendp - 2;
15726 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15727 mnemonicendp += simd_cmp_op[cmp_type].len;
15731 /* We have a reserved extension byte. Output it directly. */
15732 scratchbuf[0] = '$';
15733 print_operand_value (scratchbuf + 1, 1, cmp_type);
15734 oappend_maybe_intel (scratchbuf);
15735 scratchbuf[0] = '\0';
15740 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15741 int sizeflag ATTRIBUTE_UNUSED)
15743 /* mwait %eax,%ecx */
15746 const char **names = (address_mode == mode_64bit
15747 ? names64 : names32);
15748 strcpy (op_out[0], names[0]);
15749 strcpy (op_out[1], names[1]);
15750 two_source_ops = 1;
15752 /* Skip mod/rm byte. */
15758 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15759 int sizeflag ATTRIBUTE_UNUSED)
15761 /* monitor %eax,%ecx,%edx" */
15764 const char **op1_names;
15765 const char **names = (address_mode == mode_64bit
15766 ? names64 : names32);
15768 if (!(prefixes & PREFIX_ADDR))
15769 op1_names = (address_mode == mode_16bit
15770 ? names16 : names);
15773 /* Remove "addr16/addr32". */
15774 all_prefixes[last_addr_prefix] = 0;
15775 op1_names = (address_mode != mode_32bit
15776 ? names32 : names16);
15777 used_prefixes |= PREFIX_ADDR;
15779 strcpy (op_out[0], op1_names[0]);
15780 strcpy (op_out[1], names[1]);
15781 strcpy (op_out[2], names[2]);
15782 two_source_ops = 1;
15784 /* Skip mod/rm byte. */
15792 /* Throw away prefixes and 1st. opcode byte. */
15793 codep = insn_codep + 1;
15798 REP_Fixup (int bytemode, int sizeflag)
15800 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15802 if (prefixes & PREFIX_REPZ)
15803 all_prefixes[last_repz_prefix] = REP_PREFIX;
15810 OP_IMREG (bytemode, sizeflag);
15813 OP_ESreg (bytemode, sizeflag);
15816 OP_DSreg (bytemode, sizeflag);
15824 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15828 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15830 if (prefixes & PREFIX_REPNZ)
15831 all_prefixes[last_repnz_prefix] = BND_PREFIX;
15834 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15835 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15839 HLE_Fixup1 (int bytemode, int sizeflag)
15842 && (prefixes & PREFIX_LOCK) != 0)
15844 if (prefixes & PREFIX_REPZ)
15845 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15846 if (prefixes & PREFIX_REPNZ)
15847 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15850 OP_E (bytemode, sizeflag);
15853 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15854 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15858 HLE_Fixup2 (int bytemode, int sizeflag)
15860 if (modrm.mod != 3)
15862 if (prefixes & PREFIX_REPZ)
15863 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15864 if (prefixes & PREFIX_REPNZ)
15865 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15868 OP_E (bytemode, sizeflag);
15871 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15872 "xrelease" for memory operand. No check for LOCK prefix. */
15875 HLE_Fixup3 (int bytemode, int sizeflag)
15878 && last_repz_prefix > last_repnz_prefix
15879 && (prefixes & PREFIX_REPZ) != 0)
15880 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15882 OP_E (bytemode, sizeflag);
15886 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15891 /* Change cmpxchg8b to cmpxchg16b. */
15892 char *p = mnemonicendp - 2;
15893 mnemonicendp = stpcpy (p, "16b");
15896 else if ((prefixes & PREFIX_LOCK) != 0)
15898 if (prefixes & PREFIX_REPZ)
15899 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15900 if (prefixes & PREFIX_REPNZ)
15901 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15904 OP_M (bytemode, sizeflag);
15908 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15910 const char **names;
15914 switch (vex.length)
15928 oappend (names[reg]);
15932 CRC32_Fixup (int bytemode, int sizeflag)
15934 /* Add proper suffix to "crc32". */
15935 char *p = mnemonicendp;
15954 if (sizeflag & DFLAG)
15958 used_prefixes |= (prefixes & PREFIX_DATA);
15962 oappend (INTERNAL_DISASSEMBLER_ERROR);
15969 if (modrm.mod == 3)
15973 /* Skip mod/rm byte. */
15978 add = (rex & REX_B) ? 8 : 0;
15979 if (bytemode == b_mode)
15983 oappend (names8rex[modrm.rm + add]);
15985 oappend (names8[modrm.rm + add]);
15991 oappend (names64[modrm.rm + add]);
15992 else if ((prefixes & PREFIX_DATA))
15993 oappend (names16[modrm.rm + add]);
15995 oappend (names32[modrm.rm + add]);
15999 OP_E (bytemode, sizeflag);
16003 FXSAVE_Fixup (int bytemode, int sizeflag)
16005 /* Add proper suffix to "fxsave" and "fxrstor". */
16009 char *p = mnemonicendp;
16015 OP_M (bytemode, sizeflag);
16018 /* Display the destination register operand for instructions with
16022 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16025 const char **names;
16033 reg = vex.register_specifier;
16040 if (bytemode == vex_scalar_mode)
16042 oappend (names_xmm[reg]);
16046 switch (vex.length)
16053 case vex_vsib_q_w_dq_mode:
16063 names = names_mask;
16077 case vex_vsib_q_w_dq_mode:
16078 names = vex.w ? names_ymm : names_xmm;
16081 names = names_mask;
16095 oappend (names[reg]);
16098 /* Get the VEX immediate byte without moving codep. */
16100 static unsigned char
16101 get_vex_imm8 (int sizeflag, int opnum)
16103 int bytes_before_imm = 0;
16105 if (modrm.mod != 3)
16107 /* There are SIB/displacement bytes. */
16108 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16110 /* 32/64 bit address mode */
16111 int base = modrm.rm;
16113 /* Check SIB byte. */
16116 FETCH_DATA (the_info, codep + 1);
16118 /* When decoding the third source, don't increase
16119 bytes_before_imm as this has already been incremented
16120 by one in OP_E_memory while decoding the second
16123 bytes_before_imm++;
16126 /* Don't increase bytes_before_imm when decoding the third source,
16127 it has already been incremented by OP_E_memory while decoding
16128 the second source operand. */
16134 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16135 SIB == 5, there is a 4 byte displacement. */
16137 /* No displacement. */
16140 /* 4 byte displacement. */
16141 bytes_before_imm += 4;
16144 /* 1 byte displacement. */
16145 bytes_before_imm++;
16152 /* 16 bit address mode */
16153 /* Don't increase bytes_before_imm when decoding the third source,
16154 it has already been incremented by OP_E_memory while decoding
16155 the second source operand. */
16161 /* When modrm.rm == 6, there is a 2 byte displacement. */
16163 /* No displacement. */
16166 /* 2 byte displacement. */
16167 bytes_before_imm += 2;
16170 /* 1 byte displacement: when decoding the third source,
16171 don't increase bytes_before_imm as this has already
16172 been incremented by one in OP_E_memory while decoding
16173 the second source operand. */
16175 bytes_before_imm++;
16183 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16184 return codep [bytes_before_imm];
16188 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16190 const char **names;
16192 if (reg == -1 && modrm.mod != 3)
16194 OP_E_memory (bytemode, sizeflag);
16206 else if (reg > 7 && address_mode != mode_64bit)
16210 switch (vex.length)
16221 oappend (names[reg]);
16225 OP_EX_VexImmW (int bytemode, int sizeflag)
16228 static unsigned char vex_imm8;
16230 if (vex_w_done == 0)
16234 /* Skip mod/rm byte. */
16238 vex_imm8 = get_vex_imm8 (sizeflag, 0);
16241 reg = vex_imm8 >> 4;
16243 OP_EX_VexReg (bytemode, sizeflag, reg);
16245 else if (vex_w_done == 1)
16250 reg = vex_imm8 >> 4;
16252 OP_EX_VexReg (bytemode, sizeflag, reg);
16256 /* Output the imm8 directly. */
16257 scratchbuf[0] = '$';
16258 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16259 oappend_maybe_intel (scratchbuf);
16260 scratchbuf[0] = '\0';
16266 OP_Vex_2src (int bytemode, int sizeflag)
16268 if (modrm.mod == 3)
16270 int reg = modrm.rm;
16274 oappend (names_xmm[reg]);
16279 && (bytemode == v_mode || bytemode == v_swap_mode))
16281 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16282 used_prefixes |= (prefixes & PREFIX_DATA);
16284 OP_E (bytemode, sizeflag);
16289 OP_Vex_2src_1 (int bytemode, int sizeflag)
16291 if (modrm.mod == 3)
16293 /* Skip mod/rm byte. */
16299 oappend (names_xmm[vex.register_specifier]);
16301 OP_Vex_2src (bytemode, sizeflag);
16305 OP_Vex_2src_2 (int bytemode, int sizeflag)
16308 OP_Vex_2src (bytemode, sizeflag);
16310 oappend (names_xmm[vex.register_specifier]);
16314 OP_EX_VexW (int bytemode, int sizeflag)
16322 /* Skip mod/rm byte. */
16327 reg = get_vex_imm8 (sizeflag, 0) >> 4;
16332 reg = get_vex_imm8 (sizeflag, 1) >> 4;
16335 OP_EX_VexReg (bytemode, sizeflag, reg);
16339 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16340 int sizeflag ATTRIBUTE_UNUSED)
16342 /* Skip the immediate byte and check for invalid bits. */
16343 FETCH_DATA (the_info, codep + 1);
16344 if (*codep++ & 0xf)
16349 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16352 const char **names;
16354 FETCH_DATA (the_info, codep + 1);
16357 if (bytemode != x_mode)
16364 if (reg > 7 && address_mode != mode_64bit)
16367 switch (vex.length)
16378 oappend (names[reg]);
16382 OP_XMM_VexW (int bytemode, int sizeflag)
16384 /* Turn off the REX.W bit since it is used for swapping operands
16387 OP_XMM (bytemode, sizeflag);
16391 OP_EX_Vex (int bytemode, int sizeflag)
16393 if (modrm.mod != 3)
16395 if (vex.register_specifier != 0)
16399 OP_EX (bytemode, sizeflag);
16403 OP_XMM_Vex (int bytemode, int sizeflag)
16405 if (modrm.mod != 3)
16407 if (vex.register_specifier != 0)
16411 OP_XMM (bytemode, sizeflag);
16415 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16417 switch (vex.length)
16420 mnemonicendp = stpcpy (obuf, "vzeroupper");
16423 mnemonicendp = stpcpy (obuf, "vzeroall");
16430 static struct op vex_cmp_op[] =
16432 { STRING_COMMA_LEN ("eq") },
16433 { STRING_COMMA_LEN ("lt") },
16434 { STRING_COMMA_LEN ("le") },
16435 { STRING_COMMA_LEN ("unord") },
16436 { STRING_COMMA_LEN ("neq") },
16437 { STRING_COMMA_LEN ("nlt") },
16438 { STRING_COMMA_LEN ("nle") },
16439 { STRING_COMMA_LEN ("ord") },
16440 { STRING_COMMA_LEN ("eq_uq") },
16441 { STRING_COMMA_LEN ("nge") },
16442 { STRING_COMMA_LEN ("ngt") },
16443 { STRING_COMMA_LEN ("false") },
16444 { STRING_COMMA_LEN ("neq_oq") },
16445 { STRING_COMMA_LEN ("ge") },
16446 { STRING_COMMA_LEN ("gt") },
16447 { STRING_COMMA_LEN ("true") },
16448 { STRING_COMMA_LEN ("eq_os") },
16449 { STRING_COMMA_LEN ("lt_oq") },
16450 { STRING_COMMA_LEN ("le_oq") },
16451 { STRING_COMMA_LEN ("unord_s") },
16452 { STRING_COMMA_LEN ("neq_us") },
16453 { STRING_COMMA_LEN ("nlt_uq") },
16454 { STRING_COMMA_LEN ("nle_uq") },
16455 { STRING_COMMA_LEN ("ord_s") },
16456 { STRING_COMMA_LEN ("eq_us") },
16457 { STRING_COMMA_LEN ("nge_uq") },
16458 { STRING_COMMA_LEN ("ngt_uq") },
16459 { STRING_COMMA_LEN ("false_os") },
16460 { STRING_COMMA_LEN ("neq_os") },
16461 { STRING_COMMA_LEN ("ge_oq") },
16462 { STRING_COMMA_LEN ("gt_oq") },
16463 { STRING_COMMA_LEN ("true_us") },
16467 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16469 unsigned int cmp_type;
16471 FETCH_DATA (the_info, codep + 1);
16472 cmp_type = *codep++ & 0xff;
16473 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16476 char *p = mnemonicendp - 2;
16480 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16481 mnemonicendp += vex_cmp_op[cmp_type].len;
16485 /* We have a reserved extension byte. Output it directly. */
16486 scratchbuf[0] = '$';
16487 print_operand_value (scratchbuf + 1, 1, cmp_type);
16488 oappend_maybe_intel (scratchbuf);
16489 scratchbuf[0] = '\0';
16494 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16495 int sizeflag ATTRIBUTE_UNUSED)
16497 unsigned int cmp_type;
16502 FETCH_DATA (the_info, codep + 1);
16503 cmp_type = *codep++ & 0xff;
16504 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16505 If it's the case, print suffix, otherwise - print the immediate. */
16506 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16511 char *p = mnemonicendp - 2;
16513 /* vpcmp* can have both one- and two-lettered suffix. */
16527 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16528 mnemonicendp += simd_cmp_op[cmp_type].len;
16532 /* We have a reserved extension byte. Output it directly. */
16533 scratchbuf[0] = '$';
16534 print_operand_value (scratchbuf + 1, 1, cmp_type);
16535 oappend_maybe_intel (scratchbuf);
16536 scratchbuf[0] = '\0';
16540 static const struct op pclmul_op[] =
16542 { STRING_COMMA_LEN ("lql") },
16543 { STRING_COMMA_LEN ("hql") },
16544 { STRING_COMMA_LEN ("lqh") },
16545 { STRING_COMMA_LEN ("hqh") }
16549 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16550 int sizeflag ATTRIBUTE_UNUSED)
16552 unsigned int pclmul_type;
16554 FETCH_DATA (the_info, codep + 1);
16555 pclmul_type = *codep++ & 0xff;
16556 switch (pclmul_type)
16567 if (pclmul_type < ARRAY_SIZE (pclmul_op))
16570 char *p = mnemonicendp - 3;
16575 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16576 mnemonicendp += pclmul_op[pclmul_type].len;
16580 /* We have a reserved extension byte. Output it directly. */
16581 scratchbuf[0] = '$';
16582 print_operand_value (scratchbuf + 1, 1, pclmul_type);
16583 oappend_maybe_intel (scratchbuf);
16584 scratchbuf[0] = '\0';
16589 MOVBE_Fixup (int bytemode, int sizeflag)
16591 /* Add proper suffix to "movbe". */
16592 char *p = mnemonicendp;
16601 if (sizeflag & SUFFIX_ALWAYS)
16607 if (sizeflag & DFLAG)
16611 used_prefixes |= (prefixes & PREFIX_DATA);
16616 oappend (INTERNAL_DISASSEMBLER_ERROR);
16623 OP_M (bytemode, sizeflag);
16627 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16630 const char **names;
16632 /* Skip mod/rm byte. */
16646 oappend (names[reg]);
16650 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16652 const char **names;
16659 oappend (names[vex.register_specifier]);
16663 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16666 || bytemode != mask_mode)
16670 if ((rex & REX_R) != 0 || !vex.r)
16676 oappend (names_mask [modrm.reg]);
16680 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16683 || (bytemode != evex_rounding_mode
16684 && bytemode != evex_sae_mode))
16686 if (modrm.mod == 3 && vex.b)
16689 case evex_rounding_mode:
16690 oappend (names_rounding[vex.ll]);
16692 case evex_sae_mode: