1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2019 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma, disassemble_info *);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma get64 (void);
58 static bfd_signed_vma get32 (void);
59 static bfd_signed_vma get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VCMP_Fixup (int, int);
99 static void VPCMP_Fixup (int, int);
100 static void VPCOM_Fixup (int, int);
101 static void OP_0f07 (int, int);
102 static void OP_Monitor (int, int);
103 static void OP_Mwait (int, int);
104 static void OP_Mwaitx (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void NOTRACK_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void PCMPESTR_Fixup (int, int);
121 static void OP_LWPCB_E (int, int);
122 static void OP_LWP_E (int, int);
123 static void OP_Vex_2src_1 (int, int);
124 static void OP_Vex_2src_2 (int, int);
126 static void MOVBE_Fixup (int, int);
128 static void OP_Mask (int, int);
131 /* Points to first byte not fetched. */
132 bfd_byte *max_fetched;
133 bfd_byte the_buffer[MAX_MNEM_SIZE];
136 OPCODES_SIGJMP_BUF bailout;
146 enum address_mode address_mode;
148 /* Flags for the prefixes for the current instruction. See below. */
151 /* REX prefix the current instruction. See below. */
153 /* Bits of REX we've already used. */
155 /* REX bits in original REX prefix ignored. */
156 static int rex_ignored;
157 /* Mark parts used in the REX prefix. When we are testing for
158 empty prefix (for 8bit register REX extension), just mask it
159 out. Otherwise test for REX bit is excuse for existence of REX
160 only in case value is nonzero. */
161 #define USED_REX(value) \
166 rex_used |= (value) | REX_OPCODE; \
169 rex_used |= REX_OPCODE; \
172 /* Flags for prefixes which we somehow handled when printing the
173 current instruction. */
174 static int used_prefixes;
176 /* Flags stored in PREFIXES. */
177 #define PREFIX_REPZ 1
178 #define PREFIX_REPNZ 2
179 #define PREFIX_LOCK 4
181 #define PREFIX_SS 0x10
182 #define PREFIX_DS 0x20
183 #define PREFIX_ES 0x40
184 #define PREFIX_FS 0x80
185 #define PREFIX_GS 0x100
186 #define PREFIX_DATA 0x200
187 #define PREFIX_ADDR 0x400
188 #define PREFIX_FWAIT 0x800
190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
191 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
193 #define FETCH_DATA(info, addr) \
194 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
195 ? 1 : fetch_data ((info), (addr)))
198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
201 struct dis_private *priv = (struct dis_private *) info->private_data;
202 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
204 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
205 status = (*info->read_memory_func) (start,
207 addr - priv->max_fetched,
213 /* If we did manage to read at least one byte, then
214 print_insn_i386 will do something sensible. Otherwise, print
215 an error. We do that here because this is where we know
217 if (priv->max_fetched == priv->the_buffer)
218 (*info->memory_error_func) (status, start, info);
219 OPCODES_SIGLONGJMP (priv->bailout, 1);
222 priv->max_fetched = addr;
226 /* Possible values for prefix requirement. */
227 #define PREFIX_IGNORED_SHIFT 16
228 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
234 /* Opcode prefixes. */
235 #define PREFIX_OPCODE (PREFIX_REPZ \
239 /* Prefixes ignored. */
240 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
241 | PREFIX_IGNORED_REPNZ \
242 | PREFIX_IGNORED_DATA)
244 #define XX { NULL, 0 }
245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
247 #define Eb { OP_E, b_mode }
248 #define Ebnd { OP_E, bnd_mode }
249 #define EbS { OP_E, b_swap_mode }
250 #define EbndS { OP_E, bnd_swap_mode }
251 #define Ev { OP_E, v_mode }
252 #define Eva { OP_E, va_mode }
253 #define Ev_bnd { OP_E, v_bnd_mode }
254 #define EvS { OP_E, v_swap_mode }
255 #define Ed { OP_E, d_mode }
256 #define Edq { OP_E, dq_mode }
257 #define Edqw { OP_E, dqw_mode }
258 #define Edqb { OP_E, dqb_mode }
259 #define Edb { OP_E, db_mode }
260 #define Edw { OP_E, dw_mode }
261 #define Edqd { OP_E, dqd_mode }
262 #define Edqa { OP_E, dqa_mode }
263 #define Eq { OP_E, q_mode }
264 #define indirEv { OP_indirE, indir_v_mode }
265 #define indirEp { OP_indirE, f_mode }
266 #define stackEv { OP_E, stack_v_mode }
267 #define Em { OP_E, m_mode }
268 #define Ew { OP_E, w_mode }
269 #define M { OP_M, 0 } /* lea, lgdt, etc. */
270 #define Ma { OP_M, a_mode }
271 #define Mb { OP_M, b_mode }
272 #define Md { OP_M, d_mode }
273 #define Mo { OP_M, o_mode }
274 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
275 #define Mq { OP_M, q_mode }
276 #define Mv_bnd { OP_M, v_bndmk_mode }
277 #define Mx { OP_M, x_mode }
278 #define Mxmm { OP_M, xmm_mode }
279 #define Gb { OP_G, b_mode }
280 #define Gbnd { OP_G, bnd_mode }
281 #define Gv { OP_G, v_mode }
282 #define Gd { OP_G, d_mode }
283 #define Gdq { OP_G, dq_mode }
284 #define Gm { OP_G, m_mode }
285 #define Gva { OP_G, va_mode }
286 #define Gw { OP_G, w_mode }
287 #define Rd { OP_R, d_mode }
288 #define Rdq { OP_R, dq_mode }
289 #define Rm { OP_R, m_mode }
290 #define Ib { OP_I, b_mode }
291 #define sIb { OP_sI, b_mode } /* sign extened byte */
292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
293 #define Iv { OP_I, v_mode }
294 #define sIv { OP_sI, v_mode }
295 #define Iq { OP_I, q_mode }
296 #define Iv64 { OP_I64, v_mode }
297 #define Iw { OP_I, w_mode }
298 #define I1 { OP_I, const_1_mode }
299 #define Jb { OP_J, b_mode }
300 #define Jv { OP_J, v_mode }
301 #define Cm { OP_C, m_mode }
302 #define Dm { OP_D, m_mode }
303 #define Td { OP_T, d_mode }
304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
306 #define RMeAX { OP_REG, eAX_reg }
307 #define RMeBX { OP_REG, eBX_reg }
308 #define RMeCX { OP_REG, eCX_reg }
309 #define RMeDX { OP_REG, eDX_reg }
310 #define RMeSP { OP_REG, eSP_reg }
311 #define RMeBP { OP_REG, eBP_reg }
312 #define RMeSI { OP_REG, eSI_reg }
313 #define RMeDI { OP_REG, eDI_reg }
314 #define RMrAX { OP_REG, rAX_reg }
315 #define RMrBX { OP_REG, rBX_reg }
316 #define RMrCX { OP_REG, rCX_reg }
317 #define RMrDX { OP_REG, rDX_reg }
318 #define RMrSP { OP_REG, rSP_reg }
319 #define RMrBP { OP_REG, rBP_reg }
320 #define RMrSI { OP_REG, rSI_reg }
321 #define RMrDI { OP_REG, rDI_reg }
322 #define RMAL { OP_REG, al_reg }
323 #define RMCL { OP_REG, cl_reg }
324 #define RMDL { OP_REG, dl_reg }
325 #define RMBL { OP_REG, bl_reg }
326 #define RMAH { OP_REG, ah_reg }
327 #define RMCH { OP_REG, ch_reg }
328 #define RMDH { OP_REG, dh_reg }
329 #define RMBH { OP_REG, bh_reg }
330 #define RMAX { OP_REG, ax_reg }
331 #define RMDX { OP_REG, dx_reg }
333 #define eAX { OP_IMREG, eAX_reg }
334 #define eBX { OP_IMREG, eBX_reg }
335 #define eCX { OP_IMREG, eCX_reg }
336 #define eDX { OP_IMREG, eDX_reg }
337 #define eSP { OP_IMREG, eSP_reg }
338 #define eBP { OP_IMREG, eBP_reg }
339 #define eSI { OP_IMREG, eSI_reg }
340 #define eDI { OP_IMREG, eDI_reg }
341 #define AL { OP_IMREG, al_reg }
342 #define CL { OP_IMREG, cl_reg }
343 #define DL { OP_IMREG, dl_reg }
344 #define BL { OP_IMREG, bl_reg }
345 #define AH { OP_IMREG, ah_reg }
346 #define CH { OP_IMREG, ch_reg }
347 #define DH { OP_IMREG, dh_reg }
348 #define BH { OP_IMREG, bh_reg }
349 #define AX { OP_IMREG, ax_reg }
350 #define DX { OP_IMREG, dx_reg }
351 #define zAX { OP_IMREG, z_mode_ax_reg }
352 #define indirDX { OP_IMREG, indir_dx_reg }
354 #define Sw { OP_SEG, w_mode }
355 #define Sv { OP_SEG, v_mode }
356 #define Ap { OP_DIR, 0 }
357 #define Ob { OP_OFF64, b_mode }
358 #define Ov { OP_OFF64, v_mode }
359 #define Xb { OP_DSreg, eSI_reg }
360 #define Xv { OP_DSreg, eSI_reg }
361 #define Xz { OP_DSreg, eSI_reg }
362 #define Yb { OP_ESreg, eDI_reg }
363 #define Yv { OP_ESreg, eDI_reg }
364 #define DSBX { OP_DSreg, eBX_reg }
366 #define es { OP_REG, es_reg }
367 #define ss { OP_REG, ss_reg }
368 #define cs { OP_REG, cs_reg }
369 #define ds { OP_REG, ds_reg }
370 #define fs { OP_REG, fs_reg }
371 #define gs { OP_REG, gs_reg }
373 #define MX { OP_MMX, 0 }
374 #define XM { OP_XMM, 0 }
375 #define XMScalar { OP_XMM, scalar_mode }
376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
377 #define XMM { OP_XMM, xmm_mode }
378 #define XMxmmq { OP_XMM, xmmq_mode }
379 #define EM { OP_EM, v_mode }
380 #define EMS { OP_EM, v_swap_mode }
381 #define EMd { OP_EM, d_mode }
382 #define EMx { OP_EM, x_mode }
383 #define EXbScalar { OP_EX, b_scalar_mode }
384 #define EXw { OP_EX, w_mode }
385 #define EXwScalar { OP_EX, w_scalar_mode }
386 #define EXd { OP_EX, d_mode }
387 #define EXdScalar { OP_EX, d_scalar_mode }
388 #define EXdS { OP_EX, d_swap_mode }
389 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
390 #define EXq { OP_EX, q_mode }
391 #define EXqScalar { OP_EX, q_scalar_mode }
392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
393 #define EXqS { OP_EX, q_swap_mode }
394 #define EXx { OP_EX, x_mode }
395 #define EXxS { OP_EX, x_swap_mode }
396 #define EXxmm { OP_EX, xmm_mode }
397 #define EXymm { OP_EX, ymm_mode }
398 #define EXxmmq { OP_EX, xmmq_mode }
399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
402 #define EXxmm_md { OP_EX, xmm_md_mode }
403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
404 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
405 #define EXxmmdw { OP_EX, xmmdw_mode }
406 #define EXxmmqd { OP_EX, xmmqd_mode }
407 #define EXymmq { OP_EX, ymmq_mode }
408 #define EXVexWdq { OP_EX, vex_w_dq_mode }
409 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
410 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
411 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
412 #define MS { OP_MS, v_mode }
413 #define XS { OP_XS, v_mode }
414 #define EMCq { OP_EMC, q_mode }
415 #define MXC { OP_MXC, 0 }
416 #define OPSUF { OP_3DNowSuffix, 0 }
417 #define CMP { CMP_Fixup, 0 }
418 #define XMM0 { XMM_Fixup, 0 }
419 #define FXSAVE { FXSAVE_Fixup, 0 }
420 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
421 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
423 #define Vex { OP_VEX, vex_mode }
424 #define VexScalar { OP_VEX, vex_scalar_mode }
425 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
426 #define Vex128 { OP_VEX, vex128_mode }
427 #define Vex256 { OP_VEX, vex256_mode }
428 #define VexGdq { OP_VEX, dq_mode }
429 #define EXdVex { OP_EX_Vex, d_mode }
430 #define EXdVexS { OP_EX_Vex, d_swap_mode }
431 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
432 #define EXqVex { OP_EX_Vex, q_mode }
433 #define EXqVexS { OP_EX_Vex, q_swap_mode }
434 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
435 #define EXVexW { OP_EX_VexW, x_mode }
436 #define EXdVexW { OP_EX_VexW, d_mode }
437 #define EXqVexW { OP_EX_VexW, q_mode }
438 #define EXVexImmW { OP_EX_VexImmW, x_mode }
439 #define XMVex { OP_XMM_Vex, 0 }
440 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
441 #define XMVexW { OP_XMM_VexW, 0 }
442 #define XMVexI4 { OP_REG_VexI4, x_mode }
443 #define PCLMUL { PCLMUL_Fixup, 0 }
444 #define VCMP { VCMP_Fixup, 0 }
445 #define VPCMP { VPCMP_Fixup, 0 }
446 #define VPCOM { VPCOM_Fixup, 0 }
448 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
449 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
450 #define EXxEVexS { OP_Rounding, evex_sae_mode }
452 #define XMask { OP_Mask, mask_mode }
453 #define MaskG { OP_G, mask_mode }
454 #define MaskE { OP_E, mask_mode }
455 #define MaskBDE { OP_E, mask_bd_mode }
456 #define MaskR { OP_R, mask_mode }
457 #define MaskVex { OP_VEX, mask_mode }
459 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
460 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
461 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
462 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
464 /* Used handle "rep" prefix for string instructions. */
465 #define Xbr { REP_Fixup, eSI_reg }
466 #define Xvr { REP_Fixup, eSI_reg }
467 #define Ybr { REP_Fixup, eDI_reg }
468 #define Yvr { REP_Fixup, eDI_reg }
469 #define Yzr { REP_Fixup, eDI_reg }
470 #define indirDXr { REP_Fixup, indir_dx_reg }
471 #define ALr { REP_Fixup, al_reg }
472 #define eAXr { REP_Fixup, eAX_reg }
474 /* Used handle HLE prefix for lockable instructions. */
475 #define Ebh1 { HLE_Fixup1, b_mode }
476 #define Evh1 { HLE_Fixup1, v_mode }
477 #define Ebh2 { HLE_Fixup2, b_mode }
478 #define Evh2 { HLE_Fixup2, v_mode }
479 #define Ebh3 { HLE_Fixup3, b_mode }
480 #define Evh3 { HLE_Fixup3, v_mode }
482 #define BND { BND_Fixup, 0 }
483 #define NOTRACK { NOTRACK_Fixup, 0 }
485 #define cond_jump_flag { NULL, cond_jump_mode }
486 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
488 /* bits in sizeflag */
489 #define SUFFIX_ALWAYS 4
497 /* byte operand with operand swapped */
499 /* byte operand, sign extend like 'T' suffix */
501 /* operand size depends on prefixes */
503 /* operand size depends on prefixes with operand swapped */
505 /* operand size depends on address prefix */
509 /* double word operand */
511 /* double word operand with operand swapped */
513 /* quad word operand */
515 /* quad word operand with operand swapped */
517 /* ten-byte operand */
519 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
520 broadcast enabled. */
522 /* Similar to x_mode, but with different EVEX mem shifts. */
524 /* Similar to x_mode, but with disabled broadcast. */
526 /* Similar to x_mode, but with operands swapped and disabled broadcast
529 /* 16-byte XMM operand */
531 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
532 memory operand (depending on vector length). Broadcast isn't
535 /* Same as xmmq_mode, but broadcast is allowed. */
536 evex_half_bcst_xmmq_mode,
537 /* XMM register or byte memory operand */
539 /* XMM register or word memory operand */
541 /* XMM register or double word memory operand */
543 /* XMM register or quad word memory operand */
545 /* XMM register or double/quad word memory operand, depending on
548 /* 16-byte XMM, word, double word or quad word operand. */
550 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
552 /* 32-byte YMM operand */
554 /* quad word, ymmword or zmmword memory operand. */
556 /* 32-byte YMM or 16-byte word operand */
558 /* d_mode in 32bit, q_mode in 64bit mode. */
560 /* pair of v_mode operands */
565 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
567 /* operand size depends on REX prefixes. */
569 /* registers like dq_mode, memory like w_mode. */
573 /* bounds operand with operand swapped */
575 /* 4- or 6-byte pointer operand */
578 /* v_mode for indirect branch opcodes. */
580 /* v_mode for stack-related opcodes. */
582 /* non-quad operand size depends on prefixes */
584 /* 16-byte operand */
586 /* registers like dq_mode, memory like b_mode. */
588 /* registers like d_mode, memory like b_mode. */
590 /* registers like d_mode, memory like w_mode. */
592 /* registers like dq_mode, memory like d_mode. */
594 /* operand size depends on the W bit as well as address mode. */
596 /* normal vex mode */
598 /* 128bit vex mode */
600 /* 256bit vex mode */
602 /* operand size depends on the VEX.W bit. */
605 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
606 vex_vsib_d_w_dq_mode,
607 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
609 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
610 vex_vsib_q_w_dq_mode,
611 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
614 /* scalar, ignore vector length. */
616 /* like b_mode, ignore vector length. */
618 /* like w_mode, ignore vector length. */
620 /* like d_mode, ignore vector length. */
622 /* like d_swap_mode, ignore vector length. */
624 /* like q_mode, ignore vector length. */
626 /* like q_swap_mode, ignore vector length. */
628 /* like vex_mode, ignore vector length. */
630 /* like vex_w_dq_mode, ignore vector length. */
631 vex_scalar_w_dq_mode,
633 /* Static rounding. */
635 /* Static rounding, 64-bit mode only. */
636 evex_rounding_64_mode,
637 /* Supress all exceptions. */
640 /* Mask register operand. */
642 /* Mask register operand. */
710 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
712 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
713 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
714 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
715 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
716 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
717 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
718 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
719 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
720 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
721 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
722 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
723 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
724 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
725 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
726 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
727 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
855 MOD_VEX_0F12_PREFIX_0,
857 MOD_VEX_0F16_PREFIX_0,
860 MOD_VEX_W_0_0F41_P_0_LEN_1,
861 MOD_VEX_W_1_0F41_P_0_LEN_1,
862 MOD_VEX_W_0_0F41_P_2_LEN_1,
863 MOD_VEX_W_1_0F41_P_2_LEN_1,
864 MOD_VEX_W_0_0F42_P_0_LEN_1,
865 MOD_VEX_W_1_0F42_P_0_LEN_1,
866 MOD_VEX_W_0_0F42_P_2_LEN_1,
867 MOD_VEX_W_1_0F42_P_2_LEN_1,
868 MOD_VEX_W_0_0F44_P_0_LEN_1,
869 MOD_VEX_W_1_0F44_P_0_LEN_1,
870 MOD_VEX_W_0_0F44_P_2_LEN_1,
871 MOD_VEX_W_1_0F44_P_2_LEN_1,
872 MOD_VEX_W_0_0F45_P_0_LEN_1,
873 MOD_VEX_W_1_0F45_P_0_LEN_1,
874 MOD_VEX_W_0_0F45_P_2_LEN_1,
875 MOD_VEX_W_1_0F45_P_2_LEN_1,
876 MOD_VEX_W_0_0F46_P_0_LEN_1,
877 MOD_VEX_W_1_0F46_P_0_LEN_1,
878 MOD_VEX_W_0_0F46_P_2_LEN_1,
879 MOD_VEX_W_1_0F46_P_2_LEN_1,
880 MOD_VEX_W_0_0F47_P_0_LEN_1,
881 MOD_VEX_W_1_0F47_P_0_LEN_1,
882 MOD_VEX_W_0_0F47_P_2_LEN_1,
883 MOD_VEX_W_1_0F47_P_2_LEN_1,
884 MOD_VEX_W_0_0F4A_P_0_LEN_1,
885 MOD_VEX_W_1_0F4A_P_0_LEN_1,
886 MOD_VEX_W_0_0F4A_P_2_LEN_1,
887 MOD_VEX_W_1_0F4A_P_2_LEN_1,
888 MOD_VEX_W_0_0F4B_P_0_LEN_1,
889 MOD_VEX_W_1_0F4B_P_0_LEN_1,
890 MOD_VEX_W_0_0F4B_P_2_LEN_1,
902 MOD_VEX_W_0_0F91_P_0_LEN_0,
903 MOD_VEX_W_1_0F91_P_0_LEN_0,
904 MOD_VEX_W_0_0F91_P_2_LEN_0,
905 MOD_VEX_W_1_0F91_P_2_LEN_0,
906 MOD_VEX_W_0_0F92_P_0_LEN_0,
907 MOD_VEX_W_0_0F92_P_2_LEN_0,
908 MOD_VEX_0F92_P_3_LEN_0,
909 MOD_VEX_W_0_0F93_P_0_LEN_0,
910 MOD_VEX_W_0_0F93_P_2_LEN_0,
911 MOD_VEX_0F93_P_3_LEN_0,
912 MOD_VEX_W_0_0F98_P_0_LEN_0,
913 MOD_VEX_W_1_0F98_P_0_LEN_0,
914 MOD_VEX_W_0_0F98_P_2_LEN_0,
915 MOD_VEX_W_1_0F98_P_2_LEN_0,
916 MOD_VEX_W_0_0F99_P_0_LEN_0,
917 MOD_VEX_W_1_0F99_P_0_LEN_0,
918 MOD_VEX_W_0_0F99_P_2_LEN_0,
919 MOD_VEX_W_1_0F99_P_2_LEN_0,
922 MOD_VEX_0FD7_PREFIX_2,
923 MOD_VEX_0FE7_PREFIX_2,
924 MOD_VEX_0FF0_PREFIX_3,
925 MOD_VEX_0F381A_PREFIX_2,
926 MOD_VEX_0F382A_PREFIX_2,
927 MOD_VEX_0F382C_PREFIX_2,
928 MOD_VEX_0F382D_PREFIX_2,
929 MOD_VEX_0F382E_PREFIX_2,
930 MOD_VEX_0F382F_PREFIX_2,
931 MOD_VEX_0F385A_PREFIX_2,
932 MOD_VEX_0F388C_PREFIX_2,
933 MOD_VEX_0F388E_PREFIX_2,
934 MOD_VEX_W_0_0F3A30_P_2_LEN_0,
935 MOD_VEX_W_1_0F3A30_P_2_LEN_0,
936 MOD_VEX_W_0_0F3A31_P_2_LEN_0,
937 MOD_VEX_W_1_0F3A31_P_2_LEN_0,
938 MOD_VEX_W_0_0F3A32_P_2_LEN_0,
939 MOD_VEX_W_1_0F3A32_P_2_LEN_0,
940 MOD_VEX_W_0_0F3A33_P_2_LEN_0,
941 MOD_VEX_W_1_0F3A33_P_2_LEN_0,
943 MOD_EVEX_0F10_PREFIX_1,
944 MOD_EVEX_0F10_PREFIX_3,
945 MOD_EVEX_0F11_PREFIX_1,
946 MOD_EVEX_0F11_PREFIX_3,
947 MOD_EVEX_0F12_PREFIX_0,
948 MOD_EVEX_0F16_PREFIX_0,
949 MOD_EVEX_0F38C6_REG_1,
950 MOD_EVEX_0F38C6_REG_2,
951 MOD_EVEX_0F38C6_REG_5,
952 MOD_EVEX_0F38C6_REG_6,
953 MOD_EVEX_0F38C7_REG_1,
954 MOD_EVEX_0F38C7_REG_2,
955 MOD_EVEX_0F38C7_REG_5,
956 MOD_EVEX_0F38C7_REG_6
977 PREFIX_MOD_0_0F01_REG_5,
978 PREFIX_MOD_3_0F01_REG_5_RM_0,
979 PREFIX_MOD_3_0F01_REG_5_RM_2,
1025 PREFIX_MOD_0_0FAE_REG_4,
1026 PREFIX_MOD_3_0FAE_REG_4,
1027 PREFIX_MOD_0_0FAE_REG_5,
1028 PREFIX_MOD_3_0FAE_REG_5,
1029 PREFIX_MOD_0_0FAE_REG_6,
1030 PREFIX_MOD_1_0FAE_REG_6,
1037 PREFIX_MOD_0_0FC7_REG_6,
1038 PREFIX_MOD_3_0FC7_REG_6,
1039 PREFIX_MOD_3_0FC7_REG_7,
1169 PREFIX_VEX_0F71_REG_2,
1170 PREFIX_VEX_0F71_REG_4,
1171 PREFIX_VEX_0F71_REG_6,
1172 PREFIX_VEX_0F72_REG_2,
1173 PREFIX_VEX_0F72_REG_4,
1174 PREFIX_VEX_0F72_REG_6,
1175 PREFIX_VEX_0F73_REG_2,
1176 PREFIX_VEX_0F73_REG_3,
1177 PREFIX_VEX_0F73_REG_6,
1178 PREFIX_VEX_0F73_REG_7,
1351 PREFIX_VEX_0F38F3_REG_1,
1352 PREFIX_VEX_0F38F3_REG_2,
1353 PREFIX_VEX_0F38F3_REG_3,
1472 PREFIX_EVEX_0F71_REG_2,
1473 PREFIX_EVEX_0F71_REG_4,
1474 PREFIX_EVEX_0F71_REG_6,
1475 PREFIX_EVEX_0F72_REG_0,
1476 PREFIX_EVEX_0F72_REG_1,
1477 PREFIX_EVEX_0F72_REG_2,
1478 PREFIX_EVEX_0F72_REG_4,
1479 PREFIX_EVEX_0F72_REG_6,
1480 PREFIX_EVEX_0F73_REG_2,
1481 PREFIX_EVEX_0F73_REG_3,
1482 PREFIX_EVEX_0F73_REG_6,
1483 PREFIX_EVEX_0F73_REG_7,
1680 PREFIX_EVEX_0F38C6_REG_1,
1681 PREFIX_EVEX_0F38C6_REG_2,
1682 PREFIX_EVEX_0F38C6_REG_5,
1683 PREFIX_EVEX_0F38C6_REG_6,
1684 PREFIX_EVEX_0F38C7_REG_1,
1685 PREFIX_EVEX_0F38C7_REG_2,
1686 PREFIX_EVEX_0F38C7_REG_5,
1687 PREFIX_EVEX_0F38C7_REG_6,
1789 THREE_BYTE_0F38 = 0,
1816 VEX_LEN_0F12_P_0_M_0 = 0,
1817 VEX_LEN_0F12_P_0_M_1,
1820 VEX_LEN_0F16_P_0_M_0,
1821 VEX_LEN_0F16_P_0_M_1,
1864 VEX_LEN_0FAE_R_2_M_0,
1865 VEX_LEN_0FAE_R_3_M_0,
1872 VEX_LEN_0F381A_P_2_M_0,
1875 VEX_LEN_0F385A_P_2_M_0,
1878 VEX_LEN_0F38F3_R_1_P_0,
1879 VEX_LEN_0F38F3_R_2_P_0,
1880 VEX_LEN_0F38F3_R_3_P_0,
1923 VEX_LEN_0FXOP_08_CC,
1924 VEX_LEN_0FXOP_08_CD,
1925 VEX_LEN_0FXOP_08_CE,
1926 VEX_LEN_0FXOP_08_CF,
1927 VEX_LEN_0FXOP_08_EC,
1928 VEX_LEN_0FXOP_08_ED,
1929 VEX_LEN_0FXOP_08_EE,
1930 VEX_LEN_0FXOP_08_EF,
1931 VEX_LEN_0FXOP_09_80,
1937 EVEX_LEN_0F6E_P_2 = 0,
1941 EVEX_LEN_0F3819_P_2_W_0,
1942 EVEX_LEN_0F3819_P_2_W_1,
1943 EVEX_LEN_0F381A_P_2_W_0,
1944 EVEX_LEN_0F381A_P_2_W_1,
1945 EVEX_LEN_0F381B_P_2_W_0,
1946 EVEX_LEN_0F381B_P_2_W_1,
1947 EVEX_LEN_0F385A_P_2_W_0,
1948 EVEX_LEN_0F385A_P_2_W_1,
1949 EVEX_LEN_0F385B_P_2_W_0,
1950 EVEX_LEN_0F385B_P_2_W_1,
1951 EVEX_LEN_0F3A18_P_2_W_0,
1952 EVEX_LEN_0F3A18_P_2_W_1,
1953 EVEX_LEN_0F3A19_P_2_W_0,
1954 EVEX_LEN_0F3A19_P_2_W_1,
1955 EVEX_LEN_0F3A1A_P_2_W_0,
1956 EVEX_LEN_0F3A1A_P_2_W_1,
1957 EVEX_LEN_0F3A1B_P_2_W_0,
1958 EVEX_LEN_0F3A1B_P_2_W_1,
1959 EVEX_LEN_0F3A23_P_2_W_0,
1960 EVEX_LEN_0F3A23_P_2_W_1,
1961 EVEX_LEN_0F3A38_P_2_W_0,
1962 EVEX_LEN_0F3A38_P_2_W_1,
1963 EVEX_LEN_0F3A39_P_2_W_0,
1964 EVEX_LEN_0F3A39_P_2_W_1,
1965 EVEX_LEN_0F3A3A_P_2_W_0,
1966 EVEX_LEN_0F3A3A_P_2_W_1,
1967 EVEX_LEN_0F3A3B_P_2_W_0,
1968 EVEX_LEN_0F3A3B_P_2_W_1,
1969 EVEX_LEN_0F3A43_P_2_W_0,
1970 EVEX_LEN_0F3A43_P_2_W_1
1975 VEX_W_0F41_P_0_LEN_1 = 0,
1976 VEX_W_0F41_P_2_LEN_1,
1977 VEX_W_0F42_P_0_LEN_1,
1978 VEX_W_0F42_P_2_LEN_1,
1979 VEX_W_0F44_P_0_LEN_0,
1980 VEX_W_0F44_P_2_LEN_0,
1981 VEX_W_0F45_P_0_LEN_1,
1982 VEX_W_0F45_P_2_LEN_1,
1983 VEX_W_0F46_P_0_LEN_1,
1984 VEX_W_0F46_P_2_LEN_1,
1985 VEX_W_0F47_P_0_LEN_1,
1986 VEX_W_0F47_P_2_LEN_1,
1987 VEX_W_0F4A_P_0_LEN_1,
1988 VEX_W_0F4A_P_2_LEN_1,
1989 VEX_W_0F4B_P_0_LEN_1,
1990 VEX_W_0F4B_P_2_LEN_1,
1991 VEX_W_0F90_P_0_LEN_0,
1992 VEX_W_0F90_P_2_LEN_0,
1993 VEX_W_0F91_P_0_LEN_0,
1994 VEX_W_0F91_P_2_LEN_0,
1995 VEX_W_0F92_P_0_LEN_0,
1996 VEX_W_0F92_P_2_LEN_0,
1997 VEX_W_0F93_P_0_LEN_0,
1998 VEX_W_0F93_P_2_LEN_0,
1999 VEX_W_0F98_P_0_LEN_0,
2000 VEX_W_0F98_P_2_LEN_0,
2001 VEX_W_0F99_P_0_LEN_0,
2002 VEX_W_0F99_P_2_LEN_0,
2010 VEX_W_0F381A_P_2_M_0,
2011 VEX_W_0F382C_P_2_M_0,
2012 VEX_W_0F382D_P_2_M_0,
2013 VEX_W_0F382E_P_2_M_0,
2014 VEX_W_0F382F_P_2_M_0,
2019 VEX_W_0F385A_P_2_M_0,
2031 VEX_W_0F3A30_P_2_LEN_0,
2032 VEX_W_0F3A31_P_2_LEN_0,
2033 VEX_W_0F3A32_P_2_LEN_0,
2034 VEX_W_0F3A33_P_2_LEN_0,
2047 EVEX_W_0F10_P_1_M_0,
2048 EVEX_W_0F10_P_1_M_1,
2050 EVEX_W_0F10_P_3_M_0,
2051 EVEX_W_0F10_P_3_M_1,
2053 EVEX_W_0F11_P_1_M_0,
2054 EVEX_W_0F11_P_1_M_1,
2056 EVEX_W_0F11_P_3_M_0,
2057 EVEX_W_0F11_P_3_M_1,
2058 EVEX_W_0F12_P_0_M_0,
2059 EVEX_W_0F12_P_0_M_1,
2069 EVEX_W_0F16_P_0_M_0,
2070 EVEX_W_0F16_P_0_M_1,
2140 EVEX_W_0F72_R_2_P_2,
2141 EVEX_W_0F72_R_6_P_2,
2142 EVEX_W_0F73_R_2_P_2,
2143 EVEX_W_0F73_R_6_P_2,
2254 EVEX_W_0F38C7_R_1_P_2,
2255 EVEX_W_0F38C7_R_2_P_2,
2256 EVEX_W_0F38C7_R_5_P_2,
2257 EVEX_W_0F38C7_R_6_P_2,
2296 typedef void (*op_rtn) (int bytemode, int sizeflag);
2305 unsigned int prefix_requirement;
2308 /* Upper case letters in the instruction names here are macros.
2309 'A' => print 'b' if no register operands or suffix_always is true
2310 'B' => print 'b' if suffix_always is true
2311 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2313 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2314 suffix_always is true
2315 'E' => print 'e' if 32-bit form of jcxz
2316 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2317 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2318 'H' => print ",pt" or ",pn" branch hint
2319 'I' => honor following macro letter even in Intel mode (implemented only
2320 for some of the macro letters)
2322 'K' => print 'd' or 'q' if rex prefix is present.
2323 'L' => print 'l' if suffix_always is true
2324 'M' => print 'r' if intel_mnemonic is false.
2325 'N' => print 'n' if instruction has no wait "prefix"
2326 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2327 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2328 or suffix_always is true. print 'q' if rex prefix is present.
2329 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2331 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2332 'S' => print 'w', 'l' or 'q' if suffix_always is true
2333 'T' => print 'q' in 64bit mode if instruction has no operand size
2334 prefix and behave as 'P' otherwise
2335 'U' => print 'q' in 64bit mode if instruction has no operand size
2336 prefix and behave as 'Q' otherwise
2337 'V' => print 'q' in 64bit mode if instruction has no operand size
2338 prefix and behave as 'S' otherwise
2339 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2340 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2342 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2343 '!' => change condition from true to false or from false to true.
2344 '%' => add 1 upper case letter to the macro.
2345 '^' => print 'w' or 'l' depending on operand size prefix or
2346 suffix_always is true (lcall/ljmp).
2347 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2348 on operand size prefix.
2349 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2350 has no operand size prefix for AMD64 ISA, behave as 'P'
2353 2 upper case letter macros:
2354 "XY" => print 'x' or 'y' if suffix_always is true or no register
2355 operands and no broadcast.
2356 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2357 register operands and no broadcast.
2358 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2359 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2360 or suffix_always is true
2361 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2362 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2363 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2364 "LW" => print 'd', 'q' depending on the VEX.W bit
2365 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2366 an operand size prefix, or suffix_always is true. print
2367 'q' if rex prefix is present.
2369 Many of the above letters print nothing in Intel mode. See "putop"
2372 Braces '{' and '}', and vertical bars '|', indicate alternative
2373 mnemonic strings for AT&T and Intel. */
2375 static const struct dis386 dis386[] = {
2377 { "addB", { Ebh1, Gb }, 0 },
2378 { "addS", { Evh1, Gv }, 0 },
2379 { "addB", { Gb, EbS }, 0 },
2380 { "addS", { Gv, EvS }, 0 },
2381 { "addB", { AL, Ib }, 0 },
2382 { "addS", { eAX, Iv }, 0 },
2383 { X86_64_TABLE (X86_64_06) },
2384 { X86_64_TABLE (X86_64_07) },
2386 { "orB", { Ebh1, Gb }, 0 },
2387 { "orS", { Evh1, Gv }, 0 },
2388 { "orB", { Gb, EbS }, 0 },
2389 { "orS", { Gv, EvS }, 0 },
2390 { "orB", { AL, Ib }, 0 },
2391 { "orS", { eAX, Iv }, 0 },
2392 { X86_64_TABLE (X86_64_0D) },
2393 { Bad_Opcode }, /* 0x0f extended opcode escape */
2395 { "adcB", { Ebh1, Gb }, 0 },
2396 { "adcS", { Evh1, Gv }, 0 },
2397 { "adcB", { Gb, EbS }, 0 },
2398 { "adcS", { Gv, EvS }, 0 },
2399 { "adcB", { AL, Ib }, 0 },
2400 { "adcS", { eAX, Iv }, 0 },
2401 { X86_64_TABLE (X86_64_16) },
2402 { X86_64_TABLE (X86_64_17) },
2404 { "sbbB", { Ebh1, Gb }, 0 },
2405 { "sbbS", { Evh1, Gv }, 0 },
2406 { "sbbB", { Gb, EbS }, 0 },
2407 { "sbbS", { Gv, EvS }, 0 },
2408 { "sbbB", { AL, Ib }, 0 },
2409 { "sbbS", { eAX, Iv }, 0 },
2410 { X86_64_TABLE (X86_64_1E) },
2411 { X86_64_TABLE (X86_64_1F) },
2413 { "andB", { Ebh1, Gb }, 0 },
2414 { "andS", { Evh1, Gv }, 0 },
2415 { "andB", { Gb, EbS }, 0 },
2416 { "andS", { Gv, EvS }, 0 },
2417 { "andB", { AL, Ib }, 0 },
2418 { "andS", { eAX, Iv }, 0 },
2419 { Bad_Opcode }, /* SEG ES prefix */
2420 { X86_64_TABLE (X86_64_27) },
2422 { "subB", { Ebh1, Gb }, 0 },
2423 { "subS", { Evh1, Gv }, 0 },
2424 { "subB", { Gb, EbS }, 0 },
2425 { "subS", { Gv, EvS }, 0 },
2426 { "subB", { AL, Ib }, 0 },
2427 { "subS", { eAX, Iv }, 0 },
2428 { Bad_Opcode }, /* SEG CS prefix */
2429 { X86_64_TABLE (X86_64_2F) },
2431 { "xorB", { Ebh1, Gb }, 0 },
2432 { "xorS", { Evh1, Gv }, 0 },
2433 { "xorB", { Gb, EbS }, 0 },
2434 { "xorS", { Gv, EvS }, 0 },
2435 { "xorB", { AL, Ib }, 0 },
2436 { "xorS", { eAX, Iv }, 0 },
2437 { Bad_Opcode }, /* SEG SS prefix */
2438 { X86_64_TABLE (X86_64_37) },
2440 { "cmpB", { Eb, Gb }, 0 },
2441 { "cmpS", { Ev, Gv }, 0 },
2442 { "cmpB", { Gb, EbS }, 0 },
2443 { "cmpS", { Gv, EvS }, 0 },
2444 { "cmpB", { AL, Ib }, 0 },
2445 { "cmpS", { eAX, Iv }, 0 },
2446 { Bad_Opcode }, /* SEG DS prefix */
2447 { X86_64_TABLE (X86_64_3F) },
2449 { "inc{S|}", { RMeAX }, 0 },
2450 { "inc{S|}", { RMeCX }, 0 },
2451 { "inc{S|}", { RMeDX }, 0 },
2452 { "inc{S|}", { RMeBX }, 0 },
2453 { "inc{S|}", { RMeSP }, 0 },
2454 { "inc{S|}", { RMeBP }, 0 },
2455 { "inc{S|}", { RMeSI }, 0 },
2456 { "inc{S|}", { RMeDI }, 0 },
2458 { "dec{S|}", { RMeAX }, 0 },
2459 { "dec{S|}", { RMeCX }, 0 },
2460 { "dec{S|}", { RMeDX }, 0 },
2461 { "dec{S|}", { RMeBX }, 0 },
2462 { "dec{S|}", { RMeSP }, 0 },
2463 { "dec{S|}", { RMeBP }, 0 },
2464 { "dec{S|}", { RMeSI }, 0 },
2465 { "dec{S|}", { RMeDI }, 0 },
2467 { "pushV", { RMrAX }, 0 },
2468 { "pushV", { RMrCX }, 0 },
2469 { "pushV", { RMrDX }, 0 },
2470 { "pushV", { RMrBX }, 0 },
2471 { "pushV", { RMrSP }, 0 },
2472 { "pushV", { RMrBP }, 0 },
2473 { "pushV", { RMrSI }, 0 },
2474 { "pushV", { RMrDI }, 0 },
2476 { "popV", { RMrAX }, 0 },
2477 { "popV", { RMrCX }, 0 },
2478 { "popV", { RMrDX }, 0 },
2479 { "popV", { RMrBX }, 0 },
2480 { "popV", { RMrSP }, 0 },
2481 { "popV", { RMrBP }, 0 },
2482 { "popV", { RMrSI }, 0 },
2483 { "popV", { RMrDI }, 0 },
2485 { X86_64_TABLE (X86_64_60) },
2486 { X86_64_TABLE (X86_64_61) },
2487 { X86_64_TABLE (X86_64_62) },
2488 { X86_64_TABLE (X86_64_63) },
2489 { Bad_Opcode }, /* seg fs */
2490 { Bad_Opcode }, /* seg gs */
2491 { Bad_Opcode }, /* op size prefix */
2492 { Bad_Opcode }, /* adr size prefix */
2494 { "pushT", { sIv }, 0 },
2495 { "imulS", { Gv, Ev, Iv }, 0 },
2496 { "pushT", { sIbT }, 0 },
2497 { "imulS", { Gv, Ev, sIb }, 0 },
2498 { "ins{b|}", { Ybr, indirDX }, 0 },
2499 { X86_64_TABLE (X86_64_6D) },
2500 { "outs{b|}", { indirDXr, Xb }, 0 },
2501 { X86_64_TABLE (X86_64_6F) },
2503 { "joH", { Jb, BND, cond_jump_flag }, 0 },
2504 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
2505 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
2506 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
2507 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
2508 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
2509 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
2510 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
2512 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
2513 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
2514 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
2515 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
2516 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
2517 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
2518 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
2519 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
2521 { REG_TABLE (REG_80) },
2522 { REG_TABLE (REG_81) },
2523 { X86_64_TABLE (X86_64_82) },
2524 { REG_TABLE (REG_83) },
2525 { "testB", { Eb, Gb }, 0 },
2526 { "testS", { Ev, Gv }, 0 },
2527 { "xchgB", { Ebh2, Gb }, 0 },
2528 { "xchgS", { Evh2, Gv }, 0 },
2530 { "movB", { Ebh3, Gb }, 0 },
2531 { "movS", { Evh3, Gv }, 0 },
2532 { "movB", { Gb, EbS }, 0 },
2533 { "movS", { Gv, EvS }, 0 },
2534 { "movD", { Sv, Sw }, 0 },
2535 { MOD_TABLE (MOD_8D) },
2536 { "movD", { Sw, Sv }, 0 },
2537 { REG_TABLE (REG_8F) },
2539 { PREFIX_TABLE (PREFIX_90) },
2540 { "xchgS", { RMeCX, eAX }, 0 },
2541 { "xchgS", { RMeDX, eAX }, 0 },
2542 { "xchgS", { RMeBX, eAX }, 0 },
2543 { "xchgS", { RMeSP, eAX }, 0 },
2544 { "xchgS", { RMeBP, eAX }, 0 },
2545 { "xchgS", { RMeSI, eAX }, 0 },
2546 { "xchgS", { RMeDI, eAX }, 0 },
2548 { "cW{t|}R", { XX }, 0 },
2549 { "cR{t|}O", { XX }, 0 },
2550 { X86_64_TABLE (X86_64_9A) },
2551 { Bad_Opcode }, /* fwait */
2552 { "pushfT", { XX }, 0 },
2553 { "popfT", { XX }, 0 },
2554 { "sahf", { XX }, 0 },
2555 { "lahf", { XX }, 0 },
2557 { "mov%LB", { AL, Ob }, 0 },
2558 { "mov%LS", { eAX, Ov }, 0 },
2559 { "mov%LB", { Ob, AL }, 0 },
2560 { "mov%LS", { Ov, eAX }, 0 },
2561 { "movs{b|}", { Ybr, Xb }, 0 },
2562 { "movs{R|}", { Yvr, Xv }, 0 },
2563 { "cmps{b|}", { Xb, Yb }, 0 },
2564 { "cmps{R|}", { Xv, Yv }, 0 },
2566 { "testB", { AL, Ib }, 0 },
2567 { "testS", { eAX, Iv }, 0 },
2568 { "stosB", { Ybr, AL }, 0 },
2569 { "stosS", { Yvr, eAX }, 0 },
2570 { "lodsB", { ALr, Xb }, 0 },
2571 { "lodsS", { eAXr, Xv }, 0 },
2572 { "scasB", { AL, Yb }, 0 },
2573 { "scasS", { eAX, Yv }, 0 },
2575 { "movB", { RMAL, Ib }, 0 },
2576 { "movB", { RMCL, Ib }, 0 },
2577 { "movB", { RMDL, Ib }, 0 },
2578 { "movB", { RMBL, Ib }, 0 },
2579 { "movB", { RMAH, Ib }, 0 },
2580 { "movB", { RMCH, Ib }, 0 },
2581 { "movB", { RMDH, Ib }, 0 },
2582 { "movB", { RMBH, Ib }, 0 },
2584 { "mov%LV", { RMeAX, Iv64 }, 0 },
2585 { "mov%LV", { RMeCX, Iv64 }, 0 },
2586 { "mov%LV", { RMeDX, Iv64 }, 0 },
2587 { "mov%LV", { RMeBX, Iv64 }, 0 },
2588 { "mov%LV", { RMeSP, Iv64 }, 0 },
2589 { "mov%LV", { RMeBP, Iv64 }, 0 },
2590 { "mov%LV", { RMeSI, Iv64 }, 0 },
2591 { "mov%LV", { RMeDI, Iv64 }, 0 },
2593 { REG_TABLE (REG_C0) },
2594 { REG_TABLE (REG_C1) },
2595 { "retT", { Iw, BND }, 0 },
2596 { "retT", { BND }, 0 },
2597 { X86_64_TABLE (X86_64_C4) },
2598 { X86_64_TABLE (X86_64_C5) },
2599 { REG_TABLE (REG_C6) },
2600 { REG_TABLE (REG_C7) },
2602 { "enterT", { Iw, Ib }, 0 },
2603 { "leaveT", { XX }, 0 },
2604 { "Jret{|f}P", { Iw }, 0 },
2605 { "Jret{|f}P", { XX }, 0 },
2606 { "int3", { XX }, 0 },
2607 { "int", { Ib }, 0 },
2608 { X86_64_TABLE (X86_64_CE) },
2609 { "iret%LP", { XX }, 0 },
2611 { REG_TABLE (REG_D0) },
2612 { REG_TABLE (REG_D1) },
2613 { REG_TABLE (REG_D2) },
2614 { REG_TABLE (REG_D3) },
2615 { X86_64_TABLE (X86_64_D4) },
2616 { X86_64_TABLE (X86_64_D5) },
2618 { "xlat", { DSBX }, 0 },
2629 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2630 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2631 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2632 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2633 { "inB", { AL, Ib }, 0 },
2634 { "inG", { zAX, Ib }, 0 },
2635 { "outB", { Ib, AL }, 0 },
2636 { "outG", { Ib, zAX }, 0 },
2638 { X86_64_TABLE (X86_64_E8) },
2639 { X86_64_TABLE (X86_64_E9) },
2640 { X86_64_TABLE (X86_64_EA) },
2641 { "jmp", { Jb, BND }, 0 },
2642 { "inB", { AL, indirDX }, 0 },
2643 { "inG", { zAX, indirDX }, 0 },
2644 { "outB", { indirDX, AL }, 0 },
2645 { "outG", { indirDX, zAX }, 0 },
2647 { Bad_Opcode }, /* lock prefix */
2648 { "icebp", { XX }, 0 },
2649 { Bad_Opcode }, /* repne */
2650 { Bad_Opcode }, /* repz */
2651 { "hlt", { XX }, 0 },
2652 { "cmc", { XX }, 0 },
2653 { REG_TABLE (REG_F6) },
2654 { REG_TABLE (REG_F7) },
2656 { "clc", { XX }, 0 },
2657 { "stc", { XX }, 0 },
2658 { "cli", { XX }, 0 },
2659 { "sti", { XX }, 0 },
2660 { "cld", { XX }, 0 },
2661 { "std", { XX }, 0 },
2662 { REG_TABLE (REG_FE) },
2663 { REG_TABLE (REG_FF) },
2666 static const struct dis386 dis386_twobyte[] = {
2668 { REG_TABLE (REG_0F00 ) },
2669 { REG_TABLE (REG_0F01 ) },
2670 { "larS", { Gv, Ew }, 0 },
2671 { "lslS", { Gv, Ew }, 0 },
2673 { "syscall", { XX }, 0 },
2674 { "clts", { XX }, 0 },
2675 { "sysret%LP", { XX }, 0 },
2677 { "invd", { XX }, 0 },
2678 { PREFIX_TABLE (PREFIX_0F09) },
2680 { "ud2", { XX }, 0 },
2682 { REG_TABLE (REG_0F0D) },
2683 { "femms", { XX }, 0 },
2684 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2686 { PREFIX_TABLE (PREFIX_0F10) },
2687 { PREFIX_TABLE (PREFIX_0F11) },
2688 { PREFIX_TABLE (PREFIX_0F12) },
2689 { MOD_TABLE (MOD_0F13) },
2690 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2691 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2692 { PREFIX_TABLE (PREFIX_0F16) },
2693 { MOD_TABLE (MOD_0F17) },
2695 { REG_TABLE (REG_0F18) },
2696 { "nopQ", { Ev }, 0 },
2697 { PREFIX_TABLE (PREFIX_0F1A) },
2698 { PREFIX_TABLE (PREFIX_0F1B) },
2699 { PREFIX_TABLE (PREFIX_0F1C) },
2700 { "nopQ", { Ev }, 0 },
2701 { PREFIX_TABLE (PREFIX_0F1E) },
2702 { "nopQ", { Ev }, 0 },
2704 { "movZ", { Rm, Cm }, 0 },
2705 { "movZ", { Rm, Dm }, 0 },
2706 { "movZ", { Cm, Rm }, 0 },
2707 { "movZ", { Dm, Rm }, 0 },
2708 { MOD_TABLE (MOD_0F24) },
2710 { MOD_TABLE (MOD_0F26) },
2713 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2714 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2715 { PREFIX_TABLE (PREFIX_0F2A) },
2716 { PREFIX_TABLE (PREFIX_0F2B) },
2717 { PREFIX_TABLE (PREFIX_0F2C) },
2718 { PREFIX_TABLE (PREFIX_0F2D) },
2719 { PREFIX_TABLE (PREFIX_0F2E) },
2720 { PREFIX_TABLE (PREFIX_0F2F) },
2722 { "wrmsr", { XX }, 0 },
2723 { "rdtsc", { XX }, 0 },
2724 { "rdmsr", { XX }, 0 },
2725 { "rdpmc", { XX }, 0 },
2726 { "sysenter", { XX }, 0 },
2727 { "sysexit", { XX }, 0 },
2729 { "getsec", { XX }, 0 },
2731 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2733 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2740 { "cmovoS", { Gv, Ev }, 0 },
2741 { "cmovnoS", { Gv, Ev }, 0 },
2742 { "cmovbS", { Gv, Ev }, 0 },
2743 { "cmovaeS", { Gv, Ev }, 0 },
2744 { "cmoveS", { Gv, Ev }, 0 },
2745 { "cmovneS", { Gv, Ev }, 0 },
2746 { "cmovbeS", { Gv, Ev }, 0 },
2747 { "cmovaS", { Gv, Ev }, 0 },
2749 { "cmovsS", { Gv, Ev }, 0 },
2750 { "cmovnsS", { Gv, Ev }, 0 },
2751 { "cmovpS", { Gv, Ev }, 0 },
2752 { "cmovnpS", { Gv, Ev }, 0 },
2753 { "cmovlS", { Gv, Ev }, 0 },
2754 { "cmovgeS", { Gv, Ev }, 0 },
2755 { "cmovleS", { Gv, Ev }, 0 },
2756 { "cmovgS", { Gv, Ev }, 0 },
2758 { MOD_TABLE (MOD_0F51) },
2759 { PREFIX_TABLE (PREFIX_0F51) },
2760 { PREFIX_TABLE (PREFIX_0F52) },
2761 { PREFIX_TABLE (PREFIX_0F53) },
2762 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2763 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2764 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2765 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2767 { PREFIX_TABLE (PREFIX_0F58) },
2768 { PREFIX_TABLE (PREFIX_0F59) },
2769 { PREFIX_TABLE (PREFIX_0F5A) },
2770 { PREFIX_TABLE (PREFIX_0F5B) },
2771 { PREFIX_TABLE (PREFIX_0F5C) },
2772 { PREFIX_TABLE (PREFIX_0F5D) },
2773 { PREFIX_TABLE (PREFIX_0F5E) },
2774 { PREFIX_TABLE (PREFIX_0F5F) },
2776 { PREFIX_TABLE (PREFIX_0F60) },
2777 { PREFIX_TABLE (PREFIX_0F61) },
2778 { PREFIX_TABLE (PREFIX_0F62) },
2779 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2780 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2781 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2782 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2783 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2785 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2786 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2787 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2788 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2789 { PREFIX_TABLE (PREFIX_0F6C) },
2790 { PREFIX_TABLE (PREFIX_0F6D) },
2791 { "movK", { MX, Edq }, PREFIX_OPCODE },
2792 { PREFIX_TABLE (PREFIX_0F6F) },
2794 { PREFIX_TABLE (PREFIX_0F70) },
2795 { REG_TABLE (REG_0F71) },
2796 { REG_TABLE (REG_0F72) },
2797 { REG_TABLE (REG_0F73) },
2798 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2799 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2800 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2801 { "emms", { XX }, PREFIX_OPCODE },
2803 { PREFIX_TABLE (PREFIX_0F78) },
2804 { PREFIX_TABLE (PREFIX_0F79) },
2807 { PREFIX_TABLE (PREFIX_0F7C) },
2808 { PREFIX_TABLE (PREFIX_0F7D) },
2809 { PREFIX_TABLE (PREFIX_0F7E) },
2810 { PREFIX_TABLE (PREFIX_0F7F) },
2812 { "joH", { Jv, BND, cond_jump_flag }, 0 },
2813 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
2814 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
2815 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
2816 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
2817 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
2818 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
2819 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
2821 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
2822 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
2823 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
2824 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
2825 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
2826 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
2827 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
2828 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
2830 { "seto", { Eb }, 0 },
2831 { "setno", { Eb }, 0 },
2832 { "setb", { Eb }, 0 },
2833 { "setae", { Eb }, 0 },
2834 { "sete", { Eb }, 0 },
2835 { "setne", { Eb }, 0 },
2836 { "setbe", { Eb }, 0 },
2837 { "seta", { Eb }, 0 },
2839 { "sets", { Eb }, 0 },
2840 { "setns", { Eb }, 0 },
2841 { "setp", { Eb }, 0 },
2842 { "setnp", { Eb }, 0 },
2843 { "setl", { Eb }, 0 },
2844 { "setge", { Eb }, 0 },
2845 { "setle", { Eb }, 0 },
2846 { "setg", { Eb }, 0 },
2848 { "pushT", { fs }, 0 },
2849 { "popT", { fs }, 0 },
2850 { "cpuid", { XX }, 0 },
2851 { "btS", { Ev, Gv }, 0 },
2852 { "shldS", { Ev, Gv, Ib }, 0 },
2853 { "shldS", { Ev, Gv, CL }, 0 },
2854 { REG_TABLE (REG_0FA6) },
2855 { REG_TABLE (REG_0FA7) },
2857 { "pushT", { gs }, 0 },
2858 { "popT", { gs }, 0 },
2859 { "rsm", { XX }, 0 },
2860 { "btsS", { Evh1, Gv }, 0 },
2861 { "shrdS", { Ev, Gv, Ib }, 0 },
2862 { "shrdS", { Ev, Gv, CL }, 0 },
2863 { REG_TABLE (REG_0FAE) },
2864 { "imulS", { Gv, Ev }, 0 },
2866 { "cmpxchgB", { Ebh1, Gb }, 0 },
2867 { "cmpxchgS", { Evh1, Gv }, 0 },
2868 { MOD_TABLE (MOD_0FB2) },
2869 { "btrS", { Evh1, Gv }, 0 },
2870 { MOD_TABLE (MOD_0FB4) },
2871 { MOD_TABLE (MOD_0FB5) },
2872 { "movz{bR|x}", { Gv, Eb }, 0 },
2873 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2875 { PREFIX_TABLE (PREFIX_0FB8) },
2876 { "ud1S", { Gv, Ev }, 0 },
2877 { REG_TABLE (REG_0FBA) },
2878 { "btcS", { Evh1, Gv }, 0 },
2879 { PREFIX_TABLE (PREFIX_0FBC) },
2880 { PREFIX_TABLE (PREFIX_0FBD) },
2881 { "movs{bR|x}", { Gv, Eb }, 0 },
2882 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2884 { "xaddB", { Ebh1, Gb }, 0 },
2885 { "xaddS", { Evh1, Gv }, 0 },
2886 { PREFIX_TABLE (PREFIX_0FC2) },
2887 { MOD_TABLE (MOD_0FC3) },
2888 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
2889 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
2890 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
2891 { REG_TABLE (REG_0FC7) },
2893 { "bswap", { RMeAX }, 0 },
2894 { "bswap", { RMeCX }, 0 },
2895 { "bswap", { RMeDX }, 0 },
2896 { "bswap", { RMeBX }, 0 },
2897 { "bswap", { RMeSP }, 0 },
2898 { "bswap", { RMeBP }, 0 },
2899 { "bswap", { RMeSI }, 0 },
2900 { "bswap", { RMeDI }, 0 },
2902 { PREFIX_TABLE (PREFIX_0FD0) },
2903 { "psrlw", { MX, EM }, PREFIX_OPCODE },
2904 { "psrld", { MX, EM }, PREFIX_OPCODE },
2905 { "psrlq", { MX, EM }, PREFIX_OPCODE },
2906 { "paddq", { MX, EM }, PREFIX_OPCODE },
2907 { "pmullw", { MX, EM }, PREFIX_OPCODE },
2908 { PREFIX_TABLE (PREFIX_0FD6) },
2909 { MOD_TABLE (MOD_0FD7) },
2911 { "psubusb", { MX, EM }, PREFIX_OPCODE },
2912 { "psubusw", { MX, EM }, PREFIX_OPCODE },
2913 { "pminub", { MX, EM }, PREFIX_OPCODE },
2914 { "pand", { MX, EM }, PREFIX_OPCODE },
2915 { "paddusb", { MX, EM }, PREFIX_OPCODE },
2916 { "paddusw", { MX, EM }, PREFIX_OPCODE },
2917 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
2918 { "pandn", { MX, EM }, PREFIX_OPCODE },
2920 { "pavgb", { MX, EM }, PREFIX_OPCODE },
2921 { "psraw", { MX, EM }, PREFIX_OPCODE },
2922 { "psrad", { MX, EM }, PREFIX_OPCODE },
2923 { "pavgw", { MX, EM }, PREFIX_OPCODE },
2924 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
2925 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
2926 { PREFIX_TABLE (PREFIX_0FE6) },
2927 { PREFIX_TABLE (PREFIX_0FE7) },
2929 { "psubsb", { MX, EM }, PREFIX_OPCODE },
2930 { "psubsw", { MX, EM }, PREFIX_OPCODE },
2931 { "pminsw", { MX, EM }, PREFIX_OPCODE },
2932 { "por", { MX, EM }, PREFIX_OPCODE },
2933 { "paddsb", { MX, EM }, PREFIX_OPCODE },
2934 { "paddsw", { MX, EM }, PREFIX_OPCODE },
2935 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
2936 { "pxor", { MX, EM }, PREFIX_OPCODE },
2938 { PREFIX_TABLE (PREFIX_0FF0) },
2939 { "psllw", { MX, EM }, PREFIX_OPCODE },
2940 { "pslld", { MX, EM }, PREFIX_OPCODE },
2941 { "psllq", { MX, EM }, PREFIX_OPCODE },
2942 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
2943 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
2944 { "psadbw", { MX, EM }, PREFIX_OPCODE },
2945 { PREFIX_TABLE (PREFIX_0FF7) },
2947 { "psubb", { MX, EM }, PREFIX_OPCODE },
2948 { "psubw", { MX, EM }, PREFIX_OPCODE },
2949 { "psubd", { MX, EM }, PREFIX_OPCODE },
2950 { "psubq", { MX, EM }, PREFIX_OPCODE },
2951 { "paddb", { MX, EM }, PREFIX_OPCODE },
2952 { "paddw", { MX, EM }, PREFIX_OPCODE },
2953 { "paddd", { MX, EM }, PREFIX_OPCODE },
2954 { "ud0S", { Gv, Ev }, 0 },
2957 static const unsigned char onebyte_has_modrm[256] = {
2958 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2959 /* ------------------------------- */
2960 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2961 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2962 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2963 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2964 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2965 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2966 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2967 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2968 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2969 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2970 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2971 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2972 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2973 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2974 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2975 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2976 /* ------------------------------- */
2977 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2980 static const unsigned char twobyte_has_modrm[256] = {
2981 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2982 /* ------------------------------- */
2983 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2984 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2985 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2986 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2987 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2988 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2989 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2990 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2991 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2992 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2993 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2994 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2995 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2996 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2997 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2998 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2999 /* ------------------------------- */
3000 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3003 static char obuf[100];
3005 static char *mnemonicendp;
3006 static char scratchbuf[100];
3007 static unsigned char *start_codep;
3008 static unsigned char *insn_codep;
3009 static unsigned char *codep;
3010 static unsigned char *end_codep;
3011 static int last_lock_prefix;
3012 static int last_repz_prefix;
3013 static int last_repnz_prefix;
3014 static int last_data_prefix;
3015 static int last_addr_prefix;
3016 static int last_rex_prefix;
3017 static int last_seg_prefix;
3018 static int fwait_prefix;
3019 /* The active segment register prefix. */
3020 static int active_seg_prefix;
3021 #define MAX_CODE_LENGTH 15
3022 /* We can up to 14 prefixes since the maximum instruction length is
3024 static int all_prefixes[MAX_CODE_LENGTH - 1];
3025 static disassemble_info *the_info;
3033 static unsigned char need_modrm;
3043 int register_specifier;
3050 int mask_register_specifier;
3056 static unsigned char need_vex;
3057 static unsigned char need_vex_reg;
3058 static unsigned char vex_w_done;
3066 /* If we are accessing mod/rm/reg without need_modrm set, then the
3067 values are stale. Hitting this abort likely indicates that you
3068 need to update onebyte_has_modrm or twobyte_has_modrm. */
3069 #define MODRM_CHECK if (!need_modrm) abort ()
3071 static const char **names64;
3072 static const char **names32;
3073 static const char **names16;
3074 static const char **names8;
3075 static const char **names8rex;
3076 static const char **names_seg;
3077 static const char *index64;
3078 static const char *index32;
3079 static const char **index16;
3080 static const char **names_bnd;
3082 static const char *intel_names64[] = {
3083 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3084 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3086 static const char *intel_names32[] = {
3087 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3088 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3090 static const char *intel_names16[] = {
3091 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3092 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3094 static const char *intel_names8[] = {
3095 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3097 static const char *intel_names8rex[] = {
3098 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3099 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3101 static const char *intel_names_seg[] = {
3102 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3104 static const char *intel_index64 = "riz";
3105 static const char *intel_index32 = "eiz";
3106 static const char *intel_index16[] = {
3107 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3110 static const char *att_names64[] = {
3111 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3112 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3114 static const char *att_names32[] = {
3115 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3116 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3118 static const char *att_names16[] = {
3119 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3120 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3122 static const char *att_names8[] = {
3123 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3125 static const char *att_names8rex[] = {
3126 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3127 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3129 static const char *att_names_seg[] = {
3130 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3132 static const char *att_index64 = "%riz";
3133 static const char *att_index32 = "%eiz";
3134 static const char *att_index16[] = {
3135 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3138 static const char **names_mm;
3139 static const char *intel_names_mm[] = {
3140 "mm0", "mm1", "mm2", "mm3",
3141 "mm4", "mm5", "mm6", "mm7"
3143 static const char *att_names_mm[] = {
3144 "%mm0", "%mm1", "%mm2", "%mm3",
3145 "%mm4", "%mm5", "%mm6", "%mm7"
3148 static const char *intel_names_bnd[] = {
3149 "bnd0", "bnd1", "bnd2", "bnd3"
3152 static const char *att_names_bnd[] = {
3153 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3156 static const char **names_xmm;
3157 static const char *intel_names_xmm[] = {
3158 "xmm0", "xmm1", "xmm2", "xmm3",
3159 "xmm4", "xmm5", "xmm6", "xmm7",
3160 "xmm8", "xmm9", "xmm10", "xmm11",
3161 "xmm12", "xmm13", "xmm14", "xmm15",
3162 "xmm16", "xmm17", "xmm18", "xmm19",
3163 "xmm20", "xmm21", "xmm22", "xmm23",
3164 "xmm24", "xmm25", "xmm26", "xmm27",
3165 "xmm28", "xmm29", "xmm30", "xmm31"
3167 static const char *att_names_xmm[] = {
3168 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3169 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3170 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3171 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3172 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3173 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3174 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3175 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3178 static const char **names_ymm;
3179 static const char *intel_names_ymm[] = {
3180 "ymm0", "ymm1", "ymm2", "ymm3",
3181 "ymm4", "ymm5", "ymm6", "ymm7",
3182 "ymm8", "ymm9", "ymm10", "ymm11",
3183 "ymm12", "ymm13", "ymm14", "ymm15",
3184 "ymm16", "ymm17", "ymm18", "ymm19",
3185 "ymm20", "ymm21", "ymm22", "ymm23",
3186 "ymm24", "ymm25", "ymm26", "ymm27",
3187 "ymm28", "ymm29", "ymm30", "ymm31"
3189 static const char *att_names_ymm[] = {
3190 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3191 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3192 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3193 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3194 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3195 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3196 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3197 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3200 static const char **names_zmm;
3201 static const char *intel_names_zmm[] = {
3202 "zmm0", "zmm1", "zmm2", "zmm3",
3203 "zmm4", "zmm5", "zmm6", "zmm7",
3204 "zmm8", "zmm9", "zmm10", "zmm11",
3205 "zmm12", "zmm13", "zmm14", "zmm15",
3206 "zmm16", "zmm17", "zmm18", "zmm19",
3207 "zmm20", "zmm21", "zmm22", "zmm23",
3208 "zmm24", "zmm25", "zmm26", "zmm27",
3209 "zmm28", "zmm29", "zmm30", "zmm31"
3211 static const char *att_names_zmm[] = {
3212 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3213 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3214 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3215 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3216 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3217 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3218 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3219 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3222 static const char **names_mask;
3223 static const char *intel_names_mask[] = {
3224 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3226 static const char *att_names_mask[] = {
3227 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3230 static const char *names_rounding[] =
3238 static const struct dis386 reg_table[][8] = {
3241 { "addA", { Ebh1, Ib }, 0 },
3242 { "orA", { Ebh1, Ib }, 0 },
3243 { "adcA", { Ebh1, Ib }, 0 },
3244 { "sbbA", { Ebh1, Ib }, 0 },
3245 { "andA", { Ebh1, Ib }, 0 },
3246 { "subA", { Ebh1, Ib }, 0 },
3247 { "xorA", { Ebh1, Ib }, 0 },
3248 { "cmpA", { Eb, Ib }, 0 },
3252 { "addQ", { Evh1, Iv }, 0 },
3253 { "orQ", { Evh1, Iv }, 0 },
3254 { "adcQ", { Evh1, Iv }, 0 },
3255 { "sbbQ", { Evh1, Iv }, 0 },
3256 { "andQ", { Evh1, Iv }, 0 },
3257 { "subQ", { Evh1, Iv }, 0 },
3258 { "xorQ", { Evh1, Iv }, 0 },
3259 { "cmpQ", { Ev, Iv }, 0 },
3263 { "addQ", { Evh1, sIb }, 0 },
3264 { "orQ", { Evh1, sIb }, 0 },
3265 { "adcQ", { Evh1, sIb }, 0 },
3266 { "sbbQ", { Evh1, sIb }, 0 },
3267 { "andQ", { Evh1, sIb }, 0 },
3268 { "subQ", { Evh1, sIb }, 0 },
3269 { "xorQ", { Evh1, sIb }, 0 },
3270 { "cmpQ", { Ev, sIb }, 0 },
3274 { "popU", { stackEv }, 0 },
3275 { XOP_8F_TABLE (XOP_09) },
3279 { XOP_8F_TABLE (XOP_09) },
3283 { "rolA", { Eb, Ib }, 0 },
3284 { "rorA", { Eb, Ib }, 0 },
3285 { "rclA", { Eb, Ib }, 0 },
3286 { "rcrA", { Eb, Ib }, 0 },
3287 { "shlA", { Eb, Ib }, 0 },
3288 { "shrA", { Eb, Ib }, 0 },
3289 { "shlA", { Eb, Ib }, 0 },
3290 { "sarA", { Eb, Ib }, 0 },
3294 { "rolQ", { Ev, Ib }, 0 },
3295 { "rorQ", { Ev, Ib }, 0 },
3296 { "rclQ", { Ev, Ib }, 0 },
3297 { "rcrQ", { Ev, Ib }, 0 },
3298 { "shlQ", { Ev, Ib }, 0 },
3299 { "shrQ", { Ev, Ib }, 0 },
3300 { "shlQ", { Ev, Ib }, 0 },
3301 { "sarQ", { Ev, Ib }, 0 },
3305 { "movA", { Ebh3, Ib }, 0 },
3312 { MOD_TABLE (MOD_C6_REG_7) },
3316 { "movQ", { Evh3, Iv }, 0 },
3323 { MOD_TABLE (MOD_C7_REG_7) },
3327 { "rolA", { Eb, I1 }, 0 },
3328 { "rorA", { Eb, I1 }, 0 },
3329 { "rclA", { Eb, I1 }, 0 },
3330 { "rcrA", { Eb, I1 }, 0 },
3331 { "shlA", { Eb, I1 }, 0 },
3332 { "shrA", { Eb, I1 }, 0 },
3333 { "shlA", { Eb, I1 }, 0 },
3334 { "sarA", { Eb, I1 }, 0 },
3338 { "rolQ", { Ev, I1 }, 0 },
3339 { "rorQ", { Ev, I1 }, 0 },
3340 { "rclQ", { Ev, I1 }, 0 },
3341 { "rcrQ", { Ev, I1 }, 0 },
3342 { "shlQ", { Ev, I1 }, 0 },
3343 { "shrQ", { Ev, I1 }, 0 },
3344 { "shlQ", { Ev, I1 }, 0 },
3345 { "sarQ", { Ev, I1 }, 0 },
3349 { "rolA", { Eb, CL }, 0 },
3350 { "rorA", { Eb, CL }, 0 },
3351 { "rclA", { Eb, CL }, 0 },
3352 { "rcrA", { Eb, CL }, 0 },
3353 { "shlA", { Eb, CL }, 0 },
3354 { "shrA", { Eb, CL }, 0 },
3355 { "shlA", { Eb, CL }, 0 },
3356 { "sarA", { Eb, CL }, 0 },
3360 { "rolQ", { Ev, CL }, 0 },
3361 { "rorQ", { Ev, CL }, 0 },
3362 { "rclQ", { Ev, CL }, 0 },
3363 { "rcrQ", { Ev, CL }, 0 },
3364 { "shlQ", { Ev, CL }, 0 },
3365 { "shrQ", { Ev, CL }, 0 },
3366 { "shlQ", { Ev, CL }, 0 },
3367 { "sarQ", { Ev, CL }, 0 },
3371 { "testA", { Eb, Ib }, 0 },
3372 { "testA", { Eb, Ib }, 0 },
3373 { "notA", { Ebh1 }, 0 },
3374 { "negA", { Ebh1 }, 0 },
3375 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
3376 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
3377 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
3378 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
3382 { "testQ", { Ev, Iv }, 0 },
3383 { "testQ", { Ev, Iv }, 0 },
3384 { "notQ", { Evh1 }, 0 },
3385 { "negQ", { Evh1 }, 0 },
3386 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
3387 { "imulQ", { Ev }, 0 },
3388 { "divQ", { Ev }, 0 },
3389 { "idivQ", { Ev }, 0 },
3393 { "incA", { Ebh1 }, 0 },
3394 { "decA", { Ebh1 }, 0 },
3398 { "incQ", { Evh1 }, 0 },
3399 { "decQ", { Evh1 }, 0 },
3400 { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3401 { MOD_TABLE (MOD_FF_REG_3) },
3402 { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3403 { MOD_TABLE (MOD_FF_REG_5) },
3404 { "pushU", { stackEv }, 0 },
3409 { "sldtD", { Sv }, 0 },
3410 { "strD", { Sv }, 0 },
3411 { "lldt", { Ew }, 0 },
3412 { "ltr", { Ew }, 0 },
3413 { "verr", { Ew }, 0 },
3414 { "verw", { Ew }, 0 },
3420 { MOD_TABLE (MOD_0F01_REG_0) },
3421 { MOD_TABLE (MOD_0F01_REG_1) },
3422 { MOD_TABLE (MOD_0F01_REG_2) },
3423 { MOD_TABLE (MOD_0F01_REG_3) },
3424 { "smswD", { Sv }, 0 },
3425 { MOD_TABLE (MOD_0F01_REG_5) },
3426 { "lmsw", { Ew }, 0 },
3427 { MOD_TABLE (MOD_0F01_REG_7) },
3431 { "prefetch", { Mb }, 0 },
3432 { "prefetchw", { Mb }, 0 },
3433 { "prefetchwt1", { Mb }, 0 },
3434 { "prefetch", { Mb }, 0 },
3435 { "prefetch", { Mb }, 0 },
3436 { "prefetch", { Mb }, 0 },
3437 { "prefetch", { Mb }, 0 },
3438 { "prefetch", { Mb }, 0 },
3442 { MOD_TABLE (MOD_0F18_REG_0) },
3443 { MOD_TABLE (MOD_0F18_REG_1) },
3444 { MOD_TABLE (MOD_0F18_REG_2) },
3445 { MOD_TABLE (MOD_0F18_REG_3) },
3446 { MOD_TABLE (MOD_0F18_REG_4) },
3447 { MOD_TABLE (MOD_0F18_REG_5) },
3448 { MOD_TABLE (MOD_0F18_REG_6) },
3449 { MOD_TABLE (MOD_0F18_REG_7) },
3451 /* REG_0F1C_MOD_0 */
3453 { "cldemote", { Mb }, 0 },
3454 { "nopQ", { Ev }, 0 },
3455 { "nopQ", { Ev }, 0 },
3456 { "nopQ", { Ev }, 0 },
3457 { "nopQ", { Ev }, 0 },
3458 { "nopQ", { Ev }, 0 },
3459 { "nopQ", { Ev }, 0 },
3460 { "nopQ", { Ev }, 0 },
3462 /* REG_0F1E_MOD_3 */
3464 { "nopQ", { Ev }, 0 },
3465 { "rdsspK", { Rdq }, PREFIX_OPCODE },
3466 { "nopQ", { Ev }, 0 },
3467 { "nopQ", { Ev }, 0 },
3468 { "nopQ", { Ev }, 0 },
3469 { "nopQ", { Ev }, 0 },
3470 { "nopQ", { Ev }, 0 },
3471 { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3477 { MOD_TABLE (MOD_0F71_REG_2) },
3479 { MOD_TABLE (MOD_0F71_REG_4) },
3481 { MOD_TABLE (MOD_0F71_REG_6) },
3487 { MOD_TABLE (MOD_0F72_REG_2) },
3489 { MOD_TABLE (MOD_0F72_REG_4) },
3491 { MOD_TABLE (MOD_0F72_REG_6) },
3497 { MOD_TABLE (MOD_0F73_REG_2) },
3498 { MOD_TABLE (MOD_0F73_REG_3) },
3501 { MOD_TABLE (MOD_0F73_REG_6) },
3502 { MOD_TABLE (MOD_0F73_REG_7) },
3506 { "montmul", { { OP_0f07, 0 } }, 0 },
3507 { "xsha1", { { OP_0f07, 0 } }, 0 },
3508 { "xsha256", { { OP_0f07, 0 } }, 0 },
3512 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
3513 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
3514 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
3515 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
3516 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
3517 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
3521 { MOD_TABLE (MOD_0FAE_REG_0) },
3522 { MOD_TABLE (MOD_0FAE_REG_1) },
3523 { MOD_TABLE (MOD_0FAE_REG_2) },
3524 { MOD_TABLE (MOD_0FAE_REG_3) },
3525 { MOD_TABLE (MOD_0FAE_REG_4) },
3526 { MOD_TABLE (MOD_0FAE_REG_5) },
3527 { MOD_TABLE (MOD_0FAE_REG_6) },
3528 { MOD_TABLE (MOD_0FAE_REG_7) },
3536 { "btQ", { Ev, Ib }, 0 },
3537 { "btsQ", { Evh1, Ib }, 0 },
3538 { "btrQ", { Evh1, Ib }, 0 },
3539 { "btcQ", { Evh1, Ib }, 0 },
3544 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3546 { MOD_TABLE (MOD_0FC7_REG_3) },
3547 { MOD_TABLE (MOD_0FC7_REG_4) },
3548 { MOD_TABLE (MOD_0FC7_REG_5) },
3549 { MOD_TABLE (MOD_0FC7_REG_6) },
3550 { MOD_TABLE (MOD_0FC7_REG_7) },
3556 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3558 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3560 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3566 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3568 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3570 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3576 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3577 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3580 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3581 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3587 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3588 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3590 /* REG_VEX_0F38F3 */
3593 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3594 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3595 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3599 { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3600 { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3604 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3605 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3607 /* REG_XOP_TBM_01 */
3610 { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3611 { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3612 { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 },
3613 { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3614 { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 },
3615 { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 },
3616 { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3618 /* REG_XOP_TBM_02 */
3621 { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3626 { "blci", { { OP_LWP_E, 0 }, Ev }, 0 },
3629 #include "i386-dis-evex-reg.h"
3632 static const struct dis386 prefix_table[][4] = {
3635 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3636 { "pause", { XX }, 0 },
3637 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3638 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3641 /* PREFIX_MOD_0_0F01_REG_5 */
3644 { "rstorssp", { Mq }, PREFIX_OPCODE },
3647 /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3650 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3653 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3656 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3661 { "wbinvd", { XX }, 0 },
3662 { "wbnoinvd", { XX }, 0 },
3667 { "movups", { XM, EXx }, PREFIX_OPCODE },
3668 { "movss", { XM, EXd }, PREFIX_OPCODE },
3669 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3670 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3675 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3676 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3677 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3678 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3683 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3684 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3685 { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3686 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3691 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3692 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3693 { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3698 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3699 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3700 { "bndmov", { Gbnd, Ebnd }, 0 },
3701 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3706 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3707 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3708 { "bndmov", { EbndS, Gbnd }, 0 },
3709 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3714 { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3715 { "nopQ", { Ev }, PREFIX_OPCODE },
3716 { "nopQ", { Ev }, PREFIX_OPCODE },
3717 { "nopQ", { Ev }, PREFIX_OPCODE },
3722 { "nopQ", { Ev }, PREFIX_OPCODE },
3723 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3724 { "nopQ", { Ev }, PREFIX_OPCODE },
3725 { "nopQ", { Ev }, PREFIX_OPCODE },
3730 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3731 { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3732 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3733 { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3738 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3739 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3740 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3741 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3746 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3747 { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE },
3748 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3749 { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE },
3754 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3755 { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE },
3756 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3757 { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE },
3762 { "ucomiss",{ XM, EXd }, 0 },
3764 { "ucomisd",{ XM, EXq }, 0 },
3769 { "comiss", { XM, EXd }, 0 },
3771 { "comisd", { XM, EXq }, 0 },
3776 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3777 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3778 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3779 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3784 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3785 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3790 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3791 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3796 { "addps", { XM, EXx }, PREFIX_OPCODE },
3797 { "addss", { XM, EXd }, PREFIX_OPCODE },
3798 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3799 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3804 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3805 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3806 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3807 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3812 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3813 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3814 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3815 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3820 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3821 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3822 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3827 { "subps", { XM, EXx }, PREFIX_OPCODE },
3828 { "subss", { XM, EXd }, PREFIX_OPCODE },
3829 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3830 { "subsd", { XM, EXq }, PREFIX_OPCODE },
3835 { "minps", { XM, EXx }, PREFIX_OPCODE },
3836 { "minss", { XM, EXd }, PREFIX_OPCODE },
3837 { "minpd", { XM, EXx }, PREFIX_OPCODE },
3838 { "minsd", { XM, EXq }, PREFIX_OPCODE },
3843 { "divps", { XM, EXx }, PREFIX_OPCODE },
3844 { "divss", { XM, EXd }, PREFIX_OPCODE },
3845 { "divpd", { XM, EXx }, PREFIX_OPCODE },
3846 { "divsd", { XM, EXq }, PREFIX_OPCODE },
3851 { "maxps", { XM, EXx }, PREFIX_OPCODE },
3852 { "maxss", { XM, EXd }, PREFIX_OPCODE },
3853 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
3854 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
3859 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3861 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3866 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3868 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3873 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3875 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3882 { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3889 { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3894 { "movq", { MX, EM }, PREFIX_OPCODE },
3895 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3896 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3901 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3902 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3903 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3904 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3907 /* PREFIX_0F73_REG_3 */
3911 { "psrldq", { XS, Ib }, 0 },
3914 /* PREFIX_0F73_REG_7 */
3918 { "pslldq", { XS, Ib }, 0 },
3923 {"vmread", { Em, Gm }, 0 },
3925 {"extrq", { XS, Ib, Ib }, 0 },
3926 {"insertq", { XM, XS, Ib, Ib }, 0 },
3931 {"vmwrite", { Gm, Em }, 0 },
3933 {"extrq", { XM, XS }, 0 },
3934 {"insertq", { XM, XS }, 0 },
3941 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3942 { "haddps", { XM, EXx }, PREFIX_OPCODE },
3949 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3950 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3955 { "movK", { Edq, MX }, PREFIX_OPCODE },
3956 { "movq", { XM, EXq }, PREFIX_OPCODE },
3957 { "movK", { Edq, XM }, PREFIX_OPCODE },
3962 { "movq", { EMS, MX }, PREFIX_OPCODE },
3963 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3964 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3967 /* PREFIX_0FAE_REG_0 */
3970 { "rdfsbase", { Ev }, 0 },
3973 /* PREFIX_0FAE_REG_1 */
3976 { "rdgsbase", { Ev }, 0 },
3979 /* PREFIX_0FAE_REG_2 */
3982 { "wrfsbase", { Ev }, 0 },
3985 /* PREFIX_0FAE_REG_3 */
3988 { "wrgsbase", { Ev }, 0 },
3991 /* PREFIX_MOD_0_0FAE_REG_4 */
3993 { "xsave", { FXSAVE }, 0 },
3994 { "ptwrite%LQ", { Edq }, 0 },
3997 /* PREFIX_MOD_3_0FAE_REG_4 */
4000 { "ptwrite%LQ", { Edq }, 0 },
4003 /* PREFIX_MOD_0_0FAE_REG_5 */
4005 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
4008 /* PREFIX_MOD_3_0FAE_REG_5 */
4010 { "lfence", { Skip_MODRM }, 0 },
4011 { "incsspK", { Rdq }, PREFIX_OPCODE },
4014 /* PREFIX_MOD_0_0FAE_REG_6 */
4016 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
4017 { "clrssbsy", { Mq }, PREFIX_OPCODE },
4018 { "clwb", { Mb }, PREFIX_OPCODE },
4021 /* PREFIX_MOD_1_0FAE_REG_6 */
4023 { RM_TABLE (RM_0FAE_REG_6) },
4024 { "umonitor", { Eva }, PREFIX_OPCODE },
4025 { "tpause", { Edq }, PREFIX_OPCODE },
4026 { "umwait", { Edq }, PREFIX_OPCODE },
4029 /* PREFIX_0FAE_REG_7 */
4031 { "clflush", { Mb }, 0 },
4033 { "clflushopt", { Mb }, 0 },
4039 { "popcntS", { Gv, Ev }, 0 },
4044 { "bsfS", { Gv, Ev }, 0 },
4045 { "tzcntS", { Gv, Ev }, 0 },
4046 { "bsfS", { Gv, Ev }, 0 },
4051 { "bsrS", { Gv, Ev }, 0 },
4052 { "lzcntS", { Gv, Ev }, 0 },
4053 { "bsrS", { Gv, Ev }, 0 },
4058 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
4059 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
4060 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
4061 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
4064 /* PREFIX_MOD_0_0FC3 */
4066 { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4069 /* PREFIX_MOD_0_0FC7_REG_6 */
4071 { "vmptrld",{ Mq }, 0 },
4072 { "vmxon", { Mq }, 0 },
4073 { "vmclear",{ Mq }, 0 },
4076 /* PREFIX_MOD_3_0FC7_REG_6 */
4078 { "rdrand", { Ev }, 0 },
4080 { "rdrand", { Ev }, 0 }
4083 /* PREFIX_MOD_3_0FC7_REG_7 */
4085 { "rdseed", { Ev }, 0 },
4086 { "rdpid", { Em }, 0 },
4087 { "rdseed", { Ev }, 0 },
4094 { "addsubpd", { XM, EXx }, 0 },
4095 { "addsubps", { XM, EXx }, 0 },
4101 { "movq2dq",{ XM, MS }, 0 },
4102 { "movq", { EXqS, XM }, 0 },
4103 { "movdq2q",{ MX, XS }, 0 },
4109 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4110 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4111 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4116 { "movntq", { Mq, MX }, PREFIX_OPCODE },
4118 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4126 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4131 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4133 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4140 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4147 { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4154 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4161 { "ptest", { XM, EXx }, PREFIX_OPCODE },
4168 { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4175 { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4182 { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4189 { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4196 { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4203 { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4210 { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4217 { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4224 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4231 { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4238 { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4245 { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4252 { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4259 { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4266 { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4273 { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4280 { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4287 { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4294 { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4301 { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4308 { "pminud", { XM, EXx }, PREFIX_OPCODE },
4315 { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4322 { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4329 { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4336 { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4343 { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4350 { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4357 { "invept", { Gm, Mo }, PREFIX_OPCODE },
4364 { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4371 { "invpcid", { Gm, M }, PREFIX_OPCODE },
4376 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4381 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4386 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4391 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4396 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4401 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4408 { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4415 { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4422 { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4429 { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4436 { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4443 { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4448 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4450 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4451 { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4456 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4458 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4459 { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4466 { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4471 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4472 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
4473 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
4480 { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4481 { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4482 { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4487 { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4494 { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4501 { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4508 { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4515 { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4522 { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4529 { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4536 { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4543 { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4550 { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4557 { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4564 { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4571 { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4578 { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4585 { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4592 { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE },
4599 { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE },
4606 { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4613 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4620 { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4627 { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4634 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4641 { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4646 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4653 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4660 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4667 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4670 /* PREFIX_VEX_0F10 */
4672 { "vmovups", { XM, EXx }, 0 },
4673 { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
4674 { "vmovupd", { XM, EXx }, 0 },
4675 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
4678 /* PREFIX_VEX_0F11 */
4680 { "vmovups", { EXxS, XM }, 0 },
4681 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4682 { "vmovupd", { EXxS, XM }, 0 },
4683 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4686 /* PREFIX_VEX_0F12 */
4688 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4689 { "vmovsldup", { XM, EXx }, 0 },
4690 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4691 { "vmovddup", { XM, EXymmq }, 0 },
4694 /* PREFIX_VEX_0F16 */
4696 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4697 { "vmovshdup", { XM, EXx }, 0 },
4698 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4701 /* PREFIX_VEX_0F2A */
4704 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4706 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4709 /* PREFIX_VEX_0F2C */
4712 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4714 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4717 /* PREFIX_VEX_0F2D */
4720 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4722 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4725 /* PREFIX_VEX_0F2E */
4727 { "vucomiss", { XMScalar, EXdScalar }, 0 },
4729 { "vucomisd", { XMScalar, EXqScalar }, 0 },
4732 /* PREFIX_VEX_0F2F */
4734 { "vcomiss", { XMScalar, EXdScalar }, 0 },
4736 { "vcomisd", { XMScalar, EXqScalar }, 0 },
4739 /* PREFIX_VEX_0F41 */
4741 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4743 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4746 /* PREFIX_VEX_0F42 */
4748 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4750 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4753 /* PREFIX_VEX_0F44 */
4755 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4757 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4760 /* PREFIX_VEX_0F45 */
4762 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4764 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4767 /* PREFIX_VEX_0F46 */
4769 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4771 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4774 /* PREFIX_VEX_0F47 */
4776 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4778 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4781 /* PREFIX_VEX_0F4A */
4783 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4785 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4788 /* PREFIX_VEX_0F4B */
4790 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4792 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4795 /* PREFIX_VEX_0F51 */
4797 { "vsqrtps", { XM, EXx }, 0 },
4798 { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
4799 { "vsqrtpd", { XM, EXx }, 0 },
4800 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4803 /* PREFIX_VEX_0F52 */
4805 { "vrsqrtps", { XM, EXx }, 0 },
4806 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
4809 /* PREFIX_VEX_0F53 */
4811 { "vrcpps", { XM, EXx }, 0 },
4812 { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
4815 /* PREFIX_VEX_0F58 */
4817 { "vaddps", { XM, Vex, EXx }, 0 },
4818 { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
4819 { "vaddpd", { XM, Vex, EXx }, 0 },
4820 { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4823 /* PREFIX_VEX_0F59 */
4825 { "vmulps", { XM, Vex, EXx }, 0 },
4826 { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
4827 { "vmulpd", { XM, Vex, EXx }, 0 },
4828 { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4831 /* PREFIX_VEX_0F5A */
4833 { "vcvtps2pd", { XM, EXxmmq }, 0 },
4834 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
4835 { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4836 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
4839 /* PREFIX_VEX_0F5B */
4841 { "vcvtdq2ps", { XM, EXx }, 0 },
4842 { "vcvttps2dq", { XM, EXx }, 0 },
4843 { "vcvtps2dq", { XM, EXx }, 0 },
4846 /* PREFIX_VEX_0F5C */
4848 { "vsubps", { XM, Vex, EXx }, 0 },
4849 { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
4850 { "vsubpd", { XM, Vex, EXx }, 0 },
4851 { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4854 /* PREFIX_VEX_0F5D */
4856 { "vminps", { XM, Vex, EXx }, 0 },
4857 { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
4858 { "vminpd", { XM, Vex, EXx }, 0 },
4859 { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4862 /* PREFIX_VEX_0F5E */
4864 { "vdivps", { XM, Vex, EXx }, 0 },
4865 { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
4866 { "vdivpd", { XM, Vex, EXx }, 0 },
4867 { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4870 /* PREFIX_VEX_0F5F */
4872 { "vmaxps", { XM, Vex, EXx }, 0 },
4873 { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
4874 { "vmaxpd", { XM, Vex, EXx }, 0 },
4875 { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4878 /* PREFIX_VEX_0F60 */
4882 { "vpunpcklbw", { XM, Vex, EXx }, 0 },
4885 /* PREFIX_VEX_0F61 */
4889 { "vpunpcklwd", { XM, Vex, EXx }, 0 },
4892 /* PREFIX_VEX_0F62 */
4896 { "vpunpckldq", { XM, Vex, EXx }, 0 },
4899 /* PREFIX_VEX_0F63 */
4903 { "vpacksswb", { XM, Vex, EXx }, 0 },
4906 /* PREFIX_VEX_0F64 */
4910 { "vpcmpgtb", { XM, Vex, EXx }, 0 },
4913 /* PREFIX_VEX_0F65 */
4917 { "vpcmpgtw", { XM, Vex, EXx }, 0 },
4920 /* PREFIX_VEX_0F66 */
4924 { "vpcmpgtd", { XM, Vex, EXx }, 0 },
4927 /* PREFIX_VEX_0F67 */
4931 { "vpackuswb", { XM, Vex, EXx }, 0 },
4934 /* PREFIX_VEX_0F68 */
4938 { "vpunpckhbw", { XM, Vex, EXx }, 0 },
4941 /* PREFIX_VEX_0F69 */
4945 { "vpunpckhwd", { XM, Vex, EXx }, 0 },
4948 /* PREFIX_VEX_0F6A */
4952 { "vpunpckhdq", { XM, Vex, EXx }, 0 },
4955 /* PREFIX_VEX_0F6B */
4959 { "vpackssdw", { XM, Vex, EXx }, 0 },
4962 /* PREFIX_VEX_0F6C */
4966 { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
4969 /* PREFIX_VEX_0F6D */
4973 { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
4976 /* PREFIX_VEX_0F6E */
4980 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4983 /* PREFIX_VEX_0F6F */
4986 { "vmovdqu", { XM, EXx }, 0 },
4987 { "vmovdqa", { XM, EXx }, 0 },
4990 /* PREFIX_VEX_0F70 */
4993 { "vpshufhw", { XM, EXx, Ib }, 0 },
4994 { "vpshufd", { XM, EXx, Ib }, 0 },
4995 { "vpshuflw", { XM, EXx, Ib }, 0 },
4998 /* PREFIX_VEX_0F71_REG_2 */
5002 { "vpsrlw", { Vex, XS, Ib }, 0 },
5005 /* PREFIX_VEX_0F71_REG_4 */
5009 { "vpsraw", { Vex, XS, Ib }, 0 },
5012 /* PREFIX_VEX_0F71_REG_6 */
5016 { "vpsllw", { Vex, XS, Ib }, 0 },
5019 /* PREFIX_VEX_0F72_REG_2 */
5023 { "vpsrld", { Vex, XS, Ib }, 0 },
5026 /* PREFIX_VEX_0F72_REG_4 */
5030 { "vpsrad", { Vex, XS, Ib }, 0 },
5033 /* PREFIX_VEX_0F72_REG_6 */
5037 { "vpslld", { Vex, XS, Ib }, 0 },
5040 /* PREFIX_VEX_0F73_REG_2 */
5044 { "vpsrlq", { Vex, XS, Ib }, 0 },
5047 /* PREFIX_VEX_0F73_REG_3 */
5051 { "vpsrldq", { Vex, XS, Ib }, 0 },
5054 /* PREFIX_VEX_0F73_REG_6 */
5058 { "vpsllq", { Vex, XS, Ib }, 0 },
5061 /* PREFIX_VEX_0F73_REG_7 */
5065 { "vpslldq", { Vex, XS, Ib }, 0 },
5068 /* PREFIX_VEX_0F74 */
5072 { "vpcmpeqb", { XM, Vex, EXx }, 0 },
5075 /* PREFIX_VEX_0F75 */
5079 { "vpcmpeqw", { XM, Vex, EXx }, 0 },
5082 /* PREFIX_VEX_0F76 */
5086 { "vpcmpeqd", { XM, Vex, EXx }, 0 },
5089 /* PREFIX_VEX_0F77 */
5091 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5094 /* PREFIX_VEX_0F7C */
5098 { "vhaddpd", { XM, Vex, EXx }, 0 },
5099 { "vhaddps", { XM, Vex, EXx }, 0 },
5102 /* PREFIX_VEX_0F7D */
5106 { "vhsubpd", { XM, Vex, EXx }, 0 },
5107 { "vhsubps", { XM, Vex, EXx }, 0 },
5110 /* PREFIX_VEX_0F7E */
5113 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5114 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5117 /* PREFIX_VEX_0F7F */
5120 { "vmovdqu", { EXxS, XM }, 0 },
5121 { "vmovdqa", { EXxS, XM }, 0 },
5124 /* PREFIX_VEX_0F90 */
5126 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5128 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5131 /* PREFIX_VEX_0F91 */
5133 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5135 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5138 /* PREFIX_VEX_0F92 */
5140 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5142 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5143 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5146 /* PREFIX_VEX_0F93 */
5148 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5150 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5151 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5154 /* PREFIX_VEX_0F98 */
5156 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5158 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5161 /* PREFIX_VEX_0F99 */
5163 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5165 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5168 /* PREFIX_VEX_0FC2 */
5170 { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
5171 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5172 { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
5173 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5176 /* PREFIX_VEX_0FC4 */
5180 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5183 /* PREFIX_VEX_0FC5 */
5187 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5190 /* PREFIX_VEX_0FD0 */
5194 { "vaddsubpd", { XM, Vex, EXx }, 0 },
5195 { "vaddsubps", { XM, Vex, EXx }, 0 },
5198 /* PREFIX_VEX_0FD1 */
5202 { "vpsrlw", { XM, Vex, EXxmm }, 0 },
5205 /* PREFIX_VEX_0FD2 */
5209 { "vpsrld", { XM, Vex, EXxmm }, 0 },
5212 /* PREFIX_VEX_0FD3 */
5216 { "vpsrlq", { XM, Vex, EXxmm }, 0 },
5219 /* PREFIX_VEX_0FD4 */
5223 { "vpaddq", { XM, Vex, EXx }, 0 },
5226 /* PREFIX_VEX_0FD5 */
5230 { "vpmullw", { XM, Vex, EXx }, 0 },
5233 /* PREFIX_VEX_0FD6 */
5237 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5240 /* PREFIX_VEX_0FD7 */
5244 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5247 /* PREFIX_VEX_0FD8 */
5251 { "vpsubusb", { XM, Vex, EXx }, 0 },
5254 /* PREFIX_VEX_0FD9 */
5258 { "vpsubusw", { XM, Vex, EXx }, 0 },
5261 /* PREFIX_VEX_0FDA */
5265 { "vpminub", { XM, Vex, EXx }, 0 },
5268 /* PREFIX_VEX_0FDB */
5272 { "vpand", { XM, Vex, EXx }, 0 },
5275 /* PREFIX_VEX_0FDC */
5279 { "vpaddusb", { XM, Vex, EXx }, 0 },
5282 /* PREFIX_VEX_0FDD */
5286 { "vpaddusw", { XM, Vex, EXx }, 0 },
5289 /* PREFIX_VEX_0FDE */
5293 { "vpmaxub", { XM, Vex, EXx }, 0 },
5296 /* PREFIX_VEX_0FDF */
5300 { "vpandn", { XM, Vex, EXx }, 0 },
5303 /* PREFIX_VEX_0FE0 */
5307 { "vpavgb", { XM, Vex, EXx }, 0 },
5310 /* PREFIX_VEX_0FE1 */
5314 { "vpsraw", { XM, Vex, EXxmm }, 0 },
5317 /* PREFIX_VEX_0FE2 */
5321 { "vpsrad", { XM, Vex, EXxmm }, 0 },
5324 /* PREFIX_VEX_0FE3 */
5328 { "vpavgw", { XM, Vex, EXx }, 0 },
5331 /* PREFIX_VEX_0FE4 */
5335 { "vpmulhuw", { XM, Vex, EXx }, 0 },
5338 /* PREFIX_VEX_0FE5 */
5342 { "vpmulhw", { XM, Vex, EXx }, 0 },
5345 /* PREFIX_VEX_0FE6 */
5348 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
5349 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
5350 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
5353 /* PREFIX_VEX_0FE7 */
5357 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5360 /* PREFIX_VEX_0FE8 */
5364 { "vpsubsb", { XM, Vex, EXx }, 0 },
5367 /* PREFIX_VEX_0FE9 */
5371 { "vpsubsw", { XM, Vex, EXx }, 0 },
5374 /* PREFIX_VEX_0FEA */
5378 { "vpminsw", { XM, Vex, EXx }, 0 },
5381 /* PREFIX_VEX_0FEB */
5385 { "vpor", { XM, Vex, EXx }, 0 },
5388 /* PREFIX_VEX_0FEC */
5392 { "vpaddsb", { XM, Vex, EXx }, 0 },
5395 /* PREFIX_VEX_0FED */
5399 { "vpaddsw", { XM, Vex, EXx }, 0 },
5402 /* PREFIX_VEX_0FEE */
5406 { "vpmaxsw", { XM, Vex, EXx }, 0 },
5409 /* PREFIX_VEX_0FEF */
5413 { "vpxor", { XM, Vex, EXx }, 0 },
5416 /* PREFIX_VEX_0FF0 */
5421 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5424 /* PREFIX_VEX_0FF1 */
5428 { "vpsllw", { XM, Vex, EXxmm }, 0 },
5431 /* PREFIX_VEX_0FF2 */
5435 { "vpslld", { XM, Vex, EXxmm }, 0 },
5438 /* PREFIX_VEX_0FF3 */
5442 { "vpsllq", { XM, Vex, EXxmm }, 0 },
5445 /* PREFIX_VEX_0FF4 */
5449 { "vpmuludq", { XM, Vex, EXx }, 0 },
5452 /* PREFIX_VEX_0FF5 */
5456 { "vpmaddwd", { XM, Vex, EXx }, 0 },
5459 /* PREFIX_VEX_0FF6 */
5463 { "vpsadbw", { XM, Vex, EXx }, 0 },
5466 /* PREFIX_VEX_0FF7 */
5470 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5473 /* PREFIX_VEX_0FF8 */
5477 { "vpsubb", { XM, Vex, EXx }, 0 },
5480 /* PREFIX_VEX_0FF9 */
5484 { "vpsubw", { XM, Vex, EXx }, 0 },
5487 /* PREFIX_VEX_0FFA */
5491 { "vpsubd", { XM, Vex, EXx }, 0 },
5494 /* PREFIX_VEX_0FFB */
5498 { "vpsubq", { XM, Vex, EXx }, 0 },
5501 /* PREFIX_VEX_0FFC */
5505 { "vpaddb", { XM, Vex, EXx }, 0 },
5508 /* PREFIX_VEX_0FFD */
5512 { "vpaddw", { XM, Vex, EXx }, 0 },
5515 /* PREFIX_VEX_0FFE */
5519 { "vpaddd", { XM, Vex, EXx }, 0 },
5522 /* PREFIX_VEX_0F3800 */
5526 { "vpshufb", { XM, Vex, EXx }, 0 },
5529 /* PREFIX_VEX_0F3801 */
5533 { "vphaddw", { XM, Vex, EXx }, 0 },
5536 /* PREFIX_VEX_0F3802 */
5540 { "vphaddd", { XM, Vex, EXx }, 0 },
5543 /* PREFIX_VEX_0F3803 */
5547 { "vphaddsw", { XM, Vex, EXx }, 0 },
5550 /* PREFIX_VEX_0F3804 */
5554 { "vpmaddubsw", { XM, Vex, EXx }, 0 },
5557 /* PREFIX_VEX_0F3805 */
5561 { "vphsubw", { XM, Vex, EXx }, 0 },
5564 /* PREFIX_VEX_0F3806 */
5568 { "vphsubd", { XM, Vex, EXx }, 0 },
5571 /* PREFIX_VEX_0F3807 */
5575 { "vphsubsw", { XM, Vex, EXx }, 0 },
5578 /* PREFIX_VEX_0F3808 */
5582 { "vpsignb", { XM, Vex, EXx }, 0 },
5585 /* PREFIX_VEX_0F3809 */
5589 { "vpsignw", { XM, Vex, EXx }, 0 },
5592 /* PREFIX_VEX_0F380A */
5596 { "vpsignd", { XM, Vex, EXx }, 0 },
5599 /* PREFIX_VEX_0F380B */
5603 { "vpmulhrsw", { XM, Vex, EXx }, 0 },
5606 /* PREFIX_VEX_0F380C */
5610 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5613 /* PREFIX_VEX_0F380D */
5617 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5620 /* PREFIX_VEX_0F380E */
5624 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5627 /* PREFIX_VEX_0F380F */
5631 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5634 /* PREFIX_VEX_0F3813 */
5638 { "vcvtph2ps", { XM, EXxmmq }, 0 },
5641 /* PREFIX_VEX_0F3816 */
5645 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5648 /* PREFIX_VEX_0F3817 */
5652 { "vptest", { XM, EXx }, 0 },
5655 /* PREFIX_VEX_0F3818 */
5659 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5662 /* PREFIX_VEX_0F3819 */
5666 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5669 /* PREFIX_VEX_0F381A */
5673 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5676 /* PREFIX_VEX_0F381C */
5680 { "vpabsb", { XM, EXx }, 0 },
5683 /* PREFIX_VEX_0F381D */
5687 { "vpabsw", { XM, EXx }, 0 },
5690 /* PREFIX_VEX_0F381E */
5694 { "vpabsd", { XM, EXx }, 0 },
5697 /* PREFIX_VEX_0F3820 */
5701 { "vpmovsxbw", { XM, EXxmmq }, 0 },
5704 /* PREFIX_VEX_0F3821 */
5708 { "vpmovsxbd", { XM, EXxmmqd }, 0 },
5711 /* PREFIX_VEX_0F3822 */
5715 { "vpmovsxbq", { XM, EXxmmdw }, 0 },
5718 /* PREFIX_VEX_0F3823 */
5722 { "vpmovsxwd", { XM, EXxmmq }, 0 },
5725 /* PREFIX_VEX_0F3824 */
5729 { "vpmovsxwq", { XM, EXxmmqd }, 0 },
5732 /* PREFIX_VEX_0F3825 */
5736 { "vpmovsxdq", { XM, EXxmmq }, 0 },
5739 /* PREFIX_VEX_0F3828 */
5743 { "vpmuldq", { XM, Vex, EXx }, 0 },
5746 /* PREFIX_VEX_0F3829 */
5750 { "vpcmpeqq", { XM, Vex, EXx }, 0 },
5753 /* PREFIX_VEX_0F382A */
5757 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5760 /* PREFIX_VEX_0F382B */
5764 { "vpackusdw", { XM, Vex, EXx }, 0 },
5767 /* PREFIX_VEX_0F382C */
5771 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5774 /* PREFIX_VEX_0F382D */
5778 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5781 /* PREFIX_VEX_0F382E */
5785 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5788 /* PREFIX_VEX_0F382F */
5792 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5795 /* PREFIX_VEX_0F3830 */
5799 { "vpmovzxbw", { XM, EXxmmq }, 0 },
5802 /* PREFIX_VEX_0F3831 */
5806 { "vpmovzxbd", { XM, EXxmmqd }, 0 },
5809 /* PREFIX_VEX_0F3832 */
5813 { "vpmovzxbq", { XM, EXxmmdw }, 0 },
5816 /* PREFIX_VEX_0F3833 */
5820 { "vpmovzxwd", { XM, EXxmmq }, 0 },
5823 /* PREFIX_VEX_0F3834 */
5827 { "vpmovzxwq", { XM, EXxmmqd }, 0 },
5830 /* PREFIX_VEX_0F3835 */
5834 { "vpmovzxdq", { XM, EXxmmq }, 0 },
5837 /* PREFIX_VEX_0F3836 */
5841 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5844 /* PREFIX_VEX_0F3837 */
5848 { "vpcmpgtq", { XM, Vex, EXx }, 0 },
5851 /* PREFIX_VEX_0F3838 */
5855 { "vpminsb", { XM, Vex, EXx }, 0 },
5858 /* PREFIX_VEX_0F3839 */
5862 { "vpminsd", { XM, Vex, EXx }, 0 },
5865 /* PREFIX_VEX_0F383A */
5869 { "vpminuw", { XM, Vex, EXx }, 0 },
5872 /* PREFIX_VEX_0F383B */
5876 { "vpminud", { XM, Vex, EXx }, 0 },
5879 /* PREFIX_VEX_0F383C */
5883 { "vpmaxsb", { XM, Vex, EXx }, 0 },
5886 /* PREFIX_VEX_0F383D */
5890 { "vpmaxsd", { XM, Vex, EXx }, 0 },
5893 /* PREFIX_VEX_0F383E */
5897 { "vpmaxuw", { XM, Vex, EXx }, 0 },
5900 /* PREFIX_VEX_0F383F */
5904 { "vpmaxud", { XM, Vex, EXx }, 0 },
5907 /* PREFIX_VEX_0F3840 */
5911 { "vpmulld", { XM, Vex, EXx }, 0 },
5914 /* PREFIX_VEX_0F3841 */
5918 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5921 /* PREFIX_VEX_0F3845 */
5925 { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5928 /* PREFIX_VEX_0F3846 */
5932 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5935 /* PREFIX_VEX_0F3847 */
5939 { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5942 /* PREFIX_VEX_0F3858 */
5946 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5949 /* PREFIX_VEX_0F3859 */
5953 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5956 /* PREFIX_VEX_0F385A */
5960 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5963 /* PREFIX_VEX_0F3878 */
5967 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5970 /* PREFIX_VEX_0F3879 */
5974 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5977 /* PREFIX_VEX_0F388C */
5981 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5984 /* PREFIX_VEX_0F388E */
5988 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5991 /* PREFIX_VEX_0F3890 */
5995 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5998 /* PREFIX_VEX_0F3891 */
6002 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6005 /* PREFIX_VEX_0F3892 */
6009 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6012 /* PREFIX_VEX_0F3893 */
6016 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6019 /* PREFIX_VEX_0F3896 */
6023 { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6026 /* PREFIX_VEX_0F3897 */
6030 { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6033 /* PREFIX_VEX_0F3898 */
6037 { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6040 /* PREFIX_VEX_0F3899 */
6044 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6047 /* PREFIX_VEX_0F389A */
6051 { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6054 /* PREFIX_VEX_0F389B */
6058 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6061 /* PREFIX_VEX_0F389C */
6065 { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6068 /* PREFIX_VEX_0F389D */
6072 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6075 /* PREFIX_VEX_0F389E */
6079 { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6082 /* PREFIX_VEX_0F389F */
6086 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6089 /* PREFIX_VEX_0F38A6 */
6093 { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6097 /* PREFIX_VEX_0F38A7 */
6101 { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6104 /* PREFIX_VEX_0F38A8 */
6108 { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6111 /* PREFIX_VEX_0F38A9 */
6115 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6118 /* PREFIX_VEX_0F38AA */
6122 { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6125 /* PREFIX_VEX_0F38AB */
6129 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6132 /* PREFIX_VEX_0F38AC */
6136 { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6139 /* PREFIX_VEX_0F38AD */
6143 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6146 /* PREFIX_VEX_0F38AE */
6150 { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6153 /* PREFIX_VEX_0F38AF */
6157 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6160 /* PREFIX_VEX_0F38B6 */
6164 { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6167 /* PREFIX_VEX_0F38B7 */
6171 { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6174 /* PREFIX_VEX_0F38B8 */
6178 { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6181 /* PREFIX_VEX_0F38B9 */
6185 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6188 /* PREFIX_VEX_0F38BA */
6192 { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6195 /* PREFIX_VEX_0F38BB */
6199 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6202 /* PREFIX_VEX_0F38BC */
6206 { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6209 /* PREFIX_VEX_0F38BD */
6213 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6216 /* PREFIX_VEX_0F38BE */
6220 { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6223 /* PREFIX_VEX_0F38BF */
6227 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6230 /* PREFIX_VEX_0F38CF */
6234 { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6237 /* PREFIX_VEX_0F38DB */
6241 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6244 /* PREFIX_VEX_0F38DC */
6248 { "vaesenc", { XM, Vex, EXx }, 0 },
6251 /* PREFIX_VEX_0F38DD */
6255 { "vaesenclast", { XM, Vex, EXx }, 0 },
6258 /* PREFIX_VEX_0F38DE */
6262 { "vaesdec", { XM, Vex, EXx }, 0 },
6265 /* PREFIX_VEX_0F38DF */
6269 { "vaesdeclast", { XM, Vex, EXx }, 0 },
6272 /* PREFIX_VEX_0F38F2 */
6274 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6277 /* PREFIX_VEX_0F38F3_REG_1 */
6279 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6282 /* PREFIX_VEX_0F38F3_REG_2 */
6284 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6287 /* PREFIX_VEX_0F38F3_REG_3 */
6289 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6292 /* PREFIX_VEX_0F38F5 */
6294 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6295 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6297 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6300 /* PREFIX_VEX_0F38F6 */
6305 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6308 /* PREFIX_VEX_0F38F7 */
6310 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6311 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6312 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6313 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6316 /* PREFIX_VEX_0F3A00 */
6320 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6323 /* PREFIX_VEX_0F3A01 */
6327 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6330 /* PREFIX_VEX_0F3A02 */
6334 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6337 /* PREFIX_VEX_0F3A04 */
6341 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6344 /* PREFIX_VEX_0F3A05 */
6348 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6351 /* PREFIX_VEX_0F3A06 */
6355 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6358 /* PREFIX_VEX_0F3A08 */
6362 { "vroundps", { XM, EXx, Ib }, 0 },
6365 /* PREFIX_VEX_0F3A09 */
6369 { "vroundpd", { XM, EXx, Ib }, 0 },
6372 /* PREFIX_VEX_0F3A0A */
6376 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6379 /* PREFIX_VEX_0F3A0B */
6383 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6386 /* PREFIX_VEX_0F3A0C */
6390 { "vblendps", { XM, Vex, EXx, Ib }, 0 },
6393 /* PREFIX_VEX_0F3A0D */
6397 { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
6400 /* PREFIX_VEX_0F3A0E */
6404 { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
6407 /* PREFIX_VEX_0F3A0F */
6411 { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
6414 /* PREFIX_VEX_0F3A14 */
6418 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6421 /* PREFIX_VEX_0F3A15 */
6425 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6428 /* PREFIX_VEX_0F3A16 */
6432 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6435 /* PREFIX_VEX_0F3A17 */
6439 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6442 /* PREFIX_VEX_0F3A18 */
6446 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6449 /* PREFIX_VEX_0F3A19 */
6453 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6456 /* PREFIX_VEX_0F3A1D */
6460 { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6463 /* PREFIX_VEX_0F3A20 */
6467 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6470 /* PREFIX_VEX_0F3A21 */
6474 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6477 /* PREFIX_VEX_0F3A22 */
6481 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6484 /* PREFIX_VEX_0F3A30 */
6488 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6491 /* PREFIX_VEX_0F3A31 */
6495 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6498 /* PREFIX_VEX_0F3A32 */
6502 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6505 /* PREFIX_VEX_0F3A33 */
6509 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6512 /* PREFIX_VEX_0F3A38 */
6516 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6519 /* PREFIX_VEX_0F3A39 */
6523 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6526 /* PREFIX_VEX_0F3A40 */
6530 { "vdpps", { XM, Vex, EXx, Ib }, 0 },
6533 /* PREFIX_VEX_0F3A41 */
6537 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6540 /* PREFIX_VEX_0F3A42 */
6544 { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
6547 /* PREFIX_VEX_0F3A44 */
6551 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 },
6554 /* PREFIX_VEX_0F3A46 */
6558 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6561 /* PREFIX_VEX_0F3A48 */
6565 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6568 /* PREFIX_VEX_0F3A49 */
6572 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6575 /* PREFIX_VEX_0F3A4A */
6579 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6582 /* PREFIX_VEX_0F3A4B */
6586 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6589 /* PREFIX_VEX_0F3A4C */
6593 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6596 /* PREFIX_VEX_0F3A5C */
6600 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6603 /* PREFIX_VEX_0F3A5D */
6607 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6610 /* PREFIX_VEX_0F3A5E */
6614 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6617 /* PREFIX_VEX_0F3A5F */
6621 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6624 /* PREFIX_VEX_0F3A60 */
6628 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6632 /* PREFIX_VEX_0F3A61 */
6636 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6639 /* PREFIX_VEX_0F3A62 */
6643 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6646 /* PREFIX_VEX_0F3A63 */
6650 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6653 /* PREFIX_VEX_0F3A68 */
6657 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6660 /* PREFIX_VEX_0F3A69 */
6664 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6667 /* PREFIX_VEX_0F3A6A */
6671 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6674 /* PREFIX_VEX_0F3A6B */
6678 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6681 /* PREFIX_VEX_0F3A6C */
6685 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6688 /* PREFIX_VEX_0F3A6D */
6692 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6695 /* PREFIX_VEX_0F3A6E */
6699 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6702 /* PREFIX_VEX_0F3A6F */
6706 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6709 /* PREFIX_VEX_0F3A78 */
6713 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6716 /* PREFIX_VEX_0F3A79 */
6720 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6723 /* PREFIX_VEX_0F3A7A */
6727 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6730 /* PREFIX_VEX_0F3A7B */
6734 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6737 /* PREFIX_VEX_0F3A7C */
6741 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6745 /* PREFIX_VEX_0F3A7D */
6749 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6752 /* PREFIX_VEX_0F3A7E */
6756 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6759 /* PREFIX_VEX_0F3A7F */
6763 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6766 /* PREFIX_VEX_0F3ACE */
6770 { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6773 /* PREFIX_VEX_0F3ACF */
6777 { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6780 /* PREFIX_VEX_0F3ADF */
6784 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6787 /* PREFIX_VEX_0F3AF0 */
6792 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6795 #include "i386-dis-evex-prefix.h"
6798 static const struct dis386 x86_64_table[][2] = {
6801 { "pushP", { es }, 0 },
6806 { "popP", { es }, 0 },
6811 { "pushP", { cs }, 0 },
6816 { "pushP", { ss }, 0 },
6821 { "popP", { ss }, 0 },
6826 { "pushP", { ds }, 0 },
6831 { "popP", { ds }, 0 },
6836 { "daa", { XX }, 0 },
6841 { "das", { XX }, 0 },
6846 { "aaa", { XX }, 0 },
6851 { "aas", { XX }, 0 },
6856 { "pushaP", { XX }, 0 },
6861 { "popaP", { XX }, 0 },
6866 { MOD_TABLE (MOD_62_32BIT) },
6867 { EVEX_TABLE (EVEX_0F) },
6872 { "arpl", { Ew, Gw }, 0 },
6873 { "movs{lq|xd}", { Gv, Ed }, 0 },
6878 { "ins{R|}", { Yzr, indirDX }, 0 },
6879 { "ins{G|}", { Yzr, indirDX }, 0 },
6884 { "outs{R|}", { indirDXr, Xz }, 0 },
6885 { "outs{G|}", { indirDXr, Xz }, 0 },
6890 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6891 { REG_TABLE (REG_80) },
6896 { "Jcall{T|}", { Ap }, 0 },
6901 { MOD_TABLE (MOD_C4_32BIT) },
6902 { VEX_C4_TABLE (VEX_0F) },
6907 { MOD_TABLE (MOD_C5_32BIT) },
6908 { VEX_C5_TABLE (VEX_0F) },
6913 { "into", { XX }, 0 },
6918 { "aam", { Ib }, 0 },
6923 { "aad", { Ib }, 0 },
6928 { "callP", { Jv, BND }, 0 },
6929 { "call@", { Jv, BND }, 0 }
6934 { "jmpP", { Jv, BND }, 0 },
6935 { "jmp@", { Jv, BND }, 0 }
6940 { "Jjmp{T|}", { Ap }, 0 },
6943 /* X86_64_0F01_REG_0 */
6945 { "sgdt{Q|IQ}", { M }, 0 },
6946 { "sgdt", { M }, 0 },
6949 /* X86_64_0F01_REG_1 */
6951 { "sidt{Q|IQ}", { M }, 0 },
6952 { "sidt", { M }, 0 },
6955 /* X86_64_0F01_REG_2 */
6957 { "lgdt{Q|Q}", { M }, 0 },
6958 { "lgdt", { M }, 0 },
6961 /* X86_64_0F01_REG_3 */
6963 { "lidt{Q|Q}", { M }, 0 },
6964 { "lidt", { M }, 0 },
6968 static const struct dis386 three_byte_table[][256] = {
6970 /* THREE_BYTE_0F38 */
6973 { "pshufb", { MX, EM }, PREFIX_OPCODE },
6974 { "phaddw", { MX, EM }, PREFIX_OPCODE },
6975 { "phaddd", { MX, EM }, PREFIX_OPCODE },
6976 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
6977 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
6978 { "phsubw", { MX, EM }, PREFIX_OPCODE },
6979 { "phsubd", { MX, EM }, PREFIX_OPCODE },
6980 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
6982 { "psignb", { MX, EM }, PREFIX_OPCODE },
6983 { "psignw", { MX, EM }, PREFIX_OPCODE },
6984 { "psignd", { MX, EM }, PREFIX_OPCODE },
6985 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
6991 { PREFIX_TABLE (PREFIX_0F3810) },
6995 { PREFIX_TABLE (PREFIX_0F3814) },
6996 { PREFIX_TABLE (PREFIX_0F3815) },
6998 { PREFIX_TABLE (PREFIX_0F3817) },
7004 { "pabsb", { MX, EM }, PREFIX_OPCODE },
7005 { "pabsw", { MX, EM }, PREFIX_OPCODE },
7006 { "pabsd", { MX, EM }, PREFIX_OPCODE },
7009 { PREFIX_TABLE (PREFIX_0F3820) },
7010 { PREFIX_TABLE (PREFIX_0F3821) },
7011 { PREFIX_TABLE (PREFIX_0F3822) },
7012 { PREFIX_TABLE (PREFIX_0F3823) },
7013 { PREFIX_TABLE (PREFIX_0F3824) },
7014 { PREFIX_TABLE (PREFIX_0F3825) },
7018 { PREFIX_TABLE (PREFIX_0F3828) },
7019 { PREFIX_TABLE (PREFIX_0F3829) },
7020 { PREFIX_TABLE (PREFIX_0F382A) },
7021 { PREFIX_TABLE (PREFIX_0F382B) },
7027 { PREFIX_TABLE (PREFIX_0F3830) },
7028 { PREFIX_TABLE (PREFIX_0F3831) },
7029 { PREFIX_TABLE (PREFIX_0F3832) },
7030 { PREFIX_TABLE (PREFIX_0F3833) },
7031 { PREFIX_TABLE (PREFIX_0F3834) },
7032 { PREFIX_TABLE (PREFIX_0F3835) },
7034 { PREFIX_TABLE (PREFIX_0F3837) },
7036 { PREFIX_TABLE (PREFIX_0F3838) },
7037 { PREFIX_TABLE (PREFIX_0F3839) },
7038 { PREFIX_TABLE (PREFIX_0F383A) },
7039 { PREFIX_TABLE (PREFIX_0F383B) },
7040 { PREFIX_TABLE (PREFIX_0F383C) },
7041 { PREFIX_TABLE (PREFIX_0F383D) },
7042 { PREFIX_TABLE (PREFIX_0F383E) },
7043 { PREFIX_TABLE (PREFIX_0F383F) },
7045 { PREFIX_TABLE (PREFIX_0F3840) },
7046 { PREFIX_TABLE (PREFIX_0F3841) },
7117 { PREFIX_TABLE (PREFIX_0F3880) },
7118 { PREFIX_TABLE (PREFIX_0F3881) },
7119 { PREFIX_TABLE (PREFIX_0F3882) },
7198 { PREFIX_TABLE (PREFIX_0F38C8) },
7199 { PREFIX_TABLE (PREFIX_0F38C9) },
7200 { PREFIX_TABLE (PREFIX_0F38CA) },
7201 { PREFIX_TABLE (PREFIX_0F38CB) },
7202 { PREFIX_TABLE (PREFIX_0F38CC) },
7203 { PREFIX_TABLE (PREFIX_0F38CD) },
7205 { PREFIX_TABLE (PREFIX_0F38CF) },
7219 { PREFIX_TABLE (PREFIX_0F38DB) },
7220 { PREFIX_TABLE (PREFIX_0F38DC) },
7221 { PREFIX_TABLE (PREFIX_0F38DD) },
7222 { PREFIX_TABLE (PREFIX_0F38DE) },
7223 { PREFIX_TABLE (PREFIX_0F38DF) },
7243 { PREFIX_TABLE (PREFIX_0F38F0) },
7244 { PREFIX_TABLE (PREFIX_0F38F1) },
7248 { PREFIX_TABLE (PREFIX_0F38F5) },
7249 { PREFIX_TABLE (PREFIX_0F38F6) },
7252 { PREFIX_TABLE (PREFIX_0F38F8) },
7253 { PREFIX_TABLE (PREFIX_0F38F9) },
7261 /* THREE_BYTE_0F3A */
7273 { PREFIX_TABLE (PREFIX_0F3A08) },
7274 { PREFIX_TABLE (PREFIX_0F3A09) },
7275 { PREFIX_TABLE (PREFIX_0F3A0A) },
7276 { PREFIX_TABLE (PREFIX_0F3A0B) },
7277 { PREFIX_TABLE (PREFIX_0F3A0C) },
7278 { PREFIX_TABLE (PREFIX_0F3A0D) },
7279 { PREFIX_TABLE (PREFIX_0F3A0E) },
7280 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
7286 { PREFIX_TABLE (PREFIX_0F3A14) },
7287 { PREFIX_TABLE (PREFIX_0F3A15) },
7288 { PREFIX_TABLE (PREFIX_0F3A16) },
7289 { PREFIX_TABLE (PREFIX_0F3A17) },
7300 { PREFIX_TABLE (PREFIX_0F3A20) },
7301 { PREFIX_TABLE (PREFIX_0F3A21) },
7302 { PREFIX_TABLE (PREFIX_0F3A22) },
7336 { PREFIX_TABLE (PREFIX_0F3A40) },
7337 { PREFIX_TABLE (PREFIX_0F3A41) },
7338 { PREFIX_TABLE (PREFIX_0F3A42) },
7340 { PREFIX_TABLE (PREFIX_0F3A44) },
7372 { PREFIX_TABLE (PREFIX_0F3A60) },
7373 { PREFIX_TABLE (PREFIX_0F3A61) },
7374 { PREFIX_TABLE (PREFIX_0F3A62) },
7375 { PREFIX_TABLE (PREFIX_0F3A63) },
7493 { PREFIX_TABLE (PREFIX_0F3ACC) },
7495 { PREFIX_TABLE (PREFIX_0F3ACE) },
7496 { PREFIX_TABLE (PREFIX_0F3ACF) },
7514 { PREFIX_TABLE (PREFIX_0F3ADF) },
7554 static const struct dis386 xop_table[][256] = {
7707 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7708 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7709 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7717 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7718 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7725 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7726 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7727 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7735 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7736 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7740 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7741 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7744 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7762 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7774 { "vprotb", { XM, Vex_2src_1, Ib }, 0 },
7775 { "vprotw", { XM, Vex_2src_1, Ib }, 0 },
7776 { "vprotd", { XM, Vex_2src_1, Ib }, 0 },
7777 { "vprotq", { XM, Vex_2src_1, Ib }, 0 },
7787 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7788 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7789 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7790 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7823 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7824 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7825 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7826 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7850 { REG_TABLE (REG_XOP_TBM_01) },
7851 { REG_TABLE (REG_XOP_TBM_02) },
7869 { REG_TABLE (REG_XOP_LWPCB) },
7993 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7994 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7995 { "vfrczss", { XM, EXd }, 0 },
7996 { "vfrczsd", { XM, EXq }, 0 },
8011 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8012 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8013 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8014 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8015 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8016 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8017 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8018 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8020 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8021 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8022 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8023 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8066 { "vphaddbw", { XM, EXxmm }, 0 },
8067 { "vphaddbd", { XM, EXxmm }, 0 },
8068 { "vphaddbq", { XM, EXxmm }, 0 },
8071 { "vphaddwd", { XM, EXxmm }, 0 },
8072 { "vphaddwq", { XM, EXxmm }, 0 },
8077 { "vphadddq", { XM, EXxmm }, 0 },
8084 { "vphaddubw", { XM, EXxmm }, 0 },
8085 { "vphaddubd", { XM, EXxmm }, 0 },
8086 { "vphaddubq", { XM, EXxmm }, 0 },
8089 { "vphadduwd", { XM, EXxmm }, 0 },
8090 { "vphadduwq", { XM, EXxmm }, 0 },
8095 { "vphaddudq", { XM, EXxmm }, 0 },
8102 { "vphsubbw", { XM, EXxmm }, 0 },
8103 { "vphsubwd", { XM, EXxmm }, 0 },
8104 { "vphsubdq", { XM, EXxmm }, 0 },
8158 { "bextr", { Gv, Ev, Iq }, 0 },
8160 { REG_TABLE (REG_XOP_LWP) },
8430 static const struct dis386 vex_table[][256] = {
8452 { PREFIX_TABLE (PREFIX_VEX_0F10) },
8453 { PREFIX_TABLE (PREFIX_VEX_0F11) },
8454 { PREFIX_TABLE (PREFIX_VEX_0F12) },
8455 { MOD_TABLE (MOD_VEX_0F13) },
8456 { "vunpcklpX", { XM, Vex, EXx }, 0 },
8457 { "vunpckhpX", { XM, Vex, EXx }, 0 },
8458 { PREFIX_TABLE (PREFIX_VEX_0F16) },
8459 { MOD_TABLE (MOD_VEX_0F17) },
8479 { "vmovapX", { XM, EXx }, 0 },
8480 { "vmovapX", { EXxS, XM }, 0 },
8481 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8482 { MOD_TABLE (MOD_VEX_0F2B) },
8483 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8484 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8485 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8486 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8507 { PREFIX_TABLE (PREFIX_VEX_0F41) },
8508 { PREFIX_TABLE (PREFIX_VEX_0F42) },
8510 { PREFIX_TABLE (PREFIX_VEX_0F44) },
8511 { PREFIX_TABLE (PREFIX_VEX_0F45) },
8512 { PREFIX_TABLE (PREFIX_VEX_0F46) },
8513 { PREFIX_TABLE (PREFIX_VEX_0F47) },
8517 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8518 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8524 { MOD_TABLE (MOD_VEX_0F50) },
8525 { PREFIX_TABLE (PREFIX_VEX_0F51) },
8526 { PREFIX_TABLE (PREFIX_VEX_0F52) },
8527 { PREFIX_TABLE (PREFIX_VEX_0F53) },
8528 { "vandpX", { XM, Vex, EXx }, 0 },
8529 { "vandnpX", { XM, Vex, EXx }, 0 },
8530 { "vorpX", { XM, Vex, EXx }, 0 },
8531 { "vxorpX", { XM, Vex, EXx }, 0 },
8533 { PREFIX_TABLE (PREFIX_VEX_0F58) },
8534 { PREFIX_TABLE (PREFIX_VEX_0F59) },
8535 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8536 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8537 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8538 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8539 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8540 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8542 { PREFIX_TABLE (PREFIX_VEX_0F60) },
8543 { PREFIX_TABLE (PREFIX_VEX_0F61) },
8544 { PREFIX_TABLE (PREFIX_VEX_0F62) },
8545 { PREFIX_TABLE (PREFIX_VEX_0F63) },
8546 { PREFIX_TABLE (PREFIX_VEX_0F64) },
8547 { PREFIX_TABLE (PREFIX_VEX_0F65) },
8548 { PREFIX_TABLE (PREFIX_VEX_0F66) },
8549 { PREFIX_TABLE (PREFIX_VEX_0F67) },
8551 { PREFIX_TABLE (PREFIX_VEX_0F68) },
8552 { PREFIX_TABLE (PREFIX_VEX_0F69) },
8553 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8554 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8555 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8556 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8557 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8558 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8560 { PREFIX_TABLE (PREFIX_VEX_0F70) },
8561 { REG_TABLE (REG_VEX_0F71) },
8562 { REG_TABLE (REG_VEX_0F72) },
8563 { REG_TABLE (REG_VEX_0F73) },
8564 { PREFIX_TABLE (PREFIX_VEX_0F74) },
8565 { PREFIX_TABLE (PREFIX_VEX_0F75) },
8566 { PREFIX_TABLE (PREFIX_VEX_0F76) },
8567 { PREFIX_TABLE (PREFIX_VEX_0F77) },
8573 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8574 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8575 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8576 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8596 { PREFIX_TABLE (PREFIX_VEX_0F90) },
8597 { PREFIX_TABLE (PREFIX_VEX_0F91) },
8598 { PREFIX_TABLE (PREFIX_VEX_0F92) },
8599 { PREFIX_TABLE (PREFIX_VEX_0F93) },
8605 { PREFIX_TABLE (PREFIX_VEX_0F98) },
8606 { PREFIX_TABLE (PREFIX_VEX_0F99) },
8629 { REG_TABLE (REG_VEX_0FAE) },
8652 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8654 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8655 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8656 { "vshufpX", { XM, Vex, EXx, Ib }, 0 },
8668 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8669 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8670 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8671 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8672 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8673 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8674 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8675 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8677 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8678 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8679 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8680 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8681 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8682 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8683 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8684 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8686 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8687 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8688 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8689 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8690 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8691 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8692 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8693 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8695 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8696 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8697 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8698 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8699 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8700 { PREFIX_TABLE (PREFIX_VEX_0FED) },
8701 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8702 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8704 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8705 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8706 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8707 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8708 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8709 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8710 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8711 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8713 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8714 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8715 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8716 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8717 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8718 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8719 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8725 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8734 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8735 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8736 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8740 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8741 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8746 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8780 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8781 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8783 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8789 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8790 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8792 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8795 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8797 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8798 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8802 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8803 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8804 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8824 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8825 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8826 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8860 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8861 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8882 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8884 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8896 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8929 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8957 { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8972 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8973 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8974 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8975 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8997 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8998 { REG_TABLE (REG_VEX_0F38F3) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9001 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9002 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9017 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9020 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9022 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9026 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9027 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9028 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9029 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9030 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9031 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9032 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9038 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9048 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9052 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9053 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9054 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9079 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9080 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9088 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9094 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9098 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9099 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9101 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9119 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9120 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9121 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9122 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9124 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9125 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9126 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9127 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9134 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9135 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9136 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9137 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9138 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9139 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9140 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9151 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9152 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9153 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9154 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9155 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9156 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9157 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9158 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9247 { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9248 { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9266 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9286 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9306 #include "i386-dis-evex.h"
9308 static const struct dis386 vex_len_table[][2] = {
9309 /* VEX_LEN_0F12_P_0_M_0 */
9311 { "vmovlps", { XM, Vex128, EXq }, 0 },
9314 /* VEX_LEN_0F12_P_0_M_1 */
9316 { "vmovhlps", { XM, Vex128, EXq }, 0 },
9319 /* VEX_LEN_0F12_P_2 */
9321 { "vmovlpd", { XM, Vex128, EXq }, 0 },
9324 /* VEX_LEN_0F13_M_0 */
9326 { "vmovlpX", { EXq, XM }, 0 },
9329 /* VEX_LEN_0F16_P_0_M_0 */
9331 { "vmovhps", { XM, Vex128, EXq }, 0 },
9334 /* VEX_LEN_0F16_P_0_M_1 */
9336 { "vmovlhps", { XM, Vex128, EXq }, 0 },
9339 /* VEX_LEN_0F16_P_2 */
9341 { "vmovhpd", { XM, Vex128, EXq }, 0 },
9344 /* VEX_LEN_0F17_M_0 */
9346 { "vmovhpX", { EXq, XM }, 0 },
9349 /* VEX_LEN_0F2A_P_1 */
9351 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9352 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9355 /* VEX_LEN_0F2A_P_3 */
9357 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9358 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9361 /* VEX_LEN_0F2C_P_1 */
9363 { "vcvttss2si", { Gv, EXdScalar }, 0 },
9364 { "vcvttss2si", { Gv, EXdScalar }, 0 },
9367 /* VEX_LEN_0F2C_P_3 */
9369 { "vcvttsd2si", { Gv, EXqScalar }, 0 },
9370 { "vcvttsd2si", { Gv, EXqScalar }, 0 },
9373 /* VEX_LEN_0F2D_P_1 */
9375 { "vcvtss2si", { Gv, EXdScalar }, 0 },
9376 { "vcvtss2si", { Gv, EXdScalar }, 0 },
9379 /* VEX_LEN_0F2D_P_3 */
9381 { "vcvtsd2si", { Gv, EXqScalar }, 0 },
9382 { "vcvtsd2si", { Gv, EXqScalar }, 0 },
9385 /* VEX_LEN_0F41_P_0 */
9388 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9390 /* VEX_LEN_0F41_P_2 */
9393 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9395 /* VEX_LEN_0F42_P_0 */
9398 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9400 /* VEX_LEN_0F42_P_2 */
9403 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9405 /* VEX_LEN_0F44_P_0 */
9407 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9409 /* VEX_LEN_0F44_P_2 */
9411 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9413 /* VEX_LEN_0F45_P_0 */
9416 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9418 /* VEX_LEN_0F45_P_2 */
9421 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9423 /* VEX_LEN_0F46_P_0 */
9426 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9428 /* VEX_LEN_0F46_P_2 */
9431 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9433 /* VEX_LEN_0F47_P_0 */
9436 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9438 /* VEX_LEN_0F47_P_2 */
9441 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9443 /* VEX_LEN_0F4A_P_0 */
9446 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9448 /* VEX_LEN_0F4A_P_2 */
9451 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9453 /* VEX_LEN_0F4B_P_0 */
9456 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9458 /* VEX_LEN_0F4B_P_2 */
9461 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9464 /* VEX_LEN_0F6E_P_2 */
9466 { "vmovK", { XMScalar, Edq }, 0 },
9469 /* VEX_LEN_0F77_P_1 */
9471 { "vzeroupper", { XX }, 0 },
9472 { "vzeroall", { XX }, 0 },
9475 /* VEX_LEN_0F7E_P_1 */
9477 { "vmovq", { XMScalar, EXqScalar }, 0 },
9480 /* VEX_LEN_0F7E_P_2 */
9482 { "vmovK", { Edq, XMScalar }, 0 },
9485 /* VEX_LEN_0F90_P_0 */
9487 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9490 /* VEX_LEN_0F90_P_2 */
9492 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9495 /* VEX_LEN_0F91_P_0 */
9497 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9500 /* VEX_LEN_0F91_P_2 */
9502 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9505 /* VEX_LEN_0F92_P_0 */
9507 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9510 /* VEX_LEN_0F92_P_2 */
9512 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9515 /* VEX_LEN_0F92_P_3 */
9517 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9520 /* VEX_LEN_0F93_P_0 */
9522 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9525 /* VEX_LEN_0F93_P_2 */
9527 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9530 /* VEX_LEN_0F93_P_3 */
9532 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9535 /* VEX_LEN_0F98_P_0 */
9537 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9540 /* VEX_LEN_0F98_P_2 */
9542 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9545 /* VEX_LEN_0F99_P_0 */
9547 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9550 /* VEX_LEN_0F99_P_2 */
9552 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9555 /* VEX_LEN_0FAE_R_2_M_0 */
9557 { "vldmxcsr", { Md }, 0 },
9560 /* VEX_LEN_0FAE_R_3_M_0 */
9562 { "vstmxcsr", { Md }, 0 },
9565 /* VEX_LEN_0FC4_P_2 */
9567 { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
9570 /* VEX_LEN_0FC5_P_2 */
9572 { "vpextrw", { Gdq, XS, Ib }, 0 },
9575 /* VEX_LEN_0FD6_P_2 */
9577 { "vmovq", { EXqScalarS, XMScalar }, 0 },
9580 /* VEX_LEN_0FF7_P_2 */
9582 { "vmaskmovdqu", { XM, XS }, 0 },
9585 /* VEX_LEN_0F3816_P_2 */
9588 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9591 /* VEX_LEN_0F3819_P_2 */
9594 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9597 /* VEX_LEN_0F381A_P_2_M_0 */
9600 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9603 /* VEX_LEN_0F3836_P_2 */
9606 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9609 /* VEX_LEN_0F3841_P_2 */
9611 { "vphminposuw", { XM, EXx }, 0 },
9614 /* VEX_LEN_0F385A_P_2_M_0 */
9617 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9620 /* VEX_LEN_0F38DB_P_2 */
9622 { "vaesimc", { XM, EXx }, 0 },
9625 /* VEX_LEN_0F38F2_P_0 */
9627 { "andnS", { Gdq, VexGdq, Edq }, 0 },
9630 /* VEX_LEN_0F38F3_R_1_P_0 */
9632 { "blsrS", { VexGdq, Edq }, 0 },
9635 /* VEX_LEN_0F38F3_R_2_P_0 */
9637 { "blsmskS", { VexGdq, Edq }, 0 },
9640 /* VEX_LEN_0F38F3_R_3_P_0 */
9642 { "blsiS", { VexGdq, Edq }, 0 },
9645 /* VEX_LEN_0F38F5_P_0 */
9647 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
9650 /* VEX_LEN_0F38F5_P_1 */
9652 { "pextS", { Gdq, VexGdq, Edq }, 0 },
9655 /* VEX_LEN_0F38F5_P_3 */
9657 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
9660 /* VEX_LEN_0F38F6_P_3 */
9662 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
9665 /* VEX_LEN_0F38F7_P_0 */
9667 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
9670 /* VEX_LEN_0F38F7_P_1 */
9672 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
9675 /* VEX_LEN_0F38F7_P_2 */
9677 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
9680 /* VEX_LEN_0F38F7_P_3 */
9682 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
9685 /* VEX_LEN_0F3A00_P_2 */
9688 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9691 /* VEX_LEN_0F3A01_P_2 */
9694 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9697 /* VEX_LEN_0F3A06_P_2 */
9700 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9703 /* VEX_LEN_0F3A14_P_2 */
9705 { "vpextrb", { Edqb, XM, Ib }, 0 },
9708 /* VEX_LEN_0F3A15_P_2 */
9710 { "vpextrw", { Edqw, XM, Ib }, 0 },
9713 /* VEX_LEN_0F3A16_P_2 */
9715 { "vpextrK", { Edq, XM, Ib }, 0 },
9718 /* VEX_LEN_0F3A17_P_2 */
9720 { "vextractps", { Edqd, XM, Ib }, 0 },
9723 /* VEX_LEN_0F3A18_P_2 */
9726 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9729 /* VEX_LEN_0F3A19_P_2 */
9732 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9735 /* VEX_LEN_0F3A20_P_2 */
9737 { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
9740 /* VEX_LEN_0F3A21_P_2 */
9742 { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
9745 /* VEX_LEN_0F3A22_P_2 */
9747 { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 },
9750 /* VEX_LEN_0F3A30_P_2 */
9752 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9755 /* VEX_LEN_0F3A31_P_2 */
9757 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9760 /* VEX_LEN_0F3A32_P_2 */
9762 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9765 /* VEX_LEN_0F3A33_P_2 */
9767 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9770 /* VEX_LEN_0F3A38_P_2 */
9773 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9776 /* VEX_LEN_0F3A39_P_2 */
9779 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9782 /* VEX_LEN_0F3A41_P_2 */
9784 { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
9787 /* VEX_LEN_0F3A46_P_2 */
9790 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9793 /* VEX_LEN_0F3A60_P_2 */
9795 { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9798 /* VEX_LEN_0F3A61_P_2 */
9800 { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9803 /* VEX_LEN_0F3A62_P_2 */
9805 { "vpcmpistrm", { XM, EXx, Ib }, 0 },
9808 /* VEX_LEN_0F3A63_P_2 */
9810 { "vpcmpistri", { XM, EXx, Ib }, 0 },
9813 /* VEX_LEN_0F3A6A_P_2 */
9815 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9818 /* VEX_LEN_0F3A6B_P_2 */
9820 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9823 /* VEX_LEN_0F3A6E_P_2 */
9825 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9828 /* VEX_LEN_0F3A6F_P_2 */
9830 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9833 /* VEX_LEN_0F3A7A_P_2 */
9835 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9838 /* VEX_LEN_0F3A7B_P_2 */
9840 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9843 /* VEX_LEN_0F3A7E_P_2 */
9845 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9848 /* VEX_LEN_0F3A7F_P_2 */
9850 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9853 /* VEX_LEN_0F3ADF_P_2 */
9855 { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9858 /* VEX_LEN_0F3AF0_P_3 */
9860 { "rorxS", { Gdq, Edq, Ib }, 0 },
9863 /* VEX_LEN_0FXOP_08_CC */
9865 { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 },
9868 /* VEX_LEN_0FXOP_08_CD */
9870 { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 },
9873 /* VEX_LEN_0FXOP_08_CE */
9875 { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 },
9878 /* VEX_LEN_0FXOP_08_CF */
9880 { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 },
9883 /* VEX_LEN_0FXOP_08_EC */
9885 { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 },
9888 /* VEX_LEN_0FXOP_08_ED */
9890 { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 },
9893 /* VEX_LEN_0FXOP_08_EE */
9895 { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 },
9898 /* VEX_LEN_0FXOP_08_EF */
9900 { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 },
9903 /* VEX_LEN_0FXOP_09_80 */
9905 { "vfrczps", { XM, EXxmm }, 0 },
9906 { "vfrczps", { XM, EXymmq }, 0 },
9909 /* VEX_LEN_0FXOP_09_81 */
9911 { "vfrczpd", { XM, EXxmm }, 0 },
9912 { "vfrczpd", { XM, EXymmq }, 0 },
9916 #include "i386-dis-evex-len.h"
9918 static const struct dis386 vex_w_table[][2] = {
9920 /* VEX_W_0F41_P_0_LEN_1 */
9921 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9922 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9925 /* VEX_W_0F41_P_2_LEN_1 */
9926 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9927 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9930 /* VEX_W_0F42_P_0_LEN_1 */
9931 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9932 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9935 /* VEX_W_0F42_P_2_LEN_1 */
9936 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9937 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9940 /* VEX_W_0F44_P_0_LEN_0 */
9941 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9942 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9945 /* VEX_W_0F44_P_2_LEN_0 */
9946 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9947 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9950 /* VEX_W_0F45_P_0_LEN_1 */
9951 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9952 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9955 /* VEX_W_0F45_P_2_LEN_1 */
9956 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9957 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9960 /* VEX_W_0F46_P_0_LEN_1 */
9961 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9962 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9965 /* VEX_W_0F46_P_2_LEN_1 */
9966 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9967 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9970 /* VEX_W_0F47_P_0_LEN_1 */
9971 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9972 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9975 /* VEX_W_0F47_P_2_LEN_1 */
9976 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9977 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9980 /* VEX_W_0F4A_P_0_LEN_1 */
9981 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9982 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9985 /* VEX_W_0F4A_P_2_LEN_1 */
9986 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9987 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9990 /* VEX_W_0F4B_P_0_LEN_1 */
9991 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9992 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9995 /* VEX_W_0F4B_P_2_LEN_1 */
9996 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9999 /* VEX_W_0F90_P_0_LEN_0 */
10000 { "kmovw", { MaskG, MaskE }, 0 },
10001 { "kmovq", { MaskG, MaskE }, 0 },
10004 /* VEX_W_0F90_P_2_LEN_0 */
10005 { "kmovb", { MaskG, MaskBDE }, 0 },
10006 { "kmovd", { MaskG, MaskBDE }, 0 },
10009 /* VEX_W_0F91_P_0_LEN_0 */
10010 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10011 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10014 /* VEX_W_0F91_P_2_LEN_0 */
10015 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10016 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10019 /* VEX_W_0F92_P_0_LEN_0 */
10020 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10023 /* VEX_W_0F92_P_2_LEN_0 */
10024 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10027 /* VEX_W_0F93_P_0_LEN_0 */
10028 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10031 /* VEX_W_0F93_P_2_LEN_0 */
10032 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10035 /* VEX_W_0F98_P_0_LEN_0 */
10036 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10037 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10040 /* VEX_W_0F98_P_2_LEN_0 */
10041 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10042 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10045 /* VEX_W_0F99_P_0_LEN_0 */
10046 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10047 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10050 /* VEX_W_0F99_P_2_LEN_0 */
10051 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10052 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10055 /* VEX_W_0F380C_P_2 */
10056 { "vpermilps", { XM, Vex, EXx }, 0 },
10059 /* VEX_W_0F380D_P_2 */
10060 { "vpermilpd", { XM, Vex, EXx }, 0 },
10063 /* VEX_W_0F380E_P_2 */
10064 { "vtestps", { XM, EXx }, 0 },
10067 /* VEX_W_0F380F_P_2 */
10068 { "vtestpd", { XM, EXx }, 0 },
10071 /* VEX_W_0F3816_P_2 */
10072 { "vpermps", { XM, Vex, EXx }, 0 },
10075 /* VEX_W_0F3818_P_2 */
10076 { "vbroadcastss", { XM, EXxmm_md }, 0 },
10079 /* VEX_W_0F3819_P_2 */
10080 { "vbroadcastsd", { XM, EXxmm_mq }, 0 },
10083 /* VEX_W_0F381A_P_2_M_0 */
10084 { "vbroadcastf128", { XM, Mxmm }, 0 },
10087 /* VEX_W_0F382C_P_2_M_0 */
10088 { "vmaskmovps", { XM, Vex, Mx }, 0 },
10091 /* VEX_W_0F382D_P_2_M_0 */
10092 { "vmaskmovpd", { XM, Vex, Mx }, 0 },
10095 /* VEX_W_0F382E_P_2_M_0 */
10096 { "vmaskmovps", { Mx, Vex, XM }, 0 },
10099 /* VEX_W_0F382F_P_2_M_0 */
10100 { "vmaskmovpd", { Mx, Vex, XM }, 0 },
10103 /* VEX_W_0F3836_P_2 */
10104 { "vpermd", { XM, Vex, EXx }, 0 },
10107 /* VEX_W_0F3846_P_2 */
10108 { "vpsravd", { XM, Vex, EXx }, 0 },
10111 /* VEX_W_0F3858_P_2 */
10112 { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10115 /* VEX_W_0F3859_P_2 */
10116 { "vpbroadcastq", { XM, EXxmm_mq }, 0 },
10119 /* VEX_W_0F385A_P_2_M_0 */
10120 { "vbroadcasti128", { XM, Mxmm }, 0 },
10123 /* VEX_W_0F3878_P_2 */
10124 { "vpbroadcastb", { XM, EXxmm_mb }, 0 },
10127 /* VEX_W_0F3879_P_2 */
10128 { "vpbroadcastw", { XM, EXxmm_mw }, 0 },
10131 /* VEX_W_0F38CF_P_2 */
10132 { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10135 /* VEX_W_0F3A00_P_2 */
10137 { "vpermq", { XM, EXx, Ib }, 0 },
10140 /* VEX_W_0F3A01_P_2 */
10142 { "vpermpd", { XM, EXx, Ib }, 0 },
10145 /* VEX_W_0F3A02_P_2 */
10146 { "vpblendd", { XM, Vex, EXx, Ib }, 0 },
10149 /* VEX_W_0F3A04_P_2 */
10150 { "vpermilps", { XM, EXx, Ib }, 0 },
10153 /* VEX_W_0F3A05_P_2 */
10154 { "vpermilpd", { XM, EXx, Ib }, 0 },
10157 /* VEX_W_0F3A06_P_2 */
10158 { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 },
10161 /* VEX_W_0F3A18_P_2 */
10162 { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 },
10165 /* VEX_W_0F3A19_P_2 */
10166 { "vextractf128", { EXxmm, XM, Ib }, 0 },
10169 /* VEX_W_0F3A30_P_2_LEN_0 */
10170 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10171 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10174 /* VEX_W_0F3A31_P_2_LEN_0 */
10175 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10176 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10179 /* VEX_W_0F3A32_P_2_LEN_0 */
10180 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10181 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10184 /* VEX_W_0F3A33_P_2_LEN_0 */
10185 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10186 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10189 /* VEX_W_0F3A38_P_2 */
10190 { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 },
10193 /* VEX_W_0F3A39_P_2 */
10194 { "vextracti128", { EXxmm, XM, Ib }, 0 },
10197 /* VEX_W_0F3A46_P_2 */
10198 { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
10201 /* VEX_W_0F3A48_P_2 */
10202 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10203 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10206 /* VEX_W_0F3A49_P_2 */
10207 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10208 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10211 /* VEX_W_0F3A4A_P_2 */
10212 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 },
10215 /* VEX_W_0F3A4B_P_2 */
10216 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 },
10219 /* VEX_W_0F3A4C_P_2 */
10220 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
10223 /* VEX_W_0F3ACE_P_2 */
10225 { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10228 /* VEX_W_0F3ACF_P_2 */
10230 { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 },
10233 #include "i386-dis-evex-w.h"
10236 static const struct dis386 mod_table[][2] = {
10239 { "leaS", { Gv, M }, 0 },
10244 { RM_TABLE (RM_C6_REG_7) },
10249 { RM_TABLE (RM_C7_REG_7) },
10253 { "Jcall^", { indirEp }, 0 },
10257 { "Jjmp^", { indirEp }, 0 },
10260 /* MOD_0F01_REG_0 */
10261 { X86_64_TABLE (X86_64_0F01_REG_0) },
10262 { RM_TABLE (RM_0F01_REG_0) },
10265 /* MOD_0F01_REG_1 */
10266 { X86_64_TABLE (X86_64_0F01_REG_1) },
10267 { RM_TABLE (RM_0F01_REG_1) },
10270 /* MOD_0F01_REG_2 */
10271 { X86_64_TABLE (X86_64_0F01_REG_2) },
10272 { RM_TABLE (RM_0F01_REG_2) },
10275 /* MOD_0F01_REG_3 */
10276 { X86_64_TABLE (X86_64_0F01_REG_3) },
10277 { RM_TABLE (RM_0F01_REG_3) },
10280 /* MOD_0F01_REG_5 */
10281 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
10282 { RM_TABLE (RM_0F01_REG_5) },
10285 /* MOD_0F01_REG_7 */
10286 { "invlpg", { Mb }, 0 },
10287 { RM_TABLE (RM_0F01_REG_7) },
10290 /* MOD_0F12_PREFIX_0 */
10291 { "movlps", { XM, EXq }, PREFIX_OPCODE },
10292 { "movhlps", { XM, EXq }, PREFIX_OPCODE },
10296 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
10299 /* MOD_0F16_PREFIX_0 */
10300 { "movhps", { XM, EXq }, 0 },
10301 { "movlhps", { XM, EXq }, 0 },
10305 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
10308 /* MOD_0F18_REG_0 */
10309 { "prefetchnta", { Mb }, 0 },
10312 /* MOD_0F18_REG_1 */
10313 { "prefetcht0", { Mb }, 0 },
10316 /* MOD_0F18_REG_2 */
10317 { "prefetcht1", { Mb }, 0 },
10320 /* MOD_0F18_REG_3 */
10321 { "prefetcht2", { Mb }, 0 },
10324 /* MOD_0F18_REG_4 */
10325 { "nop/reserved", { Mb }, 0 },
10328 /* MOD_0F18_REG_5 */
10329 { "nop/reserved", { Mb }, 0 },
10332 /* MOD_0F18_REG_6 */
10333 { "nop/reserved", { Mb }, 0 },
10336 /* MOD_0F18_REG_7 */
10337 { "nop/reserved", { Mb }, 0 },
10340 /* MOD_0F1A_PREFIX_0 */
10341 { "bndldx", { Gbnd, Mv_bnd }, 0 },
10342 { "nopQ", { Ev }, 0 },
10345 /* MOD_0F1B_PREFIX_0 */
10346 { "bndstx", { Mv_bnd, Gbnd }, 0 },
10347 { "nopQ", { Ev }, 0 },
10350 /* MOD_0F1B_PREFIX_1 */
10351 { "bndmk", { Gbnd, Mv_bnd }, 0 },
10352 { "nopQ", { Ev }, 0 },
10355 /* MOD_0F1C_PREFIX_0 */
10356 { REG_TABLE (REG_0F1C_MOD_0) },
10357 { "nopQ", { Ev }, 0 },
10360 /* MOD_0F1E_PREFIX_1 */
10361 { "nopQ", { Ev }, 0 },
10362 { REG_TABLE (REG_0F1E_MOD_3) },
10367 { "movL", { Rd, Td }, 0 },
10372 { "movL", { Td, Rd }, 0 },
10375 /* MOD_0F2B_PREFIX_0 */
10376 {"movntps", { Mx, XM }, PREFIX_OPCODE },
10379 /* MOD_0F2B_PREFIX_1 */
10380 {"movntss", { Md, XM }, PREFIX_OPCODE },
10383 /* MOD_0F2B_PREFIX_2 */
10384 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
10387 /* MOD_0F2B_PREFIX_3 */
10388 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
10393 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
10396 /* MOD_0F71_REG_2 */
10398 { "psrlw", { MS, Ib }, 0 },
10401 /* MOD_0F71_REG_4 */
10403 { "psraw", { MS, Ib }, 0 },
10406 /* MOD_0F71_REG_6 */
10408 { "psllw", { MS, Ib }, 0 },
10411 /* MOD_0F72_REG_2 */
10413 { "psrld", { MS, Ib }, 0 },
10416 /* MOD_0F72_REG_4 */
10418 { "psrad", { MS, Ib }, 0 },
10421 /* MOD_0F72_REG_6 */
10423 { "pslld", { MS, Ib }, 0 },
10426 /* MOD_0F73_REG_2 */
10428 { "psrlq", { MS, Ib }, 0 },
10431 /* MOD_0F73_REG_3 */
10433 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10436 /* MOD_0F73_REG_6 */
10438 { "psllq", { MS, Ib }, 0 },
10441 /* MOD_0F73_REG_7 */
10443 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10446 /* MOD_0FAE_REG_0 */
10447 { "fxsave", { FXSAVE }, 0 },
10448 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10451 /* MOD_0FAE_REG_1 */
10452 { "fxrstor", { FXSAVE }, 0 },
10453 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10456 /* MOD_0FAE_REG_2 */
10457 { "ldmxcsr", { Md }, 0 },
10458 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10461 /* MOD_0FAE_REG_3 */
10462 { "stmxcsr", { Md }, 0 },
10463 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10466 /* MOD_0FAE_REG_4 */
10467 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
10468 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
10471 /* MOD_0FAE_REG_5 */
10472 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
10473 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
10476 /* MOD_0FAE_REG_6 */
10477 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
10478 { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
10481 /* MOD_0FAE_REG_7 */
10482 { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
10483 { RM_TABLE (RM_0FAE_REG_7) },
10487 { "lssS", { Gv, Mp }, 0 },
10491 { "lfsS", { Gv, Mp }, 0 },
10495 { "lgsS", { Gv, Mp }, 0 },
10499 { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
10502 /* MOD_0FC7_REG_3 */
10503 { "xrstors", { FXSAVE }, 0 },
10506 /* MOD_0FC7_REG_4 */
10507 { "xsavec", { FXSAVE }, 0 },
10510 /* MOD_0FC7_REG_5 */
10511 { "xsaves", { FXSAVE }, 0 },
10514 /* MOD_0FC7_REG_6 */
10515 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
10516 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
10519 /* MOD_0FC7_REG_7 */
10520 { "vmptrst", { Mq }, 0 },
10521 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
10526 { "pmovmskb", { Gdq, MS }, 0 },
10529 /* MOD_0FE7_PREFIX_2 */
10530 { "movntdq", { Mx, XM }, 0 },
10533 /* MOD_0FF0_PREFIX_3 */
10534 { "lddqu", { XM, M }, 0 },
10537 /* MOD_0F382A_PREFIX_2 */
10538 { "movntdqa", { XM, Mx }, 0 },
10541 /* MOD_0F38F5_PREFIX_2 */
10542 { "wrussK", { M, Gdq }, PREFIX_OPCODE },
10545 /* MOD_0F38F6_PREFIX_0 */
10546 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
10549 /* MOD_0F38F8_PREFIX_1 */
10550 { "enqcmds", { Gva, M }, PREFIX_OPCODE },
10553 /* MOD_0F38F8_PREFIX_2 */
10554 { "movdir64b", { Gva, M }, PREFIX_OPCODE },
10557 /* MOD_0F38F8_PREFIX_3 */
10558 { "enqcmd", { Gva, M }, PREFIX_OPCODE },
10561 /* MOD_0F38F9_PREFIX_0 */
10562 { "movdiri", { Em, Gv }, PREFIX_OPCODE },
10566 { "bound{S|}", { Gv, Ma }, 0 },
10567 { EVEX_TABLE (EVEX_0F) },
10571 { "lesS", { Gv, Mp }, 0 },
10572 { VEX_C4_TABLE (VEX_0F) },
10576 { "ldsS", { Gv, Mp }, 0 },
10577 { VEX_C5_TABLE (VEX_0F) },
10580 /* MOD_VEX_0F12_PREFIX_0 */
10581 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10582 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10586 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10589 /* MOD_VEX_0F16_PREFIX_0 */
10590 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10591 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10595 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10599 { "vmovntpX", { Mx, XM }, 0 },
10602 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10604 { "kandw", { MaskG, MaskVex, MaskR }, 0 },
10607 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10609 { "kandq", { MaskG, MaskVex, MaskR }, 0 },
10612 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10614 { "kandb", { MaskG, MaskVex, MaskR }, 0 },
10617 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10619 { "kandd", { MaskG, MaskVex, MaskR }, 0 },
10622 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10624 { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
10627 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10629 { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
10632 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10634 { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
10637 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10639 { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
10642 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10644 { "knotw", { MaskG, MaskR }, 0 },
10647 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10649 { "knotq", { MaskG, MaskR }, 0 },
10652 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10654 { "knotb", { MaskG, MaskR }, 0 },
10657 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10659 { "knotd", { MaskG, MaskR }, 0 },
10662 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10664 { "korw", { MaskG, MaskVex, MaskR }, 0 },
10667 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10669 { "korq", { MaskG, MaskVex, MaskR }, 0 },
10672 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10674 { "korb", { MaskG, MaskVex, MaskR }, 0 },
10677 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10679 { "kord", { MaskG, MaskVex, MaskR }, 0 },
10682 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10684 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
10687 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10689 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
10692 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10694 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
10697 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10699 { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
10702 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10704 { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
10707 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10709 { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
10712 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10714 { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
10717 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10719 { "kxord", { MaskG, MaskVex, MaskR }, 0 },
10722 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10724 { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
10727 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10729 { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
10732 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10734 { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
10737 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10739 { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
10742 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10744 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
10747 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10749 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
10752 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10754 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
10759 { "vmovmskpX", { Gdq, XS }, 0 },
10762 /* MOD_VEX_0F71_REG_2 */
10764 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10767 /* MOD_VEX_0F71_REG_4 */
10769 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10772 /* MOD_VEX_0F71_REG_6 */
10774 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10777 /* MOD_VEX_0F72_REG_2 */
10779 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10782 /* MOD_VEX_0F72_REG_4 */
10784 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10787 /* MOD_VEX_0F72_REG_6 */
10789 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10792 /* MOD_VEX_0F73_REG_2 */
10794 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10797 /* MOD_VEX_0F73_REG_3 */
10799 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10802 /* MOD_VEX_0F73_REG_6 */
10804 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10807 /* MOD_VEX_0F73_REG_7 */
10809 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10812 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10813 { "kmovw", { Ew, MaskG }, 0 },
10817 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10818 { "kmovq", { Eq, MaskG }, 0 },
10822 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10823 { "kmovb", { Eb, MaskG }, 0 },
10827 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10828 { "kmovd", { Ed, MaskG }, 0 },
10832 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10834 { "kmovw", { MaskG, Rdq }, 0 },
10837 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10839 { "kmovb", { MaskG, Rdq }, 0 },
10842 /* MOD_VEX_0F92_P_3_LEN_0 */
10844 { "kmovK", { MaskG, Rdq }, 0 },
10847 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10849 { "kmovw", { Gdq, MaskR }, 0 },
10852 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10854 { "kmovb", { Gdq, MaskR }, 0 },
10857 /* MOD_VEX_0F93_P_3_LEN_0 */
10859 { "kmovK", { Gdq, MaskR }, 0 },
10862 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10864 { "kortestw", { MaskG, MaskR }, 0 },
10867 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10869 { "kortestq", { MaskG, MaskR }, 0 },
10872 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10874 { "kortestb", { MaskG, MaskR }, 0 },
10877 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10879 { "kortestd", { MaskG, MaskR }, 0 },
10882 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10884 { "ktestw", { MaskG, MaskR }, 0 },
10887 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10889 { "ktestq", { MaskG, MaskR }, 0 },
10892 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10894 { "ktestb", { MaskG, MaskR }, 0 },
10897 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10899 { "ktestd", { MaskG, MaskR }, 0 },
10902 /* MOD_VEX_0FAE_REG_2 */
10903 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10906 /* MOD_VEX_0FAE_REG_3 */
10907 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10910 /* MOD_VEX_0FD7_PREFIX_2 */
10912 { "vpmovmskb", { Gdq, XS }, 0 },
10915 /* MOD_VEX_0FE7_PREFIX_2 */
10916 { "vmovntdq", { Mx, XM }, 0 },
10919 /* MOD_VEX_0FF0_PREFIX_3 */
10920 { "vlddqu", { XM, M }, 0 },
10923 /* MOD_VEX_0F381A_PREFIX_2 */
10924 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10927 /* MOD_VEX_0F382A_PREFIX_2 */
10928 { "vmovntdqa", { XM, Mx }, 0 },
10931 /* MOD_VEX_0F382C_PREFIX_2 */
10932 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10935 /* MOD_VEX_0F382D_PREFIX_2 */
10936 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10939 /* MOD_VEX_0F382E_PREFIX_2 */
10940 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10943 /* MOD_VEX_0F382F_PREFIX_2 */
10944 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10947 /* MOD_VEX_0F385A_PREFIX_2 */
10948 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10951 /* MOD_VEX_0F388C_PREFIX_2 */
10952 { "vpmaskmov%LW", { XM, Vex, Mx }, 0 },
10955 /* MOD_VEX_0F388E_PREFIX_2 */
10956 { "vpmaskmov%LW", { Mx, Vex, XM }, 0 },
10959 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10961 { "kshiftrb", { MaskG, MaskR, Ib }, 0 },
10964 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10966 { "kshiftrw", { MaskG, MaskR, Ib }, 0 },
10969 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10971 { "kshiftrd", { MaskG, MaskR, Ib }, 0 },
10974 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10976 { "kshiftrq", { MaskG, MaskR, Ib }, 0 },
10979 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10981 { "kshiftlb", { MaskG, MaskR, Ib }, 0 },
10984 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10986 { "kshiftlw", { MaskG, MaskR, Ib }, 0 },
10989 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10991 { "kshiftld", { MaskG, MaskR, Ib }, 0 },
10994 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10996 { "kshiftlq", { MaskG, MaskR, Ib }, 0 },
10999 #include "i386-dis-evex-mod.h"
11002 static const struct dis386 rm_table[][8] = {
11005 { "xabort", { Skip_MODRM, Ib }, 0 },
11009 { "xbeginT", { Skip_MODRM, Jv }, 0 },
11012 /* RM_0F01_REG_0 */
11013 { "enclv", { Skip_MODRM }, 0 },
11014 { "vmcall", { Skip_MODRM }, 0 },
11015 { "vmlaunch", { Skip_MODRM }, 0 },
11016 { "vmresume", { Skip_MODRM }, 0 },
11017 { "vmxoff", { Skip_MODRM }, 0 },
11018 { "pconfig", { Skip_MODRM }, 0 },
11021 /* RM_0F01_REG_1 */
11022 { "monitor", { { OP_Monitor, 0 } }, 0 },
11023 { "mwait", { { OP_Mwait, 0 } }, 0 },
11024 { "clac", { Skip_MODRM }, 0 },
11025 { "stac", { Skip_MODRM }, 0 },
11029 { "encls", { Skip_MODRM }, 0 },
11032 /* RM_0F01_REG_2 */
11033 { "xgetbv", { Skip_MODRM }, 0 },
11034 { "xsetbv", { Skip_MODRM }, 0 },
11037 { "vmfunc", { Skip_MODRM }, 0 },
11038 { "xend", { Skip_MODRM }, 0 },
11039 { "xtest", { Skip_MODRM }, 0 },
11040 { "enclu", { Skip_MODRM }, 0 },
11043 /* RM_0F01_REG_3 */
11044 { "vmrun", { Skip_MODRM }, 0 },
11045 { "vmmcall", { Skip_MODRM }, 0 },
11046 { "vmload", { Skip_MODRM }, 0 },
11047 { "vmsave", { Skip_MODRM }, 0 },
11048 { "stgi", { Skip_MODRM }, 0 },
11049 { "clgi", { Skip_MODRM }, 0 },
11050 { "skinit", { Skip_MODRM }, 0 },
11051 { "invlpga", { Skip_MODRM }, 0 },
11054 /* RM_0F01_REG_5 */
11055 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
11057 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
11061 { "rdpkru", { Skip_MODRM }, 0 },
11062 { "wrpkru", { Skip_MODRM }, 0 },
11065 /* RM_0F01_REG_7 */
11066 { "swapgs", { Skip_MODRM }, 0 },
11067 { "rdtscp", { Skip_MODRM }, 0 },
11068 { "monitorx", { { OP_Monitor, 0 } }, 0 },
11069 { "mwaitx", { { OP_Mwaitx, 0 } }, 0 },
11070 { "clzero", { Skip_MODRM }, 0 },
11073 /* RM_0F1E_MOD_3_REG_7 */
11074 { "nopQ", { Ev }, 0 },
11075 { "nopQ", { Ev }, 0 },
11076 { "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
11077 { "endbr32", { Skip_MODRM }, PREFIX_OPCODE },
11078 { "nopQ", { Ev }, 0 },
11079 { "nopQ", { Ev }, 0 },
11080 { "nopQ", { Ev }, 0 },
11081 { "nopQ", { Ev }, 0 },
11084 /* RM_0FAE_REG_6 */
11085 { "mfence", { Skip_MODRM }, 0 },
11088 /* RM_0FAE_REG_7 */
11089 { "sfence", { Skip_MODRM }, 0 },
11094 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11096 /* We use the high bit to indicate different name for the same
11098 #define REP_PREFIX (0xf3 | 0x100)
11099 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11100 #define XRELEASE_PREFIX (0xf3 | 0x400)
11101 #define BND_PREFIX (0xf2 | 0x400)
11102 #define NOTRACK_PREFIX (0x3e | 0x100)
11107 int newrex, i, length;
11113 last_lock_prefix = -1;
11114 last_repz_prefix = -1;
11115 last_repnz_prefix = -1;
11116 last_data_prefix = -1;
11117 last_addr_prefix = -1;
11118 last_rex_prefix = -1;
11119 last_seg_prefix = -1;
11121 active_seg_prefix = 0;
11122 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11123 all_prefixes[i] = 0;
11126 /* The maximum instruction length is 15bytes. */
11127 while (length < MAX_CODE_LENGTH - 1)
11129 FETCH_DATA (the_info, codep + 1);
11133 /* REX prefixes family. */
11150 if (address_mode == mode_64bit)
11154 last_rex_prefix = i;
11157 prefixes |= PREFIX_REPZ;
11158 last_repz_prefix = i;
11161 prefixes |= PREFIX_REPNZ;
11162 last_repnz_prefix = i;
11165 prefixes |= PREFIX_LOCK;
11166 last_lock_prefix = i;
11169 prefixes |= PREFIX_CS;
11170 last_seg_prefix = i;
11171 active_seg_prefix = PREFIX_CS;
11174 prefixes |= PREFIX_SS;
11175 last_seg_prefix = i;
11176 active_seg_prefix = PREFIX_SS;
11179 prefixes |= PREFIX_DS;
11180 last_seg_prefix = i;
11181 active_seg_prefix = PREFIX_DS;
11184 prefixes |= PREFIX_ES;
11185 last_seg_prefix = i;
11186 active_seg_prefix = PREFIX_ES;
11189 prefixes |= PREFIX_FS;
11190 last_seg_prefix = i;
11191 active_seg_prefix = PREFIX_FS;
11194 prefixes |= PREFIX_GS;
11195 last_seg_prefix = i;
11196 active_seg_prefix = PREFIX_GS;
11199 prefixes |= PREFIX_DATA;
11200 last_data_prefix = i;
11203 prefixes |= PREFIX_ADDR;
11204 last_addr_prefix = i;
11207 /* fwait is really an instruction. If there are prefixes
11208 before the fwait, they belong to the fwait, *not* to the
11209 following instruction. */
11211 if (prefixes || rex)
11213 prefixes |= PREFIX_FWAIT;
11215 /* This ensures that the previous REX prefixes are noticed
11216 as unused prefixes, as in the return case below. */
11220 prefixes = PREFIX_FWAIT;
11225 /* Rex is ignored when followed by another prefix. */
11231 if (*codep != FWAIT_OPCODE)
11232 all_prefixes[i++] = *codep;
11240 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11243 static const char *
11244 prefix_name (int pref, int sizeflag)
11246 static const char *rexes [16] =
11249 "rex.B", /* 0x41 */
11250 "rex.X", /* 0x42 */
11251 "rex.XB", /* 0x43 */
11252 "rex.R", /* 0x44 */
11253 "rex.RB", /* 0x45 */
11254 "rex.RX", /* 0x46 */
11255 "rex.RXB", /* 0x47 */
11256 "rex.W", /* 0x48 */
11257 "rex.WB", /* 0x49 */
11258 "rex.WX", /* 0x4a */
11259 "rex.WXB", /* 0x4b */
11260 "rex.WR", /* 0x4c */
11261 "rex.WRB", /* 0x4d */
11262 "rex.WRX", /* 0x4e */
11263 "rex.WRXB", /* 0x4f */
11268 /* REX prefixes family. */
11285 return rexes [pref - 0x40];
11305 return (sizeflag & DFLAG) ? "data16" : "data32";
11307 if (address_mode == mode_64bit)
11308 return (sizeflag & AFLAG) ? "addr32" : "addr64";
11310 return (sizeflag & AFLAG) ? "addr16" : "addr32";
11315 case XACQUIRE_PREFIX:
11317 case XRELEASE_PREFIX:
11321 case NOTRACK_PREFIX:
11328 static char op_out[MAX_OPERANDS][100];
11329 static int op_ad, op_index[MAX_OPERANDS];
11330 static int two_source_ops;
11331 static bfd_vma op_address[MAX_OPERANDS];
11332 static bfd_vma op_riprel[MAX_OPERANDS];
11333 static bfd_vma start_pc;
11336 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11337 * (see topic "Redundant prefixes" in the "Differences from 8086"
11338 * section of the "Virtual 8086 Mode" chapter.)
11339 * 'pc' should be the address of this instruction, it will
11340 * be used to print the target address if this is a relative jump or call
11341 * The function returns the length of this instruction in bytes.
11344 static char intel_syntax;
11345 static char intel_mnemonic = !SYSV386_COMPAT;
11346 static char open_char;
11347 static char close_char;
11348 static char separator_char;
11349 static char scale_char;
11357 static enum x86_64_isa isa64;
11359 /* Here for backwards compatibility. When gdb stops using
11360 print_insn_i386_att and print_insn_i386_intel these functions can
11361 disappear, and print_insn_i386 be merged into print_insn. */
11363 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11367 return print_insn (pc, info);
11371 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11375 return print_insn (pc, info);
11379 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11383 return print_insn (pc, info);
11387 print_i386_disassembler_options (FILE *stream)
11389 fprintf (stream, _("\n\
11390 The following i386/x86-64 specific disassembler options are supported for use\n\
11391 with the -M switch (multiple options should be separated by commas):\n"));
11393 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
11394 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
11395 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
11396 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
11397 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
11398 fprintf (stream, _(" att-mnemonic\n"
11399 " Display instruction in AT&T mnemonic\n"));
11400 fprintf (stream, _(" intel-mnemonic\n"
11401 " Display instruction in Intel mnemonic\n"));
11402 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
11403 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
11404 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
11405 fprintf (stream, _(" data32 Assume 32bit data size\n"));
11406 fprintf (stream, _(" data16 Assume 16bit data size\n"));
11407 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11408 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
11409 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
11413 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11415 /* Get a pointer to struct dis386 with a valid name. */
11417 static const struct dis386 *
11418 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11420 int vindex, vex_table_index;
11422 if (dp->name != NULL)
11425 switch (dp->op[0].bytemode)
11427 case USE_REG_TABLE:
11428 dp = ®_table[dp->op[1].bytemode][modrm.reg];
11431 case USE_MOD_TABLE:
11432 vindex = modrm.mod == 0x3 ? 1 : 0;
11433 dp = &mod_table[dp->op[1].bytemode][vindex];
11437 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11440 case USE_PREFIX_TABLE:
11443 /* The prefix in VEX is implicit. */
11444 switch (vex.prefix)
11449 case REPE_PREFIX_OPCODE:
11452 case DATA_PREFIX_OPCODE:
11455 case REPNE_PREFIX_OPCODE:
11465 int last_prefix = -1;
11468 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11469 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11471 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11473 if (last_repz_prefix > last_repnz_prefix)
11476 prefix = PREFIX_REPZ;
11477 last_prefix = last_repz_prefix;
11482 prefix = PREFIX_REPNZ;
11483 last_prefix = last_repnz_prefix;
11486 /* Check if prefix should be ignored. */
11487 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11488 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11493 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11496 prefix = PREFIX_DATA;
11497 last_prefix = last_data_prefix;
11502 used_prefixes |= prefix;
11503 all_prefixes[last_prefix] = 0;
11506 dp = &prefix_table[dp->op[1].bytemode][vindex];
11509 case USE_X86_64_TABLE:
11510 vindex = address_mode == mode_64bit ? 1 : 0;
11511 dp = &x86_64_table[dp->op[1].bytemode][vindex];
11514 case USE_3BYTE_TABLE:
11515 FETCH_DATA (info, codep + 2);
11517 dp = &three_byte_table[dp->op[1].bytemode][vindex];
11519 modrm.mod = (*codep >> 6) & 3;
11520 modrm.reg = (*codep >> 3) & 7;
11521 modrm.rm = *codep & 7;
11524 case USE_VEX_LEN_TABLE:
11528 switch (vex.length)
11541 dp = &vex_len_table[dp->op[1].bytemode][vindex];
11544 case USE_EVEX_LEN_TABLE:
11548 switch (vex.length)
11564 dp = &evex_len_table[dp->op[1].bytemode][vindex];
11567 case USE_XOP_8F_TABLE:
11568 FETCH_DATA (info, codep + 3);
11569 /* All bits in the REX prefix are ignored. */
11571 rex = ~(*codep >> 5) & 0x7;
11573 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11574 switch ((*codep & 0x1f))
11580 vex_table_index = XOP_08;
11583 vex_table_index = XOP_09;
11586 vex_table_index = XOP_0A;
11590 vex.w = *codep & 0x80;
11591 if (vex.w && address_mode == mode_64bit)
11594 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11595 if (address_mode != mode_64bit)
11597 /* In 16/32-bit mode REX_B is silently ignored. */
11601 vex.length = (*codep & 0x4) ? 256 : 128;
11602 switch ((*codep & 0x3))
11607 vex.prefix = DATA_PREFIX_OPCODE;
11610 vex.prefix = REPE_PREFIX_OPCODE;
11613 vex.prefix = REPNE_PREFIX_OPCODE;
11620 dp = &xop_table[vex_table_index][vindex];
11623 FETCH_DATA (info, codep + 1);
11624 modrm.mod = (*codep >> 6) & 3;
11625 modrm.reg = (*codep >> 3) & 7;
11626 modrm.rm = *codep & 7;
11629 case USE_VEX_C4_TABLE:
11631 FETCH_DATA (info, codep + 3);
11632 /* All bits in the REX prefix are ignored. */
11634 rex = ~(*codep >> 5) & 0x7;
11635 switch ((*codep & 0x1f))
11641 vex_table_index = VEX_0F;
11644 vex_table_index = VEX_0F38;
11647 vex_table_index = VEX_0F3A;
11651 vex.w = *codep & 0x80;
11652 if (address_mode == mode_64bit)
11659 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11660 is ignored, other REX bits are 0 and the highest bit in
11661 VEX.vvvv is also ignored (but we mustn't clear it here). */
11664 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11665 vex.length = (*codep & 0x4) ? 256 : 128;
11666 switch ((*codep & 0x3))
11671 vex.prefix = DATA_PREFIX_OPCODE;
11674 vex.prefix = REPE_PREFIX_OPCODE;
11677 vex.prefix = REPNE_PREFIX_OPCODE;
11684 dp = &vex_table[vex_table_index][vindex];
11686 /* There is no MODRM byte for VEX0F 77. */
11687 if (vex_table_index != VEX_0F || vindex != 0x77)
11689 FETCH_DATA (info, codep + 1);
11690 modrm.mod = (*codep >> 6) & 3;
11691 modrm.reg = (*codep >> 3) & 7;
11692 modrm.rm = *codep & 7;
11696 case USE_VEX_C5_TABLE:
11698 FETCH_DATA (info, codep + 2);
11699 /* All bits in the REX prefix are ignored. */
11701 rex = (*codep & 0x80) ? 0 : REX_R;
11703 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11705 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11706 vex.length = (*codep & 0x4) ? 256 : 128;
11707 switch ((*codep & 0x3))
11712 vex.prefix = DATA_PREFIX_OPCODE;
11715 vex.prefix = REPE_PREFIX_OPCODE;
11718 vex.prefix = REPNE_PREFIX_OPCODE;
11725 dp = &vex_table[dp->op[1].bytemode][vindex];
11727 /* There is no MODRM byte for VEX 77. */
11728 if (vindex != 0x77)
11730 FETCH_DATA (info, codep + 1);
11731 modrm.mod = (*codep >> 6) & 3;
11732 modrm.reg = (*codep >> 3) & 7;
11733 modrm.rm = *codep & 7;
11737 case USE_VEX_W_TABLE:
11741 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11744 case USE_EVEX_TABLE:
11745 two_source_ops = 0;
11748 FETCH_DATA (info, codep + 4);
11749 /* All bits in the REX prefix are ignored. */
11751 /* The first byte after 0x62. */
11752 rex = ~(*codep >> 5) & 0x7;
11753 vex.r = *codep & 0x10;
11754 switch ((*codep & 0xf))
11757 return &bad_opcode;
11759 vex_table_index = EVEX_0F;
11762 vex_table_index = EVEX_0F38;
11765 vex_table_index = EVEX_0F3A;
11769 /* The second byte after 0x62. */
11771 vex.w = *codep & 0x80;
11772 if (vex.w && address_mode == mode_64bit)
11775 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11778 if (!(*codep & 0x4))
11779 return &bad_opcode;
11781 switch ((*codep & 0x3))
11786 vex.prefix = DATA_PREFIX_OPCODE;
11789 vex.prefix = REPE_PREFIX_OPCODE;
11792 vex.prefix = REPNE_PREFIX_OPCODE;
11796 /* The third byte after 0x62. */
11799 /* Remember the static rounding bits. */
11800 vex.ll = (*codep >> 5) & 3;
11801 vex.b = (*codep & 0x10) != 0;
11803 vex.v = *codep & 0x8;
11804 vex.mask_register_specifier = *codep & 0x7;
11805 vex.zeroing = *codep & 0x80;
11807 if (address_mode != mode_64bit)
11809 /* In 16/32-bit mode silently ignore following bits. */
11819 dp = &evex_table[vex_table_index][vindex];
11821 FETCH_DATA (info, codep + 1);
11822 modrm.mod = (*codep >> 6) & 3;
11823 modrm.reg = (*codep >> 3) & 7;
11824 modrm.rm = *codep & 7;
11826 /* Set vector length. */
11827 if (modrm.mod == 3 && vex.b)
11843 return &bad_opcode;
11856 if (dp->name != NULL)
11859 return get_valid_dis386 (dp, info);
11863 get_sib (disassemble_info *info, int sizeflag)
11865 /* If modrm.mod == 3, operand must be register. */
11867 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11871 FETCH_DATA (info, codep + 2);
11872 sib.index = (codep [1] >> 3) & 7;
11873 sib.scale = (codep [1] >> 6) & 3;
11874 sib.base = codep [1] & 7;
11879 print_insn (bfd_vma pc, disassemble_info *info)
11881 const struct dis386 *dp;
11883 char *op_txt[MAX_OPERANDS];
11885 int sizeflag, orig_sizeflag;
11887 struct dis_private priv;
11890 priv.orig_sizeflag = AFLAG | DFLAG;
11891 if ((info->mach & bfd_mach_i386_i386) != 0)
11892 address_mode = mode_32bit;
11893 else if (info->mach == bfd_mach_i386_i8086)
11895 address_mode = mode_16bit;
11896 priv.orig_sizeflag = 0;
11899 address_mode = mode_64bit;
11901 if (intel_syntax == (char) -1)
11902 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11904 for (p = info->disassembler_options; p != NULL; )
11906 if (CONST_STRNEQ (p, "amd64"))
11908 else if (CONST_STRNEQ (p, "intel64"))
11910 else if (CONST_STRNEQ (p, "x86-64"))
11912 address_mode = mode_64bit;
11913 priv.orig_sizeflag = AFLAG | DFLAG;
11915 else if (CONST_STRNEQ (p, "i386"))
11917 address_mode = mode_32bit;
11918 priv.orig_sizeflag = AFLAG | DFLAG;
11920 else if (CONST_STRNEQ (p, "i8086"))
11922 address_mode = mode_16bit;
11923 priv.orig_sizeflag = 0;
11925 else if (CONST_STRNEQ (p, "intel"))
11928 if (CONST_STRNEQ (p + 5, "-mnemonic"))
11929 intel_mnemonic = 1;
11931 else if (CONST_STRNEQ (p, "att"))
11934 if (CONST_STRNEQ (p + 3, "-mnemonic"))
11935 intel_mnemonic = 0;
11937 else if (CONST_STRNEQ (p, "addr"))
11939 if (address_mode == mode_64bit)
11941 if (p[4] == '3' && p[5] == '2')
11942 priv.orig_sizeflag &= ~AFLAG;
11943 else if (p[4] == '6' && p[5] == '4')
11944 priv.orig_sizeflag |= AFLAG;
11948 if (p[4] == '1' && p[5] == '6')
11949 priv.orig_sizeflag &= ~AFLAG;
11950 else if (p[4] == '3' && p[5] == '2')
11951 priv.orig_sizeflag |= AFLAG;
11954 else if (CONST_STRNEQ (p, "data"))
11956 if (p[4] == '1' && p[5] == '6')
11957 priv.orig_sizeflag &= ~DFLAG;
11958 else if (p[4] == '3' && p[5] == '2')
11959 priv.orig_sizeflag |= DFLAG;
11961 else if (CONST_STRNEQ (p, "suffix"))
11962 priv.orig_sizeflag |= SUFFIX_ALWAYS;
11964 p = strchr (p, ',');
11969 if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11971 (*info->fprintf_func) (info->stream,
11972 _("64-bit address is disabled"));
11978 names64 = intel_names64;
11979 names32 = intel_names32;
11980 names16 = intel_names16;
11981 names8 = intel_names8;
11982 names8rex = intel_names8rex;
11983 names_seg = intel_names_seg;
11984 names_mm = intel_names_mm;
11985 names_bnd = intel_names_bnd;
11986 names_xmm = intel_names_xmm;
11987 names_ymm = intel_names_ymm;
11988 names_zmm = intel_names_zmm;
11989 index64 = intel_index64;
11990 index32 = intel_index32;
11991 names_mask = intel_names_mask;
11992 index16 = intel_index16;
11995 separator_char = '+';
12000 names64 = att_names64;
12001 names32 = att_names32;
12002 names16 = att_names16;
12003 names8 = att_names8;
12004 names8rex = att_names8rex;
12005 names_seg = att_names_seg;
12006 names_mm = att_names_mm;
12007 names_bnd = att_names_bnd;
12008 names_xmm = att_names_xmm;
12009 names_ymm = att_names_ymm;
12010 names_zmm = att_names_zmm;
12011 index64 = att_index64;
12012 index32 = att_index32;
12013 names_mask = att_names_mask;
12014 index16 = att_index16;
12017 separator_char = ',';
12021 /* The output looks better if we put 7 bytes on a line, since that
12022 puts most long word instructions on a single line. Use 8 bytes
12024 if ((info->mach & bfd_mach_l1om) != 0)
12025 info->bytes_per_line = 8;
12027 info->bytes_per_line = 7;
12029 info->private_data = &priv;
12030 priv.max_fetched = priv.the_buffer;
12031 priv.insn_start = pc;
12034 for (i = 0; i < MAX_OPERANDS; ++i)
12042 start_codep = priv.the_buffer;
12043 codep = priv.the_buffer;
12045 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12049 /* Getting here means we tried for data but didn't get it. That
12050 means we have an incomplete instruction of some sort. Just
12051 print the first byte as a prefix or a .byte pseudo-op. */
12052 if (codep > priv.the_buffer)
12054 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12056 (*info->fprintf_func) (info->stream, "%s", name);
12059 /* Just print the first byte as a .byte instruction. */
12060 (*info->fprintf_func) (info->stream, ".byte 0x%x",
12061 (unsigned int) priv.the_buffer[0]);
12071 sizeflag = priv.orig_sizeflag;
12073 if (!ckprefix () || rex_used)
12075 /* Too many prefixes or unused REX prefixes. */
12077 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12079 (*info->fprintf_func) (info->stream, "%s%s",
12081 prefix_name (all_prefixes[i], sizeflag));
12085 insn_codep = codep;
12087 FETCH_DATA (info, codep + 1);
12088 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12090 if (((prefixes & PREFIX_FWAIT)
12091 && ((*codep < 0xd8) || (*codep > 0xdf))))
12093 /* Handle prefixes before fwait. */
12094 for (i = 0; i < fwait_prefix && all_prefixes[i];
12096 (*info->fprintf_func) (info->stream, "%s ",
12097 prefix_name (all_prefixes[i], sizeflag));
12098 (*info->fprintf_func) (info->stream, "fwait");
12102 if (*codep == 0x0f)
12104 unsigned char threebyte;
12107 FETCH_DATA (info, codep + 1);
12108 threebyte = *codep;
12109 dp = &dis386_twobyte[threebyte];
12110 need_modrm = twobyte_has_modrm[*codep];
12115 dp = &dis386[*codep];
12116 need_modrm = onebyte_has_modrm[*codep];
12120 /* Save sizeflag for printing the extra prefixes later before updating
12121 it for mnemonic and operand processing. The prefix names depend
12122 only on the address mode. */
12123 orig_sizeflag = sizeflag;
12124 if (prefixes & PREFIX_ADDR)
12126 if ((prefixes & PREFIX_DATA))
12132 FETCH_DATA (info, codep + 1);
12133 modrm.mod = (*codep >> 6) & 3;
12134 modrm.reg = (*codep >> 3) & 7;
12135 modrm.rm = *codep & 7;
12141 memset (&vex, 0, sizeof (vex));
12143 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12145 get_sib (info, sizeflag);
12146 dofloat (sizeflag);
12150 dp = get_valid_dis386 (dp, info);
12151 if (dp != NULL && putop (dp->name, sizeflag) == 0)
12153 get_sib (info, sizeflag);
12154 for (i = 0; i < MAX_OPERANDS; ++i)
12157 op_ad = MAX_OPERANDS - 1 - i;
12159 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12160 /* For EVEX instruction after the last operand masking
12161 should be printed. */
12162 if (i == 0 && vex.evex)
12164 /* Don't print {%k0}. */
12165 if (vex.mask_register_specifier)
12168 oappend (names_mask[vex.mask_register_specifier]);
12178 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12179 are all 0s in inverted form. */
12180 if (need_vex && vex.register_specifier != 0)
12182 (*info->fprintf_func) (info->stream, "(bad)");
12183 return end_codep - priv.the_buffer;
12186 /* Check if the REX prefix is used. */
12187 if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12188 all_prefixes[last_rex_prefix] = 0;
12190 /* Check if the SEG prefix is used. */
12191 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12192 | PREFIX_FS | PREFIX_GS)) != 0
12193 && (used_prefixes & active_seg_prefix) != 0)
12194 all_prefixes[last_seg_prefix] = 0;
12196 /* Check if the ADDR prefix is used. */
12197 if ((prefixes & PREFIX_ADDR) != 0
12198 && (used_prefixes & PREFIX_ADDR) != 0)
12199 all_prefixes[last_addr_prefix] = 0;
12201 /* Check if the DATA prefix is used. */
12202 if ((prefixes & PREFIX_DATA) != 0
12203 && (used_prefixes & PREFIX_DATA) != 0)
12204 all_prefixes[last_data_prefix] = 0;
12206 /* Print the extra prefixes. */
12208 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12209 if (all_prefixes[i])
12212 name = prefix_name (all_prefixes[i], orig_sizeflag);
12215 prefix_length += strlen (name) + 1;
12216 (*info->fprintf_func) (info->stream, "%s ", name);
12219 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12220 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12221 used by putop and MMX/SSE operand and may be overriden by the
12222 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12224 if (dp->prefix_requirement == PREFIX_OPCODE
12225 && dp != &bad_opcode
12227 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12229 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12231 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12233 && (used_prefixes & PREFIX_DATA) == 0))))
12235 (*info->fprintf_func) (info->stream, "(bad)");
12236 return end_codep - priv.the_buffer;
12239 /* Check maximum code length. */
12240 if ((codep - start_codep) > MAX_CODE_LENGTH)
12242 (*info->fprintf_func) (info->stream, "(bad)");
12243 return MAX_CODE_LENGTH;
12246 obufp = mnemonicendp;
12247 for (i = strlen (obuf) + prefix_length; i < 6; i++)
12250 (*info->fprintf_func) (info->stream, "%s", obuf);
12252 /* The enter and bound instructions are printed with operands in the same
12253 order as the intel book; everything else is printed in reverse order. */
12254 if (intel_syntax || two_source_ops)
12258 for (i = 0; i < MAX_OPERANDS; ++i)
12259 op_txt[i] = op_out[i];
12261 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12262 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12264 op_txt[2] = op_out[3];
12265 op_txt[3] = op_out[2];
12268 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12270 op_ad = op_index[i];
12271 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12272 op_index[MAX_OPERANDS - 1 - i] = op_ad;
12273 riprel = op_riprel[i];
12274 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12275 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12280 for (i = 0; i < MAX_OPERANDS; ++i)
12281 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12285 for (i = 0; i < MAX_OPERANDS; ++i)
12289 (*info->fprintf_func) (info->stream, ",");
12290 if (op_index[i] != -1 && !op_riprel[i])
12291 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12293 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12297 for (i = 0; i < MAX_OPERANDS; i++)
12298 if (op_index[i] != -1 && op_riprel[i])
12300 (*info->fprintf_func) (info->stream, " # ");
12301 (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12302 + op_address[op_index[i]]), info);
12305 return codep - priv.the_buffer;
12308 static const char *float_mem[] = {
12383 static const unsigned char float_mem_mode[] = {
12458 #define ST { OP_ST, 0 }
12459 #define STi { OP_STi, 0 }
12461 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12462 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12463 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12464 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12465 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12466 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12467 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12468 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12469 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12471 static const struct dis386 float_reg[][8] = {
12474 { "fadd", { ST, STi }, 0 },
12475 { "fmul", { ST, STi }, 0 },
12476 { "fcom", { STi }, 0 },
12477 { "fcomp", { STi }, 0 },
12478 { "fsub", { ST, STi }, 0 },
12479 { "fsubr", { ST, STi }, 0 },
12480 { "fdiv", { ST, STi }, 0 },
12481 { "fdivr", { ST, STi }, 0 },
12485 { "fld", { STi }, 0 },
12486 { "fxch", { STi }, 0 },
12496 { "fcmovb", { ST, STi }, 0 },
12497 { "fcmove", { ST, STi }, 0 },
12498 { "fcmovbe",{ ST, STi }, 0 },
12499 { "fcmovu", { ST, STi }, 0 },
12507 { "fcmovnb",{ ST, STi }, 0 },
12508 { "fcmovne",{ ST, STi }, 0 },
12509 { "fcmovnbe",{ ST, STi }, 0 },
12510 { "fcmovnu",{ ST, STi }, 0 },
12512 { "fucomi", { ST, STi }, 0 },
12513 { "fcomi", { ST, STi }, 0 },
12518 { "fadd", { STi, ST }, 0 },
12519 { "fmul", { STi, ST }, 0 },
12522 { "fsub{!M|r}", { STi, ST }, 0 },
12523 { "fsub{M|}", { STi, ST }, 0 },
12524 { "fdiv{!M|r}", { STi, ST }, 0 },
12525 { "fdiv{M|}", { STi, ST }, 0 },
12529 { "ffree", { STi }, 0 },
12531 { "fst", { STi }, 0 },
12532 { "fstp", { STi }, 0 },
12533 { "fucom", { STi }, 0 },
12534 { "fucomp", { STi }, 0 },
12540 { "faddp", { STi, ST }, 0 },
12541 { "fmulp", { STi, ST }, 0 },
12544 { "fsub{!M|r}p", { STi, ST }, 0 },
12545 { "fsub{M|}p", { STi, ST }, 0 },
12546 { "fdiv{!M|r}p", { STi, ST }, 0 },
12547 { "fdiv{M|}p", { STi, ST }, 0 },
12551 { "ffreep", { STi }, 0 },
12556 { "fucomip", { ST, STi }, 0 },
12557 { "fcomip", { ST, STi }, 0 },
12562 static char *fgrps[][8] = {
12565 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12570 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12575 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12580 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12585 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12590 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12595 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12600 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12601 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12606 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12611 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12616 swap_operand (void)
12618 mnemonicendp[0] = '.';
12619 mnemonicendp[1] = 's';
12624 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12625 int sizeflag ATTRIBUTE_UNUSED)
12627 /* Skip mod/rm byte. */
12633 dofloat (int sizeflag)
12635 const struct dis386 *dp;
12636 unsigned char floatop;
12638 floatop = codep[-1];
12640 if (modrm.mod != 3)
12642 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12644 putop (float_mem[fp_indx], sizeflag);
12647 OP_E (float_mem_mode[fp_indx], sizeflag);
12650 /* Skip mod/rm byte. */
12654 dp = &float_reg[floatop - 0xd8][modrm.reg];
12655 if (dp->name == NULL)
12657 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12659 /* Instruction fnstsw is only one with strange arg. */
12660 if (floatop == 0xdf && codep[-1] == 0xe0)
12661 strcpy (op_out[0], names16[0]);
12665 putop (dp->name, sizeflag);
12670 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12675 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12679 /* Like oappend (below), but S is a string starting with '%'.
12680 In Intel syntax, the '%' is elided. */
12682 oappend_maybe_intel (const char *s)
12684 oappend (s + intel_syntax);
12688 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12690 oappend_maybe_intel ("%st");
12694 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12696 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12697 oappend_maybe_intel (scratchbuf);
12700 /* Capital letters in template are macros. */
12702 putop (const char *in_template, int sizeflag)
12707 unsigned int l = 0, len = 1;
12710 #define SAVE_LAST(c) \
12711 if (l < len && l < sizeof (last)) \
12716 for (p = in_template; *p; p++)
12732 while (*++p != '|')
12733 if (*p == '}' || *p == '\0')
12736 /* Fall through. */
12741 while (*++p != '}')
12752 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12756 if (l == 0 && len == 1)
12761 if (sizeflag & SUFFIX_ALWAYS)
12774 if (address_mode == mode_64bit
12775 && !(prefixes & PREFIX_ADDR))
12786 if (intel_syntax && !alt)
12788 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12790 if (sizeflag & DFLAG)
12791 *obufp++ = intel_syntax ? 'd' : 'l';
12793 *obufp++ = intel_syntax ? 'w' : 's';
12794 used_prefixes |= (prefixes & PREFIX_DATA);
12798 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12801 if (modrm.mod == 3)
12807 if (sizeflag & DFLAG)
12808 *obufp++ = intel_syntax ? 'd' : 'l';
12811 used_prefixes |= (prefixes & PREFIX_DATA);
12817 case 'E': /* For jcxz/jecxz */
12818 if (address_mode == mode_64bit)
12820 if (sizeflag & AFLAG)
12826 if (sizeflag & AFLAG)
12828 used_prefixes |= (prefixes & PREFIX_ADDR);
12833 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12835 if (sizeflag & AFLAG)
12836 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12838 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12839 used_prefixes |= (prefixes & PREFIX_ADDR);
12843 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12845 if ((rex & REX_W) || (sizeflag & DFLAG))
12849 if (!(rex & REX_W))
12850 used_prefixes |= (prefixes & PREFIX_DATA);
12855 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12856 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12858 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12861 if (prefixes & PREFIX_DS)
12880 if (l != 0 || len != 1)
12882 if (l != 1 || len != 2 || last[0] != 'X')
12887 if (!need_vex || !vex.evex)
12890 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12892 switch (vex.length)
12910 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12915 /* Fall through. */
12918 if (l != 0 || len != 1)
12926 if (sizeflag & SUFFIX_ALWAYS)
12930 if (intel_mnemonic != cond)
12934 if ((prefixes & PREFIX_FWAIT) == 0)
12937 used_prefixes |= PREFIX_FWAIT;
12943 else if (intel_syntax && (sizeflag & DFLAG))
12947 if (!(rex & REX_W))
12948 used_prefixes |= (prefixes & PREFIX_DATA);
12952 && address_mode == mode_64bit
12953 && isa64 == intel64)
12958 /* Fall through. */
12961 && address_mode == mode_64bit
12962 && ((sizeflag & DFLAG) || (rex & REX_W)))
12967 /* Fall through. */
12970 if (l == 0 && len == 1)
12975 if ((rex & REX_W) == 0
12976 && (prefixes & PREFIX_DATA))
12978 if ((sizeflag & DFLAG) == 0)
12980 used_prefixes |= (prefixes & PREFIX_DATA);
12984 if ((prefixes & PREFIX_DATA)
12986 || (sizeflag & SUFFIX_ALWAYS))
12993 if (sizeflag & DFLAG)
12997 used_prefixes |= (prefixes & PREFIX_DATA);
13003 if (l != 1 || len != 2 || last[0] != 'L')
13009 if ((prefixes & PREFIX_DATA)
13011 || (sizeflag & SUFFIX_ALWAYS))
13018 if (sizeflag & DFLAG)
13019 *obufp++ = intel_syntax ? 'd' : 'l';
13022 used_prefixes |= (prefixes & PREFIX_DATA);
13030 if (address_mode == mode_64bit
13031 && ((sizeflag & DFLAG) || (rex & REX_W)))
13033 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13037 /* Fall through. */
13040 if (l == 0 && len == 1)
13043 if (intel_syntax && !alt)
13046 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13052 if (sizeflag & DFLAG)
13053 *obufp++ = intel_syntax ? 'd' : 'l';
13056 used_prefixes |= (prefixes & PREFIX_DATA);
13062 if (l != 1 || len != 2 || last[0] != 'L')
13068 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13083 else if (sizeflag & DFLAG)
13092 if (intel_syntax && !p[1]
13093 && ((rex & REX_W) || (sizeflag & DFLAG)))
13095 if (!(rex & REX_W))
13096 used_prefixes |= (prefixes & PREFIX_DATA);
13099 if (l == 0 && len == 1)
13103 if (address_mode == mode_64bit
13104 && ((sizeflag & DFLAG) || (rex & REX_W)))
13106 if (sizeflag & SUFFIX_ALWAYS)
13128 /* Fall through. */
13131 if (l == 0 && len == 1)
13136 if (sizeflag & SUFFIX_ALWAYS)
13142 if (sizeflag & DFLAG)
13146 used_prefixes |= (prefixes & PREFIX_DATA);
13160 if (address_mode == mode_64bit
13161 && !(prefixes & PREFIX_ADDR))
13172 if (l != 0 || len != 1)
13177 if (need_vex && vex.prefix)
13179 if (vex.prefix == DATA_PREFIX_OPCODE)
13186 if (prefixes & PREFIX_DATA)
13190 used_prefixes |= (prefixes & PREFIX_DATA);
13194 if (l == 0 && len == 1)
13198 if (l != 1 || len != 2 || last[0] != 'X')
13206 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13208 switch (vex.length)
13224 if (l == 0 && len == 1)
13226 /* operand size flag for cwtl, cbtw */
13235 else if (sizeflag & DFLAG)
13239 if (!(rex & REX_W))
13240 used_prefixes |= (prefixes & PREFIX_DATA);
13247 && last[0] != 'L'))
13254 if (last[0] == 'X')
13255 *obufp++ = vex.w ? 'd': 's';
13257 *obufp++ = vex.w ? 'q': 'd';
13263 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13265 if (sizeflag & DFLAG)
13269 used_prefixes |= (prefixes & PREFIX_DATA);
13275 if (address_mode == mode_64bit
13276 && (isa64 == intel64
13277 || ((sizeflag & DFLAG) || (rex & REX_W))))
13279 else if ((prefixes & PREFIX_DATA))
13281 if (!(sizeflag & DFLAG))
13283 used_prefixes |= (prefixes & PREFIX_DATA);
13290 mnemonicendp = obufp;
13295 oappend (const char *s)
13297 obufp = stpcpy (obufp, s);
13303 /* Only print the active segment register. */
13304 if (!active_seg_prefix)
13307 used_prefixes |= active_seg_prefix;
13308 switch (active_seg_prefix)
13311 oappend_maybe_intel ("%cs:");
13314 oappend_maybe_intel ("%ds:");
13317 oappend_maybe_intel ("%ss:");
13320 oappend_maybe_intel ("%es:");
13323 oappend_maybe_intel ("%fs:");
13326 oappend_maybe_intel ("%gs:");
13334 OP_indirE (int bytemode, int sizeflag)
13338 OP_E (bytemode, sizeflag);
13342 print_operand_value (char *buf, int hex, bfd_vma disp)
13344 if (address_mode == mode_64bit)
13352 sprintf_vma (tmp, disp);
13353 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13354 strcpy (buf + 2, tmp + i);
13358 bfd_signed_vma v = disp;
13365 /* Check for possible overflow on 0x8000000000000000. */
13368 strcpy (buf, "9223372036854775808");
13382 tmp[28 - i] = (v % 10) + '0';
13386 strcpy (buf, tmp + 29 - i);
13392 sprintf (buf, "0x%x", (unsigned int) disp);
13394 sprintf (buf, "%d", (int) disp);
13398 /* Put DISP in BUF as signed hex number. */
13401 print_displacement (char *buf, bfd_vma disp)
13403 bfd_signed_vma val = disp;
13412 /* Check for possible overflow. */
13415 switch (address_mode)
13418 strcpy (buf + j, "0x8000000000000000");
13421 strcpy (buf + j, "0x80000000");
13424 strcpy (buf + j, "0x8000");
13434 sprintf_vma (tmp, (bfd_vma) val);
13435 for (i = 0; tmp[i] == '0'; i++)
13437 if (tmp[i] == '\0')
13439 strcpy (buf + j, tmp + i);
13443 intel_operand_size (int bytemode, int sizeflag)
13447 && (bytemode == x_mode
13448 || bytemode == evex_half_bcst_xmmq_mode))
13451 oappend ("QWORD PTR ");
13453 oappend ("DWORD PTR ");
13462 oappend ("BYTE PTR ");
13467 oappend ("WORD PTR ");
13470 if (address_mode == mode_64bit && isa64 == intel64)
13472 oappend ("QWORD PTR ");
13475 /* Fall through. */
13477 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13479 oappend ("QWORD PTR ");
13482 /* Fall through. */
13488 oappend ("QWORD PTR ");
13491 if ((sizeflag & DFLAG) || bytemode == dq_mode)
13492 oappend ("DWORD PTR ");
13494 oappend ("WORD PTR ");
13495 used_prefixes |= (prefixes & PREFIX_DATA);
13499 if ((rex & REX_W) || (sizeflag & DFLAG))
13501 oappend ("WORD PTR ");
13502 if (!(rex & REX_W))
13503 used_prefixes |= (prefixes & PREFIX_DATA);
13506 if (sizeflag & DFLAG)
13507 oappend ("QWORD PTR ");
13509 oappend ("DWORD PTR ");
13510 used_prefixes |= (prefixes & PREFIX_DATA);
13513 case d_scalar_mode:
13514 case d_scalar_swap_mode:
13517 oappend ("DWORD PTR ");
13520 case q_scalar_mode:
13521 case q_scalar_swap_mode:
13523 oappend ("QWORD PTR ");
13527 if (address_mode == mode_64bit)
13528 oappend ("QWORD PTR ");
13530 oappend ("DWORD PTR ");
13533 if (sizeflag & DFLAG)
13534 oappend ("FWORD PTR ");
13536 oappend ("DWORD PTR ");
13537 used_prefixes |= (prefixes & PREFIX_DATA);
13540 oappend ("TBYTE PTR ");
13544 case evex_x_gscat_mode:
13545 case evex_x_nobcst_mode:
13546 case b_scalar_mode:
13547 case w_scalar_mode:
13550 switch (vex.length)
13553 oappend ("XMMWORD PTR ");
13556 oappend ("YMMWORD PTR ");
13559 oappend ("ZMMWORD PTR ");
13566 oappend ("XMMWORD PTR ");
13569 oappend ("XMMWORD PTR ");
13572 oappend ("YMMWORD PTR ");
13575 case evex_half_bcst_xmmq_mode:
13579 switch (vex.length)
13582 oappend ("QWORD PTR ");
13585 oappend ("XMMWORD PTR ");
13588 oappend ("YMMWORD PTR ");
13598 switch (vex.length)
13603 oappend ("BYTE PTR ");
13613 switch (vex.length)
13618 oappend ("WORD PTR ");
13628 switch (vex.length)
13633 oappend ("DWORD PTR ");
13643 switch (vex.length)
13648 oappend ("QWORD PTR ");
13658 switch (vex.length)
13661 oappend ("WORD PTR ");
13664 oappend ("DWORD PTR ");
13667 oappend ("QWORD PTR ");
13677 switch (vex.length)
13680 oappend ("DWORD PTR ");
13683 oappend ("QWORD PTR ");
13686 oappend ("XMMWORD PTR ");
13696 switch (vex.length)
13699 oappend ("QWORD PTR ");
13702 oappend ("YMMWORD PTR ");
13705 oappend ("ZMMWORD PTR ");
13715 switch (vex.length)
13719 oappend ("XMMWORD PTR ");
13726 oappend ("OWORD PTR ");
13729 case vex_w_dq_mode:
13730 case vex_scalar_w_dq_mode:
13735 oappend ("QWORD PTR ");
13737 oappend ("DWORD PTR ");
13739 case vex_vsib_d_w_dq_mode:
13740 case vex_vsib_q_w_dq_mode:
13747 oappend ("QWORD PTR ");
13749 oappend ("DWORD PTR ");
13753 switch (vex.length)
13756 oappend ("XMMWORD PTR ");
13759 oappend ("YMMWORD PTR ");
13762 oappend ("ZMMWORD PTR ");
13769 case vex_vsib_q_w_d_mode:
13770 case vex_vsib_d_w_d_mode:
13771 if (!need_vex || !vex.evex)
13774 switch (vex.length)
13777 oappend ("QWORD PTR ");
13780 oappend ("XMMWORD PTR ");
13783 oappend ("YMMWORD PTR ");
13791 if (!need_vex || vex.length != 128)
13794 oappend ("DWORD PTR ");
13796 oappend ("BYTE PTR ");
13802 oappend ("QWORD PTR ");
13804 oappend ("WORD PTR ");
13814 OP_E_register (int bytemode, int sizeflag)
13816 int reg = modrm.rm;
13817 const char **names;
13823 if ((sizeflag & SUFFIX_ALWAYS)
13824 && (bytemode == b_swap_mode
13825 || bytemode == bnd_swap_mode
13826 || bytemode == v_swap_mode))
13852 names = address_mode == mode_64bit ? names64 : names32;
13855 case bnd_swap_mode:
13864 if (address_mode == mode_64bit && isa64 == intel64)
13869 /* Fall through. */
13871 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13877 /* Fall through. */
13890 if ((sizeflag & DFLAG)
13891 || (bytemode != v_mode
13892 && bytemode != v_swap_mode))
13896 used_prefixes |= (prefixes & PREFIX_DATA);
13900 names = (address_mode == mode_64bit
13901 ? names64 : names32);
13902 if (!(prefixes & PREFIX_ADDR))
13903 names = (address_mode == mode_16bit
13904 ? names16 : names);
13907 /* Remove "addr16/addr32". */
13908 all_prefixes[last_addr_prefix] = 0;
13909 names = (address_mode != mode_32bit
13910 ? names32 : names16);
13911 used_prefixes |= PREFIX_ADDR;
13921 names = names_mask;
13926 oappend (INTERNAL_DISASSEMBLER_ERROR);
13929 oappend (names[reg]);
13933 OP_E_memory (int bytemode, int sizeflag)
13936 int add = (rex & REX_B) ? 8 : 0;
13942 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
13944 && bytemode != x_mode
13945 && bytemode != xmmq_mode
13946 && bytemode != evex_half_bcst_xmmq_mode)
13962 if (address_mode != mode_64bit)
13968 case vex_vsib_d_w_dq_mode:
13969 case vex_vsib_d_w_d_mode:
13970 case vex_vsib_q_w_dq_mode:
13971 case vex_vsib_q_w_d_mode:
13972 case evex_x_gscat_mode:
13974 shift = vex.w ? 3 : 2;
13977 case evex_half_bcst_xmmq_mode:
13981 shift = vex.w ? 3 : 2;
13984 /* Fall through. */
13988 case evex_x_nobcst_mode:
13990 switch (vex.length)
14013 case q_scalar_mode:
14015 case q_scalar_swap_mode:
14021 case d_scalar_mode:
14023 case d_scalar_swap_mode:
14026 case w_scalar_mode:
14030 case b_scalar_mode:
14035 shift = address_mode == mode_64bit ? 3 : 2;
14040 /* Make necessary corrections to shift for modes that need it.
14041 For these modes we currently have shift 4, 5 or 6 depending on
14042 vex.length (it corresponds to xmmword, ymmword or zmmword
14043 operand). We might want to make it 3, 4 or 5 (e.g. for
14044 xmmq_mode). In case of broadcast enabled the corrections
14045 aren't needed, as element size is always 32 or 64 bits. */
14047 && (bytemode == xmmq_mode
14048 || bytemode == evex_half_bcst_xmmq_mode))
14050 else if (bytemode == xmmqd_mode)
14052 else if (bytemode == xmmdw_mode)
14054 else if (bytemode == ymmq_mode && vex.length == 128)
14062 intel_operand_size (bytemode, sizeflag);
14065 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14067 /* 32/64 bit address mode */
14077 int addr32flag = !((sizeflag & AFLAG)
14078 || bytemode == v_bnd_mode
14079 || bytemode == v_bndmk_mode
14080 || bytemode == bnd_mode
14081 || bytemode == bnd_swap_mode);
14082 const char **indexes64 = names64;
14083 const char **indexes32 = names32;
14093 vindex = sib.index;
14099 case vex_vsib_d_w_dq_mode:
14100 case vex_vsib_d_w_d_mode:
14101 case vex_vsib_q_w_dq_mode:
14102 case vex_vsib_q_w_d_mode:
14112 switch (vex.length)
14115 indexes64 = indexes32 = names_xmm;
14119 || bytemode == vex_vsib_q_w_dq_mode
14120 || bytemode == vex_vsib_q_w_d_mode)
14121 indexes64 = indexes32 = names_ymm;
14123 indexes64 = indexes32 = names_xmm;
14127 || bytemode == vex_vsib_q_w_dq_mode
14128 || bytemode == vex_vsib_q_w_d_mode)
14129 indexes64 = indexes32 = names_zmm;
14131 indexes64 = indexes32 = names_ymm;
14138 haveindex = vindex != 4;
14145 rbase = base + add;
14153 if (address_mode == mode_64bit && !havesib)
14156 if (riprel && bytemode == v_bndmk_mode)
14164 FETCH_DATA (the_info, codep + 1);
14166 if ((disp & 0x80) != 0)
14168 if (vex.evex && shift > 0)
14181 && address_mode != mode_16bit)
14183 if (address_mode == mode_64bit)
14185 /* Display eiz instead of addr32. */
14186 needindex = addr32flag;
14191 /* In 32-bit mode, we need index register to tell [offset]
14192 from [eiz*1 + offset]. */
14197 havedisp = (havebase
14199 || (havesib && (haveindex || scale != 0)));
14202 if (modrm.mod != 0 || base == 5)
14204 if (havedisp || riprel)
14205 print_displacement (scratchbuf, disp);
14207 print_operand_value (scratchbuf, 1, disp);
14208 oappend (scratchbuf);
14212 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14216 if ((havebase || haveindex || needaddr32 || riprel)
14217 && (bytemode != v_bnd_mode)
14218 && (bytemode != v_bndmk_mode)
14219 && (bytemode != bnd_mode)
14220 && (bytemode != bnd_swap_mode))
14221 used_prefixes |= PREFIX_ADDR;
14223 if (havedisp || (intel_syntax && riprel))
14225 *obufp++ = open_char;
14226 if (intel_syntax && riprel)
14229 oappend (!addr32flag ? "rip" : "eip");
14233 oappend (address_mode == mode_64bit && !addr32flag
14234 ? names64[rbase] : names32[rbase]);
14237 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14238 print index to tell base + index from base. */
14242 || (havebase && base != ESP_REG_NUM))
14244 if (!intel_syntax || havebase)
14246 *obufp++ = separator_char;
14250 oappend (address_mode == mode_64bit && !addr32flag
14251 ? indexes64[vindex] : indexes32[vindex]);
14253 oappend (address_mode == mode_64bit && !addr32flag
14254 ? index64 : index32);
14256 *obufp++ = scale_char;
14258 sprintf (scratchbuf, "%d", 1 << scale);
14259 oappend (scratchbuf);
14263 && (disp || modrm.mod != 0 || base == 5))
14265 if (!havedisp || (bfd_signed_vma) disp >= 0)
14270 else if (modrm.mod != 1 && disp != -disp)
14274 disp = - (bfd_signed_vma) disp;
14278 print_displacement (scratchbuf, disp);
14280 print_operand_value (scratchbuf, 1, disp);
14281 oappend (scratchbuf);
14284 *obufp++ = close_char;
14287 else if (intel_syntax)
14289 if (modrm.mod != 0 || base == 5)
14291 if (!active_seg_prefix)
14293 oappend (names_seg[ds_reg - es_reg]);
14296 print_operand_value (scratchbuf, 1, disp);
14297 oappend (scratchbuf);
14303 /* 16 bit address mode */
14304 used_prefixes |= prefixes & PREFIX_ADDR;
14311 if ((disp & 0x8000) != 0)
14316 FETCH_DATA (the_info, codep + 1);
14318 if ((disp & 0x80) != 0)
14320 if (vex.evex && shift > 0)
14325 if ((disp & 0x8000) != 0)
14331 if (modrm.mod != 0 || modrm.rm == 6)
14333 print_displacement (scratchbuf, disp);
14334 oappend (scratchbuf);
14337 if (modrm.mod != 0 || modrm.rm != 6)
14339 *obufp++ = open_char;
14341 oappend (index16[modrm.rm]);
14343 && (disp || modrm.mod != 0 || modrm.rm == 6))
14345 if ((bfd_signed_vma) disp >= 0)
14350 else if (modrm.mod != 1)
14354 disp = - (bfd_signed_vma) disp;
14357 print_displacement (scratchbuf, disp);
14358 oappend (scratchbuf);
14361 *obufp++ = close_char;
14364 else if (intel_syntax)
14366 if (!active_seg_prefix)
14368 oappend (names_seg[ds_reg - es_reg]);
14371 print_operand_value (scratchbuf, 1, disp & 0xffff);
14372 oappend (scratchbuf);
14375 if (vex.evex && vex.b
14376 && (bytemode == x_mode
14377 || bytemode == xmmq_mode
14378 || bytemode == evex_half_bcst_xmmq_mode))
14381 || bytemode == xmmq_mode
14382 || bytemode == evex_half_bcst_xmmq_mode)
14384 switch (vex.length)
14387 oappend ("{1to2}");
14390 oappend ("{1to4}");
14393 oappend ("{1to8}");
14401 switch (vex.length)
14404 oappend ("{1to4}");
14407 oappend ("{1to8}");
14410 oappend ("{1to16}");
14420 OP_E (int bytemode, int sizeflag)
14422 /* Skip mod/rm byte. */
14426 if (modrm.mod == 3)
14427 OP_E_register (bytemode, sizeflag);
14429 OP_E_memory (bytemode, sizeflag);
14433 OP_G (int bytemode, int sizeflag)
14436 const char **names;
14445 oappend (names8rex[modrm.reg + add]);
14447 oappend (names8[modrm.reg + add]);
14450 oappend (names16[modrm.reg + add]);
14455 oappend (names32[modrm.reg + add]);
14458 oappend (names64[modrm.reg + add]);
14461 if (modrm.reg > 0x3)
14466 oappend (names_bnd[modrm.reg]);
14475 oappend (names64[modrm.reg + add]);
14478 if ((sizeflag & DFLAG) || bytemode != v_mode)
14479 oappend (names32[modrm.reg + add]);
14481 oappend (names16[modrm.reg + add]);
14482 used_prefixes |= (prefixes & PREFIX_DATA);
14486 names = (address_mode == mode_64bit
14487 ? names64 : names32);
14488 if (!(prefixes & PREFIX_ADDR))
14490 if (address_mode == mode_16bit)
14495 /* Remove "addr16/addr32". */
14496 all_prefixes[last_addr_prefix] = 0;
14497 names = (address_mode != mode_32bit
14498 ? names32 : names16);
14499 used_prefixes |= PREFIX_ADDR;
14501 oappend (names[modrm.reg + add]);
14504 if (address_mode == mode_64bit)
14505 oappend (names64[modrm.reg + add]);
14507 oappend (names32[modrm.reg + add]);
14511 if ((modrm.reg + add) > 0x7)
14516 oappend (names_mask[modrm.reg + add]);
14519 oappend (INTERNAL_DISASSEMBLER_ERROR);
14532 FETCH_DATA (the_info, codep + 8);
14533 a = *codep++ & 0xff;
14534 a |= (*codep++ & 0xff) << 8;
14535 a |= (*codep++ & 0xff) << 16;
14536 a |= (*codep++ & 0xffu) << 24;
14537 b = *codep++ & 0xff;
14538 b |= (*codep++ & 0xff) << 8;
14539 b |= (*codep++ & 0xff) << 16;
14540 b |= (*codep++ & 0xffu) << 24;
14541 x = a + ((bfd_vma) b << 32);
14549 static bfd_signed_vma
14552 bfd_signed_vma x = 0;
14554 FETCH_DATA (the_info, codep + 4);
14555 x = *codep++ & (bfd_signed_vma) 0xff;
14556 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14557 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14558 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14562 static bfd_signed_vma
14565 bfd_signed_vma x = 0;
14567 FETCH_DATA (the_info, codep + 4);
14568 x = *codep++ & (bfd_signed_vma) 0xff;
14569 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14570 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14571 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14573 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14583 FETCH_DATA (the_info, codep + 2);
14584 x = *codep++ & 0xff;
14585 x |= (*codep++ & 0xff) << 8;
14590 set_op (bfd_vma op, int riprel)
14592 op_index[op_ad] = op_ad;
14593 if (address_mode == mode_64bit)
14595 op_address[op_ad] = op;
14596 op_riprel[op_ad] = riprel;
14600 /* Mask to get a 32-bit address. */
14601 op_address[op_ad] = op & 0xffffffff;
14602 op_riprel[op_ad] = riprel & 0xffffffff;
14607 OP_REG (int code, int sizeflag)
14614 case es_reg: case ss_reg: case cs_reg:
14615 case ds_reg: case fs_reg: case gs_reg:
14616 oappend (names_seg[code - es_reg]);
14628 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14629 case sp_reg: case bp_reg: case si_reg: case di_reg:
14630 s = names16[code - ax_reg + add];
14632 case al_reg: case ah_reg: case cl_reg: case ch_reg:
14633 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14636 s = names8rex[code - al_reg + add];
14638 s = names8[code - al_reg];
14640 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14641 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14642 if (address_mode == mode_64bit
14643 && ((sizeflag & DFLAG) || (rex & REX_W)))
14645 s = names64[code - rAX_reg + add];
14648 code += eAX_reg - rAX_reg;
14649 /* Fall through. */
14650 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14651 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14654 s = names64[code - eAX_reg + add];
14657 if (sizeflag & DFLAG)
14658 s = names32[code - eAX_reg + add];
14660 s = names16[code - eAX_reg + add];
14661 used_prefixes |= (prefixes & PREFIX_DATA);
14665 s = INTERNAL_DISASSEMBLER_ERROR;
14672 OP_IMREG (int code, int sizeflag)
14684 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14685 case sp_reg: case bp_reg: case si_reg: case di_reg:
14686 s = names16[code - ax_reg];
14688 case es_reg: case ss_reg: case cs_reg:
14689 case ds_reg: case fs_reg: case gs_reg:
14690 s = names_seg[code - es_reg];
14692 case al_reg: case ah_reg: case cl_reg: case ch_reg:
14693 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14696 s = names8rex[code - al_reg];
14698 s = names8[code - al_reg];
14700 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14701 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14704 s = names64[code - eAX_reg];
14707 if (sizeflag & DFLAG)
14708 s = names32[code - eAX_reg];
14710 s = names16[code - eAX_reg];
14711 used_prefixes |= (prefixes & PREFIX_DATA);
14714 case z_mode_ax_reg:
14715 if ((rex & REX_W) || (sizeflag & DFLAG))
14719 if (!(rex & REX_W))
14720 used_prefixes |= (prefixes & PREFIX_DATA);
14723 s = INTERNAL_DISASSEMBLER_ERROR;
14730 OP_I (int bytemode, int sizeflag)
14733 bfd_signed_vma mask = -1;
14738 FETCH_DATA (the_info, codep + 1);
14743 if (address_mode == mode_64bit)
14748 /* Fall through. */
14755 if (sizeflag & DFLAG)
14765 used_prefixes |= (prefixes & PREFIX_DATA);
14777 oappend (INTERNAL_DISASSEMBLER_ERROR);
14782 scratchbuf[0] = '$';
14783 print_operand_value (scratchbuf + 1, 1, op);
14784 oappend_maybe_intel (scratchbuf);
14785 scratchbuf[0] = '\0';
14789 OP_I64 (int bytemode, int sizeflag)
14792 bfd_signed_vma mask = -1;
14794 if (address_mode != mode_64bit)
14796 OP_I (bytemode, sizeflag);
14803 FETCH_DATA (the_info, codep + 1);
14813 if (sizeflag & DFLAG)
14823 used_prefixes |= (prefixes & PREFIX_DATA);
14831 oappend (INTERNAL_DISASSEMBLER_ERROR);
14836 scratchbuf[0] = '$';
14837 print_operand_value (scratchbuf + 1, 1, op);
14838 oappend_maybe_intel (scratchbuf);
14839 scratchbuf[0] = '\0';
14843 OP_sI (int bytemode, int sizeflag)
14851 FETCH_DATA (the_info, codep + 1);
14853 if ((op & 0x80) != 0)
14855 if (bytemode == b_T_mode)
14857 if (address_mode != mode_64bit
14858 || !((sizeflag & DFLAG) || (rex & REX_W)))
14860 /* The operand-size prefix is overridden by a REX prefix. */
14861 if ((sizeflag & DFLAG) || (rex & REX_W))
14869 if (!(rex & REX_W))
14871 if (sizeflag & DFLAG)
14879 /* The operand-size prefix is overridden by a REX prefix. */
14880 if ((sizeflag & DFLAG) || (rex & REX_W))
14886 oappend (INTERNAL_DISASSEMBLER_ERROR);
14890 scratchbuf[0] = '$';
14891 print_operand_value (scratchbuf + 1, 1, op);
14892 oappend_maybe_intel (scratchbuf);
14896 OP_J (int bytemode, int sizeflag)
14900 bfd_vma segment = 0;
14905 FETCH_DATA (the_info, codep + 1);
14907 if ((disp & 0x80) != 0)
14911 if (isa64 == amd64)
14913 if ((sizeflag & DFLAG)
14914 || (address_mode == mode_64bit
14915 && (isa64 != amd64 || (rex & REX_W))))
14920 if ((disp & 0x8000) != 0)
14922 /* In 16bit mode, address is wrapped around at 64k within
14923 the same segment. Otherwise, a data16 prefix on a jump
14924 instruction means that the pc is masked to 16 bits after
14925 the displacement is added! */
14927 if ((prefixes & PREFIX_DATA) == 0)
14928 segment = ((start_pc + (codep - start_codep))
14929 & ~((bfd_vma) 0xffff));
14931 if (address_mode != mode_64bit
14932 || (isa64 == amd64 && !(rex & REX_W)))
14933 used_prefixes |= (prefixes & PREFIX_DATA);
14936 oappend (INTERNAL_DISASSEMBLER_ERROR);
14939 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14941 print_operand_value (scratchbuf, 1, disp);
14942 oappend (scratchbuf);
14946 OP_SEG (int bytemode, int sizeflag)
14948 if (bytemode == w_mode)
14949 oappend (names_seg[modrm.reg]);
14951 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14955 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14959 if (sizeflag & DFLAG)
14969 used_prefixes |= (prefixes & PREFIX_DATA);
14971 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14973 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14974 oappend (scratchbuf);
14978 OP_OFF (int bytemode, int sizeflag)
14982 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14983 intel_operand_size (bytemode, sizeflag);
14986 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14993 if (!active_seg_prefix)
14995 oappend (names_seg[ds_reg - es_reg]);
14999 print_operand_value (scratchbuf, 1, off);
15000 oappend (scratchbuf);
15004 OP_OFF64 (int bytemode, int sizeflag)
15008 if (address_mode != mode_64bit
15009 || (prefixes & PREFIX_ADDR))
15011 OP_OFF (bytemode, sizeflag);
15015 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15016 intel_operand_size (bytemode, sizeflag);
15023 if (!active_seg_prefix)
15025 oappend (names_seg[ds_reg - es_reg]);
15029 print_operand_value (scratchbuf, 1, off);
15030 oappend (scratchbuf);
15034 ptr_reg (int code, int sizeflag)
15038 *obufp++ = open_char;
15039 used_prefixes |= (prefixes & PREFIX_ADDR);
15040 if (address_mode == mode_64bit)
15042 if (!(sizeflag & AFLAG))
15043 s = names32[code - eAX_reg];
15045 s = names64[code - eAX_reg];
15047 else if (sizeflag & AFLAG)
15048 s = names32[code - eAX_reg];
15050 s = names16[code - eAX_reg];
15052 *obufp++ = close_char;
15057 OP_ESreg (int code, int sizeflag)
15063 case 0x6d: /* insw/insl */
15064 intel_operand_size (z_mode, sizeflag);
15066 case 0xa5: /* movsw/movsl/movsq */
15067 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15068 case 0xab: /* stosw/stosl */
15069 case 0xaf: /* scasw/scasl */
15070 intel_operand_size (v_mode, sizeflag);
15073 intel_operand_size (b_mode, sizeflag);
15076 oappend_maybe_intel ("%es:");
15077 ptr_reg (code, sizeflag);
15081 OP_DSreg (int code, int sizeflag)
15087 case 0x6f: /* outsw/outsl */
15088 intel_operand_size (z_mode, sizeflag);
15090 case 0xa5: /* movsw/movsl/movsq */
15091 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15092 case 0xad: /* lodsw/lodsl/lodsq */
15093 intel_operand_size (v_mode, sizeflag);
15096 intel_operand_size (b_mode, sizeflag);
15099 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15100 default segment register DS is printed. */
15101 if (!active_seg_prefix)
15102 active_seg_prefix = PREFIX_DS;
15104 ptr_reg (code, sizeflag);
15108 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15116 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15118 all_prefixes[last_lock_prefix] = 0;
15119 used_prefixes |= PREFIX_LOCK;
15124 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15125 oappend_maybe_intel (scratchbuf);
15129 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15138 sprintf (scratchbuf, "db%d", modrm.reg + add);
15140 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15141 oappend (scratchbuf);
15145 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15147 sprintf (scratchbuf, "%%tr%d", modrm.reg);
15148 oappend_maybe_intel (scratchbuf);
15152 OP_R (int bytemode, int sizeflag)
15154 /* Skip mod/rm byte. */
15157 OP_E_register (bytemode, sizeflag);
15161 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15163 int reg = modrm.reg;
15164 const char **names;
15166 used_prefixes |= (prefixes & PREFIX_DATA);
15167 if (prefixes & PREFIX_DATA)
15176 oappend (names[reg]);
15180 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15182 int reg = modrm.reg;
15183 const char **names;
15195 && bytemode != xmm_mode
15196 && bytemode != xmmq_mode
15197 && bytemode != evex_half_bcst_xmmq_mode
15198 && bytemode != ymm_mode
15199 && bytemode != scalar_mode)
15201 switch (vex.length)
15208 || (bytemode != vex_vsib_q_w_dq_mode
15209 && bytemode != vex_vsib_q_w_d_mode))
15221 else if (bytemode == xmmq_mode
15222 || bytemode == evex_half_bcst_xmmq_mode)
15224 switch (vex.length)
15237 else if (bytemode == ymm_mode)
15241 oappend (names[reg]);
15245 OP_EM (int bytemode, int sizeflag)
15248 const char **names;
15250 if (modrm.mod != 3)
15253 && (bytemode == v_mode || bytemode == v_swap_mode))
15255 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15256 used_prefixes |= (prefixes & PREFIX_DATA);
15258 OP_E (bytemode, sizeflag);
15262 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15265 /* Skip mod/rm byte. */
15268 used_prefixes |= (prefixes & PREFIX_DATA);
15270 if (prefixes & PREFIX_DATA)
15279 oappend (names[reg]);
15282 /* cvt* are the only instructions in sse2 which have
15283 both SSE and MMX operands and also have 0x66 prefix
15284 in their opcode. 0x66 was originally used to differentiate
15285 between SSE and MMX instruction(operands). So we have to handle the
15286 cvt* separately using OP_EMC and OP_MXC */
15288 OP_EMC (int bytemode, int sizeflag)
15290 if (modrm.mod != 3)
15292 if (intel_syntax && bytemode == v_mode)
15294 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15295 used_prefixes |= (prefixes & PREFIX_DATA);
15297 OP_E (bytemode, sizeflag);
15301 /* Skip mod/rm byte. */
15304 used_prefixes |= (prefixes & PREFIX_DATA);
15305 oappend (names_mm[modrm.rm]);
15309 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15311 used_prefixes |= (prefixes & PREFIX_DATA);
15312 oappend (names_mm[modrm.reg]);
15316 OP_EX (int bytemode, int sizeflag)
15319 const char **names;
15321 /* Skip mod/rm byte. */
15325 if (modrm.mod != 3)
15327 OP_E_memory (bytemode, sizeflag);
15342 if ((sizeflag & SUFFIX_ALWAYS)
15343 && (bytemode == x_swap_mode
15344 || bytemode == d_swap_mode
15345 || bytemode == d_scalar_swap_mode
15346 || bytemode == q_swap_mode
15347 || bytemode == q_scalar_swap_mode))
15351 && bytemode != xmm_mode
15352 && bytemode != xmmdw_mode
15353 && bytemode != xmmqd_mode
15354 && bytemode != xmm_mb_mode
15355 && bytemode != xmm_mw_mode
15356 && bytemode != xmm_md_mode
15357 && bytemode != xmm_mq_mode
15358 && bytemode != xmm_mdq_mode
15359 && bytemode != xmmq_mode
15360 && bytemode != evex_half_bcst_xmmq_mode
15361 && bytemode != ymm_mode
15362 && bytemode != d_scalar_mode
15363 && bytemode != d_scalar_swap_mode
15364 && bytemode != q_scalar_mode
15365 && bytemode != q_scalar_swap_mode
15366 && bytemode != vex_scalar_w_dq_mode)
15368 switch (vex.length)
15383 else if (bytemode == xmmq_mode
15384 || bytemode == evex_half_bcst_xmmq_mode)
15386 switch (vex.length)
15399 else if (bytemode == ymm_mode)
15403 oappend (names[reg]);
15407 OP_MS (int bytemode, int sizeflag)
15409 if (modrm.mod == 3)
15410 OP_EM (bytemode, sizeflag);
15416 OP_XS (int bytemode, int sizeflag)
15418 if (modrm.mod == 3)
15419 OP_EX (bytemode, sizeflag);
15425 OP_M (int bytemode, int sizeflag)
15427 if (modrm.mod == 3)
15428 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15431 OP_E (bytemode, sizeflag);
15435 OP_0f07 (int bytemode, int sizeflag)
15437 if (modrm.mod != 3 || modrm.rm != 0)
15440 OP_E (bytemode, sizeflag);
15443 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15444 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15447 NOP_Fixup1 (int bytemode, int sizeflag)
15449 if ((prefixes & PREFIX_DATA) != 0
15452 && address_mode == mode_64bit))
15453 OP_REG (bytemode, sizeflag);
15455 strcpy (obuf, "nop");
15459 NOP_Fixup2 (int bytemode, int sizeflag)
15461 if ((prefixes & PREFIX_DATA) != 0
15464 && address_mode == mode_64bit))
15465 OP_IMREG (bytemode, sizeflag);
15468 static const char *const Suffix3DNow[] = {
15469 /* 00 */ NULL, NULL, NULL, NULL,
15470 /* 04 */ NULL, NULL, NULL, NULL,
15471 /* 08 */ NULL, NULL, NULL, NULL,
15472 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
15473 /* 10 */ NULL, NULL, NULL, NULL,
15474 /* 14 */ NULL, NULL, NULL, NULL,
15475 /* 18 */ NULL, NULL, NULL, NULL,
15476 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
15477 /* 20 */ NULL, NULL, NULL, NULL,
15478 /* 24 */ NULL, NULL, NULL, NULL,
15479 /* 28 */ NULL, NULL, NULL, NULL,
15480 /* 2C */ NULL, NULL, NULL, NULL,
15481 /* 30 */ NULL, NULL, NULL, NULL,
15482 /* 34 */ NULL, NULL, NULL, NULL,
15483 /* 38 */ NULL, NULL, NULL, NULL,
15484 /* 3C */ NULL, NULL, NULL, NULL,
15485 /* 40 */ NULL, NULL, NULL, NULL,
15486 /* 44 */ NULL, NULL, NULL, NULL,
15487 /* 48 */ NULL, NULL, NULL, NULL,
15488 /* 4C */ NULL, NULL, NULL, NULL,
15489 /* 50 */ NULL, NULL, NULL, NULL,
15490 /* 54 */ NULL, NULL, NULL, NULL,
15491 /* 58 */ NULL, NULL, NULL, NULL,
15492 /* 5C */ NULL, NULL, NULL, NULL,
15493 /* 60 */ NULL, NULL, NULL, NULL,
15494 /* 64 */ NULL, NULL, NULL, NULL,
15495 /* 68 */ NULL, NULL, NULL, NULL,
15496 /* 6C */ NULL, NULL, NULL, NULL,
15497 /* 70 */ NULL, NULL, NULL, NULL,
15498 /* 74 */ NULL, NULL, NULL, NULL,
15499 /* 78 */ NULL, NULL, NULL, NULL,
15500 /* 7C */ NULL, NULL, NULL, NULL,
15501 /* 80 */ NULL, NULL, NULL, NULL,
15502 /* 84 */ NULL, NULL, NULL, NULL,
15503 /* 88 */ NULL, NULL, "pfnacc", NULL,
15504 /* 8C */ NULL, NULL, "pfpnacc", NULL,
15505 /* 90 */ "pfcmpge", NULL, NULL, NULL,
15506 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
15507 /* 98 */ NULL, NULL, "pfsub", NULL,
15508 /* 9C */ NULL, NULL, "pfadd", NULL,
15509 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
15510 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
15511 /* A8 */ NULL, NULL, "pfsubr", NULL,
15512 /* AC */ NULL, NULL, "pfacc", NULL,
15513 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
15514 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
15515 /* B8 */ NULL, NULL, NULL, "pswapd",
15516 /* BC */ NULL, NULL, NULL, "pavgusb",
15517 /* C0 */ NULL, NULL, NULL, NULL,
15518 /* C4 */ NULL, NULL, NULL, NULL,
15519 /* C8 */ NULL, NULL, NULL, NULL,
15520 /* CC */ NULL, NULL, NULL, NULL,
15521 /* D0 */ NULL, NULL, NULL, NULL,
15522 /* D4 */ NULL, NULL, NULL, NULL,
15523 /* D8 */ NULL, NULL, NULL, NULL,
15524 /* DC */ NULL, NULL, NULL, NULL,
15525 /* E0 */ NULL, NULL, NULL, NULL,
15526 /* E4 */ NULL, NULL, NULL, NULL,
15527 /* E8 */ NULL, NULL, NULL, NULL,
15528 /* EC */ NULL, NULL, NULL, NULL,
15529 /* F0 */ NULL, NULL, NULL, NULL,
15530 /* F4 */ NULL, NULL, NULL, NULL,
15531 /* F8 */ NULL, NULL, NULL, NULL,
15532 /* FC */ NULL, NULL, NULL, NULL,
15536 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15538 const char *mnemonic;
15540 FETCH_DATA (the_info, codep + 1);
15541 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15542 place where an 8-bit immediate would normally go. ie. the last
15543 byte of the instruction. */
15544 obufp = mnemonicendp;
15545 mnemonic = Suffix3DNow[*codep++ & 0xff];
15547 oappend (mnemonic);
15550 /* Since a variable sized modrm/sib chunk is between the start
15551 of the opcode (0x0f0f) and the opcode suffix, we need to do
15552 all the modrm processing first, and don't know until now that
15553 we have a bad opcode. This necessitates some cleaning up. */
15554 op_out[0][0] = '\0';
15555 op_out[1][0] = '\0';
15558 mnemonicendp = obufp;
15561 static struct op simd_cmp_op[] =
15563 { STRING_COMMA_LEN ("eq") },
15564 { STRING_COMMA_LEN ("lt") },
15565 { STRING_COMMA_LEN ("le") },
15566 { STRING_COMMA_LEN ("unord") },
15567 { STRING_COMMA_LEN ("neq") },
15568 { STRING_COMMA_LEN ("nlt") },
15569 { STRING_COMMA_LEN ("nle") },
15570 { STRING_COMMA_LEN ("ord") }
15574 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15576 unsigned int cmp_type;
15578 FETCH_DATA (the_info, codep + 1);
15579 cmp_type = *codep++ & 0xff;
15580 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15583 char *p = mnemonicendp - 2;
15587 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15588 mnemonicendp += simd_cmp_op[cmp_type].len;
15592 /* We have a reserved extension byte. Output it directly. */
15593 scratchbuf[0] = '$';
15594 print_operand_value (scratchbuf + 1, 1, cmp_type);
15595 oappend_maybe_intel (scratchbuf);
15596 scratchbuf[0] = '\0';
15601 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
15602 int sizeflag ATTRIBUTE_UNUSED)
15604 /* mwaitx %eax,%ecx,%ebx */
15607 const char **names = (address_mode == mode_64bit
15608 ? names64 : names32);
15609 strcpy (op_out[0], names[0]);
15610 strcpy (op_out[1], names[1]);
15611 strcpy (op_out[2], names[3]);
15612 two_source_ops = 1;
15614 /* Skip mod/rm byte. */
15620 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15621 int sizeflag ATTRIBUTE_UNUSED)
15623 /* mwait %eax,%ecx */
15626 const char **names = (address_mode == mode_64bit
15627 ? names64 : names32);
15628 strcpy (op_out[0], names[0]);
15629 strcpy (op_out[1], names[1]);
15630 two_source_ops = 1;
15632 /* Skip mod/rm byte. */
15638 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15639 int sizeflag ATTRIBUTE_UNUSED)
15641 /* monitor %eax,%ecx,%edx" */
15644 const char **op1_names;
15645 const char **names = (address_mode == mode_64bit
15646 ? names64 : names32);
15648 if (!(prefixes & PREFIX_ADDR))
15649 op1_names = (address_mode == mode_16bit
15650 ? names16 : names);
15653 /* Remove "addr16/addr32". */
15654 all_prefixes[last_addr_prefix] = 0;
15655 op1_names = (address_mode != mode_32bit
15656 ? names32 : names16);
15657 used_prefixes |= PREFIX_ADDR;
15659 strcpy (op_out[0], op1_names[0]);
15660 strcpy (op_out[1], names[1]);
15661 strcpy (op_out[2], names[2]);
15662 two_source_ops = 1;
15664 /* Skip mod/rm byte. */
15672 /* Throw away prefixes and 1st. opcode byte. */
15673 codep = insn_codep + 1;
15678 REP_Fixup (int bytemode, int sizeflag)
15680 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15682 if (prefixes & PREFIX_REPZ)
15683 all_prefixes[last_repz_prefix] = REP_PREFIX;
15690 OP_IMREG (bytemode, sizeflag);
15693 OP_ESreg (bytemode, sizeflag);
15696 OP_DSreg (bytemode, sizeflag);
15704 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15708 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15710 if (prefixes & PREFIX_REPNZ)
15711 all_prefixes[last_repnz_prefix] = BND_PREFIX;
15714 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15718 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15719 int sizeflag ATTRIBUTE_UNUSED)
15721 if (active_seg_prefix == PREFIX_DS
15722 && (address_mode != mode_64bit || last_data_prefix < 0))
15724 /* NOTRACK prefix is only valid on indirect branch instructions.
15725 NB: DATA prefix is unsupported for Intel64. */
15726 active_seg_prefix = 0;
15727 all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15731 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15732 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15736 HLE_Fixup1 (int bytemode, int sizeflag)
15739 && (prefixes & PREFIX_LOCK) != 0)
15741 if (prefixes & PREFIX_REPZ)
15742 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15743 if (prefixes & PREFIX_REPNZ)
15744 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15747 OP_E (bytemode, sizeflag);
15750 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15751 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15755 HLE_Fixup2 (int bytemode, int sizeflag)
15757 if (modrm.mod != 3)
15759 if (prefixes & PREFIX_REPZ)
15760 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15761 if (prefixes & PREFIX_REPNZ)
15762 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15765 OP_E (bytemode, sizeflag);
15768 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15769 "xrelease" for memory operand. No check for LOCK prefix. */
15772 HLE_Fixup3 (int bytemode, int sizeflag)
15775 && last_repz_prefix > last_repnz_prefix
15776 && (prefixes & PREFIX_REPZ) != 0)
15777 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15779 OP_E (bytemode, sizeflag);
15783 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15788 /* Change cmpxchg8b to cmpxchg16b. */
15789 char *p = mnemonicendp - 2;
15790 mnemonicendp = stpcpy (p, "16b");
15793 else if ((prefixes & PREFIX_LOCK) != 0)
15795 if (prefixes & PREFIX_REPZ)
15796 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15797 if (prefixes & PREFIX_REPNZ)
15798 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15801 OP_M (bytemode, sizeflag);
15805 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15807 const char **names;
15811 switch (vex.length)
15825 oappend (names[reg]);
15829 CRC32_Fixup (int bytemode, int sizeflag)
15831 /* Add proper suffix to "crc32". */
15832 char *p = mnemonicendp;
15851 if (sizeflag & DFLAG)
15855 used_prefixes |= (prefixes & PREFIX_DATA);
15859 oappend (INTERNAL_DISASSEMBLER_ERROR);
15866 if (modrm.mod == 3)
15870 /* Skip mod/rm byte. */
15875 add = (rex & REX_B) ? 8 : 0;
15876 if (bytemode == b_mode)
15880 oappend (names8rex[modrm.rm + add]);
15882 oappend (names8[modrm.rm + add]);
15888 oappend (names64[modrm.rm + add]);
15889 else if ((prefixes & PREFIX_DATA))
15890 oappend (names16[modrm.rm + add]);
15892 oappend (names32[modrm.rm + add]);
15896 OP_E (bytemode, sizeflag);
15900 FXSAVE_Fixup (int bytemode, int sizeflag)
15902 /* Add proper suffix to "fxsave" and "fxrstor". */
15906 char *p = mnemonicendp;
15912 OP_M (bytemode, sizeflag);
15916 PCMPESTR_Fixup (int bytemode, int sizeflag)
15918 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15921 char *p = mnemonicendp;
15926 else if (sizeflag & SUFFIX_ALWAYS)
15933 OP_EX (bytemode, sizeflag);
15936 /* Display the destination register operand for instructions with
15940 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15943 const char **names;
15951 reg = vex.register_specifier;
15952 vex.register_specifier = 0;
15953 if (address_mode != mode_64bit)
15955 else if (vex.evex && !vex.v)
15958 if (bytemode == vex_scalar_mode)
15960 oappend (names_xmm[reg]);
15964 switch (vex.length)
15971 case vex_vsib_q_w_dq_mode:
15972 case vex_vsib_q_w_d_mode:
15988 names = names_mask;
16002 case vex_vsib_q_w_dq_mode:
16003 case vex_vsib_q_w_d_mode:
16004 names = vex.w ? names_ymm : names_xmm;
16013 names = names_mask;
16016 /* See PR binutils/20893 for a reproducer. */
16028 oappend (names[reg]);
16031 /* Get the VEX immediate byte without moving codep. */
16033 static unsigned char
16034 get_vex_imm8 (int sizeflag, int opnum)
16036 int bytes_before_imm = 0;
16038 if (modrm.mod != 3)
16040 /* There are SIB/displacement bytes. */
16041 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16043 /* 32/64 bit address mode */
16044 int base = modrm.rm;
16046 /* Check SIB byte. */
16049 FETCH_DATA (the_info, codep + 1);
16051 /* When decoding the third source, don't increase
16052 bytes_before_imm as this has already been incremented
16053 by one in OP_E_memory while decoding the second
16056 bytes_before_imm++;
16059 /* Don't increase bytes_before_imm when decoding the third source,
16060 it has already been incremented by OP_E_memory while decoding
16061 the second source operand. */
16067 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16068 SIB == 5, there is a 4 byte displacement. */
16070 /* No displacement. */
16072 /* Fall through. */
16074 /* 4 byte displacement. */
16075 bytes_before_imm += 4;
16078 /* 1 byte displacement. */
16079 bytes_before_imm++;
16086 /* 16 bit address mode */
16087 /* Don't increase bytes_before_imm when decoding the third source,
16088 it has already been incremented by OP_E_memory while decoding
16089 the second source operand. */
16095 /* When modrm.rm == 6, there is a 2 byte displacement. */
16097 /* No displacement. */
16099 /* Fall through. */
16101 /* 2 byte displacement. */
16102 bytes_before_imm += 2;
16105 /* 1 byte displacement: when decoding the third source,
16106 don't increase bytes_before_imm as this has already
16107 been incremented by one in OP_E_memory while decoding
16108 the second source operand. */
16110 bytes_before_imm++;
16118 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16119 return codep [bytes_before_imm];
16123 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16125 const char **names;
16127 if (reg == -1 && modrm.mod != 3)
16129 OP_E_memory (bytemode, sizeflag);
16141 if (address_mode != mode_64bit)
16145 switch (vex.length)
16156 oappend (names[reg]);
16160 OP_EX_VexImmW (int bytemode, int sizeflag)
16163 static unsigned char vex_imm8;
16165 if (vex_w_done == 0)
16169 /* Skip mod/rm byte. */
16173 vex_imm8 = get_vex_imm8 (sizeflag, 0);
16176 reg = vex_imm8 >> 4;
16178 OP_EX_VexReg (bytemode, sizeflag, reg);
16180 else if (vex_w_done == 1)
16185 reg = vex_imm8 >> 4;
16187 OP_EX_VexReg (bytemode, sizeflag, reg);
16191 /* Output the imm8 directly. */
16192 scratchbuf[0] = '$';
16193 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16194 oappend_maybe_intel (scratchbuf);
16195 scratchbuf[0] = '\0';
16201 OP_Vex_2src (int bytemode, int sizeflag)
16203 if (modrm.mod == 3)
16205 int reg = modrm.rm;
16209 oappend (names_xmm[reg]);
16214 && (bytemode == v_mode || bytemode == v_swap_mode))
16216 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16217 used_prefixes |= (prefixes & PREFIX_DATA);
16219 OP_E (bytemode, sizeflag);
16224 OP_Vex_2src_1 (int bytemode, int sizeflag)
16226 if (modrm.mod == 3)
16228 /* Skip mod/rm byte. */
16235 unsigned int reg = vex.register_specifier;
16236 vex.register_specifier = 0;
16238 if (address_mode != mode_64bit)
16240 oappend (names_xmm[reg]);
16243 OP_Vex_2src (bytemode, sizeflag);
16247 OP_Vex_2src_2 (int bytemode, int sizeflag)
16250 OP_Vex_2src (bytemode, sizeflag);
16253 unsigned int reg = vex.register_specifier;
16254 vex.register_specifier = 0;
16256 if (address_mode != mode_64bit)
16258 oappend (names_xmm[reg]);
16263 OP_EX_VexW (int bytemode, int sizeflag)
16269 /* Skip mod/rm byte. */
16274 reg = get_vex_imm8 (sizeflag, 0) >> 4;
16279 reg = get_vex_imm8 (sizeflag, 1) >> 4;
16282 OP_EX_VexReg (bytemode, sizeflag, reg);
16290 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16293 const char **names;
16295 FETCH_DATA (the_info, codep + 1);
16298 if (bytemode != x_mode)
16302 if (address_mode != mode_64bit)
16305 switch (vex.length)
16316 oappend (names[reg]);
16320 OP_XMM_VexW (int bytemode, int sizeflag)
16322 /* Turn off the REX.W bit since it is used for swapping operands
16325 OP_XMM (bytemode, sizeflag);
16329 OP_EX_Vex (int bytemode, int sizeflag)
16331 if (modrm.mod != 3)
16333 OP_EX (bytemode, sizeflag);
16337 OP_XMM_Vex (int bytemode, int sizeflag)
16339 if (modrm.mod != 3)
16341 OP_XMM (bytemode, sizeflag);
16344 static struct op vex_cmp_op[] =
16346 { STRING_COMMA_LEN ("eq") },
16347 { STRING_COMMA_LEN ("lt") },
16348 { STRING_COMMA_LEN ("le") },
16349 { STRING_COMMA_LEN ("unord") },
16350 { STRING_COMMA_LEN ("neq") },
16351 { STRING_COMMA_LEN ("nlt") },
16352 { STRING_COMMA_LEN ("nle") },
16353 { STRING_COMMA_LEN ("ord") },
16354 { STRING_COMMA_LEN ("eq_uq") },
16355 { STRING_COMMA_LEN ("nge") },
16356 { STRING_COMMA_LEN ("ngt") },
16357 { STRING_COMMA_LEN ("false") },
16358 { STRING_COMMA_LEN ("neq_oq") },
16359 { STRING_COMMA_LEN ("ge") },
16360 { STRING_COMMA_LEN ("gt") },
16361 { STRING_COMMA_LEN ("true") },
16362 { STRING_COMMA_LEN ("eq_os") },
16363 { STRING_COMMA_LEN ("lt_oq") },
16364 { STRING_COMMA_LEN ("le_oq") },
16365 { STRING_COMMA_LEN ("unord_s") },
16366 { STRING_COMMA_LEN ("neq_us") },
16367 { STRING_COMMA_LEN ("nlt_uq") },
16368 { STRING_COMMA_LEN ("nle_uq") },
16369 { STRING_COMMA_LEN ("ord_s") },
16370 { STRING_COMMA_LEN ("eq_us") },
16371 { STRING_COMMA_LEN ("nge_uq") },
16372 { STRING_COMMA_LEN ("ngt_uq") },
16373 { STRING_COMMA_LEN ("false_os") },
16374 { STRING_COMMA_LEN ("neq_os") },
16375 { STRING_COMMA_LEN ("ge_oq") },
16376 { STRING_COMMA_LEN ("gt_oq") },
16377 { STRING_COMMA_LEN ("true_us") },
16381 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16383 unsigned int cmp_type;
16385 FETCH_DATA (the_info, codep + 1);
16386 cmp_type = *codep++ & 0xff;
16387 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16390 char *p = mnemonicendp - 2;
16394 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16395 mnemonicendp += vex_cmp_op[cmp_type].len;
16399 /* We have a reserved extension byte. Output it directly. */
16400 scratchbuf[0] = '$';
16401 print_operand_value (scratchbuf + 1, 1, cmp_type);
16402 oappend_maybe_intel (scratchbuf);
16403 scratchbuf[0] = '\0';
16408 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16409 int sizeflag ATTRIBUTE_UNUSED)
16411 unsigned int cmp_type;
16416 FETCH_DATA (the_info, codep + 1);
16417 cmp_type = *codep++ & 0xff;
16418 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16419 If it's the case, print suffix, otherwise - print the immediate. */
16420 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16425 char *p = mnemonicendp - 2;
16427 /* vpcmp* can have both one- and two-lettered suffix. */
16441 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16442 mnemonicendp += simd_cmp_op[cmp_type].len;
16446 /* We have a reserved extension byte. Output it directly. */
16447 scratchbuf[0] = '$';
16448 print_operand_value (scratchbuf + 1, 1, cmp_type);
16449 oappend_maybe_intel (scratchbuf);
16450 scratchbuf[0] = '\0';
16454 static const struct op xop_cmp_op[] =
16456 { STRING_COMMA_LEN ("lt") },
16457 { STRING_COMMA_LEN ("le") },
16458 { STRING_COMMA_LEN ("gt") },
16459 { STRING_COMMA_LEN ("ge") },
16460 { STRING_COMMA_LEN ("eq") },
16461 { STRING_COMMA_LEN ("neq") },
16462 { STRING_COMMA_LEN ("false") },
16463 { STRING_COMMA_LEN ("true") }
16467 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16468 int sizeflag ATTRIBUTE_UNUSED)
16470 unsigned int cmp_type;
16472 FETCH_DATA (the_info, codep + 1);
16473 cmp_type = *codep++ & 0xff;
16474 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16477 char *p = mnemonicendp - 2;
16479 /* vpcom* can have both one- and two-lettered suffix. */
16493 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16494 mnemonicendp += xop_cmp_op[cmp_type].len;
16498 /* We have a reserved extension byte. Output it directly. */
16499 scratchbuf[0] = '$';
16500 print_operand_value (scratchbuf + 1, 1, cmp_type);
16501 oappend_maybe_intel (scratchbuf);
16502 scratchbuf[0] = '\0';
16506 static const struct op pclmul_op[] =
16508 { STRING_COMMA_LEN ("lql") },
16509 { STRING_COMMA_LEN ("hql") },
16510 { STRING_COMMA_LEN ("lqh") },
16511 { STRING_COMMA_LEN ("hqh") }
16515 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16516 int sizeflag ATTRIBUTE_UNUSED)
16518 unsigned int pclmul_type;
16520 FETCH_DATA (the_info, codep + 1);
16521 pclmul_type = *codep++ & 0xff;
16522 switch (pclmul_type)
16533 if (pclmul_type < ARRAY_SIZE (pclmul_op))
16536 char *p = mnemonicendp - 3;
16541 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16542 mnemonicendp += pclmul_op[pclmul_type].len;
16546 /* We have a reserved extension byte. Output it directly. */
16547 scratchbuf[0] = '$';
16548 print_operand_value (scratchbuf + 1, 1, pclmul_type);
16549 oappend_maybe_intel (scratchbuf);
16550 scratchbuf[0] = '\0';
16555 MOVBE_Fixup (int bytemode, int sizeflag)
16557 /* Add proper suffix to "movbe". */
16558 char *p = mnemonicendp;
16567 if (sizeflag & SUFFIX_ALWAYS)
16573 if (sizeflag & DFLAG)
16577 used_prefixes |= (prefixes & PREFIX_DATA);
16582 oappend (INTERNAL_DISASSEMBLER_ERROR);
16589 OP_M (bytemode, sizeflag);
16593 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16596 const char **names;
16598 /* Skip mod/rm byte. */
16612 oappend (names[reg]);
16616 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16618 const char **names;
16619 unsigned int reg = vex.register_specifier;
16620 vex.register_specifier = 0;
16627 if (address_mode != mode_64bit)
16629 oappend (names[reg]);
16633 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16636 || (bytemode != mask_mode && bytemode != mask_bd_mode))
16640 if ((rex & REX_R) != 0 || !vex.r)
16646 oappend (names_mask [modrm.reg]);
16650 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16653 || (bytemode != evex_rounding_mode
16654 && bytemode != evex_rounding_64_mode
16655 && bytemode != evex_sae_mode))
16657 if (modrm.mod == 3 && vex.b)
16660 case evex_rounding_64_mode:
16661 if (address_mode != mode_64bit)
16666 /* Fall through. */
16667 case evex_rounding_mode:
16668 oappend (names_rounding[vex.ll]);
16670 case evex_sae_mode: