1 /* Disassembler for the PA-RISC. Somewhat derived from sparc-pinsn.c.
2 Copyright 1989, 1990, 1992, 1993 Free Software Foundation, Inc.
4 Contributed by the Center for Software Science at the
5 University of Utah (pa-gdb-bugs@cs.utah.edu).
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
25 #include "opcode/hppa.h"
27 /* Integer register names, indexed by the numbers which appear in the
29 static const char *const reg_names[] =
30 {"flags", "r1", "rp", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
31 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
32 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "dp", "ret0", "ret1",
35 /* Floating point register names, indexed by the numbers which appear in the
37 static const char *const fp_reg_names[] =
38 {"fpsr", "fpe2", "fpe4", "fpe6",
39 "fr4", "fr5", "fr6", "fr7", "fr8",
40 "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
41 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
42 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31"};
44 typedef unsigned int CORE_ADDR;
46 /* Get at various relevent fields of an instruction word. */
50 #define MASK_14 0x3fff
51 #define MASK_21 0x1fffff
53 /* This macro gets bit fields using HP's numbering (MSB = 0) */
55 #define GET_FIELD(X, FROM, TO) \
56 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
58 /* Some of these have been converted to 2-d arrays because they
59 consume less storage this way. If the maintenance becomes a
60 problem, convert them back to const 1-d pointer arrays. */
61 static const char control_reg[][6] = {
62 "rctr", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
63 "pidr1", "pidr2", "ccr", "sar", "pidr3", "pidr4",
64 "iva", "eiem", "itmr", "pcsq", "pcoq", "iir", "isr",
65 "ior", "ipsw", "eirr", "tr0", "tr1", "tr2", "tr3",
66 "tr4", "tr5", "tr6", "tr7"
69 static const char compare_cond_names[][5] = {
70 "", ",=", ",<", ",<=", ",<<", ",<<=", ",sv",
71 ",od", ",tr", ",<>", ",>=", ",>", ",>>=",
74 static const char add_cond_names[][5] = {
75 "", ",=", ",<", ",<=", ",nuv", ",znv", ",sv",
76 ",od", ",tr", ",<>", ",>=", ",>", ",uv",
79 static const char *const logical_cond_names[] = {
80 "", ",=", ",<", ",<=", 0, 0, 0, ",od",
81 ",tr", ",<>", ",>=", ",>", 0, 0, 0, ",ev"};
82 static const char *const unit_cond_names[] = {
83 "", 0, ",sbz", ",shz", ",sdc", 0, ",sbc", ",shc",
84 ",tr", 0, ",nbz", ",nhz", ",ndc", 0, ",nbc", ",nhc"
86 static const char shift_cond_names[][4] = {
87 "", ",=", ",<", ",od", ",tr", ",<>", ",>=", ",ev"
89 static const char index_compl_names[][4] = {"", ",m", ",s", ",sm"};
90 static const char short_ldst_compl_names[][4] = {"", ",ma", "", ",mb"};
91 static const char *const short_bytes_compl_names[] = {
92 "", ",b,m", ",e", ",e,m"
94 static const char *const float_format_names[] = {",sgl", ",dbl", "", ",quad"};
95 static const char float_comp_names[][8] =
97 ",false?", ",false", ",?", ",!<=>", ",=", ",=t", ",?=", ",!<>",
98 ",!?>=", ",<", ",?<", ",!>=", ",!?>", ",<=", ",?<=", ",!>",
99 ",!?<=", ",>", ",?>", ",!<=", ",!?<", ",>=", ",?>=", ",!<",
100 ",!?=", ",<>", ",!=", ",!=t", ",!?", ",<=>", ",true?", ",true"
103 /* For a bunch of different instructions form an index into a
104 completer name table. */
105 #define GET_COMPL(insn) (GET_FIELD (insn, 26, 26) | \
106 GET_FIELD (insn, 18, 18) << 1)
108 #define GET_COND(insn) (GET_FIELD ((insn), 16, 18) + \
109 (GET_FIELD ((insn), 19, 19) ? 8 : 0))
111 /* Utility function to print registers. Put these first, so gcc's function
112 inlining can do its stuff. */
114 #define fputs_filtered(STR,F) (*info->fprintf_func) (info->stream, "%s", STR)
119 disassemble_info *info;
121 (*info->fprintf_func) (info->stream, reg ? reg_names[reg] : "r0");
125 fput_fp_reg (reg, info)
127 disassemble_info *info;
129 (*info->fprintf_func) (info->stream, reg ? fp_reg_names[reg] : "fr0");
133 fput_fp_reg_r (reg, info)
135 disassemble_info *info;
137 /* Special case floating point exception registers. */
139 (*info->fprintf_func) (info->stream, "fpe%d", reg * 2 + 1);
141 (*info->fprintf_func) (info->stream, "%sR", reg ? fp_reg_names[reg]
146 fput_creg (reg, info)
148 disassemble_info *info;
150 (*info->fprintf_func) (info->stream, control_reg[reg]);
153 /* print constants with sign */
156 fput_const (num, info)
158 disassemble_info *info;
161 (*info->fprintf_func) (info->stream, "-%x", -(int)num);
163 (*info->fprintf_func) (info->stream, "%x", num);
166 /* Routines to extract various sized constants out of hppa
169 /* extract a 3-bit space register number from a be, ble, mtsp or mfsp */
174 return GET_FIELD (word, 18, 18) << 2 | GET_FIELD (word, 16, 17);
178 extract_5_load (word)
181 return low_sign_extend (word >> 16 & MASK_5, 5);
184 /* extract the immediate field from a st{bhw}s instruction */
186 extract_5_store (word)
189 return low_sign_extend (word & MASK_5, 5);
192 /* extract the immediate field from a break instruction */
194 extract_5r_store (word)
197 return (word & MASK_5);
200 /* extract the immediate field from a {sr}sm instruction */
202 extract_5R_store (word)
205 return (word >> 16 & MASK_5);
208 /* extract the immediate field from a bb instruction */
210 extract_5Q_store (word)
213 return (word >> 21 & MASK_5);
216 /* extract an 11 bit immediate field */
221 return low_sign_extend (word & MASK_11, 11);
224 /* extract a 14 bit immediate field */
229 return low_sign_extend (word & MASK_14, 14);
232 /* extract a 21 bit constant */
242 val = GET_FIELD (word, 20, 20);
244 val |= GET_FIELD (word, 9, 19);
246 val |= GET_FIELD (word, 5, 6);
248 val |= GET_FIELD (word, 0, 4);
250 val |= GET_FIELD (word, 7, 8);
251 return sign_extend (val, 21) << 11;
254 /* extract a 12 bit constant from branch instructions */
260 return sign_extend (GET_FIELD (word, 19, 28) |
261 GET_FIELD (word, 29, 29) << 10 |
262 (word & 0x1) << 11, 12) << 2;
265 /* extract a 17 bit constant from branch instructions, returning the
266 19 bit signed value. */
272 return sign_extend (GET_FIELD (word, 19, 28) |
273 GET_FIELD (word, 29, 29) << 10 |
274 GET_FIELD (word, 11, 15) << 11 |
275 (word & 0x1) << 16, 17) << 2;
278 /* Print one instruction. */
280 print_insn_hppa (memaddr, info)
282 disassemble_info *info;
285 unsigned int insn, i;
289 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
292 (*info->memory_error_func) (status, memaddr, info);
297 insn = bfd_getb32 (buffer);
299 for (i = 0; i < NUMOPCODES; ++i)
301 const struct pa_opcode *opcode = &pa_opcodes[i];
302 if ((insn & opcode->mask) == opcode->match)
304 register const char *s;
306 (*info->fprintf_func) (info->stream, "%s", opcode->name);
308 if (!strchr ("cfCY<?!@-+&U>~nHNZFIMadu|", opcode->args[0]))
309 (*info->fprintf_func) (info->stream, " ");
310 for (s = opcode->args; *s != '\0'; ++s)
315 fput_reg (GET_FIELD (insn, 11, 15), info);
318 if (GET_FIELD (insn, 25, 25))
319 fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
321 fput_fp_reg (GET_FIELD (insn, 11, 15), info);
324 fput_reg (GET_FIELD (insn, 6, 10), info);
327 fput_creg (GET_FIELD (insn, 6, 10), info);
330 fput_fp_reg (GET_FIELD (insn, 6, 10), info);
333 fput_reg (GET_FIELD (insn, 27, 31), info);
336 if (GET_FIELD (insn, 25, 25))
337 fput_fp_reg_r (GET_FIELD (insn, 27, 31), info);
339 fput_fp_reg (GET_FIELD (insn, 27, 31), info);
342 fput_fp_reg (GET_FIELD (insn, 27, 31), info);
346 int reg = GET_FIELD (insn, 6, 10);
348 reg |= (GET_FIELD (insn, 26, 26) << 4);
349 fput_fp_reg (reg, info);
354 int reg = GET_FIELD (insn, 11, 15);
356 reg |= (GET_FIELD (insn, 26, 26) << 4);
357 fput_fp_reg (reg, info);
362 int reg = GET_FIELD (insn, 27, 31);
364 reg |= (GET_FIELD (insn, 26, 26) << 4);
365 fput_fp_reg (reg, info);
370 int reg = GET_FIELD (insn, 16, 20);
372 reg |= (GET_FIELD (insn, 26, 26) << 4);
373 fput_fp_reg (reg, info);
378 int reg = GET_FIELD (insn, 21, 25);
380 reg |= (GET_FIELD (insn, 26, 26) << 4);
381 fput_fp_reg (reg, info);
385 fput_const (extract_5_load (insn), info);
388 (*info->fprintf_func) (info->stream,
389 "sr%d", GET_FIELD (insn, 16, 17));
392 (*info->fprintf_func) (info->stream, "sr%d", extract_3 (insn));
395 (*info->fprintf_func) (info->stream, "%s ",
396 index_compl_names[GET_COMPL (insn)]);
399 (*info->fprintf_func) (info->stream, "%s ",
400 short_ldst_compl_names[GET_COMPL (insn)]);
403 (*info->fprintf_func) (info->stream, "%s ",
404 short_bytes_compl_names[GET_COMPL (insn)]);
406 /* these four conditions are for the set of instructions
407 which distinguish true/false conditions by opcode rather
408 than by the 'f' bit (sigh): comb, comib, addb, addib */
410 fputs_filtered (compare_cond_names[GET_FIELD (insn, 16, 18)],
414 fputs_filtered (compare_cond_names[GET_FIELD (insn, 16, 18)
415 + GET_FIELD (insn, 4, 4) * 8], info);
418 fputs_filtered (add_cond_names[GET_FIELD (insn, 16, 18)
419 + GET_FIELD (insn, 4, 4) * 8], info);
422 (*info->fprintf_func) (info->stream, "%s ",
423 compare_cond_names[GET_COND (insn)]);
426 (*info->fprintf_func) (info->stream, "%s ",
427 add_cond_names[GET_COND (insn)]);
430 (*info->fprintf_func) (info->stream, "%s",
431 add_cond_names[GET_FIELD (insn, 16, 18)]);
435 (*info->fprintf_func) (info->stream, "%s ",
436 logical_cond_names[GET_COND (insn)]);
439 (*info->fprintf_func) (info->stream, "%s ",
440 unit_cond_names[GET_COND (insn)]);
445 (*info->fprintf_func)
447 shift_cond_names[GET_FIELD (insn, 16, 18)]);
449 /* If the next character in args is 'n', it will handle
450 putting out the space. */
452 (*info->fprintf_func) (info->stream, " ");
455 fput_const (extract_5_store (insn), info);
458 fput_const (extract_5r_store (insn), info);
461 fput_const (extract_5R_store (insn), info);
464 fput_const (extract_5Q_store (insn), info);
467 fput_const (extract_11 (insn), info);
470 fput_const (extract_14 (insn), info);
473 fput_const (extract_21 (insn), info);
477 (*info->fprintf_func) (info->stream, ",n ");
479 (*info->fprintf_func) (info->stream, " ");
482 if ((insn & 0x20) && s[1])
483 (*info->fprintf_func) (info->stream, ",n ");
484 else if (insn & 0x20)
485 (*info->fprintf_func) (info->stream, ",n");
487 (*info->fprintf_func) (info->stream, " ");
490 (*info->print_address_func) (memaddr + 8 + extract_12 (insn),
494 /* 17 bit PC-relative branch. */
495 (*info->print_address_func) ((memaddr + 8
496 + extract_17 (insn)),
500 /* 17 bit displacement. This is an offset from a register
501 so it gets disasssembled as just a number, not any sort
503 fput_const (extract_17 (insn), info);
506 (*info->fprintf_func) (info->stream, "%d",
507 31 - GET_FIELD (insn, 22, 26));
510 (*info->fprintf_func) (info->stream, "%d",
511 GET_FIELD (insn, 22, 26));
514 (*info->fprintf_func) (info->stream, "%d",
515 32 - GET_FIELD (insn, 27, 31));
518 fput_const (GET_FIELD (insn, 6, 18), info);
521 if (GET_FIELD (insn, 26, 26))
522 (*info->fprintf_func) (info->stream, ",m ");
524 (*info->fprintf_func) (info->stream, " ");
527 fput_const (GET_FIELD (insn, 6, 31), info);
530 (*info->fprintf_func) (info->stream, ",%d", GET_FIELD (insn, 23, 25));
533 fput_const ((GET_FIELD (insn, 6,20) << 5 |
534 GET_FIELD (insn, 27, 31)), info);
537 fput_const (GET_FIELD (insn, 6, 20), info);
541 int reg = GET_FIELD (insn, 21, 22);
542 reg |= GET_FIELD (insn, 16, 18) << 2;
543 if (GET_FIELD (insn, 23, 23) != 0)
544 fput_fp_reg_r (reg, info);
546 fput_fp_reg (reg, info);
551 fput_const ((GET_FIELD (insn, 6, 22) << 5 |
552 GET_FIELD (insn, 27, 31)), info);
555 fput_const ((GET_FIELD (insn, 11, 20) << 5 |
556 GET_FIELD (insn, 27, 31)), info);
559 fput_const ((GET_FIELD (insn, 16, 20) << 5 |
560 GET_FIELD (insn, 27, 31)), info);
563 (*info->fprintf_func) (info->stream, ",%d", GET_FIELD (insn, 23, 25));
566 /* if no destination completer and not before a completer
567 for fcmp, need a space here */
568 if (GET_FIELD (insn, 21, 22) == 1 || s[1] == 'M')
569 fputs_filtered (float_format_names[GET_FIELD (insn, 19, 20)],
572 (*info->fprintf_func) (info->stream, "%s ",
573 float_format_names[GET_FIELD
577 (*info->fprintf_func) (info->stream, "%s ",
578 float_format_names[GET_FIELD (insn,
582 if (GET_FIELD (insn, 26, 26) == 1)
583 (*info->fprintf_func) (info->stream, "%s ",
584 float_format_names[0]);
586 (*info->fprintf_func) (info->stream, "%s ",
587 float_format_names[1]);
590 /* if no destination completer and not before a completer
591 for fcmp, need a space here */
592 if (GET_FIELD (insn, 21, 22) == 1 || s[1] == 'M')
593 fputs_filtered (float_format_names[GET_FIELD (insn, 20, 20)],
596 (*info->fprintf_func) (info->stream, "%s ",
597 float_format_names[GET_FIELD
601 if (GET_FIELD (insn, 24, 24))
602 fput_fp_reg_r (GET_FIELD (insn, 6, 10), info);
604 fput_fp_reg (GET_FIELD (insn, 6, 10), info);
608 if (GET_FIELD (insn, 19, 19))
609 fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
611 fput_fp_reg (GET_FIELD (insn, 11, 15), info);
614 (*info->fprintf_func) (info->stream, "%s ",
615 float_comp_names[GET_FIELD
619 (*info->fprintf_func) (info->stream, "%c", *s);
626 (*info->fprintf_func) (info->stream, "#%8x", insn);