3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
34 #include "libiberty.h"
39 static const CGEN_ATTR_ENTRY bool_attr[] =
46 static const CGEN_ATTR_ENTRY MACH_attr[] =
48 { "base", MACH_BASE },
50 { "fr500", MACH_FR500 },
51 { "fr400", MACH_FR400 },
52 { "tomcat", MACH_TOMCAT },
53 { "simple", MACH_SIMPLE },
58 static const CGEN_ATTR_ENTRY ISA_attr[] =
65 static const CGEN_ATTR_ENTRY UNIT_attr[] =
73 { "FM01", UNIT_FM01 },
78 { "MULT_DIV", UNIT_MULT_DIV },
79 { "LOAD", UNIT_LOAD },
80 { "NUM_UNITS", UNIT_NUM_UNITS },
84 static const CGEN_ATTR_ENTRY FR400_MAJOR_attr[] =
86 { "NONE", FR400_MAJOR_NONE },
87 { "I_1", FR400_MAJOR_I_1 },
88 { "I_2", FR400_MAJOR_I_2 },
89 { "I_3", FR400_MAJOR_I_3 },
90 { "I_4", FR400_MAJOR_I_4 },
91 { "I_5", FR400_MAJOR_I_5 },
92 { "B_1", FR400_MAJOR_B_1 },
93 { "B_2", FR400_MAJOR_B_2 },
94 { "B_3", FR400_MAJOR_B_3 },
95 { "B_4", FR400_MAJOR_B_4 },
96 { "B_5", FR400_MAJOR_B_5 },
97 { "B_6", FR400_MAJOR_B_6 },
98 { "C_1", FR400_MAJOR_C_1 },
99 { "C_2", FR400_MAJOR_C_2 },
100 { "M_1", FR400_MAJOR_M_1 },
101 { "M_2", FR400_MAJOR_M_2 },
105 static const CGEN_ATTR_ENTRY FR500_MAJOR_attr[] =
107 { "NONE", FR500_MAJOR_NONE },
108 { "I_1", FR500_MAJOR_I_1 },
109 { "I_2", FR500_MAJOR_I_2 },
110 { "I_3", FR500_MAJOR_I_3 },
111 { "I_4", FR500_MAJOR_I_4 },
112 { "I_5", FR500_MAJOR_I_5 },
113 { "I_6", FR500_MAJOR_I_6 },
114 { "B_1", FR500_MAJOR_B_1 },
115 { "B_2", FR500_MAJOR_B_2 },
116 { "B_3", FR500_MAJOR_B_3 },
117 { "B_4", FR500_MAJOR_B_4 },
118 { "B_5", FR500_MAJOR_B_5 },
119 { "B_6", FR500_MAJOR_B_6 },
120 { "C_1", FR500_MAJOR_C_1 },
121 { "C_2", FR500_MAJOR_C_2 },
122 { "F_1", FR500_MAJOR_F_1 },
123 { "F_2", FR500_MAJOR_F_2 },
124 { "F_3", FR500_MAJOR_F_3 },
125 { "F_4", FR500_MAJOR_F_4 },
126 { "F_5", FR500_MAJOR_F_5 },
127 { "F_6", FR500_MAJOR_F_6 },
128 { "F_7", FR500_MAJOR_F_7 },
129 { "F_8", FR500_MAJOR_F_8 },
130 { "M_1", FR500_MAJOR_M_1 },
131 { "M_2", FR500_MAJOR_M_2 },
132 { "M_3", FR500_MAJOR_M_3 },
133 { "M_4", FR500_MAJOR_M_4 },
134 { "M_5", FR500_MAJOR_M_5 },
135 { "M_6", FR500_MAJOR_M_6 },
136 { "M_7", FR500_MAJOR_M_7 },
137 { "M_8", FR500_MAJOR_M_8 },
141 const CGEN_ATTR_TABLE frv_cgen_ifield_attr_table[] =
143 { "MACH", & MACH_attr[0], & MACH_attr[0] },
144 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
145 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
146 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
147 { "RESERVED", &bool_attr[0], &bool_attr[0] },
148 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
149 { "SIGNED", &bool_attr[0], &bool_attr[0] },
153 const CGEN_ATTR_TABLE frv_cgen_hardware_attr_table[] =
155 { "MACH", & MACH_attr[0], & MACH_attr[0] },
156 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
157 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
158 { "PC", &bool_attr[0], &bool_attr[0] },
159 { "PROFILE", &bool_attr[0], &bool_attr[0] },
163 const CGEN_ATTR_TABLE frv_cgen_operand_attr_table[] =
165 { "MACH", & MACH_attr[0], & MACH_attr[0] },
166 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
167 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
168 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
169 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
170 { "SIGNED", &bool_attr[0], &bool_attr[0] },
171 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
172 { "RELAX", &bool_attr[0], &bool_attr[0] },
173 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
174 { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
178 const CGEN_ATTR_TABLE frv_cgen_insn_attr_table[] =
180 { "MACH", & MACH_attr[0], & MACH_attr[0] },
181 { "UNIT", & UNIT_attr[0], & UNIT_attr[0] },
182 { "FR400-MAJOR", & FR400_MAJOR_attr[0], & FR400_MAJOR_attr[0] },
183 { "FR500-MAJOR", & FR500_MAJOR_attr[0], & FR500_MAJOR_attr[0] },
184 { "ALIAS", &bool_attr[0], &bool_attr[0] },
185 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
186 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
187 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
188 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
189 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
190 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
191 { "RELAXED", &bool_attr[0], &bool_attr[0] },
192 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
193 { "PBB", &bool_attr[0], &bool_attr[0] },
194 { "PRIVILEGED", &bool_attr[0], &bool_attr[0] },
195 { "NON-EXCEPTING", &bool_attr[0], &bool_attr[0] },
196 { "CONDITIONAL", &bool_attr[0], &bool_attr[0] },
197 { "FR-ACCESS", &bool_attr[0], &bool_attr[0] },
198 { "PRESERVE-OVF", &bool_attr[0], &bool_attr[0] },
202 /* Instruction set variants. */
204 static const CGEN_ISA frv_cgen_isa_table[] = {
205 { "frv", 32, 32, 32, 32 },
209 /* Machine variants. */
211 static const CGEN_MACH frv_cgen_mach_table[] = {
212 { "frv", "frv", MACH_FRV, 0 },
213 { "fr500", "fr500", MACH_FR500, 0 },
214 { "tomcat", "tomcat", MACH_TOMCAT, 0 },
215 { "fr400", "fr400", MACH_FR400, 0 },
216 { "simple", "simple", MACH_SIMPLE, 0 },
220 static CGEN_KEYWORD_ENTRY frv_cgen_opval_gr_names_entries[] =
222 { "sp", 1, {0, {0}}, 0, 0 },
223 { "fp", 2, {0, {0}}, 0, 0 },
224 { "gr0", 0, {0, {0}}, 0, 0 },
225 { "gr1", 1, {0, {0}}, 0, 0 },
226 { "gr2", 2, {0, {0}}, 0, 0 },
227 { "gr3", 3, {0, {0}}, 0, 0 },
228 { "gr4", 4, {0, {0}}, 0, 0 },
229 { "gr5", 5, {0, {0}}, 0, 0 },
230 { "gr6", 6, {0, {0}}, 0, 0 },
231 { "gr7", 7, {0, {0}}, 0, 0 },
232 { "gr8", 8, {0, {0}}, 0, 0 },
233 { "gr9", 9, {0, {0}}, 0, 0 },
234 { "gr10", 10, {0, {0}}, 0, 0 },
235 { "gr11", 11, {0, {0}}, 0, 0 },
236 { "gr12", 12, {0, {0}}, 0, 0 },
237 { "gr13", 13, {0, {0}}, 0, 0 },
238 { "gr14", 14, {0, {0}}, 0, 0 },
239 { "gr15", 15, {0, {0}}, 0, 0 },
240 { "gr16", 16, {0, {0}}, 0, 0 },
241 { "gr17", 17, {0, {0}}, 0, 0 },
242 { "gr18", 18, {0, {0}}, 0, 0 },
243 { "gr19", 19, {0, {0}}, 0, 0 },
244 { "gr20", 20, {0, {0}}, 0, 0 },
245 { "gr21", 21, {0, {0}}, 0, 0 },
246 { "gr22", 22, {0, {0}}, 0, 0 },
247 { "gr23", 23, {0, {0}}, 0, 0 },
248 { "gr24", 24, {0, {0}}, 0, 0 },
249 { "gr25", 25, {0, {0}}, 0, 0 },
250 { "gr26", 26, {0, {0}}, 0, 0 },
251 { "gr27", 27, {0, {0}}, 0, 0 },
252 { "gr28", 28, {0, {0}}, 0, 0 },
253 { "gr29", 29, {0, {0}}, 0, 0 },
254 { "gr30", 30, {0, {0}}, 0, 0 },
255 { "gr31", 31, {0, {0}}, 0, 0 },
256 { "gr32", 32, {0, {0}}, 0, 0 },
257 { "gr33", 33, {0, {0}}, 0, 0 },
258 { "gr34", 34, {0, {0}}, 0, 0 },
259 { "gr35", 35, {0, {0}}, 0, 0 },
260 { "gr36", 36, {0, {0}}, 0, 0 },
261 { "gr37", 37, {0, {0}}, 0, 0 },
262 { "gr38", 38, {0, {0}}, 0, 0 },
263 { "gr39", 39, {0, {0}}, 0, 0 },
264 { "gr40", 40, {0, {0}}, 0, 0 },
265 { "gr41", 41, {0, {0}}, 0, 0 },
266 { "gr42", 42, {0, {0}}, 0, 0 },
267 { "gr43", 43, {0, {0}}, 0, 0 },
268 { "gr44", 44, {0, {0}}, 0, 0 },
269 { "gr45", 45, {0, {0}}, 0, 0 },
270 { "gr46", 46, {0, {0}}, 0, 0 },
271 { "gr47", 47, {0, {0}}, 0, 0 },
272 { "gr48", 48, {0, {0}}, 0, 0 },
273 { "gr49", 49, {0, {0}}, 0, 0 },
274 { "gr50", 50, {0, {0}}, 0, 0 },
275 { "gr51", 51, {0, {0}}, 0, 0 },
276 { "gr52", 52, {0, {0}}, 0, 0 },
277 { "gr53", 53, {0, {0}}, 0, 0 },
278 { "gr54", 54, {0, {0}}, 0, 0 },
279 { "gr55", 55, {0, {0}}, 0, 0 },
280 { "gr56", 56, {0, {0}}, 0, 0 },
281 { "gr57", 57, {0, {0}}, 0, 0 },
282 { "gr58", 58, {0, {0}}, 0, 0 },
283 { "gr59", 59, {0, {0}}, 0, 0 },
284 { "gr60", 60, {0, {0}}, 0, 0 },
285 { "gr61", 61, {0, {0}}, 0, 0 },
286 { "gr62", 62, {0, {0}}, 0, 0 },
287 { "gr63", 63, {0, {0}}, 0, 0 }
290 CGEN_KEYWORD frv_cgen_opval_gr_names =
292 & frv_cgen_opval_gr_names_entries[0],
297 static CGEN_KEYWORD_ENTRY frv_cgen_opval_fr_names_entries[] =
299 { "fr0", 0, {0, {0}}, 0, 0 },
300 { "fr1", 1, {0, {0}}, 0, 0 },
301 { "fr2", 2, {0, {0}}, 0, 0 },
302 { "fr3", 3, {0, {0}}, 0, 0 },
303 { "fr4", 4, {0, {0}}, 0, 0 },
304 { "fr5", 5, {0, {0}}, 0, 0 },
305 { "fr6", 6, {0, {0}}, 0, 0 },
306 { "fr7", 7, {0, {0}}, 0, 0 },
307 { "fr8", 8, {0, {0}}, 0, 0 },
308 { "fr9", 9, {0, {0}}, 0, 0 },
309 { "fr10", 10, {0, {0}}, 0, 0 },
310 { "fr11", 11, {0, {0}}, 0, 0 },
311 { "fr12", 12, {0, {0}}, 0, 0 },
312 { "fr13", 13, {0, {0}}, 0, 0 },
313 { "fr14", 14, {0, {0}}, 0, 0 },
314 { "fr15", 15, {0, {0}}, 0, 0 },
315 { "fr16", 16, {0, {0}}, 0, 0 },
316 { "fr17", 17, {0, {0}}, 0, 0 },
317 { "fr18", 18, {0, {0}}, 0, 0 },
318 { "fr19", 19, {0, {0}}, 0, 0 },
319 { "fr20", 20, {0, {0}}, 0, 0 },
320 { "fr21", 21, {0, {0}}, 0, 0 },
321 { "fr22", 22, {0, {0}}, 0, 0 },
322 { "fr23", 23, {0, {0}}, 0, 0 },
323 { "fr24", 24, {0, {0}}, 0, 0 },
324 { "fr25", 25, {0, {0}}, 0, 0 },
325 { "fr26", 26, {0, {0}}, 0, 0 },
326 { "fr27", 27, {0, {0}}, 0, 0 },
327 { "fr28", 28, {0, {0}}, 0, 0 },
328 { "fr29", 29, {0, {0}}, 0, 0 },
329 { "fr30", 30, {0, {0}}, 0, 0 },
330 { "fr31", 31, {0, {0}}, 0, 0 },
331 { "fr32", 32, {0, {0}}, 0, 0 },
332 { "fr33", 33, {0, {0}}, 0, 0 },
333 { "fr34", 34, {0, {0}}, 0, 0 },
334 { "fr35", 35, {0, {0}}, 0, 0 },
335 { "fr36", 36, {0, {0}}, 0, 0 },
336 { "fr37", 37, {0, {0}}, 0, 0 },
337 { "fr38", 38, {0, {0}}, 0, 0 },
338 { "fr39", 39, {0, {0}}, 0, 0 },
339 { "fr40", 40, {0, {0}}, 0, 0 },
340 { "fr41", 41, {0, {0}}, 0, 0 },
341 { "fr42", 42, {0, {0}}, 0, 0 },
342 { "fr43", 43, {0, {0}}, 0, 0 },
343 { "fr44", 44, {0, {0}}, 0, 0 },
344 { "fr45", 45, {0, {0}}, 0, 0 },
345 { "fr46", 46, {0, {0}}, 0, 0 },
346 { "fr47", 47, {0, {0}}, 0, 0 },
347 { "fr48", 48, {0, {0}}, 0, 0 },
348 { "fr49", 49, {0, {0}}, 0, 0 },
349 { "fr50", 50, {0, {0}}, 0, 0 },
350 { "fr51", 51, {0, {0}}, 0, 0 },
351 { "fr52", 52, {0, {0}}, 0, 0 },
352 { "fr53", 53, {0, {0}}, 0, 0 },
353 { "fr54", 54, {0, {0}}, 0, 0 },
354 { "fr55", 55, {0, {0}}, 0, 0 },
355 { "fr56", 56, {0, {0}}, 0, 0 },
356 { "fr57", 57, {0, {0}}, 0, 0 },
357 { "fr58", 58, {0, {0}}, 0, 0 },
358 { "fr59", 59, {0, {0}}, 0, 0 },
359 { "fr60", 60, {0, {0}}, 0, 0 },
360 { "fr61", 61, {0, {0}}, 0, 0 },
361 { "fr62", 62, {0, {0}}, 0, 0 },
362 { "fr63", 63, {0, {0}}, 0, 0 }
365 CGEN_KEYWORD frv_cgen_opval_fr_names =
367 & frv_cgen_opval_fr_names_entries[0],
372 static CGEN_KEYWORD_ENTRY frv_cgen_opval_cpr_names_entries[] =
374 { "cpr0", 0, {0, {0}}, 0, 0 },
375 { "cpr1", 1, {0, {0}}, 0, 0 },
376 { "cpr2", 2, {0, {0}}, 0, 0 },
377 { "cpr3", 3, {0, {0}}, 0, 0 },
378 { "cpr4", 4, {0, {0}}, 0, 0 },
379 { "cpr5", 5, {0, {0}}, 0, 0 },
380 { "cpr6", 6, {0, {0}}, 0, 0 },
381 { "cpr7", 7, {0, {0}}, 0, 0 },
382 { "cpr8", 8, {0, {0}}, 0, 0 },
383 { "cpr9", 9, {0, {0}}, 0, 0 },
384 { "cpr10", 10, {0, {0}}, 0, 0 },
385 { "cpr11", 11, {0, {0}}, 0, 0 },
386 { "cpr12", 12, {0, {0}}, 0, 0 },
387 { "cpr13", 13, {0, {0}}, 0, 0 },
388 { "cpr14", 14, {0, {0}}, 0, 0 },
389 { "cpr15", 15, {0, {0}}, 0, 0 },
390 { "cpr16", 16, {0, {0}}, 0, 0 },
391 { "cpr17", 17, {0, {0}}, 0, 0 },
392 { "cpr18", 18, {0, {0}}, 0, 0 },
393 { "cpr19", 19, {0, {0}}, 0, 0 },
394 { "cpr20", 20, {0, {0}}, 0, 0 },
395 { "cpr21", 21, {0, {0}}, 0, 0 },
396 { "cpr22", 22, {0, {0}}, 0, 0 },
397 { "cpr23", 23, {0, {0}}, 0, 0 },
398 { "cpr24", 24, {0, {0}}, 0, 0 },
399 { "cpr25", 25, {0, {0}}, 0, 0 },
400 { "cpr26", 26, {0, {0}}, 0, 0 },
401 { "cpr27", 27, {0, {0}}, 0, 0 },
402 { "cpr28", 28, {0, {0}}, 0, 0 },
403 { "cpr29", 29, {0, {0}}, 0, 0 },
404 { "cpr30", 30, {0, {0}}, 0, 0 },
405 { "cpr31", 31, {0, {0}}, 0, 0 },
406 { "cpr32", 32, {0, {0}}, 0, 0 },
407 { "cpr33", 33, {0, {0}}, 0, 0 },
408 { "cpr34", 34, {0, {0}}, 0, 0 },
409 { "cpr35", 35, {0, {0}}, 0, 0 },
410 { "cpr36", 36, {0, {0}}, 0, 0 },
411 { "cpr37", 37, {0, {0}}, 0, 0 },
412 { "cpr38", 38, {0, {0}}, 0, 0 },
413 { "cpr39", 39, {0, {0}}, 0, 0 },
414 { "cpr40", 40, {0, {0}}, 0, 0 },
415 { "cpr41", 41, {0, {0}}, 0, 0 },
416 { "cpr42", 42, {0, {0}}, 0, 0 },
417 { "cpr43", 43, {0, {0}}, 0, 0 },
418 { "cpr44", 44, {0, {0}}, 0, 0 },
419 { "cpr45", 45, {0, {0}}, 0, 0 },
420 { "cpr46", 46, {0, {0}}, 0, 0 },
421 { "cpr47", 47, {0, {0}}, 0, 0 },
422 { "cpr48", 48, {0, {0}}, 0, 0 },
423 { "cpr49", 49, {0, {0}}, 0, 0 },
424 { "cpr50", 50, {0, {0}}, 0, 0 },
425 { "cpr51", 51, {0, {0}}, 0, 0 },
426 { "cpr52", 52, {0, {0}}, 0, 0 },
427 { "cpr53", 53, {0, {0}}, 0, 0 },
428 { "cpr54", 54, {0, {0}}, 0, 0 },
429 { "cpr55", 55, {0, {0}}, 0, 0 },
430 { "cpr56", 56, {0, {0}}, 0, 0 },
431 { "cpr57", 57, {0, {0}}, 0, 0 },
432 { "cpr58", 58, {0, {0}}, 0, 0 },
433 { "cpr59", 59, {0, {0}}, 0, 0 },
434 { "cpr60", 60, {0, {0}}, 0, 0 },
435 { "cpr61", 61, {0, {0}}, 0, 0 },
436 { "cpr62", 62, {0, {0}}, 0, 0 },
437 { "cpr63", 63, {0, {0}}, 0, 0 }
440 CGEN_KEYWORD frv_cgen_opval_cpr_names =
442 & frv_cgen_opval_cpr_names_entries[0],
447 static CGEN_KEYWORD_ENTRY frv_cgen_opval_spr_names_entries[] =
449 { "psr", 0, {0, {0}}, 0, 0 },
450 { "pcsr", 1, {0, {0}}, 0, 0 },
451 { "bpcsr", 2, {0, {0}}, 0, 0 },
452 { "tbr", 3, {0, {0}}, 0, 0 },
453 { "bpsr", 4, {0, {0}}, 0, 0 },
454 { "hsr0", 16, {0, {0}}, 0, 0 },
455 { "hsr1", 17, {0, {0}}, 0, 0 },
456 { "hsr2", 18, {0, {0}}, 0, 0 },
457 { "hsr3", 19, {0, {0}}, 0, 0 },
458 { "hsr4", 20, {0, {0}}, 0, 0 },
459 { "hsr5", 21, {0, {0}}, 0, 0 },
460 { "hsr6", 22, {0, {0}}, 0, 0 },
461 { "hsr7", 23, {0, {0}}, 0, 0 },
462 { "hsr8", 24, {0, {0}}, 0, 0 },
463 { "hsr9", 25, {0, {0}}, 0, 0 },
464 { "hsr10", 26, {0, {0}}, 0, 0 },
465 { "hsr11", 27, {0, {0}}, 0, 0 },
466 { "hsr12", 28, {0, {0}}, 0, 0 },
467 { "hsr13", 29, {0, {0}}, 0, 0 },
468 { "hsr14", 30, {0, {0}}, 0, 0 },
469 { "hsr15", 31, {0, {0}}, 0, 0 },
470 { "hsr16", 32, {0, {0}}, 0, 0 },
471 { "hsr17", 33, {0, {0}}, 0, 0 },
472 { "hsr18", 34, {0, {0}}, 0, 0 },
473 { "hsr19", 35, {0, {0}}, 0, 0 },
474 { "hsr20", 36, {0, {0}}, 0, 0 },
475 { "hsr21", 37, {0, {0}}, 0, 0 },
476 { "hsr22", 38, {0, {0}}, 0, 0 },
477 { "hsr23", 39, {0, {0}}, 0, 0 },
478 { "hsr24", 40, {0, {0}}, 0, 0 },
479 { "hsr25", 41, {0, {0}}, 0, 0 },
480 { "hsr26", 42, {0, {0}}, 0, 0 },
481 { "hsr27", 43, {0, {0}}, 0, 0 },
482 { "hsr28", 44, {0, {0}}, 0, 0 },
483 { "hsr29", 45, {0, {0}}, 0, 0 },
484 { "hsr30", 46, {0, {0}}, 0, 0 },
485 { "hsr31", 47, {0, {0}}, 0, 0 },
486 { "hsr32", 48, {0, {0}}, 0, 0 },
487 { "hsr33", 49, {0, {0}}, 0, 0 },
488 { "hsr34", 50, {0, {0}}, 0, 0 },
489 { "hsr35", 51, {0, {0}}, 0, 0 },
490 { "hsr36", 52, {0, {0}}, 0, 0 },
491 { "hsr37", 53, {0, {0}}, 0, 0 },
492 { "hsr38", 54, {0, {0}}, 0, 0 },
493 { "hsr39", 55, {0, {0}}, 0, 0 },
494 { "hsr40", 56, {0, {0}}, 0, 0 },
495 { "hsr41", 57, {0, {0}}, 0, 0 },
496 { "hsr42", 58, {0, {0}}, 0, 0 },
497 { "hsr43", 59, {0, {0}}, 0, 0 },
498 { "hsr44", 60, {0, {0}}, 0, 0 },
499 { "hsr45", 61, {0, {0}}, 0, 0 },
500 { "hsr46", 62, {0, {0}}, 0, 0 },
501 { "hsr47", 63, {0, {0}}, 0, 0 },
502 { "hsr48", 64, {0, {0}}, 0, 0 },
503 { "hsr49", 65, {0, {0}}, 0, 0 },
504 { "hsr50", 66, {0, {0}}, 0, 0 },
505 { "hsr51", 67, {0, {0}}, 0, 0 },
506 { "hsr52", 68, {0, {0}}, 0, 0 },
507 { "hsr53", 69, {0, {0}}, 0, 0 },
508 { "hsr54", 70, {0, {0}}, 0, 0 },
509 { "hsr55", 71, {0, {0}}, 0, 0 },
510 { "hsr56", 72, {0, {0}}, 0, 0 },
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1242 { "iampr34", 1762, {0, {0}}, 0, 0 },
1243 { "iampr35", 1763, {0, {0}}, 0, 0 },
1244 { "iampr36", 1764, {0, {0}}, 0, 0 },
1245 { "iampr37", 1765, {0, {0}}, 0, 0 },
1246 { "iampr38", 1766, {0, {0}}, 0, 0 },
1247 { "iampr39", 1767, {0, {0}}, 0, 0 },
1248 { "iampr40", 1768, {0, {0}}, 0, 0 },
1249 { "iampr41", 1769, {0, {0}}, 0, 0 },
1250 { "iampr42", 1770, {0, {0}}, 0, 0 },
1251 { "iampr43", 1771, {0, {0}}, 0, 0 },
1252 { "iampr44", 1772, {0, {0}}, 0, 0 },
1253 { "iampr45", 1773, {0, {0}}, 0, 0 },
1254 { "iampr46", 1774, {0, {0}}, 0, 0 },
1255 { "iampr47", 1775, {0, {0}}, 0, 0 },
1256 { "iampr48", 1776, {0, {0}}, 0, 0 },
1257 { "iampr49", 1777, {0, {0}}, 0, 0 },
1258 { "iampr50", 1778, {0, {0}}, 0, 0 },
1259 { "iampr51", 1779, {0, {0}}, 0, 0 },
1260 { "iampr52", 1780, {0, {0}}, 0, 0 },
1261 { "iampr53", 1781, {0, {0}}, 0, 0 },
1262 { "iampr54", 1782, {0, {0}}, 0, 0 },
1263 { "iampr55", 1783, {0, {0}}, 0, 0 },
1264 { "iampr56", 1784, {0, {0}}, 0, 0 },
1265 { "iampr57", 1785, {0, {0}}, 0, 0 },
1266 { "iampr58", 1786, {0, {0}}, 0, 0 },
1267 { "iampr59", 1787, {0, {0}}, 0, 0 },
1268 { "iampr60", 1788, {0, {0}}, 0, 0 },
1269 { "iampr61", 1789, {0, {0}}, 0, 0 },
1270 { "iampr62", 1790, {0, {0}}, 0, 0 },
1271 { "iampr63", 1791, {0, {0}}, 0, 0 },
1272 { "damlr0", 1792, {0, {0}}, 0, 0 },
1273 { "damlr1", 1793, {0, {0}}, 0, 0 },
1274 { "damlr2", 1794, {0, {0}}, 0, 0 },
1275 { "damlr3", 1795, {0, {0}}, 0, 0 },
1276 { "damlr4", 1796, {0, {0}}, 0, 0 },
1277 { "damlr5", 1797, {0, {0}}, 0, 0 },
1278 { "damlr6", 1798, {0, {0}}, 0, 0 },
1279 { "damlr7", 1799, {0, {0}}, 0, 0 },
1280 { "damlr8", 1800, {0, {0}}, 0, 0 },
1281 { "damlr9", 1801, {0, {0}}, 0, 0 },
1282 { "damlr10", 1802, {0, {0}}, 0, 0 },
1283 { "damlr11", 1803, {0, {0}}, 0, 0 },
1284 { "damlr12", 1804, {0, {0}}, 0, 0 },
1285 { "damlr13", 1805, {0, {0}}, 0, 0 },
1286 { "damlr14", 1806, {0, {0}}, 0, 0 },
1287 { "damlr15", 1807, {0, {0}}, 0, 0 },
1288 { "damlr16", 1808, {0, {0}}, 0, 0 },
1289 { "damlr17", 1809, {0, {0}}, 0, 0 },
1290 { "damlr18", 1810, {0, {0}}, 0, 0 },
1291 { "damlr19", 1811, {0, {0}}, 0, 0 },
1292 { "damlr20", 1812, {0, {0}}, 0, 0 },
1293 { "damlr21", 1813, {0, {0}}, 0, 0 },
1294 { "damlr22", 1814, {0, {0}}, 0, 0 },
1295 { "damlr23", 1815, {0, {0}}, 0, 0 },
1296 { "damlr24", 1816, {0, {0}}, 0, 0 },
1297 { "damlr25", 1817, {0, {0}}, 0, 0 },
1298 { "damlr26", 1818, {0, {0}}, 0, 0 },
1299 { "damlr27", 1819, {0, {0}}, 0, 0 },
1300 { "damlr28", 1820, {0, {0}}, 0, 0 },
1301 { "damlr29", 1821, {0, {0}}, 0, 0 },
1302 { "damlr30", 1822, {0, {0}}, 0, 0 },
1303 { "damlr31", 1823, {0, {0}}, 0, 0 },
1304 { "damlr32", 1824, {0, {0}}, 0, 0 },
1305 { "damlr33", 1825, {0, {0}}, 0, 0 },
1306 { "damlr34", 1826, {0, {0}}, 0, 0 },
1307 { "damlr35", 1827, {0, {0}}, 0, 0 },
1308 { "damlr36", 1828, {0, {0}}, 0, 0 },
1309 { "damlr37", 1829, {0, {0}}, 0, 0 },
1310 { "damlr38", 1830, {0, {0}}, 0, 0 },
1311 { "damlr39", 1831, {0, {0}}, 0, 0 },
1312 { "damlr40", 1832, {0, {0}}, 0, 0 },
1313 { "damlr41", 1833, {0, {0}}, 0, 0 },
1314 { "damlr42", 1834, {0, {0}}, 0, 0 },
1315 { "damlr43", 1835, {0, {0}}, 0, 0 },
1316 { "damlr44", 1836, {0, {0}}, 0, 0 },
1317 { "damlr45", 1837, {0, {0}}, 0, 0 },
1318 { "damlr46", 1838, {0, {0}}, 0, 0 },
1319 { "damlr47", 1839, {0, {0}}, 0, 0 },
1320 { "damlr48", 1840, {0, {0}}, 0, 0 },
1321 { "damlr49", 1841, {0, {0}}, 0, 0 },
1322 { "damlr50", 1842, {0, {0}}, 0, 0 },
1323 { "damlr51", 1843, {0, {0}}, 0, 0 },
1324 { "damlr52", 1844, {0, {0}}, 0, 0 },
1325 { "damlr53", 1845, {0, {0}}, 0, 0 },
1326 { "damlr54", 1846, {0, {0}}, 0, 0 },
1327 { "damlr55", 1847, {0, {0}}, 0, 0 },
1328 { "damlr56", 1848, {0, {0}}, 0, 0 },
1329 { "damlr57", 1849, {0, {0}}, 0, 0 },
1330 { "damlr58", 1850, {0, {0}}, 0, 0 },
1331 { "damlr59", 1851, {0, {0}}, 0, 0 },
1332 { "damlr60", 1852, {0, {0}}, 0, 0 },
1333 { "damlr61", 1853, {0, {0}}, 0, 0 },
1334 { "damlr62", 1854, {0, {0}}, 0, 0 },
1335 { "damlr63", 1855, {0, {0}}, 0, 0 },
1336 { "dampr0", 1856, {0, {0}}, 0, 0 },
1337 { "dampr1", 1857, {0, {0}}, 0, 0 },
1338 { "dampr2", 1858, {0, {0}}, 0, 0 },
1339 { "dampr3", 1859, {0, {0}}, 0, 0 },
1340 { "dampr4", 1860, {0, {0}}, 0, 0 },
1341 { "dampr5", 1861, {0, {0}}, 0, 0 },
1342 { "dampr6", 1862, {0, {0}}, 0, 0 },
1343 { "dampr7", 1863, {0, {0}}, 0, 0 },
1344 { "dampr8", 1864, {0, {0}}, 0, 0 },
1345 { "dampr9", 1865, {0, {0}}, 0, 0 },
1346 { "dampr10", 1866, {0, {0}}, 0, 0 },
1347 { "dampr11", 1867, {0, {0}}, 0, 0 },
1348 { "dampr12", 1868, {0, {0}}, 0, 0 },
1349 { "dampr13", 1869, {0, {0}}, 0, 0 },
1350 { "dampr14", 1870, {0, {0}}, 0, 0 },
1351 { "dampr15", 1871, {0, {0}}, 0, 0 },
1352 { "dampr16", 1872, {0, {0}}, 0, 0 },
1353 { "dampr17", 1873, {0, {0}}, 0, 0 },
1354 { "dampr18", 1874, {0, {0}}, 0, 0 },
1355 { "dampr19", 1875, {0, {0}}, 0, 0 },
1356 { "dampr20", 1876, {0, {0}}, 0, 0 },
1357 { "dampr21", 1877, {0, {0}}, 0, 0 },
1358 { "dampr22", 1878, {0, {0}}, 0, 0 },
1359 { "dampr23", 1879, {0, {0}}, 0, 0 },
1360 { "dampr24", 1880, {0, {0}}, 0, 0 },
1361 { "dampr25", 1881, {0, {0}}, 0, 0 },
1362 { "dampr26", 1882, {0, {0}}, 0, 0 },
1363 { "dampr27", 1883, {0, {0}}, 0, 0 },
1364 { "dampr28", 1884, {0, {0}}, 0, 0 },
1365 { "dampr29", 1885, {0, {0}}, 0, 0 },
1366 { "dampr30", 1886, {0, {0}}, 0, 0 },
1367 { "dampr31", 1887, {0, {0}}, 0, 0 },
1368 { "dampr32", 1888, {0, {0}}, 0, 0 },
1369 { "dampr33", 1889, {0, {0}}, 0, 0 },
1370 { "dampr34", 1890, {0, {0}}, 0, 0 },
1371 { "dampr35", 1891, {0, {0}}, 0, 0 },
1372 { "dampr36", 1892, {0, {0}}, 0, 0 },
1373 { "dampr37", 1893, {0, {0}}, 0, 0 },
1374 { "dampr38", 1894, {0, {0}}, 0, 0 },
1375 { "dampr39", 1895, {0, {0}}, 0, 0 },
1376 { "dampr40", 1896, {0, {0}}, 0, 0 },
1377 { "dampr41", 1897, {0, {0}}, 0, 0 },
1378 { "dampr42", 1898, {0, {0}}, 0, 0 },
1379 { "dampr43", 1899, {0, {0}}, 0, 0 },
1380 { "dampr44", 1900, {0, {0}}, 0, 0 },
1381 { "dampr45", 1901, {0, {0}}, 0, 0 },
1382 { "dampr46", 1902, {0, {0}}, 0, 0 },
1383 { "dampr47", 1903, {0, {0}}, 0, 0 },
1384 { "dampr48", 1904, {0, {0}}, 0, 0 },
1385 { "dampr49", 1905, {0, {0}}, 0, 0 },
1386 { "dampr50", 1906, {0, {0}}, 0, 0 },
1387 { "dampr51", 1907, {0, {0}}, 0, 0 },
1388 { "dampr52", 1908, {0, {0}}, 0, 0 },
1389 { "dampr53", 1909, {0, {0}}, 0, 0 },
1390 { "dampr54", 1910, {0, {0}}, 0, 0 },
1391 { "dampr55", 1911, {0, {0}}, 0, 0 },
1392 { "dampr56", 1912, {0, {0}}, 0, 0 },
1393 { "dampr57", 1913, {0, {0}}, 0, 0 },
1394 { "dampr58", 1914, {0, {0}}, 0, 0 },
1395 { "dampr59", 1915, {0, {0}}, 0, 0 },
1396 { "dampr60", 1916, {0, {0}}, 0, 0 },
1397 { "dampr61", 1917, {0, {0}}, 0, 0 },
1398 { "dampr62", 1918, {0, {0}}, 0, 0 },
1399 { "dampr63", 1919, {0, {0}}, 0, 0 },
1400 { "amcr", 1920, {0, {0}}, 0, 0 },
1401 { "stbar", 1921, {0, {0}}, 0, 0 },
1402 { "mmcr", 1922, {0, {0}}, 0, 0 },
1403 { "dcr", 2048, {0, {0}}, 0, 0 },
1404 { "brr", 2049, {0, {0}}, 0, 0 },
1405 { "nmar", 2050, {0, {0}}, 0, 0 },
1406 { "ibar0", 2052, {0, {0}}, 0, 0 },
1407 { "ibar1", 2053, {0, {0}}, 0, 0 },
1408 { "ibar2", 2054, {0, {0}}, 0, 0 },
1409 { "ibar3", 2055, {0, {0}}, 0, 0 },
1410 { "dbar0", 2056, {0, {0}}, 0, 0 },
1411 { "dbar1", 2057, {0, {0}}, 0, 0 },
1412 { "dbar2", 2058, {0, {0}}, 0, 0 },
1413 { "dbar3", 2059, {0, {0}}, 0, 0 },
1414 { "dbdr00", 2060, {0, {0}}, 0, 0 },
1415 { "dbdr01", 2061, {0, {0}}, 0, 0 },
1416 { "dbdr02", 2062, {0, {0}}, 0, 0 },
1417 { "dbdr03", 2063, {0, {0}}, 0, 0 },
1418 { "dbdr10", 2064, {0, {0}}, 0, 0 },
1419 { "dbdr11", 2065, {0, {0}}, 0, 0 },
1420 { "dbdr12", 2066, {0, {0}}, 0, 0 },
1421 { "dbdr13", 2067, {0, {0}}, 0, 0 },
1422 { "dbdr20", 2068, {0, {0}}, 0, 0 },
1423 { "dbdr21", 2069, {0, {0}}, 0, 0 },
1424 { "dbdr22", 2070, {0, {0}}, 0, 0 },
1425 { "dbdr23", 2071, {0, {0}}, 0, 0 },
1426 { "dbdr30", 2072, {0, {0}}, 0, 0 },
1427 { "dbdr31", 2073, {0, {0}}, 0, 0 },
1428 { "dbdr32", 2074, {0, {0}}, 0, 0 },
1429 { "dbdr33", 2075, {0, {0}}, 0, 0 },
1430 { "dbmr00", 2076, {0, {0}}, 0, 0 },
1431 { "dbmr01", 2077, {0, {0}}, 0, 0 },
1432 { "dbmr02", 2078, {0, {0}}, 0, 0 },
1433 { "dbmr03", 2079, {0, {0}}, 0, 0 },
1434 { "dbmr10", 2080, {0, {0}}, 0, 0 },
1435 { "dbmr11", 2081, {0, {0}}, 0, 0 },
1436 { "dbmr12", 2082, {0, {0}}, 0, 0 },
1437 { "dbmr13", 2083, {0, {0}}, 0, 0 },
1438 { "dbmr20", 2084, {0, {0}}, 0, 0 },
1439 { "dbmr21", 2085, {0, {0}}, 0, 0 },
1440 { "dbmr22", 2086, {0, {0}}, 0, 0 },
1441 { "dbmr23", 2087, {0, {0}}, 0, 0 },
1442 { "dbmr30", 2088, {0, {0}}, 0, 0 },
1443 { "dbmr31", 2089, {0, {0}}, 0, 0 },
1444 { "dbmr32", 2090, {0, {0}}, 0, 0 },
1445 { "dbmr33", 2091, {0, {0}}, 0, 0 },
1446 { "cpcfr", 2092, {0, {0}}, 0, 0 },
1447 { "cpcr", 2093, {0, {0}}, 0, 0 },
1448 { "cpsr", 2094, {0, {0}}, 0, 0 },
1449 { "cpesr0", 2096, {0, {0}}, 0, 0 },
1450 { "cpesr1", 2097, {0, {0}}, 0, 0 },
1451 { "cpemr0", 2098, {0, {0}}, 0, 0 },
1452 { "cpemr1", 2099, {0, {0}}, 0, 0 },
1453 { "ihsr8", 3848, {0, {0}}, 0, 0 }
1456 CGEN_KEYWORD frv_cgen_opval_spr_names =
1458 & frv_cgen_opval_spr_names_entries[0],
1463 static CGEN_KEYWORD_ENTRY frv_cgen_opval_accg_names_entries[] =
1465 { "accg0", 0, {0, {0}}, 0, 0 },
1466 { "accg1", 1, {0, {0}}, 0, 0 },
1467 { "accg2", 2, {0, {0}}, 0, 0 },
1468 { "accg3", 3, {0, {0}}, 0, 0 },
1469 { "accg4", 4, {0, {0}}, 0, 0 },
1470 { "accg5", 5, {0, {0}}, 0, 0 },
1471 { "accg6", 6, {0, {0}}, 0, 0 },
1472 { "accg7", 7, {0, {0}}, 0, 0 },
1473 { "accg8", 8, {0, {0}}, 0, 0 },
1474 { "accg9", 9, {0, {0}}, 0, 0 },
1475 { "accg10", 10, {0, {0}}, 0, 0 },
1476 { "accg11", 11, {0, {0}}, 0, 0 },
1477 { "accg12", 12, {0, {0}}, 0, 0 },
1478 { "accg13", 13, {0, {0}}, 0, 0 },
1479 { "accg14", 14, {0, {0}}, 0, 0 },
1480 { "accg15", 15, {0, {0}}, 0, 0 },
1481 { "accg16", 16, {0, {0}}, 0, 0 },
1482 { "accg17", 17, {0, {0}}, 0, 0 },
1483 { "accg18", 18, {0, {0}}, 0, 0 },
1484 { "accg19", 19, {0, {0}}, 0, 0 },
1485 { "accg20", 20, {0, {0}}, 0, 0 },
1486 { "accg21", 21, {0, {0}}, 0, 0 },
1487 { "accg22", 22, {0, {0}}, 0, 0 },
1488 { "accg23", 23, {0, {0}}, 0, 0 },
1489 { "accg24", 24, {0, {0}}, 0, 0 },
1490 { "accg25", 25, {0, {0}}, 0, 0 },
1491 { "accg26", 26, {0, {0}}, 0, 0 },
1492 { "accg27", 27, {0, {0}}, 0, 0 },
1493 { "accg28", 28, {0, {0}}, 0, 0 },
1494 { "accg29", 29, {0, {0}}, 0, 0 },
1495 { "accg30", 30, {0, {0}}, 0, 0 },
1496 { "accg31", 31, {0, {0}}, 0, 0 },
1497 { "accg32", 32, {0, {0}}, 0, 0 },
1498 { "accg33", 33, {0, {0}}, 0, 0 },
1499 { "accg34", 34, {0, {0}}, 0, 0 },
1500 { "accg35", 35, {0, {0}}, 0, 0 },
1501 { "accg36", 36, {0, {0}}, 0, 0 },
1502 { "accg37", 37, {0, {0}}, 0, 0 },
1503 { "accg38", 38, {0, {0}}, 0, 0 },
1504 { "accg39", 39, {0, {0}}, 0, 0 },
1505 { "accg40", 40, {0, {0}}, 0, 0 },
1506 { "accg41", 41, {0, {0}}, 0, 0 },
1507 { "accg42", 42, {0, {0}}, 0, 0 },
1508 { "accg43", 43, {0, {0}}, 0, 0 },
1509 { "accg44", 44, {0, {0}}, 0, 0 },
1510 { "accg45", 45, {0, {0}}, 0, 0 },
1511 { "accg46", 46, {0, {0}}, 0, 0 },
1512 { "accg47", 47, {0, {0}}, 0, 0 },
1513 { "accg48", 48, {0, {0}}, 0, 0 },
1514 { "accg49", 49, {0, {0}}, 0, 0 },
1515 { "accg50", 50, {0, {0}}, 0, 0 },
1516 { "accg51", 51, {0, {0}}, 0, 0 },
1517 { "accg52", 52, {0, {0}}, 0, 0 },
1518 { "accg53", 53, {0, {0}}, 0, 0 },
1519 { "accg54", 54, {0, {0}}, 0, 0 },
1520 { "accg55", 55, {0, {0}}, 0, 0 },
1521 { "accg56", 56, {0, {0}}, 0, 0 },
1522 { "accg57", 57, {0, {0}}, 0, 0 },
1523 { "accg58", 58, {0, {0}}, 0, 0 },
1524 { "accg59", 59, {0, {0}}, 0, 0 },
1525 { "accg60", 60, {0, {0}}, 0, 0 },
1526 { "accg61", 61, {0, {0}}, 0, 0 },
1527 { "accg62", 62, {0, {0}}, 0, 0 },
1528 { "accg63", 63, {0, {0}}, 0, 0 }
1531 CGEN_KEYWORD frv_cgen_opval_accg_names =
1533 & frv_cgen_opval_accg_names_entries[0],
1538 static CGEN_KEYWORD_ENTRY frv_cgen_opval_acc_names_entries[] =
1540 { "acc0", 0, {0, {0}}, 0, 0 },
1541 { "acc1", 1, {0, {0}}, 0, 0 },
1542 { "acc2", 2, {0, {0}}, 0, 0 },
1543 { "acc3", 3, {0, {0}}, 0, 0 },
1544 { "acc4", 4, {0, {0}}, 0, 0 },
1545 { "acc5", 5, {0, {0}}, 0, 0 },
1546 { "acc6", 6, {0, {0}}, 0, 0 },
1547 { "acc7", 7, {0, {0}}, 0, 0 },
1548 { "acc8", 8, {0, {0}}, 0, 0 },
1549 { "acc9", 9, {0, {0}}, 0, 0 },
1550 { "acc10", 10, {0, {0}}, 0, 0 },
1551 { "acc11", 11, {0, {0}}, 0, 0 },
1552 { "acc12", 12, {0, {0}}, 0, 0 },
1553 { "acc13", 13, {0, {0}}, 0, 0 },
1554 { "acc14", 14, {0, {0}}, 0, 0 },
1555 { "acc15", 15, {0, {0}}, 0, 0 },
1556 { "acc16", 16, {0, {0}}, 0, 0 },
1557 { "acc17", 17, {0, {0}}, 0, 0 },
1558 { "acc18", 18, {0, {0}}, 0, 0 },
1559 { "acc19", 19, {0, {0}}, 0, 0 },
1560 { "acc20", 20, {0, {0}}, 0, 0 },
1561 { "acc21", 21, {0, {0}}, 0, 0 },
1562 { "acc22", 22, {0, {0}}, 0, 0 },
1563 { "acc23", 23, {0, {0}}, 0, 0 },
1564 { "acc24", 24, {0, {0}}, 0, 0 },
1565 { "acc25", 25, {0, {0}}, 0, 0 },
1566 { "acc26", 26, {0, {0}}, 0, 0 },
1567 { "acc27", 27, {0, {0}}, 0, 0 },
1568 { "acc28", 28, {0, {0}}, 0, 0 },
1569 { "acc29", 29, {0, {0}}, 0, 0 },
1570 { "acc30", 30, {0, {0}}, 0, 0 },
1571 { "acc31", 31, {0, {0}}, 0, 0 },
1572 { "acc32", 32, {0, {0}}, 0, 0 },
1573 { "acc33", 33, {0, {0}}, 0, 0 },
1574 { "acc34", 34, {0, {0}}, 0, 0 },
1575 { "acc35", 35, {0, {0}}, 0, 0 },
1576 { "acc36", 36, {0, {0}}, 0, 0 },
1577 { "acc37", 37, {0, {0}}, 0, 0 },
1578 { "acc38", 38, {0, {0}}, 0, 0 },
1579 { "acc39", 39, {0, {0}}, 0, 0 },
1580 { "acc40", 40, {0, {0}}, 0, 0 },
1581 { "acc41", 41, {0, {0}}, 0, 0 },
1582 { "acc42", 42, {0, {0}}, 0, 0 },
1583 { "acc43", 43, {0, {0}}, 0, 0 },
1584 { "acc44", 44, {0, {0}}, 0, 0 },
1585 { "acc45", 45, {0, {0}}, 0, 0 },
1586 { "acc46", 46, {0, {0}}, 0, 0 },
1587 { "acc47", 47, {0, {0}}, 0, 0 },
1588 { "acc48", 48, {0, {0}}, 0, 0 },
1589 { "acc49", 49, {0, {0}}, 0, 0 },
1590 { "acc50", 50, {0, {0}}, 0, 0 },
1591 { "acc51", 51, {0, {0}}, 0, 0 },
1592 { "acc52", 52, {0, {0}}, 0, 0 },
1593 { "acc53", 53, {0, {0}}, 0, 0 },
1594 { "acc54", 54, {0, {0}}, 0, 0 },
1595 { "acc55", 55, {0, {0}}, 0, 0 },
1596 { "acc56", 56, {0, {0}}, 0, 0 },
1597 { "acc57", 57, {0, {0}}, 0, 0 },
1598 { "acc58", 58, {0, {0}}, 0, 0 },
1599 { "acc59", 59, {0, {0}}, 0, 0 },
1600 { "acc60", 60, {0, {0}}, 0, 0 },
1601 { "acc61", 61, {0, {0}}, 0, 0 },
1602 { "acc62", 62, {0, {0}}, 0, 0 },
1603 { "acc63", 63, {0, {0}}, 0, 0 }
1606 CGEN_KEYWORD frv_cgen_opval_acc_names =
1608 & frv_cgen_opval_acc_names_entries[0],
1613 static CGEN_KEYWORD_ENTRY frv_cgen_opval_iccr_names_entries[] =
1615 { "icc0", 0, {0, {0}}, 0, 0 },
1616 { "icc1", 1, {0, {0}}, 0, 0 },
1617 { "icc2", 2, {0, {0}}, 0, 0 },
1618 { "icc3", 3, {0, {0}}, 0, 0 }
1621 CGEN_KEYWORD frv_cgen_opval_iccr_names =
1623 & frv_cgen_opval_iccr_names_entries[0],
1628 static CGEN_KEYWORD_ENTRY frv_cgen_opval_fccr_names_entries[] =
1630 { "fcc0", 0, {0, {0}}, 0, 0 },
1631 { "fcc1", 1, {0, {0}}, 0, 0 },
1632 { "fcc2", 2, {0, {0}}, 0, 0 },
1633 { "fcc3", 3, {0, {0}}, 0, 0 }
1636 CGEN_KEYWORD frv_cgen_opval_fccr_names =
1638 & frv_cgen_opval_fccr_names_entries[0],
1643 static CGEN_KEYWORD_ENTRY frv_cgen_opval_cccr_names_entries[] =
1645 { "cc0", 0, {0, {0}}, 0, 0 },
1646 { "cc1", 1, {0, {0}}, 0, 0 },
1647 { "cc2", 2, {0, {0}}, 0, 0 },
1648 { "cc3", 3, {0, {0}}, 0, 0 },
1649 { "cc4", 4, {0, {0}}, 0, 0 },
1650 { "cc5", 5, {0, {0}}, 0, 0 },
1651 { "cc6", 6, {0, {0}}, 0, 0 },
1652 { "cc7", 7, {0, {0}}, 0, 0 }
1655 CGEN_KEYWORD frv_cgen_opval_cccr_names =
1657 & frv_cgen_opval_cccr_names_entries[0],
1662 static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_pack_entries[] =
1664 { "", 1, {0, {0}}, 0, 0 },
1665 { ".p", 0, {0, {0}}, 0, 0 },
1666 { ".P", 0, {0, {0}}, 0, 0 }
1669 CGEN_KEYWORD frv_cgen_opval_h_pack =
1671 & frv_cgen_opval_h_pack_entries[0],
1676 static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_taken_entries[] =
1678 { "", 2, {0, {0}}, 0, 0 },
1679 { "", 0, {0, {0}}, 0, 0 },
1680 { "", 1, {0, {0}}, 0, 0 },
1681 { "", 3, {0, {0}}, 0, 0 }
1684 CGEN_KEYWORD frv_cgen_opval_h_hint_taken =
1686 & frv_cgen_opval_h_hint_taken_entries[0],
1691 static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_not_taken_entries[] =
1693 { "", 0, {0, {0}}, 0, 0 },
1694 { "", 1, {0, {0}}, 0, 0 },
1695 { "", 2, {0, {0}}, 0, 0 },
1696 { "", 3, {0, {0}}, 0, 0 }
1699 CGEN_KEYWORD frv_cgen_opval_h_hint_not_taken =
1701 & frv_cgen_opval_h_hint_not_taken_entries[0],
1707 /* The hardware table. */
1709 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1710 #define A(a) (1 << CGEN_HW_##a)
1712 #define A(a) (1 << CGEN_HW_/**/a)
1715 const CGEN_HW_ENTRY frv_cgen_hw_table[] =
1717 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1718 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1719 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1720 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1721 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1722 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
1723 { "h-psr_imple", HW_H_PSR_IMPLE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1724 { "h-psr_ver", HW_H_PSR_VER, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1725 { "h-psr_ice", HW_H_PSR_ICE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1726 { "h-psr_nem", HW_H_PSR_NEM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1727 { "h-psr_cm", HW_H_PSR_CM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1728 { "h-psr_be", HW_H_PSR_BE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1729 { "h-psr_esr", HW_H_PSR_ESR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1730 { "h-psr_ef", HW_H_PSR_EF, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1731 { "h-psr_em", HW_H_PSR_EM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1732 { "h-psr_pil", HW_H_PSR_PIL, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1733 { "h-psr_ps", HW_H_PSR_PS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1734 { "h-psr_et", HW_H_PSR_ET, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1735 { "h-psr_s", HW_H_PSR_S, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1736 { "h-tbr_tba", HW_H_TBR_TBA, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1737 { "h-tbr_tt", HW_H_TBR_TT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1738 { "h-bpsr_bs", HW_H_BPSR_BS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1739 { "h-bpsr_bet", HW_H_BPSR_BET, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
1740 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1741 { "h-gr_double", HW_H_GR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1742 { "h-gr_hi", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1743 { "h-gr_lo", HW_H_GR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1744 { "h-fr", HW_H_FR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1745 { "h-fr_double", HW_H_FR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1746 { "h-fr_int", HW_H_FR_INT, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1747 { "h-fr_hi", HW_H_FR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1748 { "h-fr_lo", HW_H_FR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1749 { "h-fr_0", HW_H_FR_0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1750 { "h-fr_1", HW_H_FR_1, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1751 { "h-fr_2", HW_H_FR_2, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1752 { "h-fr_3", HW_H_FR_3, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1753 { "h-cpr", HW_H_CPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(PROFILE), { (1<<MACH_FRV) } } },
1754 { "h-cpr_double", HW_H_CPR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_FRV) } } },
1755 { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_spr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1756 { "h-accg", HW_H_ACCG, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_accg_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1757 { "h-acc40S", HW_H_ACC40S, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1758 { "h-acc40U", HW_H_ACC40U, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
1759 { "h-iccr", HW_H_ICCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1760 { "h-fccr", HW_H_FCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1761 { "h-cccr", HW_H_CCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
1762 { "h-pack", HW_H_PACK, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_pack, { 0, { (1<<MACH_BASE) } } },
1763 { "h-hint-taken", HW_H_HINT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_taken, { 0, { (1<<MACH_BASE) } } },
1764 { "h-hint-not-taken", HW_H_HINT_NOT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_not_taken, { 0, { (1<<MACH_BASE) } } },
1765 { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
1771 /* The instruction field table. */
1773 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1774 #define A(a) (1 << CGEN_IFLD_##a)
1776 #define A(a) (1 << CGEN_IFLD_/**/a)
1779 const CGEN_IFLD frv_cgen_ifld_table[] =
1781 { FRV_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
1782 { FRV_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
1783 { FRV_F_PACK, "f-pack", 0, 32, 31, 1, { 0, { (1<<MACH_BASE) } } },
1784 { FRV_F_OP, "f-op", 0, 32, 24, 7, { 0, { (1<<MACH_BASE) } } },
1785 { FRV_F_OPE1, "f-ope1", 0, 32, 11, 6, { 0, { (1<<MACH_BASE) } } },
1786 { FRV_F_OPE2, "f-ope2", 0, 32, 9, 4, { 0, { (1<<MACH_BASE) } } },
1787 { FRV_F_OPE3, "f-ope3", 0, 32, 15, 3, { 0, { (1<<MACH_BASE) } } },
1788 { FRV_F_OPE4, "f-ope4", 0, 32, 7, 2, { 0, { (1<<MACH_BASE) } } },
1789 { FRV_F_GRI, "f-GRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } },
1790 { FRV_F_GRJ, "f-GRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } },
1791 { FRV_F_GRK, "f-GRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } },
1792 { FRV_F_FRI, "f-FRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } },
1793 { FRV_F_FRJ, "f-FRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } },
1794 { FRV_F_FRK, "f-FRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } },
1795 { FRV_F_CPRI, "f-CPRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } },
1796 { FRV_F_CPRJ, "f-CPRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } },
1797 { FRV_F_CPRK, "f-CPRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } },
1798 { FRV_F_ACCGI, "f-ACCGi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } },
1799 { FRV_F_ACCGK, "f-ACCGk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } },
1800 { FRV_F_ACC40SI, "f-ACC40Si", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } },
1801 { FRV_F_ACC40UI, "f-ACC40Ui", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } },
1802 { FRV_F_ACC40SK, "f-ACC40Sk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } },
1803 { FRV_F_ACC40UK, "f-ACC40Uk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } },
1804 { FRV_F_CRI, "f-CRi", 0, 32, 14, 3, { 0, { (1<<MACH_BASE) } } },
1805 { FRV_F_CRJ, "f-CRj", 0, 32, 2, 3, { 0, { (1<<MACH_BASE) } } },
1806 { FRV_F_CRK, "f-CRk", 0, 32, 27, 3, { 0, { (1<<MACH_BASE) } } },
1807 { FRV_F_CCI, "f-CCi", 0, 32, 11, 3, { 0, { (1<<MACH_BASE) } } },
1808 { FRV_F_CRJ_INT, "f-CRj_int", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } } },
1809 { FRV_F_CRJ_FLOAT, "f-CRj_float", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } } },
1810 { FRV_F_ICCI_1, "f-ICCi_1", 0, 32, 11, 2, { 0, { (1<<MACH_BASE) } } },
1811 { FRV_F_ICCI_2, "f-ICCi_2", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } } },
1812 { FRV_F_ICCI_3, "f-ICCi_3", 0, 32, 1, 2, { 0, { (1<<MACH_BASE) } } },
1813 { FRV_F_FCCI_1, "f-FCCi_1", 0, 32, 11, 2, { 0, { (1<<MACH_BASE) } } },
1814 { FRV_F_FCCI_2, "f-FCCi_2", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } } },
1815 { FRV_F_FCCI_3, "f-FCCi_3", 0, 32, 1, 2, { 0, { (1<<MACH_BASE) } } },
1816 { FRV_F_FCCK, "f-FCCk", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } } },
1817 { FRV_F_EIR, "f-eir", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } },
1818 { FRV_F_S10, "f-s10", 0, 32, 9, 10, { 0, { (1<<MACH_BASE) } } },
1819 { FRV_F_S12, "f-s12", 0, 32, 11, 12, { 0, { (1<<MACH_BASE) } } },
1820 { FRV_F_D12, "f-d12", 0, 32, 11, 12, { 0, { (1<<MACH_BASE) } } },
1821 { FRV_F_U16, "f-u16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } } },
1822 { FRV_F_S16, "f-s16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } } },
1823 { FRV_F_S6, "f-s6", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } },
1824 { FRV_F_S6_1, "f-s6_1", 0, 32, 11, 6, { 0, { (1<<MACH_BASE) } } },
1825 { FRV_F_U6, "f-u6", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } },
1826 { FRV_F_S5, "f-s5", 0, 32, 4, 5, { 0, { (1<<MACH_BASE) } } },
1827 { FRV_F_U12_H, "f-u12-h", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } },
1828 { FRV_F_U12_L, "f-u12-l", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } },
1829 { FRV_F_U12, "f-u12", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
1830 { FRV_F_INT_CC, "f-int-cc", 0, 32, 30, 4, { 0, { (1<<MACH_BASE) } } },
1831 { FRV_F_FLT_CC, "f-flt-cc", 0, 32, 30, 4, { 0, { (1<<MACH_BASE) } } },
1832 { FRV_F_COND, "f-cond", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } } },
1833 { FRV_F_CCOND, "f-ccond", 0, 32, 12, 1, { 0, { (1<<MACH_BASE) } } },
1834 { FRV_F_HINT, "f-hint", 0, 32, 17, 2, { 0, { (1<<MACH_BASE) } } },
1835 { FRV_F_LI, "f-LI", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } } },
1836 { FRV_F_LOCK, "f-lock", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } } },
1837 { FRV_F_DEBUG, "f-debug", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } } },
1838 { FRV_F_A, "f-A", 0, 32, 17, 1, { 0, { (1<<MACH_BASE) } } },
1839 { FRV_F_AE, "f-ae", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } } },
1840 { FRV_F_SPR_H, "f-spr-h", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } },
1841 { FRV_F_SPR_L, "f-spr-l", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } },
1842 { FRV_F_SPR, "f-spr", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
1843 { FRV_F_LABEL16, "f-label16", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
1844 { FRV_F_LABELH6, "f-labelH6", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } },
1845 { FRV_F_LABELL18, "f-labelL18", 0, 32, 17, 18, { 0, { (1<<MACH_BASE) } } },
1846 { FRV_F_LABEL24, "f-label24", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } },
1847 { FRV_F_ICCI_1_NULL, "f-ICCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1848 { FRV_F_ICCI_2_NULL, "f-ICCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1849 { FRV_F_ICCI_3_NULL, "f-ICCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1850 { FRV_F_FCCI_1_NULL, "f-FCCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1851 { FRV_F_FCCI_2_NULL, "f-FCCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1852 { FRV_F_FCCI_3_NULL, "f-FCCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1853 { FRV_F_RS_NULL, "f-rs-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1854 { FRV_F_GRI_NULL, "f-GRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1855 { FRV_F_GRJ_NULL, "f-GRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1856 { FRV_F_GRK_NULL, "f-GRk-null", 0, 32, 30, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1857 { FRV_F_FRI_NULL, "f-FRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1858 { FRV_F_FRJ_NULL, "f-FRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1859 { FRV_F_ACCJ_NULL, "f-ACCj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1860 { FRV_F_RD_NULL, "f-rd-null", 0, 32, 30, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1861 { FRV_F_COND_NULL, "f-cond-null", 0, 32, 30, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1862 { FRV_F_CCOND_NULL, "f-ccond-null", 0, 32, 12, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1863 { FRV_F_S12_NULL, "f-s12-null", 0, 32, 11, 12, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1864 { FRV_F_LABEL16_NULL, "f-label16-null", 0, 32, 15, 16, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1865 { FRV_F_MISC_NULL_1, "f-misc-null-1", 0, 32, 30, 5, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1866 { FRV_F_MISC_NULL_2, "f-misc-null-2", 0, 32, 11, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1867 { FRV_F_MISC_NULL_3, "f-misc-null-3", 0, 32, 11, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1868 { FRV_F_MISC_NULL_4, "f-misc-null-4", 0, 32, 17, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1869 { FRV_F_MISC_NULL_5, "f-misc-null-5", 0, 32, 17, 16, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1870 { FRV_F_MISC_NULL_6, "f-misc-null-6", 0, 32, 30, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1871 { FRV_F_MISC_NULL_7, "f-misc-null-7", 0, 32, 17, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1872 { FRV_F_MISC_NULL_8, "f-misc-null-8", 0, 32, 5, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1873 { FRV_F_MISC_NULL_9, "f-misc-null-9", 0, 32, 5, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1874 { FRV_F_MISC_NULL_10, "f-misc-null-10", 0, 32, 16, 5, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1875 { FRV_F_MISC_NULL_11, "f-misc-null-11", 0, 32, 5, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1876 { FRV_F_LI_OFF, "f-LI-off", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1877 { FRV_F_LI_ON, "f-LI-on", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
1878 { 0, 0, 0, 0, 0, 0, {0, {0}} }
1885 /* multi ifield declarations */
1887 const CGEN_MAYBE_MULTI_IFLD FRV_F_U12_MULTI_IFIELD [];
1888 const CGEN_MAYBE_MULTI_IFLD FRV_F_SPR_MULTI_IFIELD [];
1889 const CGEN_MAYBE_MULTI_IFLD FRV_F_LABEL24_MULTI_IFIELD [];
1892 /* multi ifield definitions */
1894 const CGEN_MAYBE_MULTI_IFLD FRV_F_U12_MULTI_IFIELD [] =
1896 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U12_H] } },
1897 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U12_L] } },
1898 { 0, { (const PTR) 0 } }
1900 const CGEN_MAYBE_MULTI_IFLD FRV_F_SPR_MULTI_IFIELD [] =
1902 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_SPR_H] } },
1903 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_SPR_L] } },
1904 { 0, { (const PTR) 0 } }
1906 const CGEN_MAYBE_MULTI_IFLD FRV_F_LABEL24_MULTI_IFIELD [] =
1908 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABELH6] } },
1909 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABELL18] } },
1910 { 0, { (const PTR) 0 } }
1913 /* The operand table. */
1915 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1916 #define A(a) (1 << CGEN_OPERAND_##a)
1918 #define A(a) (1 << CGEN_OPERAND_/**/a)
1920 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1921 #define OPERAND(op) FRV_OPERAND_##op
1923 #define OPERAND(op) FRV_OPERAND_/**/op
1926 const CGEN_OPERAND frv_cgen_operand_table[] =
1928 /* pc: program counter */
1929 { "pc", FRV_OPERAND_PC, HW_H_PC, 0, 0,
1930 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_NIL] } },
1931 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
1932 /* pack: packing bit */
1933 { "pack", FRV_OPERAND_PACK, HW_H_PACK, 31, 1,
1934 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_PACK] } },
1935 { 0, { (1<<MACH_BASE) } } },
1936 /* GRi: source register 1 */
1937 { "GRi", FRV_OPERAND_GRI, HW_H_GR, 17, 6,
1938 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRI] } },
1939 { 0, { (1<<MACH_BASE) } } },
1940 /* GRj: source register 2 */
1941 { "GRj", FRV_OPERAND_GRJ, HW_H_GR, 5, 6,
1942 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRJ] } },
1943 { 0, { (1<<MACH_BASE) } } },
1944 /* GRk: destination register */
1945 { "GRk", FRV_OPERAND_GRK, HW_H_GR, 30, 6,
1946 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
1947 { 0, { (1<<MACH_BASE) } } },
1948 /* GRkhi: destination register */
1949 { "GRkhi", FRV_OPERAND_GRKHI, HW_H_GR_HI, 30, 6,
1950 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
1951 { 0, { (1<<MACH_BASE) } } },
1952 /* GRklo: destination register */
1953 { "GRklo", FRV_OPERAND_GRKLO, HW_H_GR_LO, 30, 6,
1954 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
1955 { 0, { (1<<MACH_BASE) } } },
1956 /* GRdoublek: destination register */
1957 { "GRdoublek", FRV_OPERAND_GRDOUBLEK, HW_H_GR_DOUBLE, 30, 6,
1958 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
1959 { 0, { (1<<MACH_BASE) } } },
1960 /* ACC40Si: signed accumulator */
1961 { "ACC40Si", FRV_OPERAND_ACC40SI, HW_H_ACC40S, 17, 6,
1962 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SI] } },
1963 { 0, { (1<<MACH_BASE) } } },
1964 /* ACC40Ui: unsigned accumulator */
1965 { "ACC40Ui", FRV_OPERAND_ACC40UI, HW_H_ACC40U, 17, 6,
1966 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UI] } },
1967 { 0, { (1<<MACH_BASE) } } },
1968 /* ACC40Sk: target accumulator */
1969 { "ACC40Sk", FRV_OPERAND_ACC40SK, HW_H_ACC40S, 30, 6,
1970 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SK] } },
1971 { 0, { (1<<MACH_BASE) } } },
1972 /* ACC40Uk: target accumulator */
1973 { "ACC40Uk", FRV_OPERAND_ACC40UK, HW_H_ACC40U, 30, 6,
1974 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UK] } },
1975 { 0, { (1<<MACH_BASE) } } },
1976 /* ACCGi: source register */
1977 { "ACCGi", FRV_OPERAND_ACCGI, HW_H_ACCG, 17, 6,
1978 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGI] } },
1979 { 0, { (1<<MACH_BASE) } } },
1980 /* ACCGk: target register */
1981 { "ACCGk", FRV_OPERAND_ACCGK, HW_H_ACCG, 30, 6,
1982 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGK] } },
1983 { 0, { (1<<MACH_BASE) } } },
1984 /* CPRi: source register */
1985 { "CPRi", FRV_OPERAND_CPRI, HW_H_CPR, 17, 6,
1986 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRI] } },
1987 { 0, { (1<<MACH_FRV) } } },
1988 /* CPRj: source register */
1989 { "CPRj", FRV_OPERAND_CPRJ, HW_H_CPR, 5, 6,
1990 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRJ] } },
1991 { 0, { (1<<MACH_FRV) } } },
1992 /* CPRk: destination register */
1993 { "CPRk", FRV_OPERAND_CPRK, HW_H_CPR, 30, 6,
1994 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } },
1995 { 0, { (1<<MACH_FRV) } } },
1996 /* CPRdoublek: destination register */
1997 { "CPRdoublek", FRV_OPERAND_CPRDOUBLEK, HW_H_CPR_DOUBLE, 30, 6,
1998 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } },
1999 { 0, { (1<<MACH_FRV) } } },
2000 /* FRinti: source register 1 */
2001 { "FRinti", FRV_OPERAND_FRINTI, HW_H_FR_INT, 17, 6,
2002 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
2003 { 0, { (1<<MACH_BASE) } } },
2004 /* FRintj: source register 2 */
2005 { "FRintj", FRV_OPERAND_FRINTJ, HW_H_FR_INT, 5, 6,
2006 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
2007 { 0, { (1<<MACH_BASE) } } },
2008 /* FRintk: target register */
2009 { "FRintk", FRV_OPERAND_FRINTK, HW_H_FR_INT, 30, 6,
2010 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
2011 { 0, { (1<<MACH_BASE) } } },
2012 /* FRi: source register 1 */
2013 { "FRi", FRV_OPERAND_FRI, HW_H_FR, 17, 6,
2014 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
2015 { 0, { (1<<MACH_BASE) } } },
2016 /* FRj: source register 2 */
2017 { "FRj", FRV_OPERAND_FRJ, HW_H_FR, 5, 6,
2018 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
2019 { 0, { (1<<MACH_BASE) } } },
2020 /* FRk: destination register */
2021 { "FRk", FRV_OPERAND_FRK, HW_H_FR, 30, 6,
2022 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
2023 { 0, { (1<<MACH_BASE) } } },
2024 /* FRkhi: destination register */
2025 { "FRkhi", FRV_OPERAND_FRKHI, HW_H_FR_HI, 30, 6,
2026 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
2027 { 0, { (1<<MACH_BASE) } } },
2028 /* FRklo: destination register */
2029 { "FRklo", FRV_OPERAND_FRKLO, HW_H_FR_LO, 30, 6,
2030 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
2031 { 0, { (1<<MACH_BASE) } } },
2032 /* FRdoublei: source register 1 */
2033 { "FRdoublei", FRV_OPERAND_FRDOUBLEI, HW_H_FR_DOUBLE, 17, 6,
2034 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
2035 { 0, { (1<<MACH_BASE) } } },
2036 /* FRdoublej: source register 2 */
2037 { "FRdoublej", FRV_OPERAND_FRDOUBLEJ, HW_H_FR_DOUBLE, 5, 6,
2038 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
2039 { 0, { (1<<MACH_BASE) } } },
2040 /* FRdoublek: target register */
2041 { "FRdoublek", FRV_OPERAND_FRDOUBLEK, HW_H_FR_DOUBLE, 30, 6,
2042 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
2043 { 0, { (1<<MACH_BASE) } } },
2044 /* CRi: source register 1 */
2045 { "CRi", FRV_OPERAND_CRI, HW_H_CCCR, 14, 3,
2046 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRI] } },
2047 { 0, { (1<<MACH_BASE) } } },
2048 /* CRj: source register 2 */
2049 { "CRj", FRV_OPERAND_CRJ, HW_H_CCCR, 2, 3,
2050 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ] } },
2051 { 0, { (1<<MACH_BASE) } } },
2052 /* CRj_int: destination register */
2053 { "CRj_int", FRV_OPERAND_CRJ_INT, HW_H_CCCR, 26, 2,
2054 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_INT] } },
2055 { 0, { (1<<MACH_BASE) } } },
2056 /* CRj_float: destination register */
2057 { "CRj_float", FRV_OPERAND_CRJ_FLOAT, HW_H_CCCR, 26, 2,
2058 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_FLOAT] } },
2059 { 0, { (1<<MACH_BASE) } } },
2060 /* CRk: destination register */
2061 { "CRk", FRV_OPERAND_CRK, HW_H_CCCR, 27, 3,
2062 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRK] } },
2063 { 0, { (1<<MACH_BASE) } } },
2064 /* CCi: condition register */
2065 { "CCi", FRV_OPERAND_CCI, HW_H_CCCR, 11, 3,
2066 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCI] } },
2067 { 0, { (1<<MACH_BASE) } } },
2068 /* ICCi_1: condition register */
2069 { "ICCi_1", FRV_OPERAND_ICCI_1, HW_H_ICCR, 11, 2,
2070 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_1] } },
2071 { 0, { (1<<MACH_BASE) } } },
2072 /* ICCi_2: condition register */
2073 { "ICCi_2", FRV_OPERAND_ICCI_2, HW_H_ICCR, 26, 2,
2074 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_2] } },
2075 { 0, { (1<<MACH_BASE) } } },
2076 /* ICCi_3: condition register */
2077 { "ICCi_3", FRV_OPERAND_ICCI_3, HW_H_ICCR, 1, 2,
2078 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_3] } },
2079 { 0, { (1<<MACH_BASE) } } },
2080 /* FCCi_1: condition register */
2081 { "FCCi_1", FRV_OPERAND_FCCI_1, HW_H_FCCR, 11, 2,
2082 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_1] } },
2083 { 0, { (1<<MACH_BASE) } } },
2084 /* FCCi_2: condition register */
2085 { "FCCi_2", FRV_OPERAND_FCCI_2, HW_H_FCCR, 26, 2,
2086 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_2] } },
2087 { 0, { (1<<MACH_BASE) } } },
2088 /* FCCi_3: condition register */
2089 { "FCCi_3", FRV_OPERAND_FCCI_3, HW_H_FCCR, 1, 2,
2090 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_3] } },
2091 { 0, { (1<<MACH_BASE) } } },
2092 /* FCCk: condition register */
2093 { "FCCk", FRV_OPERAND_FCCK, HW_H_FCCR, 26, 2,
2094 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCK] } },
2095 { 0, { (1<<MACH_BASE) } } },
2096 /* eir: exception insn reg */
2097 { "eir", FRV_OPERAND_EIR, HW_H_UINT, 17, 6,
2098 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_EIR] } },
2099 { 0, { (1<<MACH_BASE) } } },
2100 /* s10: 10 bit signed immediate */
2101 { "s10", FRV_OPERAND_S10, HW_H_SINT, 9, 10,
2102 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S10] } },
2103 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
2104 /* u16: 16 bit unsigned immediate */
2105 { "u16", FRV_OPERAND_U16, HW_H_UINT, 15, 16,
2106 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
2107 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
2108 /* s16: 16 bit signed immediate */
2109 { "s16", FRV_OPERAND_S16, HW_H_SINT, 15, 16,
2110 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } },
2111 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
2112 /* s6: 6 bit signed immediate */
2113 { "s6", FRV_OPERAND_S6, HW_H_SINT, 5, 6,
2114 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6] } },
2115 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
2116 /* s6_1: 6 bit signed immediate */
2117 { "s6_1", FRV_OPERAND_S6_1, HW_H_SINT, 11, 6,
2118 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6_1] } },
2119 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
2120 /* u6: 6 bit unsigned immediate */
2121 { "u6", FRV_OPERAND_U6, HW_H_UINT, 5, 6,
2122 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U6] } },
2123 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
2124 /* s5: 5 bit signed immediate */
2125 { "s5", FRV_OPERAND_S5, HW_H_SINT, 4, 5,
2126 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S5] } },
2127 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
2128 /* cond: conditional arithmetic */
2129 { "cond", FRV_OPERAND_COND, HW_H_UINT, 8, 1,
2130 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_COND] } },
2131 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
2132 /* ccond: lr branch condition */
2133 { "ccond", FRV_OPERAND_CCOND, HW_H_UINT, 12, 1,
2134 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCOND] } },
2135 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
2136 /* hint: 2 bit branch predictor */
2137 { "hint", FRV_OPERAND_HINT, HW_H_UINT, 17, 2,
2138 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
2139 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
2140 /* hint_taken: 2 bit branch predictor */
2141 { "hint_taken", FRV_OPERAND_HINT_TAKEN, HW_H_HINT_TAKEN, 17, 2,
2142 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
2143 { 0, { (1<<MACH_BASE) } } },
2144 /* hint_not_taken: 2 bit branch predictor */
2145 { "hint_not_taken", FRV_OPERAND_HINT_NOT_TAKEN, HW_H_HINT_NOT_TAKEN, 17, 2,
2146 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
2147 { 0, { (1<<MACH_BASE) } } },
2148 /* LI: link indicator */
2149 { "LI", FRV_OPERAND_LI, HW_H_UINT, 25, 1,
2150 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LI] } },
2151 { 0, { (1<<MACH_BASE) } } },
2152 /* lock: cache lock indicator */
2153 { "lock", FRV_OPERAND_LOCK, HW_H_UINT, 25, 1,
2154 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LOCK] } },
2155 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
2156 /* debug: debug mode indicator */
2157 { "debug", FRV_OPERAND_DEBUG, HW_H_UINT, 25, 1,
2158 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_DEBUG] } },
2159 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
2160 /* A: all accumulator indicator */
2161 { "A", FRV_OPERAND_A, HW_H_UINT, 17, 1,
2162 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } },
2163 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
2164 /* ae: all entries indicator */
2165 { "ae", FRV_OPERAND_AE, HW_H_UINT, 25, 1,
2166 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_AE] } },
2167 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
2168 /* label16: 18 bit pc relative address */
2169 { "label16", FRV_OPERAND_LABEL16, HW_H_IADDR, 15, 16,
2170 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABEL16] } },
2171 { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
2172 /* label24: 26 bit pc relative address */
2173 { "label24", FRV_OPERAND_LABEL24, HW_H_IADDR, 17, 24,
2174 { 2, { (const PTR) &FRV_F_LABEL24_MULTI_IFIELD[0] } },
2175 { 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } },
2176 /* FRintieven: (even) source register 1 */
2177 { "FRintieven", FRV_OPERAND_FRINTIEVEN, HW_H_FR_INT, 17, 6,
2178 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
2179 { 0, { (1<<MACH_BASE) } } },
2180 /* FRintjeven: (even) source register 2 */
2181 { "FRintjeven", FRV_OPERAND_FRINTJEVEN, HW_H_FR_INT, 5, 6,
2182 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
2183 { 0, { (1<<MACH_BASE) } } },
2184 /* FRintkeven: (even) target register */
2185 { "FRintkeven", FRV_OPERAND_FRINTKEVEN, HW_H_FR_INT, 30, 6,
2186 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
2187 { 0, { (1<<MACH_BASE) } } },
2188 /* d12: 12 bit signed immediate */
2189 { "d12", FRV_OPERAND_D12, HW_H_SINT, 11, 12,
2190 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } },
2191 { 0, { (1<<MACH_BASE) } } },
2192 /* s12: 12 bit signed immediate */
2193 { "s12", FRV_OPERAND_S12, HW_H_SINT, 11, 12,
2194 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } },
2195 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
2196 /* u12: 12 bit signed immediate */
2197 { "u12", FRV_OPERAND_U12, HW_H_SINT, 5, 12,
2198 { 2, { (const PTR) &FRV_F_U12_MULTI_IFIELD[0] } },
2199 { 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } } },
2200 /* spr: special purpose register */
2201 { "spr", FRV_OPERAND_SPR, HW_H_SPR, 17, 12,
2202 { 2, { (const PTR) &FRV_F_SPR_MULTI_IFIELD[0] } },
2203 { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
2204 /* ulo16: 16 bit unsigned immediate, for #lo() */
2205 { "ulo16", FRV_OPERAND_ULO16, HW_H_UINT, 15, 16,
2206 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
2207 { 0, { (1<<MACH_BASE) } } },
2208 /* slo16: 16 bit unsigned immediate, for #lo() */
2209 { "slo16", FRV_OPERAND_SLO16, HW_H_SINT, 15, 16,
2210 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } },
2211 { 0, { (1<<MACH_BASE) } } },
2212 /* uhi16: 16 bit unsigned immediate, for #hi() */
2213 { "uhi16", FRV_OPERAND_UHI16, HW_H_UINT, 15, 16,
2214 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
2215 { 0, { (1<<MACH_BASE) } } },
2216 /* psr_esr: PSR.ESR bit */
2217 { "psr_esr", FRV_OPERAND_PSR_ESR, HW_H_PSR_ESR, 0, 0,
2218 { 0, { (const PTR) 0 } },
2219 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
2220 /* psr_s: PSR.S bit */
2221 { "psr_s", FRV_OPERAND_PSR_S, HW_H_PSR_S, 0, 0,
2222 { 0, { (const PTR) 0 } },
2223 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
2224 /* psr_ps: PSR.PS bit */
2225 { "psr_ps", FRV_OPERAND_PSR_PS, HW_H_PSR_PS, 0, 0,
2226 { 0, { (const PTR) 0 } },
2227 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
2228 /* psr_et: PSR.ET bit */
2229 { "psr_et", FRV_OPERAND_PSR_ET, HW_H_PSR_ET, 0, 0,
2230 { 0, { (const PTR) 0 } },
2231 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
2232 /* bpsr_bs: BPSR.BS bit */
2233 { "bpsr_bs", FRV_OPERAND_BPSR_BS, HW_H_BPSR_BS, 0, 0,
2234 { 0, { (const PTR) 0 } },
2235 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
2236 /* bpsr_bet: BPSR.BET bit */
2237 { "bpsr_bet", FRV_OPERAND_BPSR_BET, HW_H_BPSR_BET, 0, 0,
2238 { 0, { (const PTR) 0 } },
2239 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
2240 /* tbr_tba: TBR.TBA */
2241 { "tbr_tba", FRV_OPERAND_TBR_TBA, HW_H_TBR_TBA, 0, 0,
2242 { 0, { (const PTR) 0 } },
2243 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
2244 /* tbr_tt: TBR.TT */
2245 { "tbr_tt", FRV_OPERAND_TBR_TT, HW_H_TBR_TT, 0, 0,
2246 { 0, { (const PTR) 0 } },
2247 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
2250 { 0, { (const PTR) 0 } },
2257 /* The instruction table. */
2259 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2260 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
2261 #define A(a) (1 << CGEN_INSN_##a)
2263 #define A(a) (1 << CGEN_INSN_/**/a)
2266 static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
2268 /* Special null first entry.
2269 A `num' value of zero is thus invalid.
2270 Also, the special `invalid' insn resides here. */
2271 { 0, 0, 0, 0, {0, {0}} },
2272 /* add$pack $GRi,$GRj,$GRk */
2274 FRV_INSN_ADD, "add", "add", 32,
2275 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2277 /* sub$pack $GRi,$GRj,$GRk */
2279 FRV_INSN_SUB, "sub", "sub", 32,
2280 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2282 /* and$pack $GRi,$GRj,$GRk */
2284 FRV_INSN_AND, "and", "and", 32,
2285 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2287 /* or$pack $GRi,$GRj,$GRk */
2289 FRV_INSN_OR, "or", "or", 32,
2290 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2292 /* xor$pack $GRi,$GRj,$GRk */
2294 FRV_INSN_XOR, "xor", "xor", 32,
2295 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2297 /* not$pack $GRj,$GRk */
2299 FRV_INSN_NOT, "not", "not", 32,
2300 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2302 /* sdiv$pack $GRi,$GRj,$GRk */
2304 FRV_INSN_SDIV, "sdiv", "sdiv", 32,
2305 { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2307 /* nsdiv$pack $GRi,$GRj,$GRk */
2309 FRV_INSN_NSDIV, "nsdiv", "nsdiv", 32,
2310 { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
2312 /* udiv$pack $GRi,$GRj,$GRk */
2314 FRV_INSN_UDIV, "udiv", "udiv", 32,
2315 { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2317 /* nudiv$pack $GRi,$GRj,$GRk */
2319 FRV_INSN_NUDIV, "nudiv", "nudiv", 32,
2320 { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
2322 /* smul$pack $GRi,$GRj,$GRdoublek */
2324 FRV_INSN_SMUL, "smul", "smul", 32,
2325 { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2327 /* umul$pack $GRi,$GRj,$GRdoublek */
2329 FRV_INSN_UMUL, "umul", "umul", 32,
2330 { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2332 /* sll$pack $GRi,$GRj,$GRk */
2334 FRV_INSN_SLL, "sll", "sll", 32,
2335 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2337 /* srl$pack $GRi,$GRj,$GRk */
2339 FRV_INSN_SRL, "srl", "srl", 32,
2340 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2342 /* sra$pack $GRi,$GRj,$GRk */
2344 FRV_INSN_SRA, "sra", "sra", 32,
2345 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2347 /* scan$pack $GRi,$GRj,$GRk */
2349 FRV_INSN_SCAN, "scan", "scan", 32,
2350 { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2352 /* cadd$pack $GRi,$GRj,$GRk,$CCi,$cond */
2354 FRV_INSN_CADD, "cadd", "cadd", 32,
2355 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2357 /* csub$pack $GRi,$GRj,$GRk,$CCi,$cond */
2359 FRV_INSN_CSUB, "csub", "csub", 32,
2360 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2362 /* cand$pack $GRi,$GRj,$GRk,$CCi,$cond */
2364 FRV_INSN_CAND, "cand", "cand", 32,
2365 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2367 /* cor$pack $GRi,$GRj,$GRk,$CCi,$cond */
2369 FRV_INSN_COR, "cor", "cor", 32,
2370 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2372 /* cxor$pack $GRi,$GRj,$GRk,$CCi,$cond */
2374 FRV_INSN_CXOR, "cxor", "cxor", 32,
2375 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2377 /* cnot$pack $GRj,$GRk,$CCi,$cond */
2379 FRV_INSN_CNOT, "cnot", "cnot", 32,
2380 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2382 /* csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
2384 FRV_INSN_CSMUL, "csmul", "csmul", 32,
2385 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2387 /* csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
2389 FRV_INSN_CSDIV, "csdiv", "csdiv", 32,
2390 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2392 /* cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
2394 FRV_INSN_CUDIV, "cudiv", "cudiv", 32,
2395 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2397 /* csll$pack $GRi,$GRj,$GRk,$CCi,$cond */
2399 FRV_INSN_CSLL, "csll", "csll", 32,
2400 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2402 /* csrl$pack $GRi,$GRj,$GRk,$CCi,$cond */
2404 FRV_INSN_CSRL, "csrl", "csrl", 32,
2405 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2407 /* csra$pack $GRi,$GRj,$GRk,$CCi,$cond */
2409 FRV_INSN_CSRA, "csra", "csra", 32,
2410 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2412 /* cscan$pack $GRi,$GRj,$GRk,$CCi,$cond */
2414 FRV_INSN_CSCAN, "cscan", "cscan", 32,
2415 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2417 /* addcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2419 FRV_INSN_ADDCC, "addcc", "addcc", 32,
2420 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2422 /* subcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2424 FRV_INSN_SUBCC, "subcc", "subcc", 32,
2425 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2427 /* andcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2429 FRV_INSN_ANDCC, "andcc", "andcc", 32,
2430 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2432 /* orcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2434 FRV_INSN_ORCC, "orcc", "orcc", 32,
2435 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2437 /* xorcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2439 FRV_INSN_XORCC, "xorcc", "xorcc", 32,
2440 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2442 /* sllcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2444 FRV_INSN_SLLCC, "sllcc", "sllcc", 32,
2445 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2447 /* srlcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2449 FRV_INSN_SRLCC, "srlcc", "srlcc", 32,
2450 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2452 /* sracc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2454 FRV_INSN_SRACC, "sracc", "sracc", 32,
2455 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2457 /* smulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
2459 FRV_INSN_SMULCC, "smulcc", "smulcc", 32,
2460 { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2462 /* umulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
2464 FRV_INSN_UMULCC, "umulcc", "umulcc", 32,
2465 { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2467 /* caddcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2469 FRV_INSN_CADDCC, "caddcc", "caddcc", 32,
2470 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2472 /* csubcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2474 FRV_INSN_CSUBCC, "csubcc", "csubcc", 32,
2475 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2477 /* csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
2479 FRV_INSN_CSMULCC, "csmulcc", "csmulcc", 32,
2480 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2482 /* candcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2484 FRV_INSN_CANDCC, "candcc", "candcc", 32,
2485 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2487 /* corcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2489 FRV_INSN_CORCC, "corcc", "corcc", 32,
2490 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2492 /* cxorcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2494 FRV_INSN_CXORCC, "cxorcc", "cxorcc", 32,
2495 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2497 /* csllcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2499 FRV_INSN_CSLLCC, "csllcc", "csllcc", 32,
2500 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2502 /* csrlcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2504 FRV_INSN_CSRLCC, "csrlcc", "csrlcc", 32,
2505 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2507 /* csracc$pack $GRi,$GRj,$GRk,$CCi,$cond */
2509 FRV_INSN_CSRACC, "csracc", "csracc", 32,
2510 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2512 /* addx$pack $GRi,$GRj,$GRk,$ICCi_1 */
2514 FRV_INSN_ADDX, "addx", "addx", 32,
2515 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2517 /* subx$pack $GRi,$GRj,$GRk,$ICCi_1 */
2519 FRV_INSN_SUBX, "subx", "subx", 32,
2520 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2522 /* addxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2524 FRV_INSN_ADDXCC, "addxcc", "addxcc", 32,
2525 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2527 /* subxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
2529 FRV_INSN_SUBXCC, "subxcc", "subxcc", 32,
2530 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2532 /* addi$pack $GRi,$s12,$GRk */
2534 FRV_INSN_ADDI, "addi", "addi", 32,
2535 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2537 /* subi$pack $GRi,$s12,$GRk */
2539 FRV_INSN_SUBI, "subi", "subi", 32,
2540 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2542 /* andi$pack $GRi,$s12,$GRk */
2544 FRV_INSN_ANDI, "andi", "andi", 32,
2545 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2547 /* ori$pack $GRi,$s12,$GRk */
2549 FRV_INSN_ORI, "ori", "ori", 32,
2550 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2552 /* xori$pack $GRi,$s12,$GRk */
2554 FRV_INSN_XORI, "xori", "xori", 32,
2555 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2557 /* sdivi$pack $GRi,$s12,$GRk */
2559 FRV_INSN_SDIVI, "sdivi", "sdivi", 32,
2560 { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2562 /* nsdivi$pack $GRi,$s12,$GRk */
2564 FRV_INSN_NSDIVI, "nsdivi", "nsdivi", 32,
2565 { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
2567 /* udivi$pack $GRi,$s12,$GRk */
2569 FRV_INSN_UDIVI, "udivi", "udivi", 32,
2570 { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2572 /* nudivi$pack $GRi,$s12,$GRk */
2574 FRV_INSN_NUDIVI, "nudivi", "nudivi", 32,
2575 { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
2577 /* smuli$pack $GRi,$s12,$GRdoublek */
2579 FRV_INSN_SMULI, "smuli", "smuli", 32,
2580 { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2582 /* umuli$pack $GRi,$s12,$GRdoublek */
2584 FRV_INSN_UMULI, "umuli", "umuli", 32,
2585 { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2587 /* slli$pack $GRi,$s12,$GRk */
2589 FRV_INSN_SLLI, "slli", "slli", 32,
2590 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2592 /* srli$pack $GRi,$s12,$GRk */
2594 FRV_INSN_SRLI, "srli", "srli", 32,
2595 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2597 /* srai$pack $GRi,$s12,$GRk */
2599 FRV_INSN_SRAI, "srai", "srai", 32,
2600 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2602 /* scani$pack $GRi,$s12,$GRk */
2604 FRV_INSN_SCANI, "scani", "scani", 32,
2605 { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2607 /* addicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2609 FRV_INSN_ADDICC, "addicc", "addicc", 32,
2610 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2612 /* subicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2614 FRV_INSN_SUBICC, "subicc", "subicc", 32,
2615 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2617 /* andicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2619 FRV_INSN_ANDICC, "andicc", "andicc", 32,
2620 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2622 /* oricc$pack $GRi,$s10,$GRk,$ICCi_1 */
2624 FRV_INSN_ORICC, "oricc", "oricc", 32,
2625 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2627 /* xoricc$pack $GRi,$s10,$GRk,$ICCi_1 */
2629 FRV_INSN_XORICC, "xoricc", "xoricc", 32,
2630 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2632 /* smulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
2634 FRV_INSN_SMULICC, "smulicc", "smulicc", 32,
2635 { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2637 /* umulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
2639 FRV_INSN_UMULICC, "umulicc", "umulicc", 32,
2640 { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2642 /* sllicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2644 FRV_INSN_SLLICC, "sllicc", "sllicc", 32,
2645 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2647 /* srlicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2649 FRV_INSN_SRLICC, "srlicc", "srlicc", 32,
2650 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2652 /* sraicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2654 FRV_INSN_SRAICC, "sraicc", "sraicc", 32,
2655 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2657 /* addxi$pack $GRi,$s10,$GRk,$ICCi_1 */
2659 FRV_INSN_ADDXI, "addxi", "addxi", 32,
2660 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2662 /* subxi$pack $GRi,$s10,$GRk,$ICCi_1 */
2664 FRV_INSN_SUBXI, "subxi", "subxi", 32,
2665 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2667 /* addxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2669 FRV_INSN_ADDXICC, "addxicc", "addxicc", 32,
2670 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2672 /* subxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
2674 FRV_INSN_SUBXICC, "subxicc", "subxicc", 32,
2675 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2677 /* cmpb$pack $GRi,$GRj,$ICCi_1 */
2679 FRV_INSN_CMPB, "cmpb", "cmpb", 32,
2680 { 0, { (1<<MACH_FR400), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_NONE } }
2682 /* cmpba$pack $GRi,$GRj,$ICCi_1 */
2684 FRV_INSN_CMPBA, "cmpba", "cmpba", 32,
2685 { 0, { (1<<MACH_FR400), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_NONE } }
2687 /* setlo$pack $ulo16,$GRklo */
2689 FRV_INSN_SETLO, "setlo", "setlo", 32,
2690 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2692 /* sethi$pack $uhi16,$GRkhi */
2694 FRV_INSN_SETHI, "sethi", "sethi", 32,
2695 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2697 /* setlos$pack $slo16,$GRk */
2699 FRV_INSN_SETLOS, "setlos", "setlos", 32,
2700 { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
2702 /* ldsb$pack @($GRi,$GRj),$GRk */
2704 FRV_INSN_LDSB, "ldsb", "ldsb", 32,
2705 { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2707 /* ldub$pack @($GRi,$GRj),$GRk */
2709 FRV_INSN_LDUB, "ldub", "ldub", 32,
2710 { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2712 /* ldsh$pack @($GRi,$GRj),$GRk */
2714 FRV_INSN_LDSH, "ldsh", "ldsh", 32,
2715 { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2717 /* lduh$pack @($GRi,$GRj),$GRk */
2719 FRV_INSN_LDUH, "lduh", "lduh", 32,
2720 { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2722 /* ld$pack @($GRi,$GRj),$GRk */
2724 FRV_INSN_LD, "ld", "ld", 32,
2725 { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2727 /* ldbf$pack @($GRi,$GRj),$FRintk */
2729 FRV_INSN_LDBF, "ldbf", "ldbf", 32,
2730 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2732 /* ldhf$pack @($GRi,$GRj),$FRintk */
2734 FRV_INSN_LDHF, "ldhf", "ldhf", 32,
2735 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2737 /* ldf$pack @($GRi,$GRj),$FRintk */
2739 FRV_INSN_LDF, "ldf", "ldf", 32,
2740 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2742 /* ldc$pack @($GRi,$GRj),$CPRk */
2744 FRV_INSN_LDC, "ldc", "ldc", 32,
2745 { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2747 /* nldsb$pack @($GRi,$GRj),$GRk */
2749 FRV_INSN_NLDSB, "nldsb", "nldsb", 32,
2750 { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2752 /* nldub$pack @($GRi,$GRj),$GRk */
2754 FRV_INSN_NLDUB, "nldub", "nldub", 32,
2755 { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2757 /* nldsh$pack @($GRi,$GRj),$GRk */
2759 FRV_INSN_NLDSH, "nldsh", "nldsh", 32,
2760 { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2762 /* nlduh$pack @($GRi,$GRj),$GRk */
2764 FRV_INSN_NLDUH, "nlduh", "nlduh", 32,
2765 { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2767 /* nld$pack @($GRi,$GRj),$GRk */
2769 FRV_INSN_NLD, "nld", "nld", 32,
2770 { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2772 /* nldbf$pack @($GRi,$GRj),$FRintk */
2774 FRV_INSN_NLDBF, "nldbf", "nldbf", 32,
2775 { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2777 /* nldhf$pack @($GRi,$GRj),$FRintk */
2779 FRV_INSN_NLDHF, "nldhf", "nldhf", 32,
2780 { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2782 /* nldf$pack @($GRi,$GRj),$FRintk */
2784 FRV_INSN_NLDF, "nldf", "nldf", 32,
2785 { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2787 /* ldd$pack @($GRi,$GRj),$GRdoublek */
2789 FRV_INSN_LDD, "ldd", "ldd", 32,
2790 { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2792 /* lddf$pack @($GRi,$GRj),$FRdoublek */
2794 FRV_INSN_LDDF, "lddf", "lddf", 32,
2795 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2797 /* lddc$pack @($GRi,$GRj),$CPRdoublek */
2799 FRV_INSN_LDDC, "lddc", "lddc", 32,
2800 { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2802 /* nldd$pack @($GRi,$GRj),$GRdoublek */
2804 FRV_INSN_NLDD, "nldd", "nldd", 32,
2805 { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2807 /* nlddf$pack @($GRi,$GRj),$FRdoublek */
2809 FRV_INSN_NLDDF, "nlddf", "nlddf", 32,
2810 { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2812 /* ldq$pack @($GRi,$GRj),$GRk */
2814 FRV_INSN_LDQ, "ldq", "ldq", 32,
2815 { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2817 /* ldqf$pack @($GRi,$GRj),$FRintk */
2819 FRV_INSN_LDQF, "ldqf", "ldqf", 32,
2820 { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2822 /* ldqc$pack @($GRi,$GRj),$CPRk */
2824 FRV_INSN_LDQC, "ldqc", "ldqc", 32,
2825 { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2827 /* nldq$pack @($GRi,$GRj),$GRk */
2829 FRV_INSN_NLDQ, "nldq", "nldq", 32,
2830 { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2832 /* nldqf$pack @($GRi,$GRj),$FRintk */
2834 FRV_INSN_NLDQF, "nldqf", "nldqf", 32,
2835 { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2837 /* ldsbu$pack @($GRi,$GRj),$GRk */
2839 FRV_INSN_LDSBU, "ldsbu", "ldsbu", 32,
2840 { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2842 /* ldubu$pack @($GRi,$GRj),$GRk */
2844 FRV_INSN_LDUBU, "ldubu", "ldubu", 32,
2845 { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2847 /* ldshu$pack @($GRi,$GRj),$GRk */
2849 FRV_INSN_LDSHU, "ldshu", "ldshu", 32,
2850 { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2852 /* lduhu$pack @($GRi,$GRj),$GRk */
2854 FRV_INSN_LDUHU, "lduhu", "lduhu", 32,
2855 { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2857 /* ldu$pack @($GRi,$GRj),$GRk */
2859 FRV_INSN_LDU, "ldu", "ldu", 32,
2860 { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2862 /* nldsbu$pack @($GRi,$GRj),$GRk */
2864 FRV_INSN_NLDSBU, "nldsbu", "nldsbu", 32,
2865 { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2867 /* nldubu$pack @($GRi,$GRj),$GRk */
2869 FRV_INSN_NLDUBU, "nldubu", "nldubu", 32,
2870 { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2872 /* nldshu$pack @($GRi,$GRj),$GRk */
2874 FRV_INSN_NLDSHU, "nldshu", "nldshu", 32,
2875 { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2877 /* nlduhu$pack @($GRi,$GRj),$GRk */
2879 FRV_INSN_NLDUHU, "nlduhu", "nlduhu", 32,
2880 { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2882 /* nldu$pack @($GRi,$GRj),$GRk */
2884 FRV_INSN_NLDU, "nldu", "nldu", 32,
2885 { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2887 /* ldbfu$pack @($GRi,$GRj),$FRintk */
2889 FRV_INSN_LDBFU, "ldbfu", "ldbfu", 32,
2890 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2892 /* ldhfu$pack @($GRi,$GRj),$FRintk */
2894 FRV_INSN_LDHFU, "ldhfu", "ldhfu", 32,
2895 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2897 /* ldfu$pack @($GRi,$GRj),$FRintk */
2899 FRV_INSN_LDFU, "ldfu", "ldfu", 32,
2900 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2902 /* ldcu$pack @($GRi,$GRj),$CPRk */
2904 FRV_INSN_LDCU, "ldcu", "ldcu", 32,
2905 { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2907 /* nldbfu$pack @($GRi,$GRj),$FRintk */
2909 FRV_INSN_NLDBFU, "nldbfu", "nldbfu", 32,
2910 { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2912 /* nldhfu$pack @($GRi,$GRj),$FRintk */
2914 FRV_INSN_NLDHFU, "nldhfu", "nldhfu", 32,
2915 { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2917 /* nldfu$pack @($GRi,$GRj),$FRintk */
2919 FRV_INSN_NLDFU, "nldfu", "nldfu", 32,
2920 { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2922 /* lddu$pack @($GRi,$GRj),$GRdoublek */
2924 FRV_INSN_LDDU, "lddu", "lddu", 32,
2925 { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2927 /* nlddu$pack @($GRi,$GRj),$GRdoublek */
2929 FRV_INSN_NLDDU, "nlddu", "nlddu", 32,
2930 { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2932 /* lddfu$pack @($GRi,$GRj),$FRdoublek */
2934 FRV_INSN_LDDFU, "lddfu", "lddfu", 32,
2935 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2937 /* lddcu$pack @($GRi,$GRj),$CPRdoublek */
2939 FRV_INSN_LDDCU, "lddcu", "lddcu", 32,
2940 { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2942 /* nlddfu$pack @($GRi,$GRj),$FRdoublek */
2944 FRV_INSN_NLDDFU, "nlddfu", "nlddfu", 32,
2945 { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2947 /* ldqu$pack @($GRi,$GRj),$GRk */
2949 FRV_INSN_LDQU, "ldqu", "ldqu", 32,
2950 { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2952 /* nldqu$pack @($GRi,$GRj),$GRk */
2954 FRV_INSN_NLDQU, "nldqu", "nldqu", 32,
2955 { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2957 /* ldqfu$pack @($GRi,$GRj),$FRintk */
2959 FRV_INSN_LDQFU, "ldqfu", "ldqfu", 32,
2960 { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2962 /* ldqcu$pack @($GRi,$GRj),$CPRk */
2964 FRV_INSN_LDQCU, "ldqcu", "ldqcu", 32,
2965 { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2967 /* nldqfu$pack @($GRi,$GRj),$FRintk */
2969 FRV_INSN_NLDQFU, "nldqfu", "nldqfu", 32,
2970 { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
2972 /* ldsbi$pack @($GRi,$d12),$GRk */
2974 FRV_INSN_LDSBI, "ldsbi", "ldsbi", 32,
2975 { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2977 /* ldshi$pack @($GRi,$d12),$GRk */
2979 FRV_INSN_LDSHI, "ldshi", "ldshi", 32,
2980 { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2982 /* ldi$pack @($GRi,$d12),$GRk */
2984 FRV_INSN_LDI, "ldi", "ldi", 32,
2985 { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2987 /* ldubi$pack @($GRi,$d12),$GRk */
2989 FRV_INSN_LDUBI, "ldubi", "ldubi", 32,
2990 { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2992 /* lduhi$pack @($GRi,$d12),$GRk */
2994 FRV_INSN_LDUHI, "lduhi", "lduhi", 32,
2995 { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
2997 /* ldbfi$pack @($GRi,$d12),$FRintk */
2999 FRV_INSN_LDBFI, "ldbfi", "ldbfi", 32,
3000 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3002 /* ldhfi$pack @($GRi,$d12),$FRintk */
3004 FRV_INSN_LDHFI, "ldhfi", "ldhfi", 32,
3005 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3007 /* ldfi$pack @($GRi,$d12),$FRintk */
3009 FRV_INSN_LDFI, "ldfi", "ldfi", 32,
3010 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3012 /* nldsbi$pack @($GRi,$d12),$GRk */
3014 FRV_INSN_NLDSBI, "nldsbi", "nldsbi", 32,
3015 { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3017 /* nldubi$pack @($GRi,$d12),$GRk */
3019 FRV_INSN_NLDUBI, "nldubi", "nldubi", 32,
3020 { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3022 /* nldshi$pack @($GRi,$d12),$GRk */
3024 FRV_INSN_NLDSHI, "nldshi", "nldshi", 32,
3025 { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3027 /* nlduhi$pack @($GRi,$d12),$GRk */
3029 FRV_INSN_NLDUHI, "nlduhi", "nlduhi", 32,
3030 { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3032 /* nldi$pack @($GRi,$d12),$GRk */
3034 FRV_INSN_NLDI, "nldi", "nldi", 32,
3035 { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3037 /* nldbfi$pack @($GRi,$d12),$FRintk */
3039 FRV_INSN_NLDBFI, "nldbfi", "nldbfi", 32,
3040 { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3042 /* nldhfi$pack @($GRi,$d12),$FRintk */
3044 FRV_INSN_NLDHFI, "nldhfi", "nldhfi", 32,
3045 { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3047 /* nldfi$pack @($GRi,$d12),$FRintk */
3049 FRV_INSN_NLDFI, "nldfi", "nldfi", 32,
3050 { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3052 /* lddi$pack @($GRi,$d12),$GRdoublek */
3054 FRV_INSN_LDDI, "lddi", "lddi", 32,
3055 { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3057 /* lddfi$pack @($GRi,$d12),$FRdoublek */
3059 FRV_INSN_LDDFI, "lddfi", "lddfi", 32,
3060 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3062 /* nlddi$pack @($GRi,$d12),$GRdoublek */
3064 FRV_INSN_NLDDI, "nlddi", "nlddi", 32,
3065 { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3067 /* nlddfi$pack @($GRi,$d12),$FRdoublek */
3069 FRV_INSN_NLDDFI, "nlddfi", "nlddfi", 32,
3070 { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3072 /* ldqi$pack @($GRi,$d12),$GRk */
3074 FRV_INSN_LDQI, "ldqi", "ldqi", 32,
3075 { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3077 /* ldqfi$pack @($GRi,$d12),$FRintk */
3079 FRV_INSN_LDQFI, "ldqfi", "ldqfi", 32,
3080 { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3082 /* nldqi$pack @($GRi,$d12),$GRk */
3084 FRV_INSN_NLDQI, "nldqi", "nldqi", 32,
3085 { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3087 /* nldqfi$pack @($GRi,$d12),$FRintk */
3089 FRV_INSN_NLDQFI, "nldqfi", "nldqfi", 32,
3090 { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3092 /* stb$pack $GRk,@($GRi,$GRj) */
3094 FRV_INSN_STB, "stb", "stb", 32,
3095 { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3097 /* sth$pack $GRk,@($GRi,$GRj) */
3099 FRV_INSN_STH, "sth", "sth", 32,
3100 { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3102 /* st$pack $GRk,@($GRi,$GRj) */
3104 FRV_INSN_ST, "st", "st", 32,
3105 { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3107 /* stbf$pack $FRintk,@($GRi,$GRj) */
3109 FRV_INSN_STBF, "stbf", "stbf", 32,
3110 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3112 /* sthf$pack $FRintk,@($GRi,$GRj) */
3114 FRV_INSN_STHF, "sthf", "sthf", 32,
3115 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3117 /* stf$pack $FRintk,@($GRi,$GRj) */
3119 FRV_INSN_STF, "stf", "stf", 32,
3120 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3122 /* stc$pack $CPRk,@($GRi,$GRj) */
3124 FRV_INSN_STC, "stc", "stc", 32,
3125 { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3127 /* rstb$pack $GRk,@($GRi,$GRj) */
3129 FRV_INSN_RSTB, "rstb", "rstb", 32,
3130 { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3132 /* rsth$pack $GRk,@($GRi,$GRj) */
3134 FRV_INSN_RSTH, "rsth", "rsth", 32,
3135 { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3137 /* rst$pack $GRk,@($GRi,$GRj) */
3139 FRV_INSN_RST, "rst", "rst", 32,
3140 { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3142 /* rstbf$pack $FRintk,@($GRi,$GRj) */
3144 FRV_INSN_RSTBF, "rstbf", "rstbf", 32,
3145 { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3147 /* rsthf$pack $FRintk,@($GRi,$GRj) */
3149 FRV_INSN_RSTHF, "rsthf", "rsthf", 32,
3150 { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3152 /* rstf$pack $FRintk,@($GRi,$GRj) */
3154 FRV_INSN_RSTF, "rstf", "rstf", 32,
3155 { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3157 /* std$pack $GRk,@($GRi,$GRj) */
3159 FRV_INSN_STD, "std", "std", 32,
3160 { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3162 /* stdf$pack $FRk,@($GRi,$GRj) */
3164 FRV_INSN_STDF, "stdf", "stdf", 32,
3165 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3167 /* stdc$pack $CPRk,@($GRi,$GRj) */
3169 FRV_INSN_STDC, "stdc", "stdc", 32,
3170 { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3172 /* rstd$pack $GRk,@($GRi,$GRj) */
3174 FRV_INSN_RSTD, "rstd", "rstd", 32,
3175 { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3177 /* rstdf$pack $FRk,@($GRi,$GRj) */
3179 FRV_INSN_RSTDF, "rstdf", "rstdf", 32,
3180 { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3182 /* stq$pack $GRk,@($GRi,$GRj) */
3184 FRV_INSN_STQ, "stq", "stq", 32,
3185 { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3187 /* stqf$pack $FRintk,@($GRi,$GRj) */
3189 FRV_INSN_STQF, "stqf", "stqf", 32,
3190 { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3192 /* stqc$pack $CPRk,@($GRi,$GRj) */
3194 FRV_INSN_STQC, "stqc", "stqc", 32,
3195 { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3197 /* rstq$pack $GRk,@($GRi,$GRj) */
3199 FRV_INSN_RSTQ, "rstq", "rstq", 32,
3200 { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3202 /* rstqf$pack $FRintk,@($GRi,$GRj) */
3204 FRV_INSN_RSTQF, "rstqf", "rstqf", 32,
3205 { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3207 /* stbu$pack $GRk,@($GRi,$GRj) */
3209 FRV_INSN_STBU, "stbu", "stbu", 32,
3210 { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3212 /* sthu$pack $GRk,@($GRi,$GRj) */
3214 FRV_INSN_STHU, "sthu", "sthu", 32,
3215 { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3217 /* stu$pack $GRk,@($GRi,$GRj) */
3219 FRV_INSN_STU, "stu", "stu", 32,
3220 { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3222 /* stbfu$pack $FRintk,@($GRi,$GRj) */
3224 FRV_INSN_STBFU, "stbfu", "stbfu", 32,
3225 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3227 /* sthfu$pack $FRintk,@($GRi,$GRj) */
3229 FRV_INSN_STHFU, "sthfu", "sthfu", 32,
3230 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3232 /* stfu$pack $FRintk,@($GRi,$GRj) */
3234 FRV_INSN_STFU, "stfu", "stfu", 32,
3235 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3237 /* stcu$pack $CPRk,@($GRi,$GRj) */
3239 FRV_INSN_STCU, "stcu", "stcu", 32,
3240 { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3242 /* stdu$pack $GRk,@($GRi,$GRj) */
3244 FRV_INSN_STDU, "stdu", "stdu", 32,
3245 { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3247 /* stdfu$pack $FRk,@($GRi,$GRj) */
3249 FRV_INSN_STDFU, "stdfu", "stdfu", 32,
3250 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3252 /* stdcu$pack $CPRk,@($GRi,$GRj) */
3254 FRV_INSN_STDCU, "stdcu", "stdcu", 32,
3255 { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3257 /* stqu$pack $GRk,@($GRi,$GRj) */
3259 FRV_INSN_STQU, "stqu", "stqu", 32,
3260 { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3262 /* stqfu$pack $FRintk,@($GRi,$GRj) */
3264 FRV_INSN_STQFU, "stqfu", "stqfu", 32,
3265 { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3267 /* stqcu$pack $CPRk,@($GRi,$GRj) */
3269 FRV_INSN_STQCU, "stqcu", "stqcu", 32,
3270 { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3272 /* cldsb$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3274 FRV_INSN_CLDSB, "cldsb", "cldsb", 32,
3275 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3277 /* cldub$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3279 FRV_INSN_CLDUB, "cldub", "cldub", 32,
3280 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3282 /* cldsh$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3284 FRV_INSN_CLDSH, "cldsh", "cldsh", 32,
3285 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3287 /* clduh$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3289 FRV_INSN_CLDUH, "clduh", "clduh", 32,
3290 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3292 /* cld$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3294 FRV_INSN_CLD, "cld", "cld", 32,
3295 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3297 /* cldbf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3299 FRV_INSN_CLDBF, "cldbf", "cldbf", 32,
3300 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3302 /* cldhf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3304 FRV_INSN_CLDHF, "cldhf", "cldhf", 32,
3305 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3307 /* cldf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3309 FRV_INSN_CLDF, "cldf", "cldf", 32,
3310 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3312 /* cldd$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */
3314 FRV_INSN_CLDD, "cldd", "cldd", 32,
3315 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3317 /* clddf$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */
3319 FRV_INSN_CLDDF, "clddf", "clddf", 32,
3320 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3322 /* cldq$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3324 FRV_INSN_CLDQ, "cldq", "cldq", 32,
3325 { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3327 /* cldsbu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3329 FRV_INSN_CLDSBU, "cldsbu", "cldsbu", 32,
3330 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3332 /* cldubu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3334 FRV_INSN_CLDUBU, "cldubu", "cldubu", 32,
3335 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3337 /* cldshu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3339 FRV_INSN_CLDSHU, "cldshu", "cldshu", 32,
3340 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3342 /* clduhu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3344 FRV_INSN_CLDUHU, "clduhu", "clduhu", 32,
3345 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3347 /* cldu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3349 FRV_INSN_CLDU, "cldu", "cldu", 32,
3350 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3352 /* cldbfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3354 FRV_INSN_CLDBFU, "cldbfu", "cldbfu", 32,
3355 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3357 /* cldhfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3359 FRV_INSN_CLDHFU, "cldhfu", "cldhfu", 32,
3360 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3362 /* cldfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
3364 FRV_INSN_CLDFU, "cldfu", "cldfu", 32,
3365 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3367 /* clddu$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */
3369 FRV_INSN_CLDDU, "clddu", "clddu", 32,
3370 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3372 /* clddfu$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */
3374 FRV_INSN_CLDDFU, "clddfu", "clddfu", 32,
3375 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
3377 /* cldqu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3379 FRV_INSN_CLDQU, "cldqu", "cldqu", 32,
3380 { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
3382 /* cstb$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3384 FRV_INSN_CSTB, "cstb", "cstb", 32,
3385 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3387 /* csth$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3389 FRV_INSN_CSTH, "csth", "csth", 32,
3390 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3392 /* cst$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3394 FRV_INSN_CST, "cst", "cst", 32,
3395 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3397 /* cstbf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3399 FRV_INSN_CSTBF, "cstbf", "cstbf", 32,
3400 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3402 /* csthf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3404 FRV_INSN_CSTHF, "csthf", "csthf", 32,
3405 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3407 /* cstf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3409 FRV_INSN_CSTF, "cstf", "cstf", 32,
3410 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3412 /* cstd$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3414 FRV_INSN_CSTD, "cstd", "cstd", 32,
3415 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3417 /* cstdf$pack $FRk,@($GRi,$GRj),$CCi,$cond */
3419 FRV_INSN_CSTDF, "cstdf", "cstdf", 32,
3420 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3422 /* cstq$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3424 FRV_INSN_CSTQ, "cstq", "cstq", 32,
3425 { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3427 /* cstbu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3429 FRV_INSN_CSTBU, "cstbu", "cstbu", 32,
3430 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3432 /* csthu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3434 FRV_INSN_CSTHU, "csthu", "csthu", 32,
3435 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3437 /* cstu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3439 FRV_INSN_CSTU, "cstu", "cstu", 32,
3440 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3442 /* cstbfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3444 FRV_INSN_CSTBFU, "cstbfu", "cstbfu", 32,
3445 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3447 /* csthfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3449 FRV_INSN_CSTHFU, "csthfu", "csthfu", 32,
3450 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3452 /* cstfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
3454 FRV_INSN_CSTFU, "cstfu", "cstfu", 32,
3455 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3457 /* cstdu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
3459 FRV_INSN_CSTDU, "cstdu", "cstdu", 32,
3460 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3462 /* cstdfu$pack $FRk,@($GRi,$GRj),$CCi,$cond */
3464 FRV_INSN_CSTDFU, "cstdfu", "cstdfu", 32,
3465 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3467 /* stbi$pack $GRk,@($GRi,$d12) */
3469 FRV_INSN_STBI, "stbi", "stbi", 32,
3470 { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3472 /* sthi$pack $GRk,@($GRi,$d12) */
3474 FRV_INSN_STHI, "sthi", "sthi", 32,
3475 { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3477 /* sti$pack $GRk,@($GRi,$d12) */
3479 FRV_INSN_STI, "sti", "sti", 32,
3480 { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3482 /* stbfi$pack $FRintk,@($GRi,$d12) */
3484 FRV_INSN_STBFI, "stbfi", "stbfi", 32,
3485 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3487 /* sthfi$pack $FRintk,@($GRi,$d12) */
3489 FRV_INSN_STHFI, "sthfi", "sthfi", 32,
3490 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3492 /* stfi$pack $FRintk,@($GRi,$d12) */
3494 FRV_INSN_STFI, "stfi", "stfi", 32,
3495 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3497 /* stdi$pack $GRk,@($GRi,$d12) */
3499 FRV_INSN_STDI, "stdi", "stdi", 32,
3500 { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3502 /* stdfi$pack $FRk,@($GRi,$d12) */
3504 FRV_INSN_STDFI, "stdfi", "stdfi", 32,
3505 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
3507 /* stqi$pack $GRk,@($GRi,$d12) */
3509 FRV_INSN_STQI, "stqi", "stqi", 32,
3510 { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3512 /* stqfi$pack $FRintk,@($GRi,$d12) */
3514 FRV_INSN_STQFI, "stqfi", "stqfi", 32,
3515 { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
3517 /* swap$pack @($GRi,$GRj),$GRk */
3519 FRV_INSN_SWAP, "swap", "swap", 32,
3520 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
3522 /* swapi$pack @($GRi,$d12),$GRk */
3524 FRV_INSN_SWAPI, "swapi", "swapi", 32,
3525 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
3527 /* cswap$pack @($GRi,$GRj),$GRk,$CCi,$cond */
3529 FRV_INSN_CSWAP, "cswap", "cswap", 32,
3530 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
3532 /* movgf$pack $GRj,$FRintk */
3534 FRV_INSN_MOVGF, "movgf", "movgf", 32,
3535 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3537 /* movfg$pack $FRintk,$GRj */
3539 FRV_INSN_MOVFG, "movfg", "movfg", 32,
3540 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3542 /* movgfd$pack $GRj,$FRintk */
3544 FRV_INSN_MOVGFD, "movgfd", "movgfd", 32,
3545 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3547 /* movfgd$pack $FRintk,$GRj */
3549 FRV_INSN_MOVFGD, "movfgd", "movfgd", 32,
3550 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3552 /* movgfq$pack $GRj,$FRintk */
3554 FRV_INSN_MOVGFQ, "movgfq", "movgfq", 32,
3555 { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_4 } }
3557 /* movfgq$pack $FRintk,$GRj */
3559 FRV_INSN_MOVFGQ, "movfgq", "movfgq", 32,
3560 { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_4 } }
3562 /* cmovgf$pack $GRj,$FRintk,$CCi,$cond */
3564 FRV_INSN_CMOVGF, "cmovgf", "cmovgf", 32,
3565 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3567 /* cmovfg$pack $FRintk,$GRj,$CCi,$cond */
3569 FRV_INSN_CMOVFG, "cmovfg", "cmovfg", 32,
3570 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3572 /* cmovgfd$pack $GRj,$FRintk,$CCi,$cond */
3574 FRV_INSN_CMOVGFD, "cmovgfd", "cmovgfd", 32,
3575 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3577 /* cmovfgd$pack $FRintk,$GRj,$CCi,$cond */
3579 FRV_INSN_CMOVFGD, "cmovfgd", "cmovfgd", 32,
3580 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
3582 /* movgs$pack $GRj,$spr */
3584 FRV_INSN_MOVGS, "movgs", "movgs", 32,
3585 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
3587 /* movsg$pack $spr,$GRj */
3589 FRV_INSN_MOVSG, "movsg", "movsg", 32,
3590 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
3592 /* bra$pack $hint_taken$label16 */
3594 FRV_INSN_BRA, "bra", "bra", 32,
3595 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3597 /* bno$pack$hint_not_taken */
3599 FRV_INSN_BNO, "bno", "bno", 32,
3600 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3602 /* beq$pack $ICCi_2,$hint,$label16 */
3604 FRV_INSN_BEQ, "beq", "beq", 32,
3605 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3607 /* bne$pack $ICCi_2,$hint,$label16 */
3609 FRV_INSN_BNE, "bne", "bne", 32,
3610 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3612 /* ble$pack $ICCi_2,$hint,$label16 */
3614 FRV_INSN_BLE, "ble", "ble", 32,
3615 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3617 /* bgt$pack $ICCi_2,$hint,$label16 */
3619 FRV_INSN_BGT, "bgt", "bgt", 32,
3620 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3622 /* blt$pack $ICCi_2,$hint,$label16 */
3624 FRV_INSN_BLT, "blt", "blt", 32,
3625 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3627 /* bge$pack $ICCi_2,$hint,$label16 */
3629 FRV_INSN_BGE, "bge", "bge", 32,
3630 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3632 /* bls$pack $ICCi_2,$hint,$label16 */
3634 FRV_INSN_BLS, "bls", "bls", 32,
3635 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3637 /* bhi$pack $ICCi_2,$hint,$label16 */
3639 FRV_INSN_BHI, "bhi", "bhi", 32,
3640 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3642 /* bc$pack $ICCi_2,$hint,$label16 */
3644 FRV_INSN_BC, "bc", "bc", 32,
3645 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3647 /* bnc$pack $ICCi_2,$hint,$label16 */
3649 FRV_INSN_BNC, "bnc", "bnc", 32,
3650 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3652 /* bn$pack $ICCi_2,$hint,$label16 */
3654 FRV_INSN_BN, "bn", "bn", 32,
3655 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3657 /* bp$pack $ICCi_2,$hint,$label16 */
3659 FRV_INSN_BP, "bp", "bp", 32,
3660 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3662 /* bv$pack $ICCi_2,$hint,$label16 */
3664 FRV_INSN_BV, "bv", "bv", 32,
3665 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3667 /* bnv$pack $ICCi_2,$hint,$label16 */
3669 FRV_INSN_BNV, "bnv", "bnv", 32,
3670 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3672 /* fbra$pack $hint_taken$label16 */
3674 FRV_INSN_FBRA, "fbra", "fbra", 32,
3675 { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3677 /* fbno$pack$hint_not_taken */
3679 FRV_INSN_FBNO, "fbno", "fbno", 32,
3680 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3682 /* fbne$pack $FCCi_2,$hint,$label16 */
3684 FRV_INSN_FBNE, "fbne", "fbne", 32,
3685 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3687 /* fbeq$pack $FCCi_2,$hint,$label16 */
3689 FRV_INSN_FBEQ, "fbeq", "fbeq", 32,
3690 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3692 /* fblg$pack $FCCi_2,$hint,$label16 */
3694 FRV_INSN_FBLG, "fblg", "fblg", 32,
3695 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3697 /* fbue$pack $FCCi_2,$hint,$label16 */
3699 FRV_INSN_FBUE, "fbue", "fbue", 32,
3700 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3702 /* fbul$pack $FCCi_2,$hint,$label16 */
3704 FRV_INSN_FBUL, "fbul", "fbul", 32,
3705 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3707 /* fbge$pack $FCCi_2,$hint,$label16 */
3709 FRV_INSN_FBGE, "fbge", "fbge", 32,
3710 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3712 /* fblt$pack $FCCi_2,$hint,$label16 */
3714 FRV_INSN_FBLT, "fblt", "fblt", 32,
3715 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3717 /* fbuge$pack $FCCi_2,$hint,$label16 */
3719 FRV_INSN_FBUGE, "fbuge", "fbuge", 32,
3720 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3722 /* fbug$pack $FCCi_2,$hint,$label16 */
3724 FRV_INSN_FBUG, "fbug", "fbug", 32,
3725 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3727 /* fble$pack $FCCi_2,$hint,$label16 */
3729 FRV_INSN_FBLE, "fble", "fble", 32,
3730 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3732 /* fbgt$pack $FCCi_2,$hint,$label16 */
3734 FRV_INSN_FBGT, "fbgt", "fbgt", 32,
3735 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3737 /* fbule$pack $FCCi_2,$hint,$label16 */
3739 FRV_INSN_FBULE, "fbule", "fbule", 32,
3740 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3742 /* fbu$pack $FCCi_2,$hint,$label16 */
3744 FRV_INSN_FBU, "fbu", "fbu", 32,
3745 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3747 /* fbo$pack $FCCi_2,$hint,$label16 */
3749 FRV_INSN_FBO, "fbo", "fbo", 32,
3750 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
3752 /* bctrlr$pack $ccond,$hint */
3754 FRV_INSN_BCTRLR, "bctrlr", "bctrlr", 32,
3755 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3757 /* bralr$pack$hint_taken */
3759 FRV_INSN_BRALR, "bralr", "bralr", 32,
3760 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3762 /* bnolr$pack$hint_not_taken */
3764 FRV_INSN_BNOLR, "bnolr", "bnolr", 32,
3765 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3767 /* beqlr$pack $ICCi_2,$hint */
3769 FRV_INSN_BEQLR, "beqlr", "beqlr", 32,
3770 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3772 /* bnelr$pack $ICCi_2,$hint */
3774 FRV_INSN_BNELR, "bnelr", "bnelr", 32,
3775 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3777 /* blelr$pack $ICCi_2,$hint */
3779 FRV_INSN_BLELR, "blelr", "blelr", 32,
3780 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3782 /* bgtlr$pack $ICCi_2,$hint */
3784 FRV_INSN_BGTLR, "bgtlr", "bgtlr", 32,
3785 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3787 /* bltlr$pack $ICCi_2,$hint */
3789 FRV_INSN_BLTLR, "bltlr", "bltlr", 32,
3790 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3792 /* bgelr$pack $ICCi_2,$hint */
3794 FRV_INSN_BGELR, "bgelr", "bgelr", 32,
3795 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3797 /* blslr$pack $ICCi_2,$hint */
3799 FRV_INSN_BLSLR, "blslr", "blslr", 32,
3800 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3802 /* bhilr$pack $ICCi_2,$hint */
3804 FRV_INSN_BHILR, "bhilr", "bhilr", 32,
3805 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3807 /* bclr$pack $ICCi_2,$hint */
3809 FRV_INSN_BCLR, "bclr", "bclr", 32,
3810 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3812 /* bnclr$pack $ICCi_2,$hint */
3814 FRV_INSN_BNCLR, "bnclr", "bnclr", 32,
3815 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3817 /* bnlr$pack $ICCi_2,$hint */
3819 FRV_INSN_BNLR, "bnlr", "bnlr", 32,
3820 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3822 /* bplr$pack $ICCi_2,$hint */
3824 FRV_INSN_BPLR, "bplr", "bplr", 32,
3825 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3827 /* bvlr$pack $ICCi_2,$hint */
3829 FRV_INSN_BVLR, "bvlr", "bvlr", 32,
3830 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3832 /* bnvlr$pack $ICCi_2,$hint */
3834 FRV_INSN_BNVLR, "bnvlr", "bnvlr", 32,
3835 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3837 /* fbralr$pack$hint_taken */
3839 FRV_INSN_FBRALR, "fbralr", "fbralr", 32,
3840 { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3842 /* fbnolr$pack$hint_not_taken */
3844 FRV_INSN_FBNOLR, "fbnolr", "fbnolr", 32,
3845 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3847 /* fbeqlr$pack $FCCi_2,$hint */
3849 FRV_INSN_FBEQLR, "fbeqlr", "fbeqlr", 32,
3850 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3852 /* fbnelr$pack $FCCi_2,$hint */
3854 FRV_INSN_FBNELR, "fbnelr", "fbnelr", 32,
3855 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3857 /* fblglr$pack $FCCi_2,$hint */
3859 FRV_INSN_FBLGLR, "fblglr", "fblglr", 32,
3860 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3862 /* fbuelr$pack $FCCi_2,$hint */
3864 FRV_INSN_FBUELR, "fbuelr", "fbuelr", 32,
3865 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3867 /* fbullr$pack $FCCi_2,$hint */
3869 FRV_INSN_FBULLR, "fbullr", "fbullr", 32,
3870 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3872 /* fbgelr$pack $FCCi_2,$hint */
3874 FRV_INSN_FBGELR, "fbgelr", "fbgelr", 32,
3875 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3877 /* fbltlr$pack $FCCi_2,$hint */
3879 FRV_INSN_FBLTLR, "fbltlr", "fbltlr", 32,
3880 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3882 /* fbugelr$pack $FCCi_2,$hint */
3884 FRV_INSN_FBUGELR, "fbugelr", "fbugelr", 32,
3885 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3887 /* fbuglr$pack $FCCi_2,$hint */
3889 FRV_INSN_FBUGLR, "fbuglr", "fbuglr", 32,
3890 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3892 /* fblelr$pack $FCCi_2,$hint */
3894 FRV_INSN_FBLELR, "fblelr", "fblelr", 32,
3895 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3897 /* fbgtlr$pack $FCCi_2,$hint */
3899 FRV_INSN_FBGTLR, "fbgtlr", "fbgtlr", 32,
3900 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3902 /* fbulelr$pack $FCCi_2,$hint */
3904 FRV_INSN_FBULELR, "fbulelr", "fbulelr", 32,
3905 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3907 /* fbulr$pack $FCCi_2,$hint */
3909 FRV_INSN_FBULR, "fbulr", "fbulr", 32,
3910 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3912 /* fbolr$pack $FCCi_2,$hint */
3914 FRV_INSN_FBOLR, "fbolr", "fbolr", 32,
3915 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
3917 /* bcralr$pack $ccond$hint_taken */
3919 FRV_INSN_BCRALR, "bcralr", "bcralr", 32,
3920 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3922 /* bcnolr$pack$hint_not_taken */
3924 FRV_INSN_BCNOLR, "bcnolr", "bcnolr", 32,
3925 { 0, { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3927 /* bceqlr$pack $ICCi_2,$ccond,$hint */
3929 FRV_INSN_BCEQLR, "bceqlr", "bceqlr", 32,
3930 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3932 /* bcnelr$pack $ICCi_2,$ccond,$hint */
3934 FRV_INSN_BCNELR, "bcnelr", "bcnelr", 32,
3935 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3937 /* bclelr$pack $ICCi_2,$ccond,$hint */
3939 FRV_INSN_BCLELR, "bclelr", "bclelr", 32,
3940 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3942 /* bcgtlr$pack $ICCi_2,$ccond,$hint */
3944 FRV_INSN_BCGTLR, "bcgtlr", "bcgtlr", 32,
3945 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3947 /* bcltlr$pack $ICCi_2,$ccond,$hint */
3949 FRV_INSN_BCLTLR, "bcltlr", "bcltlr", 32,
3950 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3952 /* bcgelr$pack $ICCi_2,$ccond,$hint */
3954 FRV_INSN_BCGELR, "bcgelr", "bcgelr", 32,
3955 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3957 /* bclslr$pack $ICCi_2,$ccond,$hint */
3959 FRV_INSN_BCLSLR, "bclslr", "bclslr", 32,
3960 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3962 /* bchilr$pack $ICCi_2,$ccond,$hint */
3964 FRV_INSN_BCHILR, "bchilr", "bchilr", 32,
3965 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3967 /* bcclr$pack $ICCi_2,$ccond,$hint */
3969 FRV_INSN_BCCLR, "bcclr", "bcclr", 32,
3970 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3972 /* bcnclr$pack $ICCi_2,$ccond,$hint */
3974 FRV_INSN_BCNCLR, "bcnclr", "bcnclr", 32,
3975 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3977 /* bcnlr$pack $ICCi_2,$ccond,$hint */
3979 FRV_INSN_BCNLR, "bcnlr", "bcnlr", 32,
3980 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3982 /* bcplr$pack $ICCi_2,$ccond,$hint */
3984 FRV_INSN_BCPLR, "bcplr", "bcplr", 32,
3985 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3987 /* bcvlr$pack $ICCi_2,$ccond,$hint */
3989 FRV_INSN_BCVLR, "bcvlr", "bcvlr", 32,
3990 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3992 /* bcnvlr$pack $ICCi_2,$ccond,$hint */
3994 FRV_INSN_BCNVLR, "bcnvlr", "bcnvlr", 32,
3995 { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
3997 /* fcbralr$pack $ccond$hint_taken */
3999 FRV_INSN_FCBRALR, "fcbralr", "fcbralr", 32,
4000 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4002 /* fcbnolr$pack$hint_not_taken */
4004 FRV_INSN_FCBNOLR, "fcbnolr", "fcbnolr", 32,
4005 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4007 /* fcbeqlr$pack $FCCi_2,$ccond,$hint */
4009 FRV_INSN_FCBEQLR, "fcbeqlr", "fcbeqlr", 32,
4010 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4012 /* fcbnelr$pack $FCCi_2,$ccond,$hint */
4014 FRV_INSN_FCBNELR, "fcbnelr", "fcbnelr", 32,
4015 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4017 /* fcblglr$pack $FCCi_2,$ccond,$hint */
4019 FRV_INSN_FCBLGLR, "fcblglr", "fcblglr", 32,
4020 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4022 /* fcbuelr$pack $FCCi_2,$ccond,$hint */
4024 FRV_INSN_FCBUELR, "fcbuelr", "fcbuelr", 32,
4025 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4027 /* fcbullr$pack $FCCi_2,$ccond,$hint */
4029 FRV_INSN_FCBULLR, "fcbullr", "fcbullr", 32,
4030 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4032 /* fcbgelr$pack $FCCi_2,$ccond,$hint */
4034 FRV_INSN_FCBGELR, "fcbgelr", "fcbgelr", 32,
4035 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4037 /* fcbltlr$pack $FCCi_2,$ccond,$hint */
4039 FRV_INSN_FCBLTLR, "fcbltlr", "fcbltlr", 32,
4040 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4042 /* fcbugelr$pack $FCCi_2,$ccond,$hint */
4044 FRV_INSN_FCBUGELR, "fcbugelr", "fcbugelr", 32,
4045 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4047 /* fcbuglr$pack $FCCi_2,$ccond,$hint */
4049 FRV_INSN_FCBUGLR, "fcbuglr", "fcbuglr", 32,
4050 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4052 /* fcblelr$pack $FCCi_2,$ccond,$hint */
4054 FRV_INSN_FCBLELR, "fcblelr", "fcblelr", 32,
4055 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4057 /* fcbgtlr$pack $FCCi_2,$ccond,$hint */
4059 FRV_INSN_FCBGTLR, "fcbgtlr", "fcbgtlr", 32,
4060 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4062 /* fcbulelr$pack $FCCi_2,$ccond,$hint */
4064 FRV_INSN_FCBULELR, "fcbulelr", "fcbulelr", 32,
4065 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4067 /* fcbulr$pack $FCCi_2,$ccond,$hint */
4069 FRV_INSN_FCBULR, "fcbulr", "fcbulr", 32,
4070 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4072 /* fcbolr$pack $FCCi_2,$ccond,$hint */
4074 FRV_INSN_FCBOLR, "fcbolr", "fcbolr", 32,
4075 { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
4077 /* jmpl$pack @($GRi,$GRj) */
4079 FRV_INSN_JMPL, "jmpl", "jmpl", 32,
4080 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
4082 /* calll$pack @($GRi,$GRj) */
4084 FRV_INSN_CALLL, "calll", "calll", 32,
4085 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
4087 /* jmpil$pack @($GRi,$s12) */
4089 FRV_INSN_JMPIL, "jmpil", "jmpil", 32,
4090 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
4092 /* callil$pack @($GRi,$s12) */
4094 FRV_INSN_CALLIL, "callil", "callil", 32,
4095 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
4097 /* call$pack $label24 */
4099 FRV_INSN_CALL, "call", "call", 32,
4100 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_4, FR500_MAJOR_B_4 } }
4102 /* rett$pack $debug */
4104 FRV_INSN_RETT, "rett", "rett", 32,
4105 { 0|A(PRIVILEGED)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4109 FRV_INSN_REI, "rei", "rei", 32,
4110 { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_1 } }
4112 /* tra$pack $GRi,$GRj */
4114 FRV_INSN_TRA, "tra", "tra", 32,
4115 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4119 FRV_INSN_TNO, "tno", "tno", 32,
4120 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4122 /* teq$pack $ICCi_2,$GRi,$GRj */
4124 FRV_INSN_TEQ, "teq", "teq", 32,
4125 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4127 /* tne$pack $ICCi_2,$GRi,$GRj */
4129 FRV_INSN_TNE, "tne", "tne", 32,
4130 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4132 /* tle$pack $ICCi_2,$GRi,$GRj */
4134 FRV_INSN_TLE, "tle", "tle", 32,
4135 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4137 /* tgt$pack $ICCi_2,$GRi,$GRj */
4139 FRV_INSN_TGT, "tgt", "tgt", 32,
4140 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4142 /* tlt$pack $ICCi_2,$GRi,$GRj */
4144 FRV_INSN_TLT, "tlt", "tlt", 32,
4145 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4147 /* tge$pack $ICCi_2,$GRi,$GRj */
4149 FRV_INSN_TGE, "tge", "tge", 32,
4150 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4152 /* tls$pack $ICCi_2,$GRi,$GRj */
4154 FRV_INSN_TLS, "tls", "tls", 32,
4155 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4157 /* thi$pack $ICCi_2,$GRi,$GRj */
4159 FRV_INSN_THI, "thi", "thi", 32,
4160 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4162 /* tc$pack $ICCi_2,$GRi,$GRj */
4164 FRV_INSN_TC, "tc", "tc", 32,
4165 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4167 /* tnc$pack $ICCi_2,$GRi,$GRj */
4169 FRV_INSN_TNC, "tnc", "tnc", 32,
4170 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4172 /* tn$pack $ICCi_2,$GRi,$GRj */
4174 FRV_INSN_TN, "tn", "tn", 32,
4175 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4177 /* tp$pack $ICCi_2,$GRi,$GRj */
4179 FRV_INSN_TP, "tp", "tp", 32,
4180 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4182 /* tv$pack $ICCi_2,$GRi,$GRj */
4184 FRV_INSN_TV, "tv", "tv", 32,
4185 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4187 /* tnv$pack $ICCi_2,$GRi,$GRj */
4189 FRV_INSN_TNV, "tnv", "tnv", 32,
4190 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4192 /* ftra$pack $GRi,$GRj */
4194 FRV_INSN_FTRA, "ftra", "ftra", 32,
4195 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4199 FRV_INSN_FTNO, "ftno", "ftno", 32,
4200 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4202 /* ftne$pack $FCCi_2,$GRi,$GRj */
4204 FRV_INSN_FTNE, "ftne", "ftne", 32,
4205 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4207 /* fteq$pack $FCCi_2,$GRi,$GRj */
4209 FRV_INSN_FTEQ, "fteq", "fteq", 32,
4210 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4212 /* ftlg$pack $FCCi_2,$GRi,$GRj */
4214 FRV_INSN_FTLG, "ftlg", "ftlg", 32,
4215 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4217 /* ftue$pack $FCCi_2,$GRi,$GRj */
4219 FRV_INSN_FTUE, "ftue", "ftue", 32,
4220 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4222 /* ftul$pack $FCCi_2,$GRi,$GRj */
4224 FRV_INSN_FTUL, "ftul", "ftul", 32,
4225 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4227 /* ftge$pack $FCCi_2,$GRi,$GRj */
4229 FRV_INSN_FTGE, "ftge", "ftge", 32,
4230 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4232 /* ftlt$pack $FCCi_2,$GRi,$GRj */
4234 FRV_INSN_FTLT, "ftlt", "ftlt", 32,
4235 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4237 /* ftuge$pack $FCCi_2,$GRi,$GRj */
4239 FRV_INSN_FTUGE, "ftuge", "ftuge", 32,
4240 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4242 /* ftug$pack $FCCi_2,$GRi,$GRj */
4244 FRV_INSN_FTUG, "ftug", "ftug", 32,
4245 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4247 /* ftle$pack $FCCi_2,$GRi,$GRj */
4249 FRV_INSN_FTLE, "ftle", "ftle", 32,
4250 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4252 /* ftgt$pack $FCCi_2,$GRi,$GRj */
4254 FRV_INSN_FTGT, "ftgt", "ftgt", 32,
4255 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4257 /* ftule$pack $FCCi_2,$GRi,$GRj */
4259 FRV_INSN_FTULE, "ftule", "ftule", 32,
4260 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4262 /* ftu$pack $FCCi_2,$GRi,$GRj */
4264 FRV_INSN_FTU, "ftu", "ftu", 32,
4265 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4267 /* fto$pack $FCCi_2,$GRi,$GRj */
4269 FRV_INSN_FTO, "fto", "fto", 32,
4270 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4272 /* tira$pack $GRi,$s12 */
4274 FRV_INSN_TIRA, "tira", "tira", 32,
4275 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4279 FRV_INSN_TINO, "tino", "tino", 32,
4280 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4282 /* tieq$pack $ICCi_2,$GRi,$s12 */
4284 FRV_INSN_TIEQ, "tieq", "tieq", 32,
4285 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4287 /* tine$pack $ICCi_2,$GRi,$s12 */
4289 FRV_INSN_TINE, "tine", "tine", 32,
4290 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4292 /* tile$pack $ICCi_2,$GRi,$s12 */
4294 FRV_INSN_TILE, "tile", "tile", 32,
4295 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4297 /* tigt$pack $ICCi_2,$GRi,$s12 */
4299 FRV_INSN_TIGT, "tigt", "tigt", 32,
4300 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4302 /* tilt$pack $ICCi_2,$GRi,$s12 */
4304 FRV_INSN_TILT, "tilt", "tilt", 32,
4305 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4307 /* tige$pack $ICCi_2,$GRi,$s12 */
4309 FRV_INSN_TIGE, "tige", "tige", 32,
4310 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4312 /* tils$pack $ICCi_2,$GRi,$s12 */
4314 FRV_INSN_TILS, "tils", "tils", 32,
4315 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4317 /* tihi$pack $ICCi_2,$GRi,$s12 */
4319 FRV_INSN_TIHI, "tihi", "tihi", 32,
4320 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4322 /* tic$pack $ICCi_2,$GRi,$s12 */
4324 FRV_INSN_TIC, "tic", "tic", 32,
4325 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4327 /* tinc$pack $ICCi_2,$GRi,$s12 */
4329 FRV_INSN_TINC, "tinc", "tinc", 32,
4330 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4332 /* tin$pack $ICCi_2,$GRi,$s12 */
4334 FRV_INSN_TIN, "tin", "tin", 32,
4335 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4337 /* tip$pack $ICCi_2,$GRi,$s12 */
4339 FRV_INSN_TIP, "tip", "tip", 32,
4340 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4342 /* tiv$pack $ICCi_2,$GRi,$s12 */
4344 FRV_INSN_TIV, "tiv", "tiv", 32,
4345 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4347 /* tinv$pack $ICCi_2,$GRi,$s12 */
4349 FRV_INSN_TINV, "tinv", "tinv", 32,
4350 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4352 /* ftira$pack $GRi,$s12 */
4354 FRV_INSN_FTIRA, "ftira", "ftira", 32,
4355 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4359 FRV_INSN_FTINO, "ftino", "ftino", 32,
4360 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4362 /* ftine$pack $FCCi_2,$GRi,$s12 */
4364 FRV_INSN_FTINE, "ftine", "ftine", 32,
4365 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4367 /* ftieq$pack $FCCi_2,$GRi,$s12 */
4369 FRV_INSN_FTIEQ, "ftieq", "ftieq", 32,
4370 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4372 /* ftilg$pack $FCCi_2,$GRi,$s12 */
4374 FRV_INSN_FTILG, "ftilg", "ftilg", 32,
4375 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4377 /* ftiue$pack $FCCi_2,$GRi,$s12 */
4379 FRV_INSN_FTIUE, "ftiue", "ftiue", 32,
4380 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4382 /* ftiul$pack $FCCi_2,$GRi,$s12 */
4384 FRV_INSN_FTIUL, "ftiul", "ftiul", 32,
4385 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4387 /* ftige$pack $FCCi_2,$GRi,$s12 */
4389 FRV_INSN_FTIGE, "ftige", "ftige", 32,
4390 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4392 /* ftilt$pack $FCCi_2,$GRi,$s12 */
4394 FRV_INSN_FTILT, "ftilt", "ftilt", 32,
4395 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4397 /* ftiuge$pack $FCCi_2,$GRi,$s12 */
4399 FRV_INSN_FTIUGE, "ftiuge", "ftiuge", 32,
4400 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4402 /* ftiug$pack $FCCi_2,$GRi,$s12 */
4404 FRV_INSN_FTIUG, "ftiug", "ftiug", 32,
4405 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4407 /* ftile$pack $FCCi_2,$GRi,$s12 */
4409 FRV_INSN_FTILE, "ftile", "ftile", 32,
4410 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4412 /* ftigt$pack $FCCi_2,$GRi,$s12 */
4414 FRV_INSN_FTIGT, "ftigt", "ftigt", 32,
4415 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4417 /* ftiule$pack $FCCi_2,$GRi,$s12 */
4419 FRV_INSN_FTIULE, "ftiule", "ftiule", 32,
4420 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4422 /* ftiu$pack $FCCi_2,$GRi,$s12 */
4424 FRV_INSN_FTIU, "ftiu", "ftiu", 32,
4425 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4427 /* ftio$pack $FCCi_2,$GRi,$s12 */
4429 FRV_INSN_FTIO, "ftio", "ftio", 32,
4430 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4434 FRV_INSN_BREAK, "break", "break", 32,
4435 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4439 FRV_INSN_MTRAP, "mtrap", "mtrap", 32,
4440 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
4442 /* andcr$pack $CRi,$CRj,$CRk */
4444 FRV_INSN_ANDCR, "andcr", "andcr", 32,
4445 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4447 /* orcr$pack $CRi,$CRj,$CRk */
4449 FRV_INSN_ORCR, "orcr", "orcr", 32,
4450 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4452 /* xorcr$pack $CRi,$CRj,$CRk */
4454 FRV_INSN_XORCR, "xorcr", "xorcr", 32,
4455 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4457 /* nandcr$pack $CRi,$CRj,$CRk */
4459 FRV_INSN_NANDCR, "nandcr", "nandcr", 32,
4460 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4462 /* norcr$pack $CRi,$CRj,$CRk */
4464 FRV_INSN_NORCR, "norcr", "norcr", 32,
4465 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4467 /* andncr$pack $CRi,$CRj,$CRk */
4469 FRV_INSN_ANDNCR, "andncr", "andncr", 32,
4470 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4472 /* orncr$pack $CRi,$CRj,$CRk */
4474 FRV_INSN_ORNCR, "orncr", "orncr", 32,
4475 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4477 /* nandncr$pack $CRi,$CRj,$CRk */
4479 FRV_INSN_NANDNCR, "nandncr", "nandncr", 32,
4480 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4482 /* norncr$pack $CRi,$CRj,$CRk */
4484 FRV_INSN_NORNCR, "norncr", "norncr", 32,
4485 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4487 /* notcr$pack $CRj,$CRk */
4489 FRV_INSN_NOTCR, "notcr", "notcr", 32,
4490 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
4492 /* ckra$pack $CRj_int */
4494 FRV_INSN_CKRA, "ckra", "ckra", 32,
4495 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4497 /* ckno$pack $CRj_int */
4499 FRV_INSN_CKNO, "ckno", "ckno", 32,
4500 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4502 /* ckeq$pack $ICCi_3,$CRj_int */
4504 FRV_INSN_CKEQ, "ckeq", "ckeq", 32,
4505 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4507 /* ckne$pack $ICCi_3,$CRj_int */
4509 FRV_INSN_CKNE, "ckne", "ckne", 32,
4510 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4512 /* ckle$pack $ICCi_3,$CRj_int */
4514 FRV_INSN_CKLE, "ckle", "ckle", 32,
4515 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4517 /* ckgt$pack $ICCi_3,$CRj_int */
4519 FRV_INSN_CKGT, "ckgt", "ckgt", 32,
4520 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4522 /* cklt$pack $ICCi_3,$CRj_int */
4524 FRV_INSN_CKLT, "cklt", "cklt", 32,
4525 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4527 /* ckge$pack $ICCi_3,$CRj_int */
4529 FRV_INSN_CKGE, "ckge", "ckge", 32,
4530 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4532 /* ckls$pack $ICCi_3,$CRj_int */
4534 FRV_INSN_CKLS, "ckls", "ckls", 32,
4535 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4537 /* ckhi$pack $ICCi_3,$CRj_int */
4539 FRV_INSN_CKHI, "ckhi", "ckhi", 32,
4540 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4542 /* ckc$pack $ICCi_3,$CRj_int */
4544 FRV_INSN_CKC, "ckc", "ckc", 32,
4545 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4547 /* cknc$pack $ICCi_3,$CRj_int */
4549 FRV_INSN_CKNC, "cknc", "cknc", 32,
4550 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4552 /* ckn$pack $ICCi_3,$CRj_int */
4554 FRV_INSN_CKN, "ckn", "ckn", 32,
4555 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4557 /* ckp$pack $ICCi_3,$CRj_int */
4559 FRV_INSN_CKP, "ckp", "ckp", 32,
4560 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4562 /* ckv$pack $ICCi_3,$CRj_int */
4564 FRV_INSN_CKV, "ckv", "ckv", 32,
4565 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4567 /* cknv$pack $ICCi_3,$CRj_int */
4569 FRV_INSN_CKNV, "cknv", "cknv", 32,
4570 { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4572 /* fckra$pack $CRj_float */
4574 FRV_INSN_FCKRA, "fckra", "fckra", 32,
4575 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4577 /* fckno$pack $CRj_float */
4579 FRV_INSN_FCKNO, "fckno", "fckno", 32,
4580 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4582 /* fckne$pack $FCCi_3,$CRj_float */
4584 FRV_INSN_FCKNE, "fckne", "fckne", 32,
4585 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4587 /* fckeq$pack $FCCi_3,$CRj_float */
4589 FRV_INSN_FCKEQ, "fckeq", "fckeq", 32,
4590 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4592 /* fcklg$pack $FCCi_3,$CRj_float */
4594 FRV_INSN_FCKLG, "fcklg", "fcklg", 32,
4595 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4597 /* fckue$pack $FCCi_3,$CRj_float */
4599 FRV_INSN_FCKUE, "fckue", "fckue", 32,
4600 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4602 /* fckul$pack $FCCi_3,$CRj_float */
4604 FRV_INSN_FCKUL, "fckul", "fckul", 32,
4605 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4607 /* fckge$pack $FCCi_3,$CRj_float */
4609 FRV_INSN_FCKGE, "fckge", "fckge", 32,
4610 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4612 /* fcklt$pack $FCCi_3,$CRj_float */
4614 FRV_INSN_FCKLT, "fcklt", "fcklt", 32,
4615 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4617 /* fckuge$pack $FCCi_3,$CRj_float */
4619 FRV_INSN_FCKUGE, "fckuge", "fckuge", 32,
4620 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4622 /* fckug$pack $FCCi_3,$CRj_float */
4624 FRV_INSN_FCKUG, "fckug", "fckug", 32,
4625 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4627 /* fckle$pack $FCCi_3,$CRj_float */
4629 FRV_INSN_FCKLE, "fckle", "fckle", 32,
4630 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4632 /* fckgt$pack $FCCi_3,$CRj_float */
4634 FRV_INSN_FCKGT, "fckgt", "fckgt", 32,
4635 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4637 /* fckule$pack $FCCi_3,$CRj_float */
4639 FRV_INSN_FCKULE, "fckule", "fckule", 32,
4640 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4642 /* fcku$pack $FCCi_3,$CRj_float */
4644 FRV_INSN_FCKU, "fcku", "fcku", 32,
4645 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4647 /* fcko$pack $FCCi_3,$CRj_float */
4649 FRV_INSN_FCKO, "fcko", "fcko", 32,
4650 { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4652 /* cckra$pack $CRj_int,$CCi,$cond */
4654 FRV_INSN_CCKRA, "cckra", "cckra", 32,
4655 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4657 /* cckno$pack $CRj_int,$CCi,$cond */
4659 FRV_INSN_CCKNO, "cckno", "cckno", 32,
4660 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4662 /* cckeq$pack $ICCi_3,$CRj_int,$CCi,$cond */
4664 FRV_INSN_CCKEQ, "cckeq", "cckeq", 32,
4665 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4667 /* cckne$pack $ICCi_3,$CRj_int,$CCi,$cond */
4669 FRV_INSN_CCKNE, "cckne", "cckne", 32,
4670 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4672 /* cckle$pack $ICCi_3,$CRj_int,$CCi,$cond */
4674 FRV_INSN_CCKLE, "cckle", "cckle", 32,
4675 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4677 /* cckgt$pack $ICCi_3,$CRj_int,$CCi,$cond */
4679 FRV_INSN_CCKGT, "cckgt", "cckgt", 32,
4680 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4682 /* ccklt$pack $ICCi_3,$CRj_int,$CCi,$cond */
4684 FRV_INSN_CCKLT, "ccklt", "ccklt", 32,
4685 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4687 /* cckge$pack $ICCi_3,$CRj_int,$CCi,$cond */
4689 FRV_INSN_CCKGE, "cckge", "cckge", 32,
4690 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4692 /* cckls$pack $ICCi_3,$CRj_int,$CCi,$cond */
4694 FRV_INSN_CCKLS, "cckls", "cckls", 32,
4695 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4697 /* cckhi$pack $ICCi_3,$CRj_int,$CCi,$cond */
4699 FRV_INSN_CCKHI, "cckhi", "cckhi", 32,
4700 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4702 /* cckc$pack $ICCi_3,$CRj_int,$CCi,$cond */
4704 FRV_INSN_CCKC, "cckc", "cckc", 32,
4705 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4707 /* ccknc$pack $ICCi_3,$CRj_int,$CCi,$cond */
4709 FRV_INSN_CCKNC, "ccknc", "ccknc", 32,
4710 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4712 /* cckn$pack $ICCi_3,$CRj_int,$CCi,$cond */
4714 FRV_INSN_CCKN, "cckn", "cckn", 32,
4715 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4717 /* cckp$pack $ICCi_3,$CRj_int,$CCi,$cond */
4719 FRV_INSN_CCKP, "cckp", "cckp", 32,
4720 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4722 /* cckv$pack $ICCi_3,$CRj_int,$CCi,$cond */
4724 FRV_INSN_CCKV, "cckv", "cckv", 32,
4725 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4727 /* ccknv$pack $ICCi_3,$CRj_int,$CCi,$cond */
4729 FRV_INSN_CCKNV, "ccknv", "ccknv", 32,
4730 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4732 /* cfckra$pack $CRj_float,$CCi,$cond */
4734 FRV_INSN_CFCKRA, "cfckra", "cfckra", 32,
4735 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4737 /* cfckno$pack $CRj_float,$CCi,$cond */
4739 FRV_INSN_CFCKNO, "cfckno", "cfckno", 32,
4740 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4742 /* cfckne$pack $FCCi_3,$CRj_float,$CCi,$cond */
4744 FRV_INSN_CFCKNE, "cfckne", "cfckne", 32,
4745 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4747 /* cfckeq$pack $FCCi_3,$CRj_float,$CCi,$cond */
4749 FRV_INSN_CFCKEQ, "cfckeq", "cfckeq", 32,
4750 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4752 /* cfcklg$pack $FCCi_3,$CRj_float,$CCi,$cond */
4754 FRV_INSN_CFCKLG, "cfcklg", "cfcklg", 32,
4755 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4757 /* cfckue$pack $FCCi_3,$CRj_float,$CCi,$cond */
4759 FRV_INSN_CFCKUE, "cfckue", "cfckue", 32,
4760 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4762 /* cfckul$pack $FCCi_3,$CRj_float,$CCi,$cond */
4764 FRV_INSN_CFCKUL, "cfckul", "cfckul", 32,
4765 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4767 /* cfckge$pack $FCCi_3,$CRj_float,$CCi,$cond */
4769 FRV_INSN_CFCKGE, "cfckge", "cfckge", 32,
4770 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4772 /* cfcklt$pack $FCCi_3,$CRj_float,$CCi,$cond */
4774 FRV_INSN_CFCKLT, "cfcklt", "cfcklt", 32,
4775 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4777 /* cfckuge$pack $FCCi_3,$CRj_float,$CCi,$cond */
4779 FRV_INSN_CFCKUGE, "cfckuge", "cfckuge", 32,
4780 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4782 /* cfckug$pack $FCCi_3,$CRj_float,$CCi,$cond */
4784 FRV_INSN_CFCKUG, "cfckug", "cfckug", 32,
4785 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4787 /* cfckle$pack $FCCi_3,$CRj_float,$CCi,$cond */
4789 FRV_INSN_CFCKLE, "cfckle", "cfckle", 32,
4790 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4792 /* cfckgt$pack $FCCi_3,$CRj_float,$CCi,$cond */
4794 FRV_INSN_CFCKGT, "cfckgt", "cfckgt", 32,
4795 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4797 /* cfckule$pack $FCCi_3,$CRj_float,$CCi,$cond */
4799 FRV_INSN_CFCKULE, "cfckule", "cfckule", 32,
4800 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4802 /* cfcku$pack $FCCi_3,$CRj_float,$CCi,$cond */
4804 FRV_INSN_CFCKU, "cfcku", "cfcku", 32,
4805 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4807 /* cfcko$pack $FCCi_3,$CRj_float,$CCi,$cond */
4809 FRV_INSN_CFCKO, "cfcko", "cfcko", 32,
4810 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
4812 /* cjmpl$pack @($GRi,$GRj),$CCi,$cond */
4814 FRV_INSN_CJMPL, "cjmpl", "cjmpl", 32,
4815 { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
4817 /* ccalll$pack @($GRi,$GRj),$CCi,$cond */
4819 FRV_INSN_CCALLL, "ccalll", "ccalll", 32,
4820 { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
4822 /* ici$pack @($GRi,$GRj) */
4824 FRV_INSN_ICI, "ici", "ici", 32,
4825 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4827 /* dci$pack @($GRi,$GRj) */
4829 FRV_INSN_DCI, "dci", "dci", 32,
4830 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4832 /* icei$pack @($GRi,$GRj),$ae */
4834 FRV_INSN_ICEI, "icei", "icei", 32,
4835 { 0, { (1<<MACH_FR400), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE } }
4837 /* dcei$pack @($GRi,$GRj),$ae */
4839 FRV_INSN_DCEI, "dcei", "dcei", 32,
4840 { 0, { (1<<MACH_FR400), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE } }
4842 /* dcf$pack @($GRi,$GRj) */
4844 FRV_INSN_DCF, "dcf", "dcf", 32,
4845 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4847 /* dcef$pack @($GRi,$GRj),$ae */
4849 FRV_INSN_DCEF, "dcef", "dcef", 32,
4850 { 0, { (1<<MACH_FR400), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE } }
4852 /* witlb$pack $GRk,@($GRi,$GRj) */
4854 FRV_INSN_WITLB, "witlb", "witlb", 32,
4855 { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
4857 /* wdtlb$pack $GRk,@($GRi,$GRj) */
4859 FRV_INSN_WDTLB, "wdtlb", "wdtlb", 32,
4860 { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
4862 /* itlbi$pack @($GRi,$GRj) */
4864 FRV_INSN_ITLBI, "itlbi", "itlbi", 32,
4865 { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
4867 /* dtlbi$pack @($GRi,$GRj) */
4869 FRV_INSN_DTLBI, "dtlbi", "dtlbi", 32,
4870 { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
4872 /* icpl$pack $GRi,$GRj,$lock */
4874 FRV_INSN_ICPL, "icpl", "icpl", 32,
4875 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4877 /* dcpl$pack $GRi,$GRj,$lock */
4879 FRV_INSN_DCPL, "dcpl", "dcpl", 32,
4880 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4882 /* icul$pack $GRi */
4884 FRV_INSN_ICUL, "icul", "icul", 32,
4885 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4887 /* dcul$pack $GRi */
4889 FRV_INSN_DCUL, "dcul", "dcul", 32,
4890 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4894 FRV_INSN_BAR, "bar", "bar", 32,
4895 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4899 FRV_INSN_MEMBAR, "membar", "membar", 32,
4900 { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
4902 /* cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */
4904 FRV_INSN_COP1, "cop1", "cop1", 32,
4905 { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
4907 /* cop2$pack $s6_1,$CPRi,$CPRj,$CPRk */
4909 FRV_INSN_COP2, "cop2", "cop2", 32,
4910 { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
4912 /* clrgr$pack $GRk */
4914 FRV_INSN_CLRGR, "clrgr", "clrgr", 32,
4915 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4917 /* clrfr$pack $FRk */
4919 FRV_INSN_CLRFR, "clrfr", "clrfr", 32,
4920 { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4924 FRV_INSN_CLRGA, "clrga", "clrga", 32,
4925 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4929 FRV_INSN_CLRFA, "clrfa", "clrfa", 32,
4930 { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4932 /* commitgr$pack $GRk */
4934 FRV_INSN_COMMITGR, "commitgr", "commitgr", 32,
4935 { 0, { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4937 /* commitfr$pack $FRk */
4939 FRV_INSN_COMMITFR, "commitfr", "commitfr", 32,
4940 { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4944 FRV_INSN_COMMITGA, "commitga", "commitga", 32,
4945 { 0, { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4949 FRV_INSN_COMMITFA, "commitfa", "commitfa", 32,
4950 { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
4952 /* fitos$pack $FRintj,$FRk */
4954 FRV_INSN_FITOS, "fitos", "fitos", 32,
4955 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4957 /* fstoi$pack $FRj,$FRintk */
4959 FRV_INSN_FSTOI, "fstoi", "fstoi", 32,
4960 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4962 /* fitod$pack $FRintj,$FRdoublek */
4964 FRV_INSN_FITOD, "fitod", "fitod", 32,
4965 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4967 /* fdtoi$pack $FRdoublej,$FRintk */
4969 FRV_INSN_FDTOI, "fdtoi", "fdtoi", 32,
4970 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4972 /* fditos$pack $FRintj,$FRk */
4974 FRV_INSN_FDITOS, "fditos", "fditos", 32,
4975 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4977 /* fdstoi$pack $FRj,$FRintk */
4979 FRV_INSN_FDSTOI, "fdstoi", "fdstoi", 32,
4980 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4982 /* nfditos$pack $FRintj,$FRk */
4984 FRV_INSN_NFDITOS, "nfditos", "nfditos", 32,
4985 { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4987 /* nfdstoi$pack $FRj,$FRintk */
4989 FRV_INSN_NFDSTOI, "nfdstoi", "nfdstoi", 32,
4990 { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4992 /* cfitos$pack $FRintj,$FRk,$CCi,$cond */
4994 FRV_INSN_CFITOS, "cfitos", "cfitos", 32,
4995 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
4997 /* cfstoi$pack $FRj,$FRintk,$CCi,$cond */
4999 FRV_INSN_CFSTOI, "cfstoi", "cfstoi", 32,
5000 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5002 /* nfitos$pack $FRintj,$FRk */
5004 FRV_INSN_NFITOS, "nfitos", "nfitos", 32,
5005 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5007 /* nfstoi$pack $FRj,$FRintk */
5009 FRV_INSN_NFSTOI, "nfstoi", "nfstoi", 32,
5010 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5012 /* fmovs$pack $FRj,$FRk */
5014 FRV_INSN_FMOVS, "fmovs", "fmovs", 32,
5015 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5017 /* fmovd$pack $FRdoublej,$FRdoublek */
5019 FRV_INSN_FMOVD, "fmovd", "fmovd", 32,
5020 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5022 /* fdmovs$pack $FRj,$FRk */
5024 FRV_INSN_FDMOVS, "fdmovs", "fdmovs", 32,
5025 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5027 /* cfmovs$pack $FRj,$FRk,$CCi,$cond */
5029 FRV_INSN_CFMOVS, "cfmovs", "cfmovs", 32,
5030 { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5032 /* fnegs$pack $FRj,$FRk */
5034 FRV_INSN_FNEGS, "fnegs", "fnegs", 32,
5035 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5037 /* fnegd$pack $FRdoublej,$FRdoublek */
5039 FRV_INSN_FNEGD, "fnegd", "fnegd", 32,
5040 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5042 /* fdnegs$pack $FRj,$FRk */
5044 FRV_INSN_FDNEGS, "fdnegs", "fdnegs", 32,
5045 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5047 /* cfnegs$pack $FRj,$FRk,$CCi,$cond */
5049 FRV_INSN_CFNEGS, "cfnegs", "cfnegs", 32,
5050 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5052 /* fabss$pack $FRj,$FRk */
5054 FRV_INSN_FABSS, "fabss", "fabss", 32,
5055 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5057 /* fabsd$pack $FRdoublej,$FRdoublek */
5059 FRV_INSN_FABSD, "fabsd", "fabsd", 32,
5060 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5062 /* fdabss$pack $FRj,$FRk */
5064 FRV_INSN_FDABSS, "fdabss", "fdabss", 32,
5065 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5067 /* cfabss$pack $FRj,$FRk,$CCi,$cond */
5069 FRV_INSN_CFABSS, "cfabss", "cfabss", 32,
5070 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
5072 /* fsqrts$pack $FRj,$FRk */
5074 FRV_INSN_FSQRTS, "fsqrts", "fsqrts", 32,
5075 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5077 /* fdsqrts$pack $FRj,$FRk */
5079 FRV_INSN_FDSQRTS, "fdsqrts", "fdsqrts", 32,
5080 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5082 /* nfdsqrts$pack $FRj,$FRk */
5084 FRV_INSN_NFDSQRTS, "nfdsqrts", "nfdsqrts", 32,
5085 { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5087 /* fsqrtd$pack $FRdoublej,$FRdoublek */
5089 FRV_INSN_FSQRTD, "fsqrtd", "fsqrtd", 32,
5090 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5092 /* cfsqrts$pack $FRj,$FRk,$CCi,$cond */
5094 FRV_INSN_CFSQRTS, "cfsqrts", "cfsqrts", 32,
5095 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5097 /* nfsqrts$pack $FRj,$FRk */
5099 FRV_INSN_NFSQRTS, "nfsqrts", "nfsqrts", 32,
5100 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5102 /* fadds$pack $FRi,$FRj,$FRk */
5104 FRV_INSN_FADDS, "fadds", "fadds", 32,
5105 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5107 /* fsubs$pack $FRi,$FRj,$FRk */
5109 FRV_INSN_FSUBS, "fsubs", "fsubs", 32,
5110 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5112 /* fmuls$pack $FRi,$FRj,$FRk */
5114 FRV_INSN_FMULS, "fmuls", "fmuls", 32,
5115 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
5117 /* fdivs$pack $FRi,$FRj,$FRk */
5119 FRV_INSN_FDIVS, "fdivs", "fdivs", 32,
5120 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5122 /* faddd$pack $FRdoublei,$FRdoublej,$FRdoublek */
5124 FRV_INSN_FADDD, "faddd", "faddd", 32,
5125 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5127 /* fsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */
5129 FRV_INSN_FSUBD, "fsubd", "fsubd", 32,
5130 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5132 /* fmuld$pack $FRdoublei,$FRdoublej,$FRdoublek */
5134 FRV_INSN_FMULD, "fmuld", "fmuld", 32,
5135 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
5137 /* fdivd$pack $FRdoublei,$FRdoublej,$FRdoublek */
5139 FRV_INSN_FDIVD, "fdivd", "fdivd", 32,
5140 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5142 /* cfadds$pack $FRi,$FRj,$FRk,$CCi,$cond */
5144 FRV_INSN_CFADDS, "cfadds", "cfadds", 32,
5145 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5147 /* cfsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */
5149 FRV_INSN_CFSUBS, "cfsubs", "cfsubs", 32,
5150 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5152 /* cfmuls$pack $FRi,$FRj,$FRk,$CCi,$cond */
5154 FRV_INSN_CFMULS, "cfmuls", "cfmuls", 32,
5155 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
5157 /* cfdivs$pack $FRi,$FRj,$FRk,$CCi,$cond */
5159 FRV_INSN_CFDIVS, "cfdivs", "cfdivs", 32,
5160 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5162 /* nfadds$pack $FRi,$FRj,$FRk */
5164 FRV_INSN_NFADDS, "nfadds", "nfadds", 32,
5165 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5167 /* nfsubs$pack $FRi,$FRj,$FRk */
5169 FRV_INSN_NFSUBS, "nfsubs", "nfsubs", 32,
5170 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5172 /* nfmuls$pack $FRi,$FRj,$FRk */
5174 FRV_INSN_NFMULS, "nfmuls", "nfmuls", 32,
5175 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
5177 /* nfdivs$pack $FRi,$FRj,$FRk */
5179 FRV_INSN_NFDIVS, "nfdivs", "nfdivs", 32,
5180 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
5182 /* fcmps$pack $FRi,$FRj,$FCCi_2 */
5184 FRV_INSN_FCMPS, "fcmps", "fcmps", 32,
5185 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5187 /* fcmpd$pack $FRdoublei,$FRdoublej,$FCCi_2 */
5189 FRV_INSN_FCMPD, "fcmpd", "fcmpd", 32,
5190 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5192 /* cfcmps$pack $FRi,$FRj,$FCCi_2,$CCi,$cond */
5194 FRV_INSN_CFCMPS, "cfcmps", "cfcmps", 32,
5195 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
5197 /* fdcmps$pack $FRi,$FRj,$FCCi_2 */
5199 FRV_INSN_FDCMPS, "fdcmps", "fdcmps", 32,
5200 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5202 /* fmadds$pack $FRi,$FRj,$FRk */
5204 FRV_INSN_FMADDS, "fmadds", "fmadds", 32,
5205 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5207 /* fmsubs$pack $FRi,$FRj,$FRk */
5209 FRV_INSN_FMSUBS, "fmsubs", "fmsubs", 32,
5210 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5212 /* fmaddd$pack $FRdoublei,$FRdoublej,$FRdoublek */
5214 FRV_INSN_FMADDD, "fmaddd", "fmaddd", 32,
5215 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5217 /* fmsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */
5219 FRV_INSN_FMSUBD, "fmsubd", "fmsubd", 32,
5220 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5222 /* fdmadds$pack $FRi,$FRj,$FRk */
5224 FRV_INSN_FDMADDS, "fdmadds", "fdmadds", 32,
5225 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5227 /* nfdmadds$pack $FRi,$FRj,$FRk */
5229 FRV_INSN_NFDMADDS, "nfdmadds", "nfdmadds", 32,
5230 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5232 /* cfmadds$pack $FRi,$FRj,$FRk,$CCi,$cond */
5234 FRV_INSN_CFMADDS, "cfmadds", "cfmadds", 32,
5235 { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5237 /* cfmsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */
5239 FRV_INSN_CFMSUBS, "cfmsubs", "cfmsubs", 32,
5240 { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5242 /* nfmadds$pack $FRi,$FRj,$FRk */
5244 FRV_INSN_NFMADDS, "nfmadds", "nfmadds", 32,
5245 { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5247 /* nfmsubs$pack $FRi,$FRj,$FRk */
5249 FRV_INSN_NFMSUBS, "nfmsubs", "nfmsubs", 32,
5250 { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5252 /* fmas$pack $FRi,$FRj,$FRk */
5254 FRV_INSN_FMAS, "fmas", "fmas", 32,
5255 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5257 /* fmss$pack $FRi,$FRj,$FRk */
5259 FRV_INSN_FMSS, "fmss", "fmss", 32,
5260 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5262 /* fdmas$pack $FRi,$FRj,$FRk */
5264 FRV_INSN_FDMAS, "fdmas", "fdmas", 32,
5265 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5267 /* fdmss$pack $FRi,$FRj,$FRk */
5269 FRV_INSN_FDMSS, "fdmss", "fdmss", 32,
5270 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5272 /* nfdmas$pack $FRi,$FRj,$FRk */
5274 FRV_INSN_NFDMAS, "nfdmas", "nfdmas", 32,
5275 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5277 /* nfdmss$pack $FRi,$FRj,$FRk */
5279 FRV_INSN_NFDMSS, "nfdmss", "nfdmss", 32,
5280 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5282 /* cfmas$pack $FRi,$FRj,$FRk,$CCi,$cond */
5284 FRV_INSN_CFMAS, "cfmas", "cfmas", 32,
5285 { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5287 /* cfmss$pack $FRi,$FRj,$FRk,$CCi,$cond */
5289 FRV_INSN_CFMSS, "cfmss", "cfmss", 32,
5290 { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5292 /* fmad$pack $FRi,$FRj,$FRk */
5294 FRV_INSN_FMAD, "fmad", "fmad", 32,
5295 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5297 /* fmsd$pack $FRi,$FRj,$FRk */
5299 FRV_INSN_FMSD, "fmsd", "fmsd", 32,
5300 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5302 /* nfmas$pack $FRi,$FRj,$FRk */
5304 FRV_INSN_NFMAS, "nfmas", "nfmas", 32,
5305 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5307 /* nfmss$pack $FRi,$FRj,$FRk */
5309 FRV_INSN_NFMSS, "nfmss", "nfmss", 32,
5310 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
5312 /* fdadds$pack $FRi,$FRj,$FRk */
5314 FRV_INSN_FDADDS, "fdadds", "fdadds", 32,
5315 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5317 /* fdsubs$pack $FRi,$FRj,$FRk */
5319 FRV_INSN_FDSUBS, "fdsubs", "fdsubs", 32,
5320 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5322 /* fdmuls$pack $FRi,$FRj,$FRk */
5324 FRV_INSN_FDMULS, "fdmuls", "fdmuls", 32,
5325 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
5327 /* fddivs$pack $FRi,$FRj,$FRk */
5329 FRV_INSN_FDDIVS, "fddivs", "fddivs", 32,
5330 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
5332 /* fdsads$pack $FRi,$FRj,$FRk */
5334 FRV_INSN_FDSADS, "fdsads", "fdsads", 32,
5335 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5337 /* fdmulcs$pack $FRi,$FRj,$FRk */
5339 FRV_INSN_FDMULCS, "fdmulcs", "fdmulcs", 32,
5340 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
5342 /* nfdmulcs$pack $FRi,$FRj,$FRk */
5344 FRV_INSN_NFDMULCS, "nfdmulcs", "nfdmulcs", 32,
5345 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
5347 /* nfdadds$pack $FRi,$FRj,$FRk */
5349 FRV_INSN_NFDADDS, "nfdadds", "nfdadds", 32,
5350 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5352 /* nfdsubs$pack $FRi,$FRj,$FRk */
5354 FRV_INSN_NFDSUBS, "nfdsubs", "nfdsubs", 32,
5355 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5357 /* nfdmuls$pack $FRi,$FRj,$FRk */
5359 FRV_INSN_NFDMULS, "nfdmuls", "nfdmuls", 32,
5360 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
5362 /* nfddivs$pack $FRi,$FRj,$FRk */
5364 FRV_INSN_NFDDIVS, "nfddivs", "nfddivs", 32,
5365 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
5367 /* nfdsads$pack $FRi,$FRj,$FRk */
5369 FRV_INSN_NFDSADS, "nfdsads", "nfdsads", 32,
5370 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5372 /* nfdcmps$pack $FRi,$FRj,$FCCi_2 */
5374 FRV_INSN_NFDCMPS, "nfdcmps", "nfdcmps", 32,
5375 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
5377 /* mhsetlos$pack $u12,$FRklo */
5379 FRV_INSN_MHSETLOS, "mhsetlos", "mhsetlos", 32,
5380 { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5382 /* mhsethis$pack $u12,$FRkhi */
5384 FRV_INSN_MHSETHIS, "mhsethis", "mhsethis", 32,
5385 { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5387 /* mhdsets$pack $u12,$FRintk */
5389 FRV_INSN_MHDSETS, "mhdsets", "mhdsets", 32,
5390 { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5392 /* mhsetloh$pack $s5,$FRklo */
5394 FRV_INSN_MHSETLOH, "mhsetloh", "mhsetloh", 32,
5395 { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5397 /* mhsethih$pack $s5,$FRkhi */
5399 FRV_INSN_MHSETHIH, "mhsethih", "mhsethih", 32,
5400 { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5402 /* mhdseth$pack $s5,$FRintk */
5404 FRV_INSN_MHDSETH, "mhdseth", "mhdseth", 32,
5405 { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5407 /* mand$pack $FRinti,$FRintj,$FRintk */
5409 FRV_INSN_MAND, "mand", "mand", 32,
5410 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5412 /* mor$pack $FRinti,$FRintj,$FRintk */
5414 FRV_INSN_MOR, "mor", "mor", 32,
5415 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5417 /* mxor$pack $FRinti,$FRintj,$FRintk */
5419 FRV_INSN_MXOR, "mxor", "mxor", 32,
5420 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5422 /* cmand$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5424 FRV_INSN_CMAND, "cmand", "cmand", 32,
5425 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5427 /* cmor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5429 FRV_INSN_CMOR, "cmor", "cmor", 32,
5430 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5432 /* cmxor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5434 FRV_INSN_CMXOR, "cmxor", "cmxor", 32,
5435 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5437 /* mnot$pack $FRintj,$FRintk */
5439 FRV_INSN_MNOT, "mnot", "mnot", 32,
5440 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5442 /* cmnot$pack $FRintj,$FRintk,$CCi,$cond */
5444 FRV_INSN_CMNOT, "cmnot", "cmnot", 32,
5445 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5447 /* mrotli$pack $FRinti,$u6,$FRintk */
5449 FRV_INSN_MROTLI, "mrotli", "mrotli", 32,
5450 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5452 /* mrotri$pack $FRinti,$u6,$FRintk */
5454 FRV_INSN_MROTRI, "mrotri", "mrotri", 32,
5455 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5457 /* mwcut$pack $FRinti,$FRintj,$FRintk */
5459 FRV_INSN_MWCUT, "mwcut", "mwcut", 32,
5460 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5462 /* mwcuti$pack $FRinti,$u6,$FRintk */
5464 FRV_INSN_MWCUTI, "mwcuti", "mwcuti", 32,
5465 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5467 /* mcut$pack $ACC40Si,$FRintj,$FRintk */
5469 FRV_INSN_MCUT, "mcut", "mcut", 32,
5470 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5472 /* mcuti$pack $ACC40Si,$s6,$FRintk */
5474 FRV_INSN_MCUTI, "mcuti", "mcuti", 32,
5475 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5477 /* mcutss$pack $ACC40Si,$FRintj,$FRintk */
5479 FRV_INSN_MCUTSS, "mcutss", "mcutss", 32,
5480 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5482 /* mcutssi$pack $ACC40Si,$s6,$FRintk */
5484 FRV_INSN_MCUTSSI, "mcutssi", "mcutssi", 32,
5485 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5487 /* mdcutssi$pack $ACC40Si,$s6,$FRintkeven */
5489 FRV_INSN_MDCUTSSI, "mdcutssi", "mdcutssi", 32,
5490 { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5492 /* maveh$pack $FRinti,$FRintj,$FRintk */
5494 FRV_INSN_MAVEH, "maveh", "maveh", 32,
5495 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5497 /* msllhi$pack $FRinti,$u6,$FRintk */
5499 FRV_INSN_MSLLHI, "msllhi", "msllhi", 32,
5500 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5502 /* msrlhi$pack $FRinti,$u6,$FRintk */
5504 FRV_INSN_MSRLHI, "msrlhi", "msrlhi", 32,
5505 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5507 /* msrahi$pack $FRinti,$u6,$FRintk */
5509 FRV_INSN_MSRAHI, "msrahi", "msrahi", 32,
5510 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5512 /* mdrotli$pack $FRintieven,$s6,$FRintkeven */
5514 FRV_INSN_MDROTLI, "mdrotli", "mdrotli", 32,
5515 { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5517 /* mcplhi$pack $FRinti,$u6,$FRintk */
5519 FRV_INSN_MCPLHI, "mcplhi", "mcplhi", 32,
5520 { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5522 /* mcpli$pack $FRinti,$u6,$FRintk */
5524 FRV_INSN_MCPLI, "mcpli", "mcpli", 32,
5525 { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5527 /* msaths$pack $FRinti,$FRintj,$FRintk */
5529 FRV_INSN_MSATHS, "msaths", "msaths", 32,
5530 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5532 /* mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven */
5534 FRV_INSN_MQSATHS, "mqsaths", "mqsaths", 32,
5535 { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5537 /* msathu$pack $FRinti,$FRintj,$FRintk */
5539 FRV_INSN_MSATHU, "msathu", "msathu", 32,
5540 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5542 /* mcmpsh$pack $FRinti,$FRintj,$FCCk */
5544 FRV_INSN_MCMPSH, "mcmpsh", "mcmpsh", 32,
5545 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5547 /* mcmpuh$pack $FRinti,$FRintj,$FCCk */
5549 FRV_INSN_MCMPUH, "mcmpuh", "mcmpuh", 32,
5550 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5552 /* mabshs$pack $FRintj,$FRintk */
5554 FRV_INSN_MABSHS, "mabshs", "mabshs", 32,
5555 { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5557 /* maddhss$pack $FRinti,$FRintj,$FRintk */
5559 FRV_INSN_MADDHSS, "maddhss", "maddhss", 32,
5560 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5562 /* maddhus$pack $FRinti,$FRintj,$FRintk */
5564 FRV_INSN_MADDHUS, "maddhus", "maddhus", 32,
5565 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5567 /* msubhss$pack $FRinti,$FRintj,$FRintk */
5569 FRV_INSN_MSUBHSS, "msubhss", "msubhss", 32,
5570 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5572 /* msubhus$pack $FRinti,$FRintj,$FRintk */
5574 FRV_INSN_MSUBHUS, "msubhus", "msubhus", 32,
5575 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5577 /* cmaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5579 FRV_INSN_CMADDHSS, "cmaddhss", "cmaddhss", 32,
5580 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5582 /* cmaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5584 FRV_INSN_CMADDHUS, "cmaddhus", "cmaddhus", 32,
5585 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5587 /* cmsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5589 FRV_INSN_CMSUBHSS, "cmsubhss", "cmsubhss", 32,
5590 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5592 /* cmsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
5594 FRV_INSN_CMSUBHUS, "cmsubhus", "cmsubhus", 32,
5595 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
5597 /* mqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven */
5599 FRV_INSN_MQADDHSS, "mqaddhss", "mqaddhss", 32,
5600 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5602 /* mqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven */
5604 FRV_INSN_MQADDHUS, "mqaddhus", "mqaddhus", 32,
5605 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5607 /* mqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven */
5609 FRV_INSN_MQSUBHSS, "mqsubhss", "mqsubhss", 32,
5610 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5612 /* mqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven */
5614 FRV_INSN_MQSUBHUS, "mqsubhus", "mqsubhus", 32,
5615 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5617 /* cmqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
5619 FRV_INSN_CMQADDHSS, "cmqaddhss", "cmqaddhss", 32,
5620 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5622 /* cmqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
5624 FRV_INSN_CMQADDHUS, "cmqaddhus", "cmqaddhus", 32,
5625 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5627 /* cmqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
5629 FRV_INSN_CMQSUBHSS, "cmqsubhss", "cmqsubhss", 32,
5630 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5632 /* cmqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
5634 FRV_INSN_CMQSUBHUS, "cmqsubhus", "cmqsubhus", 32,
5635 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
5637 /* maddaccs$pack $ACC40Si,$ACC40Sk */
5639 FRV_INSN_MADDACCS, "maddaccs", "maddaccs", 32,
5640 { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5642 /* msubaccs$pack $ACC40Si,$ACC40Sk */
5644 FRV_INSN_MSUBACCS, "msubaccs", "msubaccs", 32,
5645 { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5647 /* mdaddaccs$pack $ACC40Si,$ACC40Sk */
5649 FRV_INSN_MDADDACCS, "mdaddaccs", "mdaddaccs", 32,
5650 { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5652 /* mdsubaccs$pack $ACC40Si,$ACC40Sk */
5654 FRV_INSN_MDSUBACCS, "mdsubaccs", "mdsubaccs", 32,
5655 { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5657 /* masaccs$pack $ACC40Si,$ACC40Sk */
5659 FRV_INSN_MASACCS, "masaccs", "masaccs", 32,
5660 { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
5662 /* mdasaccs$pack $ACC40Si,$ACC40Sk */
5664 FRV_INSN_MDASACCS, "mdasaccs", "mdasaccs", 32,
5665 { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5667 /* mmulhs$pack $FRinti,$FRintj,$ACC40Sk */
5669 FRV_INSN_MMULHS, "mmulhs", "mmulhs", 32,
5670 { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5672 /* mmulhu$pack $FRinti,$FRintj,$ACC40Sk */
5674 FRV_INSN_MMULHU, "mmulhu", "mmulhu", 32,
5675 { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5677 /* mmulxhs$pack $FRinti,$FRintj,$ACC40Sk */
5679 FRV_INSN_MMULXHS, "mmulxhs", "mmulxhs", 32,
5680 { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5682 /* mmulxhu$pack $FRinti,$FRintj,$ACC40Sk */
5684 FRV_INSN_MMULXHU, "mmulxhu", "mmulxhu", 32,
5685 { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5687 /* cmmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5689 FRV_INSN_CMMULHS, "cmmulhs", "cmmulhs", 32,
5690 { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5692 /* cmmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5694 FRV_INSN_CMMULHU, "cmmulhu", "cmmulhu", 32,
5695 { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5697 /* mqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
5699 FRV_INSN_MQMULHS, "mqmulhs", "mqmulhs", 32,
5700 { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5702 /* mqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk */
5704 FRV_INSN_MQMULHU, "mqmulhu", "mqmulhu", 32,
5705 { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5707 /* mqmulxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
5709 FRV_INSN_MQMULXHS, "mqmulxhs", "mqmulxhs", 32,
5710 { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5712 /* mqmulxhu$pack $FRintieven,$FRintjeven,$ACC40Sk */
5714 FRV_INSN_MQMULXHU, "mqmulxhu", "mqmulxhu", 32,
5715 { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5717 /* cmqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
5719 FRV_INSN_CMQMULHS, "cmqmulhs", "cmqmulhs", 32,
5720 { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5722 /* cmqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
5724 FRV_INSN_CMQMULHU, "cmqmulhu", "cmqmulhu", 32,
5725 { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5727 /* mmachs$pack $FRinti,$FRintj,$ACC40Sk */
5729 FRV_INSN_MMACHS, "mmachs", "mmachs", 32,
5730 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5732 /* mmachu$pack $FRinti,$FRintj,$ACC40Uk */
5734 FRV_INSN_MMACHU, "mmachu", "mmachu", 32,
5735 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5737 /* mmrdhs$pack $FRinti,$FRintj,$ACC40Sk */
5739 FRV_INSN_MMRDHS, "mmrdhs", "mmrdhs", 32,
5740 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5742 /* mmrdhu$pack $FRinti,$FRintj,$ACC40Uk */
5744 FRV_INSN_MMRDHU, "mmrdhu", "mmrdhu", 32,
5745 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5747 /* cmmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5749 FRV_INSN_CMMACHS, "cmmachs", "cmmachs", 32,
5750 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5752 /* cmmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */
5754 FRV_INSN_CMMACHU, "cmmachu", "cmmachu", 32,
5755 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5757 /* mqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */
5759 FRV_INSN_MQMACHS, "mqmachs", "mqmachs", 32,
5760 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5762 /* mqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk */
5764 FRV_INSN_MQMACHU, "mqmachu", "mqmachu", 32,
5765 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5767 /* cmqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
5769 FRV_INSN_CMQMACHS, "cmqmachs", "cmqmachs", 32,
5770 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5772 /* cmqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk,$CCi,$cond */
5774 FRV_INSN_CMQMACHU, "cmqmachu", "cmqmachu", 32,
5775 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5777 /* mqxmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */
5779 FRV_INSN_MQXMACHS, "mqxmachs", "mqxmachs", 32,
5780 { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5782 /* mqxmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
5784 FRV_INSN_MQXMACXHS, "mqxmacxhs", "mqxmacxhs", 32,
5785 { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5787 /* mqmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
5789 FRV_INSN_MQMACXHS, "mqmacxhs", "mqmacxhs", 32,
5790 { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
5792 /* mcpxrs$pack $FRinti,$FRintj,$ACC40Sk */
5794 FRV_INSN_MCPXRS, "mcpxrs", "mcpxrs", 32,
5795 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5797 /* mcpxru$pack $FRinti,$FRintj,$ACC40Sk */
5799 FRV_INSN_MCPXRU, "mcpxru", "mcpxru", 32,
5800 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5802 /* mcpxis$pack $FRinti,$FRintj,$ACC40Sk */
5804 FRV_INSN_MCPXIS, "mcpxis", "mcpxis", 32,
5805 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5807 /* mcpxiu$pack $FRinti,$FRintj,$ACC40Sk */
5809 FRV_INSN_MCPXIU, "mcpxiu", "mcpxiu", 32,
5810 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5812 /* cmcpxrs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5814 FRV_INSN_CMCPXRS, "cmcpxrs", "cmcpxrs", 32,
5815 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5817 /* cmcpxru$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5819 FRV_INSN_CMCPXRU, "cmcpxru", "cmcpxru", 32,
5820 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5822 /* cmcpxis$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5824 FRV_INSN_CMCPXIS, "cmcpxis", "cmcpxis", 32,
5825 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5827 /* cmcpxiu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
5829 FRV_INSN_CMCPXIU, "cmcpxiu", "cmcpxiu", 32,
5830 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
5832 /* mqcpxrs$pack $FRintieven,$FRintjeven,$ACC40Sk */
5834 FRV_INSN_MQCPXRS, "mqcpxrs", "mqcpxrs", 32,
5835 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5837 /* mqcpxru$pack $FRintieven,$FRintjeven,$ACC40Sk */
5839 FRV_INSN_MQCPXRU, "mqcpxru", "mqcpxru", 32,
5840 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5842 /* mqcpxis$pack $FRintieven,$FRintjeven,$ACC40Sk */
5844 FRV_INSN_MQCPXIS, "mqcpxis", "mqcpxis", 32,
5845 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5847 /* mqcpxiu$pack $FRintieven,$FRintjeven,$ACC40Sk */
5849 FRV_INSN_MQCPXIU, "mqcpxiu", "mqcpxiu", 32,
5850 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
5852 /* mexpdhw$pack $FRinti,$u6,$FRintk */
5854 FRV_INSN_MEXPDHW, "mexpdhw", "mexpdhw", 32,
5855 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5857 /* cmexpdhw$pack $FRinti,$u6,$FRintk,$CCi,$cond */
5859 FRV_INSN_CMEXPDHW, "cmexpdhw", "cmexpdhw", 32,
5860 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5862 /* mexpdhd$pack $FRinti,$u6,$FRintkeven */
5864 FRV_INSN_MEXPDHD, "mexpdhd", "mexpdhd", 32,
5865 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5867 /* cmexpdhd$pack $FRinti,$u6,$FRintkeven,$CCi,$cond */
5869 FRV_INSN_CMEXPDHD, "cmexpdhd", "cmexpdhd", 32,
5870 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5872 /* mpackh$pack $FRinti,$FRintj,$FRintk */
5874 FRV_INSN_MPACKH, "mpackh", "mpackh", 32,
5875 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5877 /* mdpackh$pack $FRintieven,$FRintjeven,$FRintkeven */
5879 FRV_INSN_MDPACKH, "mdpackh", "mdpackh", 32,
5880 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_5 } }
5882 /* munpackh$pack $FRinti,$FRintkeven */
5884 FRV_INSN_MUNPACKH, "munpackh", "munpackh", 32,
5885 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5887 /* mdunpackh$pack $FRintieven,$FRintk */
5889 FRV_INSN_MDUNPACKH, "mdunpackh", "mdunpackh", 32,
5890 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } }
5892 /* mbtoh$pack $FRintj,$FRintkeven */
5894 FRV_INSN_MBTOH, "mbtoh", "mbtoh", 32,
5895 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5897 /* cmbtoh$pack $FRintj,$FRintkeven,$CCi,$cond */
5899 FRV_INSN_CMBTOH, "cmbtoh", "cmbtoh", 32,
5900 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5902 /* mhtob$pack $FRintjeven,$FRintk */
5904 FRV_INSN_MHTOB, "mhtob", "mhtob", 32,
5905 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5907 /* cmhtob$pack $FRintjeven,$FRintk,$CCi,$cond */
5909 FRV_INSN_CMHTOB, "cmhtob", "cmhtob", 32,
5910 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
5912 /* mbtohe$pack $FRintj,$FRintk */
5914 FRV_INSN_MBTOHE, "mbtohe", "mbtohe", 32,
5915 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } }
5917 /* cmbtohe$pack $FRintj,$FRintk,$CCi,$cond */
5919 FRV_INSN_CMBTOHE, "cmbtohe", "cmbtohe", 32,
5920 { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } }
5922 /* mclracc$pack $ACC40Sk,$A */
5924 FRV_INSN_MCLRACC, "mclracc", "mclracc", 32,
5925 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_3 } }
5927 /* mrdacc$pack $ACC40Si,$FRintk */
5929 FRV_INSN_MRDACC, "mrdacc", "mrdacc", 32,
5930 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5932 /* mrdaccg$pack $ACCGi,$FRintk */
5934 FRV_INSN_MRDACCG, "mrdaccg", "mrdaccg", 32,
5935 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
5937 /* mwtacc$pack $FRinti,$ACC40Sk */
5939 FRV_INSN_MWTACC, "mwtacc", "mwtacc", 32,
5940 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3 } }
5942 /* mwtaccg$pack $FRinti,$ACCGk */
5944 FRV_INSN_MWTACCG, "mwtaccg", "mwtaccg", 32,
5945 { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3 } }
5947 /* mcop1$pack $FRi,$FRj,$FRk */
5949 FRV_INSN_MCOP1, "mcop1", "mcop1", 32,
5950 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_1 } }
5952 /* mcop2$pack $FRi,$FRj,$FRk */
5954 FRV_INSN_MCOP2, "mcop2", "mcop2", 32,
5955 { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_1 } }
5959 FRV_INSN_FNOP, "fnop", "fnop", 32,
5960 { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_8 } }
5967 /* Initialize anything needed to be done once, before any cpu_open call. */
5968 static void init_tables PARAMS ((void));
5975 static const CGEN_MACH * lookup_mach_via_bfd_name
5976 PARAMS ((const CGEN_MACH *, const char *));
5977 static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
5978 static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
5979 static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
5980 static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
5981 static void frv_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
5983 /* Subroutine of frv_cgen_cpu_open to look up a mach via its bfd name. */
5985 static const CGEN_MACH *
5986 lookup_mach_via_bfd_name (table, name)
5987 const CGEN_MACH *table;
5992 if (strcmp (name, table->bfd_name) == 0)
5999 /* Subroutine of frv_cgen_cpu_open to build the hardware table. */
6006 int machs = cd->machs;
6007 const CGEN_HW_ENTRY *init = & frv_cgen_hw_table[0];
6008 /* MAX_HW is only an upper bound on the number of selected entries.
6009 However each entry is indexed by it's enum so there can be holes in
6011 const CGEN_HW_ENTRY **selected =
6012 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
6014 cd->hw_table.init_entries = init;
6015 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
6016 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
6017 /* ??? For now we just use machs to determine which ones we want. */
6018 for (i = 0; init[i].name != NULL; ++i)
6019 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
6021 selected[init[i].type] = &init[i];
6022 cd->hw_table.entries = selected;
6023 cd->hw_table.num_entries = MAX_HW;
6026 /* Subroutine of frv_cgen_cpu_open to build the hardware table. */
6029 build_ifield_table (cd)
6032 cd->ifld_table = & frv_cgen_ifld_table[0];
6035 /* Subroutine of frv_cgen_cpu_open to build the hardware table. */
6038 build_operand_table (cd)
6042 int machs = cd->machs;
6043 const CGEN_OPERAND *init = & frv_cgen_operand_table[0];
6044 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
6045 However each entry is indexed by it's enum so there can be holes in
6047 const CGEN_OPERAND **selected =
6048 (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
6050 cd->operand_table.init_entries = init;
6051 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
6052 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
6053 /* ??? For now we just use mach to determine which ones we want. */
6054 for (i = 0; init[i].name != NULL; ++i)
6055 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
6057 selected[init[i].type] = &init[i];
6058 cd->operand_table.entries = selected;
6059 cd->operand_table.num_entries = MAX_OPERANDS;
6062 /* Subroutine of frv_cgen_cpu_open to build the hardware table.
6063 ??? This could leave out insns not supported by the specified mach/isa,
6064 but that would cause errors like "foo only supported by bar" to become
6065 "unknown insn", so for now we include all insns and require the app to
6066 do the checking later.
6067 ??? On the other hand, parsing of such insns may require their hardware or
6068 operand elements to be in the table [which they mightn't be]. */
6071 build_insn_table (cd)
6075 const CGEN_IBASE *ib = & frv_cgen_insn_table[0];
6076 CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
6078 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
6079 for (i = 0; i < MAX_INSNS; ++i)
6080 insns[i].base = &ib[i];
6081 cd->insn_table.init_entries = insns;
6082 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
6083 cd->insn_table.num_init_entries = MAX_INSNS;
6086 /* Subroutine of frv_cgen_cpu_open to rebuild the tables. */
6089 frv_cgen_rebuild_tables (cd)
6093 unsigned int isas = cd->isas;
6094 unsigned int machs = cd->machs;
6096 cd->int_insn_p = CGEN_INT_INSN_P;
6098 /* Data derived from the isa spec. */
6099 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
6100 cd->default_insn_bitsize = UNSET;
6101 cd->base_insn_bitsize = UNSET;
6102 cd->min_insn_bitsize = 65535; /* some ridiculously big number */
6103 cd->max_insn_bitsize = 0;
6104 for (i = 0; i < MAX_ISAS; ++i)
6105 if (((1 << i) & isas) != 0)
6107 const CGEN_ISA *isa = & frv_cgen_isa_table[i];
6109 /* Default insn sizes of all selected isas must be
6110 equal or we set the result to 0, meaning "unknown". */
6111 if (cd->default_insn_bitsize == UNSET)
6112 cd->default_insn_bitsize = isa->default_insn_bitsize;
6113 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
6116 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
6118 /* Base insn sizes of all selected isas must be equal
6119 or we set the result to 0, meaning "unknown". */
6120 if (cd->base_insn_bitsize == UNSET)
6121 cd->base_insn_bitsize = isa->base_insn_bitsize;
6122 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
6125 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
6127 /* Set min,max insn sizes. */
6128 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
6129 cd->min_insn_bitsize = isa->min_insn_bitsize;
6130 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
6131 cd->max_insn_bitsize = isa->max_insn_bitsize;
6134 /* Data derived from the mach spec. */
6135 for (i = 0; i < MAX_MACHS; ++i)
6136 if (((1 << i) & machs) != 0)
6138 const CGEN_MACH *mach = & frv_cgen_mach_table[i];
6140 if (mach->insn_chunk_bitsize != 0)
6142 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
6144 fprintf (stderr, "frv_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
6145 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
6149 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
6153 /* Determine which hw elements are used by MACH. */
6154 build_hw_table (cd);
6156 /* Build the ifield table. */
6157 build_ifield_table (cd);
6159 /* Determine which operands are used by MACH/ISA. */
6160 build_operand_table (cd);
6162 /* Build the instruction table. */
6163 build_insn_table (cd);
6166 /* Initialize a cpu table and return a descriptor.
6167 It's much like opening a file, and must be the first function called.
6168 The arguments are a set of (type/value) pairs, terminated with
6171 Currently supported values:
6172 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
6173 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
6174 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
6175 CGEN_CPU_OPEN_ENDIAN: specify endian choice
6176 CGEN_CPU_OPEN_END: terminates arguments
6178 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
6181 ??? We only support ISO C stdargs here, not K&R.
6182 Laziness, plus experiment to see if anything requires K&R - eventually
6183 K&R will no longer be supported - e.g. GDB is currently trying this. */
6186 frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
6188 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
6190 unsigned int isas = 0; /* 0 = "unspecified" */
6191 unsigned int machs = 0; /* 0 = "unspecified" */
6192 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
6201 memset (cd, 0, sizeof (*cd));
6203 va_start (ap, arg_type);
6204 while (arg_type != CGEN_CPU_OPEN_END)
6208 case CGEN_CPU_OPEN_ISAS :
6209 isas = va_arg (ap, unsigned int);
6211 case CGEN_CPU_OPEN_MACHS :
6212 machs = va_arg (ap, unsigned int);
6214 case CGEN_CPU_OPEN_BFDMACH :
6216 const char *name = va_arg (ap, const char *);
6217 const CGEN_MACH *mach =
6218 lookup_mach_via_bfd_name (frv_cgen_mach_table, name);
6220 machs |= 1 << mach->num;
6223 case CGEN_CPU_OPEN_ENDIAN :
6224 endian = va_arg (ap, enum cgen_endian);
6227 fprintf (stderr, "frv_cgen_cpu_open: unsupported argument `%d'\n",
6229 abort (); /* ??? return NULL? */
6231 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
6235 /* mach unspecified means "all" */
6237 machs = (1 << MAX_MACHS) - 1;
6238 /* base mach is always selected */
6240 /* isa unspecified means "all" */
6242 isas = (1 << MAX_ISAS) - 1;
6243 if (endian == CGEN_ENDIAN_UNKNOWN)
6245 /* ??? If target has only one, could have a default. */
6246 fprintf (stderr, "frv_cgen_cpu_open: no endianness specified\n");
6252 cd->endian = endian;
6253 /* FIXME: for the sparc case we can determine insn-endianness statically.
6254 The worry here is where both data and insn endian can be independently
6255 chosen, in which case this function will need another argument.
6256 Actually, will want to allow for more arguments in the future anyway. */
6257 cd->insn_endian = endian;
6259 /* Table (re)builder. */
6260 cd->rebuild_tables = frv_cgen_rebuild_tables;
6261 frv_cgen_rebuild_tables (cd);
6263 /* Default to not allowing signed overflow. */
6264 cd->signed_overflow_ok_p = 0;
6266 return (CGEN_CPU_DESC) cd;
6269 /* Cover fn to frv_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
6270 MACH_NAME is the bfd name of the mach. */
6273 frv_cgen_cpu_open_1 (mach_name, endian)
6274 const char *mach_name;
6275 enum cgen_endian endian;
6277 return frv_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
6278 CGEN_CPU_OPEN_ENDIAN, endian,
6282 /* Close a cpu table.
6283 ??? This can live in a machine independent file, but there's currently
6284 no place to put this file (there's no libcgen). libopcodes is the wrong
6285 place as some simulator ports use this but they don't use libopcodes. */
6288 frv_cgen_cpu_close (cd)
6292 const CGEN_INSN *insns;
6294 if (cd->macro_insn_table.init_entries)
6296 insns = cd->macro_insn_table.init_entries;
6297 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
6299 if (CGEN_INSN_RX ((insns)))
6300 regfree (CGEN_INSN_RX (insns));
6304 if (cd->insn_table.init_entries)
6306 insns = cd->insn_table.init_entries;
6307 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
6309 if (CGEN_INSN_RX (insns))
6310 regfree (CGEN_INSN_RX (insns));
6316 if (cd->macro_insn_table.init_entries)
6317 free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
6319 if (cd->insn_table.init_entries)
6320 free ((CGEN_INSN *) cd->insn_table.init_entries);
6322 if (cd->hw_table.entries)
6323 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
6325 if (cd->operand_table.entries)
6326 free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
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