1 /* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
4 THIS FILE IS USED TO GENERATE fr30-opc.c.
6 Copyright (C) 1998 Free Software Foundation, Inc.
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
27 #include "libiberty.h"
33 /* The hash functions are recorded here to help keep assembler code out of
34 the disassembler and vice versa. */
36 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
37 static unsigned int asm_hash_insn PARAMS ((const char *));
38 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
39 static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
41 /* Look up instruction INSN_VALUE and extract its fields.
42 INSN, if non-null, is the insn table entry.
43 Otherwise INSN_VALUE is examined to compute it.
44 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
45 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
46 If INSN != NULL, LENGTH must be valid.
47 ALIAS_P is non-zero if alias insns are to be included in the search.
49 The result is a pointer to the insn table entry, or NULL if the instruction
53 fr30_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
55 const CGEN_INSN *insn;
56 CGEN_INSN_BYTES insn_value;
61 unsigned char buf[CGEN_MAX_INSN_SIZE];
63 CGEN_INSN_INT base_insn;
65 CGEN_EXTRACT_INFO *info = NULL;
67 CGEN_EXTRACT_INFO ex_info;
68 CGEN_EXTRACT_INFO *info = &ex_info;
72 cgen_put_insn_value (od, buf, length, insn_value);
74 base_insn = insn_value; /*???*/
76 ex_info.dis_info = NULL;
77 ex_info.insn_bytes = insn_value;
79 base_insn = cgen_get_insn_value (od, buf, length);
85 const CGEN_INSN_LIST *insn_list;
87 /* The instructions are stored in hash lists.
88 Pick the first one and keep trying until we find the right one. */
90 insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
91 while (insn_list != NULL)
93 insn = insn_list->insn;
96 || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
98 /* Basic bit mask must be correct. */
99 /* ??? May wish to allow target to defer this check until the
101 if ((base_insn & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
103 /* ??? 0 is passed for `pc' */
104 int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
110 if (length != 0 && length != elength)
117 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
122 /* Sanity check: can't pass an alias insn if ! alias_p. */
124 && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
126 /* Sanity check: length must be correct. */
127 if (length != CGEN_INSN_BITSIZE (insn))
130 /* ??? 0 is passed for `pc' */
131 length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
133 /* Sanity check: must succeed.
134 Could relax this later if it ever proves useful. */
143 /* Fill in the operand instances used by INSN whose operands are FIELDS.
144 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
148 fr30_cgen_get_insn_operands (od, insn, fields, indices)
150 const CGEN_INSN * insn;
151 const CGEN_FIELDS * fields;
154 const CGEN_OPERAND_INSTANCE *opinst;
157 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
159 && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
162 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
164 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
166 indices[i] = fr30_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
171 /* Cover function to fr30_cgen_get_insn_operands when either INSN or FIELDS
173 The INSN, INSN_VALUE, and LENGTH arguments are passed to
174 fr30_cgen_lookup_insn unchanged.
176 The result is the insn table entry or NULL if the instruction wasn't
180 fr30_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
182 const CGEN_INSN *insn;
183 CGEN_INSN_BYTES insn_value;
189 /* Pass non-zero for ALIAS_P only if INSN != NULL.
190 If INSN == NULL, we want a real insn. */
191 insn = fr30_cgen_lookup_insn (od, insn, insn_value, length, &fields,
196 fr30_cgen_get_insn_operands (od, insn, &fields, indices);
201 static const CGEN_ATTR_ENTRY MACH_attr[] =
203 { "base", MACH_BASE },
204 { "fr30", MACH_FR30 },
209 const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
211 { "CACHE-ADDR", NULL },
212 { "FUN-ACCESS", NULL },
218 const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
220 { "ABS-ADDR", NULL },
221 { "HASH-PREFIX", NULL },
222 { "NEGATIVE", NULL },
223 { "PCREL-ADDR", NULL },
225 { "SEM-ONLY", NULL },
226 { "SIGN-OPT", NULL },
228 { "UNSIGNED", NULL },
232 const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
235 { "COND-CTI", NULL },
238 { "RELAXABLE", NULL },
239 { "SKIP-CTI", NULL },
240 { "UNCOND-CTI", NULL },
245 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_gr_entries[] =
268 CGEN_KEYWORD fr30_cgen_opval_h_gr =
270 & fr30_cgen_opval_h_gr_entries[0],
274 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_dr_entries[] =
284 CGEN_KEYWORD fr30_cgen_opval_h_dr =
286 & fr30_cgen_opval_h_dr_entries[0],
290 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
295 CGEN_KEYWORD fr30_cgen_opval_h_ps =
297 & fr30_cgen_opval_h_ps_entries[0],
301 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
306 CGEN_KEYWORD fr30_cgen_opval_h_r13 =
308 & fr30_cgen_opval_h_r13_entries[0],
312 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
317 CGEN_KEYWORD fr30_cgen_opval_h_r14 =
319 & fr30_cgen_opval_h_r14_entries[0],
323 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
328 CGEN_KEYWORD fr30_cgen_opval_h_r15 =
330 & fr30_cgen_opval_h_r15_entries[0],
335 /* The hardware table. */
337 #define HW_ENT(n) fr30_cgen_hw_entries[n]
338 static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] =
340 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { 0 } } },
341 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
342 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
343 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
344 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
345 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
346 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
347 { HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { 0, 0, { 0 } } },
348 { HW_H_PS, & HW_ENT (HW_H_PS + 1), "h-ps", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
349 { HW_H_R13, & HW_ENT (HW_H_R13 + 1), "h-r13", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, 0, { 0 } } },
350 { HW_H_R14, & HW_ENT (HW_H_R14 + 1), "h-r14", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, 0, { 0 } } },
351 { HW_H_R15, & HW_ENT (HW_H_R15 + 1), "h-r15", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, 0, { 0 } } },
352 { HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
353 { HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
354 { HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
355 { HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
356 { HW_H_IBIT, & HW_ENT (HW_H_IBIT + 1), "h-ibit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
357 { HW_H_SBIT, & HW_ENT (HW_H_SBIT + 1), "h-sbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
361 /* The operand table. */
363 #define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
364 #define OP_ENT(op) fr30_cgen_operand_table[OPERAND (op)]
366 const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
368 /* pc: program counter */
369 { "pc", & HW_ENT (HW_H_PC), 0, 0,
370 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
371 /* Ri: destination register */
372 { "Ri", & HW_ENT (HW_H_GR), 12, 4,
373 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
374 /* Rj: source register */
375 { "Rj", & HW_ENT (HW_H_GR), 8, 4,
376 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
377 /* Rs1: dedicated register */
378 { "Rs1", & HW_ENT (HW_H_DR), 8, 4,
379 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
380 /* Rs2: dedicated register */
381 { "Rs2", & HW_ENT (HW_H_DR), 12, 4,
382 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
383 /* R13: General Register 13 */
384 { "R13", & HW_ENT (HW_H_R13), 0, 0,
386 /* R14: General Register 14 */
387 { "R14", & HW_ENT (HW_H_R14), 0, 0,
389 /* R15: General Register 15 */
390 { "R15", & HW_ENT (HW_H_R15), 0, 0,
392 /* ps: Program Status register */
393 { "ps", & HW_ENT (HW_H_PS), 0, 0,
395 /* u4: 4 bit unsigned immediate */
396 { "u4", & HW_ENT (HW_H_UINT), 8, 4,
397 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
398 /* m4: 4 bit negative immediate */
399 { "m4", & HW_ENT (HW_H_UINT), 8, 4,
400 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
401 /* u8: 8 bit unsigned immediate */
402 { "u8", & HW_ENT (HW_H_UINT), 8, 8,
403 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
404 /* i8: 8 bit unsigned immediate */
405 { "i8", & HW_ENT (HW_H_UINT), 4, 8,
406 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
407 /* udisp6: 6 bit unsigned immediate */
408 { "udisp6", & HW_ENT (HW_H_UINT), 8, 4,
409 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
410 /* disp8: 8 bit signed immediate */
411 { "disp8", & HW_ENT (HW_H_SINT), 4, 8,
412 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
413 /* disp9: 9 bit signed immediate */
414 { "disp9", & HW_ENT (HW_H_SINT), 4, 8,
415 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
416 /* disp10: 10 bit signed immediate */
417 { "disp10", & HW_ENT (HW_H_SINT), 4, 8,
418 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
419 /* s10: 10 bit signed immediate */
420 { "s10", & HW_ENT (HW_H_SINT), 8, 8,
421 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
422 /* u10: 10 bit unsigned immediate */
423 { "u10", & HW_ENT (HW_H_UINT), 8, 8,
424 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
425 /* i32: 32 bit immediate */
426 { "i32", & HW_ENT (HW_H_UINT), 16, 32,
427 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
428 /* dir8: 8 bit direct address */
429 { "dir8", & HW_ENT (HW_H_UINT), 8, 8,
430 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
431 /* dir9: 9 bit direct address */
432 { "dir9", & HW_ENT (HW_H_UINT), 8, 8,
433 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
434 /* dir10: 10 bit direct address */
435 { "dir10", & HW_ENT (HW_H_UINT), 8, 8,
436 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
437 /* label9: 9 bit pc relative address */
438 { "label9", & HW_ENT (HW_H_SINT), 8, 8,
439 { 0, 0|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
440 /* label12: 12 bit pc relative address */
441 { "label12", & HW_ENT (HW_H_SINT), 5, 11,
442 { 0, 0|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
443 /* cc: condition codes */
444 { "cc", & HW_ENT (HW_H_UINT), 4, 4,
445 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
446 /* nbit: negative bit */
447 { "nbit", & HW_ENT (HW_H_NBIT), 0, 0,
448 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
449 /* vbit: overflow bit */
450 { "vbit", & HW_ENT (HW_H_VBIT), 0, 0,
451 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
453 { "zbit", & HW_ENT (HW_H_ZBIT), 0, 0,
454 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
455 /* cbit: carry bit */
456 { "cbit", & HW_ENT (HW_H_CBIT), 0, 0,
457 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
458 /* ibit: interrupt bit */
459 { "ibit", & HW_ENT (HW_H_IBIT), 0, 0,
460 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
461 /* sbit: stack bit */
462 { "sbit", & HW_ENT (HW_H_SBIT), 0, 0,
463 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
466 /* Operand references. */
468 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
469 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
470 #define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
472 static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
473 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
474 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
475 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
476 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
477 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
478 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
479 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
483 static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
484 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
485 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
486 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
487 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
488 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
489 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
490 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
494 static const CGEN_OPERAND_INSTANCE fmt_add2_ops[] = {
495 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
496 { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
497 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
498 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
499 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
500 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
501 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
505 static const CGEN_OPERAND_INSTANCE fmt_addc_ops[] = {
506 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
507 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
508 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
509 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
510 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
511 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
512 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
513 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
517 static const CGEN_OPERAND_INSTANCE fmt_addn_ops[] = {
518 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
519 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
520 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
524 static const CGEN_OPERAND_INSTANCE fmt_addni_ops[] = {
525 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
526 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
527 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
531 static const CGEN_OPERAND_INSTANCE fmt_addn2_ops[] = {
532 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
533 { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
534 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
538 static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
539 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
540 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
541 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
542 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
543 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
544 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
548 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
549 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
550 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
551 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
552 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
553 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
554 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
558 static const CGEN_OPERAND_INSTANCE fmt_cmp2_ops[] = {
559 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
560 { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
561 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
562 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
563 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
564 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
568 static const CGEN_OPERAND_INSTANCE fmt_and_ops[] = {
569 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
570 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
571 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
572 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
573 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
577 static const CGEN_OPERAND_INSTANCE fmt_andm_ops[] = {
578 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
579 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
580 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
581 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
582 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
583 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
587 static const CGEN_OPERAND_INSTANCE fmt_andh_ops[] = {
588 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
589 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
590 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RJ), 0, 0 },
591 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
592 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
593 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
597 static const CGEN_OPERAND_INSTANCE fmt_andb_ops[] = {
598 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
599 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
600 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RJ), 0, 0 },
601 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
602 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
603 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
607 static const CGEN_OPERAND_INSTANCE fmt_ldi32_ops[] = {
608 { INPUT, "i32", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I32), 0, 0 },
609 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
613 static const CGEN_OPERAND_INSTANCE fmt_mov2dr_ops[] = {
614 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
615 { OUTPUT, "Rs1", & HW_ENT (HW_H_DR), CGEN_MODE_USI, & OP_ENT (RS1), 0, 0 },
619 static const CGEN_OPERAND_INSTANCE fmt_int_ops[] = {
620 { INPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 2, 0 },
621 { INPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
622 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
623 { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (U8), 0, 0 },
624 { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 2, 0 },
625 { OUTPUT, "h_memory_reg__VM_h_dr_2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, 0 },
626 { OUTPUT, "ibit", & HW_ENT (HW_H_IBIT), CGEN_MODE_BI, 0, 0, 0 },
627 { OUTPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
628 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
632 static const CGEN_OPERAND_INSTANCE fmt_reti_ops[] = {
633 { INPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
634 { INPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 2, COND_REF },
635 { INPUT, "h_memory_reg__VM_h_dr_2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
636 { INPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 3, COND_REF },
637 { INPUT, "h_memory_reg__VM_h_dr_3", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
638 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
639 { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 2, COND_REF },
640 { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, COND_REF },
641 { OUTPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 3, COND_REF },
649 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
650 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
651 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
653 /* The instruction table.
654 This is currently non-static because the simulator accesses it
657 const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
659 /* Special null first entry.
660 A `num' value of zero is thus invalid.
661 Also, the special `invalid' insn resides here. */
666 FR30_INSN_ADD, "add", "add",
667 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
668 { 16, 16, 0xff00 }, 0xa600,
669 (PTR) & fmt_add_ops[0],
675 FR30_INSN_ADDI, "addi", "add",
676 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
677 { 16, 16, 0xff00 }, 0xa400,
678 (PTR) & fmt_addi_ops[0],
684 FR30_INSN_ADD2, "add2", "add2",
685 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
686 { 16, 16, 0xff00 }, 0xa500,
687 (PTR) & fmt_add2_ops[0],
693 FR30_INSN_ADDC, "addc", "addc",
694 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
695 { 16, 16, 0xff00 }, 0xa700,
696 (PTR) & fmt_addc_ops[0],
702 FR30_INSN_ADDN, "addn", "addn",
703 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
704 { 16, 16, 0xff00 }, 0xa200,
705 (PTR) & fmt_addn_ops[0],
711 FR30_INSN_ADDNI, "addni", "addn",
712 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
713 { 16, 16, 0xff00 }, 0xa000,
714 (PTR) & fmt_addni_ops[0],
720 FR30_INSN_ADDN2, "addn2", "addn2",
721 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
722 { 16, 16, 0xff00 }, 0xa100,
723 (PTR) & fmt_addn2_ops[0],
729 FR30_INSN_SUB, "sub", "sub",
730 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
731 { 16, 16, 0xff00 }, 0xac00,
732 (PTR) & fmt_add_ops[0],
738 FR30_INSN_SUBC, "subc", "subc",
739 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
740 { 16, 16, 0xff00 }, 0xad00,
741 (PTR) & fmt_addc_ops[0],
747 FR30_INSN_SUBN, "subn", "subn",
748 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
749 { 16, 16, 0xff00 }, 0xae00,
750 (PTR) & fmt_addn_ops[0],
756 FR30_INSN_CMP, "cmp", "cmp",
757 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
758 { 16, 16, 0xff00 }, 0xaa00,
759 (PTR) & fmt_cmp_ops[0],
765 FR30_INSN_CMPI, "cmpi", "cmp",
766 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
767 { 16, 16, 0xff00 }, 0xa800,
768 (PTR) & fmt_cmpi_ops[0],
774 FR30_INSN_CMP2, "cmp2", "cmp2",
775 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
776 { 16, 16, 0xff00 }, 0xa900,
777 (PTR) & fmt_cmp2_ops[0],
783 FR30_INSN_AND, "and", "and",
784 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
785 { 16, 16, 0xff00 }, 0x8200,
786 (PTR) & fmt_and_ops[0],
792 FR30_INSN_OR, "or", "or",
793 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
794 { 16, 16, 0xff00 }, 0x9200,
795 (PTR) & fmt_and_ops[0],
801 FR30_INSN_EOR, "eor", "eor",
802 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
803 { 16, 16, 0xff00 }, 0x9a00,
804 (PTR) & fmt_and_ops[0],
810 FR30_INSN_ANDM, "andm", "and",
811 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
812 { 16, 16, 0xff00 }, 0x8400,
813 (PTR) & fmt_andm_ops[0],
819 FR30_INSN_ANDH, "andh", "andh",
820 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
821 { 16, 16, 0xff00 }, 0x8500,
822 (PTR) & fmt_andh_ops[0],
828 FR30_INSN_ANDB, "andb", "andb",
829 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
830 { 16, 16, 0xff00 }, 0x8600,
831 (PTR) & fmt_andb_ops[0],
837 FR30_INSN_ORM, "orm", "or",
838 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
839 { 16, 16, 0xff00 }, 0x9400,
840 (PTR) & fmt_andm_ops[0],
846 FR30_INSN_ORH, "orh", "orh",
847 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
848 { 16, 16, 0xff00 }, 0x9500,
849 (PTR) & fmt_andh_ops[0],
855 FR30_INSN_ORB, "orb", "orb",
856 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
857 { 16, 16, 0xff00 }, 0x9600,
858 (PTR) & fmt_andb_ops[0],
864 FR30_INSN_EORM, "eorm", "eor",
865 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
866 { 16, 16, 0xff00 }, 0x9c00,
867 (PTR) & fmt_andm_ops[0],
873 FR30_INSN_EORH, "eorh", "eorh",
874 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
875 { 16, 16, 0xff00 }, 0x9d00,
876 (PTR) & fmt_andh_ops[0],
882 FR30_INSN_EORB, "eorb", "eorb",
883 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
884 { 16, 16, 0xff00 }, 0x9e00,
885 (PTR) & fmt_andb_ops[0],
891 FR30_INSN_BANDL, "bandl", "bandl",
892 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
893 { 16, 16, 0xff00 }, 0x8000,
900 FR30_INSN_BORL, "borl", "borl",
901 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
902 { 16, 16, 0xff00 }, 0x9000,
909 FR30_INSN_BEORL, "beorl", "beorl",
910 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
911 { 16, 16, 0xff00 }, 0x9800,
918 FR30_INSN_BANDH, "bandh", "bandh",
919 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
920 { 16, 16, 0xff00 }, 0x8100,
927 FR30_INSN_BORH, "borh", "borh",
928 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
929 { 16, 16, 0xff00 }, 0x9100,
936 FR30_INSN_BEORH, "beorh", "beorh",
937 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
938 { 16, 16, 0xff00 }, 0x9900,
945 FR30_INSN_BTSTL, "btstl", "btstl",
946 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
947 { 16, 16, 0xff00 }, 0x8800,
954 FR30_INSN_BTSTH, "btsth", "btsth",
955 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
956 { 16, 16, 0xff00 }, 0x8900,
963 FR30_INSN_MUL, "mul", "mul",
964 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
965 { 16, 16, 0xff00 }, 0xaf00,
972 FR30_INSN_MULU, "mulu", "mulu",
973 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
974 { 16, 16, 0xff00 }, 0xab00,
981 FR30_INSN_MULH, "mulh", "mulh",
982 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
983 { 16, 16, 0xff00 }, 0xbf00,
990 FR30_INSN_MULUH, "muluh", "muluh",
991 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
992 { 16, 16, 0xff00 }, 0xbb00,
999 FR30_INSN_DIV0S, "div0s", "div0s",
1000 { { MNEM, ' ', OP (RI), 0 } },
1001 { 16, 16, 0xfff0 }, 0x9740,
1008 FR30_INSN_DIV0U, "div0u", "div0u",
1009 { { MNEM, ' ', OP (RI), 0 } },
1010 { 16, 16, 0xfff0 }, 0x9750,
1017 FR30_INSN_DIV1, "div1", "div1",
1018 { { MNEM, ' ', OP (RI), 0 } },
1019 { 16, 16, 0xfff0 }, 0x9760,
1026 FR30_INSN_DIV2, "div2", "div2",
1027 { { MNEM, ' ', OP (RI), 0 } },
1028 { 16, 16, 0xfff0 }, 0x9770,
1035 FR30_INSN_DIV3, "div3", "div3",
1037 { 16, 16, 0xffff }, 0x9f60,
1044 FR30_INSN_DIV4S, "div4s", "div4s",
1046 { 16, 16, 0xffff }, 0x9f70,
1053 FR30_INSN_LSL, "lsl", "lsl",
1054 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1055 { 16, 16, 0xff00 }, 0xb600,
1062 FR30_INSN_LSLI, "lsli", "lsl",
1063 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1064 { 16, 16, 0xff00 }, 0xb400,
1071 FR30_INSN_LSL2, "lsl2", "lsl2",
1072 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1073 { 16, 16, 0xff00 }, 0xb500,
1080 FR30_INSN_LSR, "lsr", "lsr",
1081 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1082 { 16, 16, 0xff00 }, 0xb200,
1089 FR30_INSN_LSRI, "lsri", "lsr",
1090 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1091 { 16, 16, 0xff00 }, 0xb000,
1098 FR30_INSN_LSR2, "lsr2", "lsr2",
1099 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1100 { 16, 16, 0xff00 }, 0xb100,
1107 FR30_INSN_ASR, "asr", "asr",
1108 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1109 { 16, 16, 0xff00 }, 0xba00,
1116 FR30_INSN_ASRI, "asri", "asr",
1117 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1118 { 16, 16, 0xff00 }, 0xb800,
1125 FR30_INSN_ASR2, "asr2", "asr2",
1126 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1127 { 16, 16, 0xff00 }, 0xb900,
1134 FR30_INSN_LDI_8, "ldi:8", "ldi:8",
1135 { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
1136 { 16, 16, 0xf000 }, 0xc000,
1140 /* ldi:32 $i32,$Ri */
1143 FR30_INSN_LDI32, "ldi32", "ldi:32",
1144 { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
1145 { 16, 48, 0xfff0 }, 0x9f80,
1146 (PTR) & fmt_ldi32_ops[0],
1152 FR30_INSN_LD, "ld", "ld",
1153 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1154 { 16, 16, 0xff00 }, 0x400,
1161 FR30_INSN_LDUH, "lduh", "lduh",
1162 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1163 { 16, 16, 0xff00 }, 0x500,
1170 FR30_INSN_LDUB, "ldub", "ldub",
1171 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1172 { 16, 16, 0xff00 }, 0x600,
1176 /* ld @($r13,$Rj),$Ri */
1179 FR30_INSN_LDR13, "ldr13", "ld",
1180 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1181 { 16, 16, 0xff00 }, 0x0,
1185 /* lduh @($r13,$Rj),$Ri */
1188 FR30_INSN_LDR13UH, "ldr13uh", "lduh",
1189 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1190 { 16, 16, 0xff00 }, 0x100,
1194 /* ldub @($r13,$Rj),$Ri */
1197 FR30_INSN_LDR13UB, "ldr13ub", "ldub",
1198 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1199 { 16, 16, 0xff00 }, 0x200,
1203 /* ld @($r14,$disp10),$Ri */
1206 FR30_INSN_LDR14, "ldr14", "ld",
1207 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP10), ')', ',', OP (RI), 0 } },
1208 { 16, 16, 0xf000 }, 0x2000,
1212 /* lduh @($r14,$disp9),$Ri */
1215 FR30_INSN_LDR14UH, "ldr14uh", "lduh",
1216 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP9), ')', ',', OP (RI), 0 } },
1217 { 16, 16, 0xf000 }, 0x4000,
1221 /* ldub @($r14,$disp8),$Ri */
1224 FR30_INSN_LDR14UB, "ldr14ub", "ldub",
1225 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP8), ')', ',', OP (RI), 0 } },
1226 { 16, 16, 0xf000 }, 0x6000,
1230 /* ld @($r15,$udisp6),$Ri */
1233 FR30_INSN_LDR15, "ldr15", "ld",
1234 { { MNEM, ' ', '@', '(', OP (R15), ',', OP (UDISP6), ')', ',', OP (RI), 0 } },
1235 { 16, 16, 0xff00 }, 0x300,
1242 FR30_INSN_LDR15GR, "ldr15gr", "ld",
1243 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RI), 0 } },
1244 { 16, 16, 0xfff0 }, 0x700,
1248 /* ld @$r15+,$Rs2 */
1251 FR30_INSN_LDR15DR, "ldr15dr", "ld",
1252 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RS2), 0 } },
1253 { 16, 16, 0xfff0 }, 0x780,
1260 FR30_INSN_LDR15PS, "ldr15ps", "ld",
1261 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (PS), 0 } },
1262 { 16, 16, 0xffff }, 0x790,
1269 FR30_INSN_ST, "st", "st",
1270 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1271 { 16, 16, 0xff00 }, 0x1400,
1278 FR30_INSN_STH, "sth", "sth",
1279 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1280 { 16, 16, 0xff00 }, 0x1500,
1287 FR30_INSN_STB, "stb", "stb",
1288 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1289 { 16, 16, 0xff00 }, 0x1600,
1293 /* st $Ri,@($r13,$Rj) */
1296 FR30_INSN_STR13, "str13", "st",
1297 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1298 { 16, 16, 0xff00 }, 0x1000,
1302 /* sth $Ri,@($r13,$Rj) */
1305 FR30_INSN_STR13H, "str13h", "sth",
1306 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1307 { 16, 16, 0xff00 }, 0x1100,
1311 /* stb $Ri,@($r13,$Rj) */
1314 FR30_INSN_STR13B, "stR13b", "stb",
1315 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1316 { 16, 16, 0xff00 }, 0x1200,
1320 /* st $Ri,@($r14,$disp10) */
1323 FR30_INSN_STR14, "str14", "st",
1324 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP10), ')', 0 } },
1325 { 16, 16, 0xf000 }, 0x3000,
1329 /* sth $Ri,@($r14,$disp9) */
1332 FR30_INSN_STR14H, "str14h", "sth",
1333 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP9), ')', 0 } },
1334 { 16, 16, 0xf000 }, 0x5000,
1338 /* stb $Ri,@($r14,$disp8) */
1341 FR30_INSN_STR14B, "str14b", "stb",
1342 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP8), ')', 0 } },
1343 { 16, 16, 0xf000 }, 0x7000,
1347 /* st $Ri,@($r15,$udisp6) */
1350 FR30_INSN_STR15, "str15", "st",
1351 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R15), ',', OP (UDISP6), ')', 0 } },
1352 { 16, 16, 0xff00 }, 0x1300,
1359 FR30_INSN_STR15GR, "str15gr", "st",
1360 { { MNEM, ' ', OP (RI), ',', '@', '-', OP (R15), 0 } },
1361 { 16, 16, 0xfff0 }, 0x1700,
1365 /* st $Rs2,@-$r15 */
1368 FR30_INSN_STR15DR, "str15dr", "st",
1369 { { MNEM, ' ', OP (RS2), ',', '@', '-', OP (R15), 0 } },
1370 { 16, 16, 0xfff0 }, 0x1780,
1377 FR30_INSN_STR15PS, "str15ps", "st",
1378 { { MNEM, ' ', OP (PS), ',', '@', '-', OP (R15), 0 } },
1379 { 16, 16, 0xffff }, 0x1790,
1386 FR30_INSN_MOV, "mov", "mov",
1387 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1388 { 16, 16, 0xff00 }, 0x8b00,
1395 FR30_INSN_MOVDR, "movdr", "mov",
1396 { { MNEM, ' ', OP (RS1), ',', OP (RI), 0 } },
1397 { 16, 16, 0xff00 }, 0xb700,
1404 FR30_INSN_MOVPS, "movps", "mov",
1405 { { MNEM, ' ', OP (PS), ',', OP (RI), 0 } },
1406 { 16, 16, 0xfff0 }, 0x1710,
1413 FR30_INSN_MOV2DR, "mov2dr", "mov",
1414 { { MNEM, ' ', OP (RI), ',', OP (RS1), 0 } },
1415 { 16, 16, 0xff00 }, 0xb300,
1416 (PTR) & fmt_mov2dr_ops[0],
1422 FR30_INSN_MOV2PS, "mov2ps", "mov",
1423 { { MNEM, ' ', OP (RI), ',', OP (PS), 0 } },
1424 { 16, 16, 0xfff0 }, 0x710,
1431 FR30_INSN_JMP, "jmp", "jmp",
1432 { { MNEM, ' ', '@', OP (RI), 0 } },
1433 { 16, 16, 0xfff0 }, 0x9700,
1440 FR30_INSN_JMPD, "jmpd", "jmp:D",
1441 { { MNEM, ' ', '@', OP (RI), 0 } },
1442 { 16, 16, 0xfff0 }, 0x9f00,
1449 FR30_INSN_CALL, "call", "call",
1450 { { MNEM, ' ', OP (LABEL12), 0 } },
1451 { 16, 16, 0xf400 }, 0xd000,
1455 /* call:D $label12 */
1458 FR30_INSN_CALLD, "calld", "call:D",
1459 { { MNEM, ' ', OP (LABEL12), 0 } },
1460 { 16, 16, 0xf400 }, 0xd400,
1467 FR30_INSN_CALLR, "callr", "call",
1468 { { MNEM, ' ', '@', OP (RI), 0 } },
1469 { 16, 16, 0xfff0 }, 0x9710,
1476 FR30_INSN_CALLRD, "callrd", "call:D",
1477 { { MNEM, ' ', '@', OP (RI), 0 } },
1478 { 16, 16, 0xfff0 }, 0x9f10,
1485 FR30_INSN_RET, "ret", "ret",
1487 { 16, 16, 0xffff }, 0x9720,
1494 FR30_INSN_RETD, "retd", "ret:D",
1496 { 16, 16, 0xffff }, 0x9f20,
1503 FR30_INSN_INT, "int", "int",
1504 { { MNEM, ' ', OP (U8), 0 } },
1505 { 16, 16, 0xff00 }, 0x1f00,
1506 (PTR) & fmt_int_ops[0],
1507 { 0, 0|A(UNCOND_CTI), { 0 } }
1512 FR30_INSN_INTE, "inte", "inte",
1514 { 16, 16, 0xffff }, 0x9f30,
1521 FR30_INSN_RETI, "reti", "reti",
1523 { 16, 16, 0xffff }, 0x9730,
1524 (PTR) & fmt_reti_ops[0],
1525 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
1530 FR30_INSN_BRA, "bra", "bra",
1531 { { MNEM, ' ', OP (LABEL9), 0 } },
1532 { 16, 16, 0xff00 }, 0xe000,
1539 FR30_INSN_BNO, "bno", "bno",
1540 { { MNEM, ' ', OP (LABEL9), 0 } },
1541 { 16, 16, 0xff00 }, 0xe100,
1548 FR30_INSN_BEQ, "beq", "beq",
1549 { { MNEM, ' ', OP (LABEL9), 0 } },
1550 { 16, 16, 0xff00 }, 0xe200,
1557 FR30_INSN_BNE, "bne", "bne",
1558 { { MNEM, ' ', OP (LABEL9), 0 } },
1559 { 16, 16, 0xff00 }, 0xe300,
1566 FR30_INSN_BC, "bc", "bc",
1567 { { MNEM, ' ', OP (LABEL9), 0 } },
1568 { 16, 16, 0xff00 }, 0xe400,
1575 FR30_INSN_BNC, "bnc", "bnc",
1576 { { MNEM, ' ', OP (LABEL9), 0 } },
1577 { 16, 16, 0xff00 }, 0xe500,
1584 FR30_INSN_BN, "bn", "bn",
1585 { { MNEM, ' ', OP (LABEL9), 0 } },
1586 { 16, 16, 0xff00 }, 0xe600,
1593 FR30_INSN_BP, "bp", "bp",
1594 { { MNEM, ' ', OP (LABEL9), 0 } },
1595 { 16, 16, 0xff00 }, 0xe700,
1602 FR30_INSN_BV, "bv", "bv",
1603 { { MNEM, ' ', OP (LABEL9), 0 } },
1604 { 16, 16, 0xff00 }, 0xe800,
1611 FR30_INSN_BNV, "bnv", "bnv",
1612 { { MNEM, ' ', OP (LABEL9), 0 } },
1613 { 16, 16, 0xff00 }, 0xe900,
1620 FR30_INSN_BLT, "blt", "blt",
1621 { { MNEM, ' ', OP (LABEL9), 0 } },
1622 { 16, 16, 0xff00 }, 0xea00,
1629 FR30_INSN_BGE, "bge", "bge",
1630 { { MNEM, ' ', OP (LABEL9), 0 } },
1631 { 16, 16, 0xff00 }, 0xeb00,
1638 FR30_INSN_BLE, "ble", "ble",
1639 { { MNEM, ' ', OP (LABEL9), 0 } },
1640 { 16, 16, 0xff00 }, 0xec00,
1647 FR30_INSN_BGT, "bgt", "bgt",
1648 { { MNEM, ' ', OP (LABEL9), 0 } },
1649 { 16, 16, 0xff00 }, 0xed00,
1656 FR30_INSN_BLS, "bls", "bls",
1657 { { MNEM, ' ', OP (LABEL9), 0 } },
1658 { 16, 16, 0xff00 }, 0xee00,
1665 FR30_INSN_BHI, "bhi", "bhi",
1666 { { MNEM, ' ', OP (LABEL9), 0 } },
1667 { 16, 16, 0xff00 }, 0xef00,
1674 FR30_INSN_BRAD, "brad", "bra:D",
1675 { { MNEM, ' ', OP (LABEL9), 0 } },
1676 { 16, 16, 0xff00 }, 0xf000,
1683 FR30_INSN_BNOD, "bnod", "bno:D",
1684 { { MNEM, ' ', OP (LABEL9), 0 } },
1685 { 16, 16, 0xff00 }, 0xf100,
1692 FR30_INSN_BEQD, "beqd", "beq:D",
1693 { { MNEM, ' ', OP (LABEL9), 0 } },
1694 { 16, 16, 0xff00 }, 0xf200,
1701 FR30_INSN_BNED, "bned", "bne:D",
1702 { { MNEM, ' ', OP (LABEL9), 0 } },
1703 { 16, 16, 0xff00 }, 0xf300,
1710 FR30_INSN_BCD, "bcd", "bc:D",
1711 { { MNEM, ' ', OP (LABEL9), 0 } },
1712 { 16, 16, 0xff00 }, 0xf400,
1719 FR30_INSN_BNCD, "bncd", "bnc:D",
1720 { { MNEM, ' ', OP (LABEL9), 0 } },
1721 { 16, 16, 0xff00 }, 0xf500,
1728 FR30_INSN_BND, "bnd", "bn:D",
1729 { { MNEM, ' ', OP (LABEL9), 0 } },
1730 { 16, 16, 0xff00 }, 0xf600,
1737 FR30_INSN_BPD, "bpd", "bp:D",
1738 { { MNEM, ' ', OP (LABEL9), 0 } },
1739 { 16, 16, 0xff00 }, 0xf700,
1746 FR30_INSN_BVD, "bvd", "bv:D",
1747 { { MNEM, ' ', OP (LABEL9), 0 } },
1748 { 16, 16, 0xff00 }, 0xf800,
1755 FR30_INSN_BNVD, "bnvd", "bnv:D",
1756 { { MNEM, ' ', OP (LABEL9), 0 } },
1757 { 16, 16, 0xff00 }, 0xf900,
1764 FR30_INSN_BLTD, "bltd", "blt:D",
1765 { { MNEM, ' ', OP (LABEL9), 0 } },
1766 { 16, 16, 0xff00 }, 0xfa00,
1773 FR30_INSN_BGED, "bged", "bge:D",
1774 { { MNEM, ' ', OP (LABEL9), 0 } },
1775 { 16, 16, 0xff00 }, 0xfb00,
1782 FR30_INSN_BLED, "bled", "ble:D",
1783 { { MNEM, ' ', OP (LABEL9), 0 } },
1784 { 16, 16, 0xff00 }, 0xfc00,
1791 FR30_INSN_BGTD, "bgtd", "bgt:D",
1792 { { MNEM, ' ', OP (LABEL9), 0 } },
1793 { 16, 16, 0xff00 }, 0xfd00,
1800 FR30_INSN_BLSD, "blsd", "bls:D",
1801 { { MNEM, ' ', OP (LABEL9), 0 } },
1802 { 16, 16, 0xff00 }, 0xfe00,
1809 FR30_INSN_BHID, "bhid", "bhi:D",
1810 { { MNEM, ' ', OP (LABEL9), 0 } },
1811 { 16, 16, 0xff00 }, 0xff00,
1815 /* dmov @$dir10,$R13 */
1818 FR30_INSN_DMOV2R13, "dmov2r13", "dmov",
1819 { { MNEM, ' ', '@', OP (DIR10), ',', OP (R13), 0 } },
1820 { 16, 16, 0xff00 }, 0x800,
1824 /* dmovh @$dir9,$R13 */
1827 FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh",
1828 { { MNEM, ' ', '@', OP (DIR9), ',', OP (R13), 0 } },
1829 { 16, 16, 0xff00 }, 0x900,
1833 /* dmovb @$dir8,$R13 */
1836 FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb",
1837 { { MNEM, ' ', '@', OP (DIR8), ',', OP (R13), 0 } },
1838 { 16, 16, 0xff00 }, 0xa00,
1842 /* dmov $R13,@$dir10 */
1845 FR30_INSN_DMOVR13, "dmovr13", "dmov",
1846 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR10), 0 } },
1847 { 16, 16, 0xff00 }, 0x1800,
1851 /* dmovh $R13,@$dir9 */
1854 FR30_INSN_DMOVR13H, "dmovr13h", "dmovh",
1855 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR9), 0 } },
1856 { 16, 16, 0xff00 }, 0x1900,
1860 /* dmovb $R13,@$dir8 */
1863 FR30_INSN_DMOVR13B, "dmovr13b", "dmovb",
1864 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR8), 0 } },
1865 { 16, 16, 0xff00 }, 0x1a00,
1869 /* dmov @$dir10,@$R13+ */
1872 FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov",
1873 { { MNEM, ' ', '@', OP (DIR10), ',', '@', OP (R13), '+', 0 } },
1874 { 16, 16, 0xff00 }, 0xc00,
1878 /* dmovh @$dir9,@$R13+ */
1881 FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh",
1882 { { MNEM, ' ', '@', OP (DIR9), ',', '@', OP (R13), '+', 0 } },
1883 { 16, 16, 0xff00 }, 0xd00,
1887 /* dmovb @$dir8,@$R13+ */
1890 FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb",
1891 { { MNEM, ' ', '@', OP (DIR8), ',', '@', OP (R13), '+', 0 } },
1892 { 16, 16, 0xff00 }, 0xe00,
1896 /* dmov @$R13+,@$dir10 */
1899 FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov",
1900 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR10), 0 } },
1901 { 16, 16, 0xff00 }, 0x1c00,
1905 /* dmovh @$R13+,@$dir9 */
1908 FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh",
1909 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR9), 0 } },
1910 { 16, 16, 0xff00 }, 0x1d00,
1914 /* dmovb @$R13+,@$dir8 */
1917 FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb",
1918 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR8), 0 } },
1919 { 16, 16, 0xff00 }, 0x1e00,
1923 /* dmov @$dir10,@-$R15 */
1926 FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov",
1927 { { MNEM, ' ', '@', OP (DIR10), ',', '@', '-', OP (R15), 0 } },
1928 { 16, 16, 0xff00 }, 0xb00,
1932 /* dmov @$R15+,@$dir10 */
1935 FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov",
1936 { { MNEM, ' ', '@', OP (R15), '+', ',', '@', OP (DIR10), 0 } },
1937 { 16, 16, 0xff00 }, 0x1b00,
1941 /* ldres @$Ri+,$u4 */
1944 FR30_INSN_LDRES, "ldres", "ldres",
1945 { { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } },
1946 { 16, 16, 0xff00 }, 0xbc00,
1950 /* stres $u4,@$Ri+ */
1953 FR30_INSN_STRES, "stres", "stres",
1954 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } },
1955 { 16, 16, 0xff00 }, 0xbd00,
1962 FR30_INSN_NOP, "nop", "nop",
1964 { 16, 16, 0xffff }, 0x9fa0,
1971 FR30_INSN_ANDCCR, "andccr", "andccr",
1972 { { MNEM, ' ', OP (U8), 0 } },
1973 { 16, 16, 0xff00 }, 0x8300,
1980 FR30_INSN_ORCCR, "orccr", "orccr",
1981 { { MNEM, ' ', OP (U8), 0 } },
1982 { 16, 16, 0xff00 }, 0x9300,
1989 FR30_INSN_STILM, "stilm", "stilm",
1990 { { MNEM, ' ', OP (U8), 0 } },
1991 { 16, 16, 0xff00 }, 0x8700,
1998 FR30_INSN_ADDSP, "addsp", "addsp",
1999 { { MNEM, ' ', OP (S10), 0 } },
2000 { 16, 16, 0xff00 }, 0xa300,
2007 FR30_INSN_EXTSB, "extsb", "extsb",
2008 { { MNEM, ' ', OP (RI), 0 } },
2009 { 16, 16, 0xfff0 }, 0x9780,
2016 FR30_INSN_EXTUB, "extub", "extub",
2017 { { MNEM, ' ', OP (RI), 0 } },
2018 { 16, 16, 0xfff0 }, 0x9790,
2025 FR30_INSN_EXTSH, "extsh", "extsh",
2026 { { MNEM, ' ', OP (RI), 0 } },
2027 { 16, 16, 0xfff0 }, 0x97a0,
2034 FR30_INSN_EXTUH, "extuh", "extuh",
2035 { { MNEM, ' ', OP (RI), 0 } },
2036 { 16, 16, 0xfff0 }, 0x97b0,
2043 FR30_INSN_ENTER, "enter", "enter",
2044 { { MNEM, ' ', OP (U10), 0 } },
2045 { 16, 16, 0xff00 }, 0xf00,
2052 FR30_INSN_LEAVE, "leave", "leave",
2054 { 16, 16, 0xffff }, 0x9f90,
2061 FR30_INSN_XCHB, "xchb", "xchb",
2062 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2063 { 16, 16, 0xff00 }, 0x8a00,
2073 static const CGEN_INSN_TABLE insn_table =
2075 & fr30_cgen_insn_table_entries[0],
2081 /* Each non-simple macro entry points to an array of expansion possibilities. */
2083 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2084 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2085 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2087 /* The macro instruction table. */
2089 static const CGEN_INSN macro_insn_table_entries[] =
2091 /* ldi32 $i32,$Ri */
2094 -1, "ldi32m", "ldi32",
2095 { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
2096 { 16, 48, 0xfff0 }, 0x9f80,
2098 { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
2106 static const CGEN_INSN_TABLE macro_insn_table =
2108 & macro_insn_table_entries[0],
2110 (sizeof (macro_insn_table_entries) /
2111 sizeof (macro_insn_table_entries[0])),
2120 /* Return non-zero if INSN is to be added to the hash table.
2121 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
2124 asm_hash_insn_p (insn)
2125 const CGEN_INSN * insn;
2127 return CGEN_ASM_HASH_P (insn);
2131 dis_hash_insn_p (insn)
2132 const CGEN_INSN * insn;
2134 /* If building the hash table and the NO-DIS attribute is present,
2136 if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
2138 return CGEN_DIS_HASH_P (insn);
2141 /* The result is the hash value of the insn.
2142 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
2145 asm_hash_insn (mnem)
2148 return CGEN_ASM_HASH (mnem);
2151 /* BUF is a pointer to the insn's bytes in target order.
2152 VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
2156 dis_hash_insn (buf, value)
2158 CGEN_INSN_INT value;
2160 return CGEN_DIS_HASH (buf, value);
2163 /* Initialize an opcode table and return a descriptor.
2164 It's much like opening a file, and must be the first function called. */
2167 fr30_cgen_opcode_open (mach, endian)
2169 enum cgen_endian endian;
2171 CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
2180 memset (table, 0, sizeof (*table));
2182 CGEN_OPCODE_MACH (table) = mach;
2183 CGEN_OPCODE_ENDIAN (table) = endian;
2184 /* FIXME: for the sparc case we can determine insn-endianness statically.
2185 The worry here is where both data and insn endian can be independently
2186 chosen, in which case this function will need another argument.
2187 Actually, will want to allow for more arguments in the future anyway. */
2188 CGEN_OPCODE_INSN_ENDIAN (table) = endian;
2190 CGEN_OPCODE_HW_LIST (table) = & fr30_cgen_hw_entries[0];
2192 CGEN_OPCODE_OPERAND_TABLE (table) = & fr30_cgen_operand_table[0];
2194 * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
2196 * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
2198 CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
2199 CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
2200 CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
2202 CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
2203 CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
2204 CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
2206 return (CGEN_OPCODE_DESC) table;
2209 /* Close an opcode table. */
2212 fr30_cgen_opcode_close (desc)
2213 CGEN_OPCODE_DESC desc;
2218 /* Getting values from cgen_fields is handled by a collection of functions.
2219 They are distinguished by the type of the VALUE argument they return.
2220 TODO: floating point, inlining support, remove cases where result type
2224 fr30_cgen_get_int_operand (opindex, fields)
2226 const CGEN_FIELDS * fields;
2232 case FR30_OPERAND_RI :
2233 value = fields->f_Ri;
2235 case FR30_OPERAND_RJ :
2236 value = fields->f_Rj;
2238 case FR30_OPERAND_RS1 :
2239 value = fields->f_Rs1;
2241 case FR30_OPERAND_RS2 :
2242 value = fields->f_Rs2;
2244 case FR30_OPERAND_R13 :
2245 value = fields->f_nil;
2247 case FR30_OPERAND_R14 :
2248 value = fields->f_nil;
2250 case FR30_OPERAND_R15 :
2251 value = fields->f_nil;
2253 case FR30_OPERAND_PS :
2254 value = fields->f_nil;
2256 case FR30_OPERAND_U4 :
2257 value = fields->f_u4;
2259 case FR30_OPERAND_M4 :
2260 value = fields->f_m4;
2262 case FR30_OPERAND_U8 :
2263 value = fields->f_u8;
2265 case FR30_OPERAND_I8 :
2266 value = fields->f_i8;
2268 case FR30_OPERAND_UDISP6 :
2269 value = fields->f_udisp6;
2271 case FR30_OPERAND_DISP8 :
2272 value = fields->f_disp8;
2274 case FR30_OPERAND_DISP9 :
2275 value = fields->f_disp9;
2277 case FR30_OPERAND_DISP10 :
2278 value = fields->f_disp10;
2280 case FR30_OPERAND_S10 :
2281 value = fields->f_s10;
2283 case FR30_OPERAND_U10 :
2284 value = fields->f_u10;
2286 case FR30_OPERAND_I32 :
2287 value = fields->f_i32;
2289 case FR30_OPERAND_DIR8 :
2290 value = fields->f_dir8;
2292 case FR30_OPERAND_DIR9 :
2293 value = fields->f_dir9;
2295 case FR30_OPERAND_DIR10 :
2296 value = fields->f_dir10;
2298 case FR30_OPERAND_LABEL9 :
2299 value = fields->f_rel9;
2301 case FR30_OPERAND_LABEL12 :
2302 value = fields->f_rel12;
2304 case FR30_OPERAND_CC :
2305 value = fields->f_cc;
2309 /* xgettext:c-format */
2310 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
2319 fr30_cgen_get_vma_operand (opindex, fields)
2321 const CGEN_FIELDS * fields;
2327 case FR30_OPERAND_RI :
2328 value = fields->f_Ri;
2330 case FR30_OPERAND_RJ :
2331 value = fields->f_Rj;
2333 case FR30_OPERAND_RS1 :
2334 value = fields->f_Rs1;
2336 case FR30_OPERAND_RS2 :
2337 value = fields->f_Rs2;
2339 case FR30_OPERAND_R13 :
2340 value = fields->f_nil;
2342 case FR30_OPERAND_R14 :
2343 value = fields->f_nil;
2345 case FR30_OPERAND_R15 :
2346 value = fields->f_nil;
2348 case FR30_OPERAND_PS :
2349 value = fields->f_nil;
2351 case FR30_OPERAND_U4 :
2352 value = fields->f_u4;
2354 case FR30_OPERAND_M4 :
2355 value = fields->f_m4;
2357 case FR30_OPERAND_U8 :
2358 value = fields->f_u8;
2360 case FR30_OPERAND_I8 :
2361 value = fields->f_i8;
2363 case FR30_OPERAND_UDISP6 :
2364 value = fields->f_udisp6;
2366 case FR30_OPERAND_DISP8 :
2367 value = fields->f_disp8;
2369 case FR30_OPERAND_DISP9 :
2370 value = fields->f_disp9;
2372 case FR30_OPERAND_DISP10 :
2373 value = fields->f_disp10;
2375 case FR30_OPERAND_S10 :
2376 value = fields->f_s10;
2378 case FR30_OPERAND_U10 :
2379 value = fields->f_u10;
2381 case FR30_OPERAND_I32 :
2382 value = fields->f_i32;
2384 case FR30_OPERAND_DIR8 :
2385 value = fields->f_dir8;
2387 case FR30_OPERAND_DIR9 :
2388 value = fields->f_dir9;
2390 case FR30_OPERAND_DIR10 :
2391 value = fields->f_dir10;
2393 case FR30_OPERAND_LABEL9 :
2394 value = fields->f_rel9;
2396 case FR30_OPERAND_LABEL12 :
2397 value = fields->f_rel12;
2399 case FR30_OPERAND_CC :
2400 value = fields->f_cc;
2404 /* xgettext:c-format */
2405 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
2413 /* Stuffing values in cgen_fields is handled by a collection of functions.
2414 They are distinguished by the type of the VALUE argument they accept.
2415 TODO: floating point, inlining support, remove cases where argument type
2419 fr30_cgen_set_int_operand (opindex, fields, value)
2421 CGEN_FIELDS * fields;
2426 case FR30_OPERAND_RI :
2427 fields->f_Ri = value;
2429 case FR30_OPERAND_RJ :
2430 fields->f_Rj = value;
2432 case FR30_OPERAND_RS1 :
2433 fields->f_Rs1 = value;
2435 case FR30_OPERAND_RS2 :
2436 fields->f_Rs2 = value;
2438 case FR30_OPERAND_R13 :
2439 fields->f_nil = value;
2441 case FR30_OPERAND_R14 :
2442 fields->f_nil = value;
2444 case FR30_OPERAND_R15 :
2445 fields->f_nil = value;
2447 case FR30_OPERAND_PS :
2448 fields->f_nil = value;
2450 case FR30_OPERAND_U4 :
2451 fields->f_u4 = value;
2453 case FR30_OPERAND_M4 :
2454 fields->f_m4 = value;
2456 case FR30_OPERAND_U8 :
2457 fields->f_u8 = value;
2459 case FR30_OPERAND_I8 :
2460 fields->f_i8 = value;
2462 case FR30_OPERAND_UDISP6 :
2463 fields->f_udisp6 = value;
2465 case FR30_OPERAND_DISP8 :
2466 fields->f_disp8 = value;
2468 case FR30_OPERAND_DISP9 :
2469 fields->f_disp9 = value;
2471 case FR30_OPERAND_DISP10 :
2472 fields->f_disp10 = value;
2474 case FR30_OPERAND_S10 :
2475 fields->f_s10 = value;
2477 case FR30_OPERAND_U10 :
2478 fields->f_u10 = value;
2480 case FR30_OPERAND_I32 :
2481 fields->f_i32 = value;
2483 case FR30_OPERAND_DIR8 :
2484 fields->f_dir8 = value;
2486 case FR30_OPERAND_DIR9 :
2487 fields->f_dir9 = value;
2489 case FR30_OPERAND_DIR10 :
2490 fields->f_dir10 = value;
2492 case FR30_OPERAND_LABEL9 :
2493 fields->f_rel9 = value;
2495 case FR30_OPERAND_LABEL12 :
2496 fields->f_rel12 = value;
2498 case FR30_OPERAND_CC :
2499 fields->f_cc = value;
2503 /* xgettext:c-format */
2504 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
2511 fr30_cgen_set_vma_operand (opindex, fields, value)
2513 CGEN_FIELDS * fields;
2518 case FR30_OPERAND_RI :
2519 fields->f_Ri = value;
2521 case FR30_OPERAND_RJ :
2522 fields->f_Rj = value;
2524 case FR30_OPERAND_RS1 :
2525 fields->f_Rs1 = value;
2527 case FR30_OPERAND_RS2 :
2528 fields->f_Rs2 = value;
2530 case FR30_OPERAND_R13 :
2531 fields->f_nil = value;
2533 case FR30_OPERAND_R14 :
2534 fields->f_nil = value;
2536 case FR30_OPERAND_R15 :
2537 fields->f_nil = value;
2539 case FR30_OPERAND_PS :
2540 fields->f_nil = value;
2542 case FR30_OPERAND_U4 :
2543 fields->f_u4 = value;
2545 case FR30_OPERAND_M4 :
2546 fields->f_m4 = value;
2548 case FR30_OPERAND_U8 :
2549 fields->f_u8 = value;
2551 case FR30_OPERAND_I8 :
2552 fields->f_i8 = value;
2554 case FR30_OPERAND_UDISP6 :
2555 fields->f_udisp6 = value;
2557 case FR30_OPERAND_DISP8 :
2558 fields->f_disp8 = value;
2560 case FR30_OPERAND_DISP9 :
2561 fields->f_disp9 = value;
2563 case FR30_OPERAND_DISP10 :
2564 fields->f_disp10 = value;
2566 case FR30_OPERAND_S10 :
2567 fields->f_s10 = value;
2569 case FR30_OPERAND_U10 :
2570 fields->f_u10 = value;
2572 case FR30_OPERAND_I32 :
2573 fields->f_i32 = value;
2575 case FR30_OPERAND_DIR8 :
2576 fields->f_dir8 = value;
2578 case FR30_OPERAND_DIR9 :
2579 fields->f_dir9 = value;
2581 case FR30_OPERAND_DIR10 :
2582 fields->f_dir10 = value;
2584 case FR30_OPERAND_LABEL9 :
2585 fields->f_rel9 = value;
2587 case FR30_OPERAND_LABEL12 :
2588 fields->f_rel12 = value;
2590 case FR30_OPERAND_CC :
2591 fields->f_cc = value;
2595 /* xgettext:c-format */
2596 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),