1 /* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
4 THIS FILE IS USED TO GENERATE fr30-opc.c.
6 Copyright (C) 1998 Free Software Foundation, Inc.
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
27 #include "libiberty.h"
33 /* The hash functions are recorded here to help keep assembler code out of
34 the disassembler and vice versa. */
36 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
37 static unsigned int asm_hash_insn PARAMS ((const char *));
38 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
39 static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
41 /* Look up instruction INSN_VALUE and extract its fields.
42 INSN, if non-null, is the insn table entry.
43 Otherwise INSN_VALUE is examined to compute it.
44 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
45 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
46 If INSN != NULL, LENGTH must be valid.
47 ALIAS_P is non-zero if alias insns are to be included in the search.
49 The result is a pointer to the insn table entry, or NULL if the instruction
53 fr30_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
55 const CGEN_INSN *insn;
56 CGEN_INSN_BYTES insn_value;
61 unsigned char buf[CGEN_MAX_INSN_SIZE];
63 CGEN_INSN_INT base_insn;
65 CGEN_EXTRACT_INFO *info = NULL;
67 CGEN_EXTRACT_INFO ex_info;
68 CGEN_EXTRACT_INFO *info = &ex_info;
72 cgen_put_insn_value (od, buf, length, insn_value);
74 base_insn = insn_value; /*???*/
76 ex_info.dis_info = NULL;
77 ex_info.insn_bytes = insn_value;
79 base_insn = cgen_get_insn_value (od, buf, length);
85 const CGEN_INSN_LIST *insn_list;
87 /* The instructions are stored in hash lists.
88 Pick the first one and keep trying until we find the right one. */
90 insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
91 while (insn_list != NULL)
93 insn = insn_list->insn;
96 || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
98 /* Basic bit mask must be correct. */
99 /* ??? May wish to allow target to defer this check until the
101 if ((base_insn & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
103 /* ??? 0 is passed for `pc' */
104 int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
110 if (length != 0 && length != elength)
117 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
122 /* Sanity check: can't pass an alias insn if ! alias_p. */
124 && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
126 /* Sanity check: length must be correct. */
127 if (length != CGEN_INSN_BITSIZE (insn))
130 /* ??? 0 is passed for `pc' */
131 length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
133 /* Sanity check: must succeed.
134 Could relax this later if it ever proves useful. */
143 /* Fill in the operand instances used by INSN whose operands are FIELDS.
144 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
148 fr30_cgen_get_insn_operands (od, insn, fields, indices)
150 const CGEN_INSN * insn;
151 const CGEN_FIELDS * fields;
154 const CGEN_OPERAND_INSTANCE *opinst;
157 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
159 && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
162 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
164 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
166 indices[i] = fr30_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
171 /* Cover function to fr30_cgen_get_insn_operands when either INSN or FIELDS
173 The INSN, INSN_VALUE, and LENGTH arguments are passed to
174 fr30_cgen_lookup_insn unchanged.
176 The result is the insn table entry or NULL if the instruction wasn't
180 fr30_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
182 const CGEN_INSN *insn;
183 CGEN_INSN_BYTES insn_value;
189 /* Pass non-zero for ALIAS_P only if INSN != NULL.
190 If INSN == NULL, we want a real insn. */
191 insn = fr30_cgen_lookup_insn (od, insn, insn_value, length, &fields,
196 fr30_cgen_get_insn_operands (od, insn, &fields, indices);
201 static const CGEN_ATTR_ENTRY MACH_attr[] =
203 { "base", MACH_BASE },
204 { "fr30", MACH_FR30 },
209 const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
211 { "CACHE-ADDR", NULL },
212 { "FUN-ACCESS", NULL },
218 const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
220 { "ABS-ADDR", NULL },
221 { "HASH-PREFIX", NULL },
222 { "NEGATIVE", NULL },
223 { "PCREL-ADDR", NULL },
226 { "SEM-ONLY", NULL },
227 { "SIGN-OPT", NULL },
229 { "UNSIGNED", NULL },
233 const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
236 { "COND-CTI", NULL },
239 { "RELAXABLE", NULL },
240 { "SKIP-CTI", NULL },
241 { "UNCOND-CTI", NULL },
246 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_gr_entries[] =
269 CGEN_KEYWORD fr30_cgen_opval_h_gr =
271 & fr30_cgen_opval_h_gr_entries[0],
275 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_cr_entries[] =
295 CGEN_KEYWORD fr30_cgen_opval_h_cr =
297 & fr30_cgen_opval_h_cr_entries[0],
301 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_dr_entries[] =
311 CGEN_KEYWORD fr30_cgen_opval_h_dr =
313 & fr30_cgen_opval_h_dr_entries[0],
317 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
322 CGEN_KEYWORD fr30_cgen_opval_h_ps =
324 & fr30_cgen_opval_h_ps_entries[0],
328 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
333 CGEN_KEYWORD fr30_cgen_opval_h_r13 =
335 & fr30_cgen_opval_h_r13_entries[0],
339 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
344 CGEN_KEYWORD fr30_cgen_opval_h_r14 =
346 & fr30_cgen_opval_h_r14_entries[0],
350 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
355 CGEN_KEYWORD fr30_cgen_opval_h_r15 =
357 & fr30_cgen_opval_h_r15_entries[0],
362 /* The hardware table. */
364 #define HW_ENT(n) fr30_cgen_hw_entries[n]
365 static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] =
367 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { 0 } } },
368 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
369 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
370 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
371 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
372 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
373 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
374 { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_cr, { 0, 0, { 0 } } },
375 { HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
376 { HW_H_PS, & HW_ENT (HW_H_PS + 1), "h-ps", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
377 { HW_H_R13, & HW_ENT (HW_H_R13 + 1), "h-r13", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, 0, { 0 } } },
378 { HW_H_R14, & HW_ENT (HW_H_R14 + 1), "h-r14", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, 0, { 0 } } },
379 { HW_H_R15, & HW_ENT (HW_H_R15 + 1), "h-r15", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, 0, { 0 } } },
380 { HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
381 { HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
382 { HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
383 { HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
384 { HW_H_IBIT, & HW_ENT (HW_H_IBIT + 1), "h-ibit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
385 { HW_H_SBIT, & HW_ENT (HW_H_SBIT + 1), "h-sbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
389 /* The operand table. */
391 #define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
392 #define OP_ENT(op) fr30_cgen_operand_table[OPERAND (op)]
394 const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
396 /* pc: program counter */
397 { "pc", & HW_ENT (HW_H_PC), 0, 0,
398 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
399 /* Ri: destination register */
400 { "Ri", & HW_ENT (HW_H_GR), 12, 4,
401 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
402 /* Rj: source register */
403 { "Rj", & HW_ENT (HW_H_GR), 8, 4,
404 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
405 /* Ric: target register coproc insn */
406 { "Ric", & HW_ENT (HW_H_GR), 28, 4,
407 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
408 /* Rjc: source register coproc insn */
409 { "Rjc", & HW_ENT (HW_H_GR), 24, 4,
410 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
411 /* CRi: coprocessor register */
412 { "CRi", & HW_ENT (HW_H_CR), 28, 4,
413 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
414 /* CRj: coprocessor register */
415 { "CRj", & HW_ENT (HW_H_CR), 24, 4,
416 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
417 /* Rs1: dedicated register */
418 { "Rs1", & HW_ENT (HW_H_DR), 8, 4,
419 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
420 /* Rs2: dedicated register */
421 { "Rs2", & HW_ENT (HW_H_DR), 12, 4,
422 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
423 /* R13: General Register 13 */
424 { "R13", & HW_ENT (HW_H_R13), 0, 0,
426 /* R14: General Register 14 */
427 { "R14", & HW_ENT (HW_H_R14), 0, 0,
429 /* R15: General Register 15 */
430 { "R15", & HW_ENT (HW_H_R15), 0, 0,
432 /* ps: Program Status register */
433 { "ps", & HW_ENT (HW_H_PS), 0, 0,
435 /* u4: 4 bit unsigned immediate */
436 { "u4", & HW_ENT (HW_H_UINT), 8, 4,
437 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
438 /* u4c: 4 bit unsigned immediate */
439 { "u4c", & HW_ENT (HW_H_UINT), 12, 4,
440 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
441 /* m4: 4 bit negative immediate */
442 { "m4", & HW_ENT (HW_H_UINT), 8, 4,
443 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
444 /* u8: 8 bit unsigned immediate */
445 { "u8", & HW_ENT (HW_H_UINT), 8, 8,
446 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
447 /* i8: 8 bit unsigned immediate */
448 { "i8", & HW_ENT (HW_H_UINT), 4, 8,
449 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
450 /* udisp6: 6 bit unsigned immediate */
451 { "udisp6", & HW_ENT (HW_H_UINT), 8, 4,
452 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
453 /* disp8: 8 bit signed immediate */
454 { "disp8", & HW_ENT (HW_H_SINT), 4, 8,
455 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
456 /* disp9: 9 bit signed immediate */
457 { "disp9", & HW_ENT (HW_H_SINT), 4, 8,
458 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
459 /* disp10: 10 bit signed immediate */
460 { "disp10", & HW_ENT (HW_H_SINT), 4, 8,
461 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
462 /* s10: 10 bit signed immediate */
463 { "s10", & HW_ENT (HW_H_SINT), 8, 8,
464 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
465 /* u10: 10 bit unsigned immediate */
466 { "u10", & HW_ENT (HW_H_UINT), 8, 8,
467 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
468 /* i32: 32 bit immediate */
469 { "i32", & HW_ENT (HW_H_UINT), 16, 32,
470 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
471 /* dir8: 8 bit direct address */
472 { "dir8", & HW_ENT (HW_H_UINT), 8, 8,
473 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
474 /* dir9: 9 bit direct address */
475 { "dir9", & HW_ENT (HW_H_UINT), 8, 8,
476 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
477 /* dir10: 10 bit direct address */
478 { "dir10", & HW_ENT (HW_H_UINT), 8, 8,
479 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
480 /* label9: 9 bit pc relative address */
481 { "label9", & HW_ENT (HW_H_UINT), 8, 8,
482 { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
483 /* label12: 12 bit pc relative address */
484 { "label12", & HW_ENT (HW_H_SINT), 5, 11,
485 { 0, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
486 /* reglist_low: 8 bit register mask */
487 { "reglist_low", & HW_ENT (HW_H_UINT), 8, 8,
488 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
489 /* reglist_hi: 8 bit register mask */
490 { "reglist_hi", & HW_ENT (HW_H_UINT), 8, 8,
491 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
492 /* cc: condition codes */
493 { "cc", & HW_ENT (HW_H_UINT), 4, 4,
494 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
495 /* ccc: coprocessor calc */
496 { "ccc", & HW_ENT (HW_H_UINT), 16, 8,
497 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
498 /* nbit: negative bit */
499 { "nbit", & HW_ENT (HW_H_NBIT), 0, 0,
500 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
501 /* vbit: overflow bit */
502 { "vbit", & HW_ENT (HW_H_VBIT), 0, 0,
503 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
505 { "zbit", & HW_ENT (HW_H_ZBIT), 0, 0,
506 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
507 /* cbit: carry bit */
508 { "cbit", & HW_ENT (HW_H_CBIT), 0, 0,
509 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
510 /* ibit: interrupt bit */
511 { "ibit", & HW_ENT (HW_H_IBIT), 0, 0,
512 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
513 /* sbit: stack bit */
514 { "sbit", & HW_ENT (HW_H_SBIT), 0, 0,
515 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
518 /* Operand references. */
520 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
521 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
522 #define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
524 static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
525 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
526 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
527 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
528 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
529 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
530 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
531 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
535 static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
536 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
537 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
538 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
539 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
540 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
541 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
542 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
546 static const CGEN_OPERAND_INSTANCE fmt_add2_ops[] = {
547 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
548 { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
549 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
550 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
551 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
552 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
553 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
557 static const CGEN_OPERAND_INSTANCE fmt_addc_ops[] = {
558 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
559 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
560 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
561 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
562 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
563 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
564 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
565 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
569 static const CGEN_OPERAND_INSTANCE fmt_addn_ops[] = {
570 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
571 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
572 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
576 static const CGEN_OPERAND_INSTANCE fmt_addni_ops[] = {
577 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
578 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
579 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
583 static const CGEN_OPERAND_INSTANCE fmt_addn2_ops[] = {
584 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
585 { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
586 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
590 static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
591 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
592 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
593 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
594 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
595 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
596 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
600 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
601 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
602 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
603 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
604 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
605 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
606 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
610 static const CGEN_OPERAND_INSTANCE fmt_cmp2_ops[] = {
611 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
612 { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
613 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
614 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
615 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
616 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
620 static const CGEN_OPERAND_INSTANCE fmt_and_ops[] = {
621 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
622 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
623 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
624 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
625 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
629 static const CGEN_OPERAND_INSTANCE fmt_andm_ops[] = {
630 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
631 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
632 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
633 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
634 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
635 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
639 static const CGEN_OPERAND_INSTANCE fmt_andh_ops[] = {
640 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
641 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
642 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RJ), 0, 0 },
643 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
644 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
645 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
649 static const CGEN_OPERAND_INSTANCE fmt_andb_ops[] = {
650 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
651 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
652 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RJ), 0, 0 },
653 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
654 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
655 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
659 static const CGEN_OPERAND_INSTANCE fmt_bandl_ops[] = {
660 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
661 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_QI, & OP_ENT (U4), 0, 0 },
662 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
663 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
667 static const CGEN_OPERAND_INSTANCE fmt_btstl_ops[] = {
668 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_QI, & OP_ENT (U4), 0, 0 },
669 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
670 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
671 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
672 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
676 static const CGEN_OPERAND_INSTANCE fmt_ldi32_ops[] = {
677 { INPUT, "i32", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I32), 0, 0 },
678 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
682 static const CGEN_OPERAND_INSTANCE fmt_mov2dr_ops[] = {
683 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
684 { OUTPUT, "Rs1", & HW_ENT (HW_H_DR), CGEN_MODE_USI, & OP_ENT (RS1), 0, 0 },
688 static const CGEN_OPERAND_INSTANCE fmt_int_ops[] = {
689 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
690 { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (U8), 0, 0 },
691 { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 2, 0 },
692 { OUTPUT, "ibit", & HW_ENT (HW_H_IBIT), CGEN_MODE_BI, 0, 0, 0 },
693 { OUTPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
694 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
698 static const CGEN_OPERAND_INSTANCE fmt_reti_ops[] = {
699 { INPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
700 { INPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 2, COND_REF },
701 { INPUT, "h_memory_reg__VM_h_dr_2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
702 { INPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 3, COND_REF },
703 { INPUT, "h_memory_reg__VM_h_dr_3", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
704 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
705 { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 2, COND_REF },
706 { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, COND_REF },
707 { OUTPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_USI, 0, 3, COND_REF },
711 static const CGEN_OPERAND_INSTANCE fmt_bra_ops[] = {
712 { INPUT, "label9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, 0 },
713 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
721 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
722 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
723 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
725 /* The instruction table.
726 This is currently non-static because the simulator accesses it
729 const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
731 /* Special null first entry.
732 A `num' value of zero is thus invalid.
733 Also, the special `invalid' insn resides here. */
738 FR30_INSN_ADD, "add", "add",
739 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
740 { 16, 16, 0xff00 }, 0xa600,
741 (PTR) & fmt_add_ops[0],
747 FR30_INSN_ADDI, "addi", "add",
748 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
749 { 16, 16, 0xff00 }, 0xa400,
750 (PTR) & fmt_addi_ops[0],
756 FR30_INSN_ADD2, "add2", "add2",
757 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
758 { 16, 16, 0xff00 }, 0xa500,
759 (PTR) & fmt_add2_ops[0],
765 FR30_INSN_ADDC, "addc", "addc",
766 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
767 { 16, 16, 0xff00 }, 0xa700,
768 (PTR) & fmt_addc_ops[0],
774 FR30_INSN_ADDN, "addn", "addn",
775 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
776 { 16, 16, 0xff00 }, 0xa200,
777 (PTR) & fmt_addn_ops[0],
783 FR30_INSN_ADDNI, "addni", "addn",
784 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
785 { 16, 16, 0xff00 }, 0xa000,
786 (PTR) & fmt_addni_ops[0],
792 FR30_INSN_ADDN2, "addn2", "addn2",
793 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
794 { 16, 16, 0xff00 }, 0xa100,
795 (PTR) & fmt_addn2_ops[0],
801 FR30_INSN_SUB, "sub", "sub",
802 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
803 { 16, 16, 0xff00 }, 0xac00,
804 (PTR) & fmt_add_ops[0],
810 FR30_INSN_SUBC, "subc", "subc",
811 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
812 { 16, 16, 0xff00 }, 0xad00,
813 (PTR) & fmt_addc_ops[0],
819 FR30_INSN_SUBN, "subn", "subn",
820 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
821 { 16, 16, 0xff00 }, 0xae00,
822 (PTR) & fmt_addn_ops[0],
828 FR30_INSN_CMP, "cmp", "cmp",
829 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
830 { 16, 16, 0xff00 }, 0xaa00,
831 (PTR) & fmt_cmp_ops[0],
837 FR30_INSN_CMPI, "cmpi", "cmp",
838 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
839 { 16, 16, 0xff00 }, 0xa800,
840 (PTR) & fmt_cmpi_ops[0],
846 FR30_INSN_CMP2, "cmp2", "cmp2",
847 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
848 { 16, 16, 0xff00 }, 0xa900,
849 (PTR) & fmt_cmp2_ops[0],
855 FR30_INSN_AND, "and", "and",
856 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
857 { 16, 16, 0xff00 }, 0x8200,
858 (PTR) & fmt_and_ops[0],
864 FR30_INSN_OR, "or", "or",
865 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
866 { 16, 16, 0xff00 }, 0x9200,
867 (PTR) & fmt_and_ops[0],
873 FR30_INSN_EOR, "eor", "eor",
874 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
875 { 16, 16, 0xff00 }, 0x9a00,
876 (PTR) & fmt_and_ops[0],
882 FR30_INSN_ANDM, "andm", "and",
883 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
884 { 16, 16, 0xff00 }, 0x8400,
885 (PTR) & fmt_andm_ops[0],
891 FR30_INSN_ANDH, "andh", "andh",
892 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
893 { 16, 16, 0xff00 }, 0x8500,
894 (PTR) & fmt_andh_ops[0],
900 FR30_INSN_ANDB, "andb", "andb",
901 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
902 { 16, 16, 0xff00 }, 0x8600,
903 (PTR) & fmt_andb_ops[0],
909 FR30_INSN_ORM, "orm", "or",
910 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
911 { 16, 16, 0xff00 }, 0x9400,
912 (PTR) & fmt_andm_ops[0],
918 FR30_INSN_ORH, "orh", "orh",
919 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
920 { 16, 16, 0xff00 }, 0x9500,
921 (PTR) & fmt_andh_ops[0],
927 FR30_INSN_ORB, "orb", "orb",
928 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
929 { 16, 16, 0xff00 }, 0x9600,
930 (PTR) & fmt_andb_ops[0],
936 FR30_INSN_EORM, "eorm", "eor",
937 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
938 { 16, 16, 0xff00 }, 0x9c00,
939 (PTR) & fmt_andm_ops[0],
945 FR30_INSN_EORH, "eorh", "eorh",
946 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
947 { 16, 16, 0xff00 }, 0x9d00,
948 (PTR) & fmt_andh_ops[0],
954 FR30_INSN_EORB, "eorb", "eorb",
955 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
956 { 16, 16, 0xff00 }, 0x9e00,
957 (PTR) & fmt_andb_ops[0],
963 FR30_INSN_BANDL, "bandl", "bandl",
964 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
965 { 16, 16, 0xff00 }, 0x8000,
966 (PTR) & fmt_bandl_ops[0],
972 FR30_INSN_BORL, "borl", "borl",
973 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
974 { 16, 16, 0xff00 }, 0x9000,
975 (PTR) & fmt_bandl_ops[0],
981 FR30_INSN_BEORL, "beorl", "beorl",
982 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
983 { 16, 16, 0xff00 }, 0x9800,
984 (PTR) & fmt_bandl_ops[0],
990 FR30_INSN_BANDH, "bandh", "bandh",
991 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
992 { 16, 16, 0xff00 }, 0x8100,
993 (PTR) & fmt_bandl_ops[0],
999 FR30_INSN_BORH, "borh", "borh",
1000 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1001 { 16, 16, 0xff00 }, 0x9100,
1002 (PTR) & fmt_bandl_ops[0],
1005 /* beorh $u4,@$Ri */
1008 FR30_INSN_BEORH, "beorh", "beorh",
1009 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1010 { 16, 16, 0xff00 }, 0x9900,
1011 (PTR) & fmt_bandl_ops[0],
1014 /* btstl $u4,@$Ri */
1017 FR30_INSN_BTSTL, "btstl", "btstl",
1018 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1019 { 16, 16, 0xff00 }, 0x8800,
1020 (PTR) & fmt_btstl_ops[0],
1023 /* btsth $u4,@$Ri */
1026 FR30_INSN_BTSTH, "btsth", "btsth",
1027 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1028 { 16, 16, 0xff00 }, 0x8900,
1029 (PTR) & fmt_btstl_ops[0],
1035 FR30_INSN_MUL, "mul", "mul",
1036 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1037 { 16, 16, 0xff00 }, 0xaf00,
1044 FR30_INSN_MULU, "mulu", "mulu",
1045 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1046 { 16, 16, 0xff00 }, 0xab00,
1053 FR30_INSN_MULH, "mulh", "mulh",
1054 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1055 { 16, 16, 0xff00 }, 0xbf00,
1062 FR30_INSN_MULUH, "muluh", "muluh",
1063 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1064 { 16, 16, 0xff00 }, 0xbb00,
1071 FR30_INSN_DIV0S, "div0s", "div0s",
1072 { { MNEM, ' ', OP (RI), 0 } },
1073 { 16, 16, 0xfff0 }, 0x9740,
1080 FR30_INSN_DIV0U, "div0u", "div0u",
1081 { { MNEM, ' ', OP (RI), 0 } },
1082 { 16, 16, 0xfff0 }, 0x9750,
1089 FR30_INSN_DIV1, "div1", "div1",
1090 { { MNEM, ' ', OP (RI), 0 } },
1091 { 16, 16, 0xfff0 }, 0x9760,
1098 FR30_INSN_DIV2, "div2", "div2",
1099 { { MNEM, ' ', OP (RI), 0 } },
1100 { 16, 16, 0xfff0 }, 0x9770,
1107 FR30_INSN_DIV3, "div3", "div3",
1109 { 16, 16, 0xffff }, 0x9f60,
1116 FR30_INSN_DIV4S, "div4s", "div4s",
1118 { 16, 16, 0xffff }, 0x9f70,
1125 FR30_INSN_LSL, "lsl", "lsl",
1126 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1127 { 16, 16, 0xff00 }, 0xb600,
1134 FR30_INSN_LSLI, "lsli", "lsl",
1135 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1136 { 16, 16, 0xff00 }, 0xb400,
1143 FR30_INSN_LSL2, "lsl2", "lsl2",
1144 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1145 { 16, 16, 0xff00 }, 0xb500,
1152 FR30_INSN_LSR, "lsr", "lsr",
1153 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1154 { 16, 16, 0xff00 }, 0xb200,
1161 FR30_INSN_LSRI, "lsri", "lsr",
1162 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1163 { 16, 16, 0xff00 }, 0xb000,
1170 FR30_INSN_LSR2, "lsr2", "lsr2",
1171 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1172 { 16, 16, 0xff00 }, 0xb100,
1179 FR30_INSN_ASR, "asr", "asr",
1180 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1181 { 16, 16, 0xff00 }, 0xba00,
1188 FR30_INSN_ASRI, "asri", "asr",
1189 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1190 { 16, 16, 0xff00 }, 0xb800,
1197 FR30_INSN_ASR2, "asr2", "asr2",
1198 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1199 { 16, 16, 0xff00 }, 0xb900,
1206 FR30_INSN_LDI_8, "ldi:8", "ldi:8",
1207 { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
1208 { 16, 16, 0xf000 }, 0xc000,
1212 /* ldi:32 $i32,$Ri */
1215 FR30_INSN_LDI32, "ldi32", "ldi:32",
1216 { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
1217 { 16, 48, 0xfff0 }, 0x9f80,
1218 (PTR) & fmt_ldi32_ops[0],
1224 FR30_INSN_LD, "ld", "ld",
1225 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1226 { 16, 16, 0xff00 }, 0x400,
1233 FR30_INSN_LDUH, "lduh", "lduh",
1234 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1235 { 16, 16, 0xff00 }, 0x500,
1242 FR30_INSN_LDUB, "ldub", "ldub",
1243 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1244 { 16, 16, 0xff00 }, 0x600,
1248 /* ld @($R13,$Rj),$Ri */
1251 FR30_INSN_LDR13, "ldr13", "ld",
1252 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1253 { 16, 16, 0xff00 }, 0x0,
1257 /* lduh @($R13,$Rj),$Ri */
1260 FR30_INSN_LDR13UH, "ldr13uh", "lduh",
1261 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1262 { 16, 16, 0xff00 }, 0x100,
1266 /* ldub @($R13,$Rj),$Ri */
1269 FR30_INSN_LDR13UB, "ldr13ub", "ldub",
1270 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1271 { 16, 16, 0xff00 }, 0x200,
1275 /* ld @($R14,$disp10),$Ri */
1278 FR30_INSN_LDR14, "ldr14", "ld",
1279 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP10), ')', ',', OP (RI), 0 } },
1280 { 16, 16, 0xf000 }, 0x2000,
1284 /* lduh @($R14,$disp9),$Ri */
1287 FR30_INSN_LDR14UH, "ldr14uh", "lduh",
1288 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP9), ')', ',', OP (RI), 0 } },
1289 { 16, 16, 0xf000 }, 0x4000,
1293 /* ldub @($R14,$disp8),$Ri */
1296 FR30_INSN_LDR14UB, "ldr14ub", "ldub",
1297 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP8), ')', ',', OP (RI), 0 } },
1298 { 16, 16, 0xf000 }, 0x6000,
1302 /* ld @($R15,$udisp6),$Ri */
1305 FR30_INSN_LDR15, "ldr15", "ld",
1306 { { MNEM, ' ', '@', '(', OP (R15), ',', OP (UDISP6), ')', ',', OP (RI), 0 } },
1307 { 16, 16, 0xff00 }, 0x300,
1314 FR30_INSN_LDR15GR, "ldr15gr", "ld",
1315 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RI), 0 } },
1316 { 16, 16, 0xfff0 }, 0x700,
1320 /* ld @$R15+,$Rs2 */
1323 FR30_INSN_LDR15DR, "ldr15dr", "ld",
1324 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RS2), 0 } },
1325 { 16, 16, 0xfff0 }, 0x780,
1332 FR30_INSN_LDR15PS, "ldr15ps", "ld",
1333 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (PS), 0 } },
1334 { 16, 16, 0xffff }, 0x790,
1341 FR30_INSN_ST, "st", "st",
1342 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1343 { 16, 16, 0xff00 }, 0x1400,
1350 FR30_INSN_STH, "sth", "sth",
1351 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1352 { 16, 16, 0xff00 }, 0x1500,
1359 FR30_INSN_STB, "stb", "stb",
1360 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1361 { 16, 16, 0xff00 }, 0x1600,
1365 /* st $Ri,@($R13,$Rj) */
1368 FR30_INSN_STR13, "str13", "st",
1369 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1370 { 16, 16, 0xff00 }, 0x1000,
1374 /* sth $Ri,@($R13,$Rj) */
1377 FR30_INSN_STR13H, "str13h", "sth",
1378 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1379 { 16, 16, 0xff00 }, 0x1100,
1383 /* stb $Ri,@($R13,$Rj) */
1386 FR30_INSN_STR13B, "stR13b", "stb",
1387 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1388 { 16, 16, 0xff00 }, 0x1200,
1392 /* st $Ri,@($R14,$disp10) */
1395 FR30_INSN_STR14, "str14", "st",
1396 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP10), ')', 0 } },
1397 { 16, 16, 0xf000 }, 0x3000,
1401 /* sth $Ri,@($R14,$disp9) */
1404 FR30_INSN_STR14H, "str14h", "sth",
1405 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP9), ')', 0 } },
1406 { 16, 16, 0xf000 }, 0x5000,
1410 /* stb $Ri,@($R14,$disp8) */
1413 FR30_INSN_STR14B, "str14b", "stb",
1414 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP8), ')', 0 } },
1415 { 16, 16, 0xf000 }, 0x7000,
1419 /* st $Ri,@($R15,$udisp6) */
1422 FR30_INSN_STR15, "str15", "st",
1423 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R15), ',', OP (UDISP6), ')', 0 } },
1424 { 16, 16, 0xff00 }, 0x1300,
1431 FR30_INSN_STR15GR, "str15gr", "st",
1432 { { MNEM, ' ', OP (RI), ',', '@', '-', OP (R15), 0 } },
1433 { 16, 16, 0xfff0 }, 0x1700,
1437 /* st $Rs2,@-$R15 */
1440 FR30_INSN_STR15DR, "str15dr", "st",
1441 { { MNEM, ' ', OP (RS2), ',', '@', '-', OP (R15), 0 } },
1442 { 16, 16, 0xfff0 }, 0x1780,
1449 FR30_INSN_STR15PS, "str15ps", "st",
1450 { { MNEM, ' ', OP (PS), ',', '@', '-', OP (R15), 0 } },
1451 { 16, 16, 0xffff }, 0x1790,
1458 FR30_INSN_MOV, "mov", "mov",
1459 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1460 { 16, 16, 0xff00 }, 0x8b00,
1467 FR30_INSN_MOVDR, "movdr", "mov",
1468 { { MNEM, ' ', OP (RS1), ',', OP (RI), 0 } },
1469 { 16, 16, 0xff00 }, 0xb700,
1476 FR30_INSN_MOVPS, "movps", "mov",
1477 { { MNEM, ' ', OP (PS), ',', OP (RI), 0 } },
1478 { 16, 16, 0xfff0 }, 0x1710,
1485 FR30_INSN_MOV2DR, "mov2dr", "mov",
1486 { { MNEM, ' ', OP (RI), ',', OP (RS1), 0 } },
1487 { 16, 16, 0xff00 }, 0xb300,
1488 (PTR) & fmt_mov2dr_ops[0],
1494 FR30_INSN_MOV2PS, "mov2ps", "mov",
1495 { { MNEM, ' ', OP (RI), ',', OP (PS), 0 } },
1496 { 16, 16, 0xfff0 }, 0x710,
1503 FR30_INSN_JMP, "jmp", "jmp",
1504 { { MNEM, ' ', '@', OP (RI), 0 } },
1505 { 16, 16, 0xfff0 }, 0x9700,
1512 FR30_INSN_JMPD, "jmpd", "jmp:D",
1513 { { MNEM, ' ', '@', OP (RI), 0 } },
1514 { 16, 16, 0xfff0 }, 0x9f00,
1521 FR30_INSN_CALLR, "callr", "call",
1522 { { MNEM, ' ', '@', OP (RI), 0 } },
1523 { 16, 16, 0xfff0 }, 0x9710,
1530 FR30_INSN_CALLRD, "callrd", "call:D",
1531 { { MNEM, ' ', '@', OP (RI), 0 } },
1532 { 16, 16, 0xfff0 }, 0x9f10,
1539 FR30_INSN_CALL, "call", "call",
1540 { { MNEM, ' ', OP (LABEL12), 0 } },
1541 { 16, 16, 0xf400 }, 0xd000,
1545 /* call:D $label12 */
1548 FR30_INSN_CALLD, "calld", "call:D",
1549 { { MNEM, ' ', OP (LABEL12), 0 } },
1550 { 16, 16, 0xf400 }, 0xd400,
1557 FR30_INSN_RET, "ret", "ret",
1559 { 16, 16, 0xffff }, 0x9720,
1566 FR30_INSN_RETD, "retd", "ret:D",
1568 { 16, 16, 0xffff }, 0x9f20,
1575 FR30_INSN_INT, "int", "int",
1576 { { MNEM, ' ', OP (U8), 0 } },
1577 { 16, 16, 0xff00 }, 0x1f00,
1578 (PTR) & fmt_int_ops[0],
1579 { 0, 0|A(UNCOND_CTI), { 0 } }
1584 FR30_INSN_INTE, "inte", "inte",
1586 { 16, 16, 0xffff }, 0x9f30,
1593 FR30_INSN_RETI, "reti", "reti",
1595 { 16, 16, 0xffff }, 0x9730,
1596 (PTR) & fmt_reti_ops[0],
1597 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
1602 FR30_INSN_BRA, "bra", "bra",
1603 { { MNEM, ' ', OP (LABEL9), 0 } },
1604 { 16, 16, 0xff00 }, 0xe000,
1605 (PTR) & fmt_bra_ops[0],
1606 { 0, 0|A(UNCOND_CTI), { 0 } }
1611 FR30_INSN_BNO, "bno", "bno",
1612 { { MNEM, ' ', OP (LABEL9), 0 } },
1613 { 16, 16, 0xff00 }, 0xe100,
1614 (PTR) & fmt_bra_ops[0],
1615 { 0, 0|A(UNCOND_CTI), { 0 } }
1620 FR30_INSN_BEQ, "beq", "beq",
1621 { { MNEM, ' ', OP (LABEL9), 0 } },
1622 { 16, 16, 0xff00 }, 0xe200,
1623 (PTR) & fmt_bra_ops[0],
1624 { 0, 0|A(UNCOND_CTI), { 0 } }
1629 FR30_INSN_BNE, "bne", "bne",
1630 { { MNEM, ' ', OP (LABEL9), 0 } },
1631 { 16, 16, 0xff00 }, 0xe300,
1632 (PTR) & fmt_bra_ops[0],
1633 { 0, 0|A(UNCOND_CTI), { 0 } }
1638 FR30_INSN_BC, "bc", "bc",
1639 { { MNEM, ' ', OP (LABEL9), 0 } },
1640 { 16, 16, 0xff00 }, 0xe400,
1641 (PTR) & fmt_bra_ops[0],
1642 { 0, 0|A(UNCOND_CTI), { 0 } }
1647 FR30_INSN_BNC, "bnc", "bnc",
1648 { { MNEM, ' ', OP (LABEL9), 0 } },
1649 { 16, 16, 0xff00 }, 0xe500,
1650 (PTR) & fmt_bra_ops[0],
1651 { 0, 0|A(UNCOND_CTI), { 0 } }
1656 FR30_INSN_BN, "bn", "bn",
1657 { { MNEM, ' ', OP (LABEL9), 0 } },
1658 { 16, 16, 0xff00 }, 0xe600,
1659 (PTR) & fmt_bra_ops[0],
1660 { 0, 0|A(UNCOND_CTI), { 0 } }
1665 FR30_INSN_BP, "bp", "bp",
1666 { { MNEM, ' ', OP (LABEL9), 0 } },
1667 { 16, 16, 0xff00 }, 0xe700,
1668 (PTR) & fmt_bra_ops[0],
1669 { 0, 0|A(UNCOND_CTI), { 0 } }
1674 FR30_INSN_BV, "bv", "bv",
1675 { { MNEM, ' ', OP (LABEL9), 0 } },
1676 { 16, 16, 0xff00 }, 0xe800,
1677 (PTR) & fmt_bra_ops[0],
1678 { 0, 0|A(UNCOND_CTI), { 0 } }
1683 FR30_INSN_BNV, "bnv", "bnv",
1684 { { MNEM, ' ', OP (LABEL9), 0 } },
1685 { 16, 16, 0xff00 }, 0xe900,
1686 (PTR) & fmt_bra_ops[0],
1687 { 0, 0|A(UNCOND_CTI), { 0 } }
1692 FR30_INSN_BLT, "blt", "blt",
1693 { { MNEM, ' ', OP (LABEL9), 0 } },
1694 { 16, 16, 0xff00 }, 0xea00,
1695 (PTR) & fmt_bra_ops[0],
1696 { 0, 0|A(UNCOND_CTI), { 0 } }
1701 FR30_INSN_BGE, "bge", "bge",
1702 { { MNEM, ' ', OP (LABEL9), 0 } },
1703 { 16, 16, 0xff00 }, 0xeb00,
1704 (PTR) & fmt_bra_ops[0],
1705 { 0, 0|A(UNCOND_CTI), { 0 } }
1710 FR30_INSN_BLE, "ble", "ble",
1711 { { MNEM, ' ', OP (LABEL9), 0 } },
1712 { 16, 16, 0xff00 }, 0xec00,
1713 (PTR) & fmt_bra_ops[0],
1714 { 0, 0|A(UNCOND_CTI), { 0 } }
1719 FR30_INSN_BGT, "bgt", "bgt",
1720 { { MNEM, ' ', OP (LABEL9), 0 } },
1721 { 16, 16, 0xff00 }, 0xed00,
1722 (PTR) & fmt_bra_ops[0],
1723 { 0, 0|A(UNCOND_CTI), { 0 } }
1728 FR30_INSN_BLS, "bls", "bls",
1729 { { MNEM, ' ', OP (LABEL9), 0 } },
1730 { 16, 16, 0xff00 }, 0xee00,
1731 (PTR) & fmt_bra_ops[0],
1732 { 0, 0|A(UNCOND_CTI), { 0 } }
1737 FR30_INSN_BHI, "bhi", "bhi",
1738 { { MNEM, ' ', OP (LABEL9), 0 } },
1739 { 16, 16, 0xff00 }, 0xef00,
1740 (PTR) & fmt_bra_ops[0],
1741 { 0, 0|A(UNCOND_CTI), { 0 } }
1746 FR30_INSN_BRAD, "brad", "bra:D",
1747 { { MNEM, ' ', OP (LABEL9), 0 } },
1748 { 16, 16, 0xff00 }, 0xf000,
1749 (PTR) & fmt_bra_ops[0],
1750 { 0, 0|A(UNCOND_CTI), { 0 } }
1755 FR30_INSN_BNOD, "bnod", "bno:D",
1756 { { MNEM, ' ', OP (LABEL9), 0 } },
1757 { 16, 16, 0xff00 }, 0xf100,
1758 (PTR) & fmt_bra_ops[0],
1759 { 0, 0|A(UNCOND_CTI), { 0 } }
1764 FR30_INSN_BEQD, "beqd", "beq:D",
1765 { { MNEM, ' ', OP (LABEL9), 0 } },
1766 { 16, 16, 0xff00 }, 0xf200,
1767 (PTR) & fmt_bra_ops[0],
1768 { 0, 0|A(UNCOND_CTI), { 0 } }
1773 FR30_INSN_BNED, "bned", "bne:D",
1774 { { MNEM, ' ', OP (LABEL9), 0 } },
1775 { 16, 16, 0xff00 }, 0xf300,
1776 (PTR) & fmt_bra_ops[0],
1777 { 0, 0|A(UNCOND_CTI), { 0 } }
1782 FR30_INSN_BCD, "bcd", "bc:D",
1783 { { MNEM, ' ', OP (LABEL9), 0 } },
1784 { 16, 16, 0xff00 }, 0xf400,
1785 (PTR) & fmt_bra_ops[0],
1786 { 0, 0|A(UNCOND_CTI), { 0 } }
1791 FR30_INSN_BNCD, "bncd", "bnc:D",
1792 { { MNEM, ' ', OP (LABEL9), 0 } },
1793 { 16, 16, 0xff00 }, 0xf500,
1794 (PTR) & fmt_bra_ops[0],
1795 { 0, 0|A(UNCOND_CTI), { 0 } }
1800 FR30_INSN_BND, "bnd", "bn:D",
1801 { { MNEM, ' ', OP (LABEL9), 0 } },
1802 { 16, 16, 0xff00 }, 0xf600,
1803 (PTR) & fmt_bra_ops[0],
1804 { 0, 0|A(UNCOND_CTI), { 0 } }
1809 FR30_INSN_BPD, "bpd", "bp:D",
1810 { { MNEM, ' ', OP (LABEL9), 0 } },
1811 { 16, 16, 0xff00 }, 0xf700,
1812 (PTR) & fmt_bra_ops[0],
1813 { 0, 0|A(UNCOND_CTI), { 0 } }
1818 FR30_INSN_BVD, "bvd", "bv:D",
1819 { { MNEM, ' ', OP (LABEL9), 0 } },
1820 { 16, 16, 0xff00 }, 0xf800,
1821 (PTR) & fmt_bra_ops[0],
1822 { 0, 0|A(UNCOND_CTI), { 0 } }
1827 FR30_INSN_BNVD, "bnvd", "bnv:D",
1828 { { MNEM, ' ', OP (LABEL9), 0 } },
1829 { 16, 16, 0xff00 }, 0xf900,
1830 (PTR) & fmt_bra_ops[0],
1831 { 0, 0|A(UNCOND_CTI), { 0 } }
1836 FR30_INSN_BLTD, "bltd", "blt:D",
1837 { { MNEM, ' ', OP (LABEL9), 0 } },
1838 { 16, 16, 0xff00 }, 0xfa00,
1839 (PTR) & fmt_bra_ops[0],
1840 { 0, 0|A(UNCOND_CTI), { 0 } }
1845 FR30_INSN_BGED, "bged", "bge:D",
1846 { { MNEM, ' ', OP (LABEL9), 0 } },
1847 { 16, 16, 0xff00 }, 0xfb00,
1848 (PTR) & fmt_bra_ops[0],
1849 { 0, 0|A(UNCOND_CTI), { 0 } }
1854 FR30_INSN_BLED, "bled", "ble:D",
1855 { { MNEM, ' ', OP (LABEL9), 0 } },
1856 { 16, 16, 0xff00 }, 0xfc00,
1857 (PTR) & fmt_bra_ops[0],
1858 { 0, 0|A(UNCOND_CTI), { 0 } }
1863 FR30_INSN_BGTD, "bgtd", "bgt:D",
1864 { { MNEM, ' ', OP (LABEL9), 0 } },
1865 { 16, 16, 0xff00 }, 0xfd00,
1866 (PTR) & fmt_bra_ops[0],
1867 { 0, 0|A(UNCOND_CTI), { 0 } }
1872 FR30_INSN_BLSD, "blsd", "bls:D",
1873 { { MNEM, ' ', OP (LABEL9), 0 } },
1874 { 16, 16, 0xff00 }, 0xfe00,
1875 (PTR) & fmt_bra_ops[0],
1876 { 0, 0|A(UNCOND_CTI), { 0 } }
1881 FR30_INSN_BHID, "bhid", "bhi:D",
1882 { { MNEM, ' ', OP (LABEL9), 0 } },
1883 { 16, 16, 0xff00 }, 0xff00,
1884 (PTR) & fmt_bra_ops[0],
1885 { 0, 0|A(UNCOND_CTI), { 0 } }
1887 /* dmov $R13,@$dir10 */
1890 FR30_INSN_DMOVR13, "dmovr13", "dmov",
1891 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR10), 0 } },
1892 { 16, 16, 0xff00 }, 0x1800,
1896 /* dmovh $R13,@$dir9 */
1899 FR30_INSN_DMOVR13H, "dmovr13h", "dmovh",
1900 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR9), 0 } },
1901 { 16, 16, 0xff00 }, 0x1900,
1905 /* dmovb $R13,@$dir8 */
1908 FR30_INSN_DMOVR13B, "dmovr13b", "dmovb",
1909 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR8), 0 } },
1910 { 16, 16, 0xff00 }, 0x1a00,
1914 /* dmov @$R13+,@$dir10 */
1917 FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov",
1918 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR10), 0 } },
1919 { 16, 16, 0xff00 }, 0x1c00,
1923 /* dmovh @$R13+,@$dir9 */
1926 FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh",
1927 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR9), 0 } },
1928 { 16, 16, 0xff00 }, 0x1d00,
1932 /* dmovb @$R13+,@$dir8 */
1935 FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb",
1936 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR8), 0 } },
1937 { 16, 16, 0xff00 }, 0x1e00,
1941 /* dmov @$R15+,@$dir10 */
1944 FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov",
1945 { { MNEM, ' ', '@', OP (R15), '+', ',', '@', OP (DIR10), 0 } },
1946 { 16, 16, 0xff00 }, 0x1b00,
1950 /* dmov @$dir10,$R13 */
1953 FR30_INSN_DMOV2R13, "dmov2r13", "dmov",
1954 { { MNEM, ' ', '@', OP (DIR10), ',', OP (R13), 0 } },
1955 { 16, 16, 0xff00 }, 0x800,
1959 /* dmovh @$dir9,$R13 */
1962 FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh",
1963 { { MNEM, ' ', '@', OP (DIR9), ',', OP (R13), 0 } },
1964 { 16, 16, 0xff00 }, 0x900,
1968 /* dmovb @$dir8,$R13 */
1971 FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb",
1972 { { MNEM, ' ', '@', OP (DIR8), ',', OP (R13), 0 } },
1973 { 16, 16, 0xff00 }, 0xa00,
1977 /* dmov @$dir10,@$R13+ */
1980 FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov",
1981 { { MNEM, ' ', '@', OP (DIR10), ',', '@', OP (R13), '+', 0 } },
1982 { 16, 16, 0xff00 }, 0xc00,
1986 /* dmovh @$dir9,@$R13+ */
1989 FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh",
1990 { { MNEM, ' ', '@', OP (DIR9), ',', '@', OP (R13), '+', 0 } },
1991 { 16, 16, 0xff00 }, 0xd00,
1995 /* dmovb @$dir8,@$R13+ */
1998 FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb",
1999 { { MNEM, ' ', '@', OP (DIR8), ',', '@', OP (R13), '+', 0 } },
2000 { 16, 16, 0xff00 }, 0xe00,
2004 /* dmov @$dir10,@-$R15 */
2007 FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov",
2008 { { MNEM, ' ', '@', OP (DIR10), ',', '@', '-', OP (R15), 0 } },
2009 { 16, 16, 0xff00 }, 0xb00,
2013 /* ldres @$Ri+,$u4 */
2016 FR30_INSN_LDRES, "ldres", "ldres",
2017 { { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } },
2018 { 16, 16, 0xff00 }, 0xbc00,
2022 /* stres $u4,@$Ri+ */
2025 FR30_INSN_STRES, "stres", "stres",
2026 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } },
2027 { 16, 16, 0xff00 }, 0xbd00,
2031 /* copop $u4c,$ccc,$CRj,$CRi */
2034 FR30_INSN_COPOP, "copop", "copop",
2035 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (CRI), 0 } },
2036 { 16, 32, 0xfff0 }, 0x9fc0,
2040 /* copld $u4c,$ccc,$Rjc,$CRi */
2043 FR30_INSN_COPLD, "copld", "copld",
2044 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (RJC), ',', OP (CRI), 0 } },
2045 { 16, 32, 0xfff0 }, 0x9fd0,
2049 /* copst $u4c,$ccc,$CRj,$Ric */
2052 FR30_INSN_COPST, "copst", "copst",
2053 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
2054 { 16, 32, 0xfff0 }, 0x9fe0,
2058 /* copsv $u4c,$ccc,$CRj,$Ric */
2061 FR30_INSN_COPSV, "copsv", "copsv",
2062 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
2063 { 16, 32, 0xfff0 }, 0x9ff0,
2070 FR30_INSN_NOP, "nop", "nop",
2072 { 16, 16, 0xffff }, 0x9fa0,
2079 FR30_INSN_ANDCCR, "andccr", "andccr",
2080 { { MNEM, ' ', OP (U8), 0 } },
2081 { 16, 16, 0xff00 }, 0x8300,
2088 FR30_INSN_ORCCR, "orccr", "orccr",
2089 { { MNEM, ' ', OP (U8), 0 } },
2090 { 16, 16, 0xff00 }, 0x9300,
2097 FR30_INSN_STILM, "stilm", "stilm",
2098 { { MNEM, ' ', OP (U8), 0 } },
2099 { 16, 16, 0xff00 }, 0x8700,
2106 FR30_INSN_ADDSP, "addsp", "addsp",
2107 { { MNEM, ' ', OP (S10), 0 } },
2108 { 16, 16, 0xff00 }, 0xa300,
2115 FR30_INSN_EXTSB, "extsb", "extsb",
2116 { { MNEM, ' ', OP (RI), 0 } },
2117 { 16, 16, 0xfff0 }, 0x9780,
2124 FR30_INSN_EXTUB, "extub", "extub",
2125 { { MNEM, ' ', OP (RI), 0 } },
2126 { 16, 16, 0xfff0 }, 0x9790,
2133 FR30_INSN_EXTSH, "extsh", "extsh",
2134 { { MNEM, ' ', OP (RI), 0 } },
2135 { 16, 16, 0xfff0 }, 0x97a0,
2142 FR30_INSN_EXTUH, "extuh", "extuh",
2143 { { MNEM, ' ', OP (RI), 0 } },
2144 { 16, 16, 0xfff0 }, 0x97b0,
2148 /* ldm0 ($reglist_low) */
2151 FR30_INSN_LDM0, "ldm0", "ldm0",
2152 { { MNEM, ' ', '(', OP (REGLIST_LOW), ')', 0 } },
2153 { 16, 16, 0xff00 }, 0x8c00,
2157 /* ldm1 ($reglist_hi) */
2160 FR30_INSN_LDM1, "ldm1", "ldm1",
2161 { { MNEM, ' ', '(', OP (REGLIST_HI), ')', 0 } },
2162 { 16, 16, 0xff00 }, 0x8d00,
2166 /* stm0 ($reglist_low) */
2169 FR30_INSN_STM0, "stm0", "stm0",
2170 { { MNEM, ' ', '(', OP (REGLIST_LOW), ')', 0 } },
2171 { 16, 16, 0xff00 }, 0x8e00,
2175 /* stm1 ($reglist_hi) */
2178 FR30_INSN_STM1, "stm1", "stm1",
2179 { { MNEM, ' ', '(', OP (REGLIST_HI), ')', 0 } },
2180 { 16, 16, 0xff00 }, 0x8f00,
2187 FR30_INSN_ENTER, "enter", "enter",
2188 { { MNEM, ' ', OP (U10), 0 } },
2189 { 16, 16, 0xff00 }, 0xf00,
2196 FR30_INSN_LEAVE, "leave", "leave",
2198 { 16, 16, 0xffff }, 0x9f90,
2205 FR30_INSN_XCHB, "xchb", "xchb",
2206 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2207 { 16, 16, 0xff00 }, 0x8a00,
2217 static const CGEN_INSN_TABLE insn_table =
2219 & fr30_cgen_insn_table_entries[0],
2225 /* Each non-simple macro entry points to an array of expansion possibilities. */
2227 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2228 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2229 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2231 /* The macro instruction table. */
2233 static const CGEN_INSN macro_insn_table_entries[] =
2235 /* ldi32 $i32,$Ri */
2238 -1, "ldi32m", "ldi32",
2239 { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
2240 { 16, 48, 0xfff0 }, 0x9f80,
2242 { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
2250 static const CGEN_INSN_TABLE macro_insn_table =
2252 & macro_insn_table_entries[0],
2254 (sizeof (macro_insn_table_entries) /
2255 sizeof (macro_insn_table_entries[0])),
2264 /* Return non-zero if INSN is to be added to the hash table.
2265 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
2268 asm_hash_insn_p (insn)
2269 const CGEN_INSN * insn;
2271 return CGEN_ASM_HASH_P (insn);
2275 dis_hash_insn_p (insn)
2276 const CGEN_INSN * insn;
2278 /* If building the hash table and the NO-DIS attribute is present,
2280 if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
2282 return CGEN_DIS_HASH_P (insn);
2285 /* The result is the hash value of the insn.
2286 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
2289 asm_hash_insn (mnem)
2292 return CGEN_ASM_HASH (mnem);
2295 /* BUF is a pointer to the insn's bytes in target order.
2296 VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
2300 dis_hash_insn (buf, value)
2302 CGEN_INSN_INT value;
2304 return CGEN_DIS_HASH (buf, value);
2307 /* Initialize an opcode table and return a descriptor.
2308 It's much like opening a file, and must be the first function called. */
2311 fr30_cgen_opcode_open (mach, endian)
2313 enum cgen_endian endian;
2315 CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
2324 memset (table, 0, sizeof (*table));
2326 CGEN_OPCODE_MACH (table) = mach;
2327 CGEN_OPCODE_ENDIAN (table) = endian;
2328 /* FIXME: for the sparc case we can determine insn-endianness statically.
2329 The worry here is where both data and insn endian can be independently
2330 chosen, in which case this function will need another argument.
2331 Actually, will want to allow for more arguments in the future anyway. */
2332 CGEN_OPCODE_INSN_ENDIAN (table) = endian;
2334 CGEN_OPCODE_HW_LIST (table) = & fr30_cgen_hw_entries[0];
2336 CGEN_OPCODE_OPERAND_TABLE (table) = & fr30_cgen_operand_table[0];
2338 * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
2340 * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
2342 CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
2343 CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
2344 CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
2346 CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
2347 CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
2348 CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
2350 return (CGEN_OPCODE_DESC) table;
2353 /* Close an opcode table. */
2356 fr30_cgen_opcode_close (desc)
2357 CGEN_OPCODE_DESC desc;
2362 /* Getting values from cgen_fields is handled by a collection of functions.
2363 They are distinguished by the type of the VALUE argument they return.
2364 TODO: floating point, inlining support, remove cases where result type
2368 fr30_cgen_get_int_operand (opindex, fields)
2370 const CGEN_FIELDS * fields;
2376 case FR30_OPERAND_RI :
2377 value = fields->f_Ri;
2379 case FR30_OPERAND_RJ :
2380 value = fields->f_Rj;
2382 case FR30_OPERAND_RIC :
2383 value = fields->f_Ric;
2385 case FR30_OPERAND_RJC :
2386 value = fields->f_Rjc;
2388 case FR30_OPERAND_CRI :
2389 value = fields->f_CRi;
2391 case FR30_OPERAND_CRJ :
2392 value = fields->f_CRj;
2394 case FR30_OPERAND_RS1 :
2395 value = fields->f_Rs1;
2397 case FR30_OPERAND_RS2 :
2398 value = fields->f_Rs2;
2400 case FR30_OPERAND_R13 :
2401 value = fields->f_nil;
2403 case FR30_OPERAND_R14 :
2404 value = fields->f_nil;
2406 case FR30_OPERAND_R15 :
2407 value = fields->f_nil;
2409 case FR30_OPERAND_PS :
2410 value = fields->f_nil;
2412 case FR30_OPERAND_U4 :
2413 value = fields->f_u4;
2415 case FR30_OPERAND_U4C :
2416 value = fields->f_u4c;
2418 case FR30_OPERAND_M4 :
2419 value = fields->f_m4;
2421 case FR30_OPERAND_U8 :
2422 value = fields->f_u8;
2424 case FR30_OPERAND_I8 :
2425 value = fields->f_i8;
2427 case FR30_OPERAND_UDISP6 :
2428 value = fields->f_udisp6;
2430 case FR30_OPERAND_DISP8 :
2431 value = fields->f_disp8;
2433 case FR30_OPERAND_DISP9 :
2434 value = fields->f_disp9;
2436 case FR30_OPERAND_DISP10 :
2437 value = fields->f_disp10;
2439 case FR30_OPERAND_S10 :
2440 value = fields->f_s10;
2442 case FR30_OPERAND_U10 :
2443 value = fields->f_u10;
2445 case FR30_OPERAND_I32 :
2446 value = fields->f_i32;
2448 case FR30_OPERAND_DIR8 :
2449 value = fields->f_dir8;
2451 case FR30_OPERAND_DIR9 :
2452 value = fields->f_dir9;
2454 case FR30_OPERAND_DIR10 :
2455 value = fields->f_dir10;
2457 case FR30_OPERAND_LABEL9 :
2458 value = fields->f_rel9;
2460 case FR30_OPERAND_LABEL12 :
2461 value = fields->f_rel12;
2463 case FR30_OPERAND_REGLIST_LOW :
2464 value = fields->f_reglist_low;
2466 case FR30_OPERAND_REGLIST_HI :
2467 value = fields->f_reglist_hi;
2469 case FR30_OPERAND_CC :
2470 value = fields->f_cc;
2472 case FR30_OPERAND_CCC :
2473 value = fields->f_ccc;
2477 /* xgettext:c-format */
2478 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
2487 fr30_cgen_get_vma_operand (opindex, fields)
2489 const CGEN_FIELDS * fields;
2495 case FR30_OPERAND_RI :
2496 value = fields->f_Ri;
2498 case FR30_OPERAND_RJ :
2499 value = fields->f_Rj;
2501 case FR30_OPERAND_RIC :
2502 value = fields->f_Ric;
2504 case FR30_OPERAND_RJC :
2505 value = fields->f_Rjc;
2507 case FR30_OPERAND_CRI :
2508 value = fields->f_CRi;
2510 case FR30_OPERAND_CRJ :
2511 value = fields->f_CRj;
2513 case FR30_OPERAND_RS1 :
2514 value = fields->f_Rs1;
2516 case FR30_OPERAND_RS2 :
2517 value = fields->f_Rs2;
2519 case FR30_OPERAND_R13 :
2520 value = fields->f_nil;
2522 case FR30_OPERAND_R14 :
2523 value = fields->f_nil;
2525 case FR30_OPERAND_R15 :
2526 value = fields->f_nil;
2528 case FR30_OPERAND_PS :
2529 value = fields->f_nil;
2531 case FR30_OPERAND_U4 :
2532 value = fields->f_u4;
2534 case FR30_OPERAND_U4C :
2535 value = fields->f_u4c;
2537 case FR30_OPERAND_M4 :
2538 value = fields->f_m4;
2540 case FR30_OPERAND_U8 :
2541 value = fields->f_u8;
2543 case FR30_OPERAND_I8 :
2544 value = fields->f_i8;
2546 case FR30_OPERAND_UDISP6 :
2547 value = fields->f_udisp6;
2549 case FR30_OPERAND_DISP8 :
2550 value = fields->f_disp8;
2552 case FR30_OPERAND_DISP9 :
2553 value = fields->f_disp9;
2555 case FR30_OPERAND_DISP10 :
2556 value = fields->f_disp10;
2558 case FR30_OPERAND_S10 :
2559 value = fields->f_s10;
2561 case FR30_OPERAND_U10 :
2562 value = fields->f_u10;
2564 case FR30_OPERAND_I32 :
2565 value = fields->f_i32;
2567 case FR30_OPERAND_DIR8 :
2568 value = fields->f_dir8;
2570 case FR30_OPERAND_DIR9 :
2571 value = fields->f_dir9;
2573 case FR30_OPERAND_DIR10 :
2574 value = fields->f_dir10;
2576 case FR30_OPERAND_LABEL9 :
2577 value = fields->f_rel9;
2579 case FR30_OPERAND_LABEL12 :
2580 value = fields->f_rel12;
2582 case FR30_OPERAND_REGLIST_LOW :
2583 value = fields->f_reglist_low;
2585 case FR30_OPERAND_REGLIST_HI :
2586 value = fields->f_reglist_hi;
2588 case FR30_OPERAND_CC :
2589 value = fields->f_cc;
2591 case FR30_OPERAND_CCC :
2592 value = fields->f_ccc;
2596 /* xgettext:c-format */
2597 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
2605 /* Stuffing values in cgen_fields is handled by a collection of functions.
2606 They are distinguished by the type of the VALUE argument they accept.
2607 TODO: floating point, inlining support, remove cases where argument type
2611 fr30_cgen_set_int_operand (opindex, fields, value)
2613 CGEN_FIELDS * fields;
2618 case FR30_OPERAND_RI :
2619 fields->f_Ri = value;
2621 case FR30_OPERAND_RJ :
2622 fields->f_Rj = value;
2624 case FR30_OPERAND_RIC :
2625 fields->f_Ric = value;
2627 case FR30_OPERAND_RJC :
2628 fields->f_Rjc = value;
2630 case FR30_OPERAND_CRI :
2631 fields->f_CRi = value;
2633 case FR30_OPERAND_CRJ :
2634 fields->f_CRj = value;
2636 case FR30_OPERAND_RS1 :
2637 fields->f_Rs1 = value;
2639 case FR30_OPERAND_RS2 :
2640 fields->f_Rs2 = value;
2642 case FR30_OPERAND_R13 :
2643 fields->f_nil = value;
2645 case FR30_OPERAND_R14 :
2646 fields->f_nil = value;
2648 case FR30_OPERAND_R15 :
2649 fields->f_nil = value;
2651 case FR30_OPERAND_PS :
2652 fields->f_nil = value;
2654 case FR30_OPERAND_U4 :
2655 fields->f_u4 = value;
2657 case FR30_OPERAND_U4C :
2658 fields->f_u4c = value;
2660 case FR30_OPERAND_M4 :
2661 fields->f_m4 = value;
2663 case FR30_OPERAND_U8 :
2664 fields->f_u8 = value;
2666 case FR30_OPERAND_I8 :
2667 fields->f_i8 = value;
2669 case FR30_OPERAND_UDISP6 :
2670 fields->f_udisp6 = value;
2672 case FR30_OPERAND_DISP8 :
2673 fields->f_disp8 = value;
2675 case FR30_OPERAND_DISP9 :
2676 fields->f_disp9 = value;
2678 case FR30_OPERAND_DISP10 :
2679 fields->f_disp10 = value;
2681 case FR30_OPERAND_S10 :
2682 fields->f_s10 = value;
2684 case FR30_OPERAND_U10 :
2685 fields->f_u10 = value;
2687 case FR30_OPERAND_I32 :
2688 fields->f_i32 = value;
2690 case FR30_OPERAND_DIR8 :
2691 fields->f_dir8 = value;
2693 case FR30_OPERAND_DIR9 :
2694 fields->f_dir9 = value;
2696 case FR30_OPERAND_DIR10 :
2697 fields->f_dir10 = value;
2699 case FR30_OPERAND_LABEL9 :
2700 fields->f_rel9 = value;
2702 case FR30_OPERAND_LABEL12 :
2703 fields->f_rel12 = value;
2705 case FR30_OPERAND_REGLIST_LOW :
2706 fields->f_reglist_low = value;
2708 case FR30_OPERAND_REGLIST_HI :
2709 fields->f_reglist_hi = value;
2711 case FR30_OPERAND_CC :
2712 fields->f_cc = value;
2714 case FR30_OPERAND_CCC :
2715 fields->f_ccc = value;
2719 /* xgettext:c-format */
2720 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
2727 fr30_cgen_set_vma_operand (opindex, fields, value)
2729 CGEN_FIELDS * fields;
2734 case FR30_OPERAND_RI :
2735 fields->f_Ri = value;
2737 case FR30_OPERAND_RJ :
2738 fields->f_Rj = value;
2740 case FR30_OPERAND_RIC :
2741 fields->f_Ric = value;
2743 case FR30_OPERAND_RJC :
2744 fields->f_Rjc = value;
2746 case FR30_OPERAND_CRI :
2747 fields->f_CRi = value;
2749 case FR30_OPERAND_CRJ :
2750 fields->f_CRj = value;
2752 case FR30_OPERAND_RS1 :
2753 fields->f_Rs1 = value;
2755 case FR30_OPERAND_RS2 :
2756 fields->f_Rs2 = value;
2758 case FR30_OPERAND_R13 :
2759 fields->f_nil = value;
2761 case FR30_OPERAND_R14 :
2762 fields->f_nil = value;
2764 case FR30_OPERAND_R15 :
2765 fields->f_nil = value;
2767 case FR30_OPERAND_PS :
2768 fields->f_nil = value;
2770 case FR30_OPERAND_U4 :
2771 fields->f_u4 = value;
2773 case FR30_OPERAND_U4C :
2774 fields->f_u4c = value;
2776 case FR30_OPERAND_M4 :
2777 fields->f_m4 = value;
2779 case FR30_OPERAND_U8 :
2780 fields->f_u8 = value;
2782 case FR30_OPERAND_I8 :
2783 fields->f_i8 = value;
2785 case FR30_OPERAND_UDISP6 :
2786 fields->f_udisp6 = value;
2788 case FR30_OPERAND_DISP8 :
2789 fields->f_disp8 = value;
2791 case FR30_OPERAND_DISP9 :
2792 fields->f_disp9 = value;
2794 case FR30_OPERAND_DISP10 :
2795 fields->f_disp10 = value;
2797 case FR30_OPERAND_S10 :
2798 fields->f_s10 = value;
2800 case FR30_OPERAND_U10 :
2801 fields->f_u10 = value;
2803 case FR30_OPERAND_I32 :
2804 fields->f_i32 = value;
2806 case FR30_OPERAND_DIR8 :
2807 fields->f_dir8 = value;
2809 case FR30_OPERAND_DIR9 :
2810 fields->f_dir9 = value;
2812 case FR30_OPERAND_DIR10 :
2813 fields->f_dir10 = value;
2815 case FR30_OPERAND_LABEL9 :
2816 fields->f_rel9 = value;
2818 case FR30_OPERAND_LABEL12 :
2819 fields->f_rel12 = value;
2821 case FR30_OPERAND_REGLIST_LOW :
2822 fields->f_reglist_low = value;
2824 case FR30_OPERAND_REGLIST_HI :
2825 fields->f_reglist_hi = value;
2827 case FR30_OPERAND_CC :
2828 fields->f_cc = value;
2830 case FR30_OPERAND_CCC :
2831 fields->f_ccc = value;
2835 /* xgettext:c-format */
2836 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),