1 /* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
4 THIS FILE IS USED TO GENERATE fr30-opc.c.
6 Copyright (C) 1998 Free Software Foundation, Inc.
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
27 #include "libiberty.h"
33 /* Used by the ifield rtx function. */
34 #define FLD(f) (fields->f)
36 /* The hash functions are recorded here to help keep assembler code out of
37 the disassembler and vice versa. */
39 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
40 static unsigned int asm_hash_insn PARAMS ((const char *));
41 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
42 static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
44 /* Look up instruction INSN_VALUE and extract its fields.
45 INSN, if non-null, is the insn table entry.
46 Otherwise INSN_VALUE is examined to compute it.
47 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
48 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
49 If INSN != NULL, LENGTH must be valid.
50 ALIAS_P is non-zero if alias insns are to be included in the search.
52 The result is a pointer to the insn table entry, or NULL if the instruction
56 fr30_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
58 const CGEN_INSN *insn;
59 CGEN_INSN_BYTES insn_value;
64 unsigned char buf[CGEN_MAX_INSN_SIZE];
66 CGEN_INSN_INT base_insn;
68 CGEN_EXTRACT_INFO *info = NULL;
70 CGEN_EXTRACT_INFO ex_info;
71 CGEN_EXTRACT_INFO *info = &ex_info;
75 cgen_put_insn_value (od, buf, length, insn_value);
77 base_insn = insn_value; /*???*/
79 ex_info.dis_info = NULL;
80 ex_info.insn_bytes = insn_value;
82 base_insn = cgen_get_insn_value (od, buf, length);
88 const CGEN_INSN_LIST *insn_list;
90 /* The instructions are stored in hash lists.
91 Pick the first one and keep trying until we find the right one. */
93 insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
94 while (insn_list != NULL)
96 insn = insn_list->insn;
99 || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
101 /* Basic bit mask must be correct. */
102 /* ??? May wish to allow target to defer this check until the
104 if ((base_insn & CGEN_INSN_BASE_MASK (insn))
105 == CGEN_INSN_BASE_VALUE (insn))
107 /* ??? 0 is passed for `pc' */
108 int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
114 if (length != 0 && length != elength)
121 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
126 /* Sanity check: can't pass an alias insn if ! alias_p. */
128 && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
130 /* Sanity check: length must be correct. */
131 if (length != CGEN_INSN_BITSIZE (insn))
134 /* ??? 0 is passed for `pc' */
135 length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
137 /* Sanity check: must succeed.
138 Could relax this later if it ever proves useful. */
147 /* Fill in the operand instances used by INSN whose operands are FIELDS.
148 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
152 fr30_cgen_get_insn_operands (od, insn, fields, indices)
154 const CGEN_INSN * insn;
155 const CGEN_FIELDS * fields;
158 const CGEN_OPERAND_INSTANCE *opinst;
161 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
163 && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
166 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
168 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
170 indices[i] = fr30_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
175 /* Cover function to fr30_cgen_get_insn_operands when either INSN or FIELDS
177 The INSN, INSN_VALUE, and LENGTH arguments are passed to
178 fr30_cgen_lookup_insn unchanged.
180 The result is the insn table entry or NULL if the instruction wasn't
184 fr30_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
186 const CGEN_INSN *insn;
187 CGEN_INSN_BYTES insn_value;
193 /* Pass non-zero for ALIAS_P only if INSN != NULL.
194 If INSN == NULL, we want a real insn. */
195 insn = fr30_cgen_lookup_insn (od, insn, insn_value, length, &fields,
200 fr30_cgen_get_insn_operands (od, insn, &fields, indices);
205 static const CGEN_ATTR_ENTRY MACH_attr[] =
207 { "base", MACH_BASE },
208 { "fr30", MACH_FR30 },
213 const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
215 { "CACHE-ADDR", NULL },
216 { "FUN-ACCESS", NULL },
222 const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
224 { "ABS-ADDR", NULL },
225 { "HASH-PREFIX", NULL },
226 { "NEGATIVE", NULL },
227 { "PCREL-ADDR", NULL },
229 { "SEM-ONLY", NULL },
230 { "SIGN-OPT", NULL },
232 { "UNSIGNED", NULL },
237 const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
240 { "COND-CTI", NULL },
241 { "DELAY-SLOT", NULL },
243 { "NOT-IN-DELAY-SLOT", NULL },
245 { "RELAXABLE", NULL },
246 { "SKIP-CTI", NULL },
247 { "UNCOND-CTI", NULL },
252 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_gr_entries[] =
275 CGEN_KEYWORD fr30_cgen_opval_h_gr =
277 & fr30_cgen_opval_h_gr_entries[0],
281 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_cr_entries[] =
301 CGEN_KEYWORD fr30_cgen_opval_h_cr =
303 & fr30_cgen_opval_h_cr_entries[0],
307 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_dr_entries[] =
317 CGEN_KEYWORD fr30_cgen_opval_h_dr =
319 & fr30_cgen_opval_h_dr_entries[0],
323 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
328 CGEN_KEYWORD fr30_cgen_opval_h_ps =
330 & fr30_cgen_opval_h_ps_entries[0],
334 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
339 CGEN_KEYWORD fr30_cgen_opval_h_r13 =
341 & fr30_cgen_opval_h_r13_entries[0],
345 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
350 CGEN_KEYWORD fr30_cgen_opval_h_r14 =
352 & fr30_cgen_opval_h_r14_entries[0],
356 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
361 CGEN_KEYWORD fr30_cgen_opval_h_r15 =
363 & fr30_cgen_opval_h_r15_entries[0],
368 /* The hardware table. */
370 #define HW_ENT(n) fr30_cgen_hw_entries[n]
371 static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] =
373 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { 0 } } },
374 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
375 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
376 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
377 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
378 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
379 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
380 { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_cr, { 0, 0, { 0 } } },
381 { HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
382 { HW_H_PS, & HW_ENT (HW_H_PS + 1), "h-ps", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
383 { HW_H_R13, & HW_ENT (HW_H_R13 + 1), "h-r13", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, 0, { 0 } } },
384 { HW_H_R14, & HW_ENT (HW_H_R14 + 1), "h-r14", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, 0, { 0 } } },
385 { HW_H_R15, & HW_ENT (HW_H_R15 + 1), "h-r15", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, 0, { 0 } } },
386 { HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
387 { HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
388 { HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
389 { HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
390 { HW_H_IBIT, & HW_ENT (HW_H_IBIT + 1), "h-ibit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
391 { HW_H_SBIT, & HW_ENT (HW_H_SBIT + 1), "h-sbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
392 { HW_H_CCR, & HW_ENT (HW_H_CCR + 1), "h-ccr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
393 { HW_H_SCR, & HW_ENT (HW_H_SCR + 1), "h-scr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
394 { HW_H_ILM, & HW_ENT (HW_H_ILM + 1), "h-ilm", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
398 /* The instruction field table. */
400 static const CGEN_IFLD fr30_cgen_ifld_table[] =
402 { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, 0, { 0 } } },
403 { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
404 { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
405 { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
406 { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
407 { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
408 { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
409 { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
410 { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
411 { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
412 { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
413 { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
414 { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
415 { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
416 { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
417 { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
418 { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
419 { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
420 { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
421 { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
422 { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
423 { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
424 { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
425 { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
426 { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0, 0|(1<<CGEN_IFLD_SIGN_OPT)|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
427 { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
428 { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
429 { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
430 { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
431 { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
432 { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
433 { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_PCREL_ADDR)|(1<<CGEN_IFLD_SIGNED), { 0 } } },
434 { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
435 { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
436 { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
437 { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0, 0|(1<<CGEN_IFLD_PCREL_ADDR)|(1<<CGEN_IFLD_SIGNED), { 0 } } },
438 { FR30_F_REGLIST_HI, "f-reglist_hi", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
439 { FR30_F_REGLIST_LOW, "f-reglist_low", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
443 /* The operand table. */
445 #define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
446 #define OP_ENT(op) fr30_cgen_operand_table[OPERAND (op)]
448 const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
450 /* pc: program counter */
451 { "pc", & HW_ENT (HW_H_PC), 0, 0,
452 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
453 /* Ri: destination register */
454 { "Ri", & HW_ENT (HW_H_GR), 12, 4,
455 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
456 /* Rj: source register */
457 { "Rj", & HW_ENT (HW_H_GR), 8, 4,
458 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
459 /* Ric: target register coproc insn */
460 { "Ric", & HW_ENT (HW_H_GR), 12, 4,
461 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
462 /* Rjc: source register coproc insn */
463 { "Rjc", & HW_ENT (HW_H_GR), 8, 4,
464 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
465 /* CRi: coprocessor register */
466 { "CRi", & HW_ENT (HW_H_CR), 12, 4,
467 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
468 /* CRj: coprocessor register */
469 { "CRj", & HW_ENT (HW_H_CR), 8, 4,
470 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
471 /* Rs1: dedicated register */
472 { "Rs1", & HW_ENT (HW_H_DR), 8, 4,
473 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
474 /* Rs2: dedicated register */
475 { "Rs2", & HW_ENT (HW_H_DR), 12, 4,
476 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
477 /* R13: General Register 13 */
478 { "R13", & HW_ENT (HW_H_R13), 0, 0,
480 /* R14: General Register 14 */
481 { "R14", & HW_ENT (HW_H_R14), 0, 0,
483 /* R15: General Register 15 */
484 { "R15", & HW_ENT (HW_H_R15), 0, 0,
486 /* ps: Program Status register */
487 { "ps", & HW_ENT (HW_H_PS), 0, 0,
489 /* u4: 4 bit unsigned immediate */
490 { "u4", & HW_ENT (HW_H_UINT), 8, 4,
491 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
492 /* u4c: 4 bit unsigned immediate */
493 { "u4c", & HW_ENT (HW_H_UINT), 12, 4,
494 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
495 /* u8: 8 bit unsigned immediate */
496 { "u8", & HW_ENT (HW_H_UINT), 8, 8,
497 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
498 /* i8: 8 bit unsigned immediate */
499 { "i8", & HW_ENT (HW_H_UINT), 4, 8,
500 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
501 /* udisp6: 6 bit unsigned immediate */
502 { "udisp6", & HW_ENT (HW_H_UINT), 8, 4,
503 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
504 /* disp8: 8 bit signed immediate */
505 { "disp8", & HW_ENT (HW_H_SINT), 4, 8,
506 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
507 /* disp9: 9 bit signed immediate */
508 { "disp9", & HW_ENT (HW_H_SINT), 4, 8,
509 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
510 /* disp10: 10 bit signed immediate */
511 { "disp10", & HW_ENT (HW_H_SINT), 4, 8,
512 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
513 /* s10: 10 bit signed immediate */
514 { "s10", & HW_ENT (HW_H_SINT), 8, 8,
515 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
516 /* u10: 10 bit unsigned immediate */
517 { "u10", & HW_ENT (HW_H_UINT), 8, 8,
518 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
519 /* i32: 32 bit immediate */
520 { "i32", & HW_ENT (HW_H_UINT), 0, 32,
521 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
522 /* m4: 4 bit negative immediate */
523 { "m4", & HW_ENT (HW_H_SINT), 8, 4,
524 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
525 /* i20: 20 bit immediate */
526 { "i20", & HW_ENT (HW_H_UINT), 0, 20,
527 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED)|(1<<CGEN_OPERAND_VIRTUAL), { 0 } } },
528 /* dir8: 8 bit direct address */
529 { "dir8", & HW_ENT (HW_H_UINT), 8, 8,
530 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
531 /* dir9: 9 bit direct address */
532 { "dir9", & HW_ENT (HW_H_UINT), 8, 8,
533 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
534 /* dir10: 10 bit direct address */
535 { "dir10", & HW_ENT (HW_H_UINT), 8, 8,
536 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
537 /* label9: 9 bit pc relative address */
538 { "label9", & HW_ENT (HW_H_IADDR), 8, 8,
539 { 0, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
540 /* label12: 12 bit pc relative address */
541 { "label12", & HW_ENT (HW_H_IADDR), 5, 11,
542 { 0, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
543 /* reglist_low: 8 bit register mask */
544 { "reglist_low", & HW_ENT (HW_H_UINT), 8, 8,
545 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
546 /* reglist_hi: 8 bit register mask */
547 { "reglist_hi", & HW_ENT (HW_H_UINT), 8, 8,
548 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
549 /* cc: condition codes */
550 { "cc", & HW_ENT (HW_H_UINT), 4, 4,
551 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
552 /* ccc: coprocessor calc */
553 { "ccc", & HW_ENT (HW_H_UINT), 0, 8,
554 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
555 /* nbit: negative bit */
556 { "nbit", & HW_ENT (HW_H_NBIT), 0, 0,
557 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
558 /* vbit: overflow bit */
559 { "vbit", & HW_ENT (HW_H_VBIT), 0, 0,
560 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
562 { "zbit", & HW_ENT (HW_H_ZBIT), 0, 0,
563 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
564 /* cbit: carry bit */
565 { "cbit", & HW_ENT (HW_H_CBIT), 0, 0,
566 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
567 /* ibit: interrupt bit */
568 { "ibit", & HW_ENT (HW_H_IBIT), 0, 0,
569 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
570 /* sbit: stack bit */
571 { "sbit", & HW_ENT (HW_H_SBIT), 0, 0,
572 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
573 /* ccr: condition code bits */
574 { "ccr", & HW_ENT (HW_H_CCR), 0, 0,
575 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
576 /* scr: system condition bits */
577 { "scr", & HW_ENT (HW_H_SCR), 0, 0,
578 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
579 /* ilm: condition code bits */
580 { "ilm", & HW_ENT (HW_H_ILM), 0, 0,
581 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
584 /* Operand references. */
586 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
587 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
588 #define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
590 static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
591 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
592 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
593 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
594 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
595 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
596 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
597 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
601 static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
602 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
603 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
604 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
605 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
606 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
607 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
608 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
612 static const CGEN_OPERAND_INSTANCE fmt_add2_ops[] = {
613 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
614 { INPUT, "m4", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (M4), 0, 0 },
615 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
616 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
617 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
618 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
619 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
623 static const CGEN_OPERAND_INSTANCE fmt_addc_ops[] = {
624 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
625 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
626 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
627 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
628 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
629 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
630 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
631 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
635 static const CGEN_OPERAND_INSTANCE fmt_addn_ops[] = {
636 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
637 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
638 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
642 static const CGEN_OPERAND_INSTANCE fmt_addni_ops[] = {
643 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
644 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
645 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
649 static const CGEN_OPERAND_INSTANCE fmt_addn2_ops[] = {
650 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
651 { INPUT, "m4", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (M4), 0, 0 },
652 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
656 static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
657 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
658 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
659 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
660 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
661 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
662 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
666 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
667 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
668 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
669 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
670 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
671 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
672 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
676 static const CGEN_OPERAND_INSTANCE fmt_cmp2_ops[] = {
677 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
678 { INPUT, "m4", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (M4), 0, 0 },
679 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
680 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
681 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
682 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
686 static const CGEN_OPERAND_INSTANCE fmt_and_ops[] = {
687 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
688 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
689 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
690 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
691 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
695 static const CGEN_OPERAND_INSTANCE fmt_andm_ops[] = {
696 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
697 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
698 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
699 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
700 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
701 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
705 static const CGEN_OPERAND_INSTANCE fmt_andh_ops[] = {
706 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
707 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
708 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RJ), 0, 0 },
709 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
710 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
711 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
715 static const CGEN_OPERAND_INSTANCE fmt_andb_ops[] = {
716 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
717 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
718 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RJ), 0, 0 },
719 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
720 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
721 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
725 static const CGEN_OPERAND_INSTANCE fmt_bandl_ops[] = {
726 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
727 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_QI, & OP_ENT (U4), 0, 0 },
728 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
729 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
733 static const CGEN_OPERAND_INSTANCE fmt_btstl_ops[] = {
734 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_QI, & OP_ENT (U4), 0, 0 },
735 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
736 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
737 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
738 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
742 static const CGEN_OPERAND_INSTANCE fmt_mul_ops[] = {
743 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
744 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
745 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
746 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
747 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
748 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
749 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
750 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
754 static const CGEN_OPERAND_INSTANCE fmt_mulu_ops[] = {
755 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
756 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
757 { INPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
758 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
759 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
760 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
761 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
762 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
763 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
767 static const CGEN_OPERAND_INSTANCE fmt_mulh_ops[] = {
768 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
769 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
770 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
771 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
772 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
773 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
777 static const CGEN_OPERAND_INSTANCE fmt_lsl_ops[] = {
778 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
779 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
780 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
781 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
782 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
783 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
787 static const CGEN_OPERAND_INSTANCE fmt_lsli_ops[] = {
788 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
789 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
790 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
791 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
792 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
793 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
797 static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = {
798 { INPUT, "i8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I8), 0, 0 },
799 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
803 static const CGEN_OPERAND_INSTANCE fmt_ldi20_ops[] = {
804 { INPUT, "i20", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I20), 0, 0 },
805 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
809 static const CGEN_OPERAND_INSTANCE fmt_ldi32_ops[] = {
810 { INPUT, "i32", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I32), 0, 0 },
811 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
815 static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = {
816 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
817 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
818 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
822 static const CGEN_OPERAND_INSTANCE fmt_lduh_ops[] = {
823 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
824 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
825 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
829 static const CGEN_OPERAND_INSTANCE fmt_ldub_ops[] = {
830 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
831 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
832 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
836 static const CGEN_OPERAND_INSTANCE fmt_ldr13_ops[] = {
837 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
838 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
839 { INPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
840 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
844 static const CGEN_OPERAND_INSTANCE fmt_ldr13uh_ops[] = {
845 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
846 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
847 { INPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
848 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
852 static const CGEN_OPERAND_INSTANCE fmt_ldr13ub_ops[] = {
853 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
854 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
855 { INPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
856 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
860 static const CGEN_OPERAND_INSTANCE fmt_ldr14_ops[] = {
861 { INPUT, "disp10", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP10), 0, 0 },
862 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
863 { INPUT, "h_memory_add__VM_disp10_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
864 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
868 static const CGEN_OPERAND_INSTANCE fmt_ldr14uh_ops[] = {
869 { INPUT, "disp9", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP9), 0, 0 },
870 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
871 { INPUT, "h_memory_add__VM_disp9_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
872 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
876 static const CGEN_OPERAND_INSTANCE fmt_ldr14ub_ops[] = {
877 { INPUT, "disp8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP8), 0, 0 },
878 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
879 { INPUT, "h_memory_add__VM_disp8_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
880 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
884 static const CGEN_OPERAND_INSTANCE fmt_ldr15_ops[] = {
885 { INPUT, "udisp6", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UDISP6), 0, 0 },
886 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
887 { INPUT, "h_memory_add__VM_udisp6_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
888 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
892 static const CGEN_OPERAND_INSTANCE fmt_ldr15gr_ops[] = {
893 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
894 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
895 { INPUT, "f_Ri", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
896 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
897 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
901 static const CGEN_OPERAND_INSTANCE fmt_ldr15dr_ops[] = {
902 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
903 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
904 { OUTPUT, "Rs2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS2), 0, 0 },
905 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
909 static const CGEN_OPERAND_INSTANCE fmt_ldr15ps_ops[] = {
910 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
911 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
912 { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
913 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
917 static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = {
918 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
919 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
920 { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
924 static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = {
925 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
926 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
927 { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
931 static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = {
932 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
933 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
934 { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
938 static const CGEN_OPERAND_INSTANCE fmt_str13_ops[] = {
939 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
940 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
941 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
942 { OUTPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
946 static const CGEN_OPERAND_INSTANCE fmt_str13h_ops[] = {
947 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
948 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
949 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
950 { OUTPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
954 static const CGEN_OPERAND_INSTANCE fmt_str13b_ops[] = {
955 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
956 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
957 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
958 { OUTPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
962 static const CGEN_OPERAND_INSTANCE fmt_str14_ops[] = {
963 { INPUT, "disp10", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP10), 0, 0 },
964 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
965 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
966 { OUTPUT, "h_memory_add__VM_disp10_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
970 static const CGEN_OPERAND_INSTANCE fmt_str14h_ops[] = {
971 { INPUT, "disp9", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP9), 0, 0 },
972 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
973 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
974 { OUTPUT, "h_memory_add__VM_disp9_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
978 static const CGEN_OPERAND_INSTANCE fmt_str14b_ops[] = {
979 { INPUT, "disp8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP8), 0, 0 },
980 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
981 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
982 { OUTPUT, "h_memory_add__VM_disp8_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
986 static const CGEN_OPERAND_INSTANCE fmt_str15_ops[] = {
987 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
988 { INPUT, "udisp6", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UDISP6), 0, 0 },
989 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
990 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_15_udisp6", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
994 static const CGEN_OPERAND_INSTANCE fmt_str15gr_ops[] = {
995 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
996 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
997 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
998 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1002 static const CGEN_OPERAND_INSTANCE fmt_str15dr_ops[] = {
1003 { INPUT, "Rs2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS2), 0, 0 },
1004 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1005 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1006 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1010 static const CGEN_OPERAND_INSTANCE fmt_str15ps_ops[] = {
1011 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1012 { INPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
1013 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1014 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1018 static const CGEN_OPERAND_INSTANCE fmt_mov_ops[] = {
1019 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
1020 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1024 static const CGEN_OPERAND_INSTANCE fmt_movdr_ops[] = {
1025 { INPUT, "Rs1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS1), 0, 0 },
1026 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1030 static const CGEN_OPERAND_INSTANCE fmt_movps_ops[] = {
1031 { INPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
1032 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1036 static const CGEN_OPERAND_INSTANCE fmt_mov2dr_ops[] = {
1037 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1038 { OUTPUT, "Rs1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS1), 0, 0 },
1042 static const CGEN_OPERAND_INSTANCE fmt_mov2ps_ops[] = {
1043 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1044 { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
1048 static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = {
1049 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1050 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1054 static const CGEN_OPERAND_INSTANCE fmt_callr_ops[] = {
1055 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1056 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1057 { OUTPUT, "h_dr_1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 1, 0 },
1058 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1062 static const CGEN_OPERAND_INSTANCE fmt_call_ops[] = {
1063 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1064 { INPUT, "label12", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL12), 0, 0 },
1065 { OUTPUT, "h_dr_1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 1, 0 },
1066 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1070 static const CGEN_OPERAND_INSTANCE fmt_ret_ops[] = {
1071 { INPUT, "h_dr_1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 1, 0 },
1072 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1076 static const CGEN_OPERAND_INSTANCE fmt_int_ops[] = {
1077 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
1078 { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (U8), 0, 0 },
1079 { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, 0 },
1080 { OUTPUT, "ibit", & HW_ENT (HW_H_IBIT), CGEN_MODE_BI, 0, 0, 0 },
1081 { OUTPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
1082 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
1086 static const CGEN_OPERAND_INSTANCE fmt_inte_ops[] = {
1087 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
1088 { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, 0 },
1089 { OUTPUT, "ibit", & HW_ENT (HW_H_IBIT), CGEN_MODE_BI, 0, 0, 0 },
1090 { OUTPUT, "ilm", & HW_ENT (HW_H_ILM), CGEN_MODE_UQI, 0, 0, 0 },
1091 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
1095 static const CGEN_OPERAND_INSTANCE fmt_reti_ops[] = {
1096 { INPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
1097 { INPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, COND_REF },
1098 { INPUT, "h_memory_reg__VM_h_dr_2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
1099 { INPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 3, COND_REF },
1100 { INPUT, "h_memory_reg__VM_h_dr_3", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
1101 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1102 { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, COND_REF },
1103 { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, COND_REF },
1104 { OUTPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 3, COND_REF },
1108 static const CGEN_OPERAND_INSTANCE fmt_bra_ops[] = {
1109 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1110 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1114 static const CGEN_OPERAND_INSTANCE fmt_beq_ops[] = {
1115 { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
1116 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1117 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1121 static const CGEN_OPERAND_INSTANCE fmt_bc_ops[] = {
1122 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
1123 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1124 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1128 static const CGEN_OPERAND_INSTANCE fmt_bn_ops[] = {
1129 { INPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
1130 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1131 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1135 static const CGEN_OPERAND_INSTANCE fmt_bv_ops[] = {
1136 { INPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
1137 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1138 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1142 static const CGEN_OPERAND_INSTANCE fmt_blt_ops[] = {
1143 { INPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
1144 { INPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
1145 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1146 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1150 static const CGEN_OPERAND_INSTANCE fmt_ble_ops[] = {
1151 { INPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
1152 { INPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
1153 { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
1154 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1155 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1159 static const CGEN_OPERAND_INSTANCE fmt_bls_ops[] = {
1160 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
1161 { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
1162 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1163 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1167 static const CGEN_OPERAND_INSTANCE fmt_dmovr13_ops[] = {
1168 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1169 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1170 { OUTPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1174 static const CGEN_OPERAND_INSTANCE fmt_dmovr13h_ops[] = {
1175 { INPUT, "dir9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR9), 0, 0 },
1176 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1177 { OUTPUT, "h_memory_dir9", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1181 static const CGEN_OPERAND_INSTANCE fmt_dmovr13b_ops[] = {
1182 { INPUT, "dir8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR8), 0, 0 },
1183 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1184 { OUTPUT, "h_memory_dir8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1188 static const CGEN_OPERAND_INSTANCE fmt_dmovr13pi_ops[] = {
1189 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1190 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1191 { INPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1192 { OUTPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1193 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1197 static const CGEN_OPERAND_INSTANCE fmt_dmovr13pih_ops[] = {
1198 { INPUT, "dir9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR9), 0, 0 },
1199 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1200 { INPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1201 { OUTPUT, "h_memory_dir9", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1202 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1206 static const CGEN_OPERAND_INSTANCE fmt_dmovr13pib_ops[] = {
1207 { INPUT, "dir8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR8), 0, 0 },
1208 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1209 { INPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1210 { OUTPUT, "h_memory_dir8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1211 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1215 static const CGEN_OPERAND_INSTANCE fmt_dmovr15pi_ops[] = {
1216 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1217 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1218 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1219 { OUTPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1220 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1224 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13_ops[] = {
1225 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1226 { INPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1227 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1231 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13h_ops[] = {
1232 { INPUT, "dir9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR9), 0, 0 },
1233 { INPUT, "h_memory_dir9", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1234 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1238 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13b_ops[] = {
1239 { INPUT, "dir8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR8), 0, 0 },
1240 { INPUT, "h_memory_dir8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1241 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1245 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13pi_ops[] = {
1246 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1247 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1248 { INPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1249 { OUTPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1250 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1254 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13pih_ops[] = {
1255 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1256 { INPUT, "dir9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR9), 0, 0 },
1257 { INPUT, "h_memory_dir9", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1258 { OUTPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1259 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1263 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13pib_ops[] = {
1264 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1265 { INPUT, "dir8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR8), 0, 0 },
1266 { INPUT, "h_memory_dir8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1267 { OUTPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1268 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1272 static const CGEN_OPERAND_INSTANCE fmt_dmov2r15pd_ops[] = {
1273 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1274 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1275 { INPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1276 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1277 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1281 static const CGEN_OPERAND_INSTANCE fmt_andccr_ops[] = {
1282 { INPUT, "ccr", & HW_ENT (HW_H_CCR), CGEN_MODE_UQI, 0, 0, 0 },
1283 { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U8), 0, 0 },
1284 { OUTPUT, "ccr", & HW_ENT (HW_H_CCR), CGEN_MODE_UQI, 0, 0, 0 },
1288 static const CGEN_OPERAND_INSTANCE fmt_stilm_ops[] = {
1289 { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U8), 0, 0 },
1290 { OUTPUT, "ilm", & HW_ENT (HW_H_ILM), CGEN_MODE_UQI, 0, 0, 0 },
1294 static const CGEN_OPERAND_INSTANCE fmt_addsp_ops[] = {
1295 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1296 { INPUT, "s10", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (S10), 0, 0 },
1297 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1301 static const CGEN_OPERAND_INSTANCE fmt_extsb_ops[] = {
1302 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RI), 0, 0 },
1303 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1307 static const CGEN_OPERAND_INSTANCE fmt_extub_ops[] = {
1308 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_UQI, & OP_ENT (RI), 0, 0 },
1309 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1313 static const CGEN_OPERAND_INSTANCE fmt_extsh_ops[] = {
1314 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RI), 0, 0 },
1315 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1319 static const CGEN_OPERAND_INSTANCE fmt_extuh_ops[] = {
1320 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_UHI, & OP_ENT (RI), 0, 0 },
1321 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1325 static const CGEN_OPERAND_INSTANCE fmt_stm0_ops[] = {
1326 { INPUT, "reglist_low", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (REGLIST_LOW), 0, 0 },
1327 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1328 { INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, COND_REF },
1329 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1330 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
1334 static const CGEN_OPERAND_INSTANCE fmt_enter_ops[] = {
1335 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1336 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1337 { INPUT, "u10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U10), 0, 0 },
1338 { OUTPUT, "h_memory_tmp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1339 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1340 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1344 static const CGEN_OPERAND_INSTANCE fmt_leave_ops[] = {
1345 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1346 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1347 { INPUT, "h_memory_sub__VM_reg__VM_h_gr_15_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1348 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1349 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1353 static const CGEN_OPERAND_INSTANCE fmt_xchb_ops[] = {
1354 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1355 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
1356 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
1357 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1358 { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
1366 /* Instruction formats. */
1368 #define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
1370 static const CGEN_IFMT fmt_add = {
1371 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1374 static const CGEN_IFMT fmt_addi = {
1375 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1378 static const CGEN_IFMT fmt_add2 = {
1379 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
1382 static const CGEN_IFMT fmt_addc = {
1383 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1386 static const CGEN_IFMT fmt_addn = {
1387 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1390 static const CGEN_IFMT fmt_addni = {
1391 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1394 static const CGEN_IFMT fmt_addn2 = {
1395 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
1398 static const CGEN_IFMT fmt_cmp = {
1399 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1402 static const CGEN_IFMT fmt_cmpi = {
1403 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1406 static const CGEN_IFMT fmt_cmp2 = {
1407 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
1410 static const CGEN_IFMT fmt_and = {
1411 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1414 static const CGEN_IFMT fmt_andm = {
1415 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1418 static const CGEN_IFMT fmt_andh = {
1419 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1422 static const CGEN_IFMT fmt_andb = {
1423 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1426 static const CGEN_IFMT fmt_bandl = {
1427 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1430 static const CGEN_IFMT fmt_btstl = {
1431 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1434 static const CGEN_IFMT fmt_mul = {
1435 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1438 static const CGEN_IFMT fmt_mulu = {
1439 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1442 static const CGEN_IFMT fmt_mulh = {
1443 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1446 static const CGEN_IFMT fmt_div0s = {
1447 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1450 static const CGEN_IFMT fmt_div3 = {
1451 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1454 static const CGEN_IFMT fmt_lsl = {
1455 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1458 static const CGEN_IFMT fmt_lsli = {
1459 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1462 static const CGEN_IFMT fmt_ldi8 = {
1463 16, 16, 0xf000, { F (F_OP1), F (F_I8), F (F_RI), 0 }
1466 static const CGEN_IFMT fmt_ldi20 = {
1467 16, 32, 0xff00, { F (F_OP1), F (F_I20), F (F_OP2), F (F_RI), 0 }
1470 static const CGEN_IFMT fmt_ldi32 = {
1471 16, 48, 0xfff0, { F (F_OP1), F (F_I32), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1474 static const CGEN_IFMT fmt_ld = {
1475 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1478 static const CGEN_IFMT fmt_lduh = {
1479 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1482 static const CGEN_IFMT fmt_ldub = {
1483 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1486 static const CGEN_IFMT fmt_ldr13 = {
1487 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1490 static const CGEN_IFMT fmt_ldr13uh = {
1491 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1494 static const CGEN_IFMT fmt_ldr13ub = {
1495 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1498 static const CGEN_IFMT fmt_ldr14 = {
1499 16, 16, 0xf000, { F (F_OP1), F (F_DISP10), F (F_RI), 0 }
1502 static const CGEN_IFMT fmt_ldr14uh = {
1503 16, 16, 0xf000, { F (F_OP1), F (F_DISP9), F (F_RI), 0 }
1506 static const CGEN_IFMT fmt_ldr14ub = {
1507 16, 16, 0xf000, { F (F_OP1), F (F_DISP8), F (F_RI), 0 }
1510 static const CGEN_IFMT fmt_ldr15 = {
1511 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_UDISP6), F (F_RI), 0 }
1514 static const CGEN_IFMT fmt_ldr15gr = {
1515 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1518 static const CGEN_IFMT fmt_ldr15dr = {
1519 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RS2), 0 }
1522 static const CGEN_IFMT fmt_ldr15ps = {
1523 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1526 static const CGEN_IFMT fmt_st = {
1527 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1530 static const CGEN_IFMT fmt_sth = {
1531 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1534 static const CGEN_IFMT fmt_stb = {
1535 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1538 static const CGEN_IFMT fmt_str13 = {
1539 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1542 static const CGEN_IFMT fmt_str13h = {
1543 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1546 static const CGEN_IFMT fmt_str13b = {
1547 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1550 static const CGEN_IFMT fmt_str14 = {
1551 16, 16, 0xf000, { F (F_OP1), F (F_DISP10), F (F_RI), 0 }
1554 static const CGEN_IFMT fmt_str14h = {
1555 16, 16, 0xf000, { F (F_OP1), F (F_DISP9), F (F_RI), 0 }
1558 static const CGEN_IFMT fmt_str14b = {
1559 16, 16, 0xf000, { F (F_OP1), F (F_DISP8), F (F_RI), 0 }
1562 static const CGEN_IFMT fmt_str15 = {
1563 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_UDISP6), F (F_RI), 0 }
1566 static const CGEN_IFMT fmt_str15gr = {
1567 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1570 static const CGEN_IFMT fmt_str15dr = {
1571 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RS2), 0 }
1574 static const CGEN_IFMT fmt_str15ps = {
1575 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1578 static const CGEN_IFMT fmt_mov = {
1579 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1582 static const CGEN_IFMT fmt_movdr = {
1583 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RS1), F (F_RI), 0 }
1586 static const CGEN_IFMT fmt_movps = {
1587 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1590 static const CGEN_IFMT fmt_mov2dr = {
1591 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RS1), F (F_RI), 0 }
1594 static const CGEN_IFMT fmt_mov2ps = {
1595 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1598 static const CGEN_IFMT fmt_jmp = {
1599 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1602 static const CGEN_IFMT fmt_callr = {
1603 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1606 static const CGEN_IFMT fmt_call = {
1607 16, 16, 0xf800, { F (F_OP1), F (F_OP5), F (F_REL12), 0 }
1610 static const CGEN_IFMT fmt_ret = {
1611 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1614 static const CGEN_IFMT fmt_int = {
1615 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
1618 static const CGEN_IFMT fmt_inte = {
1619 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1622 static const CGEN_IFMT fmt_reti = {
1623 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1626 static const CGEN_IFMT fmt_bra = {
1627 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1630 static const CGEN_IFMT fmt_beq = {
1631 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1634 static const CGEN_IFMT fmt_bc = {
1635 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1638 static const CGEN_IFMT fmt_bn = {
1639 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1642 static const CGEN_IFMT fmt_bv = {
1643 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1646 static const CGEN_IFMT fmt_blt = {
1647 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1650 static const CGEN_IFMT fmt_ble = {
1651 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1654 static const CGEN_IFMT fmt_bls = {
1655 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1658 static const CGEN_IFMT fmt_dmovr13 = {
1659 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1662 static const CGEN_IFMT fmt_dmovr13h = {
1663 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
1666 static const CGEN_IFMT fmt_dmovr13b = {
1667 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
1670 static const CGEN_IFMT fmt_dmovr13pi = {
1671 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1674 static const CGEN_IFMT fmt_dmovr13pih = {
1675 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
1678 static const CGEN_IFMT fmt_dmovr13pib = {
1679 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
1682 static const CGEN_IFMT fmt_dmovr15pi = {
1683 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1686 static const CGEN_IFMT fmt_dmov2r13 = {
1687 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1690 static const CGEN_IFMT fmt_dmov2r13h = {
1691 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
1694 static const CGEN_IFMT fmt_dmov2r13b = {
1695 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
1698 static const CGEN_IFMT fmt_dmov2r13pi = {
1699 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1702 static const CGEN_IFMT fmt_dmov2r13pih = {
1703 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
1706 static const CGEN_IFMT fmt_dmov2r13pib = {
1707 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
1710 static const CGEN_IFMT fmt_dmov2r15pd = {
1711 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1714 static const CGEN_IFMT fmt_ldres = {
1715 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1718 static const CGEN_IFMT fmt_copop = {
1719 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_CRI), 0 }
1722 static const CGEN_IFMT fmt_copld = {
1723 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_RJC), F (F_U4C), F (F_CRI), 0 }
1726 static const CGEN_IFMT fmt_copst = {
1727 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_RIC), 0 }
1730 static const CGEN_IFMT fmt_andccr = {
1731 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
1734 static const CGEN_IFMT fmt_stilm = {
1735 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
1738 static const CGEN_IFMT fmt_addsp = {
1739 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_S10), 0 }
1742 static const CGEN_IFMT fmt_extsb = {
1743 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1746 static const CGEN_IFMT fmt_extub = {
1747 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1750 static const CGEN_IFMT fmt_extsh = {
1751 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1754 static const CGEN_IFMT fmt_extuh = {
1755 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1758 static const CGEN_IFMT fmt_ldm0 = {
1759 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_LOW), 0 }
1762 static const CGEN_IFMT fmt_ldm1 = {
1763 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_HI), 0 }
1766 static const CGEN_IFMT fmt_stm0 = {
1767 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_LOW), 0 }
1770 static const CGEN_IFMT fmt_enter = {
1771 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U10), 0 }
1774 static const CGEN_IFMT fmt_leave = {
1775 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1778 static const CGEN_IFMT fmt_xchb = {
1779 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1784 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
1785 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1786 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1788 /* The instruction table.
1789 This is currently non-static because the simulator accesses it
1792 const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
1794 /* Special null first entry.
1795 A `num' value of zero is thus invalid.
1796 Also, the special `invalid' insn resides here. */
1801 FR30_INSN_ADD, "add", "add",
1802 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1803 & fmt_add, { 0xa600 },
1804 (PTR) & fmt_add_ops[0],
1810 FR30_INSN_ADDI, "addi", "add",
1811 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1812 & fmt_addi, { 0xa400 },
1813 (PTR) & fmt_addi_ops[0],
1819 FR30_INSN_ADD2, "add2", "add2",
1820 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
1821 & fmt_add2, { 0xa500 },
1822 (PTR) & fmt_add2_ops[0],
1828 FR30_INSN_ADDC, "addc", "addc",
1829 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1830 & fmt_addc, { 0xa700 },
1831 (PTR) & fmt_addc_ops[0],
1837 FR30_INSN_ADDN, "addn", "addn",
1838 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1839 & fmt_addn, { 0xa200 },
1840 (PTR) & fmt_addn_ops[0],
1846 FR30_INSN_ADDNI, "addni", "addn",
1847 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1848 & fmt_addni, { 0xa000 },
1849 (PTR) & fmt_addni_ops[0],
1855 FR30_INSN_ADDN2, "addn2", "addn2",
1856 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
1857 & fmt_addn2, { 0xa100 },
1858 (PTR) & fmt_addn2_ops[0],
1864 FR30_INSN_SUB, "sub", "sub",
1865 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1866 & fmt_add, { 0xac00 },
1867 (PTR) & fmt_add_ops[0],
1873 FR30_INSN_SUBC, "subc", "subc",
1874 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1875 & fmt_addc, { 0xad00 },
1876 (PTR) & fmt_addc_ops[0],
1882 FR30_INSN_SUBN, "subn", "subn",
1883 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1884 & fmt_addn, { 0xae00 },
1885 (PTR) & fmt_addn_ops[0],
1891 FR30_INSN_CMP, "cmp", "cmp",
1892 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1893 & fmt_cmp, { 0xaa00 },
1894 (PTR) & fmt_cmp_ops[0],
1900 FR30_INSN_CMPI, "cmpi", "cmp",
1901 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1902 & fmt_cmpi, { 0xa800 },
1903 (PTR) & fmt_cmpi_ops[0],
1909 FR30_INSN_CMP2, "cmp2", "cmp2",
1910 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
1911 & fmt_cmp2, { 0xa900 },
1912 (PTR) & fmt_cmp2_ops[0],
1918 FR30_INSN_AND, "and", "and",
1919 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1920 & fmt_and, { 0x8200 },
1921 (PTR) & fmt_and_ops[0],
1927 FR30_INSN_OR, "or", "or",
1928 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1929 & fmt_and, { 0x9200 },
1930 (PTR) & fmt_and_ops[0],
1936 FR30_INSN_EOR, "eor", "eor",
1937 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1938 & fmt_and, { 0x9a00 },
1939 (PTR) & fmt_and_ops[0],
1945 FR30_INSN_ANDM, "andm", "and",
1946 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1947 & fmt_andm, { 0x8400 },
1948 (PTR) & fmt_andm_ops[0],
1954 FR30_INSN_ANDH, "andh", "andh",
1955 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1956 & fmt_andh, { 0x8500 },
1957 (PTR) & fmt_andh_ops[0],
1963 FR30_INSN_ANDB, "andb", "andb",
1964 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1965 & fmt_andb, { 0x8600 },
1966 (PTR) & fmt_andb_ops[0],
1972 FR30_INSN_ORM, "orm", "or",
1973 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1974 & fmt_andm, { 0x9400 },
1975 (PTR) & fmt_andm_ops[0],
1981 FR30_INSN_ORH, "orh", "orh",
1982 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1983 & fmt_andh, { 0x9500 },
1984 (PTR) & fmt_andh_ops[0],
1990 FR30_INSN_ORB, "orb", "orb",
1991 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1992 & fmt_andb, { 0x9600 },
1993 (PTR) & fmt_andb_ops[0],
1999 FR30_INSN_EORM, "eorm", "eor",
2000 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2001 & fmt_andm, { 0x9c00 },
2002 (PTR) & fmt_andm_ops[0],
2008 FR30_INSN_EORH, "eorh", "eorh",
2009 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2010 & fmt_andh, { 0x9d00 },
2011 (PTR) & fmt_andh_ops[0],
2017 FR30_INSN_EORB, "eorb", "eorb",
2018 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
2019 & fmt_andb, { 0x9e00 },
2020 (PTR) & fmt_andb_ops[0],
2023 /* bandl $u4,@$Ri */
2026 FR30_INSN_BANDL, "bandl", "bandl",
2027 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2028 & fmt_bandl, { 0x8000 },
2029 (PTR) & fmt_bandl_ops[0],
2035 FR30_INSN_BORL, "borl", "borl",
2036 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2037 & fmt_bandl, { 0x9000 },
2038 (PTR) & fmt_bandl_ops[0],
2041 /* beorl $u4,@$Ri */
2044 FR30_INSN_BEORL, "beorl", "beorl",
2045 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2046 & fmt_bandl, { 0x9800 },
2047 (PTR) & fmt_bandl_ops[0],
2050 /* bandh $u4,@$Ri */
2053 FR30_INSN_BANDH, "bandh", "bandh",
2054 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2055 & fmt_bandl, { 0x8100 },
2056 (PTR) & fmt_bandl_ops[0],
2062 FR30_INSN_BORH, "borh", "borh",
2063 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2064 & fmt_bandl, { 0x9100 },
2065 (PTR) & fmt_bandl_ops[0],
2068 /* beorh $u4,@$Ri */
2071 FR30_INSN_BEORH, "beorh", "beorh",
2072 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2073 & fmt_bandl, { 0x9900 },
2074 (PTR) & fmt_bandl_ops[0],
2077 /* btstl $u4,@$Ri */
2080 FR30_INSN_BTSTL, "btstl", "btstl",
2081 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2082 & fmt_btstl, { 0x8800 },
2083 (PTR) & fmt_btstl_ops[0],
2086 /* btsth $u4,@$Ri */
2089 FR30_INSN_BTSTH, "btsth", "btsth",
2090 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
2091 & fmt_btstl, { 0x8900 },
2092 (PTR) & fmt_btstl_ops[0],
2098 FR30_INSN_MUL, "mul", "mul",
2099 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2100 & fmt_mul, { 0xaf00 },
2101 (PTR) & fmt_mul_ops[0],
2107 FR30_INSN_MULU, "mulu", "mulu",
2108 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2109 & fmt_mulu, { 0xab00 },
2110 (PTR) & fmt_mulu_ops[0],
2116 FR30_INSN_MULH, "mulh", "mulh",
2117 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2118 & fmt_mulh, { 0xbf00 },
2119 (PTR) & fmt_mulh_ops[0],
2125 FR30_INSN_MULUH, "muluh", "muluh",
2126 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2127 & fmt_mulh, { 0xbb00 },
2128 (PTR) & fmt_mulh_ops[0],
2134 FR30_INSN_DIV0S, "div0s", "div0s",
2135 { { MNEM, ' ', OP (RI), 0 } },
2136 & fmt_div0s, { 0x9740 },
2143 FR30_INSN_DIV0U, "div0u", "div0u",
2144 { { MNEM, ' ', OP (RI), 0 } },
2145 & fmt_div0s, { 0x9750 },
2152 FR30_INSN_DIV1, "div1", "div1",
2153 { { MNEM, ' ', OP (RI), 0 } },
2154 & fmt_div0s, { 0x9760 },
2161 FR30_INSN_DIV2, "div2", "div2",
2162 { { MNEM, ' ', OP (RI), 0 } },
2163 & fmt_div0s, { 0x9770 },
2170 FR30_INSN_DIV3, "div3", "div3",
2172 & fmt_div3, { 0x9f60 },
2179 FR30_INSN_DIV4S, "div4s", "div4s",
2181 & fmt_div3, { 0x9f70 },
2188 FR30_INSN_LSL, "lsl", "lsl",
2189 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2190 & fmt_lsl, { 0xb600 },
2191 (PTR) & fmt_lsl_ops[0],
2197 FR30_INSN_LSLI, "lsli", "lsl",
2198 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2199 & fmt_lsli, { 0xb400 },
2200 (PTR) & fmt_lsli_ops[0],
2206 FR30_INSN_LSL2, "lsl2", "lsl2",
2207 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2208 & fmt_lsli, { 0xb500 },
2209 (PTR) & fmt_lsli_ops[0],
2215 FR30_INSN_LSR, "lsr", "lsr",
2216 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2217 & fmt_lsl, { 0xb200 },
2218 (PTR) & fmt_lsl_ops[0],
2224 FR30_INSN_LSRI, "lsri", "lsr",
2225 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2226 & fmt_lsli, { 0xb000 },
2227 (PTR) & fmt_lsli_ops[0],
2233 FR30_INSN_LSR2, "lsr2", "lsr2",
2234 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2235 & fmt_lsli, { 0xb100 },
2236 (PTR) & fmt_lsli_ops[0],
2242 FR30_INSN_ASR, "asr", "asr",
2243 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2244 & fmt_lsl, { 0xba00 },
2245 (PTR) & fmt_lsl_ops[0],
2251 FR30_INSN_ASRI, "asri", "asr",
2252 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2253 & fmt_lsli, { 0xb800 },
2254 (PTR) & fmt_lsli_ops[0],
2260 FR30_INSN_ASR2, "asr2", "asr2",
2261 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
2262 & fmt_lsli, { 0xb900 },
2263 (PTR) & fmt_lsli_ops[0],
2269 FR30_INSN_LDI8, "ldi8", "ldi:8",
2270 { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
2271 & fmt_ldi8, { 0xc000 },
2272 (PTR) & fmt_ldi8_ops[0],
2275 /* ldi:20 $i20,$Ri */
2278 FR30_INSN_LDI20, "ldi20", "ldi:20",
2279 { { MNEM, ' ', OP (I20), ',', OP (RI), 0 } },
2280 & fmt_ldi20, { 0x9b00 },
2281 (PTR) & fmt_ldi20_ops[0],
2282 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
2284 /* ldi:32 $i32,$Ri */
2287 FR30_INSN_LDI32, "ldi32", "ldi:32",
2288 { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
2289 & fmt_ldi32, { 0x9f80 },
2290 (PTR) & fmt_ldi32_ops[0],
2296 FR30_INSN_LD, "ld", "ld",
2297 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2298 & fmt_ld, { 0x400 },
2299 (PTR) & fmt_ld_ops[0],
2305 FR30_INSN_LDUH, "lduh", "lduh",
2306 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2307 & fmt_lduh, { 0x500 },
2308 (PTR) & fmt_lduh_ops[0],
2314 FR30_INSN_LDUB, "ldub", "ldub",
2315 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2316 & fmt_ldub, { 0x600 },
2317 (PTR) & fmt_ldub_ops[0],
2320 /* ld @($R13,$Rj),$Ri */
2323 FR30_INSN_LDR13, "ldr13", "ld",
2324 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
2325 & fmt_ldr13, { 0x0 },
2326 (PTR) & fmt_ldr13_ops[0],
2329 /* lduh @($R13,$Rj),$Ri */
2332 FR30_INSN_LDR13UH, "ldr13uh", "lduh",
2333 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
2334 & fmt_ldr13uh, { 0x100 },
2335 (PTR) & fmt_ldr13uh_ops[0],
2338 /* ldub @($R13,$Rj),$Ri */
2341 FR30_INSN_LDR13UB, "ldr13ub", "ldub",
2342 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
2343 & fmt_ldr13ub, { 0x200 },
2344 (PTR) & fmt_ldr13ub_ops[0],
2347 /* ld @($R14,$disp10),$Ri */
2350 FR30_INSN_LDR14, "ldr14", "ld",
2351 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP10), ')', ',', OP (RI), 0 } },
2352 & fmt_ldr14, { 0x2000 },
2353 (PTR) & fmt_ldr14_ops[0],
2356 /* lduh @($R14,$disp9),$Ri */
2359 FR30_INSN_LDR14UH, "ldr14uh", "lduh",
2360 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP9), ')', ',', OP (RI), 0 } },
2361 & fmt_ldr14uh, { 0x4000 },
2362 (PTR) & fmt_ldr14uh_ops[0],
2365 /* ldub @($R14,$disp8),$Ri */
2368 FR30_INSN_LDR14UB, "ldr14ub", "ldub",
2369 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP8), ')', ',', OP (RI), 0 } },
2370 & fmt_ldr14ub, { 0x6000 },
2371 (PTR) & fmt_ldr14ub_ops[0],
2374 /* ld @($R15,$udisp6),$Ri */
2377 FR30_INSN_LDR15, "ldr15", "ld",
2378 { { MNEM, ' ', '@', '(', OP (R15), ',', OP (UDISP6), ')', ',', OP (RI), 0 } },
2379 & fmt_ldr15, { 0x300 },
2380 (PTR) & fmt_ldr15_ops[0],
2386 FR30_INSN_LDR15GR, "ldr15gr", "ld",
2387 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RI), 0 } },
2388 & fmt_ldr15gr, { 0x700 },
2389 (PTR) & fmt_ldr15gr_ops[0],
2392 /* ld @$R15+,$Rs2 */
2395 FR30_INSN_LDR15DR, "ldr15dr", "ld",
2396 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RS2), 0 } },
2397 & fmt_ldr15dr, { 0x780 },
2398 (PTR) & fmt_ldr15dr_ops[0],
2404 FR30_INSN_LDR15PS, "ldr15ps", "ld",
2405 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (PS), 0 } },
2406 & fmt_ldr15ps, { 0x790 },
2407 (PTR) & fmt_ldr15ps_ops[0],
2413 FR30_INSN_ST, "st", "st",
2414 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
2415 & fmt_st, { 0x1400 },
2416 (PTR) & fmt_st_ops[0],
2422 FR30_INSN_STH, "sth", "sth",
2423 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
2424 & fmt_sth, { 0x1500 },
2425 (PTR) & fmt_sth_ops[0],
2431 FR30_INSN_STB, "stb", "stb",
2432 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
2433 & fmt_stb, { 0x1600 },
2434 (PTR) & fmt_stb_ops[0],
2437 /* st $Ri,@($R13,$Rj) */
2440 FR30_INSN_STR13, "str13", "st",
2441 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
2442 & fmt_str13, { 0x1000 },
2443 (PTR) & fmt_str13_ops[0],
2446 /* sth $Ri,@($R13,$Rj) */
2449 FR30_INSN_STR13H, "str13h", "sth",
2450 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
2451 & fmt_str13h, { 0x1100 },
2452 (PTR) & fmt_str13h_ops[0],
2455 /* stb $Ri,@($R13,$Rj) */
2458 FR30_INSN_STR13B, "str13b", "stb",
2459 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
2460 & fmt_str13b, { 0x1200 },
2461 (PTR) & fmt_str13b_ops[0],
2464 /* st $Ri,@($R14,$disp10) */
2467 FR30_INSN_STR14, "str14", "st",
2468 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP10), ')', 0 } },
2469 & fmt_str14, { 0x3000 },
2470 (PTR) & fmt_str14_ops[0],
2473 /* sth $Ri,@($R14,$disp9) */
2476 FR30_INSN_STR14H, "str14h", "sth",
2477 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP9), ')', 0 } },
2478 & fmt_str14h, { 0x5000 },
2479 (PTR) & fmt_str14h_ops[0],
2482 /* stb $Ri,@($R14,$disp8) */
2485 FR30_INSN_STR14B, "str14b", "stb",
2486 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP8), ')', 0 } },
2487 & fmt_str14b, { 0x7000 },
2488 (PTR) & fmt_str14b_ops[0],
2491 /* st $Ri,@($R15,$udisp6) */
2494 FR30_INSN_STR15, "str15", "st",
2495 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R15), ',', OP (UDISP6), ')', 0 } },
2496 & fmt_str15, { 0x1300 },
2497 (PTR) & fmt_str15_ops[0],
2503 FR30_INSN_STR15GR, "str15gr", "st",
2504 { { MNEM, ' ', OP (RI), ',', '@', '-', OP (R15), 0 } },
2505 & fmt_str15gr, { 0x1700 },
2506 (PTR) & fmt_str15gr_ops[0],
2509 /* st $Rs2,@-$R15 */
2512 FR30_INSN_STR15DR, "str15dr", "st",
2513 { { MNEM, ' ', OP (RS2), ',', '@', '-', OP (R15), 0 } },
2514 & fmt_str15dr, { 0x1780 },
2515 (PTR) & fmt_str15dr_ops[0],
2521 FR30_INSN_STR15PS, "str15ps", "st",
2522 { { MNEM, ' ', OP (PS), ',', '@', '-', OP (R15), 0 } },
2523 & fmt_str15ps, { 0x1790 },
2524 (PTR) & fmt_str15ps_ops[0],
2530 FR30_INSN_MOV, "mov", "mov",
2531 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
2532 & fmt_mov, { 0x8b00 },
2533 (PTR) & fmt_mov_ops[0],
2539 FR30_INSN_MOVDR, "movdr", "mov",
2540 { { MNEM, ' ', OP (RS1), ',', OP (RI), 0 } },
2541 & fmt_movdr, { 0xb700 },
2542 (PTR) & fmt_movdr_ops[0],
2548 FR30_INSN_MOVPS, "movps", "mov",
2549 { { MNEM, ' ', OP (PS), ',', OP (RI), 0 } },
2550 & fmt_movps, { 0x1710 },
2551 (PTR) & fmt_movps_ops[0],
2557 FR30_INSN_MOV2DR, "mov2dr", "mov",
2558 { { MNEM, ' ', OP (RI), ',', OP (RS1), 0 } },
2559 & fmt_mov2dr, { 0xb300 },
2560 (PTR) & fmt_mov2dr_ops[0],
2566 FR30_INSN_MOV2PS, "mov2ps", "mov",
2567 { { MNEM, ' ', OP (RI), ',', OP (PS), 0 } },
2568 & fmt_mov2ps, { 0x710 },
2569 (PTR) & fmt_mov2ps_ops[0],
2575 FR30_INSN_JMP, "jmp", "jmp",
2576 { { MNEM, ' ', '@', OP (RI), 0 } },
2577 & fmt_jmp, { 0x9700 },
2578 (PTR) & fmt_jmp_ops[0],
2579 { 0, 0|A(UNCOND_CTI), { 0 } }
2584 FR30_INSN_JMPD, "jmpd", "jmp:d",
2585 { { MNEM, ' ', '@', OP (RI), 0 } },
2586 & fmt_jmp, { 0x9f00 },
2587 (PTR) & fmt_jmp_ops[0],
2588 { 0, 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
2593 FR30_INSN_CALLR, "callr", "call",
2594 { { MNEM, ' ', '@', OP (RI), 0 } },
2595 & fmt_callr, { 0x9710 },
2596 (PTR) & fmt_callr_ops[0],
2597 { 0, 0|A(UNCOND_CTI), { 0 } }
2602 FR30_INSN_CALLRD, "callrd", "call:d",
2603 { { MNEM, ' ', '@', OP (RI), 0 } },
2604 & fmt_callr, { 0x9f10 },
2605 (PTR) & fmt_callr_ops[0],
2606 { 0, 0|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
2611 FR30_INSN_CALL, "call", "call",
2612 { { MNEM, ' ', OP (LABEL12), 0 } },
2613 & fmt_call, { 0xd000 },
2614 (PTR) & fmt_call_ops[0],
2615 { 0, 0|A(UNCOND_CTI), { 0 } }
2617 /* call:d $label12 */
2620 FR30_INSN_CALLD, "calld", "call:d",
2621 { { MNEM, ' ', OP (LABEL12), 0 } },
2622 & fmt_call, { 0xd800 },
2623 (PTR) & fmt_call_ops[0],
2624 { 0, 0|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
2629 FR30_INSN_RET, "ret", "ret",
2631 & fmt_ret, { 0x9720 },
2632 (PTR) & fmt_ret_ops[0],
2633 { 0, 0|A(UNCOND_CTI), { 0 } }
2638 FR30_INSN_RET_D, "ret:d", "ret:d",
2640 & fmt_ret, { 0x9f20 },
2641 (PTR) & fmt_ret_ops[0],
2642 { 0, 0|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
2647 FR30_INSN_INT, "int", "int",
2648 { { MNEM, ' ', OP (U8), 0 } },
2649 & fmt_int, { 0x1f00 },
2650 (PTR) & fmt_int_ops[0],
2651 { 0, 0|A(UNCOND_CTI), { 0 } }
2656 FR30_INSN_INTE, "inte", "inte",
2658 & fmt_inte, { 0x9f30 },
2659 (PTR) & fmt_inte_ops[0],
2660 { 0, 0|A(UNCOND_CTI), { 0 } }
2665 FR30_INSN_RETI, "reti", "reti",
2667 & fmt_reti, { 0x9730 },
2668 (PTR) & fmt_reti_ops[0],
2669 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2674 FR30_INSN_BRA, "bra", "bra",
2675 { { MNEM, ' ', OP (LABEL9), 0 } },
2676 & fmt_bra, { 0xe000 },
2677 (PTR) & fmt_bra_ops[0],
2678 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2683 FR30_INSN_BRAD, "brad", "bra:d",
2684 { { MNEM, ' ', OP (LABEL9), 0 } },
2685 & fmt_bra, { 0xf000 },
2686 (PTR) & fmt_bra_ops[0],
2687 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2692 FR30_INSN_BNO, "bno", "bno",
2693 { { MNEM, ' ', OP (LABEL9), 0 } },
2694 & fmt_bra, { 0xe100 },
2695 (PTR) & fmt_bra_ops[0],
2696 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2701 FR30_INSN_BNOD, "bnod", "bno:d",
2702 { { MNEM, ' ', OP (LABEL9), 0 } },
2703 & fmt_bra, { 0xf100 },
2704 (PTR) & fmt_bra_ops[0],
2705 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2710 FR30_INSN_BEQ, "beq", "beq",
2711 { { MNEM, ' ', OP (LABEL9), 0 } },
2712 & fmt_beq, { 0xe200 },
2713 (PTR) & fmt_beq_ops[0],
2714 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2719 FR30_INSN_BEQD, "beqd", "beq:d",
2720 { { MNEM, ' ', OP (LABEL9), 0 } },
2721 & fmt_beq, { 0xf200 },
2722 (PTR) & fmt_beq_ops[0],
2723 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2728 FR30_INSN_BNE, "bne", "bne",
2729 { { MNEM, ' ', OP (LABEL9), 0 } },
2730 & fmt_beq, { 0xe300 },
2731 (PTR) & fmt_beq_ops[0],
2732 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2737 FR30_INSN_BNED, "bned", "bne:d",
2738 { { MNEM, ' ', OP (LABEL9), 0 } },
2739 & fmt_beq, { 0xf300 },
2740 (PTR) & fmt_beq_ops[0],
2741 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2746 FR30_INSN_BC, "bc", "bc",
2747 { { MNEM, ' ', OP (LABEL9), 0 } },
2748 & fmt_bc, { 0xe400 },
2749 (PTR) & fmt_bc_ops[0],
2750 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2755 FR30_INSN_BCD, "bcd", "bc:d",
2756 { { MNEM, ' ', OP (LABEL9), 0 } },
2757 & fmt_bc, { 0xf400 },
2758 (PTR) & fmt_bc_ops[0],
2759 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2764 FR30_INSN_BNC, "bnc", "bnc",
2765 { { MNEM, ' ', OP (LABEL9), 0 } },
2766 & fmt_bc, { 0xe500 },
2767 (PTR) & fmt_bc_ops[0],
2768 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2773 FR30_INSN_BNCD, "bncd", "bnc:d",
2774 { { MNEM, ' ', OP (LABEL9), 0 } },
2775 & fmt_bc, { 0xf500 },
2776 (PTR) & fmt_bc_ops[0],
2777 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2782 FR30_INSN_BN, "bn", "bn",
2783 { { MNEM, ' ', OP (LABEL9), 0 } },
2784 & fmt_bn, { 0xe600 },
2785 (PTR) & fmt_bn_ops[0],
2786 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2791 FR30_INSN_BND, "bnd", "bn:d",
2792 { { MNEM, ' ', OP (LABEL9), 0 } },
2793 & fmt_bn, { 0xf600 },
2794 (PTR) & fmt_bn_ops[0],
2795 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2800 FR30_INSN_BP, "bp", "bp",
2801 { { MNEM, ' ', OP (LABEL9), 0 } },
2802 & fmt_bn, { 0xe700 },
2803 (PTR) & fmt_bn_ops[0],
2804 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2809 FR30_INSN_BPD, "bpd", "bp:d",
2810 { { MNEM, ' ', OP (LABEL9), 0 } },
2811 & fmt_bn, { 0xf700 },
2812 (PTR) & fmt_bn_ops[0],
2813 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2818 FR30_INSN_BV, "bv", "bv",
2819 { { MNEM, ' ', OP (LABEL9), 0 } },
2820 & fmt_bv, { 0xe800 },
2821 (PTR) & fmt_bv_ops[0],
2822 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2827 FR30_INSN_BVD, "bvd", "bv:d",
2828 { { MNEM, ' ', OP (LABEL9), 0 } },
2829 & fmt_bv, { 0xf800 },
2830 (PTR) & fmt_bv_ops[0],
2831 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2836 FR30_INSN_BNV, "bnv", "bnv",
2837 { { MNEM, ' ', OP (LABEL9), 0 } },
2838 & fmt_bv, { 0xe900 },
2839 (PTR) & fmt_bv_ops[0],
2840 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2845 FR30_INSN_BNVD, "bnvd", "bnv:d",
2846 { { MNEM, ' ', OP (LABEL9), 0 } },
2847 & fmt_bv, { 0xf900 },
2848 (PTR) & fmt_bv_ops[0],
2849 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2854 FR30_INSN_BLT, "blt", "blt",
2855 { { MNEM, ' ', OP (LABEL9), 0 } },
2856 & fmt_blt, { 0xea00 },
2857 (PTR) & fmt_blt_ops[0],
2858 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2863 FR30_INSN_BLTD, "bltd", "blt:d",
2864 { { MNEM, ' ', OP (LABEL9), 0 } },
2865 & fmt_blt, { 0xfa00 },
2866 (PTR) & fmt_blt_ops[0],
2867 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2872 FR30_INSN_BGE, "bge", "bge",
2873 { { MNEM, ' ', OP (LABEL9), 0 } },
2874 & fmt_blt, { 0xeb00 },
2875 (PTR) & fmt_blt_ops[0],
2876 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2881 FR30_INSN_BGED, "bged", "bge:d",
2882 { { MNEM, ' ', OP (LABEL9), 0 } },
2883 & fmt_blt, { 0xfb00 },
2884 (PTR) & fmt_blt_ops[0],
2885 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2890 FR30_INSN_BLE, "ble", "ble",
2891 { { MNEM, ' ', OP (LABEL9), 0 } },
2892 & fmt_ble, { 0xec00 },
2893 (PTR) & fmt_ble_ops[0],
2894 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2899 FR30_INSN_BLED, "bled", "ble:d",
2900 { { MNEM, ' ', OP (LABEL9), 0 } },
2901 & fmt_ble, { 0xfc00 },
2902 (PTR) & fmt_ble_ops[0],
2903 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2908 FR30_INSN_BGT, "bgt", "bgt",
2909 { { MNEM, ' ', OP (LABEL9), 0 } },
2910 & fmt_ble, { 0xed00 },
2911 (PTR) & fmt_ble_ops[0],
2912 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2917 FR30_INSN_BGTD, "bgtd", "bgt:d",
2918 { { MNEM, ' ', OP (LABEL9), 0 } },
2919 & fmt_ble, { 0xfd00 },
2920 (PTR) & fmt_ble_ops[0],
2921 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2926 FR30_INSN_BLS, "bls", "bls",
2927 { { MNEM, ' ', OP (LABEL9), 0 } },
2928 & fmt_bls, { 0xee00 },
2929 (PTR) & fmt_bls_ops[0],
2930 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2935 FR30_INSN_BLSD, "blsd", "bls:d",
2936 { { MNEM, ' ', OP (LABEL9), 0 } },
2937 & fmt_bls, { 0xfe00 },
2938 (PTR) & fmt_bls_ops[0],
2939 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2944 FR30_INSN_BHI, "bhi", "bhi",
2945 { { MNEM, ' ', OP (LABEL9), 0 } },
2946 & fmt_bls, { 0xef00 },
2947 (PTR) & fmt_bls_ops[0],
2948 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
2953 FR30_INSN_BHID, "bhid", "bhi:d",
2954 { { MNEM, ' ', OP (LABEL9), 0 } },
2955 & fmt_bls, { 0xff00 },
2956 (PTR) & fmt_bls_ops[0],
2957 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
2959 /* dmov $R13,@$dir10 */
2962 FR30_INSN_DMOVR13, "dmovr13", "dmov",
2963 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR10), 0 } },
2964 & fmt_dmovr13, { 0x1800 },
2965 (PTR) & fmt_dmovr13_ops[0],
2968 /* dmovh $R13,@$dir9 */
2971 FR30_INSN_DMOVR13H, "dmovr13h", "dmovh",
2972 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR9), 0 } },
2973 & fmt_dmovr13h, { 0x1900 },
2974 (PTR) & fmt_dmovr13h_ops[0],
2977 /* dmovb $R13,@$dir8 */
2980 FR30_INSN_DMOVR13B, "dmovr13b", "dmovb",
2981 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR8), 0 } },
2982 & fmt_dmovr13b, { 0x1a00 },
2983 (PTR) & fmt_dmovr13b_ops[0],
2986 /* dmov @$R13+,@$dir10 */
2989 FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov",
2990 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR10), 0 } },
2991 & fmt_dmovr13pi, { 0x1c00 },
2992 (PTR) & fmt_dmovr13pi_ops[0],
2995 /* dmovh @$R13+,@$dir9 */
2998 FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh",
2999 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR9), 0 } },
3000 & fmt_dmovr13pih, { 0x1d00 },
3001 (PTR) & fmt_dmovr13pih_ops[0],
3004 /* dmovb @$R13+,@$dir8 */
3007 FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb",
3008 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR8), 0 } },
3009 & fmt_dmovr13pib, { 0x1e00 },
3010 (PTR) & fmt_dmovr13pib_ops[0],
3013 /* dmov @$R15+,@$dir10 */
3016 FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov",
3017 { { MNEM, ' ', '@', OP (R15), '+', ',', '@', OP (DIR10), 0 } },
3018 & fmt_dmovr15pi, { 0x1b00 },
3019 (PTR) & fmt_dmovr15pi_ops[0],
3022 /* dmov @$dir10,$R13 */
3025 FR30_INSN_DMOV2R13, "dmov2r13", "dmov",
3026 { { MNEM, ' ', '@', OP (DIR10), ',', OP (R13), 0 } },
3027 & fmt_dmov2r13, { 0x800 },
3028 (PTR) & fmt_dmov2r13_ops[0],
3031 /* dmovh @$dir9,$R13 */
3034 FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh",
3035 { { MNEM, ' ', '@', OP (DIR9), ',', OP (R13), 0 } },
3036 & fmt_dmov2r13h, { 0x900 },
3037 (PTR) & fmt_dmov2r13h_ops[0],
3040 /* dmovb @$dir8,$R13 */
3043 FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb",
3044 { { MNEM, ' ', '@', OP (DIR8), ',', OP (R13), 0 } },
3045 & fmt_dmov2r13b, { 0xa00 },
3046 (PTR) & fmt_dmov2r13b_ops[0],
3049 /* dmov @$dir10,@$R13+ */
3052 FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov",
3053 { { MNEM, ' ', '@', OP (DIR10), ',', '@', OP (R13), '+', 0 } },
3054 & fmt_dmov2r13pi, { 0xc00 },
3055 (PTR) & fmt_dmov2r13pi_ops[0],
3058 /* dmovh @$dir9,@$R13+ */
3061 FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh",
3062 { { MNEM, ' ', '@', OP (DIR9), ',', '@', OP (R13), '+', 0 } },
3063 & fmt_dmov2r13pih, { 0xd00 },
3064 (PTR) & fmt_dmov2r13pih_ops[0],
3067 /* dmovb @$dir8,@$R13+ */
3070 FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb",
3071 { { MNEM, ' ', '@', OP (DIR8), ',', '@', OP (R13), '+', 0 } },
3072 & fmt_dmov2r13pib, { 0xe00 },
3073 (PTR) & fmt_dmov2r13pib_ops[0],
3076 /* dmov @$dir10,@-$R15 */
3079 FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov",
3080 { { MNEM, ' ', '@', OP (DIR10), ',', '@', '-', OP (R15), 0 } },
3081 & fmt_dmov2r15pd, { 0xb00 },
3082 (PTR) & fmt_dmov2r15pd_ops[0],
3085 /* ldres @$Ri+,$u4 */
3088 FR30_INSN_LDRES, "ldres", "ldres",
3089 { { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } },
3090 & fmt_ldres, { 0xbc00 },
3094 /* stres $u4,@$Ri+ */
3097 FR30_INSN_STRES, "stres", "stres",
3098 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } },
3099 & fmt_ldres, { 0xbd00 },
3103 /* copop $u4c,$ccc,$CRj,$CRi */
3106 FR30_INSN_COPOP, "copop", "copop",
3107 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (CRI), 0 } },
3108 & fmt_copop, { 0x9fc0 },
3112 /* copld $u4c,$ccc,$Rjc,$CRi */
3115 FR30_INSN_COPLD, "copld", "copld",
3116 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (RJC), ',', OP (CRI), 0 } },
3117 & fmt_copld, { 0x9fd0 },
3121 /* copst $u4c,$ccc,$CRj,$Ric */
3124 FR30_INSN_COPST, "copst", "copst",
3125 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
3126 & fmt_copst, { 0x9fe0 },
3130 /* copsv $u4c,$ccc,$CRj,$Ric */
3133 FR30_INSN_COPSV, "copsv", "copsv",
3134 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
3135 & fmt_copst, { 0x9ff0 },
3142 FR30_INSN_NOP, "nop", "nop",
3144 & fmt_div3, { 0x9fa0 },
3151 FR30_INSN_ANDCCR, "andccr", "andccr",
3152 { { MNEM, ' ', OP (U8), 0 } },
3153 & fmt_andccr, { 0x8300 },
3154 (PTR) & fmt_andccr_ops[0],
3160 FR30_INSN_ORCCR, "orccr", "orccr",
3161 { { MNEM, ' ', OP (U8), 0 } },
3162 & fmt_andccr, { 0x9300 },
3163 (PTR) & fmt_andccr_ops[0],
3169 FR30_INSN_STILM, "stilm", "stilm",
3170 { { MNEM, ' ', OP (U8), 0 } },
3171 & fmt_stilm, { 0x8700 },
3172 (PTR) & fmt_stilm_ops[0],
3178 FR30_INSN_ADDSP, "addsp", "addsp",
3179 { { MNEM, ' ', OP (S10), 0 } },
3180 & fmt_addsp, { 0xa300 },
3181 (PTR) & fmt_addsp_ops[0],
3187 FR30_INSN_EXTSB, "extsb", "extsb",
3188 { { MNEM, ' ', OP (RI), 0 } },
3189 & fmt_extsb, { 0x9780 },
3190 (PTR) & fmt_extsb_ops[0],
3196 FR30_INSN_EXTUB, "extub", "extub",
3197 { { MNEM, ' ', OP (RI), 0 } },
3198 & fmt_extub, { 0x9790 },
3199 (PTR) & fmt_extub_ops[0],
3205 FR30_INSN_EXTSH, "extsh", "extsh",
3206 { { MNEM, ' ', OP (RI), 0 } },
3207 & fmt_extsh, { 0x97a0 },
3208 (PTR) & fmt_extsh_ops[0],
3214 FR30_INSN_EXTUH, "extuh", "extuh",
3215 { { MNEM, ' ', OP (RI), 0 } },
3216 & fmt_extuh, { 0x97b0 },
3217 (PTR) & fmt_extuh_ops[0],
3220 /* ldm0 ($reglist_low) */
3223 FR30_INSN_LDM0, "ldm0", "ldm0",
3224 { { MNEM, ' ', '(', OP (REGLIST_LOW), ')', 0 } },
3225 & fmt_ldm0, { 0x8c00 },
3229 /* ldm1 ($reglist_hi) */
3232 FR30_INSN_LDM1, "ldm1", "ldm1",
3233 { { MNEM, ' ', '(', OP (REGLIST_HI), ')', 0 } },
3234 & fmt_ldm1, { 0x8d00 },
3238 /* stm0 ($reglist_low) */
3241 FR30_INSN_STM0, "stm0", "stm0",
3242 { { MNEM, ' ', '(', OP (REGLIST_LOW), ')', 0 } },
3243 & fmt_stm0, { 0x8e00 },
3244 (PTR) & fmt_stm0_ops[0],
3247 /* stm1 ($reglist_hi) */
3250 FR30_INSN_STM1, "stm1", "stm1",
3251 { { MNEM, ' ', '(', OP (REGLIST_HI), ')', 0 } },
3252 & fmt_ldm1, { 0x8f00 },
3259 FR30_INSN_ENTER, "enter", "enter",
3260 { { MNEM, ' ', OP (U10), 0 } },
3261 & fmt_enter, { 0xf00 },
3262 (PTR) & fmt_enter_ops[0],
3268 FR30_INSN_LEAVE, "leave", "leave",
3270 & fmt_leave, { 0x9f90 },
3271 (PTR) & fmt_leave_ops[0],
3277 FR30_INSN_XCHB, "xchb", "xchb",
3278 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
3279 & fmt_xchb, { 0x8a00 },
3280 (PTR) & fmt_xchb_ops[0],
3289 static const CGEN_INSN_TABLE insn_table =
3291 & fr30_cgen_insn_table_entries[0],
3297 /* Formats for ALIAS macro-insns. */
3299 #define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
3301 static const CGEN_IFMT fmt_ldi8m = {
3302 16, 16, 0xf000, { F (F_OP1), F (F_I8), F (F_RI), 0 }
3305 static const CGEN_IFMT fmt_ldi20m = {
3306 16, 32, 0xff00, { F (F_OP1), F (F_I20), F (F_OP2), F (F_RI), 0 }
3309 static const CGEN_IFMT fmt_ldi32m = {
3310 16, 48, 0xfff0, { F (F_OP1), F (F_I32), F (F_OP2), F (F_OP3), F (F_RI), 0 }
3315 /* Each non-simple macro entry points to an array of expansion possibilities. */
3317 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
3318 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
3319 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
3321 /* The macro instruction table. */
3323 static const CGEN_INSN macro_insn_table_entries[] =
3328 -1, "ldi8m", "ldi8",
3329 { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
3330 & fmt_ldi8m, { 0xc000 },
3332 { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
3334 /* ldi20 $i20,$Ri */
3337 -1, "ldi20m", "ldi20",
3338 { { MNEM, ' ', OP (I20), ',', OP (RI), 0 } },
3339 & fmt_ldi20m, { 0x9b00 },
3341 { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
3343 /* ldi32 $i32,$Ri */
3346 -1, "ldi32m", "ldi32",
3347 { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
3348 & fmt_ldi32m, { 0x9f80 },
3350 { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
3358 static const CGEN_INSN_TABLE macro_insn_table =
3360 & macro_insn_table_entries[0],
3362 (sizeof (macro_insn_table_entries) /
3363 sizeof (macro_insn_table_entries[0])),
3372 /* Return non-zero if INSN is to be added to the hash table.
3373 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
3376 asm_hash_insn_p (insn)
3377 const CGEN_INSN * insn;
3379 return CGEN_ASM_HASH_P (insn);
3383 dis_hash_insn_p (insn)
3384 const CGEN_INSN * insn;
3386 /* If building the hash table and the NO-DIS attribute is present,
3388 if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
3390 return CGEN_DIS_HASH_P (insn);
3393 /* The result is the hash value of the insn.
3394 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
3397 asm_hash_insn (mnem)
3400 return CGEN_ASM_HASH (mnem);
3403 /* BUF is a pointer to the insn's bytes in target order.
3404 VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
3408 dis_hash_insn (buf, value)
3410 CGEN_INSN_INT value;
3412 return CGEN_DIS_HASH (buf, value);
3415 /* Initialize an opcode table and return a descriptor.
3416 It's much like opening a file, and must be the first function called. */
3419 fr30_cgen_opcode_open (mach, endian)
3421 enum cgen_endian endian;
3423 CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
3432 memset (table, 0, sizeof (*table));
3434 CGEN_OPCODE_MACH (table) = mach;
3435 CGEN_OPCODE_ENDIAN (table) = endian;
3436 /* FIXME: for the sparc case we can determine insn-endianness statically.
3437 The worry here is where both data and insn endian can be independently
3438 chosen, in which case this function will need another argument.
3439 Actually, will want to allow for more arguments in the future anyway. */
3440 CGEN_OPCODE_INSN_ENDIAN (table) = endian;
3442 CGEN_OPCODE_HW_LIST (table) = & fr30_cgen_hw_entries[0];
3444 CGEN_OPCODE_IFLD_TABLE (table) = & fr30_cgen_ifld_table[0];
3446 CGEN_OPCODE_OPERAND_TABLE (table) = & fr30_cgen_operand_table[0];
3448 * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
3450 * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
3452 CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
3453 CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
3454 CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
3456 CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
3457 CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
3458 CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
3460 return (CGEN_OPCODE_DESC) table;
3463 /* Close an opcode table. */
3466 fr30_cgen_opcode_close (desc)
3467 CGEN_OPCODE_DESC desc;
3472 /* Getting values from cgen_fields is handled by a collection of functions.
3473 They are distinguished by the type of the VALUE argument they return.
3474 TODO: floating point, inlining support, remove cases where result type
3478 fr30_cgen_get_int_operand (opindex, fields)
3480 const CGEN_FIELDS * fields;
3486 case FR30_OPERAND_RI :
3487 value = fields->f_Ri;
3489 case FR30_OPERAND_RJ :
3490 value = fields->f_Rj;
3492 case FR30_OPERAND_RIC :
3493 value = fields->f_Ric;
3495 case FR30_OPERAND_RJC :
3496 value = fields->f_Rjc;
3498 case FR30_OPERAND_CRI :
3499 value = fields->f_CRi;
3501 case FR30_OPERAND_CRJ :
3502 value = fields->f_CRj;
3504 case FR30_OPERAND_RS1 :
3505 value = fields->f_Rs1;
3507 case FR30_OPERAND_RS2 :
3508 value = fields->f_Rs2;
3510 case FR30_OPERAND_R13 :
3511 value = fields->f_nil;
3513 case FR30_OPERAND_R14 :
3514 value = fields->f_nil;
3516 case FR30_OPERAND_R15 :
3517 value = fields->f_nil;
3519 case FR30_OPERAND_PS :
3520 value = fields->f_nil;
3522 case FR30_OPERAND_U4 :
3523 value = fields->f_u4;
3525 case FR30_OPERAND_U4C :
3526 value = fields->f_u4c;
3528 case FR30_OPERAND_U8 :
3529 value = fields->f_u8;
3531 case FR30_OPERAND_I8 :
3532 value = fields->f_i8;
3534 case FR30_OPERAND_UDISP6 :
3535 value = fields->f_udisp6;
3537 case FR30_OPERAND_DISP8 :
3538 value = fields->f_disp8;
3540 case FR30_OPERAND_DISP9 :
3541 value = fields->f_disp9;
3543 case FR30_OPERAND_DISP10 :
3544 value = fields->f_disp10;
3546 case FR30_OPERAND_S10 :
3547 value = fields->f_s10;
3549 case FR30_OPERAND_U10 :
3550 value = fields->f_u10;
3552 case FR30_OPERAND_I32 :
3553 value = fields->f_i32;
3555 case FR30_OPERAND_M4 :
3556 value = fields->f_m4;
3558 case FR30_OPERAND_I20 :
3559 value = fields->f_i20;
3561 case FR30_OPERAND_DIR8 :
3562 value = fields->f_dir8;
3564 case FR30_OPERAND_DIR9 :
3565 value = fields->f_dir9;
3567 case FR30_OPERAND_DIR10 :
3568 value = fields->f_dir10;
3570 case FR30_OPERAND_LABEL9 :
3571 value = fields->f_rel9;
3573 case FR30_OPERAND_LABEL12 :
3574 value = fields->f_rel12;
3576 case FR30_OPERAND_REGLIST_LOW :
3577 value = fields->f_reglist_low;
3579 case FR30_OPERAND_REGLIST_HI :
3580 value = fields->f_reglist_hi;
3582 case FR30_OPERAND_CC :
3583 value = fields->f_cc;
3585 case FR30_OPERAND_CCC :
3586 value = fields->f_ccc;
3590 /* xgettext:c-format */
3591 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
3600 fr30_cgen_get_vma_operand (opindex, fields)
3602 const CGEN_FIELDS * fields;
3608 case FR30_OPERAND_RI :
3609 value = fields->f_Ri;
3611 case FR30_OPERAND_RJ :
3612 value = fields->f_Rj;
3614 case FR30_OPERAND_RIC :
3615 value = fields->f_Ric;
3617 case FR30_OPERAND_RJC :
3618 value = fields->f_Rjc;
3620 case FR30_OPERAND_CRI :
3621 value = fields->f_CRi;
3623 case FR30_OPERAND_CRJ :
3624 value = fields->f_CRj;
3626 case FR30_OPERAND_RS1 :
3627 value = fields->f_Rs1;
3629 case FR30_OPERAND_RS2 :
3630 value = fields->f_Rs2;
3632 case FR30_OPERAND_R13 :
3633 value = fields->f_nil;
3635 case FR30_OPERAND_R14 :
3636 value = fields->f_nil;
3638 case FR30_OPERAND_R15 :
3639 value = fields->f_nil;
3641 case FR30_OPERAND_PS :
3642 value = fields->f_nil;
3644 case FR30_OPERAND_U4 :
3645 value = fields->f_u4;
3647 case FR30_OPERAND_U4C :
3648 value = fields->f_u4c;
3650 case FR30_OPERAND_U8 :
3651 value = fields->f_u8;
3653 case FR30_OPERAND_I8 :
3654 value = fields->f_i8;
3656 case FR30_OPERAND_UDISP6 :
3657 value = fields->f_udisp6;
3659 case FR30_OPERAND_DISP8 :
3660 value = fields->f_disp8;
3662 case FR30_OPERAND_DISP9 :
3663 value = fields->f_disp9;
3665 case FR30_OPERAND_DISP10 :
3666 value = fields->f_disp10;
3668 case FR30_OPERAND_S10 :
3669 value = fields->f_s10;
3671 case FR30_OPERAND_U10 :
3672 value = fields->f_u10;
3674 case FR30_OPERAND_I32 :
3675 value = fields->f_i32;
3677 case FR30_OPERAND_M4 :
3678 value = fields->f_m4;
3680 case FR30_OPERAND_I20 :
3681 value = fields->f_i20;
3683 case FR30_OPERAND_DIR8 :
3684 value = fields->f_dir8;
3686 case FR30_OPERAND_DIR9 :
3687 value = fields->f_dir9;
3689 case FR30_OPERAND_DIR10 :
3690 value = fields->f_dir10;
3692 case FR30_OPERAND_LABEL9 :
3693 value = fields->f_rel9;
3695 case FR30_OPERAND_LABEL12 :
3696 value = fields->f_rel12;
3698 case FR30_OPERAND_REGLIST_LOW :
3699 value = fields->f_reglist_low;
3701 case FR30_OPERAND_REGLIST_HI :
3702 value = fields->f_reglist_hi;
3704 case FR30_OPERAND_CC :
3705 value = fields->f_cc;
3707 case FR30_OPERAND_CCC :
3708 value = fields->f_ccc;
3712 /* xgettext:c-format */
3713 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
3721 /* Stuffing values in cgen_fields is handled by a collection of functions.
3722 They are distinguished by the type of the VALUE argument they accept.
3723 TODO: floating point, inlining support, remove cases where argument type
3727 fr30_cgen_set_int_operand (opindex, fields, value)
3729 CGEN_FIELDS * fields;
3734 case FR30_OPERAND_RI :
3735 fields->f_Ri = value;
3737 case FR30_OPERAND_RJ :
3738 fields->f_Rj = value;
3740 case FR30_OPERAND_RIC :
3741 fields->f_Ric = value;
3743 case FR30_OPERAND_RJC :
3744 fields->f_Rjc = value;
3746 case FR30_OPERAND_CRI :
3747 fields->f_CRi = value;
3749 case FR30_OPERAND_CRJ :
3750 fields->f_CRj = value;
3752 case FR30_OPERAND_RS1 :
3753 fields->f_Rs1 = value;
3755 case FR30_OPERAND_RS2 :
3756 fields->f_Rs2 = value;
3758 case FR30_OPERAND_R13 :
3759 fields->f_nil = value;
3761 case FR30_OPERAND_R14 :
3762 fields->f_nil = value;
3764 case FR30_OPERAND_R15 :
3765 fields->f_nil = value;
3767 case FR30_OPERAND_PS :
3768 fields->f_nil = value;
3770 case FR30_OPERAND_U4 :
3771 fields->f_u4 = value;
3773 case FR30_OPERAND_U4C :
3774 fields->f_u4c = value;
3776 case FR30_OPERAND_U8 :
3777 fields->f_u8 = value;
3779 case FR30_OPERAND_I8 :
3780 fields->f_i8 = value;
3782 case FR30_OPERAND_UDISP6 :
3783 fields->f_udisp6 = value;
3785 case FR30_OPERAND_DISP8 :
3786 fields->f_disp8 = value;
3788 case FR30_OPERAND_DISP9 :
3789 fields->f_disp9 = value;
3791 case FR30_OPERAND_DISP10 :
3792 fields->f_disp10 = value;
3794 case FR30_OPERAND_S10 :
3795 fields->f_s10 = value;
3797 case FR30_OPERAND_U10 :
3798 fields->f_u10 = value;
3800 case FR30_OPERAND_I32 :
3801 fields->f_i32 = value;
3803 case FR30_OPERAND_M4 :
3804 fields->f_m4 = value;
3806 case FR30_OPERAND_I20 :
3807 fields->f_i20 = value;
3809 case FR30_OPERAND_DIR8 :
3810 fields->f_dir8 = value;
3812 case FR30_OPERAND_DIR9 :
3813 fields->f_dir9 = value;
3815 case FR30_OPERAND_DIR10 :
3816 fields->f_dir10 = value;
3818 case FR30_OPERAND_LABEL9 :
3819 fields->f_rel9 = value;
3821 case FR30_OPERAND_LABEL12 :
3822 fields->f_rel12 = value;
3824 case FR30_OPERAND_REGLIST_LOW :
3825 fields->f_reglist_low = value;
3827 case FR30_OPERAND_REGLIST_HI :
3828 fields->f_reglist_hi = value;
3830 case FR30_OPERAND_CC :
3831 fields->f_cc = value;
3833 case FR30_OPERAND_CCC :
3834 fields->f_ccc = value;
3838 /* xgettext:c-format */
3839 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
3846 fr30_cgen_set_vma_operand (opindex, fields, value)
3848 CGEN_FIELDS * fields;
3853 case FR30_OPERAND_RI :
3854 fields->f_Ri = value;
3856 case FR30_OPERAND_RJ :
3857 fields->f_Rj = value;
3859 case FR30_OPERAND_RIC :
3860 fields->f_Ric = value;
3862 case FR30_OPERAND_RJC :
3863 fields->f_Rjc = value;
3865 case FR30_OPERAND_CRI :
3866 fields->f_CRi = value;
3868 case FR30_OPERAND_CRJ :
3869 fields->f_CRj = value;
3871 case FR30_OPERAND_RS1 :
3872 fields->f_Rs1 = value;
3874 case FR30_OPERAND_RS2 :
3875 fields->f_Rs2 = value;
3877 case FR30_OPERAND_R13 :
3878 fields->f_nil = value;
3880 case FR30_OPERAND_R14 :
3881 fields->f_nil = value;
3883 case FR30_OPERAND_R15 :
3884 fields->f_nil = value;
3886 case FR30_OPERAND_PS :
3887 fields->f_nil = value;
3889 case FR30_OPERAND_U4 :
3890 fields->f_u4 = value;
3892 case FR30_OPERAND_U4C :
3893 fields->f_u4c = value;
3895 case FR30_OPERAND_U8 :
3896 fields->f_u8 = value;
3898 case FR30_OPERAND_I8 :
3899 fields->f_i8 = value;
3901 case FR30_OPERAND_UDISP6 :
3902 fields->f_udisp6 = value;
3904 case FR30_OPERAND_DISP8 :
3905 fields->f_disp8 = value;
3907 case FR30_OPERAND_DISP9 :
3908 fields->f_disp9 = value;
3910 case FR30_OPERAND_DISP10 :
3911 fields->f_disp10 = value;
3913 case FR30_OPERAND_S10 :
3914 fields->f_s10 = value;
3916 case FR30_OPERAND_U10 :
3917 fields->f_u10 = value;
3919 case FR30_OPERAND_I32 :
3920 fields->f_i32 = value;
3922 case FR30_OPERAND_M4 :
3923 fields->f_m4 = value;
3925 case FR30_OPERAND_I20 :
3926 fields->f_i20 = value;
3928 case FR30_OPERAND_DIR8 :
3929 fields->f_dir8 = value;
3931 case FR30_OPERAND_DIR9 :
3932 fields->f_dir9 = value;
3934 case FR30_OPERAND_DIR10 :
3935 fields->f_dir10 = value;
3937 case FR30_OPERAND_LABEL9 :
3938 fields->f_rel9 = value;
3940 case FR30_OPERAND_LABEL12 :
3941 fields->f_rel12 = value;
3943 case FR30_OPERAND_REGLIST_LOW :
3944 fields->f_reglist_low = value;
3946 case FR30_OPERAND_REGLIST_HI :
3947 fields->f_reglist_hi = value;
3949 case FR30_OPERAND_CC :
3950 fields->f_cc = value;
3952 case FR30_OPERAND_CCC :
3953 fields->f_ccc = value;
3957 /* xgettext:c-format */
3958 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),