1 /* Disassembler interface for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
4 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 - the resultant file is machine generated, cgen-dis.in isn't
7 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007,
8 2008, 2010 Free Software Foundation, Inc.
10 This file is part of libopcodes.
12 This library is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 It is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software Foundation, Inc.,
24 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
26 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
35 #include "libiberty.h"
36 #include "fr30-desc.h"
40 /* Default text to print if an instruction isn't recognized. */
41 #define UNKNOWN_INSN_MSG _("*unknown*")
43 static void print_normal
44 (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
45 static void print_address
46 (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
47 static void print_keyword
48 (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
49 static void print_insn_normal
50 (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
52 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned);
53 static int default_print_insn
54 (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
56 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
59 /* -- disassembler routines inserted here. */
63 print_register_list (void * dis_info,
66 int load_store) /* 0 == load, 1 == store. */
68 disassemble_info *info = dis_info;
80 (*info->fprintf_func) (info->stream, "r%li", reg_index + offset);
84 for (reg_index = 1; reg_index <= 7; ++reg_index)
93 (*info->fprintf_func) (info->stream, "%sr%li", comma, reg_index + offset);
100 print_hi_register_list_ld (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
103 unsigned int attrs ATTRIBUTE_UNUSED,
104 bfd_vma pc ATTRIBUTE_UNUSED,
105 int length ATTRIBUTE_UNUSED)
107 print_register_list (dis_info, value, 8, 0 /* Load. */);
111 print_low_register_list_ld (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
114 unsigned int attrs ATTRIBUTE_UNUSED,
115 bfd_vma pc ATTRIBUTE_UNUSED,
116 int length ATTRIBUTE_UNUSED)
118 print_register_list (dis_info, value, 0, 0 /* Load. */);
122 print_hi_register_list_st (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
125 unsigned int attrs ATTRIBUTE_UNUSED,
126 bfd_vma pc ATTRIBUTE_UNUSED,
127 int length ATTRIBUTE_UNUSED)
129 print_register_list (dis_info, value, 8, 1 /* Store. */);
133 print_low_register_list_st (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
136 unsigned int attrs ATTRIBUTE_UNUSED,
137 bfd_vma pc ATTRIBUTE_UNUSED,
138 int length ATTRIBUTE_UNUSED)
140 print_register_list (dis_info, value, 0, 1 /* Store. */);
144 print_m4 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
147 unsigned int attrs ATTRIBUTE_UNUSED,
148 bfd_vma pc ATTRIBUTE_UNUSED,
149 int length ATTRIBUTE_UNUSED)
151 disassemble_info *info = (disassemble_info *) dis_info;
153 (*info->fprintf_func) (info->stream, "%ld", value);
157 void fr30_cgen_print_operand
158 (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
160 /* Main entry point for printing operands.
161 XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
162 of dis-asm.h on cgen.h.
164 This function is basically just a big switch statement. Earlier versions
165 used tables to look up the function to use, but
166 - if the table contains both assembler and disassembler functions then
167 the disassembler contains much of the assembler and vice-versa,
168 - there's a lot of inlining possibilities as things grow,
169 - using a switch statement avoids the function call overhead.
171 This function could be moved into `print_insn_normal', but keeping it
172 separate makes clear the interface between `print_insn_normal' and each of
176 fr30_cgen_print_operand (CGEN_CPU_DESC cd,
180 void const *attrs ATTRIBUTE_UNUSED,
184 disassemble_info *info = (disassemble_info *) xinfo;
188 case FR30_OPERAND_CRI :
189 print_keyword (cd, info, & fr30_cgen_opval_cr_names, fields->f_CRi, 0);
191 case FR30_OPERAND_CRJ :
192 print_keyword (cd, info, & fr30_cgen_opval_cr_names, fields->f_CRj, 0);
194 case FR30_OPERAND_R13 :
195 print_keyword (cd, info, & fr30_cgen_opval_h_r13, 0, 0);
197 case FR30_OPERAND_R14 :
198 print_keyword (cd, info, & fr30_cgen_opval_h_r14, 0, 0);
200 case FR30_OPERAND_R15 :
201 print_keyword (cd, info, & fr30_cgen_opval_h_r15, 0, 0);
203 case FR30_OPERAND_RI :
204 print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Ri, 0);
206 case FR30_OPERAND_RIC :
207 print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Ric, 0);
209 case FR30_OPERAND_RJ :
210 print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Rj, 0);
212 case FR30_OPERAND_RJC :
213 print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Rjc, 0);
215 case FR30_OPERAND_RS1 :
216 print_keyword (cd, info, & fr30_cgen_opval_dr_names, fields->f_Rs1, 0);
218 case FR30_OPERAND_RS2 :
219 print_keyword (cd, info, & fr30_cgen_opval_dr_names, fields->f_Rs2, 0);
221 case FR30_OPERAND_CC :
222 print_normal (cd, info, fields->f_cc, 0, pc, length);
224 case FR30_OPERAND_CCC :
225 print_normal (cd, info, fields->f_ccc, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
227 case FR30_OPERAND_DIR10 :
228 print_normal (cd, info, fields->f_dir10, 0, pc, length);
230 case FR30_OPERAND_DIR8 :
231 print_normal (cd, info, fields->f_dir8, 0, pc, length);
233 case FR30_OPERAND_DIR9 :
234 print_normal (cd, info, fields->f_dir9, 0, pc, length);
236 case FR30_OPERAND_DISP10 :
237 print_normal (cd, info, fields->f_disp10, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
239 case FR30_OPERAND_DISP8 :
240 print_normal (cd, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
242 case FR30_OPERAND_DISP9 :
243 print_normal (cd, info, fields->f_disp9, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
245 case FR30_OPERAND_I20 :
246 print_normal (cd, info, fields->f_i20, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
248 case FR30_OPERAND_I32 :
249 print_normal (cd, info, fields->f_i32, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
251 case FR30_OPERAND_I8 :
252 print_normal (cd, info, fields->f_i8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
254 case FR30_OPERAND_LABEL12 :
255 print_address (cd, info, fields->f_rel12, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
257 case FR30_OPERAND_LABEL9 :
258 print_address (cd, info, fields->f_rel9, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
260 case FR30_OPERAND_M4 :
261 print_m4 (cd, info, fields->f_m4, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
263 case FR30_OPERAND_PS :
264 print_keyword (cd, info, & fr30_cgen_opval_h_ps, 0, 0);
266 case FR30_OPERAND_REGLIST_HI_LD :
267 print_hi_register_list_ld (cd, info, fields->f_reglist_hi_ld, 0, pc, length);
269 case FR30_OPERAND_REGLIST_HI_ST :
270 print_hi_register_list_st (cd, info, fields->f_reglist_hi_st, 0, pc, length);
272 case FR30_OPERAND_REGLIST_LOW_LD :
273 print_low_register_list_ld (cd, info, fields->f_reglist_low_ld, 0, pc, length);
275 case FR30_OPERAND_REGLIST_LOW_ST :
276 print_low_register_list_st (cd, info, fields->f_reglist_low_st, 0, pc, length);
278 case FR30_OPERAND_S10 :
279 print_normal (cd, info, fields->f_s10, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
281 case FR30_OPERAND_U10 :
282 print_normal (cd, info, fields->f_u10, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
284 case FR30_OPERAND_U4 :
285 print_normal (cd, info, fields->f_u4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
287 case FR30_OPERAND_U4C :
288 print_normal (cd, info, fields->f_u4c, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
290 case FR30_OPERAND_U8 :
291 print_normal (cd, info, fields->f_u8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
293 case FR30_OPERAND_UDISP6 :
294 print_normal (cd, info, fields->f_udisp6, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
298 /* xgettext:c-format */
299 fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
305 cgen_print_fn * const fr30_cgen_print_handlers[] =
312 fr30_cgen_init_dis (CGEN_CPU_DESC cd)
314 fr30_cgen_init_opcode_table (cd);
315 fr30_cgen_init_ibld_table (cd);
316 cd->print_handlers = & fr30_cgen_print_handlers[0];
317 cd->print_operand = fr30_cgen_print_operand;
321 /* Default print handler. */
324 print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
328 bfd_vma pc ATTRIBUTE_UNUSED,
329 int length ATTRIBUTE_UNUSED)
331 disassemble_info *info = (disassemble_info *) dis_info;
333 /* Print the operand as directed by the attributes. */
334 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
335 ; /* nothing to do */
336 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
337 (*info->fprintf_func) (info->stream, "%ld", value);
339 (*info->fprintf_func) (info->stream, "0x%lx", value);
342 /* Default address handler. */
345 print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
349 bfd_vma pc ATTRIBUTE_UNUSED,
350 int length ATTRIBUTE_UNUSED)
352 disassemble_info *info = (disassemble_info *) dis_info;
354 /* Print the operand as directed by the attributes. */
355 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
356 ; /* Nothing to do. */
357 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
358 (*info->print_address_func) (value, info);
359 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
360 (*info->print_address_func) (value, info);
361 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
362 (*info->fprintf_func) (info->stream, "%ld", (long) value);
364 (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
367 /* Keyword print handler. */
370 print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
372 CGEN_KEYWORD *keyword_table,
374 unsigned int attrs ATTRIBUTE_UNUSED)
376 disassemble_info *info = (disassemble_info *) dis_info;
377 const CGEN_KEYWORD_ENTRY *ke;
379 ke = cgen_keyword_lookup_value (keyword_table, value);
381 (*info->fprintf_func) (info->stream, "%s", ke->name);
383 (*info->fprintf_func) (info->stream, "???");
386 /* Default insn printer.
388 DIS_INFO is defined as `void *' so the disassembler needn't know anything
389 about disassemble_info. */
392 print_insn_normal (CGEN_CPU_DESC cd,
394 const CGEN_INSN *insn,
399 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
400 disassemble_info *info = (disassemble_info *) dis_info;
401 const CGEN_SYNTAX_CHAR_TYPE *syn;
403 CGEN_INIT_PRINT (cd);
405 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
407 if (CGEN_SYNTAX_MNEMONIC_P (*syn))
409 (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
412 if (CGEN_SYNTAX_CHAR_P (*syn))
414 (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
418 /* We have an operand. */
419 fr30_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
420 fields, CGEN_INSN_ATTRS (insn), pc, length);
424 /* Subroutine of print_insn. Reads an insn into the given buffers and updates
426 Returns 0 if all is well, non-zero otherwise. */
429 read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
431 disassemble_info *info,
434 CGEN_EXTRACT_INFO *ex_info,
435 unsigned long *insn_value)
437 int status = (*info->read_memory_func) (pc, buf, buflen, info);
441 (*info->memory_error_func) (status, pc, info);
445 ex_info->dis_info = info;
446 ex_info->valid = (1 << buflen) - 1;
447 ex_info->insn_bytes = buf;
449 *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
453 /* Utility to print an insn.
454 BUF is the base part of the insn, target byte order, BUFLEN bytes long.
455 The result is the size of the insn in bytes or zero for an unknown insn
456 or -1 if an error occurs fetching data (memory_error_func will have
460 print_insn (CGEN_CPU_DESC cd,
462 disassemble_info *info,
466 CGEN_INSN_INT insn_value;
467 const CGEN_INSN_LIST *insn_list;
468 CGEN_EXTRACT_INFO ex_info;
471 /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
472 basesize = cd->base_insn_bitsize < buflen * 8 ?
473 cd->base_insn_bitsize : buflen * 8;
474 insn_value = cgen_get_insn_value (cd, buf, basesize);
477 /* Fill in ex_info fields like read_insn would. Don't actually call
478 read_insn, since the incoming buffer is already read (and possibly
479 modified a la m32r). */
480 ex_info.valid = (1 << buflen) - 1;
481 ex_info.dis_info = info;
482 ex_info.insn_bytes = buf;
484 /* The instructions are stored in hash lists.
485 Pick the first one and keep trying until we find the right one. */
487 insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
488 while (insn_list != NULL)
490 const CGEN_INSN *insn = insn_list->insn;
493 unsigned long insn_value_cropped;
495 #ifdef CGEN_VALIDATE_INSN_SUPPORTED
496 /* Not needed as insn shouldn't be in hash lists if not supported. */
497 /* Supported by this cpu? */
498 if (! fr30_cgen_insn_supported (cd, insn))
500 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
505 /* Basic bit mask must be correct. */
506 /* ??? May wish to allow target to defer this check until the extract
509 /* Base size may exceed this instruction's size. Extract the
510 relevant part from the buffer. */
511 if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
512 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
513 insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
514 info->endian == BFD_ENDIAN_BIG);
516 insn_value_cropped = insn_value;
518 if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
519 == CGEN_INSN_BASE_VALUE (insn))
521 /* Printing is handled in two passes. The first pass parses the
522 machine insn and extracts the fields. The second pass prints
525 /* Make sure the entire insn is loaded into insn_value, if it
527 if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
528 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
530 unsigned long full_insn_value;
531 int rc = read_insn (cd, pc, info, buf,
532 CGEN_INSN_BITSIZE (insn) / 8,
533 & ex_info, & full_insn_value);
536 length = CGEN_EXTRACT_FN (cd, insn)
537 (cd, insn, &ex_info, full_insn_value, &fields, pc);
540 length = CGEN_EXTRACT_FN (cd, insn)
541 (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
543 /* Length < 0 -> error. */
548 CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
549 /* Length is in bits, result is in bytes. */
554 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
560 /* Default value for CGEN_PRINT_INSN.
561 The result is the size of the insn in bytes or zero for an unknown insn
562 or -1 if an error occured fetching bytes. */
564 #ifndef CGEN_PRINT_INSN
565 #define CGEN_PRINT_INSN default_print_insn
569 default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
571 bfd_byte buf[CGEN_MAX_INSN_SIZE];
575 /* Attempt to read the base part of the insn. */
576 buflen = cd->base_insn_bitsize / 8;
577 status = (*info->read_memory_func) (pc, buf, buflen, info);
579 /* Try again with the minimum part, if min < base. */
580 if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
582 buflen = cd->min_insn_bitsize / 8;
583 status = (*info->read_memory_func) (pc, buf, buflen, info);
588 (*info->memory_error_func) (status, pc, info);
592 return print_insn (cd, pc, info, buf, buflen);
596 Print one instruction from PC on INFO->STREAM.
597 Return the size of the instruction (in bytes). */
599 typedef struct cpu_desc_list
601 struct cpu_desc_list *next;
609 print_insn_fr30 (bfd_vma pc, disassemble_info *info)
611 static cpu_desc_list *cd_list = 0;
612 cpu_desc_list *cl = 0;
613 static CGEN_CPU_DESC cd = 0;
614 static CGEN_BITSET *prev_isa;
615 static int prev_mach;
616 static int prev_endian;
620 int endian = (info->endian == BFD_ENDIAN_BIG
622 : CGEN_ENDIAN_LITTLE);
623 enum bfd_architecture arch;
625 /* ??? gdb will set mach but leave the architecture as "unknown" */
626 #ifndef CGEN_BFD_ARCH
627 #define CGEN_BFD_ARCH bfd_arch_fr30
630 if (arch == bfd_arch_unknown)
631 arch = CGEN_BFD_ARCH;
633 /* There's no standard way to compute the machine or isa number
634 so we leave it to the target. */
635 #ifdef CGEN_COMPUTE_MACH
636 mach = CGEN_COMPUTE_MACH (info);
641 #ifdef CGEN_COMPUTE_ISA
643 static CGEN_BITSET *permanent_isa;
646 permanent_isa = cgen_bitset_create (MAX_ISAS);
648 cgen_bitset_clear (isa);
649 cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
652 isa = info->insn_sets;
655 /* If we've switched cpu's, try to find a handle we've used before */
657 && (cgen_bitset_compare (isa, prev_isa) != 0
659 || endian != prev_endian))
662 for (cl = cd_list; cl; cl = cl->next)
664 if (cgen_bitset_compare (cl->isa, isa) == 0 &&
666 cl->endian == endian)
675 /* If we haven't initialized yet, initialize the opcode table. */
678 const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
679 const char *mach_name;
683 mach_name = arch_type->printable_name;
685 prev_isa = cgen_bitset_copy (isa);
687 prev_endian = endian;
688 cd = fr30_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
689 CGEN_CPU_OPEN_BFDMACH, mach_name,
690 CGEN_CPU_OPEN_ENDIAN, prev_endian,
695 /* Save this away for future reference. */
696 cl = xmalloc (sizeof (struct cpu_desc_list));
704 fr30_cgen_init_dis (cd);
707 /* We try to have as much common code as possible.
708 But at this point some targets need to take over. */
709 /* ??? Some targets may need a hook elsewhere. Try to avoid this,
710 but if not possible try to move this hook elsewhere rather than
712 length = CGEN_PRINT_INSN (cd, pc, info);
718 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
719 return cd->default_insn_bitsize / 8;