1 /* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
4 THIS FILE IS MACHINE GENERATED WITH CGEN.
6 Copyright (C) 1996-2018 Free Software Foundation, Inc.
8 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
10 This file is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 It is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License along
21 with this program; if not, write to the Free Software Foundation, Inc.,
22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
32 #include "fr30-desc.h"
35 #include "libiberty.h"
40 static const CGEN_ATTR_ENTRY bool_attr[] =
47 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
49 { "base", MACH_BASE },
50 { "fr30", MACH_FR30 },
55 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
62 const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[] =
64 { "MACH", & MACH_attr[0], & MACH_attr[0] },
65 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
66 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
67 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
68 { "RESERVED", &bool_attr[0], &bool_attr[0] },
69 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
70 { "SIGNED", &bool_attr[0], &bool_attr[0] },
74 const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
76 { "MACH", & MACH_attr[0], & MACH_attr[0] },
77 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
78 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
79 { "PC", &bool_attr[0], &bool_attr[0] },
80 { "PROFILE", &bool_attr[0], &bool_attr[0] },
84 const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
86 { "MACH", & MACH_attr[0], & MACH_attr[0] },
87 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
88 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
89 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
90 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
91 { "SIGNED", &bool_attr[0], &bool_attr[0] },
92 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
93 { "RELAX", &bool_attr[0], &bool_attr[0] },
94 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
95 { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
99 const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
101 { "MACH", & MACH_attr[0], & MACH_attr[0] },
102 { "ALIAS", &bool_attr[0], &bool_attr[0] },
103 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
104 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
105 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
106 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
107 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
108 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
109 { "RELAXED", &bool_attr[0], &bool_attr[0] },
110 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
111 { "PBB", &bool_attr[0], &bool_attr[0] },
112 { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
116 /* Instruction set variants. */
118 static const CGEN_ISA fr30_cgen_isa_table[] = {
119 { "fr30", 16, 16, 16, 48 },
123 /* Machine variants. */
125 static const CGEN_MACH fr30_cgen_mach_table[] = {
126 { "fr30", "fr30", MACH_FR30, 0 },
130 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_gr_names_entries[] =
132 { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
133 { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
134 { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
135 { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
136 { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
137 { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
138 { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
139 { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
140 { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
141 { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
142 { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
143 { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
144 { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
145 { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
146 { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
147 { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
148 { "ac", 13, {0, {{{0, 0}}}}, 0, 0 },
149 { "fp", 14, {0, {{{0, 0}}}}, 0, 0 },
150 { "sp", 15, {0, {{{0, 0}}}}, 0, 0 }
153 CGEN_KEYWORD fr30_cgen_opval_gr_names =
155 & fr30_cgen_opval_gr_names_entries[0],
160 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_cr_names_entries[] =
162 { "cr0", 0, {0, {{{0, 0}}}}, 0, 0 },
163 { "cr1", 1, {0, {{{0, 0}}}}, 0, 0 },
164 { "cr2", 2, {0, {{{0, 0}}}}, 0, 0 },
165 { "cr3", 3, {0, {{{0, 0}}}}, 0, 0 },
166 { "cr4", 4, {0, {{{0, 0}}}}, 0, 0 },
167 { "cr5", 5, {0, {{{0, 0}}}}, 0, 0 },
168 { "cr6", 6, {0, {{{0, 0}}}}, 0, 0 },
169 { "cr7", 7, {0, {{{0, 0}}}}, 0, 0 },
170 { "cr8", 8, {0, {{{0, 0}}}}, 0, 0 },
171 { "cr9", 9, {0, {{{0, 0}}}}, 0, 0 },
172 { "cr10", 10, {0, {{{0, 0}}}}, 0, 0 },
173 { "cr11", 11, {0, {{{0, 0}}}}, 0, 0 },
174 { "cr12", 12, {0, {{{0, 0}}}}, 0, 0 },
175 { "cr13", 13, {0, {{{0, 0}}}}, 0, 0 },
176 { "cr14", 14, {0, {{{0, 0}}}}, 0, 0 },
177 { "cr15", 15, {0, {{{0, 0}}}}, 0, 0 }
180 CGEN_KEYWORD fr30_cgen_opval_cr_names =
182 & fr30_cgen_opval_cr_names_entries[0],
187 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_dr_names_entries[] =
189 { "tbr", 0, {0, {{{0, 0}}}}, 0, 0 },
190 { "rp", 1, {0, {{{0, 0}}}}, 0, 0 },
191 { "ssp", 2, {0, {{{0, 0}}}}, 0, 0 },
192 { "usp", 3, {0, {{{0, 0}}}}, 0, 0 },
193 { "mdh", 4, {0, {{{0, 0}}}}, 0, 0 },
194 { "mdl", 5, {0, {{{0, 0}}}}, 0, 0 }
197 CGEN_KEYWORD fr30_cgen_opval_dr_names =
199 & fr30_cgen_opval_dr_names_entries[0],
204 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
206 { "ps", 0, {0, {{{0, 0}}}}, 0, 0 }
209 CGEN_KEYWORD fr30_cgen_opval_h_ps =
211 & fr30_cgen_opval_h_ps_entries[0],
216 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
218 { "r13", 0, {0, {{{0, 0}}}}, 0, 0 }
221 CGEN_KEYWORD fr30_cgen_opval_h_r13 =
223 & fr30_cgen_opval_h_r13_entries[0],
228 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
230 { "r14", 0, {0, {{{0, 0}}}}, 0, 0 }
233 CGEN_KEYWORD fr30_cgen_opval_h_r14 =
235 & fr30_cgen_opval_h_r14_entries[0],
240 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
242 { "r15", 0, {0, {{{0, 0}}}}, 0, 0 }
245 CGEN_KEYWORD fr30_cgen_opval_h_r15 =
247 & fr30_cgen_opval_h_r15_entries[0],
253 /* The hardware table. */
255 #define A(a) (1 << CGEN_HW_##a)
257 const CGEN_HW_ENTRY fr30_cgen_hw_table[] =
259 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
260 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
261 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
262 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
263 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
264 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
265 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
266 { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
267 { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_dr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
268 { "h-ps", HW_H_PS, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, { { { (1<<MACH_BASE), 0 } } } } },
269 { "h-r13", HW_H_R13, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, { { { (1<<MACH_BASE), 0 } } } } },
270 { "h-r14", HW_H_R14, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, { { { (1<<MACH_BASE), 0 } } } } },
271 { "h-r15", HW_H_R15, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, { { { (1<<MACH_BASE), 0 } } } } },
272 { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
273 { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
274 { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
275 { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
276 { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
277 { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
278 { "h-tbit", HW_H_TBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
279 { "h-d0bit", HW_H_D0BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
280 { "h-d1bit", HW_H_D1BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
281 { "h-ccr", HW_H_CCR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
282 { "h-scr", HW_H_SCR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
283 { "h-ilm", HW_H_ILM, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
284 { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
290 /* The instruction field table. */
292 #define A(a) (1 << CGEN_IFLD_##a)
294 const CGEN_IFLD fr30_cgen_ifld_table[] =
296 { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
297 { FR30_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
298 { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
299 { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
300 { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
301 { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
302 { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
303 { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
304 { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
305 { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
306 { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
307 { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
308 { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
309 { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
310 { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
311 { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
312 { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
313 { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
314 { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
315 { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
316 { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
317 { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
318 { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
319 { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
320 { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
321 { FR30_F_I20, "f-i20", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
322 { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
323 { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
324 { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
325 { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
326 { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
327 { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
328 { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
329 { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
330 { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
331 { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
332 { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
333 { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
334 { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
335 { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
336 { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
337 { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
338 { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
345 /* multi ifield declarations */
347 const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [];
350 /* multi ifield definitions */
352 const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [] =
354 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I20_4] } },
355 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I20_16] } },
356 { 0, { (const PTR) 0 } }
359 /* The operand table. */
361 #define A(a) (1 << CGEN_OPERAND_##a)
362 #define OPERAND(op) FR30_OPERAND_##op
364 const CGEN_OPERAND fr30_cgen_operand_table[] =
366 /* pc: program counter */
367 { "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0,
368 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_NIL] } },
369 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
370 /* Ri: destination register */
371 { "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4,
372 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RI] } },
373 { 0, { { { (1<<MACH_BASE), 0 } } } } },
374 /* Rj: source register */
375 { "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4,
376 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJ] } },
377 { 0, { { { (1<<MACH_BASE), 0 } } } } },
378 /* Ric: target register coproc insn */
379 { "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4,
380 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RIC] } },
381 { 0, { { { (1<<MACH_BASE), 0 } } } } },
382 /* Rjc: source register coproc insn */
383 { "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4,
384 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJC] } },
385 { 0, { { { (1<<MACH_BASE), 0 } } } } },
386 /* CRi: coprocessor register */
387 { "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4,
388 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRI] } },
389 { 0, { { { (1<<MACH_BASE), 0 } } } } },
390 /* CRj: coprocessor register */
391 { "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4,
392 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRJ] } },
393 { 0, { { { (1<<MACH_BASE), 0 } } } } },
394 /* Rs1: dedicated register */
395 { "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4,
396 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS1] } },
397 { 0, { { { (1<<MACH_BASE), 0 } } } } },
398 /* Rs2: dedicated register */
399 { "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4,
400 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS2] } },
401 { 0, { { { (1<<MACH_BASE), 0 } } } } },
402 /* R13: General Register 13 */
403 { "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0,
404 { 0, { (const PTR) 0 } },
405 { 0, { { { (1<<MACH_BASE), 0 } } } } },
406 /* R14: General Register 14 */
407 { "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0,
408 { 0, { (const PTR) 0 } },
409 { 0, { { { (1<<MACH_BASE), 0 } } } } },
410 /* R15: General Register 15 */
411 { "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0,
412 { 0, { (const PTR) 0 } },
413 { 0, { { { (1<<MACH_BASE), 0 } } } } },
414 /* ps: Program Status register */
415 { "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0,
416 { 0, { (const PTR) 0 } },
417 { 0, { { { (1<<MACH_BASE), 0 } } } } },
418 /* u4: 4 bit unsigned immediate */
419 { "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
420 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4] } },
421 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
422 /* u4c: 4 bit unsigned immediate */
423 { "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
424 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4C] } },
425 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
426 /* u8: 8 bit unsigned immediate */
427 { "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8,
428 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U8] } },
429 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
430 /* i8: 8 bit unsigned immediate */
431 { "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8,
432 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I8] } },
433 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
434 /* udisp6: 6 bit unsigned immediate */
435 { "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4,
436 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_UDISP6] } },
437 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
438 /* disp8: 8 bit signed immediate */
439 { "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8,
440 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP8] } },
441 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
442 /* disp9: 9 bit signed immediate */
443 { "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8,
444 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP9] } },
445 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
446 /* disp10: 10 bit signed immediate */
447 { "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8,
448 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP10] } },
449 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
450 /* s10: 10 bit signed immediate */
451 { "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8,
452 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_S10] } },
453 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
454 /* u10: 10 bit unsigned immediate */
455 { "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8,
456 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U10] } },
457 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
458 /* i32: 32 bit immediate */
459 { "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32,
460 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I32] } },
461 { 0|A(HASH_PREFIX)|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
462 /* m4: 4 bit negative immediate */
463 { "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4,
464 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_M4] } },
465 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
466 /* i20: 20 bit immediate */
467 { "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20,
468 { 2, { (const PTR) &FR30_F_I20_MULTI_IFIELD[0] } },
469 { 0|A(HASH_PREFIX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
470 /* dir8: 8 bit direct address */
471 { "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8,
472 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR8] } },
473 { 0, { { { (1<<MACH_BASE), 0 } } } } },
474 /* dir9: 9 bit direct address */
475 { "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8,
476 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR9] } },
477 { 0, { { { (1<<MACH_BASE), 0 } } } } },
478 /* dir10: 10 bit direct address */
479 { "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8,
480 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR10] } },
481 { 0, { { { (1<<MACH_BASE), 0 } } } } },
482 /* label9: 9 bit pc relative address */
483 { "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8,
484 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL9] } },
485 { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
486 /* label12: 12 bit pc relative address */
487 { "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11,
488 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL12] } },
489 { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
490 /* reglist_low_ld: 8 bit low register mask for ldm */
491 { "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8,
492 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_LD] } },
493 { 0, { { { (1<<MACH_BASE), 0 } } } } },
494 /* reglist_hi_ld: 8 bit high register mask for ldm */
495 { "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8,
496 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_LD] } },
497 { 0, { { { (1<<MACH_BASE), 0 } } } } },
498 /* reglist_low_st: 8 bit low register mask for stm */
499 { "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8,
500 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_ST] } },
501 { 0, { { { (1<<MACH_BASE), 0 } } } } },
502 /* reglist_hi_st: 8 bit high register mask for stm */
503 { "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8,
504 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_ST] } },
505 { 0, { { { (1<<MACH_BASE), 0 } } } } },
506 /* cc: condition codes */
507 { "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4,
508 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CC] } },
509 { 0, { { { (1<<MACH_BASE), 0 } } } } },
510 /* ccc: coprocessor calc */
511 { "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8,
512 { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CCC] } },
513 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
514 /* nbit: negative bit */
515 { "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0,
516 { 0, { (const PTR) 0 } },
517 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
518 /* vbit: overflow bit */
519 { "vbit", FR30_OPERAND_VBIT, HW_H_VBIT, 0, 0,
520 { 0, { (const PTR) 0 } },
521 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
523 { "zbit", FR30_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
524 { 0, { (const PTR) 0 } },
525 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
526 /* cbit: carry bit */
527 { "cbit", FR30_OPERAND_CBIT, HW_H_CBIT, 0, 0,
528 { 0, { (const PTR) 0 } },
529 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
530 /* ibit: interrupt bit */
531 { "ibit", FR30_OPERAND_IBIT, HW_H_IBIT, 0, 0,
532 { 0, { (const PTR) 0 } },
533 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
534 /* sbit: stack bit */
535 { "sbit", FR30_OPERAND_SBIT, HW_H_SBIT, 0, 0,
536 { 0, { (const PTR) 0 } },
537 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
538 /* tbit: trace trap bit */
539 { "tbit", FR30_OPERAND_TBIT, HW_H_TBIT, 0, 0,
540 { 0, { (const PTR) 0 } },
541 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
542 /* d0bit: division 0 bit */
543 { "d0bit", FR30_OPERAND_D0BIT, HW_H_D0BIT, 0, 0,
544 { 0, { (const PTR) 0 } },
545 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
546 /* d1bit: division 1 bit */
547 { "d1bit", FR30_OPERAND_D1BIT, HW_H_D1BIT, 0, 0,
548 { 0, { (const PTR) 0 } },
549 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
550 /* ccr: condition code bits */
551 { "ccr", FR30_OPERAND_CCR, HW_H_CCR, 0, 0,
552 { 0, { (const PTR) 0 } },
553 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
554 /* scr: system condition bits */
555 { "scr", FR30_OPERAND_SCR, HW_H_SCR, 0, 0,
556 { 0, { (const PTR) 0 } },
557 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
558 /* ilm: interrupt level mask */
559 { "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0,
560 { 0, { (const PTR) 0 } },
561 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
564 { 0, { (const PTR) 0 } },
565 { 0, { { { (1<<MACH_BASE), 0 } } } } }
571 /* The instruction table. */
573 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
574 #define A(a) (1 << CGEN_INSN_##a)
576 static const CGEN_IBASE fr30_cgen_insn_table[MAX_INSNS] =
578 /* Special null first entry.
579 A `num' value of zero is thus invalid.
580 Also, the special `invalid' insn resides here. */
581 { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
584 FR30_INSN_ADD, "add", "add", 16,
585 { 0, { { { (1<<MACH_BASE), 0 } } } }
589 FR30_INSN_ADDI, "addi", "add", 16,
590 { 0, { { { (1<<MACH_BASE), 0 } } } }
594 FR30_INSN_ADD2, "add2", "add2", 16,
595 { 0, { { { (1<<MACH_BASE), 0 } } } }
599 FR30_INSN_ADDC, "addc", "addc", 16,
600 { 0, { { { (1<<MACH_BASE), 0 } } } }
604 FR30_INSN_ADDN, "addn", "addn", 16,
605 { 0, { { { (1<<MACH_BASE), 0 } } } }
609 FR30_INSN_ADDNI, "addni", "addn", 16,
610 { 0, { { { (1<<MACH_BASE), 0 } } } }
614 FR30_INSN_ADDN2, "addn2", "addn2", 16,
615 { 0, { { { (1<<MACH_BASE), 0 } } } }
619 FR30_INSN_SUB, "sub", "sub", 16,
620 { 0, { { { (1<<MACH_BASE), 0 } } } }
624 FR30_INSN_SUBC, "subc", "subc", 16,
625 { 0, { { { (1<<MACH_BASE), 0 } } } }
629 FR30_INSN_SUBN, "subn", "subn", 16,
630 { 0, { { { (1<<MACH_BASE), 0 } } } }
634 FR30_INSN_CMP, "cmp", "cmp", 16,
635 { 0, { { { (1<<MACH_BASE), 0 } } } }
639 FR30_INSN_CMPI, "cmpi", "cmp", 16,
640 { 0, { { { (1<<MACH_BASE), 0 } } } }
644 FR30_INSN_CMP2, "cmp2", "cmp2", 16,
645 { 0, { { { (1<<MACH_BASE), 0 } } } }
649 FR30_INSN_AND, "and", "and", 16,
650 { 0, { { { (1<<MACH_BASE), 0 } } } }
654 FR30_INSN_OR, "or", "or", 16,
655 { 0, { { { (1<<MACH_BASE), 0 } } } }
659 FR30_INSN_EOR, "eor", "eor", 16,
660 { 0, { { { (1<<MACH_BASE), 0 } } } }
664 FR30_INSN_ANDM, "andm", "and", 16,
665 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
669 FR30_INSN_ANDH, "andh", "andh", 16,
670 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
674 FR30_INSN_ANDB, "andb", "andb", 16,
675 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
679 FR30_INSN_ORM, "orm", "or", 16,
680 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
684 FR30_INSN_ORH, "orh", "orh", 16,
685 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
689 FR30_INSN_ORB, "orb", "orb", 16,
690 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
694 FR30_INSN_EORM, "eorm", "eor", 16,
695 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
699 FR30_INSN_EORH, "eorh", "eorh", 16,
700 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
704 FR30_INSN_EORB, "eorb", "eorb", 16,
705 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
709 FR30_INSN_BANDL, "bandl", "bandl", 16,
710 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
714 FR30_INSN_BORL, "borl", "borl", 16,
715 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
719 FR30_INSN_BEORL, "beorl", "beorl", 16,
720 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
724 FR30_INSN_BANDH, "bandh", "bandh", 16,
725 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
729 FR30_INSN_BORH, "borh", "borh", 16,
730 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
734 FR30_INSN_BEORH, "beorh", "beorh", 16,
735 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
739 FR30_INSN_BTSTL, "btstl", "btstl", 16,
740 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
744 FR30_INSN_BTSTH, "btsth", "btsth", 16,
745 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
749 FR30_INSN_MUL, "mul", "mul", 16,
750 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
754 FR30_INSN_MULU, "mulu", "mulu", 16,
755 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
759 FR30_INSN_MULH, "mulh", "mulh", 16,
760 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
764 FR30_INSN_MULUH, "muluh", "muluh", 16,
765 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
769 FR30_INSN_DIV0S, "div0s", "div0s", 16,
770 { 0, { { { (1<<MACH_BASE), 0 } } } }
774 FR30_INSN_DIV0U, "div0u", "div0u", 16,
775 { 0, { { { (1<<MACH_BASE), 0 } } } }
779 FR30_INSN_DIV1, "div1", "div1", 16,
780 { 0, { { { (1<<MACH_BASE), 0 } } } }
784 FR30_INSN_DIV2, "div2", "div2", 16,
785 { 0, { { { (1<<MACH_BASE), 0 } } } }
789 FR30_INSN_DIV3, "div3", "div3", 16,
790 { 0, { { { (1<<MACH_BASE), 0 } } } }
794 FR30_INSN_DIV4S, "div4s", "div4s", 16,
795 { 0, { { { (1<<MACH_BASE), 0 } } } }
799 FR30_INSN_LSL, "lsl", "lsl", 16,
800 { 0, { { { (1<<MACH_BASE), 0 } } } }
804 FR30_INSN_LSLI, "lsli", "lsl", 16,
805 { 0, { { { (1<<MACH_BASE), 0 } } } }
809 FR30_INSN_LSL2, "lsl2", "lsl2", 16,
810 { 0, { { { (1<<MACH_BASE), 0 } } } }
814 FR30_INSN_LSR, "lsr", "lsr", 16,
815 { 0, { { { (1<<MACH_BASE), 0 } } } }
819 FR30_INSN_LSRI, "lsri", "lsr", 16,
820 { 0, { { { (1<<MACH_BASE), 0 } } } }
824 FR30_INSN_LSR2, "lsr2", "lsr2", 16,
825 { 0, { { { (1<<MACH_BASE), 0 } } } }
829 FR30_INSN_ASR, "asr", "asr", 16,
830 { 0, { { { (1<<MACH_BASE), 0 } } } }
834 FR30_INSN_ASRI, "asri", "asr", 16,
835 { 0, { { { (1<<MACH_BASE), 0 } } } }
839 FR30_INSN_ASR2, "asr2", "asr2", 16,
840 { 0, { { { (1<<MACH_BASE), 0 } } } }
844 FR30_INSN_LDI8, "ldi8", "ldi:8", 16,
845 { 0, { { { (1<<MACH_BASE), 0 } } } }
847 /* ldi:20 $i20,$Ri */
849 FR30_INSN_LDI20, "ldi20", "ldi:20", 32,
850 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
852 /* ldi:32 $i32,$Ri */
854 FR30_INSN_LDI32, "ldi32", "ldi:32", 48,
855 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
859 FR30_INSN_LD, "ld", "ld", 16,
860 { 0, { { { (1<<MACH_BASE), 0 } } } }
864 FR30_INSN_LDUH, "lduh", "lduh", 16,
865 { 0, { { { (1<<MACH_BASE), 0 } } } }
869 FR30_INSN_LDUB, "ldub", "ldub", 16,
870 { 0, { { { (1<<MACH_BASE), 0 } } } }
872 /* ld @($R13,$Rj),$Ri */
874 FR30_INSN_LDR13, "ldr13", "ld", 16,
875 { 0, { { { (1<<MACH_BASE), 0 } } } }
877 /* lduh @($R13,$Rj),$Ri */
879 FR30_INSN_LDR13UH, "ldr13uh", "lduh", 16,
880 { 0, { { { (1<<MACH_BASE), 0 } } } }
882 /* ldub @($R13,$Rj),$Ri */
884 FR30_INSN_LDR13UB, "ldr13ub", "ldub", 16,
885 { 0, { { { (1<<MACH_BASE), 0 } } } }
887 /* ld @($R14,$disp10),$Ri */
889 FR30_INSN_LDR14, "ldr14", "ld", 16,
890 { 0, { { { (1<<MACH_BASE), 0 } } } }
892 /* lduh @($R14,$disp9),$Ri */
894 FR30_INSN_LDR14UH, "ldr14uh", "lduh", 16,
895 { 0, { { { (1<<MACH_BASE), 0 } } } }
897 /* ldub @($R14,$disp8),$Ri */
899 FR30_INSN_LDR14UB, "ldr14ub", "ldub", 16,
900 { 0, { { { (1<<MACH_BASE), 0 } } } }
902 /* ld @($R15,$udisp6),$Ri */
904 FR30_INSN_LDR15, "ldr15", "ld", 16,
905 { 0, { { { (1<<MACH_BASE), 0 } } } }
909 FR30_INSN_LDR15GR, "ldr15gr", "ld", 16,
910 { 0, { { { (1<<MACH_BASE), 0 } } } }
914 FR30_INSN_LDR15DR, "ldr15dr", "ld", 16,
915 { 0, { { { (1<<MACH_BASE), 0 } } } }
919 FR30_INSN_LDR15PS, "ldr15ps", "ld", 16,
920 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
924 FR30_INSN_ST, "st", "st", 16,
925 { 0, { { { (1<<MACH_BASE), 0 } } } }
929 FR30_INSN_STH, "sth", "sth", 16,
930 { 0, { { { (1<<MACH_BASE), 0 } } } }
934 FR30_INSN_STB, "stb", "stb", 16,
935 { 0, { { { (1<<MACH_BASE), 0 } } } }
937 /* st $Ri,@($R13,$Rj) */
939 FR30_INSN_STR13, "str13", "st", 16,
940 { 0, { { { (1<<MACH_BASE), 0 } } } }
942 /* sth $Ri,@($R13,$Rj) */
944 FR30_INSN_STR13H, "str13h", "sth", 16,
945 { 0, { { { (1<<MACH_BASE), 0 } } } }
947 /* stb $Ri,@($R13,$Rj) */
949 FR30_INSN_STR13B, "str13b", "stb", 16,
950 { 0, { { { (1<<MACH_BASE), 0 } } } }
952 /* st $Ri,@($R14,$disp10) */
954 FR30_INSN_STR14, "str14", "st", 16,
955 { 0, { { { (1<<MACH_BASE), 0 } } } }
957 /* sth $Ri,@($R14,$disp9) */
959 FR30_INSN_STR14H, "str14h", "sth", 16,
960 { 0, { { { (1<<MACH_BASE), 0 } } } }
962 /* stb $Ri,@($R14,$disp8) */
964 FR30_INSN_STR14B, "str14b", "stb", 16,
965 { 0, { { { (1<<MACH_BASE), 0 } } } }
967 /* st $Ri,@($R15,$udisp6) */
969 FR30_INSN_STR15, "str15", "st", 16,
970 { 0, { { { (1<<MACH_BASE), 0 } } } }
974 FR30_INSN_STR15GR, "str15gr", "st", 16,
975 { 0, { { { (1<<MACH_BASE), 0 } } } }
979 FR30_INSN_STR15DR, "str15dr", "st", 16,
980 { 0, { { { (1<<MACH_BASE), 0 } } } }
984 FR30_INSN_STR15PS, "str15ps", "st", 16,
985 { 0, { { { (1<<MACH_BASE), 0 } } } }
989 FR30_INSN_MOV, "mov", "mov", 16,
990 { 0, { { { (1<<MACH_BASE), 0 } } } }
994 FR30_INSN_MOVDR, "movdr", "mov", 16,
995 { 0, { { { (1<<MACH_BASE), 0 } } } }
999 FR30_INSN_MOVPS, "movps", "mov", 16,
1000 { 0, { { { (1<<MACH_BASE), 0 } } } }
1004 FR30_INSN_MOV2DR, "mov2dr", "mov", 16,
1005 { 0, { { { (1<<MACH_BASE), 0 } } } }
1009 FR30_INSN_MOV2PS, "mov2ps", "mov", 16,
1010 { 0, { { { (1<<MACH_BASE), 0 } } } }
1014 FR30_INSN_JMP, "jmp", "jmp", 16,
1015 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1019 FR30_INSN_JMPD, "jmpd", "jmp:d", 16,
1020 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1024 FR30_INSN_CALLR, "callr", "call", 16,
1025 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1029 FR30_INSN_CALLRD, "callrd", "call:d", 16,
1030 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1034 FR30_INSN_CALL, "call", "call", 16,
1035 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1037 /* call:d $label12 */
1039 FR30_INSN_CALLD, "calld", "call:d", 16,
1040 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1044 FR30_INSN_RET, "ret", "ret", 16,
1045 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1049 FR30_INSN_RET_D, "ret:d", "ret:d", 16,
1050 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1054 FR30_INSN_INT, "int", "int", 16,
1055 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1059 FR30_INSN_INTE, "inte", "inte", 16,
1060 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1064 FR30_INSN_RETI, "reti", "reti", 16,
1065 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1069 FR30_INSN_BRAD, "brad", "bra:d", 16,
1070 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1074 FR30_INSN_BRA, "bra", "bra", 16,
1075 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1079 FR30_INSN_BNOD, "bnod", "bno:d", 16,
1080 { 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1084 FR30_INSN_BNO, "bno", "bno", 16,
1085 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1089 FR30_INSN_BEQD, "beqd", "beq:d", 16,
1090 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1094 FR30_INSN_BEQ, "beq", "beq", 16,
1095 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1099 FR30_INSN_BNED, "bned", "bne:d", 16,
1100 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1104 FR30_INSN_BNE, "bne", "bne", 16,
1105 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1109 FR30_INSN_BCD, "bcd", "bc:d", 16,
1110 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1114 FR30_INSN_BC, "bc", "bc", 16,
1115 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1119 FR30_INSN_BNCD, "bncd", "bnc:d", 16,
1120 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1124 FR30_INSN_BNC, "bnc", "bnc", 16,
1125 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1129 FR30_INSN_BND, "bnd", "bn:d", 16,
1130 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1134 FR30_INSN_BN, "bn", "bn", 16,
1135 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1139 FR30_INSN_BPD, "bpd", "bp:d", 16,
1140 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1144 FR30_INSN_BP, "bp", "bp", 16,
1145 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1149 FR30_INSN_BVD, "bvd", "bv:d", 16,
1150 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1154 FR30_INSN_BV, "bv", "bv", 16,
1155 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1159 FR30_INSN_BNVD, "bnvd", "bnv:d", 16,
1160 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1164 FR30_INSN_BNV, "bnv", "bnv", 16,
1165 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1169 FR30_INSN_BLTD, "bltd", "blt:d", 16,
1170 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1174 FR30_INSN_BLT, "blt", "blt", 16,
1175 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1179 FR30_INSN_BGED, "bged", "bge:d", 16,
1180 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1184 FR30_INSN_BGE, "bge", "bge", 16,
1185 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1189 FR30_INSN_BLED, "bled", "ble:d", 16,
1190 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1194 FR30_INSN_BLE, "ble", "ble", 16,
1195 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1199 FR30_INSN_BGTD, "bgtd", "bgt:d", 16,
1200 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1204 FR30_INSN_BGT, "bgt", "bgt", 16,
1205 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1209 FR30_INSN_BLSD, "blsd", "bls:d", 16,
1210 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1214 FR30_INSN_BLS, "bls", "bls", 16,
1215 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1219 FR30_INSN_BHID, "bhid", "bhi:d", 16,
1220 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1224 FR30_INSN_BHI, "bhi", "bhi", 16,
1225 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1227 /* dmov $R13,@$dir10 */
1229 FR30_INSN_DMOVR13, "dmovr13", "dmov", 16,
1230 { 0, { { { (1<<MACH_BASE), 0 } } } }
1232 /* dmovh $R13,@$dir9 */
1234 FR30_INSN_DMOVR13H, "dmovr13h", "dmovh", 16,
1235 { 0, { { { (1<<MACH_BASE), 0 } } } }
1237 /* dmovb $R13,@$dir8 */
1239 FR30_INSN_DMOVR13B, "dmovr13b", "dmovb", 16,
1240 { 0, { { { (1<<MACH_BASE), 0 } } } }
1242 /* dmov @$R13+,@$dir10 */
1244 FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov", 16,
1245 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1247 /* dmovh @$R13+,@$dir9 */
1249 FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh", 16,
1250 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1252 /* dmovb @$R13+,@$dir8 */
1254 FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb", 16,
1255 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1257 /* dmov @$R15+,@$dir10 */
1259 FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov", 16,
1260 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1262 /* dmov @$dir10,$R13 */
1264 FR30_INSN_DMOV2R13, "dmov2r13", "dmov", 16,
1265 { 0, { { { (1<<MACH_BASE), 0 } } } }
1267 /* dmovh @$dir9,$R13 */
1269 FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh", 16,
1270 { 0, { { { (1<<MACH_BASE), 0 } } } }
1272 /* dmovb @$dir8,$R13 */
1274 FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb", 16,
1275 { 0, { { { (1<<MACH_BASE), 0 } } } }
1277 /* dmov @$dir10,@$R13+ */
1279 FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov", 16,
1280 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1282 /* dmovh @$dir9,@$R13+ */
1284 FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh", 16,
1285 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1287 /* dmovb @$dir8,@$R13+ */
1289 FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb", 16,
1290 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1292 /* dmov @$dir10,@-$R15 */
1294 FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov", 16,
1295 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1297 /* ldres @$Ri+,$u4 */
1299 FR30_INSN_LDRES, "ldres", "ldres", 16,
1300 { 0, { { { (1<<MACH_BASE), 0 } } } }
1302 /* stres $u4,@$Ri+ */
1304 FR30_INSN_STRES, "stres", "stres", 16,
1305 { 0, { { { (1<<MACH_BASE), 0 } } } }
1307 /* copop $u4c,$ccc,$CRj,$CRi */
1309 FR30_INSN_COPOP, "copop", "copop", 32,
1310 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1312 /* copld $u4c,$ccc,$Rjc,$CRi */
1314 FR30_INSN_COPLD, "copld", "copld", 32,
1315 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1317 /* copst $u4c,$ccc,$CRj,$Ric */
1319 FR30_INSN_COPST, "copst", "copst", 32,
1320 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1322 /* copsv $u4c,$ccc,$CRj,$Ric */
1324 FR30_INSN_COPSV, "copsv", "copsv", 32,
1325 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1329 FR30_INSN_NOP, "nop", "nop", 16,
1330 { 0, { { { (1<<MACH_BASE), 0 } } } }
1334 FR30_INSN_ANDCCR, "andccr", "andccr", 16,
1335 { 0, { { { (1<<MACH_BASE), 0 } } } }
1339 FR30_INSN_ORCCR, "orccr", "orccr", 16,
1340 { 0, { { { (1<<MACH_BASE), 0 } } } }
1344 FR30_INSN_STILM, "stilm", "stilm", 16,
1345 { 0, { { { (1<<MACH_BASE), 0 } } } }
1349 FR30_INSN_ADDSP, "addsp", "addsp", 16,
1350 { 0, { { { (1<<MACH_BASE), 0 } } } }
1354 FR30_INSN_EXTSB, "extsb", "extsb", 16,
1355 { 0, { { { (1<<MACH_BASE), 0 } } } }
1359 FR30_INSN_EXTUB, "extub", "extub", 16,
1360 { 0, { { { (1<<MACH_BASE), 0 } } } }
1364 FR30_INSN_EXTSH, "extsh", "extsh", 16,
1365 { 0, { { { (1<<MACH_BASE), 0 } } } }
1369 FR30_INSN_EXTUH, "extuh", "extuh", 16,
1370 { 0, { { { (1<<MACH_BASE), 0 } } } }
1372 /* ldm0 ($reglist_low_ld) */
1374 FR30_INSN_LDM0, "ldm0", "ldm0", 16,
1375 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1377 /* ldm1 ($reglist_hi_ld) */
1379 FR30_INSN_LDM1, "ldm1", "ldm1", 16,
1380 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1382 /* stm0 ($reglist_low_st) */
1384 FR30_INSN_STM0, "stm0", "stm0", 16,
1385 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1387 /* stm1 ($reglist_hi_st) */
1389 FR30_INSN_STM1, "stm1", "stm1", 16,
1390 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1394 FR30_INSN_ENTER, "enter", "enter", 16,
1395 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1399 FR30_INSN_LEAVE, "leave", "leave", 16,
1400 { 0, { { { (1<<MACH_BASE), 0 } } } }
1404 FR30_INSN_XCHB, "xchb", "xchb", 16,
1405 { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
1412 /* Initialize anything needed to be done once, before any cpu_open call. */
1419 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
1420 static void build_hw_table (CGEN_CPU_TABLE *);
1421 static void build_ifield_table (CGEN_CPU_TABLE *);
1422 static void build_operand_table (CGEN_CPU_TABLE *);
1423 static void build_insn_table (CGEN_CPU_TABLE *);
1424 static void fr30_cgen_rebuild_tables (CGEN_CPU_TABLE *);
1426 /* Subroutine of fr30_cgen_cpu_open to look up a mach via its bfd name. */
1428 static const CGEN_MACH *
1429 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
1433 if (strcmp (name, table->bfd_name) == 0)
1440 /* Subroutine of fr30_cgen_cpu_open to build the hardware table. */
1443 build_hw_table (CGEN_CPU_TABLE *cd)
1446 int machs = cd->machs;
1447 const CGEN_HW_ENTRY *init = & fr30_cgen_hw_table[0];
1448 /* MAX_HW is only an upper bound on the number of selected entries.
1449 However each entry is indexed by it's enum so there can be holes in
1451 const CGEN_HW_ENTRY **selected =
1452 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1454 cd->hw_table.init_entries = init;
1455 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1456 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1457 /* ??? For now we just use machs to determine which ones we want. */
1458 for (i = 0; init[i].name != NULL; ++i)
1459 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1461 selected[init[i].type] = &init[i];
1462 cd->hw_table.entries = selected;
1463 cd->hw_table.num_entries = MAX_HW;
1466 /* Subroutine of fr30_cgen_cpu_open to build the hardware table. */
1469 build_ifield_table (CGEN_CPU_TABLE *cd)
1471 cd->ifld_table = & fr30_cgen_ifld_table[0];
1474 /* Subroutine of fr30_cgen_cpu_open to build the hardware table. */
1477 build_operand_table (CGEN_CPU_TABLE *cd)
1480 int machs = cd->machs;
1481 const CGEN_OPERAND *init = & fr30_cgen_operand_table[0];
1482 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1483 However each entry is indexed by it's enum so there can be holes in
1485 const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
1487 cd->operand_table.init_entries = init;
1488 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1489 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1490 /* ??? For now we just use mach to determine which ones we want. */
1491 for (i = 0; init[i].name != NULL; ++i)
1492 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1494 selected[init[i].type] = &init[i];
1495 cd->operand_table.entries = selected;
1496 cd->operand_table.num_entries = MAX_OPERANDS;
1499 /* Subroutine of fr30_cgen_cpu_open to build the hardware table.
1500 ??? This could leave out insns not supported by the specified mach/isa,
1501 but that would cause errors like "foo only supported by bar" to become
1502 "unknown insn", so for now we include all insns and require the app to
1503 do the checking later.
1504 ??? On the other hand, parsing of such insns may require their hardware or
1505 operand elements to be in the table [which they mightn't be]. */
1508 build_insn_table (CGEN_CPU_TABLE *cd)
1511 const CGEN_IBASE *ib = & fr30_cgen_insn_table[0];
1512 CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1514 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1515 for (i = 0; i < MAX_INSNS; ++i)
1516 insns[i].base = &ib[i];
1517 cd->insn_table.init_entries = insns;
1518 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1519 cd->insn_table.num_init_entries = MAX_INSNS;
1522 /* Subroutine of fr30_cgen_cpu_open to rebuild the tables. */
1525 fr30_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
1528 CGEN_BITSET *isas = cd->isas;
1529 unsigned int machs = cd->machs;
1531 cd->int_insn_p = CGEN_INT_INSN_P;
1533 /* Data derived from the isa spec. */
1534 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
1535 cd->default_insn_bitsize = UNSET;
1536 cd->base_insn_bitsize = UNSET;
1537 cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
1538 cd->max_insn_bitsize = 0;
1539 for (i = 0; i < MAX_ISAS; ++i)
1540 if (cgen_bitset_contains (isas, i))
1542 const CGEN_ISA *isa = & fr30_cgen_isa_table[i];
1544 /* Default insn sizes of all selected isas must be
1545 equal or we set the result to 0, meaning "unknown". */
1546 if (cd->default_insn_bitsize == UNSET)
1547 cd->default_insn_bitsize = isa->default_insn_bitsize;
1548 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1551 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1553 /* Base insn sizes of all selected isas must be equal
1554 or we set the result to 0, meaning "unknown". */
1555 if (cd->base_insn_bitsize == UNSET)
1556 cd->base_insn_bitsize = isa->base_insn_bitsize;
1557 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1560 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1562 /* Set min,max insn sizes. */
1563 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1564 cd->min_insn_bitsize = isa->min_insn_bitsize;
1565 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1566 cd->max_insn_bitsize = isa->max_insn_bitsize;
1569 /* Data derived from the mach spec. */
1570 for (i = 0; i < MAX_MACHS; ++i)
1571 if (((1 << i) & machs) != 0)
1573 const CGEN_MACH *mach = & fr30_cgen_mach_table[i];
1575 if (mach->insn_chunk_bitsize != 0)
1577 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1579 fprintf (stderr, "fr30_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
1580 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1584 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1588 /* Determine which hw elements are used by MACH. */
1589 build_hw_table (cd);
1591 /* Build the ifield table. */
1592 build_ifield_table (cd);
1594 /* Determine which operands are used by MACH/ISA. */
1595 build_operand_table (cd);
1597 /* Build the instruction table. */
1598 build_insn_table (cd);
1601 /* Initialize a cpu table and return a descriptor.
1602 It's much like opening a file, and must be the first function called.
1603 The arguments are a set of (type/value) pairs, terminated with
1606 Currently supported values:
1607 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
1608 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
1609 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1610 CGEN_CPU_OPEN_ENDIAN: specify endian choice
1611 CGEN_CPU_OPEN_END: terminates arguments
1613 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1617 fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1619 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1621 CGEN_BITSET *isas = 0; /* 0 = "unspecified" */
1622 unsigned int machs = 0; /* 0 = "unspecified" */
1623 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1632 memset (cd, 0, sizeof (*cd));
1634 va_start (ap, arg_type);
1635 while (arg_type != CGEN_CPU_OPEN_END)
1639 case CGEN_CPU_OPEN_ISAS :
1640 isas = va_arg (ap, CGEN_BITSET *);
1642 case CGEN_CPU_OPEN_MACHS :
1643 machs = va_arg (ap, unsigned int);
1645 case CGEN_CPU_OPEN_BFDMACH :
1647 const char *name = va_arg (ap, const char *);
1648 const CGEN_MACH *mach =
1649 lookup_mach_via_bfd_name (fr30_cgen_mach_table, name);
1652 machs |= 1 << mach->num;
1655 case CGEN_CPU_OPEN_ENDIAN :
1656 endian = va_arg (ap, enum cgen_endian);
1659 fprintf (stderr, "fr30_cgen_cpu_open: unsupported argument `%d'\n",
1661 abort (); /* ??? return NULL? */
1663 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1667 /* Mach unspecified means "all". */
1669 machs = (1 << MAX_MACHS) - 1;
1670 /* Base mach is always selected. */
1672 if (endian == CGEN_ENDIAN_UNKNOWN)
1674 /* ??? If target has only one, could have a default. */
1675 fprintf (stderr, "fr30_cgen_cpu_open: no endianness specified\n");
1679 cd->isas = cgen_bitset_copy (isas);
1681 cd->endian = endian;
1682 /* FIXME: for the sparc case we can determine insn-endianness statically.
1683 The worry here is where both data and insn endian can be independently
1684 chosen, in which case this function will need another argument.
1685 Actually, will want to allow for more arguments in the future anyway. */
1686 cd->insn_endian = endian;
1688 /* Table (re)builder. */
1689 cd->rebuild_tables = fr30_cgen_rebuild_tables;
1690 fr30_cgen_rebuild_tables (cd);
1692 /* Default to not allowing signed overflow. */
1693 cd->signed_overflow_ok_p = 0;
1695 return (CGEN_CPU_DESC) cd;
1698 /* Cover fn to fr30_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1699 MACH_NAME is the bfd name of the mach. */
1702 fr30_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
1704 return fr30_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1705 CGEN_CPU_OPEN_ENDIAN, endian,
1709 /* Close a cpu table.
1710 ??? This can live in a machine independent file, but there's currently
1711 no place to put this file (there's no libcgen). libopcodes is the wrong
1712 place as some simulator ports use this but they don't use libopcodes. */
1715 fr30_cgen_cpu_close (CGEN_CPU_DESC cd)
1718 const CGEN_INSN *insns;
1720 if (cd->macro_insn_table.init_entries)
1722 insns = cd->macro_insn_table.init_entries;
1723 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
1724 if (CGEN_INSN_RX ((insns)))
1725 regfree (CGEN_INSN_RX (insns));
1728 if (cd->insn_table.init_entries)
1730 insns = cd->insn_table.init_entries;
1731 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
1732 if (CGEN_INSN_RX (insns))
1733 regfree (CGEN_INSN_RX (insns));
1736 if (cd->macro_insn_table.init_entries)
1737 free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
1739 if (cd->insn_table.init_entries)
1740 free ((CGEN_INSN *) cd->insn_table.init_entries);
1742 if (cd->hw_table.entries)
1743 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1745 if (cd->operand_table.entries)
1746 free ((CGEN_HW_ENTRY *) cd->operand_table.entries);