1 /* Disassemble D10V instructions.
2 Copyright 1996, 1997, 1998, 2000, 2001, 2005 Free Software Foundation, Inc.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
17 MA 02110-1301, USA. */
22 #include "opcode/d10v.h"
25 /* The PC wraps at 18 bits, except for the segment number,
26 so use this mask to keep the parts we want. */
27 #define PC_MASK 0x0303FFFF
30 print_operand (struct d10v_operand *oper,
32 struct d10v_opcode *op,
34 struct disassemble_info *info)
38 if (oper->flags == OPERAND_ATMINUS)
40 (*info->fprintf_func) (info->stream, "@-");
43 if (oper->flags == OPERAND_MINUS)
45 (*info->fprintf_func) (info->stream, "-");
48 if (oper->flags == OPERAND_PLUS)
50 (*info->fprintf_func) (info->stream, "+");
53 if (oper->flags == OPERAND_ATSIGN)
55 (*info->fprintf_func) (info->stream, "@");
58 if (oper->flags == OPERAND_ATPAR)
60 (*info->fprintf_func) (info->stream, "@(");
66 /* The LONG_L format shifts registers over by 15. */
67 if (op->format == LONG_L && (oper->flags & OPERAND_REG))
70 num = (insn >> shift) & (0x7FFFFFFF >> (31 - oper->bits));
72 if (oper->flags & OPERAND_REG)
78 & (OPERAND_GPR | OPERAND_FFLAG | OPERAND_CFLAG | OPERAND_CONTROL));
79 if (oper->flags & (OPERAND_ACC0 | OPERAND_ACC1))
80 num += num ? OPERAND_ACC1 : OPERAND_ACC0;
81 for (i = 0; i < d10v_reg_name_cnt (); i++)
83 if (num == (d10v_predefined_registers[i].value & ~ OPERAND_SP))
85 if (d10v_predefined_registers[i].pname)
86 (*info->fprintf_func) (info->stream, "%s",
87 d10v_predefined_registers[i].pname);
89 (*info->fprintf_func) (info->stream, "%s",
90 d10v_predefined_registers[i].name);
97 /* This would only get executed if a register was not in the
99 if (oper->flags & (OPERAND_ACC0 | OPERAND_ACC1))
100 (*info->fprintf_func) (info->stream, "a");
101 else if (oper->flags & OPERAND_CONTROL)
102 (*info->fprintf_func) (info->stream, "cr");
103 else if (oper->flags & OPERAND_REG)
104 (*info->fprintf_func) (info->stream, "r");
105 (*info->fprintf_func) (info->stream, "%d", num & REGISTER_MASK);
110 /* Addresses are right-shifted by 2. */
111 if (oper->flags & OPERAND_ADDR)
116 max = (1 << (oper->bits - 1));
119 num = -num & ((1 << oper->bits) - 1);
123 if (info->flags & INSN_HAS_RELOC)
124 (*info->print_address_func) (num & PC_MASK, info);
128 (*info->print_address_func) ((memaddr - num) & PC_MASK, info);
130 (*info->print_address_func) ((memaddr + num) & PC_MASK, info);
135 if (oper->flags & OPERAND_SIGNED)
137 int max = (1 << (oper->bits - 1));
140 num = -num & ((1 << oper->bits) - 1);
141 (*info->fprintf_func) (info->stream, "-");
144 (*info->fprintf_func) (info->stream, "0x%x", num);
150 dis_long (unsigned long insn,
152 struct disassemble_info *info)
155 struct d10v_opcode *op = (struct d10v_opcode *) d10v_opcodes;
156 struct d10v_operand *oper;
162 if ((op->format & LONG_OPCODE)
163 && ((op->mask & insn) == (unsigned long) op->opcode))
166 (*info->fprintf_func) (info->stream, "%s\t", op->name);
168 for (i = 0; op->operands[i]; i++)
170 oper = (struct d10v_operand *) &d10v_operands[op->operands[i]];
171 if (oper->flags == OPERAND_ATPAR)
173 print_operand (oper, insn, op, memaddr, info);
174 if (op->operands[i + 1] && oper->bits
175 && d10v_operands[op->operands[i + 1]].flags != OPERAND_PLUS
176 && d10v_operands[op->operands[i + 1]].flags != OPERAND_MINUS)
177 (*info->fprintf_func) (info->stream, ", ");
185 (*info->fprintf_func) (info->stream, ".long\t0x%08lx", insn);
188 (*info->fprintf_func) (info->stream, ")");
192 dis_2_short (unsigned long insn,
194 struct disassemble_info *info,
199 struct d10v_opcode *op;
200 int match, num_match = 0;
201 struct d10v_operand *oper;
204 ins[0] = (insn & 0x3FFFFFFF) >> 15;
205 ins[1] = insn & 0x00007FFF;
207 for (j = 0; j < 2; j++)
209 op = (struct d10v_opcode *) d10v_opcodes;
213 if ((op->format & SHORT_OPCODE)
214 && ((((unsigned int) op->mask) & ins[j])
215 == (unsigned int) op->opcode))
217 (*info->fprintf_func) (info->stream, "%s\t", op->name);
218 for (i = 0; op->operands[i]; i++)
220 oper = (struct d10v_operand *) &d10v_operands[op->operands[i]];
221 if (oper->flags == OPERAND_ATPAR)
223 print_operand (oper, ins[j], op, memaddr, info);
224 if (op->operands[i + 1] && oper->bits
225 && d10v_operands[op->operands[i + 1]].flags != OPERAND_PLUS
226 && d10v_operands[op->operands[i + 1]].flags != OPERAND_MINUS)
227 (*info->fprintf_func) (info->stream, ", ");
236 (*info->fprintf_func) (info->stream, "unknown");
241 (*info->fprintf_func) (info->stream, "\t->\t");
245 (*info->fprintf_func) (info->stream, "\t<-\t");
249 (*info->fprintf_func) (info->stream, "\t||\t");
258 (*info->fprintf_func) (info->stream, ".long\t0x%08lx", insn);
261 (*info->fprintf_func) (info->stream, ")");
265 print_insn_d10v (bfd_vma memaddr, struct disassemble_info *info)
271 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
274 (*info->memory_error_func) (status, memaddr, info);
277 insn = bfd_getb32 (buffer);
279 status = insn & FM11;
283 dis_2_short (insn, memaddr, info, 2);
286 dis_2_short (insn, memaddr, info, 0);
289 dis_2_short (insn, memaddr, info, 1);
292 dis_long (insn, memaddr, info);