opcodes/arm-dis.c

   1 /* Instruction printing code for the ARM
   2    Copyright (C) 1994-2015 Free Software Foundation, Inc.
   3    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
   4    Modification by James G. Smith (jsmith@cygnus.co.uk)
   5
   6    This file is part of libopcodes.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include "sysdep.h"
  24
  25 #include "dis-asm.h"
  26 #include "opcode/arm.h"
  27 #include "opintl.h"
  28 #include "safe-ctype.h"
  29 #include "floatformat.h"
  30
  31 /* FIXME: This shouldn't be done here.  */
  32 #include "coff/internal.h"
  33 #include "libcoff.h"
  34 #include "elf-bfd.h"
  35 #include "elf/internal.h"
  36 #include "elf/arm.h"
  37
  38 /* FIXME: Belongs in global header.  */
  39 #ifndef strneq
  40 #define strneq(a,b,n)   (strncmp ((a), (b), (n)) == 0)
  41 #endif
  42
  43 #ifndef NUM_ELEM
  44 #define NUM_ELEM(a)     (sizeof (a) / sizeof (a)[0])
  45 #endif
  46
  47 /* Cached mapping symbol state.  */
  48 enum map_type
  49 {
  50   MAP_ARM,
  51   MAP_THUMB,
  52   MAP_DATA
  53 };
  54
  55 struct arm_private_data
  56 {
  57   /* The features to use when disassembling optional instructions.  */
  58   arm_feature_set features;
  59
  60   /* Whether any mapping symbols are present in the provided symbol
  61      table.  -1 if we do not know yet, otherwise 0 or 1.  */
  62   int has_mapping_symbols;
  63
  64   /* Track the last type (although this doesn't seem to be useful) */
  65   enum map_type last_type;
  66
  67   /* Tracking symbol table information */
  68   int last_mapping_sym;
  69   bfd_vma last_mapping_addr;
  70 };
  71
  72 struct opcode32
  73 {
  74   arm_feature_set arch;         /* Architecture defining this insn.  */
  75   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
  76   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
  77   const char *  assembler;      /* How to disassemble this insn.  */
  78 };
  79
  80 struct opcode16
  81 {
  82   arm_feature_set arch;         /* Architecture defining this insn.  */
  83   unsigned short value, mask;   /* Recognise insn if (op & mask) == value.  */
  84   const char *assembler;        /* How to disassemble this insn.  */
  85 };
  86
  87 /* print_insn_coprocessor recognizes the following format control codes:
  88
  89    %%                   %
  90
  91    %c                   print condition code (always bits 28-31 in ARM mode)
  92    %q                   print shifter argument
  93    %u                   print condition code (unconditional in ARM mode,
  94                           UNPREDICTABLE if not AL in Thumb)
  95    %A                   print address for ldc/stc/ldf/stf instruction
  96    %B                   print vstm/vldm register list
  97    %I                   print cirrus signed shift immediate: bits 0..3|4..6
  98    %F                   print the COUNT field of a LFM/SFM instruction.
  99    %P                   print floating point precision in arithmetic insn
 100    %Q                   print floating point precision in ldf/stf insn
 101    %R                   print floating point rounding mode
 102
 103    %<bitfield>c         print as a condition code (for vsel)
 104    %<bitfield>r         print as an ARM register
 105    %<bitfield>R         as %<>r but r15 is UNPREDICTABLE
 106    %<bitfield>ru        as %<>r but each u register must be unique.
 107    %<bitfield>d         print the bitfield in decimal
 108    %<bitfield>k         print immediate for VFPv3 conversion instruction
 109    %<bitfield>x         print the bitfield in hex
 110    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
 111    %<bitfield>f         print a floating point constant if >7 else a
 112                         floating point register
 113    %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
 114    %<bitfield>g         print as an iWMMXt 64-bit register
 115    %<bitfield>G         print as an iWMMXt general purpose or control register
 116    %<bitfield>D         print as a NEON D register
 117    %<bitfield>Q         print as a NEON Q register
 118
 119    %y<code>             print a single precision VFP reg.
 120                           Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
 121    %z<code>             print a double precision VFP reg
 122                           Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
 123
 124    %<bitfield>'c        print specified char iff bitfield is all ones
 125    %<bitfield>`c        print specified char iff bitfield is all zeroes
 126    %<bitfield>?ab...    select from array of values in big endian order
 127
 128    %L                   print as an iWMMXt N/M width field.
 129    %Z                   print the Immediate of a WSHUFH instruction.
 130    %l                   like 'A' except use byte offsets for 'B' & 'H'
 131                         versions.
 132    %i                   print 5-bit immediate in bits 8,3..0
 133                         (print "32" when 0)
 134    %r                   print register offset address for wldt/wstr instruction.  */
 135
 136 enum opcode_sentinel_enum
 137 {
 138   SENTINEL_IWMMXT_START = 1,
 139   SENTINEL_IWMMXT_END,
 140   SENTINEL_GENERIC_START
 141 } opcode_sentinels;
 142
 143 #define UNDEFINED_INSTRUCTION      "\t\t; <UNDEFINED> instruction: %0-31x"
 144 #define UNPREDICTABLE_INSTRUCTION  "\t; <UNPREDICTABLE>"
 145
 146 /* Common coprocessor opcodes shared between Arm and Thumb-2.  */
 147
 148 static const struct opcode32 coprocessor_opcodes[] =
 149 {
 150   /* XScale instructions.  */
 151   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 152     0x0e200010, 0x0fff0ff0,
 153     "mia%c\tacc0, %0-3r, %12-15r"},
 154   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 155     0x0e280010, 0x0fff0ff0,
 156     "miaph%c\tacc0, %0-3r, %12-15r"},
 157   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 158     0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
 159   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 160     0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
 161   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 162     0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
 163
 164   /* Intel Wireless MMX technology instructions.  */
 165   {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
 166   {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
 167     0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
 168   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 169     0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
 170   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 171     0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
 172   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 173     0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
 174   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 175     0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
 176   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 177     0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
 178   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 179     0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
 180   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 181     0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
 182   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 183     0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
 184   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 185     0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
 186   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 187     0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
 188   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 189     0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
 190   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 191     0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
 192   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 193     0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
 194   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 195     0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
 196   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 197     0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
 198   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 199     0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
 200   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 201     0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 202   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 203     0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
 204   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 205     0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
 206   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 207     0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
 208   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 209     0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
 210   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 211     0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
 212   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 213     0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
 214   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 215     0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
 216   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 217     0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 218   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 219     0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 220   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 221     0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
 222   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 223     0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
 224   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 225     0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
 226   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 227     0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
 228   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 229     0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
 230   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 231     0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
 232   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 233     0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 234   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 235     0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
 236   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 237     0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 238   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 239     0x0e800120, 0x0f800ff0,
 240     "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 241   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 242     0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 243   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 244     0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
 245   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 246     0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
 247   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 248     0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
 249   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 250     0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
 251   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 252     0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
 253   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 254     0x0e8000a0, 0x0f800ff0,
 255     "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 256   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 257     0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 258   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 259     0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 260   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 261     0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
 262   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 263     0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 264   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 265     0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
 266   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 267     0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 268   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 269     0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
 270   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 271     0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
 272   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 273     0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
 274   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 275     0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
 276   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 277     0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 278   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 279     0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 280   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 281     0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
 282   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 283     0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 284   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 285     0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 286   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 287     0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
 288   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 289     0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 290   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 291     0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 292   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 293     0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
 294   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 295     0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
 296   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 297     0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
 298   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 299     0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 300   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 301     0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
 302   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 303     0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 304   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 305     0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
 306   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 307     0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
 308   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 309     0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
 310   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 311     0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
 312   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 313     0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 314   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 315     0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 316   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 317     0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
 318   {ARM_FEATURE_CORE_LOW (0),
 319     SENTINEL_IWMMXT_END, 0, "" },
 320
 321   /* Floating point coprocessor (FPA) instructions.  */
 322   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 323     0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 324   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 325     0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 326   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 327     0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 328   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 329     0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 330   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 331     0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 332   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 333     0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 334   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 335     0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
 336   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 337     0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
 338   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 339     0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 340   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 341     0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
 342   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 343     0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
 344   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 345     0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
 346   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 347     0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
 348   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 349     0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
 350   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 351     0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
 352   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 353     0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
 354   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 355     0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
 356   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 357     0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
 358   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 359     0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
 360   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 361     0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
 362   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 363     0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
 364   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 365     0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
 366   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 367     0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
 368   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 369     0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
 370   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 371     0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
 372   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 373     0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
 374   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 375     0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
 376   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 377     0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
 378   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 379     0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
 380   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 381     0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
 382   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 383     0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
 384   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 385     0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
 386   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 387     0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
 388   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 389     0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
 390   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 391     0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
 392   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 393     0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
 394   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 395     0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
 396   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 397     0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
 398   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 399     0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
 400   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 401     0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
 402   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 403     0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
 404   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 405     0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
 406   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 407     0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
 408
 409   /* Register load/store.  */
 410   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 411     0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
 412   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 413     0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
 414   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 415     0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
 416   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 417     0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
 418   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 419     0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
 420   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 421     0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
 422   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 423     0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
 424   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 425     0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
 426   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 427     0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
 428   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 429     0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
 430   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 431     0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
 432   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 433     0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
 434   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 435     0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
 436   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 437     0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
 438   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 439     0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
 440   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 441     0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
 442
 443   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 444     0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 445   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 446     0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 447   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 448     0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 449   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 450     0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 451
 452   /* Data transfer between ARM and NEON registers.  */
 453   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 454     0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
 455   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 456     0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
 457   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 458     0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
 459   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 460     0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
 461   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 462     0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
 463   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 464     0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
 465   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 466     0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
 467   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 468     0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
 469   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 470     0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
 471   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 472     0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
 473   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 474     0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
 475   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 476     0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
 477   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 478     0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
 479   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 480     0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
 481   /* Half-precision conversion instructions.  */
 482   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 483     0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
 484   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 485     0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
 486   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 487     0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
 488   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 489     0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
 490
 491   /* Floating point coprocessor (VFP) instructions.  */
 492   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 493     0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
 494   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 495     0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
 496   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 497     0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
 498   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 499     0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
 500   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 501     0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
 502   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 503     0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
 504   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 505     0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
 506   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 507     0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
 508   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 509     0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
 510   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 511     0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
 512   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 513     0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
 514   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 515     0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
 516   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 517     0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
 518   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 519     0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
 520   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 521     0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
 522   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 523     0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
 524   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 525     0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
 526   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 527     0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
 528   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 529     0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
 530   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 531     0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
 532   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 533     0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
 534   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 535     0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
 536   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 537     0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
 538   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 539     0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
 540   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 541     0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
 542   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 543     0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
 544   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 545     0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
 546   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 547     0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
 548   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 549     0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
 550   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 551     0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
 552   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 553     0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
 554   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 555     0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
 556   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 557     0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
 558   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 559     0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
 560   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 561     0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
 562   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 563     0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
 564   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 565     0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
 566   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 567     0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
 568   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 569     0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
 570   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 571     0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
 572   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 573     0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
 574   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 575     0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
 576   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 577     0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
 578   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 579     0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
 580   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 581     0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19d"},
 582   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 583     0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19d"},
 584   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 585     0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
 586   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 587     0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
 588   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 589     0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
 590   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 591     0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
 592   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 593     0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
 594   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 595     0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
 596   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 597     0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
 598   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 599     0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
 600   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 601     0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
 602   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 603     0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
 604   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 605     0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
 606   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 607     0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
 608   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 609     0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
 610   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 611     0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
 612   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 613     0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
 614   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 615     0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
 616   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 617     0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
 618   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 619     0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
 620   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 621     0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
 622   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 623     0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
 624   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 625     0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
 626
 627   /* Cirrus coprocessor instructions.  */
 628   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 629     0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 630   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 631     0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 632   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 633     0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 634   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 635     0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 636   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 637     0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 638   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 639     0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 640   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 641     0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 642   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 643     0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 644   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 645     0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 646   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 647     0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 648   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 649     0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 650   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 651     0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 652   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 653     0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 654   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 655     0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 656   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 657     0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 658   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 659     0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 660   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 661     0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
 662   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 663     0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
 664   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 665     0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
 666   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 667     0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
 668   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 669     0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
 670   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 671     0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
 672   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 673     0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
 674   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 675     0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
 676   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 677     0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
 678   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 679     0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
 680   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 681     0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
 682   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 683     0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
 684   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 685     0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
 686   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 687     0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
 688   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 689     0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
 690   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 691     0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
 692   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 693     0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
 694   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 695     0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
 696   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 697     0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
 698   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 699     0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
 700   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 701     0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
 702   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 703     0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
 704   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 705     0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
 706   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 707     0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
 708   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 709     0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
 710   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 711     0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
 712   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 713     0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
 714   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 715     0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
 716   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 717     0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
 718   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 719     0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
 720   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 721     0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
 722   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 723     0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
 724   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 725     0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
 726   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 727     0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
 728   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 729     0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
 730   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 731     0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
 732   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 733     0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
 734   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 735     0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
 736   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 737     0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
 738   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 739     0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
 740   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 741     0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
 742   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 743     0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
 744   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 745     0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
 746   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 747     0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
 748   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 749     0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
 750   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 751     0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
 752   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 753     0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 754   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 755     0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 756   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 757     0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 758   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 759     0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 760   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 761     0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 762   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 763     0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 764   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 765     0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
 766   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 767     0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
 768   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 769     0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
 770   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 771     0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
 772   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 773     0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 774   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 775     0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 776   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 777     0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 778   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 779     0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 780   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 781     0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 782   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 783     0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 784   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 785     0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 786   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 787     0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 788   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 789     0x0e000600, 0x0ff00f10,
 790     "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 791   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 792     0x0e100600, 0x0ff00f10,
 793     "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 794   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 795     0x0e200600, 0x0ff00f10,
 796     "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 797   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 798     0x0e300600, 0x0ff00f10,
 799     "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 800
 801   /* VFP Fused multiply add instructions.  */
 802   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 803     0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
 804   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 805     0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
 806   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 807     0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
 808   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 809     0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
 810   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 811     0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
 812   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 813     0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
 814   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 815     0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
 816   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 817     0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
 818
 819   /* FP v5.  */
 820   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 821     0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
 822   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 823     0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
 824   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 825     0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"},
 826   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 827     0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"},
 828   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 829     0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"},
 830   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 831     0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},
 832   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 833     0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
 834   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 835     0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
 836   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 837     0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
 838   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 839     0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
 840   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 841     0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
 842   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 843     0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
 844
 845   /* Generic coprocessor instructions.  */
 846   {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
 847   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
 848     0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
 849   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
 850     0x0c500000, 0x0ff00000,
 851     "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 852   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 853     0x0e000000, 0x0f000010,
 854     "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 855   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 856     0x0e10f010, 0x0f10f010,
 857     "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
 858   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 859     0x0e100010, 0x0f100010,
 860     "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 861   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 862     0x0e000010, 0x0f100010,
 863     "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 864   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 865     0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
 866   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 867     0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
 868
 869   /* V6 coprocessor instructions.  */
 870   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
 871     0xfc500000, 0xfff00000,
 872     "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 873   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
 874     0xfc400000, 0xfff00000,
 875     "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
 876
 877   /* V5 coprocessor instructions.  */
 878   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 879     0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
 880   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 881     0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
 882   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 883     0xfe000000, 0xff000010,
 884     "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 885   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 886     0xfe000010, 0xff100010,
 887     "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 888   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 889     0xfe100010, 0xff100010,
 890     "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 891
 892   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
 893 };
 894
 895 /* Neon opcode table:  This does not encode the top byte -- that is
 896    checked by the print_insn_neon routine, as it depends on whether we are
 897    doing thumb32 or arm32 disassembly.  */
 898
 899 /* print_insn_neon recognizes the following format control codes:
 900
 901    %%                   %
 902
 903    %c                   print condition code
 904    %u                   print condition code (unconditional in ARM mode,
 905                           UNPREDICTABLE if not AL in Thumb)
 906    %A                   print v{st,ld}[1234] operands
 907    %B                   print v{st,ld}[1234] any one operands
 908    %C                   print v{st,ld}[1234] single->all operands
 909    %D                   print scalar
 910    %E                   print vmov, vmvn, vorr, vbic encoded constant
 911    %F                   print vtbl,vtbx register list
 912
 913    %<bitfield>r         print as an ARM register
 914    %<bitfield>d         print the bitfield in decimal
 915    %<bitfield>e         print the 2^N - bitfield in decimal
 916    %<bitfield>D         print as a NEON D register
 917    %<bitfield>Q         print as a NEON Q register
 918    %<bitfield>R         print as a NEON D or Q register
 919    %<bitfield>Sn        print byte scaled width limited by n
 920    %<bitfield>Tn        print short scaled width limited by n
 921    %<bitfield>Un        print long scaled width limited by n
 922
 923    %<bitfield>'c        print specified char iff bitfield is all ones
 924    %<bitfield>`c        print specified char iff bitfield is all zeroes
 925    %<bitfield>?ab...    select from array of values in big endian order.  */
 926
 927 static const struct opcode32 neon_opcodes[] =
 928 {
 929   /* Extract.  */
 930   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 931     0xf2b00840, 0xffb00850,
 932     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
 933   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 934     0xf2b00000, 0xffb00810,
 935     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
 936
 937   /* Move data element to all lanes.  */
 938   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 939     0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
 940   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 941     0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
 942   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 943     0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
 944
 945   /* Table lookup.  */
 946   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 947     0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
 948   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 949     0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
 950
 951   /* Half-precision conversions.  */
 952   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 953     0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
 954   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 955     0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
 956
 957   /* NEON fused multiply add instructions.  */
 958   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
 959     0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 960   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
 961     0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 962
 963   /* Two registers, miscellaneous.  */
 964   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
 965     0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
 966   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
 967     0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
 968   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
 969     0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
 970   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
 971     0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
 972   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
 973     0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
 974   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
 975     0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
 976   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
 977     0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
 978   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
 979     0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
 980   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
 981     0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
 982   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 983     0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
 984   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 985     0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
 986   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 987     0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
 988   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 989     0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
 990   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 991     0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
 992   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 993     0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
 994   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 995     0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
 996   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 997     0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
 998   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 999     0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1000   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1001     0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1002   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1003     0xf3b20300, 0xffb30fd0,
1004     "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1005   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1006     0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1007   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1008     0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1009   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1010     0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1011   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1012     0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1013   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1014     0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1015   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1016     0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1017   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1018     0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1019   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1020     0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1021   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1022     0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1023   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1024     0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1025   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1026     0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1027   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1028     0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1029   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1030     0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1031   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1032     0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1033   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1034     0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1035   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1036     0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1037   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1038     0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1039   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1040     0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1041   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1042     0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1043   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1044     0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1045   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1046     0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1047   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1048     0xf3b30600, 0xffb30e10,
1049     "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1050
1051   /* Three registers of the same length.  */
1052   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1053     0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1054   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1055     0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1056   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1057     0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1058   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1059     0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1060   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1061     0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1062   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1063     0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1064   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1065     0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1066   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1067     0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1068   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1069     0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1070   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1071     0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1072   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1073     0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1074   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1075     0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1076   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1077     0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1078   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1079     0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1080   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1081     0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1082   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1083     0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1084   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1085     0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1086   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1087     0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1088   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1089     0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1090   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1091     0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1092   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1093     0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1094   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1095     0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1096   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1097     0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1098   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1099     0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1100   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1101     0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1102   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1103     0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1104   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1105     0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1106   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1107     0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1108   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1109     0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1110   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1111     0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1112   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1113     0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1114   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1115     0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1116   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1117     0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1118   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1119     0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1120   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1121     0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1122   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1123     0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1124   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1125     0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1126   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1127     0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1128   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1129     0xf2000b00, 0xff800f10,
1130     "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1131   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1132     0xf2000b10, 0xff800f10,
1133     "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1134   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1135     0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1136   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1137     0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1138   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1139     0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1140   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1141     0xf3000b00, 0xff800f10,
1142     "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1143   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1144     0xf2000000, 0xfe800f10,
1145     "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1146   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1147     0xf2000010, 0xfe800f10,
1148     "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1149   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1150     0xf2000100, 0xfe800f10,
1151     "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1152   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1153     0xf2000200, 0xfe800f10,
1154     "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1155   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1156     0xf2000210, 0xfe800f10,
1157     "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1158   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1159     0xf2000300, 0xfe800f10,
1160     "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1161   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1162     0xf2000310, 0xfe800f10,
1163     "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1164   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1165     0xf2000400, 0xfe800f10,
1166     "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1167   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1168     0xf2000410, 0xfe800f10,
1169     "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1170   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1171     0xf2000500, 0xfe800f10,
1172     "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1173   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1174     0xf2000510, 0xfe800f10,
1175     "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1176   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1177     0xf2000600, 0xfe800f10,
1178     "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1179   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1180     0xf2000610, 0xfe800f10,
1181     "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1182   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1183     0xf2000700, 0xfe800f10,
1184     "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1185   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1186     0xf2000710, 0xfe800f10,
1187     "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1188   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1189     0xf2000910, 0xfe800f10,
1190     "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1191   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1192     0xf2000a00, 0xfe800f10,
1193     "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1194   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1195     0xf2000a10, 0xfe800f10,
1196     "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1197   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1198     0xf3000b10, 0xff800f10,
1199     "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1200   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1201     0xf3000c10, 0xff800f10,
1202     "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1203
1204   /* One register and an immediate value.  */
1205   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1206     0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1207   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1208     0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1209   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1210     0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1211   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1212     0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1213   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1214     0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1215   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1216     0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1217   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1218     0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1219   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1220     0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1221   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1222     0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1223   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1224     0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1225   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1226     0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1227   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1228     0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1229   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1230     0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1231
1232   /* Two registers and a shift amount.  */
1233   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1234     0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1235   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1236     0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1237   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1238     0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1239   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1240     0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1241   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1242     0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1243   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1244     0xf2880950, 0xfeb80fd0,
1245     "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1246   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1247     0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1248   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1249     0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1250   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1251     0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1252   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1253     0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1254   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1255     0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1256   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1257     0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1258   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1259     0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1260   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1261     0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1262   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1263     0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1264   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1265     0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1266   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1267     0xf2900950, 0xfeb00fd0,
1268     "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1269   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1270     0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1271   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1272     0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1273   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1274     0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1275   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1276     0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1277   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1278     0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1279   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1280     0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1281   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1282     0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1283   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1284     0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1285   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1286     0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1287   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1288     0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1289   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1290     0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1291   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1292     0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1293   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1294     0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1295   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1296     0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1297   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1298     0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1299   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1300     0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1301   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1302     0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1303   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1304     0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1305   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1306     0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1307   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1308     0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1309   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1310     0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1311   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1312     0xf2a00950, 0xfea00fd0,
1313     "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1314   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1315     0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1316   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1317     0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1318   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1319     0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1320   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1321     0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1322   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1323     0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1324   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1325     0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1326   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1327     0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1328   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1329     0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1330   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1331     0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1332   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1333     0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1334   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1335     0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1336   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1337     0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1338   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1339     0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1340   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1341     0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1342   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1343     0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1344   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1345     0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1346   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1347     0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1348   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1349     0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1350   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1351     0xf2a00e10, 0xfea00e90,
1352     "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1353
1354   /* Three registers of different lengths.  */
1355   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1356     0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1357   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1358     0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1359   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1360     0xf2800400, 0xff800f50,
1361     "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1362   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1363     0xf2800600, 0xff800f50,
1364     "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1365   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1366     0xf2800900, 0xff800f50,
1367     "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1368   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1369     0xf2800b00, 0xff800f50,
1370     "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1371   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1372     0xf2800d00, 0xff800f50,
1373     "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1374   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1375     0xf3800400, 0xff800f50,
1376     "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1377   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1378     0xf3800600, 0xff800f50,
1379     "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1380   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1381     0xf2800000, 0xfe800f50,
1382     "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1383   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1384     0xf2800100, 0xfe800f50,
1385     "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1386   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1387     0xf2800200, 0xfe800f50,
1388     "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1389   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1390     0xf2800300, 0xfe800f50,
1391     "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1392   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1393     0xf2800500, 0xfe800f50,
1394     "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1395   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1396     0xf2800700, 0xfe800f50,
1397     "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1398   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1399     0xf2800800, 0xfe800f50,
1400     "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1401   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1402     0xf2800a00, 0xfe800f50,
1403     "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1404   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1405     0xf2800c00, 0xfe800f50,
1406     "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1407
1408   /* Two registers and a scalar.  */
1409   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1410     0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1411   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1412     0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1413   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1414     0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1415   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1416     0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1417   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1418     0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1419   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1420     0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1421   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1422     0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1423   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424     0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1425   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1426     0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1427   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1428     0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1429   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1430     0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1431   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1432     0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1433   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1434     0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1435   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436     0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1437   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1438     0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1439   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440     0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1441   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442     0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1443   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1444     0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1445   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1446     0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1447   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448     0xf2800240, 0xfe800f50,
1449     "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1450   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1451     0xf2800640, 0xfe800f50,
1452     "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1453   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1454     0xf2800a40, 0xfe800f50,
1455     "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1456   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1457     0xf2800e40, 0xff800f50,
1458    "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1459   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1460     0xf2800f40, 0xff800f50,
1461    "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1462   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1463     0xf3800e40, 0xff800f50,
1464    "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1465   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1466     0xf3800f40, 0xff800f50,
1467    "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1468   },
1469
1470   /* Element and structure load/store.  */
1471   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1472     0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1473   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1474     0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1475   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1476     0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1477   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1478     0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1479   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1480     0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1481   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1482     0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1483   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484     0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1485   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1486     0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1487   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1488     0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1489   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1490     0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1491   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492     0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1493   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494     0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1495   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1496     0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1497   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498     0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1499   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1500     0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1501   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1502     0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1503   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504     0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1505   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506     0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1507   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508     0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1509
1510   {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1511 };
1512
1513 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb.  All three are partially
1514    ordered: they must be searched linearly from the top to obtain a correct
1515    match.  */
1516
1517 /* print_insn_arm recognizes the following format control codes:
1518
1519    %%                   %
1520
1521    %a                   print address for ldr/str instruction
1522    %s                   print address for ldr/str halfword/signextend instruction
1523    %S                   like %s but allow UNPREDICTABLE addressing
1524    %b                   print branch destination
1525    %c                   print condition code (always bits 28-31)
1526    %m                   print register mask for ldm/stm instruction
1527    %o                   print operand2 (immediate or register + shift)
1528    %p                   print 'p' iff bits 12-15 are 15
1529    %t                   print 't' iff bit 21 set and bit 24 clear
1530    %B                   print arm BLX(1) destination
1531    %C                   print the PSR sub type.
1532    %U                   print barrier type.
1533    %P                   print address for pli instruction.
1534
1535    %<bitfield>r         print as an ARM register
1536    %<bitfield>T         print as an ARM register + 1
1537    %<bitfield>R         as %r but r15 is UNPREDICTABLE
1538    %<bitfield>{r|R}u    as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1539    %<bitfield>{r|R}U    as %{r|R} but if matches the other %U field then is UNPREDICTABLE
1540    %<bitfield>d         print the bitfield in decimal
1541    %<bitfield>W         print the bitfield plus one in decimal
1542    %<bitfield>x         print the bitfield in hex
1543    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
1544
1545    %<bitfield>'c        print specified char iff bitfield is all ones
1546    %<bitfield>`c        print specified char iff bitfield is all zeroes
1547    %<bitfield>?ab...    select from array of values in big endian order
1548
1549    %e                   print arm SMI operand (bits 0..7,8..19).
1550    %E                   print the LSB and WIDTH fields of a BFI or BFC instruction.
1551    %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.
1552    %R                   print the SPSR/CPSR or banked register of an MRS.  */
1553
1554 static const struct opcode32 arm_opcodes[] =
1555 {
1556   /* ARM instructions.  */
1557   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1558     0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1559   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1560     0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1561
1562   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1563     0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1564   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1565     0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1566   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1567     0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1568   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1569     0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1570   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1571     0x00800090, 0x0fa000f0,
1572     "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1573   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1574     0x00a00090, 0x0fa000f0,
1575     "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1576
1577   /* V8 instructions.  */
1578   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1579     0x0320f005, 0x0fffffff, "sevl"},
1580   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1581     0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
1582   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1583     0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
1584   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1585     0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1586   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1587     0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1588   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1589     0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
1590   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1591     0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
1592   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1593     0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
1594   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1595     0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
1596   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1597     0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
1598   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1599     0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
1600   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1601     0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
1602   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1603     0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
1604   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1605     0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
1606   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1607     0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
1608   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1609     0x01f00c9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
1610   /* CRC32 instructions.  */
1611   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1612     0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1613   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1614     0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1615   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1616     0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1617   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1618     0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1619   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1620     0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1621   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1622     0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
1623
1624   /* Privileged Access Never extension instructions.  */
1625   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1626     0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1627
1628   /* Virtualization Extension instructions.  */
1629   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1630   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
1631
1632   /* Integer Divide Extension instructions.  */
1633   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1634     0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1635   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1636     0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
1637
1638   /* MP Extension instructions.  */
1639   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
1640
1641   /* V7 instructions.  */
1642   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1643   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1644   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1645   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1646   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1647   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1648   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
1649
1650   /* ARM V6T2 instructions.  */
1651   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1652     0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1653   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1654     0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1655   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1656     0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1657   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1658     0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1659
1660   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1661     0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1662   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1663     0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1664
1665   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1666     0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
1667   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1668     0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1669   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1670     0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1671   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1672     0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
1673
1674   /* ARM Security extension instructions.  */
1675   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1676     0x01600070, 0x0ff000f0, "smc%c\t%e"},
1677
1678   /* ARM V6K instructions.  */
1679   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1680     0xf57ff01f, 0xffffffff, "clrex"},
1681   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1682     0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1683   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1684     0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1685   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1686     0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1687   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1688     0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1689   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1690     0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1691   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1692     0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
1693
1694   /* ARM V6K NOP hints.  */
1695   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1696     0x0320f001, 0x0fffffff, "yield%c"},
1697   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1698     0x0320f002, 0x0fffffff, "wfe%c"},
1699   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1700     0x0320f003, 0x0fffffff, "wfi%c"},
1701   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1702     0x0320f004, 0x0fffffff, "sev%c"},
1703   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1704     0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
1705
1706   /* ARM V6 instructions.  */
1707   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1708     0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1709   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1710     0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1711   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1712     0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1713   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1714     0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1715   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1716     0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1717   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1718     0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1719   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1720     0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1721   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1722     0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1723   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1724     0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1725   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1726     0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1727   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1728     0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1729   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1730     0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1731   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1732     0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1733   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1734     0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1735   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1736     0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1737   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1738     0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1739   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1740     0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1741   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1742     0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1743   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1744     0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1745   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1746     0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1747   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1748     0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1749   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1750     0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1751   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1752     0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1753   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1754     0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1755   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1756     0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1757   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1758     0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1759   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1760     0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1761   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1762     0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1763   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1764     0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1765   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1766     0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1767   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1768     0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1769   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1770     0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1771   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1772     0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1773   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1774     0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1775   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1776     0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1777   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1778     0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
1779   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1780     0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
1781   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1782     0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
1783   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1784     0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
1785   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1786     0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
1787   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1788     0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
1789   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1790     0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
1791   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1792     0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
1793   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1794     0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
1795   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1796     0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
1797   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1798     0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
1799   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1800     0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
1801   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1802     0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
1803   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1804     0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
1805   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1806     0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
1807   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1808     0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
1809   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1810     0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
1811   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1812     0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
1813   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1814     0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
1815   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1816     0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
1817   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1818     0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
1819   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1820     0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
1821   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1822     0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
1823   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1824     0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
1825   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1826     0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
1827   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1828     0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
1829   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1830     0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
1831   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1832     0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
1833   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1834     0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
1835   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1836     0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
1837   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1838     0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
1839   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1840     0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
1841   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1842     0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
1843   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1844     0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
1845   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1846     0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
1847   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1848     0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
1849   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1850     0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
1851   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1852     0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
1853   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1854     0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
1855   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1856     0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
1857   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1858     0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1859   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1860     0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1861   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1862     0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1863   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1864     0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
1865   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1866     0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1867   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1868     0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1869   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1870     0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1871   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1872     0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
1873   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1874     0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1875   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1876     0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1877   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1878     0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1879   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1880     0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
1881   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1882     0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1883   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1884     0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1885   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1886     0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1887   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1888     0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
1889   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1890     0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1891   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1892     0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1893   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1894     0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
1895   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1896     0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
1897   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1898     0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1899   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1900     0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1901   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1902     0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1903   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1904     0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
1905   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1906     0xf1010000, 0xfffffc00, "setend\t%9?ble"},
1907   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1908     0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
1909   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1910     0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
1911   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1912     0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1913   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1914     0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1915   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1916     0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1917   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1918     0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1919   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1920     0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
1921   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1922     0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1923   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1924     0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1925   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1926     0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
1927   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1928     0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
1929   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1930     0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
1931   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1932     0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
1933   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1934     0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
1935   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1936     0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
1937   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1938     0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
1939   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1940     0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
1941   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1942     0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1943   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1944     0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
1945   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1946     0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
1947   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1948     0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
1949   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1950     0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
1951
1952   /* V5J instruction.  */
1953   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
1954     0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
1955
1956   /* V5 Instructions.  */
1957   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1958     0xe1200070, 0xfff000f0,
1959     "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
1960   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1961     0xfa000000, 0xfe000000, "blx\t%B"},
1962   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1963     0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
1964   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1965     0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
1966
1967   /* V5E "El Segundo" Instructions.  */
1968   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1969     0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
1970   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1971     0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
1972   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1973     0xf450f000, 0xfc70f000, "pld\t%a"},
1974   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1975     0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1976   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1977     0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1978   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1979     0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1980   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1981     0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
1982
1983   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1984     0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1985   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1986     0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
1987
1988   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1989     0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1990   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1991     0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1992   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1993     0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1994   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1995     0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1996
1997   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1998     0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
1999   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2000     0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2001   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2002     0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2003   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2004     0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2005
2006   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2007     0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2008   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2009     0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2010
2011   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2012     0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15R, %0-3R, %16-19R"},
2013   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2014     0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2015   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2016     0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15R, %0-3R, %16-19R"},
2017   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2018     0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
2019
2020   /* ARM Instructions.  */
2021   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2022     0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2023
2024   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2025     0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2026   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2027     0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2028   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2029     0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2030   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2031     0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2032   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2033     0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2034   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2035     0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2036
2037   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2038     0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2039   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2040     0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2041   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2042     0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2043   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2044     0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2045
2046   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2047     0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2048   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2049     0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2050   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2051     0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2052   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2053     0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2054
2055   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2056     0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2057   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2058     0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2059   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2060     0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2061
2062   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2063     0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2064   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2065     0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2066   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2067     0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2068
2069   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2070     0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2071   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2072     0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2073   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2074     0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2075
2076   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2077     0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2078   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2079     0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2080   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2081     0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2082
2083   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2084     0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2085   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2086     0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2087   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2088     0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2089
2090   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2091     0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2092   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2093     0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2094   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2095     0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2096
2097   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2098     0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2099   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2100     0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2101   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2102     0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2103
2104   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2105     0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2106   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2107     0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2108   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2109     0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2110
2111   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2112     0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2113   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2114     0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2115   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2116     0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2117
2118   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2119     0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2120   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2121     0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2122   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2123     0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2124
2125   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2126     0x03200000, 0x0fe00000, "teq%p%c\t%16-19r, %o"},
2127   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2128     0x01200000, 0x0fe00010, "teq%p%c\t%16-19r, %o"},
2129   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2130     0x01200010, 0x0fe00090, "teq%p%c\t%16-19R, %o"},
2131
2132   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2133     0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2134   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2135     0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2136   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2137     0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2138
2139   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2140     0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2141   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2142     0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2143   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2144     0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2145
2146   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2147     0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2148   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2149     0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2150   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2151     0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2152
2153   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2154     0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2155   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2156     0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2157   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2158     0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2159   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2160     0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2161   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2162     0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2163   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2164     0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2165   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2166     0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2167
2168   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2169     0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2170   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2171     0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2172   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2173     0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2174
2175   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2176     0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2177   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2178     0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2179   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2180     0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2181
2182   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2183     0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2184   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2185     0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2186
2187   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2188     0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2189
2190   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2191     0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2192   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2193     0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2194
2195   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2196     0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2197   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2198     0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2199   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2200     0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2201   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2202     0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2203   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2204     0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2205   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2206     0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2207   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2208     0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2209   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2210     0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2211   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2212     0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2213   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2214     0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2215   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2216     0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2217   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2218     0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2219   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2220     0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2221   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2222     0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2223   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2224     0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2225   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2226     0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2227   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2228     0x092d0000, 0x0fff0000, "push%c\t%m"},
2229   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2230     0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2231   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2232     0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2233
2234   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2235     0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2236   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2237     0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2238   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2239     0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2240   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2241     0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2242   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2243     0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2244   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2245     0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2246   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2247     0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2248   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2249     0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2250   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2251     0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2252   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2253     0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2254   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2255     0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2256   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2257     0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2258   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2259     0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2260   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2261     0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2262   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2263     0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2264   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2265     0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2266   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2267     0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2268   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2269     0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2270   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2271     0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2272
2273   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2274     0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2275   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2276     0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
2277
2278   /* The rest.  */
2279   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2280     0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2281   {ARM_FEATURE_CORE_LOW (0),
2282     0x00000000, 0x00000000, 0}
2283 };
2284
2285 /* print_insn_thumb16 recognizes the following format control codes:
2286
2287    %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
2288    %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
2289    %<bitfield>I         print bitfield as a signed decimal
2290                                 (top bit of range being the sign bit)
2291    %N                   print Thumb register mask (with LR)
2292    %O                   print Thumb register mask (with PC)
2293    %M                   print Thumb register mask
2294    %b                   print CZB's 6-bit unsigned branch destination
2295    %s                   print Thumb right-shift immediate (6..10; 0 == 32).
2296    %c                   print the condition code
2297    %C                   print the condition code, or "s" if not conditional
2298    %x                   print warning if conditional an not at end of IT block"
2299    %X                   print "\t; unpredictable <IT:code>" if conditional
2300    %I                   print IT instruction suffix and operands
2301    %W                   print Thumb Writeback indicator for LDMIA
2302    %<bitfield>r         print bitfield as an ARM register
2303    %<bitfield>d         print bitfield as a decimal
2304    %<bitfield>H         print (bitfield * 2) as a decimal
2305    %<bitfield>W         print (bitfield * 4) as a decimal
2306    %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
2307    %<bitfield>B         print Thumb branch destination (signed displacement)
2308    %<bitfield>c         print bitfield as a condition code
2309    %<bitnum>'c          print specified char iff bit is one
2310    %<bitnum>?ab         print a if bit is one else print b.  */
2311
2312 static const struct opcode16 thumb_opcodes[] =
2313 {
2314   /* Thumb instructions.  */
2315
2316   /* ARM V8 instructions.  */
2317   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xbf50, 0xffff, "sevl%c"},
2318   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xba80, 0xffc0, "hlt\t%0-5x"},
2319   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),  0xb610, 0xfff7, "setpan\t#%3-3d"},
2320
2321   /* ARM V6K no-argument instructions.  */
2322   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2323   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2324   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2325   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2326   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2327   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
2328
2329   /* ARM V6T2 instructions.  */
2330   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2331   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
2332   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
2333
2334   /* ARM V6.  */
2335   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2336   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2337   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2338   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2339   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2340   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2341   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2342   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2343   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2344   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2345   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
2346
2347   /* ARM V5 ISA extends Thumb.  */
2348   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2349     0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
2350   /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
2351   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2352     0x4780, 0xff87, "blx%c\t%3-6r%x"},  /* note: 4 bit register number.  */
2353   /* ARM V4T ISA (Thumb v1).  */
2354   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2355     0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
2356   /* Format 4.  */
2357   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2358   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2359   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2360   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2361   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2362   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2363   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2364   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2365   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2366   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2367   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2368   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2369   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2370   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2371   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2372   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
2373   /* format 13 */
2374   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2375   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
2376   /* format 5 */
2377   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2378   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2379   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2380   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
2381   /* format 14 */
2382   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2383   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
2384   /* format 2 */
2385   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2386     0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2387   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2388     0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2389   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2390     0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2391   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2392     0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
2393   /* format 8 */
2394   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2395     0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2396   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2397     0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2398   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2399     0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
2400   /* format 7 */
2401   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2402     0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2403   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2404     0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2405   /* format 1 */
2406   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2407   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2408     0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2409   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2410   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
2411   /* format 3 */
2412   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2413   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2414   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2415   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
2416   /* format 6 */
2417   /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2418   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2419     0x4800, 0xF800,
2420     "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
2421   /* format 9 */
2422   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2423     0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2424   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2425     0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2426   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2427     0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2428   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2429     0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
2430   /* format 10 */
2431   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2432     0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2433   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2434     0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
2435   /* format 11 */
2436   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2437     0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2438   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2439     0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
2440   /* format 12 */
2441   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2442     0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2443   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2444     0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
2445   /* format 15 */
2446   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2447   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
2448   /* format 17 */
2449   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
2450   /* format 16 */
2451   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2452   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2453   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
2454   /* format 18 */
2455   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
2456
2457   /* The E800 .. FFFF range is unconditionally redirected to the
2458      32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2459      are processed via that table.  Thus, we can never encounter a
2460      bare "second half of BL/BLX(1)" instruction here.  */
2461   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),  0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2462   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2463 };
2464
2465 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
2466    We adopt the convention that hw1 is the high 16 bits of .value and
2467    .mask, hw2 the low 16 bits.
2468
2469    print_insn_thumb32 recognizes the following format control codes:
2470
2471        %%               %
2472
2473        %I               print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2474        %M               print a modified 12-bit immediate (same location)
2475        %J               print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2476        %K               print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
2477        %H               print a 16-bit immediate from hw2[3:0],hw1[11:0]
2478        %S               print a possibly-shifted Rm
2479
2480        %L               print address for a ldrd/strd instruction
2481        %a               print the address of a plain load/store
2482        %w               print the width and signedness of a core load/store
2483        %m               print register mask for ldm/stm
2484
2485        %E               print the lsb and width fields of a bfc/bfi instruction
2486        %F               print the lsb and width fields of a sbfx/ubfx instruction
2487        %b               print a conditional branch offset
2488        %B               print an unconditional branch offset
2489        %s               print the shift field of an SSAT instruction
2490        %R               print the rotation field of an SXT instruction
2491        %U               print barrier type.
2492        %P               print address for pli instruction.
2493        %c               print the condition code
2494        %x               print warning if conditional an not at end of IT block"
2495        %X               print "\t; unpredictable <IT:code>" if conditional
2496
2497        %<bitfield>d     print bitfield in decimal
2498        %<bitfield>D     print bitfield plus one in decimal
2499        %<bitfield>W     print bitfield*4 in decimal
2500        %<bitfield>r     print bitfield as an ARM register
2501        %<bitfield>R     as %<>r but r15 is UNPREDICTABLE
2502        %<bitfield>S     as %<>R but r13 is UNPREDICTABLE
2503        %<bitfield>c     print bitfield as a condition code
2504
2505        %<bitfield>'c    print specified char iff bitfield is all ones
2506        %<bitfield>`c    print specified char iff bitfield is all zeroes
2507        %<bitfield>?ab... select from array of values in big endian order
2508
2509    With one exception at the bottom (done because BL and BLX(1) need
2510    to come dead last), this table was machine-sorted first in
2511    decreasing order of number of bits set in the mask, then in
2512    increasing numeric order of mask, then in increasing numeric order
2513    of opcode.  This order is not the clearest for a human reader, but
2514    is guaranteed never to catch a special-case bit pattern with a more
2515    general mask, which is important, because this instruction encoding
2516    makes heavy use of special-case bit patterns.  */
2517 static const struct opcode32 thumb32_opcodes[] =
2518 {
2519   /* V8 instructions.  */
2520   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2521     0xf3af8005, 0xffffffff, "sevl%c.w"},
2522   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2523     0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2524   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2525     0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2526   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2527     0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2528   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2529     0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2530   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2531     0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2532   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2533     0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2534   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2535     0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2536   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2537     0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2538   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2539     0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2540   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2541     0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2542   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2543     0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2544   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2545     0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2546   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2547     0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2548   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2549     0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2550   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2551     0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
2552
2553   /* CRC32 instructions.  */
2554   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2555     0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"},
2556   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2557     0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"},
2558   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2559     0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"},
2560   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2561     0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"},
2562   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2563     0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"},
2564   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2565     0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"},
2566
2567   /* V7 instructions.  */
2568   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2569   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2570   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2571   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2572   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2573   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2574   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2575   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2576     0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2577   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2578     0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
2579
2580   /* Virtualization Extension instructions.  */
2581   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
2582   /* We skip ERET as that is SUBS pc, lr, #0.  */
2583
2584   /* MP Extension instructions.  */
2585   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP),   0xf830f000, 0xff70f000, "pldw%c\t%a"},
2586
2587   /* Security extension instructions.  */
2588   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
2589
2590   /* Instructions defined in the basic V6T2 set.  */
2591   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2592   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2593   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2594   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2595   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2596   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2597     0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2598   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2599
2600   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2601     0xf3bf8f2f, 0xffffffff, "clrex%c"},
2602   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2603     0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2604   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2605     0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2606   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2607     0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2608   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2609     0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2610   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2611     0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2612   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2613     0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2614   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2615     0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2616   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2617     0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2618   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2619     0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2620   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2621     0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2622   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2623     0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2624   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2625     0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2626   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2627     0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
2628   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2629     0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
2630   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2631     0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2632   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2633     0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2634   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2635     0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2636   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2637     0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2638   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2639     0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2640   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2641     0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2642   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2643     0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2644   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2645     0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2646   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2647     0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
2648   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2649     0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2650   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2651     0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2652   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2653     0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2654   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2655     0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2656   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2657     0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2658   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2659     0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2660   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2661     0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2662   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2663     0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2664   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2665     0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2666   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2667     0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2668   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2669     0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2670   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2671     0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2672   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2673     0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2674   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2675     0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2676   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2677     0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2678   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2679     0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2680   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2681     0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2682   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2683     0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2684   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2685     0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2686   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2687     0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2688   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2689     0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2690   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2691     0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2692   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2693     0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2694   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2695     0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2696   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2697     0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2698   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2699     0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2700   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2701     0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2702   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2703     0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2704   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2705     0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2706   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2707     0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2708   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2709     0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2710   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2711     0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2712   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2713     0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2714   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2715     0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2716   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2717     0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2718   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2719     0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2720   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2721     0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2722   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2723     0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2724   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2725     0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2726   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2727     0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2728   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2729     0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2730   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2731     0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2732   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2733     0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2734   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2735     0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2736   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2737     0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2738   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2739     0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2740   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2741     0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
2742   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2743     0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
2744   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2745     0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
2746   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2747     0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
2748   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2749     0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2750   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2751     0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2752   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2753     0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2754   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2755     0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
2756   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2757     0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
2758   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2759     0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
2760   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2761     0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
2762   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2763     0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
2764   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2765     0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2766   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2767     0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
2768   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2769     0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
2770   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2771     0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2772   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2773     0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2774   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2775     0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2776   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2777     0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2778   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2779     0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2780   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2781     0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2782   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2783     0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2784   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2785     0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
2786   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2787     0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
2788   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2789     0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
2790   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2791     0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
2792   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2793     0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
2794   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2795     0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
2796   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2797     0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
2798   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2799     0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
2800   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2801     0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
2802   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2803     0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
2804   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2805     0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
2806   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2807     0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
2808   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2809     0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2810   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2811     0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2812   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2813     0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2814   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2815     0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2816   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2817     0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2818   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2819     0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2820   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2821     0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2822   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2823     0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2824   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2825     0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
2826   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2827     0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
2828   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2829     0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
2830   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2831     0xf810f000, 0xff70f000, "pld%c\t%a"},
2832   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2833     0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2834   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2835     0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2836   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2837     0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2838   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2839     0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2840   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2841     0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2842   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2843     0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2844   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2845     0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2846   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2847     0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
2848   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2849     0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
2850   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2851     0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
2852   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2853     0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
2854   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2855     0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
2856   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2857     0xfb100000, 0xfff000c0,
2858     "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2859   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2860     0xfbc00080, 0xfff000c0,
2861     "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
2862   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2863     0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
2864   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2865     0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
2866   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2867     0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
2868   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2869     0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
2870   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2871     0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
2872   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2873     0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
2874   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2875     0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
2876   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2877     0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
2878   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2879     0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
2880   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2881     0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
2882   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2883     0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
2884   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2885     0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
2886   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2887     0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
2888   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2889     0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
2890   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2891     0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
2892   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2893     0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
2894   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2895     0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
2896   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2897     0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
2898   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2899     0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
2900   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2901     0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
2902   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2903     0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
2904   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2905     0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
2906   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2907     0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
2908   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2909     0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
2910   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2911     0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
2912   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2913     0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
2914   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2915     0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
2916   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2917     0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
2918   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2919     0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
2920   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2921     0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
2922   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2923     0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
2924   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2925     0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
2926   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2927     0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
2928   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2929     0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
2930   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2931     0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
2932   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2933     0xe9400000, 0xff500000,
2934     "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
2935   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2936     0xe9500000, 0xff500000,
2937     "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
2938   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2939     0xe8600000, 0xff700000,
2940     "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
2941   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2942     0xe8700000, 0xff700000,
2943     "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
2944   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2945     0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
2946   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2947     0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
2948
2949   /* Filter out Bcc with cond=E or F, which are used for other instructions.  */
2950   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2951     0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
2952   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2953     0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
2954   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2955     0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
2956   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2957     0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
2958
2959   /* These have been 32-bit since the invention of Thumb.  */
2960   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2961      0xf000c000, 0xf800d001, "blx%c\t%B%x"},
2962   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2963      0xf000d000, 0xf800d000, "bl%c\t%B%x"},
2964
2965   /* Fallback.  */
2966   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2967       0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2968   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2969 };
2970
2971 static const char *const arm_conditional[] =
2972 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
2973  "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
2974
2975 static const char *const arm_fp_const[] =
2976 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
2977
2978 static const char *const arm_shift[] =
2979 {"lsl", "lsr", "asr", "ror"};
2980
2981 typedef struct
2982 {
2983   const char *name;
2984   const char *description;
2985   const char *reg_names[16];
2986 }
2987 arm_regname;
2988
2989 static const arm_regname regnames[] =
2990 {
2991   { "raw" , "Select raw register names",
2992     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
2993   { "gcc",  "Select register names used by GCC",
2994     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
2995   { "std",  "Select register names used in ARM's ISA documentation",
2996     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp",  "lr",  "pc" }},
2997   { "apcs", "Select register names used in the APCS",
2998     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
2999   { "atpcs", "Select register names used in the ATPCS",
3000     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7",  "v8",  "IP",  "SP",  "LR",  "PC" }},
3001   { "special-atpcs", "Select special register names used in the ATPCS",
3002     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }},
3003 };
3004
3005 static const char *const iwmmxt_wwnames[] =
3006 {"b", "h", "w", "d"};
3007
3008 static const char *const iwmmxt_wwssnames[] =
3009 {"b", "bus", "bc", "bss",
3010  "h", "hus", "hc", "hss",
3011  "w", "wus", "wc", "wss",
3012  "d", "dus", "dc", "dss"
3013 };
3014
3015 static const char *const iwmmxt_regnames[] =
3016 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3017   "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3018 };
3019
3020 static const char *const iwmmxt_cregnames[] =
3021 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3022   "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3023 };
3024
3025 /* Default to GCC register name set.  */
3026 static unsigned int regname_selected = 1;
3027
3028 #define NUM_ARM_REGNAMES  NUM_ELEM (regnames)
3029 #define arm_regnames      regnames[regname_selected].reg_names
3030
3031 static bfd_boolean force_thumb = FALSE;
3032
3033 /* Current IT instruction state.  This contains the same state as the IT
3034    bits in the CPSR.  */
3035 static unsigned int ifthen_state;
3036 /* IT state for the next instruction.  */
3037 static unsigned int ifthen_next_state;
3038 /* The address of the insn for which the IT state is valid.  */
3039 static bfd_vma ifthen_address;
3040 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
3041 /* Indicates that the current Conditional state is unconditional or outside
3042    an IT block.  */
3043 #define COND_UNCOND 16
3044
3045 \f
3046 /* Functions.  */
3047 int
3048 get_arm_regname_num_options (void)
3049 {
3050   return NUM_ARM_REGNAMES;
3051 }
3052
3053 int
3054 set_arm_regname_option (int option)
3055 {
3056   int old = regname_selected;
3057   regname_selected = option;
3058   return old;
3059 }
3060
3061 int
3062 get_arm_regnames (int option,
3063                   const char **setname,
3064                   const char **setdescription,
3065                   const char *const **register_names)
3066 {
3067   *setname = regnames[option].name;
3068   *setdescription = regnames[option].description;
3069   *register_names = regnames[option].reg_names;
3070   return 16;
3071 }
3072
3073 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3074    Returns pointer to following character of the format string and
3075    fills in *VALUEP and *WIDTHP with the extracted value and number of
3076    bits extracted.  WIDTHP can be NULL.  */
3077
3078 static const char *
3079 arm_decode_bitfield (const char *ptr,
3080                      unsigned long insn,
3081                      unsigned long *valuep,
3082                      int *widthp)
3083 {
3084   unsigned long value = 0;
3085   int width = 0;
3086
3087   do
3088     {
3089       int start, end;
3090       int bits;
3091
3092       for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3093         start = start * 10 + *ptr - '0';
3094       if (*ptr == '-')
3095         for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3096           end = end * 10 + *ptr - '0';
3097       else
3098         end = start;
3099       bits = end - start;
3100       if (bits < 0)
3101         abort ();
3102       value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3103       width += bits + 1;
3104     }
3105   while (*ptr++ == ',');
3106   *valuep = value;
3107   if (widthp)
3108     *widthp = width;
3109   return ptr - 1;
3110 }
3111
3112 static void
3113 arm_decode_shift (long given, fprintf_ftype func, void *stream,
3114                   bfd_boolean print_shift)
3115 {
3116   func (stream, "%s", arm_regnames[given & 0xf]);
3117
3118   if ((given & 0xff0) != 0)
3119     {
3120       if ((given & 0x10) == 0)
3121         {
3122           int amount = (given & 0xf80) >> 7;
3123           int shift = (given & 0x60) >> 5;
3124
3125           if (amount == 0)
3126             {
3127               if (shift == 3)
3128                 {
3129                   func (stream, ", rrx");
3130                   return;
3131                 }
3132
3133               amount = 32;
3134             }
3135
3136           if (print_shift)
3137             func (stream, ", %s #%d", arm_shift[shift], amount);
3138           else
3139             func (stream, ", #%d", amount);
3140         }
3141       else if ((given & 0x80) == 0x80)
3142         func (stream, "\t; <illegal shifter operand>");
3143       else if (print_shift)
3144         func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3145               arm_regnames[(given & 0xf00) >> 8]);
3146       else
3147         func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
3148     }
3149 }
3150
3151 #define W_BIT 21
3152 #define I_BIT 22
3153 #define U_BIT 23
3154 #define P_BIT 24
3155
3156 #define WRITEBACK_BIT_SET   (given & (1 << W_BIT))
3157 #define IMMEDIATE_BIT_SET   (given & (1 << I_BIT))
3158 #define NEGATIVE_BIT_SET   ((given & (1 << U_BIT)) == 0)
3159 #define PRE_BIT_SET         (given & (1 << P_BIT))
3160
3161 /* Print one coprocessor instruction on INFO->STREAM.
3162    Return TRUE if the instuction matched, FALSE if this is not a
3163    recognised coprocessor instruction.  */
3164
3165 static bfd_boolean
3166 print_insn_coprocessor (bfd_vma pc,
3167                         struct disassemble_info *info,
3168                         long given,
3169                         bfd_boolean thumb)
3170 {
3171   const struct opcode32 *insn;
3172   void *stream = info->stream;
3173   fprintf_ftype func = info->fprintf_func;
3174   unsigned long mask;
3175   unsigned long value = 0;
3176   int cond;
3177   struct arm_private_data *private_data = info->private_data;
3178   arm_feature_set allowed_arches = ARM_ARCH_NONE;
3179
3180   ARM_FEATURE_COPY (allowed_arches, private_data->features);
3181
3182   for (insn = coprocessor_opcodes; insn->assembler; insn++)
3183     {
3184       unsigned long u_reg = 16;
3185       bfd_boolean is_unpredictable = FALSE;
3186       signed long value_in_comment = 0;
3187       const char *c;
3188
3189       if (ARM_FEATURE_ZERO (insn->arch))
3190         switch (insn->value)
3191           {
3192           case SENTINEL_IWMMXT_START:
3193             if (info->mach != bfd_mach_arm_XScale
3194                 && info->mach != bfd_mach_arm_iWMMXt
3195                 && info->mach != bfd_mach_arm_iWMMXt2)
3196               do
3197                 insn++;
3198               while ((! ARM_FEATURE_ZERO (insn->arch))
3199                      && insn->value != SENTINEL_IWMMXT_END);
3200             continue;
3201
3202           case SENTINEL_IWMMXT_END:
3203             continue;
3204
3205           case SENTINEL_GENERIC_START:
3206             ARM_FEATURE_COPY (allowed_arches, private_data->features);
3207             continue;
3208
3209           default:
3210             abort ();
3211           }
3212
3213       mask = insn->mask;
3214       value = insn->value;
3215       if (thumb)
3216         {
3217           /* The high 4 bits are 0xe for Arm conditional instructions, and
3218              0xe for arm unconditional instructions.  The rest of the
3219              encoding is the same.  */
3220           mask |= 0xf0000000;
3221           value |= 0xe0000000;
3222           if (ifthen_state)
3223             cond = IFTHEN_COND;
3224           else
3225             cond = COND_UNCOND;
3226         }
3227       else
3228         {
3229           /* Only match unconditional instuctions against unconditional
3230              patterns.  */
3231           if ((given & 0xf0000000) == 0xf0000000)
3232             {
3233               mask |= 0xf0000000;
3234               cond = COND_UNCOND;
3235             }
3236           else
3237             {
3238               cond = (given >> 28) & 0xf;
3239               if (cond == 0xe)
3240                 cond = COND_UNCOND;
3241             }
3242         }
3243
3244       if ((given & mask) != value)
3245         continue;
3246
3247       if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
3248         continue;
3249
3250       for (c = insn->assembler; *c; c++)
3251         {
3252           if (*c == '%')
3253             {
3254               switch (*++c)
3255                 {
3256                 case '%':
3257                   func (stream, "%%");
3258                   break;
3259
3260                 case 'A':
3261                   {
3262                     int rn = (given >> 16) & 0xf;
3263                     bfd_vma offset = given & 0xff;
3264
3265                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3266
3267                     if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3268                       {
3269                         /* Not unindexed.  The offset is scaled.  */
3270                         offset = offset * 4;
3271                         if (NEGATIVE_BIT_SET)
3272                           offset = - offset;
3273                         if (rn != 15)
3274                           value_in_comment = offset;
3275                       }
3276
3277                     if (PRE_BIT_SET)
3278                       {
3279                         if (offset)
3280                           func (stream, ", #%d]%s",
3281                                 (int) offset,
3282                                 WRITEBACK_BIT_SET ? "!" : "");
3283                         else if (NEGATIVE_BIT_SET)
3284                           func (stream, ", #-0]");
3285                         else
3286                           func (stream, "]");
3287                       }
3288                     else
3289                       {
3290                         func (stream, "]");
3291
3292                         if (WRITEBACK_BIT_SET)
3293                           {
3294                             if (offset)
3295                               func (stream, ", #%d", (int) offset);
3296                             else if (NEGATIVE_BIT_SET)
3297                               func (stream, ", #-0");
3298                           }
3299                         else
3300                           {
3301                             func (stream, ", {%s%d}",
3302                                   (NEGATIVE_BIT_SET && !offset) ? "-" : "",
3303                                   (int) offset);
3304                             value_in_comment = offset;
3305                           }
3306                       }
3307                     if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3308                       {
3309                         func (stream, "\t; ");
3310                         /* For unaligned PCs, apply off-by-alignment
3311                            correction.  */
3312                         info->print_address_func (offset + pc
3313                                                   + info->bytes_per_chunk * 2
3314                                                   - (pc & 3),
3315                                                   info);
3316                       }
3317                   }
3318                   break;
3319
3320                 case 'B':
3321                   {
3322                     int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3323                     int offset = (given >> 1) & 0x3f;
3324
3325                     if (offset == 1)
3326                       func (stream, "{d%d}", regno);
3327                     else if (regno + offset > 32)
3328                       func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3329                     else
3330                       func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3331                   }
3332                   break;
3333
3334                 case 'u':
3335                   if (cond != COND_UNCOND)
3336                     is_unpredictable = TRUE;
3337
3338                   /* Fall through.  */
3339                 case 'c':
3340                   func (stream, "%s", arm_conditional[cond]);
3341                   break;
3342
3343                 case 'I':
3344                   /* Print a Cirrus/DSP shift immediate.  */
3345                   /* Immediates are 7bit signed ints with bits 0..3 in
3346                      bits 0..3 of opcode and bits 4..6 in bits 5..7
3347                      of opcode.  */
3348                   {
3349                     int imm;
3350
3351                     imm = (given & 0xf) | ((given & 0xe0) >> 1);
3352
3353                     /* Is ``imm'' a negative number?  */
3354                     if (imm & 0x40)
3355                       imm |= (-1 << 7);
3356
3357                     func (stream, "%d", imm);
3358                   }
3359
3360                   break;
3361
3362                 case 'F':
3363                   switch (given & 0x00408000)
3364                     {
3365                     case 0:
3366                       func (stream, "4");
3367                       break;
3368                     case 0x8000:
3369                       func (stream, "1");
3370                       break;
3371                     case 0x00400000:
3372                       func (stream, "2");
3373                       break;
3374                     default:
3375                       func (stream, "3");
3376                     }
3377                   break;
3378
3379                 case 'P':
3380                   switch (given & 0x00080080)
3381                     {
3382                     case 0:
3383                       func (stream, "s");
3384                       break;
3385                     case 0x80:
3386                       func (stream, "d");
3387                       break;
3388                     case 0x00080000:
3389                       func (stream, "e");
3390                       break;
3391                     default:
3392                       func (stream, _("<illegal precision>"));
3393                       break;
3394                     }
3395                   break;
3396
3397                 case 'Q':
3398                   switch (given & 0x00408000)
3399                     {
3400                     case 0:
3401                       func (stream, "s");
3402                       break;
3403                     case 0x8000:
3404                       func (stream, "d");
3405                       break;
3406                     case 0x00400000:
3407                       func (stream, "e");
3408                       break;
3409                     default:
3410                       func (stream, "p");
3411                       break;
3412                     }
3413                   break;
3414
3415                 case 'R':
3416                   switch (given & 0x60)
3417                     {
3418                     case 0:
3419                       break;
3420                     case 0x20:
3421                       func (stream, "p");
3422                       break;
3423                     case 0x40:
3424                       func (stream, "m");
3425                       break;
3426                     default:
3427                       func (stream, "z");
3428                       break;
3429                     }
3430                   break;
3431
3432                 case '0': case '1': case '2': case '3': case '4':
3433                 case '5': case '6': case '7': case '8': case '9':
3434                   {
3435                     int width;
3436
3437                     c = arm_decode_bitfield (c, given, &value, &width);
3438
3439                     switch (*c)
3440                       {
3441                       case 'R':
3442                         if (value == 15)
3443                           is_unpredictable = TRUE;
3444                         /* Fall through.  */
3445                       case 'r':
3446                         if (c[1] == 'u')
3447                           {
3448                             /* Eat the 'u' character.  */
3449                             ++ c;
3450
3451                             if (u_reg == value)
3452                               is_unpredictable = TRUE;
3453                             u_reg = value;
3454                           }
3455                         func (stream, "%s", arm_regnames[value]);
3456                         break;
3457                       case 'D':
3458                         func (stream, "d%ld", value);
3459                         break;
3460                       case 'Q':
3461                         if (value & 1)
3462                           func (stream, "<illegal reg q%ld.5>", value >> 1);
3463                         else
3464                           func (stream, "q%ld", value >> 1);
3465                         break;
3466                       case 'd':
3467                         func (stream, "%ld", value);
3468                         value_in_comment = value;
3469                         break;
3470                       case 'k':
3471                         {
3472                           int from = (given & (1 << 7)) ? 32 : 16;
3473                           func (stream, "%ld", from - value);
3474                         }
3475                         break;
3476
3477                       case 'f':
3478                         if (value > 7)
3479                           func (stream, "#%s", arm_fp_const[value & 7]);
3480                         else
3481                           func (stream, "f%ld", value);
3482                         break;
3483
3484                       case 'w':
3485                         if (width == 2)
3486                           func (stream, "%s", iwmmxt_wwnames[value]);
3487                         else
3488                           func (stream, "%s", iwmmxt_wwssnames[value]);
3489                         break;
3490
3491                       case 'g':
3492                         func (stream, "%s", iwmmxt_regnames[value]);
3493                         break;
3494                       case 'G':
3495                         func (stream, "%s", iwmmxt_cregnames[value]);
3496                         break;
3497
3498                       case 'x':
3499                         func (stream, "0x%lx", (value & 0xffffffffUL));
3500                         break;
3501
3502                       case 'c':
3503                         switch (value)
3504                           {
3505                           case 0:
3506                             func (stream, "eq");
3507                             break;
3508
3509                           case 1:
3510                             func (stream, "vs");
3511                             break;
3512
3513                           case 2:
3514                             func (stream, "ge");
3515                             break;
3516
3517                           case 3:
3518                             func (stream, "gt");
3519                             break;
3520
3521                           default:
3522                             func (stream, "??");
3523                             break;
3524                           }
3525                         break;
3526
3527                       case '`':
3528                         c++;
3529                         if (value == 0)
3530                           func (stream, "%c", *c);
3531                         break;
3532                       case '\'':
3533                         c++;
3534                         if (value == ((1ul << width) - 1))
3535                           func (stream, "%c", *c);
3536                         break;
3537                       case '?':
3538                         func (stream, "%c", c[(1 << width) - (int) value]);
3539                         c += 1 << width;
3540                         break;
3541                       default:
3542                         abort ();
3543                       }
3544                     break;
3545
3546                   case 'y':
3547                   case 'z':
3548                     {
3549                       int single = *c++ == 'y';
3550                       int regno;
3551
3552                       switch (*c)
3553                         {
3554                         case '4': /* Sm pair */
3555                         case '0': /* Sm, Dm */
3556                           regno = given & 0x0000000f;
3557                           if (single)
3558                             {
3559                               regno <<= 1;
3560                               regno += (given >> 5) & 1;
3561                             }
3562                           else
3563                             regno += ((given >> 5) & 1) << 4;
3564                           break;
3565
3566                         case '1': /* Sd, Dd */
3567                           regno = (given >> 12) & 0x0000000f;
3568                           if (single)
3569                             {
3570                               regno <<= 1;
3571                               regno += (given >> 22) & 1;
3572                             }
3573                           else
3574                             regno += ((given >> 22) & 1) << 4;
3575                           break;
3576
3577                         case '2': /* Sn, Dn */
3578                           regno = (given >> 16) & 0x0000000f;
3579                           if (single)
3580                             {
3581                               regno <<= 1;
3582                               regno += (given >> 7) & 1;
3583                             }
3584                           else
3585                             regno += ((given >> 7) & 1) << 4;
3586                           break;
3587
3588                         case '3': /* List */
3589                           func (stream, "{");
3590                           regno = (given >> 12) & 0x0000000f;
3591                           if (single)
3592                             {
3593                               regno <<= 1;
3594                               regno += (given >> 22) & 1;
3595                             }
3596                           else
3597                             regno += ((given >> 22) & 1) << 4;
3598                           break;
3599
3600                         default:
3601                           abort ();
3602                         }
3603
3604                       func (stream, "%c%d", single ? 's' : 'd', regno);
3605
3606                       if (*c == '3')
3607                         {
3608                           int count = given & 0xff;
3609
3610                           if (single == 0)
3611                             count >>= 1;
3612
3613                           if (--count)
3614                             {
3615                               func (stream, "-%c%d",
3616                                     single ? 's' : 'd',
3617                                     regno + count);
3618                             }
3619
3620                           func (stream, "}");
3621                         }
3622                       else if (*c == '4')
3623                         func (stream, ", %c%d", single ? 's' : 'd',
3624                               regno + 1);
3625                     }
3626                     break;
3627
3628                   case 'L':
3629                     switch (given & 0x00400100)
3630                       {
3631                       case 0x00000000: func (stream, "b"); break;
3632                       case 0x00400000: func (stream, "h"); break;
3633                       case 0x00000100: func (stream, "w"); break;
3634                       case 0x00400100: func (stream, "d"); break;
3635                       default:
3636                         break;
3637                       }
3638                     break;
3639
3640                   case 'Z':
3641                     {
3642                       /* given (20, 23) | given (0, 3) */
3643                       value = ((given >> 16) & 0xf0) | (given & 0xf);
3644                       func (stream, "%d", (int) value);
3645                     }
3646                     break;
3647
3648                   case 'l':
3649                     /* This is like the 'A' operator, except that if
3650                        the width field "M" is zero, then the offset is
3651                        *not* multiplied by four.  */
3652                     {
3653                       int offset = given & 0xff;
3654                       int multiplier = (given & 0x00000100) ? 4 : 1;
3655
3656                       func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3657
3658                       if (multiplier > 1)
3659                         {
3660                           value_in_comment = offset * multiplier;
3661                           if (NEGATIVE_BIT_SET)
3662                             value_in_comment = - value_in_comment;
3663                         }
3664
3665                       if (offset)
3666                         {
3667                           if (PRE_BIT_SET)
3668                             func (stream, ", #%s%d]%s",
3669                                   NEGATIVE_BIT_SET ? "-" : "",
3670                                   offset * multiplier,
3671                                   WRITEBACK_BIT_SET ? "!" : "");
3672                           else
3673                             func (stream, "], #%s%d",
3674                                   NEGATIVE_BIT_SET ? "-" : "",
3675                                   offset * multiplier);
3676                         }
3677                       else
3678                         func (stream, "]");
3679                     }
3680                     break;
3681
3682                   case 'r':
3683                     {
3684                       int imm4 = (given >> 4) & 0xf;
3685                       int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3686                       int ubit = ! NEGATIVE_BIT_SET;
3687                       const char *rm = arm_regnames [given & 0xf];
3688                       const char *rn = arm_regnames [(given >> 16) & 0xf];
3689
3690                       switch (puw_bits)
3691                         {
3692                         case 1:
3693                         case 3:
3694                           func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3695                           if (imm4)
3696                             func (stream, ", lsl #%d", imm4);
3697                           break;
3698
3699                         case 4:
3700                         case 5:
3701                         case 6:
3702                         case 7:
3703                           func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3704                           if (imm4 > 0)
3705                             func (stream, ", lsl #%d", imm4);
3706                           func (stream, "]");
3707                           if (puw_bits == 5 || puw_bits == 7)
3708                             func (stream, "!");
3709                           break;
3710
3711                         default:
3712                           func (stream, "INVALID");
3713                         }
3714                     }
3715                     break;
3716
3717                   case 'i':
3718                     {
3719                       long imm5;
3720                       imm5 = ((given & 0x100) >> 4) | (given & 0xf);
3721                       func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
3722                     }
3723                     break;
3724
3725                   default:
3726                     abort ();
3727                   }
3728                 }
3729             }
3730           else
3731             func (stream, "%c", *c);
3732         }
3733
3734       if (value_in_comment > 32 || value_in_comment < -16)
3735         func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
3736
3737       if (is_unpredictable)
3738         func (stream, UNPREDICTABLE_INSTRUCTION);
3739
3740       return TRUE;
3741     }
3742   return FALSE;
3743 }
3744
3745 /* Decodes and prints ARM addressing modes.  Returns the offset
3746    used in the address, if any, if it is worthwhile printing the
3747    offset as a hexadecimal value in a comment at the end of the
3748    line of disassembly.  */
3749
3750 static signed long
3751 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
3752 {
3753   void *stream = info->stream;
3754   fprintf_ftype func = info->fprintf_func;
3755   bfd_vma offset = 0;
3756
3757   if (((given & 0x000f0000) == 0x000f0000)
3758       && ((given & 0x02000000) == 0))
3759     {
3760       offset = given & 0xfff;
3761
3762       func (stream, "[pc");
3763
3764       if (PRE_BIT_SET)
3765         {
3766           /* Pre-indexed.  Elide offset of positive zero when
3767              non-writeback.  */
3768           if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
3769             func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3770
3771           if (NEGATIVE_BIT_SET)
3772             offset = -offset;
3773
3774           offset += pc + 8;
3775
3776           /* Cope with the possibility of write-back
3777              being used.  Probably a very dangerous thing
3778              for the programmer to do, but who are we to
3779              argue ?  */
3780           func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
3781         }
3782       else  /* Post indexed.  */
3783         {
3784           func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3785
3786           /* Ie ignore the offset.  */
3787           offset = pc + 8;
3788         }
3789
3790       func (stream, "\t; ");
3791       info->print_address_func (offset, info);
3792       offset = 0;
3793     }
3794   else
3795     {
3796       func (stream, "[%s",
3797             arm_regnames[(given >> 16) & 0xf]);
3798
3799       if (PRE_BIT_SET)
3800         {
3801           if ((given & 0x02000000) == 0)
3802             {
3803               /* Elide offset of positive zero when non-writeback.  */
3804               offset = given & 0xfff;
3805               if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
3806                 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3807             }
3808           else
3809             {
3810               func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
3811               arm_decode_shift (given, func, stream, TRUE);
3812             }
3813
3814           func (stream, "]%s",
3815                 WRITEBACK_BIT_SET ? "!" : "");
3816         }
3817       else
3818         {
3819           if ((given & 0x02000000) == 0)
3820             {
3821               /* Always show offset.  */
3822               offset = given & 0xfff;
3823               func (stream, "], #%s%d",
3824                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3825             }
3826           else
3827             {
3828               func (stream, "], %s",
3829                     NEGATIVE_BIT_SET ? "-" : "");
3830               arm_decode_shift (given, func, stream, TRUE);
3831             }
3832         }
3833       if (NEGATIVE_BIT_SET)
3834         offset = -offset;
3835     }
3836
3837   return (signed long) offset;
3838 }
3839
3840 /* Print one neon instruction on INFO->STREAM.
3841    Return TRUE if the instuction matched, FALSE if this is not a
3842    recognised neon instruction.  */
3843
3844 static bfd_boolean
3845 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
3846 {
3847   const struct opcode32 *insn;
3848   void *stream = info->stream;
3849   fprintf_ftype func = info->fprintf_func;
3850
3851   if (thumb)
3852     {
3853       if ((given & 0xef000000) == 0xef000000)
3854         {
3855           /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding.  */
3856           unsigned long bit28 = given & (1 << 28);
3857
3858           given &= 0x00ffffff;
3859           if (bit28)
3860             given |= 0xf3000000;
3861           else
3862             given |= 0xf2000000;
3863         }
3864       else if ((given & 0xff000000) == 0xf9000000)
3865         given ^= 0xf9000000 ^ 0xf4000000;
3866       else
3867         return FALSE;
3868     }
3869
3870   for (insn = neon_opcodes; insn->assembler; insn++)
3871     {
3872       if ((given & insn->mask) == insn->value)
3873         {
3874           signed long value_in_comment = 0;
3875           bfd_boolean is_unpredictable = FALSE;
3876           const char *c;
3877
3878           for (c = insn->assembler; *c; c++)
3879             {
3880               if (*c == '%')
3881                 {
3882                   switch (*++c)
3883                     {
3884                     case '%':
3885                       func (stream, "%%");
3886                       break;
3887
3888                     case 'u':
3889                       if (thumb && ifthen_state)
3890                         is_unpredictable = TRUE;
3891
3892                       /* Fall through.  */
3893                     case 'c':
3894                       if (thumb && ifthen_state)
3895                         func (stream, "%s", arm_conditional[IFTHEN_COND]);
3896                       break;
3897
3898                     case 'A':
3899                       {
3900                         static const unsigned char enc[16] =
3901                         {
3902                           0x4, 0x14, /* st4 0,1 */
3903                           0x4, /* st1 2 */
3904                           0x4, /* st2 3 */
3905                           0x3, /* st3 4 */
3906                           0x13, /* st3 5 */
3907                           0x3, /* st1 6 */
3908                           0x1, /* st1 7 */
3909                           0x2, /* st2 8 */
3910                           0x12, /* st2 9 */
3911                           0x2, /* st1 10 */
3912                           0, 0, 0, 0, 0
3913                         };
3914                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
3915                         int rn = ((given >> 16) & 0xf);
3916                         int rm = ((given >> 0) & 0xf);
3917                         int align = ((given >> 4) & 0x3);
3918                         int type = ((given >> 8) & 0xf);
3919                         int n = enc[type] & 0xf;
3920                         int stride = (enc[type] >> 4) + 1;
3921                         int ix;
3922
3923                         func (stream, "{");
3924                         if (stride > 1)
3925                           for (ix = 0; ix != n; ix++)
3926                             func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
3927                         else if (n == 1)
3928                           func (stream, "d%d", rd);
3929                         else
3930                           func (stream, "d%d-d%d", rd, rd + n - 1);
3931                         func (stream, "}, [%s", arm_regnames[rn]);
3932                         if (align)
3933                           func (stream, " :%d", 32 << align);
3934                         func (stream, "]");
3935                         if (rm == 0xd)
3936                           func (stream, "!");
3937                         else if (rm != 0xf)
3938                           func (stream, ", %s", arm_regnames[rm]);
3939                       }
3940                       break;
3941
3942                     case 'B':
3943                       {
3944                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
3945                         int rn = ((given >> 16) & 0xf);
3946                         int rm = ((given >> 0) & 0xf);
3947                         int idx_align = ((given >> 4) & 0xf);
3948                         int align = 0;
3949                         int size = ((given >> 10) & 0x3);
3950                         int idx = idx_align >> (size + 1);
3951                         int length = ((given >> 8) & 3) + 1;
3952                         int stride = 1;
3953                         int i;
3954
3955                         if (length > 1 && size > 0)
3956                           stride = (idx_align & (1 << size)) ? 2 : 1;
3957
3958                         switch (length)
3959                           {
3960                           case 1:
3961                             {
3962                               int amask = (1 << size) - 1;
3963                               if ((idx_align & (1 << size)) != 0)
3964                                 return FALSE;
3965                               if (size > 0)
3966                                 {
3967                                   if ((idx_align & amask) == amask)
3968                                     align = 8 << size;
3969                                   else if ((idx_align & amask) != 0)
3970                                     return FALSE;
3971                                 }
3972                               }
3973                             break;
3974
3975                           case 2:
3976                             if (size == 2 && (idx_align & 2) != 0)
3977                               return FALSE;
3978                             align = (idx_align & 1) ? 16 << size : 0;
3979                             break;
3980
3981                           case 3:
3982                             if ((size == 2 && (idx_align & 3) != 0)
3983                                 || (idx_align & 1) != 0)
3984                               return FALSE;
3985                             break;
3986
3987                           case 4:
3988                             if (size == 2)
3989                               {
3990                                 if ((idx_align & 3) == 3)
3991                                   return FALSE;
3992                                 align = (idx_align & 3) * 64;
3993                               }
3994                             else
3995                               align = (idx_align & 1) ? 32 << size : 0;
3996                             break;
3997
3998                           default:
3999                             abort ();
4000                           }
4001
4002                         func (stream, "{");
4003                         for (i = 0; i < length; i++)
4004                           func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4005                             rd + i * stride, idx);
4006                         func (stream, "}, [%s", arm_regnames[rn]);
4007                         if (align)
4008                           func (stream, " :%d", align);
4009                         func (stream, "]");
4010                         if (rm == 0xd)
4011                           func (stream, "!");
4012                         else if (rm != 0xf)
4013                           func (stream, ", %s", arm_regnames[rm]);
4014                       }
4015                       break;
4016
4017                     case 'C':
4018                       {
4019                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4020                         int rn = ((given >> 16) & 0xf);
4021                         int rm = ((given >> 0) & 0xf);
4022                         int align = ((given >> 4) & 0x1);
4023                         int size = ((given >> 6) & 0x3);
4024                         int type = ((given >> 8) & 0x3);
4025                         int n = type + 1;
4026                         int stride = ((given >> 5) & 0x1);
4027                         int ix;
4028
4029                         if (stride && (n == 1))
4030                           n++;
4031                         else
4032                           stride++;
4033
4034                         func (stream, "{");
4035                         if (stride > 1)
4036                           for (ix = 0; ix != n; ix++)
4037                             func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4038                         else if (n == 1)
4039                           func (stream, "d%d[]", rd);
4040                         else
4041                           func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4042                         func (stream, "}, [%s", arm_regnames[rn]);
4043                         if (align)
4044                           {
4045                             align = (8 * (type + 1)) << size;
4046                             if (type == 3)
4047                               align = (size > 1) ? align >> 1 : align;
4048                             if (type == 2 || (type == 0 && !size))
4049                               func (stream, " :<bad align %d>", align);
4050                             else
4051                               func (stream, " :%d", align);
4052                           }
4053                         func (stream, "]");
4054                         if (rm == 0xd)
4055                           func (stream, "!");
4056                         else if (rm != 0xf)
4057                           func (stream, ", %s", arm_regnames[rm]);
4058                       }
4059                       break;
4060
4061                     case 'D':
4062                       {
4063                         int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4064                         int size = (given >> 20) & 3;
4065                         int reg = raw_reg & ((4 << size) - 1);
4066                         int ix = raw_reg >> size >> 2;
4067
4068                         func (stream, "d%d[%d]", reg, ix);
4069                       }
4070                       break;
4071
4072                     case 'E':
4073                       /* Neon encoded constant for mov, mvn, vorr, vbic.  */
4074                       {
4075                         int bits = 0;
4076                         int cmode = (given >> 8) & 0xf;
4077                         int op = (given >> 5) & 0x1;
4078                         unsigned long value = 0, hival = 0;
4079                         unsigned shift;
4080                         int size = 0;
4081                         int isfloat = 0;
4082
4083                         bits |= ((given >> 24) & 1) << 7;
4084                         bits |= ((given >> 16) & 7) << 4;
4085                         bits |= ((given >> 0) & 15) << 0;
4086
4087                         if (cmode < 8)
4088                           {
4089                             shift = (cmode >> 1) & 3;
4090                             value = (unsigned long) bits << (8 * shift);
4091                             size = 32;
4092                           }
4093                         else if (cmode < 12)
4094                           {
4095                             shift = (cmode >> 1) & 1;
4096                             value = (unsigned long) bits << (8 * shift);
4097                             size = 16;
4098                           }
4099                         else if (cmode < 14)
4100                           {
4101                             shift = (cmode & 1) + 1;
4102                             value = (unsigned long) bits << (8 * shift);
4103                             value |= (1ul << (8 * shift)) - 1;
4104                             size = 32;
4105                           }
4106                         else if (cmode == 14)
4107                           {
4108                             if (op)
4109                               {
4110                                 /* Bit replication into bytes.  */
4111                                 int ix;
4112                                 unsigned long mask;
4113
4114                                 value = 0;
4115                                 hival = 0;
4116                                 for (ix = 7; ix >= 0; ix--)
4117                                   {
4118                                     mask = ((bits >> ix) & 1) ? 0xff : 0;
4119                                     if (ix <= 3)
4120                                       value = (value << 8) | mask;
4121                                     else
4122                                       hival = (hival << 8) | mask;
4123                                   }
4124                                 size = 64;
4125                               }
4126                             else
4127                               {
4128                                 /* Byte replication.  */
4129                                 value = (unsigned long) bits;
4130                                 size = 8;
4131                               }
4132                           }
4133                         else if (!op)
4134                           {
4135                             /* Floating point encoding.  */
4136                             int tmp;
4137
4138                             value = (unsigned long)  (bits & 0x7f) << 19;
4139                             value |= (unsigned long) (bits & 0x80) << 24;
4140                             tmp = bits & 0x40 ? 0x3c : 0x40;
4141                             value |= (unsigned long) tmp << 24;
4142                             size = 32;
4143                             isfloat = 1;
4144                           }
4145                         else
4146                           {
4147                             func (stream, "<illegal constant %.8x:%x:%x>",
4148                                   bits, cmode, op);
4149                             size = 32;
4150                             break;
4151                           }
4152                         switch (size)
4153                           {
4154                           case 8:
4155                             func (stream, "#%ld\t; 0x%.2lx", value, value);
4156                             break;
4157
4158                           case 16:
4159                             func (stream, "#%ld\t; 0x%.4lx", value, value);
4160                             break;
4161
4162                           case 32:
4163                             if (isfloat)
4164                               {
4165                                 unsigned char valbytes[4];
4166                                 double fvalue;
4167
4168                                 /* Do this a byte at a time so we don't have to
4169                                    worry about the host's endianness.  */
4170                                 valbytes[0] = value & 0xff;
4171                                 valbytes[1] = (value >> 8) & 0xff;
4172                                 valbytes[2] = (value >> 16) & 0xff;
4173                                 valbytes[3] = (value >> 24) & 0xff;
4174
4175                                 floatformat_to_double
4176                                   (& floatformat_ieee_single_little, valbytes,
4177                                   & fvalue);
4178
4179                                 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4180                                       value);
4181                               }
4182                             else
4183                               func (stream, "#%ld\t; 0x%.8lx",
4184                                     (long) (((value & 0x80000000L) != 0)
4185                                             ? value | ~0xffffffffL : value),
4186                                     value);
4187                             break;
4188
4189                           case 64:
4190                             func (stream, "#0x%.8lx%.8lx", hival, value);
4191                             break;
4192
4193                           default:
4194                             abort ();
4195                           }
4196                       }
4197                       break;
4198
4199                     case 'F':
4200                       {
4201                         int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4202                         int num = (given >> 8) & 0x3;
4203
4204                         if (!num)
4205                           func (stream, "{d%d}", regno);
4206                         else if (num + regno >= 32)
4207                           func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4208                         else
4209                           func (stream, "{d%d-d%d}", regno, regno + num);
4210                       }
4211                       break;
4212
4213
4214                     case '0': case '1': case '2': case '3': case '4':
4215                     case '5': case '6': case '7': case '8': case '9':
4216                       {
4217                         int width;
4218                         unsigned long value;
4219
4220                         c = arm_decode_bitfield (c, given, &value, &width);
4221
4222                         switch (*c)
4223                           {
4224                           case 'r':
4225                             func (stream, "%s", arm_regnames[value]);
4226                             break;
4227                           case 'd':
4228                             func (stream, "%ld", value);
4229                             value_in_comment = value;
4230                             break;
4231                           case 'e':
4232                             func (stream, "%ld", (1ul << width) - value);
4233                             break;
4234
4235                           case 'S':
4236                           case 'T':
4237                           case 'U':
4238                             /* Various width encodings.  */
4239                             {
4240                               int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4241                               int limit;
4242                               unsigned low, high;
4243
4244                               c++;
4245                               if (*c >= '0' && *c <= '9')
4246                                 limit = *c - '0';
4247                               else if (*c >= 'a' && *c <= 'f')
4248                                 limit = *c - 'a' + 10;
4249                               else
4250                                 abort ();
4251                               low = limit >> 2;
4252                               high = limit & 3;
4253
4254                               if (value < low || value > high)
4255                                 func (stream, "<illegal width %d>", base << value);
4256                               else
4257                                 func (stream, "%d", base << value);
4258                             }
4259                             break;
4260                           case 'R':
4261                             if (given & (1 << 6))
4262                               goto Q;
4263                             /* FALLTHROUGH */
4264                           case 'D':
4265                             func (stream, "d%ld", value);
4266                             break;
4267                           case 'Q':
4268                           Q:
4269                             if (value & 1)
4270                               func (stream, "<illegal reg q%ld.5>", value >> 1);
4271                             else
4272                               func (stream, "q%ld", value >> 1);
4273                             break;
4274
4275                           case '`':
4276                             c++;
4277                             if (value == 0)
4278                               func (stream, "%c", *c);
4279                             break;
4280                           case '\'':
4281                             c++;
4282                             if (value == ((1ul << width) - 1))
4283                               func (stream, "%c", *c);
4284                             break;
4285                           case '?':
4286                             func (stream, "%c", c[(1 << width) - (int) value]);
4287                             c += 1 << width;
4288                             break;
4289                           default:
4290                             abort ();
4291                           }
4292                         break;
4293
4294                       default:
4295                         abort ();
4296                       }
4297                     }
4298                 }
4299               else
4300                 func (stream, "%c", *c);
4301             }
4302
4303           if (value_in_comment > 32 || value_in_comment < -16)
4304             func (stream, "\t; 0x%lx", value_in_comment);
4305
4306           if (is_unpredictable)
4307             func (stream, UNPREDICTABLE_INSTRUCTION);
4308
4309           return TRUE;
4310         }
4311     }
4312   return FALSE;
4313 }
4314
4315 /* Return the name of a v7A special register.  */
4316
4317 static const char *
4318 banked_regname (unsigned reg)
4319 {
4320   switch (reg)
4321     {
4322       case 15: return "CPSR";
4323       case 32: return "R8_usr";
4324       case 33: return "R9_usr";
4325       case 34: return "R10_usr";
4326       case 35: return "R11_usr";
4327       case 36: return "R12_usr";
4328       case 37: return "SP_usr";
4329       case 38: return "LR_usr";
4330       case 40: return "R8_fiq";
4331       case 41: return "R9_fiq";
4332       case 42: return "R10_fiq";
4333       case 43: return "R11_fiq";
4334       case 44: return "R12_fiq";
4335       case 45: return "SP_fiq";
4336       case 46: return "LR_fiq";
4337       case 48: return "LR_irq";
4338       case 49: return "SP_irq";
4339       case 50: return "LR_svc";
4340       case 51: return "SP_svc";
4341       case 52: return "LR_abt";
4342       case 53: return "SP_abt";
4343       case 54: return "LR_und";
4344       case 55: return "SP_und";
4345       case 60: return "LR_mon";
4346       case 61: return "SP_mon";
4347       case 62: return "ELR_hyp";
4348       case 63: return "SP_hyp";
4349       case 79: return "SPSR";
4350       case 110: return "SPSR_fiq";
4351       case 112: return "SPSR_irq";
4352       case 114: return "SPSR_svc";
4353       case 116: return "SPSR_abt";
4354       case 118: return "SPSR_und";
4355       case 124: return "SPSR_mon";
4356       case 126: return "SPSR_hyp";
4357       default: return NULL;
4358     }
4359 }
4360
4361 /* Return the name of the DMB/DSB option.  */
4362 static const char *
4363 data_barrier_option (unsigned option)
4364 {
4365   switch (option & 0xf)
4366     {
4367     case 0xf: return "sy";
4368     case 0xe: return "st";
4369     case 0xd: return "ld";
4370     case 0xb: return "ish";
4371     case 0xa: return "ishst";
4372     case 0x9: return "ishld";
4373     case 0x7: return "un";
4374     case 0x6: return "unst";
4375     case 0x5: return "nshld";
4376     case 0x3: return "osh";
4377     case 0x2: return "oshst";
4378     case 0x1: return "oshld";
4379     default:  return NULL;
4380     }
4381 }
4382
4383 /* Print one ARM instruction from PC on INFO->STREAM.  */
4384
4385 static void
4386 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
4387 {
4388   const struct opcode32 *insn;
4389   void *stream = info->stream;
4390   fprintf_ftype func = info->fprintf_func;
4391   struct arm_private_data *private_data = info->private_data;
4392
4393   if (print_insn_coprocessor (pc, info, given, FALSE))
4394     return;
4395
4396   if (print_insn_neon (info, given, FALSE))
4397     return;
4398
4399   for (insn = arm_opcodes; insn->assembler; insn++)
4400     {
4401       if ((given & insn->mask) != insn->value)
4402         continue;
4403
4404       if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
4405         continue;
4406
4407       /* Special case: an instruction with all bits set in the condition field
4408          (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4409          or by the catchall at the end of the table.  */
4410       if ((given & 0xF0000000) != 0xF0000000
4411           || (insn->mask & 0xF0000000) == 0xF0000000
4412           || (insn->mask == 0 && insn->value == 0))
4413         {
4414           unsigned long u_reg = 16;
4415           unsigned long U_reg = 16;
4416           bfd_boolean is_unpredictable = FALSE;
4417           signed long value_in_comment = 0;
4418           const char *c;
4419
4420           for (c = insn->assembler; *c; c++)
4421             {
4422               if (*c == '%')
4423                 {
4424                   bfd_boolean allow_unpredictable = FALSE;
4425
4426                   switch (*++c)
4427                     {
4428                     case '%':
4429                       func (stream, "%%");
4430                       break;
4431
4432                     case 'a':
4433                       value_in_comment = print_arm_address (pc, info, given);
4434                       break;
4435
4436                     case 'P':
4437                       /* Set P address bit and use normal address
4438                          printing routine.  */
4439                       value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
4440                       break;
4441
4442                     case 'S':
4443                       allow_unpredictable = TRUE;
4444                     case 's':
4445                       if ((given & 0x004f0000) == 0x004f0000)
4446                         {
4447                           /* PC relative with immediate offset.  */
4448                           bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
4449
4450                           if (PRE_BIT_SET)
4451                             {
4452                               /* Elide positive zero offset.  */
4453                               if (offset || NEGATIVE_BIT_SET)
4454                                 func (stream, "[pc, #%s%d]\t; ",
4455                                       NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4456                               else
4457                                 func (stream, "[pc]\t; ");
4458                               if (NEGATIVE_BIT_SET)
4459                                 offset = -offset;
4460                               info->print_address_func (offset + pc + 8, info);
4461                             }
4462                           else
4463                             {
4464                               /* Always show the offset.  */
4465                               func (stream, "[pc], #%s%d",
4466                                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4467                               if (! allow_unpredictable)
4468                                 is_unpredictable = TRUE;
4469                             }
4470                         }
4471                       else
4472                         {
4473                           int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4474
4475                           func (stream, "[%s",
4476                                 arm_regnames[(given >> 16) & 0xf]);
4477
4478                           if (PRE_BIT_SET)
4479                             {
4480                               if (IMMEDIATE_BIT_SET)
4481                                 {
4482                                   /* Elide offset for non-writeback
4483                                      positive zero.  */
4484                                   if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4485                                       || offset)
4486                                     func (stream, ", #%s%d",
4487                                           NEGATIVE_BIT_SET ? "-" : "", offset);
4488
4489                                   if (NEGATIVE_BIT_SET)
4490                                     offset = -offset;
4491
4492                                   value_in_comment = offset;
4493                                 }
4494                               else
4495                                 {
4496                                   /* Register Offset or Register Pre-Indexed.  */
4497                                   func (stream, ", %s%s",
4498                                         NEGATIVE_BIT_SET ? "-" : "",
4499                                         arm_regnames[given & 0xf]);
4500
4501                                   /* Writing back to the register that is the source/
4502                                      destination of the load/store is unpredictable.  */
4503                                   if (! allow_unpredictable
4504                                       && WRITEBACK_BIT_SET
4505                                       && ((given & 0xf) == ((given >> 12) & 0xf)))
4506                                     is_unpredictable = TRUE;
4507                                 }
4508
4509                               func (stream, "]%s",
4510                                     WRITEBACK_BIT_SET ? "!" : "");
4511                             }
4512                           else
4513                             {
4514                               if (IMMEDIATE_BIT_SET)
4515                                 {
4516                                   /* Immediate Post-indexed.  */
4517                                   /* PR 10924: Offset must be printed, even if it is zero.  */
4518                                   func (stream, "], #%s%d",
4519                                         NEGATIVE_BIT_SET ? "-" : "", offset);
4520                                   if (NEGATIVE_BIT_SET)
4521                                     offset = -offset;
4522                                   value_in_comment = offset;
4523                                 }
4524                               else
4525                                 {
4526                                   /* Register Post-indexed.  */
4527                                   func (stream, "], %s%s",
4528                                         NEGATIVE_BIT_SET ? "-" : "",
4529                                         arm_regnames[given & 0xf]);
4530
4531                                   /* Writing back to the register that is the source/
4532                                      destination of the load/store is unpredictable.  */
4533                                   if (! allow_unpredictable
4534                                       && (given & 0xf) == ((given >> 12) & 0xf))
4535                                     is_unpredictable = TRUE;
4536                                 }
4537
4538                               if (! allow_unpredictable)
4539                                 {
4540                                   /* Writeback is automatically implied by post- addressing.
4541                                      Setting the W bit is unnecessary and ARM specify it as
4542                                      being unpredictable.  */
4543                                   if (WRITEBACK_BIT_SET
4544                                       /* Specifying the PC register as the post-indexed
4545                                          registers is also unpredictable.  */
4546                                       || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4547                                     is_unpredictable = TRUE;
4548                                 }
4549                             }
4550                         }
4551                       break;
4552
4553                     case 'b':
4554                       {
4555                         bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
4556                         info->print_address_func (disp * 4 + pc + 8, info);
4557                       }
4558                       break;
4559
4560                     case 'c':
4561                       if (((given >> 28) & 0xf) != 0xe)
4562                         func (stream, "%s",
4563                               arm_conditional [(given >> 28) & 0xf]);
4564                       break;
4565
4566                     case 'm':
4567                       {
4568                         int started = 0;
4569                         int reg;
4570
4571                         func (stream, "{");
4572                         for (reg = 0; reg < 16; reg++)
4573                           if ((given & (1 << reg)) != 0)
4574                             {
4575                               if (started)
4576                                 func (stream, ", ");
4577                               started = 1;
4578                               func (stream, "%s", arm_regnames[reg]);
4579                             }
4580                         func (stream, "}");
4581                         if (! started)
4582                           is_unpredictable = TRUE;
4583                       }
4584                       break;
4585
4586                     case 'q':
4587                       arm_decode_shift (given, func, stream, FALSE);
4588                       break;
4589
4590                     case 'o':
4591                       if ((given & 0x02000000) != 0)
4592                         {
4593                           unsigned int rotate = (given & 0xf00) >> 7;
4594                           unsigned int immed = (given & 0xff);
4595                           unsigned int a, i;
4596
4597                           a = (((immed << (32 - rotate))
4598                                 | (immed >> rotate)) & 0xffffffff);
4599                           /* If there is another encoding with smaller rotate,
4600                              the rotate should be specified directly.  */
4601                           for (i = 0; i < 32; i += 2)
4602                             if ((a << i | a >> (32 - i)) <= 0xff)
4603                               break;
4604
4605                           if (i != rotate)
4606                             func (stream, "#%d, %d", immed, rotate);
4607                           else
4608                             func (stream, "#%d", a);
4609                           value_in_comment = a;
4610                         }
4611                       else
4612                         arm_decode_shift (given, func, stream, TRUE);
4613                       break;
4614
4615                     case 'p':
4616                       if ((given & 0x0000f000) == 0x0000f000)
4617                         {
4618                           arm_feature_set arm_ext_v6 =
4619                             ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4620
4621                           /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4622                              mechanism for setting PSR flag bits.  They are
4623                              obsolete in V6 onwards.  */
4624                           if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4625                                                      arm_ext_v6))
4626                             func (stream, "p");
4627                         }
4628                       break;
4629
4630                     case 't':
4631                       if ((given & 0x01200000) == 0x00200000)
4632                         func (stream, "t");
4633                       break;
4634
4635                     case 'A':
4636                       {
4637                         int offset = given & 0xff;
4638
4639                         value_in_comment = offset * 4;
4640                         if (NEGATIVE_BIT_SET)
4641                           value_in_comment = - value_in_comment;
4642
4643                         func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
4644
4645                         if (PRE_BIT_SET)
4646                           {
4647                             if (offset)
4648                               func (stream, ", #%d]%s",
4649                                     (int) value_in_comment,
4650                                     WRITEBACK_BIT_SET ? "!" : "");
4651                             else
4652                               func (stream, "]");
4653                           }
4654                         else
4655                           {
4656                             func (stream, "]");
4657
4658                             if (WRITEBACK_BIT_SET)
4659                               {
4660                                 if (offset)
4661                                   func (stream, ", #%d", (int) value_in_comment);
4662                               }
4663                             else
4664                               {
4665                                 func (stream, ", {%d}", (int) offset);
4666                                 value_in_comment = offset;
4667                               }
4668                           }
4669                       }
4670                       break;
4671
4672                     case 'B':
4673                       /* Print ARM V5 BLX(1) address: pc+25 bits.  */
4674                       {
4675                         bfd_vma address;
4676                         bfd_vma offset = 0;
4677
4678                         if (! NEGATIVE_BIT_SET)
4679                           /* Is signed, hi bits should be ones.  */
4680                           offset = (-1) ^ 0x00ffffff;
4681
4682                         /* Offset is (SignExtend(offset field)<<2).  */
4683                         offset += given & 0x00ffffff;
4684                         offset <<= 2;
4685                         address = offset + pc + 8;
4686
4687                         if (given & 0x01000000)
4688                           /* H bit allows addressing to 2-byte boundaries.  */
4689                           address += 2;
4690
4691                         info->print_address_func (address, info);
4692                       }
4693                       break;
4694
4695                     case 'C':
4696                       if ((given & 0x02000200) == 0x200)
4697                         {
4698                           const char * name;
4699                           unsigned sysm = (given & 0x004f0000) >> 16;
4700
4701                           sysm |= (given & 0x300) >> 4;
4702                           name = banked_regname (sysm);
4703
4704                           if (name != NULL)
4705                             func (stream, "%s", name);
4706                           else
4707                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
4708                         }
4709                       else
4710                         {
4711                           func (stream, "%cPSR_",
4712                                 (given & 0x00400000) ? 'S' : 'C');
4713                           if (given & 0x80000)
4714                             func (stream, "f");
4715                           if (given & 0x40000)
4716                             func (stream, "s");
4717                           if (given & 0x20000)
4718                             func (stream, "x");
4719                           if (given & 0x10000)
4720                             func (stream, "c");
4721                         }
4722                       break;
4723
4724                     case 'U':
4725                       if ((given & 0xf0) == 0x60)
4726                         {
4727                           switch (given & 0xf)
4728                             {
4729                             case 0xf: func (stream, "sy"); break;
4730                             default:
4731                               func (stream, "#%d", (int) given & 0xf);
4732                               break;
4733                             }
4734                         }
4735                       else
4736                         {
4737                           const char * opt = data_barrier_option (given & 0xf);
4738                           if (opt != NULL)
4739                             func (stream, "%s", opt);
4740                           else
4741                               func (stream, "#%d", (int) given & 0xf);
4742                         }
4743                       break;
4744
4745                     case '0': case '1': case '2': case '3': case '4':
4746                     case '5': case '6': case '7': case '8': case '9':
4747                       {
4748                         int width;
4749                         unsigned long value;
4750
4751                         c = arm_decode_bitfield (c, given, &value, &width);
4752
4753                         switch (*c)
4754                           {
4755                           case 'R':
4756                             if (value == 15)
4757                               is_unpredictable = TRUE;
4758                             /* Fall through.  */
4759                           case 'r':
4760                           case 'T':
4761                             /* We want register + 1 when decoding T.  */
4762                             if (*c == 'T')
4763                               ++value;
4764
4765                             if (c[1] == 'u')
4766                               {
4767                                 /* Eat the 'u' character.  */
4768                                 ++ c;
4769
4770                                 if (u_reg == value)
4771                                   is_unpredictable = TRUE;
4772                                 u_reg = value;
4773                               }
4774                             if (c[1] == 'U')
4775                               {
4776                                 /* Eat the 'U' character.  */
4777                                 ++ c;
4778
4779                                 if (U_reg == value)
4780                                   is_unpredictable = TRUE;
4781                                 U_reg = value;
4782                               }
4783                             func (stream, "%s", arm_regnames[value]);
4784                             break;
4785                           case 'd':
4786                             func (stream, "%ld", value);
4787                             value_in_comment = value;
4788                             break;
4789                           case 'b':
4790                             func (stream, "%ld", value * 8);
4791                             value_in_comment = value * 8;
4792                             break;
4793                           case 'W':
4794                             func (stream, "%ld", value + 1);
4795                             value_in_comment = value + 1;
4796                             break;
4797                           case 'x':
4798                             func (stream, "0x%08lx", value);
4799
4800                             /* Some SWI instructions have special
4801                                meanings.  */
4802                             if ((given & 0x0fffffff) == 0x0FF00000)
4803                               func (stream, "\t; IMB");
4804                             else if ((given & 0x0fffffff) == 0x0FF00001)
4805                               func (stream, "\t; IMBRange");
4806                             break;
4807                           case 'X':
4808                             func (stream, "%01lx", value & 0xf);
4809                             value_in_comment = value;
4810                             break;
4811                           case '`':
4812                             c++;
4813                             if (value == 0)
4814                               func (stream, "%c", *c);
4815                             break;
4816                           case '\'':
4817                             c++;
4818                             if (value == ((1ul << width) - 1))
4819                               func (stream, "%c", *c);
4820                             break;
4821                           case '?':
4822                             func (stream, "%c", c[(1 << width) - (int) value]);
4823                             c += 1 << width;
4824                             break;
4825                           default:
4826                             abort ();
4827                           }
4828                         break;
4829
4830                       case 'e':
4831                         {
4832                           int imm;
4833
4834                           imm = (given & 0xf) | ((given & 0xfff00) >> 4);
4835                           func (stream, "%d", imm);
4836                           value_in_comment = imm;
4837                         }
4838                         break;
4839
4840                       case 'E':
4841                         /* LSB and WIDTH fields of BFI or BFC.  The machine-
4842                            language instruction encodes LSB and MSB.  */
4843                         {
4844                           long msb = (given & 0x001f0000) >> 16;
4845                           long lsb = (given & 0x00000f80) >> 7;
4846                           long w = msb - lsb + 1;
4847
4848                           if (w > 0)
4849                             func (stream, "#%lu, #%lu", lsb, w);
4850                           else
4851                             func (stream, "(invalid: %lu:%lu)", lsb, msb);
4852                         }
4853                         break;
4854
4855                       case 'R':
4856                         /* Get the PSR/banked register name.  */
4857                         {
4858                           const char * name;
4859                           unsigned sysm = (given & 0x004f0000) >> 16;
4860
4861                           sysm |= (given & 0x300) >> 4;
4862                           name = banked_regname (sysm);
4863
4864                           if (name != NULL)
4865                             func (stream, "%s", name);
4866                           else
4867                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
4868                         }
4869                         break;
4870
4871                       case 'V':
4872                         /* 16-bit unsigned immediate from a MOVT or MOVW
4873                            instruction, encoded in bits 0:11 and 15:19.  */
4874                         {
4875                           long hi = (given & 0x000f0000) >> 4;
4876                           long lo = (given & 0x00000fff);
4877                           long imm16 = hi | lo;
4878
4879                           func (stream, "#%lu", imm16);
4880                           value_in_comment = imm16;
4881                         }
4882                         break;
4883
4884                       default:
4885                         abort ();
4886                       }
4887                     }
4888                 }
4889               else
4890                 func (stream, "%c", *c);
4891             }
4892
4893           if (value_in_comment > 32 || value_in_comment < -16)
4894             func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
4895
4896           if (is_unpredictable)
4897             func (stream, UNPREDICTABLE_INSTRUCTION);
4898
4899           return;
4900         }
4901     }
4902   abort ();
4903 }
4904
4905 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM.  */
4906
4907 static void
4908 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
4909 {
4910   const struct opcode16 *insn;
4911   void *stream = info->stream;
4912   fprintf_ftype func = info->fprintf_func;
4913
4914   for (insn = thumb_opcodes; insn->assembler; insn++)
4915     if ((given & insn->mask) == insn->value)
4916       {
4917         signed long value_in_comment = 0;
4918         const char *c = insn->assembler;
4919
4920         for (; *c; c++)
4921           {
4922             int domaskpc = 0;
4923             int domasklr = 0;
4924
4925             if (*c != '%')
4926               {
4927                 func (stream, "%c", *c);
4928                 continue;
4929               }
4930
4931             switch (*++c)
4932               {
4933               case '%':
4934                 func (stream, "%%");
4935                 break;
4936
4937               case 'c':
4938                 if (ifthen_state)
4939                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
4940                 break;
4941
4942               case 'C':
4943                 if (ifthen_state)
4944                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
4945                 else
4946                   func (stream, "s");
4947                 break;
4948
4949               case 'I':
4950                 {
4951                   unsigned int tmp;
4952
4953                   ifthen_next_state = given & 0xff;
4954                   for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
4955                     func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
4956                   func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
4957                 }
4958                 break;
4959
4960               case 'x':
4961                 if (ifthen_next_state)
4962                   func (stream, "\t; unpredictable branch in IT block\n");
4963                 break;
4964
4965               case 'X':
4966                 if (ifthen_state)
4967                   func (stream, "\t; unpredictable <IT:%s>",
4968                         arm_conditional[IFTHEN_COND]);
4969                 break;
4970
4971               case 'S':
4972                 {
4973                   long reg;
4974
4975                   reg = (given >> 3) & 0x7;
4976                   if (given & (1 << 6))
4977                     reg += 8;
4978
4979                   func (stream, "%s", arm_regnames[reg]);
4980                 }
4981                 break;
4982
4983               case 'D':
4984                 {
4985                   long reg;
4986
4987                   reg = given & 0x7;
4988                   if (given & (1 << 7))
4989                     reg += 8;
4990
4991                   func (stream, "%s", arm_regnames[reg]);
4992                 }
4993                 break;
4994
4995               case 'N':
4996                 if (given & (1 << 8))
4997                   domasklr = 1;
4998                 /* Fall through.  */
4999               case 'O':
5000                 if (*c == 'O' && (given & (1 << 8)))
5001                   domaskpc = 1;
5002                 /* Fall through.  */
5003               case 'M':
5004                 {
5005                   int started = 0;
5006                   int reg;
5007
5008                   func (stream, "{");
5009
5010                   /* It would be nice if we could spot
5011                      ranges, and generate the rS-rE format: */
5012                   for (reg = 0; (reg < 8); reg++)
5013                     if ((given & (1 << reg)) != 0)
5014                       {
5015                         if (started)
5016                           func (stream, ", ");
5017                         started = 1;
5018                         func (stream, "%s", arm_regnames[reg]);
5019                       }
5020
5021                   if (domasklr)
5022                     {
5023                       if (started)
5024                         func (stream, ", ");
5025                       started = 1;
5026                       func (stream, "%s", arm_regnames[14] /* "lr" */);
5027                     }
5028
5029                   if (domaskpc)
5030                     {
5031                       if (started)
5032                         func (stream, ", ");
5033                       func (stream, "%s", arm_regnames[15] /* "pc" */);
5034                     }
5035
5036                   func (stream, "}");
5037                 }
5038                 break;
5039
5040               case 'W':
5041                 /* Print writeback indicator for a LDMIA.  We are doing a
5042                    writeback if the base register is not in the register
5043                    mask.  */
5044                 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5045                   func (stream, "!");
5046                 break;
5047
5048               case 'b':
5049                 /* Print ARM V6T2 CZB address: pc+4+6 bits.  */
5050                 {
5051                   bfd_vma address = (pc + 4
5052                                      + ((given & 0x00f8) >> 2)
5053                                      + ((given & 0x0200) >> 3));
5054                   info->print_address_func (address, info);
5055                 }
5056                 break;
5057
5058               case 's':
5059                 /* Right shift immediate -- bits 6..10; 1-31 print
5060                    as themselves, 0 prints as 32.  */
5061                 {
5062                   long imm = (given & 0x07c0) >> 6;
5063                   if (imm == 0)
5064                     imm = 32;
5065                   func (stream, "#%ld", imm);
5066                 }
5067                 break;
5068
5069               case '0': case '1': case '2': case '3': case '4':
5070               case '5': case '6': case '7': case '8': case '9':
5071                 {
5072                   int bitstart = *c++ - '0';
5073                   int bitend = 0;
5074
5075                   while (*c >= '0' && *c <= '9')
5076                     bitstart = (bitstart * 10) + *c++ - '0';
5077
5078                   switch (*c)
5079                     {
5080                     case '-':
5081                       {
5082                         bfd_vma reg;
5083
5084                         c++;
5085                         while (*c >= '0' && *c <= '9')
5086                           bitend = (bitend * 10) + *c++ - '0';
5087                         if (!bitend)
5088                           abort ();
5089                         reg = given >> bitstart;
5090                         reg &= (2 << (bitend - bitstart)) - 1;
5091
5092                         switch (*c)
5093                           {
5094                           case 'r':
5095                             func (stream, "%s", arm_regnames[reg]);
5096                             break;
5097
5098                           case 'd':
5099                             func (stream, "%ld", (long) reg);
5100                             value_in_comment = reg;
5101                             break;
5102
5103                           case 'H':
5104                             func (stream, "%ld", (long) (reg << 1));
5105                             value_in_comment = reg << 1;
5106                             break;
5107
5108                           case 'W':
5109                             func (stream, "%ld", (long) (reg << 2));
5110                             value_in_comment = reg << 2;
5111                             break;
5112
5113                           case 'a':
5114                             /* PC-relative address -- the bottom two
5115                                bits of the address are dropped
5116                                before the calculation.  */
5117                             info->print_address_func
5118                               (((pc + 4) & ~3) + (reg << 2), info);
5119                             value_in_comment = 0;
5120                             break;
5121
5122                           case 'x':
5123                             func (stream, "0x%04lx", (long) reg);
5124                             break;
5125
5126                           case 'B':
5127                             reg = ((reg ^ (1 << bitend)) - (1 << bitend));
5128                             info->print_address_func (reg * 2 + pc + 4, info);
5129                             value_in_comment = 0;
5130                             break;
5131
5132                           case 'c':
5133                             func (stream, "%s", arm_conditional [reg]);
5134                             break;
5135
5136                           default:
5137                             abort ();
5138                           }
5139                       }
5140                       break;
5141
5142                     case '\'':
5143                       c++;
5144                       if ((given & (1 << bitstart)) != 0)
5145                         func (stream, "%c", *c);
5146                       break;
5147
5148                     case '?':
5149                       ++c;
5150                       if ((given & (1 << bitstart)) != 0)
5151                         func (stream, "%c", *c++);
5152                       else
5153                         func (stream, "%c", *++c);
5154                       break;
5155
5156                     default:
5157                       abort ();
5158                     }
5159                 }
5160                 break;
5161
5162               default:
5163                 abort ();
5164               }
5165           }
5166
5167         if (value_in_comment > 32 || value_in_comment < -16)
5168           func (stream, "\t; 0x%lx", value_in_comment);
5169         return;
5170       }
5171
5172   /* No match.  */
5173   abort ();
5174 }
5175
5176 /* Return the name of an V7M special register.  */
5177
5178 static const char *
5179 psr_name (int regno)
5180 {
5181   switch (regno)
5182     {
5183     case 0: return "APSR";
5184     case 1: return "IAPSR";
5185     case 2: return "EAPSR";
5186     case 3: return "PSR";
5187     case 5: return "IPSR";
5188     case 6: return "EPSR";
5189     case 7: return "IEPSR";
5190     case 8: return "MSP";
5191     case 9: return "PSP";
5192     case 16: return "PRIMASK";
5193     case 17: return "BASEPRI";
5194     case 18: return "BASEPRI_MAX";
5195     case 19: return "FAULTMASK";
5196     case 20: return "CONTROL";
5197     default: return "<unknown>";
5198     }
5199 }
5200
5201 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM.  */
5202
5203 static void
5204 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
5205 {
5206   const struct opcode32 *insn;
5207   void *stream = info->stream;
5208   fprintf_ftype func = info->fprintf_func;
5209
5210   if (print_insn_coprocessor (pc, info, given, TRUE))
5211     return;
5212
5213   if (print_insn_neon (info, given, TRUE))
5214     return;
5215
5216   for (insn = thumb32_opcodes; insn->assembler; insn++)
5217     if ((given & insn->mask) == insn->value)
5218       {
5219         bfd_boolean is_unpredictable = FALSE;
5220         signed long value_in_comment = 0;
5221         const char *c = insn->assembler;
5222
5223         for (; *c; c++)
5224           {
5225             if (*c != '%')
5226               {
5227                 func (stream, "%c", *c);
5228                 continue;
5229               }
5230
5231             switch (*++c)
5232               {
5233               case '%':
5234                 func (stream, "%%");
5235                 break;
5236
5237               case 'c':
5238                 if (ifthen_state)
5239                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
5240                 break;
5241
5242               case 'x':
5243                 if (ifthen_next_state)
5244                   func (stream, "\t; unpredictable branch in IT block\n");
5245                 break;
5246
5247               case 'X':
5248                 if (ifthen_state)
5249                   func (stream, "\t; unpredictable <IT:%s>",
5250                         arm_conditional[IFTHEN_COND]);
5251                 break;
5252
5253               case 'I':
5254                 {
5255                   unsigned int imm12 = 0;
5256
5257                   imm12 |= (given & 0x000000ffu);
5258                   imm12 |= (given & 0x00007000u) >> 4;
5259                   imm12 |= (given & 0x04000000u) >> 15;
5260                   func (stream, "#%u", imm12);
5261                   value_in_comment = imm12;
5262                 }
5263                 break;
5264
5265               case 'M':
5266                 {
5267                   unsigned int bits = 0, imm, imm8, mod;
5268
5269                   bits |= (given & 0x000000ffu);
5270                   bits |= (given & 0x00007000u) >> 4;
5271                   bits |= (given & 0x04000000u) >> 15;
5272                   imm8 = (bits & 0x0ff);
5273                   mod = (bits & 0xf00) >> 8;
5274                   switch (mod)
5275                     {
5276                     case 0: imm = imm8; break;
5277                     case 1: imm = ((imm8 << 16) | imm8); break;
5278                     case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5279                     case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
5280                     default:
5281                       mod  = (bits & 0xf80) >> 7;
5282                       imm8 = (bits & 0x07f) | 0x80;
5283                       imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5284                     }
5285                   func (stream, "#%u", imm);
5286                   value_in_comment = imm;
5287                 }
5288                 break;
5289
5290               case 'J':
5291                 {
5292                   unsigned int imm = 0;
5293
5294                   imm |= (given & 0x000000ffu);
5295                   imm |= (given & 0x00007000u) >> 4;
5296                   imm |= (given & 0x04000000u) >> 15;
5297                   imm |= (given & 0x000f0000u) >> 4;
5298                   func (stream, "#%u", imm);
5299                   value_in_comment = imm;
5300                 }
5301                 break;
5302
5303               case 'K':
5304                 {
5305                   unsigned int imm = 0;
5306
5307                   imm |= (given & 0x000f0000u) >> 16;
5308                   imm |= (given & 0x00000ff0u) >> 0;
5309                   imm |= (given & 0x0000000fu) << 12;
5310                   func (stream, "#%u", imm);
5311                   value_in_comment = imm;
5312                 }
5313                 break;
5314
5315               case 'H':
5316                 {
5317                   unsigned int imm = 0;
5318
5319                   imm |= (given & 0x000f0000u) >> 4;
5320                   imm |= (given & 0x00000fffu) >> 0;
5321                   func (stream, "#%u", imm);
5322                   value_in_comment = imm;
5323                 }
5324                 break;
5325
5326               case 'V':
5327                 {
5328                   unsigned int imm = 0;
5329
5330                   imm |= (given & 0x00000fffu);
5331                   imm |= (given & 0x000f0000u) >> 4;
5332                   func (stream, "#%u", imm);
5333                   value_in_comment = imm;
5334                 }
5335                 break;
5336
5337               case 'S':
5338                 {
5339                   unsigned int reg = (given & 0x0000000fu);
5340                   unsigned int stp = (given & 0x00000030u) >> 4;
5341                   unsigned int imm = 0;
5342                   imm |= (given & 0x000000c0u) >> 6;
5343                   imm |= (given & 0x00007000u) >> 10;
5344
5345                   func (stream, "%s", arm_regnames[reg]);
5346                   switch (stp)
5347                     {
5348                     case 0:
5349                       if (imm > 0)
5350                         func (stream, ", lsl #%u", imm);
5351                       break;
5352
5353                     case 1:
5354                       if (imm == 0)
5355                         imm = 32;
5356                       func (stream, ", lsr #%u", imm);
5357                       break;
5358
5359                     case 2:
5360                       if (imm == 0)
5361                         imm = 32;
5362                       func (stream, ", asr #%u", imm);
5363                       break;
5364
5365                     case 3:
5366                       if (imm == 0)
5367                         func (stream, ", rrx");
5368                       else
5369                         func (stream, ", ror #%u", imm);
5370                     }
5371                 }
5372                 break;
5373
5374               case 'a':
5375                 {
5376                   unsigned int Rn  = (given & 0x000f0000) >> 16;
5377                   unsigned int U   = ! NEGATIVE_BIT_SET;
5378                   unsigned int op  = (given & 0x00000f00) >> 8;
5379                   unsigned int i12 = (given & 0x00000fff);
5380                   unsigned int i8  = (given & 0x000000ff);
5381                   bfd_boolean writeback = FALSE, postind = FALSE;
5382                   bfd_vma offset = 0;
5383
5384                   func (stream, "[%s", arm_regnames[Rn]);
5385                   if (U) /* 12-bit positive immediate offset.  */
5386                     {
5387                       offset = i12;
5388                       if (Rn != 15)
5389                         value_in_comment = offset;
5390                     }
5391                   else if (Rn == 15) /* 12-bit negative immediate offset.  */
5392                     offset = - (int) i12;
5393                   else if (op == 0x0) /* Shifted register offset.  */
5394                     {
5395                       unsigned int Rm = (i8 & 0x0f);
5396                       unsigned int sh = (i8 & 0x30) >> 4;
5397
5398                       func (stream, ", %s", arm_regnames[Rm]);
5399                       if (sh)
5400                         func (stream, ", lsl #%u", sh);
5401                       func (stream, "]");
5402                       break;
5403                     }
5404                   else switch (op)
5405                     {
5406                     case 0xE:  /* 8-bit positive immediate offset.  */
5407                       offset = i8;
5408                       break;
5409
5410                     case 0xC:  /* 8-bit negative immediate offset.  */
5411                       offset = -i8;
5412                       break;
5413
5414                     case 0xF:  /* 8-bit + preindex with wb.  */
5415                       offset = i8;
5416                       writeback = TRUE;
5417                       break;
5418
5419                     case 0xD:  /* 8-bit - preindex with wb.  */
5420                       offset = -i8;
5421                       writeback = TRUE;
5422                       break;
5423
5424                     case 0xB:  /* 8-bit + postindex.  */
5425                       offset = i8;
5426                       postind = TRUE;
5427                       break;
5428
5429                     case 0x9:  /* 8-bit - postindex.  */
5430                       offset = -i8;
5431                       postind = TRUE;
5432                       break;
5433
5434                     default:
5435                       func (stream, ", <undefined>]");
5436                       goto skip;
5437                     }
5438
5439                   if (postind)
5440                     func (stream, "], #%d", (int) offset);
5441                   else
5442                     {
5443                       if (offset)
5444                         func (stream, ", #%d", (int) offset);
5445                       func (stream, writeback ? "]!" : "]");
5446                     }
5447
5448                   if (Rn == 15)
5449                     {
5450                       func (stream, "\t; ");
5451                       info->print_address_func (((pc + 4) & ~3) + offset, info);
5452                     }
5453                 }
5454               skip:
5455                 break;
5456
5457               case 'A':
5458                 {
5459                   unsigned int U   = ! NEGATIVE_BIT_SET;
5460                   unsigned int W   = WRITEBACK_BIT_SET;
5461                   unsigned int Rn  = (given & 0x000f0000) >> 16;
5462                   unsigned int off = (given & 0x000000ff);
5463
5464                   func (stream, "[%s", arm_regnames[Rn]);
5465
5466                   if (PRE_BIT_SET)
5467                     {
5468                       if (off || !U)
5469                         {
5470                           func (stream, ", #%c%u", U ? '+' : '-', off * 4);
5471                           value_in_comment = off * 4 * U ? 1 : -1;
5472                         }
5473                       func (stream, "]");
5474                       if (W)
5475                         func (stream, "!");
5476                     }
5477                   else
5478                     {
5479                       func (stream, "], ");
5480                       if (W)
5481                         {
5482                           func (stream, "#%c%u", U ? '+' : '-', off * 4);
5483                           value_in_comment = off * 4 * U ? 1 : -1;
5484                         }
5485                       else
5486                         {
5487                           func (stream, "{%u}", off);
5488                           value_in_comment = off;
5489                         }
5490                     }
5491                 }
5492                 break;
5493
5494               case 'w':
5495                 {
5496                   unsigned int Sbit = (given & 0x01000000) >> 24;
5497                   unsigned int type = (given & 0x00600000) >> 21;
5498
5499                   switch (type)
5500                     {
5501                     case 0: func (stream, Sbit ? "sb" : "b"); break;
5502                     case 1: func (stream, Sbit ? "sh" : "h"); break;
5503                     case 2:
5504                       if (Sbit)
5505                         func (stream, "??");
5506                       break;
5507                     case 3:
5508                       func (stream, "??");
5509                       break;
5510                     }
5511                 }
5512                 break;
5513
5514               case 'm':
5515                 {
5516                   int started = 0;
5517                   int reg;
5518
5519                   func (stream, "{");
5520                   for (reg = 0; reg < 16; reg++)
5521                     if ((given & (1 << reg)) != 0)
5522                       {
5523                         if (started)
5524                           func (stream, ", ");
5525                         started = 1;
5526                         func (stream, "%s", arm_regnames[reg]);
5527                       }
5528                   func (stream, "}");
5529                 }
5530                 break;
5531
5532               case 'E':
5533                 {
5534                   unsigned int msb = (given & 0x0000001f);
5535                   unsigned int lsb = 0;
5536
5537                   lsb |= (given & 0x000000c0u) >> 6;
5538                   lsb |= (given & 0x00007000u) >> 10;
5539                   func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5540                 }
5541                 break;
5542
5543               case 'F':
5544                 {
5545                   unsigned int width = (given & 0x0000001f) + 1;
5546                   unsigned int lsb = 0;
5547
5548                   lsb |= (given & 0x000000c0u) >> 6;
5549                   lsb |= (given & 0x00007000u) >> 10;
5550                   func (stream, "#%u, #%u", lsb, width);
5551                 }
5552                 break;
5553
5554               case 'b':
5555                 {
5556                   unsigned int S = (given & 0x04000000u) >> 26;
5557                   unsigned int J1 = (given & 0x00002000u) >> 13;
5558                   unsigned int J2 = (given & 0x00000800u) >> 11;
5559                   bfd_vma offset = 0;
5560
5561                   offset |= !S << 20;
5562                   offset |= J2 << 19;
5563                   offset |= J1 << 18;
5564                   offset |= (given & 0x003f0000) >> 4;
5565                   offset |= (given & 0x000007ff) << 1;
5566                   offset -= (1 << 20);
5567
5568                   info->print_address_func (pc + 4 + offset, info);
5569                 }
5570                 break;
5571
5572               case 'B':
5573                 {
5574                   unsigned int S = (given & 0x04000000u) >> 26;
5575                   unsigned int I1 = (given & 0x00002000u) >> 13;
5576                   unsigned int I2 = (given & 0x00000800u) >> 11;
5577                   bfd_vma offset = 0;
5578
5579                   offset |= !S << 24;
5580                   offset |= !(I1 ^ S) << 23;
5581                   offset |= !(I2 ^ S) << 22;
5582                   offset |= (given & 0x03ff0000u) >> 4;
5583                   offset |= (given & 0x000007ffu) << 1;
5584                   offset -= (1 << 24);
5585                   offset += pc + 4;
5586
5587                   /* BLX target addresses are always word aligned.  */
5588                   if ((given & 0x00001000u) == 0)
5589                       offset &= ~2u;
5590
5591                   info->print_address_func (offset, info);
5592                 }
5593                 break;
5594
5595               case 's':
5596                 {
5597                   unsigned int shift = 0;
5598
5599                   shift |= (given & 0x000000c0u) >> 6;
5600                   shift |= (given & 0x00007000u) >> 10;
5601                   if (WRITEBACK_BIT_SET)
5602                     func (stream, ", asr #%u", shift);
5603                   else if (shift)
5604                     func (stream, ", lsl #%u", shift);
5605                   /* else print nothing - lsl #0 */
5606                 }
5607                 break;
5608
5609               case 'R':
5610                 {
5611                   unsigned int rot = (given & 0x00000030) >> 4;
5612
5613                   if (rot)
5614                     func (stream, ", ror #%u", rot * 8);
5615                 }
5616                 break;
5617
5618               case 'U':
5619                 if ((given & 0xf0) == 0x60)
5620                   {
5621                     switch (given & 0xf)
5622                       {
5623                         case 0xf: func (stream, "sy"); break;
5624                         default:
5625                           func (stream, "#%d", (int) given & 0xf);
5626                               break;
5627                       }
5628                   }
5629                 else
5630                   {
5631                     const char * opt = data_barrier_option (given & 0xf);
5632                     if (opt != NULL)
5633                       func (stream, "%s", opt);
5634                     else
5635                       func (stream, "#%d", (int) given & 0xf);
5636                    }
5637                 break;
5638
5639               case 'C':
5640                 if ((given & 0xff) == 0)
5641                   {
5642                     func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5643                     if (given & 0x800)
5644                       func (stream, "f");
5645                     if (given & 0x400)
5646                       func (stream, "s");
5647                     if (given & 0x200)
5648                       func (stream, "x");
5649                     if (given & 0x100)
5650                       func (stream, "c");
5651                   }
5652                 else if ((given & 0x20) == 0x20)
5653                   {
5654                     char const* name;
5655                     unsigned sysm = (given & 0xf00) >> 8;
5656
5657                     sysm |= (given & 0x30);
5658                     sysm |= (given & 0x00100000) >> 14;
5659                     name = banked_regname (sysm);
5660
5661                     if (name != NULL)
5662                       func (stream, "%s", name);
5663                     else
5664                       func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5665                   }
5666                 else
5667                   {
5668                     func (stream, "%s", psr_name (given & 0xff));
5669                   }
5670                 break;
5671
5672               case 'D':
5673                 if (((given & 0xff) == 0)
5674                     || ((given & 0x20) == 0x20))
5675                   {
5676                     char const* name;
5677                     unsigned sm = (given & 0xf0000) >> 16;
5678
5679                     sm |= (given & 0x30);
5680                     sm |= (given & 0x00100000) >> 14;
5681                     name = banked_regname (sm);
5682
5683                     if (name != NULL)
5684                       func (stream, "%s", name);
5685                     else
5686                       func (stream, "(UNDEF: %lu)", (unsigned long) sm);
5687                   }
5688                 else
5689                   func (stream, "%s", psr_name (given & 0xff));
5690                 break;
5691
5692               case '0': case '1': case '2': case '3': case '4':
5693               case '5': case '6': case '7': case '8': case '9':
5694                 {
5695                   int width;
5696                   unsigned long val;
5697
5698                   c = arm_decode_bitfield (c, given, &val, &width);
5699
5700                   switch (*c)
5701                     {
5702                     case 'd':
5703                       func (stream, "%lu", val);
5704                       value_in_comment = val;
5705                       break;
5706
5707                     case 'D':
5708                       func (stream, "%lu", val + 1);
5709                       value_in_comment = val + 1;
5710                       break;
5711
5712                     case 'W':
5713                       func (stream, "%lu", val * 4);
5714                       value_in_comment = val * 4;
5715                       break;
5716
5717                     case 'S':
5718                       if (val == 13)
5719                         is_unpredictable = TRUE;
5720                       /* Fall through.  */
5721                     case 'R':
5722                       if (val == 15)
5723                         is_unpredictable = TRUE;
5724                       /* Fall through.  */
5725                     case 'r':
5726                       func (stream, "%s", arm_regnames[val]);
5727                       break;
5728
5729                     case 'c':
5730                       func (stream, "%s", arm_conditional[val]);
5731                       break;
5732
5733                     case '\'':
5734                       c++;
5735                       if (val == ((1ul << width) - 1))
5736                         func (stream, "%c", *c);
5737                       break;
5738
5739                     case '`':
5740                       c++;
5741                       if (val == 0)
5742                         func (stream, "%c", *c);
5743                       break;
5744
5745                     case '?':
5746                       func (stream, "%c", c[(1 << width) - (int) val]);
5747                       c += 1 << width;
5748                       break;
5749
5750                     case 'x':
5751                       func (stream, "0x%lx", val & 0xffffffffUL);
5752                       break;
5753
5754                     default:
5755                       abort ();
5756                     }
5757                 }
5758                 break;
5759
5760               case 'L':
5761                 /* PR binutils/12534
5762                    If we have a PC relative offset in an LDRD or STRD
5763                    instructions then display the decoded address.  */
5764                 if (((given >> 16) & 0xf) == 0xf)
5765                   {
5766                     bfd_vma offset = (given & 0xff) * 4;
5767
5768                     if ((given & (1 << 23)) == 0)
5769                       offset = - offset;
5770                     func (stream, "\t; ");
5771                     info->print_address_func ((pc & ~3) + 4 + offset, info);
5772                   }
5773                 break;
5774
5775               default:
5776                 abort ();
5777               }
5778           }
5779
5780         if (value_in_comment > 32 || value_in_comment < -16)
5781           func (stream, "\t; 0x%lx", value_in_comment);
5782
5783         if (is_unpredictable)
5784           func (stream, UNPREDICTABLE_INSTRUCTION);
5785
5786         return;
5787       }
5788
5789   /* No match.  */
5790   abort ();
5791 }
5792
5793 /* Print data bytes on INFO->STREAM.  */
5794
5795 static void
5796 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
5797                  struct disassemble_info *info,
5798                  long given)
5799 {
5800   switch (info->bytes_per_chunk)
5801     {
5802     case 1:
5803       info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
5804       break;
5805     case 2:
5806       info->fprintf_func (info->stream, ".short\t0x%04lx", given);
5807       break;
5808     case 4:
5809       info->fprintf_func (info->stream, ".word\t0x%08lx", given);
5810       break;
5811     default:
5812       abort ();
5813     }
5814 }
5815
5816 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
5817    being displayed in symbol relative addresses.
5818
5819    Also disallow private symbol, with __tagsym$$ prefix,
5820    from ARM RVCT toolchain being displayed.  */
5821
5822 bfd_boolean
5823 arm_symbol_is_valid (asymbol * sym,
5824                      struct disassemble_info * info ATTRIBUTE_UNUSED)
5825 {
5826   const char * name;
5827
5828   if (sym == NULL)
5829     return FALSE;
5830
5831   name = bfd_asymbol_name (sym);
5832
5833   return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
5834 }
5835
5836 /* Parse an individual disassembler option.  */
5837
5838 void
5839 parse_arm_disassembler_option (char *option)
5840 {
5841   if (option == NULL)
5842     return;
5843
5844   if (CONST_STRNEQ (option, "reg-names-"))
5845     {
5846       int i;
5847
5848       option += 10;
5849
5850       for (i = NUM_ARM_REGNAMES; i--;)
5851         if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
5852           {
5853             regname_selected = i;
5854             break;
5855           }
5856
5857       if (i < 0)
5858         /* XXX - should break 'option' at following delimiter.  */
5859         fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
5860     }
5861   else if (CONST_STRNEQ (option, "force-thumb"))
5862     force_thumb = 1;
5863   else if (CONST_STRNEQ (option, "no-force-thumb"))
5864     force_thumb = 0;
5865   else
5866     /* XXX - should break 'option' at following delimiter.  */
5867     fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
5868
5869   return;
5870 }
5871
5872 /* Parse the string of disassembler options, spliting it at whitespaces
5873    or commas.  (Whitespace separators supported for backwards compatibility).  */
5874
5875 static void
5876 parse_disassembler_options (char *options)
5877 {
5878   if (options == NULL)
5879     return;
5880
5881   while (*options)
5882     {
5883       parse_arm_disassembler_option (options);
5884
5885       /* Skip forward to next seperator.  */
5886       while ((*options) && (! ISSPACE (*options)) && (*options != ','))
5887         ++ options;
5888       /* Skip forward past seperators.  */
5889       while (ISSPACE (*options) || (*options == ','))
5890         ++ options;
5891     }
5892 }
5893
5894 /* Search back through the insn stream to determine if this instruction is
5895    conditionally executed.  */
5896
5897 static void
5898 find_ifthen_state (bfd_vma pc,
5899                    struct disassemble_info *info,
5900                    bfd_boolean little)
5901 {
5902   unsigned char b[2];
5903   unsigned int insn;
5904   int status;
5905   /* COUNT is twice the number of instructions seen.  It will be odd if we
5906      just crossed an instruction boundary.  */
5907   int count;
5908   int it_count;
5909   unsigned int seen_it;
5910   bfd_vma addr;
5911
5912   ifthen_address = pc;
5913   ifthen_state = 0;
5914
5915   addr = pc;
5916   count = 1;
5917   it_count = 0;
5918   seen_it = 0;
5919   /* Scan backwards looking for IT instructions, keeping track of where
5920      instruction boundaries are.  We don't know if something is actually an
5921      IT instruction until we find a definite instruction boundary.  */
5922   for (;;)
5923     {
5924       if (addr == 0 || info->symbol_at_address_func (addr, info))
5925         {
5926           /* A symbol must be on an instruction boundary, and will not
5927              be within an IT block.  */
5928           if (seen_it && (count & 1))
5929             break;
5930
5931           return;
5932         }
5933       addr -= 2;
5934       status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
5935       if (status)
5936         return;
5937
5938       if (little)
5939         insn = (b[0]) | (b[1] << 8);
5940       else
5941         insn = (b[1]) | (b[0] << 8);
5942       if (seen_it)
5943         {
5944           if ((insn & 0xf800) < 0xe800)
5945             {
5946               /* Addr + 2 is an instruction boundary.  See if this matches
5947                  the expected boundary based on the position of the last
5948                  IT candidate.  */
5949               if (count & 1)
5950                 break;
5951               seen_it = 0;
5952             }
5953         }
5954       if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
5955         {
5956           /* This could be an IT instruction.  */
5957           seen_it = insn;
5958           it_count = count >> 1;
5959         }
5960       if ((insn & 0xf800) >= 0xe800)
5961         count++;
5962       else
5963         count = (count + 2) | 1;
5964       /* IT blocks contain at most 4 instructions.  */
5965       if (count >= 8 && !seen_it)
5966         return;
5967     }
5968   /* We found an IT instruction.  */
5969   ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
5970   if ((ifthen_state & 0xf) == 0)
5971     ifthen_state = 0;
5972 }
5973
5974 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
5975    mapping symbol.  */
5976
5977 static int
5978 is_mapping_symbol (struct disassemble_info *info, int n,
5979                    enum map_type *map_type)
5980 {
5981   const char *name;
5982
5983   name = bfd_asymbol_name (info->symtab[n]);
5984   if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
5985       && (name[2] == 0 || name[2] == '.'))
5986     {
5987       *map_type = ((name[1] == 'a') ? MAP_ARM
5988                    : (name[1] == 't') ? MAP_THUMB
5989                    : MAP_DATA);
5990       return TRUE;
5991     }
5992
5993   return FALSE;
5994 }
5995
5996 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
5997    Returns nonzero if *MAP_TYPE was set.  */
5998
5999 static int
6000 get_map_sym_type (struct disassemble_info *info,
6001                   int n,
6002                   enum map_type *map_type)
6003 {
6004   /* If the symbol is in a different section, ignore it.  */
6005   if (info->section != NULL && info->section != info->symtab[n]->section)
6006     return FALSE;
6007
6008   return is_mapping_symbol (info, n, map_type);
6009 }
6010
6011 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
6012    Returns nonzero if *MAP_TYPE was set.  */
6013
6014 static int
6015 get_sym_code_type (struct disassemble_info *info,
6016                    int n,
6017                    enum map_type *map_type)
6018 {
6019   elf_symbol_type *es;
6020   unsigned int type;
6021
6022   /* If the symbol is in a different section, ignore it.  */
6023   if (info->section != NULL && info->section != info->symtab[n]->section)
6024     return FALSE;
6025
6026   es = *(elf_symbol_type **)(info->symtab + n);
6027   type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6028
6029   /* If the symbol has function type then use that.  */
6030   if (type == STT_FUNC || type == STT_GNU_IFUNC)
6031     {
6032       if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB)
6033         *map_type = MAP_THUMB;
6034       else
6035         *map_type = MAP_ARM;
6036       return TRUE;
6037     }
6038
6039   return FALSE;
6040 }
6041
6042 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
6043    of the supplied arm_feature_set structure with bitmasks indicating
6044    the support base architectures and coprocessor extensions.
6045
6046    FIXME: This could more efficiently implemented as a constant array,
6047    although it would also be less robust.  */
6048
6049 static void
6050 select_arm_features (unsigned long mach,
6051                      arm_feature_set * features)
6052 {
6053 #undef ARM_SET_FEATURES
6054 #define ARM_SET_FEATURES(FSET) \
6055   {                                                     \
6056     const arm_feature_set fset = FSET;                  \
6057     arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \
6058     ARM_MERGE_FEATURE_SETS (*features, tmp, fset);      \
6059   }
6060
6061   switch (mach)
6062     {
6063     case bfd_mach_arm_2:       ARM_SET_FEATURES (ARM_ARCH_V2); break;
6064     case bfd_mach_arm_2a:      ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6065     case bfd_mach_arm_3:       ARM_SET_FEATURES (ARM_ARCH_V3); break;
6066     case bfd_mach_arm_3M:      ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6067     case bfd_mach_arm_4:       ARM_SET_FEATURES (ARM_ARCH_V4); break;
6068     case bfd_mach_arm_4T:      ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6069     case bfd_mach_arm_5:       ARM_SET_FEATURES (ARM_ARCH_V5); break;
6070     case bfd_mach_arm_5T:      ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6071     case bfd_mach_arm_5TE:     ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6072     case bfd_mach_arm_XScale:  ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
6073     case bfd_mach_arm_ep9312:
6074       ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6075                                          ARM_CEXT_MAVERICK | FPU_MAVERICK));
6076        break;
6077     case bfd_mach_arm_iWMMXt:  ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6078     case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
6079       /* If the machine type is unknown allow all
6080          architecture types and all extensions.  */
6081     case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
6082     default:
6083       abort ();
6084     }
6085
6086 #undef ARM_SET_FEATURES
6087 }
6088
6089
6090 /* NOTE: There are no checks in these routines that
6091    the relevant number of data bytes exist.  */
6092
6093 static int
6094 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
6095 {
6096   unsigned char b[4];
6097   long          given;
6098   int           status;
6099   int           is_thumb = FALSE;
6100   int           is_data = FALSE;
6101   int           little_code;
6102   unsigned int  size = 4;
6103   void          (*printer) (bfd_vma, struct disassemble_info *, long);
6104   bfd_boolean   found = FALSE;
6105   struct arm_private_data *private_data;
6106
6107   if (info->disassembler_options)
6108     {
6109       parse_disassembler_options (info->disassembler_options);
6110
6111       /* To avoid repeated parsing of these options, we remove them here.  */
6112       info->disassembler_options = NULL;
6113     }
6114
6115   /* PR 10288: Control which instructions will be disassembled.  */
6116   if (info->private_data == NULL)
6117     {
6118       static struct arm_private_data private;
6119
6120       if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6121         /* If the user did not use the -m command line switch then default to
6122            disassembling all types of ARM instruction.
6123
6124            The info->mach value has to be ignored as this will be based on
6125            the default archictecture for the target and/or hints in the notes
6126            section, but it will never be greater than the current largest arm
6127            machine value (iWMMXt2), which is only equivalent to the V5TE
6128            architecture.  ARM architectures have advanced beyond the machine
6129            value encoding, and these newer architectures would be ignored if
6130            the machine value was used.
6131
6132            Ie the -m switch is used to restrict which instructions will be
6133            disassembled.  If it is necessary to use the -m switch to tell
6134            objdump that an ARM binary is being disassembled, eg because the
6135            input is a raw binary file, but it is also desired to disassemble
6136            all ARM instructions then use "-marm".  This will select the
6137            "unknown" arm architecture which is compatible with any ARM
6138            instruction.  */
6139           info->mach = bfd_mach_arm_unknown;
6140
6141       /* Compute the architecture bitmask from the machine number.
6142          Note: This assumes that the machine number will not change
6143          during disassembly....  */
6144       select_arm_features (info->mach, & private.features);
6145
6146       private.has_mapping_symbols = -1;
6147       private.last_mapping_sym = -1;
6148       private.last_mapping_addr = 0;
6149
6150       info->private_data = & private;
6151     }
6152
6153   private_data = info->private_data;
6154
6155   /* Decide if our code is going to be little-endian, despite what the
6156      function argument might say.  */
6157   little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6158
6159   /* For ELF, consult the symbol table to determine what kind of code
6160      or data we have.  */
6161   if (info->symtab_size != 0
6162       && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6163     {
6164       bfd_vma addr;
6165       int n, start;
6166       int last_sym = -1;
6167       enum map_type type = MAP_ARM;
6168
6169       /* Start scanning at the start of the function, or wherever
6170          we finished last time.  */
6171       /* PR 14006.  When the address is 0 we are either at the start of the
6172          very first function, or else the first function in a new, unlinked
6173          executable section (eg because uf -ffunction-sections).  Either way
6174          start scanning from the beginning of the symbol table, not where we
6175          left off last time.  */
6176       if (pc == 0)
6177         start = 0;
6178       else
6179         {
6180           start = info->symtab_pos + 1;
6181           if (start < private_data->last_mapping_sym)
6182             start = private_data->last_mapping_sym;
6183         }
6184       found = FALSE;
6185
6186       /* First, look for mapping symbols.  */
6187       if (private_data->has_mapping_symbols != 0)
6188         {
6189           /* Scan up to the location being disassembled.  */
6190           for (n = start; n < info->symtab_size; n++)
6191             {
6192               addr = bfd_asymbol_value (info->symtab[n]);
6193               if (addr > pc)
6194                 break;
6195               if (get_map_sym_type (info, n, &type))
6196                 {
6197                   last_sym = n;
6198                   found = TRUE;
6199                 }
6200             }
6201
6202           if (!found)
6203             {
6204               /* No mapping symbol found at this address.  Look backwards
6205                  for a preceding one.  */
6206               for (n = start - 1; n >= 0; n--)
6207                 {
6208                   if (get_map_sym_type (info, n, &type))
6209                     {
6210                       last_sym = n;
6211                       found = TRUE;
6212                       break;
6213                     }
6214                 }
6215             }
6216
6217           if (found)
6218             private_data->has_mapping_symbols = 1;
6219
6220           /* No mapping symbols were found.  A leading $d may be
6221              omitted for sections which start with data; but for
6222              compatibility with legacy and stripped binaries, only
6223              assume the leading $d if there is at least one mapping
6224              symbol in the file.  */
6225           if (!found && private_data->has_mapping_symbols == -1)
6226             {
6227               /* Look for mapping symbols, in any section.  */
6228               for (n = 0; n < info->symtab_size; n++)
6229                 if (is_mapping_symbol (info, n, &type))
6230                   {
6231                     private_data->has_mapping_symbols = 1;
6232                     break;
6233                   }
6234               if (private_data->has_mapping_symbols == -1)
6235                 private_data->has_mapping_symbols = 0;
6236             }
6237
6238           if (!found && private_data->has_mapping_symbols == 1)
6239             {
6240               type = MAP_DATA;
6241               found = TRUE;
6242             }
6243         }
6244
6245       /* Next search for function symbols to separate ARM from Thumb
6246          in binaries without mapping symbols.  */
6247       if (!found)
6248         {
6249           /* Scan up to the location being disassembled.  */
6250           for (n = start; n < info->symtab_size; n++)
6251             {
6252               addr = bfd_asymbol_value (info->symtab[n]);
6253               if (addr > pc)
6254                 break;
6255               if (get_sym_code_type (info, n, &type))
6256                 {
6257                   last_sym = n;
6258                   found = TRUE;
6259                 }
6260             }
6261
6262           if (!found)
6263             {
6264               /* No mapping symbol found at this address.  Look backwards
6265                  for a preceding one.  */
6266               for (n = start - 1; n >= 0; n--)
6267                 {
6268                   if (get_sym_code_type (info, n, &type))
6269                     {
6270                       last_sym = n;
6271                       found = TRUE;
6272                       break;
6273                     }
6274                 }
6275             }
6276         }
6277
6278       private_data->last_mapping_sym = last_sym;
6279       private_data->last_type = type;
6280       is_thumb = (private_data->last_type == MAP_THUMB);
6281       is_data = (private_data->last_type == MAP_DATA);
6282
6283       /* Look a little bit ahead to see if we should print out
6284          two or four bytes of data.  If there's a symbol,
6285          mapping or otherwise, after two bytes then don't
6286          print more.  */
6287       if (is_data)
6288         {
6289           size = 4 - (pc & 3);
6290           for (n = last_sym + 1; n < info->symtab_size; n++)
6291             {
6292               addr = bfd_asymbol_value (info->symtab[n]);
6293               if (addr > pc
6294                   && (info->section == NULL
6295                       || info->section == info->symtab[n]->section))
6296                 {
6297                   if (addr - pc < size)
6298                     size = addr - pc;
6299                   break;
6300                 }
6301             }
6302           /* If the next symbol is after three bytes, we need to
6303              print only part of the data, so that we can use either
6304              .byte or .short.  */
6305           if (size == 3)
6306             size = (pc & 1) ? 1 : 2;
6307         }
6308     }
6309
6310   if (info->symbols != NULL)
6311     {
6312       if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6313         {
6314           coff_symbol_type * cs;
6315
6316           cs = coffsymbol (*info->symbols);
6317           is_thumb = (   cs->native->u.syment.n_sclass == C_THUMBEXT
6318                       || cs->native->u.syment.n_sclass == C_THUMBSTAT
6319                       || cs->native->u.syment.n_sclass == C_THUMBLABEL
6320                       || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6321                       || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6322         }
6323       else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6324                && !found)
6325         {
6326           /* If no mapping symbol has been found then fall back to the type
6327              of the function symbol.  */
6328           elf_symbol_type *  es;
6329           unsigned int       type;
6330
6331           es = *(elf_symbol_type **)(info->symbols);
6332           type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6333
6334           is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym)
6335                        == ST_BRANCH_TO_THUMB)
6336                       || type == STT_ARM_16BIT);
6337         }
6338     }
6339
6340   if (force_thumb)
6341     is_thumb = TRUE;
6342
6343   if (is_data)
6344     info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6345   else
6346     info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6347
6348   info->bytes_per_line = 4;
6349
6350   /* PR 10263: Disassemble data if requested to do so by the user.  */
6351   if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
6352     {
6353       int i;
6354
6355       /* Size was already set above.  */
6356       info->bytes_per_chunk = size;
6357       printer = print_insn_data;
6358
6359       status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
6360       given = 0;
6361       if (little)
6362         for (i = size - 1; i >= 0; i--)
6363           given = b[i] | (given << 8);
6364       else
6365         for (i = 0; i < (int) size; i++)
6366           given = b[i] | (given << 8);
6367     }
6368   else if (!is_thumb)
6369     {
6370       /* In ARM mode endianness is a straightforward issue: the instruction
6371          is four bytes long and is either ordered 0123 or 3210.  */
6372       printer = print_insn_arm;
6373       info->bytes_per_chunk = 4;
6374       size = 4;
6375
6376       status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
6377       if (little_code)
6378         given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6379       else
6380         given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
6381     }
6382   else
6383     {
6384       /* In Thumb mode we have the additional wrinkle of two
6385          instruction lengths.  Fortunately, the bits that determine
6386          the length of the current instruction are always to be found
6387          in the first two bytes.  */
6388       printer = print_insn_thumb16;
6389       info->bytes_per_chunk = 2;
6390       size = 2;
6391
6392       status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
6393       if (little_code)
6394         given = (b[0]) | (b[1] << 8);
6395       else
6396         given = (b[1]) | (b[0] << 8);
6397
6398       if (!status)
6399         {
6400           /* These bit patterns signal a four-byte Thumb
6401              instruction.  */
6402           if ((given & 0xF800) == 0xF800
6403               || (given & 0xF800) == 0xF000
6404               || (given & 0xF800) == 0xE800)
6405             {
6406               status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
6407               if (little_code)
6408                 given = (b[0]) | (b[1] << 8) | (given << 16);
6409               else
6410                 given = (b[1]) | (b[0] << 8) | (given << 16);
6411
6412               printer = print_insn_thumb32;
6413               size = 4;
6414             }
6415         }
6416
6417       if (ifthen_address != pc)
6418         find_ifthen_state (pc, info, little_code);
6419
6420       if (ifthen_state)
6421         {
6422           if ((ifthen_state & 0xf) == 0x8)
6423             ifthen_next_state = 0;
6424           else
6425             ifthen_next_state = (ifthen_state & 0xe0)
6426                                 | ((ifthen_state & 0xf) << 1);
6427         }
6428     }
6429
6430   if (status)
6431     {
6432       info->memory_error_func (status, pc, info);
6433       return -1;
6434     }
6435   if (info->flags & INSN_HAS_RELOC)
6436     /* If the instruction has a reloc associated with it, then
6437        the offset field in the instruction will actually be the
6438        addend for the reloc.  (We are using REL type relocs).
6439        In such cases, we can ignore the pc when computing
6440        addresses, since the addend is not currently pc-relative.  */
6441     pc = 0;
6442
6443   printer (pc, info, given);
6444
6445   if (is_thumb)
6446     {
6447       ifthen_state = ifthen_next_state;
6448       ifthen_address += size;
6449     }
6450   return size;
6451 }
6452
6453 int
6454 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
6455 {
6456   /* Detect BE8-ness and record it in the disassembler info.  */
6457   if (info->flavour == bfd_target_elf_flavour
6458       && info->section != NULL
6459       && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6460     info->endian_code = BFD_ENDIAN_LITTLE;
6461
6462   return print_insn (pc, info, FALSE);
6463 }
6464
6465 int
6466 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
6467 {
6468   return print_insn (pc, info, TRUE);
6469 }
6470
6471 void
6472 print_arm_disassembler_options (FILE *stream)
6473 {
6474   int i;
6475
6476   fprintf (stream, _("\n\
6477 The following ARM specific disassembler options are supported for use with\n\
6478 the -M switch:\n"));
6479
6480   for (i = NUM_ARM_REGNAMES; i--;)
6481     fprintf (stream, "  reg-names-%s %*c%s\n",
6482              regnames[i].name,
6483              (int)(14 - strlen (regnames[i].name)), ' ',
6484              regnames[i].description);
6485
6486   fprintf (stream, "  force-thumb              Assume all insns are Thumb insns\n");
6487   fprintf (stream, "  no-force-thumb           Examine preceding label to determine an insn's type\n\n");
6488 }