1 /* Instruction printing code for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2012
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modification by James G. Smith (jsmith@cygnus.co.uk)
8 This file is part of libopcodes.
10 This library is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 It is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
23 MA 02110-1301, USA. */
28 #include "opcode/arm.h"
30 #include "safe-ctype.h"
31 #include "floatformat.h"
33 /* FIXME: This shouldn't be done here. */
34 #include "coff/internal.h"
37 #include "elf/internal.h"
40 /* FIXME: Belongs in global header. */
42 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
46 #define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
49 /* Cached mapping symbol state. */
57 struct arm_private_data
59 /* The features to use when disassembling optional instructions. */
60 arm_feature_set features;
62 /* Whether any mapping symbols are present in the provided symbol
63 table. -1 if we do not know yet, otherwise 0 or 1. */
64 int has_mapping_symbols;
66 /* Track the last type (although this doesn't seem to be useful) */
67 enum map_type last_type;
69 /* Tracking symbol table information */
71 bfd_vma last_mapping_addr;
76 unsigned long arch; /* Architecture defining this insn. */
77 unsigned long value; /* If arch == 0 then value is a sentinel. */
78 unsigned long mask; /* Recognise insn if (op & mask) == value. */
79 const char * assembler; /* How to disassemble this insn. */
84 unsigned long arch; /* Architecture defining this insn. */
85 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
86 const char *assembler; /* How to disassemble this insn. */
89 /* print_insn_coprocessor recognizes the following format control codes:
93 %c print condition code (always bits 28-31 in ARM mode)
94 %q print shifter argument
95 %u print condition code (unconditional in ARM mode,
96 UNPREDICTABLE if not AL in Thumb)
97 %A print address for ldc/stc/ldf/stf instruction
98 %B print vstm/vldm register list
99 %I print cirrus signed shift immediate: bits 0..3|4..6
100 %F print the COUNT field of a LFM/SFM instruction.
101 %P print floating point precision in arithmetic insn
102 %Q print floating point precision in ldf/stf insn
103 %R print floating point rounding mode
105 %<bitfield>c print as a condition code (for vsel)
106 %<bitfield>r print as an ARM register
107 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
108 %<bitfield>ru as %<>r but each u register must be unique.
109 %<bitfield>d print the bitfield in decimal
110 %<bitfield>k print immediate for VFPv3 conversion instruction
111 %<bitfield>x print the bitfield in hex
112 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
113 %<bitfield>f print a floating point constant if >7 else a
114 floating point register
115 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
116 %<bitfield>g print as an iWMMXt 64-bit register
117 %<bitfield>G print as an iWMMXt general purpose or control register
118 %<bitfield>D print as a NEON D register
119 %<bitfield>Q print as a NEON Q register
121 %y<code> print a single precision VFP reg.
122 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
123 %z<code> print a double precision VFP reg
124 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
126 %<bitfield>'c print specified char iff bitfield is all ones
127 %<bitfield>`c print specified char iff bitfield is all zeroes
128 %<bitfield>?ab... select from array of values in big endian order
130 %L print as an iWMMXt N/M width field.
131 %Z print the Immediate of a WSHUFH instruction.
132 %l like 'A' except use byte offsets for 'B' & 'H'
134 %i print 5-bit immediate in bits 8,3..0
136 %r print register offset address for wldt/wstr instruction. */
138 enum opcode_sentinel_enum
140 SENTINEL_IWMMXT_START = 1,
142 SENTINEL_GENERIC_START
145 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
146 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
148 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
150 static const struct opcode32 coprocessor_opcodes[] =
152 /* XScale instructions. */
153 {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"},
154 {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"},
155 {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
156 {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
157 {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
159 /* Intel Wireless MMX technology instructions. */
160 { 0, SENTINEL_IWMMXT_START, 0, "" },
161 {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
162 {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
163 {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
164 {ARM_CEXT_XSCALE, 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
165 {ARM_CEXT_XSCALE, 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
166 {ARM_CEXT_XSCALE, 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
167 {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
168 {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
169 {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
170 {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
171 {ARM_CEXT_XSCALE, 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
172 {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
173 {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
174 {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
175 {ARM_CEXT_XSCALE, 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
176 {ARM_CEXT_XSCALE, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
177 {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
178 {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
179 {ARM_CEXT_XSCALE, 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
180 {ARM_CEXT_XSCALE, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
181 {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
182 {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
183 {ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
184 {ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
185 {ARM_CEXT_XSCALE, 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
186 {ARM_CEXT_XSCALE, 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
187 {ARM_CEXT_XSCALE, 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
188 {ARM_CEXT_XSCALE, 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
189 {ARM_CEXT_XSCALE, 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
190 {ARM_CEXT_XSCALE, 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
191 {ARM_CEXT_XSCALE, 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
192 {ARM_CEXT_XSCALE, 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
193 {ARM_CEXT_XSCALE, 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
194 {ARM_CEXT_XSCALE, 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
195 {ARM_CEXT_XSCALE, 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
196 {ARM_CEXT_XSCALE, 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
197 {ARM_CEXT_XSCALE, 0x0e800120, 0x0f800ff0, "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
198 {ARM_CEXT_XSCALE, 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
199 {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
200 {ARM_CEXT_XSCALE, 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
201 {ARM_CEXT_XSCALE, 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
202 {ARM_CEXT_XSCALE, 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
203 {ARM_CEXT_XSCALE, 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
204 {ARM_CEXT_XSCALE, 0x0e8000a0, 0x0f800ff0, "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
205 {ARM_CEXT_XSCALE, 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
206 {ARM_CEXT_XSCALE, 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
207 {ARM_CEXT_XSCALE, 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
208 {ARM_CEXT_XSCALE, 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
209 {ARM_CEXT_XSCALE, 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
210 {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
211 {ARM_CEXT_XSCALE, 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
212 {ARM_CEXT_XSCALE, 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
213 {ARM_CEXT_XSCALE, 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
214 {ARM_CEXT_XSCALE, 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
215 {ARM_CEXT_XSCALE, 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
216 {ARM_CEXT_XSCALE, 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
217 {ARM_CEXT_XSCALE, 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
218 {ARM_CEXT_XSCALE, 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
219 {ARM_CEXT_XSCALE, 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
220 {ARM_CEXT_XSCALE, 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
221 {ARM_CEXT_XSCALE, 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
222 {ARM_CEXT_XSCALE, 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
223 {ARM_CEXT_XSCALE, 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
224 {ARM_CEXT_XSCALE, 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
225 {ARM_CEXT_XSCALE, 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
226 {ARM_CEXT_XSCALE, 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
227 {ARM_CEXT_XSCALE, 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
228 {ARM_CEXT_XSCALE, 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
229 {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
230 {ARM_CEXT_XSCALE, 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
231 {ARM_CEXT_XSCALE, 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
232 {ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
233 {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
234 {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
235 {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
236 { 0, SENTINEL_IWMMXT_END, 0, "" },
238 /* Floating point coprocessor (FPA) instructions. */
239 {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
240 {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
241 {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
242 {FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
243 {FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
244 {FPU_FPA_EXT_V1, 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
245 {FPU_FPA_EXT_V1, 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
246 {FPU_FPA_EXT_V1, 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
247 {FPU_FPA_EXT_V1, 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
248 {FPU_FPA_EXT_V1, 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
249 {FPU_FPA_EXT_V1, 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
250 {FPU_FPA_EXT_V1, 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
251 {FPU_FPA_EXT_V1, 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
252 {FPU_FPA_EXT_V1, 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
253 {FPU_FPA_EXT_V1, 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
254 {FPU_FPA_EXT_V1, 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
255 {FPU_FPA_EXT_V1, 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
256 {FPU_FPA_EXT_V1, 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
257 {FPU_FPA_EXT_V1, 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
258 {FPU_FPA_EXT_V1, 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
259 {FPU_FPA_EXT_V1, 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
260 {FPU_FPA_EXT_V1, 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
261 {FPU_FPA_EXT_V1, 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
262 {FPU_FPA_EXT_V1, 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
263 {FPU_FPA_EXT_V1, 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
264 {FPU_FPA_EXT_V1, 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
265 {FPU_FPA_EXT_V1, 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
266 {FPU_FPA_EXT_V1, 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
267 {FPU_FPA_EXT_V1, 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
268 {FPU_FPA_EXT_V1, 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
269 {FPU_FPA_EXT_V1, 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
270 {FPU_FPA_EXT_V1, 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
271 {FPU_FPA_EXT_V1, 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
272 {FPU_FPA_EXT_V1, 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
273 {FPU_FPA_EXT_V1, 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
274 {FPU_FPA_EXT_V1, 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
275 {FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
276 {FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
277 {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
278 {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
279 {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
280 {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
281 {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
283 /* Register load/store. */
284 {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
285 {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
286 {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
287 {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
288 {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
289 {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
290 {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
291 {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
292 {FPU_VFP_EXT_V1xD, 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
293 {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
294 {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
295 {FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
296 {FPU_VFP_EXT_V1xD, 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
297 {FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
298 {FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
299 {FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
301 {FPU_VFP_EXT_V1xD, 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
302 {FPU_VFP_EXT_V1xD, 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
303 {FPU_VFP_EXT_V1xD, 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
304 {FPU_VFP_EXT_V1xD, 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
306 /* Data transfer between ARM and NEON registers. */
307 {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
308 {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
309 {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
310 {FPU_NEON_EXT_V1, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
311 {FPU_NEON_EXT_V1, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
312 {FPU_NEON_EXT_V1, 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
313 {FPU_NEON_EXT_V1, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
314 {FPU_NEON_EXT_V1, 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
315 {FPU_NEON_EXT_V1, 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
316 {FPU_NEON_EXT_V1, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
317 {FPU_NEON_EXT_V1, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
318 {FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
319 {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
320 {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
321 /* Half-precision conversion instructions. */
322 {FPU_VFP_EXT_ARMV8, 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
323 {FPU_VFP_EXT_ARMV8, 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
324 {FPU_VFP_EXT_FP16, 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
325 {FPU_VFP_EXT_FP16, 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
327 /* Floating point coprocessor (VFP) instructions. */
328 {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
329 {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
330 {FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
331 {FPU_VFP_EXT_V1xD, 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
332 {FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
333 {FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
334 {FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
335 {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
336 {FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
337 {FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
338 {FPU_VFP_EXT_V1xD, 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
339 {FPU_VFP_EXT_V1xD, 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
340 {FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
341 {FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
342 {FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
343 {FPU_VFP_EXT_V1, 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
344 {FPU_VFP_EXT_V1, 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
345 {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
346 {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
347 {FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
348 {FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
349 {FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
350 {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
351 {FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
352 {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
353 {FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
354 {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
355 {FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
356 {FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
357 {FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
358 {FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
359 {FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
360 {FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
361 {FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
362 {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
363 {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
364 {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
365 {FPU_VFP_EXT_V3xD, 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
366 {FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
367 {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
368 {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
369 {FPU_VFP_EXT_V3xD, 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
370 {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
371 {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
372 {FPU_VFP_EXT_V3xD, 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19d"},
373 {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19d"},
374 {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
375 {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
376 {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
377 {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
378 {FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
379 {FPU_VFP_EXT_V1, 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
380 {FPU_VFP_EXT_V1, 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
381 {FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
382 {FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
383 {FPU_VFP_EXT_V1, 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
384 {FPU_VFP_EXT_V1, 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
385 {FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
386 {FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
387 {FPU_VFP_EXT_V1, 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
388 {FPU_VFP_EXT_V1, 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
389 {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
390 {FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
391 {FPU_VFP_EXT_V1, 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
392 {FPU_VFP_EXT_V1, 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
393 {FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
394 {FPU_VFP_EXT_V1, 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
396 /* Cirrus coprocessor instructions. */
397 {ARM_CEXT_MAVERICK, 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
398 {ARM_CEXT_MAVERICK, 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
399 {ARM_CEXT_MAVERICK, 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
400 {ARM_CEXT_MAVERICK, 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
401 {ARM_CEXT_MAVERICK, 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
402 {ARM_CEXT_MAVERICK, 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
403 {ARM_CEXT_MAVERICK, 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
404 {ARM_CEXT_MAVERICK, 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
405 {ARM_CEXT_MAVERICK, 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
406 {ARM_CEXT_MAVERICK, 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
407 {ARM_CEXT_MAVERICK, 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
408 {ARM_CEXT_MAVERICK, 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
409 {ARM_CEXT_MAVERICK, 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
410 {ARM_CEXT_MAVERICK, 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
411 {ARM_CEXT_MAVERICK, 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
412 {ARM_CEXT_MAVERICK, 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
413 {ARM_CEXT_MAVERICK, 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
414 {ARM_CEXT_MAVERICK, 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
415 {ARM_CEXT_MAVERICK, 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
416 {ARM_CEXT_MAVERICK, 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
417 {ARM_CEXT_MAVERICK, 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
418 {ARM_CEXT_MAVERICK, 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
419 {ARM_CEXT_MAVERICK, 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
420 {ARM_CEXT_MAVERICK, 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
421 {ARM_CEXT_MAVERICK, 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
422 {ARM_CEXT_MAVERICK, 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
423 {ARM_CEXT_MAVERICK, 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
424 {ARM_CEXT_MAVERICK, 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
425 {ARM_CEXT_MAVERICK, 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
426 {ARM_CEXT_MAVERICK, 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
427 {ARM_CEXT_MAVERICK, 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
428 {ARM_CEXT_MAVERICK, 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
429 {ARM_CEXT_MAVERICK, 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
430 {ARM_CEXT_MAVERICK, 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
431 {ARM_CEXT_MAVERICK, 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
432 {ARM_CEXT_MAVERICK, 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
433 {ARM_CEXT_MAVERICK, 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
434 {ARM_CEXT_MAVERICK, 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
435 {ARM_CEXT_MAVERICK, 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
436 {ARM_CEXT_MAVERICK, 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
437 {ARM_CEXT_MAVERICK, 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
438 {ARM_CEXT_MAVERICK, 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
439 {ARM_CEXT_MAVERICK, 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
440 {ARM_CEXT_MAVERICK, 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
441 {ARM_CEXT_MAVERICK, 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
442 {ARM_CEXT_MAVERICK, 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
443 {ARM_CEXT_MAVERICK, 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
444 {ARM_CEXT_MAVERICK, 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
445 {ARM_CEXT_MAVERICK, 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
446 {ARM_CEXT_MAVERICK, 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
447 {ARM_CEXT_MAVERICK, 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
448 {ARM_CEXT_MAVERICK, 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
449 {ARM_CEXT_MAVERICK, 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
450 {ARM_CEXT_MAVERICK, 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
451 {ARM_CEXT_MAVERICK, 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
452 {ARM_CEXT_MAVERICK, 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
453 {ARM_CEXT_MAVERICK, 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
454 {ARM_CEXT_MAVERICK, 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
455 {ARM_CEXT_MAVERICK, 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
456 {ARM_CEXT_MAVERICK, 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
457 {ARM_CEXT_MAVERICK, 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
458 {ARM_CEXT_MAVERICK, 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
459 {ARM_CEXT_MAVERICK, 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
460 {ARM_CEXT_MAVERICK, 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
461 {ARM_CEXT_MAVERICK, 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
462 {ARM_CEXT_MAVERICK, 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
463 {ARM_CEXT_MAVERICK, 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
464 {ARM_CEXT_MAVERICK, 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
465 {ARM_CEXT_MAVERICK, 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
466 {ARM_CEXT_MAVERICK, 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
467 {ARM_CEXT_MAVERICK, 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
468 {ARM_CEXT_MAVERICK, 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
469 {ARM_CEXT_MAVERICK, 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
470 {ARM_CEXT_MAVERICK, 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
471 {ARM_CEXT_MAVERICK, 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
472 {ARM_CEXT_MAVERICK, 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
473 {ARM_CEXT_MAVERICK, 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
474 {ARM_CEXT_MAVERICK, 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
475 {ARM_CEXT_MAVERICK, 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
476 {ARM_CEXT_MAVERICK, 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
477 {ARM_CEXT_MAVERICK, 0x0e000600, 0x0ff00f10, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
478 {ARM_CEXT_MAVERICK, 0x0e100600, 0x0ff00f10, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
479 {ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
480 {ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
482 /* VFP Fused multiply add instructions. */
483 {FPU_VFP_EXT_FMA, 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
484 {FPU_VFP_EXT_FMA, 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
485 {FPU_VFP_EXT_FMA, 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
486 {FPU_VFP_EXT_FMA, 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
487 {FPU_VFP_EXT_FMA, 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
488 {FPU_VFP_EXT_FMA, 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
489 {FPU_VFP_EXT_FMA, 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
490 {FPU_VFP_EXT_FMA, 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
493 {FPU_VFP_EXT_ARMV8, 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
494 {FPU_VFP_EXT_ARMV8, 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
495 {FPU_VFP_EXT_ARMV8, 0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"},
496 {FPU_VFP_EXT_ARMV8, 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"},
497 {FPU_VFP_EXT_ARMV8, 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"},
498 {FPU_VFP_EXT_ARMV8, 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},
499 {FPU_VFP_EXT_ARMV8, 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
500 {FPU_VFP_EXT_ARMV8, 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
501 {FPU_VFP_EXT_ARMV8, 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32.f32\t%y1, %y0"},
502 {FPU_VFP_EXT_ARMV8, 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64.f64\t%z1, %z0"},
503 {FPU_VFP_EXT_ARMV8, 0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32.f32\t%y1, %y0"},
504 {FPU_VFP_EXT_ARMV8, 0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64.f64\t%z1, %z0"},
506 /* Generic coprocessor instructions. */
507 { 0, SENTINEL_GENERIC_START, 0, "" },
508 {ARM_EXT_V5E, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
509 {ARM_EXT_V5E, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
510 {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
511 {ARM_EXT_V2, 0x0e10f010, 0x0f10f010, "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
512 {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
513 {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
514 {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
515 {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
517 /* V6 coprocessor instructions. */
518 {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
519 {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
521 /* V5 coprocessor instructions. */
522 {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
523 {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
524 {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
525 {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
526 {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
531 /* Neon opcode table: This does not encode the top byte -- that is
532 checked by the print_insn_neon routine, as it depends on whether we are
533 doing thumb32 or arm32 disassembly. */
535 /* print_insn_neon recognizes the following format control codes:
539 %c print condition code
540 %u print condition code (unconditional in ARM mode,
541 UNPREDICTABLE if not AL in Thumb)
542 %A print v{st,ld}[1234] operands
543 %B print v{st,ld}[1234] any one operands
544 %C print v{st,ld}[1234] single->all operands
546 %E print vmov, vmvn, vorr, vbic encoded constant
547 %F print vtbl,vtbx register list
549 %<bitfield>r print as an ARM register
550 %<bitfield>d print the bitfield in decimal
551 %<bitfield>e print the 2^N - bitfield in decimal
552 %<bitfield>D print as a NEON D register
553 %<bitfield>Q print as a NEON Q register
554 %<bitfield>R print as a NEON D or Q register
555 %<bitfield>Sn print byte scaled width limited by n
556 %<bitfield>Tn print short scaled width limited by n
557 %<bitfield>Un print long scaled width limited by n
559 %<bitfield>'c print specified char iff bitfield is all ones
560 %<bitfield>`c print specified char iff bitfield is all zeroes
561 %<bitfield>?ab... select from array of values in big endian order. */
563 static const struct opcode32 neon_opcodes[] =
566 {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
567 {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
569 /* Move data element to all lanes. */
570 {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
571 {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
572 {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
575 {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
576 {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
578 /* Half-precision conversions. */
579 {FPU_VFP_EXT_FP16, 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
580 {FPU_VFP_EXT_FP16, 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
582 /* NEON fused multiply add instructions. */
583 {FPU_NEON_EXT_FMA, 0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
584 {FPU_NEON_EXT_FMA, 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
586 /* Two registers, miscellaneous. */
587 {FPU_NEON_EXT_ARMV8, 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32.f32\t%12-15,22R, %0-3,5R"},
588 {FPU_NEON_EXT_ARMV8, 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
589 {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
590 {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
591 {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
592 {FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
593 {FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
594 {FPU_NEON_EXT_V1, 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
595 {FPU_NEON_EXT_V1, 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
596 {FPU_NEON_EXT_V1, 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
597 {FPU_NEON_EXT_V1, 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
598 {FPU_NEON_EXT_V1, 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
599 {FPU_NEON_EXT_V1, 0xf3b20300, 0xffb30fd0, "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
600 {FPU_NEON_EXT_V1, 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
601 {FPU_NEON_EXT_V1, 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
602 {FPU_NEON_EXT_V1, 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
603 {FPU_NEON_EXT_V1, 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
604 {FPU_NEON_EXT_V1, 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
605 {FPU_NEON_EXT_V1, 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
606 {FPU_NEON_EXT_V1, 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
607 {FPU_NEON_EXT_V1, 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
608 {FPU_NEON_EXT_V1, 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
609 {FPU_NEON_EXT_V1, 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
610 {FPU_NEON_EXT_V1, 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
611 {FPU_NEON_EXT_V1, 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
612 {FPU_NEON_EXT_V1, 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
613 {FPU_NEON_EXT_V1, 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
614 {FPU_NEON_EXT_V1, 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
615 {FPU_NEON_EXT_V1, 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
616 {FPU_NEON_EXT_V1, 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
617 {FPU_NEON_EXT_V1, 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
618 {FPU_NEON_EXT_V1, 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
619 {FPU_NEON_EXT_V1, 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
620 {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
621 {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
623 /* Three registers of the same length. */
624 {FPU_NEON_EXT_ARMV8, 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
625 {FPU_NEON_EXT_ARMV8, 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
626 {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
627 {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
628 {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
629 {FPU_NEON_EXT_V1, 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
630 {FPU_NEON_EXT_V1, 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
631 {FPU_NEON_EXT_V1, 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
632 {FPU_NEON_EXT_V1, 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
633 {FPU_NEON_EXT_V1, 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
634 {FPU_NEON_EXT_V1, 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
635 {FPU_NEON_EXT_V1, 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
636 {FPU_NEON_EXT_V1, 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
637 {FPU_NEON_EXT_V1, 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
638 {FPU_NEON_EXT_V1, 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
639 {FPU_NEON_EXT_V1, 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
640 {FPU_NEON_EXT_V1, 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
641 {FPU_NEON_EXT_V1, 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
642 {FPU_NEON_EXT_V1, 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
643 {FPU_NEON_EXT_V1, 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
644 {FPU_NEON_EXT_V1, 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
645 {FPU_NEON_EXT_V1, 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
646 {FPU_NEON_EXT_V1, 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
647 {FPU_NEON_EXT_V1, 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
648 {FPU_NEON_EXT_V1, 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
649 {FPU_NEON_EXT_V1, 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
650 {FPU_NEON_EXT_V1, 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
651 {FPU_NEON_EXT_V1, 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
652 {FPU_NEON_EXT_V1, 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
653 {FPU_NEON_EXT_V1, 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
654 {FPU_NEON_EXT_V1, 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
655 {FPU_NEON_EXT_V1, 0xf2000b00, 0xff800f10, "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
656 {FPU_NEON_EXT_V1, 0xf2000b10, 0xff800f10, "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
657 {FPU_NEON_EXT_V1, 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
658 {FPU_NEON_EXT_V1, 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
659 {FPU_NEON_EXT_V1, 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
660 {FPU_NEON_EXT_V1, 0xf3000b00, 0xff800f10, "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
661 {FPU_NEON_EXT_V1, 0xf2000000, 0xfe800f10, "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
662 {FPU_NEON_EXT_V1, 0xf2000010, 0xfe800f10, "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
663 {FPU_NEON_EXT_V1, 0xf2000100, 0xfe800f10, "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
664 {FPU_NEON_EXT_V1, 0xf2000200, 0xfe800f10, "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
665 {FPU_NEON_EXT_V1, 0xf2000210, 0xfe800f10, "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
666 {FPU_NEON_EXT_V1, 0xf2000300, 0xfe800f10, "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
667 {FPU_NEON_EXT_V1, 0xf2000310, 0xfe800f10, "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
668 {FPU_NEON_EXT_V1, 0xf2000400, 0xfe800f10, "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
669 {FPU_NEON_EXT_V1, 0xf2000410, 0xfe800f10, "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
670 {FPU_NEON_EXT_V1, 0xf2000500, 0xfe800f10, "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
671 {FPU_NEON_EXT_V1, 0xf2000510, 0xfe800f10, "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
672 {FPU_NEON_EXT_V1, 0xf2000600, 0xfe800f10, "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
673 {FPU_NEON_EXT_V1, 0xf2000610, 0xfe800f10, "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
674 {FPU_NEON_EXT_V1, 0xf2000700, 0xfe800f10, "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
675 {FPU_NEON_EXT_V1, 0xf2000710, 0xfe800f10, "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
676 {FPU_NEON_EXT_V1, 0xf2000910, 0xfe800f10, "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
677 {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
678 {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
680 /* One register and an immediate value. */
681 {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
682 {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
683 {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
684 {FPU_NEON_EXT_V1, 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
685 {FPU_NEON_EXT_V1, 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
686 {FPU_NEON_EXT_V1, 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
687 {FPU_NEON_EXT_V1, 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
688 {FPU_NEON_EXT_V1, 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
689 {FPU_NEON_EXT_V1, 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
690 {FPU_NEON_EXT_V1, 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
691 {FPU_NEON_EXT_V1, 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
692 {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
693 {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
695 /* Two registers and a shift amount. */
696 {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
697 {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
698 {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
699 {FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
700 {FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
701 {FPU_NEON_EXT_V1, 0xf2880950, 0xfeb80fd0, "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
702 {FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22D, %0-3,5Q, #%16-18d"},
703 {FPU_NEON_EXT_V1, 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
704 {FPU_NEON_EXT_V1, 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
705 {FPU_NEON_EXT_V1, 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
706 {FPU_NEON_EXT_V1, 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
707 {FPU_NEON_EXT_V1, 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
708 {FPU_NEON_EXT_V1, 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
709 {FPU_NEON_EXT_V1, 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
710 {FPU_NEON_EXT_V1, 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
711 {FPU_NEON_EXT_V1, 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
712 {FPU_NEON_EXT_V1, 0xf2900950, 0xfeb00fd0, "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
713 {FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-19d"},
714 {FPU_NEON_EXT_V1, 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
715 {FPU_NEON_EXT_V1, 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
716 {FPU_NEON_EXT_V1, 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
717 {FPU_NEON_EXT_V1, 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
718 {FPU_NEON_EXT_V1, 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
719 {FPU_NEON_EXT_V1, 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
720 {FPU_NEON_EXT_V1, 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
721 {FPU_NEON_EXT_V1, 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
722 {FPU_NEON_EXT_V1, 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
723 {FPU_NEON_EXT_V1, 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
724 {FPU_NEON_EXT_V1, 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
725 {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-20d"},
726 {FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
727 {FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
728 {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
729 {FPU_NEON_EXT_V1, 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
730 {FPU_NEON_EXT_V1, 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
731 {FPU_NEON_EXT_V1, 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
732 {FPU_NEON_EXT_V1, 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
733 {FPU_NEON_EXT_V1, 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
734 {FPU_NEON_EXT_V1, 0xf2a00950, 0xfea00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
735 {FPU_NEON_EXT_V1, 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
736 {FPU_NEON_EXT_V1, 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
737 {FPU_NEON_EXT_V1, 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
738 {FPU_NEON_EXT_V1, 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
739 {FPU_NEON_EXT_V1, 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
740 {FPU_NEON_EXT_V1, 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
741 {FPU_NEON_EXT_V1, 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
742 {FPU_NEON_EXT_V1, 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
743 {FPU_NEON_EXT_V1, 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
744 {FPU_NEON_EXT_V1, 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
745 {FPU_NEON_EXT_V1, 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
746 {FPU_NEON_EXT_V1, 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
747 {FPU_NEON_EXT_V1, 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
748 {FPU_NEON_EXT_V1, 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
749 {FPU_NEON_EXT_V1, 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
750 {FPU_NEON_EXT_V1, 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
751 {FPU_NEON_EXT_V1, 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
752 {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
753 {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
755 /* Three registers of different lengths. */
756 {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
757 {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
758 {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
759 {FPU_NEON_EXT_V1, 0xf2800900, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
760 {FPU_NEON_EXT_V1, 0xf2800b00, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
761 {FPU_NEON_EXT_V1, 0xf2800d00, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
762 {FPU_NEON_EXT_V1, 0xf3800400, 0xff800f50, "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
763 {FPU_NEON_EXT_V1, 0xf3800600, 0xff800f50, "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
764 {FPU_NEON_EXT_V1, 0xf2800000, 0xfe800f50, "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
765 {FPU_NEON_EXT_V1, 0xf2800100, 0xfe800f50, "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
766 {FPU_NEON_EXT_V1, 0xf2800200, 0xfe800f50, "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
767 {FPU_NEON_EXT_V1, 0xf2800300, 0xfe800f50, "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
768 {FPU_NEON_EXT_V1, 0xf2800500, 0xfe800f50, "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
769 {FPU_NEON_EXT_V1, 0xf2800700, 0xfe800f50, "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
770 {FPU_NEON_EXT_V1, 0xf2800800, 0xfe800f50, "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
771 {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
772 {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
774 /* Two registers and a scalar. */
775 {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
776 {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
777 {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
778 {FPU_NEON_EXT_V1, 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
779 {FPU_NEON_EXT_V1, 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
780 {FPU_NEON_EXT_V1, 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
781 {FPU_NEON_EXT_V1, 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
782 {FPU_NEON_EXT_V1, 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
783 {FPU_NEON_EXT_V1, 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
784 {FPU_NEON_EXT_V1, 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
785 {FPU_NEON_EXT_V1, 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
786 {FPU_NEON_EXT_V1, 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
787 {FPU_NEON_EXT_V1, 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
788 {FPU_NEON_EXT_V1, 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
789 {FPU_NEON_EXT_V1, 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
790 {FPU_NEON_EXT_V1, 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
791 {FPU_NEON_EXT_V1, 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
792 {FPU_NEON_EXT_V1, 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
793 {FPU_NEON_EXT_V1, 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
794 {FPU_NEON_EXT_V1, 0xf2800240, 0xfe800f50, "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
795 {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
796 {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
798 /* Element and structure load/store. */
799 {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
800 {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
801 {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
802 {FPU_NEON_EXT_V1, 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
803 {FPU_NEON_EXT_V1, 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
804 {FPU_NEON_EXT_V1, 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
805 {FPU_NEON_EXT_V1, 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
806 {FPU_NEON_EXT_V1, 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
807 {FPU_NEON_EXT_V1, 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
808 {FPU_NEON_EXT_V1, 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
809 {FPU_NEON_EXT_V1, 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
810 {FPU_NEON_EXT_V1, 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
811 {FPU_NEON_EXT_V1, 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
812 {FPU_NEON_EXT_V1, 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
813 {FPU_NEON_EXT_V1, 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
814 {FPU_NEON_EXT_V1, 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
815 {FPU_NEON_EXT_V1, 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
816 {FPU_NEON_EXT_V1, 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
817 {FPU_NEON_EXT_V1, 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
822 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
823 ordered: they must be searched linearly from the top to obtain a correct
826 /* print_insn_arm recognizes the following format control codes:
830 %a print address for ldr/str instruction
831 %s print address for ldr/str halfword/signextend instruction
832 %S like %s but allow UNPREDICTABLE addressing
833 %b print branch destination
834 %c print condition code (always bits 28-31)
835 %m print register mask for ldm/stm instruction
836 %o print operand2 (immediate or register + shift)
837 %p print 'p' iff bits 12-15 are 15
838 %t print 't' iff bit 21 set and bit 24 clear
839 %B print arm BLX(1) destination
840 %C print the PSR sub type.
841 %U print barrier type.
842 %P print address for pli instruction.
844 %<bitfield>r print as an ARM register
845 %<bitfield>T print as an ARM register + 1
846 %<bitfield>R as %r but r15 is UNPREDICTABLE
847 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
848 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
849 %<bitfield>d print the bitfield in decimal
850 %<bitfield>W print the bitfield plus one in decimal
851 %<bitfield>x print the bitfield in hex
852 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
854 %<bitfield>'c print specified char iff bitfield is all ones
855 %<bitfield>`c print specified char iff bitfield is all zeroes
856 %<bitfield>?ab... select from array of values in big endian order
858 %e print arm SMI operand (bits 0..7,8..19).
859 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
860 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
861 %R print the SPSR/CPSR or banked register of an MRS. */
863 static const struct opcode32 arm_opcodes[] =
865 /* ARM instructions. */
866 {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
867 {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
868 {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
869 {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
870 {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
871 {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
872 {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
874 /* V8 instructions. */
875 {ARM_EXT_V8, 0x0320f005, 0x0fffffff, "sevl"},
876 {ARM_EXT_V8, 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
877 {ARM_EXT_V8, 0x01800e90, 0x0ff00ff0, "strlex%c\t%12-15r, %0-3r, [%16-19R]"},
878 {ARM_EXT_V8, 0x01900e9f, 0x0ff00fff, "ldraex%c\t%12-15r, [%16-19R]"},
879 {ARM_EXT_V8, 0x01a00e90, 0x0ff00ff0, "strlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
880 {ARM_EXT_V8, 0x01b00e9f, 0x0ff00fff, "ldraexd%c\t%12-15r, %12-15T, [%16-19R]"},
881 {ARM_EXT_V8, 0x01c00e90, 0x0ff00ff0, "strlexb%c\t%12-15r, %0-3r, [%16-19R]"},
882 {ARM_EXT_V8, 0x01d00e9f, 0x0ff00fff, "ldraexb%c\t%12-15r, [%16-19R]"},
883 {ARM_EXT_V8, 0x01e00e90, 0x0ff00ff0, "strlexh%c\t%12-15r, %0-3r, [%16-19R]"},
884 {ARM_EXT_V8, 0x01f00e9f, 0x0ff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
885 {ARM_EXT_V8, 0x0180fc90, 0x0ff0fff0, "strl%c\t%0-3r, [%16-19R]"},
886 {ARM_EXT_V8, 0x01900c9f, 0x0ff00fff, "ldra%c\t%12-15r, [%16-19R]"},
887 {ARM_EXT_V8, 0x01c0fc90, 0x0ff0fff0, "strlb%c\t%0-3r, [%16-19R]"},
888 {ARM_EXT_V8, 0x01d00c9f, 0x0ff00fff, "ldrab%c\t%12-15r, [%16-19R]"},
889 {ARM_EXT_V8, 0x01e0fc90, 0x0ff0fff0, "strlh%c\t%0-3r, [%16-19R]"},
890 {ARM_EXT_V8, 0x01f00c9f, 0x0ff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
892 /* Virtualization Extension instructions. */
893 {ARM_EXT_VIRT, 0x0160006e, 0x0fffffff, "eret%c"},
894 {ARM_EXT_VIRT, 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
896 /* Integer Divide Extension instructions. */
897 {ARM_EXT_ADIV, 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
898 {ARM_EXT_ADIV, 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
900 /* MP Extension instructions. */
901 {ARM_EXT_MP, 0xf410f000, 0xfc70f000, "pldw\t%a"},
903 /* V7 instructions. */
904 {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"},
905 {ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
906 {ARM_EXT_V8, 0xf57ff051, 0xfffffff3, "dmb\t%U"},
907 {ARM_EXT_V8, 0xf57ff041, 0xfffffff3, "dsb\t%U"},
908 {ARM_EXT_V7, 0xf57ff050, 0xfffffff0, "dmb\t%U"},
909 {ARM_EXT_V7, 0xf57ff040, 0xfffffff0, "dsb\t%U"},
910 {ARM_EXT_V7, 0xf57ff060, 0xfffffff0, "isb\t%U"},
912 /* ARM V6T2 instructions. */
913 {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
914 {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
915 {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
916 {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "strht%c\t%12-15R, %S"},
918 {ARM_EXT_V6T2, 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
919 {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
921 {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
922 {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
923 {ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
924 {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
926 /* ARM Security extension instructions. */
927 {ARM_EXT_SEC, 0x01600070, 0x0ff000f0, "smc%c\t%e"},
929 /* ARM V6K instructions. */
930 {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"},
931 {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
932 {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
933 {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
934 {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
935 {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
936 {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
938 /* ARM V6K NOP hints. */
939 {ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"},
940 {ARM_EXT_V6K, 0x0320f002, 0x0fffffff, "wfe%c"},
941 {ARM_EXT_V6K, 0x0320f003, 0x0fffffff, "wfi%c"},
942 {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"},
943 {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
945 /* ARM V6 instructions. */
946 {ARM_EXT_V6, 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
947 {ARM_EXT_V6, 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
948 {ARM_EXT_V6, 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
949 {ARM_EXT_V6, 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
950 {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
951 {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
952 {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
953 {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
954 {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
955 {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
956 {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
957 {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
958 {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
959 {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
960 {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
961 {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
962 {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
963 {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
964 {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
965 {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
966 {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
967 {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
968 {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
969 {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
970 {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
971 {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
972 {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
973 {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
974 {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
975 {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
976 {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
977 {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
978 {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
979 {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
980 {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
981 {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
982 {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
983 {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
984 {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
985 {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
986 {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
987 {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
988 {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
989 {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
990 {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
991 {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
992 {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
993 {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
994 {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
995 {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
996 {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
997 {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
998 {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
999 {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
1000 {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
1001 {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
1002 {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
1003 {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
1004 {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
1005 {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
1006 {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
1007 {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
1008 {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
1009 {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
1010 {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
1011 {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
1012 {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
1013 {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
1014 {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
1015 {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
1016 {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
1017 {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
1018 {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
1019 {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
1020 {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
1021 {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1022 {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1023 {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1024 {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
1025 {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1026 {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1027 {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1028 {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
1029 {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1030 {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1031 {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1032 {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
1033 {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1034 {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1035 {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1036 {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
1037 {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1038 {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1039 {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
1040 {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
1041 {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1042 {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1043 {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1044 {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
1045 {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
1046 {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
1047 {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
1048 {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1049 {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1050 {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1051 {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1052 {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
1053 {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1054 {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1055 {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
1056 {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
1057 {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
1058 {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
1059 {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
1060 {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
1061 {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
1062 {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
1063 {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1064 {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
1065 {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
1066 {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
1067 {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
1069 /* V5J instruction. */
1070 {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
1072 /* V5 Instructions. */
1073 {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
1074 {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"},
1075 {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
1076 {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
1078 /* V5E "El Segundo" Instructions. */
1079 {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
1080 {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
1081 {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"},
1082 {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1083 {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1084 {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1085 {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
1087 {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1088 {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
1090 {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1091 {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1092 {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1093 {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1095 {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
1096 {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
1097 {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
1098 {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
1100 {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
1101 {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
1103 {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
1104 {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
1105 {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
1106 {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
1108 /* ARM Instructions. */
1109 {ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
1111 {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
1112 {ARM_EXT_V1, 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
1113 {ARM_EXT_V1, 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
1114 {ARM_EXT_V1, 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
1115 {ARM_EXT_V1, 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
1116 {ARM_EXT_V1, 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
1118 {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
1119 {ARM_EXT_V1, 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
1120 {ARM_EXT_V1, 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
1121 {ARM_EXT_V1, 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
1123 {ARM_EXT_V1, 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
1124 {ARM_EXT_V1, 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
1125 {ARM_EXT_V1, 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
1126 {ARM_EXT_V1, 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
1128 {ARM_EXT_V1, 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
1129 {ARM_EXT_V1, 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
1130 {ARM_EXT_V1, 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
1132 {ARM_EXT_V1, 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
1133 {ARM_EXT_V1, 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
1134 {ARM_EXT_V1, 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
1136 {ARM_EXT_V1, 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
1137 {ARM_EXT_V1, 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
1138 {ARM_EXT_V1, 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
1140 {ARM_EXT_V1, 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
1141 {ARM_EXT_V1, 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
1142 {ARM_EXT_V1, 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
1144 {ARM_EXT_V1, 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
1145 {ARM_EXT_V1, 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
1146 {ARM_EXT_V1, 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
1148 {ARM_EXT_V1, 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
1149 {ARM_EXT_V1, 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
1150 {ARM_EXT_V1, 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
1152 {ARM_EXT_V1, 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
1153 {ARM_EXT_V1, 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
1154 {ARM_EXT_V1, 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
1156 {ARM_EXT_V1, 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
1157 {ARM_EXT_V1, 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
1158 {ARM_EXT_V1, 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
1160 {ARM_EXT_VIRT, 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
1161 {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
1162 {ARM_EXT_V3, 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
1164 {ARM_EXT_V1, 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
1165 {ARM_EXT_V1, 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
1166 {ARM_EXT_V1, 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
1168 {ARM_EXT_V1, 0x03200000, 0x0fe00000, "teq%p%c\t%16-19r, %o"},
1169 {ARM_EXT_V1, 0x01200000, 0x0fe00010, "teq%p%c\t%16-19r, %o"},
1170 {ARM_EXT_V1, 0x01200010, 0x0fe00090, "teq%p%c\t%16-19R, %o"},
1172 {ARM_EXT_V1, 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
1173 {ARM_EXT_V1, 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
1174 {ARM_EXT_V1, 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
1176 {ARM_EXT_V1, 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
1177 {ARM_EXT_V1, 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
1178 {ARM_EXT_V1, 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
1180 {ARM_EXT_V1, 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
1181 {ARM_EXT_V1, 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
1182 {ARM_EXT_V1, 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
1184 {ARM_EXT_V1, 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
1185 {ARM_EXT_V1, 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
1186 {ARM_EXT_V1, 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
1187 {ARM_EXT_V1, 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
1188 {ARM_EXT_V1, 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
1189 {ARM_EXT_V1, 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
1190 {ARM_EXT_V1, 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
1192 {ARM_EXT_V1, 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
1193 {ARM_EXT_V1, 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
1194 {ARM_EXT_V1, 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
1196 {ARM_EXT_V1, 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
1197 {ARM_EXT_V1, 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
1198 {ARM_EXT_V1, 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
1200 {ARM_EXT_V1, 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
1201 {ARM_EXT_V1, 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
1203 {ARM_EXT_V1, 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
1205 {ARM_EXT_V1, 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
1206 {ARM_EXT_V1, 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
1208 {ARM_EXT_V1, 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1209 {ARM_EXT_V1, 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1210 {ARM_EXT_V1, 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1211 {ARM_EXT_V1, 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1212 {ARM_EXT_V1, 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1213 {ARM_EXT_V1, 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1214 {ARM_EXT_V1, 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1215 {ARM_EXT_V1, 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1216 {ARM_EXT_V1, 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1217 {ARM_EXT_V1, 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1218 {ARM_EXT_V1, 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1219 {ARM_EXT_V1, 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1220 {ARM_EXT_V1, 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1221 {ARM_EXT_V1, 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1222 {ARM_EXT_V1, 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1223 {ARM_EXT_V1, 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1224 {ARM_EXT_V1, 0x092d0000, 0x0fff0000, "push%c\t%m"},
1225 {ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
1226 {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
1228 {ARM_EXT_V1, 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1229 {ARM_EXT_V1, 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1230 {ARM_EXT_V1, 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1231 {ARM_EXT_V1, 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1232 {ARM_EXT_V1, 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1233 {ARM_EXT_V1, 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1234 {ARM_EXT_V1, 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1235 {ARM_EXT_V1, 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1236 {ARM_EXT_V1, 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1237 {ARM_EXT_V1, 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1238 {ARM_EXT_V1, 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1239 {ARM_EXT_V1, 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1240 {ARM_EXT_V1, 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1241 {ARM_EXT_V1, 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1242 {ARM_EXT_V1, 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1243 {ARM_EXT_V1, 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1244 {ARM_EXT_V1, 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
1245 {ARM_EXT_V1, 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
1246 {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
1248 {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
1249 {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
1252 {ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
1253 {0, 0x00000000, 0x00000000, 0}
1256 /* print_insn_thumb16 recognizes the following format control codes:
1258 %S print Thumb register (bits 3..5 as high number if bit 6 set)
1259 %D print Thumb register (bits 0..2 as high number if bit 7 set)
1260 %<bitfield>I print bitfield as a signed decimal
1261 (top bit of range being the sign bit)
1262 %N print Thumb register mask (with LR)
1263 %O print Thumb register mask (with PC)
1264 %M print Thumb register mask
1265 %b print CZB's 6-bit unsigned branch destination
1266 %s print Thumb right-shift immediate (6..10; 0 == 32).
1267 %c print the condition code
1268 %C print the condition code, or "s" if not conditional
1269 %x print warning if conditional an not at end of IT block"
1270 %X print "\t; unpredictable <IT:code>" if conditional
1271 %I print IT instruction suffix and operands
1272 %W print Thumb Writeback indicator for LDMIA
1273 %<bitfield>r print bitfield as an ARM register
1274 %<bitfield>d print bitfield as a decimal
1275 %<bitfield>H print (bitfield * 2) as a decimal
1276 %<bitfield>W print (bitfield * 4) as a decimal
1277 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
1278 %<bitfield>B print Thumb branch destination (signed displacement)
1279 %<bitfield>c print bitfield as a condition code
1280 %<bitnum>'c print specified char iff bit is one
1281 %<bitnum>?ab print a if bit is one else print b. */
1283 static const struct opcode16 thumb_opcodes[] =
1285 /* Thumb instructions. */
1287 /* ARM V8 instructions. */
1288 {ARM_EXT_V8, 0xbf50, 0xffff, "sevl%c"},
1289 {ARM_EXT_V8, 0xba80, 0xffc0, "hlt\t%0-5x"},
1291 /* ARM V6K no-argument instructions. */
1292 {ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"},
1293 {ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"},
1294 {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe%c"},
1295 {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi%c"},
1296 {ARM_EXT_V6K, 0xbf40, 0xffff, "sev%c"},
1297 {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
1299 /* ARM V6T2 instructions. */
1300 {ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
1301 {ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
1302 {ARM_EXT_V6T2, 0xbf00, 0xff00, "it%I%X"},
1305 {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
1306 {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
1307 {ARM_EXT_V6, 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
1308 {ARM_EXT_V6, 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
1309 {ARM_EXT_V6, 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
1310 {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
1311 {ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble%X"},
1312 {ARM_EXT_V6, 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
1313 {ARM_EXT_V6, 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
1314 {ARM_EXT_V6, 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
1315 {ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
1317 /* ARM V5 ISA extends Thumb. */
1318 {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
1319 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
1320 {ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
1321 /* ARM V4T ISA (Thumb v1). */
1322 {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
1324 {ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
1325 {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
1326 {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
1327 {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
1328 {ARM_EXT_V4T, 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
1329 {ARM_EXT_V4T, 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
1330 {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
1331 {ARM_EXT_V4T, 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
1332 {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
1333 {ARM_EXT_V4T, 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
1334 {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
1335 {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
1336 {ARM_EXT_V4T, 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
1337 {ARM_EXT_V4T, 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
1338 {ARM_EXT_V4T, 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
1339 {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
1341 {ARM_EXT_V4T, 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
1342 {ARM_EXT_V4T, 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
1344 {ARM_EXT_V4T, 0x4700, 0xFF80, "bx%c\t%S%x"},
1345 {ARM_EXT_V4T, 0x4400, 0xFF00, "add%c\t%D, %S"},
1346 {ARM_EXT_V4T, 0x4500, 0xFF00, "cmp%c\t%D, %S"},
1347 {ARM_EXT_V4T, 0x4600, 0xFF00, "mov%c\t%D, %S"},
1349 {ARM_EXT_V4T, 0xB400, 0xFE00, "push%c\t%N"},
1350 {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop%c\t%O"},
1352 {ARM_EXT_V4T, 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
1353 {ARM_EXT_V4T, 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
1354 {ARM_EXT_V4T, 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
1355 {ARM_EXT_V4T, 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
1357 {ARM_EXT_V4T, 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
1358 {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
1359 {ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
1361 {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
1362 {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
1364 {ARM_EXT_V4T, 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
1365 {ARM_EXT_V4T, 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
1366 {ARM_EXT_V4T, 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
1367 {ARM_EXT_V4T, 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
1369 {ARM_EXT_V4T, 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
1370 {ARM_EXT_V4T, 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
1371 {ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
1372 {ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
1374 {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
1376 {ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
1377 {ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
1378 {ARM_EXT_V4T, 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
1379 {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
1381 {ARM_EXT_V4T, 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
1382 {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
1384 {ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
1385 {ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
1387 {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
1388 {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
1390 {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
1391 {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
1393 {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"},
1395 {ARM_EXT_V4T, 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
1396 {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
1398 {ARM_EXT_V4T, 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
1400 /* The E800 .. FFFF range is unconditionally redirected to the
1401 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
1402 are processed via that table. Thus, we can never encounter a
1403 bare "second half of BL/BLX(1)" instruction here. */
1404 {ARM_EXT_V1, 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
1408 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
1409 We adopt the convention that hw1 is the high 16 bits of .value and
1410 .mask, hw2 the low 16 bits.
1412 print_insn_thumb32 recognizes the following format control codes:
1416 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
1417 %M print a modified 12-bit immediate (same location)
1418 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
1419 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
1420 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
1421 %S print a possibly-shifted Rm
1423 %L print address for a ldrd/strd instruction
1424 %a print the address of a plain load/store
1425 %w print the width and signedness of a core load/store
1426 %m print register mask for ldm/stm
1428 %E print the lsb and width fields of a bfc/bfi instruction
1429 %F print the lsb and width fields of a sbfx/ubfx instruction
1430 %b print a conditional branch offset
1431 %B print an unconditional branch offset
1432 %s print the shift field of an SSAT instruction
1433 %R print the rotation field of an SXT instruction
1434 %U print barrier type.
1435 %P print address for pli instruction.
1436 %c print the condition code
1437 %x print warning if conditional an not at end of IT block"
1438 %X print "\t; unpredictable <IT:code>" if conditional
1440 %<bitfield>d print bitfield in decimal
1441 %<bitfield>W print bitfield*4 in decimal
1442 %<bitfield>r print bitfield as an ARM register
1443 %<bitfield>R as %<>r bit r15 is UNPREDICTABLE
1444 %<bitfield>c print bitfield as a condition code
1446 %<bitfield>'c print specified char iff bitfield is all ones
1447 %<bitfield>`c print specified char iff bitfield is all zeroes
1448 %<bitfield>?ab... select from array of values in big endian order
1450 With one exception at the bottom (done because BL and BLX(1) need
1451 to come dead last), this table was machine-sorted first in
1452 decreasing order of number of bits set in the mask, then in
1453 increasing numeric order of mask, then in increasing numeric order
1454 of opcode. This order is not the clearest for a human reader, but
1455 is guaranteed never to catch a special-case bit pattern with a more
1456 general mask, which is important, because this instruction encoding
1457 makes heavy use of special-case bit patterns. */
1458 static const struct opcode32 thumb32_opcodes[] =
1460 /* V8 instructions. */
1461 {ARM_EXT_V8, 0xf3af8005, 0xffffffff, "sevl%c.w"},
1462 {ARM_EXT_V8, 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
1463 {ARM_EXT_V8, 0xe8c00f8f, 0xfff00fff, "strlb%c\t%12-15r, [%16-19R]"},
1464 {ARM_EXT_V8, 0xe8c00f9f, 0xfff00fff, "strlh%c\t%12-15r, [%16-19R]"},
1465 {ARM_EXT_V8, 0xe8c00faf, 0xfff00fff, "strl%c\t%12-15r, [%16-19R]"},
1466 {ARM_EXT_V8, 0xe8c00fc0, 0xfff00ff0, "strlexb%c\t%0-3r, %12-15r, [%16-19R]"},
1467 {ARM_EXT_V8, 0xe8c00fd0, 0xfff00ff0, "strlexh%c\t%0-3r, %12-15r, [%16-19R]"},
1468 {ARM_EXT_V8, 0xe8c00fe0, 0xfff00ff0, "strlex%c\t%0-3r, %12-15r, [%16-19R]"},
1469 {ARM_EXT_V8, 0xe8c000f0, 0xfff000f0, "strlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
1470 {ARM_EXT_V8, 0xe8d00f8f, 0xfff00fff, "ldrab%c\t%12-15r, [%16-19R]"},
1471 {ARM_EXT_V8, 0xe8d00f9f, 0xfff00fff, "ldrah%c\t%12-15r, [%16-19R]"},
1472 {ARM_EXT_V8, 0xe8d00faf, 0xfff00fff, "ldra%c\t%12-15r, [%16-19R]"},
1473 {ARM_EXT_V8, 0xe8d00fcf, 0xfff00fff, "ldraexb%c\t%12-15r, [%16-19R]"},
1474 {ARM_EXT_V8, 0xe8d00fdf, 0xfff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
1475 {ARM_EXT_V8, 0xe8d00fef, 0xfff00fff, "ldraex%c\t%12-15r, [%16-19R]"},
1476 {ARM_EXT_V8, 0xe8d000ff, 0xfff000ff, "ldraexd%c\t%12-15r, %8-11r, [%16-19R]"},
1478 /* V7 instructions. */
1479 {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
1480 {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
1481 {ARM_EXT_V8, 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
1482 {ARM_EXT_V8, 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
1483 {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
1484 {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
1485 {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
1486 {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
1487 {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
1489 /* Virtualization Extension instructions. */
1490 {ARM_EXT_VIRT, 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
1491 /* We skip ERET as that is SUBS pc, lr, #0. */
1493 /* MP Extension instructions. */
1494 {ARM_EXT_MP, 0xf830f000, 0xff70f000, "pldw%c\t%a"},
1496 /* Security extension instructions. */
1497 {ARM_EXT_SEC, 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
1499 /* Instructions defined in the basic V6T2 set. */
1500 {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"},
1501 {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"},
1502 {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"},
1503 {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"},
1504 {ARM_EXT_V6T2, 0xf3af8004, 0xffffffff, "sev%c.w"},
1505 {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
1507 {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"},
1508 {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
1509 {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
1510 {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
1511 {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
1512 {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
1513 {ARM_EXT_V6T2, 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
1514 {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
1515 {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
1516 {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
1517 {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
1518 {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
1519 {ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
1520 {ARM_EXT_V6T2, 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
1521 {ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
1522 {ARM_EXT_V6T2, 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
1523 {ARM_EXT_V6T2, 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
1524 {ARM_EXT_V6T2, 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
1525 {ARM_EXT_V6T2, 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
1526 {ARM_EXT_V6T2, 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
1527 {ARM_EXT_V6T2, 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
1528 {ARM_EXT_V6T2, 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
1529 {ARM_EXT_V6T2, 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
1530 {ARM_EXT_V6T2, 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
1531 {ARM_EXT_V6T2, 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
1532 {ARM_EXT_V6T2, 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
1533 {ARM_EXT_V6T2, 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
1534 {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
1535 {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
1536 {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
1537 {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
1538 {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
1539 {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
1540 {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
1541 {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
1542 {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
1543 {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
1544 {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
1545 {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
1546 {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
1547 {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
1548 {ARM_EXT_V6T2, 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
1549 {ARM_EXT_V6T2, 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
1550 {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
1551 {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
1552 {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
1553 {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
1554 {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
1555 {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
1556 {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
1557 {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
1558 {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
1559 {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
1560 {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
1561 {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
1562 {ARM_EXT_V6T2, 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
1563 {ARM_EXT_V6T2, 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
1564 {ARM_EXT_V6T2, 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
1565 {ARM_EXT_V6T2, 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
1566 {ARM_EXT_V6T2, 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
1567 {ARM_EXT_V6T2, 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
1568 {ARM_EXT_V6T2, 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
1569 {ARM_EXT_V6T2, 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
1570 {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
1571 {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
1572 {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
1573 {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
1574 {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
1575 {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
1576 {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
1577 {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
1578 {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
1579 {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
1580 {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
1581 {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
1582 {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
1583 {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
1584 {ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
1585 {ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
1586 {ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"},
1587 {ARM_EXT_V6T2, 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
1588 {ARM_EXT_V6T2, 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
1589 {ARM_EXT_V6T2, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
1590 {ARM_EXT_V6T2, 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
1591 {ARM_EXT_V6T2, 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
1592 {ARM_EXT_V6T2, 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
1593 {ARM_EXT_V6T2, 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
1594 {ARM_EXT_V6T2, 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
1595 {ARM_EXT_V6T2, 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
1596 {ARM_EXT_V6T2, 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
1597 {ARM_EXT_V6T2, 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
1598 {ARM_EXT_V6T2, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
1599 {ARM_EXT_V6T2, 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
1600 {ARM_EXT_V6T2, 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
1601 {ARM_EXT_V6T2, 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
1602 {ARM_EXT_V6T2, 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
1603 {ARM_EXT_V6T2, 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
1604 {ARM_EXT_V6T2, 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
1605 {ARM_EXT_V6T2, 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
1606 {ARM_EXT_V6T2, 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
1607 {ARM_EXT_V6T2, 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
1608 {ARM_EXT_V6T2, 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
1609 {ARM_EXT_V6T2, 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
1610 {ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
1611 {ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1612 {ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1613 {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1614 {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1615 {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1616 {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1617 {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1618 {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1619 {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
1620 {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
1621 {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
1622 {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld%c\t%a"},
1623 {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1624 {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1625 {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1626 {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1627 {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1628 {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1629 {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1630 {ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
1631 {ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
1632 {ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
1633 {ARM_EXT_V6T2, 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
1634 {ARM_EXT_V6T2, 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
1635 {ARM_EXT_V6T2, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1636 {ARM_EXT_V6T2, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
1637 {ARM_EXT_V6T2, 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
1638 {ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
1639 {ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"},
1640 {ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
1641 {ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
1642 {ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
1643 {ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
1644 {ARM_EXT_V6T2, 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
1645 {ARM_EXT_V6T2, 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
1646 {ARM_EXT_V6T2, 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
1647 {ARM_EXT_V6T2, 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
1648 {ARM_EXT_V6T2, 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
1649 {ARM_EXT_V6T2, 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
1650 {ARM_EXT_V6T2, 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
1651 {ARM_EXT_V6T2, 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
1652 {ARM_EXT_V6T2, 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
1653 {ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
1654 {ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
1655 {ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
1656 {ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
1657 {ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
1658 {ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
1659 {ARM_EXT_V6T2, 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
1660 {ARM_EXT_V6T2, 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
1661 {ARM_EXT_V6T2, 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
1662 {ARM_EXT_V6T2, 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
1663 {ARM_EXT_V6T2, 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
1664 {ARM_EXT_V6T2, 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
1665 {ARM_EXT_V6T2, 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
1666 {ARM_EXT_V6T2, 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
1667 {ARM_EXT_V6T2, 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
1668 {ARM_EXT_V6T2, 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
1669 {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
1670 {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
1671 {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
1672 {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
1673 {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
1674 {ARM_EXT_V6T2, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
1675 {ARM_EXT_V6T2, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
1676 {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
1677 {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
1679 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
1680 {ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
1681 {ARM_EXT_V6T2, 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
1682 {ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
1683 {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
1685 /* These have been 32-bit since the invention of Thumb. */
1686 {ARM_EXT_V4T, 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
1687 {ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
1690 {ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
1694 static const char *const arm_conditional[] =
1695 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
1696 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
1698 static const char *const arm_fp_const[] =
1699 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
1701 static const char *const arm_shift[] =
1702 {"lsl", "lsr", "asr", "ror"};
1707 const char *description;
1708 const char *reg_names[16];
1712 static const arm_regname regnames[] =
1714 { "raw" , "Select raw register names",
1715 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
1716 { "gcc", "Select register names used by GCC",
1717 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
1718 { "std", "Select register names used in ARM's ISA documentation",
1719 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
1720 { "apcs", "Select register names used in the APCS",
1721 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
1722 { "atpcs", "Select register names used in the ATPCS",
1723 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
1724 { "special-atpcs", "Select special register names used in the ATPCS",
1725 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
1728 static const char *const iwmmxt_wwnames[] =
1729 {"b", "h", "w", "d"};
1731 static const char *const iwmmxt_wwssnames[] =
1732 {"b", "bus", "bc", "bss",
1733 "h", "hus", "hc", "hss",
1734 "w", "wus", "wc", "wss",
1735 "d", "dus", "dc", "dss"
1738 static const char *const iwmmxt_regnames[] =
1739 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
1740 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
1743 static const char *const iwmmxt_cregnames[] =
1744 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
1745 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
1748 /* Default to GCC register name set. */
1749 static unsigned int regname_selected = 1;
1751 #define NUM_ARM_REGNAMES NUM_ELEM (regnames)
1752 #define arm_regnames regnames[regname_selected].reg_names
1754 static bfd_boolean force_thumb = FALSE;
1756 /* Current IT instruction state. This contains the same state as the IT
1757 bits in the CPSR. */
1758 static unsigned int ifthen_state;
1759 /* IT state for the next instruction. */
1760 static unsigned int ifthen_next_state;
1761 /* The address of the insn for which the IT state is valid. */
1762 static bfd_vma ifthen_address;
1763 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
1764 /* Indicates that the current Conditional state is unconditional or outside
1766 #define COND_UNCOND 16
1771 get_arm_regname_num_options (void)
1773 return NUM_ARM_REGNAMES;
1777 set_arm_regname_option (int option)
1779 int old = regname_selected;
1780 regname_selected = option;
1785 get_arm_regnames (int option,
1786 const char **setname,
1787 const char **setdescription,
1788 const char *const **register_names)
1790 *setname = regnames[option].name;
1791 *setdescription = regnames[option].description;
1792 *register_names = regnames[option].reg_names;
1796 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
1797 Returns pointer to following character of the format string and
1798 fills in *VALUEP and *WIDTHP with the extracted value and number of
1799 bits extracted. WIDTHP can be NULL. */
1802 arm_decode_bitfield (const char *ptr,
1804 unsigned long *valuep,
1807 unsigned long value = 0;
1815 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
1816 start = start * 10 + *ptr - '0';
1818 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
1819 end = end * 10 + *ptr - '0';
1825 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
1828 while (*ptr++ == ',');
1836 arm_decode_shift (long given, fprintf_ftype func, void *stream,
1837 bfd_boolean print_shift)
1839 func (stream, "%s", arm_regnames[given & 0xf]);
1841 if ((given & 0xff0) != 0)
1843 if ((given & 0x10) == 0)
1845 int amount = (given & 0xf80) >> 7;
1846 int shift = (given & 0x60) >> 5;
1852 func (stream, ", rrx");
1860 func (stream, ", %s #%d", arm_shift[shift], amount);
1862 func (stream, ", #%d", amount);
1864 else if ((given & 0x80) == 0x80)
1865 func (stream, "\t; <illegal shifter operand>");
1866 else if (print_shift)
1867 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
1868 arm_regnames[(given & 0xf00) >> 8]);
1870 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
1879 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
1880 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
1881 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
1882 #define PRE_BIT_SET (given & (1 << P_BIT))
1884 /* Print one coprocessor instruction on INFO->STREAM.
1885 Return TRUE if the instuction matched, FALSE if this is not a
1886 recognised coprocessor instruction. */
1889 print_insn_coprocessor (bfd_vma pc,
1890 struct disassemble_info *info,
1894 const struct opcode32 *insn;
1895 void *stream = info->stream;
1896 fprintf_ftype func = info->fprintf_func;
1898 unsigned long value = 0;
1899 struct arm_private_data *private_data = info->private_data;
1900 unsigned long allowed_arches = private_data->features.coproc;
1903 for (insn = coprocessor_opcodes; insn->assembler; insn++)
1905 unsigned long u_reg = 16;
1906 bfd_boolean is_unpredictable = FALSE;
1907 signed long value_in_comment = 0;
1910 if (insn->arch == 0)
1911 switch (insn->value)
1913 case SENTINEL_IWMMXT_START:
1914 if (info->mach != bfd_mach_arm_XScale
1915 && info->mach != bfd_mach_arm_iWMMXt
1916 && info->mach != bfd_mach_arm_iWMMXt2)
1919 while (insn->arch != 0 && insn->value != SENTINEL_IWMMXT_END);
1922 case SENTINEL_IWMMXT_END:
1925 case SENTINEL_GENERIC_START:
1926 allowed_arches = private_data->features.core;
1934 value = insn->value;
1937 /* The high 4 bits are 0xe for Arm conditional instructions, and
1938 0xe for arm unconditional instructions. The rest of the
1939 encoding is the same. */
1941 value |= 0xe0000000;
1949 /* Only match unconditional instuctions against unconditional
1951 if ((given & 0xf0000000) == 0xf0000000)
1958 cond = (given >> 28) & 0xf;
1964 if ((given & mask) != value)
1967 if ((insn->arch & allowed_arches) == 0)
1970 for (c = insn->assembler; *c; c++)
1977 func (stream, "%%");
1982 int rn = (given >> 16) & 0xf;
1983 bfd_vma offset = given & 0xff;
1985 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
1987 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
1989 /* Not unindexed. The offset is scaled. */
1990 offset = offset * 4;
1991 if (NEGATIVE_BIT_SET)
1994 value_in_comment = offset;
2000 func (stream, ", #%d]%s",
2002 WRITEBACK_BIT_SET ? "!" : "");
2003 else if (NEGATIVE_BIT_SET)
2004 func (stream, ", #-0]");
2012 if (WRITEBACK_BIT_SET)
2015 func (stream, ", #%d", (int) offset);
2016 else if (NEGATIVE_BIT_SET)
2017 func (stream, ", #-0");
2021 func (stream, ", {%s%d}",
2022 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
2024 value_in_comment = offset;
2027 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
2029 func (stream, "\t; ");
2030 /* For unaligned PCs, apply off-by-alignment
2032 info->print_address_func (offset + pc
2033 + info->bytes_per_chunk * 2
2042 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
2043 int offset = (given >> 1) & 0x3f;
2046 func (stream, "{d%d}", regno);
2047 else if (regno + offset > 32)
2048 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
2050 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
2055 if (cond != COND_UNCOND)
2056 is_unpredictable = TRUE;
2060 func (stream, "%s", arm_conditional[cond]);
2064 /* Print a Cirrus/DSP shift immediate. */
2065 /* Immediates are 7bit signed ints with bits 0..3 in
2066 bits 0..3 of opcode and bits 4..6 in bits 5..7
2071 imm = (given & 0xf) | ((given & 0xe0) >> 1);
2073 /* Is ``imm'' a negative number? */
2077 func (stream, "%d", imm);
2083 switch (given & 0x00408000)
2100 switch (given & 0x00080080)
2112 func (stream, _("<illegal precision>"));
2118 switch (given & 0x00408000)
2136 switch (given & 0x60)
2152 case '0': case '1': case '2': case '3': case '4':
2153 case '5': case '6': case '7': case '8': case '9':
2157 c = arm_decode_bitfield (c, given, &value, &width);
2163 is_unpredictable = TRUE;
2168 /* Eat the 'u' character. */
2172 is_unpredictable = TRUE;
2175 func (stream, "%s", arm_regnames[value]);
2178 func (stream, "d%ld", value);
2182 func (stream, "<illegal reg q%ld.5>", value >> 1);
2184 func (stream, "q%ld", value >> 1);
2187 func (stream, "%ld", value);
2188 value_in_comment = value;
2192 int from = (given & (1 << 7)) ? 32 : 16;
2193 func (stream, "%ld", from - value);
2199 func (stream, "#%s", arm_fp_const[value & 7]);
2201 func (stream, "f%ld", value);
2206 func (stream, "%s", iwmmxt_wwnames[value]);
2208 func (stream, "%s", iwmmxt_wwssnames[value]);
2212 func (stream, "%s", iwmmxt_regnames[value]);
2215 func (stream, "%s", iwmmxt_cregnames[value]);
2219 func (stream, "0x%lx", (value & 0xffffffffUL));
2226 func (stream, "eq");
2230 func (stream, "vs");
2234 func (stream, "ge");
2238 func (stream, "gt");
2242 func (stream, "??");
2250 func (stream, "%c", *c);
2254 if (value == ((1ul << width) - 1))
2255 func (stream, "%c", *c);
2258 func (stream, "%c", c[(1 << width) - (int) value]);
2269 int single = *c++ == 'y';
2274 case '4': /* Sm pair */
2275 case '0': /* Sm, Dm */
2276 regno = given & 0x0000000f;
2280 regno += (given >> 5) & 1;
2283 regno += ((given >> 5) & 1) << 4;
2286 case '1': /* Sd, Dd */
2287 regno = (given >> 12) & 0x0000000f;
2291 regno += (given >> 22) & 1;
2294 regno += ((given >> 22) & 1) << 4;
2297 case '2': /* Sn, Dn */
2298 regno = (given >> 16) & 0x0000000f;
2302 regno += (given >> 7) & 1;
2305 regno += ((given >> 7) & 1) << 4;
2308 case '3': /* List */
2310 regno = (given >> 12) & 0x0000000f;
2314 regno += (given >> 22) & 1;
2317 regno += ((given >> 22) & 1) << 4;
2324 func (stream, "%c%d", single ? 's' : 'd', regno);
2328 int count = given & 0xff;
2335 func (stream, "-%c%d",
2343 func (stream, ", %c%d", single ? 's' : 'd',
2349 switch (given & 0x00400100)
2351 case 0x00000000: func (stream, "b"); break;
2352 case 0x00400000: func (stream, "h"); break;
2353 case 0x00000100: func (stream, "w"); break;
2354 case 0x00400100: func (stream, "d"); break;
2362 /* given (20, 23) | given (0, 3) */
2363 value = ((given >> 16) & 0xf0) | (given & 0xf);
2364 func (stream, "%d", (int) value);
2369 /* This is like the 'A' operator, except that if
2370 the width field "M" is zero, then the offset is
2371 *not* multiplied by four. */
2373 int offset = given & 0xff;
2374 int multiplier = (given & 0x00000100) ? 4 : 1;
2376 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
2380 value_in_comment = offset * multiplier;
2381 if (NEGATIVE_BIT_SET)
2382 value_in_comment = - value_in_comment;
2388 func (stream, ", #%s%d]%s",
2389 NEGATIVE_BIT_SET ? "-" : "",
2390 offset * multiplier,
2391 WRITEBACK_BIT_SET ? "!" : "");
2393 func (stream, "], #%s%d",
2394 NEGATIVE_BIT_SET ? "-" : "",
2395 offset * multiplier);
2404 int imm4 = (given >> 4) & 0xf;
2405 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
2406 int ubit = ! NEGATIVE_BIT_SET;
2407 const char *rm = arm_regnames [given & 0xf];
2408 const char *rn = arm_regnames [(given >> 16) & 0xf];
2414 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
2416 func (stream, ", lsl #%d", imm4);
2423 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
2425 func (stream, ", lsl #%d", imm4);
2427 if (puw_bits == 5 || puw_bits == 7)
2432 func (stream, "INVALID");
2440 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
2441 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
2451 func (stream, "%c", *c);
2454 if (value_in_comment > 32 || value_in_comment < -16)
2455 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
2457 if (is_unpredictable)
2458 func (stream, UNPREDICTABLE_INSTRUCTION);
2465 /* Decodes and prints ARM addressing modes. Returns the offset
2466 used in the address, if any, if it is worthwhile printing the
2467 offset as a hexadecimal value in a comment at the end of the
2468 line of disassembly. */
2471 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
2473 void *stream = info->stream;
2474 fprintf_ftype func = info->fprintf_func;
2477 if (((given & 0x000f0000) == 0x000f0000)
2478 && ((given & 0x02000000) == 0))
2480 offset = given & 0xfff;
2482 func (stream, "[pc");
2486 /* Pre-indexed. Elide offset of positive zero when
2488 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
2489 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
2491 if (NEGATIVE_BIT_SET)
2496 /* Cope with the possibility of write-back
2497 being used. Probably a very dangerous thing
2498 for the programmer to do, but who are we to
2500 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
2502 else /* Post indexed. */
2504 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
2506 /* Ie ignore the offset. */
2510 func (stream, "\t; ");
2511 info->print_address_func (offset, info);
2516 func (stream, "[%s",
2517 arm_regnames[(given >> 16) & 0xf]);
2521 if ((given & 0x02000000) == 0)
2523 /* Elide offset of positive zero when non-writeback. */
2524 offset = given & 0xfff;
2525 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
2526 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
2530 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
2531 arm_decode_shift (given, func, stream, TRUE);
2534 func (stream, "]%s",
2535 WRITEBACK_BIT_SET ? "!" : "");
2539 if ((given & 0x02000000) == 0)
2541 /* Always show offset. */
2542 offset = given & 0xfff;
2543 func (stream, "], #%s%d",
2544 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
2548 func (stream, "], %s",
2549 NEGATIVE_BIT_SET ? "-" : "");
2550 arm_decode_shift (given, func, stream, TRUE);
2555 return (signed long) offset;
2558 /* Print one neon instruction on INFO->STREAM.
2559 Return TRUE if the instuction matched, FALSE if this is not a
2560 recognised neon instruction. */
2563 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
2565 const struct opcode32 *insn;
2566 void *stream = info->stream;
2567 fprintf_ftype func = info->fprintf_func;
2571 if ((given & 0xef000000) == 0xef000000)
2573 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
2574 unsigned long bit28 = given & (1 << 28);
2576 given &= 0x00ffffff;
2578 given |= 0xf3000000;
2580 given |= 0xf2000000;
2582 else if ((given & 0xff000000) == 0xf9000000)
2583 given ^= 0xf9000000 ^ 0xf4000000;
2588 for (insn = neon_opcodes; insn->assembler; insn++)
2590 if ((given & insn->mask) == insn->value)
2592 signed long value_in_comment = 0;
2593 bfd_boolean is_unpredictable = FALSE;
2596 for (c = insn->assembler; *c; c++)
2603 func (stream, "%%");
2607 if (thumb && ifthen_state)
2608 is_unpredictable = TRUE;
2612 if (thumb && ifthen_state)
2613 func (stream, "%s", arm_conditional[IFTHEN_COND]);
2618 static const unsigned char enc[16] =
2620 0x4, 0x14, /* st4 0,1 */
2632 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2633 int rn = ((given >> 16) & 0xf);
2634 int rm = ((given >> 0) & 0xf);
2635 int align = ((given >> 4) & 0x3);
2636 int type = ((given >> 8) & 0xf);
2637 int n = enc[type] & 0xf;
2638 int stride = (enc[type] >> 4) + 1;
2643 for (ix = 0; ix != n; ix++)
2644 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
2646 func (stream, "d%d", rd);
2648 func (stream, "d%d-d%d", rd, rd + n - 1);
2649 func (stream, "}, [%s", arm_regnames[rn]);
2651 func (stream, " :%d", 32 << align);
2656 func (stream, ", %s", arm_regnames[rm]);
2662 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2663 int rn = ((given >> 16) & 0xf);
2664 int rm = ((given >> 0) & 0xf);
2665 int idx_align = ((given >> 4) & 0xf);
2667 int size = ((given >> 10) & 0x3);
2668 int idx = idx_align >> (size + 1);
2669 int length = ((given >> 8) & 3) + 1;
2673 if (length > 1 && size > 0)
2674 stride = (idx_align & (1 << size)) ? 2 : 1;
2680 int amask = (1 << size) - 1;
2681 if ((idx_align & (1 << size)) != 0)
2685 if ((idx_align & amask) == amask)
2687 else if ((idx_align & amask) != 0)
2694 if (size == 2 && (idx_align & 2) != 0)
2696 align = (idx_align & 1) ? 16 << size : 0;
2700 if ((size == 2 && (idx_align & 3) != 0)
2701 || (idx_align & 1) != 0)
2708 if ((idx_align & 3) == 3)
2710 align = (idx_align & 3) * 64;
2713 align = (idx_align & 1) ? 32 << size : 0;
2721 for (i = 0; i < length; i++)
2722 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
2723 rd + i * stride, idx);
2724 func (stream, "}, [%s", arm_regnames[rn]);
2726 func (stream, " :%d", align);
2731 func (stream, ", %s", arm_regnames[rm]);
2737 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2738 int rn = ((given >> 16) & 0xf);
2739 int rm = ((given >> 0) & 0xf);
2740 int align = ((given >> 4) & 0x1);
2741 int size = ((given >> 6) & 0x3);
2742 int type = ((given >> 8) & 0x3);
2744 int stride = ((given >> 5) & 0x1);
2747 if (stride && (n == 1))
2754 for (ix = 0; ix != n; ix++)
2755 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
2757 func (stream, "d%d[]", rd);
2759 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
2760 func (stream, "}, [%s", arm_regnames[rn]);
2763 align = (8 * (type + 1)) << size;
2765 align = (size > 1) ? align >> 1 : align;
2766 if (type == 2 || (type == 0 && !size))
2767 func (stream, " :<bad align %d>", align);
2769 func (stream, " :%d", align);
2775 func (stream, ", %s", arm_regnames[rm]);
2781 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
2782 int size = (given >> 20) & 3;
2783 int reg = raw_reg & ((4 << size) - 1);
2784 int ix = raw_reg >> size >> 2;
2786 func (stream, "d%d[%d]", reg, ix);
2791 /* Neon encoded constant for mov, mvn, vorr, vbic. */
2794 int cmode = (given >> 8) & 0xf;
2795 int op = (given >> 5) & 0x1;
2796 unsigned long value = 0, hival = 0;
2801 bits |= ((given >> 24) & 1) << 7;
2802 bits |= ((given >> 16) & 7) << 4;
2803 bits |= ((given >> 0) & 15) << 0;
2807 shift = (cmode >> 1) & 3;
2808 value = (unsigned long) bits << (8 * shift);
2811 else if (cmode < 12)
2813 shift = (cmode >> 1) & 1;
2814 value = (unsigned long) bits << (8 * shift);
2817 else if (cmode < 14)
2819 shift = (cmode & 1) + 1;
2820 value = (unsigned long) bits << (8 * shift);
2821 value |= (1ul << (8 * shift)) - 1;
2824 else if (cmode == 14)
2828 /* Bit replication into bytes. */
2834 for (ix = 7; ix >= 0; ix--)
2836 mask = ((bits >> ix) & 1) ? 0xff : 0;
2838 value = (value << 8) | mask;
2840 hival = (hival << 8) | mask;
2846 /* Byte replication. */
2847 value = (unsigned long) bits;
2853 /* Floating point encoding. */
2856 value = (unsigned long) (bits & 0x7f) << 19;
2857 value |= (unsigned long) (bits & 0x80) << 24;
2858 tmp = bits & 0x40 ? 0x3c : 0x40;
2859 value |= (unsigned long) tmp << 24;
2865 func (stream, "<illegal constant %.8x:%x:%x>",
2873 func (stream, "#%ld\t; 0x%.2lx", value, value);
2877 func (stream, "#%ld\t; 0x%.4lx", value, value);
2883 unsigned char valbytes[4];
2886 /* Do this a byte at a time so we don't have to
2887 worry about the host's endianness. */
2888 valbytes[0] = value & 0xff;
2889 valbytes[1] = (value >> 8) & 0xff;
2890 valbytes[2] = (value >> 16) & 0xff;
2891 valbytes[3] = (value >> 24) & 0xff;
2893 floatformat_to_double
2894 (& floatformat_ieee_single_little, valbytes,
2897 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
2901 func (stream, "#%ld\t; 0x%.8lx",
2902 (long) (((value & 0x80000000L) != 0)
2903 ? value | ~0xffffffffL : value),
2908 func (stream, "#0x%.8lx%.8lx", hival, value);
2919 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
2920 int num = (given >> 8) & 0x3;
2923 func (stream, "{d%d}", regno);
2924 else if (num + regno >= 32)
2925 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
2927 func (stream, "{d%d-d%d}", regno, regno + num);
2932 case '0': case '1': case '2': case '3': case '4':
2933 case '5': case '6': case '7': case '8': case '9':
2936 unsigned long value;
2938 c = arm_decode_bitfield (c, given, &value, &width);
2943 func (stream, "%s", arm_regnames[value]);
2946 func (stream, "%ld", value);
2947 value_in_comment = value;
2950 func (stream, "%ld", (1ul << width) - value);
2956 /* Various width encodings. */
2958 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
2963 if (*c >= '0' && *c <= '9')
2965 else if (*c >= 'a' && *c <= 'f')
2966 limit = *c - 'a' + 10;
2972 if (value < low || value > high)
2973 func (stream, "<illegal width %d>", base << value);
2975 func (stream, "%d", base << value);
2979 if (given & (1 << 6))
2983 func (stream, "d%ld", value);
2988 func (stream, "<illegal reg q%ld.5>", value >> 1);
2990 func (stream, "q%ld", value >> 1);
2996 func (stream, "%c", *c);
3000 if (value == ((1ul << width) - 1))
3001 func (stream, "%c", *c);
3004 func (stream, "%c", c[(1 << width) - (int) value]);
3018 func (stream, "%c", *c);
3021 if (value_in_comment > 32 || value_in_comment < -16)
3022 func (stream, "\t; 0x%lx", value_in_comment);
3024 if (is_unpredictable)
3025 func (stream, UNPREDICTABLE_INSTRUCTION);
3033 /* Return the name of a v7A special register. */
3036 banked_regname (unsigned reg)
3040 case 15: return "CPSR";
3041 case 32: return "R8_usr";
3042 case 33: return "R9_usr";
3043 case 34: return "R10_usr";
3044 case 35: return "R11_usr";
3045 case 36: return "R12_usr";
3046 case 37: return "SP_usr";
3047 case 38: return "LR_usr";
3048 case 40: return "R8_fiq";
3049 case 41: return "R9_fiq";
3050 case 42: return "R10_fiq";
3051 case 43: return "R11_fiq";
3052 case 44: return "R12_fiq";
3053 case 45: return "SP_fiq";
3054 case 46: return "LR_fiq";
3055 case 48: return "LR_irq";
3056 case 49: return "SP_irq";
3057 case 50: return "LR_svc";
3058 case 51: return "SP_svc";
3059 case 52: return "LR_abt";
3060 case 53: return "SP_abt";
3061 case 54: return "LR_und";
3062 case 55: return "SP_und";
3063 case 60: return "LR_mon";
3064 case 61: return "SP_mon";
3065 case 62: return "ELR_hyp";
3066 case 63: return "SP_hyp";
3067 case 79: return "SPSR";
3068 case 110: return "SPSR_fiq";
3069 case 112: return "SPSR_irq";
3070 case 114: return "SPSR_svc";
3071 case 116: return "SPSR_abt";
3072 case 118: return "SPSR_und";
3073 case 124: return "SPSR_mon";
3074 case 126: return "SPSR_hyp";
3075 default: return NULL;
3079 /* Return the name of the DMB/DSB option. */
3081 data_barrier_option (unsigned option)
3083 switch (option & 0xf)
3085 case 0xf: return "sy";
3086 case 0xe: return "st";
3087 case 0xd: return "ld";
3088 case 0xb: return "ish";
3089 case 0xa: return "ishst";
3090 case 0x9: return "ishld";
3091 case 0x7: return "un";
3092 case 0x6: return "unst";
3093 case 0x5: return "nshld";
3094 case 0x3: return "osh";
3095 case 0x2: return "oshst";
3096 case 0x1: return "oshld";
3097 default: return NULL;
3101 /* Print one ARM instruction from PC on INFO->STREAM. */
3104 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
3106 const struct opcode32 *insn;
3107 void *stream = info->stream;
3108 fprintf_ftype func = info->fprintf_func;
3109 struct arm_private_data *private_data = info->private_data;
3111 if (print_insn_coprocessor (pc, info, given, FALSE))
3114 if (print_insn_neon (info, given, FALSE))
3117 for (insn = arm_opcodes; insn->assembler; insn++)
3119 if ((given & insn->mask) != insn->value)
3122 if ((insn->arch & private_data->features.core) == 0)
3125 /* Special case: an instruction with all bits set in the condition field
3126 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
3127 or by the catchall at the end of the table. */
3128 if ((given & 0xF0000000) != 0xF0000000
3129 || (insn->mask & 0xF0000000) == 0xF0000000
3130 || (insn->mask == 0 && insn->value == 0))
3132 unsigned long u_reg = 16;
3133 unsigned long U_reg = 16;
3134 bfd_boolean is_unpredictable = FALSE;
3135 signed long value_in_comment = 0;
3138 for (c = insn->assembler; *c; c++)
3142 bfd_boolean allow_unpredictable = FALSE;
3147 func (stream, "%%");
3151 value_in_comment = print_arm_address (pc, info, given);
3155 /* Set P address bit and use normal address
3156 printing routine. */
3157 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
3161 allow_unpredictable = TRUE;
3163 if ((given & 0x004f0000) == 0x004f0000)
3165 /* PC relative with immediate offset. */
3166 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
3170 /* Elide positive zero offset. */
3171 if (offset || NEGATIVE_BIT_SET)
3172 func (stream, "[pc, #%s%d]\t; ",
3173 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3175 func (stream, "[pc]\t; ");
3176 if (NEGATIVE_BIT_SET)
3178 info->print_address_func (offset + pc + 8, info);
3182 /* Always show the offset. */
3183 func (stream, "[pc], #%s%d",
3184 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3185 if (! allow_unpredictable)
3186 is_unpredictable = TRUE;
3191 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
3193 func (stream, "[%s",
3194 arm_regnames[(given >> 16) & 0xf]);
3198 if (IMMEDIATE_BIT_SET)
3200 /* Elide offset for non-writeback
3202 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
3204 func (stream, ", #%s%d",
3205 NEGATIVE_BIT_SET ? "-" : "", offset);
3207 if (NEGATIVE_BIT_SET)
3210 value_in_comment = offset;
3214 /* Register Offset or Register Pre-Indexed. */
3215 func (stream, ", %s%s",
3216 NEGATIVE_BIT_SET ? "-" : "",
3217 arm_regnames[given & 0xf]);
3219 /* Writing back to the register that is the source/
3220 destination of the load/store is unpredictable. */
3221 if (! allow_unpredictable
3222 && WRITEBACK_BIT_SET
3223 && ((given & 0xf) == ((given >> 12) & 0xf)))
3224 is_unpredictable = TRUE;
3227 func (stream, "]%s",
3228 WRITEBACK_BIT_SET ? "!" : "");
3232 if (IMMEDIATE_BIT_SET)
3234 /* Immediate Post-indexed. */
3235 /* PR 10924: Offset must be printed, even if it is zero. */
3236 func (stream, "], #%s%d",
3237 NEGATIVE_BIT_SET ? "-" : "", offset);
3238 if (NEGATIVE_BIT_SET)
3240 value_in_comment = offset;
3244 /* Register Post-indexed. */
3245 func (stream, "], %s%s",
3246 NEGATIVE_BIT_SET ? "-" : "",
3247 arm_regnames[given & 0xf]);
3249 /* Writing back to the register that is the source/
3250 destination of the load/store is unpredictable. */
3251 if (! allow_unpredictable
3252 && (given & 0xf) == ((given >> 12) & 0xf))
3253 is_unpredictable = TRUE;
3256 if (! allow_unpredictable)
3258 /* Writeback is automatically implied by post- addressing.
3259 Setting the W bit is unnecessary and ARM specify it as
3260 being unpredictable. */
3261 if (WRITEBACK_BIT_SET
3262 /* Specifying the PC register as the post-indexed
3263 registers is also unpredictable. */
3264 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
3265 is_unpredictable = TRUE;
3273 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
3274 info->print_address_func (disp * 4 + pc + 8, info);
3279 if (((given >> 28) & 0xf) != 0xe)
3281 arm_conditional [(given >> 28) & 0xf]);
3290 for (reg = 0; reg < 16; reg++)
3291 if ((given & (1 << reg)) != 0)
3294 func (stream, ", ");
3296 func (stream, "%s", arm_regnames[reg]);
3300 is_unpredictable = TRUE;
3305 arm_decode_shift (given, func, stream, FALSE);
3309 if ((given & 0x02000000) != 0)
3311 unsigned int rotate = (given & 0xf00) >> 7;
3312 unsigned int immed = (given & 0xff);
3315 a = (((immed << (32 - rotate))
3316 | (immed >> rotate)) & 0xffffffff);
3317 /* If there is another encoding with smaller rotate,
3318 the rotate should be specified directly. */
3319 for (i = 0; i < 32; i += 2)
3320 if ((a << i | a >> (32 - i)) <= 0xff)
3324 func (stream, "#%d, %d", immed, rotate);
3326 func (stream, "#%d", a);
3327 value_in_comment = a;
3330 arm_decode_shift (given, func, stream, TRUE);
3334 if ((given & 0x0000f000) == 0x0000f000)
3336 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
3337 mechanism for setting PSR flag bits. They are
3338 obsolete in V6 onwards. */
3339 if ((private_data->features.core & ARM_EXT_V6) == 0)
3345 if ((given & 0x01200000) == 0x00200000)
3351 int offset = given & 0xff;
3353 value_in_comment = offset * 4;
3354 if (NEGATIVE_BIT_SET)
3355 value_in_comment = - value_in_comment;
3357 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3362 func (stream, ", #%d]%s",
3363 (int) value_in_comment,
3364 WRITEBACK_BIT_SET ? "!" : "");
3372 if (WRITEBACK_BIT_SET)
3375 func (stream, ", #%d", (int) value_in_comment);
3379 func (stream, ", {%d}", (int) offset);
3380 value_in_comment = offset;
3387 /* Print ARM V5 BLX(1) address: pc+25 bits. */
3392 if (! NEGATIVE_BIT_SET)
3393 /* Is signed, hi bits should be ones. */
3394 offset = (-1) ^ 0x00ffffff;
3396 /* Offset is (SignExtend(offset field)<<2). */
3397 offset += given & 0x00ffffff;
3399 address = offset + pc + 8;
3401 if (given & 0x01000000)
3402 /* H bit allows addressing to 2-byte boundaries. */
3405 info->print_address_func (address, info);
3410 if ((given & 0x02000200) == 0x200)
3413 unsigned sysm = (given & 0x004f0000) >> 16;
3415 sysm |= (given & 0x300) >> 4;
3416 name = banked_regname (sysm);
3419 func (stream, "%s", name);
3421 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
3425 func (stream, "%cPSR_",
3426 (given & 0x00400000) ? 'S' : 'C');
3427 if (given & 0x80000)
3429 if (given & 0x40000)
3431 if (given & 0x20000)
3433 if (given & 0x10000)
3439 if ((given & 0xf0) == 0x60)
3441 switch (given & 0xf)
3443 case 0xf: func (stream, "sy"); break;
3445 func (stream, "#%d", (int) given & 0xf);
3451 const char * opt = data_barrier_option (given & 0xf);
3453 func (stream, "%s", opt);
3455 func (stream, "#%d", (int) given & 0xf);
3459 case '0': case '1': case '2': case '3': case '4':
3460 case '5': case '6': case '7': case '8': case '9':
3463 unsigned long value;
3465 c = arm_decode_bitfield (c, given, &value, &width);
3471 is_unpredictable = TRUE;
3475 /* We want register + 1 when decoding T. */
3481 /* Eat the 'u' character. */
3485 is_unpredictable = TRUE;
3490 /* Eat the 'U' character. */
3494 is_unpredictable = TRUE;
3497 func (stream, "%s", arm_regnames[value]);
3500 func (stream, "%ld", value);
3501 value_in_comment = value;
3504 func (stream, "%ld", value * 8);
3505 value_in_comment = value * 8;
3508 func (stream, "%ld", value + 1);
3509 value_in_comment = value + 1;
3512 func (stream, "0x%08lx", value);
3514 /* Some SWI instructions have special
3516 if ((given & 0x0fffffff) == 0x0FF00000)
3517 func (stream, "\t; IMB");
3518 else if ((given & 0x0fffffff) == 0x0FF00001)
3519 func (stream, "\t; IMBRange");
3522 func (stream, "%01lx", value & 0xf);
3523 value_in_comment = value;
3528 func (stream, "%c", *c);
3532 if (value == ((1ul << width) - 1))
3533 func (stream, "%c", *c);
3536 func (stream, "%c", c[(1 << width) - (int) value]);
3548 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
3549 func (stream, "%d", imm);
3550 value_in_comment = imm;
3555 /* LSB and WIDTH fields of BFI or BFC. The machine-
3556 language instruction encodes LSB and MSB. */
3558 long msb = (given & 0x001f0000) >> 16;
3559 long lsb = (given & 0x00000f80) >> 7;
3560 long w = msb - lsb + 1;
3563 func (stream, "#%lu, #%lu", lsb, w);
3565 func (stream, "(invalid: %lu:%lu)", lsb, msb);
3570 /* Get the PSR/banked register name. */
3573 unsigned sysm = (given & 0x004f0000) >> 16;
3575 sysm |= (given & 0x300) >> 4;
3576 name = banked_regname (sysm);
3579 func (stream, "%s", name);
3581 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
3586 /* 16-bit unsigned immediate from a MOVT or MOVW
3587 instruction, encoded in bits 0:11 and 15:19. */
3589 long hi = (given & 0x000f0000) >> 4;
3590 long lo = (given & 0x00000fff);
3591 long imm16 = hi | lo;
3593 func (stream, "#%lu", imm16);
3594 value_in_comment = imm16;
3604 func (stream, "%c", *c);
3607 if (value_in_comment > 32 || value_in_comment < -16)
3608 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
3610 if (is_unpredictable)
3611 func (stream, UNPREDICTABLE_INSTRUCTION);
3619 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
3622 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
3624 const struct opcode16 *insn;
3625 void *stream = info->stream;
3626 fprintf_ftype func = info->fprintf_func;
3628 for (insn = thumb_opcodes; insn->assembler; insn++)
3629 if ((given & insn->mask) == insn->value)
3631 signed long value_in_comment = 0;
3632 const char *c = insn->assembler;
3641 func (stream, "%c", *c);
3648 func (stream, "%%");
3653 func (stream, "%s", arm_conditional[IFTHEN_COND]);
3658 func (stream, "%s", arm_conditional[IFTHEN_COND]);
3667 ifthen_next_state = given & 0xff;
3668 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
3669 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
3670 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
3675 if (ifthen_next_state)
3676 func (stream, "\t; unpredictable branch in IT block\n");
3681 func (stream, "\t; unpredictable <IT:%s>",
3682 arm_conditional[IFTHEN_COND]);
3689 reg = (given >> 3) & 0x7;
3690 if (given & (1 << 6))
3693 func (stream, "%s", arm_regnames[reg]);
3702 if (given & (1 << 7))
3705 func (stream, "%s", arm_regnames[reg]);
3710 if (given & (1 << 8))
3714 if (*c == 'O' && (given & (1 << 8)))
3724 /* It would be nice if we could spot
3725 ranges, and generate the rS-rE format: */
3726 for (reg = 0; (reg < 8); reg++)
3727 if ((given & (1 << reg)) != 0)
3730 func (stream, ", ");
3732 func (stream, "%s", arm_regnames[reg]);
3738 func (stream, ", ");
3740 func (stream, "%s", arm_regnames[14] /* "lr" */);
3746 func (stream, ", ");
3747 func (stream, "%s", arm_regnames[15] /* "pc" */);
3755 /* Print writeback indicator for a LDMIA. We are doing a
3756 writeback if the base register is not in the register
3758 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
3763 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
3765 bfd_vma address = (pc + 4
3766 + ((given & 0x00f8) >> 2)
3767 + ((given & 0x0200) >> 3));
3768 info->print_address_func (address, info);
3773 /* Right shift immediate -- bits 6..10; 1-31 print
3774 as themselves, 0 prints as 32. */
3776 long imm = (given & 0x07c0) >> 6;
3779 func (stream, "#%ld", imm);
3783 case '0': case '1': case '2': case '3': case '4':
3784 case '5': case '6': case '7': case '8': case '9':
3786 int bitstart = *c++ - '0';
3789 while (*c >= '0' && *c <= '9')
3790 bitstart = (bitstart * 10) + *c++ - '0';
3799 while (*c >= '0' && *c <= '9')
3800 bitend = (bitend * 10) + *c++ - '0';
3803 reg = given >> bitstart;
3804 reg &= (2 << (bitend - bitstart)) - 1;
3809 func (stream, "%s", arm_regnames[reg]);
3813 func (stream, "%ld", (long) reg);
3814 value_in_comment = reg;
3818 func (stream, "%ld", (long) (reg << 1));
3819 value_in_comment = reg << 1;
3823 func (stream, "%ld", (long) (reg << 2));
3824 value_in_comment = reg << 2;
3828 /* PC-relative address -- the bottom two
3829 bits of the address are dropped
3830 before the calculation. */
3831 info->print_address_func
3832 (((pc + 4) & ~3) + (reg << 2), info);
3833 value_in_comment = 0;
3837 func (stream, "0x%04lx", (long) reg);
3841 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
3842 info->print_address_func (reg * 2 + pc + 4, info);
3843 value_in_comment = 0;
3847 func (stream, "%s", arm_conditional [reg]);
3858 if ((given & (1 << bitstart)) != 0)
3859 func (stream, "%c", *c);
3864 if ((given & (1 << bitstart)) != 0)
3865 func (stream, "%c", *c++);
3867 func (stream, "%c", *++c);
3881 if (value_in_comment > 32 || value_in_comment < -16)
3882 func (stream, "\t; 0x%lx", value_in_comment);
3890 /* Return the name of an V7M special register. */
3893 psr_name (int regno)
3897 case 0: return "APSR";
3898 case 1: return "IAPSR";
3899 case 2: return "EAPSR";
3900 case 3: return "PSR";
3901 case 5: return "IPSR";
3902 case 6: return "EPSR";
3903 case 7: return "IEPSR";
3904 case 8: return "MSP";
3905 case 9: return "PSP";
3906 case 16: return "PRIMASK";
3907 case 17: return "BASEPRI";
3908 case 18: return "BASEPRI_MAX";
3909 case 19: return "FAULTMASK";
3910 case 20: return "CONTROL";
3911 default: return "<unknown>";
3915 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
3918 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
3920 const struct opcode32 *insn;
3921 void *stream = info->stream;
3922 fprintf_ftype func = info->fprintf_func;
3924 if (print_insn_coprocessor (pc, info, given, TRUE))
3927 if (print_insn_neon (info, given, TRUE))
3930 for (insn = thumb32_opcodes; insn->assembler; insn++)
3931 if ((given & insn->mask) == insn->value)
3933 bfd_boolean is_unpredictable = FALSE;
3934 signed long value_in_comment = 0;
3935 const char *c = insn->assembler;
3941 func (stream, "%c", *c);
3948 func (stream, "%%");
3953 func (stream, "%s", arm_conditional[IFTHEN_COND]);
3957 if (ifthen_next_state)
3958 func (stream, "\t; unpredictable branch in IT block\n");
3963 func (stream, "\t; unpredictable <IT:%s>",
3964 arm_conditional[IFTHEN_COND]);
3969 unsigned int imm12 = 0;
3971 imm12 |= (given & 0x000000ffu);
3972 imm12 |= (given & 0x00007000u) >> 4;
3973 imm12 |= (given & 0x04000000u) >> 15;
3974 func (stream, "#%u", imm12);
3975 value_in_comment = imm12;
3981 unsigned int bits = 0, imm, imm8, mod;
3983 bits |= (given & 0x000000ffu);
3984 bits |= (given & 0x00007000u) >> 4;
3985 bits |= (given & 0x04000000u) >> 15;
3986 imm8 = (bits & 0x0ff);
3987 mod = (bits & 0xf00) >> 8;
3990 case 0: imm = imm8; break;
3991 case 1: imm = ((imm8 << 16) | imm8); break;
3992 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
3993 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
3995 mod = (bits & 0xf80) >> 7;
3996 imm8 = (bits & 0x07f) | 0x80;
3997 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
3999 func (stream, "#%u", imm);
4000 value_in_comment = imm;
4006 unsigned int imm = 0;
4008 imm |= (given & 0x000000ffu);
4009 imm |= (given & 0x00007000u) >> 4;
4010 imm |= (given & 0x04000000u) >> 15;
4011 imm |= (given & 0x000f0000u) >> 4;
4012 func (stream, "#%u", imm);
4013 value_in_comment = imm;
4019 unsigned int imm = 0;
4021 imm |= (given & 0x000f0000u) >> 16;
4022 imm |= (given & 0x00000ff0u) >> 0;
4023 imm |= (given & 0x0000000fu) << 12;
4024 func (stream, "#%u", imm);
4025 value_in_comment = imm;
4031 unsigned int imm = 0;
4033 imm |= (given & 0x00000fffu);
4034 imm |= (given & 0x000f0000u) >> 4;
4035 func (stream, "#%u", imm);
4036 value_in_comment = imm;
4042 unsigned int reg = (given & 0x0000000fu);
4043 unsigned int stp = (given & 0x00000030u) >> 4;
4044 unsigned int imm = 0;
4045 imm |= (given & 0x000000c0u) >> 6;
4046 imm |= (given & 0x00007000u) >> 10;
4048 func (stream, "%s", arm_regnames[reg]);
4053 func (stream, ", lsl #%u", imm);
4059 func (stream, ", lsr #%u", imm);
4065 func (stream, ", asr #%u", imm);
4070 func (stream, ", rrx");
4072 func (stream, ", ror #%u", imm);
4079 unsigned int Rn = (given & 0x000f0000) >> 16;
4080 unsigned int U = ! NEGATIVE_BIT_SET;
4081 unsigned int op = (given & 0x00000f00) >> 8;
4082 unsigned int i12 = (given & 0x00000fff);
4083 unsigned int i8 = (given & 0x000000ff);
4084 bfd_boolean writeback = FALSE, postind = FALSE;
4087 func (stream, "[%s", arm_regnames[Rn]);
4088 if (U) /* 12-bit positive immediate offset. */
4092 value_in_comment = offset;
4094 else if (Rn == 15) /* 12-bit negative immediate offset. */
4095 offset = - (int) i12;
4096 else if (op == 0x0) /* Shifted register offset. */
4098 unsigned int Rm = (i8 & 0x0f);
4099 unsigned int sh = (i8 & 0x30) >> 4;
4101 func (stream, ", %s", arm_regnames[Rm]);
4103 func (stream, ", lsl #%u", sh);
4109 case 0xE: /* 8-bit positive immediate offset. */
4113 case 0xC: /* 8-bit negative immediate offset. */
4117 case 0xF: /* 8-bit + preindex with wb. */
4122 case 0xD: /* 8-bit - preindex with wb. */
4127 case 0xB: /* 8-bit + postindex. */
4132 case 0x9: /* 8-bit - postindex. */
4138 func (stream, ", <undefined>]");
4143 func (stream, "], #%d", (int) offset);
4147 func (stream, ", #%d", (int) offset);
4148 func (stream, writeback ? "]!" : "]");
4153 func (stream, "\t; ");
4154 info->print_address_func (((pc + 4) & ~3) + offset, info);
4162 unsigned int U = ! NEGATIVE_BIT_SET;
4163 unsigned int W = WRITEBACK_BIT_SET;
4164 unsigned int Rn = (given & 0x000f0000) >> 16;
4165 unsigned int off = (given & 0x000000ff);
4167 func (stream, "[%s", arm_regnames[Rn]);
4173 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
4174 value_in_comment = off * 4 * U ? 1 : -1;
4182 func (stream, "], ");
4185 func (stream, "#%c%u", U ? '+' : '-', off * 4);
4186 value_in_comment = off * 4 * U ? 1 : -1;
4190 func (stream, "{%u}", off);
4191 value_in_comment = off;
4199 unsigned int Sbit = (given & 0x01000000) >> 24;
4200 unsigned int type = (given & 0x00600000) >> 21;
4204 case 0: func (stream, Sbit ? "sb" : "b"); break;
4205 case 1: func (stream, Sbit ? "sh" : "h"); break;
4208 func (stream, "??");
4211 func (stream, "??");
4223 for (reg = 0; reg < 16; reg++)
4224 if ((given & (1 << reg)) != 0)
4227 func (stream, ", ");
4229 func (stream, "%s", arm_regnames[reg]);
4237 unsigned int msb = (given & 0x0000001f);
4238 unsigned int lsb = 0;
4240 lsb |= (given & 0x000000c0u) >> 6;
4241 lsb |= (given & 0x00007000u) >> 10;
4242 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
4248 unsigned int width = (given & 0x0000001f) + 1;
4249 unsigned int lsb = 0;
4251 lsb |= (given & 0x000000c0u) >> 6;
4252 lsb |= (given & 0x00007000u) >> 10;
4253 func (stream, "#%u, #%u", lsb, width);
4259 unsigned int S = (given & 0x04000000u) >> 26;
4260 unsigned int J1 = (given & 0x00002000u) >> 13;
4261 unsigned int J2 = (given & 0x00000800u) >> 11;
4267 offset |= (given & 0x003f0000) >> 4;
4268 offset |= (given & 0x000007ff) << 1;
4269 offset -= (1 << 20);
4271 info->print_address_func (pc + 4 + offset, info);
4277 unsigned int S = (given & 0x04000000u) >> 26;
4278 unsigned int I1 = (given & 0x00002000u) >> 13;
4279 unsigned int I2 = (given & 0x00000800u) >> 11;
4283 offset |= !(I1 ^ S) << 23;
4284 offset |= !(I2 ^ S) << 22;
4285 offset |= (given & 0x03ff0000u) >> 4;
4286 offset |= (given & 0x000007ffu) << 1;
4287 offset -= (1 << 24);
4290 /* BLX target addresses are always word aligned. */
4291 if ((given & 0x00001000u) == 0)
4294 info->print_address_func (offset, info);
4300 unsigned int shift = 0;
4302 shift |= (given & 0x000000c0u) >> 6;
4303 shift |= (given & 0x00007000u) >> 10;
4304 if (WRITEBACK_BIT_SET)
4305 func (stream, ", asr #%u", shift);
4307 func (stream, ", lsl #%u", shift);
4308 /* else print nothing - lsl #0 */
4314 unsigned int rot = (given & 0x00000030) >> 4;
4317 func (stream, ", ror #%u", rot * 8);
4322 if ((given & 0xf0) == 0x60)
4324 switch (given & 0xf)
4326 case 0xf: func (stream, "sy"); break;
4328 func (stream, "#%d", (int) given & 0xf);
4334 const char * opt = data_barrier_option (given & 0xf);
4336 func (stream, "%s", opt);
4338 func (stream, "#%d", (int) given & 0xf);
4343 if ((given & 0xff) == 0)
4345 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
4355 else if ((given & 0x20) == 0x20)
4358 unsigned sysm = (given & 0xf00) >> 8;
4360 sysm |= (given & 0x30);
4361 sysm |= (given & 0x00100000) >> 14;
4362 name = banked_regname (sysm);
4365 func (stream, "%s", name);
4367 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
4371 func (stream, "%s", psr_name (given & 0xff));
4376 if (((given & 0xff) == 0)
4377 || ((given & 0x20) == 0x20))
4380 unsigned sm = (given & 0xf0000) >> 16;
4382 sm |= (given & 0x30);
4383 sm |= (given & 0x00100000) >> 14;
4384 name = banked_regname (sm);
4387 func (stream, "%s", name);
4389 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
4392 func (stream, "%s", psr_name (given & 0xff));
4395 case '0': case '1': case '2': case '3': case '4':
4396 case '5': case '6': case '7': case '8': case '9':
4401 c = arm_decode_bitfield (c, given, &val, &width);
4406 func (stream, "%lu", val);
4407 value_in_comment = val;
4411 func (stream, "%lu", val * 4);
4412 value_in_comment = val * 4;
4417 is_unpredictable = TRUE;
4420 func (stream, "%s", arm_regnames[val]);
4424 func (stream, "%s", arm_conditional[val]);
4429 if (val == ((1ul << width) - 1))
4430 func (stream, "%c", *c);
4436 func (stream, "%c", *c);
4440 func (stream, "%c", c[(1 << width) - (int) val]);
4445 func (stream, "0x%lx", val & 0xffffffffUL);
4455 /* PR binutils/12534
4456 If we have a PC relative offset in an LDRD or STRD
4457 instructions then display the decoded address. */
4458 if (((given >> 16) & 0xf) == 0xf)
4460 bfd_vma offset = (given & 0xff) * 4;
4462 if ((given & (1 << 23)) == 0)
4464 func (stream, "\t; ");
4465 info->print_address_func ((pc & ~3) + 4 + offset, info);
4474 if (value_in_comment > 32 || value_in_comment < -16)
4475 func (stream, "\t; 0x%lx", value_in_comment);
4477 if (is_unpredictable)
4478 func (stream, UNPREDICTABLE_INSTRUCTION);
4487 /* Print data bytes on INFO->STREAM. */
4490 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
4491 struct disassemble_info *info,
4494 switch (info->bytes_per_chunk)
4497 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
4500 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
4503 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
4510 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
4511 being displayed in symbol relative addresses. */
4514 arm_symbol_is_valid (asymbol * sym,
4515 struct disassemble_info * info ATTRIBUTE_UNUSED)
4522 name = bfd_asymbol_name (sym);
4524 return (name && *name != '$');
4527 /* Parse an individual disassembler option. */
4530 parse_arm_disassembler_option (char *option)
4535 if (CONST_STRNEQ (option, "reg-names-"))
4541 for (i = NUM_ARM_REGNAMES; i--;)
4542 if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
4544 regname_selected = i;
4549 /* XXX - should break 'option' at following delimiter. */
4550 fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
4552 else if (CONST_STRNEQ (option, "force-thumb"))
4554 else if (CONST_STRNEQ (option, "no-force-thumb"))
4557 /* XXX - should break 'option' at following delimiter. */
4558 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
4563 /* Parse the string of disassembler options, spliting it at whitespaces
4564 or commas. (Whitespace separators supported for backwards compatibility). */
4567 parse_disassembler_options (char *options)
4569 if (options == NULL)
4574 parse_arm_disassembler_option (options);
4576 /* Skip forward to next seperator. */
4577 while ((*options) && (! ISSPACE (*options)) && (*options != ','))
4579 /* Skip forward past seperators. */
4580 while (ISSPACE (*options) || (*options == ','))
4585 /* Search back through the insn stream to determine if this instruction is
4586 conditionally executed. */
4589 find_ifthen_state (bfd_vma pc,
4590 struct disassemble_info *info,
4596 /* COUNT is twice the number of instructions seen. It will be odd if we
4597 just crossed an instruction boundary. */
4600 unsigned int seen_it;
4603 ifthen_address = pc;
4610 /* Scan backwards looking for IT instructions, keeping track of where
4611 instruction boundaries are. We don't know if something is actually an
4612 IT instruction until we find a definite instruction boundary. */
4615 if (addr == 0 || info->symbol_at_address_func (addr, info))
4617 /* A symbol must be on an instruction boundary, and will not
4618 be within an IT block. */
4619 if (seen_it && (count & 1))
4625 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
4630 insn = (b[0]) | (b[1] << 8);
4632 insn = (b[1]) | (b[0] << 8);
4635 if ((insn & 0xf800) < 0xe800)
4637 /* Addr + 2 is an instruction boundary. See if this matches
4638 the expected boundary based on the position of the last
4645 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
4647 /* This could be an IT instruction. */
4649 it_count = count >> 1;
4651 if ((insn & 0xf800) >= 0xe800)
4654 count = (count + 2) | 1;
4655 /* IT blocks contain at most 4 instructions. */
4656 if (count >= 8 && !seen_it)
4659 /* We found an IT instruction. */
4660 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
4661 if ((ifthen_state & 0xf) == 0)
4665 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
4669 is_mapping_symbol (struct disassemble_info *info, int n,
4670 enum map_type *map_type)
4674 name = bfd_asymbol_name (info->symtab[n]);
4675 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
4676 && (name[2] == 0 || name[2] == '.'))
4678 *map_type = ((name[1] == 'a') ? MAP_ARM
4679 : (name[1] == 't') ? MAP_THUMB
4687 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
4688 Returns nonzero if *MAP_TYPE was set. */
4691 get_map_sym_type (struct disassemble_info *info,
4693 enum map_type *map_type)
4695 /* If the symbol is in a different section, ignore it. */
4696 if (info->section != NULL && info->section != info->symtab[n]->section)
4699 return is_mapping_symbol (info, n, map_type);
4702 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
4703 Returns nonzero if *MAP_TYPE was set. */
4706 get_sym_code_type (struct disassemble_info *info,
4708 enum map_type *map_type)
4710 elf_symbol_type *es;
4713 /* If the symbol is in a different section, ignore it. */
4714 if (info->section != NULL && info->section != info->symtab[n]->section)
4717 es = *(elf_symbol_type **)(info->symtab + n);
4718 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
4720 /* If the symbol has function type then use that. */
4721 if (type == STT_FUNC || type == STT_GNU_IFUNC)
4723 if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB)
4724 *map_type = MAP_THUMB;
4726 *map_type = MAP_ARM;
4733 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
4734 of the supplied arm_feature_set structure with bitmasks indicating
4735 the support base architectures and coprocessor extensions.
4737 FIXME: This could more efficiently implemented as a constant array,
4738 although it would also be less robust. */
4741 select_arm_features (unsigned long mach,
4742 arm_feature_set * features)
4745 #define ARM_FEATURE(ARCH,CEXT) \
4746 features->core = (ARCH); \
4747 features->coproc = (CEXT) | FPU_FPA; \
4752 case bfd_mach_arm_2: ARM_ARCH_V2;
4753 case bfd_mach_arm_2a: ARM_ARCH_V2S;
4754 case bfd_mach_arm_3: ARM_ARCH_V3;
4755 case bfd_mach_arm_3M: ARM_ARCH_V3M;
4756 case bfd_mach_arm_4: ARM_ARCH_V4;
4757 case bfd_mach_arm_4T: ARM_ARCH_V4T;
4758 case bfd_mach_arm_5: ARM_ARCH_V5;
4759 case bfd_mach_arm_5T: ARM_ARCH_V5T;
4760 case bfd_mach_arm_5TE: ARM_ARCH_V5TE;
4761 case bfd_mach_arm_XScale: ARM_ARCH_XSCALE;
4762 case bfd_mach_arm_ep9312: ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK | FPU_MAVERICK);
4763 case bfd_mach_arm_iWMMXt: ARM_ARCH_IWMMXT;
4764 case bfd_mach_arm_iWMMXt2: ARM_ARCH_IWMMXT2;
4765 /* If the machine type is unknown allow all
4766 architecture types and all extensions. */
4767 case bfd_mach_arm_unknown: ARM_FEATURE (-1UL, -1UL);
4774 /* NOTE: There are no checks in these routines that
4775 the relevant number of data bytes exist. */
4778 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
4783 int is_thumb = FALSE;
4784 int is_data = FALSE;
4786 unsigned int size = 4;
4787 void (*printer) (bfd_vma, struct disassemble_info *, long);
4788 bfd_boolean found = FALSE;
4789 struct arm_private_data *private_data;
4791 if (info->disassembler_options)
4793 parse_disassembler_options (info->disassembler_options);
4795 /* To avoid repeated parsing of these options, we remove them here. */
4796 info->disassembler_options = NULL;
4799 /* PR 10288: Control which instructions will be disassembled. */
4800 if (info->private_data == NULL)
4802 static struct arm_private_data private;
4804 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
4805 /* If the user did not use the -m command line switch then default to
4806 disassembling all types of ARM instruction.
4808 The info->mach value has to be ignored as this will be based on
4809 the default archictecture for the target and/or hints in the notes
4810 section, but it will never be greater than the current largest arm
4811 machine value (iWMMXt2), which is only equivalent to the V5TE
4812 architecture. ARM architectures have advanced beyond the machine
4813 value encoding, and these newer architectures would be ignored if
4814 the machine value was used.
4816 Ie the -m switch is used to restrict which instructions will be
4817 disassembled. If it is necessary to use the -m switch to tell
4818 objdump that an ARM binary is being disassembled, eg because the
4819 input is a raw binary file, but it is also desired to disassemble
4820 all ARM instructions then use "-marm". This will select the
4821 "unknown" arm architecture which is compatible with any ARM
4823 info->mach = bfd_mach_arm_unknown;
4825 /* Compute the architecture bitmask from the machine number.
4826 Note: This assumes that the machine number will not change
4827 during disassembly.... */
4828 select_arm_features (info->mach, & private.features);
4830 private.has_mapping_symbols = -1;
4831 private.last_mapping_sym = -1;
4832 private.last_mapping_addr = 0;
4834 info->private_data = & private;
4837 private_data = info->private_data;
4839 /* Decide if our code is going to be little-endian, despite what the
4840 function argument might say. */
4841 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
4843 /* For ELF, consult the symbol table to determine what kind of code
4845 if (info->symtab_size != 0
4846 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
4851 enum map_type type = MAP_ARM;
4853 /* Start scanning at the start of the function, or wherever
4854 we finished last time. */
4855 /* PR 14006. When the address is 0 we are either at the start of the
4856 very first function, or else the first function in a new, unlinked
4857 executable section (eg because uf -ffunction-sections). Either way
4858 start scanning from the beginning of the symbol table, not where we
4859 left off last time. */
4864 start = info->symtab_pos + 1;
4865 if (start < private_data->last_mapping_sym)
4866 start = private_data->last_mapping_sym;
4870 /* First, look for mapping symbols. */
4871 if (private_data->has_mapping_symbols != 0)
4873 /* Scan up to the location being disassembled. */
4874 for (n = start; n < info->symtab_size; n++)
4876 addr = bfd_asymbol_value (info->symtab[n]);
4879 if (get_map_sym_type (info, n, &type))
4888 /* No mapping symbol found at this address. Look backwards
4889 for a preceding one. */
4890 for (n = start - 1; n >= 0; n--)
4892 if (get_map_sym_type (info, n, &type))
4902 private_data->has_mapping_symbols = 1;
4904 /* No mapping symbols were found. A leading $d may be
4905 omitted for sections which start with data; but for
4906 compatibility with legacy and stripped binaries, only
4907 assume the leading $d if there is at least one mapping
4908 symbol in the file. */
4909 if (!found && private_data->has_mapping_symbols == -1)
4911 /* Look for mapping symbols, in any section. */
4912 for (n = 0; n < info->symtab_size; n++)
4913 if (is_mapping_symbol (info, n, &type))
4915 private_data->has_mapping_symbols = 1;
4918 if (private_data->has_mapping_symbols == -1)
4919 private_data->has_mapping_symbols = 0;
4922 if (!found && private_data->has_mapping_symbols == 1)
4929 /* Next search for function symbols to separate ARM from Thumb
4930 in binaries without mapping symbols. */
4933 /* Scan up to the location being disassembled. */
4934 for (n = start; n < info->symtab_size; n++)
4936 addr = bfd_asymbol_value (info->symtab[n]);
4939 if (get_sym_code_type (info, n, &type))
4948 /* No mapping symbol found at this address. Look backwards
4949 for a preceding one. */
4950 for (n = start - 1; n >= 0; n--)
4952 if (get_sym_code_type (info, n, &type))
4962 private_data->last_mapping_sym = last_sym;
4963 private_data->last_type = type;
4964 is_thumb = (private_data->last_type == MAP_THUMB);
4965 is_data = (private_data->last_type == MAP_DATA);
4967 /* Look a little bit ahead to see if we should print out
4968 two or four bytes of data. If there's a symbol,
4969 mapping or otherwise, after two bytes then don't
4973 size = 4 - (pc & 3);
4974 for (n = last_sym + 1; n < info->symtab_size; n++)
4976 addr = bfd_asymbol_value (info->symtab[n]);
4978 && (info->section == NULL
4979 || info->section == info->symtab[n]->section))
4981 if (addr - pc < size)
4986 /* If the next symbol is after three bytes, we need to
4987 print only part of the data, so that we can use either
4990 size = (pc & 1) ? 1 : 2;
4994 if (info->symbols != NULL)
4996 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
4998 coff_symbol_type * cs;
5000 cs = coffsymbol (*info->symbols);
5001 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
5002 || cs->native->u.syment.n_sclass == C_THUMBSTAT
5003 || cs->native->u.syment.n_sclass == C_THUMBLABEL
5004 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
5005 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
5007 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
5010 /* If no mapping symbol has been found then fall back to the type
5011 of the function symbol. */
5012 elf_symbol_type * es;
5015 es = *(elf_symbol_type **)(info->symbols);
5016 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
5018 is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym)
5019 == ST_BRANCH_TO_THUMB)
5020 || type == STT_ARM_16BIT);
5028 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
5030 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
5032 info->bytes_per_line = 4;
5034 /* PR 10263: Disassemble data if requested to do so by the user. */
5035 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
5039 /* Size was already set above. */
5040 info->bytes_per_chunk = size;
5041 printer = print_insn_data;
5043 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
5046 for (i = size - 1; i >= 0; i--)
5047 given = b[i] | (given << 8);
5049 for (i = 0; i < (int) size; i++)
5050 given = b[i] | (given << 8);
5054 /* In ARM mode endianness is a straightforward issue: the instruction
5055 is four bytes long and is either ordered 0123 or 3210. */
5056 printer = print_insn_arm;
5057 info->bytes_per_chunk = 4;
5060 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
5062 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
5064 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
5068 /* In Thumb mode we have the additional wrinkle of two
5069 instruction lengths. Fortunately, the bits that determine
5070 the length of the current instruction are always to be found
5071 in the first two bytes. */
5072 printer = print_insn_thumb16;
5073 info->bytes_per_chunk = 2;
5076 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
5078 given = (b[0]) | (b[1] << 8);
5080 given = (b[1]) | (b[0] << 8);
5084 /* These bit patterns signal a four-byte Thumb
5086 if ((given & 0xF800) == 0xF800
5087 || (given & 0xF800) == 0xF000
5088 || (given & 0xF800) == 0xE800)
5090 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
5092 given = (b[0]) | (b[1] << 8) | (given << 16);
5094 given = (b[1]) | (b[0] << 8) | (given << 16);
5096 printer = print_insn_thumb32;
5101 if (ifthen_address != pc)
5102 find_ifthen_state (pc, info, little_code);
5106 if ((ifthen_state & 0xf) == 0x8)
5107 ifthen_next_state = 0;
5109 ifthen_next_state = (ifthen_state & 0xe0)
5110 | ((ifthen_state & 0xf) << 1);
5116 info->memory_error_func (status, pc, info);
5119 if (info->flags & INSN_HAS_RELOC)
5120 /* If the instruction has a reloc associated with it, then
5121 the offset field in the instruction will actually be the
5122 addend for the reloc. (We are using REL type relocs).
5123 In such cases, we can ignore the pc when computing
5124 addresses, since the addend is not currently pc-relative. */
5127 printer (pc, info, given);
5131 ifthen_state = ifthen_next_state;
5132 ifthen_address += size;
5138 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
5140 /* Detect BE8-ness and record it in the disassembler info. */
5141 if (info->flavour == bfd_target_elf_flavour
5142 && info->section != NULL
5143 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
5144 info->endian_code = BFD_ENDIAN_LITTLE;
5146 return print_insn (pc, info, FALSE);
5150 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
5152 return print_insn (pc, info, TRUE);
5156 print_arm_disassembler_options (FILE *stream)
5160 fprintf (stream, _("\n\
5161 The following ARM specific disassembler options are supported for use with\n\
5162 the -M switch:\n"));
5164 for (i = NUM_ARM_REGNAMES; i--;)
5165 fprintf (stream, " reg-names-%s %*c%s\n",
5167 (int)(14 - strlen (regnames[i].name)), ' ',
5168 regnames[i].description);
5170 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
5171 fprintf (stream, " no-force-thumb Examine preceding label to determine an insn's type\n\n");