opcodes/arm-dis.c

   1 /* Instruction printing code for the ARM
   2    Copyright (C) 1994-2019 Free Software Foundation, Inc.
   3    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
   4    Modification by James G. Smith (jsmith@cygnus.co.uk)
   5
   6    This file is part of libopcodes.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include "sysdep.h"
  24 #include <assert.h>
  25
  26 #include "disassemble.h"
  27 #include "opcode/arm.h"
  28 #include "opintl.h"
  29 #include "safe-ctype.h"
  30 #include "libiberty.h"
  31 #include "floatformat.h"
  32
  33 /* FIXME: This shouldn't be done here.  */
  34 #include "coff/internal.h"
  35 #include "libcoff.h"
  36 #include "bfd.h"
  37 #include "elf-bfd.h"
  38 #include "elf/internal.h"
  39 #include "elf/arm.h"
  40 #include "mach-o.h"
  41
  42 /* FIXME: Belongs in global header.  */
  43 #ifndef strneq
  44 #define strneq(a,b,n)   (strncmp ((a), (b), (n)) == 0)
  45 #endif
  46
  47 /* Cached mapping symbol state.  */
  48 enum map_type
  49 {
  50   MAP_ARM,
  51   MAP_THUMB,
  52   MAP_DATA
  53 };
  54
  55 struct arm_private_data
  56 {
  57   /* The features to use when disassembling optional instructions.  */
  58   arm_feature_set features;
  59
  60   /* Track the last type (although this doesn't seem to be useful) */
  61   enum map_type last_type;
  62
  63   /* Tracking symbol table information */
  64   int last_mapping_sym;
  65
  66   /* The end range of the current range being disassembled.  */
  67   bfd_vma last_stop_offset;
  68   bfd_vma last_mapping_addr;
  69 };
  70
  71 enum mve_instructions
  72 {
  73   MVE_VPST,
  74   MVE_VPT_FP_T1,
  75   MVE_VPT_FP_T2,
  76   MVE_VPT_VEC_T1,
  77   MVE_VPT_VEC_T2,
  78   MVE_VPT_VEC_T3,
  79   MVE_VPT_VEC_T4,
  80   MVE_VPT_VEC_T5,
  81   MVE_VPT_VEC_T6,
  82   MVE_VCMP_FP_T1,
  83   MVE_VCMP_FP_T2,
  84   MVE_VCMP_VEC_T1,
  85   MVE_VCMP_VEC_T2,
  86   MVE_VCMP_VEC_T3,
  87   MVE_VCMP_VEC_T4,
  88   MVE_VCMP_VEC_T5,
  89   MVE_VCMP_VEC_T6,
  90   MVE_VDUP,
  91   MVE_VEOR,
  92   MVE_VFMAS_FP_SCALAR,
  93   MVE_VFMA_FP_SCALAR,
  94   MVE_VFMA_FP,
  95   MVE_VFMS_FP,
  96   MVE_VHADD_T1,
  97   MVE_VHADD_T2,
  98   MVE_VHSUB_T1,
  99   MVE_VHSUB_T2,
 100   MVE_VRHADD,
 101   MVE_NONE
 102 };
 103
 104 enum mve_unpredictable
 105 {
 106   UNPRED_IT_BLOCK,              /* Unpredictable because mve insn in it block.
 107                                  */
 108   UNPRED_FCA_0_FCB_1,           /* Unpredictable because fcA = 0 and
 109                                    fcB = 1 (vpt).  */
 110   UNPRED_R13,                   /* Unpredictable because r13 (sp) or
 111                                    r15 (sp) used.  */
 112   UNPRED_R15,                   /* Unpredictable because r15 (pc) is used.  */
 113   UNPRED_NONE                   /* No unpredictable behavior.  */
 114 };
 115
 116 enum mve_undefined
 117 {
 118   UNDEF_SIZE_3,                 /* undefined because size == 3.  */
 119   UNDEF_NONE                    /* no undefined behavior.  */
 120 };
 121
 122 struct opcode32
 123 {
 124   arm_feature_set arch;         /* Architecture defining this insn.  */
 125   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
 126   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
 127   const char *  assembler;      /* How to disassemble this insn.  */
 128 };
 129
 130 /* MVE opcodes.  */
 131
 132 struct mopcode32
 133 {
 134   arm_feature_set arch;         /* Architecture defining this insn.  */
 135   enum mve_instructions mve_op;  /* Specific mve instruction for faster
 136                                     decoding.  */
 137   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
 138   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
 139   const char *  assembler;      /* How to disassemble this insn.  */
 140 };
 141
 142 enum isa {
 143   ANY,
 144   T32,
 145   ARM
 146 };
 147
 148
 149 /* Shared (between Arm and Thumb mode) opcode.  */
 150 struct sopcode32
 151 {
 152   enum isa isa;                 /* Execution mode instruction availability.  */
 153   arm_feature_set arch;         /* Architecture defining this insn.  */
 154   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
 155   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
 156   const char *  assembler;      /* How to disassemble this insn.  */
 157 };
 158
 159 struct opcode16
 160 {
 161   arm_feature_set arch;         /* Architecture defining this insn.  */
 162   unsigned short value, mask;   /* Recognise insn if (op & mask) == value.  */
 163   const char *assembler;        /* How to disassemble this insn.  */
 164 };
 165
 166 /* print_insn_coprocessor recognizes the following format control codes:
 167
 168    %%                   %
 169
 170    %c                   print condition code (always bits 28-31 in ARM mode)
 171    %q                   print shifter argument
 172    %u                   print condition code (unconditional in ARM mode,
 173                           UNPREDICTABLE if not AL in Thumb)
 174    %A                   print address for ldc/stc/ldf/stf instruction
 175    %B                   print vstm/vldm register list
 176    %C                   print vscclrm register list
 177    %I                   print cirrus signed shift immediate: bits 0..3|4..6
 178    %J                   print register for VLDR instruction
 179    %K                   print address for VLDR instruction
 180    %F                   print the COUNT field of a LFM/SFM instruction.
 181    %P                   print floating point precision in arithmetic insn
 182    %Q                   print floating point precision in ldf/stf insn
 183    %R                   print floating point rounding mode
 184
 185    %<bitfield>c         print as a condition code (for vsel)
 186    %<bitfield>r         print as an ARM register
 187    %<bitfield>R         as %<>r but r15 is UNPREDICTABLE
 188    %<bitfield>ru        as %<>r but each u register must be unique.
 189    %<bitfield>d         print the bitfield in decimal
 190    %<bitfield>k         print immediate for VFPv3 conversion instruction
 191    %<bitfield>x         print the bitfield in hex
 192    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
 193    %<bitfield>f         print a floating point constant if >7 else a
 194                         floating point register
 195    %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
 196    %<bitfield>g         print as an iWMMXt 64-bit register
 197    %<bitfield>G         print as an iWMMXt general purpose or control register
 198    %<bitfield>D         print as a NEON D register
 199    %<bitfield>Q         print as a NEON Q register
 200    %<bitfield>V         print as a NEON D or Q register
 201    %<bitfield>E         print a quarter-float immediate value
 202
 203    %y<code>             print a single precision VFP reg.
 204                           Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
 205    %z<code>             print a double precision VFP reg
 206                           Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
 207
 208    %<bitfield>'c        print specified char iff bitfield is all ones
 209    %<bitfield>`c        print specified char iff bitfield is all zeroes
 210    %<bitfield>?ab...    select from array of values in big endian order
 211
 212    %L                   print as an iWMMXt N/M width field.
 213    %Z                   print the Immediate of a WSHUFH instruction.
 214    %l                   like 'A' except use byte offsets for 'B' & 'H'
 215                         versions.
 216    %i                   print 5-bit immediate in bits 8,3..0
 217                         (print "32" when 0)
 218    %r                   print register offset address for wldt/wstr instruction.  */
 219
 220 enum opcode_sentinel_enum
 221 {
 222   SENTINEL_IWMMXT_START = 1,
 223   SENTINEL_IWMMXT_END,
 224   SENTINEL_GENERIC_START
 225 } opcode_sentinels;
 226
 227 #define UNDEFINED_INSTRUCTION      "\t\t; <UNDEFINED> instruction: %0-31x"
 228 #define UNKNOWN_INSTRUCTION_32BIT  "\t\t; <UNDEFINED> instruction: %08x"
 229 #define UNKNOWN_INSTRUCTION_16BIT  "\t\t; <UNDEFINED> instruction: %04x"
 230 #define UNPREDICTABLE_INSTRUCTION  "\t; <UNPREDICTABLE>"
 231
 232 /* Common coprocessor opcodes shared between Arm and Thumb-2.  */
 233
 234 static const struct sopcode32 coprocessor_opcodes[] =
 235 {
 236   /* XScale instructions.  */
 237   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 238     0x0e200010, 0x0fff0ff0,
 239     "mia%c\tacc0, %0-3r, %12-15r"},
 240   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 241     0x0e280010, 0x0fff0ff0,
 242     "miaph%c\tacc0, %0-3r, %12-15r"},
 243   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 244     0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
 245   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 246     0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
 247   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 248     0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
 249
 250   /* Intel Wireless MMX technology instructions.  */
 251   {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
 252   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
 253     0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
 254   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 255     0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
 256   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 257     0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
 258   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 259     0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
 260   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 261     0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
 262   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 263     0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
 264   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 265     0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
 266   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 267     0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
 268   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 269     0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
 270   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 271     0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
 272   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 273     0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
 274   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 275     0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
 276   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 277     0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
 278   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 279     0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
 280   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 281     0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
 282   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 283     0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
 284   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 285     0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
 286   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 287     0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 288   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 289     0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
 290   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 291     0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
 292   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 293     0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
 294   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 295     0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
 296   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 297     0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
 298   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 299     0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
 300   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 301     0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
 302   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 303     0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 304   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 305     0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 306   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 307     0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
 308   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 309     0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
 310   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 311     0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
 312   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 313     0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
 314   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 315     0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
 316   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 317     0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
 318   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 319     0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 320   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 321     0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
 322   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 323     0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 324   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 325     0x0e800120, 0x0f800ff0,
 326     "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 327   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 328     0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 329   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 330     0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
 331   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 332     0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
 333   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 334     0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
 335   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 336     0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
 337   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 338     0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
 339   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 340     0x0e8000a0, 0x0f800ff0,
 341     "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 342   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 343     0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 344   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 345     0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 346   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 347     0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
 348   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 349     0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 350   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 351     0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
 352   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 353     0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 354   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 355     0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
 356   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 357     0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
 358   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 359     0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
 360   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 361     0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
 362   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 363     0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 364   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 365     0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 366   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 367     0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
 368   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 369     0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 370   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 371     0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 372   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 373     0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
 374   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 375     0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 376   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 377     0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 378   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 379     0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
 380   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 381     0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
 382   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 383     0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
 384   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 385     0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 386   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 387     0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
 388   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 389     0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 390   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 391     0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
 392   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 393     0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
 394   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 395     0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
 396   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 397     0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
 398   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 399     0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 400   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 401     0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 402   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 403     0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
 404   {ANY, ARM_FEATURE_CORE_LOW (0),
 405     SENTINEL_IWMMXT_END, 0, "" },
 406
 407   /* Floating point coprocessor (FPA) instructions.  */
 408   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 409     0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 410   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 411     0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 412   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 413     0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 414   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 415     0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 416   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 417     0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 418   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 419     0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 420   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 421     0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
 422   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 423     0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
 424   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 425     0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 426   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 427     0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
 428   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 429     0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
 430   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 431     0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
 432   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 433     0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
 434   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 435     0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
 436   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 437     0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
 438   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 439     0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
 440   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 441     0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
 442   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 443     0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
 444   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 445     0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
 446   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 447     0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
 448   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 449     0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
 450   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 451     0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
 452   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 453     0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
 454   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 455     0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
 456   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 457     0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
 458   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 459     0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
 460   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 461     0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
 462   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 463     0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
 464   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 465     0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
 466   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 467     0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
 468   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 469     0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
 470   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 471     0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
 472   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 473     0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
 474   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 475     0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
 476   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 477     0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
 478   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 479     0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
 480   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 481     0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
 482   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 483     0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
 484   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 485     0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
 486   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 487     0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
 488   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 489     0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
 490   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 491     0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
 492   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 493     0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
 494
 495   /* Armv8.1-M Mainline instructions.  */
 496   {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 497     0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
 498   {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 499     0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
 500
 501   /* ARMv8-M Mainline Security Extensions instructions.  */
 502   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 503     0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
 504   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 505     0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
 506
 507   /* Register load/store.  */
 508   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 509     0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
 510   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 511     0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
 512   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 513     0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
 514   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 515     0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
 516   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 517     0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
 518   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 519     0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
 520   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 521     0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
 522   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 523     0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
 524   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 525     0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
 526   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 527     0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
 528   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 529     0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
 530   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 531     0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
 532   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 533     0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
 534   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 535     0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
 536   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 537     0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
 538   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 539     0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
 540   {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
 541     0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
 542   {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
 543     0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
 544
 545   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 546     0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 547   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 548     0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 549   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 550     0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 551   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 552     0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 553
 554   /* Data transfer between ARM and NEON registers.  */
 555   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 556     0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
 557   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 558     0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
 559   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 560     0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
 561   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 562     0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
 563   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 564     0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
 565   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 566     0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
 567   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 568     0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
 569   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 570     0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
 571   /* Half-precision conversion instructions.  */
 572   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 573     0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
 574   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 575     0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
 576   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 577     0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
 578   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 579     0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
 580
 581   /* Floating point coprocessor (VFP) instructions.  */
 582   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 583     0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
 584   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 585     0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
 586   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 587     0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
 588   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 589     0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
 590   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 591     0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
 592   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 593     0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
 594   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 595     0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
 596   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 597     0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
 598   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 599     0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
 600   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 601     0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
 602   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 603     0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
 604   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 605     0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
 606   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 607     0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
 608   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 609     0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
 610   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 611     0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
 612   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 613     0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
 614   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 615     0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
 616   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 617     0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
 618   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 619     0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
 620   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 621     0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
 622   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 623     0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
 624   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 625     0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
 626   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 627     0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
 628   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 629     0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
 630   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 631     0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
 632   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 633     0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
 634   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 635     0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
 636   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 637     0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
 638   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 639     0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
 640   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 641     0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
 642   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 643     0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
 644   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 645     0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
 646   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 647     0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
 648   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 649     0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
 650   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 651     0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
 652   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 653     0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
 654   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 655     0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
 656   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 657     0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
 658   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 659     0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
 660   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 661     0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
 662   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 663     0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
 664   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 665     0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
 666   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 667     0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
 668   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 669     0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
 670   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 671     0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
 672   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 673     0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
 674   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 675     0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
 676   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 677     0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
 678   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 679     0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
 680   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 681     0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
 682   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 683     0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
 684   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 685     0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
 686   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 687     0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
 688   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 689     0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
 690   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 691     0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
 692   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 693     0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
 694   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 695     0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
 696   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 697     0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
 698   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 699     0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
 700   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 701     0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
 702   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 703     0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
 704   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 705     0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
 706   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 707     0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
 708   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 709     0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
 710   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 711     0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
 712   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 713     0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
 714   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 715     0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
 716   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 717     0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
 718   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 719     0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
 720
 721   /* Cirrus coprocessor instructions.  */
 722   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 723     0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 724   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 725     0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 726   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 727     0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 728   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 729     0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 730   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 731     0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 732   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 733     0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 734   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 735     0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 736   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 737     0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 738   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 739     0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 740   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 741     0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 742   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 743     0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 744   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 745     0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 746   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 747     0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 748   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 749     0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 750   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 751     0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 752   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 753     0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 754   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 755     0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
 756   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 757     0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
 758   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 759     0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
 760   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 761     0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
 762   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 763     0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
 764   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 765     0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
 766   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 767     0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
 768   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 769     0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
 770   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 771     0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
 772   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 773     0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
 774   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 775     0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
 776   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 777     0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
 778   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 779     0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
 780   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 781     0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
 782   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 783     0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
 784   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 785     0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
 786   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 787     0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
 788   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 789     0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
 790   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 791     0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
 792   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 793     0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
 794   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 795     0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
 796   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 797     0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
 798   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 799     0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
 800   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 801     0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
 802   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 803     0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
 804   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 805     0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
 806   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 807     0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
 808   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 809     0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
 810   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 811     0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
 812   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 813     0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
 814   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 815     0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
 816   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 817     0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
 818   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 819     0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
 820   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 821     0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
 822   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 823     0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
 824   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 825     0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
 826   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 827     0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
 828   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 829     0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
 830   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 831     0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
 832   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 833     0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
 834   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 835     0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
 836   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 837     0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
 838   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 839     0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
 840   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 841     0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
 842   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 843     0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
 844   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 845     0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
 846   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 847     0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 848   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 849     0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 850   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 851     0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 852   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 853     0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 854   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 855     0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 856   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 857     0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 858   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 859     0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
 860   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 861     0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
 862   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 863     0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
 864   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 865     0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
 866   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 867     0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 868   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 869     0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 870   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 871     0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 872   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 873     0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 874   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 875     0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 876   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 877     0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 878   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 879     0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 880   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 881     0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 882   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 883     0x0e000600, 0x0ff00f10,
 884     "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 885   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 886     0x0e100600, 0x0ff00f10,
 887     "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 888   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 889     0x0e200600, 0x0ff00f10,
 890     "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 891   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 892     0x0e300600, 0x0ff00f10,
 893     "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 894
 895   /* VFP Fused multiply add instructions.  */
 896   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 897     0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
 898   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 899     0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
 900   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 901     0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
 902   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 903     0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
 904   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 905     0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
 906   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 907     0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
 908   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 909     0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
 910   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 911     0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
 912
 913   /* FP v5.  */
 914   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 915     0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
 916   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 917     0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
 918   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 919     0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
 920   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 921     0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
 922   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 923     0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
 924   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 925     0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
 926   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 927     0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
 928   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 929     0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
 930   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 931     0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
 932   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 933     0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
 934   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 935     0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
 936   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 937     0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
 938
 939   /* Generic coprocessor instructions.  */
 940   {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
 941   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
 942     0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
 943   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
 944     0x0c500000, 0x0ff00000,
 945     "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 946   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 947     0x0e000000, 0x0f000010,
 948     "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 949   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 950     0x0e10f010, 0x0f10f010,
 951     "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
 952   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 953     0x0e100010, 0x0f100010,
 954     "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 955   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 956     0x0e000010, 0x0f100010,
 957     "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 958   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 959     0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
 960   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 961     0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
 962
 963   /* V6 coprocessor instructions.  */
 964   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
 965     0xfc500000, 0xfff00000,
 966     "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 967   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
 968     0xfc400000, 0xfff00000,
 969     "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
 970
 971   /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8.  */
 972   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 973     0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
 974   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 975     0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
 976   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 977     0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
 978   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 979     0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
 980   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 981     0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
 982   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 983     0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
 984   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 985     0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
 986   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 987     0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
 988   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 989     0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
 990   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 991     0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
 992
 993   /* Dot Product instructions in the space of coprocessor 13.  */
 994   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
 995     0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
 996   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
 997     0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
 998
 999   /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8.  */
1000   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1001     0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1002   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1003     0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1004   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1005     0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1006   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1007     0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1008   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1009     0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1010   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1011     0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1012   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1013     0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1014   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1015     0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1016
1017   /* V5 coprocessor instructions.  */
1018   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1019     0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1020   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1021     0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1022   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1023     0xfe000000, 0xff000010,
1024     "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1025   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1026     0xfe000010, 0xff100010,
1027     "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1028   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1029     0xfe100010, 0xff100010,
1030     "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1031
1032   /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1033      cp_num: bit <11:8> == 0b1001.
1034      cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE.  */
1035   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1036     0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1037   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1038     0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1039   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1040     0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1041   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1042     0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1043   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1044     0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1045   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1046     0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1047   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1048     0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1049   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1050     0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1051   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1052     0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1053   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1054     0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1055   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1056     0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1057   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1058     0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1059   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1060     0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1061   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1062     0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1063   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1064     0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1065   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1066     0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1067   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1068     0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1069   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1070     0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1071   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1072     0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1073   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1074     0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1075   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1076     0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1077   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1078     0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1079   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1080     0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1081   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1082     0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1083   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1084     0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1085   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1086     0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1087   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1088     0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1089   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1090     0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1091   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1092     0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1093   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1094     0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1095   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1096     0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1097   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1098     0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1099   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1100     0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1101   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1102     0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1103   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1104     0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1105
1106   /* ARMv8.3 javascript conversion instruction.  */
1107   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1108     0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1109
1110   {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1111 };
1112
1113 /* Neon opcode table:  This does not encode the top byte -- that is
1114    checked by the print_insn_neon routine, as it depends on whether we are
1115    doing thumb32 or arm32 disassembly.  */
1116
1117 /* print_insn_neon recognizes the following format control codes:
1118
1119    %%                   %
1120
1121    %c                   print condition code
1122    %u                   print condition code (unconditional in ARM mode,
1123                           UNPREDICTABLE if not AL in Thumb)
1124    %A                   print v{st,ld}[1234] operands
1125    %B                   print v{st,ld}[1234] any one operands
1126    %C                   print v{st,ld}[1234] single->all operands
1127    %D                   print scalar
1128    %E                   print vmov, vmvn, vorr, vbic encoded constant
1129    %F                   print vtbl,vtbx register list
1130
1131    %<bitfield>r         print as an ARM register
1132    %<bitfield>d         print the bitfield in decimal
1133    %<bitfield>e         print the 2^N - bitfield in decimal
1134    %<bitfield>D         print as a NEON D register
1135    %<bitfield>Q         print as a NEON Q register
1136    %<bitfield>R         print as a NEON D or Q register
1137    %<bitfield>Sn        print byte scaled width limited by n
1138    %<bitfield>Tn        print short scaled width limited by n
1139    %<bitfield>Un        print long scaled width limited by n
1140
1141    %<bitfield>'c        print specified char iff bitfield is all ones
1142    %<bitfield>`c        print specified char iff bitfield is all zeroes
1143    %<bitfield>?ab...    select from array of values in big endian order.  */
1144
1145 static const struct opcode32 neon_opcodes[] =
1146 {
1147   /* Extract.  */
1148   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1149     0xf2b00840, 0xffb00850,
1150     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1151   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1152     0xf2b00000, 0xffb00810,
1153     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1154
1155   /* Data transfer between ARM and NEON registers.  */
1156   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1157     0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1158   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1159     0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1160   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1161     0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1162   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1163     0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1164   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1165     0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1166   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1167     0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1168
1169   /* Move data element to all lanes.  */
1170   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1171     0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1172   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1173     0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1174   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1175     0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1176
1177   /* Table lookup.  */
1178   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1179     0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1180   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1181     0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1182
1183   /* Half-precision conversions.  */
1184   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1185     0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1186   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1187     0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1188
1189   /* NEON fused multiply add instructions.  */
1190   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1191     0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1192   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1193     0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1194   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1195     0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1196   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1197     0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1198
1199   /* Two registers, miscellaneous.  */
1200   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1201     0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1202   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1203     0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1204   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1205     0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1206   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1207     0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1208   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1209     0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1210   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1211     0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1212   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1213     0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1214   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1215     0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1216   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1217     0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1218   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1219     0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1220   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1221     0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1222   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1223     0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1224   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1225     0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1226   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1227     0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1228   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1229     0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1230   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1231     0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1232   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1233     0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1234   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1235     0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1236   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1237     0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1238   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1239     0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1240   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1241     0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1242   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1243     0xf3b20300, 0xffb30fd0,
1244     "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1245   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1246     0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1247   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1248     0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1249   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1250     0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1251   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1252     0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1253   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1254     0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1255   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1256     0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1257   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1258     0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1259   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1260     0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1261   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1262     0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1263   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1264     0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1265   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1266     0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1267   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1268     0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1269   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1270     0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1271   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1272     0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1273   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1274     0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1275   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1276     0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1277   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1278     0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1279   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1280     0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1281   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1282     0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1283   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1284     0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1285   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1286     0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1287   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1288     0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1289   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1290     0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1291   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1292     0xf3bb0600, 0xffbf0e10,
1293     "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1294   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1295     0xf3b70600, 0xffbf0e10,
1296     "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1297
1298   /* Three registers of the same length.  */
1299   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1300     0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1301   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1302     0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1303   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1304     0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1305   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1306     0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1307   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1308     0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1309   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1310     0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1311   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1312     0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1313   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1314     0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1315   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1316     0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1317   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1318     0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1319   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1320     0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1321   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1322     0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1323   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1324     0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1325   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1326     0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1327   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1328     0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1329   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1330     0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1331   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1332     0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1333   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1334     0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1335   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1336     0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1337   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1338     0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1339   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1340     0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1341   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1342     0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1343   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1344     0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1345   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1346     0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1347   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1348     0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1349   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1350     0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1351   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1352     0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1353   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1354     0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1355   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1356     0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1357   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1358     0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1359   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1360     0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1361   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1362     0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1363   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1364     0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1365   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1366     0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1367   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1368     0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1369   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1370     0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1371   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1372     0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1373   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1374     0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1375   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1376     0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1377   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1378     0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1379   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1380     0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1381   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1382     0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1383   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1384     0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1385   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1386     0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1387   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1388     0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1389   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1390     0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1391   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1392     0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1393   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1394     0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1395   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1396     0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1397   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1398     0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1399   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1400     0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1401   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1402     0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1403   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1404     0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1405   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1406     0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1407   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1408     0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1409   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1410     0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1411   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1412     0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1413   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1414     0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1415   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1416     0xf2000b00, 0xff800f10,
1417     "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1418   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419     0xf2000b10, 0xff800f10,
1420     "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1421   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1422     0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1423   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424     0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1425   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1426     0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1427   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1428     0xf3000b00, 0xff800f10,
1429     "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1430   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1431     0xf2000000, 0xfe800f10,
1432     "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1433   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1434     0xf2000010, 0xfe800f10,
1435     "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1436   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1437     0xf2000100, 0xfe800f10,
1438     "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1439   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440     0xf2000200, 0xfe800f10,
1441     "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1442   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1443     0xf2000210, 0xfe800f10,
1444     "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1445   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1446     0xf2000300, 0xfe800f10,
1447     "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1448   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1449     0xf2000310, 0xfe800f10,
1450     "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1451   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1452     0xf2000400, 0xfe800f10,
1453     "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1454   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1455     0xf2000410, 0xfe800f10,
1456     "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1457   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1458     0xf2000500, 0xfe800f10,
1459     "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1460   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1461     0xf2000510, 0xfe800f10,
1462     "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1463   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1464     0xf2000600, 0xfe800f10,
1465     "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1466   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1467     0xf2000610, 0xfe800f10,
1468     "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1469   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1470     0xf2000700, 0xfe800f10,
1471     "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1472   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473     0xf2000710, 0xfe800f10,
1474     "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1475   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1476     0xf2000910, 0xfe800f10,
1477     "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1478   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479     0xf2000a00, 0xfe800f10,
1480     "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1481   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1482     0xf2000a10, 0xfe800f10,
1483     "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1484   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1485     0xf3000b10, 0xff800f10,
1486     "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1487   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1488     0xf3000c10, 0xff800f10,
1489     "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1490
1491   /* One register and an immediate value.  */
1492   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1493     0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1494   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1495     0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1496   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1497     0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1498   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1499     0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1500   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1501     0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1502   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1503     0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1504   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1505     0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1506   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1507     0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1508   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1509     0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1510   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1511     0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1512   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1513     0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1514   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1515     0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1516   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1517     0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1518
1519   /* Two registers and a shift amount.  */
1520   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1521     0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1522   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1523     0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1524   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1525     0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1526   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1527     0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1528   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1529     0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1530   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1531     0xf2880950, 0xfeb80fd0,
1532     "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1533   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1534     0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1535   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536     0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1537   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1538     0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1539   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1540     0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1541   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1542     0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1543   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1544     0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1545   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1546     0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1547   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1548     0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1549   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1550     0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1551   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552     0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1553   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1554     0xf2900950, 0xfeb00fd0,
1555     "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1556   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1557     0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1558   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1559     0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1560   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1561     0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1562   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1563     0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1564   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1565     0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1566   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1567     0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1568   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1569     0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1570   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1571     0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1572   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1573     0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1574   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1575     0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1576   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1577     0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1578   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1579     0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1580   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1581     0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1582   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1583     0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1584   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1585     0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1586   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1587     0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1588   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1589     0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1590   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1591     0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1592   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1593     0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1594   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1595     0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1596   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1597     0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1598   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1599     0xf2a00950, 0xfea00fd0,
1600     "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1601   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1602     0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1603   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1604     0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1605   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606     0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1607   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1608     0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1609   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1610     0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1611   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1612     0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1613   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1614     0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1615   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1616     0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1617   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618     0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1619   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1620     0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1621   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1622     0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1623   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1624     0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1625   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626     0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1627   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628     0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1629   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630     0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1631   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1632     0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1633   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1634     0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1635   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1636     0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1637   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638     0xf2a00e10, 0xfea00e90,
1639     "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1640   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1641     0xf2a00c10, 0xfea00e90,
1642     "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1643
1644   /* Three registers of different lengths.  */
1645   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1646     0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1647   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1648     0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1649   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650     0xf2800400, 0xff800f50,
1651     "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1652   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1653     0xf2800600, 0xff800f50,
1654     "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1655   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1656     0xf2800900, 0xff800f50,
1657     "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1658   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1659     0xf2800b00, 0xff800f50,
1660     "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1661   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1662     0xf2800d00, 0xff800f50,
1663     "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1664   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1665     0xf3800400, 0xff800f50,
1666     "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1667   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1668     0xf3800600, 0xff800f50,
1669     "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1670   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1671     0xf2800000, 0xfe800f50,
1672     "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1673   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1674     0xf2800100, 0xfe800f50,
1675     "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1676   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1677     0xf2800200, 0xfe800f50,
1678     "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1679   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1680     0xf2800300, 0xfe800f50,
1681     "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1682   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1683     0xf2800500, 0xfe800f50,
1684     "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1685   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1686     0xf2800700, 0xfe800f50,
1687     "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1688   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1689     0xf2800800, 0xfe800f50,
1690     "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1691   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1692     0xf2800a00, 0xfe800f50,
1693     "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1694   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1695     0xf2800c00, 0xfe800f50,
1696     "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1697
1698   /* Two registers and a scalar.  */
1699   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1700     0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1701   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1702     0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1703   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1704     0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1705   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1706     0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1707   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1708     0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1709   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1710     0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1711   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1712     0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1713   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1714     0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1715   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1716     0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1717   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1718     0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1719   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1720     0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1721   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1722     0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1723   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1724     0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1725   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1726     0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1727   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1728     0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1729   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1730     0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1731   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1732     0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1733   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1734     0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1735   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1736     0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1737   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1738     0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1739   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1740     0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1741   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1742     0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1743   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1744     0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1745   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1746     0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1747   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1748     0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1749   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1750     0xf2800240, 0xfe800f50,
1751     "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1752   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1753     0xf2800640, 0xfe800f50,
1754     "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1755   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1756     0xf2800a40, 0xfe800f50,
1757     "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1758   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1759     0xf2800e40, 0xff800f50,
1760    "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1761   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1762     0xf2800f40, 0xff800f50,
1763    "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1764   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1765     0xf3800e40, 0xff800f50,
1766    "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1767   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1768     0xf3800f40, 0xff800f50,
1769    "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1770   },
1771
1772   /* Element and structure load/store.  */
1773   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1774     0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1775   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1776     0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1777   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1778     0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1779   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1780     0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1781   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1782     0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1783   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1784     0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1785   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1786     0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1787   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1788     0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1789   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1790     0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1791   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1792     0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1793   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794     0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1795   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1796     0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1797   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1798     0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1799   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800     0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1801   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1802     0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1803   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1804     0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1805   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1806     0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1807   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1808     0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1809   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1810     0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1811
1812   {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1813 };
1814
1815 /* mve opcode table.  */
1816
1817 /* print_insn_mve recognizes the following format control codes:
1818
1819    %%                   %
1820
1821    %c                   print condition code
1822    %i                   print MVE predicate(s) for vpt and vpst
1823    %n                   print vector comparison code for predicated instruction
1824    %v                   print vector predicate for instruction in predicated
1825                         block
1826    %<bitfield>r         print as an ARM register
1827    %<bitfield>Q         print as a MVE Q register
1828    %<bitfield>Z         as %<>r but r15 is ZR instead of PC and r13 is
1829                         UNPREDICTABLE
1830    %<bitfield>s         print size for vector predicate & non VMOV instructions
1831 */
1832
1833 static const struct mopcode32 mve_opcodes[] =
1834 {
1835   /* MVE.  */
1836
1837   {ARM_FEATURE_COPROC (FPU_MVE),
1838    MVE_VPST,
1839    0xfe310f4d, 0xffbf1fff,
1840    "vpst%i"
1841   },
1842
1843   /* Floating point VPT T1.  */
1844   {ARM_FEATURE_COPROC (FPU_MVE_FP),
1845    MVE_VPT_FP_T1,
1846    0xee310f00, 0xefb10f50,
1847    "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
1848   /* Floating point VPT T2.  */
1849   {ARM_FEATURE_COPROC (FPU_MVE_FP),
1850    MVE_VPT_FP_T2,
1851    0xee310f40, 0xefb10f50,
1852    "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
1853
1854   /* Vector VPT T1.  */
1855   {ARM_FEATURE_COPROC (FPU_MVE),
1856    MVE_VPT_VEC_T1,
1857    0xfe010f00, 0xff811f51,
1858    "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
1859   /* Vector VPT T2.  */
1860   {ARM_FEATURE_COPROC (FPU_MVE),
1861    MVE_VPT_VEC_T2,
1862    0xfe010f01, 0xff811f51,
1863    "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
1864   /* Vector VPT T3.  */
1865   {ARM_FEATURE_COPROC (FPU_MVE),
1866    MVE_VPT_VEC_T3,
1867    0xfe011f00, 0xff811f50,
1868    "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
1869   /* Vector VPT T4.  */
1870   {ARM_FEATURE_COPROC (FPU_MVE),
1871    MVE_VPT_VEC_T4,
1872    0xfe010f40, 0xff811f70,
1873    "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
1874   /* Vector VPT T5.  */
1875   {ARM_FEATURE_COPROC (FPU_MVE),
1876    MVE_VPT_VEC_T5,
1877    0xfe010f60, 0xff811f70,
1878    "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
1879   /* Vector VPT T6.  */
1880   {ARM_FEATURE_COPROC (FPU_MVE),
1881    MVE_VPT_VEC_T6,
1882    0xfe011f40, 0xff811f50,
1883    "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
1884
1885   /* Vector VCMP floating point T1.  */
1886   {ARM_FEATURE_COPROC (FPU_MVE_FP),
1887    MVE_VCMP_FP_T1,
1888    0xee310f00, 0xeff1ef50,
1889    "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
1890
1891   /* Vector VCMP floating point T2.  */
1892   {ARM_FEATURE_COPROC (FPU_MVE_FP),
1893    MVE_VCMP_FP_T2,
1894    0xee310f40, 0xeff1ef50,
1895    "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
1896
1897   /* Vector VCMP T1.  */
1898   {ARM_FEATURE_COPROC (FPU_MVE),
1899    MVE_VCMP_VEC_T1,
1900    0xfe010f00, 0xffc1ff51,
1901    "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
1902   /* Vector VCMP T2.  */
1903   {ARM_FEATURE_COPROC (FPU_MVE),
1904    MVE_VCMP_VEC_T2,
1905    0xfe010f01, 0xffc1ff51,
1906    "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
1907   /* Vector VCMP T3.  */
1908   {ARM_FEATURE_COPROC (FPU_MVE),
1909    MVE_VCMP_VEC_T3,
1910    0xfe011f00, 0xffc1ff50,
1911    "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
1912   /* Vector VCMP T4.  */
1913   {ARM_FEATURE_COPROC (FPU_MVE),
1914    MVE_VCMP_VEC_T4,
1915    0xfe010f40, 0xffc1ff70,
1916    "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
1917   /* Vector VCMP T5.  */
1918   {ARM_FEATURE_COPROC (FPU_MVE),
1919    MVE_VCMP_VEC_T5,
1920    0xfe010f60, 0xffc1ff70,
1921    "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
1922   /* Vector VCMP T6.  */
1923   {ARM_FEATURE_COPROC (FPU_MVE),
1924    MVE_VCMP_VEC_T6,
1925    0xfe011f40, 0xffc1ff50,
1926    "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
1927
1928   /* Vector VDUP.  */
1929   {ARM_FEATURE_COPROC (FPU_MVE),
1930    MVE_VDUP,
1931    0xeea00b10, 0xffb10f5f,
1932    "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
1933
1934   /* Vector VEOR.  */
1935   {ARM_FEATURE_COPROC (FPU_MVE),
1936    MVE_VEOR,
1937    0xff000150, 0xffd11f51,
1938    "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
1939
1940   /* Vector VFMA, vector * scalar.  */
1941   {ARM_FEATURE_COPROC (FPU_MVE_FP),
1942    MVE_VFMA_FP_SCALAR,
1943    0xee310e40, 0xefb11f70,
1944    "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
1945
1946   /* Vector VFMA floating point.  */
1947   {ARM_FEATURE_COPROC (FPU_MVE_FP),
1948    MVE_VFMA_FP,
1949    0xef000c50, 0xffa11f51,
1950    "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
1951
1952   /* Vector VFMS floating point.  */
1953   {ARM_FEATURE_COPROC (FPU_MVE_FP),
1954    MVE_VFMS_FP,
1955    0xef200c50, 0xffa11f51,
1956    "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
1957
1958   /* Vector VFMAS, vector * scalar.  */
1959   {ARM_FEATURE_COPROC (FPU_MVE_FP),
1960    MVE_VFMAS_FP_SCALAR,
1961    0xee311e40, 0xefb11f70,
1962    "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
1963
1964   /* Vector VHADD T1.  */
1965   {ARM_FEATURE_COPROC (FPU_MVE),
1966    MVE_VHADD_T1,
1967    0xef000040, 0xef811f51,
1968    "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
1969
1970   /* Vector VHADD T2.  */
1971   {ARM_FEATURE_COPROC (FPU_MVE),
1972    MVE_VHADD_T2,
1973    0xee000f40, 0xef811f70,
1974    "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
1975
1976   /* Vector VHSUB T1.  */
1977   {ARM_FEATURE_COPROC (FPU_MVE),
1978    MVE_VHSUB_T1,
1979    0xef000240, 0xef811f51,
1980    "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
1981
1982   /* Vector VHSUB T2.  */
1983   {ARM_FEATURE_COPROC (FPU_MVE),
1984    MVE_VHSUB_T2,
1985    0xee001f40, 0xef811f70,
1986    "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
1987
1988   /* Vector VDUP.  */
1989   {ARM_FEATURE_COPROC (FPU_MVE),
1990    MVE_VDUP,
1991    0xeea00b10, 0xffb10f5f,
1992    "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
1993
1994   /* Vector VRHADD.  */
1995   {ARM_FEATURE_COPROC (FPU_MVE),
1996    MVE_VRHADD,
1997    0xef000140, 0xef811f51,
1998    "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
1999
2000   {ARM_FEATURE_CORE_LOW (0),
2001    MVE_NONE,
2002    0x00000000, 0x00000000, 0}
2003 };
2004
2005 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb.  All three are partially
2006    ordered: they must be searched linearly from the top to obtain a correct
2007    match.  */
2008
2009 /* print_insn_arm recognizes the following format control codes:
2010
2011    %%                   %
2012
2013    %a                   print address for ldr/str instruction
2014    %s                   print address for ldr/str halfword/signextend instruction
2015    %S                   like %s but allow UNPREDICTABLE addressing
2016    %b                   print branch destination
2017    %c                   print condition code (always bits 28-31)
2018    %m                   print register mask for ldm/stm instruction
2019    %o                   print operand2 (immediate or register + shift)
2020    %p                   print 'p' iff bits 12-15 are 15
2021    %t                   print 't' iff bit 21 set and bit 24 clear
2022    %B                   print arm BLX(1) destination
2023    %C                   print the PSR sub type.
2024    %U                   print barrier type.
2025    %P                   print address for pli instruction.
2026
2027    %<bitfield>r         print as an ARM register
2028    %<bitfield>T         print as an ARM register + 1
2029    %<bitfield>R         as %r but r15 is UNPREDICTABLE
2030    %<bitfield>{r|R}u    as %{r|R} but if matches the other %u field then is UNPREDICTABLE
2031    %<bitfield>{r|R}U    as %{r|R} but if matches the other %U field then is UNPREDICTABLE
2032    %<bitfield>d         print the bitfield in decimal
2033    %<bitfield>W         print the bitfield plus one in decimal
2034    %<bitfield>x         print the bitfield in hex
2035    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
2036
2037    %<bitfield>'c        print specified char iff bitfield is all ones
2038    %<bitfield>`c        print specified char iff bitfield is all zeroes
2039    %<bitfield>?ab...    select from array of values in big endian order
2040
2041    %e                   print arm SMI operand (bits 0..7,8..19).
2042    %E                   print the LSB and WIDTH fields of a BFI or BFC instruction.
2043    %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.
2044    %R                   print the SPSR/CPSR or banked register of an MRS.  */
2045
2046 static const struct opcode32 arm_opcodes[] =
2047 {
2048   /* ARM instructions.  */
2049   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2050     0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
2051   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2052     0xe7f000f0, 0xfff000f0, "udf\t#%e"},
2053
2054   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
2055     0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
2056   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
2057     0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
2058   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
2059     0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2060   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
2061     0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
2062   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
2063     0x00800090, 0x0fa000f0,
2064     "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2065   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
2066     0x00a00090, 0x0fa000f0,
2067     "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2068
2069   /* V8.2 RAS extension instructions.  */
2070   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
2071     0xe320f010, 0xffffffff, "esb"},
2072
2073   /* V8 instructions.  */
2074   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2075     0x0320f005, 0x0fffffff, "sevl"},
2076   /* Defined in V8 but is in NOP space so available to all arch.  */
2077   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2078     0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
2079   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
2080     0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
2081   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2082     0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2083   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2084     0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
2085   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2086     0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
2087   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2088     0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
2089   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2090     0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2091   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2092     0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
2093   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2094     0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2095   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2096     0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
2097   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2098     0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
2099   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2100     0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
2101   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2102     0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2103   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2104     0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
2105   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2106     0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2107   /* CRC32 instructions.  */
2108   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2109     0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
2110   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2111     0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
2112   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2113     0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
2114   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2115     0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
2116   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2117     0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
2118   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2119     0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
2120
2121   /* Privileged Access Never extension instructions.  */
2122   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
2123     0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
2124
2125   /* Virtualization Extension instructions.  */
2126   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
2127   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
2128
2129   /* Integer Divide Extension instructions.  */
2130   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
2131     0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
2132   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
2133     0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
2134
2135   /* MP Extension instructions.  */
2136   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
2137
2138   /* Speculation Barriers.  */
2139   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
2140   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
2141   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
2142
2143   /* V7 instructions.  */
2144   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
2145   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
2146   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
2147   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
2148   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
2149   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
2150   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
2151    {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2152     0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
2153
2154   /* ARM V6T2 instructions.  */
2155   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2156     0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
2157   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2158     0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
2159   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2160     0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2161   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2162     0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
2163
2164   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2165     0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
2166   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2167     0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
2168
2169   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2170     0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
2171   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2172     0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
2173   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2174     0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
2175   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2176     0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
2177
2178   /* ARM Security extension instructions.  */
2179   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
2180     0x01600070, 0x0ff000f0, "smc%c\t%e"},
2181
2182   /* ARM V6K instructions.  */
2183   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2184     0xf57ff01f, 0xffffffff, "clrex"},
2185   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2186     0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
2187   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2188     0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
2189   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2190     0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
2191   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2192     0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
2193   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2194     0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
2195   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2196     0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
2197
2198   /* ARMv8.5-A instructions.  */
2199   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
2200
2201   /* ARM V6K NOP hints.  */
2202   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2203     0x0320f001, 0x0fffffff, "yield%c"},
2204   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2205     0x0320f002, 0x0fffffff, "wfe%c"},
2206   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2207     0x0320f003, 0x0fffffff, "wfi%c"},
2208   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2209     0x0320f004, 0x0fffffff, "sev%c"},
2210   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2211     0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
2212
2213   /* ARM V6 instructions.  */
2214   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2215     0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
2216   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2217     0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
2218   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2219     0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
2220   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2221     0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
2222   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2223     0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
2224   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2225     0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
2226   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2227     0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
2228   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2229     0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
2230   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2231     0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
2232   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2233     0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
2234   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2235     0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
2236   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2237     0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
2238   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2239     0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
2240   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2241     0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
2242   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2243     0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
2244   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2245     0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
2246   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2247     0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
2248   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2249     0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
2250   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2251     0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
2252   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2253     0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
2254   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2255     0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
2256   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2257     0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
2258   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2259     0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
2260   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2261     0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
2262   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2263     0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
2264   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2265     0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
2266   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2267     0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
2268   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2269     0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
2270   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2271     0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
2272   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2273     0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
2274   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2275     0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
2276   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2277     0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
2278   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2279     0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
2280   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2281     0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
2282   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2283     0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
2284   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2285     0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
2286   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2287     0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
2288   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2289     0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
2290   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2291     0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
2292   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2293     0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
2294   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2295     0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
2296   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2297     0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2298   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2299     0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2300   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2301     0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2302   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2303     0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2304   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2305     0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2306   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2307     0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2308   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2309     0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2310   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2311     0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2312   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2313     0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
2314   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2315     0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2316   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2317     0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2318   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2319     0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2320   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2321     0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2322   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2323     0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2324   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2325     0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2326   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2327     0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2328   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2329     0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2330   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2331     0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2332   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2333     0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2334   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2335     0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2336   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2337     0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2338   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2339     0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2340   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2341     0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2342   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2343     0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2344   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2345     0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2346   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2347     0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2348   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2349     0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2350   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2351     0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2352   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2353     0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2354   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2355     0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2356   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2357     0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2358   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2359     0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2360   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2361     0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2362   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2363     0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2364   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2365     0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2366   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2367     0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2368   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2369     0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2370   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2371     0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2372   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2373     0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2374   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2375     0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2376   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2377     0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2378   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2379     0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2380   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2381     0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2382   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2383     0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2384   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2385     0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2386   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2387     0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2388   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2389     0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2390   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2391     0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2392   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2393     0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2394   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2395     0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2396   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2397     0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2398   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2399     0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2400   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2401     0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2402   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2403     0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2404   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2405     0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2406   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2407     0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2408   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2409     0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2410   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2411     0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2412   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2413     0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2414   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2415     0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2416   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2417     0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2418   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2419     0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2420   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2421     0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2422   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2423     0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2424   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2425     0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2426   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2427     0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2428   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2429     0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2430   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2431     0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2432   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2433     0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2434   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2435     0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2436   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2437     0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2438   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2439     0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2440   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2441     0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2442   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2443     0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2444   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2445     0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2446   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2447     0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2448   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2449     0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2450   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2451     0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2452   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2453     0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2454   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2455     0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2456   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2457     0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
2458
2459   /* V5J instruction.  */
2460   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2461     0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
2462
2463   /* V5 Instructions.  */
2464   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2465     0xe1200070, 0xfff000f0,
2466     "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2467   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2468     0xfa000000, 0xfe000000, "blx\t%B"},
2469   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2470     0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2471   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2472     0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2473
2474   /* V5E "El Segundo" Instructions.  */
2475   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2476     0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2477   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2478     0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2479   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2480     0xf450f000, 0xfc70f000, "pld\t%a"},
2481   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2482     0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2483   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2484     0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2485   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2486     0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2487   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2488     0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2489
2490   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2491     0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2492   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2493     0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2494
2495   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2496     0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2497   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2498     0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2499   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2500     0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2501   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2502     0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2503
2504   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2505     0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2506   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2507     0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2508   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2509     0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2510   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2511     0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2512
2513   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2514     0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2515   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2516     0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2517
2518   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2519     0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15R, %0-3R, %16-19R"},
2520   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2521     0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2522   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2523     0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15R, %0-3R, %16-19R"},
2524   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2525     0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
2526
2527   /* ARM Instructions.  */
2528   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2529     0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2530
2531   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2532     0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2533   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2534     0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2535   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2536     0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2537   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2538     0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2539   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2540     0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2541   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2542     0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2543
2544   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2545     0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2546   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2547     0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2548   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2549     0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2550   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2551     0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2552
2553   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2554     0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2555   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2556     0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2557   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2558     0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2559   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2560     0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2561
2562   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2563     0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2564   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2565     0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2566   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2567     0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2568
2569   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2570     0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2571   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2572     0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2573   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2574     0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2575
2576   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2577     0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2578   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2579     0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2580   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2581     0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2582
2583   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2584     0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2585   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2586     0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2587   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2588     0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2589
2590   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2591     0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2592   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2593     0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2594   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2595     0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2596
2597   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2598     0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2599   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2600     0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2601   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2602     0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2603
2604   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2605     0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2606   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2607     0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2608   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2609     0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2610
2611   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2612     0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2613   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2614     0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2615   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2616     0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2617
2618   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2619     0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2620   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2621     0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2622   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2623     0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2624
2625   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2626     0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2627   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2628     0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2629   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2630     0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2631
2632   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2633     0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
2634   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2635     0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
2636   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2637     0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
2638
2639   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2640     0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2641   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2642     0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2643   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2644     0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2645
2646   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2647     0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2648   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2649     0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2650   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2651     0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2652
2653   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2654     0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2655   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2656     0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2657   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2658     0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2659
2660   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2661     0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2662   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2663     0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2664   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2665     0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2666   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2667     0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2668   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2669     0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2670   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2671     0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2672   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2673     0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2674
2675   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2676     0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2677   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2678     0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2679   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2680     0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2681
2682   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2683     0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2684   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2685     0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2686   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2687     0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2688
2689   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2690     0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2691   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2692     0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2693
2694   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2695     0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2696
2697   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2698     0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2699   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2700     0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2701
2702   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2703     0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2704   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2705     0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2706   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2707     0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2708   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2709     0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2710   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2711     0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2712   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2713     0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2714   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2715     0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2716   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2717     0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2718   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2719     0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2720   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2721     0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2722   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2723     0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2724   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2725     0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2726   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2727     0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2728   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2729     0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2730   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2731     0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2732   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2733     0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2734   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2735     0x092d0000, 0x0fff0000, "push%c\t%m"},
2736   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2737     0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2738   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2739     0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2740
2741   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2742     0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2743   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2744     0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2745   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2746     0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2747   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2748     0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2749   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2750     0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2751   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2752     0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2753   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2754     0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2755   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2756     0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2757   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2758     0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2759   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2760     0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2761   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2762     0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2763   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2764     0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2765   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2766     0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2767   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2768     0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2769   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2770     0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2771   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2772     0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2773   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2774     0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2775   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2776     0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2777   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2778     0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2779
2780   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2781     0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2782   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2783     0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
2784
2785   /* The rest.  */
2786   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2787     0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
2788   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2789     0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2790   {ARM_FEATURE_CORE_LOW (0),
2791     0x00000000, 0x00000000, 0}
2792 };
2793
2794 /* print_insn_thumb16 recognizes the following format control codes:
2795
2796    %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
2797    %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
2798    %<bitfield>I         print bitfield as a signed decimal
2799                                 (top bit of range being the sign bit)
2800    %N                   print Thumb register mask (with LR)
2801    %O                   print Thumb register mask (with PC)
2802    %M                   print Thumb register mask
2803    %b                   print CZB's 6-bit unsigned branch destination
2804    %s                   print Thumb right-shift immediate (6..10; 0 == 32).
2805    %c                   print the condition code
2806    %C                   print the condition code, or "s" if not conditional
2807    %x                   print warning if conditional an not at end of IT block"
2808    %X                   print "\t; unpredictable <IT:code>" if conditional
2809    %I                   print IT instruction suffix and operands
2810    %W                   print Thumb Writeback indicator for LDMIA
2811    %<bitfield>r         print bitfield as an ARM register
2812    %<bitfield>d         print bitfield as a decimal
2813    %<bitfield>H         print (bitfield * 2) as a decimal
2814    %<bitfield>W         print (bitfield * 4) as a decimal
2815    %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
2816    %<bitfield>B         print Thumb branch destination (signed displacement)
2817    %<bitfield>c         print bitfield as a condition code
2818    %<bitnum>'c          print specified char iff bit is one
2819    %<bitnum>?ab         print a if bit is one else print b.  */
2820
2821 static const struct opcode16 thumb_opcodes[] =
2822 {
2823   /* Thumb instructions.  */
2824
2825   /* ARMv8-M Security Extensions instructions.  */
2826   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
2827   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
2828
2829   /* ARM V8 instructions.  */
2830   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xbf50, 0xffff, "sevl%c"},
2831   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xba80, 0xffc0, "hlt\t%0-5x"},
2832   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),  0xb610, 0xfff7, "setpan\t#%3-3d"},
2833
2834   /* ARM V6K no-argument instructions.  */
2835   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2836   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2837   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2838   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2839   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2840   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
2841
2842   /* ARM V6T2 instructions.  */
2843   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2844     0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2845   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2846     0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
2847   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
2848
2849   /* ARM V6.  */
2850   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2851   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2852   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2853   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2854   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2855   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2856   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2857   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2858   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2859   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2860   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
2861
2862   /* ARM V5 ISA extends Thumb.  */
2863   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2864     0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
2865   /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
2866   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2867     0x4780, 0xff87, "blx%c\t%3-6r%x"},  /* note: 4 bit register number.  */
2868   /* ARM V4T ISA (Thumb v1).  */
2869   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2870     0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
2871   /* Format 4.  */
2872   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2873   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2874   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2875   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2876   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2877   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2878   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2879   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2880   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2881   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2882   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2883   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2884   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2885   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2886   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2887   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
2888   /* format 13 */
2889   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2890   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
2891   /* format 5 */
2892   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2893   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2894   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2895   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
2896   /* format 14 */
2897   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2898   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
2899   /* format 2 */
2900   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2901     0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2902   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2903     0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2904   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2905     0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2906   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2907     0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
2908   /* format 8 */
2909   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2910     0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2911   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2912     0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2913   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2914     0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
2915   /* format 7 */
2916   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2917     0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2918   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2919     0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2920   /* format 1 */
2921   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2922   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2923     0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2924   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2925   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
2926   /* format 3 */
2927   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2928   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2929   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2930   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
2931   /* format 6 */
2932   /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2933   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2934     0x4800, 0xF800,
2935     "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
2936   /* format 9 */
2937   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2938     0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2939   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2940     0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2941   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2942     0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2943   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2944     0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
2945   /* format 10 */
2946   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2947     0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2948   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2949     0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
2950   /* format 11 */
2951   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2952     0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2953   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2954     0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
2955   /* format 12 */
2956   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2957     0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2958   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2959     0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
2960   /* format 15 */
2961   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2962   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
2963   /* format 17 */
2964   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
2965   /* format 16 */
2966   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2967   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2968   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
2969   /* format 18 */
2970   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
2971
2972   /* The E800 .. FFFF range is unconditionally redirected to the
2973      32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2974      are processed via that table.  Thus, we can never encounter a
2975      bare "second half of BL/BLX(1)" instruction here.  */
2976   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),  0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2977   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2978 };
2979
2980 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
2981    We adopt the convention that hw1 is the high 16 bits of .value and
2982    .mask, hw2 the low 16 bits.
2983
2984    print_insn_thumb32 recognizes the following format control codes:
2985
2986        %%               %
2987
2988        %I               print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2989        %M               print a modified 12-bit immediate (same location)
2990        %J               print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2991        %K               print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
2992        %H               print a 16-bit immediate from hw2[3:0],hw1[11:0]
2993        %S               print a possibly-shifted Rm
2994
2995        %L               print address for a ldrd/strd instruction
2996        %a               print the address of a plain load/store
2997        %w               print the width and signedness of a core load/store
2998        %m               print register mask for ldm/stm
2999        %n               print register mask for clrm
3000
3001        %E               print the lsb and width fields of a bfc/bfi instruction
3002        %F               print the lsb and width fields of a sbfx/ubfx instruction
3003        %G               print a fallback offset for Branch Future instructions
3004        %W               print an offset for BF instruction
3005        %Y               print an offset for BFL instruction
3006        %Z               print an offset for BFCSEL instruction
3007        %Q               print an offset for Low Overhead Loop instructions
3008        %P               print an offset for Low Overhead Loop end instructions
3009        %b               print a conditional branch offset
3010        %B               print an unconditional branch offset
3011        %s               print the shift field of an SSAT instruction
3012        %R               print the rotation field of an SXT instruction
3013        %U               print barrier type.
3014        %P               print address for pli instruction.
3015        %c               print the condition code
3016        %x               print warning if conditional an not at end of IT block"
3017        %X               print "\t; unpredictable <IT:code>" if conditional
3018
3019        %<bitfield>d     print bitfield in decimal
3020        %<bitfield>D     print bitfield plus one in decimal
3021        %<bitfield>W     print bitfield*4 in decimal
3022        %<bitfield>r     print bitfield as an ARM register
3023        %<bitfield>R     as %<>r but r15 is UNPREDICTABLE
3024        %<bitfield>S     as %<>r but r13 and r15 is UNPREDICTABLE
3025        %<bitfield>c     print bitfield as a condition code
3026
3027        %<bitfield>'c    print specified char iff bitfield is all ones
3028        %<bitfield>`c    print specified char iff bitfield is all zeroes
3029        %<bitfield>?ab... select from array of values in big endian order
3030
3031    With one exception at the bottom (done because BL and BLX(1) need
3032    to come dead last), this table was machine-sorted first in
3033    decreasing order of number of bits set in the mask, then in
3034    increasing numeric order of mask, then in increasing numeric order
3035    of opcode.  This order is not the clearest for a human reader, but
3036    is guaranteed never to catch a special-case bit pattern with a more
3037    general mask, which is important, because this instruction encoding
3038    makes heavy use of special-case bit patterns.  */
3039 static const struct opcode32 thumb32_opcodes[] =
3040 {
3041   /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
3042      instructions.  */
3043   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3044     0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
3045   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3046     0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
3047   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3048     0xf02fc001, 0xfffff001, "le\t%P"},
3049   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3050     0xf00fc001, 0xfffff001, "le\tlr, %P"},
3051
3052   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3053     0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
3054   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3055     0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
3056   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3057     0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
3058   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3059     0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
3060   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3061     0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
3062
3063   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3064     0xe89f0000, 0xffff2000, "clrm%c\t%n"},
3065
3066   /* ARMv8-M and ARMv8-M Security Extensions instructions.  */
3067   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
3068   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3069     0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
3070   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3071     0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
3072   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3073     0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
3074   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3075     0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
3076
3077   /* ARM V8.2 RAS extension instructions.  */
3078   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
3079     0xf3af8010, 0xffffffff, "esb"},
3080
3081   /* V8 instructions.  */
3082   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3083     0xf3af8005, 0xffffffff, "sevl%c.w"},
3084   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3085     0xf78f8000, 0xfffffffc, "dcps%0-1d"},
3086   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3087     0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
3088   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3089     0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
3090   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3091     0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
3092   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3093     0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
3094   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3095     0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
3096   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3097     0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
3098   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3099     0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
3100   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3101     0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3102   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3103     0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3104   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3105     0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
3106   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3107     0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3108   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3109     0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3110   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3111     0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3112   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3113     0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
3114
3115   /* CRC32 instructions.  */
3116   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3117     0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
3118   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3119     0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
3120   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3121     0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
3122   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3123     0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
3124   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3125     0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
3126   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3127     0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
3128
3129   /* Speculation Barriers.  */
3130   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
3131   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
3132   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
3133
3134   /* V7 instructions.  */
3135   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
3136   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
3137   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
3138   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
3139   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
3140   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
3141   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
3142   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
3143     0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
3144   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
3145     0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
3146
3147   /* Virtualization Extension instructions.  */
3148   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
3149   /* We skip ERET as that is SUBS pc, lr, #0.  */
3150
3151   /* MP Extension instructions.  */
3152   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP),   0xf830f000, 0xff70f000, "pldw%c\t%a"},
3153
3154   /* Security extension instructions.  */
3155   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
3156
3157   /* ARMv8.5-A instructions.  */
3158   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
3159
3160   /* Instructions defined in the basic V6T2 set.  */
3161   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
3162   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
3163   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
3164   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
3165   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
3166   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3167     0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
3168   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
3169
3170   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3171     0xf3bf8f2f, 0xffffffff, "clrex%c"},
3172   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3173     0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
3174   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3175     0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
3176   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3177     0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
3178   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3179     0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
3180   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3181     0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
3182   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3183     0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
3184   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3185     0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
3186   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3187     0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
3188   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3189     0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
3190   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3191     0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
3192   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3193     0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
3194   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3195     0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
3196   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3197     0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
3198   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3199     0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
3200   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3201     0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
3202   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3203     0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
3204   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3205     0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
3206   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3207     0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
3208   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3209     0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
3210   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3211     0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
3212   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3213     0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
3214   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3215     0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
3216   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3217     0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
3218   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3219     0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
3220   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3221     0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
3222   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3223     0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
3224   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3225     0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
3226   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3227     0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
3228   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3229     0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
3230   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3231     0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
3232   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3233     0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
3234   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3235     0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
3236   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3237     0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
3238   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3239     0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
3240   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3241     0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
3242   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3243     0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
3244   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3245     0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
3246   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3247     0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
3248   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3249     0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
3250   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3251     0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
3252   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3253     0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
3254   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3255     0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
3256   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3257     0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
3258   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3259     0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
3260   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3261     0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
3262   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3263     0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
3264   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3265     0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
3266   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3267     0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
3268   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3269     0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
3270   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3271     0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
3272   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3273     0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
3274   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3275     0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
3276   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3277     0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
3278   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3279     0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
3280   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3281     0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
3282   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3283     0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
3284   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3285     0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
3286   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3287     0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
3288   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3289     0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
3290   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3291     0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
3292   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3293     0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
3294   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3295     0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
3296   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3297     0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
3298   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3299     0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
3300   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3301     0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
3302   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3303     0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
3304   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3305     0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
3306   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3307     0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
3308   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3309     0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
3310   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3311     0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
3312   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3313     0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
3314   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3315     0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
3316   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3317     0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
3318   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3319     0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3320   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3321     0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3322   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3323     0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3324   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3325     0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
3326   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3327     0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
3328   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3329     0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
3330   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3331     0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
3332   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3333     0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
3334   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3335     0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3336   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3337     0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
3338   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3339     0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
3340   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3341     0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3342   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3343     0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3344   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3345     0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3346   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3347     0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3348   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3349     0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3350   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3351     0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3352   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3353     0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3354   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3355     0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
3356   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3357     0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
3358   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3359     0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3360   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3361     0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3362   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3363     0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3364   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3365     0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3366   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3367     0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3368   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3369     0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3370   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3371     0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3372   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3373     0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3374   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3375     0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3376   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3377     0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3378   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3379     0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3380   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3381     0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3382   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3383     0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3384   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3385     0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3386   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3387     0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3388   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3389     0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3390   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3391     0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3392   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3393     0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3394   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3395     0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3396   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3397     0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3398   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3399     0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3400   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3401     0xf810f000, 0xff70f000, "pld%c\t%a"},
3402   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3403     0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3404   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3405     0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3406   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3407     0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3408   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3409     0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3410   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3411     0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3412   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3413     0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3414   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3415     0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3416   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3417     0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3418   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3419     0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3420   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3421     0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3422   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3423     0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3424   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3425     0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3426   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3427     0xfb100000, 0xfff000c0,
3428     "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3429   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3430     0xfbc00080, 0xfff000c0,
3431     "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3432   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3433     0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3434   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3435     0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3436   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3437     0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
3438   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3439     0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3440   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3441     0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
3442   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3443     0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3444   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3445     0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
3446   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3447     0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3448   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3449     0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3450   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3451     0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3452   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3453     0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3454   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3455     0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3456   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3457     0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3458   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3459     0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3460   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3461     0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3462   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3463     0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3464   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3465     0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3466   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3467     0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
3468   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3469     0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3470   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3471     0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3472   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3473     0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3474   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3475     0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3476   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3477     0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3478   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3479     0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3480   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3481     0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3482   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3483     0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3484   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3485     0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3486   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3487     0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3488   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3489     0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3490   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3491     0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3492   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3493     0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3494   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3495     0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3496   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3497     0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3498   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3499     0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3500   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3501     0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3502   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3503     0xe9400000, 0xff500000,
3504     "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3505   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3506     0xe9500000, 0xff500000,
3507     "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3508   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3509     0xe8600000, 0xff700000,
3510     "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3511   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3512     0xe8700000, 0xff700000,
3513     "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3514   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3515     0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3516   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3517     0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
3518
3519   /* Filter out Bcc with cond=E or F, which are used for other instructions.  */
3520   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3521     0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3522   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3523     0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3524   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3525     0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3526   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3527     0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
3528
3529   /* These have been 32-bit since the invention of Thumb.  */
3530   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3531      0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3532   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3533      0xf000d000, 0xf800d000, "bl%c\t%B%x"},
3534
3535   /* Fallback.  */
3536   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3537       0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3538   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3539 };
3540
3541 static const char *const arm_conditional[] =
3542 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
3543  "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
3544
3545 static const char *const arm_fp_const[] =
3546 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3547
3548 static const char *const arm_shift[] =
3549 {"lsl", "lsr", "asr", "ror"};
3550
3551 typedef struct
3552 {
3553   const char *name;
3554   const char *description;
3555   const char *reg_names[16];
3556 }
3557 arm_regname;
3558
3559 static const arm_regname regnames[] =
3560 {
3561   { "reg-names-raw", N_("Select raw register names"),
3562     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3563   { "reg-names-gcc", N_("Select register names used by GCC"),
3564     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
3565   { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
3566     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp",  "lr",  "pc" }},
3567   { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
3568   { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
3569   { "reg-names-apcs", N_("Select register names used in the APCS"),
3570     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
3571   { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
3572     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7",  "v8",  "IP",  "SP",  "LR",  "PC" }},
3573   { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3574     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }}
3575 };
3576
3577 static const char *const iwmmxt_wwnames[] =
3578 {"b", "h", "w", "d"};
3579
3580 static const char *const iwmmxt_wwssnames[] =
3581 {"b", "bus", "bc", "bss",
3582  "h", "hus", "hc", "hss",
3583  "w", "wus", "wc", "wss",
3584  "d", "dus", "dc", "dss"
3585 };
3586
3587 static const char *const iwmmxt_regnames[] =
3588 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3589   "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3590 };
3591
3592 static const char *const iwmmxt_cregnames[] =
3593 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3594   "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3595 };
3596
3597 static const char *const vec_condnames[] =
3598 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
3599 };
3600
3601 static const char *const mve_predicatenames[] =
3602 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
3603   "eee", "ee", "eet", "e", "ett", "et", "ete"
3604 };
3605
3606 /* Names for 2-bit size field for mve vector isntructions.  */
3607 static const char *const mve_vec_sizename[] =
3608   { "8", "16", "32", "64"};
3609
3610 /* Indicates whether we are processing a then predicate,
3611    else predicate or none at all.  */
3612 enum vpt_pred_state
3613 {
3614   PRED_NONE,
3615   PRED_THEN,
3616   PRED_ELSE
3617 };
3618
3619 /* Information used to process a vpt block and subsequent instructions.  */
3620 struct vpt_block
3621 {
3622   /* Are we in a vpt block.  */
3623   bfd_boolean in_vpt_block;
3624
3625   /* Next predicate state if in vpt block.  */
3626   enum vpt_pred_state next_pred_state;
3627
3628   /* Mask from vpt/vpst instruction.  */
3629   long predicate_mask;
3630
3631   /* Instruction number in vpt block.  */
3632   long current_insn_num;
3633
3634   /* Number of instructions in vpt block..   */
3635   long num_pred_insn;
3636 };
3637
3638 static struct vpt_block vpt_block_state =
3639 {
3640   FALSE,
3641   PRED_NONE,
3642   0,
3643   0,
3644   0
3645 };
3646
3647 /* Default to GCC register name set.  */
3648 static unsigned int regname_selected = 1;
3649
3650 #define NUM_ARM_OPTIONS   ARRAY_SIZE (regnames)
3651 #define arm_regnames      regnames[regname_selected].reg_names
3652
3653 static bfd_boolean force_thumb = FALSE;
3654
3655 /* Current IT instruction state.  This contains the same state as the IT
3656    bits in the CPSR.  */
3657 static unsigned int ifthen_state;
3658 /* IT state for the next instruction.  */
3659 static unsigned int ifthen_next_state;
3660 /* The address of the insn for which the IT state is valid.  */
3661 static bfd_vma ifthen_address;
3662 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
3663 /* Indicates that the current Conditional state is unconditional or outside
3664    an IT block.  */
3665 #define COND_UNCOND 16
3666
3667 \f
3668 /* Functions.  */
3669 /* Extract the predicate mask for a VPT or VPST instruction.
3670    The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh).  */
3671
3672 static long
3673 mve_extract_pred_mask (long given)
3674 {
3675   return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
3676 }
3677
3678 /* Return the number of instructions in a MVE predicate block.  */
3679 static long
3680 num_instructions_vpt_block (long given)
3681 {
3682   long mask = mve_extract_pred_mask (given);
3683   if (mask == 0)
3684     return 0;
3685
3686   if (mask == 8)
3687     return 1;
3688
3689   if ((mask & 7) == 4)
3690     return 2;
3691
3692   if ((mask & 3) == 2)
3693     return 3;
3694
3695   if ((mask & 1) == 1)
3696     return 4;
3697
3698   return 0;
3699 }
3700
3701 static void
3702 mark_outside_vpt_block (void)
3703 {
3704   vpt_block_state.in_vpt_block = FALSE;
3705   vpt_block_state.next_pred_state = PRED_NONE;
3706   vpt_block_state.predicate_mask = 0;
3707   vpt_block_state.current_insn_num = 0;
3708   vpt_block_state.num_pred_insn = 0;
3709 }
3710
3711 static void
3712 mark_inside_vpt_block (long given)
3713 {
3714   vpt_block_state.in_vpt_block = TRUE;
3715   vpt_block_state.next_pred_state = PRED_THEN;
3716   vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
3717   vpt_block_state.current_insn_num = 0;
3718   vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
3719   assert (vpt_block_state.num_pred_insn >= 1);
3720 }
3721
3722 static enum vpt_pred_state
3723 invert_next_predicate_state (enum vpt_pred_state astate)
3724 {
3725   if (astate == PRED_THEN)
3726     return PRED_ELSE;
3727   else if (astate == PRED_ELSE)
3728     return PRED_THEN;
3729   else
3730     return PRED_NONE;
3731 }
3732
3733 static enum vpt_pred_state
3734 update_next_predicate_state (void)
3735 {
3736   long pred_mask = vpt_block_state.predicate_mask;
3737   long mask_for_insn = 0;
3738
3739   switch (vpt_block_state.current_insn_num)
3740     {
3741     case 1:
3742       mask_for_insn = 8;
3743       break;
3744
3745     case 2:
3746       mask_for_insn = 4;
3747       break;
3748
3749     case 3:
3750       mask_for_insn = 2;
3751       break;
3752
3753     case 4:
3754       return PRED_NONE;
3755     }
3756
3757   if (pred_mask & mask_for_insn)
3758     return invert_next_predicate_state (vpt_block_state.next_pred_state);
3759   else
3760     return vpt_block_state.next_pred_state;
3761 }
3762
3763 static void
3764 update_vpt_block_state (void)
3765 {
3766   vpt_block_state.current_insn_num++;
3767   if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
3768     {
3769       /* No more instructions to process in vpt block.  */
3770       mark_outside_vpt_block ();
3771       return;
3772     }
3773
3774   vpt_block_state.next_pred_state = update_next_predicate_state ();
3775 }
3776
3777 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3778    Returns pointer to following character of the format string and
3779    fills in *VALUEP and *WIDTHP with the extracted value and number of
3780    bits extracted.  WIDTHP can be NULL.  */
3781
3782 static const char *
3783 arm_decode_bitfield (const char *ptr,
3784                      unsigned long insn,
3785                      unsigned long *valuep,
3786                      int *widthp)
3787 {
3788   unsigned long value = 0;
3789   int width = 0;
3790
3791   do
3792     {
3793       int start, end;
3794       int bits;
3795
3796       for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3797         start = start * 10 + *ptr - '0';
3798       if (*ptr == '-')
3799         for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3800           end = end * 10 + *ptr - '0';
3801       else
3802         end = start;
3803       bits = end - start;
3804       if (bits < 0)
3805         abort ();
3806       value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3807       width += bits + 1;
3808     }
3809   while (*ptr++ == ',');
3810   *valuep = value;
3811   if (widthp)
3812     *widthp = width;
3813   return ptr - 1;
3814 }
3815
3816 static void
3817 arm_decode_shift (long given, fprintf_ftype func, void *stream,
3818                   bfd_boolean print_shift)
3819 {
3820   func (stream, "%s", arm_regnames[given & 0xf]);
3821
3822   if ((given & 0xff0) != 0)
3823     {
3824       if ((given & 0x10) == 0)
3825         {
3826           int amount = (given & 0xf80) >> 7;
3827           int shift = (given & 0x60) >> 5;
3828
3829           if (amount == 0)
3830             {
3831               if (shift == 3)
3832                 {
3833                   func (stream, ", rrx");
3834                   return;
3835                 }
3836
3837               amount = 32;
3838             }
3839
3840           if (print_shift)
3841             func (stream, ", %s #%d", arm_shift[shift], amount);
3842           else
3843             func (stream, ", #%d", amount);
3844         }
3845       else if ((given & 0x80) == 0x80)
3846         func (stream, "\t; <illegal shifter operand>");
3847       else if (print_shift)
3848         func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3849               arm_regnames[(given & 0xf00) >> 8]);
3850       else
3851         func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
3852     }
3853 }
3854
3855 /* Return TRUE if the MATCHED_INSN can be inside an IT block.  */
3856
3857 static bfd_boolean
3858 is_mve_okay_in_it (enum mve_instructions matched_insn)
3859 {
3860   return FALSE;
3861 }
3862
3863 static bfd_boolean
3864 is_mve_architecture (struct disassemble_info *info)
3865 {
3866   struct arm_private_data *private_data = info->private_data;
3867   arm_feature_set allowed_arches = private_data->features;
3868
3869   arm_feature_set arm_ext_v8_1m_main
3870     = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
3871
3872   if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
3873       && !ARM_CPU_IS_ANY (allowed_arches))
3874     return TRUE;
3875   else
3876     return FALSE;
3877 }
3878
3879 static bfd_boolean
3880 is_vpt_instruction (long given)
3881 {
3882
3883   /* If mkh:mkl is '0000' then its not a vpt/vpst instruction.  */
3884   if ((given & 0x0040e000) == 0)
3885     return FALSE;
3886
3887   /* VPT floating point T1 variant.  */
3888   if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
3889   /* VPT floating point T2 variant.  */
3890       || ((given & 0xefb10f50) == 0xee310f40)
3891   /* VPT vector T1 variant.  */
3892       || ((given & 0xff811f51) == 0xfe010f00)
3893   /* VPT vector T2 variant.  */
3894       || ((given & 0xff811f51) == 0xfe010f01
3895           && ((given & 0x300000) != 0x300000))
3896   /* VPT vector T3 variant.  */
3897       || ((given & 0xff811f50) == 0xfe011f00)
3898   /* VPT vector T4 variant.  */
3899       || ((given & 0xff811f70) == 0xfe010f40)
3900   /* VPT vector T5 variant.  */
3901       || ((given & 0xff811f70) == 0xfe010f60)
3902   /* VPT vector T6 variant.  */
3903       || ((given & 0xff811f50) == 0xfe011f40)
3904   /* VPST vector T variant.  */
3905       || ((given & 0xffbf1fff) == 0xfe310f4d))
3906     return TRUE;
3907   else
3908     return FALSE;
3909 }
3910
3911 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
3912    and ending bitfield = END.  END must be greater than START.  */
3913
3914 static unsigned long
3915 arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
3916 {
3917   int bits = end - start;
3918
3919   if (bits < 0)
3920     abort ();
3921
3922   return ((given >> start) & ((2ul << bits) - 1));
3923 }
3924
3925 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
3926    START:END and START2:END2.  END/END2 must be greater than
3927    START/START2.  */
3928
3929 static unsigned long
3930 arm_decode_field_multiple (unsigned long given, unsigned int start,
3931                            unsigned int end, unsigned int start2,
3932                            unsigned int end2)
3933 {
3934   int bits = end - start;
3935   int bits2 = end2 - start2;
3936   unsigned long value = 0;
3937   int width = 0;
3938
3939   if (bits2 < 0)
3940     abort ();
3941
3942   value = arm_decode_field (given, start, end);
3943   width += bits + 1;
3944
3945   value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
3946   return value;
3947 }
3948
3949 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
3950    This helps us decode instructions that change mnemonic depending on specific
3951    operand values/encodings.  */
3952
3953 static bfd_boolean
3954 is_mve_encoding_conflict (unsigned long given,
3955                           enum mve_instructions matched_insn)
3956 {
3957   switch (matched_insn)
3958     {
3959     case MVE_VPST:
3960       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
3961         return TRUE;
3962       else
3963         return FALSE;
3964
3965     case MVE_VPT_FP_T1:
3966       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
3967         return TRUE;
3968       if ((arm_decode_field (given, 12, 12) == 0)
3969           && (arm_decode_field (given, 0, 0) == 1))
3970         return TRUE;
3971       return FALSE;
3972
3973     case MVE_VPT_FP_T2:
3974       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
3975         return TRUE;
3976       if (arm_decode_field (given, 0, 3) == 0xd)
3977         return TRUE;
3978       return FALSE;
3979
3980     case MVE_VPT_VEC_T1:
3981     case MVE_VPT_VEC_T2:
3982     case MVE_VPT_VEC_T3:
3983     case MVE_VPT_VEC_T4:
3984     case MVE_VPT_VEC_T5:
3985     case MVE_VPT_VEC_T6:
3986       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
3987         return TRUE;
3988       if (arm_decode_field (given, 20, 21) == 3)
3989         return TRUE;
3990       return FALSE;
3991
3992     case MVE_VCMP_FP_T1:
3993       if ((arm_decode_field (given, 12, 12) == 0)
3994           && (arm_decode_field (given, 0, 0) == 1))
3995         return TRUE;
3996       else
3997         return FALSE;
3998
3999     case MVE_VCMP_FP_T2:
4000       if (arm_decode_field (given, 0, 3) == 0xd)
4001         return TRUE;
4002       else
4003         return FALSE;
4004
4005     case MVE_VHADD_T2:
4006     case MVE_VHSUB_T2:
4007     case MVE_VCMP_VEC_T1:
4008     case MVE_VCMP_VEC_T2:
4009     case MVE_VCMP_VEC_T3:
4010     case MVE_VCMP_VEC_T4:
4011     case MVE_VCMP_VEC_T5:
4012     case MVE_VCMP_VEC_T6:
4013       if (arm_decode_field (given, 20, 21) == 3)
4014         return TRUE;
4015       else
4016         return FALSE;
4017
4018     default:
4019       return FALSE;
4020
4021     }
4022 }
4023
4024 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
4025    Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
4026    this encoding is undefined.  */
4027
4028 static bfd_boolean
4029 is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
4030                   enum mve_undefined *undefined_code)
4031 {
4032   *undefined_code = UNDEF_NONE;
4033
4034   switch (matched_insn)
4035     {
4036     case MVE_VDUP:
4037       if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
4038         {
4039           *undefined_code = UNDEF_SIZE_3;
4040           return TRUE;
4041         }
4042       else
4043         return FALSE;
4044
4045     case MVE_VRHADD:
4046     case MVE_VHADD_T1:
4047     case MVE_VHSUB_T1:
4048       if (arm_decode_field (given, 20, 21) == 3)
4049         {
4050           *undefined_code = UNDEF_SIZE_3;
4051           return TRUE;
4052         }
4053       else
4054         return FALSE;
4055
4056     default:
4057       return FALSE;
4058     }
4059 }
4060
4061 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
4062    Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
4063    why this encoding is unpredictable.  */
4064
4065 static bfd_boolean
4066 is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
4067                       enum mve_unpredictable *unpredictable_code)
4068 {
4069   *unpredictable_code = UNPRED_NONE;
4070
4071   switch (matched_insn)
4072     {
4073     case MVE_VCMP_FP_T2:
4074     case MVE_VPT_FP_T2:
4075       if ((arm_decode_field (given, 12, 12) == 0)
4076           && (arm_decode_field (given, 5, 5) == 1))
4077         {
4078           *unpredictable_code = UNPRED_FCA_0_FCB_1;
4079           return TRUE;
4080         }
4081       else
4082         return FALSE;
4083
4084     case MVE_VPT_VEC_T4:
4085     case MVE_VPT_VEC_T5:
4086     case MVE_VPT_VEC_T6:
4087     case MVE_VCMP_VEC_T4:
4088     case MVE_VCMP_VEC_T5:
4089     case MVE_VCMP_VEC_T6:
4090       if (arm_decode_field (given, 0, 3) == 0xd)
4091         {
4092           *unpredictable_code = UNPRED_R13;
4093           return TRUE;
4094         }
4095       else
4096         return FALSE;
4097
4098     case MVE_VDUP:
4099       {
4100         unsigned long gpr = arm_decode_field (given, 12, 15);
4101         if (gpr == 0xd)
4102           {
4103             *unpredictable_code = UNPRED_R13;
4104             return TRUE;
4105           }
4106         else if (gpr == 0xf)
4107           {
4108             *unpredictable_code = UNPRED_R15;
4109             return TRUE;
4110           }
4111
4112         return FALSE;
4113       }
4114
4115     case MVE_VFMA_FP_SCALAR:
4116     case MVE_VFMAS_FP_SCALAR:
4117     case MVE_VHADD_T2:
4118     case MVE_VHSUB_T2:
4119       {
4120         unsigned long gpr = arm_decode_field (given, 0, 3);
4121         if (gpr == 0xd)
4122           {
4123             *unpredictable_code = UNPRED_R13;
4124             return TRUE;
4125           }
4126         else if (gpr == 0xf)
4127           {
4128             *unpredictable_code = UNPRED_R15;
4129             return TRUE;
4130           }
4131
4132         return FALSE;
4133       }
4134
4135     default:
4136       return FALSE;
4137     }
4138 }
4139
4140 static void
4141 print_mve_undefined (struct disassemble_info *info,
4142                      enum mve_undefined undefined_code)
4143 {
4144   void *stream = info->stream;
4145   fprintf_ftype func = info->fprintf_func;
4146
4147   func (stream, "\t\tundefined instruction: ");
4148
4149   switch (undefined_code)
4150     {
4151     case UNDEF_SIZE_3:
4152       func (stream, "size equals three");
4153       break;
4154
4155     case UNDEF_NONE:
4156       break;
4157     }
4158
4159 }
4160
4161 static void
4162 print_mve_unpredictable (struct disassemble_info *info,
4163                          enum mve_unpredictable unpredict_code)
4164 {
4165   void *stream = info->stream;
4166   fprintf_ftype func = info->fprintf_func;
4167
4168   func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
4169
4170   switch (unpredict_code)
4171     {
4172     case UNPRED_IT_BLOCK:
4173       func (stream, "mve instruction in it block");
4174       break;
4175
4176     case UNPRED_FCA_0_FCB_1:
4177       func (stream, "condition bits, fca = 0 and fcb = 1");
4178       break;
4179
4180     case UNPRED_R13:
4181       func (stream, "use of r13 (sp)");
4182       break;
4183
4184     case UNPRED_R15:
4185       func (stream, "use of r15 (pc)");
4186       break;
4187
4188     case UNPRED_NONE:
4189       break;
4190     }
4191 }
4192
4193 static void
4194 print_instruction_predicate (struct disassemble_info *info)
4195 {
4196   void *stream = info->stream;
4197   fprintf_ftype func = info->fprintf_func;
4198
4199   if (vpt_block_state.next_pred_state == PRED_THEN)
4200     func (stream, "t");
4201   else if (vpt_block_state.next_pred_state == PRED_ELSE)
4202     func (stream, "e");
4203 }
4204
4205 static void
4206 print_mve_size (struct disassemble_info *info,
4207                 unsigned long size,
4208                 enum mve_instructions matched_insn)
4209 {
4210   void *stream = info->stream;
4211   fprintf_ftype func = info->fprintf_func;
4212
4213   switch (matched_insn)
4214     {
4215     case MVE_VCMP_VEC_T1:
4216     case MVE_VCMP_VEC_T2:
4217     case MVE_VCMP_VEC_T3:
4218     case MVE_VCMP_VEC_T4:
4219     case MVE_VCMP_VEC_T5:
4220     case MVE_VCMP_VEC_T6:
4221     case MVE_VHADD_T1:
4222     case MVE_VHADD_T2:
4223     case MVE_VHSUB_T1:
4224     case MVE_VHSUB_T2:
4225     case MVE_VPT_VEC_T1:
4226     case MVE_VPT_VEC_T2:
4227     case MVE_VPT_VEC_T3:
4228     case MVE_VPT_VEC_T4:
4229     case MVE_VPT_VEC_T5:
4230     case MVE_VPT_VEC_T6:
4231     case MVE_VRHADD:
4232       if (size <= 3)
4233         func (stream, "%s", mve_vec_sizename[size]);
4234       else
4235         func (stream, "<undef size>");
4236       break;
4237
4238     case MVE_VCMP_FP_T1:
4239     case MVE_VCMP_FP_T2:
4240     case MVE_VFMA_FP_SCALAR:
4241     case MVE_VFMA_FP:
4242     case MVE_VFMS_FP:
4243     case MVE_VFMAS_FP_SCALAR:
4244     case MVE_VPT_FP_T1:
4245     case MVE_VPT_FP_T2:
4246       if (size == 0)
4247         func (stream, "32");
4248       else if (size == 1)
4249         func (stream, "16");
4250       break;
4251
4252     case MVE_VDUP:
4253       switch (size)
4254         {
4255         case 0:
4256           func (stream, "32");
4257           break;
4258         case 1:
4259           func (stream, "16");
4260           break;
4261         case 2:
4262           func (stream, "8");
4263           break;
4264         default:
4265           break;
4266         }
4267       break;
4268
4269     default:
4270       break;
4271     }
4272 }
4273
4274 static void
4275 print_vec_condition (struct disassemble_info *info, long given,
4276                      enum mve_instructions matched_insn)
4277 {
4278   void *stream = info->stream;
4279   fprintf_ftype func = info->fprintf_func;
4280   long vec_cond = 0;
4281
4282   switch (matched_insn)
4283     {
4284     case MVE_VPT_FP_T1:
4285     case MVE_VCMP_FP_T1:
4286       vec_cond = (((given & 0x1000) >> 10)
4287                   | ((given & 1) << 1)
4288                   | ((given & 0x0080) >> 7));
4289       func (stream, "%s",vec_condnames[vec_cond]);
4290       break;
4291
4292     case MVE_VPT_FP_T2:
4293     case MVE_VCMP_FP_T2:
4294       vec_cond = (((given & 0x1000) >> 10)
4295                   | ((given & 0x0020) >> 4)
4296                   | ((given & 0x0080) >> 7));
4297       func (stream, "%s",vec_condnames[vec_cond]);
4298       break;
4299
4300     case MVE_VPT_VEC_T1:
4301     case MVE_VCMP_VEC_T1:
4302       vec_cond = (given & 0x0080) >> 7;
4303       func (stream, "%s",vec_condnames[vec_cond]);
4304       break;
4305
4306     case MVE_VPT_VEC_T2:
4307     case MVE_VCMP_VEC_T2:
4308       vec_cond = 2 | ((given & 0x0080) >> 7);
4309       func (stream, "%s",vec_condnames[vec_cond]);
4310       break;
4311
4312     case MVE_VPT_VEC_T3:
4313     case MVE_VCMP_VEC_T3:
4314       vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
4315       func (stream, "%s",vec_condnames[vec_cond]);
4316       break;
4317
4318     case MVE_VPT_VEC_T4:
4319     case MVE_VCMP_VEC_T4:
4320       vec_cond = (given & 0x0080) >> 7;
4321       func (stream, "%s",vec_condnames[vec_cond]);
4322       break;
4323
4324     case MVE_VPT_VEC_T5:
4325     case MVE_VCMP_VEC_T5:
4326       vec_cond = 2 | ((given & 0x0080) >> 7);
4327       func (stream, "%s",vec_condnames[vec_cond]);
4328       break;
4329
4330     case MVE_VPT_VEC_T6:
4331     case MVE_VCMP_VEC_T6:
4332       vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
4333       func (stream, "%s",vec_condnames[vec_cond]);
4334       break;
4335
4336     case MVE_NONE:
4337     case MVE_VPST:
4338     default:
4339       break;
4340     }
4341 }
4342
4343 #define W_BIT 21
4344 #define I_BIT 22
4345 #define U_BIT 23
4346 #define P_BIT 24
4347
4348 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
4349 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
4350 #define NEGATIVE_BIT_SET  ((given & (1 << U_BIT)) == 0)
4351 #define PRE_BIT_SET       (given & (1 << P_BIT))
4352
4353
4354 /* Print one coprocessor instruction on INFO->STREAM.
4355    Return TRUE if the instuction matched, FALSE if this is not a
4356    recognised coprocessor instruction.  */
4357
4358 static bfd_boolean
4359 print_insn_coprocessor (bfd_vma pc,
4360                         struct disassemble_info *info,
4361                         long given,
4362                         bfd_boolean thumb)
4363 {
4364   const struct sopcode32 *insn;
4365   void *stream = info->stream;
4366   fprintf_ftype func = info->fprintf_func;
4367   unsigned long mask;
4368   unsigned long value = 0;
4369   int cond;
4370   int cp_num;
4371   struct arm_private_data *private_data = info->private_data;
4372   arm_feature_set allowed_arches = ARM_ARCH_NONE;
4373   arm_feature_set arm_ext_v8_1m_main =
4374     ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
4375
4376   allowed_arches = private_data->features;
4377
4378   for (insn = coprocessor_opcodes; insn->assembler; insn++)
4379     {
4380       unsigned long u_reg = 16;
4381       bfd_boolean is_unpredictable = FALSE;
4382       signed long value_in_comment = 0;
4383       const char *c;
4384
4385       if (ARM_FEATURE_ZERO (insn->arch))
4386         switch (insn->value)
4387           {
4388           case SENTINEL_IWMMXT_START:
4389             if (info->mach != bfd_mach_arm_XScale
4390                 && info->mach != bfd_mach_arm_iWMMXt
4391                 && info->mach != bfd_mach_arm_iWMMXt2)
4392               do
4393                 insn++;
4394               while ((! ARM_FEATURE_ZERO (insn->arch))
4395                      && insn->value != SENTINEL_IWMMXT_END);
4396             continue;
4397
4398           case SENTINEL_IWMMXT_END:
4399             continue;
4400
4401           case SENTINEL_GENERIC_START:
4402             allowed_arches = private_data->features;
4403             continue;
4404
4405           default:
4406             abort ();
4407           }
4408
4409       mask = insn->mask;
4410       value = insn->value;
4411       cp_num = (given >> 8) & 0xf;
4412
4413       if (thumb)
4414         {
4415           /* The high 4 bits are 0xe for Arm conditional instructions, and
4416              0xe for arm unconditional instructions.  The rest of the
4417              encoding is the same.  */
4418           mask |= 0xf0000000;
4419           value |= 0xe0000000;
4420           if (ifthen_state)
4421             cond = IFTHEN_COND;
4422           else
4423             cond = COND_UNCOND;
4424         }
4425       else
4426         {
4427           /* Only match unconditional instuctions against unconditional
4428              patterns.  */
4429           if ((given & 0xf0000000) == 0xf0000000)
4430             {
4431               mask |= 0xf0000000;
4432               cond = COND_UNCOND;
4433             }
4434           else
4435             {
4436               cond = (given >> 28) & 0xf;
4437               if (cond == 0xe)
4438                 cond = COND_UNCOND;
4439             }
4440         }
4441
4442       if ((insn->isa == T32 && !thumb)
4443           || (insn->isa == ARM && thumb))
4444         continue;
4445
4446       if ((given & mask) != value)
4447         continue;
4448
4449       if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
4450         continue;
4451
4452       if (insn->value == 0xfe000010     /* mcr2  */
4453           || insn->value == 0xfe100010  /* mrc2  */
4454           || insn->value == 0xfc100000  /* ldc2  */
4455           || insn->value == 0xfc000000) /* stc2  */
4456         {
4457           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
4458             is_unpredictable = TRUE;
4459
4460           /* Armv8.1-M Mainline FP & MVE instructions.  */
4461           if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
4462               && !ARM_CPU_IS_ANY (allowed_arches)
4463               && (cp_num == 8 || cp_num == 14 || cp_num == 15))
4464             continue;
4465
4466         }
4467       else if (insn->value == 0x0e000000     /* cdp  */
4468                || insn->value == 0xfe000000  /* cdp2  */
4469                || insn->value == 0x0e000010  /* mcr  */
4470                || insn->value == 0x0e100010  /* mrc  */
4471                || insn->value == 0x0c100000  /* ldc  */
4472                || insn->value == 0x0c000000) /* stc  */
4473         {
4474           /* Floating-point instructions.  */
4475           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
4476             continue;
4477
4478           /* Armv8.1-M Mainline FP & MVE instructions.  */
4479           if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
4480               && !ARM_CPU_IS_ANY (allowed_arches)
4481               && (cp_num == 8 || cp_num == 14 || cp_num == 15))
4482             continue;
4483         }
4484
4485       for (c = insn->assembler; *c; c++)
4486         {
4487           if (*c == '%')
4488             {
4489               const char mod = *++c;
4490               switch (mod)
4491                 {
4492                 case '%':
4493                   func (stream, "%%");
4494                   break;
4495
4496                 case 'A':
4497                 case 'K':
4498                   {
4499                     int rn = (given >> 16) & 0xf;
4500                     bfd_vma offset = given & 0xff;
4501
4502                     if (mod == 'K')
4503                       offset = given & 0x7f;
4504
4505                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
4506
4507                     if (PRE_BIT_SET || WRITEBACK_BIT_SET)
4508                       {
4509                         /* Not unindexed.  The offset is scaled.  */
4510                         if (cp_num == 9)
4511                           /* vldr.16/vstr.16 will shift the address
4512                              left by 1 bit only.  */
4513                           offset = offset * 2;
4514                         else
4515                           offset = offset * 4;
4516
4517                         if (NEGATIVE_BIT_SET)
4518                           offset = - offset;
4519                         if (rn != 15)
4520                           value_in_comment = offset;
4521                       }
4522
4523                     if (PRE_BIT_SET)
4524                       {
4525                         if (offset)
4526                           func (stream, ", #%d]%s",
4527                                 (int) offset,
4528                                 WRITEBACK_BIT_SET ? "!" : "");
4529                         else if (NEGATIVE_BIT_SET)
4530                           func (stream, ", #-0]");
4531                         else
4532                           func (stream, "]");
4533                       }
4534                     else
4535                       {
4536                         func (stream, "]");
4537
4538                         if (WRITEBACK_BIT_SET)
4539                           {
4540                             if (offset)
4541                               func (stream, ", #%d", (int) offset);
4542                             else if (NEGATIVE_BIT_SET)
4543                               func (stream, ", #-0");
4544                           }
4545                         else
4546                           {
4547                             func (stream, ", {%s%d}",
4548                                   (NEGATIVE_BIT_SET && !offset) ? "-" : "",
4549                                   (int) offset);
4550                             value_in_comment = offset;
4551                           }
4552                       }
4553                     if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
4554                       {
4555                         func (stream, "\t; ");
4556                         /* For unaligned PCs, apply off-by-alignment
4557                            correction.  */
4558                         info->print_address_func (offset + pc
4559                                                   + info->bytes_per_chunk * 2
4560                                                   - (pc & 3),
4561                                                   info);
4562                       }
4563                   }
4564                   break;
4565
4566                 case 'B':
4567                   {
4568                     int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
4569                     int offset = (given >> 1) & 0x3f;
4570
4571                     if (offset == 1)
4572                       func (stream, "{d%d}", regno);
4573                     else if (regno + offset > 32)
4574                       func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
4575                     else
4576                       func (stream, "{d%d-d%d}", regno, regno + offset - 1);
4577                   }
4578                   break;
4579
4580                 case 'C':
4581                   {
4582                     bfd_boolean single = ((given >> 8) & 1) == 0;
4583                     char reg_prefix = single ? 's' : 'd';
4584                     int Dreg = (given >> 22) & 0x1;
4585                     int Vdreg = (given >> 12) & 0xf;
4586                     int reg = single ? ((Vdreg << 1) | Dreg)
4587                                      : ((Dreg << 4) | Vdreg);
4588                     int num = (given >> (single ? 0 : 1)) & 0x7f;
4589                     int maxreg = single ? 31 : 15;
4590                     int topreg = reg + num - 1;
4591
4592                     if (!num)
4593                       func (stream, "{VPR}");
4594                     else if (num == 1)
4595                       func (stream, "{%c%d, VPR}", reg_prefix, reg);
4596                     else if (topreg > maxreg)
4597                       func (stream, "{%c%d-<overflow reg d%d, VPR}",
4598                             reg_prefix, reg, single ? topreg >> 1 : topreg);
4599                     else
4600                       func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
4601                             reg_prefix, topreg);
4602                   }
4603                   break;
4604
4605                 case 'u':
4606                   if (cond != COND_UNCOND)
4607                     is_unpredictable = TRUE;
4608
4609                   /* Fall through.  */
4610                 case 'c':
4611                   if (cond != COND_UNCOND && cp_num == 9)
4612                     is_unpredictable = TRUE;
4613
4614                   func (stream, "%s", arm_conditional[cond]);
4615                   break;
4616
4617                 case 'I':
4618                   /* Print a Cirrus/DSP shift immediate.  */
4619                   /* Immediates are 7bit signed ints with bits 0..3 in
4620                      bits 0..3 of opcode and bits 4..6 in bits 5..7
4621                      of opcode.  */
4622                   {
4623                     int imm;
4624
4625                     imm = (given & 0xf) | ((given & 0xe0) >> 1);
4626
4627                     /* Is ``imm'' a negative number?  */
4628                     if (imm & 0x40)
4629                       imm -= 0x80;
4630
4631                     func (stream, "%d", imm);
4632                   }
4633
4634                   break;
4635
4636                 case 'J':
4637                   {
4638                     unsigned long regno
4639                       = arm_decode_field_multiple (given, 13, 15, 22, 22);
4640
4641                     switch (regno)
4642                       {
4643                       case 0x1:
4644                         func (stream, "FPSCR");
4645                         break;
4646                       case 0x2:
4647                         func (stream, "FPSCR_nzcvqc");
4648                         break;
4649                       case 0xc:
4650                         func (stream, "VPR");
4651                         break;
4652                       case 0xd:
4653                         func (stream, "P0");
4654                         break;
4655                       case 0xe:
4656                         func (stream, "FPCXTNS");
4657                         break;
4658                       case 0xf:
4659                         func (stream, "FPCXTS");
4660                         break;
4661                       default:
4662                         func (stream, "<invalid reg %lu>", regno);
4663                         break;
4664                       }
4665                   }
4666                   break;
4667
4668                 case 'F':
4669                   switch (given & 0x00408000)
4670                     {
4671                     case 0:
4672                       func (stream, "4");
4673                       break;
4674                     case 0x8000:
4675                       func (stream, "1");
4676                       break;
4677                     case 0x00400000:
4678                       func (stream, "2");
4679                       break;
4680                     default:
4681                       func (stream, "3");
4682                     }
4683                   break;
4684
4685                 case 'P':
4686                   switch (given & 0x00080080)
4687                     {
4688                     case 0:
4689                       func (stream, "s");
4690                       break;
4691                     case 0x80:
4692                       func (stream, "d");
4693                       break;
4694                     case 0x00080000:
4695                       func (stream, "e");
4696                       break;
4697                     default:
4698                       func (stream, _("<illegal precision>"));
4699                       break;
4700                     }
4701                   break;
4702
4703                 case 'Q':
4704                   switch (given & 0x00408000)
4705                     {
4706                     case 0:
4707                       func (stream, "s");
4708                       break;
4709                     case 0x8000:
4710                       func (stream, "d");
4711                       break;
4712                     case 0x00400000:
4713                       func (stream, "e");
4714                       break;
4715                     default:
4716                       func (stream, "p");
4717                       break;
4718                     }
4719                   break;
4720
4721                 case 'R':
4722                   switch (given & 0x60)
4723                     {
4724                     case 0:
4725                       break;
4726                     case 0x20:
4727                       func (stream, "p");
4728                       break;
4729                     case 0x40:
4730                       func (stream, "m");
4731                       break;
4732                     default:
4733                       func (stream, "z");
4734                       break;
4735                     }
4736                   break;
4737
4738                 case '0': case '1': case '2': case '3': case '4':
4739                 case '5': case '6': case '7': case '8': case '9':
4740                   {
4741                     int width;
4742
4743                     c = arm_decode_bitfield (c, given, &value, &width);
4744
4745                     switch (*c)
4746                       {
4747                       case 'R':
4748                         if (value == 15)
4749                           is_unpredictable = TRUE;
4750                         /* Fall through.  */
4751                       case 'r':
4752                         if (c[1] == 'u')
4753                           {
4754                             /* Eat the 'u' character.  */
4755                             ++ c;
4756
4757                             if (u_reg == value)
4758                               is_unpredictable = TRUE;
4759                             u_reg = value;
4760                           }
4761                         func (stream, "%s", arm_regnames[value]);
4762                         break;
4763                       case 'V':
4764                         if (given & (1 << 6))
4765                           goto Q;
4766                         /* FALLTHROUGH */
4767                       case 'D':
4768                         func (stream, "d%ld", value);
4769                         break;
4770                       case 'Q':
4771                       Q:
4772                         if (value & 1)
4773                           func (stream, "<illegal reg q%ld.5>", value >> 1);
4774                         else
4775                           func (stream, "q%ld", value >> 1);
4776                         break;
4777                       case 'd':
4778                         func (stream, "%ld", value);
4779                         value_in_comment = value;
4780                         break;
4781                       case 'E':
4782                         {
4783                           /* Converts immediate 8 bit back to float value.  */
4784                           unsigned floatVal = (value & 0x80) << 24
4785                             | (value & 0x3F) << 19
4786                             | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
4787
4788                           /* Quarter float have a maximum value of 31.0.
4789                              Get floating point value multiplied by 1e7.
4790                              The maximum value stays in limit of a 32-bit int.  */
4791                           unsigned decVal =
4792                             (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
4793                             (16 + (value & 0xF));
4794
4795                           if (!(decVal % 1000000))
4796                             func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
4797                                   floatVal, value & 0x80 ? '-' : ' ',
4798                                   decVal / 10000000,
4799                                   decVal % 10000000 / 1000000);
4800                           else if (!(decVal % 10000))
4801                             func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
4802                                   floatVal, value & 0x80 ? '-' : ' ',
4803                                   decVal / 10000000,
4804                                   decVal % 10000000 / 10000);
4805                           else
4806                             func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
4807                                   floatVal, value & 0x80 ? '-' : ' ',
4808                                   decVal / 10000000, decVal % 10000000);
4809                           break;
4810                         }
4811                       case 'k':
4812                         {
4813                           int from = (given & (1 << 7)) ? 32 : 16;
4814                           func (stream, "%ld", from - value);
4815                         }
4816                         break;
4817
4818                       case 'f':
4819                         if (value > 7)
4820                           func (stream, "#%s", arm_fp_const[value & 7]);
4821                         else
4822                           func (stream, "f%ld", value);
4823                         break;
4824
4825                       case 'w':
4826                         if (width == 2)
4827                           func (stream, "%s", iwmmxt_wwnames[value]);
4828                         else
4829                           func (stream, "%s", iwmmxt_wwssnames[value]);
4830                         break;
4831
4832                       case 'g':
4833                         func (stream, "%s", iwmmxt_regnames[value]);
4834                         break;
4835                       case 'G':
4836                         func (stream, "%s", iwmmxt_cregnames[value]);
4837                         break;
4838
4839                       case 'x':
4840                         func (stream, "0x%lx", (value & 0xffffffffUL));
4841                         break;
4842
4843                       case 'c':
4844                         switch (value)
4845                           {
4846                           case 0:
4847                             func (stream, "eq");
4848                             break;
4849
4850                           case 1:
4851                             func (stream, "vs");
4852                             break;
4853
4854                           case 2:
4855                             func (stream, "ge");
4856                             break;
4857
4858                           case 3:
4859                             func (stream, "gt");
4860                             break;
4861
4862                           default:
4863                             func (stream, "??");
4864                             break;
4865                           }
4866                         break;
4867
4868                       case '`':
4869                         c++;
4870                         if (value == 0)
4871                           func (stream, "%c", *c);
4872                         break;
4873                       case '\'':
4874                         c++;
4875                         if (value == ((1ul << width) - 1))
4876                           func (stream, "%c", *c);
4877                         break;
4878                       case '?':
4879                         func (stream, "%c", c[(1 << width) - (int) value]);
4880                         c += 1 << width;
4881                         break;
4882                       default:
4883                         abort ();
4884                       }
4885                   }
4886                   break;
4887
4888                 case 'y':
4889                 case 'z':
4890                   {
4891                     int single = *c++ == 'y';
4892                     int regno;
4893
4894                     switch (*c)
4895                       {
4896                       case '4': /* Sm pair */
4897                       case '0': /* Sm, Dm */
4898                         regno = given & 0x0000000f;
4899                         if (single)
4900                           {
4901                             regno <<= 1;
4902                             regno += (given >> 5) & 1;
4903                           }
4904                         else
4905                           regno += ((given >> 5) & 1) << 4;
4906                         break;
4907
4908                       case '1': /* Sd, Dd */
4909                         regno = (given >> 12) & 0x0000000f;
4910                         if (single)
4911                           {
4912                             regno <<= 1;
4913                             regno += (given >> 22) & 1;
4914                           }
4915                         else
4916                           regno += ((given >> 22) & 1) << 4;
4917                         break;
4918
4919                       case '2': /* Sn, Dn */
4920                         regno = (given >> 16) & 0x0000000f;
4921                         if (single)
4922                           {
4923                             regno <<= 1;
4924                             regno += (given >> 7) & 1;
4925                           }
4926                         else
4927                           regno += ((given >> 7) & 1) << 4;
4928                         break;
4929
4930                       case '3': /* List */
4931                         func (stream, "{");
4932                         regno = (given >> 12) & 0x0000000f;
4933                         if (single)
4934                           {
4935                             regno <<= 1;
4936                             regno += (given >> 22) & 1;
4937                           }
4938                         else
4939                           regno += ((given >> 22) & 1) << 4;
4940                         break;
4941
4942                       default:
4943                         abort ();
4944                       }
4945
4946                     func (stream, "%c%d", single ? 's' : 'd', regno);
4947
4948                     if (*c == '3')
4949                       {
4950                         int count = given & 0xff;
4951
4952                         if (single == 0)
4953                           count >>= 1;
4954
4955                         if (--count)
4956                           {
4957                             func (stream, "-%c%d",
4958                                   single ? 's' : 'd',
4959                                   regno + count);
4960                           }
4961
4962                         func (stream, "}");
4963                       }
4964                     else if (*c == '4')
4965                       func (stream, ", %c%d", single ? 's' : 'd',
4966                             regno + 1);
4967                   }
4968                   break;
4969
4970                 case 'L':
4971                   switch (given & 0x00400100)
4972                     {
4973                     case 0x00000000: func (stream, "b"); break;
4974                     case 0x00400000: func (stream, "h"); break;
4975                     case 0x00000100: func (stream, "w"); break;
4976                     case 0x00400100: func (stream, "d"); break;
4977                     default:
4978                       break;
4979                     }
4980                   break;
4981
4982                 case 'Z':
4983                   {
4984                     /* given (20, 23) | given (0, 3) */
4985                     value = ((given >> 16) & 0xf0) | (given & 0xf);
4986                     func (stream, "%d", (int) value);
4987                   }
4988                   break;
4989
4990                 case 'l':
4991                   /* This is like the 'A' operator, except that if
4992                      the width field "M" is zero, then the offset is
4993                      *not* multiplied by four.  */
4994                   {
4995                     int offset = given & 0xff;
4996                     int multiplier = (given & 0x00000100) ? 4 : 1;
4997
4998                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
4999
5000                     if (multiplier > 1)
5001                       {
5002                         value_in_comment = offset * multiplier;
5003                         if (NEGATIVE_BIT_SET)
5004                           value_in_comment = - value_in_comment;
5005                       }
5006
5007                     if (offset)
5008                       {
5009                         if (PRE_BIT_SET)
5010                           func (stream, ", #%s%d]%s",
5011                                 NEGATIVE_BIT_SET ? "-" : "",
5012                                 offset * multiplier,
5013                                 WRITEBACK_BIT_SET ? "!" : "");
5014                         else
5015                           func (stream, "], #%s%d",
5016                                 NEGATIVE_BIT_SET ? "-" : "",
5017                                 offset * multiplier);
5018                       }
5019                     else
5020                       func (stream, "]");
5021                   }
5022                   break;
5023
5024                 case 'r':
5025                   {
5026                     int imm4 = (given >> 4) & 0xf;
5027                     int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
5028                     int ubit = ! NEGATIVE_BIT_SET;
5029                     const char *rm = arm_regnames [given & 0xf];
5030                     const char *rn = arm_regnames [(given >> 16) & 0xf];
5031
5032                     switch (puw_bits)
5033                       {
5034                       case 1:
5035                       case 3:
5036                         func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
5037                         if (imm4)
5038                           func (stream, ", lsl #%d", imm4);
5039                         break;
5040
5041                       case 4:
5042                       case 5:
5043                       case 6:
5044                       case 7:
5045                         func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
5046                         if (imm4 > 0)
5047                           func (stream, ", lsl #%d", imm4);
5048                         func (stream, "]");
5049                         if (puw_bits == 5 || puw_bits == 7)
5050                           func (stream, "!");
5051                         break;
5052
5053                       default:
5054                         func (stream, "INVALID");
5055                       }
5056                   }
5057                   break;
5058
5059                 case 'i':
5060                   {
5061                     long imm5;
5062                     imm5 = ((given & 0x100) >> 4) | (given & 0xf);
5063                     func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
5064                   }
5065                   break;
5066
5067                 default:
5068                   abort ();
5069                 }
5070             }
5071           else
5072             func (stream, "%c", *c);
5073         }
5074
5075       if (value_in_comment > 32 || value_in_comment < -16)
5076         func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
5077
5078       if (is_unpredictable)
5079         func (stream, UNPREDICTABLE_INSTRUCTION);
5080
5081       return TRUE;
5082     }
5083   return FALSE;
5084 }
5085
5086 /* Decodes and prints ARM addressing modes.  Returns the offset
5087    used in the address, if any, if it is worthwhile printing the
5088    offset as a hexadecimal value in a comment at the end of the
5089    line of disassembly.  */
5090
5091 static signed long
5092 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
5093 {
5094   void *stream = info->stream;
5095   fprintf_ftype func = info->fprintf_func;
5096   bfd_vma offset = 0;
5097
5098   if (((given & 0x000f0000) == 0x000f0000)
5099       && ((given & 0x02000000) == 0))
5100     {
5101       offset = given & 0xfff;
5102
5103       func (stream, "[pc");
5104
5105       if (PRE_BIT_SET)
5106         {
5107           /* Pre-indexed.  Elide offset of positive zero when
5108              non-writeback.  */
5109           if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
5110             func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
5111
5112           if (NEGATIVE_BIT_SET)
5113             offset = -offset;
5114
5115           offset += pc + 8;
5116
5117           /* Cope with the possibility of write-back
5118              being used.  Probably a very dangerous thing
5119              for the programmer to do, but who are we to
5120              argue ?  */
5121           func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
5122         }
5123       else  /* Post indexed.  */
5124         {
5125           func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
5126
5127           /* Ie ignore the offset.  */
5128           offset = pc + 8;
5129         }
5130
5131       func (stream, "\t; ");
5132       info->print_address_func (offset, info);
5133       offset = 0;
5134     }
5135   else
5136     {
5137       func (stream, "[%s",
5138             arm_regnames[(given >> 16) & 0xf]);
5139
5140       if (PRE_BIT_SET)
5141         {
5142           if ((given & 0x02000000) == 0)
5143             {
5144               /* Elide offset of positive zero when non-writeback.  */
5145               offset = given & 0xfff;
5146               if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
5147                 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
5148             }
5149           else
5150             {
5151               func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
5152               arm_decode_shift (given, func, stream, TRUE);
5153             }
5154
5155           func (stream, "]%s",
5156                 WRITEBACK_BIT_SET ? "!" : "");
5157         }
5158       else
5159         {
5160           if ((given & 0x02000000) == 0)
5161             {
5162               /* Always show offset.  */
5163               offset = given & 0xfff;
5164               func (stream, "], #%s%d",
5165                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
5166             }
5167           else
5168             {
5169               func (stream, "], %s",
5170                     NEGATIVE_BIT_SET ? "-" : "");
5171               arm_decode_shift (given, func, stream, TRUE);
5172             }
5173         }
5174       if (NEGATIVE_BIT_SET)
5175         offset = -offset;
5176     }
5177
5178   return (signed long) offset;
5179 }
5180
5181 /* Print one neon instruction on INFO->STREAM.
5182    Return TRUE if the instuction matched, FALSE if this is not a
5183    recognised neon instruction.  */
5184
5185 static bfd_boolean
5186 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
5187 {
5188   const struct opcode32 *insn;
5189   void *stream = info->stream;
5190   fprintf_ftype func = info->fprintf_func;
5191
5192   if (thumb)
5193     {
5194       if ((given & 0xef000000) == 0xef000000)
5195         {
5196           /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding.  */
5197           unsigned long bit28 = given & (1 << 28);
5198
5199           given &= 0x00ffffff;
5200           if (bit28)
5201             given |= 0xf3000000;
5202           else
5203             given |= 0xf2000000;
5204         }
5205       else if ((given & 0xff000000) == 0xf9000000)
5206         given ^= 0xf9000000 ^ 0xf4000000;
5207       /* vdup is also a valid neon instruction.  */
5208       else if ((given & 0xff910f5f) != 0xee800b10)
5209         return FALSE;
5210     }
5211
5212   for (insn = neon_opcodes; insn->assembler; insn++)
5213     {
5214       if ((given & insn->mask) == insn->value)
5215         {
5216           signed long value_in_comment = 0;
5217           bfd_boolean is_unpredictable = FALSE;
5218           const char *c;
5219
5220           for (c = insn->assembler; *c; c++)
5221             {
5222               if (*c == '%')
5223                 {
5224                   switch (*++c)
5225                     {
5226                     case '%':
5227                       func (stream, "%%");
5228                       break;
5229
5230                     case 'u':
5231                       if (thumb && ifthen_state)
5232                         is_unpredictable = TRUE;
5233
5234                       /* Fall through.  */
5235                     case 'c':
5236                       if (thumb && ifthen_state)
5237                         func (stream, "%s", arm_conditional[IFTHEN_COND]);
5238                       break;
5239
5240                     case 'A':
5241                       {
5242                         static const unsigned char enc[16] =
5243                         {
5244                           0x4, 0x14, /* st4 0,1 */
5245                           0x4, /* st1 2 */
5246                           0x4, /* st2 3 */
5247                           0x3, /* st3 4 */
5248                           0x13, /* st3 5 */
5249                           0x3, /* st1 6 */
5250                           0x1, /* st1 7 */
5251                           0x2, /* st2 8 */
5252                           0x12, /* st2 9 */
5253                           0x2, /* st1 10 */
5254                           0, 0, 0, 0, 0
5255                         };
5256                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
5257                         int rn = ((given >> 16) & 0xf);
5258                         int rm = ((given >> 0) & 0xf);
5259                         int align = ((given >> 4) & 0x3);
5260                         int type = ((given >> 8) & 0xf);
5261                         int n = enc[type] & 0xf;
5262                         int stride = (enc[type] >> 4) + 1;
5263                         int ix;
5264
5265                         func (stream, "{");
5266                         if (stride > 1)
5267                           for (ix = 0; ix != n; ix++)
5268                             func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
5269                         else if (n == 1)
5270                           func (stream, "d%d", rd);
5271                         else
5272                           func (stream, "d%d-d%d", rd, rd + n - 1);
5273                         func (stream, "}, [%s", arm_regnames[rn]);
5274                         if (align)
5275                           func (stream, " :%d", 32 << align);
5276                         func (stream, "]");
5277                         if (rm == 0xd)
5278                           func (stream, "!");
5279                         else if (rm != 0xf)
5280                           func (stream, ", %s", arm_regnames[rm]);
5281                       }
5282                       break;
5283
5284                     case 'B':
5285                       {
5286                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
5287                         int rn = ((given >> 16) & 0xf);
5288                         int rm = ((given >> 0) & 0xf);
5289                         int idx_align = ((given >> 4) & 0xf);
5290                         int align = 0;
5291                         int size = ((given >> 10) & 0x3);
5292                         int idx = idx_align >> (size + 1);
5293                         int length = ((given >> 8) & 3) + 1;
5294                         int stride = 1;
5295                         int i;
5296
5297                         if (length > 1 && size > 0)
5298                           stride = (idx_align & (1 << size)) ? 2 : 1;
5299
5300                         switch (length)
5301                           {
5302                           case 1:
5303                             {
5304                               int amask = (1 << size) - 1;
5305                               if ((idx_align & (1 << size)) != 0)
5306                                 return FALSE;
5307                               if (size > 0)
5308                                 {
5309                                   if ((idx_align & amask) == amask)
5310                                     align = 8 << size;
5311                                   else if ((idx_align & amask) != 0)
5312                                     return FALSE;
5313                                 }
5314                               }
5315                             break;
5316
5317                           case 2:
5318                             if (size == 2 && (idx_align & 2) != 0)
5319                               return FALSE;
5320                             align = (idx_align & 1) ? 16 << size : 0;
5321                             break;
5322
5323                           case 3:
5324                             if ((size == 2 && (idx_align & 3) != 0)
5325                                 || (idx_align & 1) != 0)
5326                               return FALSE;
5327                             break;
5328
5329                           case 4:
5330                             if (size == 2)
5331                               {
5332                                 if ((idx_align & 3) == 3)
5333                                   return FALSE;
5334                                 align = (idx_align & 3) * 64;
5335                               }
5336                             else
5337                               align = (idx_align & 1) ? 32 << size : 0;
5338                             break;
5339
5340                           default:
5341                             abort ();
5342                           }
5343
5344                         func (stream, "{");
5345                         for (i = 0; i < length; i++)
5346                           func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
5347                             rd + i * stride, idx);
5348                         func (stream, "}, [%s", arm_regnames[rn]);
5349                         if (align)
5350                           func (stream, " :%d", align);
5351                         func (stream, "]");
5352                         if (rm == 0xd)
5353                           func (stream, "!");
5354                         else if (rm != 0xf)
5355                           func (stream, ", %s", arm_regnames[rm]);
5356                       }
5357                       break;
5358
5359                     case 'C':
5360                       {
5361                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
5362                         int rn = ((given >> 16) & 0xf);
5363                         int rm = ((given >> 0) & 0xf);
5364                         int align = ((given >> 4) & 0x1);
5365                         int size = ((given >> 6) & 0x3);
5366                         int type = ((given >> 8) & 0x3);
5367                         int n = type + 1;
5368                         int stride = ((given >> 5) & 0x1);
5369                         int ix;
5370
5371                         if (stride && (n == 1))
5372                           n++;
5373                         else
5374                           stride++;
5375
5376                         func (stream, "{");
5377                         if (stride > 1)
5378                           for (ix = 0; ix != n; ix++)
5379                             func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
5380                         else if (n == 1)
5381                           func (stream, "d%d[]", rd);
5382                         else
5383                           func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
5384                         func (stream, "}, [%s", arm_regnames[rn]);
5385                         if (align)
5386                           {
5387                             align = (8 * (type + 1)) << size;
5388                             if (type == 3)
5389                               align = (size > 1) ? align >> 1 : align;
5390                             if (type == 2 || (type == 0 && !size))
5391                               func (stream, " :<bad align %d>", align);
5392                             else
5393                               func (stream, " :%d", align);
5394                           }
5395                         func (stream, "]");
5396                         if (rm == 0xd)
5397                           func (stream, "!");
5398                         else if (rm != 0xf)
5399                           func (stream, ", %s", arm_regnames[rm]);
5400                       }
5401                       break;
5402
5403                     case 'D':
5404                       {
5405                         int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
5406                         int size = (given >> 20) & 3;
5407                         int reg = raw_reg & ((4 << size) - 1);
5408                         int ix = raw_reg >> size >> 2;
5409
5410                         func (stream, "d%d[%d]", reg, ix);
5411                       }
5412                       break;
5413
5414                     case 'E':
5415                       /* Neon encoded constant for mov, mvn, vorr, vbic.  */
5416                       {
5417                         int bits = 0;
5418                         int cmode = (given >> 8) & 0xf;
5419                         int op = (given >> 5) & 0x1;
5420                         unsigned long value = 0, hival = 0;
5421                         unsigned shift;
5422                         int size = 0;
5423                         int isfloat = 0;
5424
5425                         bits |= ((given >> 24) & 1) << 7;
5426                         bits |= ((given >> 16) & 7) << 4;
5427                         bits |= ((given >> 0) & 15) << 0;
5428
5429                         if (cmode < 8)
5430                           {
5431                             shift = (cmode >> 1) & 3;
5432                             value = (unsigned long) bits << (8 * shift);
5433                             size = 32;
5434                           }
5435                         else if (cmode < 12)
5436                           {
5437                             shift = (cmode >> 1) & 1;
5438                             value = (unsigned long) bits << (8 * shift);
5439                             size = 16;
5440                           }
5441                         else if (cmode < 14)
5442                           {
5443                             shift = (cmode & 1) + 1;
5444                             value = (unsigned long) bits << (8 * shift);
5445                             value |= (1ul << (8 * shift)) - 1;
5446                             size = 32;
5447                           }
5448                         else if (cmode == 14)
5449                           {
5450                             if (op)
5451                               {
5452                                 /* Bit replication into bytes.  */
5453                                 int ix;
5454                                 unsigned long mask;
5455
5456                                 value = 0;
5457                                 hival = 0;
5458                                 for (ix = 7; ix >= 0; ix--)
5459                                   {
5460                                     mask = ((bits >> ix) & 1) ? 0xff : 0;
5461                                     if (ix <= 3)
5462                                       value = (value << 8) | mask;
5463                                     else
5464                                       hival = (hival << 8) | mask;
5465                                   }
5466                                 size = 64;
5467                               }
5468                             else
5469                               {
5470                                 /* Byte replication.  */
5471                                 value = (unsigned long) bits;
5472                                 size = 8;
5473                               }
5474                           }
5475                         else if (!op)
5476                           {
5477                             /* Floating point encoding.  */
5478                             int tmp;
5479
5480                             value = (unsigned long)  (bits & 0x7f) << 19;
5481                             value |= (unsigned long) (bits & 0x80) << 24;
5482                             tmp = bits & 0x40 ? 0x3c : 0x40;
5483                             value |= (unsigned long) tmp << 24;
5484                             size = 32;
5485                             isfloat = 1;
5486                           }
5487                         else
5488                           {
5489                             func (stream, "<illegal constant %.8x:%x:%x>",
5490                                   bits, cmode, op);
5491                             size = 32;
5492                             break;
5493                           }
5494                         switch (size)
5495                           {
5496                           case 8:
5497                             func (stream, "#%ld\t; 0x%.2lx", value, value);
5498                             break;
5499
5500                           case 16:
5501                             func (stream, "#%ld\t; 0x%.4lx", value, value);
5502                             break;
5503
5504                           case 32:
5505                             if (isfloat)
5506                               {
5507                                 unsigned char valbytes[4];
5508                                 double fvalue;
5509
5510                                 /* Do this a byte at a time so we don't have to
5511                                    worry about the host's endianness.  */
5512                                 valbytes[0] = value & 0xff;
5513                                 valbytes[1] = (value >> 8) & 0xff;
5514                                 valbytes[2] = (value >> 16) & 0xff;
5515                                 valbytes[3] = (value >> 24) & 0xff;
5516
5517                                 floatformat_to_double
5518                                   (& floatformat_ieee_single_little, valbytes,
5519                                   & fvalue);
5520
5521                                 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
5522                                       value);
5523                               }
5524                             else
5525                               func (stream, "#%ld\t; 0x%.8lx",
5526                                     (long) (((value & 0x80000000L) != 0)
5527                                             ? value | ~0xffffffffL : value),
5528                                     value);
5529                             break;
5530
5531                           case 64:
5532                             func (stream, "#0x%.8lx%.8lx", hival, value);
5533                             break;
5534
5535                           default:
5536                             abort ();
5537                           }
5538                       }
5539                       break;
5540
5541                     case 'F':
5542                       {
5543                         int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
5544                         int num = (given >> 8) & 0x3;
5545
5546                         if (!num)
5547                           func (stream, "{d%d}", regno);
5548                         else if (num + regno >= 32)
5549                           func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
5550                         else
5551                           func (stream, "{d%d-d%d}", regno, regno + num);
5552                       }
5553                       break;
5554
5555
5556                     case '0': case '1': case '2': case '3': case '4':
5557                     case '5': case '6': case '7': case '8': case '9':
5558                       {
5559                         int width;
5560                         unsigned long value;
5561
5562                         c = arm_decode_bitfield (c, given, &value, &width);
5563
5564                         switch (*c)
5565                           {
5566                           case 'r':
5567                             func (stream, "%s", arm_regnames[value]);
5568                             break;
5569                           case 'd':
5570                             func (stream, "%ld", value);
5571                             value_in_comment = value;
5572                             break;
5573                           case 'e':
5574                             func (stream, "%ld", (1ul << width) - value);
5575                             break;
5576
5577                           case 'S':
5578                           case 'T':
5579                           case 'U':
5580                             /* Various width encodings.  */
5581                             {
5582                               int base = 8 << (*c - 'S'); /* 8,16 or 32 */
5583                               int limit;
5584                               unsigned low, high;
5585
5586                               c++;
5587                               if (*c >= '0' && *c <= '9')
5588                                 limit = *c - '0';
5589                               else if (*c >= 'a' && *c <= 'f')
5590                                 limit = *c - 'a' + 10;
5591                               else
5592                                 abort ();
5593                               low = limit >> 2;
5594                               high = limit & 3;
5595
5596                               if (value < low || value > high)
5597                                 func (stream, "<illegal width %d>", base << value);
5598                               else
5599                                 func (stream, "%d", base << value);
5600                             }
5601                             break;
5602                           case 'R':
5603                             if (given & (1 << 6))
5604                               goto Q;
5605                             /* FALLTHROUGH */
5606                           case 'D':
5607                             func (stream, "d%ld", value);
5608                             break;
5609                           case 'Q':
5610                           Q:
5611                             if (value & 1)
5612                               func (stream, "<illegal reg q%ld.5>", value >> 1);
5613                             else
5614                               func (stream, "q%ld", value >> 1);
5615                             break;
5616
5617                           case '`':
5618                             c++;
5619                             if (value == 0)
5620                               func (stream, "%c", *c);
5621                             break;
5622                           case '\'':
5623                             c++;
5624                             if (value == ((1ul << width) - 1))
5625                               func (stream, "%c", *c);
5626                             break;
5627                           case '?':
5628                             func (stream, "%c", c[(1 << width) - (int) value]);
5629                             c += 1 << width;
5630                             break;
5631                           default:
5632                             abort ();
5633                           }
5634                       }
5635                       break;
5636
5637                     default:
5638                       abort ();
5639                     }
5640                 }
5641               else
5642                 func (stream, "%c", *c);
5643             }
5644
5645           if (value_in_comment > 32 || value_in_comment < -16)
5646             func (stream, "\t; 0x%lx", value_in_comment);
5647
5648           if (is_unpredictable)
5649             func (stream, UNPREDICTABLE_INSTRUCTION);
5650
5651           return TRUE;
5652         }
5653     }
5654   return FALSE;
5655 }
5656
5657 /* Print one mve instruction on INFO->STREAM.
5658    Return TRUE if the instuction matched, FALSE if this is not a
5659    recognised mve instruction.  */
5660
5661 static bfd_boolean
5662 print_insn_mve (struct disassemble_info *info, long given)
5663 {
5664   const struct mopcode32 *insn;
5665   void *stream = info->stream;
5666   fprintf_ftype func = info->fprintf_func;
5667
5668   for (insn = mve_opcodes; insn->assembler; insn++)
5669     {
5670       if (((given & insn->mask) == insn->value)
5671           && !is_mve_encoding_conflict (given, insn->mve_op))
5672         {
5673           signed long value_in_comment = 0;
5674           bfd_boolean is_unpredictable = FALSE;
5675           bfd_boolean is_undefined = FALSE;
5676           const char *c;
5677           enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
5678           enum mve_undefined undefined_cond = UNDEF_NONE;
5679
5680           /* Most vector mve instruction are illegal in a it block.
5681              There are a few exceptions; check for them.  */
5682           if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
5683             {
5684               is_unpredictable = TRUE;
5685               unpredictable_cond = UNPRED_IT_BLOCK;
5686             }
5687           else if (is_mve_unpredictable (given, insn->mve_op,
5688                                          &unpredictable_cond))
5689             is_unpredictable = TRUE;
5690
5691           if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
5692             is_undefined = TRUE;
5693
5694           for (c = insn->assembler; *c; c++)
5695             {
5696               if (*c == '%')
5697                 {
5698                   switch (*++c)
5699                     {
5700                     case '%':
5701                       func (stream, "%%");
5702                       break;
5703
5704                     case 'c':
5705                       if (ifthen_state)
5706                         func (stream, "%s", arm_conditional[IFTHEN_COND]);
5707                       break;
5708
5709                     case 'i':
5710                       {
5711                         long mve_mask = mve_extract_pred_mask (given);
5712                         func (stream, "%s", mve_predicatenames[mve_mask]);
5713                       }
5714                       break;
5715
5716                     case 'n':
5717                       print_vec_condition (info, given, insn->mve_op);
5718                       break;
5719
5720                     case 'v':
5721                       print_instruction_predicate (info);
5722                       break;
5723
5724                     case '0': case '1': case '2': case '3': case '4':
5725                     case '5': case '6': case '7': case '8': case '9':
5726                       {
5727                         int width;
5728                         unsigned long value;
5729
5730                         c = arm_decode_bitfield (c, given, &value, &width);
5731
5732                         switch (*c)
5733                           {
5734                           case 'Z':
5735                             if (value == 13)
5736                               is_unpredictable = TRUE;
5737                             else if (value == 15)
5738                               func (stream, "zr");
5739                             else
5740                               func (stream, "%s", arm_regnames[value]);
5741                             break;
5742                           case 's':
5743                             print_mve_size (info,
5744                                             value,
5745                                             insn->mve_op);
5746                             break;
5747                           case 'r':
5748                             func (stream, "%s", arm_regnames[value]);
5749                             break;
5750                           case 'Q':
5751                             if (value & 0x8)
5752                               func (stream, "<illegal reg q%ld.5>", value);
5753                             else
5754                               func (stream, "q%ld", value);
5755                             break;
5756                           default:
5757                             abort ();
5758                           }
5759                         break;
5760                       default:
5761                         abort ();
5762                       }
5763                     }
5764                 }
5765               else
5766                 func (stream, "%c", *c);
5767             }
5768
5769           if (value_in_comment > 32 || value_in_comment < -16)
5770             func (stream, "\t; 0x%lx", value_in_comment);
5771
5772           if (is_unpredictable)
5773             print_mve_unpredictable (info, unpredictable_cond);
5774
5775           if (is_undefined)
5776             print_mve_undefined (info, undefined_cond);
5777
5778           if ((vpt_block_state.in_vpt_block == FALSE)
5779               && !ifthen_state
5780               && (is_vpt_instruction (given) == TRUE))
5781             mark_inside_vpt_block (given);
5782           else if (vpt_block_state.in_vpt_block == TRUE)
5783             update_vpt_block_state ();
5784
5785           return TRUE;
5786         }
5787     }
5788   return FALSE;
5789 }
5790
5791
5792 /* Return the name of a v7A special register.  */
5793
5794 static const char *
5795 banked_regname (unsigned reg)
5796 {
5797   switch (reg)
5798     {
5799       case 15: return "CPSR";
5800       case 32: return "R8_usr";
5801       case 33: return "R9_usr";
5802       case 34: return "R10_usr";
5803       case 35: return "R11_usr";
5804       case 36: return "R12_usr";
5805       case 37: return "SP_usr";
5806       case 38: return "LR_usr";
5807       case 40: return "R8_fiq";
5808       case 41: return "R9_fiq";
5809       case 42: return "R10_fiq";
5810       case 43: return "R11_fiq";
5811       case 44: return "R12_fiq";
5812       case 45: return "SP_fiq";
5813       case 46: return "LR_fiq";
5814       case 48: return "LR_irq";
5815       case 49: return "SP_irq";
5816       case 50: return "LR_svc";
5817       case 51: return "SP_svc";
5818       case 52: return "LR_abt";
5819       case 53: return "SP_abt";
5820       case 54: return "LR_und";
5821       case 55: return "SP_und";
5822       case 60: return "LR_mon";
5823       case 61: return "SP_mon";
5824       case 62: return "ELR_hyp";
5825       case 63: return "SP_hyp";
5826       case 79: return "SPSR";
5827       case 110: return "SPSR_fiq";
5828       case 112: return "SPSR_irq";
5829       case 114: return "SPSR_svc";
5830       case 116: return "SPSR_abt";
5831       case 118: return "SPSR_und";
5832       case 124: return "SPSR_mon";
5833       case 126: return "SPSR_hyp";
5834       default: return NULL;
5835     }
5836 }
5837
5838 /* Return the name of the DMB/DSB option.  */
5839 static const char *
5840 data_barrier_option (unsigned option)
5841 {
5842   switch (option & 0xf)
5843     {
5844     case 0xf: return "sy";
5845     case 0xe: return "st";
5846     case 0xd: return "ld";
5847     case 0xb: return "ish";
5848     case 0xa: return "ishst";
5849     case 0x9: return "ishld";
5850     case 0x7: return "un";
5851     case 0x6: return "unst";
5852     case 0x5: return "nshld";
5853     case 0x3: return "osh";
5854     case 0x2: return "oshst";
5855     case 0x1: return "oshld";
5856     default:  return NULL;
5857     }
5858 }
5859
5860 /* Print one ARM instruction from PC on INFO->STREAM.  */
5861
5862 static void
5863 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
5864 {
5865   const struct opcode32 *insn;
5866   void *stream = info->stream;
5867   fprintf_ftype func = info->fprintf_func;
5868   struct arm_private_data *private_data = info->private_data;
5869
5870   if (print_insn_coprocessor (pc, info, given, FALSE))
5871     return;
5872
5873   if (print_insn_neon (info, given, FALSE))
5874     return;
5875
5876   for (insn = arm_opcodes; insn->assembler; insn++)
5877     {
5878       if ((given & insn->mask) != insn->value)
5879         continue;
5880
5881       if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
5882         continue;
5883
5884       /* Special case: an instruction with all bits set in the condition field
5885          (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
5886          or by the catchall at the end of the table.  */
5887       if ((given & 0xF0000000) != 0xF0000000
5888           || (insn->mask & 0xF0000000) == 0xF0000000
5889           || (insn->mask == 0 && insn->value == 0))
5890         {
5891           unsigned long u_reg = 16;
5892           unsigned long U_reg = 16;
5893           bfd_boolean is_unpredictable = FALSE;
5894           signed long value_in_comment = 0;
5895           const char *c;
5896
5897           for (c = insn->assembler; *c; c++)
5898             {
5899               if (*c == '%')
5900                 {
5901                   bfd_boolean allow_unpredictable = FALSE;
5902
5903                   switch (*++c)
5904                     {
5905                     case '%':
5906                       func (stream, "%%");
5907                       break;
5908
5909                     case 'a':
5910                       value_in_comment = print_arm_address (pc, info, given);
5911                       break;
5912
5913                     case 'P':
5914                       /* Set P address bit and use normal address
5915                          printing routine.  */
5916                       value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
5917                       break;
5918
5919                     case 'S':
5920                       allow_unpredictable = TRUE;
5921                       /* Fall through.  */
5922                     case 's':
5923                       if ((given & 0x004f0000) == 0x004f0000)
5924                         {
5925                           /* PC relative with immediate offset.  */
5926                           bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
5927
5928                           if (PRE_BIT_SET)
5929                             {
5930                               /* Elide positive zero offset.  */
5931                               if (offset || NEGATIVE_BIT_SET)
5932                                 func (stream, "[pc, #%s%d]\t; ",
5933                                       NEGATIVE_BIT_SET ? "-" : "", (int) offset);
5934                               else
5935                                 func (stream, "[pc]\t; ");
5936                               if (NEGATIVE_BIT_SET)
5937                                 offset = -offset;
5938                               info->print_address_func (offset + pc + 8, info);
5939                             }
5940                           else
5941                             {
5942                               /* Always show the offset.  */
5943                               func (stream, "[pc], #%s%d",
5944                                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
5945                               if (! allow_unpredictable)
5946                                 is_unpredictable = TRUE;
5947                             }
5948                         }
5949                       else
5950                         {
5951                           int offset = ((given & 0xf00) >> 4) | (given & 0xf);
5952
5953                           func (stream, "[%s",
5954                                 arm_regnames[(given >> 16) & 0xf]);
5955
5956                           if (PRE_BIT_SET)
5957                             {
5958                               if (IMMEDIATE_BIT_SET)
5959                                 {
5960                                   /* Elide offset for non-writeback
5961                                      positive zero.  */
5962                                   if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
5963                                       || offset)
5964                                     func (stream, ", #%s%d",
5965                                           NEGATIVE_BIT_SET ? "-" : "", offset);
5966
5967                                   if (NEGATIVE_BIT_SET)
5968                                     offset = -offset;
5969
5970                                   value_in_comment = offset;
5971                                 }
5972                               else
5973                                 {
5974                                   /* Register Offset or Register Pre-Indexed.  */
5975                                   func (stream, ", %s%s",
5976                                         NEGATIVE_BIT_SET ? "-" : "",
5977                                         arm_regnames[given & 0xf]);
5978
5979                                   /* Writing back to the register that is the source/
5980                                      destination of the load/store is unpredictable.  */
5981                                   if (! allow_unpredictable
5982                                       && WRITEBACK_BIT_SET
5983                                       && ((given & 0xf) == ((given >> 12) & 0xf)))
5984                                     is_unpredictable = TRUE;
5985                                 }
5986
5987                               func (stream, "]%s",
5988                                     WRITEBACK_BIT_SET ? "!" : "");
5989                             }
5990                           else
5991                             {
5992                               if (IMMEDIATE_BIT_SET)
5993                                 {
5994                                   /* Immediate Post-indexed.  */
5995                                   /* PR 10924: Offset must be printed, even if it is zero.  */
5996                                   func (stream, "], #%s%d",
5997                                         NEGATIVE_BIT_SET ? "-" : "", offset);
5998                                   if (NEGATIVE_BIT_SET)
5999                                     offset = -offset;
6000                                   value_in_comment = offset;
6001                                 }
6002                               else
6003                                 {
6004                                   /* Register Post-indexed.  */
6005                                   func (stream, "], %s%s",
6006                                         NEGATIVE_BIT_SET ? "-" : "",
6007                                         arm_regnames[given & 0xf]);
6008
6009                                   /* Writing back to the register that is the source/
6010                                      destination of the load/store is unpredictable.  */
6011                                   if (! allow_unpredictable
6012                                       && (given & 0xf) == ((given >> 12) & 0xf))
6013                                     is_unpredictable = TRUE;
6014                                 }
6015
6016                               if (! allow_unpredictable)
6017                                 {
6018                                   /* Writeback is automatically implied by post- addressing.
6019                                      Setting the W bit is unnecessary and ARM specify it as
6020                                      being unpredictable.  */
6021                                   if (WRITEBACK_BIT_SET
6022                                       /* Specifying the PC register as the post-indexed
6023                                          registers is also unpredictable.  */
6024                                       || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
6025                                     is_unpredictable = TRUE;
6026                                 }
6027                             }
6028                         }
6029                       break;
6030
6031                     case 'b':
6032                       {
6033                         bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
6034                         info->print_address_func (disp * 4 + pc + 8, info);
6035                       }
6036                       break;
6037
6038                     case 'c':
6039                       if (((given >> 28) & 0xf) != 0xe)
6040                         func (stream, "%s",
6041                               arm_conditional [(given >> 28) & 0xf]);
6042                       break;
6043
6044                     case 'm':
6045                       {
6046                         int started = 0;
6047                         int reg;
6048
6049                         func (stream, "{");
6050                         for (reg = 0; reg < 16; reg++)
6051                           if ((given & (1 << reg)) != 0)
6052                             {
6053                               if (started)
6054                                 func (stream, ", ");
6055                               started = 1;
6056                               func (stream, "%s", arm_regnames[reg]);
6057                             }
6058                         func (stream, "}");
6059                         if (! started)
6060                           is_unpredictable = TRUE;
6061                       }
6062                       break;
6063
6064                     case 'q':
6065                       arm_decode_shift (given, func, stream, FALSE);
6066                       break;
6067
6068                     case 'o':
6069                       if ((given & 0x02000000) != 0)
6070                         {
6071                           unsigned int rotate = (given & 0xf00) >> 7;
6072                           unsigned int immed = (given & 0xff);
6073                           unsigned int a, i;
6074
6075                           a = (((immed << (32 - rotate))
6076                                 | (immed >> rotate)) & 0xffffffff);
6077                           /* If there is another encoding with smaller rotate,
6078                              the rotate should be specified directly.  */
6079                           for (i = 0; i < 32; i += 2)
6080                             if ((a << i | a >> (32 - i)) <= 0xff)
6081                               break;
6082
6083                           if (i != rotate)
6084                             func (stream, "#%d, %d", immed, rotate);
6085                           else
6086                             func (stream, "#%d", a);
6087                           value_in_comment = a;
6088                         }
6089                       else
6090                         arm_decode_shift (given, func, stream, TRUE);
6091                       break;
6092
6093                     case 'p':
6094                       if ((given & 0x0000f000) == 0x0000f000)
6095                         {
6096                           arm_feature_set arm_ext_v6 =
6097                             ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
6098
6099                           /* The p-variants of tst/cmp/cmn/teq are the pre-V6
6100                              mechanism for setting PSR flag bits.  They are
6101                              obsolete in V6 onwards.  */
6102                           if (! ARM_CPU_HAS_FEATURE (private_data->features, \
6103                                                      arm_ext_v6))
6104                             func (stream, "p");
6105                           else
6106                             is_unpredictable = TRUE;
6107                         }
6108                       break;
6109
6110                     case 't':
6111                       if ((given & 0x01200000) == 0x00200000)
6112                         func (stream, "t");
6113                       break;
6114
6115                     case 'A':
6116                       {
6117                         int offset = given & 0xff;
6118
6119                         value_in_comment = offset * 4;
6120                         if (NEGATIVE_BIT_SET)
6121                           value_in_comment = - value_in_comment;
6122
6123                         func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
6124
6125                         if (PRE_BIT_SET)
6126                           {
6127                             if (offset)
6128                               func (stream, ", #%d]%s",
6129                                     (int) value_in_comment,
6130                                     WRITEBACK_BIT_SET ? "!" : "");
6131                             else
6132                               func (stream, "]");
6133                           }
6134                         else
6135                           {
6136                             func (stream, "]");
6137
6138                             if (WRITEBACK_BIT_SET)
6139                               {
6140                                 if (offset)
6141                                   func (stream, ", #%d", (int) value_in_comment);
6142                               }
6143                             else
6144                               {
6145                                 func (stream, ", {%d}", (int) offset);
6146                                 value_in_comment = offset;
6147                               }
6148                           }
6149                       }
6150                       break;
6151
6152                     case 'B':
6153                       /* Print ARM V5 BLX(1) address: pc+25 bits.  */
6154                       {
6155                         bfd_vma address;
6156                         bfd_vma offset = 0;
6157
6158                         if (! NEGATIVE_BIT_SET)
6159                           /* Is signed, hi bits should be ones.  */
6160                           offset = (-1) ^ 0x00ffffff;
6161
6162                         /* Offset is (SignExtend(offset field)<<2).  */
6163                         offset += given & 0x00ffffff;
6164                         offset <<= 2;
6165                         address = offset + pc + 8;
6166
6167                         if (given & 0x01000000)
6168                           /* H bit allows addressing to 2-byte boundaries.  */
6169                           address += 2;
6170
6171                         info->print_address_func (address, info);
6172                       }
6173                       break;
6174
6175                     case 'C':
6176                       if ((given & 0x02000200) == 0x200)
6177                         {
6178                           const char * name;
6179                           unsigned sysm = (given & 0x004f0000) >> 16;
6180
6181                           sysm |= (given & 0x300) >> 4;
6182                           name = banked_regname (sysm);
6183
6184                           if (name != NULL)
6185                             func (stream, "%s", name);
6186                           else
6187                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
6188                         }
6189                       else
6190                         {
6191                           func (stream, "%cPSR_",
6192                                 (given & 0x00400000) ? 'S' : 'C');
6193                           if (given & 0x80000)
6194                             func (stream, "f");
6195                           if (given & 0x40000)
6196                             func (stream, "s");
6197                           if (given & 0x20000)
6198                             func (stream, "x");
6199                           if (given & 0x10000)
6200                             func (stream, "c");
6201                         }
6202                       break;
6203
6204                     case 'U':
6205                       if ((given & 0xf0) == 0x60)
6206                         {
6207                           switch (given & 0xf)
6208                             {
6209                             case 0xf: func (stream, "sy"); break;
6210                             default:
6211                               func (stream, "#%d", (int) given & 0xf);
6212                               break;
6213                             }
6214                         }
6215                       else
6216                         {
6217                           const char * opt = data_barrier_option (given & 0xf);
6218                           if (opt != NULL)
6219                             func (stream, "%s", opt);
6220                           else
6221                               func (stream, "#%d", (int) given & 0xf);
6222                         }
6223                       break;
6224
6225                     case '0': case '1': case '2': case '3': case '4':
6226                     case '5': case '6': case '7': case '8': case '9':
6227                       {
6228                         int width;
6229                         unsigned long value;
6230
6231                         c = arm_decode_bitfield (c, given, &value, &width);
6232
6233                         switch (*c)
6234                           {
6235                           case 'R':
6236                             if (value == 15)
6237                               is_unpredictable = TRUE;
6238                             /* Fall through.  */
6239                           case 'r':
6240                           case 'T':
6241                             /* We want register + 1 when decoding T.  */
6242                             if (*c == 'T')
6243                               ++value;
6244
6245                             if (c[1] == 'u')
6246                               {
6247                                 /* Eat the 'u' character.  */
6248                                 ++ c;
6249
6250                                 if (u_reg == value)
6251                                   is_unpredictable = TRUE;
6252                                 u_reg = value;
6253                               }
6254                             if (c[1] == 'U')
6255                               {
6256                                 /* Eat the 'U' character.  */
6257                                 ++ c;
6258
6259                                 if (U_reg == value)
6260                                   is_unpredictable = TRUE;
6261                                 U_reg = value;
6262                               }
6263                             func (stream, "%s", arm_regnames[value]);
6264                             break;
6265                           case 'd':
6266                             func (stream, "%ld", value);
6267                             value_in_comment = value;
6268                             break;
6269                           case 'b':
6270                             func (stream, "%ld", value * 8);
6271                             value_in_comment = value * 8;
6272                             break;
6273                           case 'W':
6274                             func (stream, "%ld", value + 1);
6275                             value_in_comment = value + 1;
6276                             break;
6277                           case 'x':
6278                             func (stream, "0x%08lx", value);
6279
6280                             /* Some SWI instructions have special
6281                                meanings.  */
6282                             if ((given & 0x0fffffff) == 0x0FF00000)
6283                               func (stream, "\t; IMB");
6284                             else if ((given & 0x0fffffff) == 0x0FF00001)
6285                               func (stream, "\t; IMBRange");
6286                             break;
6287                           case 'X':
6288                             func (stream, "%01lx", value & 0xf);
6289                             value_in_comment = value;
6290                             break;
6291                           case '`':
6292                             c++;
6293                             if (value == 0)
6294                               func (stream, "%c", *c);
6295                             break;
6296                           case '\'':
6297                             c++;
6298                             if (value == ((1ul << width) - 1))
6299                               func (stream, "%c", *c);
6300                             break;
6301                           case '?':
6302                             func (stream, "%c", c[(1 << width) - (int) value]);
6303                             c += 1 << width;
6304                             break;
6305                           default:
6306                             abort ();
6307                           }
6308                       }
6309                       break;
6310
6311                     case 'e':
6312                       {
6313                         int imm;
6314
6315                         imm = (given & 0xf) | ((given & 0xfff00) >> 4);
6316                         func (stream, "%d", imm);
6317                         value_in_comment = imm;
6318                       }
6319                       break;
6320
6321                     case 'E':
6322                       /* LSB and WIDTH fields of BFI or BFC.  The machine-
6323                          language instruction encodes LSB and MSB.  */
6324                       {
6325                         long msb = (given & 0x001f0000) >> 16;
6326                         long lsb = (given & 0x00000f80) >> 7;
6327                         long w = msb - lsb + 1;
6328
6329                         if (w > 0)
6330                           func (stream, "#%lu, #%lu", lsb, w);
6331                         else
6332                           func (stream, "(invalid: %lu:%lu)", lsb, msb);
6333                       }
6334                       break;
6335
6336                     case 'R':
6337                       /* Get the PSR/banked register name.  */
6338                       {
6339                         const char * name;
6340                         unsigned sysm = (given & 0x004f0000) >> 16;
6341
6342                         sysm |= (given & 0x300) >> 4;
6343                         name = banked_regname (sysm);
6344
6345                         if (name != NULL)
6346                           func (stream, "%s", name);
6347                         else
6348                           func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
6349                       }
6350                       break;
6351
6352                     case 'V':
6353                       /* 16-bit unsigned immediate from a MOVT or MOVW
6354                          instruction, encoded in bits 0:11 and 15:19.  */
6355                       {
6356                         long hi = (given & 0x000f0000) >> 4;
6357                         long lo = (given & 0x00000fff);
6358                         long imm16 = hi | lo;
6359
6360                         func (stream, "#%lu", imm16);
6361                         value_in_comment = imm16;
6362                       }
6363                       break;
6364
6365                     default:
6366                       abort ();
6367                     }
6368                 }
6369               else
6370                 func (stream, "%c", *c);
6371             }
6372
6373           if (value_in_comment > 32 || value_in_comment < -16)
6374             func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
6375
6376           if (is_unpredictable)
6377             func (stream, UNPREDICTABLE_INSTRUCTION);
6378
6379           return;
6380         }
6381     }
6382   func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
6383   return;
6384 }
6385
6386 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM.  */
6387
6388 static void
6389 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
6390 {
6391   const struct opcode16 *insn;
6392   void *stream = info->stream;
6393   fprintf_ftype func = info->fprintf_func;
6394
6395   for (insn = thumb_opcodes; insn->assembler; insn++)
6396     if ((given & insn->mask) == insn->value)
6397       {
6398         signed long value_in_comment = 0;
6399         const char *c = insn->assembler;
6400
6401         for (; *c; c++)
6402           {
6403             int domaskpc = 0;
6404             int domasklr = 0;
6405
6406             if (*c != '%')
6407               {
6408                 func (stream, "%c", *c);
6409                 continue;
6410               }
6411
6412             switch (*++c)
6413               {
6414               case '%':
6415                 func (stream, "%%");
6416                 break;
6417
6418               case 'c':
6419                 if (ifthen_state)
6420                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
6421                 break;
6422
6423               case 'C':
6424                 if (ifthen_state)
6425                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
6426                 else
6427                   func (stream, "s");
6428                 break;
6429
6430               case 'I':
6431                 {
6432                   unsigned int tmp;
6433
6434                   ifthen_next_state = given & 0xff;
6435                   for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
6436                     func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
6437                   func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
6438                 }
6439                 break;
6440
6441               case 'x':
6442                 if (ifthen_next_state)
6443                   func (stream, "\t; unpredictable branch in IT block\n");
6444                 break;
6445
6446               case 'X':
6447                 if (ifthen_state)
6448                   func (stream, "\t; unpredictable <IT:%s>",
6449                         arm_conditional[IFTHEN_COND]);
6450                 break;
6451
6452               case 'S':
6453                 {
6454                   long reg;
6455
6456                   reg = (given >> 3) & 0x7;
6457                   if (given & (1 << 6))
6458                     reg += 8;
6459
6460                   func (stream, "%s", arm_regnames[reg]);
6461                 }
6462                 break;
6463
6464               case 'D':
6465                 {
6466                   long reg;
6467
6468                   reg = given & 0x7;
6469                   if (given & (1 << 7))
6470                     reg += 8;
6471
6472                   func (stream, "%s", arm_regnames[reg]);
6473                 }
6474                 break;
6475
6476               case 'N':
6477                 if (given & (1 << 8))
6478                   domasklr = 1;
6479                 /* Fall through.  */
6480               case 'O':
6481                 if (*c == 'O' && (given & (1 << 8)))
6482                   domaskpc = 1;
6483                 /* Fall through.  */
6484               case 'M':
6485                 {
6486                   int started = 0;
6487                   int reg;
6488
6489                   func (stream, "{");
6490
6491                   /* It would be nice if we could spot
6492                      ranges, and generate the rS-rE format: */
6493                   for (reg = 0; (reg < 8); reg++)
6494                     if ((given & (1 << reg)) != 0)
6495                       {
6496                         if (started)
6497                           func (stream, ", ");
6498                         started = 1;
6499                         func (stream, "%s", arm_regnames[reg]);
6500                       }
6501
6502                   if (domasklr)
6503                     {
6504                       if (started)
6505                         func (stream, ", ");
6506                       started = 1;
6507                       func (stream, "%s", arm_regnames[14] /* "lr" */);
6508                     }
6509
6510                   if (domaskpc)
6511                     {
6512                       if (started)
6513                         func (stream, ", ");
6514                       func (stream, "%s", arm_regnames[15] /* "pc" */);
6515                     }
6516
6517                   func (stream, "}");
6518                 }
6519                 break;
6520
6521               case 'W':
6522                 /* Print writeback indicator for a LDMIA.  We are doing a
6523                    writeback if the base register is not in the register
6524                    mask.  */
6525                 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
6526                   func (stream, "!");
6527                 break;
6528
6529               case 'b':
6530                 /* Print ARM V6T2 CZB address: pc+4+6 bits.  */
6531                 {
6532                   bfd_vma address = (pc + 4
6533                                      + ((given & 0x00f8) >> 2)
6534                                      + ((given & 0x0200) >> 3));
6535                   info->print_address_func (address, info);
6536                 }
6537                 break;
6538
6539               case 's':
6540                 /* Right shift immediate -- bits 6..10; 1-31 print
6541                    as themselves, 0 prints as 32.  */
6542                 {
6543                   long imm = (given & 0x07c0) >> 6;
6544                   if (imm == 0)
6545                     imm = 32;
6546                   func (stream, "#%ld", imm);
6547                 }
6548                 break;
6549
6550               case '0': case '1': case '2': case '3': case '4':
6551               case '5': case '6': case '7': case '8': case '9':
6552                 {
6553                   int bitstart = *c++ - '0';
6554                   int bitend = 0;
6555
6556                   while (*c >= '0' && *c <= '9')
6557                     bitstart = (bitstart * 10) + *c++ - '0';
6558
6559                   switch (*c)
6560                     {
6561                     case '-':
6562                       {
6563                         bfd_vma reg;
6564
6565                         c++;
6566                         while (*c >= '0' && *c <= '9')
6567                           bitend = (bitend * 10) + *c++ - '0';
6568                         if (!bitend)
6569                           abort ();
6570                         reg = given >> bitstart;
6571                         reg &= (2 << (bitend - bitstart)) - 1;
6572
6573                         switch (*c)
6574                           {
6575                           case 'r':
6576                             func (stream, "%s", arm_regnames[reg]);
6577                             break;
6578
6579                           case 'd':
6580                             func (stream, "%ld", (long) reg);
6581                             value_in_comment = reg;
6582                             break;
6583
6584                           case 'H':
6585                             func (stream, "%ld", (long) (reg << 1));
6586                             value_in_comment = reg << 1;
6587                             break;
6588
6589                           case 'W':
6590                             func (stream, "%ld", (long) (reg << 2));
6591                             value_in_comment = reg << 2;
6592                             break;
6593
6594                           case 'a':
6595                             /* PC-relative address -- the bottom two
6596                                bits of the address are dropped
6597                                before the calculation.  */
6598                             info->print_address_func
6599                               (((pc + 4) & ~3) + (reg << 2), info);
6600                             value_in_comment = 0;
6601                             break;
6602
6603                           case 'x':
6604                             func (stream, "0x%04lx", (long) reg);
6605                             break;
6606
6607                           case 'B':
6608                             reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6609                             info->print_address_func (reg * 2 + pc + 4, info);
6610                             value_in_comment = 0;
6611                             break;
6612
6613                           case 'c':
6614                             func (stream, "%s", arm_conditional [reg]);
6615                             break;
6616
6617                           default:
6618                             abort ();
6619                           }
6620                       }
6621                       break;
6622
6623                     case '\'':
6624                       c++;
6625                       if ((given & (1 << bitstart)) != 0)
6626                         func (stream, "%c", *c);
6627                       break;
6628
6629                     case '?':
6630                       ++c;
6631                       if ((given & (1 << bitstart)) != 0)
6632                         func (stream, "%c", *c++);
6633                       else
6634                         func (stream, "%c", *++c);
6635                       break;
6636
6637                     default:
6638                       abort ();
6639                     }
6640                 }
6641                 break;
6642
6643               default:
6644                 abort ();
6645               }
6646           }
6647
6648         if (value_in_comment > 32 || value_in_comment < -16)
6649           func (stream, "\t; 0x%lx", value_in_comment);
6650         return;
6651       }
6652
6653   /* No match.  */
6654   func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
6655   return;
6656 }
6657
6658 /* Return the name of an V7M special register.  */
6659
6660 static const char *
6661 psr_name (int regno)
6662 {
6663   switch (regno)
6664     {
6665     case 0x0: return "APSR";
6666     case 0x1: return "IAPSR";
6667     case 0x2: return "EAPSR";
6668     case 0x3: return "PSR";
6669     case 0x5: return "IPSR";
6670     case 0x6: return "EPSR";
6671     case 0x7: return "IEPSR";
6672     case 0x8: return "MSP";
6673     case 0x9: return "PSP";
6674     case 0xa: return "MSPLIM";
6675     case 0xb: return "PSPLIM";
6676     case 0x10: return "PRIMASK";
6677     case 0x11: return "BASEPRI";
6678     case 0x12: return "BASEPRI_MAX";
6679     case 0x13: return "FAULTMASK";
6680     case 0x14: return "CONTROL";
6681     case 0x88: return "MSP_NS";
6682     case 0x89: return "PSP_NS";
6683     case 0x8a: return "MSPLIM_NS";
6684     case 0x8b: return "PSPLIM_NS";
6685     case 0x90: return "PRIMASK_NS";
6686     case 0x91: return "BASEPRI_NS";
6687     case 0x93: return "FAULTMASK_NS";
6688     case 0x94: return "CONTROL_NS";
6689     case 0x98: return "SP_NS";
6690     default: return "<unknown>";
6691     }
6692 }
6693
6694 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM.  */
6695
6696 static void
6697 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
6698 {
6699   const struct opcode32 *insn;
6700   void *stream = info->stream;
6701   fprintf_ftype func = info->fprintf_func;
6702   bfd_boolean is_mve = is_mve_architecture (info);
6703
6704   if (print_insn_coprocessor (pc, info, given, TRUE))
6705     return;
6706
6707   if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
6708     return;
6709
6710   if (is_mve && print_insn_mve (info, given))
6711     return;
6712
6713   for (insn = thumb32_opcodes; insn->assembler; insn++)
6714     if ((given & insn->mask) == insn->value)
6715       {
6716         bfd_boolean is_clrm = FALSE;
6717         bfd_boolean is_unpredictable = FALSE;
6718         signed long value_in_comment = 0;
6719         const char *c = insn->assembler;
6720
6721         for (; *c; c++)
6722           {
6723             if (*c != '%')
6724               {
6725                 func (stream, "%c", *c);
6726                 continue;
6727               }
6728
6729             switch (*++c)
6730               {
6731               case '%':
6732                 func (stream, "%%");
6733                 break;
6734
6735               case 'c':
6736                 if (ifthen_state)
6737                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
6738                 break;
6739
6740               case 'x':
6741                 if (ifthen_next_state)
6742                   func (stream, "\t; unpredictable branch in IT block\n");
6743                 break;
6744
6745               case 'X':
6746                 if (ifthen_state)
6747                   func (stream, "\t; unpredictable <IT:%s>",
6748                         arm_conditional[IFTHEN_COND]);
6749                 break;
6750
6751               case 'I':
6752                 {
6753                   unsigned int imm12 = 0;
6754
6755                   imm12 |= (given & 0x000000ffu);
6756                   imm12 |= (given & 0x00007000u) >> 4;
6757                   imm12 |= (given & 0x04000000u) >> 15;
6758                   func (stream, "#%u", imm12);
6759                   value_in_comment = imm12;
6760                 }
6761                 break;
6762
6763               case 'M':
6764                 {
6765                   unsigned int bits = 0, imm, imm8, mod;
6766
6767                   bits |= (given & 0x000000ffu);
6768                   bits |= (given & 0x00007000u) >> 4;
6769                   bits |= (given & 0x04000000u) >> 15;
6770                   imm8 = (bits & 0x0ff);
6771                   mod = (bits & 0xf00) >> 8;
6772                   switch (mod)
6773                     {
6774                     case 0: imm = imm8; break;
6775                     case 1: imm = ((imm8 << 16) | imm8); break;
6776                     case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
6777                     case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
6778                     default:
6779                       mod  = (bits & 0xf80) >> 7;
6780                       imm8 = (bits & 0x07f) | 0x80;
6781                       imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
6782                     }
6783                   func (stream, "#%u", imm);
6784                   value_in_comment = imm;
6785                 }
6786                 break;
6787
6788               case 'J':
6789                 {
6790                   unsigned int imm = 0;
6791
6792                   imm |= (given & 0x000000ffu);
6793                   imm |= (given & 0x00007000u) >> 4;
6794                   imm |= (given & 0x04000000u) >> 15;
6795                   imm |= (given & 0x000f0000u) >> 4;
6796                   func (stream, "#%u", imm);
6797                   value_in_comment = imm;
6798                 }
6799                 break;
6800
6801               case 'K':
6802                 {
6803                   unsigned int imm = 0;
6804
6805                   imm |= (given & 0x000f0000u) >> 16;
6806                   imm |= (given & 0x00000ff0u) >> 0;
6807                   imm |= (given & 0x0000000fu) << 12;
6808                   func (stream, "#%u", imm);
6809                   value_in_comment = imm;
6810                 }
6811                 break;
6812
6813               case 'H':
6814                 {
6815                   unsigned int imm = 0;
6816
6817                   imm |= (given & 0x000f0000u) >> 4;
6818                   imm |= (given & 0x00000fffu) >> 0;
6819                   func (stream, "#%u", imm);
6820                   value_in_comment = imm;
6821                 }
6822                 break;
6823
6824               case 'V':
6825                 {
6826                   unsigned int imm = 0;
6827
6828                   imm |= (given & 0x00000fffu);
6829                   imm |= (given & 0x000f0000u) >> 4;
6830                   func (stream, "#%u", imm);
6831                   value_in_comment = imm;
6832                 }
6833                 break;
6834
6835               case 'S':
6836                 {
6837                   unsigned int reg = (given & 0x0000000fu);
6838                   unsigned int stp = (given & 0x00000030u) >> 4;
6839                   unsigned int imm = 0;
6840                   imm |= (given & 0x000000c0u) >> 6;
6841                   imm |= (given & 0x00007000u) >> 10;
6842
6843                   func (stream, "%s", arm_regnames[reg]);
6844                   switch (stp)
6845                     {
6846                     case 0:
6847                       if (imm > 0)
6848                         func (stream, ", lsl #%u", imm);
6849                       break;
6850
6851                     case 1:
6852                       if (imm == 0)
6853                         imm = 32;
6854                       func (stream, ", lsr #%u", imm);
6855                       break;
6856
6857                     case 2:
6858                       if (imm == 0)
6859                         imm = 32;
6860                       func (stream, ", asr #%u", imm);
6861                       break;
6862
6863                     case 3:
6864                       if (imm == 0)
6865                         func (stream, ", rrx");
6866                       else
6867                         func (stream, ", ror #%u", imm);
6868                     }
6869                 }
6870                 break;
6871
6872               case 'a':
6873                 {
6874                   unsigned int Rn  = (given & 0x000f0000) >> 16;
6875                   unsigned int U   = ! NEGATIVE_BIT_SET;
6876                   unsigned int op  = (given & 0x00000f00) >> 8;
6877                   unsigned int i12 = (given & 0x00000fff);
6878                   unsigned int i8  = (given & 0x000000ff);
6879                   bfd_boolean writeback = FALSE, postind = FALSE;
6880                   bfd_vma offset = 0;
6881
6882                   func (stream, "[%s", arm_regnames[Rn]);
6883                   if (U) /* 12-bit positive immediate offset.  */
6884                     {
6885                       offset = i12;
6886                       if (Rn != 15)
6887                         value_in_comment = offset;
6888                     }
6889                   else if (Rn == 15) /* 12-bit negative immediate offset.  */
6890                     offset = - (int) i12;
6891                   else if (op == 0x0) /* Shifted register offset.  */
6892                     {
6893                       unsigned int Rm = (i8 & 0x0f);
6894                       unsigned int sh = (i8 & 0x30) >> 4;
6895
6896                       func (stream, ", %s", arm_regnames[Rm]);
6897                       if (sh)
6898                         func (stream, ", lsl #%u", sh);
6899                       func (stream, "]");
6900                       break;
6901                     }
6902                   else switch (op)
6903                     {
6904                     case 0xE:  /* 8-bit positive immediate offset.  */
6905                       offset = i8;
6906                       break;
6907
6908                     case 0xC:  /* 8-bit negative immediate offset.  */
6909                       offset = -i8;
6910                       break;
6911
6912                     case 0xF:  /* 8-bit + preindex with wb.  */
6913                       offset = i8;
6914                       writeback = TRUE;
6915                       break;
6916
6917                     case 0xD:  /* 8-bit - preindex with wb.  */
6918                       offset = -i8;
6919                       writeback = TRUE;
6920                       break;
6921
6922                     case 0xB:  /* 8-bit + postindex.  */
6923                       offset = i8;
6924                       postind = TRUE;
6925                       break;
6926
6927                     case 0x9:  /* 8-bit - postindex.  */
6928                       offset = -i8;
6929                       postind = TRUE;
6930                       break;
6931
6932                     default:
6933                       func (stream, ", <undefined>]");
6934                       goto skip;
6935                     }
6936
6937                   if (postind)
6938                     func (stream, "], #%d", (int) offset);
6939                   else
6940                     {
6941                       if (offset)
6942                         func (stream, ", #%d", (int) offset);
6943                       func (stream, writeback ? "]!" : "]");
6944                     }
6945
6946                   if (Rn == 15)
6947                     {
6948                       func (stream, "\t; ");
6949                       info->print_address_func (((pc + 4) & ~3) + offset, info);
6950                     }
6951                 }
6952               skip:
6953                 break;
6954
6955               case 'A':
6956                 {
6957                   unsigned int U   = ! NEGATIVE_BIT_SET;
6958                   unsigned int W   = WRITEBACK_BIT_SET;
6959                   unsigned int Rn  = (given & 0x000f0000) >> 16;
6960                   unsigned int off = (given & 0x000000ff);
6961
6962                   func (stream, "[%s", arm_regnames[Rn]);
6963
6964                   if (PRE_BIT_SET)
6965                     {
6966                       if (off || !U)
6967                         {
6968                           func (stream, ", #%c%u", U ? '+' : '-', off * 4);
6969                           value_in_comment = off * 4 * (U ? 1 : -1);
6970                         }
6971                       func (stream, "]");
6972                       if (W)
6973                         func (stream, "!");
6974                     }
6975                   else
6976                     {
6977                       func (stream, "], ");
6978                       if (W)
6979                         {
6980                           func (stream, "#%c%u", U ? '+' : '-', off * 4);
6981                           value_in_comment = off * 4 * (U ? 1 : -1);
6982                         }
6983                       else
6984                         {
6985                           func (stream, "{%u}", off);
6986                           value_in_comment = off;
6987                         }
6988                     }
6989                 }
6990                 break;
6991
6992               case 'w':
6993                 {
6994                   unsigned int Sbit = (given & 0x01000000) >> 24;
6995                   unsigned int type = (given & 0x00600000) >> 21;
6996
6997                   switch (type)
6998                     {
6999                     case 0: func (stream, Sbit ? "sb" : "b"); break;
7000                     case 1: func (stream, Sbit ? "sh" : "h"); break;
7001                     case 2:
7002                       if (Sbit)
7003                         func (stream, "??");
7004                       break;
7005                     case 3:
7006                       func (stream, "??");
7007                       break;
7008                     }
7009                 }
7010                 break;
7011
7012               case 'n':
7013                 is_clrm = TRUE;
7014                 /* Fall through.  */
7015               case 'm':
7016                 {
7017                   int started = 0;
7018                   int reg;
7019
7020                   func (stream, "{");
7021                   for (reg = 0; reg < 16; reg++)
7022                     if ((given & (1 << reg)) != 0)
7023                       {
7024                         if (started)
7025                           func (stream, ", ");
7026                         started = 1;
7027                         if (is_clrm && reg == 13)
7028                           func (stream, "(invalid: %s)", arm_regnames[reg]);
7029                         else if (is_clrm && reg == 15)
7030                           func (stream, "%s", "APSR");
7031                         else
7032                           func (stream, "%s", arm_regnames[reg]);
7033                       }
7034                   func (stream, "}");
7035                 }
7036                 break;
7037
7038               case 'E':
7039                 {
7040                   unsigned int msb = (given & 0x0000001f);
7041                   unsigned int lsb = 0;
7042
7043                   lsb |= (given & 0x000000c0u) >> 6;
7044                   lsb |= (given & 0x00007000u) >> 10;
7045                   func (stream, "#%u, #%u", lsb, msb - lsb + 1);
7046                 }
7047                 break;
7048
7049               case 'F':
7050                 {
7051                   unsigned int width = (given & 0x0000001f) + 1;
7052                   unsigned int lsb = 0;
7053
7054                   lsb |= (given & 0x000000c0u) >> 6;
7055                   lsb |= (given & 0x00007000u) >> 10;
7056                   func (stream, "#%u, #%u", lsb, width);
7057                 }
7058                 break;
7059
7060               case 'G':
7061                 {
7062                   unsigned int boff = (((given & 0x07800000) >> 23) << 1);
7063                   func (stream, "%x", boff);
7064                 }
7065                 break;
7066
7067               case 'W':
7068                 {
7069                   unsigned int immA = (given & 0x001f0000u) >> 16;
7070                   unsigned int immB = (given & 0x000007feu) >> 1;
7071                   unsigned int immC = (given & 0x00000800u) >> 11;
7072                   bfd_vma offset = 0;
7073
7074                   offset |= immA << 12;
7075                   offset |= immB << 2;
7076                   offset |= immC << 1;
7077                   /* Sign extend.  */
7078                   offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
7079
7080                   info->print_address_func (pc + 4 + offset, info);
7081                 }
7082                 break;
7083
7084               case 'Y':
7085                 {
7086                   unsigned int immA = (given & 0x007f0000u) >> 16;
7087                   unsigned int immB = (given & 0x000007feu) >> 1;
7088                   unsigned int immC = (given & 0x00000800u) >> 11;
7089                   bfd_vma offset = 0;
7090
7091                   offset |= immA << 12;
7092                   offset |= immB << 2;
7093                   offset |= immC << 1;
7094                   /* Sign extend.  */
7095                   offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
7096
7097                   info->print_address_func (pc + 4 + offset, info);
7098                 }
7099                 break;
7100
7101               case 'Z':
7102                 {
7103                   unsigned int immA = (given & 0x00010000u) >> 16;
7104                   unsigned int immB = (given & 0x000007feu) >> 1;
7105                   unsigned int immC = (given & 0x00000800u) >> 11;
7106                   bfd_vma offset = 0;
7107
7108                   offset |= immA << 12;
7109                   offset |= immB << 2;
7110                   offset |= immC << 1;
7111                   /* Sign extend.  */
7112                   offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
7113
7114                   info->print_address_func (pc + 4 + offset, info);
7115
7116                   unsigned int T    = (given & 0x00020000u) >> 17;
7117                   unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
7118                   unsigned int boffset   = (T == 1) ? 4 : 2;
7119                   func (stream, ", ");
7120                   func (stream, "%x", endoffset + boffset);
7121                 }
7122                 break;
7123
7124               case 'Q':
7125                 {
7126                   unsigned int immh = (given & 0x000007feu) >> 1;
7127                   unsigned int imml = (given & 0x00000800u) >> 11;
7128                   bfd_vma imm32 = 0;
7129
7130                   imm32 |= immh << 2;
7131                   imm32 |= imml << 1;
7132
7133                   info->print_address_func (pc + 4 + imm32, info);
7134                 }
7135                 break;
7136
7137               case 'P':
7138                 {
7139                   unsigned int immh = (given & 0x000007feu) >> 1;
7140                   unsigned int imml = (given & 0x00000800u) >> 11;
7141                   bfd_vma imm32 = 0;
7142
7143                   imm32 |= immh << 2;
7144                   imm32 |= imml << 1;
7145
7146                   info->print_address_func (pc + 4 - imm32, info);
7147                 }
7148                 break;
7149
7150               case 'b':
7151                 {
7152                   unsigned int S = (given & 0x04000000u) >> 26;
7153                   unsigned int J1 = (given & 0x00002000u) >> 13;
7154                   unsigned int J2 = (given & 0x00000800u) >> 11;
7155                   bfd_vma offset = 0;
7156
7157                   offset |= !S << 20;
7158                   offset |= J2 << 19;
7159                   offset |= J1 << 18;
7160                   offset |= (given & 0x003f0000) >> 4;
7161                   offset |= (given & 0x000007ff) << 1;
7162                   offset -= (1 << 20);
7163
7164                   info->print_address_func (pc + 4 + offset, info);
7165                 }
7166                 break;
7167
7168               case 'B':
7169                 {
7170                   unsigned int S = (given & 0x04000000u) >> 26;
7171                   unsigned int I1 = (given & 0x00002000u) >> 13;
7172                   unsigned int I2 = (given & 0x00000800u) >> 11;
7173                   bfd_vma offset = 0;
7174
7175                   offset |= !S << 24;
7176                   offset |= !(I1 ^ S) << 23;
7177                   offset |= !(I2 ^ S) << 22;
7178                   offset |= (given & 0x03ff0000u) >> 4;
7179                   offset |= (given & 0x000007ffu) << 1;
7180                   offset -= (1 << 24);
7181                   offset += pc + 4;
7182
7183                   /* BLX target addresses are always word aligned.  */
7184                   if ((given & 0x00001000u) == 0)
7185                       offset &= ~2u;
7186
7187                   info->print_address_func (offset, info);
7188                 }
7189                 break;
7190
7191               case 's':
7192                 {
7193                   unsigned int shift = 0;
7194
7195                   shift |= (given & 0x000000c0u) >> 6;
7196                   shift |= (given & 0x00007000u) >> 10;
7197                   if (WRITEBACK_BIT_SET)
7198                     func (stream, ", asr #%u", shift);
7199                   else if (shift)
7200                     func (stream, ", lsl #%u", shift);
7201                   /* else print nothing - lsl #0 */
7202                 }
7203                 break;
7204
7205               case 'R':
7206                 {
7207                   unsigned int rot = (given & 0x00000030) >> 4;
7208
7209                   if (rot)
7210                     func (stream, ", ror #%u", rot * 8);
7211                 }
7212                 break;
7213
7214               case 'U':
7215                 if ((given & 0xf0) == 0x60)
7216                   {
7217                     switch (given & 0xf)
7218                       {
7219                         case 0xf: func (stream, "sy"); break;
7220                         default:
7221                           func (stream, "#%d", (int) given & 0xf);
7222                               break;
7223                       }
7224                   }
7225                 else
7226                   {
7227                     const char * opt = data_barrier_option (given & 0xf);
7228                     if (opt != NULL)
7229                       func (stream, "%s", opt);
7230                     else
7231                       func (stream, "#%d", (int) given & 0xf);
7232                    }
7233                 break;
7234
7235               case 'C':
7236                 if ((given & 0xff) == 0)
7237                   {
7238                     func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
7239                     if (given & 0x800)
7240                       func (stream, "f");
7241                     if (given & 0x400)
7242                       func (stream, "s");
7243                     if (given & 0x200)
7244                       func (stream, "x");
7245                     if (given & 0x100)
7246                       func (stream, "c");
7247                   }
7248                 else if ((given & 0x20) == 0x20)
7249                   {
7250                     char const* name;
7251                     unsigned sysm = (given & 0xf00) >> 8;
7252
7253                     sysm |= (given & 0x30);
7254                     sysm |= (given & 0x00100000) >> 14;
7255                     name = banked_regname (sysm);
7256
7257                     if (name != NULL)
7258                       func (stream, "%s", name);
7259                     else
7260                       func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
7261                   }
7262                 else
7263                   {
7264                     func (stream, "%s", psr_name (given & 0xff));
7265                   }
7266                 break;
7267
7268               case 'D':
7269                 if (((given & 0xff) == 0)
7270                     || ((given & 0x20) == 0x20))
7271                   {
7272                     char const* name;
7273                     unsigned sm = (given & 0xf0000) >> 16;
7274
7275                     sm |= (given & 0x30);
7276                     sm |= (given & 0x00100000) >> 14;
7277                     name = banked_regname (sm);
7278
7279                     if (name != NULL)
7280                       func (stream, "%s", name);
7281                     else
7282                       func (stream, "(UNDEF: %lu)", (unsigned long) sm);
7283                   }
7284                 else
7285                   func (stream, "%s", psr_name (given & 0xff));
7286                 break;
7287
7288               case '0': case '1': case '2': case '3': case '4':
7289               case '5': case '6': case '7': case '8': case '9':
7290                 {
7291                   int width;
7292                   unsigned long val;
7293
7294                   c = arm_decode_bitfield (c, given, &val, &width);
7295
7296                   switch (*c)
7297                     {
7298                     case 'd':
7299                       func (stream, "%lu", val);
7300                       value_in_comment = val;
7301                       break;
7302
7303                     case 'D':
7304                       func (stream, "%lu", val + 1);
7305                       value_in_comment = val + 1;
7306                       break;
7307
7308                     case 'W':
7309                       func (stream, "%lu", val * 4);
7310                       value_in_comment = val * 4;
7311                       break;
7312
7313                     case 'S':
7314                       if (val == 13)
7315                         is_unpredictable = TRUE;
7316                       /* Fall through.  */
7317                     case 'R':
7318                       if (val == 15)
7319                         is_unpredictable = TRUE;
7320                       /* Fall through.  */
7321                     case 'r':
7322                       func (stream, "%s", arm_regnames[val]);
7323                       break;
7324
7325                     case 'c':
7326                       func (stream, "%s", arm_conditional[val]);
7327                       break;
7328
7329                     case '\'':
7330                       c++;
7331                       if (val == ((1ul << width) - 1))
7332                         func (stream, "%c", *c);
7333                       break;
7334
7335                     case '`':
7336                       c++;
7337                       if (val == 0)
7338                         func (stream, "%c", *c);
7339                       break;
7340
7341                     case '?':
7342                       func (stream, "%c", c[(1 << width) - (int) val]);
7343                       c += 1 << width;
7344                       break;
7345
7346                     case 'x':
7347                       func (stream, "0x%lx", val & 0xffffffffUL);
7348                       break;
7349
7350                     default:
7351                       abort ();
7352                     }
7353                 }
7354                 break;
7355
7356               case 'L':
7357                 /* PR binutils/12534
7358                    If we have a PC relative offset in an LDRD or STRD
7359                    instructions then display the decoded address.  */
7360                 if (((given >> 16) & 0xf) == 0xf)
7361                   {
7362                     bfd_vma offset = (given & 0xff) * 4;
7363
7364                     if ((given & (1 << 23)) == 0)
7365                       offset = - offset;
7366                     func (stream, "\t; ");
7367                     info->print_address_func ((pc & ~3) + 4 + offset, info);
7368                   }
7369                 break;
7370
7371               default:
7372                 abort ();
7373               }
7374           }
7375
7376         if (value_in_comment > 32 || value_in_comment < -16)
7377           func (stream, "\t; 0x%lx", value_in_comment);
7378
7379         if (is_unpredictable)
7380           func (stream, UNPREDICTABLE_INSTRUCTION);
7381
7382         return;
7383       }
7384
7385   /* No match.  */
7386   func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
7387   return;
7388 }
7389
7390 /* Print data bytes on INFO->STREAM.  */
7391
7392 static void
7393 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
7394                  struct disassemble_info *info,
7395                  long given)
7396 {
7397   switch (info->bytes_per_chunk)
7398     {
7399     case 1:
7400       info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
7401       break;
7402     case 2:
7403       info->fprintf_func (info->stream, ".short\t0x%04lx", given);
7404       break;
7405     case 4:
7406       info->fprintf_func (info->stream, ".word\t0x%08lx", given);
7407       break;
7408     default:
7409       abort ();
7410     }
7411 }
7412
7413 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
7414    being displayed in symbol relative addresses.
7415
7416    Also disallow private symbol, with __tagsym$$ prefix,
7417    from ARM RVCT toolchain being displayed.  */
7418
7419 bfd_boolean
7420 arm_symbol_is_valid (asymbol * sym,
7421                      struct disassemble_info * info ATTRIBUTE_UNUSED)
7422 {
7423   const char * name;
7424
7425   if (sym == NULL)
7426     return FALSE;
7427
7428   name = bfd_asymbol_name (sym);
7429
7430   return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
7431 }
7432
7433 /* Parse the string of disassembler options.  */
7434
7435 static void
7436 parse_arm_disassembler_options (const char *options)
7437 {
7438   const char *opt;
7439
7440   FOR_EACH_DISASSEMBLER_OPTION (opt, options)
7441     {
7442       if (CONST_STRNEQ (opt, "reg-names-"))
7443         {
7444           unsigned int i;
7445           for (i = 0; i < NUM_ARM_OPTIONS; i++)
7446             if (disassembler_options_cmp (opt, regnames[i].name) == 0)
7447               {
7448                 regname_selected = i;
7449                 break;
7450               }
7451
7452           if (i >= NUM_ARM_OPTIONS)
7453             /* xgettext: c-format */
7454             opcodes_error_handler (_("unrecognised register name set: %s"),
7455                                    opt);
7456         }
7457       else if (CONST_STRNEQ (opt, "force-thumb"))
7458         force_thumb = 1;
7459       else if (CONST_STRNEQ (opt, "no-force-thumb"))
7460         force_thumb = 0;
7461       else
7462         /* xgettext: c-format */
7463         opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
7464     }
7465
7466   return;
7467 }
7468
7469 static bfd_boolean
7470 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
7471                          enum map_type *map_symbol);
7472
7473 /* Search back through the insn stream to determine if this instruction is
7474    conditionally executed.  */
7475
7476 static void
7477 find_ifthen_state (bfd_vma pc,
7478                    struct disassemble_info *info,
7479                    bfd_boolean little)
7480 {
7481   unsigned char b[2];
7482   unsigned int insn;
7483   int status;
7484   /* COUNT is twice the number of instructions seen.  It will be odd if we
7485      just crossed an instruction boundary.  */
7486   int count;
7487   int it_count;
7488   unsigned int seen_it;
7489   bfd_vma addr;
7490
7491   ifthen_address = pc;
7492   ifthen_state = 0;
7493
7494   addr = pc;
7495   count = 1;
7496   it_count = 0;
7497   seen_it = 0;
7498   /* Scan backwards looking for IT instructions, keeping track of where
7499      instruction boundaries are.  We don't know if something is actually an
7500      IT instruction until we find a definite instruction boundary.  */
7501   for (;;)
7502     {
7503       if (addr == 0 || info->symbol_at_address_func (addr, info))
7504         {
7505           /* A symbol must be on an instruction boundary, and will not
7506              be within an IT block.  */
7507           if (seen_it && (count & 1))
7508             break;
7509
7510           return;
7511         }
7512       addr -= 2;
7513       status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
7514       if (status)
7515         return;
7516
7517       if (little)
7518         insn = (b[0]) | (b[1] << 8);
7519       else
7520         insn = (b[1]) | (b[0] << 8);
7521       if (seen_it)
7522         {
7523           if ((insn & 0xf800) < 0xe800)
7524             {
7525               /* Addr + 2 is an instruction boundary.  See if this matches
7526                  the expected boundary based on the position of the last
7527                  IT candidate.  */
7528               if (count & 1)
7529                 break;
7530               seen_it = 0;
7531             }
7532         }
7533       if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
7534         {
7535           enum map_type type = MAP_ARM;
7536           bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
7537
7538           if (!found || (found && type == MAP_THUMB))
7539             {
7540               /* This could be an IT instruction.  */
7541               seen_it = insn;
7542               it_count = count >> 1;
7543             }
7544         }
7545       if ((insn & 0xf800) >= 0xe800)
7546         count++;
7547       else
7548         count = (count + 2) | 1;
7549       /* IT blocks contain at most 4 instructions.  */
7550       if (count >= 8 && !seen_it)
7551         return;
7552     }
7553   /* We found an IT instruction.  */
7554   ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
7555   if ((ifthen_state & 0xf) == 0)
7556     ifthen_state = 0;
7557 }
7558
7559 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
7560    mapping symbol.  */
7561
7562 static int
7563 is_mapping_symbol (struct disassemble_info *info, int n,
7564                    enum map_type *map_type)
7565 {
7566   const char *name;
7567
7568   name = bfd_asymbol_name (info->symtab[n]);
7569   if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
7570       && (name[2] == 0 || name[2] == '.'))
7571     {
7572       *map_type = ((name[1] == 'a') ? MAP_ARM
7573                    : (name[1] == 't') ? MAP_THUMB
7574                    : MAP_DATA);
7575       return TRUE;
7576     }
7577
7578   return FALSE;
7579 }
7580
7581 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
7582    Returns nonzero if *MAP_TYPE was set.  */
7583
7584 static int
7585 get_map_sym_type (struct disassemble_info *info,
7586                   int n,
7587                   enum map_type *map_type)
7588 {
7589   /* If the symbol is in a different section, ignore it.  */
7590   if (info->section != NULL && info->section != info->symtab[n]->section)
7591     return FALSE;
7592
7593   return is_mapping_symbol (info, n, map_type);
7594 }
7595
7596 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
7597    Returns nonzero if *MAP_TYPE was set.  */
7598
7599 static int
7600 get_sym_code_type (struct disassemble_info *info,
7601                    int n,
7602                    enum map_type *map_type)
7603 {
7604   elf_symbol_type *es;
7605   unsigned int type;
7606
7607   /* If the symbol is in a different section, ignore it.  */
7608   if (info->section != NULL && info->section != info->symtab[n]->section)
7609     return FALSE;
7610
7611   es = *(elf_symbol_type **)(info->symtab + n);
7612   type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
7613
7614   /* If the symbol has function type then use that.  */
7615   if (type == STT_FUNC || type == STT_GNU_IFUNC)
7616     {
7617       if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
7618           == ST_BRANCH_TO_THUMB)
7619         *map_type = MAP_THUMB;
7620       else
7621         *map_type = MAP_ARM;
7622       return TRUE;
7623     }
7624
7625   return FALSE;
7626 }
7627
7628 /* Search the mapping symbol state for instruction at pc.  This is only
7629    applicable for elf target.
7630
7631    There is an assumption Here, info->private_data contains the correct AND
7632    up-to-date information about current scan process.  The information will be
7633    used to speed this search process.
7634
7635    Return TRUE if the mapping state can be determined, and map_symbol
7636    will be updated accordingly.  Otherwise, return FALSE.  */
7637
7638 static bfd_boolean
7639 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
7640                          enum map_type *map_symbol)
7641 {
7642   bfd_vma addr, section_vma = 0;
7643   int n, last_sym = -1;
7644   bfd_boolean found = FALSE;
7645   bfd_boolean can_use_search_opt_p = FALSE;
7646
7647   /* Default to DATA.  A text section is required by the ABI to contain an
7648      INSN mapping symbol at the start.  A data section has no such
7649      requirement, hence if no mapping symbol is found the section must
7650      contain only data.  This however isn't very useful if the user has
7651      fully stripped the binaries.  If this is the case use the section
7652      attributes to determine the default.  If we have no section default to
7653      INSN as well, as we may be disassembling some raw bytes on a baremetal
7654      HEX file or similar.  */
7655   enum map_type type = MAP_DATA;
7656   if ((info->section && info->section->flags & SEC_CODE) || !info->section)
7657     type = MAP_ARM;
7658   struct arm_private_data *private_data;
7659
7660   if (info->private_data == NULL
7661       || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
7662     return FALSE;
7663
7664   private_data = info->private_data;
7665
7666   /* First, look for mapping symbols.  */
7667   if (info->symtab_size != 0)
7668   {
7669     if (pc <= private_data->last_mapping_addr)
7670       private_data->last_mapping_sym = -1;
7671
7672     /* Start scanning at the start of the function, or wherever
7673        we finished last time.  */
7674     n = info->symtab_pos + 1;
7675
7676     /* If the last stop offset is different from the current one it means we
7677        are disassembling a different glob of bytes.  As such the optimization
7678        would not be safe and we should start over.  */
7679     can_use_search_opt_p
7680       = private_data->last_mapping_sym >= 0
7681         && info->stop_offset == private_data->last_stop_offset;
7682
7683     if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
7684       n = private_data->last_mapping_sym;
7685
7686     /* Look down while we haven't passed the location being disassembled.
7687        The reason for this is that there's no defined order between a symbol
7688        and an mapping symbol that may be at the same address.  We may have to
7689        look at least one position ahead.  */
7690     for (; n < info->symtab_size; n++)
7691       {
7692         addr = bfd_asymbol_value (info->symtab[n]);
7693         if (addr > pc)
7694           break;
7695         if (get_map_sym_type (info, n, &type))
7696           {
7697             last_sym = n;
7698             found = TRUE;
7699           }
7700       }
7701
7702     if (!found)
7703       {
7704         n = info->symtab_pos;
7705         if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
7706           n = private_data->last_mapping_sym;
7707
7708         /* No mapping symbol found at this address.  Look backwards
7709            for a preceeding one, but don't go pass the section start
7710            otherwise a data section with no mapping symbol can pick up
7711            a text mapping symbol of a preceeding section.  The documentation
7712            says section can be NULL, in which case we will seek up all the
7713            way to the top.  */
7714         if (info->section)
7715           section_vma = info->section->vma;
7716
7717         for (; n >= 0; n--)
7718           {
7719             addr = bfd_asymbol_value (info->symtab[n]);
7720             if (addr < section_vma)
7721               break;
7722
7723             if (get_map_sym_type (info, n, &type))
7724               {
7725                 last_sym = n;
7726                 found = TRUE;
7727                 break;
7728               }
7729           }
7730       }
7731   }
7732
7733   /* If no mapping symbol was found, try looking up without a mapping
7734      symbol.  This is done by walking up from the current PC to the nearest
7735      symbol.  We don't actually have to loop here since symtab_pos will
7736      contain the nearest symbol already.  */
7737   if (!found)
7738     {
7739       n = info->symtab_pos;
7740       if (n >= 0 && get_sym_code_type (info, n, &type))
7741         {
7742           last_sym = n;
7743           found = TRUE;
7744         }
7745     }
7746
7747   private_data->last_mapping_sym = last_sym;
7748   private_data->last_type = type;
7749   private_data->last_stop_offset = info->stop_offset;
7750
7751   *map_symbol = type;
7752   return found;
7753 }
7754
7755 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
7756    of the supplied arm_feature_set structure with bitmasks indicating
7757    the supported base architectures and coprocessor extensions.
7758
7759    FIXME: This could more efficiently implemented as a constant array,
7760    although it would also be less robust.  */
7761
7762 static void
7763 select_arm_features (unsigned long mach,
7764                      arm_feature_set * features)
7765 {
7766   arm_feature_set arch_fset;
7767   const arm_feature_set fpu_any = FPU_ANY;
7768
7769 #undef ARM_SET_FEATURES
7770 #define ARM_SET_FEATURES(FSET) \
7771   {                                                     \
7772     const arm_feature_set fset = FSET;                  \
7773     arch_fset = fset;                                   \
7774   }
7775
7776   /* When several architecture versions share the same bfd_mach_arm_XXX value
7777      the most featureful is chosen.  */
7778   switch (mach)
7779     {
7780     case bfd_mach_arm_2:         ARM_SET_FEATURES (ARM_ARCH_V2); break;
7781     case bfd_mach_arm_2a:        ARM_SET_FEATURES (ARM_ARCH_V2S); break;
7782     case bfd_mach_arm_3:         ARM_SET_FEATURES (ARM_ARCH_V3); break;
7783     case bfd_mach_arm_3M:        ARM_SET_FEATURES (ARM_ARCH_V3M); break;
7784     case bfd_mach_arm_4:         ARM_SET_FEATURES (ARM_ARCH_V4); break;
7785     case bfd_mach_arm_4T:        ARM_SET_FEATURES (ARM_ARCH_V4T); break;
7786     case bfd_mach_arm_5:         ARM_SET_FEATURES (ARM_ARCH_V5); break;
7787     case bfd_mach_arm_5T:        ARM_SET_FEATURES (ARM_ARCH_V5T); break;
7788     case bfd_mach_arm_5TE:       ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
7789     case bfd_mach_arm_XScale:    ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
7790     case bfd_mach_arm_ep9312:
7791         ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
7792                                            ARM_CEXT_MAVERICK | FPU_MAVERICK));
7793        break;
7794     case bfd_mach_arm_iWMMXt:    ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
7795     case bfd_mach_arm_iWMMXt2:   ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
7796     case bfd_mach_arm_5TEJ:      ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
7797     case bfd_mach_arm_6:         ARM_SET_FEATURES (ARM_ARCH_V6); break;
7798     case bfd_mach_arm_6KZ:       ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
7799     case bfd_mach_arm_6T2:       ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
7800     case bfd_mach_arm_6K:        ARM_SET_FEATURES (ARM_ARCH_V6K); break;
7801     case bfd_mach_arm_7:         ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
7802     case bfd_mach_arm_6M:        ARM_SET_FEATURES (ARM_ARCH_V6M); break;
7803     case bfd_mach_arm_6SM:       ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
7804     case bfd_mach_arm_7EM:       ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
7805     case bfd_mach_arm_8:
7806         {
7807           /* Add bits for extensions that Armv8.5-A recognizes.  */
7808           arm_feature_set armv8_5_ext_fset
7809             = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
7810           ARM_SET_FEATURES (ARM_ARCH_V8_5A);
7811           ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
7812           break;
7813         }
7814     case bfd_mach_arm_8R:        ARM_SET_FEATURES (ARM_ARCH_V8R); break;
7815     case bfd_mach_arm_8M_BASE:   ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
7816     case bfd_mach_arm_8M_MAIN:   ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
7817     case bfd_mach_arm_8_1M_MAIN:
7818       ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
7819       force_thumb = 1;
7820       break;
7821       /* If the machine type is unknown allow all architecture types and all
7822          extensions.  */
7823     case bfd_mach_arm_unknown:   ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
7824     default:
7825       abort ();
7826     }
7827 #undef ARM_SET_FEATURES
7828
7829   /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
7830      and thus on bfd_mach_arm_XXX value.  Therefore for a given
7831      bfd_mach_arm_XXX value all coprocessor feature bits should be allowed.  */
7832   ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
7833 }
7834
7835
7836 /* NOTE: There are no checks in these routines that
7837    the relevant number of data bytes exist.  */
7838
7839 static int
7840 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
7841 {
7842   unsigned char b[4];
7843   long          given;
7844   int           status;
7845   int           is_thumb = FALSE;
7846   int           is_data = FALSE;
7847   int           little_code;
7848   unsigned int  size = 4;
7849   void          (*printer) (bfd_vma, struct disassemble_info *, long);
7850   bfd_boolean   found = FALSE;
7851   struct arm_private_data *private_data;
7852
7853   if (info->disassembler_options)
7854     {
7855       parse_arm_disassembler_options (info->disassembler_options);
7856
7857       /* To avoid repeated parsing of these options, we remove them here.  */
7858       info->disassembler_options = NULL;
7859     }
7860
7861   /* PR 10288: Control which instructions will be disassembled.  */
7862   if (info->private_data == NULL)
7863     {
7864       static struct arm_private_data private;
7865
7866       if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
7867         /* If the user did not use the -m command line switch then default to
7868            disassembling all types of ARM instruction.
7869
7870            The info->mach value has to be ignored as this will be based on
7871            the default archictecture for the target and/or hints in the notes
7872            section, but it will never be greater than the current largest arm
7873            machine value (iWMMXt2), which is only equivalent to the V5TE
7874            architecture.  ARM architectures have advanced beyond the machine
7875            value encoding, and these newer architectures would be ignored if
7876            the machine value was used.
7877
7878            Ie the -m switch is used to restrict which instructions will be
7879            disassembled.  If it is necessary to use the -m switch to tell
7880            objdump that an ARM binary is being disassembled, eg because the
7881            input is a raw binary file, but it is also desired to disassemble
7882            all ARM instructions then use "-marm".  This will select the
7883            "unknown" arm architecture which is compatible with any ARM
7884            instruction.  */
7885           info->mach = bfd_mach_arm_unknown;
7886
7887       /* Compute the architecture bitmask from the machine number.
7888          Note: This assumes that the machine number will not change
7889          during disassembly....  */
7890       select_arm_features (info->mach, & private.features);
7891
7892       private.last_mapping_sym = -1;
7893       private.last_mapping_addr = 0;
7894       private.last_stop_offset = 0;
7895
7896       info->private_data = & private;
7897     }
7898
7899   private_data = info->private_data;
7900
7901   /* Decide if our code is going to be little-endian, despite what the
7902      function argument might say.  */
7903   little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
7904
7905   /* For ELF, consult the symbol table to determine what kind of code
7906      or data we have.  */
7907   if (info->symtab_size != 0
7908       && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
7909     {
7910       bfd_vma addr;
7911       int n;
7912       int last_sym = -1;
7913       enum map_type type = MAP_ARM;
7914
7915       found = mapping_symbol_for_insn (pc, info, &type);
7916       last_sym = private_data->last_mapping_sym;
7917
7918       is_thumb = (private_data->last_type == MAP_THUMB);
7919       is_data = (private_data->last_type == MAP_DATA);
7920
7921       /* Look a little bit ahead to see if we should print out
7922          two or four bytes of data.  If there's a symbol,
7923          mapping or otherwise, after two bytes then don't
7924          print more.  */
7925       if (is_data)
7926         {
7927           size = 4 - (pc & 3);
7928           for (n = last_sym + 1; n < info->symtab_size; n++)
7929             {
7930               addr = bfd_asymbol_value (info->symtab[n]);
7931               if (addr > pc
7932                   && (info->section == NULL
7933                       || info->section == info->symtab[n]->section))
7934                 {
7935                   if (addr - pc < size)
7936                     size = addr - pc;
7937                   break;
7938                 }
7939             }
7940           /* If the next symbol is after three bytes, we need to
7941              print only part of the data, so that we can use either
7942              .byte or .short.  */
7943           if (size == 3)
7944             size = (pc & 1) ? 1 : 2;
7945         }
7946     }
7947
7948   if (info->symbols != NULL)
7949     {
7950       if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
7951         {
7952           coff_symbol_type * cs;
7953
7954           cs = coffsymbol (*info->symbols);
7955           is_thumb = (   cs->native->u.syment.n_sclass == C_THUMBEXT
7956                       || cs->native->u.syment.n_sclass == C_THUMBSTAT
7957                       || cs->native->u.syment.n_sclass == C_THUMBLABEL
7958                       || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
7959                       || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
7960         }
7961       else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
7962                && !found)
7963         {
7964           /* If no mapping symbol has been found then fall back to the type
7965              of the function symbol.  */
7966           elf_symbol_type *  es;
7967           unsigned int       type;
7968
7969           es = *(elf_symbol_type **)(info->symbols);
7970           type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
7971
7972           is_thumb =
7973             ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
7974               == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
7975         }
7976       else if (bfd_asymbol_flavour (*info->symbols)
7977                == bfd_target_mach_o_flavour)
7978         {
7979           bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
7980
7981           is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
7982         }
7983     }
7984
7985   if (force_thumb)
7986     is_thumb = TRUE;
7987
7988   if (is_data)
7989     info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
7990   else
7991     info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
7992
7993   info->bytes_per_line = 4;
7994
7995   /* PR 10263: Disassemble data if requested to do so by the user.  */
7996   if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
7997     {
7998       int i;
7999
8000       /* Size was already set above.  */
8001       info->bytes_per_chunk = size;
8002       printer = print_insn_data;
8003
8004       status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
8005       given = 0;
8006       if (little)
8007         for (i = size - 1; i >= 0; i--)
8008           given = b[i] | (given << 8);
8009       else
8010         for (i = 0; i < (int) size; i++)
8011           given = b[i] | (given << 8);
8012     }
8013   else if (!is_thumb)
8014     {
8015       /* In ARM mode endianness is a straightforward issue: the instruction
8016          is four bytes long and is either ordered 0123 or 3210.  */
8017       printer = print_insn_arm;
8018       info->bytes_per_chunk = 4;
8019       size = 4;
8020
8021       status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
8022       if (little_code)
8023         given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
8024       else
8025         given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
8026     }
8027   else
8028     {
8029       /* In Thumb mode we have the additional wrinkle of two
8030          instruction lengths.  Fortunately, the bits that determine
8031          the length of the current instruction are always to be found
8032          in the first two bytes.  */
8033       printer = print_insn_thumb16;
8034       info->bytes_per_chunk = 2;
8035       size = 2;
8036
8037       status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
8038       if (little_code)
8039         given = (b[0]) | (b[1] << 8);
8040       else
8041         given = (b[1]) | (b[0] << 8);
8042
8043       if (!status)
8044         {
8045           /* These bit patterns signal a four-byte Thumb
8046              instruction.  */
8047           if ((given & 0xF800) == 0xF800
8048               || (given & 0xF800) == 0xF000
8049               || (given & 0xF800) == 0xE800)
8050             {
8051               status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
8052               if (little_code)
8053                 given = (b[0]) | (b[1] << 8) | (given << 16);
8054               else
8055                 given = (b[1]) | (b[0] << 8) | (given << 16);
8056
8057               printer = print_insn_thumb32;
8058               size = 4;
8059             }
8060         }
8061
8062       if (ifthen_address != pc)
8063         find_ifthen_state (pc, info, little_code);
8064
8065       if (ifthen_state)
8066         {
8067           if ((ifthen_state & 0xf) == 0x8)
8068             ifthen_next_state = 0;
8069           else
8070             ifthen_next_state = (ifthen_state & 0xe0)
8071                                 | ((ifthen_state & 0xf) << 1);
8072         }
8073     }
8074
8075   if (status)
8076     {
8077       info->memory_error_func (status, pc, info);
8078       return -1;
8079     }
8080   if (info->flags & INSN_HAS_RELOC)
8081     /* If the instruction has a reloc associated with it, then
8082        the offset field in the instruction will actually be the
8083        addend for the reloc.  (We are using REL type relocs).
8084        In such cases, we can ignore the pc when computing
8085        addresses, since the addend is not currently pc-relative.  */
8086     pc = 0;
8087
8088   printer (pc, info, given);
8089
8090   if (is_thumb)
8091     {
8092       ifthen_state = ifthen_next_state;
8093       ifthen_address += size;
8094     }
8095   return size;
8096 }
8097
8098 int
8099 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
8100 {
8101   /* Detect BE8-ness and record it in the disassembler info.  */
8102   if (info->flavour == bfd_target_elf_flavour
8103       && info->section != NULL
8104       && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
8105     info->endian_code = BFD_ENDIAN_LITTLE;
8106
8107   return print_insn (pc, info, FALSE);
8108 }
8109
8110 int
8111 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
8112 {
8113   return print_insn (pc, info, TRUE);
8114 }
8115
8116 const disasm_options_and_args_t *
8117 disassembler_options_arm (void)
8118 {
8119   static disasm_options_and_args_t *opts_and_args;
8120
8121   if (opts_and_args == NULL)
8122     {
8123       disasm_options_t *opts;
8124       unsigned int i;
8125
8126       opts_and_args = XNEW (disasm_options_and_args_t);
8127       opts_and_args->args = NULL;
8128
8129       opts = &opts_and_args->options;
8130       opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
8131       opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
8132       opts->arg = NULL;
8133       for (i = 0; i < NUM_ARM_OPTIONS; i++)
8134         {
8135           opts->name[i] = regnames[i].name;
8136           if (regnames[i].description != NULL)
8137             opts->description[i] = _(regnames[i].description);
8138           else
8139             opts->description[i] = NULL;
8140         }
8141       /* The array we return must be NULL terminated.  */
8142       opts->name[i] = NULL;
8143       opts->description[i] = NULL;
8144     }
8145
8146   return opts_and_args;
8147 }
8148
8149 void
8150 print_arm_disassembler_options (FILE *stream)
8151 {
8152   unsigned int i, max_len = 0;
8153   fprintf (stream, _("\n\
8154 The following ARM specific disassembler options are supported for use with\n\
8155 the -M switch:\n"));
8156
8157   for (i = 0; i < NUM_ARM_OPTIONS; i++)
8158     {
8159       unsigned int len = strlen (regnames[i].name);
8160       if (max_len < len)
8161         max_len = len;
8162     }
8163
8164   for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
8165     fprintf (stream, "  %s%*c %s\n",
8166              regnames[i].name,
8167              (int)(max_len - strlen (regnames[i].name)), ' ',
8168              _(regnames[i].description));
8169 }