1 /* Instruction printing code for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
5 Modification by James G. Smith (jsmith@cygnus.co.uk)
7 This file is part of libopcodes.
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
27 #include "opcode/arm.h"
29 #include "safe-ctype.h"
30 #include "floatformat.h"
32 /* FIXME: This shouldn't be done here. */
33 #include "coff/internal.h"
36 #include "elf/internal.h"
39 /* FIXME: Belongs in global header. */
41 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
45 #define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
48 struct arm_private_data
50 /* The features to use when disassembling optional instructions. */
51 arm_feature_set features;
53 /* Whether any mapping symbols are present in the provided symbol
54 table. -1 if we do not know yet, otherwise 0 or 1. */
55 int has_mapping_symbols;
60 unsigned long arch; /* Architecture defining this insn. */
61 unsigned long value; /* If arch == 0 then value is a sentinel. */
62 unsigned long mask; /* Recognise insn if (op & mask) == value. */
63 const char * assembler; /* How to disassemble this insn. */
68 unsigned long arch; /* Architecture defining this insn. */
69 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
70 const char *assembler; /* How to disassemble this insn. */
73 /* print_insn_coprocessor recognizes the following format control codes:
77 %c print condition code (always bits 28-31 in ARM mode)
78 %q print shifter argument
79 %u print condition code (unconditional in ARM mode)
80 %A print address for ldc/stc/ldf/stf instruction
81 %B print vstm/vldm register list
82 %I print cirrus signed shift immediate: bits 0..3|4..6
83 %F print the COUNT field of a LFM/SFM instruction.
84 %P print floating point precision in arithmetic insn
85 %Q print floating point precision in ldf/stf insn
86 %R print floating point rounding mode
88 %<bitfield>r print as an ARM register
89 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
90 %<bitfield>ru as %<>r but each u register must be unique.
91 %<bitfield>d print the bitfield in decimal
92 %<bitfield>k print immediate for VFPv3 conversion instruction
93 %<bitfield>x print the bitfield in hex
94 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
95 %<bitfield>f print a floating point constant if >7 else a
96 floating point register
97 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
98 %<bitfield>g print as an iWMMXt 64-bit register
99 %<bitfield>G print as an iWMMXt general purpose or control register
100 %<bitfield>D print as a NEON D register
101 %<bitfield>Q print as a NEON Q register
103 %y<code> print a single precision VFP reg.
104 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
105 %z<code> print a double precision VFP reg
106 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
108 %<bitfield>'c print specified char iff bitfield is all ones
109 %<bitfield>`c print specified char iff bitfield is all zeroes
110 %<bitfield>?ab... select from array of values in big endian order
112 %L print as an iWMMXt N/M width field.
113 %Z print the Immediate of a WSHUFH instruction.
114 %l like 'A' except use byte offsets for 'B' & 'H'
116 %i print 5-bit immediate in bits 8,3..0
118 %r print register offset address for wldt/wstr instruction. */
120 enum opcode_sentinel_enum
122 SENTINEL_IWMMXT_START = 1,
124 SENTINEL_GENERIC_START
127 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
128 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
130 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
132 static const struct opcode32 coprocessor_opcodes[] =
134 /* XScale instructions. */
135 {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"},
136 {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"},
137 {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
138 {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
139 {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
141 /* Intel Wireless MMX technology instructions. */
142 { 0, SENTINEL_IWMMXT_START, 0, "" },
143 {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
144 {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
145 {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
146 {ARM_CEXT_XSCALE, 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
147 {ARM_CEXT_XSCALE, 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
148 {ARM_CEXT_XSCALE, 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
149 {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
150 {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
151 {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
152 {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
153 {ARM_CEXT_XSCALE, 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
154 {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
155 {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
156 {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
157 {ARM_CEXT_XSCALE, 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
158 {ARM_CEXT_XSCALE, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
159 {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
160 {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
161 {ARM_CEXT_XSCALE, 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
162 {ARM_CEXT_XSCALE, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
163 {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
164 {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
165 {ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
166 {ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
167 {ARM_CEXT_XSCALE, 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
168 {ARM_CEXT_XSCALE, 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
169 {ARM_CEXT_XSCALE, 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
170 {ARM_CEXT_XSCALE, 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
171 {ARM_CEXT_XSCALE, 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
172 {ARM_CEXT_XSCALE, 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
173 {ARM_CEXT_XSCALE, 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
174 {ARM_CEXT_XSCALE, 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
175 {ARM_CEXT_XSCALE, 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
176 {ARM_CEXT_XSCALE, 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
177 {ARM_CEXT_XSCALE, 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
178 {ARM_CEXT_XSCALE, 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
179 {ARM_CEXT_XSCALE, 0x0e800120, 0x0f800ff0, "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
180 {ARM_CEXT_XSCALE, 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
181 {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
182 {ARM_CEXT_XSCALE, 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
183 {ARM_CEXT_XSCALE, 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
184 {ARM_CEXT_XSCALE, 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
185 {ARM_CEXT_XSCALE, 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
186 {ARM_CEXT_XSCALE, 0x0e8000a0, 0x0f800ff0, "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
187 {ARM_CEXT_XSCALE, 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
188 {ARM_CEXT_XSCALE, 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
189 {ARM_CEXT_XSCALE, 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
190 {ARM_CEXT_XSCALE, 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
191 {ARM_CEXT_XSCALE, 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
192 {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
193 {ARM_CEXT_XSCALE, 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
194 {ARM_CEXT_XSCALE, 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
195 {ARM_CEXT_XSCALE, 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
196 {ARM_CEXT_XSCALE, 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
197 {ARM_CEXT_XSCALE, 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
198 {ARM_CEXT_XSCALE, 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
199 {ARM_CEXT_XSCALE, 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
200 {ARM_CEXT_XSCALE, 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
201 {ARM_CEXT_XSCALE, 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
202 {ARM_CEXT_XSCALE, 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
203 {ARM_CEXT_XSCALE, 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
204 {ARM_CEXT_XSCALE, 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
205 {ARM_CEXT_XSCALE, 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
206 {ARM_CEXT_XSCALE, 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
207 {ARM_CEXT_XSCALE, 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
208 {ARM_CEXT_XSCALE, 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
209 {ARM_CEXT_XSCALE, 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
210 {ARM_CEXT_XSCALE, 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
211 {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
212 {ARM_CEXT_XSCALE, 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
213 {ARM_CEXT_XSCALE, 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
214 {ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
215 {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
216 {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
217 {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
218 { 0, SENTINEL_IWMMXT_END, 0, "" },
220 /* Floating point coprocessor (FPA) instructions. */
221 {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
222 {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
223 {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
224 {FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
225 {FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
226 {FPU_FPA_EXT_V1, 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
227 {FPU_FPA_EXT_V1, 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
228 {FPU_FPA_EXT_V1, 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
229 {FPU_FPA_EXT_V1, 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
230 {FPU_FPA_EXT_V1, 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
231 {FPU_FPA_EXT_V1, 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
232 {FPU_FPA_EXT_V1, 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
233 {FPU_FPA_EXT_V1, 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
234 {FPU_FPA_EXT_V1, 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
235 {FPU_FPA_EXT_V1, 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
236 {FPU_FPA_EXT_V1, 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
237 {FPU_FPA_EXT_V1, 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
238 {FPU_FPA_EXT_V1, 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
239 {FPU_FPA_EXT_V1, 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
240 {FPU_FPA_EXT_V1, 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
241 {FPU_FPA_EXT_V1, 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
242 {FPU_FPA_EXT_V1, 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
243 {FPU_FPA_EXT_V1, 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
244 {FPU_FPA_EXT_V1, 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
245 {FPU_FPA_EXT_V1, 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
246 {FPU_FPA_EXT_V1, 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
247 {FPU_FPA_EXT_V1, 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
248 {FPU_FPA_EXT_V1, 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
249 {FPU_FPA_EXT_V1, 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
250 {FPU_FPA_EXT_V1, 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
251 {FPU_FPA_EXT_V1, 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
252 {FPU_FPA_EXT_V1, 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
253 {FPU_FPA_EXT_V1, 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
254 {FPU_FPA_EXT_V1, 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
255 {FPU_FPA_EXT_V1, 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
256 {FPU_FPA_EXT_V1, 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
257 {FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
258 {FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
259 {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
260 {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
261 {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
262 {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
263 {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
265 /* Register load/store. */
266 {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
267 {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
268 {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
269 {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
270 {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
271 {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
272 {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
273 {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
274 {FPU_VFP_EXT_V1xD, 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
275 {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
276 {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
277 {FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
278 {FPU_VFP_EXT_V1xD, 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
279 {FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
280 {FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
281 {FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
283 {FPU_VFP_EXT_V1xD, 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
284 {FPU_VFP_EXT_V1xD, 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
285 {FPU_VFP_EXT_V1xD, 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
286 {FPU_VFP_EXT_V1xD, 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
288 /* Data transfer between ARM and NEON registers. */
289 {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
290 {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
291 {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
292 {FPU_NEON_EXT_V1, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
293 {FPU_NEON_EXT_V1, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
294 {FPU_NEON_EXT_V1, 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
295 {FPU_NEON_EXT_V1, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
296 {FPU_NEON_EXT_V1, 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
297 {FPU_NEON_EXT_V1, 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
298 {FPU_NEON_EXT_V1, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
299 {FPU_NEON_EXT_V1, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
300 {FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
301 {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
302 {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
303 /* Half-precision conversion instructions. */
304 {FPU_VFP_EXT_FP16, 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
305 {FPU_VFP_EXT_FP16, 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
307 /* Floating point coprocessor (VFP) instructions. */
308 {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
309 {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
310 {FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
311 {FPU_VFP_EXT_V1xD, 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
312 {FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
313 {FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
314 {FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
315 {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
316 {FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
317 {FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
318 {FPU_VFP_EXT_V1xD, 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
319 {FPU_VFP_EXT_V1xD, 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
320 {FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
321 {FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
322 {FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
323 {FPU_VFP_EXT_V1, 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
324 {FPU_VFP_EXT_V1, 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
325 {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
326 {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
327 {FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
328 {FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
329 {FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
330 {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
331 {FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
332 {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
333 {FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
334 {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
335 {FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
336 {FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
337 {FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
338 {FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
339 {FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
340 {FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
341 {FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
342 {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
343 {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
344 {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
345 {FPU_VFP_EXT_V3xD, 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
346 {FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
347 {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
348 {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
349 {FPU_VFP_EXT_V3xD, 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
350 {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
351 {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
352 {FPU_VFP_EXT_V3xD, 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19d"},
353 {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19d"},
354 {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
355 {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
356 {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
357 {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
358 {FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
359 {FPU_VFP_EXT_V1, 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
360 {FPU_VFP_EXT_V1, 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
361 {FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
362 {FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
363 {FPU_VFP_EXT_V1, 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
364 {FPU_VFP_EXT_V1, 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
365 {FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
366 {FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
367 {FPU_VFP_EXT_V1, 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
368 {FPU_VFP_EXT_V1, 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
369 {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
370 {FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
371 {FPU_VFP_EXT_V1, 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
372 {FPU_VFP_EXT_V1, 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
373 {FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
374 {FPU_VFP_EXT_V1, 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
376 /* Cirrus coprocessor instructions. */
377 {ARM_CEXT_MAVERICK, 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
378 {ARM_CEXT_MAVERICK, 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
379 {ARM_CEXT_MAVERICK, 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
380 {ARM_CEXT_MAVERICK, 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
381 {ARM_CEXT_MAVERICK, 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
382 {ARM_CEXT_MAVERICK, 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
383 {ARM_CEXT_MAVERICK, 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
384 {ARM_CEXT_MAVERICK, 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
385 {ARM_CEXT_MAVERICK, 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
386 {ARM_CEXT_MAVERICK, 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
387 {ARM_CEXT_MAVERICK, 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
388 {ARM_CEXT_MAVERICK, 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
389 {ARM_CEXT_MAVERICK, 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
390 {ARM_CEXT_MAVERICK, 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
391 {ARM_CEXT_MAVERICK, 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
392 {ARM_CEXT_MAVERICK, 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
393 {ARM_CEXT_MAVERICK, 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
394 {ARM_CEXT_MAVERICK, 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
395 {ARM_CEXT_MAVERICK, 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
396 {ARM_CEXT_MAVERICK, 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
397 {ARM_CEXT_MAVERICK, 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
398 {ARM_CEXT_MAVERICK, 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
399 {ARM_CEXT_MAVERICK, 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
400 {ARM_CEXT_MAVERICK, 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
401 {ARM_CEXT_MAVERICK, 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
402 {ARM_CEXT_MAVERICK, 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
403 {ARM_CEXT_MAVERICK, 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
404 {ARM_CEXT_MAVERICK, 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
405 {ARM_CEXT_MAVERICK, 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
406 {ARM_CEXT_MAVERICK, 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
407 {ARM_CEXT_MAVERICK, 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
408 {ARM_CEXT_MAVERICK, 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
409 {ARM_CEXT_MAVERICK, 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
410 {ARM_CEXT_MAVERICK, 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
411 {ARM_CEXT_MAVERICK, 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
412 {ARM_CEXT_MAVERICK, 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
413 {ARM_CEXT_MAVERICK, 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
414 {ARM_CEXT_MAVERICK, 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
415 {ARM_CEXT_MAVERICK, 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
416 {ARM_CEXT_MAVERICK, 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
417 {ARM_CEXT_MAVERICK, 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
418 {ARM_CEXT_MAVERICK, 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
419 {ARM_CEXT_MAVERICK, 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
420 {ARM_CEXT_MAVERICK, 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
421 {ARM_CEXT_MAVERICK, 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
422 {ARM_CEXT_MAVERICK, 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
423 {ARM_CEXT_MAVERICK, 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
424 {ARM_CEXT_MAVERICK, 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
425 {ARM_CEXT_MAVERICK, 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
426 {ARM_CEXT_MAVERICK, 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
427 {ARM_CEXT_MAVERICK, 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
428 {ARM_CEXT_MAVERICK, 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
429 {ARM_CEXT_MAVERICK, 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
430 {ARM_CEXT_MAVERICK, 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
431 {ARM_CEXT_MAVERICK, 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
432 {ARM_CEXT_MAVERICK, 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
433 {ARM_CEXT_MAVERICK, 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
434 {ARM_CEXT_MAVERICK, 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
435 {ARM_CEXT_MAVERICK, 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
436 {ARM_CEXT_MAVERICK, 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
437 {ARM_CEXT_MAVERICK, 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
438 {ARM_CEXT_MAVERICK, 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
439 {ARM_CEXT_MAVERICK, 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
440 {ARM_CEXT_MAVERICK, 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
441 {ARM_CEXT_MAVERICK, 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
442 {ARM_CEXT_MAVERICK, 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
443 {ARM_CEXT_MAVERICK, 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
444 {ARM_CEXT_MAVERICK, 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
445 {ARM_CEXT_MAVERICK, 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
446 {ARM_CEXT_MAVERICK, 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
447 {ARM_CEXT_MAVERICK, 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
448 {ARM_CEXT_MAVERICK, 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
449 {ARM_CEXT_MAVERICK, 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
450 {ARM_CEXT_MAVERICK, 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
451 {ARM_CEXT_MAVERICK, 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
452 {ARM_CEXT_MAVERICK, 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
453 {ARM_CEXT_MAVERICK, 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
454 {ARM_CEXT_MAVERICK, 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
455 {ARM_CEXT_MAVERICK, 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
456 {ARM_CEXT_MAVERICK, 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
457 {ARM_CEXT_MAVERICK, 0x0e000600, 0x0ff00f10, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
458 {ARM_CEXT_MAVERICK, 0x0e100600, 0x0ff00f10, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
459 {ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
460 {ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
462 /* VFP Fused multiply add instructions. */
463 {FPU_VFP_EXT_FMA, 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
464 {FPU_VFP_EXT_FMA, 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
465 {FPU_VFP_EXT_FMA, 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
466 {FPU_VFP_EXT_FMA, 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
467 {FPU_VFP_EXT_FMA, 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
468 {FPU_VFP_EXT_FMA, 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
469 {FPU_VFP_EXT_FMA, 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
470 {FPU_VFP_EXT_FMA, 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
472 /* Generic coprocessor instructions. */
473 { 0, SENTINEL_GENERIC_START, 0, "" },
474 {ARM_EXT_V5E, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
475 {ARM_EXT_V5E, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
476 {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
477 {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
478 {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
479 {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
480 {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
482 /* V6 coprocessor instructions. */
483 {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
484 {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
486 /* V5 coprocessor instructions. */
487 {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
488 {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
489 {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
490 {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
491 {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
496 /* Neon opcode table: This does not encode the top byte -- that is
497 checked by the print_insn_neon routine, as it depends on whether we are
498 doing thumb32 or arm32 disassembly. */
500 /* print_insn_neon recognizes the following format control codes:
504 %c print condition code
505 %A print v{st,ld}[1234] operands
506 %B print v{st,ld}[1234] any one operands
507 %C print v{st,ld}[1234] single->all operands
509 %E print vmov, vmvn, vorr, vbic encoded constant
510 %F print vtbl,vtbx register list
512 %<bitfield>r print as an ARM register
513 %<bitfield>d print the bitfield in decimal
514 %<bitfield>e print the 2^N - bitfield in decimal
515 %<bitfield>D print as a NEON D register
516 %<bitfield>Q print as a NEON Q register
517 %<bitfield>R print as a NEON D or Q register
518 %<bitfield>Sn print byte scaled width limited by n
519 %<bitfield>Tn print short scaled width limited by n
520 %<bitfield>Un print long scaled width limited by n
522 %<bitfield>'c print specified char iff bitfield is all ones
523 %<bitfield>`c print specified char iff bitfield is all zeroes
524 %<bitfield>?ab... select from array of values in big endian order. */
526 static const struct opcode32 neon_opcodes[] =
529 {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
530 {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
532 /* Move data element to all lanes. */
533 {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
534 {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
535 {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
538 {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
539 {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
541 /* Half-precision conversions. */
542 {FPU_VFP_EXT_FP16, 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
543 {FPU_VFP_EXT_FP16, 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
545 /* NEON fused multiply add instructions. */
546 {FPU_NEON_EXT_FMA, 0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
547 {FPU_NEON_EXT_FMA, 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
549 /* Two registers, miscellaneous. */
550 {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
551 {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
552 {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
553 {FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
554 {FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
555 {FPU_NEON_EXT_V1, 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
556 {FPU_NEON_EXT_V1, 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
557 {FPU_NEON_EXT_V1, 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
558 {FPU_NEON_EXT_V1, 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
559 {FPU_NEON_EXT_V1, 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
560 {FPU_NEON_EXT_V1, 0xf3b20300, 0xffb30fd0, "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
561 {FPU_NEON_EXT_V1, 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
562 {FPU_NEON_EXT_V1, 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
563 {FPU_NEON_EXT_V1, 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
564 {FPU_NEON_EXT_V1, 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
565 {FPU_NEON_EXT_V1, 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
566 {FPU_NEON_EXT_V1, 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
567 {FPU_NEON_EXT_V1, 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
568 {FPU_NEON_EXT_V1, 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
569 {FPU_NEON_EXT_V1, 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
570 {FPU_NEON_EXT_V1, 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
571 {FPU_NEON_EXT_V1, 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
572 {FPU_NEON_EXT_V1, 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
573 {FPU_NEON_EXT_V1, 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
574 {FPU_NEON_EXT_V1, 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
575 {FPU_NEON_EXT_V1, 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
576 {FPU_NEON_EXT_V1, 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
577 {FPU_NEON_EXT_V1, 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
578 {FPU_NEON_EXT_V1, 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
579 {FPU_NEON_EXT_V1, 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
580 {FPU_NEON_EXT_V1, 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
581 {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
582 {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
584 /* Three registers of the same length. */
585 {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
586 {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
587 {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
588 {FPU_NEON_EXT_V1, 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
589 {FPU_NEON_EXT_V1, 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
590 {FPU_NEON_EXT_V1, 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
591 {FPU_NEON_EXT_V1, 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
592 {FPU_NEON_EXT_V1, 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
593 {FPU_NEON_EXT_V1, 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
594 {FPU_NEON_EXT_V1, 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
595 {FPU_NEON_EXT_V1, 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
596 {FPU_NEON_EXT_V1, 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
597 {FPU_NEON_EXT_V1, 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
598 {FPU_NEON_EXT_V1, 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
599 {FPU_NEON_EXT_V1, 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
600 {FPU_NEON_EXT_V1, 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
601 {FPU_NEON_EXT_V1, 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
602 {FPU_NEON_EXT_V1, 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
603 {FPU_NEON_EXT_V1, 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
604 {FPU_NEON_EXT_V1, 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
605 {FPU_NEON_EXT_V1, 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
606 {FPU_NEON_EXT_V1, 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
607 {FPU_NEON_EXT_V1, 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
608 {FPU_NEON_EXT_V1, 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
609 {FPU_NEON_EXT_V1, 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
610 {FPU_NEON_EXT_V1, 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
611 {FPU_NEON_EXT_V1, 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
612 {FPU_NEON_EXT_V1, 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
613 {FPU_NEON_EXT_V1, 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
614 {FPU_NEON_EXT_V1, 0xf2000b00, 0xff800f10, "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
615 {FPU_NEON_EXT_V1, 0xf2000b10, 0xff800f10, "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
616 {FPU_NEON_EXT_V1, 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
617 {FPU_NEON_EXT_V1, 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
618 {FPU_NEON_EXT_V1, 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
619 {FPU_NEON_EXT_V1, 0xf3000b00, 0xff800f10, "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
620 {FPU_NEON_EXT_V1, 0xf2000000, 0xfe800f10, "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
621 {FPU_NEON_EXT_V1, 0xf2000010, 0xfe800f10, "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
622 {FPU_NEON_EXT_V1, 0xf2000100, 0xfe800f10, "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
623 {FPU_NEON_EXT_V1, 0xf2000200, 0xfe800f10, "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
624 {FPU_NEON_EXT_V1, 0xf2000210, 0xfe800f10, "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
625 {FPU_NEON_EXT_V1, 0xf2000300, 0xfe800f10, "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
626 {FPU_NEON_EXT_V1, 0xf2000310, 0xfe800f10, "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
627 {FPU_NEON_EXT_V1, 0xf2000400, 0xfe800f10, "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
628 {FPU_NEON_EXT_V1, 0xf2000410, 0xfe800f10, "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
629 {FPU_NEON_EXT_V1, 0xf2000500, 0xfe800f10, "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
630 {FPU_NEON_EXT_V1, 0xf2000510, 0xfe800f10, "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
631 {FPU_NEON_EXT_V1, 0xf2000600, 0xfe800f10, "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
632 {FPU_NEON_EXT_V1, 0xf2000610, 0xfe800f10, "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
633 {FPU_NEON_EXT_V1, 0xf2000700, 0xfe800f10, "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
634 {FPU_NEON_EXT_V1, 0xf2000710, 0xfe800f10, "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
635 {FPU_NEON_EXT_V1, 0xf2000910, 0xfe800f10, "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
636 {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
637 {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
639 /* One register and an immediate value. */
640 {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
641 {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
642 {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
643 {FPU_NEON_EXT_V1, 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
644 {FPU_NEON_EXT_V1, 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
645 {FPU_NEON_EXT_V1, 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
646 {FPU_NEON_EXT_V1, 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
647 {FPU_NEON_EXT_V1, 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
648 {FPU_NEON_EXT_V1, 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
649 {FPU_NEON_EXT_V1, 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
650 {FPU_NEON_EXT_V1, 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
651 {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
652 {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
654 /* Two registers and a shift amount. */
655 {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
656 {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
657 {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
658 {FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
659 {FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
660 {FPU_NEON_EXT_V1, 0xf2880950, 0xfeb80fd0, "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
661 {FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22D, %0-3,5Q, #%16-18d"},
662 {FPU_NEON_EXT_V1, 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
663 {FPU_NEON_EXT_V1, 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
664 {FPU_NEON_EXT_V1, 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
665 {FPU_NEON_EXT_V1, 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
666 {FPU_NEON_EXT_V1, 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
667 {FPU_NEON_EXT_V1, 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
668 {FPU_NEON_EXT_V1, 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
669 {FPU_NEON_EXT_V1, 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
670 {FPU_NEON_EXT_V1, 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
671 {FPU_NEON_EXT_V1, 0xf2900950, 0xfeb00fd0, "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
672 {FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-19d"},
673 {FPU_NEON_EXT_V1, 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
674 {FPU_NEON_EXT_V1, 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
675 {FPU_NEON_EXT_V1, 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
676 {FPU_NEON_EXT_V1, 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
677 {FPU_NEON_EXT_V1, 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
678 {FPU_NEON_EXT_V1, 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
679 {FPU_NEON_EXT_V1, 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
680 {FPU_NEON_EXT_V1, 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
681 {FPU_NEON_EXT_V1, 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
682 {FPU_NEON_EXT_V1, 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
683 {FPU_NEON_EXT_V1, 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
684 {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-20d"},
685 {FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
686 {FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
687 {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
688 {FPU_NEON_EXT_V1, 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
689 {FPU_NEON_EXT_V1, 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
690 {FPU_NEON_EXT_V1, 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
691 {FPU_NEON_EXT_V1, 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
692 {FPU_NEON_EXT_V1, 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
693 {FPU_NEON_EXT_V1, 0xf2a00950, 0xfea00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
694 {FPU_NEON_EXT_V1, 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
695 {FPU_NEON_EXT_V1, 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
696 {FPU_NEON_EXT_V1, 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
697 {FPU_NEON_EXT_V1, 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
698 {FPU_NEON_EXT_V1, 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
699 {FPU_NEON_EXT_V1, 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
700 {FPU_NEON_EXT_V1, 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
701 {FPU_NEON_EXT_V1, 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
702 {FPU_NEON_EXT_V1, 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
703 {FPU_NEON_EXT_V1, 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
704 {FPU_NEON_EXT_V1, 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
705 {FPU_NEON_EXT_V1, 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
706 {FPU_NEON_EXT_V1, 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
707 {FPU_NEON_EXT_V1, 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
708 {FPU_NEON_EXT_V1, 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
709 {FPU_NEON_EXT_V1, 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
710 {FPU_NEON_EXT_V1, 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
711 {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
712 {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
714 /* Three registers of different lengths. */
715 {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
716 {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
717 {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
718 {FPU_NEON_EXT_V1, 0xf2800900, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
719 {FPU_NEON_EXT_V1, 0xf2800b00, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
720 {FPU_NEON_EXT_V1, 0xf2800d00, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
721 {FPU_NEON_EXT_V1, 0xf3800400, 0xff800f50, "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
722 {FPU_NEON_EXT_V1, 0xf3800600, 0xff800f50, "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
723 {FPU_NEON_EXT_V1, 0xf2800000, 0xfe800f50, "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
724 {FPU_NEON_EXT_V1, 0xf2800100, 0xfe800f50, "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
725 {FPU_NEON_EXT_V1, 0xf2800200, 0xfe800f50, "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
726 {FPU_NEON_EXT_V1, 0xf2800300, 0xfe800f50, "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
727 {FPU_NEON_EXT_V1, 0xf2800500, 0xfe800f50, "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
728 {FPU_NEON_EXT_V1, 0xf2800700, 0xfe800f50, "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
729 {FPU_NEON_EXT_V1, 0xf2800800, 0xfe800f50, "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
730 {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
731 {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
733 /* Two registers and a scalar. */
734 {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
735 {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
736 {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
737 {FPU_NEON_EXT_V1, 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
738 {FPU_NEON_EXT_V1, 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
739 {FPU_NEON_EXT_V1, 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
740 {FPU_NEON_EXT_V1, 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
741 {FPU_NEON_EXT_V1, 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
742 {FPU_NEON_EXT_V1, 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
743 {FPU_NEON_EXT_V1, 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
744 {FPU_NEON_EXT_V1, 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
745 {FPU_NEON_EXT_V1, 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
746 {FPU_NEON_EXT_V1, 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
747 {FPU_NEON_EXT_V1, 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
748 {FPU_NEON_EXT_V1, 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
749 {FPU_NEON_EXT_V1, 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
750 {FPU_NEON_EXT_V1, 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
751 {FPU_NEON_EXT_V1, 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
752 {FPU_NEON_EXT_V1, 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
753 {FPU_NEON_EXT_V1, 0xf2800240, 0xfe800f50, "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
754 {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
755 {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
757 /* Element and structure load/store. */
758 {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
759 {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
760 {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
761 {FPU_NEON_EXT_V1, 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
762 {FPU_NEON_EXT_V1, 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
763 {FPU_NEON_EXT_V1, 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
764 {FPU_NEON_EXT_V1, 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
765 {FPU_NEON_EXT_V1, 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
766 {FPU_NEON_EXT_V1, 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
767 {FPU_NEON_EXT_V1, 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
768 {FPU_NEON_EXT_V1, 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
769 {FPU_NEON_EXT_V1, 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
770 {FPU_NEON_EXT_V1, 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
771 {FPU_NEON_EXT_V1, 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
772 {FPU_NEON_EXT_V1, 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
773 {FPU_NEON_EXT_V1, 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
774 {FPU_NEON_EXT_V1, 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
775 {FPU_NEON_EXT_V1, 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
776 {FPU_NEON_EXT_V1, 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
781 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
782 ordered: they must be searched linearly from the top to obtain a correct
785 /* print_insn_arm recognizes the following format control codes:
789 %a print address for ldr/str instruction
790 %s print address for ldr/str halfword/signextend instruction
791 %S like %s but allow UNPREDICTABLE addressing
792 %b print branch destination
793 %c print condition code (always bits 28-31)
794 %m print register mask for ldm/stm instruction
795 %o print operand2 (immediate or register + shift)
796 %p print 'p' iff bits 12-15 are 15
797 %t print 't' iff bit 21 set and bit 24 clear
798 %B print arm BLX(1) destination
799 %C print the PSR sub type.
800 %U print barrier type.
801 %P print address for pli instruction.
803 %<bitfield>r print as an ARM register
804 %<bitfield>R as %r but r15 is UNPREDICTABLE
805 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
806 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
807 %<bitfield>d print the bitfield in decimal
808 %<bitfield>W print the bitfield plus one in decimal
809 %<bitfield>x print the bitfield in hex
810 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
812 %<bitfield>'c print specified char iff bitfield is all ones
813 %<bitfield>`c print specified char iff bitfield is all zeroes
814 %<bitfield>?ab... select from array of values in big endian order
816 %e print arm SMI operand (bits 0..7,8..19).
817 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
818 %V print the 16-bit immediate field of a MOVT or MOVW instruction. */
820 static const struct opcode32 arm_opcodes[] =
822 /* ARM instructions. */
823 {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
824 {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
825 {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
826 {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
827 {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
828 {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
829 {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
831 /* V7 instructions. */
832 {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"},
833 {ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
834 {ARM_EXT_V7, 0xf57ff050, 0xfffffff0, "dmb\t%U"},
835 {ARM_EXT_V7, 0xf57ff040, 0xfffffff0, "dsb\t%U"},
836 {ARM_EXT_V7, 0xf57ff060, 0xfffffff0, "isb\t%U"},
838 /* ARM V6T2 instructions. */
839 {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
840 {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
841 {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
842 {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "strht%c\t%12-15R, %S"},
844 {ARM_EXT_V6T2, 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
845 {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
847 {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
848 {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
849 {ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
850 {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
852 /* ARM V6Z instructions. */
853 {ARM_EXT_V6Z, 0x01600070, 0x0ff000f0, "smc%c\t%e"},
855 /* ARM V6K instructions. */
856 {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"},
857 {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
858 {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
859 {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
860 {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
861 {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
862 {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
864 /* ARM V6K NOP hints. */
865 {ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"},
866 {ARM_EXT_V6K, 0x0320f002, 0x0fffffff, "wfe%c"},
867 {ARM_EXT_V6K, 0x0320f003, 0x0fffffff, "wfi%c"},
868 {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"},
869 {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
871 /* ARM V6 instructions. */
872 {ARM_EXT_V6, 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
873 {ARM_EXT_V6, 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
874 {ARM_EXT_V6, 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
875 {ARM_EXT_V6, 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
876 {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
877 {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
878 {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
879 {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
880 {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
881 {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
882 {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
883 {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
884 {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
885 {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
886 {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
887 {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
888 {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
889 {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
890 {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
891 {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
892 {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
893 {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
894 {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
895 {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
896 {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
897 {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
898 {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
899 {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
900 {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
901 {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
902 {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
903 {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
904 {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
905 {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
906 {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
907 {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
908 {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
909 {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
910 {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
911 {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
912 {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
913 {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
914 {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
915 {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
916 {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
917 {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
918 {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
919 {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
920 {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
921 {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
922 {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
923 {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
924 {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
925 {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
926 {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
927 {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
928 {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
929 {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
930 {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
931 {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
932 {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
933 {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
934 {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
935 {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
936 {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
937 {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
938 {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
939 {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
940 {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
941 {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
942 {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
943 {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
944 {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
945 {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
946 {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
947 {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
948 {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
949 {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
950 {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
951 {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
952 {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
953 {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
954 {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
955 {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
956 {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
957 {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
958 {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
959 {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
960 {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
961 {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
962 {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
963 {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
964 {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
965 {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
966 {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
967 {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
968 {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
969 {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
970 {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
971 {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
972 {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
973 {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
974 {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
975 {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
976 {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
977 {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
978 {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
979 {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
980 {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
981 {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
982 {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
983 {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
984 {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
985 {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
986 {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
987 {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
988 {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
989 {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
990 {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
991 {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
992 {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
993 {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
995 /* V5J instruction. */
996 {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
998 /* V5 Instructions. */
999 {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
1000 {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"},
1001 {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
1002 {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
1004 /* V5E "El Segundo" Instructions. */
1005 {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
1006 {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
1007 {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"},
1008 {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1009 {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1010 {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1011 {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
1013 {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1014 {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
1016 {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1017 {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1018 {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1019 {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1021 {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
1022 {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
1023 {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
1024 {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
1026 {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
1027 {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
1029 {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
1030 {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
1031 {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
1032 {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
1034 /* ARM Instructions. */
1035 {ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
1037 {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
1038 {ARM_EXT_V1, 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
1039 {ARM_EXT_V1, 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
1040 {ARM_EXT_V1, 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
1041 {ARM_EXT_V1, 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
1042 {ARM_EXT_V1, 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
1044 {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
1045 {ARM_EXT_V1, 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
1046 {ARM_EXT_V1, 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
1047 {ARM_EXT_V1, 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
1049 {ARM_EXT_V1, 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
1050 {ARM_EXT_V1, 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
1051 {ARM_EXT_V1, 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
1052 {ARM_EXT_V1, 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
1054 {ARM_EXT_V1, 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
1055 {ARM_EXT_V1, 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
1056 {ARM_EXT_V1, 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
1058 {ARM_EXT_V1, 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
1059 {ARM_EXT_V1, 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
1060 {ARM_EXT_V1, 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
1062 {ARM_EXT_V1, 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
1063 {ARM_EXT_V1, 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
1064 {ARM_EXT_V1, 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
1066 {ARM_EXT_V1, 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
1067 {ARM_EXT_V1, 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
1068 {ARM_EXT_V1, 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
1070 {ARM_EXT_V1, 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
1071 {ARM_EXT_V1, 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
1072 {ARM_EXT_V1, 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
1074 {ARM_EXT_V1, 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
1075 {ARM_EXT_V1, 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
1076 {ARM_EXT_V1, 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
1078 {ARM_EXT_V1, 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
1079 {ARM_EXT_V1, 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
1080 {ARM_EXT_V1, 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
1082 {ARM_EXT_V1, 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
1083 {ARM_EXT_V1, 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
1084 {ARM_EXT_V1, 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
1086 {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"},
1087 {ARM_EXT_V3, 0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15R, %22?SCPSR"},
1089 {ARM_EXT_V1, 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
1090 {ARM_EXT_V1, 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
1091 {ARM_EXT_V1, 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
1093 {ARM_EXT_V1, 0x03200000, 0x0fe00000, "teq%p%c\t%16-19r, %o"},
1094 {ARM_EXT_V1, 0x01200000, 0x0fe00010, "teq%p%c\t%16-19r, %o"},
1095 {ARM_EXT_V1, 0x01200010, 0x0fe00090, "teq%p%c\t%16-19R, %o"},
1097 {ARM_EXT_V1, 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
1098 {ARM_EXT_V3, 0x01400000, 0x0ff00010, "mrs%c\t%12-15R, %22?SCPSR"},
1099 {ARM_EXT_V1, 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
1100 {ARM_EXT_V1, 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
1102 {ARM_EXT_V1, 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
1103 {ARM_EXT_V1, 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
1104 {ARM_EXT_V1, 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
1106 {ARM_EXT_V1, 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
1107 {ARM_EXT_V1, 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
1108 {ARM_EXT_V1, 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
1110 {ARM_EXT_V1, 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
1111 {ARM_EXT_V1, 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
1112 {ARM_EXT_V1, 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
1113 {ARM_EXT_V1, 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
1114 {ARM_EXT_V1, 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
1115 {ARM_EXT_V1, 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
1116 {ARM_EXT_V1, 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
1118 {ARM_EXT_V1, 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
1119 {ARM_EXT_V1, 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
1120 {ARM_EXT_V1, 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
1122 {ARM_EXT_V1, 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
1123 {ARM_EXT_V1, 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
1124 {ARM_EXT_V1, 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
1126 {ARM_EXT_V1, 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
1127 {ARM_EXT_V1, 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
1129 {ARM_EXT_V1, 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
1131 {ARM_EXT_V1, 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
1132 {ARM_EXT_V1, 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
1134 {ARM_EXT_V1, 0x092d0000, 0x0fff0000, "push%c\t%m"},
1135 {ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
1136 {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
1137 {ARM_EXT_V1, 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
1138 {ARM_EXT_V1, 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
1139 {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
1140 {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
1141 {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
1144 {ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
1145 {0, 0x00000000, 0x00000000, 0}
1148 /* print_insn_thumb16 recognizes the following format control codes:
1150 %S print Thumb register (bits 3..5 as high number if bit 6 set)
1151 %D print Thumb register (bits 0..2 as high number if bit 7 set)
1152 %<bitfield>I print bitfield as a signed decimal
1153 (top bit of range being the sign bit)
1154 %N print Thumb register mask (with LR)
1155 %O print Thumb register mask (with PC)
1156 %M print Thumb register mask
1157 %b print CZB's 6-bit unsigned branch destination
1158 %s print Thumb right-shift immediate (6..10; 0 == 32).
1159 %c print the condition code
1160 %C print the condition code, or "s" if not conditional
1161 %x print warning if conditional an not at end of IT block"
1162 %X print "\t; unpredictable <IT:code>" if conditional
1163 %I print IT instruction suffix and operands
1164 %W print Thumb Writeback indicator for LDMIA
1165 %<bitfield>r print bitfield as an ARM register
1166 %<bitfield>d print bitfield as a decimal
1167 %<bitfield>H print (bitfield * 2) as a decimal
1168 %<bitfield>W print (bitfield * 4) as a decimal
1169 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
1170 %<bitfield>B print Thumb branch destination (signed displacement)
1171 %<bitfield>c print bitfield as a condition code
1172 %<bitnum>'c print specified char iff bit is one
1173 %<bitnum>?ab print a if bit is one else print b. */
1175 static const struct opcode16 thumb_opcodes[] =
1177 /* Thumb instructions. */
1179 /* ARM V6K no-argument instructions. */
1180 {ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"},
1181 {ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"},
1182 {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe%c"},
1183 {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi%c"},
1184 {ARM_EXT_V6K, 0xbf40, 0xffff, "sev%c"},
1185 {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
1187 /* ARM V6T2 instructions. */
1188 {ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
1189 {ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
1190 {ARM_EXT_V6T2, 0xbf00, 0xff00, "it%I%X"},
1193 {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
1194 {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
1195 {ARM_EXT_V6, 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
1196 {ARM_EXT_V6, 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
1197 {ARM_EXT_V6, 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
1198 {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
1199 {ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble%X"},
1200 {ARM_EXT_V6, 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
1201 {ARM_EXT_V6, 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
1202 {ARM_EXT_V6, 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
1203 {ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
1205 /* ARM V5 ISA extends Thumb. */
1206 {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
1207 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
1208 {ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
1209 /* ARM V4T ISA (Thumb v1). */
1210 {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
1212 {ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
1213 {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
1214 {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
1215 {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
1216 {ARM_EXT_V4T, 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
1217 {ARM_EXT_V4T, 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
1218 {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
1219 {ARM_EXT_V4T, 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
1220 {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
1221 {ARM_EXT_V4T, 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
1222 {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
1223 {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
1224 {ARM_EXT_V4T, 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
1225 {ARM_EXT_V4T, 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
1226 {ARM_EXT_V4T, 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
1227 {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
1229 {ARM_EXT_V4T, 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
1230 {ARM_EXT_V4T, 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
1232 {ARM_EXT_V4T, 0x4700, 0xFF80, "bx%c\t%S%x"},
1233 {ARM_EXT_V4T, 0x4400, 0xFF00, "add%c\t%D, %S"},
1234 {ARM_EXT_V4T, 0x4500, 0xFF00, "cmp%c\t%D, %S"},
1235 {ARM_EXT_V4T, 0x4600, 0xFF00, "mov%c\t%D, %S"},
1237 {ARM_EXT_V4T, 0xB400, 0xFE00, "push%c\t%N"},
1238 {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop%c\t%O"},
1240 {ARM_EXT_V4T, 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
1241 {ARM_EXT_V4T, 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
1242 {ARM_EXT_V4T, 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
1243 {ARM_EXT_V4T, 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
1245 {ARM_EXT_V4T, 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
1246 {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
1247 {ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
1249 {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
1250 {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
1252 {ARM_EXT_V4T, 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
1253 {ARM_EXT_V4T, 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
1254 {ARM_EXT_V4T, 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
1255 {ARM_EXT_V4T, 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
1257 {ARM_EXT_V4T, 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
1258 {ARM_EXT_V4T, 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
1259 {ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
1260 {ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
1262 {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
1264 {ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
1265 {ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
1266 {ARM_EXT_V4T, 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
1267 {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
1269 {ARM_EXT_V4T, 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
1270 {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
1272 {ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
1273 {ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
1275 {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
1276 {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
1278 {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
1279 {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
1281 {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"},
1283 {ARM_EXT_V4T, 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
1284 {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
1286 {ARM_EXT_V4T, 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
1288 /* The E800 .. FFFF range is unconditionally redirected to the
1289 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
1290 are processed via that table. Thus, we can never encounter a
1291 bare "second half of BL/BLX(1)" instruction here. */
1292 {ARM_EXT_V1, 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
1296 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
1297 We adopt the convention that hw1 is the high 16 bits of .value and
1298 .mask, hw2 the low 16 bits.
1300 print_insn_thumb32 recognizes the following format control codes:
1304 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
1305 %M print a modified 12-bit immediate (same location)
1306 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
1307 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
1308 %S print a possibly-shifted Rm
1310 %a print the address of a plain load/store
1311 %w print the width and signedness of a core load/store
1312 %m print register mask for ldm/stm
1314 %E print the lsb and width fields of a bfc/bfi instruction
1315 %F print the lsb and width fields of a sbfx/ubfx instruction
1316 %b print a conditional branch offset
1317 %B print an unconditional branch offset
1318 %s print the shift field of an SSAT instruction
1319 %R print the rotation field of an SXT instruction
1320 %U print barrier type.
1321 %P print address for pli instruction.
1322 %c print the condition code
1323 %x print warning if conditional an not at end of IT block"
1324 %X print "\t; unpredictable <IT:code>" if conditional
1326 %<bitfield>d print bitfield in decimal
1327 %<bitfield>W print bitfield*4 in decimal
1328 %<bitfield>r print bitfield as an ARM register
1329 %<bitfield>R as %<>r bit r15 is UNPREDICTABLE
1330 %<bitfield>c print bitfield as a condition code
1332 %<bitfield>'c print specified char iff bitfield is all ones
1333 %<bitfield>`c print specified char iff bitfield is all zeroes
1334 %<bitfield>?ab... select from array of values in big endian order
1336 With one exception at the bottom (done because BL and BLX(1) need
1337 to come dead last), this table was machine-sorted first in
1338 decreasing order of number of bits set in the mask, then in
1339 increasing numeric order of mask, then in increasing numeric order
1340 of opcode. This order is not the clearest for a human reader, but
1341 is guaranteed never to catch a special-case bit pattern with a more
1342 general mask, which is important, because this instruction encoding
1343 makes heavy use of special-case bit patterns. */
1344 static const struct opcode32 thumb32_opcodes[] =
1346 /* V7 instructions. */
1347 {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
1348 {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
1349 {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
1350 {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
1351 {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
1352 {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
1353 {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
1355 /* Instructions defined in the basic V6T2 set. */
1356 {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"},
1357 {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"},
1358 {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"},
1359 {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"},
1360 {ARM_EXT_V6T2, 0xf3af8004, 0xffffffff, "sev%c.w"},
1361 {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
1363 {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"},
1364 {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
1365 {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
1366 {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
1367 {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
1368 {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
1369 {ARM_EXT_V6T2, 0xf3ef8000, 0xffeff000, "mrs%c\t%8-11r, %D"},
1370 {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
1371 {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
1372 {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
1373 {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
1374 {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
1375 {ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
1376 {ARM_EXT_V6T2, 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
1377 {ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
1378 {ARM_EXT_V6T2, 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
1379 {ARM_EXT_V6T2, 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
1380 {ARM_EXT_V6T2, 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
1381 {ARM_EXT_V6T2, 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
1382 {ARM_EXT_V6T2, 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
1383 {ARM_EXT_V6T2, 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
1384 {ARM_EXT_V6T2, 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
1385 {ARM_EXT_V6T2, 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
1386 {ARM_EXT_V6T2, 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
1387 {ARM_EXT_V6T2, 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
1388 {ARM_EXT_V6T2, 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
1389 {ARM_EXT_V6T2, 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
1390 {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
1391 {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
1392 {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
1393 {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
1394 {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
1395 {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
1396 {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
1397 {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
1398 {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
1399 {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
1400 {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
1401 {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
1402 {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
1403 {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
1404 {ARM_EXT_V6T2, 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
1405 {ARM_EXT_V6T2, 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
1406 {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
1407 {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
1408 {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
1409 {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
1410 {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
1411 {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
1412 {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
1413 {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
1414 {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
1415 {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
1416 {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
1417 {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
1418 {ARM_EXT_V6T2, 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
1419 {ARM_EXT_V6T2, 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
1420 {ARM_EXT_V6T2, 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
1421 {ARM_EXT_V6T2, 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
1422 {ARM_EXT_V6T2, 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
1423 {ARM_EXT_V6T2, 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
1424 {ARM_EXT_V6T2, 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
1425 {ARM_EXT_V6T2, 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
1426 {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
1427 {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
1428 {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
1429 {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
1430 {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
1431 {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
1432 {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
1433 {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
1434 {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
1435 {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
1436 {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
1437 {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
1438 {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
1439 {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
1440 {ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
1441 {ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
1442 {ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"},
1443 {ARM_EXT_V6T2, 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
1444 {ARM_EXT_V6T2, 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
1445 {ARM_EXT_V6T2, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
1446 {ARM_EXT_V6T2, 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
1447 {ARM_EXT_V6T2, 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
1448 {ARM_EXT_V6T2, 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
1449 {ARM_EXT_V6T2, 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
1450 {ARM_EXT_V6T2, 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
1451 {ARM_EXT_V6T2, 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
1452 {ARM_EXT_V6T2, 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
1453 {ARM_EXT_V6T2, 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
1454 {ARM_EXT_V6T2, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
1455 {ARM_EXT_V6T2, 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
1456 {ARM_EXT_V6T2, 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
1457 {ARM_EXT_V6T2, 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
1458 {ARM_EXT_V6T2, 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
1459 {ARM_EXT_V6T2, 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
1460 {ARM_EXT_V6T2, 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
1461 {ARM_EXT_V6T2, 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
1462 {ARM_EXT_V6T2, 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
1463 {ARM_EXT_V6T2, 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
1464 {ARM_EXT_V6T2, 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
1465 {ARM_EXT_V6T2, 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
1466 {ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
1467 {ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1468 {ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1469 {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1470 {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1471 {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1472 {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1473 {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1474 {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1475 {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
1476 {ARM_EXT_V6T2, 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
1477 {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
1478 {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
1479 {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld%c\t%a"},
1480 {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1481 {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1482 {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1483 {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1484 {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1485 {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1486 {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1487 {ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
1488 {ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
1489 {ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
1490 {ARM_EXT_V6T2, 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
1491 {ARM_EXT_V6T2, 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
1492 {ARM_EXT_V6T2, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1493 {ARM_EXT_V6T2, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
1494 {ARM_EXT_V6T2, 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
1495 {ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
1496 {ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"},
1497 {ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
1498 {ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
1499 {ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
1500 {ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
1501 {ARM_EXT_V6T2, 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
1502 {ARM_EXT_V6T2, 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
1503 {ARM_EXT_V6T2, 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
1504 {ARM_EXT_V6T2, 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
1505 {ARM_EXT_V6T2, 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
1506 {ARM_EXT_V6T2, 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
1507 {ARM_EXT_V6T2, 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
1508 {ARM_EXT_V6T2, 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
1509 {ARM_EXT_V6T2, 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
1510 {ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
1511 {ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
1512 {ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
1513 {ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
1514 {ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
1515 {ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
1516 {ARM_EXT_V6T2, 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
1517 {ARM_EXT_V6T2, 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
1518 {ARM_EXT_V6T2, 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
1519 {ARM_EXT_V6T2, 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
1520 {ARM_EXT_V6T2, 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
1521 {ARM_EXT_V6T2, 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
1522 {ARM_EXT_V6T2, 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
1523 {ARM_EXT_V6T2, 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
1524 {ARM_EXT_V6T2, 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
1525 {ARM_EXT_V6T2, 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
1526 {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
1527 {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
1528 {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
1529 {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"},
1530 {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"},
1531 {ARM_EXT_V6T2, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"},
1532 {ARM_EXT_V6T2, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"},
1533 {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
1534 {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
1536 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
1537 {ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
1538 {ARM_EXT_V6T2, 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
1539 {ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
1540 {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
1542 /* These have been 32-bit since the invention of Thumb. */
1543 {ARM_EXT_V4T, 0xf000c000, 0xf800d000, "blx%c\t%B%x"},
1544 {ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
1547 {ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
1551 static const char *const arm_conditional[] =
1552 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
1553 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
1555 static const char *const arm_fp_const[] =
1556 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
1558 static const char *const arm_shift[] =
1559 {"lsl", "lsr", "asr", "ror"};
1564 const char *description;
1565 const char *reg_names[16];
1569 static const arm_regname regnames[] =
1571 { "raw" , "Select raw register names",
1572 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
1573 { "gcc", "Select register names used by GCC",
1574 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
1575 { "std", "Select register names used in ARM's ISA documentation",
1576 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
1577 { "apcs", "Select register names used in the APCS",
1578 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
1579 { "atpcs", "Select register names used in the ATPCS",
1580 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
1581 { "special-atpcs", "Select special register names used in the ATPCS",
1582 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
1585 static const char *const iwmmxt_wwnames[] =
1586 {"b", "h", "w", "d"};
1588 static const char *const iwmmxt_wwssnames[] =
1589 {"b", "bus", "bc", "bss",
1590 "h", "hus", "hc", "hss",
1591 "w", "wus", "wc", "wss",
1592 "d", "dus", "dc", "dss"
1595 static const char *const iwmmxt_regnames[] =
1596 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
1597 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
1600 static const char *const iwmmxt_cregnames[] =
1601 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
1602 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
1605 /* Default to GCC register name set. */
1606 static unsigned int regname_selected = 1;
1608 #define NUM_ARM_REGNAMES NUM_ELEM (regnames)
1609 #define arm_regnames regnames[regname_selected].reg_names
1611 static bfd_boolean force_thumb = FALSE;
1613 /* Current IT instruction state. This contains the same state as the IT
1614 bits in the CPSR. */
1615 static unsigned int ifthen_state;
1616 /* IT state for the next instruction. */
1617 static unsigned int ifthen_next_state;
1618 /* The address of the insn for which the IT state is valid. */
1619 static bfd_vma ifthen_address;
1620 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
1622 /* Cached mapping symbol state. */
1630 enum map_type last_type;
1631 int last_mapping_sym = -1;
1632 bfd_vma last_mapping_addr = 0;
1637 get_arm_regname_num_options (void)
1639 return NUM_ARM_REGNAMES;
1643 set_arm_regname_option (int option)
1645 int old = regname_selected;
1646 regname_selected = option;
1651 get_arm_regnames (int option,
1652 const char **setname,
1653 const char **setdescription,
1654 const char *const **register_names)
1656 *setname = regnames[option].name;
1657 *setdescription = regnames[option].description;
1658 *register_names = regnames[option].reg_names;
1662 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
1663 Returns pointer to following character of the format string and
1664 fills in *VALUEP and *WIDTHP with the extracted value and number of
1665 bits extracted. WIDTHP can be NULL. */
1668 arm_decode_bitfield (const char *ptr,
1670 unsigned long *valuep,
1673 unsigned long value = 0;
1681 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
1682 start = start * 10 + *ptr - '0';
1684 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
1685 end = end * 10 + *ptr - '0';
1691 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
1694 while (*ptr++ == ',');
1702 arm_decode_shift (long given, fprintf_ftype func, void *stream,
1703 bfd_boolean print_shift)
1705 func (stream, "%s", arm_regnames[given & 0xf]);
1707 if ((given & 0xff0) != 0)
1709 if ((given & 0x10) == 0)
1711 int amount = (given & 0xf80) >> 7;
1712 int shift = (given & 0x60) >> 5;
1718 func (stream, ", rrx");
1726 func (stream, ", %s #%d", arm_shift[shift], amount);
1728 func (stream, ", #%d", amount);
1730 else if ((given & 0x80) == 0x80)
1731 func (stream, "\t; <illegal shifter operand>");
1732 else if (print_shift)
1733 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
1734 arm_regnames[(given & 0xf00) >> 8]);
1736 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
1745 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
1746 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
1747 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
1748 #define PRE_BIT_SET (given & (1 << P_BIT))
1750 /* Print one coprocessor instruction on INFO->STREAM.
1751 Return TRUE if the instuction matched, FALSE if this is not a
1752 recognised coprocessor instruction. */
1755 print_insn_coprocessor (bfd_vma pc,
1756 struct disassemble_info *info,
1760 const struct opcode32 *insn;
1761 void *stream = info->stream;
1762 fprintf_ftype func = info->fprintf_func;
1764 unsigned long value = 0;
1765 struct arm_private_data *private_data = info->private_data;
1766 unsigned long allowed_arches = private_data->features.coproc;
1769 for (insn = coprocessor_opcodes; insn->assembler; insn++)
1771 unsigned long u_reg = 16;
1772 bfd_boolean is_unpredictable = FALSE;
1773 signed long value_in_comment = 0;
1776 if (insn->arch == 0)
1777 switch (insn->value)
1779 case SENTINEL_IWMMXT_START:
1780 if (info->mach != bfd_mach_arm_XScale
1781 && info->mach != bfd_mach_arm_iWMMXt
1782 && info->mach != bfd_mach_arm_iWMMXt2)
1785 while (insn->arch != 0 && insn->value != SENTINEL_IWMMXT_END);
1788 case SENTINEL_IWMMXT_END:
1791 case SENTINEL_GENERIC_START:
1792 allowed_arches = private_data->features.core;
1800 value = insn->value;
1803 /* The high 4 bits are 0xe for Arm conditional instructions, and
1804 0xe for arm unconditional instructions. The rest of the
1805 encoding is the same. */
1807 value |= 0xe0000000;
1815 /* Only match unconditional instuctions against unconditional
1817 if ((given & 0xf0000000) == 0xf0000000)
1824 cond = (given >> 28) & 0xf;
1830 if ((given & mask) != value)
1833 if ((insn->arch & allowed_arches) == 0)
1836 for (c = insn->assembler; *c; c++)
1843 func (stream, "%%");
1848 int rn = (given >> 16) & 0xf;
1849 int offset = given & 0xff;
1851 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
1853 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
1855 /* Not unindexed. The offset is scaled. */
1856 offset = offset * 4;
1857 if (NEGATIVE_BIT_SET)
1860 value_in_comment = offset;
1866 func (stream, ", #%d]%s",
1868 WRITEBACK_BIT_SET ? "!" : "");
1876 if (WRITEBACK_BIT_SET)
1879 func (stream, ", #%d", offset);
1883 func (stream, ", {%d}", offset);
1884 value_in_comment = offset;
1887 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
1889 func (stream, "\t; ");
1890 info->print_address_func (offset + pc
1891 + info->bytes_per_chunk * 2, info);
1898 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
1899 int offset = (given >> 1) & 0x3f;
1902 func (stream, "{d%d}", regno);
1903 else if (regno + offset > 32)
1904 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
1906 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
1911 func (stream, "%s", arm_conditional[cond]);
1915 /* Print a Cirrus/DSP shift immediate. */
1916 /* Immediates are 7bit signed ints with bits 0..3 in
1917 bits 0..3 of opcode and bits 4..6 in bits 5..7
1922 imm = (given & 0xf) | ((given & 0xe0) >> 1);
1924 /* Is ``imm'' a negative number? */
1928 func (stream, "%d", imm);
1934 switch (given & 0x00408000)
1951 switch (given & 0x00080080)
1963 func (stream, _("<illegal precision>"));
1969 switch (given & 0x00408000)
1987 switch (given & 0x60)
2003 case '0': case '1': case '2': case '3': case '4':
2004 case '5': case '6': case '7': case '8': case '9':
2008 c = arm_decode_bitfield (c, given, &value, &width);
2014 is_unpredictable = TRUE;
2019 /* Eat the 'u' character. */
2023 is_unpredictable = TRUE;
2026 func (stream, "%s", arm_regnames[value]);
2029 func (stream, "d%ld", value);
2033 func (stream, "<illegal reg q%ld.5>", value >> 1);
2035 func (stream, "q%ld", value >> 1);
2038 func (stream, "%ld", value);
2039 value_in_comment = value;
2043 int from = (given & (1 << 7)) ? 32 : 16;
2044 func (stream, "%ld", from - value);
2050 func (stream, "#%s", arm_fp_const[value & 7]);
2052 func (stream, "f%ld", value);
2057 func (stream, "%s", iwmmxt_wwnames[value]);
2059 func (stream, "%s", iwmmxt_wwssnames[value]);
2063 func (stream, "%s", iwmmxt_regnames[value]);
2066 func (stream, "%s", iwmmxt_cregnames[value]);
2070 func (stream, "0x%lx", (value & 0xffffffffUL));
2076 func (stream, "%c", *c);
2080 if (value == ((1ul << width) - 1))
2081 func (stream, "%c", *c);
2084 func (stream, "%c", c[(1 << width) - (int) value]);
2095 int single = *c++ == 'y';
2100 case '4': /* Sm pair */
2101 case '0': /* Sm, Dm */
2102 regno = given & 0x0000000f;
2106 regno += (given >> 5) & 1;
2109 regno += ((given >> 5) & 1) << 4;
2112 case '1': /* Sd, Dd */
2113 regno = (given >> 12) & 0x0000000f;
2117 regno += (given >> 22) & 1;
2120 regno += ((given >> 22) & 1) << 4;
2123 case '2': /* Sn, Dn */
2124 regno = (given >> 16) & 0x0000000f;
2128 regno += (given >> 7) & 1;
2131 regno += ((given >> 7) & 1) << 4;
2134 case '3': /* List */
2136 regno = (given >> 12) & 0x0000000f;
2140 regno += (given >> 22) & 1;
2143 regno += ((given >> 22) & 1) << 4;
2150 func (stream, "%c%d", single ? 's' : 'd', regno);
2154 int count = given & 0xff;
2161 func (stream, "-%c%d",
2169 func (stream, ", %c%d", single ? 's' : 'd',
2175 switch (given & 0x00400100)
2177 case 0x00000000: func (stream, "b"); break;
2178 case 0x00400000: func (stream, "h"); break;
2179 case 0x00000100: func (stream, "w"); break;
2180 case 0x00400100: func (stream, "d"); break;
2188 /* given (20, 23) | given (0, 3) */
2189 value = ((given >> 16) & 0xf0) | (given & 0xf);
2190 func (stream, "%d", value);
2195 /* This is like the 'A' operator, except that if
2196 the width field "M" is zero, then the offset is
2197 *not* multiplied by four. */
2199 int offset = given & 0xff;
2200 int multiplier = (given & 0x00000100) ? 4 : 1;
2202 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
2206 value_in_comment = offset * multiplier;
2207 if (NEGATIVE_BIT_SET)
2208 value_in_comment = - value_in_comment;
2214 func (stream, ", #%s%d]%s",
2215 NEGATIVE_BIT_SET ? "-" : "",
2216 offset * multiplier,
2217 WRITEBACK_BIT_SET ? "!" : "");
2219 func (stream, "], #%s%d",
2220 NEGATIVE_BIT_SET ? "-" : "",
2221 offset * multiplier);
2230 int imm4 = (given >> 4) & 0xf;
2231 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
2232 int ubit = ! NEGATIVE_BIT_SET;
2233 const char *rm = arm_regnames [given & 0xf];
2234 const char *rn = arm_regnames [(given >> 16) & 0xf];
2240 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
2242 func (stream, ", lsl #%d", imm4);
2249 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
2251 func (stream, ", lsl #%d", imm4);
2253 if (puw_bits == 5 || puw_bits == 7)
2258 func (stream, "INVALID");
2266 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
2267 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
2277 func (stream, "%c", *c);
2280 if (value_in_comment > 32 || value_in_comment < -16)
2281 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
2283 if (is_unpredictable)
2284 func (stream, UNPREDICTABLE_INSTRUCTION);
2291 /* Decodes and prints ARM addressing modes. Returns the offset
2292 used in the address, if any, if it is worthwhile printing the
2293 offset as a hexadecimal value in a comment at the end of the
2294 line of disassembly. */
2297 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
2299 void *stream = info->stream;
2300 fprintf_ftype func = info->fprintf_func;
2303 if (((given & 0x000f0000) == 0x000f0000)
2304 && ((given & 0x02000000) == 0))
2306 offset = given & 0xfff;
2308 func (stream, "[pc");
2310 if (NEGATIVE_BIT_SET)
2316 func (stream, ", #%d]", offset);
2320 /* Cope with the possibility of write-back
2321 being used. Probably a very dangerous thing
2322 for the programmer to do, but who are we to
2324 if (WRITEBACK_BIT_SET)
2327 else /* Post indexed. */
2329 func (stream, "], #%d", offset);
2331 /* Ie ignore the offset. */
2335 func (stream, "\t; ");
2336 info->print_address_func (offset, info);
2341 func (stream, "[%s",
2342 arm_regnames[(given >> 16) & 0xf]);
2346 if ((given & 0x02000000) == 0)
2348 offset = given & 0xfff;
2350 func (stream, ", #%s%d",
2351 NEGATIVE_BIT_SET ? "-" : "", offset);
2355 func (stream, ", %s",
2356 NEGATIVE_BIT_SET ? "-" : "");
2357 arm_decode_shift (given, func, stream, TRUE);
2360 func (stream, "]%s",
2361 WRITEBACK_BIT_SET ? "!" : "");
2365 if ((given & 0x02000000) == 0)
2367 offset = given & 0xfff;
2369 func (stream, "], #%s%d",
2370 NEGATIVE_BIT_SET ? "-" : "", offset);
2376 func (stream, "], %s",
2377 NEGATIVE_BIT_SET ? "-" : "");
2378 arm_decode_shift (given, func, stream, TRUE);
2383 return (signed long) offset;
2386 /* Print one neon instruction on INFO->STREAM.
2387 Return TRUE if the instuction matched, FALSE if this is not a
2388 recognised neon instruction. */
2391 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
2393 const struct opcode32 *insn;
2394 void *stream = info->stream;
2395 fprintf_ftype func = info->fprintf_func;
2399 if ((given & 0xef000000) == 0xef000000)
2401 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
2402 unsigned long bit28 = given & (1 << 28);
2404 given &= 0x00ffffff;
2406 given |= 0xf3000000;
2408 given |= 0xf2000000;
2410 else if ((given & 0xff000000) == 0xf9000000)
2411 given ^= 0xf9000000 ^ 0xf4000000;
2416 for (insn = neon_opcodes; insn->assembler; insn++)
2418 if ((given & insn->mask) == insn->value)
2420 signed long value_in_comment = 0;
2423 for (c = insn->assembler; *c; c++)
2430 func (stream, "%%");
2434 if (thumb && ifthen_state)
2435 func (stream, "%s", arm_conditional[IFTHEN_COND]);
2440 static const unsigned char enc[16] =
2442 0x4, 0x14, /* st4 0,1 */
2454 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2455 int rn = ((given >> 16) & 0xf);
2456 int rm = ((given >> 0) & 0xf);
2457 int align = ((given >> 4) & 0x3);
2458 int type = ((given >> 8) & 0xf);
2459 int n = enc[type] & 0xf;
2460 int stride = (enc[type] >> 4) + 1;
2465 for (ix = 0; ix != n; ix++)
2466 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
2468 func (stream, "d%d", rd);
2470 func (stream, "d%d-d%d", rd, rd + n - 1);
2471 func (stream, "}, [%s", arm_regnames[rn]);
2473 func (stream, " :%d", 32 << align);
2478 func (stream, ", %s", arm_regnames[rm]);
2484 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2485 int rn = ((given >> 16) & 0xf);
2486 int rm = ((given >> 0) & 0xf);
2487 int idx_align = ((given >> 4) & 0xf);
2489 int size = ((given >> 10) & 0x3);
2490 int idx = idx_align >> (size + 1);
2491 int length = ((given >> 8) & 3) + 1;
2495 if (length > 1 && size > 0)
2496 stride = (idx_align & (1 << size)) ? 2 : 1;
2502 int amask = (1 << size) - 1;
2503 if ((idx_align & (1 << size)) != 0)
2507 if ((idx_align & amask) == amask)
2509 else if ((idx_align & amask) != 0)
2516 if (size == 2 && (idx_align & 2) != 0)
2518 align = (idx_align & 1) ? 16 << size : 0;
2522 if ((size == 2 && (idx_align & 3) != 0)
2523 || (idx_align & 1) != 0)
2530 if ((idx_align & 3) == 3)
2532 align = (idx_align & 3) * 64;
2535 align = (idx_align & 1) ? 32 << size : 0;
2543 for (i = 0; i < length; i++)
2544 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
2545 rd + i * stride, idx);
2546 func (stream, "}, [%s", arm_regnames[rn]);
2548 func (stream, " :%d", align);
2553 func (stream, ", %s", arm_regnames[rm]);
2559 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2560 int rn = ((given >> 16) & 0xf);
2561 int rm = ((given >> 0) & 0xf);
2562 int align = ((given >> 4) & 0x1);
2563 int size = ((given >> 6) & 0x3);
2564 int type = ((given >> 8) & 0x3);
2566 int stride = ((given >> 5) & 0x1);
2569 if (stride && (n == 1))
2576 for (ix = 0; ix != n; ix++)
2577 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
2579 func (stream, "d%d[]", rd);
2581 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
2582 func (stream, "}, [%s", arm_regnames[rn]);
2585 align = (8 * (type + 1)) << size;
2587 align = (size > 1) ? align >> 1 : align;
2588 if (type == 2 || (type == 0 && !size))
2589 func (stream, " :<bad align %d>", align);
2591 func (stream, " :%d", align);
2597 func (stream, ", %s", arm_regnames[rm]);
2603 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
2604 int size = (given >> 20) & 3;
2605 int reg = raw_reg & ((4 << size) - 1);
2606 int ix = raw_reg >> size >> 2;
2608 func (stream, "d%d[%d]", reg, ix);
2613 /* Neon encoded constant for mov, mvn, vorr, vbic. */
2616 int cmode = (given >> 8) & 0xf;
2617 int op = (given >> 5) & 0x1;
2618 unsigned long value = 0, hival = 0;
2623 bits |= ((given >> 24) & 1) << 7;
2624 bits |= ((given >> 16) & 7) << 4;
2625 bits |= ((given >> 0) & 15) << 0;
2629 shift = (cmode >> 1) & 3;
2630 value = (unsigned long) bits << (8 * shift);
2633 else if (cmode < 12)
2635 shift = (cmode >> 1) & 1;
2636 value = (unsigned long) bits << (8 * shift);
2639 else if (cmode < 14)
2641 shift = (cmode & 1) + 1;
2642 value = (unsigned long) bits << (8 * shift);
2643 value |= (1ul << (8 * shift)) - 1;
2646 else if (cmode == 14)
2650 /* Bit replication into bytes. */
2656 for (ix = 7; ix >= 0; ix--)
2658 mask = ((bits >> ix) & 1) ? 0xff : 0;
2660 value = (value << 8) | mask;
2662 hival = (hival << 8) | mask;
2668 /* Byte replication. */
2669 value = (unsigned long) bits;
2675 /* Floating point encoding. */
2678 value = (unsigned long) (bits & 0x7f) << 19;
2679 value |= (unsigned long) (bits & 0x80) << 24;
2680 tmp = bits & 0x40 ? 0x3c : 0x40;
2681 value |= (unsigned long) tmp << 24;
2687 func (stream, "<illegal constant %.8x:%x:%x>",
2695 func (stream, "#%ld\t; 0x%.2lx", value, value);
2699 func (stream, "#%ld\t; 0x%.4lx", value, value);
2705 unsigned char valbytes[4];
2708 /* Do this a byte at a time so we don't have to
2709 worry about the host's endianness. */
2710 valbytes[0] = value & 0xff;
2711 valbytes[1] = (value >> 8) & 0xff;
2712 valbytes[2] = (value >> 16) & 0xff;
2713 valbytes[3] = (value >> 24) & 0xff;
2715 floatformat_to_double
2716 (& floatformat_ieee_single_little, valbytes,
2719 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
2723 func (stream, "#%ld\t; 0x%.8lx",
2724 (long) (((value & 0x80000000L) != 0)
2725 ? value | ~0xffffffffL : value),
2730 func (stream, "#0x%.8lx%.8lx", hival, value);
2741 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
2742 int num = (given >> 8) & 0x3;
2745 func (stream, "{d%d}", regno);
2746 else if (num + regno >= 32)
2747 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
2749 func (stream, "{d%d-d%d}", regno, regno + num);
2754 case '0': case '1': case '2': case '3': case '4':
2755 case '5': case '6': case '7': case '8': case '9':
2758 unsigned long value;
2760 c = arm_decode_bitfield (c, given, &value, &width);
2765 func (stream, "%s", arm_regnames[value]);
2768 func (stream, "%ld", value);
2769 value_in_comment = value;
2772 func (stream, "%ld", (1ul << width) - value);
2778 /* Various width encodings. */
2780 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
2785 if (*c >= '0' && *c <= '9')
2787 else if (*c >= 'a' && *c <= 'f')
2788 limit = *c - 'a' + 10;
2794 if (value < low || value > high)
2795 func (stream, "<illegal width %d>", base << value);
2797 func (stream, "%d", base << value);
2801 if (given & (1 << 6))
2805 func (stream, "d%ld", value);
2810 func (stream, "<illegal reg q%ld.5>", value >> 1);
2812 func (stream, "q%ld", value >> 1);
2818 func (stream, "%c", *c);
2822 if (value == ((1ul << width) - 1))
2823 func (stream, "%c", *c);
2826 func (stream, "%c", c[(1 << width) - (int) value]);
2840 func (stream, "%c", *c);
2843 if (value_in_comment > 32 || value_in_comment < -16)
2844 func (stream, "\t; 0x%lx", value_in_comment);
2852 /* Print one ARM instruction from PC on INFO->STREAM. */
2855 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
2857 const struct opcode32 *insn;
2858 void *stream = info->stream;
2859 fprintf_ftype func = info->fprintf_func;
2860 struct arm_private_data *private_data = info->private_data;
2862 if (print_insn_coprocessor (pc, info, given, FALSE))
2865 if (print_insn_neon (info, given, FALSE))
2868 for (insn = arm_opcodes; insn->assembler; insn++)
2870 if ((given & insn->mask) != insn->value)
2873 if ((insn->arch & private_data->features.core) == 0)
2876 /* Special case: an instruction with all bits set in the condition field
2877 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
2878 or by the catchall at the end of the table. */
2879 if ((given & 0xF0000000) != 0xF0000000
2880 || (insn->mask & 0xF0000000) == 0xF0000000
2881 || (insn->mask == 0 && insn->value == 0))
2883 unsigned long u_reg = 16;
2884 unsigned long U_reg = 16;
2885 bfd_boolean is_unpredictable = FALSE;
2886 signed long value_in_comment = 0;
2889 for (c = insn->assembler; *c; c++)
2893 bfd_boolean allow_unpredictable = FALSE;
2898 func (stream, "%%");
2902 value_in_comment = print_arm_address (pc, info, given);
2906 /* Set P address bit and use normal address
2907 printing routine. */
2908 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
2912 allow_unpredictable = TRUE;
2914 if ((given & 0x004f0000) == 0x004f0000)
2916 /* PC relative with immediate offset. */
2917 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
2919 if (NEGATIVE_BIT_SET)
2925 func (stream, "[pc, #%d]\t; ", offset);
2927 func (stream, "[pc]\t; ");
2928 info->print_address_func (offset + pc + 8, info);
2932 func (stream, "[pc], #%d", offset);
2933 if (! allow_unpredictable)
2934 is_unpredictable = TRUE;
2939 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
2941 if (NEGATIVE_BIT_SET)
2944 func (stream, "[%s",
2945 arm_regnames[(given >> 16) & 0xf]);
2949 if (IMMEDIATE_BIT_SET)
2951 if (WRITEBACK_BIT_SET)
2952 /* Immediate Pre-indexed. */
2953 /* PR 10924: Offset must be printed, even if it is zero. */
2954 func (stream, ", #%d", offset);
2956 /* Immediate Offset: printing zero offset is optional. */
2957 func (stream, ", #%d", offset);
2959 value_in_comment = offset;
2963 /* Register Offset or Register Pre-Indexed. */
2964 func (stream, ", %s%s",
2965 NEGATIVE_BIT_SET ? "-" : "",
2966 arm_regnames[given & 0xf]);
2968 /* Writing back to the register that is the source/
2969 destination of the load/store is unpredictable. */
2970 if (! allow_unpredictable
2971 && WRITEBACK_BIT_SET
2972 && ((given & 0xf) == ((given >> 12) & 0xf)))
2973 is_unpredictable = TRUE;
2976 func (stream, "]%s",
2977 WRITEBACK_BIT_SET ? "!" : "");
2981 if (IMMEDIATE_BIT_SET)
2983 /* Immediate Post-indexed. */
2984 /* PR 10924: Offset must be printed, even if it is zero. */
2985 func (stream, "], #%d", offset);
2986 value_in_comment = offset;
2990 /* Register Post-indexed. */
2991 func (stream, "], %s%s",
2992 NEGATIVE_BIT_SET ? "-" : "",
2993 arm_regnames[given & 0xf]);
2995 /* Writing back to the register that is the source/
2996 destination of the load/store is unpredictable. */
2997 if (! allow_unpredictable
2998 && (given & 0xf) == ((given >> 12) & 0xf))
2999 is_unpredictable = TRUE;
3002 if (! allow_unpredictable)
3004 /* Writeback is automatically implied by post- addressing.
3005 Setting the W bit is unnecessary and ARM specify it as
3006 being unpredictable. */
3007 if (WRITEBACK_BIT_SET
3008 /* Specifying the PC register as the post-indexed
3009 registers is also unpredictable. */
3010 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
3011 is_unpredictable = TRUE;
3019 int disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
3020 info->print_address_func (disp * 4 + pc + 8, info);
3025 if (((given >> 28) & 0xf) != 0xe)
3027 arm_conditional [(given >> 28) & 0xf]);
3036 for (reg = 0; reg < 16; reg++)
3037 if ((given & (1 << reg)) != 0)
3040 func (stream, ", ");
3042 func (stream, "%s", arm_regnames[reg]);
3046 is_unpredictable = TRUE;
3051 arm_decode_shift (given, func, stream, FALSE);
3055 if ((given & 0x02000000) != 0)
3057 int rotate = (given & 0xf00) >> 7;
3058 int immed = (given & 0xff);
3060 immed = (((immed << (32 - rotate))
3061 | (immed >> rotate)) & 0xffffffff);
3062 func (stream, "#%d", immed);
3063 value_in_comment = immed;
3066 arm_decode_shift (given, func, stream, TRUE);
3070 if ((given & 0x0000f000) == 0x0000f000)
3072 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
3073 mechanism for setting PSR flag bits. They are
3074 obsolete in V6 onwards. */
3075 if ((private_data->features.core & ARM_EXT_V6) == 0)
3081 if ((given & 0x01200000) == 0x00200000)
3087 int offset = given & 0xff;
3089 value_in_comment = offset * 4;
3090 if (NEGATIVE_BIT_SET)
3091 value_in_comment = - value_in_comment;
3093 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3098 func (stream, ", #%d]%s",
3100 WRITEBACK_BIT_SET ? "!" : "");
3108 if (WRITEBACK_BIT_SET)
3111 func (stream, ", #%d", value_in_comment);
3115 func (stream, ", {%d}", offset);
3116 value_in_comment = offset;
3123 /* Print ARM V5 BLX(1) address: pc+25 bits. */
3128 if (! NEGATIVE_BIT_SET)
3129 /* Is signed, hi bits should be ones. */
3130 offset = (-1) ^ 0x00ffffff;
3132 /* Offset is (SignExtend(offset field)<<2). */
3133 offset += given & 0x00ffffff;
3135 address = offset + pc + 8;
3137 if (given & 0x01000000)
3138 /* H bit allows addressing to 2-byte boundaries. */
3141 info->print_address_func (address, info);
3147 if (given & 0x80000)
3149 if (given & 0x40000)
3151 if (given & 0x20000)
3153 if (given & 0x10000)
3158 switch (given & 0xf)
3160 case 0xf: func (stream, "sy"); break;
3161 case 0x7: func (stream, "un"); break;
3162 case 0xe: func (stream, "st"); break;
3163 case 0x6: func (stream, "unst"); break;
3165 func (stream, "#%d", (int) given & 0xf);
3170 case '0': case '1': case '2': case '3': case '4':
3171 case '5': case '6': case '7': case '8': case '9':
3174 unsigned long value;
3176 c = arm_decode_bitfield (c, given, &value, &width);
3182 is_unpredictable = TRUE;
3187 /* Eat the 'u' character. */
3191 is_unpredictable = TRUE;
3196 /* Eat the 'U' character. */
3200 is_unpredictable = TRUE;
3203 func (stream, "%s", arm_regnames[value]);
3206 func (stream, "%ld", value);
3207 value_in_comment = value;
3210 func (stream, "%ld", value * 8);
3211 value_in_comment = value * 8;
3214 func (stream, "%ld", value + 1);
3215 value_in_comment = value + 1;
3218 func (stream, "0x%08lx", value);
3220 /* Some SWI instructions have special
3222 if ((given & 0x0fffffff) == 0x0FF00000)
3223 func (stream, "\t; IMB");
3224 else if ((given & 0x0fffffff) == 0x0FF00001)
3225 func (stream, "\t; IMBRange");
3228 func (stream, "%01lx", value & 0xf);
3229 value_in_comment = value;
3234 func (stream, "%c", *c);
3238 if (value == ((1ul << width) - 1))
3239 func (stream, "%c", *c);
3242 func (stream, "%c", c[(1 << width) - (int) value]);
3254 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
3255 func (stream, "%d", imm);
3256 value_in_comment = imm;
3261 /* LSB and WIDTH fields of BFI or BFC. The machine-
3262 language instruction encodes LSB and MSB. */
3264 long msb = (given & 0x001f0000) >> 16;
3265 long lsb = (given & 0x00000f80) >> 7;
3266 long w = msb - lsb + 1;
3269 func (stream, "#%lu, #%lu", lsb, w);
3271 func (stream, "(invalid: %lu:%lu)", lsb, msb);
3276 /* 16-bit unsigned immediate from a MOVT or MOVW
3277 instruction, encoded in bits 0:11 and 15:19. */
3279 long hi = (given & 0x000f0000) >> 4;
3280 long lo = (given & 0x00000fff);
3281 long imm16 = hi | lo;
3283 func (stream, "#%lu", imm16);
3284 value_in_comment = imm16;
3294 func (stream, "%c", *c);
3297 if (value_in_comment > 32 || value_in_comment < -16)
3298 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
3300 if (is_unpredictable)
3301 func (stream, UNPREDICTABLE_INSTRUCTION);
3309 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
3312 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
3314 const struct opcode16 *insn;
3315 void *stream = info->stream;
3316 fprintf_ftype func = info->fprintf_func;
3318 for (insn = thumb_opcodes; insn->assembler; insn++)
3319 if ((given & insn->mask) == insn->value)
3321 signed long value_in_comment = 0;
3322 const char *c = insn->assembler;
3331 func (stream, "%c", *c);
3338 func (stream, "%%");
3343 func (stream, "%s", arm_conditional[IFTHEN_COND]);
3348 func (stream, "%s", arm_conditional[IFTHEN_COND]);
3357 ifthen_next_state = given & 0xff;
3358 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
3359 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
3360 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
3365 if (ifthen_next_state)
3366 func (stream, "\t; unpredictable branch in IT block\n");
3371 func (stream, "\t; unpredictable <IT:%s>",
3372 arm_conditional[IFTHEN_COND]);
3379 reg = (given >> 3) & 0x7;
3380 if (given & (1 << 6))
3383 func (stream, "%s", arm_regnames[reg]);
3392 if (given & (1 << 7))
3395 func (stream, "%s", arm_regnames[reg]);
3400 if (given & (1 << 8))
3404 if (*c == 'O' && (given & (1 << 8)))
3414 /* It would be nice if we could spot
3415 ranges, and generate the rS-rE format: */
3416 for (reg = 0; (reg < 8); reg++)
3417 if ((given & (1 << reg)) != 0)
3420 func (stream, ", ");
3422 func (stream, "%s", arm_regnames[reg]);
3428 func (stream, ", ");
3430 func (stream, arm_regnames[14] /* "lr" */);
3436 func (stream, ", ");
3437 func (stream, arm_regnames[15] /* "pc" */);
3445 /* Print writeback indicator for a LDMIA. We are doing a
3446 writeback if the base register is not in the register
3448 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
3453 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
3455 bfd_vma address = (pc + 4
3456 + ((given & 0x00f8) >> 2)
3457 + ((given & 0x0200) >> 3));
3458 info->print_address_func (address, info);
3463 /* Right shift immediate -- bits 6..10; 1-31 print
3464 as themselves, 0 prints as 32. */
3466 long imm = (given & 0x07c0) >> 6;
3469 func (stream, "#%ld", imm);
3473 case '0': case '1': case '2': case '3': case '4':
3474 case '5': case '6': case '7': case '8': case '9':
3476 int bitstart = *c++ - '0';
3479 while (*c >= '0' && *c <= '9')
3480 bitstart = (bitstart * 10) + *c++ - '0';
3489 while (*c >= '0' && *c <= '9')
3490 bitend = (bitend * 10) + *c++ - '0';
3493 reg = given >> bitstart;
3494 reg &= (2 << (bitend - bitstart)) - 1;
3499 func (stream, "%s", arm_regnames[reg]);
3503 func (stream, "%ld", reg);
3504 value_in_comment = reg;
3508 func (stream, "%ld", reg << 1);
3509 value_in_comment = reg << 1;
3513 func (stream, "%ld", reg << 2);
3514 value_in_comment = reg << 2;
3518 /* PC-relative address -- the bottom two
3519 bits of the address are dropped
3520 before the calculation. */
3521 info->print_address_func
3522 (((pc + 4) & ~3) + (reg << 2), info);
3523 value_in_comment = 0;
3527 func (stream, "0x%04lx", reg);
3531 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
3532 info->print_address_func (reg * 2 + pc + 4, info);
3533 value_in_comment = 0;
3537 func (stream, "%s", arm_conditional [reg]);
3548 if ((given & (1 << bitstart)) != 0)
3549 func (stream, "%c", *c);
3554 if ((given & (1 << bitstart)) != 0)
3555 func (stream, "%c", *c++);
3557 func (stream, "%c", *++c);
3571 if (value_in_comment > 32 || value_in_comment < -16)
3572 func (stream, "\t; 0x%lx", value_in_comment);
3580 /* Return the name of an V7M special register. */
3583 psr_name (int regno)
3587 case 0: return "APSR";
3588 case 1: return "IAPSR";
3589 case 2: return "EAPSR";
3590 case 3: return "PSR";
3591 case 5: return "IPSR";
3592 case 6: return "EPSR";
3593 case 7: return "IEPSR";
3594 case 8: return "MSP";
3595 case 9: return "PSP";
3596 case 16: return "PRIMASK";
3597 case 17: return "BASEPRI";
3598 case 18: return "BASEPRI_MASK";
3599 case 19: return "FAULTMASK";
3600 case 20: return "CONTROL";
3601 default: return "<unknown>";
3605 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
3608 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
3610 const struct opcode32 *insn;
3611 void *stream = info->stream;
3612 fprintf_ftype func = info->fprintf_func;
3614 if (print_insn_coprocessor (pc, info, given, TRUE))
3617 if (print_insn_neon (info, given, TRUE))
3620 for (insn = thumb32_opcodes; insn->assembler; insn++)
3621 if ((given & insn->mask) == insn->value)
3623 bfd_boolean is_unpredictable = FALSE;
3624 signed long value_in_comment = 0;
3625 const char *c = insn->assembler;
3631 func (stream, "%c", *c);
3638 func (stream, "%%");
3643 func (stream, "%s", arm_conditional[IFTHEN_COND]);
3647 if (ifthen_next_state)
3648 func (stream, "\t; unpredictable branch in IT block\n");
3653 func (stream, "\t; unpredictable <IT:%s>",
3654 arm_conditional[IFTHEN_COND]);
3659 unsigned int imm12 = 0;
3661 imm12 |= (given & 0x000000ffu);
3662 imm12 |= (given & 0x00007000u) >> 4;
3663 imm12 |= (given & 0x04000000u) >> 15;
3664 func (stream, "#%u", imm12);
3665 value_in_comment = imm12;
3671 unsigned int bits = 0, imm, imm8, mod;
3673 bits |= (given & 0x000000ffu);
3674 bits |= (given & 0x00007000u) >> 4;
3675 bits |= (given & 0x04000000u) >> 15;
3676 imm8 = (bits & 0x0ff);
3677 mod = (bits & 0xf00) >> 8;
3680 case 0: imm = imm8; break;
3681 case 1: imm = ((imm8 << 16) | imm8); break;
3682 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
3683 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
3685 mod = (bits & 0xf80) >> 7;
3686 imm8 = (bits & 0x07f) | 0x80;
3687 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
3689 func (stream, "#%u", imm);
3690 value_in_comment = imm;
3696 unsigned int imm = 0;
3698 imm |= (given & 0x000000ffu);
3699 imm |= (given & 0x00007000u) >> 4;
3700 imm |= (given & 0x04000000u) >> 15;
3701 imm |= (given & 0x000f0000u) >> 4;
3702 func (stream, "#%u", imm);
3703 value_in_comment = imm;
3709 unsigned int imm = 0;
3711 imm |= (given & 0x000f0000u) >> 16;
3712 imm |= (given & 0x00000ff0u) >> 0;
3713 imm |= (given & 0x0000000fu) << 12;
3714 func (stream, "#%u", imm);
3715 value_in_comment = imm;
3721 unsigned int reg = (given & 0x0000000fu);
3722 unsigned int stp = (given & 0x00000030u) >> 4;
3723 unsigned int imm = 0;
3724 imm |= (given & 0x000000c0u) >> 6;
3725 imm |= (given & 0x00007000u) >> 10;
3727 func (stream, "%s", arm_regnames[reg]);
3732 func (stream, ", lsl #%u", imm);
3738 func (stream, ", lsr #%u", imm);
3744 func (stream, ", asr #%u", imm);
3749 func (stream, ", rrx");
3751 func (stream, ", ror #%u", imm);
3758 unsigned int Rn = (given & 0x000f0000) >> 16;
3759 unsigned int U = ! NEGATIVE_BIT_SET;
3760 unsigned int op = (given & 0x00000f00) >> 8;
3761 unsigned int i12 = (given & 0x00000fff);
3762 unsigned int i8 = (given & 0x000000ff);
3763 bfd_boolean writeback = FALSE, postind = FALSE;
3766 func (stream, "[%s", arm_regnames[Rn]);
3767 if (U) /* 12-bit positive immediate offset. */
3771 value_in_comment = offset;
3773 else if (Rn == 15) /* 12-bit negative immediate offset. */
3774 offset = - (int) i12;
3775 else if (op == 0x0) /* Shifted register offset. */
3777 unsigned int Rm = (i8 & 0x0f);
3778 unsigned int sh = (i8 & 0x30) >> 4;
3780 func (stream, ", %s", arm_regnames[Rm]);
3782 func (stream, ", lsl #%u", sh);
3788 case 0xE: /* 8-bit positive immediate offset. */
3792 case 0xC: /* 8-bit negative immediate offset. */
3796 case 0xF: /* 8-bit + preindex with wb. */
3801 case 0xD: /* 8-bit - preindex with wb. */
3806 case 0xB: /* 8-bit + postindex. */
3811 case 0x9: /* 8-bit - postindex. */
3817 func (stream, ", <undefined>]");
3822 func (stream, "], #%d", offset);
3826 func (stream, ", #%d", offset);
3827 func (stream, writeback ? "]!" : "]");
3832 func (stream, "\t; ");
3833 info->print_address_func (((pc + 4) & ~3) + offset, info);
3841 unsigned int U = ! NEGATIVE_BIT_SET;
3842 unsigned int W = WRITEBACK_BIT_SET;
3843 unsigned int Rn = (given & 0x000f0000) >> 16;
3844 unsigned int off = (given & 0x000000ff);
3846 func (stream, "[%s", arm_regnames[Rn]);
3852 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
3853 value_in_comment = off * 4 * U ? 1 : -1;
3861 func (stream, "], ");
3864 func (stream, "#%c%u", U ? '+' : '-', off * 4);
3865 value_in_comment = off * 4 * U ? 1 : -1;
3869 func (stream, "{%u}", off);
3870 value_in_comment = off;
3878 unsigned int Sbit = (given & 0x01000000) >> 24;
3879 unsigned int type = (given & 0x00600000) >> 21;
3883 case 0: func (stream, Sbit ? "sb" : "b"); break;
3884 case 1: func (stream, Sbit ? "sh" : "h"); break;
3887 func (stream, "??");
3890 func (stream, "??");
3902 for (reg = 0; reg < 16; reg++)
3903 if ((given & (1 << reg)) != 0)
3906 func (stream, ", ");
3908 func (stream, "%s", arm_regnames[reg]);
3916 unsigned int msb = (given & 0x0000001f);
3917 unsigned int lsb = 0;
3919 lsb |= (given & 0x000000c0u) >> 6;
3920 lsb |= (given & 0x00007000u) >> 10;
3921 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
3927 unsigned int width = (given & 0x0000001f) + 1;
3928 unsigned int lsb = 0;
3930 lsb |= (given & 0x000000c0u) >> 6;
3931 lsb |= (given & 0x00007000u) >> 10;
3932 func (stream, "#%u, #%u", lsb, width);
3938 unsigned int S = (given & 0x04000000u) >> 26;
3939 unsigned int J1 = (given & 0x00002000u) >> 13;
3940 unsigned int J2 = (given & 0x00000800u) >> 11;
3946 offset |= (given & 0x003f0000) >> 4;
3947 offset |= (given & 0x000007ff) << 1;
3948 offset -= (1 << 20);
3950 info->print_address_func (pc + 4 + offset, info);
3956 unsigned int S = (given & 0x04000000u) >> 26;
3957 unsigned int I1 = (given & 0x00002000u) >> 13;
3958 unsigned int I2 = (given & 0x00000800u) >> 11;
3962 offset |= !(I1 ^ S) << 23;
3963 offset |= !(I2 ^ S) << 22;
3964 offset |= (given & 0x03ff0000u) >> 4;
3965 offset |= (given & 0x000007ffu) << 1;
3966 offset -= (1 << 24);
3969 /* BLX target addresses are always word aligned. */
3970 if ((given & 0x00001000u) == 0)
3973 info->print_address_func (offset, info);
3979 unsigned int shift = 0;
3981 shift |= (given & 0x000000c0u) >> 6;
3982 shift |= (given & 0x00007000u) >> 10;
3983 if (WRITEBACK_BIT_SET)
3984 func (stream, ", asr #%u", shift);
3986 func (stream, ", lsl #%u", shift);
3987 /* else print nothing - lsl #0 */
3993 unsigned int rot = (given & 0x00000030) >> 4;
3996 func (stream, ", ror #%u", rot * 8);
4001 switch (given & 0xf)
4003 case 0xf: func (stream, "sy"); break;
4004 case 0x7: func (stream, "un"); break;
4005 case 0xe: func (stream, "st"); break;
4006 case 0x6: func (stream, "unst"); break;
4008 func (stream, "#%d", (int) given & 0xf);
4014 if ((given & 0xff) == 0)
4016 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
4028 func (stream, psr_name (given & 0xff));
4033 if ((given & 0xff) == 0)
4034 func (stream, "%cPSR", (given & 0x100000) ? 'S' : 'C');
4036 func (stream, psr_name (given & 0xff));
4039 case '0': case '1': case '2': case '3': case '4':
4040 case '5': case '6': case '7': case '8': case '9':
4045 c = arm_decode_bitfield (c, given, &val, &width);
4050 func (stream, "%lu", val);
4051 value_in_comment = val;
4055 func (stream, "%lu", val * 4);
4056 value_in_comment = val * 4;
4061 is_unpredictable = TRUE;
4064 func (stream, "%s", arm_regnames[val]);
4068 func (stream, "%s", arm_conditional[val]);
4073 if (val == ((1ul << width) - 1))
4074 func (stream, "%c", *c);
4080 func (stream, "%c", *c);
4084 func (stream, "%c", c[(1 << width) - (int) val]);
4089 func (stream, "0x%lx", val & 0xffffffffUL);
4103 if (value_in_comment > 32 || value_in_comment < -16)
4104 func (stream, "\t; 0x%lx", value_in_comment);
4106 if (is_unpredictable)
4107 func (stream, UNPREDICTABLE_INSTRUCTION);
4116 /* Print data bytes on INFO->STREAM. */
4119 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
4120 struct disassemble_info *info,
4123 switch (info->bytes_per_chunk)
4126 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
4129 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
4132 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
4139 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
4140 being displayed in symbol relative addresses. */
4143 arm_symbol_is_valid (asymbol * sym,
4144 struct disassemble_info * info ATTRIBUTE_UNUSED)
4151 name = bfd_asymbol_name (sym);
4153 return (name && *name != '$');
4156 /* Parse an individual disassembler option. */
4159 parse_arm_disassembler_option (char *option)
4164 if (CONST_STRNEQ (option, "reg-names-"))
4170 for (i = NUM_ARM_REGNAMES; i--;)
4171 if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
4173 regname_selected = i;
4178 /* XXX - should break 'option' at following delimiter. */
4179 fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
4181 else if (CONST_STRNEQ (option, "force-thumb"))
4183 else if (CONST_STRNEQ (option, "no-force-thumb"))
4186 /* XXX - should break 'option' at following delimiter. */
4187 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
4192 /* Parse the string of disassembler options, spliting it at whitespaces
4193 or commas. (Whitespace separators supported for backwards compatibility). */
4196 parse_disassembler_options (char *options)
4198 if (options == NULL)
4203 parse_arm_disassembler_option (options);
4205 /* Skip forward to next seperator. */
4206 while ((*options) && (! ISSPACE (*options)) && (*options != ','))
4208 /* Skip forward past seperators. */
4209 while (ISSPACE (*options) || (*options == ','))
4214 /* Search back through the insn stream to determine if this instruction is
4215 conditionally executed. */
4218 find_ifthen_state (bfd_vma pc,
4219 struct disassemble_info *info,
4225 /* COUNT is twice the number of instructions seen. It will be odd if we
4226 just crossed an instruction boundary. */
4229 unsigned int seen_it;
4232 ifthen_address = pc;
4239 /* Scan backwards looking for IT instructions, keeping track of where
4240 instruction boundaries are. We don't know if something is actually an
4241 IT instruction until we find a definite instruction boundary. */
4244 if (addr == 0 || info->symbol_at_address_func (addr, info))
4246 /* A symbol must be on an instruction boundary, and will not
4247 be within an IT block. */
4248 if (seen_it && (count & 1))
4254 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
4259 insn = (b[0]) | (b[1] << 8);
4261 insn = (b[1]) | (b[0] << 8);
4264 if ((insn & 0xf800) < 0xe800)
4266 /* Addr + 2 is an instruction boundary. See if this matches
4267 the expected boundary based on the position of the last
4274 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
4276 /* This could be an IT instruction. */
4278 it_count = count >> 1;
4280 if ((insn & 0xf800) >= 0xe800)
4283 count = (count + 2) | 1;
4284 /* IT blocks contain at most 4 instructions. */
4285 if (count >= 8 && !seen_it)
4288 /* We found an IT instruction. */
4289 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
4290 if ((ifthen_state & 0xf) == 0)
4294 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
4298 is_mapping_symbol (struct disassemble_info *info, int n,
4299 enum map_type *map_type)
4303 name = bfd_asymbol_name (info->symtab[n]);
4304 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
4305 && (name[2] == 0 || name[2] == '.'))
4307 *map_type = ((name[1] == 'a') ? MAP_ARM
4308 : (name[1] == 't') ? MAP_THUMB
4316 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
4317 Returns nonzero if *MAP_TYPE was set. */
4320 get_map_sym_type (struct disassemble_info *info,
4322 enum map_type *map_type)
4324 /* If the symbol is in a different section, ignore it. */
4325 if (info->section != NULL && info->section != info->symtab[n]->section)
4328 return is_mapping_symbol (info, n, map_type);
4331 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
4332 Returns nonzero if *MAP_TYPE was set. */
4335 get_sym_code_type (struct disassemble_info *info,
4337 enum map_type *map_type)
4339 elf_symbol_type *es;
4342 /* If the symbol is in a different section, ignore it. */
4343 if (info->section != NULL && info->section != info->symtab[n]->section)
4346 es = *(elf_symbol_type **)(info->symtab + n);
4347 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
4349 /* If the symbol has function type then use that. */
4350 if (type == STT_FUNC || type == STT_ARM_TFUNC)
4352 *map_type = (type == STT_ARM_TFUNC) ? MAP_THUMB : MAP_ARM;
4359 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
4360 of the supplied arm_feature_set structure with bitmasks indicating
4361 the support base architectures and coprocessor extensions.
4363 FIXME: This could more efficiently implemented as a constant array,
4364 although it would also be less robust. */
4367 select_arm_features (unsigned long mach,
4368 arm_feature_set * features)
4371 #define ARM_FEATURE(ARCH,CEXT) \
4372 features->core = (ARCH); \
4373 features->coproc = (CEXT) | FPU_FPA; \
4378 case bfd_mach_arm_2: ARM_ARCH_V2;
4379 case bfd_mach_arm_2a: ARM_ARCH_V2S;
4380 case bfd_mach_arm_3: ARM_ARCH_V3;
4381 case bfd_mach_arm_3M: ARM_ARCH_V3M;
4382 case bfd_mach_arm_4: ARM_ARCH_V4;
4383 case bfd_mach_arm_4T: ARM_ARCH_V4T;
4384 case bfd_mach_arm_5: ARM_ARCH_V5;
4385 case bfd_mach_arm_5T: ARM_ARCH_V5T;
4386 case bfd_mach_arm_5TE: ARM_ARCH_V5TE;
4387 case bfd_mach_arm_XScale: ARM_ARCH_XSCALE;
4388 case bfd_mach_arm_ep9312: ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK | FPU_MAVERICK);
4389 case bfd_mach_arm_iWMMXt: ARM_ARCH_IWMMXT;
4390 case bfd_mach_arm_iWMMXt2: ARM_ARCH_IWMMXT2;
4391 /* If the machine type is unknown allow all
4392 architecture types and all extensions. */
4393 case bfd_mach_arm_unknown: ARM_FEATURE (-1UL, -1UL);
4400 /* NOTE: There are no checks in these routines that
4401 the relevant number of data bytes exist. */
4404 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
4409 int is_thumb = FALSE;
4410 int is_data = FALSE;
4412 unsigned int size = 4;
4413 void (*printer) (bfd_vma, struct disassemble_info *, long);
4414 bfd_boolean found = FALSE;
4415 struct arm_private_data *private_data;
4417 if (info->disassembler_options)
4419 parse_disassembler_options (info->disassembler_options);
4421 /* To avoid repeated parsing of these options, we remove them here. */
4422 info->disassembler_options = NULL;
4425 /* PR 10288: Control which instructions will be disassembled. */
4426 if (info->private_data == NULL)
4428 static struct arm_private_data private;
4430 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
4431 /* If the user did not use the -m command line switch then default to
4432 disassembling all types of ARM instruction.
4434 The info->mach value has to be ignored as this will be based on
4435 the default archictecture for the target and/or hints in the notes
4436 section, but it will never be greater than the current largest arm
4437 machine value (iWMMXt2), which is only equivalent to the V5TE
4438 architecture. ARM architectures have advanced beyond the machine
4439 value encoding, and these newer architectures would be ignored if
4440 the machine value was used.
4442 Ie the -m switch is used to restrict which instructions will be
4443 disassembled. If it is necessary to use the -m switch to tell
4444 objdump that an ARM binary is being disassembled, eg because the
4445 input is a raw binary file, but it is also desired to disassemble
4446 all ARM instructions then use "-marm". This will select the
4447 "unknown" arm architecture which is compatible with any ARM
4449 info->mach = bfd_mach_arm_unknown;
4451 /* Compute the architecture bitmask from the machine number.
4452 Note: This assumes that the machine number will not change
4453 during disassembly.... */
4454 select_arm_features (info->mach, & private.features);
4456 private.has_mapping_symbols = -1;
4458 info->private_data = & private;
4461 private_data = info->private_data;
4463 /* Decide if our code is going to be little-endian, despite what the
4464 function argument might say. */
4465 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
4467 /* For ELF, consult the symbol table to determine what kind of code
4469 if (info->symtab_size != 0
4470 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
4475 enum map_type type = MAP_ARM;
4477 /* Start scanning at the start of the function, or wherever
4478 we finished last time. */
4479 start = info->symtab_pos + 1;
4480 if (start < last_mapping_sym)
4481 start = last_mapping_sym;
4484 /* First, look for mapping symbols. */
4485 if (private_data->has_mapping_symbols != 0)
4487 /* Scan up to the location being disassembled. */
4488 for (n = start; n < info->symtab_size; n++)
4490 addr = bfd_asymbol_value (info->symtab[n]);
4493 if (get_map_sym_type (info, n, &type))
4502 /* No mapping symbol found at this address. Look backwards
4503 for a preceeding one. */
4504 for (n = start - 1; n >= 0; n--)
4506 if (get_map_sym_type (info, n, &type))
4516 private_data->has_mapping_symbols = 1;
4518 /* No mapping symbols were found. A leading $d may be
4519 omitted for sections which start with data; but for
4520 compatibility with legacy and stripped binaries, only
4521 assume the leading $d if there is at least one mapping
4522 symbol in the file. */
4523 if (!found && private_data->has_mapping_symbols == -1)
4525 /* Look for mapping symbols, in any section. */
4526 for (n = 0; n < info->symtab_size; n++)
4527 if (is_mapping_symbol (info, n, &type))
4529 private_data->has_mapping_symbols = 1;
4532 if (private_data->has_mapping_symbols == -1)
4533 private_data->has_mapping_symbols = 0;
4536 if (!found && private_data->has_mapping_symbols == 1)
4543 /* Next search for function symbols to separate ARM from Thumb
4544 in binaries without mapping symbols. */
4547 /* Scan up to the location being disassembled. */
4548 for (n = start; n < info->symtab_size; n++)
4550 addr = bfd_asymbol_value (info->symtab[n]);
4553 if (get_sym_code_type (info, n, &type))
4562 /* No mapping symbol found at this address. Look backwards
4563 for a preceeding one. */
4564 for (n = start - 1; n >= 0; n--)
4566 if (get_sym_code_type (info, n, &type))
4576 last_mapping_sym = last_sym;
4578 is_thumb = (last_type == MAP_THUMB);
4579 is_data = (last_type == MAP_DATA);
4581 /* Look a little bit ahead to see if we should print out
4582 two or four bytes of data. If there's a symbol,
4583 mapping or otherwise, after two bytes then don't
4587 size = 4 - (pc & 3);
4588 for (n = last_sym + 1; n < info->symtab_size; n++)
4590 addr = bfd_asymbol_value (info->symtab[n]);
4592 && (info->section == NULL
4593 || info->section == info->symtab[n]->section))
4595 if (addr - pc < size)
4600 /* If the next symbol is after three bytes, we need to
4601 print only part of the data, so that we can use either
4604 size = (pc & 1) ? 1 : 2;
4608 if (info->symbols != NULL)
4610 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
4612 coff_symbol_type * cs;
4614 cs = coffsymbol (*info->symbols);
4615 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
4616 || cs->native->u.syment.n_sclass == C_THUMBSTAT
4617 || cs->native->u.syment.n_sclass == C_THUMBLABEL
4618 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
4619 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
4621 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
4624 /* If no mapping symbol has been found then fall back to the type
4625 of the function symbol. */
4626 elf_symbol_type * es;
4629 es = *(elf_symbol_type **)(info->symbols);
4630 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
4632 is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT);
4640 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
4642 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
4644 info->bytes_per_line = 4;
4646 /* PR 10263: Disassemble data if requested to do so by the user. */
4647 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
4651 /* Size was already set above. */
4652 info->bytes_per_chunk = size;
4653 printer = print_insn_data;
4655 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
4658 for (i = size - 1; i >= 0; i--)
4659 given = b[i] | (given << 8);
4661 for (i = 0; i < (int) size; i++)
4662 given = b[i] | (given << 8);
4666 /* In ARM mode endianness is a straightforward issue: the instruction
4667 is four bytes long and is either ordered 0123 or 3210. */
4668 printer = print_insn_arm;
4669 info->bytes_per_chunk = 4;
4672 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
4674 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
4676 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
4680 /* In Thumb mode we have the additional wrinkle of two
4681 instruction lengths. Fortunately, the bits that determine
4682 the length of the current instruction are always to be found
4683 in the first two bytes. */
4684 printer = print_insn_thumb16;
4685 info->bytes_per_chunk = 2;
4688 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
4690 given = (b[0]) | (b[1] << 8);
4692 given = (b[1]) | (b[0] << 8);
4696 /* These bit patterns signal a four-byte Thumb
4698 if ((given & 0xF800) == 0xF800
4699 || (given & 0xF800) == 0xF000
4700 || (given & 0xF800) == 0xE800)
4702 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
4704 given = (b[0]) | (b[1] << 8) | (given << 16);
4706 given = (b[1]) | (b[0] << 8) | (given << 16);
4708 printer = print_insn_thumb32;
4713 if (ifthen_address != pc)
4714 find_ifthen_state (pc, info, little_code);
4718 if ((ifthen_state & 0xf) == 0x8)
4719 ifthen_next_state = 0;
4721 ifthen_next_state = (ifthen_state & 0xe0)
4722 | ((ifthen_state & 0xf) << 1);
4728 info->memory_error_func (status, pc, info);
4731 if (info->flags & INSN_HAS_RELOC)
4732 /* If the instruction has a reloc associated with it, then
4733 the offset field in the instruction will actually be the
4734 addend for the reloc. (We are using REL type relocs).
4735 In such cases, we can ignore the pc when computing
4736 addresses, since the addend is not currently pc-relative. */
4739 printer (pc, info, given);
4743 ifthen_state = ifthen_next_state;
4744 ifthen_address += size;
4750 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
4752 /* Detect BE8-ness and record it in the disassembler info. */
4753 if (info->flavour == bfd_target_elf_flavour
4754 && info->section != NULL
4755 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
4756 info->endian_code = BFD_ENDIAN_LITTLE;
4758 return print_insn (pc, info, FALSE);
4762 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
4764 return print_insn (pc, info, TRUE);
4768 print_arm_disassembler_options (FILE *stream)
4772 fprintf (stream, _("\n\
4773 The following ARM specific disassembler options are supported for use with\n\
4774 the -M switch:\n"));
4776 for (i = NUM_ARM_REGNAMES; i--;)
4777 fprintf (stream, " reg-names-%s %*c%s\n",
4779 (int)(14 - strlen (regnames[i].name)), ' ',
4780 regnames[i].description);
4782 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
4783 fprintf (stream, " no-force-thumb Examine preceeding label to determine an insn's type\n\n");