1 /* Instruction printing code for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
3 Free Software Foundation, Inc.
4 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
5 Modification by James G. Smith (jsmith@cygnus.co.uk)
7 This file is part of libopcodes.
9 This program is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 2 of the License, or (at your option)
14 This program is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
26 #include "opcode/arm.h"
28 #include "safe-ctype.h"
30 /* FIXME: This shouldn't be done here. */
31 #include "coff/internal.h"
34 #include "elf/internal.h"
37 /* FIXME: Belongs in global header. */
39 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
43 #define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
48 unsigned long arch; /* Architecture defining this insn. */
49 unsigned long value, mask; /* Recognise insn if (op&mask)==value. */
50 const char *assembler; /* How to disassemble this insn. */
55 unsigned long arch; /* Architecture defining this insn. */
56 unsigned short value, mask; /* Recognise insn if (op&mask)==value. */
57 const char *assembler; /* How to disassemble this insn. */
60 /* print_insn_coprocessor recognizes the following format control codes:
64 %c print condition code (always bits 28-31)
65 %A print address for ldc/stc/ldf/stf instruction
66 %B print vstm/vldm register list
67 %C print vstr/vldr address operand
68 %I print cirrus signed shift immediate: bits 0..3|4..6
69 %F print the COUNT field of a LFM/SFM instruction.
70 %P print floating point precision in arithmetic insn
71 %Q print floating point precision in ldf/stf insn
72 %R print floating point rounding mode
74 %<bitfield>r print as an ARM register
75 %<bitfield>d print the bitfield in decimal
76 %<bitfield>k print immediate for VFPv3 conversion instruction
77 %<bitfield>x print the bitfield in hex
78 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
79 %<bitfield>f print a floating point constant if >7 else a
80 floating point register
81 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
82 %<bitfield>g print as an iWMMXt 64-bit register
83 %<bitfield>G print as an iWMMXt general purpose or control register
84 %<bitfield>D print as a NEON D register
85 %<bitfield>Q print as a NEON Q register
87 %y<code> print a single precision VFP reg.
88 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
89 %z<code> print a double precision VFP reg
90 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
92 %<bitfield>'c print specified char iff bitfield is all ones
93 %<bitfield>`c print specified char iff bitfield is all zeroes
94 %<bitfield>?ab... select from array of values in big endian order
96 %L print as an iWMMXt N/M width field.
97 %Z print the Immediate of a WSHUFH instruction.
98 %l like 'A' except use byte offsets for 'B' & 'H'
101 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
103 static const struct opcode32 coprocessor_opcodes[] =
105 /* XScale instructions. */
106 {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"},
107 {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"},
108 {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
109 {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
110 {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
112 /* Intel Wireless MMX technology instructions. */
113 #define FIRST_IWMMXT_INSN 0x0e130130
114 #define IWMMXT_INSN_COUNT 47
115 {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
116 {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
117 {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
118 {ARM_CEXT_XSCALE, 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
119 {ARM_CEXT_XSCALE, 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
120 {ARM_CEXT_XSCALE, 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
121 {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
122 {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
123 {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
124 {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
125 {ARM_CEXT_XSCALE, 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
126 {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
127 {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
128 {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
129 {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
130 {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
131 {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
132 {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
133 {ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
134 {ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
135 {ARM_CEXT_XSCALE, 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
136 {ARM_CEXT_XSCALE, 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
137 {ARM_CEXT_XSCALE, 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
138 {ARM_CEXT_XSCALE, 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
139 {ARM_CEXT_XSCALE, 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
140 {ARM_CEXT_XSCALE, 0x0e800100, 0x0fd00ff0, "wmadd%21?su%c\t%12-15g, %16-19g, %0-3g"},
141 {ARM_CEXT_XSCALE, 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
142 {ARM_CEXT_XSCALE, 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
143 {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%c\t%12-15g, %16-19g, %0-3g"},
144 {ARM_CEXT_XSCALE, 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
145 {ARM_CEXT_XSCALE, 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
146 {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
147 {ARM_CEXT_XSCALE, 0x0e300148, 0x0f300ffc, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
148 {ARM_CEXT_XSCALE, 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
149 {ARM_CEXT_XSCALE, 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
150 {ARM_CEXT_XSCALE, 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
151 {ARM_CEXT_XSCALE, 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
152 {ARM_CEXT_XSCALE, 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
153 {ARM_CEXT_XSCALE, 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
154 {ARM_CEXT_XSCALE, 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
155 {ARM_CEXT_XSCALE, 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
156 {ARM_CEXT_XSCALE, 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
157 {ARM_CEXT_XSCALE, 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
158 {ARM_CEXT_XSCALE, 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
159 {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0f100fff, "wunpckeh%21?su%22-23w%c\t%12-15g, %16-19g"},
160 {ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
161 {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
162 {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
163 {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
165 /* Floating point coprocessor (FPA) instructions */
166 {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
167 {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
168 {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
169 {FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
170 {FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
171 {FPU_FPA_EXT_V1, 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
172 {FPU_FPA_EXT_V1, 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
173 {FPU_FPA_EXT_V1, 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
174 {FPU_FPA_EXT_V1, 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
175 {FPU_FPA_EXT_V1, 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
176 {FPU_FPA_EXT_V1, 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
177 {FPU_FPA_EXT_V1, 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
178 {FPU_FPA_EXT_V1, 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
179 {FPU_FPA_EXT_V1, 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
180 {FPU_FPA_EXT_V1, 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
181 {FPU_FPA_EXT_V1, 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
182 {FPU_FPA_EXT_V1, 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
183 {FPU_FPA_EXT_V1, 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
184 {FPU_FPA_EXT_V1, 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
185 {FPU_FPA_EXT_V1, 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
186 {FPU_FPA_EXT_V1, 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
187 {FPU_FPA_EXT_V1, 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
188 {FPU_FPA_EXT_V1, 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
189 {FPU_FPA_EXT_V1, 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
190 {FPU_FPA_EXT_V1, 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
191 {FPU_FPA_EXT_V1, 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
192 {FPU_FPA_EXT_V1, 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
193 {FPU_FPA_EXT_V1, 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
194 {FPU_FPA_EXT_V1, 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
195 {FPU_FPA_EXT_V1, 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
196 {FPU_FPA_EXT_V1, 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
197 {FPU_FPA_EXT_V1, 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
198 {FPU_FPA_EXT_V1, 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
199 {FPU_FPA_EXT_V1, 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
200 {FPU_FPA_EXT_V1, 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
201 {FPU_FPA_EXT_V1, 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
202 {FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
203 {FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
204 {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
205 {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
206 {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
207 {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
208 {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
210 /* Register load/store */
211 {FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %C"},
212 {FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %C"},
213 {FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %B"},
214 {FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %B"},
215 {FPU_NEON_EXT_V1, 0x0d000b00, 0x0f900f00, "vstmdb%c\t%16-19r%21'!, %B"},
216 {FPU_NEON_EXT_V1, 0x0d100b00, 0x0f900f00, "vldmdb%c\t%16-19r%21'!, %B"},
218 /* Data transfer between ARM and NEON registers */
219 {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
220 {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
221 {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
222 {FPU_NEON_EXT_V1, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
223 {FPU_NEON_EXT_V1, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
224 {FPU_NEON_EXT_V1, 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
225 {FPU_NEON_EXT_V1, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
226 {FPU_NEON_EXT_V1, 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
227 {FPU_NEON_EXT_V1, 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
228 {FPU_NEON_EXT_V1, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
229 {FPU_NEON_EXT_V1, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
230 {FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
231 {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
232 {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
234 /* Floating point coprocessor (VFP) instructions */
235 {FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "fmstat%c"},
236 {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "fmxr%c\tfpsid, %12-15r"},
237 {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "fmxr%c\tfpscr, %12-15r"},
238 {FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "fmxr%c\tfpexc, %12-15r"},
239 {FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "fmxr%c\tfpinst, %12-15r\t@ Impl def"},
240 {FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "fmxr%c\tfpinst2, %12-15r\t@ Impl def"},
241 {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpsid"},
242 {FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpscr"},
243 {FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpexc"},
244 {FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst\t@ Impl def"},
245 {FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst2\t@ Impl def"},
246 {FPU_VFP_EXT_V1, 0x0e000b10, 0x0ff00fff, "fmdlr%c\t%z2, %12-15r"},
247 {FPU_VFP_EXT_V1, 0x0e100b10, 0x0ff00fff, "fmrdl%c\t%12-15r, %z2"},
248 {FPU_VFP_EXT_V1, 0x0e200b10, 0x0ff00fff, "fmdhr%c\t%z2, %12-15r"},
249 {FPU_VFP_EXT_V1, 0x0e300b10, 0x0ff00fff, "fmrdh%c\t%12-15r, %z2"},
250 {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "fmxr%c\t<impl def 0x%16-19x>, %12-15r"},
251 {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "fmrx%c\t%12-15r, <impl def 0x%16-19x>"},
252 {FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "fmsr%c\t%y2, %12-15r"},
253 {FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "fmrs%c\t%12-15r, %y2"},
254 {FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "fcmp%7'ezs%c\t%y1"},
255 {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fbf0f70, "fcmp%7'ezd%c\t%z1"},
256 {FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "fcpys%c\t%y1, %y0"},
257 {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "fabss%c\t%y1, %y0"},
258 {FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fbf0fd0, "fcpyd%c\t%z1, %z0"},
259 {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fbf0fd0, "fabsd%c\t%z1, %z0"},
260 {FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "fnegs%c\t%y1, %y0"},
261 {FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "fsqrts%c\t%y1, %y0"},
262 {FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fbf0fd0, "fnegd%c\t%z1, %z0"},
263 {FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fbf0fd0, "fsqrtd%c\t%z1, %z0"},
264 {FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fbf0fd0, "fcvtds%c\t%z1, %y0"},
265 {FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0fd0, "fcvtsd%c\t%y1, %z0"},
266 {FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0fd0, "fuitos%c\t%y1, %y0"},
267 {FPU_VFP_EXT_V1xD, 0x0eb80ac0, 0x0fbf0fd0, "fsitos%c\t%y1, %y0"},
268 {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0fd0, "fuitod%c\t%z1, %y0"},
269 {FPU_VFP_EXT_V1, 0x0eb80bc0, 0x0fbf0fd0, "fsitod%c\t%z1, %y0"},
270 {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "fcmp%7'es%c\t%y1, %y0"},
271 {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "fcmp%7'ed%c\t%z1, %z0"},
272 {FPU_VFP_EXT_V3, 0x0eba0a40, 0x0fbe0f50, "f%16?us%7?lhtos%c\t%y1, #%5,0-3k"},
273 {FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "f%16?us%7?lhtod%c\t%z1, #%5,0-3k"},
274 {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "fto%16?sui%7'zs%c\t%y1, %y0"},
275 {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "fto%16?sui%7'zd%c\t%y1, %z0"},
276 {FPU_VFP_EXT_V3, 0x0ebe0a40, 0x0fbe0f50, "fto%16?us%7?lhs%c\t%y1, #%5,0-3k"},
277 {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "fto%16?us%7?lhd%c\t%z1, #%5,0-3k"},
278 {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "fmrrd%c\t%12-15r, %16-19r, %z0"},
279 {FPU_VFP_EXT_V3, 0x0eb00a00, 0x0fb00ff0, "fconsts%c\t%y1, #%16-19,0-3d"},
280 {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "fconstd%c\t%z1, #%16-19,0-3d"},
281 {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "fmsrr%c\t%12-15r, %16-19r, %y4"},
282 {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "fmdrr%c\t%z0, %12-15r, %16-19r"},
283 {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "fmrrs%c\t%12-15r, %16-19r, %y4"},
284 {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "fmacs%c\t%y1, %y2, %y0"},
285 {FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "fnmacs%c\t%y1, %y2, %y0"},
286 {FPU_VFP_EXT_V1, 0x0e000b00, 0x0fb00f50, "fmacd%c\t%z1, %z2, %z0"},
287 {FPU_VFP_EXT_V1, 0x0e000b40, 0x0fb00f50, "fnmacd%c\t%z1, %z2, %z0"},
288 {FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "fmscs%c\t%y1, %y2, %y0"},
289 {FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "fnmscs%c\t%y1, %y2, %y0"},
290 {FPU_VFP_EXT_V1, 0x0e100b00, 0x0fb00f50, "fmscd%c\t%z1, %z2, %z0"},
291 {FPU_VFP_EXT_V1, 0x0e100b40, 0x0fb00f50, "fnmscd%c\t%z1, %z2, %z0"},
292 {FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "fmuls%c\t%y1, %y2, %y0"},
293 {FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "fnmuls%c\t%y1, %y2, %y0"},
294 {FPU_VFP_EXT_V1, 0x0e200b00, 0x0fb00f50, "fmuld%c\t%z1, %z2, %z0"},
295 {FPU_VFP_EXT_V1, 0x0e200b40, 0x0fb00f50, "fnmuld%c\t%z1, %z2, %z0"},
296 {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "fadds%c\t%y1, %y2, %y0"},
297 {FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "fsubs%c\t%y1, %y2, %y0"},
298 {FPU_VFP_EXT_V1, 0x0e300b00, 0x0fb00f50, "faddd%c\t%z1, %z2, %z0"},
299 {FPU_VFP_EXT_V1, 0x0e300b40, 0x0fb00f50, "fsubd%c\t%z1, %z2, %z0"},
300 {FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "fdivs%c\t%y1, %y2, %y0"},
301 {FPU_VFP_EXT_V1, 0x0e800b00, 0x0fb00f50, "fdivd%c\t%z1, %z2, %z0"},
302 {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "fstmdbs%c\t%16-19r!, %y3"},
303 {FPU_VFP_EXT_V1xD, 0x0d200b00, 0x0fb00f00, "fstmdb%0?xd%c\t%16-19r!, %z3"},
304 {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "fldmdbs%c\t%16-19r!, %y3"},
305 {FPU_VFP_EXT_V1xD, 0x0d300b00, 0x0fb00f00, "fldmdb%0?xd%c\t%16-19r!, %z3"},
306 {FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "fsts%c\t%y1, %A"},
307 {FPU_VFP_EXT_V1, 0x0d000b00, 0x0f300f00, "fstd%c\t%z1, %A"},
308 {FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "flds%c\t%y1, %A"},
309 {FPU_VFP_EXT_V1, 0x0d100b00, 0x0f300f00, "fldd%c\t%z1, %A"},
310 {FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "fstmias%c\t%16-19r%21'!, %y3"},
311 {FPU_VFP_EXT_V1xD, 0x0c800b00, 0x0f900f00, "fstmia%0?xd%c\t%16-19r%21'!, %z3"},
312 {FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "fldmias%c\t%16-19r%21'!, %y3"},
313 {FPU_VFP_EXT_V1xD, 0x0c900b00, 0x0f900f00, "fldmia%0?xd%c\t%16-19r%21'!, %z3"},
315 /* Cirrus coprocessor instructions. */
316 {ARM_CEXT_MAVERICK, 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
317 {ARM_CEXT_MAVERICK, 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
318 {ARM_CEXT_MAVERICK, 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
319 {ARM_CEXT_MAVERICK, 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
320 {ARM_CEXT_MAVERICK, 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
321 {ARM_CEXT_MAVERICK, 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
322 {ARM_CEXT_MAVERICK, 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
323 {ARM_CEXT_MAVERICK, 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
324 {ARM_CEXT_MAVERICK, 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
325 {ARM_CEXT_MAVERICK, 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
326 {ARM_CEXT_MAVERICK, 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
327 {ARM_CEXT_MAVERICK, 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
328 {ARM_CEXT_MAVERICK, 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
329 {ARM_CEXT_MAVERICK, 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
330 {ARM_CEXT_MAVERICK, 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
331 {ARM_CEXT_MAVERICK, 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
332 {ARM_CEXT_MAVERICK, 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
333 {ARM_CEXT_MAVERICK, 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
334 {ARM_CEXT_MAVERICK, 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
335 {ARM_CEXT_MAVERICK, 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
336 {ARM_CEXT_MAVERICK, 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
337 {ARM_CEXT_MAVERICK, 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
338 {ARM_CEXT_MAVERICK, 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
339 {ARM_CEXT_MAVERICK, 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
340 {ARM_CEXT_MAVERICK, 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
341 {ARM_CEXT_MAVERICK, 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
342 {ARM_CEXT_MAVERICK, 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
343 {ARM_CEXT_MAVERICK, 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
344 {ARM_CEXT_MAVERICK, 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
345 {ARM_CEXT_MAVERICK, 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
346 {ARM_CEXT_MAVERICK, 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
347 {ARM_CEXT_MAVERICK, 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
348 {ARM_CEXT_MAVERICK, 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
349 {ARM_CEXT_MAVERICK, 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
350 {ARM_CEXT_MAVERICK, 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
351 {ARM_CEXT_MAVERICK, 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
352 {ARM_CEXT_MAVERICK, 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
353 {ARM_CEXT_MAVERICK, 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
354 {ARM_CEXT_MAVERICK, 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
355 {ARM_CEXT_MAVERICK, 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
356 {ARM_CEXT_MAVERICK, 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
357 {ARM_CEXT_MAVERICK, 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
358 {ARM_CEXT_MAVERICK, 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
359 {ARM_CEXT_MAVERICK, 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
360 {ARM_CEXT_MAVERICK, 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
361 {ARM_CEXT_MAVERICK, 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
362 {ARM_CEXT_MAVERICK, 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
363 {ARM_CEXT_MAVERICK, 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
364 {ARM_CEXT_MAVERICK, 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
365 {ARM_CEXT_MAVERICK, 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
366 {ARM_CEXT_MAVERICK, 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
367 {ARM_CEXT_MAVERICK, 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
368 {ARM_CEXT_MAVERICK, 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
369 {ARM_CEXT_MAVERICK, 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
370 {ARM_CEXT_MAVERICK, 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
371 {ARM_CEXT_MAVERICK, 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
372 {ARM_CEXT_MAVERICK, 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
373 {ARM_CEXT_MAVERICK, 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
374 {ARM_CEXT_MAVERICK, 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
375 {ARM_CEXT_MAVERICK, 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
376 {ARM_CEXT_MAVERICK, 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
377 {ARM_CEXT_MAVERICK, 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
378 {ARM_CEXT_MAVERICK, 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
379 {ARM_CEXT_MAVERICK, 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
380 {ARM_CEXT_MAVERICK, 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
381 {ARM_CEXT_MAVERICK, 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
382 {ARM_CEXT_MAVERICK, 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
383 {ARM_CEXT_MAVERICK, 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
384 {ARM_CEXT_MAVERICK, 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
385 {ARM_CEXT_MAVERICK, 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
386 {ARM_CEXT_MAVERICK, 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
387 {ARM_CEXT_MAVERICK, 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
388 {ARM_CEXT_MAVERICK, 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
389 {ARM_CEXT_MAVERICK, 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
390 {ARM_CEXT_MAVERICK, 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
391 {ARM_CEXT_MAVERICK, 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
392 {ARM_CEXT_MAVERICK, 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
393 {ARM_CEXT_MAVERICK, 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
394 {ARM_CEXT_MAVERICK, 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
395 {ARM_CEXT_MAVERICK, 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
396 {ARM_CEXT_MAVERICK, 0x0e000600, 0x0ff00f10, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
397 {ARM_CEXT_MAVERICK, 0x0e100600, 0x0ff00f10, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
398 {ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
399 {ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
401 /* Generic coprocessor instructions */
402 {ARM_EXT_V2, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
403 {ARM_EXT_V2, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
404 {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
405 {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
406 {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
407 {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%c%22'l\t%8-11d, cr%12-15d, %A"},
408 {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%c%22'l\t%8-11d, cr%12-15d, %A"},
410 /* V6 coprocessor instructions */
411 {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
412 {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
414 /* V5 coprocessor instructions */
415 {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l\t%8-11d, cr%12-15d, %A"},
416 {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l\t%8-11d, cr%12-15d, %A"},
417 {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
418 {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
419 {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
424 /* Neon opcode table: This does not encode the top byte -- that is
425 checked by the print_insn_neon routine, as it depends on whether we are
426 doing thumb32 or arm32 disassembly. */
428 /* print_insn_neon recognizes the following format control codes:
432 %A print v{st,ld}[1234] operands
433 %B print v{st,ld}[1234] any one operands
434 %C print v{st,ld}[1234] single->all operands
436 %E print vmov, vmvn, vorr, vbic encoded constant
437 %F print vtbl,vtbx register list
439 %<bitfield>r print as an ARM register
440 %<bitfield>d print the bitfield in decimal
441 %<bitfield>e print the 2^N - bitfield in decimal
442 %<bitfield>D print as a NEON D register
443 %<bitfield>Q print as a NEON Q register
444 %<bitfield>R print as a NEON D or Q register
445 %<bitfield>Sn print byte scaled width limited by n
446 %<bitfield>Tn print short scaled width limited by n
447 %<bitfield>Un print long scaled width limited by n
449 %<bitfield>'c print specified char iff bitfield is all ones
450 %<bitfield>`c print specified char iff bitfield is all zeroes
451 %<bitfield>?ab... select from array of values in big endian order */
453 static const struct opcode32 neon_opcodes[] =
456 {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
457 {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
459 /* Move data element to all lanes */
460 {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup.32\t%12-15,22R, %0-3,5D[%19d]"},
461 {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup.16\t%12-15,22R, %0-3,5D[%18-19d]"},
462 {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup.8\t%12-15,22R, %0-3,5D[%17-19d]"},
465 {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl.8\t%12-15,22D, %F, %0-3,5D"},
466 {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx.8\t%12-15,22D, %F, %0-3,5D"},
468 /* Two registers, miscellaneous */
469 {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl.%24?us8\t%12-15,22Q, %0-3,5D"},
470 {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl.%24?us16\t%12-15,22Q, %0-3,5D"},
471 {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl.%24?us32\t%12-15,22Q, %0-3,5D"},
472 {FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt.8\t%12-15,22R, %0-3,5R"},
473 {FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn\t%12-15,22R, %0-3,5R"},
474 {FPU_NEON_EXT_V1, 0xf3b20000, 0xffbf0f90, "vswp\t%12-15,22R, %0-3,5R"},
475 {FPU_NEON_EXT_V1, 0xf3b20200, 0xffb30fd0, "vmovn.i%18-19S2\t%12-15,22D, %0-3,5Q"},
476 {FPU_NEON_EXT_V1, 0xf3b20240, 0xffb30fd0, "vqmovun.s%18-19T2\t%12-15,22D, %0-3,5Q"},
477 {FPU_NEON_EXT_V1, 0xf3b20280, 0xffb30fd0, "vqmovn.s%18-19T2\t%12-15,22D, %0-3,5Q"},
478 {FPU_NEON_EXT_V1, 0xf3b202c0, 0xffb30fd0, "vqmovn.u%18-19T2\t%12-15,22D, %0-3,5Q"},
479 {FPU_NEON_EXT_V1, 0xf3b20300, 0xffb30fd0, "vshll.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
480 {FPU_NEON_EXT_V1, 0xf3bb0400, 0xffbf0e90, "vrecpe.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
481 {FPU_NEON_EXT_V1, 0xf3bb0480, 0xffbf0e90, "vrsqrte.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
482 {FPU_NEON_EXT_V1, 0xf3b00000, 0xffb30f90, "vrev64.%18-19S2\t%12-15,22R, %0-3,5R"},
483 {FPU_NEON_EXT_V1, 0xf3b00080, 0xffb30f90, "vrev32.%18-19S2\t%12-15,22R, %0-3,5R"},
484 {FPU_NEON_EXT_V1, 0xf3b00100, 0xffb30f90, "vrev16.%18-19S2\t%12-15,22R, %0-3,5R"},
485 {FPU_NEON_EXT_V1, 0xf3b00400, 0xffb30f90, "vcls.s%18-19S2\t%12-15,22R, %0-3,5R"},
486 {FPU_NEON_EXT_V1, 0xf3b00480, 0xffb30f90, "vclz.i%18-19S2\t%12-15,22R, %0-3,5R"},
487 {FPU_NEON_EXT_V1, 0xf3b00700, 0xffb30f90, "vqabs.s%18-19S2\t%12-15,22R, %0-3,5R"},
488 {FPU_NEON_EXT_V1, 0xf3b00780, 0xffb30f90, "vqneg.s%18-19S2\t%12-15,22R, %0-3,5R"},
489 {FPU_NEON_EXT_V1, 0xf3b20080, 0xffb30f90, "vtrn.%18-19S2\t%12-15,22R, %0-3,5R"},
490 {FPU_NEON_EXT_V1, 0xf3b20100, 0xffb30f90, "vuzp.%18-19S2\t%12-15,22R, %0-3,5R"},
491 {FPU_NEON_EXT_V1, 0xf3b20180, 0xffb30f90, "vzip.%18-19S2\t%12-15,22R, %0-3,5R"},
492 {FPU_NEON_EXT_V1, 0xf3b10000, 0xffb30b90, "vcgt.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
493 {FPU_NEON_EXT_V1, 0xf3b10080, 0xffb30b90, "vcge.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
494 {FPU_NEON_EXT_V1, 0xf3b10100, 0xffb30b90, "vceq.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
495 {FPU_NEON_EXT_V1, 0xf3b10180, 0xffb30b90, "vcle.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
496 {FPU_NEON_EXT_V1, 0xf3b10200, 0xffb30b90, "vclt.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
497 {FPU_NEON_EXT_V1, 0xf3b10300, 0xffb30b90, "vabs.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
498 {FPU_NEON_EXT_V1, 0xf3b10380, 0xffb30b90, "vneg.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
499 {FPU_NEON_EXT_V1, 0xf3b00200, 0xffb30f10, "vpaddl.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
500 {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
501 {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
503 /* Three registers of the same length */
504 {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand\t%12-15,22R, %16-19,7R, %0-3,5R"},
505 {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic\t%12-15,22R, %16-19,7R, %0-3,5R"},
506 {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr\t%12-15,22R, %16-19,7R, %0-3,5R"},
507 {FPU_NEON_EXT_V1, 0xf2300110, 0xffb00f10, "vorn\t%12-15,22R, %16-19,7R, %0-3,5R"},
508 {FPU_NEON_EXT_V1, 0xf3000110, 0xffb00f10, "veor\t%12-15,22R, %16-19,7R, %0-3,5R"},
509 {FPU_NEON_EXT_V1, 0xf3100110, 0xffb00f10, "vbsl\t%12-15,22R, %16-19,7R, %0-3,5R"},
510 {FPU_NEON_EXT_V1, 0xf3200110, 0xffb00f10, "vbit\t%12-15,22R, %16-19,7R, %0-3,5R"},
511 {FPU_NEON_EXT_V1, 0xf3300110, 0xffb00f10, "vbif\t%12-15,22R, %16-19,7R, %0-3,5R"},
512 {FPU_NEON_EXT_V1, 0xf2000d00, 0xffa00f10, "vadd.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
513 {FPU_NEON_EXT_V1, 0xf2000d10, 0xffa00f10, "vmla.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
514 {FPU_NEON_EXT_V1, 0xf2000e00, 0xffa00f10, "vceq.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
515 {FPU_NEON_EXT_V1, 0xf2000f00, 0xffa00f10, "vmax.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
516 {FPU_NEON_EXT_V1, 0xf2000f10, 0xffa00f10, "vrecps.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
517 {FPU_NEON_EXT_V1, 0xf2200d00, 0xffa00f10, "vsub.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
518 {FPU_NEON_EXT_V1, 0xf2200d10, 0xffa00f10, "vmls.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
519 {FPU_NEON_EXT_V1, 0xf2200f00, 0xffa00f10, "vmin.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
520 {FPU_NEON_EXT_V1, 0xf2200f10, 0xffa00f10, "vrsqrts.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
521 {FPU_NEON_EXT_V1, 0xf3000d00, 0xffa00f10, "vpadd.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
522 {FPU_NEON_EXT_V1, 0xf3000d10, 0xffa00f10, "vmul.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
523 {FPU_NEON_EXT_V1, 0xf3000e00, 0xffa00f10, "vcge.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
524 {FPU_NEON_EXT_V1, 0xf3000e10, 0xffa00f10, "vacge.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
525 {FPU_NEON_EXT_V1, 0xf3000f00, 0xffa00f10, "vpmax.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
526 {FPU_NEON_EXT_V1, 0xf3200d00, 0xffa00f10, "vabd.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
527 {FPU_NEON_EXT_V1, 0xf3200e00, 0xffa00f10, "vcgt.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
528 {FPU_NEON_EXT_V1, 0xf3200e10, 0xffa00f10, "vacgt.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
529 {FPU_NEON_EXT_V1, 0xf3200f00, 0xffa00f10, "vpmin.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
530 {FPU_NEON_EXT_V1, 0xf2000800, 0xff800f10, "vadd.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
531 {FPU_NEON_EXT_V1, 0xf2000810, 0xff800f10, "vtst.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
532 {FPU_NEON_EXT_V1, 0xf2000900, 0xff800f10, "vmla.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
533 {FPU_NEON_EXT_V1, 0xf2000b00, 0xff800f10, "vqdmulh.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
534 {FPU_NEON_EXT_V1, 0xf2000b10, 0xff800f10, "vpadd.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
535 {FPU_NEON_EXT_V1, 0xf3000800, 0xff800f10, "vsub.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
536 {FPU_NEON_EXT_V1, 0xf3000810, 0xff800f10, "vceq.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
537 {FPU_NEON_EXT_V1, 0xf3000900, 0xff800f10, "vmls.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
538 {FPU_NEON_EXT_V1, 0xf3000b00, 0xff800f10, "vqrdmulh.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
539 {FPU_NEON_EXT_V1, 0xf2000000, 0xfe800f10, "vhadd.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
540 {FPU_NEON_EXT_V1, 0xf2000010, 0xfe800f10, "vqadd.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
541 {FPU_NEON_EXT_V1, 0xf2000100, 0xfe800f10, "vrhadd.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
542 {FPU_NEON_EXT_V1, 0xf2000200, 0xfe800f10, "vhsub.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
543 {FPU_NEON_EXT_V1, 0xf2000210, 0xfe800f10, "vqsub.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
544 {FPU_NEON_EXT_V1, 0xf2000300, 0xfe800f10, "vcgt.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
545 {FPU_NEON_EXT_V1, 0xf2000310, 0xfe800f10, "vcge.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
546 {FPU_NEON_EXT_V1, 0xf2000400, 0xfe800f10, "vshl.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
547 {FPU_NEON_EXT_V1, 0xf2000410, 0xfe800f10, "vqshl.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
548 {FPU_NEON_EXT_V1, 0xf2000500, 0xfe800f10, "vrshl.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
549 {FPU_NEON_EXT_V1, 0xf2000510, 0xfe800f10, "vqrshl.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
550 {FPU_NEON_EXT_V1, 0xf2000600, 0xfe800f10, "vmax.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
551 {FPU_NEON_EXT_V1, 0xf2000610, 0xfe800f10, "vmin.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
552 {FPU_NEON_EXT_V1, 0xf2000700, 0xfe800f10, "vabd.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
553 {FPU_NEON_EXT_V1, 0xf2000710, 0xfe800f10, "vaba.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
554 {FPU_NEON_EXT_V1, 0xf2000910, 0xfe800f10, "vmul.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
555 {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
556 {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
558 /* One register and an immediate value */
559 {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov.i8\t%12-15,22R, %E"},
560 {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov.i64\t%12-15,22R, %E"},
561 {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov.f32\t%12-15,22R, %E"},
562 {FPU_NEON_EXT_V1, 0xf2800810, 0xfeb80db0, "vmov.i16\t%12-15,22R, %E"},
563 {FPU_NEON_EXT_V1, 0xf2800830, 0xfeb80db0, "vmvn.i16\t%12-15,22R, %E"},
564 {FPU_NEON_EXT_V1, 0xf2800910, 0xfeb80db0, "vorr.i16\t%12-15,22R, %E"},
565 {FPU_NEON_EXT_V1, 0xf2800930, 0xfeb80db0, "vbic.i16\t%12-15,22R, %E"},
566 {FPU_NEON_EXT_V1, 0xf2800c10, 0xfeb80eb0, "vmov.i32\t%12-15,22R, %E"},
567 {FPU_NEON_EXT_V1, 0xf2800c30, 0xfeb80eb0, "vmvn.i32\t%12-15,22R, %E"},
568 {FPU_NEON_EXT_V1, 0xf2800110, 0xfeb809b0, "vorr.i32\t%12-15,22R, %E"},
569 {FPU_NEON_EXT_V1, 0xf2800130, 0xfeb809b0, "vbic.i32\t%12-15,22R, %E"},
570 {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov.i32\t%12-15,22R, %E"},
571 {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn.i32\t%12-15,22R, %E"},
573 /* Two registers and a shift amount */
574 {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
575 {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
576 {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
577 {FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
578 {FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
579 {FPU_NEON_EXT_V1, 0xf2880950, 0xfeb80fd0, "vqrshrn.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
580 {FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll.%24?us8\t%12-15,22D, %0-3,5Q, #%16-18d"},
581 {FPU_NEON_EXT_V1, 0xf2900810, 0xffb00fd0, "vshrn.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
582 {FPU_NEON_EXT_V1, 0xf2900850, 0xffb00fd0, "vrshrn.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
583 {FPU_NEON_EXT_V1, 0xf2880510, 0xffb80f90, "vshl.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
584 {FPU_NEON_EXT_V1, 0xf3880410, 0xffb80f90, "vsri.8\t%12-15,22R, %0-3,5R, #%16-18e"},
585 {FPU_NEON_EXT_V1, 0xf3880510, 0xffb80f90, "vsli.8\t%12-15,22R, %0-3,5R, #%16-18d"},
586 {FPU_NEON_EXT_V1, 0xf3880610, 0xffb80f90, "vqshlu.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
587 {FPU_NEON_EXT_V1, 0xf2900810, 0xfeb00fd0, "vqshrun.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
588 {FPU_NEON_EXT_V1, 0xf2900850, 0xfeb00fd0, "vqrshrun.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
589 {FPU_NEON_EXT_V1, 0xf2900910, 0xfeb00fd0, "vqshrn.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
590 {FPU_NEON_EXT_V1, 0xf2900950, 0xfeb00fd0, "vqrshrn.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
591 {FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll.%24?us16\t%12-15,22D, %0-3,5Q, #%16-19d"},
592 {FPU_NEON_EXT_V1, 0xf2880010, 0xfeb80f90, "vshr.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
593 {FPU_NEON_EXT_V1, 0xf2880110, 0xfeb80f90, "vsra.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
594 {FPU_NEON_EXT_V1, 0xf2880210, 0xfeb80f90, "vrshr.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
595 {FPU_NEON_EXT_V1, 0xf2880310, 0xfeb80f90, "vrsra.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
596 {FPU_NEON_EXT_V1, 0xf2880710, 0xfeb80f90, "vqshl.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
597 {FPU_NEON_EXT_V1, 0xf2a00810, 0xffa00fd0, "vshrn.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
598 {FPU_NEON_EXT_V1, 0xf2a00850, 0xffa00fd0, "vrshrn.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
599 {FPU_NEON_EXT_V1, 0xf2900510, 0xffb00f90, "vshl.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
600 {FPU_NEON_EXT_V1, 0xf3900410, 0xffb00f90, "vsri.16\t%12-15,22R, %0-3,5R, #%16-19e"},
601 {FPU_NEON_EXT_V1, 0xf3900510, 0xffb00f90, "vsli.16\t%12-15,22R, %0-3,5R, #%16-19d"},
602 {FPU_NEON_EXT_V1, 0xf3900610, 0xffb00f90, "vqshlu.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
603 {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll.%24?us32\t%12-15,22D, %0-3,5Q, #%16-20d"},
604 {FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
605 {FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
606 {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
607 {FPU_NEON_EXT_V1, 0xf2900310, 0xfeb00f90, "vrsra.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
608 {FPU_NEON_EXT_V1, 0xf2900710, 0xfeb00f90, "vqshl.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
609 {FPU_NEON_EXT_V1, 0xf2800810, 0xfec00fd0, "vqshrun.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
610 {FPU_NEON_EXT_V1, 0xf2800850, 0xfec00fd0, "vqrshrun.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
611 {FPU_NEON_EXT_V1, 0xf2800910, 0xfec00fd0, "vqshrn.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
612 {FPU_NEON_EXT_V1, 0xf2800950, 0xfec00fd0, "vqrshrn.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
613 {FPU_NEON_EXT_V1, 0xf2a00510, 0xffa00f90, "vshl.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
614 {FPU_NEON_EXT_V1, 0xf3a00410, 0xffa00f90, "vsri.32\t%12-15,22R, %0-3,5R, #%16-20e"},
615 {FPU_NEON_EXT_V1, 0xf3a00510, 0xffa00f90, "vsli.32\t%12-15,22R, %0-3,5R, #%16-20d"},
616 {FPU_NEON_EXT_V1, 0xf3a00610, 0xffa00f90, "vqshlu.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
617 {FPU_NEON_EXT_V1, 0xf2a00010, 0xfea00f90, "vshr.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
618 {FPU_NEON_EXT_V1, 0xf2a00110, 0xfea00f90, "vsra.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
619 {FPU_NEON_EXT_V1, 0xf2a00210, 0xfea00f90, "vrshr.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
620 {FPU_NEON_EXT_V1, 0xf2a00310, 0xfea00f90, "vrsra.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
621 {FPU_NEON_EXT_V1, 0xf2a00710, 0xfea00f90, "vqshl.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
622 {FPU_NEON_EXT_V1, 0xf2800590, 0xff800f90, "vshl.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
623 {FPU_NEON_EXT_V1, 0xf3800490, 0xff800f90, "vsri.64\t%12-15,22R, %0-3,5R, #%16-21e"},
624 {FPU_NEON_EXT_V1, 0xf3800590, 0xff800f90, "vsli.64\t%12-15,22R, %0-3,5R, #%16-21d"},
625 {FPU_NEON_EXT_V1, 0xf3800690, 0xff800f90, "vqshlu.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
626 {FPU_NEON_EXT_V1, 0xf2800090, 0xfe800f90, "vshr.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
627 {FPU_NEON_EXT_V1, 0xf2800190, 0xfe800f90, "vsra.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
628 {FPU_NEON_EXT_V1, 0xf2800290, 0xfe800f90, "vrshr.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
629 {FPU_NEON_EXT_V1, 0xf2800390, 0xfe800f90, "vrsra.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
630 {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
631 {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
633 /* Three registers of different lengths */
634 {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
635 {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
636 {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
637 {FPU_NEON_EXT_V1, 0xf2800900, 0xff800f50, "vqdmlal.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
638 {FPU_NEON_EXT_V1, 0xf2800b00, 0xff800f50, "vqdmlsl.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
639 {FPU_NEON_EXT_V1, 0xf2800d00, 0xff800f50, "vqdmull.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
640 {FPU_NEON_EXT_V1, 0xf3800400, 0xff800f50, "vraddhn.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
641 {FPU_NEON_EXT_V1, 0xf3800600, 0xff800f50, "vrsubhn.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
642 {FPU_NEON_EXT_V1, 0xf2800000, 0xfe800f50, "vaddl.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
643 {FPU_NEON_EXT_V1, 0xf2800100, 0xfe800f50, "vaddw.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
644 {FPU_NEON_EXT_V1, 0xf2800200, 0xfe800f50, "vsubl.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
645 {FPU_NEON_EXT_V1, 0xf2800300, 0xfe800f50, "vsubw.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
646 {FPU_NEON_EXT_V1, 0xf2800500, 0xfe800f50, "vabal.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
647 {FPU_NEON_EXT_V1, 0xf2800700, 0xfe800f50, "vabdl.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
648 {FPU_NEON_EXT_V1, 0xf2800800, 0xfe800f50, "vmlal.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
649 {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
650 {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
652 /* Two registers and a scalar */
653 {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
654 {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
655 {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
656 {FPU_NEON_EXT_V1, 0xf2800440, 0xff800f50, "vmls.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
657 {FPU_NEON_EXT_V1, 0xf2800540, 0xff800f50, "vmls.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
658 {FPU_NEON_EXT_V1, 0xf2800740, 0xff800f50, "vqdmlsl.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
659 {FPU_NEON_EXT_V1, 0xf2800840, 0xff800f50, "vmul.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
660 {FPU_NEON_EXT_V1, 0xf2800940, 0xff800f50, "vmul.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
661 {FPU_NEON_EXT_V1, 0xf2800b40, 0xff800f50, "vqdmull.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
662 {FPU_NEON_EXT_V1, 0xf2800c40, 0xff800f50, "vqdmulh.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
663 {FPU_NEON_EXT_V1, 0xf2800d40, 0xff800f50, "vqrdmulh.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
664 {FPU_NEON_EXT_V1, 0xf3800040, 0xff800f50, "vmla.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
665 {FPU_NEON_EXT_V1, 0xf3800140, 0xff800f50, "vmla.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
666 {FPU_NEON_EXT_V1, 0xf3800440, 0xff800f50, "vmls.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
667 {FPU_NEON_EXT_V1, 0xf3800540, 0xff800f50, "vmls.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
668 {FPU_NEON_EXT_V1, 0xf3800840, 0xff800f50, "vmul.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
669 {FPU_NEON_EXT_V1, 0xf3800940, 0xff800f50, "vmul.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
670 {FPU_NEON_EXT_V1, 0xf3800c40, 0xff800f50, "vqdmulh.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
671 {FPU_NEON_EXT_V1, 0xf3800d40, 0xff800f50, "vqrdmulh.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
672 {FPU_NEON_EXT_V1, 0xf2800240, 0xfe800f50, "vmlal.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
673 {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
674 {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
676 /* Element and structure load/store */
677 {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4.32\t%C"},
678 {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1.%6-7S2\t%C"},
679 {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2.%6-7S2\t%C"},
680 {FPU_NEON_EXT_V1, 0xf4a00e00, 0xffb00f00, "vld3.%6-7S2\t%C"},
681 {FPU_NEON_EXT_V1, 0xf4a00f00, 0xffb00f00, "vld4.%6-7S2\t%C"},
682 {FPU_NEON_EXT_V1, 0xf4000200, 0xff900f00, "v%21?ls%21?dt1.%6-7S3\t%A"},
683 {FPU_NEON_EXT_V1, 0xf4000300, 0xff900f00, "v%21?ls%21?dt2.%6-7S2\t%A"},
684 {FPU_NEON_EXT_V1, 0xf4000400, 0xff900f00, "v%21?ls%21?dt3.%6-7S2\t%A"},
685 {FPU_NEON_EXT_V1, 0xf4000500, 0xff900f00, "v%21?ls%21?dt3.%6-7S2\t%A"},
686 {FPU_NEON_EXT_V1, 0xf4000600, 0xff900f00, "v%21?ls%21?dt1.%6-7S3\t%A"},
687 {FPU_NEON_EXT_V1, 0xf4000700, 0xff900f00, "v%21?ls%21?dt1.%6-7S3\t%A"},
688 {FPU_NEON_EXT_V1, 0xf4000800, 0xff900f00, "v%21?ls%21?dt2.%6-7S2\t%A"},
689 {FPU_NEON_EXT_V1, 0xf4000900, 0xff900f00, "v%21?ls%21?dt2.%6-7S2\t%A"},
690 {FPU_NEON_EXT_V1, 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1.%6-7S3\t%A"},
691 {FPU_NEON_EXT_V1, 0xf4000000, 0xff900e00, "v%21?ls%21?dt4.%6-7S2\t%A"},
692 {FPU_NEON_EXT_V1, 0xf4800000, 0xff900300, "v%21?ls%21?dt1.%10-11S2\t%B"},
693 {FPU_NEON_EXT_V1, 0xf4800100, 0xff900300, "v%21?ls%21?dt2.%10-11S2\t%B"},
694 {FPU_NEON_EXT_V1, 0xf4800200, 0xff900300, "v%21?ls%21?dt3.%10-11S2\t%B"},
695 {FPU_NEON_EXT_V1, 0xf4800300, 0xff900300, "v%21?ls%21?dt4.%10-11S2\t%B"},
700 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
701 ordered: they must be searched linearly from the top to obtain a correct
704 /* print_insn_arm recognizes the following format control codes:
708 %a print address for ldr/str instruction
709 %s print address for ldr/str halfword/signextend instruction
710 %b print branch destination
711 %c print condition code (always bits 28-31)
712 %m print register mask for ldm/stm instruction
713 %o print operand2 (immediate or register + shift)
714 %p print 'p' iff bits 12-15 are 15
715 %t print 't' iff bit 21 set and bit 24 clear
716 %B print arm BLX(1) destination
717 %C print the PSR sub type.
718 %U print barrier type.
719 %P print address for pli instruction.
721 %<bitfield>r print as an ARM register
722 %<bitfield>d print the bitfield in decimal
723 %<bitfield>W print the bitfield plus one in decimal
724 %<bitfield>x print the bitfield in hex
725 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
727 %<bitfield>'c print specified char iff bitfield is all ones
728 %<bitfield>`c print specified char iff bitfield is all zeroes
729 %<bitfield>?ab... select from array of values in big endian order
731 %e print arm SMI operand (bits 0..7,8..19).
732 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
733 %V print the 16-bit immediate field of a MOVT or MOVW instruction. */
735 static const struct opcode32 arm_opcodes[] =
737 /* ARM instructions. */
738 {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"},
739 {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
740 {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"},
741 {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"},
742 {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"},
743 {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
744 {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
746 /* V7 instructions. */
747 {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"},
748 {ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
749 {ARM_EXT_V7, 0xf57ff050, 0xfffffff0, "dmb\t%U"},
750 {ARM_EXT_V7, 0xf57ff040, 0xfffffff0, "dsb\t%U"},
751 {ARM_EXT_V7, 0xf57ff060, 0xfffffff0, "isb\t%U"},
753 /* ARM V6T2 instructions. */
754 {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15r, %E"},
755 {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15r, %0-3r, %E"},
756 {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
757 {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "str%cht\t%12-15r, %s"},
758 {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%c%6's%5?hbt\t%12-15r, %s"},
759 {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15r, %V"},
760 {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15r, %V"},
761 {ARM_EXT_V6T2, 0x03ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"},
762 {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
764 /* ARM V6Z instructions. */
765 {ARM_EXT_V6Z, 0x01600070, 0x0ff000f0, "smc%c\t%e"},
767 /* ARM V6K instructions. */
768 {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"},
769 {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15r, [%16-19r]"},
770 {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19r]"},
771 {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15r, [%16-19r]"},
772 {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15r, %0-3r, [%16-19r]"},
773 {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15r, %0-3r, [%16-19r]"},
774 {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15r, %0-3r, [%16-19r]"},
776 /* ARM V6K NOP hints. */
777 {ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"},
778 {ARM_EXT_V6K, 0x0320f002, 0x0fffffff, "wfe%c"},
779 {ARM_EXT_V6K, 0x0320f003, 0x0fffffff, "wfi%c"},
780 {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"},
781 {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
783 /* ARM V6 instructions. */
784 {ARM_EXT_V6, 0xf1080000, 0xfffdfe3f, "cpsie\t%8'a%7'i%6'f"},
785 {ARM_EXT_V6, 0xf1080000, 0xfffdfe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
786 {ARM_EXT_V6, 0xf10C0000, 0xfffdfe3f, "cpsid\t%8'a%7'i%6'f"},
787 {ARM_EXT_V6, 0xf10C0000, 0xfffdfe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
788 {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
789 {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15r, %16-19r, %0-3r"},
790 {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15r, %16-19r, %0-3r, LSL #%7-11d"},
791 {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #32"},
792 {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #%7-11d"},
793 {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19r]"},
794 {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15r, %16-19r, %0-3r"},
795 {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15r, %16-19r, %0-3r"},
796 {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qaddsubx%c\t%12-15r, %16-19r, %0-3r"},
797 {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15r, %16-19r, %0-3r"},
798 {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15r, %16-19r, %0-3r"},
799 {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsubaddx%c\t%12-15r, %16-19r, %0-3r"},
800 {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15r, %16-19r, %0-3r"},
801 {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15r, %16-19r, %0-3r"},
802 {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "saddaddx%c\t%12-15r, %16-19r, %0-3r"},
803 {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15r, %16-19r, %0-3r"},
804 {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15r, %16-19r, %0-3r"},
805 {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shaddsubx%c\t%12-15r, %16-19r, %0-3r"},
806 {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15r, %16-19r, %0-3r"},
807 {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15r, %16-19r, %0-3r"},
808 {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsubaddx%c\t%12-15r, %16-19r, %0-3r"},
809 {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15r, %16-19r, %0-3r"},
810 {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15r, %16-19r, %0-3r"},
811 {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssubaddx%c\t%12-15r, %16-19r, %0-3r"},
812 {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15r, %16-19r, %0-3r"},
813 {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15r, %16-19r, %0-3r"},
814 {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uaddsubx%c\t%12-15r, %16-19r, %0-3r"},
815 {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15r, %16-19r, %0-3r"},
816 {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15r, %16-19r, %0-3r"},
817 {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhaddsubx%c\t%12-15r, %16-19r, %0-3r"},
818 {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15r, %16-19r, %0-3r"},
819 {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15r, %16-19r, %0-3r"},
820 {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsubaddx%c\t%12-15r, %16-19r, %0-3r"},
821 {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15r, %16-19r, %0-3r"},
822 {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15r, %16-19r, %0-3r"},
823 {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqaddsubx%c\t%12-15r, %16-19r, %0-3r"},
824 {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15r, %16-19r, %0-3r"},
825 {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15r, %16-19r, %0-3r"},
826 {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsubaddx%c\t%12-15r, %16-19r, %0-3r"},
827 {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15r, %16-19r, %0-3r"},
828 {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15r, %16-19r, %0-3r"},
829 {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usubaddx%c\t%12-15r, %16-19r, %0-3r"},
830 {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t\%12-15r, %0-3r"},
831 {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t\%12-15r, %0-3r"},
832 {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t\%12-15r, %0-3r"},
833 {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t\%16-19r%21'!"},
834 {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c %12-15r,%0-3r"},
835 {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #8"},
836 {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #16"},
837 {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #24"},
838 {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r"},
839 {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #8"},
840 {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #16"},
841 {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #24"},
842 {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r"},
843 {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #8"},
844 {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #16"},
845 {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #24"},
846 {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c %12-15r,%0-3r"},
847 {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #8"},
848 {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #16"},
849 {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #24"},
850 {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r"},
851 {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #8"},
852 {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #16"},
853 {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #24"},
854 {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r"},
855 {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #8"},
856 {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #16"},
857 {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #24"},
858 {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r"},
859 {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
860 {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
861 {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
862 {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r"},
863 {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
864 {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
865 {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
866 {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r"},
867 {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
868 {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
869 {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
870 {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r"},
871 {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
872 {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
873 {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
874 {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r"},
875 {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
876 {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
877 {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
878 {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r"},
879 {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
880 {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
881 {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
882 {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"},
883 {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
884 {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19r, %0-3r, %8-11r"},
885 {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19r, %0-3r, %8-11r"},
886 {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
887 {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
888 {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
889 {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
890 {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19r, %0-3r, %8-11r"},
891 {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
892 {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
893 {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t#%0-4d%21'!"},
894 {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15r, #%16-20W, %0-3r"},
895 {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, LSL #%7-11d"},
896 {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, ASR #%7-11d"},
897 {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
898 {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15r, %0-3r, [%16-19r]"},
899 {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
900 {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19r, %0-3r, %8-11r"},
901 {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
902 {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15r, #%16-20d, %0-3r"},
903 {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, LSL #%7-11d"},
904 {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, ASR #%7-11d"},
905 {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15r, #%16-19d, %0-3r"},
907 /* V5J instruction. */
908 {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3r"},
910 /* V5 Instructions. */
911 {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
912 {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"},
913 {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"},
914 {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"},
916 /* V5E "El Segundo" Instructions. */
917 {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldr%cd\t%12-15r, %s"},
918 {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "str%cd\t%12-15r, %s"},
919 {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"},
920 {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
921 {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
922 {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
923 {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
925 {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
926 {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
928 {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
929 {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
930 {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
931 {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
933 {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19r, %0-3r, %8-11r"},
934 {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19r, %0-3r, %8-11r"},
935 {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19r, %0-3r, %8-11r"},
936 {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19r, %0-3r, %8-11r"},
938 {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19r, %0-3r, %8-11r"},
939 {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19r, %0-3r, %8-11r"},
941 {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15r, %0-3r, %16-19r"},
942 {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"},
943 {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15r, %0-3r, %16-19r"},
944 {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"},
946 /* ARM Instructions. */
947 {ARM_EXT_V1, 0x00000090, 0x0e100090, "str%c%6's%5?hb\t%12-15r, %s"},
948 {ARM_EXT_V1, 0x00100090, 0x0e100090, "ldr%c%6's%5?hb\t%12-15r, %s"},
949 {ARM_EXT_V1, 0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"},
950 {ARM_EXT_V1, 0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"},
951 {ARM_EXT_V1, 0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"},
952 {ARM_EXT_V1, 0x00600000, 0x0de00000, "rsb%c%20's\t%12-15r, %16-19r, %o"},
953 {ARM_EXT_V1, 0x00800000, 0x0de00000, "add%c%20's\t%12-15r, %16-19r, %o"},
954 {ARM_EXT_V1, 0x00a00000, 0x0de00000, "adc%c%20's\t%12-15r, %16-19r, %o"},
955 {ARM_EXT_V1, 0x00c00000, 0x0de00000, "sbc%c%20's\t%12-15r, %16-19r, %o"},
956 {ARM_EXT_V1, 0x00e00000, 0x0de00000, "rsc%c%20's\t%12-15r, %16-19r, %o"},
957 {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"},
958 {ARM_EXT_V3, 0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"},
959 {ARM_EXT_V1, 0x01000000, 0x0de00000, "tst%c%p\t%16-19r, %o"},
960 {ARM_EXT_V1, 0x01200000, 0x0de00000, "teq%c%p\t%16-19r, %o"},
961 {ARM_EXT_V1, 0x01400000, 0x0de00000, "cmp%c%p\t%16-19r, %o"},
962 {ARM_EXT_V1, 0x01600000, 0x0de00000, "cmn%c%p\t%16-19r, %o"},
963 {ARM_EXT_V1, 0x01800000, 0x0de00000, "orr%c%20's\t%12-15r, %16-19r, %o"},
964 {ARM_EXT_V1, 0x01a00000, 0x0de00000, "mov%c%20's\t%12-15r, %o"},
965 {ARM_EXT_V1, 0x01c00000, 0x0de00000, "bic%c%20's\t%12-15r, %16-19r, %o"},
966 {ARM_EXT_V1, 0x01e00000, 0x0de00000, "mvn%c%20's\t%12-15r, %o"},
967 {ARM_EXT_V1, 0x04000000, 0x0e100000, "str%c%22'b%t\t%12-15r, %a"},
968 {ARM_EXT_V1, 0x06000000, 0x0e100ff0, "str%c%22'b%t\t%12-15r, %a"},
969 {ARM_EXT_V1, 0x04000000, 0x0c100010, "str%c%22'b%t\t%12-15r, %a"},
970 {ARM_EXT_V1, 0x06000010, 0x0e000010, "undefined"},
971 {ARM_EXT_V1, 0x04100000, 0x0c100000, "ldr%c%22'b%t\t%12-15r, %a"},
972 {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},
973 {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},
974 {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
975 {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
978 {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined instruction %0-31x"},
979 {0, 0x00000000, 0x00000000, 0}
982 /* print_insn_thumb16 recognizes the following format control codes:
984 %S print Thumb register (bits 3..5 as high number if bit 6 set)
985 %D print Thumb register (bits 0..2 as high number if bit 7 set)
986 %<bitfield>I print bitfield as a signed decimal
987 (top bit of range being the sign bit)
988 %N print Thumb register mask (with LR)
989 %O print Thumb register mask (with PC)
990 %M print Thumb register mask
991 %b print CZB's 6-bit unsigned branch destination
992 %s print Thumb right-shift immediate (6..10; 0 == 32).
993 %<bitfield>r print bitfield as an ARM register
994 %<bitfield>d print bitfield as a decimal
995 %<bitfield>H print (bitfield * 2) as a decimal
996 %<bitfield>W print (bitfield * 4) as a decimal
997 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
998 %<bitfield>B print Thumb branch destination (signed displacement)
999 %<bitfield>c print bitfield as a condition code
1000 %<bitnum>'c print specified char iff bit is one
1001 %<bitnum>?ab print a if bit is one else print b. */
1003 static const struct opcode16 thumb_opcodes[] =
1005 /* Thumb instructions. */
1007 /* ARM V6K no-argument instructions. */
1008 {ARM_EXT_V6K, 0xbf00, 0xffff, "nop"},
1009 {ARM_EXT_V6K, 0xbf10, 0xffff, "yield"},
1010 {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe"},
1011 {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi"},
1012 {ARM_EXT_V6K, 0xbf40, 0xffff, "sev"},
1013 {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop\t{%4-7d}"},
1015 /* ARM V6T2 instructions. */
1016 {ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b"},
1017 {ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b"},
1018 {ARM_EXT_V6T2, 0xbf08, 0xff0f, "it\t%4-7c"},
1019 {ARM_EXT_V6T2, 0xbf14, 0xff17, "it%3?te\t%4-7c"},
1020 {ARM_EXT_V6T2, 0xbf04, 0xff17, "it%3?et\t%4-7c"},
1021 {ARM_EXT_V6T2, 0xbf12, 0xff13, "it%3?te%2?te\t%4-7c"},
1022 {ARM_EXT_V6T2, 0xbf02, 0xff13, "it%3?et%2?et\t%4-7c"},
1023 {ARM_EXT_V6T2, 0xbf11, 0xff11, "it%3?te%2?te%1?te\t%4-7c"},
1024 {ARM_EXT_V6T2, 0xbf01, 0xff11, "it%3?et%2?et%1?et\t%4-7c"},
1027 {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f"},
1028 {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f"},
1029 {ARM_EXT_V6, 0x4600, 0xffc0, "mov\t%0-2r, %3-5r"},
1030 {ARM_EXT_V6, 0xba00, 0xffc0, "rev\t%0-2r, %3-5r"},
1031 {ARM_EXT_V6, 0xba40, 0xffc0, "rev16\t%0-2r, %3-5r"},
1032 {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh\t%0-2r, %3-5r"},
1033 {ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble"},
1034 {ARM_EXT_V6, 0xb200, 0xffc0, "sxth\t%0-2r, %3-5r"},
1035 {ARM_EXT_V6, 0xb240, 0xffc0, "sxtb\t%0-2r, %3-5r"},
1036 {ARM_EXT_V6, 0xb280, 0xffc0, "uxth\t%0-2r, %3-5r"},
1037 {ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb\t%0-2r, %3-5r"},
1039 /* ARM V5 ISA extends Thumb. */
1040 {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"},
1041 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
1042 {ARM_EXT_V5T, 0x4780, 0xff87, "blx\t%3-6r"}, /* note: 4 bit register number. */
1043 /* ARM V4T ISA (Thumb v1). */
1044 {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop\t\t\t(mov r8, r8)"},
1046 {ARM_EXT_V4T, 0x4000, 0xFFC0, "ands\t%0-2r, %3-5r"},
1047 {ARM_EXT_V4T, 0x4040, 0xFFC0, "eors\t%0-2r, %3-5r"},
1048 {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsls\t%0-2r, %3-5r"},
1049 {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsrs\t%0-2r, %3-5r"},
1050 {ARM_EXT_V4T, 0x4100, 0xFFC0, "asrs\t%0-2r, %3-5r"},
1051 {ARM_EXT_V4T, 0x4140, 0xFFC0, "adcs\t%0-2r, %3-5r"},
1052 {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbcs\t%0-2r, %3-5r"},
1053 {ARM_EXT_V4T, 0x41C0, 0xFFC0, "rors\t%0-2r, %3-5r"},
1054 {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst\t%0-2r, %3-5r"},
1055 {ARM_EXT_V4T, 0x4240, 0xFFC0, "negs\t%0-2r, %3-5r"},
1056 {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp\t%0-2r, %3-5r"},
1057 {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn\t%0-2r, %3-5r"},
1058 {ARM_EXT_V4T, 0x4300, 0xFFC0, "orrs\t%0-2r, %3-5r"},
1059 {ARM_EXT_V4T, 0x4340, 0xFFC0, "muls\t%0-2r, %3-5r"},
1060 {ARM_EXT_V4T, 0x4380, 0xFFC0, "bics\t%0-2r, %3-5r"},
1061 {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvns\t%0-2r, %3-5r"},
1063 {ARM_EXT_V4T, 0xB000, 0xFF80, "add\tsp, #%0-6W"},
1064 {ARM_EXT_V4T, 0xB080, 0xFF80, "sub\tsp, #%0-6W"},
1066 {ARM_EXT_V4T, 0x4700, 0xFF80, "bx\t%S"},
1067 {ARM_EXT_V4T, 0x4400, 0xFF00, "add\t%D, %S"},
1068 {ARM_EXT_V4T, 0x4500, 0xFF00, "cmp\t%D, %S"},
1069 {ARM_EXT_V4T, 0x4600, 0xFF00, "mov\t%D, %S"},
1071 {ARM_EXT_V4T, 0xB400, 0xFE00, "push\t%N"},
1072 {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop\t%O"},
1074 {ARM_EXT_V4T, 0x1800, 0xFE00, "adds\t%0-2r, %3-5r, %6-8r"},
1075 {ARM_EXT_V4T, 0x1A00, 0xFE00, "subs\t%0-2r, %3-5r, %6-8r"},
1076 {ARM_EXT_V4T, 0x1C00, 0xFE00, "adds\t%0-2r, %3-5r, #%6-8d"},
1077 {ARM_EXT_V4T, 0x1E00, 0xFE00, "subs\t%0-2r, %3-5r, #%6-8d"},
1079 {ARM_EXT_V4T, 0x5200, 0xFE00, "strh\t%0-2r, [%3-5r, %6-8r]"},
1080 {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh\t%0-2r, [%3-5r, %6-8r]"},
1081 {ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb\t%0-2r, [%3-5r, %6-8r]"},
1083 {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b\t%0-2r, [%3-5r, %6-8r]"},
1084 {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b\t%0-2r, [%3-5r, %6-8r]"},
1086 {ARM_EXT_V4T, 0x0000, 0xF800, "lsls\t%0-2r, %3-5r, #%6-10d"},
1087 {ARM_EXT_V4T, 0x0800, 0xF800, "lsrs\t%0-2r, %3-5r, %s"},
1088 {ARM_EXT_V4T, 0x1000, 0xF800, "asrs\t%0-2r, %3-5r, %s"},
1090 {ARM_EXT_V4T, 0x2000, 0xF800, "movs\t%8-10r, #%0-7d"},
1091 {ARM_EXT_V4T, 0x2800, 0xF800, "cmp\t%8-10r, #%0-7d"},
1092 {ARM_EXT_V4T, 0x3000, 0xF800, "adds\t%8-10r, #%0-7d"},
1093 {ARM_EXT_V4T, 0x3800, 0xF800, "subs\t%8-10r, #%0-7d"},
1095 {ARM_EXT_V4T, 0x4800, 0xF800, "ldr\t%8-10r, [pc, #%0-7W]\t(%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
1097 {ARM_EXT_V4T, 0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"},
1098 {ARM_EXT_V4T, 0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"},
1099 {ARM_EXT_V4T, 0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"},
1100 {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"},
1102 {ARM_EXT_V4T, 0x8000, 0xF800, "strh\t%0-2r, [%3-5r, #%6-10H]"},
1103 {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh\t%0-2r, [%3-5r, #%6-10H]"},
1105 {ARM_EXT_V4T, 0x9000, 0xF800, "str\t%8-10r, [sp, #%0-7W]"},
1106 {ARM_EXT_V4T, 0x9800, 0xF800, "ldr\t%8-10r, [sp, #%0-7W]"},
1108 {ARM_EXT_V4T, 0xA000, 0xF800, "add\t%8-10r, pc, #%0-7W\t(adr %8-10r,%0-7a)"},
1109 {ARM_EXT_V4T, 0xA800, 0xF800, "add\t%8-10r, sp, #%0-7W"},
1111 {ARM_EXT_V4T, 0xC000, 0xF800, "stmia\t%8-10r!, %M"},
1112 {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia\t%8-10r!, %M"},
1114 {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc\t%0-7d"},
1116 {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B"},
1118 {ARM_EXT_V4T, 0xE000, 0xF800, "b.n\t%0-10B"},
1120 /* The E800 .. FFFF range is unconditionally redirected to the
1121 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
1122 are processed via that table. Thus, we can never encounter a
1123 bare "second half of BL/BLX(1)" instruction here. */
1124 {ARM_EXT_V1, 0x0000, 0x0000, "undefined"},
1128 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
1129 We adopt the convention that hw1 is the high 16 bits of .value and
1130 .mask, hw2 the low 16 bits.
1132 print_insn_thumb32 recognizes the following format control codes:
1136 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
1137 %M print a modified 12-bit immediate (same location)
1138 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
1139 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
1140 %S print a possibly-shifted Rm
1142 %a print the address of a plain load/store
1143 %w print the width and signedness of a core load/store
1144 %m print register mask for ldm/stm
1146 %E print the lsb and width fields of a bfc/bfi instruction
1147 %F print the lsb and width fields of a sbfx/ubfx instruction
1148 %b print a conditional branch offset
1149 %B print an unconditional branch offset
1150 %s print the shift field of an SSAT instruction
1151 %R print the rotation field of an SXT instruction
1152 %U print barrier type.
1153 %P print address for pli instruction.
1155 %<bitfield>d print bitfield in decimal
1156 %<bitfield>W print bitfield*4 in decimal
1157 %<bitfield>r print bitfield as an ARM register
1158 %<bitfield>c print bitfield as a condition code
1160 %<bitfield>'c print specified char iff bitfield is all ones
1161 %<bitfield>`c print specified char iff bitfield is all zeroes
1162 %<bitfield>?ab... select from array of values in big endian order
1164 With one exception at the bottom (done because BL and BLX(1) need
1165 to come dead last), this table was machine-sorted first in
1166 decreasing order of number of bits set in the mask, then in
1167 increasing numeric order of mask, then in increasing numeric order
1168 of opcode. This order is not the clearest for a human reader, but
1169 is guaranteed never to catch a special-case bit pattern with a more
1170 general mask, which is important, because this instruction encoding
1171 makes heavy use of special-case bit patterns. */
1172 static const struct opcode32 thumb32_opcodes[] =
1174 /* V7 instructions. */
1175 {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli\t%a"},
1176 {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg\t#%0-3d"},
1177 {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb\t%U"},
1178 {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb\t%U"},
1179 {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb\t%U"},
1180 {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv\t%8-11r, %16-19r, %0-3r"},
1181 {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv\t%8-11r, %16-19r, %0-3r"},
1183 /* Instructions defined in the basic V6T2 set. */
1184 {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop.w"},
1185 {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield.w"},
1186 {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe.w"},
1187 {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi.w"},
1188 {ARM_EXT_V6T2, 0xf3af9004, 0xffffffff, "sev.w"},
1189 {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop.w\t{%0-7d}"},
1191 {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex"},
1192 {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f"},
1193 {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f"},
1194 {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj\t%16-19r"},
1195 {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb\t%16-19r%21'!"},
1196 {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia\t%16-19r%21'!"},
1197 {ARM_EXT_V6T2, 0xf3ef8000, 0xffeff000, "mrs\t%8-11r, %D"},
1198 {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d"},
1199 {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb\t[%16-19r, %0-3r]"},
1200 {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh\t[%16-19r, %0-3r, lsl #1]"},
1201 {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d"},
1202 {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d"},
1203 {ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs\tpc, lr, #%0-7d"},
1204 {ARM_EXT_V6T2, 0xf3808000, 0xffe0f000, "msr\t%C, %16-19r"},
1205 {ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "ldrex\t%12-15r, [%16-19r]"},
1206 {ARM_EXT_V6T2, 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb\t%12-15r, [%16-19r]"},
1207 {ARM_EXT_V6T2, 0xe800c000, 0xffd0ffe0, "srsdb\t#%0-4d%21'!"},
1208 {ARM_EXT_V6T2, 0xe980c000, 0xffd0ffe0, "srsia\t#%0-4d%21'!"},
1209 {ARM_EXT_V6T2, 0xfa0ff080, 0xfffff0c0, "sxth.w\t%8-11r, %0-3r%R"},
1210 {ARM_EXT_V6T2, 0xfa1ff080, 0xfffff0c0, "uxth.w\t%8-11r, %0-3r%R"},
1211 {ARM_EXT_V6T2, 0xfa2ff080, 0xfffff0c0, "sxtb16\t%8-11r, %0-3r%R"},
1212 {ARM_EXT_V6T2, 0xfa3ff080, 0xfffff0c0, "uxtb16\t%8-11r, %0-3r%R"},
1213 {ARM_EXT_V6T2, 0xfa4ff080, 0xfffff0c0, "sxtb.w\t%8-11r, %0-3r%R"},
1214 {ARM_EXT_V6T2, 0xfa5ff080, 0xfffff0c0, "uxtb.w\t%8-11r, %0-3r%R"},
1215 {ARM_EXT_V6T2, 0xe8400000, 0xfff000ff, "strex\t%8-11r, %12-15r, [%16-19r]"},
1216 {ARM_EXT_V6T2, 0xe8d0007f, 0xfff000ff, "ldrexd\t%12-15r, %8-11r, [%16-19r]"},
1217 {ARM_EXT_V6T2, 0xfa80f000, 0xfff0f0f0, "sadd8\t%8-11r, %16-19r, %0-3r"},
1218 {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8\t%8-11r, %16-19r, %0-3r"},
1219 {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8\t%8-11r, %16-19r, %0-3r"},
1220 {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8\t%8-11r, %16-19r, %0-3r"},
1221 {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8\t%8-11r, %16-19r, %0-3r"},
1222 {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8\t%8-11r, %16-19r, %0-3r"},
1223 {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd\t%8-11r, %0-3r, %16-19r"},
1224 {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd\t%8-11r, %0-3r, %16-19r"},
1225 {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub\t%8-11r, %0-3r, %16-19r"},
1226 {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub\t%8-11r, %0-3r, %16-19r"},
1227 {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16\t%8-11r, %16-19r, %0-3r"},
1228 {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16\t%8-11r, %16-19r, %0-3r"},
1229 {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16\t%8-11r, %16-19r, %0-3r"},
1230 {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16\t%8-11r, %16-19r, %0-3r"},
1231 {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16\t%8-11r, %16-19r, %0-3r"},
1232 {ARM_EXT_V6T2, 0xfa90f060, 0xfff0f0f0, "uhadd16\t%8-11r, %16-19r, %0-3r"},
1233 {ARM_EXT_V6T2, 0xfa90f080, 0xfff0f0f0, "rev.w\t%8-11r, %16-19r"},
1234 {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16.w\t%8-11r, %16-19r"},
1235 {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit\t%8-11r, %16-19r"},
1236 {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh.w\t%8-11r, %16-19r"},
1237 {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "saddsubx\t%8-11r, %16-19r, %0-3r"},
1238 {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qaddsubx\t%8-11r, %16-19r, %0-3r"},
1239 {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shaddsubx\t%8-11r, %16-19r, %0-3r"},
1240 {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uaddsubx\t%8-11r, %16-19r, %0-3r"},
1241 {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqaddsubx\t%8-11r, %16-19r, %0-3r"},
1242 {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhaddsubx\t%8-11r, %16-19r, %0-3r"},
1243 {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel\t%8-11r, %16-19r, %0-3r"},
1244 {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz\t%8-11r, %16-19r"},
1245 {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8\t%8-11r, %16-19r, %0-3r"},
1246 {ARM_EXT_V6T2, 0xfac0f010, 0xfff0f0f0, "qsub8\t%8-11r, %16-19r, %0-3r"},
1247 {ARM_EXT_V6T2, 0xfac0f020, 0xfff0f0f0, "shsub8\t%8-11r, %16-19r, %0-3r"},
1248 {ARM_EXT_V6T2, 0xfac0f040, 0xfff0f0f0, "usub8\t%8-11r, %16-19r, %0-3r"},
1249 {ARM_EXT_V6T2, 0xfac0f050, 0xfff0f0f0, "uqsub8\t%8-11r, %16-19r, %0-3r"},
1250 {ARM_EXT_V6T2, 0xfac0f060, 0xfff0f0f0, "uhsub8\t%8-11r, %16-19r, %0-3r"},
1251 {ARM_EXT_V6T2, 0xfad0f000, 0xfff0f0f0, "ssub16\t%8-11r, %16-19r, %0-3r"},
1252 {ARM_EXT_V6T2, 0xfad0f010, 0xfff0f0f0, "qsub16\t%8-11r, %16-19r, %0-3r"},
1253 {ARM_EXT_V6T2, 0xfad0f020, 0xfff0f0f0, "shsub16\t%8-11r, %16-19r, %0-3r"},
1254 {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16\t%8-11r, %16-19r, %0-3r"},
1255 {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16\t%8-11r, %16-19r, %0-3r"},
1256 {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16\t%8-11r, %16-19r, %0-3r"},
1257 {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssubaddx\t%8-11r, %16-19r, %0-3r"},
1258 {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsubaddx\t%8-11r, %16-19r, %0-3r"},
1259 {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsubaddx\t%8-11r, %16-19r, %0-3r"},
1260 {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usubaddx\t%8-11r, %16-19r, %0-3r"},
1261 {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsubaddx\t%8-11r, %16-19r, %0-3r"},
1262 {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsubaddx\t%8-11r, %16-19r, %0-3r"},
1263 {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul.w\t%8-11r, %16-19r, %0-3r"},
1264 {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8\t%8-11r, %16-19r, %0-3r"},
1265 {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's.w\t%8-11r, %16-19r, %0-3r"},
1266 {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's.w\t%8-11r, %16-19r, %0-3r"},
1267 {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's.w\t%8-11r, %16-19r, %0-3r"},
1268 {ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ror%20's.w\t%8-11r, %16-19r, %0-3r"},
1269 {ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "strex%4?hb\t%0-3r, %12-15r, [%16-19r]"},
1270 {ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16\t%8-11r, #%0-4d, %16-19r"},
1271 {ARM_EXT_V6T2, 0xf3a00000, 0xfff0f0e0, "usat16\t%8-11r, #%0-4d, %16-19r"},
1272 {ARM_EXT_V6T2, 0xfb20f000, 0xfff0f0e0, "smuad%4'x\t%8-11r, %16-19r, %0-3r"},
1273 {ARM_EXT_V6T2, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb\t%8-11r, %16-19r, %0-3r"},
1274 {ARM_EXT_V6T2, 0xfb40f000, 0xfff0f0e0, "smusd%4'x\t%8-11r, %16-19r, %0-3r"},
1275 {ARM_EXT_V6T2, 0xfb50f000, 0xfff0f0e0, "smmul%4'r\t%8-11r, %16-19r, %0-3r"},
1276 {ARM_EXT_V6T2, 0xfa00f080, 0xfff0f0c0, "sxtah\t%8-11r, %16-19r, %0-3r%R"},
1277 {ARM_EXT_V6T2, 0xfa10f080, 0xfff0f0c0, "uxtah\t%8-11r, %16-19r, %0-3r%R"},
1278 {ARM_EXT_V6T2, 0xfa20f080, 0xfff0f0c0, "sxtab16\t%8-11r, %16-19r, %0-3r%R"},
1279 {ARM_EXT_V6T2, 0xfa30f080, 0xfff0f0c0, "uxtab16\t%8-11r, %16-19r, %0-3r%R"},
1280 {ARM_EXT_V6T2, 0xfa40f080, 0xfff0f0c0, "sxtab\t%8-11r, %16-19r, %0-3r%R"},
1281 {ARM_EXT_V6T2, 0xfa50f080, 0xfff0f0c0, "uxtab\t%8-11r, %16-19r, %0-3r%R"},
1282 {ARM_EXT_V6T2, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb\t%8-11r, %16-19r, %0-3r"},
1283 {ARM_EXT_V6T2, 0xf36f0000, 0xffff8020, "bfc\t%8-11r, %E"},
1284 {ARM_EXT_V6T2, 0xea100f00, 0xfff08f00, "tst.w\t%16-19r, %S"},
1285 {ARM_EXT_V6T2, 0xea900f00, 0xfff08f00, "teq\t%16-19r, %S"},
1286 {ARM_EXT_V6T2, 0xeb100f00, 0xfff08f00, "cmn.w\t%16-19r, %S"},
1287 {ARM_EXT_V6T2, 0xebb00f00, 0xfff08f00, "cmp.w\t%16-19r, %S"},
1288 {ARM_EXT_V6T2, 0xf0100f00, 0xfbf08f00, "tst.w\t%16-19r, %M"},
1289 {ARM_EXT_V6T2, 0xf0900f00, 0xfbf08f00, "teq\t%16-19r, %M"},
1290 {ARM_EXT_V6T2, 0xf1100f00, 0xfbf08f00, "cmn.w\t%16-19r, %M"},
1291 {ARM_EXT_V6T2, 0xf1b00f00, 0xfbf08f00, "cmp.w\t%16-19r, %M"},
1292 {ARM_EXT_V6T2, 0xea4f0000, 0xffef8000, "mov%20's.w\t%8-11r, %S"},
1293 {ARM_EXT_V6T2, 0xea6f0000, 0xffef8000, "mvn%20's.w\t%8-11r, %S"},
1294 {ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
1295 {ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "mla\t%8-11r, %16-19r, %0-3r, %12-15r"},
1296 {ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "mls\t%8-11r, %16-19r, %0-3r, %12-15r"},
1297 {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8\t%8-11r, %16-19r, %0-3r, %12-15r"},
1298 {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull\t%12-15r, %8-11r, %16-19r, %0-3r"},
1299 {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull\t%12-15r, %8-11r, %16-19r, %0-3r"},
1300 {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal\t%12-15r, %8-11r, %16-19r, %0-3r"},
1301 {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal\t%12-15r, %8-11r, %16-19r, %0-3r"},
1302 {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal\t%12-15r, %8-11r, %16-19r, %0-3r"},
1303 {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex\t%12-15r, [%16-19r, #%0-7W]"},
1304 {ARM_EXT_V6T2, 0xf7f08000, 0xfff0f000, "smc\t%K"},
1305 {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's.w\t%8-11r, %M"},
1306 {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's.w\t%8-11r, %M"},
1307 {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld\t%a"},
1308 {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x\t%8-11r, %16-19r, %0-3r, %12-15r"},
1309 {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb\t%8-11r, %16-19r, %0-3r, %12-15r"},
1310 {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x\t%8-11r, %16-19r, %0-3r, %12-15r"},
1311 {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r\t%8-11r, %16-19r, %0-3r, %12-15r"},
1312 {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r\t%8-11r, %16-19r, %0-3r, %12-15r"},
1313 {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x\t%12-15r, %8-11r, %16-19r, %0-3r"},
1314 {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x\t%12-15r, %8-11r, %16-19r, %0-3r"},
1315 {ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt\t%8-11r, %16-19r, %S"},
1316 {ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb\t%8-11r, %16-19r, %S"},
1317 {ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "sbfx\t%8-11r, %16-19r, %F"},
1318 {ARM_EXT_V6T2, 0xf3c00000, 0xfff08020, "ubfx\t%8-11r, %16-19r, %F"},
1319 {ARM_EXT_V6T2, 0xf8000e00, 0xff900f00, "str%wt\t%12-15r, %a"},
1320 {ARM_EXT_V6T2, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb\t%8-11r, %16-19r, %0-3r, %12-15r"},
1321 {ARM_EXT_V6T2, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb\t%12-15r, %8-11r, %16-19r, %0-3r"},
1322 {ARM_EXT_V6T2, 0xf3600000, 0xfff08020, "bfi\t%8-11r, %16-19r, %E"},
1323 {ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt\t%12-15r, %a"},
1324 {ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat\t%8-11r, #%0-4d, %16-19r%s"},
1325 {ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat\t%8-11r, #%0-4d, %16-19r%s"},
1326 {ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw\t%8-11r, %16-19r, %I"},
1327 {ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw\t%8-11r, %J"},
1328 {ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw\t%8-11r, %16-19r, %I"},
1329 {ARM_EXT_V6T2, 0xf2c00000, 0xfbf08000, "movt\t%8-11r, %J"},
1330 {ARM_EXT_V6T2, 0xea000000, 0xffe08000, "and%20's.w\t%8-11r, %16-19r, %S"},
1331 {ARM_EXT_V6T2, 0xea200000, 0xffe08000, "bic%20's.w\t%8-11r, %16-19r, %S"},
1332 {ARM_EXT_V6T2, 0xea400000, 0xffe08000, "orr%20's.w\t%8-11r, %16-19r, %S"},
1333 {ARM_EXT_V6T2, 0xea600000, 0xffe08000, "orn%20's\t%8-11r, %16-19r, %S"},
1334 {ARM_EXT_V6T2, 0xea800000, 0xffe08000, "eor%20's.w\t%8-11r, %16-19r, %S"},
1335 {ARM_EXT_V6T2, 0xeb000000, 0xffe08000, "add%20's.w\t%8-11r, %16-19r, %S"},
1336 {ARM_EXT_V6T2, 0xeb400000, 0xffe08000, "adc%20's.w\t%8-11r, %16-19r, %S"},
1337 {ARM_EXT_V6T2, 0xeb600000, 0xffe08000, "sbc%20's.w\t%8-11r, %16-19r, %S"},
1338 {ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's.w\t%8-11r, %16-19r, %S"},
1339 {ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's\t%8-11r, %16-19r, %S"},
1340 {ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
1341 {ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's.w\t%8-11r, %16-19r, %M"},
1342 {ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's.w\t%8-11r, %16-19r, %M"},
1343 {ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's.w\t%8-11r, %16-19r, %M"},
1344 {ARM_EXT_V6T2, 0xf0600000, 0xfbe08000, "orn%20's\t%8-11r, %16-19r, %M"},
1345 {ARM_EXT_V6T2, 0xf0800000, 0xfbe08000, "eor%20's.w\t%8-11r, %16-19r, %M"},
1346 {ARM_EXT_V6T2, 0xf1000000, 0xfbe08000, "add%20's.w\t%8-11r, %16-19r, %M"},
1347 {ARM_EXT_V6T2, 0xf1400000, 0xfbe08000, "adc%20's.w\t%8-11r, %16-19r, %M"},
1348 {ARM_EXT_V6T2, 0xf1600000, 0xfbe08000, "sbc%20's.w\t%8-11r, %16-19r, %M"},
1349 {ARM_EXT_V6T2, 0xf1a00000, 0xfbe08000, "sub%20's.w\t%8-11r, %16-19r, %M"},
1350 {ARM_EXT_V6T2, 0xf1c00000, 0xfbe08000, "rsb%20's\t%8-11r, %16-19r, %M"},
1351 {ARM_EXT_V6T2, 0xe8800000, 0xffd00000, "stmia.w\t%16-19r%21'!, %m"},
1352 {ARM_EXT_V6T2, 0xe8900000, 0xffd00000, "ldmia.w\t%16-19r%21'!, %m"},
1353 {ARM_EXT_V6T2, 0xe9000000, 0xffd00000, "stmdb\t%16-19r%21'!, %m"},
1354 {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb\t%16-19r%21'!, %m"},
1355 {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd\t%12-15r, %8-11r, [%16-19r]"},
1356 {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd\t%12-15r, %8-11r, [%16-19r]"},
1357 {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]"},
1358 {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]"},
1359 {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w.w\t%12-15r, %a"},
1360 {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w.w\t%12-15r, %a"},
1362 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
1363 {ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
1364 {ARM_EXT_V6T2, 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
1365 {ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b"},
1366 {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b.w\t%B"},
1368 /* These have been 32-bit since the invention of Thumb. */
1369 {ARM_EXT_V4T, 0xf000c000, 0xf800d000, "blx\t%B"},
1370 {ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl\t%B"},
1373 {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined"},
1377 static const char *const arm_conditional[] =
1378 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
1379 "hi", "ls", "ge", "lt", "gt", "le", "", "<und>"};
1381 static const char *const arm_fp_const[] =
1382 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
1384 static const char *const arm_shift[] =
1385 {"lsl", "lsr", "asr", "ror"};
1390 const char *description;
1391 const char *reg_names[16];
1395 static const arm_regname regnames[] =
1397 { "raw" , "Select raw register names",
1398 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
1399 { "gcc", "Select register names used by GCC",
1400 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
1401 { "std", "Select register names used in ARM's ISA documentation",
1402 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
1403 { "apcs", "Select register names used in the APCS",
1404 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
1405 { "atpcs", "Select register names used in the ATPCS",
1406 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
1407 { "special-atpcs", "Select special register names used in the ATPCS",
1408 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
1411 static const char *const iwmmxt_wwnames[] =
1412 {"b", "h", "w", "d"};
1414 static const char *const iwmmxt_wwssnames[] =
1415 {"b", "bus", "b", "bss",
1416 "h", "hus", "h", "hss",
1417 "w", "wus", "w", "wss",
1418 "d", "dus", "d", "dss"
1421 static const char *const iwmmxt_regnames[] =
1422 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
1423 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
1426 static const char *const iwmmxt_cregnames[] =
1427 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
1428 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
1431 /* Default to GCC register name set. */
1432 static unsigned int regname_selected = 1;
1434 #define NUM_ARM_REGNAMES NUM_ELEM (regnames)
1435 #define arm_regnames regnames[regname_selected].reg_names
1437 static bfd_boolean force_thumb = FALSE;
1442 get_arm_regname_num_options (void)
1444 return NUM_ARM_REGNAMES;
1448 set_arm_regname_option (int option)
1450 int old = regname_selected;
1451 regname_selected = option;
1456 get_arm_regnames (int option, const char **setname, const char **setdescription,
1457 const char *const **register_names)
1459 *setname = regnames[option].name;
1460 *setdescription = regnames[option].description;
1461 *register_names = regnames[option].reg_names;
1465 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
1466 Returns pointer to following character of the format string and
1467 fills in *VALUEP and *WIDTHP with the extracted value and number of
1468 bits extracted. WIDTHP can be NULL. */
1471 arm_decode_bitfield (const char *ptr, unsigned long insn,
1472 unsigned long *valuep, int *widthp)
1474 unsigned long value = 0;
1482 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
1483 start = start * 10 + *ptr - '0';
1485 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
1486 end = end * 10 + *ptr - '0';
1492 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
1495 while (*ptr++ == ',');
1503 arm_decode_shift (long given, fprintf_ftype func, void *stream)
1505 func (stream, "%s", arm_regnames[given & 0xf]);
1507 if ((given & 0xff0) != 0)
1509 if ((given & 0x10) == 0)
1511 int amount = (given & 0xf80) >> 7;
1512 int shift = (given & 0x60) >> 5;
1518 func (stream, ", rrx");
1525 func (stream, ", %s #%d", arm_shift[shift], amount);
1528 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
1529 arm_regnames[(given & 0xf00) >> 8]);
1533 /* Print one coprocessor instruction on INFO->STREAM.
1534 Return TRUE if the instuction matched, FALSE if this is not a
1535 recognised coprocessor instruction. */
1538 print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
1541 const struct opcode32 *insn;
1542 void *stream = info->stream;
1543 fprintf_ftype func = info->fprintf_func;
1545 unsigned long value;
1547 for (insn = coprocessor_opcodes; insn->assembler; insn++)
1549 if (insn->value == FIRST_IWMMXT_INSN
1550 && info->mach != bfd_mach_arm_XScale
1551 && info->mach != bfd_mach_arm_iWMMXt)
1552 insn = insn + IWMMXT_INSN_COUNT;
1555 value = insn->value;
1558 /* The high 4 bits are 0xe for Arm conditional instructions, and
1559 0xe for arm unconditional instructions. The rest of the
1560 encoding is the same. */
1562 value |= 0xe0000000;
1566 /* Only match unconditional instuctions against unconditional
1568 if ((given & 0xf0000000) == 0xf0000000)
1571 if ((given & mask) == value)
1575 for (c = insn->assembler; *c; c++)
1582 func (stream, "%%");
1586 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
1588 if ((given & (1 << 24)) != 0)
1590 int offset = given & 0xff;
1593 func (stream, ", #%s%d]%s",
1594 ((given & 0x00800000) == 0 ? "-" : ""),
1596 ((given & 0x00200000) != 0 ? "!" : ""));
1602 int offset = given & 0xff;
1606 if (given & (1 << 21))
1609 func (stream, ", #%s%d",
1610 ((given & 0x00800000) == 0 ? "-" : ""),
1614 func (stream, ", {%d}", offset);
1620 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
1621 int offset = (given >> 1) & 0x3f;
1624 func (stream, "{d%d}", regno);
1625 else if (regno + offset > 32)
1626 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
1628 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
1634 int rn = (given >> 16) & 0xf;
1635 int offset = (given & 0xff) * 4;
1636 int add = (given >> 23) & 1;
1638 func (stream, "[%s", arm_regnames[rn]);
1644 func (stream, ", #%d", offset);
1649 func (stream, "\t; ");
1650 /* FIXME: Unsure if info->bytes_per_chunk is the
1651 right thing to use here. */
1652 info->print_address_func (offset + pc
1653 + info->bytes_per_chunk * 2, info);
1660 arm_conditional [(given >> 28) & 0xf]);
1664 /* Print a Cirrus/DSP shift immediate. */
1665 /* Immediates are 7bit signed ints with bits 0..3 in
1666 bits 0..3 of opcode and bits 4..6 in bits 5..7
1671 imm = (given & 0xf) | ((given & 0xe0) >> 1);
1673 /* Is ``imm'' a negative number? */
1677 func (stream, "%d", imm);
1683 switch (given & 0x00408000)
1700 switch (given & 0x00080080)
1712 func (stream, _("<illegal precision>"));
1717 switch (given & 0x00408000)
1734 switch (given & 0x60)
1750 case '0': case '1': case '2': case '3': case '4':
1751 case '5': case '6': case '7': case '8': case '9':
1754 unsigned long value;
1756 c = arm_decode_bitfield (c, given, &value, &width);
1761 func (stream, "%s", arm_regnames[value]);
1764 func (stream, "d%ld", value);
1768 func (stream, "<illegal reg q%ld.5>", value >> 1);
1770 func (stream, "q%ld", value >> 1);
1773 func (stream, "%ld", value);
1777 int from = (given & (1 << 7)) ? 32 : 16;
1778 func (stream, "%ld", from - value);
1784 func (stream, "#%s", arm_fp_const[value & 7]);
1786 func (stream, "f%ld", value);
1791 func (stream, "%s", iwmmxt_wwnames[value]);
1793 func (stream, "%s", iwmmxt_wwssnames[value]);
1797 func (stream, "%s", iwmmxt_regnames[value]);
1800 func (stream, "%s", iwmmxt_cregnames[value]);
1805 func (stream, "%c", *c);
1809 if (value == ((1ul << width) - 1))
1810 func (stream, "%c", *c);
1813 func (stream, "%c", c[(1 << width) - (int)value]);
1824 int single = *c++ == 'y';
1829 case '4': /* Sm pair */
1832 case '0': /* Sm, Dm */
1833 regno = given & 0x0000000f;
1837 regno += (given >> 5) & 1;
1840 regno += ((given >> 5) & 1) << 4;
1843 case '1': /* Sd, Dd */
1844 regno = (given >> 12) & 0x0000000f;
1848 regno += (given >> 22) & 1;
1851 regno += ((given >> 22) & 1) << 4;
1854 case '2': /* Sn, Dn */
1855 regno = (given >> 16) & 0x0000000f;
1859 regno += (given >> 7) & 1;
1862 regno += ((given >> 7) & 1) << 4;
1865 case '3': /* List */
1867 regno = (given >> 12) & 0x0000000f;
1871 regno += (given >> 22) & 1;
1874 regno += ((given >> 22) & 1) << 4;
1881 func (stream, "%c%d", single ? 's' : 'd', regno);
1885 int count = given & 0xff;
1892 func (stream, "-%c%d",
1900 func (stream, ", %c%d}", single ? 's' : 'd',
1906 switch (given & 0x00400100)
1908 case 0x00000000: func (stream, "b"); break;
1909 case 0x00400000: func (stream, "h"); break;
1910 case 0x00000100: func (stream, "w"); break;
1911 case 0x00400100: func (stream, "d"); break;
1920 /* given (20, 23) | given (0, 3) */
1921 value = ((given >> 16) & 0xf0) | (given & 0xf);
1922 func (stream, "%d", value);
1927 /* This is like the 'A' operator, except that if
1928 the width field "M" is zero, then the offset is
1929 *not* multiplied by four. */
1931 int offset = given & 0xff;
1932 int multiplier = (given & 0x00000100) ? 4 : 1;
1934 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
1938 if ((given & 0x01000000) != 0)
1939 func (stream, ", #%s%d]%s",
1940 ((given & 0x00800000) == 0 ? "-" : ""),
1941 offset * multiplier,
1942 ((given & 0x00200000) != 0 ? "!" : ""));
1944 func (stream, "], #%s%d",
1945 ((given & 0x00800000) == 0 ? "-" : ""),
1946 offset * multiplier);
1959 func (stream, "%c", *c);
1968 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
1970 void *stream = info->stream;
1971 fprintf_ftype func = info->fprintf_func;
1973 if (((given & 0x000f0000) == 0x000f0000)
1974 && ((given & 0x02000000) == 0))
1976 int offset = given & 0xfff;
1978 func (stream, "[pc");
1980 if (given & 0x01000000)
1982 if ((given & 0x00800000) == 0)
1986 func (stream, ", #%d]", offset);
1990 /* Cope with the possibility of write-back
1991 being used. Probably a very dangerous thing
1992 for the programmer to do, but who are we to
1994 if (given & 0x00200000)
2000 func (stream, "], #%d", offset);
2002 /* ie ignore the offset. */
2006 func (stream, "\t; ");
2007 info->print_address_func (offset, info);
2011 func (stream, "[%s",
2012 arm_regnames[(given >> 16) & 0xf]);
2013 if ((given & 0x01000000) != 0)
2015 if ((given & 0x02000000) == 0)
2017 int offset = given & 0xfff;
2019 func (stream, ", #%s%d",
2020 (((given & 0x00800000) == 0)
2021 ? "-" : ""), offset);
2025 func (stream, ", %s",
2026 (((given & 0x00800000) == 0)
2028 arm_decode_shift (given, func, stream);
2031 func (stream, "]%s",
2032 ((given & 0x00200000) != 0) ? "!" : "");
2036 if ((given & 0x02000000) == 0)
2038 int offset = given & 0xfff;
2040 func (stream, "], #%s%d",
2041 (((given & 0x00800000) == 0)
2042 ? "-" : ""), offset);
2048 func (stream, "], %s",
2049 (((given & 0x00800000) == 0)
2051 arm_decode_shift (given, func, stream);
2057 /* Print one neon instruction on INFO->STREAM.
2058 Return TRUE if the instuction matched, FALSE if this is not a
2059 recognised neon instruction. */
2062 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
2064 const struct opcode32 *insn;
2065 void *stream = info->stream;
2066 fprintf_ftype func = info->fprintf_func;
2070 if ((given & 0xef000000) == 0xef000000)
2072 /* move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
2073 unsigned long bit28 = given & (1 << 28);
2075 given &= 0x00ffffff;
2077 given |= 0xf3000000;
2079 given |= 0xf2000000;
2081 else if ((given & 0xff000000) == 0xf9000000)
2082 given ^= 0xf9000000 ^ 0xf4000000;
2087 for (insn = neon_opcodes; insn->assembler; insn++)
2089 if ((given & insn->mask) == insn->value)
2093 for (c = insn->assembler; *c; c++)
2100 func (stream, "%%");
2105 static const unsigned char enc[16] =
2107 0x4, 0x14, /* st4 0,1 */
2119 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2120 int rn = ((given >> 16) & 0xf);
2121 int rm = ((given >> 0) & 0xf);
2122 int align = ((given >> 4) & 0x3);
2123 int type = ((given >> 8) & 0xf);
2124 int n = enc[type] & 0xf;
2125 int stride = (enc[type] >> 4) + 1;
2130 for (ix = 0; ix != n; ix++)
2131 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
2133 func (stream, "d%d", rd);
2135 func (stream, "d%d-d%d", rd, rd + n - 1);
2136 func (stream, "}, [%s", arm_regnames[rn]);
2138 func (stream, ", :%d", 32 << align);
2143 func (stream, ", %s", arm_regnames[rm]);
2149 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2150 int rn = ((given >> 16) & 0xf);
2151 int rm = ((given >> 0) & 0xf);
2152 int idx_align = ((given >> 4) & 0xf);
2154 int size = ((given >> 10) & 0x3);
2155 int idx = idx_align >> (size + 1);
2156 int length = ((given >> 8) & 3) + 1;
2160 if (length > 1 && size > 0)
2161 stride = (idx_align & (1 << size)) ? 2 : 1;
2167 int amask = (1 << size) - 1;
2168 if ((idx_align & (1 << size)) != 0)
2172 if ((idx_align & amask) == amask)
2174 else if ((idx_align & amask) != 0)
2181 if (size == 2 && (idx_align & 2) != 0)
2183 align = (idx_align & 1) ? 16 << size : 0;
2187 if ((size == 2 && (idx_align & 3) != 0)
2188 || (idx_align & 1) != 0)
2195 if ((idx_align & 3) == 3)
2197 align = (idx_align & 3) * 64;
2200 align = (idx_align & 1) ? 32 << size : 0;
2208 for (i = 0; i < length; i++)
2209 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
2210 rd + i * stride, idx);
2211 func (stream, "}, [%s", arm_regnames[rn]);
2213 func (stream, ", :%d", align);
2218 func (stream, ", %s", arm_regnames[rm]);
2224 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2225 int rn = ((given >> 16) & 0xf);
2226 int rm = ((given >> 0) & 0xf);
2227 int align = ((given >> 4) & 0x1);
2228 int size = ((given >> 6) & 0x3);
2229 int type = ((given >> 8) & 0x3);
2231 int stride = ((given >> 5) & 0x1);
2234 if (stride && (n == 1))
2241 for (ix = 0; ix != n; ix++)
2242 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
2244 func (stream, "d%d[]", rd);
2246 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
2247 func (stream, "}, [%s", arm_regnames[rn]);
2250 int align = (8 * (type + 1)) << size;
2252 align = (size > 1) ? align >> 1 : align;
2253 if (type == 2 || (type == 0 && !size))
2254 func (stream, ", :<bad align %d>", align);
2256 func (stream, ", :%d", align);
2262 func (stream, ", %s", arm_regnames[rm]);
2268 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
2269 int size = (given >> 20) & 3;
2270 int reg = raw_reg & ((4 << size) - 1);
2271 int ix = raw_reg >> size >> 2;
2273 func (stream, "d%d[%d]", reg, ix);
2278 /* Neon encoded constant for mov, mvn, vorr, vbic */
2281 int cmode = (given >> 8) & 0xf;
2282 int op = (given >> 5) & 0x1;
2283 unsigned long value = 0, hival = 0;
2287 bits |= ((given >> 24) & 1) << 7;
2288 bits |= ((given >> 16) & 7) << 4;
2289 bits |= ((given >> 0) & 15) << 0;
2293 shift = (cmode >> 1) & 3;
2294 value = (unsigned long)bits << (8 * shift);
2297 else if (cmode < 12)
2299 shift = (cmode >> 1) & 1;
2300 value = (unsigned long)bits << (8 * shift);
2303 else if (cmode < 14)
2305 shift = (cmode & 1) + 1;
2306 value = (unsigned long)bits << (8 * shift);
2307 value |= (1ul << (8 * shift)) - 1;
2310 else if (cmode == 14)
2314 /* bit replication into bytes */
2320 for (ix = 7; ix >= 0; ix--)
2322 mask = ((bits >> ix) & 1) ? 0xff : 0;
2324 value = (value << 8) | mask;
2326 hival = (hival << 8) | mask;
2332 /* byte replication */
2333 value = (unsigned long)bits;
2339 /* floating point encoding */
2342 value = (unsigned long)(bits & 0x7f) << (24 - 6);
2343 value |= (unsigned long)(bits & 0x80) << 24;
2344 tmp = bits & 0x40 ? 0x3c : 0x40;
2345 value |= (unsigned long)tmp << 24;
2350 func (stream, "<illegal constant %.8x:%x:%x>",
2358 func (stream, "#%ld\t; 0x%.2lx", value, value);
2362 func (stream, "#%ld\t; 0x%.4lx", value, value);
2366 func (stream, "#%ld\t; 0x%.8lx", value, value);
2370 func (stream, "#0x%.8lx%.8lx", hival, value);
2381 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
2382 int num = (given >> 8) & 0x3;
2385 func (stream, "{d%d}", regno);
2386 else if (num + regno >= 32)
2387 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
2389 func (stream, "{d%d-d%d}", regno, regno + num);
2394 case '0': case '1': case '2': case '3': case '4':
2395 case '5': case '6': case '7': case '8': case '9':
2398 unsigned long value;
2400 c = arm_decode_bitfield (c, given, &value, &width);
2405 func (stream, "%s", arm_regnames[value]);
2408 func (stream, "%ld", value);
2411 func (stream, "%ld", (1ul << width) - value);
2417 /* various width encodings */
2419 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
2424 if (*c >= '0' && *c <= '9')
2426 else if (*c >= 'a' && *c <= 'f')
2427 limit = *c - 'a' + 10;
2433 if (value < low || value > high)
2434 func (stream, "<illegal width %d>", base << value);
2436 func (stream, "%d", base << value);
2440 if (given & (1 << 6))
2444 func (stream, "d%ld", value);
2449 func (stream, "<illegal reg q%ld.5>", value >> 1);
2451 func (stream, "q%ld", value >> 1);
2457 func (stream, "%c", *c);
2461 if (value == ((1ul << width) - 1))
2462 func (stream, "%c", *c);
2465 func (stream, "%c", c[(1 << width) - (int)value]);
2479 func (stream, "%c", *c);
2487 /* Print one ARM instruction from PC on INFO->STREAM. */
2490 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
2492 const struct opcode32 *insn;
2493 void *stream = info->stream;
2494 fprintf_ftype func = info->fprintf_func;
2496 if (print_insn_coprocessor (pc, info, given, FALSE))
2499 if (print_insn_neon (info, given, FALSE))
2502 for (insn = arm_opcodes; insn->assembler; insn++)
2504 if (insn->value == FIRST_IWMMXT_INSN
2505 && info->mach != bfd_mach_arm_XScale
2506 && info->mach != bfd_mach_arm_iWMMXt)
2507 insn = insn + IWMMXT_INSN_COUNT;
2509 if ((given & insn->mask) == insn->value
2510 /* Special case: an instruction with all bits set in the condition field
2511 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
2512 or by the catchall at the end of the table. */
2513 && ((given & 0xF0000000) != 0xF0000000
2514 || (insn->mask & 0xF0000000) == 0xF0000000
2515 || (insn->mask == 0 && insn->value == 0)))
2519 for (c = insn->assembler; *c; c++)
2526 func (stream, "%%");
2530 print_arm_address (pc, info, given);
2534 /* Set P address bit and use normal address
2535 printing routine. */
2536 print_arm_address (pc, info, given | (1 << 24));
2540 if ((given & 0x004f0000) == 0x004f0000)
2542 /* PC relative with immediate offset. */
2543 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
2545 if ((given & 0x00800000) == 0)
2548 func (stream, "[pc, #%d]\t; ", offset);
2549 info->print_address_func (offset + pc + 8, info);
2553 func (stream, "[%s",
2554 arm_regnames[(given >> 16) & 0xf]);
2555 if ((given & 0x01000000) != 0)
2558 if ((given & 0x00400000) == 0x00400000)
2561 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
2563 func (stream, ", #%s%d",
2564 (((given & 0x00800000) == 0)
2565 ? "-" : ""), offset);
2570 func (stream, ", %s%s",
2571 (((given & 0x00800000) == 0)
2573 arm_regnames[given & 0xf]);
2576 func (stream, "]%s",
2577 ((given & 0x00200000) != 0) ? "!" : "");
2582 if ((given & 0x00400000) == 0x00400000)
2585 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
2587 func (stream, "], #%s%d",
2588 (((given & 0x00800000) == 0)
2589 ? "-" : ""), offset);
2596 func (stream, "], %s%s",
2597 (((given & 0x00800000) == 0)
2599 arm_regnames[given & 0xf]);
2607 int disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
2608 info->print_address_func (disp*4 + pc + 8, info);
2614 arm_conditional [(given >> 28) & 0xf]);
2623 for (reg = 0; reg < 16; reg++)
2624 if ((given & (1 << reg)) != 0)
2627 func (stream, ", ");
2629 func (stream, "%s", arm_regnames[reg]);
2636 if ((given & 0x02000000) != 0)
2638 int rotate = (given & 0xf00) >> 7;
2639 int immed = (given & 0xff);
2640 immed = (((immed << (32 - rotate))
2641 | (immed >> rotate)) & 0xffffffff);
2642 func (stream, "#%d\t; 0x%x", immed, immed);
2645 arm_decode_shift (given, func, stream);
2649 if ((given & 0x0000f000) == 0x0000f000)
2654 if ((given & 0x01200000) == 0x00200000)
2659 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
2661 if ((given & (1 << 24)) != 0)
2663 int offset = given & 0xff;
2666 func (stream, ", #%s%d]%s",
2667 ((given & 0x00800000) == 0 ? "-" : ""),
2669 ((given & 0x00200000) != 0 ? "!" : ""));
2675 int offset = given & 0xff;
2679 if (given & (1 << 21))
2682 func (stream, ", #%s%d",
2683 ((given & 0x00800000) == 0 ? "-" : ""),
2687 func (stream, ", {%d}", offset);
2692 /* Print ARM V5 BLX(1) address: pc+25 bits. */
2697 if (given & 0x00800000)
2698 /* Is signed, hi bits should be ones. */
2699 offset = (-1) ^ 0x00ffffff;
2701 /* Offset is (SignExtend(offset field)<<2). */
2702 offset += given & 0x00ffffff;
2704 address = offset + pc + 8;
2706 if (given & 0x01000000)
2707 /* H bit allows addressing to 2-byte boundaries. */
2710 info->print_address_func (address, info);
2716 if (given & 0x80000)
2718 if (given & 0x40000)
2720 if (given & 0x20000)
2722 if (given & 0x10000)
2727 switch (given & 0xf)
2729 case 0xf: func(stream, "sy"); break;
2730 case 0x7: func(stream, "un"); break;
2731 case 0xe: func(stream, "st"); break;
2732 case 0x6: func(stream, "unst"); break;
2734 func(stream, "#%d", (int)given & 0xf);
2739 case '0': case '1': case '2': case '3': case '4':
2740 case '5': case '6': case '7': case '8': case '9':
2743 unsigned long value;
2745 c = arm_decode_bitfield (c, given, &value, &width);
2750 func (stream, "%s", arm_regnames[value]);
2753 func (stream, "%ld", value);
2756 func (stream, "%ld", value * 8);
2759 func (stream, "%ld", value + 1);
2762 func (stream, "0x%08lx", value);
2764 /* Some SWI instructions have special
2766 if ((given & 0x0fffffff) == 0x0FF00000)
2767 func (stream, "\t; IMB");
2768 else if ((given & 0x0fffffff) == 0x0FF00001)
2769 func (stream, "\t; IMBRange");
2772 func (stream, "%01lx", value & 0xf);
2777 func (stream, "%c", *c);
2781 if (value == ((1ul << width) - 1))
2782 func (stream, "%c", *c);
2785 func (stream, "%c", c[(1 << width) - (int)value]);
2797 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
2798 func (stream, "%d", imm);
2803 /* LSB and WIDTH fields of BFI or BFC. The machine-
2804 language instruction encodes LSB and MSB. */
2806 long msb = (given & 0x001f0000) >> 16;
2807 long lsb = (given & 0x00000f80) >> 7;
2809 long width = msb - lsb + 1;
2811 func (stream, "#%lu, #%lu", lsb, width);
2813 func (stream, "(invalid: %lu:%lu)", lsb, msb);
2818 /* 16-bit unsigned immediate from a MOVT or MOVW
2819 instruction, encoded in bits 0:11 and 15:19. */
2821 long hi = (given & 0x000f0000) >> 4;
2822 long lo = (given & 0x00000fff);
2823 long imm16 = hi | lo;
2824 func (stream, "#%lu\t; 0x%lx", imm16, imm16);
2834 func (stream, "%c", *c);
2842 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
2845 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
2847 const struct opcode16 *insn;
2848 void *stream = info->stream;
2849 fprintf_ftype func = info->fprintf_func;
2851 for (insn = thumb_opcodes; insn->assembler; insn++)
2852 if ((given & insn->mask) == insn->value)
2854 const char *c = insn->assembler;
2862 func (stream, "%c", *c);
2869 func (stream, "%%");
2876 reg = (given >> 3) & 0x7;
2877 if (given & (1 << 6))
2880 func (stream, "%s", arm_regnames[reg]);
2889 if (given & (1 << 7))
2892 func (stream, "%s", arm_regnames[reg]);
2897 if (given & (1 << 8))
2901 if (*c == 'O' && (given & (1 << 8)))
2911 /* It would be nice if we could spot
2912 ranges, and generate the rS-rE format: */
2913 for (reg = 0; (reg < 8); reg++)
2914 if ((given & (1 << reg)) != 0)
2917 func (stream, ", ");
2919 func (stream, "%s", arm_regnames[reg]);
2925 func (stream, ", ");
2927 func (stream, arm_regnames[14] /* "lr" */);
2933 func (stream, ", ");
2934 func (stream, arm_regnames[15] /* "pc" */);
2942 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
2944 bfd_vma address = (pc + 4
2945 + ((given & 0x00f8) >> 2)
2946 + ((given & 0x0200) >> 3));
2947 info->print_address_func (address, info);
2952 /* Right shift immediate -- bits 6..10; 1-31 print
2953 as themselves, 0 prints as 32. */
2955 long imm = (given & 0x07c0) >> 6;
2958 func (stream, "#%ld", imm);
2962 case '0': case '1': case '2': case '3': case '4':
2963 case '5': case '6': case '7': case '8': case '9':
2965 int bitstart = *c++ - '0';
2968 while (*c >= '0' && *c <= '9')
2969 bitstart = (bitstart * 10) + *c++ - '0';
2978 while (*c >= '0' && *c <= '9')
2979 bitend = (bitend * 10) + *c++ - '0';
2982 reg = given >> bitstart;
2983 reg &= (2 << (bitend - bitstart)) - 1;
2987 func (stream, "%s", arm_regnames[reg]);
2991 func (stream, "%ld", reg);
2995 func (stream, "%ld", reg << 1);
2999 func (stream, "%ld", reg << 2);
3003 /* PC-relative address -- the bottom two
3004 bits of the address are dropped
3005 before the calculation. */
3006 info->print_address_func
3007 (((pc + 4) & ~3) + (reg << 2), info);
3011 func (stream, "0x%04lx", reg);
3015 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
3016 info->print_address_func (reg * 2 + pc + 4, info);
3021 /* Must print 0xE as 'al' to distinguish
3022 unconditional B from conditional BAL. */
3024 func (stream, "al");
3026 func (stream, "%s", arm_conditional [reg]);
3038 if ((given & (1 << bitstart)) != 0)
3039 func (stream, "%c", *c);
3044 if ((given & (1 << bitstart)) != 0)
3045 func (stream, "%c", *c++);
3047 func (stream, "%c", *++c);
3067 /* Return the name of an V7M special register. */
3069 psr_name (int regno)
3073 case 0: return "APSR";
3074 case 1: return "IAPSR";
3075 case 2: return "EAPSR";
3076 case 3: return "PSR";
3077 case 5: return "IPSR";
3078 case 6: return "EPSR";
3079 case 7: return "IEPSR";
3080 case 8: return "MSP";
3081 case 9: return "PSP";
3082 case 16: return "PRIMASK";
3083 case 17: return "BASEPRI";
3084 case 18: return "BASEPRI_MASK";
3085 case 19: return "FAULTMASK";
3086 case 20: return "CONTROL";
3087 default: return "<unknown>";
3091 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
3094 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
3096 const struct opcode32 *insn;
3097 void *stream = info->stream;
3098 fprintf_ftype func = info->fprintf_func;
3100 if (print_insn_coprocessor (pc, info, given, TRUE))
3103 if (print_insn_neon (info, given, TRUE))
3106 for (insn = thumb32_opcodes; insn->assembler; insn++)
3107 if ((given & insn->mask) == insn->value)
3109 const char *c = insn->assembler;
3114 func (stream, "%c", *c);
3121 func (stream, "%%");
3126 unsigned int imm12 = 0;
3127 imm12 |= (given & 0x000000ffu);
3128 imm12 |= (given & 0x00007000u) >> 4;
3129 imm12 |= (given & 0x04000000u) >> 15;
3130 func (stream, "#%u\t; 0x%x", imm12, imm12);
3136 unsigned int bits = 0, imm, imm8, mod;
3137 bits |= (given & 0x000000ffu);
3138 bits |= (given & 0x00007000u) >> 4;
3139 bits |= (given & 0x04000000u) >> 15;
3140 imm8 = (bits & 0x0ff);
3141 mod = (bits & 0xf00) >> 8;
3144 case 0: imm = imm8; break;
3145 case 1: imm = ((imm8<<16) | imm8); break;
3146 case 2: imm = ((imm8<<24) | (imm8 << 8)); break;
3147 case 3: imm = ((imm8<<24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
3149 mod = (bits & 0xf80) >> 7;
3150 imm8 = (bits & 0x07f) | 0x80;
3151 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
3153 func (stream, "#%u\t; 0x%x", imm, imm);
3159 unsigned int imm = 0;
3160 imm |= (given & 0x000000ffu);
3161 imm |= (given & 0x00007000u) >> 4;
3162 imm |= (given & 0x04000000u) >> 15;
3163 imm |= (given & 0x000f0000u) >> 4;
3164 func (stream, "#%u\t; 0x%x", imm, imm);
3170 unsigned int imm = 0;
3171 imm |= (given & 0x000f0000u) >> 16;
3172 imm |= (given & 0x00000ff0u) >> 0;
3173 imm |= (given & 0x0000000fu) << 12;
3174 func (stream, "#%u\t; 0x%x", imm, imm);
3180 unsigned int reg = (given & 0x0000000fu);
3181 unsigned int stp = (given & 0x00000030u) >> 4;
3182 unsigned int imm = 0;
3183 imm |= (given & 0x000000c0u) >> 6;
3184 imm |= (given & 0x00007000u) >> 10;
3186 func (stream, "%s", arm_regnames[reg]);
3191 func (stream, ", lsl #%u", imm);
3197 func (stream, ", lsr #%u", imm);
3203 func (stream, ", asr #%u", imm);
3208 func (stream, ", rrx");
3210 func (stream, ", ror #%u", imm);
3217 unsigned int Rn = (given & 0x000f0000) >> 16;
3218 unsigned int U = (given & 0x00800000) >> 23;
3219 unsigned int op = (given & 0x00000f00) >> 8;
3220 unsigned int i12 = (given & 0x00000fff);
3221 unsigned int i8 = (given & 0x000000ff);
3222 bfd_boolean writeback = FALSE, postind = FALSE;
3225 func (stream, "[%s", arm_regnames[Rn]);
3226 if (U) /* 12-bit positive immediate offset */
3228 else if (Rn == 15) /* 12-bit negative immediate offset */
3230 else if (op == 0x0) /* shifted register offset */
3232 unsigned int Rm = (i8 & 0x0f);
3233 unsigned int sh = (i8 & 0x30) >> 4;
3234 func (stream, ", %s", arm_regnames[Rm]);
3236 func (stream, ", lsl #%u", sh);
3242 case 0xE: /* 8-bit positive immediate offset */
3246 case 0xC: /* 8-bit negative immediate offset */
3250 case 0xF: /* 8-bit + preindex with wb */
3255 case 0xD: /* 8-bit - preindex with wb */
3260 case 0xB: /* 8-bit + postindex */
3265 case 0x9: /* 8-bit - postindex */
3271 func (stream, ", <undefined>]");
3276 func (stream, "], #%d", offset);
3280 func (stream, ", #%d", offset);
3281 func (stream, writeback ? "]!" : "]");
3286 func (stream, "\t; ");
3287 info->print_address_func (((pc + 4) & ~3) + offset, info);
3295 unsigned int P = (given & 0x01000000) >> 24;
3296 unsigned int U = (given & 0x00800000) >> 23;
3297 unsigned int W = (given & 0x00400000) >> 21;
3298 unsigned int Rn = (given & 0x000f0000) >> 16;
3299 unsigned int off = (given & 0x000000ff);
3301 func (stream, "[%s", arm_regnames[Rn]);
3305 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
3312 func (stream, "], ");
3314 func (stream, "#%c%u", U ? '+' : '-', off * 4);
3316 func (stream, "{%u}", off);
3323 unsigned int Sbit = (given & 0x01000000) >> 24;
3324 unsigned int type = (given & 0x00600000) >> 21;
3327 case 0: func (stream, Sbit ? "sb" : "b"); break;
3328 case 1: func (stream, Sbit ? "sh" : "h"); break;
3331 func (stream, "??");
3334 func (stream, "??");
3346 for (reg = 0; reg < 16; reg++)
3347 if ((given & (1 << reg)) != 0)
3350 func (stream, ", ");
3352 func (stream, "%s", arm_regnames[reg]);
3360 unsigned int msb = (given & 0x0000001f);
3361 unsigned int lsb = 0;
3362 lsb |= (given & 0x000000c0u) >> 6;
3363 lsb |= (given & 0x00007000u) >> 10;
3364 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
3370 unsigned int width = (given & 0x0000001f) + 1;
3371 unsigned int lsb = 0;
3372 lsb |= (given & 0x000000c0u) >> 6;
3373 lsb |= (given & 0x00007000u) >> 10;
3374 func (stream, "#%u, #%u", lsb, width);
3380 unsigned int S = (given & 0x04000000u) >> 26;
3381 unsigned int J1 = (given & 0x00002000u) >> 13;
3382 unsigned int J2 = (given & 0x00000800u) >> 11;
3388 offset |= (given & 0x003f0000) >> 4;
3389 offset |= (given & 0x000007ff) << 1;
3390 offset -= (1 << 20);
3392 info->print_address_func (pc + 4 + offset, info);
3398 unsigned int S = (given & 0x04000000u) >> 26;
3399 unsigned int I1 = (given & 0x00002000u) >> 13;
3400 unsigned int I2 = (given & 0x00000800u) >> 11;
3404 offset |= !(I1 ^ S) << 23;
3405 offset |= !(I2 ^ S) << 22;
3406 offset |= (given & 0x03ff0000u) >> 4;
3407 offset |= (given & 0x000007ffu) << 1;
3408 offset -= (1 << 24);
3411 /* BLX target addresses are always word aligned. */
3412 if ((given & 0x00001000u) == 0)
3415 info->print_address_func (offset, info);
3421 unsigned int shift = 0;
3422 shift |= (given & 0x000000c0u) >> 6;
3423 shift |= (given & 0x00007000u) >> 10;
3424 if (given & 0x00200000u)
3425 func (stream, ", asr #%u", shift);
3427 func (stream, ", lsl #%u", shift);
3428 /* else print nothing - lsl #0 */
3434 unsigned int rot = (given & 0x00000030) >> 4;
3436 func (stream, ", ror #%u", rot * 8);
3441 switch (given & 0xf)
3443 case 0xf: func(stream, "sy"); break;
3444 case 0x7: func(stream, "un"); break;
3445 case 0xe: func(stream, "st"); break;
3446 case 0x6: func(stream, "unst"); break;
3448 func(stream, "#%d", (int)given & 0xf);
3454 if ((given & 0xff) == 0)
3456 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
3468 func (stream, psr_name (given & 0xff));
3473 if ((given & 0xff) == 0)
3474 func (stream, "%cPSR", (given & 0x100000) ? 'S' : 'C');
3476 func (stream, psr_name (given & 0xff));
3479 case '0': case '1': case '2': case '3': case '4':
3480 case '5': case '6': case '7': case '8': case '9':
3485 c = arm_decode_bitfield (c, given, &val, &width);
3489 case 'd': func (stream, "%lu", val); break;
3490 case 'W': func (stream, "%lu", val * 4); break;
3491 case 'r': func (stream, "%s", arm_regnames[val]); break;
3495 func (stream, "al");
3497 func (stream, "%s", arm_conditional[val]);
3502 if (val == ((1ul << width) - 1))
3503 func (stream, "%c", *c);
3509 func (stream, "%c", *c);
3513 func (stream, "%c", c[(1 << width) - (int)val]);
3534 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
3535 being displayed in symbol relative addresses. */
3538 arm_symbol_is_valid (asymbol * sym,
3539 struct disassemble_info * info ATTRIBUTE_UNUSED)
3546 name = bfd_asymbol_name (sym);
3548 return (name && *name != '$');
3551 /* Parse an individual disassembler option. */
3554 parse_arm_disassembler_option (char *option)
3559 if (strneq (option, "reg-names-", 10))
3565 for (i = NUM_ARM_REGNAMES; i--;)
3566 if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
3568 regname_selected = i;
3573 /* XXX - should break 'option' at following delimiter. */
3574 fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
3576 else if (strneq (option, "force-thumb", 11))
3578 else if (strneq (option, "no-force-thumb", 14))
3581 /* XXX - should break 'option' at following delimiter. */
3582 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
3587 /* Parse the string of disassembler options, spliting it at whitespaces
3588 or commas. (Whitespace separators supported for backwards compatibility). */
3591 parse_disassembler_options (char *options)
3593 if (options == NULL)
3598 parse_arm_disassembler_option (options);
3600 /* Skip forward to next seperator. */
3601 while ((*options) && (! ISSPACE (*options)) && (*options != ','))
3603 /* Skip forward past seperators. */
3604 while (ISSPACE (*options) || (*options == ','))
3609 /* NOTE: There are no checks in these routines that
3610 the relevant number of data bytes exist. */
3613 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
3620 void (*printer) (bfd_vma, struct disassemble_info *, long);
3622 if (info->disassembler_options)
3624 parse_disassembler_options (info->disassembler_options);
3626 /* To avoid repeated parsing of these options, we remove them here. */
3627 info->disassembler_options = NULL;
3630 is_thumb = force_thumb;
3632 if (!is_thumb && info->symbols != NULL)
3634 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
3636 coff_symbol_type * cs;
3638 cs = coffsymbol (*info->symbols);
3639 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
3640 || cs->native->u.syment.n_sclass == C_THUMBSTAT
3641 || cs->native->u.syment.n_sclass == C_THUMBLABEL
3642 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
3643 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
3645 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour)
3647 elf_symbol_type * es;
3650 es = *(elf_symbol_type **)(info->symbols);
3651 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
3653 is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT);
3657 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
3658 info->bytes_per_line = 4;
3662 /* In ARM mode endianness is a straightforward issue: the instruction
3663 is four bytes long and is either ordered 0123 or 3210. */
3664 printer = print_insn_arm;
3665 info->bytes_per_chunk = 4;
3668 status = info->read_memory_func (pc, (bfd_byte *)b, 4, info);
3670 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
3672 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
3676 /* In Thumb mode we have the additional wrinkle of two
3677 instruction lengths. Fortunately, the bits that determine
3678 the length of the current instruction are always to be found
3679 in the first two bytes. */
3680 printer = print_insn_thumb16;
3681 info->bytes_per_chunk = 2;
3684 status = info->read_memory_func (pc, (bfd_byte *)b, 2, info);
3686 given = (b[0]) | (b[1] << 8);
3688 given = (b[1]) | (b[0] << 8);
3692 /* These bit patterns signal a four-byte Thumb
3694 if ((given & 0xF800) == 0xF800
3695 || (given & 0xF800) == 0xF000
3696 || (given & 0xF800) == 0xE800)
3698 status = info->read_memory_func (pc + 2, (bfd_byte *)b, 2, info);
3700 given = (b[0]) | (b[1] << 8) | (given << 16);
3702 given = (b[1]) | (b[0] << 8) | (given << 16);
3704 printer = print_insn_thumb32;
3712 info->memory_error_func (status, pc, info);
3715 if (info->flags & INSN_HAS_RELOC)
3716 /* If the instruction has a reloc associated with it, then
3717 the offset field in the instruction will actually be the
3718 addend for the reloc. (We are using REL type relocs).
3719 In such cases, we can ignore the pc when computing
3720 addresses, since the addend is not currently pc-relative. */
3723 printer (pc, info, given);
3728 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
3730 return print_insn (pc, info, FALSE);
3734 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
3736 return print_insn (pc, info, TRUE);
3740 print_arm_disassembler_options (FILE *stream)
3744 fprintf (stream, _("\n\
3745 The following ARM specific disassembler options are supported for use with\n\
3746 the -M switch:\n"));
3748 for (i = NUM_ARM_REGNAMES; i--;)
3749 fprintf (stream, " reg-names-%s %*c%s\n",
3751 (int)(14 - strlen (regnames[i].name)), ' ',
3752 regnames[i].description);
3754 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
3755 fprintf (stream, " no-force-thumb Examine preceeding label to determine an insn's type\n\n");