opcodes/arm-dis.c

   1 /* Instruction printing code for the ARM
   2    Copyright (C) 1994-2018 Free Software Foundation, Inc.
   3    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
   4    Modification by James G. Smith (jsmith@cygnus.co.uk)
   5
   6    This file is part of libopcodes.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include "sysdep.h"
  24
  25 #include "disassemble.h"
  26 #include "opcode/arm.h"
  27 #include "opintl.h"
  28 #include "safe-ctype.h"
  29 #include "libiberty.h"
  30 #include "floatformat.h"
  31
  32 /* FIXME: This shouldn't be done here.  */
  33 #include "coff/internal.h"
  34 #include "libcoff.h"
  35 #include "elf-bfd.h"
  36 #include "elf/internal.h"
  37 #include "elf/arm.h"
  38 #include "mach-o.h"
  39
  40 /* FIXME: Belongs in global header.  */
  41 #ifndef strneq
  42 #define strneq(a,b,n)   (strncmp ((a), (b), (n)) == 0)
  43 #endif
  44
  45 /* Cached mapping symbol state.  */
  46 enum map_type
  47 {
  48   MAP_ARM,
  49   MAP_THUMB,
  50   MAP_DATA
  51 };
  52
  53 struct arm_private_data
  54 {
  55   /* The features to use when disassembling optional instructions.  */
  56   arm_feature_set features;
  57
  58   /* Whether any mapping symbols are present in the provided symbol
  59      table.  -1 if we do not know yet, otherwise 0 or 1.  */
  60   int has_mapping_symbols;
  61
  62   /* Track the last type (although this doesn't seem to be useful) */
  63   enum map_type last_type;
  64
  65   /* Tracking symbol table information */
  66   int last_mapping_sym;
  67   bfd_vma last_mapping_addr;
  68 };
  69
  70 struct opcode32
  71 {
  72   arm_feature_set arch;         /* Architecture defining this insn.  */
  73   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
  74   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
  75   const char *  assembler;      /* How to disassemble this insn.  */
  76 };
  77
  78 struct opcode16
  79 {
  80   arm_feature_set arch;         /* Architecture defining this insn.  */
  81   unsigned short value, mask;   /* Recognise insn if (op & mask) == value.  */
  82   const char *assembler;        /* How to disassemble this insn.  */
  83 };
  84
  85 /* print_insn_coprocessor recognizes the following format control codes:
  86
  87    %%                   %
  88
  89    %c                   print condition code (always bits 28-31 in ARM mode)
  90    %q                   print shifter argument
  91    %u                   print condition code (unconditional in ARM mode,
  92                           UNPREDICTABLE if not AL in Thumb)
  93    %A                   print address for ldc/stc/ldf/stf instruction
  94    %B                   print vstm/vldm register list
  95    %I                   print cirrus signed shift immediate: bits 0..3|4..6
  96    %F                   print the COUNT field of a LFM/SFM instruction.
  97    %P                   print floating point precision in arithmetic insn
  98    %Q                   print floating point precision in ldf/stf insn
  99    %R                   print floating point rounding mode
 100
 101    %<bitfield>c         print as a condition code (for vsel)
 102    %<bitfield>r         print as an ARM register
 103    %<bitfield>R         as %<>r but r15 is UNPREDICTABLE
 104    %<bitfield>ru        as %<>r but each u register must be unique.
 105    %<bitfield>d         print the bitfield in decimal
 106    %<bitfield>k         print immediate for VFPv3 conversion instruction
 107    %<bitfield>x         print the bitfield in hex
 108    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
 109    %<bitfield>f         print a floating point constant if >7 else a
 110                         floating point register
 111    %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
 112    %<bitfield>g         print as an iWMMXt 64-bit register
 113    %<bitfield>G         print as an iWMMXt general purpose or control register
 114    %<bitfield>D         print as a NEON D register
 115    %<bitfield>Q         print as a NEON Q register
 116    %<bitfield>V         print as a NEON D or Q register
 117    %<bitfield>E         print a quarter-float immediate value
 118
 119    %y<code>             print a single precision VFP reg.
 120                           Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
 121    %z<code>             print a double precision VFP reg
 122                           Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
 123
 124    %<bitfield>'c        print specified char iff bitfield is all ones
 125    %<bitfield>`c        print specified char iff bitfield is all zeroes
 126    %<bitfield>?ab...    select from array of values in big endian order
 127
 128    %L                   print as an iWMMXt N/M width field.
 129    %Z                   print the Immediate of a WSHUFH instruction.
 130    %l                   like 'A' except use byte offsets for 'B' & 'H'
 131                         versions.
 132    %i                   print 5-bit immediate in bits 8,3..0
 133                         (print "32" when 0)
 134    %r                   print register offset address for wldt/wstr instruction.  */
 135
 136 enum opcode_sentinel_enum
 137 {
 138   SENTINEL_IWMMXT_START = 1,
 139   SENTINEL_IWMMXT_END,
 140   SENTINEL_GENERIC_START
 141 } opcode_sentinels;
 142
 143 #define UNDEFINED_INSTRUCTION      "\t\t; <UNDEFINED> instruction: %0-31x"
 144 #define UNKNOWN_INSTRUCTION_32BIT  "\t\t; <UNDEFINED> instruction: %08x"
 145 #define UNKNOWN_INSTRUCTION_16BIT  "\t\t; <UNDEFINED> instruction: %04x"
 146 #define UNPREDICTABLE_INSTRUCTION  "\t; <UNPREDICTABLE>"
 147
 148 /* Common coprocessor opcodes shared between Arm and Thumb-2.  */
 149
 150 static const struct opcode32 coprocessor_opcodes[] =
 151 {
 152   /* XScale instructions.  */
 153   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 154     0x0e200010, 0x0fff0ff0,
 155     "mia%c\tacc0, %0-3r, %12-15r"},
 156   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 157     0x0e280010, 0x0fff0ff0,
 158     "miaph%c\tacc0, %0-3r, %12-15r"},
 159   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 160     0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
 161   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 162     0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
 163   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 164     0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
 165
 166   /* Intel Wireless MMX technology instructions.  */
 167   {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
 168   {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
 169     0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
 170   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 171     0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
 172   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 173     0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
 174   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 175     0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
 176   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 177     0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
 178   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 179     0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
 180   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 181     0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
 182   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 183     0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
 184   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 185     0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
 186   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 187     0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
 188   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 189     0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
 190   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 191     0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
 192   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 193     0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
 194   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 195     0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
 196   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 197     0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
 198   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 199     0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
 200   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 201     0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
 202   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 203     0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 204   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 205     0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
 206   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 207     0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
 208   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 209     0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
 210   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 211     0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
 212   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 213     0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
 214   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 215     0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
 216   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 217     0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
 218   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 219     0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 220   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 221     0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 222   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 223     0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
 224   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 225     0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
 226   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 227     0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
 228   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 229     0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
 230   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 231     0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
 232   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 233     0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
 234   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 235     0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 236   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 237     0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
 238   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 239     0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 240   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 241     0x0e800120, 0x0f800ff0,
 242     "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 243   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 244     0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 245   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 246     0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
 247   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 248     0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
 249   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 250     0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
 251   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 252     0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
 253   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 254     0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
 255   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 256     0x0e8000a0, 0x0f800ff0,
 257     "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 258   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 259     0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 260   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 261     0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 262   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 263     0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
 264   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 265     0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 266   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 267     0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
 268   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 269     0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 270   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 271     0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
 272   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 273     0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
 274   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 275     0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
 276   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 277     0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
 278   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 279     0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 280   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 281     0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 282   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 283     0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
 284   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 285     0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 286   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 287     0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 288   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 289     0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
 290   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 291     0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 292   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 293     0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 294   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 295     0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
 296   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 297     0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
 298   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 299     0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
 300   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 301     0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 302   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 303     0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
 304   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 305     0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 306   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 307     0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
 308   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 309     0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
 310   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 311     0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
 312   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 313     0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
 314   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 315     0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 316   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 317     0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 318   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 319     0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
 320   {ARM_FEATURE_CORE_LOW (0),
 321     SENTINEL_IWMMXT_END, 0, "" },
 322
 323   /* Floating point coprocessor (FPA) instructions.  */
 324   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 325     0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 326   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 327     0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 328   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 329     0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 330   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 331     0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 332   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 333     0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 334   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 335     0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 336   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 337     0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
 338   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 339     0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
 340   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 341     0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 342   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 343     0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
 344   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 345     0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
 346   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 347     0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
 348   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 349     0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
 350   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 351     0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
 352   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 353     0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
 354   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 355     0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
 356   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 357     0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
 358   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 359     0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
 360   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 361     0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
 362   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 363     0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
 364   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 365     0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
 366   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 367     0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
 368   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 369     0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
 370   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 371     0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
 372   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 373     0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
 374   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 375     0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
 376   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 377     0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
 378   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 379     0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
 380   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 381     0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
 382   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 383     0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
 384   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 385     0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
 386   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 387     0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
 388   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 389     0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
 390   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 391     0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
 392   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 393     0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
 394   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 395     0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
 396   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 397     0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
 398   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 399     0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
 400   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 401     0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
 402   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 403     0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
 404   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 405     0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
 406   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 407     0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
 408   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 409     0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
 410
 411   /* ARMv8-M Mainline Security Extensions instructions.  */
 412   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 413     0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
 414   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 415     0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
 416
 417   /* Register load/store.  */
 418   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 419     0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
 420   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 421     0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
 422   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 423     0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
 424   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 425     0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
 426   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 427     0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
 428   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 429     0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
 430   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 431     0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
 432   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 433     0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
 434   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 435     0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
 436   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 437     0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
 438   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 439     0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
 440   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 441     0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
 442   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 443     0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
 444   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 445     0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
 446   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 447     0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
 448   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 449     0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
 450
 451   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 452     0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 453   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 454     0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 455   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 456     0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 457   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 458     0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 459
 460   /* Data transfer between ARM and NEON registers.  */
 461   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 462     0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
 463   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 464     0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
 465   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 466     0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
 467   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 468     0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
 469   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 470     0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
 471   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 472     0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
 473   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 474     0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
 475   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 476     0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
 477   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 478     0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
 479   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 480     0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
 481   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 482     0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
 483   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 484     0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
 485   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 486     0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
 487   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 488     0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
 489   /* Half-precision conversion instructions.  */
 490   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 491     0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
 492   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 493     0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
 494   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 495     0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
 496   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 497     0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
 498
 499   /* Floating point coprocessor (VFP) instructions.  */
 500   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 501     0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
 502   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 503     0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
 504   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 505     0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
 506   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 507     0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
 508   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 509     0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
 510   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 511     0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
 512   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 513     0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
 514   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 515     0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
 516   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 517     0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
 518   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 519     0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
 520   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 521     0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
 522   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 523     0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
 524   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 525     0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
 526   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 527     0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
 528   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 529     0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
 530   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 531     0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
 532   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 533     0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
 534   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 535     0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
 536   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 537     0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
 538   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 539     0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
 540   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 541     0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
 542   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 543     0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
 544   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 545     0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
 546   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 547     0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
 548   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 549     0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
 550   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 551     0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
 552   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 553     0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
 554   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 555     0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
 556   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 557     0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
 558   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 559     0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
 560   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 561     0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
 562   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 563     0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
 564   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 565     0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
 566   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 567     0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
 568   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 569     0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
 570   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 571     0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
 572   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 573     0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
 574   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 575     0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
 576   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 577     0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
 578   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 579     0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
 580   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 581     0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
 582   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 583     0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
 584   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 585     0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
 586   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 587     0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
 588   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 589     0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
 590   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 591     0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
 592   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 593     0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
 594   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 595     0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
 596   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 597     0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
 598   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 599     0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
 600   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 601     0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
 602   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 603     0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
 604   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 605     0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
 606   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 607     0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
 608   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 609     0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
 610   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 611     0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
 612   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 613     0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
 614   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 615     0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
 616   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 617     0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
 618   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 619     0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
 620   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 621     0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
 622   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 623     0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
 624   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 625     0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
 626   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 627     0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
 628   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 629     0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
 630   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 631     0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
 632   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 633     0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
 634   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 635     0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
 636   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 637     0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
 638
 639   /* Cirrus coprocessor instructions.  */
 640   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 641     0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 642   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 643     0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 644   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 645     0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 646   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 647     0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 648   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 649     0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 650   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 651     0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 652   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 653     0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 654   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 655     0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 656   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 657     0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 658   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 659     0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 660   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 661     0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 662   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 663     0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 664   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 665     0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 666   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 667     0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 668   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 669     0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 670   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 671     0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 672   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 673     0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
 674   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 675     0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
 676   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 677     0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
 678   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 679     0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
 680   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 681     0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
 682   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 683     0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
 684   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 685     0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
 686   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 687     0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
 688   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 689     0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
 690   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 691     0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
 692   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 693     0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
 694   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 695     0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
 696   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 697     0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
 698   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 699     0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
 700   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 701     0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
 702   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 703     0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
 704   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 705     0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
 706   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 707     0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
 708   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 709     0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
 710   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 711     0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
 712   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 713     0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
 714   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 715     0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
 716   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 717     0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
 718   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 719     0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
 720   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 721     0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
 722   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 723     0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
 724   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 725     0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
 726   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 727     0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
 728   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 729     0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
 730   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 731     0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
 732   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 733     0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
 734   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 735     0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
 736   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 737     0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
 738   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 739     0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
 740   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 741     0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
 742   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 743     0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
 744   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 745     0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
 746   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 747     0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
 748   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 749     0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
 750   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 751     0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
 752   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 753     0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
 754   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 755     0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
 756   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 757     0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
 758   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 759     0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
 760   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 761     0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
 762   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 763     0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
 764   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 765     0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 766   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 767     0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 768   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 769     0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 770   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 771     0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 772   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 773     0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 774   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 775     0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 776   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 777     0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
 778   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 779     0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
 780   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 781     0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
 782   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 783     0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
 784   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 785     0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 786   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 787     0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 788   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 789     0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 790   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 791     0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 792   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 793     0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 794   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 795     0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 796   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 797     0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 798   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 799     0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 800   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 801     0x0e000600, 0x0ff00f10,
 802     "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 803   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 804     0x0e100600, 0x0ff00f10,
 805     "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 806   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 807     0x0e200600, 0x0ff00f10,
 808     "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 809   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 810     0x0e300600, 0x0ff00f10,
 811     "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 812
 813   /* VFP Fused multiply add instructions.  */
 814   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 815     0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
 816   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 817     0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
 818   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 819     0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
 820   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 821     0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
 822   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 823     0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
 824   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 825     0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
 826   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 827     0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
 828   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 829     0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
 830
 831   /* FP v5.  */
 832   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 833     0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
 834   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 835     0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
 836   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 837     0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
 838   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 839     0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
 840   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 841     0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
 842   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 843     0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
 844   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 845     0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
 846   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 847     0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
 848   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 849     0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
 850   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 851     0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
 852   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 853     0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
 854   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 855     0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
 856
 857   /* Generic coprocessor instructions.  */
 858   {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
 859   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
 860     0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
 861   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
 862     0x0c500000, 0x0ff00000,
 863     "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 864   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 865     0x0e000000, 0x0f000010,
 866     "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 867   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 868     0x0e10f010, 0x0f10f010,
 869     "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
 870   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 871     0x0e100010, 0x0f100010,
 872     "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 873   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 874     0x0e000010, 0x0f100010,
 875     "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 876   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 877     0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
 878   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 879     0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
 880
 881   /* V6 coprocessor instructions.  */
 882   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
 883     0xfc500000, 0xfff00000,
 884     "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 885   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
 886     0xfc400000, 0xfff00000,
 887     "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
 888
 889   /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8.  */
 890   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 891     0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
 892   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 893     0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
 894   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 895     0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
 896   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 897     0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
 898   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 899     0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
 900   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 901     0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
 902   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 903     0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
 904   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 905     0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
 906   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 907     0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
 908   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 909     0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
 910
 911   /* Dot Product instructions in the space of coprocessor 13.  */
 912   {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
 913     0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
 914   {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
 915     0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
 916
 917   /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8.  */
 918   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 919     0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
 920   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 921     0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
 922   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 923     0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
 924   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 925     0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
 926   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 927     0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
 928   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 929     0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
 930   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 931     0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
 932   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
 933     0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
 934
 935   /* V5 coprocessor instructions.  */
 936   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 937     0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
 938   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 939     0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
 940   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 941     0xfe000000, 0xff000010,
 942     "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 943   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 944     0xfe000010, 0xff100010,
 945     "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 946   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 947     0xfe100010, 0xff100010,
 948     "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 949
 950   /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
 951      cp_num: bit <11:8> == 0b1001.
 952      cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE.  */
 953   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 954     0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
 955   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 956     0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
 957   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 958     0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
 959   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 960     0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
 961   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 962     0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
 963   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 964     0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
 965   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 966     0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
 967   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 968     0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
 969   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 970     0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
 971   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 972     0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
 973   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 974     0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
 975   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 976     0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
 977   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 978     0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
 979   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 980     0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
 981   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 982     0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
 983   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 984     0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
 985   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 986     0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
 987   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 988     0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
 989   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 990     0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
 991   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 992     0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
 993   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 994     0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
 995   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 996     0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
 997   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 998     0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
 999   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1000     0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1001   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1002     0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1003   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1004     0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1005   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1006     0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1007   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1008     0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1009   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1010     0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1011   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1012     0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1013   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1014     0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1015   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1016     0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1017   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1018     0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1019   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1020     0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1021   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1022     0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1023
1024   /* ARMv8.3 javascript conversion instruction.  */
1025   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1026     0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1027
1028   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1029 };
1030
1031 /* Neon opcode table:  This does not encode the top byte -- that is
1032    checked by the print_insn_neon routine, as it depends on whether we are
1033    doing thumb32 or arm32 disassembly.  */
1034
1035 /* print_insn_neon recognizes the following format control codes:
1036
1037    %%                   %
1038
1039    %c                   print condition code
1040    %u                   print condition code (unconditional in ARM mode,
1041                           UNPREDICTABLE if not AL in Thumb)
1042    %A                   print v{st,ld}[1234] operands
1043    %B                   print v{st,ld}[1234] any one operands
1044    %C                   print v{st,ld}[1234] single->all operands
1045    %D                   print scalar
1046    %E                   print vmov, vmvn, vorr, vbic encoded constant
1047    %F                   print vtbl,vtbx register list
1048
1049    %<bitfield>r         print as an ARM register
1050    %<bitfield>d         print the bitfield in decimal
1051    %<bitfield>e         print the 2^N - bitfield in decimal
1052    %<bitfield>D         print as a NEON D register
1053    %<bitfield>Q         print as a NEON Q register
1054    %<bitfield>R         print as a NEON D or Q register
1055    %<bitfield>Sn        print byte scaled width limited by n
1056    %<bitfield>Tn        print short scaled width limited by n
1057    %<bitfield>Un        print long scaled width limited by n
1058
1059    %<bitfield>'c        print specified char iff bitfield is all ones
1060    %<bitfield>`c        print specified char iff bitfield is all zeroes
1061    %<bitfield>?ab...    select from array of values in big endian order.  */
1062
1063 static const struct opcode32 neon_opcodes[] =
1064 {
1065   /* Extract.  */
1066   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1067     0xf2b00840, 0xffb00850,
1068     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1069   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1070     0xf2b00000, 0xffb00810,
1071     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1072
1073   /* Move data element to all lanes.  */
1074   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1075     0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1076   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1077     0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1078   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1079     0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1080
1081   /* Table lookup.  */
1082   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1083     0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1084   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1085     0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1086
1087   /* Half-precision conversions.  */
1088   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1089     0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1090   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1091     0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1092
1093   /* NEON fused multiply add instructions.  */
1094   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1095     0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1096   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1097     0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1098   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1099     0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1100   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1101     0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1102
1103   /* Two registers, miscellaneous.  */
1104   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1105     0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1106   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1107     0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1108   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1109     0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1110   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1111     0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1112   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1113     0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1114   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1115     0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1116   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1117     0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1118   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1119     0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1120   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1121     0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1122   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1123     0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1124   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1125     0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1126   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1127     0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1128   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1129     0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1130   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1131     0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1132   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1133     0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1134   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1135     0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1136   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1137     0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1138   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1139     0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1140   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1141     0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1142   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1143     0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1144   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1145     0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1146   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1147     0xf3b20300, 0xffb30fd0,
1148     "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1149   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1150     0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1151   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1152     0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1153   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1154     0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1155   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1156     0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1157   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1158     0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1159   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1160     0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1161   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1162     0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1163   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1164     0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1165   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1166     0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1167   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1168     0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1169   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1170     0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1171   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1172     0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1173   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1174     0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1175   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1176     0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1177   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1178     0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1179   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1180     0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1181   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1182     0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1183   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1184     0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1185   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1186     0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1187   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1188     0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1189   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1190     0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1191   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1192     0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1193   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1194     0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1195   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1196     0xf3bb0600, 0xffbf0e10,
1197     "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1198   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1199     0xf3b70600, 0xffbf0e10,
1200     "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1201
1202   /* Three registers of the same length.  */
1203   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1204     0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1205   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1206     0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1207   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1208     0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1209   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1210     0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1211   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1212     0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1213   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1214     0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1215   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1216     0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1217   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1218     0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1219   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1220     0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1221   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1222     0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1223   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1224     0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1225   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1226     0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1227   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1228     0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1229   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1230     0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1231   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1232     0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1233   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1234     0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1235   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1236     0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1237   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1238     0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1239   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1240     0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1241   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1242     0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1243   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1244     0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1245   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1246     0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1247   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1248     0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1249   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1250     0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1251   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1252     0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1253   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1254     0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1255   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1256     0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1257   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1258     0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1259   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1260     0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1261   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1262     0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1263   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1264     0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1265   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1266     0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1267   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1268     0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1269   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1270     0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1271   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1272     0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1273   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1274     0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1275   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1276     0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1277   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1278     0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1279   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1280     0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1281   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1282     0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1283   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1284     0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1285   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1286     0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1287   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1288     0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1289   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1290     0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1291   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1292     0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1293   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1294     0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1295   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1296     0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1297   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1298     0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1299   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1300     0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1301   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1302     0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1303   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1304     0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1305   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1306     0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1307   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1308     0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1309   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1310     0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1311   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1312     0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1313   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1314     0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1315   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1316     0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1317   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1318     0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1319   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1320     0xf2000b00, 0xff800f10,
1321     "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1322   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1323     0xf2000b10, 0xff800f10,
1324     "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1325   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1326     0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1327   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1328     0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1329   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1330     0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1331   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1332     0xf3000b00, 0xff800f10,
1333     "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1334   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1335     0xf2000000, 0xfe800f10,
1336     "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1337   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1338     0xf2000010, 0xfe800f10,
1339     "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1340   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1341     0xf2000100, 0xfe800f10,
1342     "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1343   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1344     0xf2000200, 0xfe800f10,
1345     "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1346   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1347     0xf2000210, 0xfe800f10,
1348     "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1349   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1350     0xf2000300, 0xfe800f10,
1351     "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1352   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1353     0xf2000310, 0xfe800f10,
1354     "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1355   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1356     0xf2000400, 0xfe800f10,
1357     "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1358   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1359     0xf2000410, 0xfe800f10,
1360     "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1361   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1362     0xf2000500, 0xfe800f10,
1363     "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1364   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1365     0xf2000510, 0xfe800f10,
1366     "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1367   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1368     0xf2000600, 0xfe800f10,
1369     "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1370   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1371     0xf2000610, 0xfe800f10,
1372     "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1373   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1374     0xf2000700, 0xfe800f10,
1375     "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1376   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1377     0xf2000710, 0xfe800f10,
1378     "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1379   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1380     0xf2000910, 0xfe800f10,
1381     "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1382   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1383     0xf2000a00, 0xfe800f10,
1384     "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1385   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1386     0xf2000a10, 0xfe800f10,
1387     "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1388   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1389     0xf3000b10, 0xff800f10,
1390     "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1391   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1392     0xf3000c10, 0xff800f10,
1393     "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1394
1395   /* One register and an immediate value.  */
1396   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1397     0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1398   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1399     0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1400   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401     0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1402   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1403     0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1404   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1405     0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1406   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407     0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1408   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1409     0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1410   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411     0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1412   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413     0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1414   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415     0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1416   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1417     0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1418   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419     0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1420   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1421     0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1422
1423   /* Two registers and a shift amount.  */
1424   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1425     0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1426   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427     0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1428   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429     0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1430   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1431     0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1432   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1433     0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1434   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1435     0xf2880950, 0xfeb80fd0,
1436     "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1437   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1438     0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1439   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440     0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1441   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442     0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1443   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1444     0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1445   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1446     0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1447   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448     0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1449   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1450     0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1451   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1452     0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1453   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1454     0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1455   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456     0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1457   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1458     0xf2900950, 0xfeb00fd0,
1459     "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1460   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1461     0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1462   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1463     0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1464   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1465     0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1466   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1467     0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1468   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1469     0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1470   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471     0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1472   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473     0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1474   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475     0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1476   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477     0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1478   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479     0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1480   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481     0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1482   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1483     0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1484   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1485     0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1486   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487     0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1488   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1489     0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1490   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1491     0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1492   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1493     0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1494   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1495     0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1496   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1497     0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1498   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1499     0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1500   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1501     0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1502   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1503     0xf2a00950, 0xfea00fd0,
1504     "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1505   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506     0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1507   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508     0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1509   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510     0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1511   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512     0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1513   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514     0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1515   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516     0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1517   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518     0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1519   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520     0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1521   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1522     0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1523   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1524     0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1525   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1526     0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1527   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1528     0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1529   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530     0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1531   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1532     0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1533   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1534     0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1535   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536     0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1537   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1538     0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1539   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1540     0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1541   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1542     0xf2a00e10, 0xfea00e90,
1543     "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1544   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1545     0xf2a00c10, 0xfea00e90,
1546     "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1547
1548   /* Three registers of different lengths.  */
1549   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1550     0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1551   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552     0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1553   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1554     0xf2800400, 0xff800f50,
1555     "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1556   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1557     0xf2800600, 0xff800f50,
1558     "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1559   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1560     0xf2800900, 0xff800f50,
1561     "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1562   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1563     0xf2800b00, 0xff800f50,
1564     "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1565   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1566     0xf2800d00, 0xff800f50,
1567     "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1568   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1569     0xf3800400, 0xff800f50,
1570     "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1571   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1572     0xf3800600, 0xff800f50,
1573     "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1574   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1575     0xf2800000, 0xfe800f50,
1576     "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1577   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1578     0xf2800100, 0xfe800f50,
1579     "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1580   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1581     0xf2800200, 0xfe800f50,
1582     "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1583   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584     0xf2800300, 0xfe800f50,
1585     "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1586   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1587     0xf2800500, 0xfe800f50,
1588     "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1589   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590     0xf2800700, 0xfe800f50,
1591     "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1592   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1593     0xf2800800, 0xfe800f50,
1594     "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1595   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1596     0xf2800a00, 0xfe800f50,
1597     "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1598   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1599     0xf2800c00, 0xfe800f50,
1600     "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1601
1602   /* Two registers and a scalar.  */
1603   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1604     0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1605   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606     0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1607   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1608     0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1609   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1610     0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1611   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1612     0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1613   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1614     0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1615   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1616     0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1617   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618     0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1619   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1620     0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1621   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1622     0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1623   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1624     0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1625   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626     0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1627   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628     0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1629   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630     0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1631   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1632     0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1633   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1634     0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1635   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1636     0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1637   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638     0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1639   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1640     0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1641   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1642     0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1643   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1644     0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1645   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1646     0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1647   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1648     0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1649   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650     0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1651   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1652     0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1653   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1654     0xf2800240, 0xfe800f50,
1655     "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1656   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1657     0xf2800640, 0xfe800f50,
1658     "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1659   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1660     0xf2800a40, 0xfe800f50,
1661     "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1662   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1663     0xf2800e40, 0xff800f50,
1664    "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1665   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1666     0xf2800f40, 0xff800f50,
1667    "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1668   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1669     0xf3800e40, 0xff800f50,
1670    "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1671   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1672     0xf3800f40, 0xff800f50,
1673    "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1674   },
1675
1676   /* Element and structure load/store.  */
1677   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1678     0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1679   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1680     0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1681   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1682     0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1683   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1684     0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1685   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1686     0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1687   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1688     0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1689   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1690     0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1691   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1692     0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1693   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1694     0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1695   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1696     0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1697   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1698     0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1699   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1700     0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1701   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1702     0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1703   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1704     0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1705   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1706     0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1707   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1708     0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1709   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1710     0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1711   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1712     0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1713   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1714     0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1715
1716   {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1717 };
1718
1719 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb.  All three are partially
1720    ordered: they must be searched linearly from the top to obtain a correct
1721    match.  */
1722
1723 /* print_insn_arm recognizes the following format control codes:
1724
1725    %%                   %
1726
1727    %a                   print address for ldr/str instruction
1728    %s                   print address for ldr/str halfword/signextend instruction
1729    %S                   like %s but allow UNPREDICTABLE addressing
1730    %b                   print branch destination
1731    %c                   print condition code (always bits 28-31)
1732    %m                   print register mask for ldm/stm instruction
1733    %o                   print operand2 (immediate or register + shift)
1734    %p                   print 'p' iff bits 12-15 are 15
1735    %t                   print 't' iff bit 21 set and bit 24 clear
1736    %B                   print arm BLX(1) destination
1737    %C                   print the PSR sub type.
1738    %U                   print barrier type.
1739    %P                   print address for pli instruction.
1740
1741    %<bitfield>r         print as an ARM register
1742    %<bitfield>T         print as an ARM register + 1
1743    %<bitfield>R         as %r but r15 is UNPREDICTABLE
1744    %<bitfield>{r|R}u    as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1745    %<bitfield>{r|R}U    as %{r|R} but if matches the other %U field then is UNPREDICTABLE
1746    %<bitfield>d         print the bitfield in decimal
1747    %<bitfield>W         print the bitfield plus one in decimal
1748    %<bitfield>x         print the bitfield in hex
1749    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
1750
1751    %<bitfield>'c        print specified char iff bitfield is all ones
1752    %<bitfield>`c        print specified char iff bitfield is all zeroes
1753    %<bitfield>?ab...    select from array of values in big endian order
1754
1755    %e                   print arm SMI operand (bits 0..7,8..19).
1756    %E                   print the LSB and WIDTH fields of a BFI or BFC instruction.
1757    %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.
1758    %R                   print the SPSR/CPSR or banked register of an MRS.  */
1759
1760 static const struct opcode32 arm_opcodes[] =
1761 {
1762   /* ARM instructions.  */
1763   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1764     0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1765   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1766     0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1767
1768   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1769     0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1770   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1771     0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1772   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1773     0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1774   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1775     0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1776   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1777     0x00800090, 0x0fa000f0,
1778     "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1779   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1780     0x00a00090, 0x0fa000f0,
1781     "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1782
1783   /* V8.2 RAS extension instructions.  */
1784   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
1785     0xe320f010, 0xffffffff, "esb"},
1786
1787   /* V8 instructions.  */
1788   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1789     0x0320f005, 0x0fffffff, "sevl"},
1790   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1791     0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
1792   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
1793     0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
1794   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1795     0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1796   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1797     0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1798   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1799     0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
1800   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1801     0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
1802   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1803     0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
1804   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1805     0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
1806   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1807     0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
1808   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1809     0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
1810   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1811     0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
1812   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1813     0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
1814   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1815     0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
1816   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1817     0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
1818   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1819     0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
1820   /* CRC32 instructions.  */
1821   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1822     0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1823   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1824     0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1825   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1826     0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1827   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1828     0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1829   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1830     0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1831   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1832     0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
1833
1834   /* Privileged Access Never extension instructions.  */
1835   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1836     0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1837
1838   /* Virtualization Extension instructions.  */
1839   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1840   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
1841
1842   /* Integer Divide Extension instructions.  */
1843   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1844     0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1845   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1846     0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
1847
1848   /* MP Extension instructions.  */
1849   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
1850
1851   /* Speculation Barriers.  */
1852   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
1853   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
1854   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
1855
1856   /* V7 instructions.  */
1857   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1858   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1859   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1860   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1861   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1862   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1863   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
1864    {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1865     0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
1866
1867   /* ARM V6T2 instructions.  */
1868   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1869     0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1870   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1871     0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1872   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1873     0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1874   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1875     0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1876
1877   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1878     0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1879   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1880     0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1881
1882   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
1883     0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
1884   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
1885     0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1886   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1887     0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1888   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1889     0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
1890
1891   /* ARM Security extension instructions.  */
1892   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1893     0x01600070, 0x0ff000f0, "smc%c\t%e"},
1894
1895   /* ARM V6K instructions.  */
1896   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1897     0xf57ff01f, 0xffffffff, "clrex"},
1898   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1899     0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1900   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1901     0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1902   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1903     0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1904   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1905     0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1906   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1907     0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1908   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1909     0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
1910
1911   /* ARMv8.5-A instructions.  */
1912   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
1913
1914   /* ARM V6K NOP hints.  */
1915   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1916     0x0320f001, 0x0fffffff, "yield%c"},
1917   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1918     0x0320f002, 0x0fffffff, "wfe%c"},
1919   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1920     0x0320f003, 0x0fffffff, "wfi%c"},
1921   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1922     0x0320f004, 0x0fffffff, "sev%c"},
1923   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1924     0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
1925
1926   /* ARM V6 instructions.  */
1927   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1928     0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1929   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1930     0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1931   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1932     0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1933   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1934     0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1935   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1936     0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1937   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1938     0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1939   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1940     0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1941   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1942     0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1943   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1944     0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1945   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1946     0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1947   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1948     0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1949   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1950     0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1951   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1952     0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1953   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1954     0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1955   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1956     0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1957   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1958     0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1959   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1960     0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1961   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1962     0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1963   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1964     0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1965   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1966     0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1967   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1968     0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1969   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1970     0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1971   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1972     0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1973   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1974     0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1975   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1976     0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1977   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1978     0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1979   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1980     0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1981   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1982     0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1983   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1984     0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1985   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1986     0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1987   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1988     0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1989   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1990     0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1991   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1992     0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1993   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1994     0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1995   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1996     0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1997   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1998     0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
1999   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2000     0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
2001   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2002     0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
2003   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2004     0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
2005   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2006     0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
2007   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2008     0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
2009   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2010     0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2011   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2012     0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2013   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2014     0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2015   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2016     0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2017   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2018     0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2019   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2020     0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2021   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2022     0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2023   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2024     0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2025   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2026     0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
2027   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2028     0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2029   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2030     0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2031   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2032     0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2033   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2034     0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2035   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2036     0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2037   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2038     0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2039   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2040     0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2041   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2042     0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2043   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2044     0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2045   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2046     0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2047   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2048     0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2049   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2050     0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2051   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2052     0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2053   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2054     0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2055   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2056     0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2057   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2058     0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2059   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2060     0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2061   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2062     0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2063   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2064     0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2065   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2066     0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2067   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2068     0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2069   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2070     0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2071   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2072     0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2073   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2074     0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2075   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2076     0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2077   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2078     0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2079   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2080     0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2081   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2082     0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2083   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2084     0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2085   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2086     0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2087   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2088     0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2089   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2090     0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2091   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2092     0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2093   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2094     0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2095   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2096     0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2097   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2098     0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2099   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2100     0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2101   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2102     0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2103   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2104     0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2105   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2106     0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2107   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2108     0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2109   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2110     0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2111   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2112     0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2113   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2114     0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2115   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2116     0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2117   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2118     0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2119   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2120     0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2121   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2122     0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2123   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2124     0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2125   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2126     0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2127   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2128     0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2129   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2130     0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2131   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2132     0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2133   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2134     0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2135   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2136     0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2137   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2138     0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2139   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2140     0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2141   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2142     0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2143   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2144     0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2145   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2146     0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2147   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2148     0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2149   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2150     0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2151   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2152     0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2153   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2154     0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2155   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2156     0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2157   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2158     0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2159   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2160     0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2161   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2162     0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2163   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2164     0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2165   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2166     0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2167   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2168     0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2169   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2170     0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
2171
2172   /* V5J instruction.  */
2173   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2174     0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
2175
2176   /* V5 Instructions.  */
2177   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2178     0xe1200070, 0xfff000f0,
2179     "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2180   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2181     0xfa000000, 0xfe000000, "blx\t%B"},
2182   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2183     0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2184   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2185     0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2186
2187   /* V5E "El Segundo" Instructions.  */
2188   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2189     0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2190   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2191     0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2192   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2193     0xf450f000, 0xfc70f000, "pld\t%a"},
2194   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2195     0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2196   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2197     0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2198   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2199     0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2200   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2201     0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2202
2203   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2204     0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2205   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2206     0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2207
2208   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2209     0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2210   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2211     0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2212   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2213     0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2214   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2215     0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2216
2217   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2218     0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2219   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2220     0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2221   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2222     0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2223   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2224     0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2225
2226   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2227     0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2228   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2229     0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2230
2231   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2232     0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15R, %0-3R, %16-19R"},
2233   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2234     0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2235   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2236     0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15R, %0-3R, %16-19R"},
2237   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2238     0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
2239
2240   /* ARM Instructions.  */
2241   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2242     0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2243
2244   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2245     0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2246   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2247     0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2248   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2249     0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2250   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2251     0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2252   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2253     0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2254   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2255     0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2256
2257   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2258     0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2259   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2260     0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2261   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2262     0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2263   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2264     0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2265
2266   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2267     0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2268   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2269     0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2270   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2271     0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2272   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2273     0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2274
2275   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2276     0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2277   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2278     0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2279   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2280     0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2281
2282   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2283     0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2284   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2285     0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2286   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2287     0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2288
2289   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2290     0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2291   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2292     0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2293   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2294     0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2295
2296   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2297     0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2298   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2299     0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2300   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2301     0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2302
2303   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2304     0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2305   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2306     0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2307   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2308     0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2309
2310   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2311     0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2312   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2313     0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2314   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2315     0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2316
2317   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2318     0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2319   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2320     0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2321   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2322     0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2323
2324   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2325     0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2326   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2327     0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2328   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2329     0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2330
2331   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2332     0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2333   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2334     0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2335   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2336     0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2337
2338   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2339     0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2340   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2341     0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2342   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2343     0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2344
2345   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2346     0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
2347   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2348     0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
2349   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2350     0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
2351
2352   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2353     0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2354   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2355     0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2356   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2357     0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2358
2359   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2360     0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2361   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2362     0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2363   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2364     0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2365
2366   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2367     0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2368   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2369     0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2370   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2371     0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2372
2373   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2374     0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2375   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2376     0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2377   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2378     0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2379   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2380     0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2381   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2382     0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2383   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2384     0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2385   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2386     0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2387
2388   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2389     0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2390   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2391     0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2392   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2393     0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2394
2395   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2396     0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2397   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2398     0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2399   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2400     0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2401
2402   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2403     0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2404   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2405     0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2406
2407   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2408     0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2409
2410   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2411     0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2412   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2413     0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2414
2415   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2416     0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2417   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2418     0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2419   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2420     0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2421   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2422     0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2423   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2424     0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2425   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2426     0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2427   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2428     0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2429   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2430     0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2431   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2432     0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2433   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2434     0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2435   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2436     0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2437   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2438     0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2439   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2440     0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2441   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2442     0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2443   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2444     0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2445   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2446     0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2447   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2448     0x092d0000, 0x0fff0000, "push%c\t%m"},
2449   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2450     0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2451   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2452     0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2453
2454   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2455     0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2456   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2457     0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2458   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2459     0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2460   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2461     0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2462   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2463     0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2464   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2465     0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2466   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2467     0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2468   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2469     0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2470   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2471     0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2472   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2473     0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2474   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2475     0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2476   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2477     0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2478   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2479     0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2480   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2481     0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2482   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2483     0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2484   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2485     0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2486   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2487     0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2488   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2489     0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2490   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2491     0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2492
2493   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2494     0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2495   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2496     0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
2497
2498   /* The rest.  */
2499   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2500     0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
2501   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2502     0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2503   {ARM_FEATURE_CORE_LOW (0),
2504     0x00000000, 0x00000000, 0}
2505 };
2506
2507 /* print_insn_thumb16 recognizes the following format control codes:
2508
2509    %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
2510    %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
2511    %<bitfield>I         print bitfield as a signed decimal
2512                                 (top bit of range being the sign bit)
2513    %N                   print Thumb register mask (with LR)
2514    %O                   print Thumb register mask (with PC)
2515    %M                   print Thumb register mask
2516    %b                   print CZB's 6-bit unsigned branch destination
2517    %s                   print Thumb right-shift immediate (6..10; 0 == 32).
2518    %c                   print the condition code
2519    %C                   print the condition code, or "s" if not conditional
2520    %x                   print warning if conditional an not at end of IT block"
2521    %X                   print "\t; unpredictable <IT:code>" if conditional
2522    %I                   print IT instruction suffix and operands
2523    %W                   print Thumb Writeback indicator for LDMIA
2524    %<bitfield>r         print bitfield as an ARM register
2525    %<bitfield>d         print bitfield as a decimal
2526    %<bitfield>H         print (bitfield * 2) as a decimal
2527    %<bitfield>W         print (bitfield * 4) as a decimal
2528    %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
2529    %<bitfield>B         print Thumb branch destination (signed displacement)
2530    %<bitfield>c         print bitfield as a condition code
2531    %<bitnum>'c          print specified char iff bit is one
2532    %<bitnum>?ab         print a if bit is one else print b.  */
2533
2534 static const struct opcode16 thumb_opcodes[] =
2535 {
2536   /* Thumb instructions.  */
2537
2538   /* ARMv8-M Security Extensions instructions.  */
2539   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
2540   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
2541
2542   /* ARM V8 instructions.  */
2543   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xbf50, 0xffff, "sevl%c"},
2544   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xba80, 0xffc0, "hlt\t%0-5x"},
2545   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),  0xb610, 0xfff7, "setpan\t#%3-3d"},
2546
2547   /* ARM V6K no-argument instructions.  */
2548   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2549   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2550   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2551   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2552   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2553   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
2554
2555   /* ARM V6T2 instructions.  */
2556   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2557     0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2558   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2559     0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
2560   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
2561
2562   /* ARM V6.  */
2563   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2564   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2565   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2566   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2567   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2568   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2569   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2570   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2571   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2572   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2573   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
2574
2575   /* ARM V5 ISA extends Thumb.  */
2576   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2577     0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
2578   /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
2579   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2580     0x4780, 0xff87, "blx%c\t%3-6r%x"},  /* note: 4 bit register number.  */
2581   /* ARM V4T ISA (Thumb v1).  */
2582   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2583     0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
2584   /* Format 4.  */
2585   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2586   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2587   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2588   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2589   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2590   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2591   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2592   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2593   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2594   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2595   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2596   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2597   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2598   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2599   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2600   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
2601   /* format 13 */
2602   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2603   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
2604   /* format 5 */
2605   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2606   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2607   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2608   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
2609   /* format 14 */
2610   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2611   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
2612   /* format 2 */
2613   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2614     0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2615   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2616     0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2617   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2618     0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2619   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2620     0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
2621   /* format 8 */
2622   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2623     0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2624   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2625     0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2626   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2627     0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
2628   /* format 7 */
2629   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2630     0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2631   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2632     0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2633   /* format 1 */
2634   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2635   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2636     0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2637   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2638   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
2639   /* format 3 */
2640   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2641   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2642   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2643   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
2644   /* format 6 */
2645   /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2646   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2647     0x4800, 0xF800,
2648     "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
2649   /* format 9 */
2650   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2651     0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2652   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2653     0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2654   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2655     0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2656   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2657     0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
2658   /* format 10 */
2659   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2660     0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2661   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2662     0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
2663   /* format 11 */
2664   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2665     0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2666   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2667     0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
2668   /* format 12 */
2669   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2670     0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2671   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2672     0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
2673   /* format 15 */
2674   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2675   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
2676   /* format 17 */
2677   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
2678   /* format 16 */
2679   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2680   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2681   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
2682   /* format 18 */
2683   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
2684
2685   /* The E800 .. FFFF range is unconditionally redirected to the
2686      32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2687      are processed via that table.  Thus, we can never encounter a
2688      bare "second half of BL/BLX(1)" instruction here.  */
2689   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),  0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2690   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2691 };
2692
2693 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
2694    We adopt the convention that hw1 is the high 16 bits of .value and
2695    .mask, hw2 the low 16 bits.
2696
2697    print_insn_thumb32 recognizes the following format control codes:
2698
2699        %%               %
2700
2701        %I               print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2702        %M               print a modified 12-bit immediate (same location)
2703        %J               print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2704        %K               print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
2705        %H               print a 16-bit immediate from hw2[3:0],hw1[11:0]
2706        %S               print a possibly-shifted Rm
2707
2708        %L               print address for a ldrd/strd instruction
2709        %a               print the address of a plain load/store
2710        %w               print the width and signedness of a core load/store
2711        %m               print register mask for ldm/stm
2712
2713        %E               print the lsb and width fields of a bfc/bfi instruction
2714        %F               print the lsb and width fields of a sbfx/ubfx instruction
2715        %b               print a conditional branch offset
2716        %B               print an unconditional branch offset
2717        %s               print the shift field of an SSAT instruction
2718        %R               print the rotation field of an SXT instruction
2719        %U               print barrier type.
2720        %P               print address for pli instruction.
2721        %c               print the condition code
2722        %x               print warning if conditional an not at end of IT block"
2723        %X               print "\t; unpredictable <IT:code>" if conditional
2724
2725        %<bitfield>d     print bitfield in decimal
2726        %<bitfield>D     print bitfield plus one in decimal
2727        %<bitfield>W     print bitfield*4 in decimal
2728        %<bitfield>r     print bitfield as an ARM register
2729        %<bitfield>R     as %<>r but r15 is UNPREDICTABLE
2730        %<bitfield>c     print bitfield as a condition code
2731
2732        %<bitfield>'c    print specified char iff bitfield is all ones
2733        %<bitfield>`c    print specified char iff bitfield is all zeroes
2734        %<bitfield>?ab... select from array of values in big endian order
2735
2736    With one exception at the bottom (done because BL and BLX(1) need
2737    to come dead last), this table was machine-sorted first in
2738    decreasing order of number of bits set in the mask, then in
2739    increasing numeric order of mask, then in increasing numeric order
2740    of opcode.  This order is not the clearest for a human reader, but
2741    is guaranteed never to catch a special-case bit pattern with a more
2742    general mask, which is important, because this instruction encoding
2743    makes heavy use of special-case bit patterns.  */
2744 static const struct opcode32 thumb32_opcodes[] =
2745 {
2746   /* ARMv8-M and ARMv8-M Security Extensions instructions.  */
2747   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
2748   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2749     0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2750   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2751     0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
2752   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2753     0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
2754   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2755     0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
2756
2757   /* ARM V8.2 RAS extension instructions.  */
2758   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
2759     0xf3af8010, 0xffffffff, "esb"},
2760
2761   /* V8 instructions.  */
2762   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2763     0xf3af8005, 0xffffffff, "sevl%c.w"},
2764   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2765     0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2766   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2767     0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2768   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2769     0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2770   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2771     0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2772   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2773     0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2774   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2775     0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2776   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2777     0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2778   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2779     0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2780   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2781     0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2782   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2783     0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2784   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2785     0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2786   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2787     0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2788   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2789     0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2790   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2791     0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2792   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2793     0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
2794
2795   /* CRC32 instructions.  */
2796   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2797     0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
2798   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2799     0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
2800   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2801     0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
2802   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2803     0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
2804   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2805     0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
2806   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2807     0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
2808
2809   /* Speculation Barriers.  */
2810   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
2811   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
2812   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
2813
2814   /* V7 instructions.  */
2815   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2816   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2817   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2818   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2819   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2820   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2821   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2822   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2823     0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2824   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2825     0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
2826
2827   /* Virtualization Extension instructions.  */
2828   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
2829   /* We skip ERET as that is SUBS pc, lr, #0.  */
2830
2831   /* MP Extension instructions.  */
2832   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP),   0xf830f000, 0xff70f000, "pldw%c\t%a"},
2833
2834   /* Security extension instructions.  */
2835   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
2836
2837   /* ARMv8.5-A instructions.  */
2838   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
2839
2840   /* Instructions defined in the basic V6T2 set.  */
2841   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2842   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2843   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2844   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2845   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2846   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2847     0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2848   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2849
2850   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2851     0xf3bf8f2f, 0xffffffff, "clrex%c"},
2852   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2853     0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2854   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2855     0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2856   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2857     0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2858   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2859     0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2860   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2861     0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2862   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2863     0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2864   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2865     0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2866   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2867     0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2868   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2869     0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2870   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2871     0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2872   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2873     0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2874   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2875     0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2876   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2877     0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
2878   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2879     0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
2880   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2881     0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2882   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2883     0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2884   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2885     0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2886   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2887     0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2888   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2889     0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2890   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2891     0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2892   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2893     0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2894   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2895     0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2896   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2897     0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
2898   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2899     0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2900   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2901     0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2902   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2903     0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2904   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2905     0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2906   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2907     0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2908   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2909     0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2910   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2911     0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2912   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2913     0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2914   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2915     0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2916   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2917     0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2918   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2919     0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2920   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2921     0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2922   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2923     0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2924   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2925     0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2926   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2927     0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2928   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2929     0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2930   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2931     0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2932   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2933     0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2934   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2935     0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2936   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2937     0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2938   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2939     0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2940   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2941     0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2942   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2943     0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2944   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2945     0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2946   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2947     0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2948   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2949     0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2950   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2951     0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2952   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2953     0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2954   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2955     0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2956   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2957     0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2958   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2959     0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2960   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2961     0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2962   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2963     0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2964   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2965     0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2966   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2967     0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2968   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2969     0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2970   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2971     0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2972   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2973     0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2974   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2975     0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2976   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2977     0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2978   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2979     0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2980   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2981     0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2982   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2983     0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2984   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2985     0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2986   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2987     0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2988   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2989     0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2990   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2991     0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
2992   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2993     0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
2994   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2995     0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
2996   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2997     0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
2998   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2999     0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3000   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3001     0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3002   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3003     0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3004   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3005     0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
3006   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3007     0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
3008   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3009     0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
3010   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3011     0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
3012   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3013     0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
3014   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3015     0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3016   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3017     0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
3018   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3019     0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
3020   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3021     0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3022   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3023     0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3024   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3025     0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3026   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3027     0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3028   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3029     0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3030   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3031     0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3032   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3033     0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3034   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3035     0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
3036   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3037     0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
3038   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3039     0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3040   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3041     0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3042   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3043     0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3044   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3045     0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3046   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3047     0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3048   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3049     0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3050   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3051     0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3052   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3053     0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3054   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3055     0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3056   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3057     0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3058   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3059     0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3060   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3061     0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3062   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3063     0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3064   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3065     0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3066   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3067     0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3068   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3069     0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3070   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3071     0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3072   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3073     0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3074   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3075     0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3076   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3077     0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3078   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3079     0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3080   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3081     0xf810f000, 0xff70f000, "pld%c\t%a"},
3082   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3083     0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3084   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3085     0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3086   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3087     0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3088   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3089     0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3090   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3091     0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3092   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3093     0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3094   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3095     0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3096   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3097     0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3098   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3099     0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3100   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3101     0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3102   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3103     0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3104   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3105     0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3106   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3107     0xfb100000, 0xfff000c0,
3108     "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3109   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3110     0xfbc00080, 0xfff000c0,
3111     "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3112   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3113     0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3114   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3115     0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3116   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3117     0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
3118   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3119     0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3120   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3121     0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
3122   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3123     0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3124   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3125     0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
3126   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3127     0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3128   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3129     0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3130   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3131     0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3132   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3133     0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3134   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3135     0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3136   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3137     0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3138   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3139     0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3140   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3141     0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3142   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3143     0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3144   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3145     0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3146   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3147     0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
3148   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3149     0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3150   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3151     0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3152   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3153     0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3154   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3155     0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3156   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3157     0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3158   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3159     0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3160   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3161     0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3162   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3163     0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3164   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3165     0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3166   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3167     0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3168   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3169     0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3170   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3171     0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3172   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3173     0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3174   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3175     0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3176   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3177     0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3178   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3179     0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3180   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3181     0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3182   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3183     0xe9400000, 0xff500000,
3184     "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3185   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3186     0xe9500000, 0xff500000,
3187     "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3188   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3189     0xe8600000, 0xff700000,
3190     "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3191   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3192     0xe8700000, 0xff700000,
3193     "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3194   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3195     0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3196   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3197     0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
3198
3199   /* Filter out Bcc with cond=E or F, which are used for other instructions.  */
3200   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3201     0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3202   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3203     0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3204   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3205     0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3206   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3207     0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
3208
3209   /* These have been 32-bit since the invention of Thumb.  */
3210   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3211      0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3212   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3213      0xf000d000, 0xf800d000, "bl%c\t%B%x"},
3214
3215   /* Fallback.  */
3216   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3217       0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3218   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3219 };
3220
3221 static const char *const arm_conditional[] =
3222 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
3223  "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
3224
3225 static const char *const arm_fp_const[] =
3226 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3227
3228 static const char *const arm_shift[] =
3229 {"lsl", "lsr", "asr", "ror"};
3230
3231 typedef struct
3232 {
3233   const char *name;
3234   const char *description;
3235   const char *reg_names[16];
3236 }
3237 arm_regname;
3238
3239 static const arm_regname regnames[] =
3240 {
3241   { "reg-names-raw", N_("Select raw register names"),
3242     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3243   { "reg-names-gcc", N_("Select register names used by GCC"),
3244     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
3245   { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
3246     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp",  "lr",  "pc" }},
3247   { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
3248   { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
3249   { "reg-names-apcs", N_("Select register names used in the APCS"),
3250     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
3251   { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
3252     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7",  "v8",  "IP",  "SP",  "LR",  "PC" }},
3253   { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3254     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }}
3255 };
3256
3257 static const char *const iwmmxt_wwnames[] =
3258 {"b", "h", "w", "d"};
3259
3260 static const char *const iwmmxt_wwssnames[] =
3261 {"b", "bus", "bc", "bss",
3262  "h", "hus", "hc", "hss",
3263  "w", "wus", "wc", "wss",
3264  "d", "dus", "dc", "dss"
3265 };
3266
3267 static const char *const iwmmxt_regnames[] =
3268 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3269   "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3270 };
3271
3272 static const char *const iwmmxt_cregnames[] =
3273 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3274   "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3275 };
3276
3277 /* Default to GCC register name set.  */
3278 static unsigned int regname_selected = 1;
3279
3280 #define NUM_ARM_OPTIONS   ARRAY_SIZE (regnames)
3281 #define arm_regnames      regnames[regname_selected].reg_names
3282
3283 static bfd_boolean force_thumb = FALSE;
3284
3285 /* Current IT instruction state.  This contains the same state as the IT
3286    bits in the CPSR.  */
3287 static unsigned int ifthen_state;
3288 /* IT state for the next instruction.  */
3289 static unsigned int ifthen_next_state;
3290 /* The address of the insn for which the IT state is valid.  */
3291 static bfd_vma ifthen_address;
3292 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
3293 /* Indicates that the current Conditional state is unconditional or outside
3294    an IT block.  */
3295 #define COND_UNCOND 16
3296
3297 \f
3298 /* Functions.  */
3299
3300 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3301    Returns pointer to following character of the format string and
3302    fills in *VALUEP and *WIDTHP with the extracted value and number of
3303    bits extracted.  WIDTHP can be NULL.  */
3304
3305 static const char *
3306 arm_decode_bitfield (const char *ptr,
3307                      unsigned long insn,
3308                      unsigned long *valuep,
3309                      int *widthp)
3310 {
3311   unsigned long value = 0;
3312   int width = 0;
3313
3314   do
3315     {
3316       int start, end;
3317       int bits;
3318
3319       for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3320         start = start * 10 + *ptr - '0';
3321       if (*ptr == '-')
3322         for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3323           end = end * 10 + *ptr - '0';
3324       else
3325         end = start;
3326       bits = end - start;
3327       if (bits < 0)
3328         abort ();
3329       value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3330       width += bits + 1;
3331     }
3332   while (*ptr++ == ',');
3333   *valuep = value;
3334   if (widthp)
3335     *widthp = width;
3336   return ptr - 1;
3337 }
3338
3339 static void
3340 arm_decode_shift (long given, fprintf_ftype func, void *stream,
3341                   bfd_boolean print_shift)
3342 {
3343   func (stream, "%s", arm_regnames[given & 0xf]);
3344
3345   if ((given & 0xff0) != 0)
3346     {
3347       if ((given & 0x10) == 0)
3348         {
3349           int amount = (given & 0xf80) >> 7;
3350           int shift = (given & 0x60) >> 5;
3351
3352           if (amount == 0)
3353             {
3354               if (shift == 3)
3355                 {
3356                   func (stream, ", rrx");
3357                   return;
3358                 }
3359
3360               amount = 32;
3361             }
3362
3363           if (print_shift)
3364             func (stream, ", %s #%d", arm_shift[shift], amount);
3365           else
3366             func (stream, ", #%d", amount);
3367         }
3368       else if ((given & 0x80) == 0x80)
3369         func (stream, "\t; <illegal shifter operand>");
3370       else if (print_shift)
3371         func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3372               arm_regnames[(given & 0xf00) >> 8]);
3373       else
3374         func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
3375     }
3376 }
3377
3378 #define W_BIT 21
3379 #define I_BIT 22
3380 #define U_BIT 23
3381 #define P_BIT 24
3382
3383 #define WRITEBACK_BIT_SET   (given & (1 << W_BIT))
3384 #define IMMEDIATE_BIT_SET   (given & (1 << I_BIT))
3385 #define NEGATIVE_BIT_SET   ((given & (1 << U_BIT)) == 0)
3386 #define PRE_BIT_SET         (given & (1 << P_BIT))
3387
3388 /* Print one coprocessor instruction on INFO->STREAM.
3389    Return TRUE if the instuction matched, FALSE if this is not a
3390    recognised coprocessor instruction.  */
3391
3392 static bfd_boolean
3393 print_insn_coprocessor (bfd_vma pc,
3394                         struct disassemble_info *info,
3395                         long given,
3396                         bfd_boolean thumb)
3397 {
3398   const struct opcode32 *insn;
3399   void *stream = info->stream;
3400   fprintf_ftype func = info->fprintf_func;
3401   unsigned long mask;
3402   unsigned long value = 0;
3403   int cond;
3404   int cp_num;
3405   struct arm_private_data *private_data = info->private_data;
3406   arm_feature_set allowed_arches = ARM_ARCH_NONE;
3407
3408   allowed_arches = private_data->features;
3409
3410   for (insn = coprocessor_opcodes; insn->assembler; insn++)
3411     {
3412       unsigned long u_reg = 16;
3413       bfd_boolean is_unpredictable = FALSE;
3414       signed long value_in_comment = 0;
3415       const char *c;
3416
3417       if (ARM_FEATURE_ZERO (insn->arch))
3418         switch (insn->value)
3419           {
3420           case SENTINEL_IWMMXT_START:
3421             if (info->mach != bfd_mach_arm_XScale
3422                 && info->mach != bfd_mach_arm_iWMMXt
3423                 && info->mach != bfd_mach_arm_iWMMXt2)
3424               do
3425                 insn++;
3426               while ((! ARM_FEATURE_ZERO (insn->arch))
3427                      && insn->value != SENTINEL_IWMMXT_END);
3428             continue;
3429
3430           case SENTINEL_IWMMXT_END:
3431             continue;
3432
3433           case SENTINEL_GENERIC_START:
3434             allowed_arches = private_data->features;
3435             continue;
3436
3437           default:
3438             abort ();
3439           }
3440
3441       mask = insn->mask;
3442       value = insn->value;
3443       cp_num = (given >> 8) & 0xf;
3444
3445       if (thumb)
3446         {
3447           /* The high 4 bits are 0xe for Arm conditional instructions, and
3448              0xe for arm unconditional instructions.  The rest of the
3449              encoding is the same.  */
3450           mask |= 0xf0000000;
3451           value |= 0xe0000000;
3452           if (ifthen_state)
3453             cond = IFTHEN_COND;
3454           else
3455             cond = COND_UNCOND;
3456         }
3457       else
3458         {
3459           /* Only match unconditional instuctions against unconditional
3460              patterns.  */
3461           if ((given & 0xf0000000) == 0xf0000000)
3462             {
3463               mask |= 0xf0000000;
3464               cond = COND_UNCOND;
3465             }
3466           else
3467             {
3468               cond = (given >> 28) & 0xf;
3469               if (cond == 0xe)
3470                 cond = COND_UNCOND;
3471             }
3472         }
3473
3474       if ((given & mask) != value)
3475         continue;
3476
3477       if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
3478         continue;
3479
3480       if (insn->value == 0xfe000010     /* mcr2  */
3481           || insn->value == 0xfe100010  /* mrc2  */
3482           || insn->value == 0xfc100000  /* ldc2  */
3483           || insn->value == 0xfc000000) /* stc2  */
3484         {
3485           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
3486             is_unpredictable = TRUE;
3487         }
3488       else if (insn->value == 0x0e000000     /* cdp  */
3489                || insn->value == 0xfe000000  /* cdp2  */
3490                || insn->value == 0x0e000010  /* mcr  */
3491                || insn->value == 0x0e100010  /* mrc  */
3492                || insn->value == 0x0c100000  /* ldc  */
3493                || insn->value == 0x0c000000) /* stc  */
3494         {
3495           /* Floating-point instructions.  */
3496           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
3497             continue;
3498         }
3499
3500       for (c = insn->assembler; *c; c++)
3501         {
3502           if (*c == '%')
3503             {
3504               switch (*++c)
3505                 {
3506                 case '%':
3507                   func (stream, "%%");
3508                   break;
3509
3510                 case 'A':
3511                   {
3512                     int rn = (given >> 16) & 0xf;
3513                     bfd_vma offset = given & 0xff;
3514
3515                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3516
3517                     if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3518                       {
3519                         /* Not unindexed.  The offset is scaled.  */
3520                         if (cp_num == 9)
3521                           /* vldr.16/vstr.16 will shift the address
3522                              left by 1 bit only.  */
3523                           offset = offset * 2;
3524                         else
3525                           offset = offset * 4;
3526
3527                         if (NEGATIVE_BIT_SET)
3528                           offset = - offset;
3529                         if (rn != 15)
3530                           value_in_comment = offset;
3531                       }
3532
3533                     if (PRE_BIT_SET)
3534                       {
3535                         if (offset)
3536                           func (stream, ", #%d]%s",
3537                                 (int) offset,
3538                                 WRITEBACK_BIT_SET ? "!" : "");
3539                         else if (NEGATIVE_BIT_SET)
3540                           func (stream, ", #-0]");
3541                         else
3542                           func (stream, "]");
3543                       }
3544                     else
3545                       {
3546                         func (stream, "]");
3547
3548                         if (WRITEBACK_BIT_SET)
3549                           {
3550                             if (offset)
3551                               func (stream, ", #%d", (int) offset);
3552                             else if (NEGATIVE_BIT_SET)
3553                               func (stream, ", #-0");
3554                           }
3555                         else
3556                           {
3557                             func (stream, ", {%s%d}",
3558                                   (NEGATIVE_BIT_SET && !offset) ? "-" : "",
3559                                   (int) offset);
3560                             value_in_comment = offset;
3561                           }
3562                       }
3563                     if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3564                       {
3565                         func (stream, "\t; ");
3566                         /* For unaligned PCs, apply off-by-alignment
3567                            correction.  */
3568                         info->print_address_func (offset + pc
3569                                                   + info->bytes_per_chunk * 2
3570                                                   - (pc & 3),
3571                                                   info);
3572                       }
3573                   }
3574                   break;
3575
3576                 case 'B':
3577                   {
3578                     int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3579                     int offset = (given >> 1) & 0x3f;
3580
3581                     if (offset == 1)
3582                       func (stream, "{d%d}", regno);
3583                     else if (regno + offset > 32)
3584                       func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3585                     else
3586                       func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3587                   }
3588                   break;
3589
3590                 case 'u':
3591                   if (cond != COND_UNCOND)
3592                     is_unpredictable = TRUE;
3593
3594                   /* Fall through.  */
3595                 case 'c':
3596                   if (cond != COND_UNCOND && cp_num == 9)
3597                     is_unpredictable = TRUE;
3598
3599                   func (stream, "%s", arm_conditional[cond]);
3600                   break;
3601
3602                 case 'I':
3603                   /* Print a Cirrus/DSP shift immediate.  */
3604                   /* Immediates are 7bit signed ints with bits 0..3 in
3605                      bits 0..3 of opcode and bits 4..6 in bits 5..7
3606                      of opcode.  */
3607                   {
3608                     int imm;
3609
3610                     imm = (given & 0xf) | ((given & 0xe0) >> 1);
3611
3612                     /* Is ``imm'' a negative number?  */
3613                     if (imm & 0x40)
3614                       imm -= 0x80;
3615
3616                     func (stream, "%d", imm);
3617                   }
3618
3619                   break;
3620
3621                 case 'F':
3622                   switch (given & 0x00408000)
3623                     {
3624                     case 0:
3625                       func (stream, "4");
3626                       break;
3627                     case 0x8000:
3628                       func (stream, "1");
3629                       break;
3630                     case 0x00400000:
3631                       func (stream, "2");
3632                       break;
3633                     default:
3634                       func (stream, "3");
3635                     }
3636                   break;
3637
3638                 case 'P':
3639                   switch (given & 0x00080080)
3640                     {
3641                     case 0:
3642                       func (stream, "s");
3643                       break;
3644                     case 0x80:
3645                       func (stream, "d");
3646                       break;
3647                     case 0x00080000:
3648                       func (stream, "e");
3649                       break;
3650                     default:
3651                       func (stream, _("<illegal precision>"));
3652                       break;
3653                     }
3654                   break;
3655
3656                 case 'Q':
3657                   switch (given & 0x00408000)
3658                     {
3659                     case 0:
3660                       func (stream, "s");
3661                       break;
3662                     case 0x8000:
3663                       func (stream, "d");
3664                       break;
3665                     case 0x00400000:
3666                       func (stream, "e");
3667                       break;
3668                     default:
3669                       func (stream, "p");
3670                       break;
3671                     }
3672                   break;
3673
3674                 case 'R':
3675                   switch (given & 0x60)
3676                     {
3677                     case 0:
3678                       break;
3679                     case 0x20:
3680                       func (stream, "p");
3681                       break;
3682                     case 0x40:
3683                       func (stream, "m");
3684                       break;
3685                     default:
3686                       func (stream, "z");
3687                       break;
3688                     }
3689                   break;
3690
3691                 case '0': case '1': case '2': case '3': case '4':
3692                 case '5': case '6': case '7': case '8': case '9':
3693                   {
3694                     int width;
3695
3696                     c = arm_decode_bitfield (c, given, &value, &width);
3697
3698                     switch (*c)
3699                       {
3700                       case 'R':
3701                         if (value == 15)
3702                           is_unpredictable = TRUE;
3703                         /* Fall through.  */
3704                       case 'r':
3705                         if (c[1] == 'u')
3706                           {
3707                             /* Eat the 'u' character.  */
3708                             ++ c;
3709
3710                             if (u_reg == value)
3711                               is_unpredictable = TRUE;
3712                             u_reg = value;
3713                           }
3714                         func (stream, "%s", arm_regnames[value]);
3715                         break;
3716                       case 'V':
3717                         if (given & (1 << 6))
3718                           goto Q;
3719                         /* FALLTHROUGH */
3720                       case 'D':
3721                         func (stream, "d%ld", value);
3722                         break;
3723                       case 'Q':
3724                       Q:
3725                         if (value & 1)
3726                           func (stream, "<illegal reg q%ld.5>", value >> 1);
3727                         else
3728                           func (stream, "q%ld", value >> 1);
3729                         break;
3730                       case 'd':
3731                         func (stream, "%ld", value);
3732                         value_in_comment = value;
3733                         break;
3734                       case 'E':
3735                         {
3736                           /* Converts immediate 8 bit back to float value.  */
3737                           unsigned floatVal = (value & 0x80) << 24
3738                             | (value & 0x3F) << 19
3739                             | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3740
3741                           /* Quarter float have a maximum value of 31.0.
3742                              Get floating point value multiplied by 1e7.
3743                              The maximum value stays in limit of a 32-bit int.  */
3744                           unsigned decVal =
3745                             (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3746                             (16 + (value & 0xF));
3747
3748                           if (!(decVal % 1000000))
3749                             func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3750                                   floatVal, value & 0x80 ? '-' : ' ',
3751                                   decVal / 10000000,
3752                                   decVal % 10000000 / 1000000);
3753                           else if (!(decVal % 10000))
3754                             func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3755                                   floatVal, value & 0x80 ? '-' : ' ',
3756                                   decVal / 10000000,
3757                                   decVal % 10000000 / 10000);
3758                           else
3759                             func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3760                                   floatVal, value & 0x80 ? '-' : ' ',
3761                                   decVal / 10000000, decVal % 10000000);
3762                           break;
3763                         }
3764                       case 'k':
3765                         {
3766                           int from = (given & (1 << 7)) ? 32 : 16;
3767                           func (stream, "%ld", from - value);
3768                         }
3769                         break;
3770
3771                       case 'f':
3772                         if (value > 7)
3773                           func (stream, "#%s", arm_fp_const[value & 7]);
3774                         else
3775                           func (stream, "f%ld", value);
3776                         break;
3777
3778                       case 'w':
3779                         if (width == 2)
3780                           func (stream, "%s", iwmmxt_wwnames[value]);
3781                         else
3782                           func (stream, "%s", iwmmxt_wwssnames[value]);
3783                         break;
3784
3785                       case 'g':
3786                         func (stream, "%s", iwmmxt_regnames[value]);
3787                         break;
3788                       case 'G':
3789                         func (stream, "%s", iwmmxt_cregnames[value]);
3790                         break;
3791
3792                       case 'x':
3793                         func (stream, "0x%lx", (value & 0xffffffffUL));
3794                         break;
3795
3796                       case 'c':
3797                         switch (value)
3798                           {
3799                           case 0:
3800                             func (stream, "eq");
3801                             break;
3802
3803                           case 1:
3804                             func (stream, "vs");
3805                             break;
3806
3807                           case 2:
3808                             func (stream, "ge");
3809                             break;
3810
3811                           case 3:
3812                             func (stream, "gt");
3813                             break;
3814
3815                           default:
3816                             func (stream, "??");
3817                             break;
3818                           }
3819                         break;
3820
3821                       case '`':
3822                         c++;
3823                         if (value == 0)
3824                           func (stream, "%c", *c);
3825                         break;
3826                       case '\'':
3827                         c++;
3828                         if (value == ((1ul << width) - 1))
3829                           func (stream, "%c", *c);
3830                         break;
3831                       case '?':
3832                         func (stream, "%c", c[(1 << width) - (int) value]);
3833                         c += 1 << width;
3834                         break;
3835                       default:
3836                         abort ();
3837                       }
3838                     break;
3839
3840                   case 'y':
3841                   case 'z':
3842                     {
3843                       int single = *c++ == 'y';
3844                       int regno;
3845
3846                       switch (*c)
3847                         {
3848                         case '4': /* Sm pair */
3849                         case '0': /* Sm, Dm */
3850                           regno = given & 0x0000000f;
3851                           if (single)
3852                             {
3853                               regno <<= 1;
3854                               regno += (given >> 5) & 1;
3855                             }
3856                           else
3857                             regno += ((given >> 5) & 1) << 4;
3858                           break;
3859
3860                         case '1': /* Sd, Dd */
3861                           regno = (given >> 12) & 0x0000000f;
3862                           if (single)
3863                             {
3864                               regno <<= 1;
3865                               regno += (given >> 22) & 1;
3866                             }
3867                           else
3868                             regno += ((given >> 22) & 1) << 4;
3869                           break;
3870
3871                         case '2': /* Sn, Dn */
3872                           regno = (given >> 16) & 0x0000000f;
3873                           if (single)
3874                             {
3875                               regno <<= 1;
3876                               regno += (given >> 7) & 1;
3877                             }
3878                           else
3879                             regno += ((given >> 7) & 1) << 4;
3880                           break;
3881
3882                         case '3': /* List */
3883                           func (stream, "{");
3884                           regno = (given >> 12) & 0x0000000f;
3885                           if (single)
3886                             {
3887                               regno <<= 1;
3888                               regno += (given >> 22) & 1;
3889                             }
3890                           else
3891                             regno += ((given >> 22) & 1) << 4;
3892                           break;
3893
3894                         default:
3895                           abort ();
3896                         }
3897
3898                       func (stream, "%c%d", single ? 's' : 'd', regno);
3899
3900                       if (*c == '3')
3901                         {
3902                           int count = given & 0xff;
3903
3904                           if (single == 0)
3905                             count >>= 1;
3906
3907                           if (--count)
3908                             {
3909                               func (stream, "-%c%d",
3910                                     single ? 's' : 'd',
3911                                     regno + count);
3912                             }
3913
3914                           func (stream, "}");
3915                         }
3916                       else if (*c == '4')
3917                         func (stream, ", %c%d", single ? 's' : 'd',
3918                               regno + 1);
3919                     }
3920                     break;
3921
3922                   case 'L':
3923                     switch (given & 0x00400100)
3924                       {
3925                       case 0x00000000: func (stream, "b"); break;
3926                       case 0x00400000: func (stream, "h"); break;
3927                       case 0x00000100: func (stream, "w"); break;
3928                       case 0x00400100: func (stream, "d"); break;
3929                       default:
3930                         break;
3931                       }
3932                     break;
3933
3934                   case 'Z':
3935                     {
3936                       /* given (20, 23) | given (0, 3) */
3937                       value = ((given >> 16) & 0xf0) | (given & 0xf);
3938                       func (stream, "%d", (int) value);
3939                     }
3940                     break;
3941
3942                   case 'l':
3943                     /* This is like the 'A' operator, except that if
3944                        the width field "M" is zero, then the offset is
3945                        *not* multiplied by four.  */
3946                     {
3947                       int offset = given & 0xff;
3948                       int multiplier = (given & 0x00000100) ? 4 : 1;
3949
3950                       func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3951
3952                       if (multiplier > 1)
3953                         {
3954                           value_in_comment = offset * multiplier;
3955                           if (NEGATIVE_BIT_SET)
3956                             value_in_comment = - value_in_comment;
3957                         }
3958
3959                       if (offset)
3960                         {
3961                           if (PRE_BIT_SET)
3962                             func (stream, ", #%s%d]%s",
3963                                   NEGATIVE_BIT_SET ? "-" : "",
3964                                   offset * multiplier,
3965                                   WRITEBACK_BIT_SET ? "!" : "");
3966                           else
3967                             func (stream, "], #%s%d",
3968                                   NEGATIVE_BIT_SET ? "-" : "",
3969                                   offset * multiplier);
3970                         }
3971                       else
3972                         func (stream, "]");
3973                     }
3974                     break;
3975
3976                   case 'r':
3977                     {
3978                       int imm4 = (given >> 4) & 0xf;
3979                       int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3980                       int ubit = ! NEGATIVE_BIT_SET;
3981                       const char *rm = arm_regnames [given & 0xf];
3982                       const char *rn = arm_regnames [(given >> 16) & 0xf];
3983
3984                       switch (puw_bits)
3985                         {
3986                         case 1:
3987                         case 3:
3988                           func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3989                           if (imm4)
3990                             func (stream, ", lsl #%d", imm4);
3991                           break;
3992
3993                         case 4:
3994                         case 5:
3995                         case 6:
3996                         case 7:
3997                           func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3998                           if (imm4 > 0)
3999                             func (stream, ", lsl #%d", imm4);
4000                           func (stream, "]");
4001                           if (puw_bits == 5 || puw_bits == 7)
4002                             func (stream, "!");
4003                           break;
4004
4005                         default:
4006                           func (stream, "INVALID");
4007                         }
4008                     }
4009                     break;
4010
4011                   case 'i':
4012                     {
4013                       long imm5;
4014                       imm5 = ((given & 0x100) >> 4) | (given & 0xf);
4015                       func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
4016                     }
4017                     break;
4018
4019                   default:
4020                     abort ();
4021                   }
4022                 }
4023             }
4024           else
4025             func (stream, "%c", *c);
4026         }
4027
4028       if (value_in_comment > 32 || value_in_comment < -16)
4029         func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
4030
4031       if (is_unpredictable)
4032         func (stream, UNPREDICTABLE_INSTRUCTION);
4033
4034       return TRUE;
4035     }
4036   return FALSE;
4037 }
4038
4039 /* Decodes and prints ARM addressing modes.  Returns the offset
4040    used in the address, if any, if it is worthwhile printing the
4041    offset as a hexadecimal value in a comment at the end of the
4042    line of disassembly.  */
4043
4044 static signed long
4045 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
4046 {
4047   void *stream = info->stream;
4048   fprintf_ftype func = info->fprintf_func;
4049   bfd_vma offset = 0;
4050
4051   if (((given & 0x000f0000) == 0x000f0000)
4052       && ((given & 0x02000000) == 0))
4053     {
4054       offset = given & 0xfff;
4055
4056       func (stream, "[pc");
4057
4058       if (PRE_BIT_SET)
4059         {
4060           /* Pre-indexed.  Elide offset of positive zero when
4061              non-writeback.  */
4062           if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
4063             func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4064
4065           if (NEGATIVE_BIT_SET)
4066             offset = -offset;
4067
4068           offset += pc + 8;
4069
4070           /* Cope with the possibility of write-back
4071              being used.  Probably a very dangerous thing
4072              for the programmer to do, but who are we to
4073              argue ?  */
4074           func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
4075         }
4076       else  /* Post indexed.  */
4077         {
4078           func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4079
4080           /* Ie ignore the offset.  */
4081           offset = pc + 8;
4082         }
4083
4084       func (stream, "\t; ");
4085       info->print_address_func (offset, info);
4086       offset = 0;
4087     }
4088   else
4089     {
4090       func (stream, "[%s",
4091             arm_regnames[(given >> 16) & 0xf]);
4092
4093       if (PRE_BIT_SET)
4094         {
4095           if ((given & 0x02000000) == 0)
4096             {
4097               /* Elide offset of positive zero when non-writeback.  */
4098               offset = given & 0xfff;
4099               if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
4100                 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4101             }
4102           else
4103             {
4104               func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
4105               arm_decode_shift (given, func, stream, TRUE);
4106             }
4107
4108           func (stream, "]%s",
4109                 WRITEBACK_BIT_SET ? "!" : "");
4110         }
4111       else
4112         {
4113           if ((given & 0x02000000) == 0)
4114             {
4115               /* Always show offset.  */
4116               offset = given & 0xfff;
4117               func (stream, "], #%s%d",
4118                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4119             }
4120           else
4121             {
4122               func (stream, "], %s",
4123                     NEGATIVE_BIT_SET ? "-" : "");
4124               arm_decode_shift (given, func, stream, TRUE);
4125             }
4126         }
4127       if (NEGATIVE_BIT_SET)
4128         offset = -offset;
4129     }
4130
4131   return (signed long) offset;
4132 }
4133
4134 /* Print one neon instruction on INFO->STREAM.
4135    Return TRUE if the instuction matched, FALSE if this is not a
4136    recognised neon instruction.  */
4137
4138 static bfd_boolean
4139 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
4140 {
4141   const struct opcode32 *insn;
4142   void *stream = info->stream;
4143   fprintf_ftype func = info->fprintf_func;
4144
4145   if (thumb)
4146     {
4147       if ((given & 0xef000000) == 0xef000000)
4148         {
4149           /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding.  */
4150           unsigned long bit28 = given & (1 << 28);
4151
4152           given &= 0x00ffffff;
4153           if (bit28)
4154             given |= 0xf3000000;
4155           else
4156             given |= 0xf2000000;
4157         }
4158       else if ((given & 0xff000000) == 0xf9000000)
4159         given ^= 0xf9000000 ^ 0xf4000000;
4160       else
4161         return FALSE;
4162     }
4163
4164   for (insn = neon_opcodes; insn->assembler; insn++)
4165     {
4166       if ((given & insn->mask) == insn->value)
4167         {
4168           signed long value_in_comment = 0;
4169           bfd_boolean is_unpredictable = FALSE;
4170           const char *c;
4171
4172           for (c = insn->assembler; *c; c++)
4173             {
4174               if (*c == '%')
4175                 {
4176                   switch (*++c)
4177                     {
4178                     case '%':
4179                       func (stream, "%%");
4180                       break;
4181
4182                     case 'u':
4183                       if (thumb && ifthen_state)
4184                         is_unpredictable = TRUE;
4185
4186                       /* Fall through.  */
4187                     case 'c':
4188                       if (thumb && ifthen_state)
4189                         func (stream, "%s", arm_conditional[IFTHEN_COND]);
4190                       break;
4191
4192                     case 'A':
4193                       {
4194                         static const unsigned char enc[16] =
4195                         {
4196                           0x4, 0x14, /* st4 0,1 */
4197                           0x4, /* st1 2 */
4198                           0x4, /* st2 3 */
4199                           0x3, /* st3 4 */
4200                           0x13, /* st3 5 */
4201                           0x3, /* st1 6 */
4202                           0x1, /* st1 7 */
4203                           0x2, /* st2 8 */
4204                           0x12, /* st2 9 */
4205                           0x2, /* st1 10 */
4206                           0, 0, 0, 0, 0
4207                         };
4208                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4209                         int rn = ((given >> 16) & 0xf);
4210                         int rm = ((given >> 0) & 0xf);
4211                         int align = ((given >> 4) & 0x3);
4212                         int type = ((given >> 8) & 0xf);
4213                         int n = enc[type] & 0xf;
4214                         int stride = (enc[type] >> 4) + 1;
4215                         int ix;
4216
4217                         func (stream, "{");
4218                         if (stride > 1)
4219                           for (ix = 0; ix != n; ix++)
4220                             func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
4221                         else if (n == 1)
4222                           func (stream, "d%d", rd);
4223                         else
4224                           func (stream, "d%d-d%d", rd, rd + n - 1);
4225                         func (stream, "}, [%s", arm_regnames[rn]);
4226                         if (align)
4227                           func (stream, " :%d", 32 << align);
4228                         func (stream, "]");
4229                         if (rm == 0xd)
4230                           func (stream, "!");
4231                         else if (rm != 0xf)
4232                           func (stream, ", %s", arm_regnames[rm]);
4233                       }
4234                       break;
4235
4236                     case 'B':
4237                       {
4238                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4239                         int rn = ((given >> 16) & 0xf);
4240                         int rm = ((given >> 0) & 0xf);
4241                         int idx_align = ((given >> 4) & 0xf);
4242                         int align = 0;
4243                         int size = ((given >> 10) & 0x3);
4244                         int idx = idx_align >> (size + 1);
4245                         int length = ((given >> 8) & 3) + 1;
4246                         int stride = 1;
4247                         int i;
4248
4249                         if (length > 1 && size > 0)
4250                           stride = (idx_align & (1 << size)) ? 2 : 1;
4251
4252                         switch (length)
4253                           {
4254                           case 1:
4255                             {
4256                               int amask = (1 << size) - 1;
4257                               if ((idx_align & (1 << size)) != 0)
4258                                 return FALSE;
4259                               if (size > 0)
4260                                 {
4261                                   if ((idx_align & amask) == amask)
4262                                     align = 8 << size;
4263                                   else if ((idx_align & amask) != 0)
4264                                     return FALSE;
4265                                 }
4266                               }
4267                             break;
4268
4269                           case 2:
4270                             if (size == 2 && (idx_align & 2) != 0)
4271                               return FALSE;
4272                             align = (idx_align & 1) ? 16 << size : 0;
4273                             break;
4274
4275                           case 3:
4276                             if ((size == 2 && (idx_align & 3) != 0)
4277                                 || (idx_align & 1) != 0)
4278                               return FALSE;
4279                             break;
4280
4281                           case 4:
4282                             if (size == 2)
4283                               {
4284                                 if ((idx_align & 3) == 3)
4285                                   return FALSE;
4286                                 align = (idx_align & 3) * 64;
4287                               }
4288                             else
4289                               align = (idx_align & 1) ? 32 << size : 0;
4290                             break;
4291
4292                           default:
4293                             abort ();
4294                           }
4295
4296                         func (stream, "{");
4297                         for (i = 0; i < length; i++)
4298                           func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4299                             rd + i * stride, idx);
4300                         func (stream, "}, [%s", arm_regnames[rn]);
4301                         if (align)
4302                           func (stream, " :%d", align);
4303                         func (stream, "]");
4304                         if (rm == 0xd)
4305                           func (stream, "!");
4306                         else if (rm != 0xf)
4307                           func (stream, ", %s", arm_regnames[rm]);
4308                       }
4309                       break;
4310
4311                     case 'C':
4312                       {
4313                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4314                         int rn = ((given >> 16) & 0xf);
4315                         int rm = ((given >> 0) & 0xf);
4316                         int align = ((given >> 4) & 0x1);
4317                         int size = ((given >> 6) & 0x3);
4318                         int type = ((given >> 8) & 0x3);
4319                         int n = type + 1;
4320                         int stride = ((given >> 5) & 0x1);
4321                         int ix;
4322
4323                         if (stride && (n == 1))
4324                           n++;
4325                         else
4326                           stride++;
4327
4328                         func (stream, "{");
4329                         if (stride > 1)
4330                           for (ix = 0; ix != n; ix++)
4331                             func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4332                         else if (n == 1)
4333                           func (stream, "d%d[]", rd);
4334                         else
4335                           func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4336                         func (stream, "}, [%s", arm_regnames[rn]);
4337                         if (align)
4338                           {
4339                             align = (8 * (type + 1)) << size;
4340                             if (type == 3)
4341                               align = (size > 1) ? align >> 1 : align;
4342                             if (type == 2 || (type == 0 && !size))
4343                               func (stream, " :<bad align %d>", align);
4344                             else
4345                               func (stream, " :%d", align);
4346                           }
4347                         func (stream, "]");
4348                         if (rm == 0xd)
4349                           func (stream, "!");
4350                         else if (rm != 0xf)
4351                           func (stream, ", %s", arm_regnames[rm]);
4352                       }
4353                       break;
4354
4355                     case 'D':
4356                       {
4357                         int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4358                         int size = (given >> 20) & 3;
4359                         int reg = raw_reg & ((4 << size) - 1);
4360                         int ix = raw_reg >> size >> 2;
4361
4362                         func (stream, "d%d[%d]", reg, ix);
4363                       }
4364                       break;
4365
4366                     case 'E':
4367                       /* Neon encoded constant for mov, mvn, vorr, vbic.  */
4368                       {
4369                         int bits = 0;
4370                         int cmode = (given >> 8) & 0xf;
4371                         int op = (given >> 5) & 0x1;
4372                         unsigned long value = 0, hival = 0;
4373                         unsigned shift;
4374                         int size = 0;
4375                         int isfloat = 0;
4376
4377                         bits |= ((given >> 24) & 1) << 7;
4378                         bits |= ((given >> 16) & 7) << 4;
4379                         bits |= ((given >> 0) & 15) << 0;
4380
4381                         if (cmode < 8)
4382                           {
4383                             shift = (cmode >> 1) & 3;
4384                             value = (unsigned long) bits << (8 * shift);
4385                             size = 32;
4386                           }
4387                         else if (cmode < 12)
4388                           {
4389                             shift = (cmode >> 1) & 1;
4390                             value = (unsigned long) bits << (8 * shift);
4391                             size = 16;
4392                           }
4393                         else if (cmode < 14)
4394                           {
4395                             shift = (cmode & 1) + 1;
4396                             value = (unsigned long) bits << (8 * shift);
4397                             value |= (1ul << (8 * shift)) - 1;
4398                             size = 32;
4399                           }
4400                         else if (cmode == 14)
4401                           {
4402                             if (op)
4403                               {
4404                                 /* Bit replication into bytes.  */
4405                                 int ix;
4406                                 unsigned long mask;
4407
4408                                 value = 0;
4409                                 hival = 0;
4410                                 for (ix = 7; ix >= 0; ix--)
4411                                   {
4412                                     mask = ((bits >> ix) & 1) ? 0xff : 0;
4413                                     if (ix <= 3)
4414                                       value = (value << 8) | mask;
4415                                     else
4416                                       hival = (hival << 8) | mask;
4417                                   }
4418                                 size = 64;
4419                               }
4420                             else
4421                               {
4422                                 /* Byte replication.  */
4423                                 value = (unsigned long) bits;
4424                                 size = 8;
4425                               }
4426                           }
4427                         else if (!op)
4428                           {
4429                             /* Floating point encoding.  */
4430                             int tmp;
4431
4432                             value = (unsigned long)  (bits & 0x7f) << 19;
4433                             value |= (unsigned long) (bits & 0x80) << 24;
4434                             tmp = bits & 0x40 ? 0x3c : 0x40;
4435                             value |= (unsigned long) tmp << 24;
4436                             size = 32;
4437                             isfloat = 1;
4438                           }
4439                         else
4440                           {
4441                             func (stream, "<illegal constant %.8x:%x:%x>",
4442                                   bits, cmode, op);
4443                             size = 32;
4444                             break;
4445                           }
4446                         switch (size)
4447                           {
4448                           case 8:
4449                             func (stream, "#%ld\t; 0x%.2lx", value, value);
4450                             break;
4451
4452                           case 16:
4453                             func (stream, "#%ld\t; 0x%.4lx", value, value);
4454                             break;
4455
4456                           case 32:
4457                             if (isfloat)
4458                               {
4459                                 unsigned char valbytes[4];
4460                                 double fvalue;
4461
4462                                 /* Do this a byte at a time so we don't have to
4463                                    worry about the host's endianness.  */
4464                                 valbytes[0] = value & 0xff;
4465                                 valbytes[1] = (value >> 8) & 0xff;
4466                                 valbytes[2] = (value >> 16) & 0xff;
4467                                 valbytes[3] = (value >> 24) & 0xff;
4468
4469                                 floatformat_to_double
4470                                   (& floatformat_ieee_single_little, valbytes,
4471                                   & fvalue);
4472
4473                                 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4474                                       value);
4475                               }
4476                             else
4477                               func (stream, "#%ld\t; 0x%.8lx",
4478                                     (long) (((value & 0x80000000L) != 0)
4479                                             ? value | ~0xffffffffL : value),
4480                                     value);
4481                             break;
4482
4483                           case 64:
4484                             func (stream, "#0x%.8lx%.8lx", hival, value);
4485                             break;
4486
4487                           default:
4488                             abort ();
4489                           }
4490                       }
4491                       break;
4492
4493                     case 'F':
4494                       {
4495                         int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4496                         int num = (given >> 8) & 0x3;
4497
4498                         if (!num)
4499                           func (stream, "{d%d}", regno);
4500                         else if (num + regno >= 32)
4501                           func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4502                         else
4503                           func (stream, "{d%d-d%d}", regno, regno + num);
4504                       }
4505                       break;
4506
4507
4508                     case '0': case '1': case '2': case '3': case '4':
4509                     case '5': case '6': case '7': case '8': case '9':
4510                       {
4511                         int width;
4512                         unsigned long value;
4513
4514                         c = arm_decode_bitfield (c, given, &value, &width);
4515
4516                         switch (*c)
4517                           {
4518                           case 'r':
4519                             func (stream, "%s", arm_regnames[value]);
4520                             break;
4521                           case 'd':
4522                             func (stream, "%ld", value);
4523                             value_in_comment = value;
4524                             break;
4525                           case 'e':
4526                             func (stream, "%ld", (1ul << width) - value);
4527                             break;
4528
4529                           case 'S':
4530                           case 'T':
4531                           case 'U':
4532                             /* Various width encodings.  */
4533                             {
4534                               int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4535                               int limit;
4536                               unsigned low, high;
4537
4538                               c++;
4539                               if (*c >= '0' && *c <= '9')
4540                                 limit = *c - '0';
4541                               else if (*c >= 'a' && *c <= 'f')
4542                                 limit = *c - 'a' + 10;
4543                               else
4544                                 abort ();
4545                               low = limit >> 2;
4546                               high = limit & 3;
4547
4548                               if (value < low || value > high)
4549                                 func (stream, "<illegal width %d>", base << value);
4550                               else
4551                                 func (stream, "%d", base << value);
4552                             }
4553                             break;
4554                           case 'R':
4555                             if (given & (1 << 6))
4556                               goto Q;
4557                             /* FALLTHROUGH */
4558                           case 'D':
4559                             func (stream, "d%ld", value);
4560                             break;
4561                           case 'Q':
4562                           Q:
4563                             if (value & 1)
4564                               func (stream, "<illegal reg q%ld.5>", value >> 1);
4565                             else
4566                               func (stream, "q%ld", value >> 1);
4567                             break;
4568
4569                           case '`':
4570                             c++;
4571                             if (value == 0)
4572                               func (stream, "%c", *c);
4573                             break;
4574                           case '\'':
4575                             c++;
4576                             if (value == ((1ul << width) - 1))
4577                               func (stream, "%c", *c);
4578                             break;
4579                           case '?':
4580                             func (stream, "%c", c[(1 << width) - (int) value]);
4581                             c += 1 << width;
4582                             break;
4583                           default:
4584                             abort ();
4585                           }
4586                         break;
4587
4588                       default:
4589                         abort ();
4590                       }
4591                     }
4592                 }
4593               else
4594                 func (stream, "%c", *c);
4595             }
4596
4597           if (value_in_comment > 32 || value_in_comment < -16)
4598             func (stream, "\t; 0x%lx", value_in_comment);
4599
4600           if (is_unpredictable)
4601             func (stream, UNPREDICTABLE_INSTRUCTION);
4602
4603           return TRUE;
4604         }
4605     }
4606   return FALSE;
4607 }
4608
4609 /* Return the name of a v7A special register.  */
4610
4611 static const char *
4612 banked_regname (unsigned reg)
4613 {
4614   switch (reg)
4615     {
4616       case 15: return "CPSR";
4617       case 32: return "R8_usr";
4618       case 33: return "R9_usr";
4619       case 34: return "R10_usr";
4620       case 35: return "R11_usr";
4621       case 36: return "R12_usr";
4622       case 37: return "SP_usr";
4623       case 38: return "LR_usr";
4624       case 40: return "R8_fiq";
4625       case 41: return "R9_fiq";
4626       case 42: return "R10_fiq";
4627       case 43: return "R11_fiq";
4628       case 44: return "R12_fiq";
4629       case 45: return "SP_fiq";
4630       case 46: return "LR_fiq";
4631       case 48: return "LR_irq";
4632       case 49: return "SP_irq";
4633       case 50: return "LR_svc";
4634       case 51: return "SP_svc";
4635       case 52: return "LR_abt";
4636       case 53: return "SP_abt";
4637       case 54: return "LR_und";
4638       case 55: return "SP_und";
4639       case 60: return "LR_mon";
4640       case 61: return "SP_mon";
4641       case 62: return "ELR_hyp";
4642       case 63: return "SP_hyp";
4643       case 79: return "SPSR";
4644       case 110: return "SPSR_fiq";
4645       case 112: return "SPSR_irq";
4646       case 114: return "SPSR_svc";
4647       case 116: return "SPSR_abt";
4648       case 118: return "SPSR_und";
4649       case 124: return "SPSR_mon";
4650       case 126: return "SPSR_hyp";
4651       default: return NULL;
4652     }
4653 }
4654
4655 /* Return the name of the DMB/DSB option.  */
4656 static const char *
4657 data_barrier_option (unsigned option)
4658 {
4659   switch (option & 0xf)
4660     {
4661     case 0xf: return "sy";
4662     case 0xe: return "st";
4663     case 0xd: return "ld";
4664     case 0xb: return "ish";
4665     case 0xa: return "ishst";
4666     case 0x9: return "ishld";
4667     case 0x7: return "un";
4668     case 0x6: return "unst";
4669     case 0x5: return "nshld";
4670     case 0x3: return "osh";
4671     case 0x2: return "oshst";
4672     case 0x1: return "oshld";
4673     default:  return NULL;
4674     }
4675 }
4676
4677 /* Print one ARM instruction from PC on INFO->STREAM.  */
4678
4679 static void
4680 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
4681 {
4682   const struct opcode32 *insn;
4683   void *stream = info->stream;
4684   fprintf_ftype func = info->fprintf_func;
4685   struct arm_private_data *private_data = info->private_data;
4686
4687   if (print_insn_coprocessor (pc, info, given, FALSE))
4688     return;
4689
4690   if (print_insn_neon (info, given, FALSE))
4691     return;
4692
4693   for (insn = arm_opcodes; insn->assembler; insn++)
4694     {
4695       if ((given & insn->mask) != insn->value)
4696         continue;
4697
4698       if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
4699         continue;
4700
4701       /* Special case: an instruction with all bits set in the condition field
4702          (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4703          or by the catchall at the end of the table.  */
4704       if ((given & 0xF0000000) != 0xF0000000
4705           || (insn->mask & 0xF0000000) == 0xF0000000
4706           || (insn->mask == 0 && insn->value == 0))
4707         {
4708           unsigned long u_reg = 16;
4709           unsigned long U_reg = 16;
4710           bfd_boolean is_unpredictable = FALSE;
4711           signed long value_in_comment = 0;
4712           const char *c;
4713
4714           for (c = insn->assembler; *c; c++)
4715             {
4716               if (*c == '%')
4717                 {
4718                   bfd_boolean allow_unpredictable = FALSE;
4719
4720                   switch (*++c)
4721                     {
4722                     case '%':
4723                       func (stream, "%%");
4724                       break;
4725
4726                     case 'a':
4727                       value_in_comment = print_arm_address (pc, info, given);
4728                       break;
4729
4730                     case 'P':
4731                       /* Set P address bit and use normal address
4732                          printing routine.  */
4733                       value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
4734                       break;
4735
4736                     case 'S':
4737                       allow_unpredictable = TRUE;
4738                       /* Fall through.  */
4739                     case 's':
4740                       if ((given & 0x004f0000) == 0x004f0000)
4741                         {
4742                           /* PC relative with immediate offset.  */
4743                           bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
4744
4745                           if (PRE_BIT_SET)
4746                             {
4747                               /* Elide positive zero offset.  */
4748                               if (offset || NEGATIVE_BIT_SET)
4749                                 func (stream, "[pc, #%s%d]\t; ",
4750                                       NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4751                               else
4752                                 func (stream, "[pc]\t; ");
4753                               if (NEGATIVE_BIT_SET)
4754                                 offset = -offset;
4755                               info->print_address_func (offset + pc + 8, info);
4756                             }
4757                           else
4758                             {
4759                               /* Always show the offset.  */
4760                               func (stream, "[pc], #%s%d",
4761                                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4762                               if (! allow_unpredictable)
4763                                 is_unpredictable = TRUE;
4764                             }
4765                         }
4766                       else
4767                         {
4768                           int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4769
4770                           func (stream, "[%s",
4771                                 arm_regnames[(given >> 16) & 0xf]);
4772
4773                           if (PRE_BIT_SET)
4774                             {
4775                               if (IMMEDIATE_BIT_SET)
4776                                 {
4777                                   /* Elide offset for non-writeback
4778                                      positive zero.  */
4779                                   if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4780                                       || offset)
4781                                     func (stream, ", #%s%d",
4782                                           NEGATIVE_BIT_SET ? "-" : "", offset);
4783
4784                                   if (NEGATIVE_BIT_SET)
4785                                     offset = -offset;
4786
4787                                   value_in_comment = offset;
4788                                 }
4789                               else
4790                                 {
4791                                   /* Register Offset or Register Pre-Indexed.  */
4792                                   func (stream, ", %s%s",
4793                                         NEGATIVE_BIT_SET ? "-" : "",
4794                                         arm_regnames[given & 0xf]);
4795
4796                                   /* Writing back to the register that is the source/
4797                                      destination of the load/store is unpredictable.  */
4798                                   if (! allow_unpredictable
4799                                       && WRITEBACK_BIT_SET
4800                                       && ((given & 0xf) == ((given >> 12) & 0xf)))
4801                                     is_unpredictable = TRUE;
4802                                 }
4803
4804                               func (stream, "]%s",
4805                                     WRITEBACK_BIT_SET ? "!" : "");
4806                             }
4807                           else
4808                             {
4809                               if (IMMEDIATE_BIT_SET)
4810                                 {
4811                                   /* Immediate Post-indexed.  */
4812                                   /* PR 10924: Offset must be printed, even if it is zero.  */
4813                                   func (stream, "], #%s%d",
4814                                         NEGATIVE_BIT_SET ? "-" : "", offset);
4815                                   if (NEGATIVE_BIT_SET)
4816                                     offset = -offset;
4817                                   value_in_comment = offset;
4818                                 }
4819                               else
4820                                 {
4821                                   /* Register Post-indexed.  */
4822                                   func (stream, "], %s%s",
4823                                         NEGATIVE_BIT_SET ? "-" : "",
4824                                         arm_regnames[given & 0xf]);
4825
4826                                   /* Writing back to the register that is the source/
4827                                      destination of the load/store is unpredictable.  */
4828                                   if (! allow_unpredictable
4829                                       && (given & 0xf) == ((given >> 12) & 0xf))
4830                                     is_unpredictable = TRUE;
4831                                 }
4832
4833                               if (! allow_unpredictable)
4834                                 {
4835                                   /* Writeback is automatically implied by post- addressing.
4836                                      Setting the W bit is unnecessary and ARM specify it as
4837                                      being unpredictable.  */
4838                                   if (WRITEBACK_BIT_SET
4839                                       /* Specifying the PC register as the post-indexed
4840                                          registers is also unpredictable.  */
4841                                       || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4842                                     is_unpredictable = TRUE;
4843                                 }
4844                             }
4845                         }
4846                       break;
4847
4848                     case 'b':
4849                       {
4850                         bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
4851                         info->print_address_func (disp * 4 + pc + 8, info);
4852                       }
4853                       break;
4854
4855                     case 'c':
4856                       if (((given >> 28) & 0xf) != 0xe)
4857                         func (stream, "%s",
4858                               arm_conditional [(given >> 28) & 0xf]);
4859                       break;
4860
4861                     case 'm':
4862                       {
4863                         int started = 0;
4864                         int reg;
4865
4866                         func (stream, "{");
4867                         for (reg = 0; reg < 16; reg++)
4868                           if ((given & (1 << reg)) != 0)
4869                             {
4870                               if (started)
4871                                 func (stream, ", ");
4872                               started = 1;
4873                               func (stream, "%s", arm_regnames[reg]);
4874                             }
4875                         func (stream, "}");
4876                         if (! started)
4877                           is_unpredictable = TRUE;
4878                       }
4879                       break;
4880
4881                     case 'q':
4882                       arm_decode_shift (given, func, stream, FALSE);
4883                       break;
4884
4885                     case 'o':
4886                       if ((given & 0x02000000) != 0)
4887                         {
4888                           unsigned int rotate = (given & 0xf00) >> 7;
4889                           unsigned int immed = (given & 0xff);
4890                           unsigned int a, i;
4891
4892                           a = (((immed << (32 - rotate))
4893                                 | (immed >> rotate)) & 0xffffffff);
4894                           /* If there is another encoding with smaller rotate,
4895                              the rotate should be specified directly.  */
4896                           for (i = 0; i < 32; i += 2)
4897                             if ((a << i | a >> (32 - i)) <= 0xff)
4898                               break;
4899
4900                           if (i != rotate)
4901                             func (stream, "#%d, %d", immed, rotate);
4902                           else
4903                             func (stream, "#%d", a);
4904                           value_in_comment = a;
4905                         }
4906                       else
4907                         arm_decode_shift (given, func, stream, TRUE);
4908                       break;
4909
4910                     case 'p':
4911                       if ((given & 0x0000f000) == 0x0000f000)
4912                         {
4913                           arm_feature_set arm_ext_v6 =
4914                             ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4915
4916                           /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4917                              mechanism for setting PSR flag bits.  They are
4918                              obsolete in V6 onwards.  */
4919                           if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4920                                                      arm_ext_v6))
4921                             func (stream, "p");
4922                           else
4923                             is_unpredictable = TRUE;
4924                         }
4925                       break;
4926
4927                     case 't':
4928                       if ((given & 0x01200000) == 0x00200000)
4929                         func (stream, "t");
4930                       break;
4931
4932                     case 'A':
4933                       {
4934                         int offset = given & 0xff;
4935
4936                         value_in_comment = offset * 4;
4937                         if (NEGATIVE_BIT_SET)
4938                           value_in_comment = - value_in_comment;
4939
4940                         func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
4941
4942                         if (PRE_BIT_SET)
4943                           {
4944                             if (offset)
4945                               func (stream, ", #%d]%s",
4946                                     (int) value_in_comment,
4947                                     WRITEBACK_BIT_SET ? "!" : "");
4948                             else
4949                               func (stream, "]");
4950                           }
4951                         else
4952                           {
4953                             func (stream, "]");
4954
4955                             if (WRITEBACK_BIT_SET)
4956                               {
4957                                 if (offset)
4958                                   func (stream, ", #%d", (int) value_in_comment);
4959                               }
4960                             else
4961                               {
4962                                 func (stream, ", {%d}", (int) offset);
4963                                 value_in_comment = offset;
4964                               }
4965                           }
4966                       }
4967                       break;
4968
4969                     case 'B':
4970                       /* Print ARM V5 BLX(1) address: pc+25 bits.  */
4971                       {
4972                         bfd_vma address;
4973                         bfd_vma offset = 0;
4974
4975                         if (! NEGATIVE_BIT_SET)
4976                           /* Is signed, hi bits should be ones.  */
4977                           offset = (-1) ^ 0x00ffffff;
4978
4979                         /* Offset is (SignExtend(offset field)<<2).  */
4980                         offset += given & 0x00ffffff;
4981                         offset <<= 2;
4982                         address = offset + pc + 8;
4983
4984                         if (given & 0x01000000)
4985                           /* H bit allows addressing to 2-byte boundaries.  */
4986                           address += 2;
4987
4988                         info->print_address_func (address, info);
4989                       }
4990                       break;
4991
4992                     case 'C':
4993                       if ((given & 0x02000200) == 0x200)
4994                         {
4995                           const char * name;
4996                           unsigned sysm = (given & 0x004f0000) >> 16;
4997
4998                           sysm |= (given & 0x300) >> 4;
4999                           name = banked_regname (sysm);
5000
5001                           if (name != NULL)
5002                             func (stream, "%s", name);
5003                           else
5004                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5005                         }
5006                       else
5007                         {
5008                           func (stream, "%cPSR_",
5009                                 (given & 0x00400000) ? 'S' : 'C');
5010                           if (given & 0x80000)
5011                             func (stream, "f");
5012                           if (given & 0x40000)
5013                             func (stream, "s");
5014                           if (given & 0x20000)
5015                             func (stream, "x");
5016                           if (given & 0x10000)
5017                             func (stream, "c");
5018                         }
5019                       break;
5020
5021                     case 'U':
5022                       if ((given & 0xf0) == 0x60)
5023                         {
5024                           switch (given & 0xf)
5025                             {
5026                             case 0xf: func (stream, "sy"); break;
5027                             default:
5028                               func (stream, "#%d", (int) given & 0xf);
5029                               break;
5030                             }
5031                         }
5032                       else
5033                         {
5034                           const char * opt = data_barrier_option (given & 0xf);
5035                           if (opt != NULL)
5036                             func (stream, "%s", opt);
5037                           else
5038                               func (stream, "#%d", (int) given & 0xf);
5039                         }
5040                       break;
5041
5042                     case '0': case '1': case '2': case '3': case '4':
5043                     case '5': case '6': case '7': case '8': case '9':
5044                       {
5045                         int width;
5046                         unsigned long value;
5047
5048                         c = arm_decode_bitfield (c, given, &value, &width);
5049
5050                         switch (*c)
5051                           {
5052                           case 'R':
5053                             if (value == 15)
5054                               is_unpredictable = TRUE;
5055                             /* Fall through.  */
5056                           case 'r':
5057                           case 'T':
5058                             /* We want register + 1 when decoding T.  */
5059                             if (*c == 'T')
5060                               ++value;
5061
5062                             if (c[1] == 'u')
5063                               {
5064                                 /* Eat the 'u' character.  */
5065                                 ++ c;
5066
5067                                 if (u_reg == value)
5068                                   is_unpredictable = TRUE;
5069                                 u_reg = value;
5070                               }
5071                             if (c[1] == 'U')
5072                               {
5073                                 /* Eat the 'U' character.  */
5074                                 ++ c;
5075
5076                                 if (U_reg == value)
5077                                   is_unpredictable = TRUE;
5078                                 U_reg = value;
5079                               }
5080                             func (stream, "%s", arm_regnames[value]);
5081                             break;
5082                           case 'd':
5083                             func (stream, "%ld", value);
5084                             value_in_comment = value;
5085                             break;
5086                           case 'b':
5087                             func (stream, "%ld", value * 8);
5088                             value_in_comment = value * 8;
5089                             break;
5090                           case 'W':
5091                             func (stream, "%ld", value + 1);
5092                             value_in_comment = value + 1;
5093                             break;
5094                           case 'x':
5095                             func (stream, "0x%08lx", value);
5096
5097                             /* Some SWI instructions have special
5098                                meanings.  */
5099                             if ((given & 0x0fffffff) == 0x0FF00000)
5100                               func (stream, "\t; IMB");
5101                             else if ((given & 0x0fffffff) == 0x0FF00001)
5102                               func (stream, "\t; IMBRange");
5103                             break;
5104                           case 'X':
5105                             func (stream, "%01lx", value & 0xf);
5106                             value_in_comment = value;
5107                             break;
5108                           case '`':
5109                             c++;
5110                             if (value == 0)
5111                               func (stream, "%c", *c);
5112                             break;
5113                           case '\'':
5114                             c++;
5115                             if (value == ((1ul << width) - 1))
5116                               func (stream, "%c", *c);
5117                             break;
5118                           case '?':
5119                             func (stream, "%c", c[(1 << width) - (int) value]);
5120                             c += 1 << width;
5121                             break;
5122                           default:
5123                             abort ();
5124                           }
5125                         break;
5126
5127                       case 'e':
5128                         {
5129                           int imm;
5130
5131                           imm = (given & 0xf) | ((given & 0xfff00) >> 4);
5132                           func (stream, "%d", imm);
5133                           value_in_comment = imm;
5134                         }
5135                         break;
5136
5137                       case 'E':
5138                         /* LSB and WIDTH fields of BFI or BFC.  The machine-
5139                            language instruction encodes LSB and MSB.  */
5140                         {
5141                           long msb = (given & 0x001f0000) >> 16;
5142                           long lsb = (given & 0x00000f80) >> 7;
5143                           long w = msb - lsb + 1;
5144
5145                           if (w > 0)
5146                             func (stream, "#%lu, #%lu", lsb, w);
5147                           else
5148                             func (stream, "(invalid: %lu:%lu)", lsb, msb);
5149                         }
5150                         break;
5151
5152                       case 'R':
5153                         /* Get the PSR/banked register name.  */
5154                         {
5155                           const char * name;
5156                           unsigned sysm = (given & 0x004f0000) >> 16;
5157
5158                           sysm |= (given & 0x300) >> 4;
5159                           name = banked_regname (sysm);
5160
5161                           if (name != NULL)
5162                             func (stream, "%s", name);
5163                           else
5164                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5165                         }
5166                         break;
5167
5168                       case 'V':
5169                         /* 16-bit unsigned immediate from a MOVT or MOVW
5170                            instruction, encoded in bits 0:11 and 15:19.  */
5171                         {
5172                           long hi = (given & 0x000f0000) >> 4;
5173                           long lo = (given & 0x00000fff);
5174                           long imm16 = hi | lo;
5175
5176                           func (stream, "#%lu", imm16);
5177                           value_in_comment = imm16;
5178                         }
5179                         break;
5180
5181                       default:
5182                         abort ();
5183                       }
5184                     }
5185                 }
5186               else
5187                 func (stream, "%c", *c);
5188             }
5189
5190           if (value_in_comment > 32 || value_in_comment < -16)
5191             func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
5192
5193           if (is_unpredictable)
5194             func (stream, UNPREDICTABLE_INSTRUCTION);
5195
5196           return;
5197         }
5198     }
5199   func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
5200   return;
5201 }
5202
5203 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM.  */
5204
5205 static void
5206 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
5207 {
5208   const struct opcode16 *insn;
5209   void *stream = info->stream;
5210   fprintf_ftype func = info->fprintf_func;
5211
5212   for (insn = thumb_opcodes; insn->assembler; insn++)
5213     if ((given & insn->mask) == insn->value)
5214       {
5215         signed long value_in_comment = 0;
5216         const char *c = insn->assembler;
5217
5218         for (; *c; c++)
5219           {
5220             int domaskpc = 0;
5221             int domasklr = 0;
5222
5223             if (*c != '%')
5224               {
5225                 func (stream, "%c", *c);
5226                 continue;
5227               }
5228
5229             switch (*++c)
5230               {
5231               case '%':
5232                 func (stream, "%%");
5233                 break;
5234
5235               case 'c':
5236                 if (ifthen_state)
5237                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
5238                 break;
5239
5240               case 'C':
5241                 if (ifthen_state)
5242                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
5243                 else
5244                   func (stream, "s");
5245                 break;
5246
5247               case 'I':
5248                 {
5249                   unsigned int tmp;
5250
5251                   ifthen_next_state = given & 0xff;
5252                   for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
5253                     func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5254                   func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
5255                 }
5256                 break;
5257
5258               case 'x':
5259                 if (ifthen_next_state)
5260                   func (stream, "\t; unpredictable branch in IT block\n");
5261                 break;
5262
5263               case 'X':
5264                 if (ifthen_state)
5265                   func (stream, "\t; unpredictable <IT:%s>",
5266                         arm_conditional[IFTHEN_COND]);
5267                 break;
5268
5269               case 'S':
5270                 {
5271                   long reg;
5272
5273                   reg = (given >> 3) & 0x7;
5274                   if (given & (1 << 6))
5275                     reg += 8;
5276
5277                   func (stream, "%s", arm_regnames[reg]);
5278                 }
5279                 break;
5280
5281               case 'D':
5282                 {
5283                   long reg;
5284
5285                   reg = given & 0x7;
5286                   if (given & (1 << 7))
5287                     reg += 8;
5288
5289                   func (stream, "%s", arm_regnames[reg]);
5290                 }
5291                 break;
5292
5293               case 'N':
5294                 if (given & (1 << 8))
5295                   domasklr = 1;
5296                 /* Fall through.  */
5297               case 'O':
5298                 if (*c == 'O' && (given & (1 << 8)))
5299                   domaskpc = 1;
5300                 /* Fall through.  */
5301               case 'M':
5302                 {
5303                   int started = 0;
5304                   int reg;
5305
5306                   func (stream, "{");
5307
5308                   /* It would be nice if we could spot
5309                      ranges, and generate the rS-rE format: */
5310                   for (reg = 0; (reg < 8); reg++)
5311                     if ((given & (1 << reg)) != 0)
5312                       {
5313                         if (started)
5314                           func (stream, ", ");
5315                         started = 1;
5316                         func (stream, "%s", arm_regnames[reg]);
5317                       }
5318
5319                   if (domasklr)
5320                     {
5321                       if (started)
5322                         func (stream, ", ");
5323                       started = 1;
5324                       func (stream, "%s", arm_regnames[14] /* "lr" */);
5325                     }
5326
5327                   if (domaskpc)
5328                     {
5329                       if (started)
5330                         func (stream, ", ");
5331                       func (stream, "%s", arm_regnames[15] /* "pc" */);
5332                     }
5333
5334                   func (stream, "}");
5335                 }
5336                 break;
5337
5338               case 'W':
5339                 /* Print writeback indicator for a LDMIA.  We are doing a
5340                    writeback if the base register is not in the register
5341                    mask.  */
5342                 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5343                   func (stream, "!");
5344                 break;
5345
5346               case 'b':
5347                 /* Print ARM V6T2 CZB address: pc+4+6 bits.  */
5348                 {
5349                   bfd_vma address = (pc + 4
5350                                      + ((given & 0x00f8) >> 2)
5351                                      + ((given & 0x0200) >> 3));
5352                   info->print_address_func (address, info);
5353                 }
5354                 break;
5355
5356               case 's':
5357                 /* Right shift immediate -- bits 6..10; 1-31 print
5358                    as themselves, 0 prints as 32.  */
5359                 {
5360                   long imm = (given & 0x07c0) >> 6;
5361                   if (imm == 0)
5362                     imm = 32;
5363                   func (stream, "#%ld", imm);
5364                 }
5365                 break;
5366
5367               case '0': case '1': case '2': case '3': case '4':
5368               case '5': case '6': case '7': case '8': case '9':
5369                 {
5370                   int bitstart = *c++ - '0';
5371                   int bitend = 0;
5372
5373                   while (*c >= '0' && *c <= '9')
5374                     bitstart = (bitstart * 10) + *c++ - '0';
5375
5376                   switch (*c)
5377                     {
5378                     case '-':
5379                       {
5380                         bfd_vma reg;
5381
5382                         c++;
5383                         while (*c >= '0' && *c <= '9')
5384                           bitend = (bitend * 10) + *c++ - '0';
5385                         if (!bitend)
5386                           abort ();
5387                         reg = given >> bitstart;
5388                         reg &= (2 << (bitend - bitstart)) - 1;
5389
5390                         switch (*c)
5391                           {
5392                           case 'r':
5393                             func (stream, "%s", arm_regnames[reg]);
5394                             break;
5395
5396                           case 'd':
5397                             func (stream, "%ld", (long) reg);
5398                             value_in_comment = reg;
5399                             break;
5400
5401                           case 'H':
5402                             func (stream, "%ld", (long) (reg << 1));
5403                             value_in_comment = reg << 1;
5404                             break;
5405
5406                           case 'W':
5407                             func (stream, "%ld", (long) (reg << 2));
5408                             value_in_comment = reg << 2;
5409                             break;
5410
5411                           case 'a':
5412                             /* PC-relative address -- the bottom two
5413                                bits of the address are dropped
5414                                before the calculation.  */
5415                             info->print_address_func
5416                               (((pc + 4) & ~3) + (reg << 2), info);
5417                             value_in_comment = 0;
5418                             break;
5419
5420                           case 'x':
5421                             func (stream, "0x%04lx", (long) reg);
5422                             break;
5423
5424                           case 'B':
5425                             reg = ((reg ^ (1 << bitend)) - (1 << bitend));
5426                             info->print_address_func (reg * 2 + pc + 4, info);
5427                             value_in_comment = 0;
5428                             break;
5429
5430                           case 'c':
5431                             func (stream, "%s", arm_conditional [reg]);
5432                             break;
5433
5434                           default:
5435                             abort ();
5436                           }
5437                       }
5438                       break;
5439
5440                     case '\'':
5441                       c++;
5442                       if ((given & (1 << bitstart)) != 0)
5443                         func (stream, "%c", *c);
5444                       break;
5445
5446                     case '?':
5447                       ++c;
5448                       if ((given & (1 << bitstart)) != 0)
5449                         func (stream, "%c", *c++);
5450                       else
5451                         func (stream, "%c", *++c);
5452                       break;
5453
5454                     default:
5455                       abort ();
5456                     }
5457                 }
5458                 break;
5459
5460               default:
5461                 abort ();
5462               }
5463           }
5464
5465         if (value_in_comment > 32 || value_in_comment < -16)
5466           func (stream, "\t; 0x%lx", value_in_comment);
5467         return;
5468       }
5469
5470   /* No match.  */
5471   func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
5472   return;
5473 }
5474
5475 /* Return the name of an V7M special register.  */
5476
5477 static const char *
5478 psr_name (int regno)
5479 {
5480   switch (regno)
5481     {
5482     case 0x0: return "APSR";
5483     case 0x1: return "IAPSR";
5484     case 0x2: return "EAPSR";
5485     case 0x3: return "PSR";
5486     case 0x5: return "IPSR";
5487     case 0x6: return "EPSR";
5488     case 0x7: return "IEPSR";
5489     case 0x8: return "MSP";
5490     case 0x9: return "PSP";
5491     case 0xa: return "MSPLIM";
5492     case 0xb: return "PSPLIM";
5493     case 0x10: return "PRIMASK";
5494     case 0x11: return "BASEPRI";
5495     case 0x12: return "BASEPRI_MAX";
5496     case 0x13: return "FAULTMASK";
5497     case 0x14: return "CONTROL";
5498     case 0x88: return "MSP_NS";
5499     case 0x89: return "PSP_NS";
5500     case 0x8a: return "MSPLIM_NS";
5501     case 0x8b: return "PSPLIM_NS";
5502     case 0x90: return "PRIMASK_NS";
5503     case 0x91: return "BASEPRI_NS";
5504     case 0x93: return "FAULTMASK_NS";
5505     case 0x94: return "CONTROL_NS";
5506     case 0x98: return "SP_NS";
5507     default: return "<unknown>";
5508     }
5509 }
5510
5511 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM.  */
5512
5513 static void
5514 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
5515 {
5516   const struct opcode32 *insn;
5517   void *stream = info->stream;
5518   fprintf_ftype func = info->fprintf_func;
5519
5520   if (print_insn_coprocessor (pc, info, given, TRUE))
5521     return;
5522
5523   if (print_insn_neon (info, given, TRUE))
5524     return;
5525
5526   for (insn = thumb32_opcodes; insn->assembler; insn++)
5527     if ((given & insn->mask) == insn->value)
5528       {
5529         bfd_boolean is_unpredictable = FALSE;
5530         signed long value_in_comment = 0;
5531         const char *c = insn->assembler;
5532
5533         for (; *c; c++)
5534           {
5535             if (*c != '%')
5536               {
5537                 func (stream, "%c", *c);
5538                 continue;
5539               }
5540
5541             switch (*++c)
5542               {
5543               case '%':
5544                 func (stream, "%%");
5545                 break;
5546
5547               case 'c':
5548                 if (ifthen_state)
5549                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
5550                 break;
5551
5552               case 'x':
5553                 if (ifthen_next_state)
5554                   func (stream, "\t; unpredictable branch in IT block\n");
5555                 break;
5556
5557               case 'X':
5558                 if (ifthen_state)
5559                   func (stream, "\t; unpredictable <IT:%s>",
5560                         arm_conditional[IFTHEN_COND]);
5561                 break;
5562
5563               case 'I':
5564                 {
5565                   unsigned int imm12 = 0;
5566
5567                   imm12 |= (given & 0x000000ffu);
5568                   imm12 |= (given & 0x00007000u) >> 4;
5569                   imm12 |= (given & 0x04000000u) >> 15;
5570                   func (stream, "#%u", imm12);
5571                   value_in_comment = imm12;
5572                 }
5573                 break;
5574
5575               case 'M':
5576                 {
5577                   unsigned int bits = 0, imm, imm8, mod;
5578
5579                   bits |= (given & 0x000000ffu);
5580                   bits |= (given & 0x00007000u) >> 4;
5581                   bits |= (given & 0x04000000u) >> 15;
5582                   imm8 = (bits & 0x0ff);
5583                   mod = (bits & 0xf00) >> 8;
5584                   switch (mod)
5585                     {
5586                     case 0: imm = imm8; break;
5587                     case 1: imm = ((imm8 << 16) | imm8); break;
5588                     case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5589                     case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
5590                     default:
5591                       mod  = (bits & 0xf80) >> 7;
5592                       imm8 = (bits & 0x07f) | 0x80;
5593                       imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5594                     }
5595                   func (stream, "#%u", imm);
5596                   value_in_comment = imm;
5597                 }
5598                 break;
5599
5600               case 'J':
5601                 {
5602                   unsigned int imm = 0;
5603
5604                   imm |= (given & 0x000000ffu);
5605                   imm |= (given & 0x00007000u) >> 4;
5606                   imm |= (given & 0x04000000u) >> 15;
5607                   imm |= (given & 0x000f0000u) >> 4;
5608                   func (stream, "#%u", imm);
5609                   value_in_comment = imm;
5610                 }
5611                 break;
5612
5613               case 'K':
5614                 {
5615                   unsigned int imm = 0;
5616
5617                   imm |= (given & 0x000f0000u) >> 16;
5618                   imm |= (given & 0x00000ff0u) >> 0;
5619                   imm |= (given & 0x0000000fu) << 12;
5620                   func (stream, "#%u", imm);
5621                   value_in_comment = imm;
5622                 }
5623                 break;
5624
5625               case 'H':
5626                 {
5627                   unsigned int imm = 0;
5628
5629                   imm |= (given & 0x000f0000u) >> 4;
5630                   imm |= (given & 0x00000fffu) >> 0;
5631                   func (stream, "#%u", imm);
5632                   value_in_comment = imm;
5633                 }
5634                 break;
5635
5636               case 'V':
5637                 {
5638                   unsigned int imm = 0;
5639
5640                   imm |= (given & 0x00000fffu);
5641                   imm |= (given & 0x000f0000u) >> 4;
5642                   func (stream, "#%u", imm);
5643                   value_in_comment = imm;
5644                 }
5645                 break;
5646
5647               case 'S':
5648                 {
5649                   unsigned int reg = (given & 0x0000000fu);
5650                   unsigned int stp = (given & 0x00000030u) >> 4;
5651                   unsigned int imm = 0;
5652                   imm |= (given & 0x000000c0u) >> 6;
5653                   imm |= (given & 0x00007000u) >> 10;
5654
5655                   func (stream, "%s", arm_regnames[reg]);
5656                   switch (stp)
5657                     {
5658                     case 0:
5659                       if (imm > 0)
5660                         func (stream, ", lsl #%u", imm);
5661                       break;
5662
5663                     case 1:
5664                       if (imm == 0)
5665                         imm = 32;
5666                       func (stream, ", lsr #%u", imm);
5667                       break;
5668
5669                     case 2:
5670                       if (imm == 0)
5671                         imm = 32;
5672                       func (stream, ", asr #%u", imm);
5673                       break;
5674
5675                     case 3:
5676                       if (imm == 0)
5677                         func (stream, ", rrx");
5678                       else
5679                         func (stream, ", ror #%u", imm);
5680                     }
5681                 }
5682                 break;
5683
5684               case 'a':
5685                 {
5686                   unsigned int Rn  = (given & 0x000f0000) >> 16;
5687                   unsigned int U   = ! NEGATIVE_BIT_SET;
5688                   unsigned int op  = (given & 0x00000f00) >> 8;
5689                   unsigned int i12 = (given & 0x00000fff);
5690                   unsigned int i8  = (given & 0x000000ff);
5691                   bfd_boolean writeback = FALSE, postind = FALSE;
5692                   bfd_vma offset = 0;
5693
5694                   func (stream, "[%s", arm_regnames[Rn]);
5695                   if (U) /* 12-bit positive immediate offset.  */
5696                     {
5697                       offset = i12;
5698                       if (Rn != 15)
5699                         value_in_comment = offset;
5700                     }
5701                   else if (Rn == 15) /* 12-bit negative immediate offset.  */
5702                     offset = - (int) i12;
5703                   else if (op == 0x0) /* Shifted register offset.  */
5704                     {
5705                       unsigned int Rm = (i8 & 0x0f);
5706                       unsigned int sh = (i8 & 0x30) >> 4;
5707
5708                       func (stream, ", %s", arm_regnames[Rm]);
5709                       if (sh)
5710                         func (stream, ", lsl #%u", sh);
5711                       func (stream, "]");
5712                       break;
5713                     }
5714                   else switch (op)
5715                     {
5716                     case 0xE:  /* 8-bit positive immediate offset.  */
5717                       offset = i8;
5718                       break;
5719
5720                     case 0xC:  /* 8-bit negative immediate offset.  */
5721                       offset = -i8;
5722                       break;
5723
5724                     case 0xF:  /* 8-bit + preindex with wb.  */
5725                       offset = i8;
5726                       writeback = TRUE;
5727                       break;
5728
5729                     case 0xD:  /* 8-bit - preindex with wb.  */
5730                       offset = -i8;
5731                       writeback = TRUE;
5732                       break;
5733
5734                     case 0xB:  /* 8-bit + postindex.  */
5735                       offset = i8;
5736                       postind = TRUE;
5737                       break;
5738
5739                     case 0x9:  /* 8-bit - postindex.  */
5740                       offset = -i8;
5741                       postind = TRUE;
5742                       break;
5743
5744                     default:
5745                       func (stream, ", <undefined>]");
5746                       goto skip;
5747                     }
5748
5749                   if (postind)
5750                     func (stream, "], #%d", (int) offset);
5751                   else
5752                     {
5753                       if (offset)
5754                         func (stream, ", #%d", (int) offset);
5755                       func (stream, writeback ? "]!" : "]");
5756                     }
5757
5758                   if (Rn == 15)
5759                     {
5760                       func (stream, "\t; ");
5761                       info->print_address_func (((pc + 4) & ~3) + offset, info);
5762                     }
5763                 }
5764               skip:
5765                 break;
5766
5767               case 'A':
5768                 {
5769                   unsigned int U   = ! NEGATIVE_BIT_SET;
5770                   unsigned int W   = WRITEBACK_BIT_SET;
5771                   unsigned int Rn  = (given & 0x000f0000) >> 16;
5772                   unsigned int off = (given & 0x000000ff);
5773
5774                   func (stream, "[%s", arm_regnames[Rn]);
5775
5776                   if (PRE_BIT_SET)
5777                     {
5778                       if (off || !U)
5779                         {
5780                           func (stream, ", #%c%u", U ? '+' : '-', off * 4);
5781                           value_in_comment = off * 4 * (U ? 1 : -1);
5782                         }
5783                       func (stream, "]");
5784                       if (W)
5785                         func (stream, "!");
5786                     }
5787                   else
5788                     {
5789                       func (stream, "], ");
5790                       if (W)
5791                         {
5792                           func (stream, "#%c%u", U ? '+' : '-', off * 4);
5793                           value_in_comment = off * 4 * (U ? 1 : -1);
5794                         }
5795                       else
5796                         {
5797                           func (stream, "{%u}", off);
5798                           value_in_comment = off;
5799                         }
5800                     }
5801                 }
5802                 break;
5803
5804               case 'w':
5805                 {
5806                   unsigned int Sbit = (given & 0x01000000) >> 24;
5807                   unsigned int type = (given & 0x00600000) >> 21;
5808
5809                   switch (type)
5810                     {
5811                     case 0: func (stream, Sbit ? "sb" : "b"); break;
5812                     case 1: func (stream, Sbit ? "sh" : "h"); break;
5813                     case 2:
5814                       if (Sbit)
5815                         func (stream, "??");
5816                       break;
5817                     case 3:
5818                       func (stream, "??");
5819                       break;
5820                     }
5821                 }
5822                 break;
5823
5824               case 'm':
5825                 {
5826                   int started = 0;
5827                   int reg;
5828
5829                   func (stream, "{");
5830                   for (reg = 0; reg < 16; reg++)
5831                     if ((given & (1 << reg)) != 0)
5832                       {
5833                         if (started)
5834                           func (stream, ", ");
5835                         started = 1;
5836                         func (stream, "%s", arm_regnames[reg]);
5837                       }
5838                   func (stream, "}");
5839                 }
5840                 break;
5841
5842               case 'E':
5843                 {
5844                   unsigned int msb = (given & 0x0000001f);
5845                   unsigned int lsb = 0;
5846
5847                   lsb |= (given & 0x000000c0u) >> 6;
5848                   lsb |= (given & 0x00007000u) >> 10;
5849                   func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5850                 }
5851                 break;
5852
5853               case 'F':
5854                 {
5855                   unsigned int width = (given & 0x0000001f) + 1;
5856                   unsigned int lsb = 0;
5857
5858                   lsb |= (given & 0x000000c0u) >> 6;
5859                   lsb |= (given & 0x00007000u) >> 10;
5860                   func (stream, "#%u, #%u", lsb, width);
5861                 }
5862                 break;
5863
5864               case 'b':
5865                 {
5866                   unsigned int S = (given & 0x04000000u) >> 26;
5867                   unsigned int J1 = (given & 0x00002000u) >> 13;
5868                   unsigned int J2 = (given & 0x00000800u) >> 11;
5869                   bfd_vma offset = 0;
5870
5871                   offset |= !S << 20;
5872                   offset |= J2 << 19;
5873                   offset |= J1 << 18;
5874                   offset |= (given & 0x003f0000) >> 4;
5875                   offset |= (given & 0x000007ff) << 1;
5876                   offset -= (1 << 20);
5877
5878                   info->print_address_func (pc + 4 + offset, info);
5879                 }
5880                 break;
5881
5882               case 'B':
5883                 {
5884                   unsigned int S = (given & 0x04000000u) >> 26;
5885                   unsigned int I1 = (given & 0x00002000u) >> 13;
5886                   unsigned int I2 = (given & 0x00000800u) >> 11;
5887                   bfd_vma offset = 0;
5888
5889                   offset |= !S << 24;
5890                   offset |= !(I1 ^ S) << 23;
5891                   offset |= !(I2 ^ S) << 22;
5892                   offset |= (given & 0x03ff0000u) >> 4;
5893                   offset |= (given & 0x000007ffu) << 1;
5894                   offset -= (1 << 24);
5895                   offset += pc + 4;
5896
5897                   /* BLX target addresses are always word aligned.  */
5898                   if ((given & 0x00001000u) == 0)
5899                       offset &= ~2u;
5900
5901                   info->print_address_func (offset, info);
5902                 }
5903                 break;
5904
5905               case 's':
5906                 {
5907                   unsigned int shift = 0;
5908
5909                   shift |= (given & 0x000000c0u) >> 6;
5910                   shift |= (given & 0x00007000u) >> 10;
5911                   if (WRITEBACK_BIT_SET)
5912                     func (stream, ", asr #%u", shift);
5913                   else if (shift)
5914                     func (stream, ", lsl #%u", shift);
5915                   /* else print nothing - lsl #0 */
5916                 }
5917                 break;
5918
5919               case 'R':
5920                 {
5921                   unsigned int rot = (given & 0x00000030) >> 4;
5922
5923                   if (rot)
5924                     func (stream, ", ror #%u", rot * 8);
5925                 }
5926                 break;
5927
5928               case 'U':
5929                 if ((given & 0xf0) == 0x60)
5930                   {
5931                     switch (given & 0xf)
5932                       {
5933                         case 0xf: func (stream, "sy"); break;
5934                         default:
5935                           func (stream, "#%d", (int) given & 0xf);
5936                               break;
5937                       }
5938                   }
5939                 else
5940                   {
5941                     const char * opt = data_barrier_option (given & 0xf);
5942                     if (opt != NULL)
5943                       func (stream, "%s", opt);
5944                     else
5945                       func (stream, "#%d", (int) given & 0xf);
5946                    }
5947                 break;
5948
5949               case 'C':
5950                 if ((given & 0xff) == 0)
5951                   {
5952                     func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5953                     if (given & 0x800)
5954                       func (stream, "f");
5955                     if (given & 0x400)
5956                       func (stream, "s");
5957                     if (given & 0x200)
5958                       func (stream, "x");
5959                     if (given & 0x100)
5960                       func (stream, "c");
5961                   }
5962                 else if ((given & 0x20) == 0x20)
5963                   {
5964                     char const* name;
5965                     unsigned sysm = (given & 0xf00) >> 8;
5966
5967                     sysm |= (given & 0x30);
5968                     sysm |= (given & 0x00100000) >> 14;
5969                     name = banked_regname (sysm);
5970
5971                     if (name != NULL)
5972                       func (stream, "%s", name);
5973                     else
5974                       func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5975                   }
5976                 else
5977                   {
5978                     func (stream, "%s", psr_name (given & 0xff));
5979                   }
5980                 break;
5981
5982               case 'D':
5983                 if (((given & 0xff) == 0)
5984                     || ((given & 0x20) == 0x20))
5985                   {
5986                     char const* name;
5987                     unsigned sm = (given & 0xf0000) >> 16;
5988
5989                     sm |= (given & 0x30);
5990                     sm |= (given & 0x00100000) >> 14;
5991                     name = banked_regname (sm);
5992
5993                     if (name != NULL)
5994                       func (stream, "%s", name);
5995                     else
5996                       func (stream, "(UNDEF: %lu)", (unsigned long) sm);
5997                   }
5998                 else
5999                   func (stream, "%s", psr_name (given & 0xff));
6000                 break;
6001
6002               case '0': case '1': case '2': case '3': case '4':
6003               case '5': case '6': case '7': case '8': case '9':
6004                 {
6005                   int width;
6006                   unsigned long val;
6007
6008                   c = arm_decode_bitfield (c, given, &val, &width);
6009
6010                   switch (*c)
6011                     {
6012                     case 'd':
6013                       func (stream, "%lu", val);
6014                       value_in_comment = val;
6015                       break;
6016
6017                     case 'D':
6018                       func (stream, "%lu", val + 1);
6019                       value_in_comment = val + 1;
6020                       break;
6021
6022                     case 'W':
6023                       func (stream, "%lu", val * 4);
6024                       value_in_comment = val * 4;
6025                       break;
6026
6027                     case 'R':
6028                       if (val == 15)
6029                         is_unpredictable = TRUE;
6030                       /* Fall through.  */
6031                     case 'r':
6032                       func (stream, "%s", arm_regnames[val]);
6033                       break;
6034
6035                     case 'c':
6036                       func (stream, "%s", arm_conditional[val]);
6037                       break;
6038
6039                     case '\'':
6040                       c++;
6041                       if (val == ((1ul << width) - 1))
6042                         func (stream, "%c", *c);
6043                       break;
6044
6045                     case '`':
6046                       c++;
6047                       if (val == 0)
6048                         func (stream, "%c", *c);
6049                       break;
6050
6051                     case '?':
6052                       func (stream, "%c", c[(1 << width) - (int) val]);
6053                       c += 1 << width;
6054                       break;
6055
6056                     case 'x':
6057                       func (stream, "0x%lx", val & 0xffffffffUL);
6058                       break;
6059
6060                     default:
6061                       abort ();
6062                     }
6063                 }
6064                 break;
6065
6066               case 'L':
6067                 /* PR binutils/12534
6068                    If we have a PC relative offset in an LDRD or STRD
6069                    instructions then display the decoded address.  */
6070                 if (((given >> 16) & 0xf) == 0xf)
6071                   {
6072                     bfd_vma offset = (given & 0xff) * 4;
6073
6074                     if ((given & (1 << 23)) == 0)
6075                       offset = - offset;
6076                     func (stream, "\t; ");
6077                     info->print_address_func ((pc & ~3) + 4 + offset, info);
6078                   }
6079                 break;
6080
6081               default:
6082                 abort ();
6083               }
6084           }
6085
6086         if (value_in_comment > 32 || value_in_comment < -16)
6087           func (stream, "\t; 0x%lx", value_in_comment);
6088
6089         if (is_unpredictable)
6090           func (stream, UNPREDICTABLE_INSTRUCTION);
6091
6092         return;
6093       }
6094
6095   /* No match.  */
6096   func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
6097   return;
6098 }
6099
6100 /* Print data bytes on INFO->STREAM.  */
6101
6102 static void
6103 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
6104                  struct disassemble_info *info,
6105                  long given)
6106 {
6107   switch (info->bytes_per_chunk)
6108     {
6109     case 1:
6110       info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
6111       break;
6112     case 2:
6113       info->fprintf_func (info->stream, ".short\t0x%04lx", given);
6114       break;
6115     case 4:
6116       info->fprintf_func (info->stream, ".word\t0x%08lx", given);
6117       break;
6118     default:
6119       abort ();
6120     }
6121 }
6122
6123 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
6124    being displayed in symbol relative addresses.
6125
6126    Also disallow private symbol, with __tagsym$$ prefix,
6127    from ARM RVCT toolchain being displayed.  */
6128
6129 bfd_boolean
6130 arm_symbol_is_valid (asymbol * sym,
6131                      struct disassemble_info * info ATTRIBUTE_UNUSED)
6132 {
6133   const char * name;
6134
6135   if (sym == NULL)
6136     return FALSE;
6137
6138   name = bfd_asymbol_name (sym);
6139
6140   return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
6141 }
6142
6143 /* Parse the string of disassembler options.  */
6144
6145 static void
6146 parse_arm_disassembler_options (const char *options)
6147 {
6148   const char *opt;
6149
6150   FOR_EACH_DISASSEMBLER_OPTION (opt, options)
6151     {
6152       if (CONST_STRNEQ (opt, "reg-names-"))
6153         {
6154           unsigned int i;
6155           for (i = 0; i < NUM_ARM_OPTIONS; i++)
6156             if (disassembler_options_cmp (opt, regnames[i].name) == 0)
6157               {
6158                 regname_selected = i;
6159                 break;
6160               }
6161
6162           if (i >= NUM_ARM_OPTIONS)
6163             /* xgettext: c-format */
6164             opcodes_error_handler (_("unrecognised register name set: %s"),
6165                                    opt);
6166         }
6167       else if (CONST_STRNEQ (opt, "force-thumb"))
6168         force_thumb = 1;
6169       else if (CONST_STRNEQ (opt, "no-force-thumb"))
6170         force_thumb = 0;
6171       else
6172         /* xgettext: c-format */
6173         opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
6174     }
6175
6176   return;
6177 }
6178
6179 static bfd_boolean
6180 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6181                          enum map_type *map_symbol);
6182
6183 /* Search back through the insn stream to determine if this instruction is
6184    conditionally executed.  */
6185
6186 static void
6187 find_ifthen_state (bfd_vma pc,
6188                    struct disassemble_info *info,
6189                    bfd_boolean little)
6190 {
6191   unsigned char b[2];
6192   unsigned int insn;
6193   int status;
6194   /* COUNT is twice the number of instructions seen.  It will be odd if we
6195      just crossed an instruction boundary.  */
6196   int count;
6197   int it_count;
6198   unsigned int seen_it;
6199   bfd_vma addr;
6200
6201   ifthen_address = pc;
6202   ifthen_state = 0;
6203
6204   addr = pc;
6205   count = 1;
6206   it_count = 0;
6207   seen_it = 0;
6208   /* Scan backwards looking for IT instructions, keeping track of where
6209      instruction boundaries are.  We don't know if something is actually an
6210      IT instruction until we find a definite instruction boundary.  */
6211   for (;;)
6212     {
6213       if (addr == 0 || info->symbol_at_address_func (addr, info))
6214         {
6215           /* A symbol must be on an instruction boundary, and will not
6216              be within an IT block.  */
6217           if (seen_it && (count & 1))
6218             break;
6219
6220           return;
6221         }
6222       addr -= 2;
6223       status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
6224       if (status)
6225         return;
6226
6227       if (little)
6228         insn = (b[0]) | (b[1] << 8);
6229       else
6230         insn = (b[1]) | (b[0] << 8);
6231       if (seen_it)
6232         {
6233           if ((insn & 0xf800) < 0xe800)
6234             {
6235               /* Addr + 2 is an instruction boundary.  See if this matches
6236                  the expected boundary based on the position of the last
6237                  IT candidate.  */
6238               if (count & 1)
6239                 break;
6240               seen_it = 0;
6241             }
6242         }
6243       if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6244         {
6245           enum map_type type = MAP_ARM;
6246           bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
6247
6248           if (!found || (found && type == MAP_THUMB))
6249             {
6250               /* This could be an IT instruction.  */
6251               seen_it = insn;
6252               it_count = count >> 1;
6253             }
6254         }
6255       if ((insn & 0xf800) >= 0xe800)
6256         count++;
6257       else
6258         count = (count + 2) | 1;
6259       /* IT blocks contain at most 4 instructions.  */
6260       if (count >= 8 && !seen_it)
6261         return;
6262     }
6263   /* We found an IT instruction.  */
6264   ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6265   if ((ifthen_state & 0xf) == 0)
6266     ifthen_state = 0;
6267 }
6268
6269 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6270    mapping symbol.  */
6271
6272 static int
6273 is_mapping_symbol (struct disassemble_info *info, int n,
6274                    enum map_type *map_type)
6275 {
6276   const char *name;
6277
6278   name = bfd_asymbol_name (info->symtab[n]);
6279   if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6280       && (name[2] == 0 || name[2] == '.'))
6281     {
6282       *map_type = ((name[1] == 'a') ? MAP_ARM
6283                    : (name[1] == 't') ? MAP_THUMB
6284                    : MAP_DATA);
6285       return TRUE;
6286     }
6287
6288   return FALSE;
6289 }
6290
6291 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6292    Returns nonzero if *MAP_TYPE was set.  */
6293
6294 static int
6295 get_map_sym_type (struct disassemble_info *info,
6296                   int n,
6297                   enum map_type *map_type)
6298 {
6299   /* If the symbol is in a different section, ignore it.  */
6300   if (info->section != NULL && info->section != info->symtab[n]->section)
6301     return FALSE;
6302
6303   return is_mapping_symbol (info, n, map_type);
6304 }
6305
6306 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
6307    Returns nonzero if *MAP_TYPE was set.  */
6308
6309 static int
6310 get_sym_code_type (struct disassemble_info *info,
6311                    int n,
6312                    enum map_type *map_type)
6313 {
6314   elf_symbol_type *es;
6315   unsigned int type;
6316
6317   /* If the symbol is in a different section, ignore it.  */
6318   if (info->section != NULL && info->section != info->symtab[n]->section)
6319     return FALSE;
6320
6321   es = *(elf_symbol_type **)(info->symtab + n);
6322   type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6323
6324   /* If the symbol has function type then use that.  */
6325   if (type == STT_FUNC || type == STT_GNU_IFUNC)
6326     {
6327       if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6328           == ST_BRANCH_TO_THUMB)
6329         *map_type = MAP_THUMB;
6330       else
6331         *map_type = MAP_ARM;
6332       return TRUE;
6333     }
6334
6335   return FALSE;
6336 }
6337
6338 /* Search the mapping symbol state for instruction at pc.  This is only
6339    applicable for elf target.
6340
6341    There is an assumption Here, info->private_data contains the correct AND
6342    up-to-date information about current scan process.  The information will be
6343    used to speed this search process.
6344
6345    Return TRUE if the mapping state can be determined, and map_symbol
6346    will be updated accordingly.  Otherwise, return FALSE.  */
6347
6348 static bfd_boolean
6349 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6350                          enum map_type *map_symbol)
6351 {
6352   bfd_vma addr;
6353   int n, start = 0;
6354   bfd_boolean found = FALSE;
6355   enum map_type type = MAP_ARM;
6356   struct arm_private_data *private_data;
6357
6358   if (info->private_data == NULL || info->symtab_size == 0
6359       || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
6360     return FALSE;
6361
6362   private_data = info->private_data;
6363   if (pc == 0)
6364     start = 0;
6365   else
6366     start = private_data->last_mapping_sym;
6367
6368   start = (start == -1)? 0 : start;
6369   addr = bfd_asymbol_value (info->symtab[start]);
6370
6371   if (pc >= addr)
6372     {
6373       if (get_map_sym_type (info, start, &type))
6374       found = TRUE;
6375     }
6376   else
6377     {
6378       for (n = start - 1; n >= 0; n--)
6379         {
6380           if (get_map_sym_type (info, n, &type))
6381             {
6382               found = TRUE;
6383               break;
6384             }
6385         }
6386     }
6387
6388   /* No mapping symbols were found.  A leading $d may be
6389      omitted for sections which start with data; but for
6390      compatibility with legacy and stripped binaries, only
6391      assume the leading $d if there is at least one mapping
6392      symbol in the file.  */
6393   if (!found && private_data->has_mapping_symbols == 1)
6394     {
6395       type = MAP_DATA;
6396       found = TRUE;
6397     }
6398
6399   *map_symbol = type;
6400   return found;
6401 }
6402
6403 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
6404    of the supplied arm_feature_set structure with bitmasks indicating
6405    the supported base architectures and coprocessor extensions.
6406
6407    FIXME: This could more efficiently implemented as a constant array,
6408    although it would also be less robust.  */
6409
6410 static void
6411 select_arm_features (unsigned long mach,
6412                      arm_feature_set * features)
6413 {
6414   arm_feature_set arch_fset;
6415   const arm_feature_set fpu_any = FPU_ANY;
6416
6417 #undef ARM_SET_FEATURES
6418 #define ARM_SET_FEATURES(FSET) \
6419   {                                                     \
6420     const arm_feature_set fset = FSET;                  \
6421     arch_fset = fset;                                   \
6422   }
6423
6424   /* When several architecture versions share the same bfd_mach_arm_XXX value
6425      the most featureful is chosen.  */
6426   switch (mach)
6427     {
6428     case bfd_mach_arm_2:         ARM_SET_FEATURES (ARM_ARCH_V2); break;
6429     case bfd_mach_arm_2a:        ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6430     case bfd_mach_arm_3:         ARM_SET_FEATURES (ARM_ARCH_V3); break;
6431     case bfd_mach_arm_3M:        ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6432     case bfd_mach_arm_4:         ARM_SET_FEATURES (ARM_ARCH_V4); break;
6433     case bfd_mach_arm_4T:        ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6434     case bfd_mach_arm_5:         ARM_SET_FEATURES (ARM_ARCH_V5); break;
6435     case bfd_mach_arm_5T:        ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6436     case bfd_mach_arm_5TE:       ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6437     case bfd_mach_arm_XScale:    ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
6438     case bfd_mach_arm_ep9312:
6439         ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6440                                            ARM_CEXT_MAVERICK | FPU_MAVERICK));
6441        break;
6442     case bfd_mach_arm_iWMMXt:    ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6443     case bfd_mach_arm_iWMMXt2:   ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
6444     case bfd_mach_arm_5TEJ:      ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
6445     case bfd_mach_arm_6:         ARM_SET_FEATURES (ARM_ARCH_V6); break;
6446     case bfd_mach_arm_6KZ:       ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
6447     case bfd_mach_arm_6T2:       ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
6448     case bfd_mach_arm_6K:        ARM_SET_FEATURES (ARM_ARCH_V6K); break;
6449     case bfd_mach_arm_7:         ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
6450     case bfd_mach_arm_6M:        ARM_SET_FEATURES (ARM_ARCH_V6M); break;
6451     case bfd_mach_arm_6SM:       ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
6452     case bfd_mach_arm_7EM:       ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
6453     case bfd_mach_arm_8:
6454         {
6455           /* Add bits for extensions that Armv8.5-A recognizes.  */
6456           arm_feature_set armv8_5_ext_fset
6457             = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
6458           ARM_SET_FEATURES (ARM_ARCH_V8_5A);
6459           ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
6460           break;
6461         }
6462     case bfd_mach_arm_8R:        ARM_SET_FEATURES (ARM_ARCH_V8R); break;
6463     case bfd_mach_arm_8M_BASE:   ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
6464     case bfd_mach_arm_8M_MAIN:   ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
6465       /* If the machine type is unknown allow all architecture types and all
6466          extensions.  */
6467     case bfd_mach_arm_unknown:   ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
6468     default:
6469       abort ();
6470     }
6471 #undef ARM_SET_FEATURES
6472
6473   /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
6474      and thus on bfd_mach_arm_XXX value.  Therefore for a given
6475      bfd_mach_arm_XXX value all coprocessor feature bits should be allowed.  */
6476   ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
6477 }
6478
6479
6480 /* NOTE: There are no checks in these routines that
6481    the relevant number of data bytes exist.  */
6482
6483 static int
6484 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
6485 {
6486   unsigned char b[4];
6487   long          given;
6488   int           status;
6489   int           is_thumb = FALSE;
6490   int           is_data = FALSE;
6491   int           little_code;
6492   unsigned int  size = 4;
6493   void          (*printer) (bfd_vma, struct disassemble_info *, long);
6494   bfd_boolean   found = FALSE;
6495   struct arm_private_data *private_data;
6496
6497   if (info->disassembler_options)
6498     {
6499       parse_arm_disassembler_options (info->disassembler_options);
6500
6501       /* To avoid repeated parsing of these options, we remove them here.  */
6502       info->disassembler_options = NULL;
6503     }
6504
6505   /* PR 10288: Control which instructions will be disassembled.  */
6506   if (info->private_data == NULL)
6507     {
6508       static struct arm_private_data private;
6509
6510       if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6511         /* If the user did not use the -m command line switch then default to
6512            disassembling all types of ARM instruction.
6513
6514            The info->mach value has to be ignored as this will be based on
6515            the default archictecture for the target and/or hints in the notes
6516            section, but it will never be greater than the current largest arm
6517            machine value (iWMMXt2), which is only equivalent to the V5TE
6518            architecture.  ARM architectures have advanced beyond the machine
6519            value encoding, and these newer architectures would be ignored if
6520            the machine value was used.
6521
6522            Ie the -m switch is used to restrict which instructions will be
6523            disassembled.  If it is necessary to use the -m switch to tell
6524            objdump that an ARM binary is being disassembled, eg because the
6525            input is a raw binary file, but it is also desired to disassemble
6526            all ARM instructions then use "-marm".  This will select the
6527            "unknown" arm architecture which is compatible with any ARM
6528            instruction.  */
6529           info->mach = bfd_mach_arm_unknown;
6530
6531       /* Compute the architecture bitmask from the machine number.
6532          Note: This assumes that the machine number will not change
6533          during disassembly....  */
6534       select_arm_features (info->mach, & private.features);
6535
6536       private.has_mapping_symbols = -1;
6537       private.last_mapping_sym = -1;
6538       private.last_mapping_addr = 0;
6539
6540       info->private_data = & private;
6541     }
6542
6543   private_data = info->private_data;
6544
6545   /* Decide if our code is going to be little-endian, despite what the
6546      function argument might say.  */
6547   little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6548
6549   /* For ELF, consult the symbol table to determine what kind of code
6550      or data we have.  */
6551   if (info->symtab_size != 0
6552       && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6553     {
6554       bfd_vma addr;
6555       int n, start;
6556       int last_sym = -1;
6557       enum map_type type = MAP_ARM;
6558
6559       /* Start scanning at the start of the function, or wherever
6560          we finished last time.  */
6561       /* PR 14006.  When the address is 0 we are either at the start of the
6562          very first function, or else the first function in a new, unlinked
6563          executable section (eg because of -ffunction-sections).  Either way
6564          start scanning from the beginning of the symbol table, not where we
6565          left off last time.  */
6566       if (pc == 0)
6567         start = 0;
6568       else
6569         {
6570           start = info->symtab_pos + 1;
6571           if (start < private_data->last_mapping_sym)
6572             start = private_data->last_mapping_sym;
6573         }
6574       found = FALSE;
6575
6576       /* First, look for mapping symbols.  */
6577       if (private_data->has_mapping_symbols != 0)
6578         {
6579           /* Scan up to the location being disassembled.  */
6580           for (n = start; n < info->symtab_size; n++)
6581             {
6582               addr = bfd_asymbol_value (info->symtab[n]);
6583               if (addr > pc)
6584                 break;
6585               if (get_map_sym_type (info, n, &type))
6586                 {
6587                   last_sym = n;
6588                   found = TRUE;
6589                 }
6590             }
6591
6592           if (!found)
6593             {
6594               /* No mapping symbol found at this address.  Look backwards
6595                  for a preceding one.  */
6596               for (n = start - 1; n >= 0; n--)
6597                 {
6598                   if (get_map_sym_type (info, n, &type))
6599                     {
6600                       last_sym = n;
6601                       found = TRUE;
6602                       break;
6603                     }
6604                 }
6605             }
6606
6607           if (found)
6608             private_data->has_mapping_symbols = 1;
6609
6610           /* No mapping symbols were found.  A leading $d may be
6611              omitted for sections which start with data; but for
6612              compatibility with legacy and stripped binaries, only
6613              assume the leading $d if there is at least one mapping
6614              symbol in the file.  */
6615           if (!found && private_data->has_mapping_symbols == -1)
6616             {
6617               /* Look for mapping symbols, in any section.  */
6618               for (n = 0; n < info->symtab_size; n++)
6619                 if (is_mapping_symbol (info, n, &type))
6620                   {
6621                     private_data->has_mapping_symbols = 1;
6622                     break;
6623                   }
6624               if (private_data->has_mapping_symbols == -1)
6625                 private_data->has_mapping_symbols = 0;
6626             }
6627
6628           if (!found && private_data->has_mapping_symbols == 1)
6629             {
6630               type = MAP_DATA;
6631               found = TRUE;
6632             }
6633         }
6634
6635       /* Next search for function symbols to separate ARM from Thumb
6636          in binaries without mapping symbols.  */
6637       if (!found)
6638         {
6639           /* Scan up to the location being disassembled.  */
6640           for (n = start; n < info->symtab_size; n++)
6641             {
6642               addr = bfd_asymbol_value (info->symtab[n]);
6643               if (addr > pc)
6644                 break;
6645               if (get_sym_code_type (info, n, &type))
6646                 {
6647                   last_sym = n;
6648                   found = TRUE;
6649                 }
6650             }
6651
6652           if (!found)
6653             {
6654               /* No mapping symbol found at this address.  Look backwards
6655                  for a preceding one.  */
6656               for (n = start - 1; n >= 0; n--)
6657                 {
6658                   if (get_sym_code_type (info, n, &type))
6659                     {
6660                       last_sym = n;
6661                       found = TRUE;
6662                       break;
6663                     }
6664                 }
6665             }
6666         }
6667
6668       private_data->last_mapping_sym = last_sym;
6669       private_data->last_type = type;
6670       is_thumb = (private_data->last_type == MAP_THUMB);
6671       is_data = (private_data->last_type == MAP_DATA);
6672
6673       /* Look a little bit ahead to see if we should print out
6674          two or four bytes of data.  If there's a symbol,
6675          mapping or otherwise, after two bytes then don't
6676          print more.  */
6677       if (is_data)
6678         {
6679           size = 4 - (pc & 3);
6680           for (n = last_sym + 1; n < info->symtab_size; n++)
6681             {
6682               addr = bfd_asymbol_value (info->symtab[n]);
6683               if (addr > pc
6684                   && (info->section == NULL
6685                       || info->section == info->symtab[n]->section))
6686                 {
6687                   if (addr - pc < size)
6688                     size = addr - pc;
6689                   break;
6690                 }
6691             }
6692           /* If the next symbol is after three bytes, we need to
6693              print only part of the data, so that we can use either
6694              .byte or .short.  */
6695           if (size == 3)
6696             size = (pc & 1) ? 1 : 2;
6697         }
6698     }
6699
6700   if (info->symbols != NULL)
6701     {
6702       if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6703         {
6704           coff_symbol_type * cs;
6705
6706           cs = coffsymbol (*info->symbols);
6707           is_thumb = (   cs->native->u.syment.n_sclass == C_THUMBEXT
6708                       || cs->native->u.syment.n_sclass == C_THUMBSTAT
6709                       || cs->native->u.syment.n_sclass == C_THUMBLABEL
6710                       || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6711                       || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6712         }
6713       else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6714                && !found)
6715         {
6716           /* If no mapping symbol has been found then fall back to the type
6717              of the function symbol.  */
6718           elf_symbol_type *  es;
6719           unsigned int       type;
6720
6721           es = *(elf_symbol_type **)(info->symbols);
6722           type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6723
6724           is_thumb =
6725             ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6726               == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
6727         }
6728       else if (bfd_asymbol_flavour (*info->symbols)
6729                == bfd_target_mach_o_flavour)
6730         {
6731           bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
6732
6733           is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
6734         }
6735     }
6736
6737   if (force_thumb)
6738     is_thumb = TRUE;
6739
6740   if (is_data)
6741     info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6742   else
6743     info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6744
6745   info->bytes_per_line = 4;
6746
6747   /* PR 10263: Disassemble data if requested to do so by the user.  */
6748   if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
6749     {
6750       int i;
6751
6752       /* Size was already set above.  */
6753       info->bytes_per_chunk = size;
6754       printer = print_insn_data;
6755
6756       status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
6757       given = 0;
6758       if (little)
6759         for (i = size - 1; i >= 0; i--)
6760           given = b[i] | (given << 8);
6761       else
6762         for (i = 0; i < (int) size; i++)
6763           given = b[i] | (given << 8);
6764     }
6765   else if (!is_thumb)
6766     {
6767       /* In ARM mode endianness is a straightforward issue: the instruction
6768          is four bytes long and is either ordered 0123 or 3210.  */
6769       printer = print_insn_arm;
6770       info->bytes_per_chunk = 4;
6771       size = 4;
6772
6773       status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
6774       if (little_code)
6775         given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6776       else
6777         given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
6778     }
6779   else
6780     {
6781       /* In Thumb mode we have the additional wrinkle of two
6782          instruction lengths.  Fortunately, the bits that determine
6783          the length of the current instruction are always to be found
6784          in the first two bytes.  */
6785       printer = print_insn_thumb16;
6786       info->bytes_per_chunk = 2;
6787       size = 2;
6788
6789       status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
6790       if (little_code)
6791         given = (b[0]) | (b[1] << 8);
6792       else
6793         given = (b[1]) | (b[0] << 8);
6794
6795       if (!status)
6796         {
6797           /* These bit patterns signal a four-byte Thumb
6798              instruction.  */
6799           if ((given & 0xF800) == 0xF800
6800               || (given & 0xF800) == 0xF000
6801               || (given & 0xF800) == 0xE800)
6802             {
6803               status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
6804               if (little_code)
6805                 given = (b[0]) | (b[1] << 8) | (given << 16);
6806               else
6807                 given = (b[1]) | (b[0] << 8) | (given << 16);
6808
6809               printer = print_insn_thumb32;
6810               size = 4;
6811             }
6812         }
6813
6814       if (ifthen_address != pc)
6815         find_ifthen_state (pc, info, little_code);
6816
6817       if (ifthen_state)
6818         {
6819           if ((ifthen_state & 0xf) == 0x8)
6820             ifthen_next_state = 0;
6821           else
6822             ifthen_next_state = (ifthen_state & 0xe0)
6823                                 | ((ifthen_state & 0xf) << 1);
6824         }
6825     }
6826
6827   if (status)
6828     {
6829       info->memory_error_func (status, pc, info);
6830       return -1;
6831     }
6832   if (info->flags & INSN_HAS_RELOC)
6833     /* If the instruction has a reloc associated with it, then
6834        the offset field in the instruction will actually be the
6835        addend for the reloc.  (We are using REL type relocs).
6836        In such cases, we can ignore the pc when computing
6837        addresses, since the addend is not currently pc-relative.  */
6838     pc = 0;
6839
6840   printer (pc, info, given);
6841
6842   if (is_thumb)
6843     {
6844       ifthen_state = ifthen_next_state;
6845       ifthen_address += size;
6846     }
6847   return size;
6848 }
6849
6850 int
6851 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
6852 {
6853   /* Detect BE8-ness and record it in the disassembler info.  */
6854   if (info->flavour == bfd_target_elf_flavour
6855       && info->section != NULL
6856       && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6857     info->endian_code = BFD_ENDIAN_LITTLE;
6858
6859   return print_insn (pc, info, FALSE);
6860 }
6861
6862 int
6863 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
6864 {
6865   return print_insn (pc, info, TRUE);
6866 }
6867
6868 const disasm_options_and_args_t *
6869 disassembler_options_arm (void)
6870 {
6871   static disasm_options_and_args_t *opts_and_args;
6872
6873   if (opts_and_args == NULL)
6874     {
6875       disasm_options_t *opts;
6876       unsigned int i;
6877
6878       opts_and_args = XNEW (disasm_options_and_args_t);
6879       opts_and_args->args = NULL;
6880
6881       opts = &opts_and_args->options;
6882       opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
6883       opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
6884       opts->arg = NULL;
6885       for (i = 0; i < NUM_ARM_OPTIONS; i++)
6886         {
6887           opts->name[i] = regnames[i].name;
6888           if (regnames[i].description != NULL)
6889             opts->description[i] = _(regnames[i].description);
6890           else
6891             opts->description[i] = NULL;
6892         }
6893       /* The array we return must be NULL terminated.  */
6894       opts->name[i] = NULL;
6895       opts->description[i] = NULL;
6896     }
6897
6898   return opts_and_args;
6899 }
6900
6901 void
6902 print_arm_disassembler_options (FILE *stream)
6903 {
6904   unsigned int i, max_len = 0;
6905   fprintf (stream, _("\n\
6906 The following ARM specific disassembler options are supported for use with\n\
6907 the -M switch:\n"));
6908
6909   for (i = 0; i < NUM_ARM_OPTIONS; i++)
6910     {
6911       unsigned int len = strlen (regnames[i].name);
6912       if (max_len < len)
6913         max_len = len;
6914     }
6915
6916   for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
6917     fprintf (stream, "  %s%*c %s\n",
6918              regnames[i].name,
6919              (int)(max_len - strlen (regnames[i].name)), ' ',
6920              _(regnames[i].description));
6921 }