opcodes/arm-dis.c

   1 /* Instruction printing code for the ARM
   2    Copyright (C) 1994-2019 Free Software Foundation, Inc.
   3    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
   4    Modification by James G. Smith (jsmith@cygnus.co.uk)
   5
   6    This file is part of libopcodes.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include "sysdep.h"
  24 #include <assert.h>
  25
  26 #include "disassemble.h"
  27 #include "opcode/arm.h"
  28 #include "opintl.h"
  29 #include "safe-ctype.h"
  30 #include "libiberty.h"
  31 #include "floatformat.h"
  32
  33 /* FIXME: This shouldn't be done here.  */
  34 #include "coff/internal.h"
  35 #include "libcoff.h"
  36 #include "bfd.h"
  37 #include "elf-bfd.h"
  38 #include "elf/internal.h"
  39 #include "elf/arm.h"
  40 #include "mach-o.h"
  41
  42 /* FIXME: Belongs in global header.  */
  43 #ifndef strneq
  44 #define strneq(a,b,n)   (strncmp ((a), (b), (n)) == 0)
  45 #endif
  46
  47 /* Cached mapping symbol state.  */
  48 enum map_type
  49 {
  50   MAP_ARM,
  51   MAP_THUMB,
  52   MAP_DATA
  53 };
  54
  55 struct arm_private_data
  56 {
  57   /* The features to use when disassembling optional instructions.  */
  58   arm_feature_set features;
  59
  60   /* Track the last type (although this doesn't seem to be useful) */
  61   enum map_type last_type;
  62
  63   /* Tracking symbol table information */
  64   int last_mapping_sym;
  65
  66   /* The end range of the current range being disassembled.  */
  67   bfd_vma last_stop_offset;
  68   bfd_vma last_mapping_addr;
  69 };
  70
  71 enum mve_instructions
  72 {
  73   MVE_VPST,
  74   MVE_VPT_FP_T1,
  75   MVE_VPT_FP_T2,
  76   MVE_VPT_VEC_T1,
  77   MVE_VPT_VEC_T2,
  78   MVE_VPT_VEC_T3,
  79   MVE_VPT_VEC_T4,
  80   MVE_VPT_VEC_T5,
  81   MVE_VPT_VEC_T6,
  82   MVE_VCMP_FP_T1,
  83   MVE_VCMP_FP_T2,
  84   MVE_VCMP_VEC_T1,
  85   MVE_VCMP_VEC_T2,
  86   MVE_VCMP_VEC_T3,
  87   MVE_VCMP_VEC_T4,
  88   MVE_VCMP_VEC_T5,
  89   MVE_VCMP_VEC_T6,
  90   MVE_VDUP,
  91   MVE_VEOR,
  92   MVE_VFMAS_FP_SCALAR,
  93   MVE_VFMA_FP_SCALAR,
  94   MVE_VFMA_FP,
  95   MVE_VFMS_FP,
  96   MVE_VHADD_T1,
  97   MVE_VHADD_T2,
  98   MVE_VHSUB_T1,
  99   MVE_VHSUB_T2,
 100   MVE_VRHADD,
 101   MVE_VLD2,
 102   MVE_VLD4,
 103   MVE_VST2,
 104   MVE_VST4,
 105   MVE_NONE
 106 };
 107
 108 enum mve_unpredictable
 109 {
 110   UNPRED_IT_BLOCK,              /* Unpredictable because mve insn in it block.
 111                                  */
 112   UNPRED_FCA_0_FCB_1,           /* Unpredictable because fcA = 0 and
 113                                    fcB = 1 (vpt).  */
 114   UNPRED_R13,                   /* Unpredictable because r13 (sp) or
 115                                    r15 (sp) used.  */
 116   UNPRED_R15,                   /* Unpredictable because r15 (pc) is used.  */
 117   UNPRED_Q_GT_4,                /* Unpredictable because
 118                                    vec reg start > 4 (vld4/st4).  */
 119   UNPRED_Q_GT_6,                /* Unpredictable because
 120                                    vec reg start > 6 (vld2/st2).  */
 121   UNPRED_R13_AND_WB,            /* Unpredictable becase gp reg = r13
 122                                    and WB bit = 1.  */
 123   UNPRED_NONE                   /* No unpredictable behavior.  */
 124 };
 125
 126 enum mve_undefined
 127 {
 128   UNDEF_SIZE_3,                 /* undefined because size == 3.  */
 129   UNDEF_NONE                    /* no undefined behavior.  */
 130 };
 131
 132 struct opcode32
 133 {
 134   arm_feature_set arch;         /* Architecture defining this insn.  */
 135   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
 136   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
 137   const char *  assembler;      /* How to disassemble this insn.  */
 138 };
 139
 140 /* MVE opcodes.  */
 141
 142 struct mopcode32
 143 {
 144   arm_feature_set arch;         /* Architecture defining this insn.  */
 145   enum mve_instructions mve_op;  /* Specific mve instruction for faster
 146                                     decoding.  */
 147   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
 148   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
 149   const char *  assembler;      /* How to disassemble this insn.  */
 150 };
 151
 152 enum isa {
 153   ANY,
 154   T32,
 155   ARM
 156 };
 157
 158
 159 /* Shared (between Arm and Thumb mode) opcode.  */
 160 struct sopcode32
 161 {
 162   enum isa isa;                 /* Execution mode instruction availability.  */
 163   arm_feature_set arch;         /* Architecture defining this insn.  */
 164   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
 165   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
 166   const char *  assembler;      /* How to disassemble this insn.  */
 167 };
 168
 169 struct opcode16
 170 {
 171   arm_feature_set arch;         /* Architecture defining this insn.  */
 172   unsigned short value, mask;   /* Recognise insn if (op & mask) == value.  */
 173   const char *assembler;        /* How to disassemble this insn.  */
 174 };
 175
 176 /* print_insn_coprocessor recognizes the following format control codes:
 177
 178    %%                   %
 179
 180    %c                   print condition code (always bits 28-31 in ARM mode)
 181    %q                   print shifter argument
 182    %u                   print condition code (unconditional in ARM mode,
 183                           UNPREDICTABLE if not AL in Thumb)
 184    %A                   print address for ldc/stc/ldf/stf instruction
 185    %B                   print vstm/vldm register list
 186    %C                   print vscclrm register list
 187    %I                   print cirrus signed shift immediate: bits 0..3|4..6
 188    %J                   print register for VLDR instruction
 189    %K                   print address for VLDR instruction
 190    %F                   print the COUNT field of a LFM/SFM instruction.
 191    %P                   print floating point precision in arithmetic insn
 192    %Q                   print floating point precision in ldf/stf insn
 193    %R                   print floating point rounding mode
 194
 195    %<bitfield>c         print as a condition code (for vsel)
 196    %<bitfield>r         print as an ARM register
 197    %<bitfield>R         as %<>r but r15 is UNPREDICTABLE
 198    %<bitfield>ru        as %<>r but each u register must be unique.
 199    %<bitfield>d         print the bitfield in decimal
 200    %<bitfield>k         print immediate for VFPv3 conversion instruction
 201    %<bitfield>x         print the bitfield in hex
 202    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
 203    %<bitfield>f         print a floating point constant if >7 else a
 204                         floating point register
 205    %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
 206    %<bitfield>g         print as an iWMMXt 64-bit register
 207    %<bitfield>G         print as an iWMMXt general purpose or control register
 208    %<bitfield>D         print as a NEON D register
 209    %<bitfield>Q         print as a NEON Q register
 210    %<bitfield>V         print as a NEON D or Q register
 211    %<bitfield>E         print a quarter-float immediate value
 212
 213    %y<code>             print a single precision VFP reg.
 214                           Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
 215    %z<code>             print a double precision VFP reg
 216                           Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
 217
 218    %<bitfield>'c        print specified char iff bitfield is all ones
 219    %<bitfield>`c        print specified char iff bitfield is all zeroes
 220    %<bitfield>?ab...    select from array of values in big endian order
 221
 222    %L                   print as an iWMMXt N/M width field.
 223    %Z                   print the Immediate of a WSHUFH instruction.
 224    %l                   like 'A' except use byte offsets for 'B' & 'H'
 225                         versions.
 226    %i                   print 5-bit immediate in bits 8,3..0
 227                         (print "32" when 0)
 228    %r                   print register offset address for wldt/wstr instruction.  */
 229
 230 enum opcode_sentinel_enum
 231 {
 232   SENTINEL_IWMMXT_START = 1,
 233   SENTINEL_IWMMXT_END,
 234   SENTINEL_GENERIC_START
 235 } opcode_sentinels;
 236
 237 #define UNDEFINED_INSTRUCTION      "\t\t; <UNDEFINED> instruction: %0-31x"
 238 #define UNKNOWN_INSTRUCTION_32BIT  "\t\t; <UNDEFINED> instruction: %08x"
 239 #define UNKNOWN_INSTRUCTION_16BIT  "\t\t; <UNDEFINED> instruction: %04x"
 240 #define UNPREDICTABLE_INSTRUCTION  "\t; <UNPREDICTABLE>"
 241
 242 /* Common coprocessor opcodes shared between Arm and Thumb-2.  */
 243
 244 static const struct sopcode32 coprocessor_opcodes[] =
 245 {
 246   /* XScale instructions.  */
 247   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 248     0x0e200010, 0x0fff0ff0,
 249     "mia%c\tacc0, %0-3r, %12-15r"},
 250   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 251     0x0e280010, 0x0fff0ff0,
 252     "miaph%c\tacc0, %0-3r, %12-15r"},
 253   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 254     0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
 255   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 256     0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
 257   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 258     0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
 259
 260   /* Intel Wireless MMX technology instructions.  */
 261   {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
 262   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
 263     0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
 264   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 265     0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
 266   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 267     0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
 268   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 269     0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
 270   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 271     0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
 272   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 273     0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
 274   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 275     0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
 276   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 277     0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
 278   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 279     0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
 280   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 281     0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
 282   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 283     0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
 284   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 285     0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
 286   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 287     0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
 288   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 289     0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
 290   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 291     0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
 292   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 293     0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
 294   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 295     0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
 296   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 297     0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 298   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 299     0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
 300   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 301     0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
 302   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 303     0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
 304   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 305     0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
 306   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 307     0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
 308   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 309     0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
 310   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 311     0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
 312   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 313     0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 314   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 315     0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 316   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 317     0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
 318   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 319     0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
 320   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 321     0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
 322   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 323     0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
 324   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 325     0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
 326   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 327     0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
 328   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 329     0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 330   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 331     0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
 332   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 333     0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 334   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 335     0x0e800120, 0x0f800ff0,
 336     "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 337   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 338     0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 339   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 340     0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
 341   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 342     0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
 343   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 344     0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
 345   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 346     0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
 347   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 348     0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
 349   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 350     0x0e8000a0, 0x0f800ff0,
 351     "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 352   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 353     0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 354   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 355     0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 356   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 357     0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
 358   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 359     0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 360   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 361     0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
 362   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 363     0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 364   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 365     0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
 366   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 367     0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
 368   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 369     0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
 370   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 371     0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
 372   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 373     0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 374   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 375     0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 376   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 377     0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
 378   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 379     0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 380   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 381     0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 382   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 383     0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
 384   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 385     0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 386   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 387     0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 388   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 389     0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
 390   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 391     0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
 392   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 393     0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
 394   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 395     0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 396   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 397     0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
 398   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 399     0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 400   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 401     0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
 402   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 403     0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
 404   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 405     0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
 406   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 407     0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
 408   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 409     0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 410   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 411     0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 412   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 413     0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
 414   {ANY, ARM_FEATURE_CORE_LOW (0),
 415     SENTINEL_IWMMXT_END, 0, "" },
 416
 417   /* Floating point coprocessor (FPA) instructions.  */
 418   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 419     0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 420   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 421     0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 422   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 423     0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 424   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 425     0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 426   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 427     0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 428   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 429     0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 430   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 431     0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
 432   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 433     0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
 434   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 435     0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 436   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 437     0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
 438   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 439     0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
 440   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 441     0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
 442   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 443     0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
 444   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 445     0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
 446   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 447     0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
 448   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 449     0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
 450   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 451     0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
 452   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 453     0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
 454   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 455     0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
 456   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 457     0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
 458   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 459     0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
 460   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 461     0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
 462   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 463     0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
 464   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 465     0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
 466   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 467     0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
 468   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 469     0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
 470   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 471     0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
 472   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 473     0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
 474   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 475     0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
 476   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 477     0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
 478   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 479     0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
 480   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 481     0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
 482   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 483     0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
 484   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 485     0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
 486   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 487     0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
 488   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 489     0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
 490   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 491     0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
 492   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 493     0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
 494   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 495     0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
 496   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 497     0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
 498   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 499     0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
 500   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 501     0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
 502   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 503     0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
 504
 505   /* Armv8.1-M Mainline instructions.  */
 506   {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 507     0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
 508   {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 509     0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
 510
 511   /* ARMv8-M Mainline Security Extensions instructions.  */
 512   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 513     0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
 514   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 515     0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
 516
 517   /* Register load/store.  */
 518   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 519     0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
 520   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 521     0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
 522   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 523     0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
 524   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 525     0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
 526   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 527     0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
 528   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 529     0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
 530   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 531     0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
 532   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 533     0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
 534   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 535     0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
 536   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 537     0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
 538   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 539     0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
 540   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 541     0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
 542   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 543     0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
 544   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 545     0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
 546   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 547     0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
 548   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 549     0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
 550   {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
 551     0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
 552   {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
 553     0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
 554
 555   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 556     0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 557   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 558     0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 559   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 560     0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 561   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 562     0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 563
 564   /* Data transfer between ARM and NEON registers.  */
 565   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 566     0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
 567   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 568     0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
 569   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 570     0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
 571   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 572     0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
 573   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 574     0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
 575   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 576     0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
 577   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 578     0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
 579   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 580     0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
 581   /* Half-precision conversion instructions.  */
 582   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 583     0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
 584   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 585     0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
 586   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 587     0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
 588   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 589     0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
 590
 591   /* Floating point coprocessor (VFP) instructions.  */
 592   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 593     0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
 594   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 595     0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
 596   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 597     0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
 598   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 599     0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
 600   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 601     0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
 602   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 603     0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
 604   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 605     0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
 606   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 607     0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
 608   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 609     0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
 610   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 611     0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
 612   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 613     0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
 614   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 615     0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
 616   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 617     0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
 618   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 619     0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
 620   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 621     0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
 622   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 623     0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
 624   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 625     0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
 626   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 627     0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
 628   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 629     0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
 630   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 631     0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
 632   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 633     0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
 634   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 635     0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
 636   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 637     0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
 638   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 639     0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
 640   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 641     0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
 642   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 643     0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
 644   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 645     0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
 646   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 647     0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
 648   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 649     0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
 650   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 651     0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
 652   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 653     0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
 654   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 655     0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
 656   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 657     0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
 658   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 659     0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
 660   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 661     0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
 662   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 663     0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
 664   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 665     0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
 666   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 667     0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
 668   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 669     0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
 670   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 671     0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
 672   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 673     0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
 674   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 675     0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
 676   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 677     0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
 678   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 679     0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
 680   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 681     0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
 682   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 683     0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
 684   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 685     0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
 686   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 687     0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
 688   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 689     0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
 690   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 691     0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
 692   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 693     0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
 694   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 695     0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
 696   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 697     0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
 698   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 699     0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
 700   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 701     0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
 702   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 703     0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
 704   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 705     0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
 706   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 707     0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
 708   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 709     0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
 710   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 711     0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
 712   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 713     0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
 714   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 715     0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
 716   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 717     0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
 718   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 719     0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
 720   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 721     0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
 722   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 723     0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
 724   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 725     0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
 726   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 727     0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
 728   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 729     0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
 730
 731   /* Cirrus coprocessor instructions.  */
 732   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 733     0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 734   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 735     0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 736   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 737     0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 738   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 739     0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 740   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 741     0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 742   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 743     0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 744   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 745     0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 746   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 747     0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 748   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 749     0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 750   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 751     0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 752   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 753     0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 754   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 755     0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 756   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 757     0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 758   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 759     0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 760   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 761     0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 762   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 763     0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 764   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 765     0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
 766   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 767     0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
 768   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 769     0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
 770   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 771     0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
 772   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 773     0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
 774   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 775     0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
 776   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 777     0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
 778   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 779     0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
 780   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 781     0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
 782   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 783     0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
 784   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 785     0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
 786   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 787     0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
 788   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 789     0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
 790   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 791     0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
 792   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 793     0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
 794   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 795     0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
 796   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 797     0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
 798   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 799     0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
 800   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 801     0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
 802   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 803     0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
 804   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 805     0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
 806   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 807     0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
 808   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 809     0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
 810   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 811     0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
 812   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 813     0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
 814   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 815     0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
 816   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 817     0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
 818   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 819     0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
 820   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 821     0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
 822   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 823     0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
 824   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 825     0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
 826   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 827     0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
 828   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 829     0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
 830   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 831     0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
 832   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 833     0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
 834   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 835     0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
 836   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 837     0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
 838   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 839     0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
 840   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 841     0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
 842   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 843     0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
 844   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 845     0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
 846   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 847     0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
 848   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 849     0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
 850   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 851     0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
 852   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 853     0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
 854   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 855     0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
 856   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 857     0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 858   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 859     0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 860   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 861     0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 862   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 863     0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 864   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 865     0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 866   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 867     0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 868   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 869     0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
 870   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 871     0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
 872   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 873     0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
 874   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 875     0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
 876   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 877     0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 878   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 879     0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 880   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 881     0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 882   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 883     0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 884   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 885     0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 886   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 887     0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 888   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 889     0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 890   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 891     0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 892   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 893     0x0e000600, 0x0ff00f10,
 894     "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 895   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 896     0x0e100600, 0x0ff00f10,
 897     "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 898   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 899     0x0e200600, 0x0ff00f10,
 900     "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 901   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 902     0x0e300600, 0x0ff00f10,
 903     "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 904
 905   /* VFP Fused multiply add instructions.  */
 906   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 907     0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
 908   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 909     0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
 910   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 911     0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
 912   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 913     0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
 914   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 915     0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
 916   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 917     0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
 918   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 919     0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
 920   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 921     0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
 922
 923   /* FP v5.  */
 924   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 925     0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
 926   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 927     0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
 928   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 929     0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
 930   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 931     0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
 932   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 933     0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
 934   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 935     0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
 936   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 937     0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
 938   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 939     0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
 940   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 941     0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
 942   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 943     0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
 944   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 945     0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
 946   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 947     0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
 948
 949   /* Generic coprocessor instructions.  */
 950   {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
 951   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
 952     0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
 953   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
 954     0x0c500000, 0x0ff00000,
 955     "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 956   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 957     0x0e000000, 0x0f000010,
 958     "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 959   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 960     0x0e10f010, 0x0f10f010,
 961     "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
 962   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 963     0x0e100010, 0x0f100010,
 964     "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 965   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 966     0x0e000010, 0x0f100010,
 967     "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 968   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 969     0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
 970   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 971     0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
 972
 973   /* V6 coprocessor instructions.  */
 974   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
 975     0xfc500000, 0xfff00000,
 976     "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 977   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
 978     0xfc400000, 0xfff00000,
 979     "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
 980
 981   /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8.  */
 982   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 983     0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
 984   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 985     0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
 986   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 987     0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
 988   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 989     0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
 990   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 991     0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
 992   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 993     0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
 994   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 995     0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
 996   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 997     0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
 998   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 999     0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1000   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1001     0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1002
1003   /* Dot Product instructions in the space of coprocessor 13.  */
1004   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1005     0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1006   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1007     0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1008
1009   /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8.  */
1010   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1011     0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1012   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1013     0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1014   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1015     0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1016   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1017     0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1018   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1019     0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1020   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1021     0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1022   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1023     0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1024   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1025     0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1026
1027   /* V5 coprocessor instructions.  */
1028   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1029     0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1030   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1031     0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1032   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1033     0xfe000000, 0xff000010,
1034     "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1035   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1036     0xfe000010, 0xff100010,
1037     "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1038   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1039     0xfe100010, 0xff100010,
1040     "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1041
1042   /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1043      cp_num: bit <11:8> == 0b1001.
1044      cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE.  */
1045   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1046     0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1047   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1048     0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1049   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1050     0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1051   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1052     0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1053   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1054     0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1055   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1056     0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1057   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1058     0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1059   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1060     0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1061   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1062     0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1063   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1064     0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1065   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1066     0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1067   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1068     0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1069   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1070     0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1071   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1072     0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1073   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1074     0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1075   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1076     0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1077   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1078     0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1079   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1080     0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1081   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1082     0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1083   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1084     0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1085   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1086     0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1087   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1088     0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1089   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1090     0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1091   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1092     0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1093   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1094     0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1095   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1096     0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1097   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1098     0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1099   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1100     0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1101   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1102     0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1103   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1104     0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1105   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1106     0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1107   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1108     0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1109   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1110     0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1111   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1112     0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1113   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1114     0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1115
1116   /* ARMv8.3 javascript conversion instruction.  */
1117   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1118     0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1119
1120   {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1121 };
1122
1123 /* Neon opcode table:  This does not encode the top byte -- that is
1124    checked by the print_insn_neon routine, as it depends on whether we are
1125    doing thumb32 or arm32 disassembly.  */
1126
1127 /* print_insn_neon recognizes the following format control codes:
1128
1129    %%                   %
1130
1131    %c                   print condition code
1132    %u                   print condition code (unconditional in ARM mode,
1133                           UNPREDICTABLE if not AL in Thumb)
1134    %A                   print v{st,ld}[1234] operands
1135    %B                   print v{st,ld}[1234] any one operands
1136    %C                   print v{st,ld}[1234] single->all operands
1137    %D                   print scalar
1138    %E                   print vmov, vmvn, vorr, vbic encoded constant
1139    %F                   print vtbl,vtbx register list
1140
1141    %<bitfield>r         print as an ARM register
1142    %<bitfield>d         print the bitfield in decimal
1143    %<bitfield>e         print the 2^N - bitfield in decimal
1144    %<bitfield>D         print as a NEON D register
1145    %<bitfield>Q         print as a NEON Q register
1146    %<bitfield>R         print as a NEON D or Q register
1147    %<bitfield>Sn        print byte scaled width limited by n
1148    %<bitfield>Tn        print short scaled width limited by n
1149    %<bitfield>Un        print long scaled width limited by n
1150
1151    %<bitfield>'c        print specified char iff bitfield is all ones
1152    %<bitfield>`c        print specified char iff bitfield is all zeroes
1153    %<bitfield>?ab...    select from array of values in big endian order.  */
1154
1155 static const struct opcode32 neon_opcodes[] =
1156 {
1157   /* Extract.  */
1158   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1159     0xf2b00840, 0xffb00850,
1160     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1161   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1162     0xf2b00000, 0xffb00810,
1163     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1164
1165   /* Data transfer between ARM and NEON registers.  */
1166   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1167     0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1168   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1169     0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1170   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1171     0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1172   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1173     0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1174   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1175     0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1176   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1177     0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1178
1179   /* Move data element to all lanes.  */
1180   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1181     0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1182   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1183     0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1184   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1185     0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1186
1187   /* Table lookup.  */
1188   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1189     0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1190   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1191     0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1192
1193   /* Half-precision conversions.  */
1194   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1195     0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1196   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1197     0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1198
1199   /* NEON fused multiply add instructions.  */
1200   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1201     0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1202   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1203     0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1204   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1205     0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1206   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1207     0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1208
1209   /* Two registers, miscellaneous.  */
1210   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1211     0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1212   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1213     0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1214   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1215     0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1216   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1217     0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1218   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1219     0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1220   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1221     0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1222   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1223     0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1224   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1225     0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1226   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1227     0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1228   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1229     0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1230   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1231     0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1232   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1233     0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1234   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1235     0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1236   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1237     0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1238   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1239     0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1240   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1241     0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1242   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1243     0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1244   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1245     0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1246   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1247     0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1248   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1249     0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1250   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1251     0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1252   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1253     0xf3b20300, 0xffb30fd0,
1254     "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1255   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1256     0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1257   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1258     0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1259   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1260     0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1261   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1262     0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1263   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1264     0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1265   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1266     0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1267   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1268     0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1269   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1270     0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1271   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1272     0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1273   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1274     0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1275   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1276     0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1277   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1278     0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1279   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1280     0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1281   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1282     0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1283   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1284     0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1285   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1286     0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1287   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1288     0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1289   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1290     0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1291   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1292     0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1293   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1294     0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1295   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1296     0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1297   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1298     0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1299   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1300     0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1301   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1302     0xf3bb0600, 0xffbf0e10,
1303     "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1304   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1305     0xf3b70600, 0xffbf0e10,
1306     "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1307
1308   /* Three registers of the same length.  */
1309   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1310     0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1311   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1312     0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1313   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1314     0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1315   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1316     0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1317   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1318     0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1319   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1320     0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1321   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1322     0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1323   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1324     0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1325   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1326     0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1327   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1328     0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1329   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1330     0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1331   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1332     0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1333   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1334     0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1335   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1336     0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1337   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1338     0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1339   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1340     0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1341   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1342     0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1343   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1344     0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1345   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1346     0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1347   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1348     0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1349   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1350     0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1351   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1352     0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1353   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1354     0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1355   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1356     0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1357   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1358     0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1359   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1360     0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1361   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1362     0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1363   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1364     0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1365   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1366     0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1367   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1368     0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1369   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1370     0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1371   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1372     0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1373   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1374     0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1375   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1376     0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1377   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1378     0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1379   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1380     0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1381   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1382     0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1383   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1384     0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1385   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1386     0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1387   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1388     0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1389   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1390     0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1391   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1392     0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1393   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1394     0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1395   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1396     0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1397   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1398     0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1399   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1400     0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1401   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1402     0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1403   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1404     0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1405   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1406     0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1407   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1408     0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1409   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1410     0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1411   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1412     0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1413   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1414     0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1415   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1416     0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1417   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1418     0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1419   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1420     0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1421   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1422     0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1423   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424     0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1425   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1426     0xf2000b00, 0xff800f10,
1427     "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1428   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429     0xf2000b10, 0xff800f10,
1430     "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1431   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1432     0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1433   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1434     0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1435   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436     0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1437   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1438     0xf3000b00, 0xff800f10,
1439     "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1440   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1441     0xf2000000, 0xfe800f10,
1442     "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1443   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1444     0xf2000010, 0xfe800f10,
1445     "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1446   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1447     0xf2000100, 0xfe800f10,
1448     "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1449   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1450     0xf2000200, 0xfe800f10,
1451     "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1452   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1453     0xf2000210, 0xfe800f10,
1454     "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1455   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456     0xf2000300, 0xfe800f10,
1457     "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1458   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1459     0xf2000310, 0xfe800f10,
1460     "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1461   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1462     0xf2000400, 0xfe800f10,
1463     "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1464   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1465     0xf2000410, 0xfe800f10,
1466     "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1467   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1468     0xf2000500, 0xfe800f10,
1469     "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1470   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471     0xf2000510, 0xfe800f10,
1472     "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1473   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1474     0xf2000600, 0xfe800f10,
1475     "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1476   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477     0xf2000610, 0xfe800f10,
1478     "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1479   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1480     0xf2000700, 0xfe800f10,
1481     "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1482   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1483     0xf2000710, 0xfe800f10,
1484     "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1485   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1486     0xf2000910, 0xfe800f10,
1487     "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1488   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1489     0xf2000a00, 0xfe800f10,
1490     "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1491   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492     0xf2000a10, 0xfe800f10,
1493     "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1494   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1495     0xf3000b10, 0xff800f10,
1496     "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1497   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1498     0xf3000c10, 0xff800f10,
1499     "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1500
1501   /* One register and an immediate value.  */
1502   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1503     0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1504   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1505     0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1506   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1507     0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1508   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1509     0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1510   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1511     0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1512   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1513     0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1514   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1515     0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1516   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1517     0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1518   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1519     0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1520   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1521     0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1522   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1523     0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1524   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1525     0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1526   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1527     0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1528
1529   /* Two registers and a shift amount.  */
1530   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1531     0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1532   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1533     0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1534   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1535     0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1536   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1537     0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1538   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1539     0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1540   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1541     0xf2880950, 0xfeb80fd0,
1542     "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1543   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1544     0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1545   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1546     0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1547   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1548     0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1549   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1550     0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1551   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552     0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1553   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1554     0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1555   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1556     0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1557   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1558     0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1559   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1560     0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1561   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1562     0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1563   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1564     0xf2900950, 0xfeb00fd0,
1565     "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1566   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1567     0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1568   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1569     0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1570   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1571     0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1572   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1573     0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1574   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1575     0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1576   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1577     0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1578   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1579     0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1580   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1581     0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1582   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1583     0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1584   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1585     0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1586   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1587     0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1588   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1589     0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1590   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1591     0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1592   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1593     0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1594   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1595     0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1596   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1597     0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1598   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1599     0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1600   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1601     0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1602   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1603     0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1604   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1605     0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1606   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1607     0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1608   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1609     0xf2a00950, 0xfea00fd0,
1610     "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1611   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1612     0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1613   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1614     0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1615   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1616     0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1617   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618     0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1619   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1620     0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1621   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1622     0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1623   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1624     0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1625   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626     0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1627   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628     0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1629   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630     0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1631   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1632     0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1633   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1634     0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1635   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1636     0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1637   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638     0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1639   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1640     0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1641   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1642     0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1643   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1644     0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1645   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1646     0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1647   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1648     0xf2a00e10, 0xfea00e90,
1649     "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1650   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1651     0xf2a00c10, 0xfea00e90,
1652     "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1653
1654   /* Three registers of different lengths.  */
1655   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1656     0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1657   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1658     0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1659   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1660     0xf2800400, 0xff800f50,
1661     "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1662   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1663     0xf2800600, 0xff800f50,
1664     "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1665   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1666     0xf2800900, 0xff800f50,
1667     "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1668   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1669     0xf2800b00, 0xff800f50,
1670     "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1671   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1672     0xf2800d00, 0xff800f50,
1673     "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1674   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1675     0xf3800400, 0xff800f50,
1676     "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1677   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1678     0xf3800600, 0xff800f50,
1679     "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1680   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1681     0xf2800000, 0xfe800f50,
1682     "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1683   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1684     0xf2800100, 0xfe800f50,
1685     "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1686   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1687     0xf2800200, 0xfe800f50,
1688     "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1689   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1690     0xf2800300, 0xfe800f50,
1691     "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1692   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1693     0xf2800500, 0xfe800f50,
1694     "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1695   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1696     0xf2800700, 0xfe800f50,
1697     "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1698   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1699     0xf2800800, 0xfe800f50,
1700     "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1701   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1702     0xf2800a00, 0xfe800f50,
1703     "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1704   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1705     0xf2800c00, 0xfe800f50,
1706     "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1707
1708   /* Two registers and a scalar.  */
1709   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1710     0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1711   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1712     0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1713   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1714     0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1715   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1716     0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1717   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1718     0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1719   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1720     0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1721   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1722     0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1723   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1724     0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1725   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1726     0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1727   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1728     0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1729   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1730     0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1731   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1732     0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1733   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1734     0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1735   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1736     0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1737   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1738     0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1739   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1740     0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1741   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1742     0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1743   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1744     0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1745   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1746     0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1747   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1748     0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1749   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1750     0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1751   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1752     0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1753   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1754     0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1755   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1756     0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1757   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1758     0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1759   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1760     0xf2800240, 0xfe800f50,
1761     "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1762   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1763     0xf2800640, 0xfe800f50,
1764     "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1765   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1766     0xf2800a40, 0xfe800f50,
1767     "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1768   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1769     0xf2800e40, 0xff800f50,
1770    "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1771   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1772     0xf2800f40, 0xff800f50,
1773    "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1774   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1775     0xf3800e40, 0xff800f50,
1776    "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1777   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1778     0xf3800f40, 0xff800f50,
1779    "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1780   },
1781
1782   /* Element and structure load/store.  */
1783   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1784     0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1785   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1786     0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1787   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1788     0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1789   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1790     0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1791   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1792     0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1793   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794     0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1795   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1796     0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1797   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1798     0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1799   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800     0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1801   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1802     0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1803   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1804     0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1805   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1806     0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1807   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1808     0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1809   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1810     0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1811   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1812     0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1813   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1814     0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1815   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1816     0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1817   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1818     0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1819   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1820     0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1821
1822   {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1823 };
1824
1825 /* mve opcode table.  */
1826
1827 /* print_insn_mve recognizes the following format control codes:
1828
1829    %%                   %
1830
1831    %c                   print condition code
1832    %i                   print MVE predicate(s) for vpt and vpst
1833    %n                   print vector comparison code for predicated instruction
1834    %v                   print vector predicate for instruction in predicated
1835                         block
1836    %w                   print writeback mode for MVE v{st,ld}[24]
1837    %B                   print v{st,ld}[24] any one operands
1838
1839    %<bitfield>r         print as an ARM register
1840    %<bitfield>d         print the bitfield in decimal
1841    %<bitfield>Q         print as a MVE Q register
1842    %<bitfield>Z         as %<>r but r15 is ZR instead of PC and r13 is
1843                         UNPREDICTABLE
1844    %<bitfield>s         print size for vector predicate & non VMOV instructions
1845 */
1846
1847 static const struct mopcode32 mve_opcodes[] =
1848 {
1849   /* MVE.  */
1850
1851   {ARM_FEATURE_COPROC (FPU_MVE),
1852    MVE_VPST,
1853    0xfe310f4d, 0xffbf1fff,
1854    "vpst%i"
1855   },
1856
1857   /* Floating point VPT T1.  */
1858   {ARM_FEATURE_COPROC (FPU_MVE_FP),
1859    MVE_VPT_FP_T1,
1860    0xee310f00, 0xefb10f50,
1861    "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
1862   /* Floating point VPT T2.  */
1863   {ARM_FEATURE_COPROC (FPU_MVE_FP),
1864    MVE_VPT_FP_T2,
1865    0xee310f40, 0xefb10f50,
1866    "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
1867
1868   /* Vector VPT T1.  */
1869   {ARM_FEATURE_COPROC (FPU_MVE),
1870    MVE_VPT_VEC_T1,
1871    0xfe010f00, 0xff811f51,
1872    "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
1873   /* Vector VPT T2.  */
1874   {ARM_FEATURE_COPROC (FPU_MVE),
1875    MVE_VPT_VEC_T2,
1876    0xfe010f01, 0xff811f51,
1877    "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
1878   /* Vector VPT T3.  */
1879   {ARM_FEATURE_COPROC (FPU_MVE),
1880    MVE_VPT_VEC_T3,
1881    0xfe011f00, 0xff811f50,
1882    "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
1883   /* Vector VPT T4.  */
1884   {ARM_FEATURE_COPROC (FPU_MVE),
1885    MVE_VPT_VEC_T4,
1886    0xfe010f40, 0xff811f70,
1887    "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
1888   /* Vector VPT T5.  */
1889   {ARM_FEATURE_COPROC (FPU_MVE),
1890    MVE_VPT_VEC_T5,
1891    0xfe010f60, 0xff811f70,
1892    "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
1893   /* Vector VPT T6.  */
1894   {ARM_FEATURE_COPROC (FPU_MVE),
1895    MVE_VPT_VEC_T6,
1896    0xfe011f40, 0xff811f50,
1897    "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
1898
1899   /* Vector VCMP floating point T1.  */
1900   {ARM_FEATURE_COPROC (FPU_MVE_FP),
1901    MVE_VCMP_FP_T1,
1902    0xee310f00, 0xeff1ef50,
1903    "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
1904
1905   /* Vector VCMP floating point T2.  */
1906   {ARM_FEATURE_COPROC (FPU_MVE_FP),
1907    MVE_VCMP_FP_T2,
1908    0xee310f40, 0xeff1ef50,
1909    "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
1910
1911   /* Vector VCMP T1.  */
1912   {ARM_FEATURE_COPROC (FPU_MVE),
1913    MVE_VCMP_VEC_T1,
1914    0xfe010f00, 0xffc1ff51,
1915    "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
1916   /* Vector VCMP T2.  */
1917   {ARM_FEATURE_COPROC (FPU_MVE),
1918    MVE_VCMP_VEC_T2,
1919    0xfe010f01, 0xffc1ff51,
1920    "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
1921   /* Vector VCMP T3.  */
1922   {ARM_FEATURE_COPROC (FPU_MVE),
1923    MVE_VCMP_VEC_T3,
1924    0xfe011f00, 0xffc1ff50,
1925    "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
1926   /* Vector VCMP T4.  */
1927   {ARM_FEATURE_COPROC (FPU_MVE),
1928    MVE_VCMP_VEC_T4,
1929    0xfe010f40, 0xffc1ff70,
1930    "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
1931   /* Vector VCMP T5.  */
1932   {ARM_FEATURE_COPROC (FPU_MVE),
1933    MVE_VCMP_VEC_T5,
1934    0xfe010f60, 0xffc1ff70,
1935    "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
1936   /* Vector VCMP T6.  */
1937   {ARM_FEATURE_COPROC (FPU_MVE),
1938    MVE_VCMP_VEC_T6,
1939    0xfe011f40, 0xffc1ff50,
1940    "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
1941
1942   /* Vector VDUP.  */
1943   {ARM_FEATURE_COPROC (FPU_MVE),
1944    MVE_VDUP,
1945    0xeea00b10, 0xffb10f5f,
1946    "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
1947
1948   /* Vector VEOR.  */
1949   {ARM_FEATURE_COPROC (FPU_MVE),
1950    MVE_VEOR,
1951    0xff000150, 0xffd11f51,
1952    "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
1953
1954   /* Vector VFMA, vector * scalar.  */
1955   {ARM_FEATURE_COPROC (FPU_MVE_FP),
1956    MVE_VFMA_FP_SCALAR,
1957    0xee310e40, 0xefb11f70,
1958    "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
1959
1960   /* Vector VFMA floating point.  */
1961   {ARM_FEATURE_COPROC (FPU_MVE_FP),
1962    MVE_VFMA_FP,
1963    0xef000c50, 0xffa11f51,
1964    "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
1965
1966   /* Vector VFMS floating point.  */
1967   {ARM_FEATURE_COPROC (FPU_MVE_FP),
1968    MVE_VFMS_FP,
1969    0xef200c50, 0xffa11f51,
1970    "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
1971
1972   /* Vector VFMAS, vector * scalar.  */
1973   {ARM_FEATURE_COPROC (FPU_MVE_FP),
1974    MVE_VFMAS_FP_SCALAR,
1975    0xee311e40, 0xefb11f70,
1976    "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
1977
1978   /* Vector VHADD T1.  */
1979   {ARM_FEATURE_COPROC (FPU_MVE),
1980    MVE_VHADD_T1,
1981    0xef000040, 0xef811f51,
1982    "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
1983
1984   /* Vector VHADD T2.  */
1985   {ARM_FEATURE_COPROC (FPU_MVE),
1986    MVE_VHADD_T2,
1987    0xee000f40, 0xef811f70,
1988    "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
1989
1990   /* Vector VHSUB T1.  */
1991   {ARM_FEATURE_COPROC (FPU_MVE),
1992    MVE_VHSUB_T1,
1993    0xef000240, 0xef811f51,
1994    "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
1995
1996   /* Vector VHSUB T2.  */
1997   {ARM_FEATURE_COPROC (FPU_MVE),
1998    MVE_VHSUB_T2,
1999    0xee001f40, 0xef811f70,
2000    "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2001
2002   /* Vector VDUP.  */
2003   {ARM_FEATURE_COPROC (FPU_MVE),
2004    MVE_VDUP,
2005    0xeea00b10, 0xffb10f5f,
2006    "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2007
2008   /* Vector VRHADD.  */
2009   {ARM_FEATURE_COPROC (FPU_MVE),
2010    MVE_VRHADD,
2011    0xef000140, 0xef811f51,
2012    "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2013
2014   /* Vector VLD2.  */
2015   {ARM_FEATURE_COPROC (FPU_MVE),
2016    MVE_VLD2,
2017    0xfc901e00, 0xff901e5f,
2018    "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2019
2020   /* Vector VLD4.  */
2021   {ARM_FEATURE_COPROC (FPU_MVE),
2022    MVE_VLD4,
2023    0xfc901e01, 0xff901e1f,
2024    "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2025
2026   /* Vector VST2 no writeback.  */
2027   {ARM_FEATURE_COPROC (FPU_MVE),
2028    MVE_VST2,
2029    0xfc801e00, 0xffb01e5f,
2030    "vst2%5d.%7-8s\t%B, [%16-19r]"},
2031
2032   /* Vector VST2 writeback.  */
2033   {ARM_FEATURE_COPROC (FPU_MVE),
2034    MVE_VST2,
2035    0xfca01e00, 0xffb01e5f,
2036    "vst2%5d.%7-8s\t%B, [%16-19r]!"},
2037
2038   /* Vector VST4 no writeback.  */
2039   {ARM_FEATURE_COPROC (FPU_MVE),
2040    MVE_VST4,
2041    0xfc801e01, 0xffb01e1f,
2042    "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
2043
2044   /* Vector VST4 writeback.  */
2045   {ARM_FEATURE_COPROC (FPU_MVE),
2046    MVE_VST4,
2047    0xfca01e01, 0xffb01e1f,
2048    "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
2049
2050   {ARM_FEATURE_CORE_LOW (0),
2051    MVE_NONE,
2052    0x00000000, 0x00000000, 0}
2053 };
2054
2055 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb.  All three are partially
2056    ordered: they must be searched linearly from the top to obtain a correct
2057    match.  */
2058
2059 /* print_insn_arm recognizes the following format control codes:
2060
2061    %%                   %
2062
2063    %a                   print address for ldr/str instruction
2064    %s                   print address for ldr/str halfword/signextend instruction
2065    %S                   like %s but allow UNPREDICTABLE addressing
2066    %b                   print branch destination
2067    %c                   print condition code (always bits 28-31)
2068    %m                   print register mask for ldm/stm instruction
2069    %o                   print operand2 (immediate or register + shift)
2070    %p                   print 'p' iff bits 12-15 are 15
2071    %t                   print 't' iff bit 21 set and bit 24 clear
2072    %B                   print arm BLX(1) destination
2073    %C                   print the PSR sub type.
2074    %U                   print barrier type.
2075    %P                   print address for pli instruction.
2076
2077    %<bitfield>r         print as an ARM register
2078    %<bitfield>T         print as an ARM register + 1
2079    %<bitfield>R         as %r but r15 is UNPREDICTABLE
2080    %<bitfield>{r|R}u    as %{r|R} but if matches the other %u field then is UNPREDICTABLE
2081    %<bitfield>{r|R}U    as %{r|R} but if matches the other %U field then is UNPREDICTABLE
2082    %<bitfield>d         print the bitfield in decimal
2083    %<bitfield>W         print the bitfield plus one in decimal
2084    %<bitfield>x         print the bitfield in hex
2085    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
2086
2087    %<bitfield>'c        print specified char iff bitfield is all ones
2088    %<bitfield>`c        print specified char iff bitfield is all zeroes
2089    %<bitfield>?ab...    select from array of values in big endian order
2090
2091    %e                   print arm SMI operand (bits 0..7,8..19).
2092    %E                   print the LSB and WIDTH fields of a BFI or BFC instruction.
2093    %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.
2094    %R                   print the SPSR/CPSR or banked register of an MRS.  */
2095
2096 static const struct opcode32 arm_opcodes[] =
2097 {
2098   /* ARM instructions.  */
2099   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2100     0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
2101   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2102     0xe7f000f0, 0xfff000f0, "udf\t#%e"},
2103
2104   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
2105     0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
2106   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
2107     0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
2108   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
2109     0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2110   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
2111     0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
2112   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
2113     0x00800090, 0x0fa000f0,
2114     "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2115   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
2116     0x00a00090, 0x0fa000f0,
2117     "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2118
2119   /* V8.2 RAS extension instructions.  */
2120   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
2121     0xe320f010, 0xffffffff, "esb"},
2122
2123   /* V8 instructions.  */
2124   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2125     0x0320f005, 0x0fffffff, "sevl"},
2126   /* Defined in V8 but is in NOP space so available to all arch.  */
2127   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2128     0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
2129   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
2130     0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
2131   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2132     0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2133   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2134     0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
2135   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2136     0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
2137   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2138     0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
2139   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2140     0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2141   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2142     0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
2143   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2144     0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2145   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2146     0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
2147   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2148     0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
2149   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2150     0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
2151   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2152     0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2153   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2154     0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
2155   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
2156     0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2157   /* CRC32 instructions.  */
2158   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2159     0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
2160   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2161     0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
2162   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2163     0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
2164   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2165     0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
2166   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2167     0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
2168   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2169     0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
2170
2171   /* Privileged Access Never extension instructions.  */
2172   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
2173     0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
2174
2175   /* Virtualization Extension instructions.  */
2176   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
2177   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
2178
2179   /* Integer Divide Extension instructions.  */
2180   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
2181     0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
2182   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
2183     0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
2184
2185   /* MP Extension instructions.  */
2186   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
2187
2188   /* Speculation Barriers.  */
2189   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
2190   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
2191   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
2192
2193   /* V7 instructions.  */
2194   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
2195   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
2196   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
2197   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
2198   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
2199   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
2200   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
2201    {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2202     0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
2203
2204   /* ARM V6T2 instructions.  */
2205   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2206     0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
2207   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2208     0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
2209   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2210     0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2211   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2212     0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
2213
2214   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2215     0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
2216   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2217     0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
2218
2219   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2220     0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
2221   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2222     0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
2223   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2224     0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
2225   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2226     0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
2227
2228   /* ARM Security extension instructions.  */
2229   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
2230     0x01600070, 0x0ff000f0, "smc%c\t%e"},
2231
2232   /* ARM V6K instructions.  */
2233   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2234     0xf57ff01f, 0xffffffff, "clrex"},
2235   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2236     0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
2237   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2238     0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
2239   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2240     0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
2241   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2242     0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
2243   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2244     0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
2245   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2246     0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
2247
2248   /* ARMv8.5-A instructions.  */
2249   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
2250
2251   /* ARM V6K NOP hints.  */
2252   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2253     0x0320f001, 0x0fffffff, "yield%c"},
2254   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2255     0x0320f002, 0x0fffffff, "wfe%c"},
2256   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2257     0x0320f003, 0x0fffffff, "wfi%c"},
2258   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2259     0x0320f004, 0x0fffffff, "sev%c"},
2260   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2261     0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
2262
2263   /* ARM V6 instructions.  */
2264   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2265     0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
2266   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2267     0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
2268   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2269     0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
2270   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2271     0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
2272   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2273     0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
2274   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2275     0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
2276   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2277     0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
2278   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2279     0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
2280   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2281     0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
2282   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2283     0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
2284   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2285     0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
2286   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2287     0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
2288   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2289     0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
2290   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2291     0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
2292   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2293     0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
2294   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2295     0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
2296   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2297     0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
2298   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2299     0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
2300   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2301     0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
2302   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2303     0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
2304   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2305     0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
2306   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2307     0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
2308   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2309     0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
2310   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2311     0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
2312   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2313     0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
2314   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2315     0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
2316   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2317     0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
2318   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2319     0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
2320   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2321     0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
2322   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2323     0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
2324   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2325     0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
2326   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2327     0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
2328   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2329     0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
2330   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2331     0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
2332   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2333     0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
2334   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2335     0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
2336   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2337     0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
2338   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2339     0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
2340   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2341     0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
2342   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2343     0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
2344   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2345     0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
2346   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2347     0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2348   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2349     0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2350   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2351     0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2352   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2353     0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2354   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2355     0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2356   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2357     0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2358   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2359     0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2360   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2361     0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2362   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2363     0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
2364   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2365     0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2366   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2367     0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2368   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2369     0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2370   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2371     0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2372   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2373     0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2374   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2375     0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2376   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2377     0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2378   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2379     0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2380   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2381     0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2382   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2383     0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2384   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2385     0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2386   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2387     0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2388   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2389     0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2390   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2391     0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2392   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2393     0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2394   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2395     0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2396   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2397     0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2398   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2399     0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2400   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2401     0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2402   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2403     0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2404   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2405     0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2406   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2407     0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2408   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2409     0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2410   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2411     0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2412   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2413     0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2414   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2415     0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2416   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2417     0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2418   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2419     0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2420   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2421     0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2422   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2423     0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2424   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2425     0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2426   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2427     0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2428   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2429     0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2430   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2431     0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2432   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2433     0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2434   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2435     0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2436   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2437     0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2438   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2439     0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2440   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2441     0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2442   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2443     0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2444   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2445     0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2446   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2447     0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2448   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2449     0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2450   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2451     0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2452   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2453     0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2454   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2455     0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2456   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2457     0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2458   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2459     0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2460   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2461     0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2462   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2463     0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2464   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2465     0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2466   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2467     0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2468   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2469     0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2470   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2471     0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2472   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2473     0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2474   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2475     0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2476   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2477     0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2478   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2479     0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2480   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2481     0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2482   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2483     0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2484   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2485     0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2486   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2487     0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2488   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2489     0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2490   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2491     0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2492   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2493     0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2494   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2495     0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2496   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2497     0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2498   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2499     0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2500   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2501     0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2502   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2503     0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2504   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2505     0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2506   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2507     0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
2508
2509   /* V5J instruction.  */
2510   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2511     0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
2512
2513   /* V5 Instructions.  */
2514   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2515     0xe1200070, 0xfff000f0,
2516     "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2517   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2518     0xfa000000, 0xfe000000, "blx\t%B"},
2519   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2520     0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2521   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2522     0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2523
2524   /* V5E "El Segundo" Instructions.  */
2525   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2526     0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2527   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2528     0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2529   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2530     0xf450f000, 0xfc70f000, "pld\t%a"},
2531   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2532     0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2533   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2534     0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2535   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2536     0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2537   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2538     0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2539
2540   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2541     0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2542   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2543     0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2544
2545   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2546     0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2547   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2548     0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2549   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2550     0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2551   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2552     0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2553
2554   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2555     0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2556   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2557     0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2558   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2559     0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2560   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2561     0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2562
2563   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2564     0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2565   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2566     0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2567
2568   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2569     0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15R, %0-3R, %16-19R"},
2570   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2571     0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2572   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2573     0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15R, %0-3R, %16-19R"},
2574   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2575     0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
2576
2577   /* ARM Instructions.  */
2578   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2579     0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2580
2581   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2582     0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2583   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2584     0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2585   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2586     0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2587   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2588     0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2589   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2590     0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2591   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2592     0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2593
2594   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2595     0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2596   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2597     0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2598   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2599     0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2600   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2601     0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2602
2603   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2604     0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2605   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2606     0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2607   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2608     0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2609   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2610     0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2611
2612   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2613     0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2614   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2615     0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2616   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2617     0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2618
2619   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2620     0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2621   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2622     0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2623   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2624     0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2625
2626   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2627     0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2628   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2629     0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2630   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2631     0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2632
2633   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2634     0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2635   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2636     0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2637   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2638     0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2639
2640   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2641     0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2642   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2643     0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2644   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2645     0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2646
2647   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2648     0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2649   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2650     0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2651   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2652     0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2653
2654   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2655     0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2656   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2657     0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2658   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2659     0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2660
2661   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2662     0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2663   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2664     0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2665   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2666     0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2667
2668   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2669     0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2670   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2671     0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2672   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2673     0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2674
2675   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2676     0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2677   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2678     0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2679   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2680     0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2681
2682   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2683     0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
2684   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2685     0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
2686   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2687     0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
2688
2689   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2690     0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2691   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2692     0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2693   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2694     0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2695
2696   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2697     0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2698   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2699     0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2700   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2701     0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2702
2703   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2704     0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2705   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2706     0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2707   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2708     0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2709
2710   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2711     0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2712   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2713     0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2714   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2715     0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2716   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2717     0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2718   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2719     0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2720   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2721     0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2722   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2723     0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2724
2725   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2726     0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2727   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2728     0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2729   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2730     0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2731
2732   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2733     0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2734   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2735     0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2736   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2737     0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2738
2739   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2740     0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2741   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2742     0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2743
2744   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2745     0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2746
2747   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2748     0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2749   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2750     0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2751
2752   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2753     0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2754   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2755     0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2756   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2757     0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2758   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2759     0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2760   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2761     0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2762   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2763     0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2764   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2765     0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2766   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2767     0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2768   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2769     0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2770   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2771     0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2772   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2773     0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2774   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2775     0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2776   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2777     0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2778   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2779     0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2780   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2781     0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2782   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2783     0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2784   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2785     0x092d0000, 0x0fff0000, "push%c\t%m"},
2786   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2787     0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2788   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2789     0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2790
2791   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2792     0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2793   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2794     0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2795   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2796     0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2797   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2798     0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2799   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2800     0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2801   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2802     0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2803   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2804     0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2805   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2806     0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2807   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2808     0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2809   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2810     0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2811   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2812     0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2813   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2814     0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2815   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2816     0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2817   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2818     0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2819   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2820     0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2821   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2822     0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2823   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2824     0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2825   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2826     0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2827   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2828     0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2829
2830   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2831     0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2832   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2833     0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
2834
2835   /* The rest.  */
2836   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2837     0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
2838   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2839     0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2840   {ARM_FEATURE_CORE_LOW (0),
2841     0x00000000, 0x00000000, 0}
2842 };
2843
2844 /* print_insn_thumb16 recognizes the following format control codes:
2845
2846    %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
2847    %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
2848    %<bitfield>I         print bitfield as a signed decimal
2849                                 (top bit of range being the sign bit)
2850    %N                   print Thumb register mask (with LR)
2851    %O                   print Thumb register mask (with PC)
2852    %M                   print Thumb register mask
2853    %b                   print CZB's 6-bit unsigned branch destination
2854    %s                   print Thumb right-shift immediate (6..10; 0 == 32).
2855    %c                   print the condition code
2856    %C                   print the condition code, or "s" if not conditional
2857    %x                   print warning if conditional an not at end of IT block"
2858    %X                   print "\t; unpredictable <IT:code>" if conditional
2859    %I                   print IT instruction suffix and operands
2860    %W                   print Thumb Writeback indicator for LDMIA
2861    %<bitfield>r         print bitfield as an ARM register
2862    %<bitfield>d         print bitfield as a decimal
2863    %<bitfield>H         print (bitfield * 2) as a decimal
2864    %<bitfield>W         print (bitfield * 4) as a decimal
2865    %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
2866    %<bitfield>B         print Thumb branch destination (signed displacement)
2867    %<bitfield>c         print bitfield as a condition code
2868    %<bitnum>'c          print specified char iff bit is one
2869    %<bitnum>?ab         print a if bit is one else print b.  */
2870
2871 static const struct opcode16 thumb_opcodes[] =
2872 {
2873   /* Thumb instructions.  */
2874
2875   /* ARMv8-M Security Extensions instructions.  */
2876   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
2877   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
2878
2879   /* ARM V8 instructions.  */
2880   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xbf50, 0xffff, "sevl%c"},
2881   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xba80, 0xffc0, "hlt\t%0-5x"},
2882   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),  0xb610, 0xfff7, "setpan\t#%3-3d"},
2883
2884   /* ARM V6K no-argument instructions.  */
2885   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2886   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2887   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2888   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2889   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2890   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
2891
2892   /* ARM V6T2 instructions.  */
2893   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2894     0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2895   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2896     0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
2897   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
2898
2899   /* ARM V6.  */
2900   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2901   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2902   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2903   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2904   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2905   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2906   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2907   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2908   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2909   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2910   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
2911
2912   /* ARM V5 ISA extends Thumb.  */
2913   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2914     0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
2915   /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
2916   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2917     0x4780, 0xff87, "blx%c\t%3-6r%x"},  /* note: 4 bit register number.  */
2918   /* ARM V4T ISA (Thumb v1).  */
2919   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2920     0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
2921   /* Format 4.  */
2922   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2923   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2924   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2925   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2926   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2927   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2928   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2929   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2930   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2931   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2932   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2933   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2934   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2935   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2936   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2937   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
2938   /* format 13 */
2939   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2940   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
2941   /* format 5 */
2942   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2943   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2944   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2945   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
2946   /* format 14 */
2947   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2948   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
2949   /* format 2 */
2950   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2951     0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2952   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2953     0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2954   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2955     0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2956   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2957     0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
2958   /* format 8 */
2959   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2960     0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2961   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2962     0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2963   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2964     0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
2965   /* format 7 */
2966   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2967     0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2968   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2969     0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2970   /* format 1 */
2971   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2972   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2973     0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2974   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2975   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
2976   /* format 3 */
2977   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2978   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2979   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2980   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
2981   /* format 6 */
2982   /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2983   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2984     0x4800, 0xF800,
2985     "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
2986   /* format 9 */
2987   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2988     0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2989   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2990     0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2991   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2992     0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2993   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2994     0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
2995   /* format 10 */
2996   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2997     0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2998   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2999     0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
3000   /* format 11 */
3001   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3002     0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
3003   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3004     0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
3005   /* format 12 */
3006   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3007     0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
3008   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3009     0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
3010   /* format 15 */
3011   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
3012   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
3013   /* format 17 */
3014   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
3015   /* format 16 */
3016   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
3017   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
3018   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
3019   /* format 18 */
3020   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
3021
3022   /* The E800 .. FFFF range is unconditionally redirected to the
3023      32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
3024      are processed via that table.  Thus, we can never encounter a
3025      bare "second half of BL/BLX(1)" instruction here.  */
3026   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),  0x0000, 0x0000, UNDEFINED_INSTRUCTION},
3027   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3028 };
3029
3030 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
3031    We adopt the convention that hw1 is the high 16 bits of .value and
3032    .mask, hw2 the low 16 bits.
3033
3034    print_insn_thumb32 recognizes the following format control codes:
3035
3036        %%               %
3037
3038        %I               print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
3039        %M               print a modified 12-bit immediate (same location)
3040        %J               print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
3041        %K               print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
3042        %H               print a 16-bit immediate from hw2[3:0],hw1[11:0]
3043        %S               print a possibly-shifted Rm
3044
3045        %L               print address for a ldrd/strd instruction
3046        %a               print the address of a plain load/store
3047        %w               print the width and signedness of a core load/store
3048        %m               print register mask for ldm/stm
3049        %n               print register mask for clrm
3050
3051        %E               print the lsb and width fields of a bfc/bfi instruction
3052        %F               print the lsb and width fields of a sbfx/ubfx instruction
3053        %G               print a fallback offset for Branch Future instructions
3054        %W               print an offset for BF instruction
3055        %Y               print an offset for BFL instruction
3056        %Z               print an offset for BFCSEL instruction
3057        %Q               print an offset for Low Overhead Loop instructions
3058        %P               print an offset for Low Overhead Loop end instructions
3059        %b               print a conditional branch offset
3060        %B               print an unconditional branch offset
3061        %s               print the shift field of an SSAT instruction
3062        %R               print the rotation field of an SXT instruction
3063        %U               print barrier type.
3064        %P               print address for pli instruction.
3065        %c               print the condition code
3066        %x               print warning if conditional an not at end of IT block"
3067        %X               print "\t; unpredictable <IT:code>" if conditional
3068
3069        %<bitfield>d     print bitfield in decimal
3070        %<bitfield>D     print bitfield plus one in decimal
3071        %<bitfield>W     print bitfield*4 in decimal
3072        %<bitfield>r     print bitfield as an ARM register
3073        %<bitfield>R     as %<>r but r15 is UNPREDICTABLE
3074        %<bitfield>S     as %<>r but r13 and r15 is UNPREDICTABLE
3075        %<bitfield>c     print bitfield as a condition code
3076
3077        %<bitfield>'c    print specified char iff bitfield is all ones
3078        %<bitfield>`c    print specified char iff bitfield is all zeroes
3079        %<bitfield>?ab... select from array of values in big endian order
3080
3081    With one exception at the bottom (done because BL and BLX(1) need
3082    to come dead last), this table was machine-sorted first in
3083    decreasing order of number of bits set in the mask, then in
3084    increasing numeric order of mask, then in increasing numeric order
3085    of opcode.  This order is not the clearest for a human reader, but
3086    is guaranteed never to catch a special-case bit pattern with a more
3087    general mask, which is important, because this instruction encoding
3088    makes heavy use of special-case bit patterns.  */
3089 static const struct opcode32 thumb32_opcodes[] =
3090 {
3091   /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
3092      instructions.  */
3093   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3094     0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
3095   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3096     0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
3097   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3098     0xf02fc001, 0xfffff001, "le\t%P"},
3099   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3100     0xf00fc001, 0xfffff001, "le\tlr, %P"},
3101
3102   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3103     0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
3104   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3105     0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
3106   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3107     0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
3108   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3109     0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
3110   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3111     0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
3112
3113   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3114     0xe89f0000, 0xffff2000, "clrm%c\t%n"},
3115
3116   /* ARMv8-M and ARMv8-M Security Extensions instructions.  */
3117   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
3118   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3119     0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
3120   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3121     0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
3122   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3123     0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
3124   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3125     0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
3126
3127   /* ARM V8.2 RAS extension instructions.  */
3128   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
3129     0xf3af8010, 0xffffffff, "esb"},
3130
3131   /* V8 instructions.  */
3132   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3133     0xf3af8005, 0xffffffff, "sevl%c.w"},
3134   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3135     0xf78f8000, 0xfffffffc, "dcps%0-1d"},
3136   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3137     0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
3138   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3139     0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
3140   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3141     0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
3142   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3143     0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
3144   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3145     0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
3146   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3147     0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
3148   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3149     0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
3150   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3151     0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3152   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3153     0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3154   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3155     0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
3156   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3157     0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3158   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3159     0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3160   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3161     0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3162   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3163     0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
3164
3165   /* CRC32 instructions.  */
3166   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3167     0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
3168   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3169     0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
3170   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3171     0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
3172   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3173     0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
3174   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3175     0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
3176   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3177     0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
3178
3179   /* Speculation Barriers.  */
3180   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
3181   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
3182   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
3183
3184   /* V7 instructions.  */
3185   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
3186   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
3187   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
3188   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
3189   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
3190   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
3191   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
3192   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
3193     0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
3194   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
3195     0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
3196
3197   /* Virtualization Extension instructions.  */
3198   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
3199   /* We skip ERET as that is SUBS pc, lr, #0.  */
3200
3201   /* MP Extension instructions.  */
3202   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP),   0xf830f000, 0xff70f000, "pldw%c\t%a"},
3203
3204   /* Security extension instructions.  */
3205   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
3206
3207   /* ARMv8.5-A instructions.  */
3208   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
3209
3210   /* Instructions defined in the basic V6T2 set.  */
3211   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
3212   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
3213   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
3214   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
3215   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
3216   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3217     0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
3218   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
3219
3220   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3221     0xf3bf8f2f, 0xffffffff, "clrex%c"},
3222   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3223     0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
3224   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3225     0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
3226   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3227     0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
3228   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3229     0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
3230   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3231     0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
3232   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3233     0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
3234   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3235     0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
3236   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3237     0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
3238   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3239     0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
3240   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3241     0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
3242   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3243     0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
3244   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3245     0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
3246   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3247     0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
3248   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3249     0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
3250   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3251     0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
3252   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3253     0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
3254   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3255     0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
3256   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3257     0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
3258   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3259     0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
3260   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3261     0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
3262   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3263     0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
3264   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3265     0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
3266   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3267     0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
3268   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3269     0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
3270   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3271     0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
3272   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3273     0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
3274   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3275     0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
3276   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3277     0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
3278   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3279     0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
3280   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3281     0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
3282   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3283     0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
3284   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3285     0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
3286   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3287     0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
3288   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3289     0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
3290   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3291     0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
3292   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3293     0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
3294   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3295     0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
3296   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3297     0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
3298   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3299     0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
3300   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3301     0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
3302   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3303     0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
3304   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3305     0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
3306   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3307     0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
3308   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3309     0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
3310   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3311     0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
3312   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3313     0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
3314   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3315     0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
3316   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3317     0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
3318   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3319     0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
3320   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3321     0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
3322   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3323     0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
3324   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3325     0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
3326   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3327     0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
3328   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3329     0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
3330   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3331     0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
3332   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3333     0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
3334   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3335     0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
3336   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3337     0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
3338   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3339     0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
3340   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3341     0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
3342   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3343     0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
3344   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3345     0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
3346   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3347     0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
3348   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3349     0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
3350   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3351     0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
3352   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3353     0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
3354   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3355     0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
3356   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3357     0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
3358   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3359     0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
3360   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3361     0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
3362   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3363     0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
3364   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3365     0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
3366   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3367     0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
3368   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3369     0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3370   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3371     0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3372   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3373     0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3374   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3375     0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
3376   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3377     0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
3378   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3379     0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
3380   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3381     0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
3382   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3383     0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
3384   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3385     0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3386   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3387     0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
3388   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3389     0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
3390   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3391     0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3392   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3393     0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3394   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3395     0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3396   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3397     0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3398   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3399     0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3400   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3401     0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3402   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3403     0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3404   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3405     0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
3406   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3407     0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
3408   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3409     0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3410   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3411     0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3412   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3413     0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3414   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3415     0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3416   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3417     0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3418   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3419     0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3420   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3421     0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3422   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3423     0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3424   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3425     0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3426   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3427     0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3428   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3429     0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3430   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3431     0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3432   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3433     0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3434   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3435     0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3436   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3437     0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3438   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3439     0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3440   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3441     0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3442   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3443     0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3444   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3445     0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3446   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3447     0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3448   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3449     0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3450   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3451     0xf810f000, 0xff70f000, "pld%c\t%a"},
3452   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3453     0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3454   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3455     0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3456   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3457     0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3458   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3459     0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3460   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3461     0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3462   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3463     0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3464   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3465     0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3466   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3467     0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3468   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3469     0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3470   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3471     0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3472   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3473     0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3474   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3475     0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3476   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3477     0xfb100000, 0xfff000c0,
3478     "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3479   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3480     0xfbc00080, 0xfff000c0,
3481     "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3482   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3483     0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3484   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3485     0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3486   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3487     0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
3488   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3489     0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3490   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3491     0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
3492   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3493     0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3494   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3495     0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
3496   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3497     0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3498   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3499     0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3500   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3501     0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3502   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3503     0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3504   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3505     0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3506   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3507     0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3508   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3509     0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3510   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3511     0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3512   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3513     0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3514   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3515     0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3516   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3517     0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
3518   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3519     0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3520   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3521     0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3522   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3523     0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3524   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3525     0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3526   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3527     0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3528   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3529     0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3530   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3531     0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3532   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3533     0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3534   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3535     0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3536   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3537     0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3538   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3539     0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3540   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3541     0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3542   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3543     0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3544   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3545     0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3546   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3547     0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3548   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3549     0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3550   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3551     0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3552   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3553     0xe9400000, 0xff500000,
3554     "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3555   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3556     0xe9500000, 0xff500000,
3557     "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3558   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3559     0xe8600000, 0xff700000,
3560     "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3561   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3562     0xe8700000, 0xff700000,
3563     "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3564   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3565     0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3566   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3567     0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
3568
3569   /* Filter out Bcc with cond=E or F, which are used for other instructions.  */
3570   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3571     0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3572   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3573     0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3574   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3575     0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3576   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3577     0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
3578
3579   /* These have been 32-bit since the invention of Thumb.  */
3580   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3581      0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3582   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3583      0xf000d000, 0xf800d000, "bl%c\t%B%x"},
3584
3585   /* Fallback.  */
3586   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3587       0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3588   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3589 };
3590
3591 static const char *const arm_conditional[] =
3592 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
3593  "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
3594
3595 static const char *const arm_fp_const[] =
3596 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3597
3598 static const char *const arm_shift[] =
3599 {"lsl", "lsr", "asr", "ror"};
3600
3601 typedef struct
3602 {
3603   const char *name;
3604   const char *description;
3605   const char *reg_names[16];
3606 }
3607 arm_regname;
3608
3609 static const arm_regname regnames[] =
3610 {
3611   { "reg-names-raw", N_("Select raw register names"),
3612     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3613   { "reg-names-gcc", N_("Select register names used by GCC"),
3614     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
3615   { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
3616     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp",  "lr",  "pc" }},
3617   { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
3618   { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
3619   { "reg-names-apcs", N_("Select register names used in the APCS"),
3620     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
3621   { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
3622     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7",  "v8",  "IP",  "SP",  "LR",  "PC" }},
3623   { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3624     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }}
3625 };
3626
3627 static const char *const iwmmxt_wwnames[] =
3628 {"b", "h", "w", "d"};
3629
3630 static const char *const iwmmxt_wwssnames[] =
3631 {"b", "bus", "bc", "bss",
3632  "h", "hus", "hc", "hss",
3633  "w", "wus", "wc", "wss",
3634  "d", "dus", "dc", "dss"
3635 };
3636
3637 static const char *const iwmmxt_regnames[] =
3638 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3639   "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3640 };
3641
3642 static const char *const iwmmxt_cregnames[] =
3643 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3644   "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3645 };
3646
3647 static const char *const vec_condnames[] =
3648 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
3649 };
3650
3651 static const char *const mve_predicatenames[] =
3652 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
3653   "eee", "ee", "eet", "e", "ett", "et", "ete"
3654 };
3655
3656 /* Names for 2-bit size field for mve vector isntructions.  */
3657 static const char *const mve_vec_sizename[] =
3658   { "8", "16", "32", "64"};
3659
3660 /* Indicates whether we are processing a then predicate,
3661    else predicate or none at all.  */
3662 enum vpt_pred_state
3663 {
3664   PRED_NONE,
3665   PRED_THEN,
3666   PRED_ELSE
3667 };
3668
3669 /* Information used to process a vpt block and subsequent instructions.  */
3670 struct vpt_block
3671 {
3672   /* Are we in a vpt block.  */
3673   bfd_boolean in_vpt_block;
3674
3675   /* Next predicate state if in vpt block.  */
3676   enum vpt_pred_state next_pred_state;
3677
3678   /* Mask from vpt/vpst instruction.  */
3679   long predicate_mask;
3680
3681   /* Instruction number in vpt block.  */
3682   long current_insn_num;
3683
3684   /* Number of instructions in vpt block..   */
3685   long num_pred_insn;
3686 };
3687
3688 static struct vpt_block vpt_block_state =
3689 {
3690   FALSE,
3691   PRED_NONE,
3692   0,
3693   0,
3694   0
3695 };
3696
3697 /* Default to GCC register name set.  */
3698 static unsigned int regname_selected = 1;
3699
3700 #define NUM_ARM_OPTIONS   ARRAY_SIZE (regnames)
3701 #define arm_regnames      regnames[regname_selected].reg_names
3702
3703 static bfd_boolean force_thumb = FALSE;
3704
3705 /* Current IT instruction state.  This contains the same state as the IT
3706    bits in the CPSR.  */
3707 static unsigned int ifthen_state;
3708 /* IT state for the next instruction.  */
3709 static unsigned int ifthen_next_state;
3710 /* The address of the insn for which the IT state is valid.  */
3711 static bfd_vma ifthen_address;
3712 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
3713 /* Indicates that the current Conditional state is unconditional or outside
3714    an IT block.  */
3715 #define COND_UNCOND 16
3716
3717 \f
3718 /* Functions.  */
3719 /* Extract the predicate mask for a VPT or VPST instruction.
3720    The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh).  */
3721
3722 static long
3723 mve_extract_pred_mask (long given)
3724 {
3725   return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
3726 }
3727
3728 /* Return the number of instructions in a MVE predicate block.  */
3729 static long
3730 num_instructions_vpt_block (long given)
3731 {
3732   long mask = mve_extract_pred_mask (given);
3733   if (mask == 0)
3734     return 0;
3735
3736   if (mask == 8)
3737     return 1;
3738
3739   if ((mask & 7) == 4)
3740     return 2;
3741
3742   if ((mask & 3) == 2)
3743     return 3;
3744
3745   if ((mask & 1) == 1)
3746     return 4;
3747
3748   return 0;
3749 }
3750
3751 static void
3752 mark_outside_vpt_block (void)
3753 {
3754   vpt_block_state.in_vpt_block = FALSE;
3755   vpt_block_state.next_pred_state = PRED_NONE;
3756   vpt_block_state.predicate_mask = 0;
3757   vpt_block_state.current_insn_num = 0;
3758   vpt_block_state.num_pred_insn = 0;
3759 }
3760
3761 static void
3762 mark_inside_vpt_block (long given)
3763 {
3764   vpt_block_state.in_vpt_block = TRUE;
3765   vpt_block_state.next_pred_state = PRED_THEN;
3766   vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
3767   vpt_block_state.current_insn_num = 0;
3768   vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
3769   assert (vpt_block_state.num_pred_insn >= 1);
3770 }
3771
3772 static enum vpt_pred_state
3773 invert_next_predicate_state (enum vpt_pred_state astate)
3774 {
3775   if (astate == PRED_THEN)
3776     return PRED_ELSE;
3777   else if (astate == PRED_ELSE)
3778     return PRED_THEN;
3779   else
3780     return PRED_NONE;
3781 }
3782
3783 static enum vpt_pred_state
3784 update_next_predicate_state (void)
3785 {
3786   long pred_mask = vpt_block_state.predicate_mask;
3787   long mask_for_insn = 0;
3788
3789   switch (vpt_block_state.current_insn_num)
3790     {
3791     case 1:
3792       mask_for_insn = 8;
3793       break;
3794
3795     case 2:
3796       mask_for_insn = 4;
3797       break;
3798
3799     case 3:
3800       mask_for_insn = 2;
3801       break;
3802
3803     case 4:
3804       return PRED_NONE;
3805     }
3806
3807   if (pred_mask & mask_for_insn)
3808     return invert_next_predicate_state (vpt_block_state.next_pred_state);
3809   else
3810     return vpt_block_state.next_pred_state;
3811 }
3812
3813 static void
3814 update_vpt_block_state (void)
3815 {
3816   vpt_block_state.current_insn_num++;
3817   if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
3818     {
3819       /* No more instructions to process in vpt block.  */
3820       mark_outside_vpt_block ();
3821       return;
3822     }
3823
3824   vpt_block_state.next_pred_state = update_next_predicate_state ();
3825 }
3826
3827 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3828    Returns pointer to following character of the format string and
3829    fills in *VALUEP and *WIDTHP with the extracted value and number of
3830    bits extracted.  WIDTHP can be NULL.  */
3831
3832 static const char *
3833 arm_decode_bitfield (const char *ptr,
3834                      unsigned long insn,
3835                      unsigned long *valuep,
3836                      int *widthp)
3837 {
3838   unsigned long value = 0;
3839   int width = 0;
3840
3841   do
3842     {
3843       int start, end;
3844       int bits;
3845
3846       for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3847         start = start * 10 + *ptr - '0';
3848       if (*ptr == '-')
3849         for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3850           end = end * 10 + *ptr - '0';
3851       else
3852         end = start;
3853       bits = end - start;
3854       if (bits < 0)
3855         abort ();
3856       value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3857       width += bits + 1;
3858     }
3859   while (*ptr++ == ',');
3860   *valuep = value;
3861   if (widthp)
3862     *widthp = width;
3863   return ptr - 1;
3864 }
3865
3866 static void
3867 arm_decode_shift (long given, fprintf_ftype func, void *stream,
3868                   bfd_boolean print_shift)
3869 {
3870   func (stream, "%s", arm_regnames[given & 0xf]);
3871
3872   if ((given & 0xff0) != 0)
3873     {
3874       if ((given & 0x10) == 0)
3875         {
3876           int amount = (given & 0xf80) >> 7;
3877           int shift = (given & 0x60) >> 5;
3878
3879           if (amount == 0)
3880             {
3881               if (shift == 3)
3882                 {
3883                   func (stream, ", rrx");
3884                   return;
3885                 }
3886
3887               amount = 32;
3888             }
3889
3890           if (print_shift)
3891             func (stream, ", %s #%d", arm_shift[shift], amount);
3892           else
3893             func (stream, ", #%d", amount);
3894         }
3895       else if ((given & 0x80) == 0x80)
3896         func (stream, "\t; <illegal shifter operand>");
3897       else if (print_shift)
3898         func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3899               arm_regnames[(given & 0xf00) >> 8]);
3900       else
3901         func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
3902     }
3903 }
3904
3905 /* Return TRUE if the MATCHED_INSN can be inside an IT block.  */
3906
3907 static bfd_boolean
3908 is_mve_okay_in_it (enum mve_instructions matched_insn)
3909 {
3910   return FALSE;
3911 }
3912
3913 static bfd_boolean
3914 is_mve_architecture (struct disassemble_info *info)
3915 {
3916   struct arm_private_data *private_data = info->private_data;
3917   arm_feature_set allowed_arches = private_data->features;
3918
3919   arm_feature_set arm_ext_v8_1m_main
3920     = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
3921
3922   if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
3923       && !ARM_CPU_IS_ANY (allowed_arches))
3924     return TRUE;
3925   else
3926     return FALSE;
3927 }
3928
3929 static bfd_boolean
3930 is_vpt_instruction (long given)
3931 {
3932
3933   /* If mkh:mkl is '0000' then its not a vpt/vpst instruction.  */
3934   if ((given & 0x0040e000) == 0)
3935     return FALSE;
3936
3937   /* VPT floating point T1 variant.  */
3938   if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
3939   /* VPT floating point T2 variant.  */
3940       || ((given & 0xefb10f50) == 0xee310f40)
3941   /* VPT vector T1 variant.  */
3942       || ((given & 0xff811f51) == 0xfe010f00)
3943   /* VPT vector T2 variant.  */
3944       || ((given & 0xff811f51) == 0xfe010f01
3945           && ((given & 0x300000) != 0x300000))
3946   /* VPT vector T3 variant.  */
3947       || ((given & 0xff811f50) == 0xfe011f00)
3948   /* VPT vector T4 variant.  */
3949       || ((given & 0xff811f70) == 0xfe010f40)
3950   /* VPT vector T5 variant.  */
3951       || ((given & 0xff811f70) == 0xfe010f60)
3952   /* VPT vector T6 variant.  */
3953       || ((given & 0xff811f50) == 0xfe011f40)
3954   /* VPST vector T variant.  */
3955       || ((given & 0xffbf1fff) == 0xfe310f4d))
3956     return TRUE;
3957   else
3958     return FALSE;
3959 }
3960
3961 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
3962    and ending bitfield = END.  END must be greater than START.  */
3963
3964 static unsigned long
3965 arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
3966 {
3967   int bits = end - start;
3968
3969   if (bits < 0)
3970     abort ();
3971
3972   return ((given >> start) & ((2ul << bits) - 1));
3973 }
3974
3975 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
3976    START:END and START2:END2.  END/END2 must be greater than
3977    START/START2.  */
3978
3979 static unsigned long
3980 arm_decode_field_multiple (unsigned long given, unsigned int start,
3981                            unsigned int end, unsigned int start2,
3982                            unsigned int end2)
3983 {
3984   int bits = end - start;
3985   int bits2 = end2 - start2;
3986   unsigned long value = 0;
3987   int width = 0;
3988
3989   if (bits2 < 0)
3990     abort ();
3991
3992   value = arm_decode_field (given, start, end);
3993   width += bits + 1;
3994
3995   value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
3996   return value;
3997 }
3998
3999 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
4000    This helps us decode instructions that change mnemonic depending on specific
4001    operand values/encodings.  */
4002
4003 static bfd_boolean
4004 is_mve_encoding_conflict (unsigned long given,
4005                           enum mve_instructions matched_insn)
4006 {
4007   switch (matched_insn)
4008     {
4009     case MVE_VPST:
4010       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4011         return TRUE;
4012       else
4013         return FALSE;
4014
4015     case MVE_VPT_FP_T1:
4016       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4017         return TRUE;
4018       if ((arm_decode_field (given, 12, 12) == 0)
4019           && (arm_decode_field (given, 0, 0) == 1))
4020         return TRUE;
4021       return FALSE;
4022
4023     case MVE_VPT_FP_T2:
4024       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4025         return TRUE;
4026       if (arm_decode_field (given, 0, 3) == 0xd)
4027         return TRUE;
4028       return FALSE;
4029
4030     case MVE_VPT_VEC_T1:
4031     case MVE_VPT_VEC_T2:
4032     case MVE_VPT_VEC_T3:
4033     case MVE_VPT_VEC_T4:
4034     case MVE_VPT_VEC_T5:
4035     case MVE_VPT_VEC_T6:
4036       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4037         return TRUE;
4038       if (arm_decode_field (given, 20, 21) == 3)
4039         return TRUE;
4040       return FALSE;
4041
4042     case MVE_VCMP_FP_T1:
4043       if ((arm_decode_field (given, 12, 12) == 0)
4044           && (arm_decode_field (given, 0, 0) == 1))
4045         return TRUE;
4046       else
4047         return FALSE;
4048
4049     case MVE_VCMP_FP_T2:
4050       if (arm_decode_field (given, 0, 3) == 0xd)
4051         return TRUE;
4052       else
4053         return FALSE;
4054
4055     case MVE_VHADD_T2:
4056     case MVE_VHSUB_T2:
4057     case MVE_VCMP_VEC_T1:
4058     case MVE_VCMP_VEC_T2:
4059     case MVE_VCMP_VEC_T3:
4060     case MVE_VCMP_VEC_T4:
4061     case MVE_VCMP_VEC_T5:
4062     case MVE_VCMP_VEC_T6:
4063       if (arm_decode_field (given, 20, 21) == 3)
4064         return TRUE;
4065       else
4066         return FALSE;
4067
4068     case MVE_VLD2:
4069     case MVE_VLD4:
4070     case MVE_VST2:
4071     case MVE_VST4:
4072       if (arm_decode_field (given, 7, 8) == 3)
4073         return TRUE;
4074       else
4075         return FALSE;
4076
4077     default:
4078       return FALSE;
4079
4080     }
4081 }
4082
4083 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
4084    Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
4085    this encoding is undefined.  */
4086
4087 static bfd_boolean
4088 is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
4089                   enum mve_undefined *undefined_code)
4090 {
4091   *undefined_code = UNDEF_NONE;
4092
4093   switch (matched_insn)
4094     {
4095     case MVE_VDUP:
4096       if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
4097         {
4098           *undefined_code = UNDEF_SIZE_3;
4099           return TRUE;
4100         }
4101       else
4102         return FALSE;
4103
4104     case MVE_VRHADD:
4105     case MVE_VHADD_T1:
4106     case MVE_VHSUB_T1:
4107       if (arm_decode_field (given, 20, 21) == 3)
4108         {
4109           *undefined_code = UNDEF_SIZE_3;
4110           return TRUE;
4111         }
4112       else
4113         return FALSE;
4114
4115     default:
4116       return FALSE;
4117     }
4118 }
4119
4120 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
4121    Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
4122    why this encoding is unpredictable.  */
4123
4124 static bfd_boolean
4125 is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
4126                       enum mve_unpredictable *unpredictable_code)
4127 {
4128   *unpredictable_code = UNPRED_NONE;
4129
4130   switch (matched_insn)
4131     {
4132     case MVE_VCMP_FP_T2:
4133     case MVE_VPT_FP_T2:
4134       if ((arm_decode_field (given, 12, 12) == 0)
4135           && (arm_decode_field (given, 5, 5) == 1))
4136         {
4137           *unpredictable_code = UNPRED_FCA_0_FCB_1;
4138           return TRUE;
4139         }
4140       else
4141         return FALSE;
4142
4143     case MVE_VPT_VEC_T4:
4144     case MVE_VPT_VEC_T5:
4145     case MVE_VPT_VEC_T6:
4146     case MVE_VCMP_VEC_T4:
4147     case MVE_VCMP_VEC_T5:
4148     case MVE_VCMP_VEC_T6:
4149       if (arm_decode_field (given, 0, 3) == 0xd)
4150         {
4151           *unpredictable_code = UNPRED_R13;
4152           return TRUE;
4153         }
4154       else
4155         return FALSE;
4156
4157     case MVE_VDUP:
4158       {
4159         unsigned long gpr = arm_decode_field (given, 12, 15);
4160         if (gpr == 0xd)
4161           {
4162             *unpredictable_code = UNPRED_R13;
4163             return TRUE;
4164           }
4165         else if (gpr == 0xf)
4166           {
4167             *unpredictable_code = UNPRED_R15;
4168             return TRUE;
4169           }
4170
4171         return FALSE;
4172       }
4173
4174     case MVE_VFMA_FP_SCALAR:
4175     case MVE_VFMAS_FP_SCALAR:
4176     case MVE_VHADD_T2:
4177     case MVE_VHSUB_T2:
4178       {
4179         unsigned long gpr = arm_decode_field (given, 0, 3);
4180         if (gpr == 0xd)
4181           {
4182             *unpredictable_code = UNPRED_R13;
4183             return TRUE;
4184           }
4185         else if (gpr == 0xf)
4186           {
4187             *unpredictable_code = UNPRED_R15;
4188             return TRUE;
4189           }
4190
4191         return FALSE;
4192       }
4193
4194     case MVE_VLD2:
4195     case MVE_VST2:
4196       {
4197         unsigned long rn = arm_decode_field (given, 16, 19);
4198
4199         if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
4200           {
4201             *unpredictable_code = UNPRED_R13_AND_WB;
4202             return TRUE;
4203           }
4204
4205         if (rn == 0xf)
4206           {
4207             *unpredictable_code = UNPRED_R15;
4208             return TRUE;
4209           }
4210
4211         if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
4212           {
4213             *unpredictable_code = UNPRED_Q_GT_6;
4214             return TRUE;
4215           }
4216         else
4217           return FALSE;
4218       }
4219
4220     case MVE_VLD4:
4221     case MVE_VST4:
4222       {
4223         unsigned long rn = arm_decode_field (given, 16, 19);
4224
4225         if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
4226           {
4227             *unpredictable_code = UNPRED_R13_AND_WB;
4228             return TRUE;
4229           }
4230
4231         if (rn == 0xf)
4232           {
4233             *unpredictable_code = UNPRED_R15;
4234             return TRUE;
4235           }
4236
4237         if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
4238           {
4239             *unpredictable_code = UNPRED_Q_GT_4;
4240             return TRUE;
4241           }
4242         else
4243           return FALSE;
4244       }
4245
4246     default:
4247       return FALSE;
4248     }
4249 }
4250
4251 static void
4252 print_mve_undefined (struct disassemble_info *info,
4253                      enum mve_undefined undefined_code)
4254 {
4255   void *stream = info->stream;
4256   fprintf_ftype func = info->fprintf_func;
4257
4258   func (stream, "\t\tundefined instruction: ");
4259
4260   switch (undefined_code)
4261     {
4262     case UNDEF_SIZE_3:
4263       func (stream, "size equals three");
4264       break;
4265
4266     case UNDEF_NONE:
4267       break;
4268     }
4269
4270 }
4271
4272 static void
4273 print_mve_unpredictable (struct disassemble_info *info,
4274                          enum mve_unpredictable unpredict_code)
4275 {
4276   void *stream = info->stream;
4277   fprintf_ftype func = info->fprintf_func;
4278
4279   func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
4280
4281   switch (unpredict_code)
4282     {
4283     case UNPRED_IT_BLOCK:
4284       func (stream, "mve instruction in it block");
4285       break;
4286
4287     case UNPRED_FCA_0_FCB_1:
4288       func (stream, "condition bits, fca = 0 and fcb = 1");
4289       break;
4290
4291     case UNPRED_R13:
4292       func (stream, "use of r13 (sp)");
4293       break;
4294
4295     case UNPRED_R15:
4296       func (stream, "use of r15 (pc)");
4297       break;
4298
4299     case UNPRED_Q_GT_4:
4300       func (stream, "start register block > r4");
4301       break;
4302
4303     case UNPRED_Q_GT_6:
4304       func (stream, "start register block > r6");
4305       break;
4306
4307     case UNPRED_R13_AND_WB:
4308       func (stream, "use of r13 and write back");
4309       break;
4310
4311     case UNPRED_NONE:
4312       break;
4313     }
4314 }
4315
4316 /* Print register block operand for mve vld2/vld4/vst2/vld4.  */
4317
4318 static void
4319 print_mve_register_blocks (struct disassemble_info *info,
4320                            unsigned long given,
4321                            enum mve_instructions matched_insn)
4322 {
4323   void *stream = info->stream;
4324   fprintf_ftype func = info->fprintf_func;
4325
4326   unsigned long q_reg_start = arm_decode_field_multiple (given,
4327                                                          13, 15,
4328                                                          22, 22);
4329   switch (matched_insn)
4330     {
4331     case MVE_VLD2:
4332     case MVE_VST2:
4333       if (q_reg_start <= 6)
4334         func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
4335       else
4336         func (stream, "<illegal reg q%ld>", q_reg_start);
4337       break;
4338
4339     case MVE_VLD4:
4340     case MVE_VST4:
4341       if (q_reg_start <= 4)
4342         func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
4343               q_reg_start + 1, q_reg_start + 2,
4344               q_reg_start + 3);
4345       else
4346         func (stream, "<illegal reg q%ld>", q_reg_start);
4347       break;
4348
4349     default:
4350       break;
4351     }
4352 }
4353
4354 static void
4355 print_instruction_predicate (struct disassemble_info *info)
4356 {
4357   void *stream = info->stream;
4358   fprintf_ftype func = info->fprintf_func;
4359
4360   if (vpt_block_state.next_pred_state == PRED_THEN)
4361     func (stream, "t");
4362   else if (vpt_block_state.next_pred_state == PRED_ELSE)
4363     func (stream, "e");
4364 }
4365
4366 static void
4367 print_mve_size (struct disassemble_info *info,
4368                 unsigned long size,
4369                 enum mve_instructions matched_insn)
4370 {
4371   void *stream = info->stream;
4372   fprintf_ftype func = info->fprintf_func;
4373
4374   switch (matched_insn)
4375     {
4376     case MVE_VCMP_VEC_T1:
4377     case MVE_VCMP_VEC_T2:
4378     case MVE_VCMP_VEC_T3:
4379     case MVE_VCMP_VEC_T4:
4380     case MVE_VCMP_VEC_T5:
4381     case MVE_VCMP_VEC_T6:
4382     case MVE_VHADD_T1:
4383     case MVE_VHADD_T2:
4384     case MVE_VHSUB_T1:
4385     case MVE_VHSUB_T2:
4386     case MVE_VLD2:
4387     case MVE_VLD4:
4388     case MVE_VPT_VEC_T1:
4389     case MVE_VPT_VEC_T2:
4390     case MVE_VPT_VEC_T3:
4391     case MVE_VPT_VEC_T4:
4392     case MVE_VPT_VEC_T5:
4393     case MVE_VPT_VEC_T6:
4394     case MVE_VRHADD:
4395     case MVE_VST2:
4396     case MVE_VST4:
4397       if (size <= 3)
4398         func (stream, "%s", mve_vec_sizename[size]);
4399       else
4400         func (stream, "<undef size>");
4401       break;
4402
4403     case MVE_VCMP_FP_T1:
4404     case MVE_VCMP_FP_T2:
4405     case MVE_VFMA_FP_SCALAR:
4406     case MVE_VFMA_FP:
4407     case MVE_VFMS_FP:
4408     case MVE_VFMAS_FP_SCALAR:
4409     case MVE_VPT_FP_T1:
4410     case MVE_VPT_FP_T2:
4411       if (size == 0)
4412         func (stream, "32");
4413       else if (size == 1)
4414         func (stream, "16");
4415       break;
4416
4417     case MVE_VDUP:
4418       switch (size)
4419         {
4420         case 0:
4421           func (stream, "32");
4422           break;
4423         case 1:
4424           func (stream, "16");
4425           break;
4426         case 2:
4427           func (stream, "8");
4428           break;
4429         default:
4430           break;
4431         }
4432       break;
4433
4434     default:
4435       break;
4436     }
4437 }
4438
4439 static void
4440 print_vec_condition (struct disassemble_info *info, long given,
4441                      enum mve_instructions matched_insn)
4442 {
4443   void *stream = info->stream;
4444   fprintf_ftype func = info->fprintf_func;
4445   long vec_cond = 0;
4446
4447   switch (matched_insn)
4448     {
4449     case MVE_VPT_FP_T1:
4450     case MVE_VCMP_FP_T1:
4451       vec_cond = (((given & 0x1000) >> 10)
4452                   | ((given & 1) << 1)
4453                   | ((given & 0x0080) >> 7));
4454       func (stream, "%s",vec_condnames[vec_cond]);
4455       break;
4456
4457     case MVE_VPT_FP_T2:
4458     case MVE_VCMP_FP_T2:
4459       vec_cond = (((given & 0x1000) >> 10)
4460                   | ((given & 0x0020) >> 4)
4461                   | ((given & 0x0080) >> 7));
4462       func (stream, "%s",vec_condnames[vec_cond]);
4463       break;
4464
4465     case MVE_VPT_VEC_T1:
4466     case MVE_VCMP_VEC_T1:
4467       vec_cond = (given & 0x0080) >> 7;
4468       func (stream, "%s",vec_condnames[vec_cond]);
4469       break;
4470
4471     case MVE_VPT_VEC_T2:
4472     case MVE_VCMP_VEC_T2:
4473       vec_cond = 2 | ((given & 0x0080) >> 7);
4474       func (stream, "%s",vec_condnames[vec_cond]);
4475       break;
4476
4477     case MVE_VPT_VEC_T3:
4478     case MVE_VCMP_VEC_T3:
4479       vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
4480       func (stream, "%s",vec_condnames[vec_cond]);
4481       break;
4482
4483     case MVE_VPT_VEC_T4:
4484     case MVE_VCMP_VEC_T4:
4485       vec_cond = (given & 0x0080) >> 7;
4486       func (stream, "%s",vec_condnames[vec_cond]);
4487       break;
4488
4489     case MVE_VPT_VEC_T5:
4490     case MVE_VCMP_VEC_T5:
4491       vec_cond = 2 | ((given & 0x0080) >> 7);
4492       func (stream, "%s",vec_condnames[vec_cond]);
4493       break;
4494
4495     case MVE_VPT_VEC_T6:
4496     case MVE_VCMP_VEC_T6:
4497       vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
4498       func (stream, "%s",vec_condnames[vec_cond]);
4499       break;
4500
4501     case MVE_NONE:
4502     case MVE_VPST:
4503     default:
4504       break;
4505     }
4506 }
4507
4508 #define W_BIT 21
4509 #define I_BIT 22
4510 #define U_BIT 23
4511 #define P_BIT 24
4512
4513 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
4514 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
4515 #define NEGATIVE_BIT_SET  ((given & (1 << U_BIT)) == 0)
4516 #define PRE_BIT_SET       (given & (1 << P_BIT))
4517
4518
4519 /* Print one coprocessor instruction on INFO->STREAM.
4520    Return TRUE if the instuction matched, FALSE if this is not a
4521    recognised coprocessor instruction.  */
4522
4523 static bfd_boolean
4524 print_insn_coprocessor (bfd_vma pc,
4525                         struct disassemble_info *info,
4526                         long given,
4527                         bfd_boolean thumb)
4528 {
4529   const struct sopcode32 *insn;
4530   void *stream = info->stream;
4531   fprintf_ftype func = info->fprintf_func;
4532   unsigned long mask;
4533   unsigned long value = 0;
4534   int cond;
4535   int cp_num;
4536   struct arm_private_data *private_data = info->private_data;
4537   arm_feature_set allowed_arches = ARM_ARCH_NONE;
4538   arm_feature_set arm_ext_v8_1m_main =
4539     ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
4540
4541   allowed_arches = private_data->features;
4542
4543   for (insn = coprocessor_opcodes; insn->assembler; insn++)
4544     {
4545       unsigned long u_reg = 16;
4546       bfd_boolean is_unpredictable = FALSE;
4547       signed long value_in_comment = 0;
4548       const char *c;
4549
4550       if (ARM_FEATURE_ZERO (insn->arch))
4551         switch (insn->value)
4552           {
4553           case SENTINEL_IWMMXT_START:
4554             if (info->mach != bfd_mach_arm_XScale
4555                 && info->mach != bfd_mach_arm_iWMMXt
4556                 && info->mach != bfd_mach_arm_iWMMXt2)
4557               do
4558                 insn++;
4559               while ((! ARM_FEATURE_ZERO (insn->arch))
4560                      && insn->value != SENTINEL_IWMMXT_END);
4561             continue;
4562
4563           case SENTINEL_IWMMXT_END:
4564             continue;
4565
4566           case SENTINEL_GENERIC_START:
4567             allowed_arches = private_data->features;
4568             continue;
4569
4570           default:
4571             abort ();
4572           }
4573
4574       mask = insn->mask;
4575       value = insn->value;
4576       cp_num = (given >> 8) & 0xf;
4577
4578       if (thumb)
4579         {
4580           /* The high 4 bits are 0xe for Arm conditional instructions, and
4581              0xe for arm unconditional instructions.  The rest of the
4582              encoding is the same.  */
4583           mask |= 0xf0000000;
4584           value |= 0xe0000000;
4585           if (ifthen_state)
4586             cond = IFTHEN_COND;
4587           else
4588             cond = COND_UNCOND;
4589         }
4590       else
4591         {
4592           /* Only match unconditional instuctions against unconditional
4593              patterns.  */
4594           if ((given & 0xf0000000) == 0xf0000000)
4595             {
4596               mask |= 0xf0000000;
4597               cond = COND_UNCOND;
4598             }
4599           else
4600             {
4601               cond = (given >> 28) & 0xf;
4602               if (cond == 0xe)
4603                 cond = COND_UNCOND;
4604             }
4605         }
4606
4607       if ((insn->isa == T32 && !thumb)
4608           || (insn->isa == ARM && thumb))
4609         continue;
4610
4611       if ((given & mask) != value)
4612         continue;
4613
4614       if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
4615         continue;
4616
4617       if (insn->value == 0xfe000010     /* mcr2  */
4618           || insn->value == 0xfe100010  /* mrc2  */
4619           || insn->value == 0xfc100000  /* ldc2  */
4620           || insn->value == 0xfc000000) /* stc2  */
4621         {
4622           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
4623             is_unpredictable = TRUE;
4624
4625           /* Armv8.1-M Mainline FP & MVE instructions.  */
4626           if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
4627               && !ARM_CPU_IS_ANY (allowed_arches)
4628               && (cp_num == 8 || cp_num == 14 || cp_num == 15))
4629             continue;
4630
4631         }
4632       else if (insn->value == 0x0e000000     /* cdp  */
4633                || insn->value == 0xfe000000  /* cdp2  */
4634                || insn->value == 0x0e000010  /* mcr  */
4635                || insn->value == 0x0e100010  /* mrc  */
4636                || insn->value == 0x0c100000  /* ldc  */
4637                || insn->value == 0x0c000000) /* stc  */
4638         {
4639           /* Floating-point instructions.  */
4640           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
4641             continue;
4642
4643           /* Armv8.1-M Mainline FP & MVE instructions.  */
4644           if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
4645               && !ARM_CPU_IS_ANY (allowed_arches)
4646               && (cp_num == 8 || cp_num == 14 || cp_num == 15))
4647             continue;
4648         }
4649
4650       for (c = insn->assembler; *c; c++)
4651         {
4652           if (*c == '%')
4653             {
4654               const char mod = *++c;
4655               switch (mod)
4656                 {
4657                 case '%':
4658                   func (stream, "%%");
4659                   break;
4660
4661                 case 'A':
4662                 case 'K':
4663                   {
4664                     int rn = (given >> 16) & 0xf;
4665                     bfd_vma offset = given & 0xff;
4666
4667                     if (mod == 'K')
4668                       offset = given & 0x7f;
4669
4670                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
4671
4672                     if (PRE_BIT_SET || WRITEBACK_BIT_SET)
4673                       {
4674                         /* Not unindexed.  The offset is scaled.  */
4675                         if (cp_num == 9)
4676                           /* vldr.16/vstr.16 will shift the address
4677                              left by 1 bit only.  */
4678                           offset = offset * 2;
4679                         else
4680                           offset = offset * 4;
4681
4682                         if (NEGATIVE_BIT_SET)
4683                           offset = - offset;
4684                         if (rn != 15)
4685                           value_in_comment = offset;
4686                       }
4687
4688                     if (PRE_BIT_SET)
4689                       {
4690                         if (offset)
4691                           func (stream, ", #%d]%s",
4692                                 (int) offset,
4693                                 WRITEBACK_BIT_SET ? "!" : "");
4694                         else if (NEGATIVE_BIT_SET)
4695                           func (stream, ", #-0]");
4696                         else
4697                           func (stream, "]");
4698                       }
4699                     else
4700                       {
4701                         func (stream, "]");
4702
4703                         if (WRITEBACK_BIT_SET)
4704                           {
4705                             if (offset)
4706                               func (stream, ", #%d", (int) offset);
4707                             else if (NEGATIVE_BIT_SET)
4708                               func (stream, ", #-0");
4709                           }
4710                         else
4711                           {
4712                             func (stream, ", {%s%d}",
4713                                   (NEGATIVE_BIT_SET && !offset) ? "-" : "",
4714                                   (int) offset);
4715                             value_in_comment = offset;
4716                           }
4717                       }
4718                     if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
4719                       {
4720                         func (stream, "\t; ");
4721                         /* For unaligned PCs, apply off-by-alignment
4722                            correction.  */
4723                         info->print_address_func (offset + pc
4724                                                   + info->bytes_per_chunk * 2
4725                                                   - (pc & 3),
4726                                                   info);
4727                       }
4728                   }
4729                   break;
4730
4731                 case 'B':
4732                   {
4733                     int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
4734                     int offset = (given >> 1) & 0x3f;
4735
4736                     if (offset == 1)
4737                       func (stream, "{d%d}", regno);
4738                     else if (regno + offset > 32)
4739                       func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
4740                     else
4741                       func (stream, "{d%d-d%d}", regno, regno + offset - 1);
4742                   }
4743                   break;
4744
4745                 case 'C':
4746                   {
4747                     bfd_boolean single = ((given >> 8) & 1) == 0;
4748                     char reg_prefix = single ? 's' : 'd';
4749                     int Dreg = (given >> 22) & 0x1;
4750                     int Vdreg = (given >> 12) & 0xf;
4751                     int reg = single ? ((Vdreg << 1) | Dreg)
4752                                      : ((Dreg << 4) | Vdreg);
4753                     int num = (given >> (single ? 0 : 1)) & 0x7f;
4754                     int maxreg = single ? 31 : 15;
4755                     int topreg = reg + num - 1;
4756
4757                     if (!num)
4758                       func (stream, "{VPR}");
4759                     else if (num == 1)
4760                       func (stream, "{%c%d, VPR}", reg_prefix, reg);
4761                     else if (topreg > maxreg)
4762                       func (stream, "{%c%d-<overflow reg d%d, VPR}",
4763                             reg_prefix, reg, single ? topreg >> 1 : topreg);
4764                     else
4765                       func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
4766                             reg_prefix, topreg);
4767                   }
4768                   break;
4769
4770                 case 'u':
4771                   if (cond != COND_UNCOND)
4772                     is_unpredictable = TRUE;
4773
4774                   /* Fall through.  */
4775                 case 'c':
4776                   if (cond != COND_UNCOND && cp_num == 9)
4777                     is_unpredictable = TRUE;
4778
4779                   func (stream, "%s", arm_conditional[cond]);
4780                   break;
4781
4782                 case 'I':
4783                   /* Print a Cirrus/DSP shift immediate.  */
4784                   /* Immediates are 7bit signed ints with bits 0..3 in
4785                      bits 0..3 of opcode and bits 4..6 in bits 5..7
4786                      of opcode.  */
4787                   {
4788                     int imm;
4789
4790                     imm = (given & 0xf) | ((given & 0xe0) >> 1);
4791
4792                     /* Is ``imm'' a negative number?  */
4793                     if (imm & 0x40)
4794                       imm -= 0x80;
4795
4796                     func (stream, "%d", imm);
4797                   }
4798
4799                   break;
4800
4801                 case 'J':
4802                   {
4803                     unsigned long regno
4804                       = arm_decode_field_multiple (given, 13, 15, 22, 22);
4805
4806                     switch (regno)
4807                       {
4808                       case 0x1:
4809                         func (stream, "FPSCR");
4810                         break;
4811                       case 0x2:
4812                         func (stream, "FPSCR_nzcvqc");
4813                         break;
4814                       case 0xc:
4815                         func (stream, "VPR");
4816                         break;
4817                       case 0xd:
4818                         func (stream, "P0");
4819                         break;
4820                       case 0xe:
4821                         func (stream, "FPCXTNS");
4822                         break;
4823                       case 0xf:
4824                         func (stream, "FPCXTS");
4825                         break;
4826                       default:
4827                         func (stream, "<invalid reg %lu>", regno);
4828                         break;
4829                       }
4830                   }
4831                   break;
4832
4833                 case 'F':
4834                   switch (given & 0x00408000)
4835                     {
4836                     case 0:
4837                       func (stream, "4");
4838                       break;
4839                     case 0x8000:
4840                       func (stream, "1");
4841                       break;
4842                     case 0x00400000:
4843                       func (stream, "2");
4844                       break;
4845                     default:
4846                       func (stream, "3");
4847                     }
4848                   break;
4849
4850                 case 'P':
4851                   switch (given & 0x00080080)
4852                     {
4853                     case 0:
4854                       func (stream, "s");
4855                       break;
4856                     case 0x80:
4857                       func (stream, "d");
4858                       break;
4859                     case 0x00080000:
4860                       func (stream, "e");
4861                       break;
4862                     default:
4863                       func (stream, _("<illegal precision>"));
4864                       break;
4865                     }
4866                   break;
4867
4868                 case 'Q':
4869                   switch (given & 0x00408000)
4870                     {
4871                     case 0:
4872                       func (stream, "s");
4873                       break;
4874                     case 0x8000:
4875                       func (stream, "d");
4876                       break;
4877                     case 0x00400000:
4878                       func (stream, "e");
4879                       break;
4880                     default:
4881                       func (stream, "p");
4882                       break;
4883                     }
4884                   break;
4885
4886                 case 'R':
4887                   switch (given & 0x60)
4888                     {
4889                     case 0:
4890                       break;
4891                     case 0x20:
4892                       func (stream, "p");
4893                       break;
4894                     case 0x40:
4895                       func (stream, "m");
4896                       break;
4897                     default:
4898                       func (stream, "z");
4899                       break;
4900                     }
4901                   break;
4902
4903                 case '0': case '1': case '2': case '3': case '4':
4904                 case '5': case '6': case '7': case '8': case '9':
4905                   {
4906                     int width;
4907
4908                     c = arm_decode_bitfield (c, given, &value, &width);
4909
4910                     switch (*c)
4911                       {
4912                       case 'R':
4913                         if (value == 15)
4914                           is_unpredictable = TRUE;
4915                         /* Fall through.  */
4916                       case 'r':
4917                         if (c[1] == 'u')
4918                           {
4919                             /* Eat the 'u' character.  */
4920                             ++ c;
4921
4922                             if (u_reg == value)
4923                               is_unpredictable = TRUE;
4924                             u_reg = value;
4925                           }
4926                         func (stream, "%s", arm_regnames[value]);
4927                         break;
4928                       case 'V':
4929                         if (given & (1 << 6))
4930                           goto Q;
4931                         /* FALLTHROUGH */
4932                       case 'D':
4933                         func (stream, "d%ld", value);
4934                         break;
4935                       case 'Q':
4936                       Q:
4937                         if (value & 1)
4938                           func (stream, "<illegal reg q%ld.5>", value >> 1);
4939                         else
4940                           func (stream, "q%ld", value >> 1);
4941                         break;
4942                       case 'd':
4943                         func (stream, "%ld", value);
4944                         value_in_comment = value;
4945                         break;
4946                       case 'E':
4947                         {
4948                           /* Converts immediate 8 bit back to float value.  */
4949                           unsigned floatVal = (value & 0x80) << 24
4950                             | (value & 0x3F) << 19
4951                             | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
4952
4953                           /* Quarter float have a maximum value of 31.0.
4954                              Get floating point value multiplied by 1e7.
4955                              The maximum value stays in limit of a 32-bit int.  */
4956                           unsigned decVal =
4957                             (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
4958                             (16 + (value & 0xF));
4959
4960                           if (!(decVal % 1000000))
4961                             func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
4962                                   floatVal, value & 0x80 ? '-' : ' ',
4963                                   decVal / 10000000,
4964                                   decVal % 10000000 / 1000000);
4965                           else if (!(decVal % 10000))
4966                             func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
4967                                   floatVal, value & 0x80 ? '-' : ' ',
4968                                   decVal / 10000000,
4969                                   decVal % 10000000 / 10000);
4970                           else
4971                             func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
4972                                   floatVal, value & 0x80 ? '-' : ' ',
4973                                   decVal / 10000000, decVal % 10000000);
4974                           break;
4975                         }
4976                       case 'k':
4977                         {
4978                           int from = (given & (1 << 7)) ? 32 : 16;
4979                           func (stream, "%ld", from - value);
4980                         }
4981                         break;
4982
4983                       case 'f':
4984                         if (value > 7)
4985                           func (stream, "#%s", arm_fp_const[value & 7]);
4986                         else
4987                           func (stream, "f%ld", value);
4988                         break;
4989
4990                       case 'w':
4991                         if (width == 2)
4992                           func (stream, "%s", iwmmxt_wwnames[value]);
4993                         else
4994                           func (stream, "%s", iwmmxt_wwssnames[value]);
4995                         break;
4996
4997                       case 'g':
4998                         func (stream, "%s", iwmmxt_regnames[value]);
4999                         break;
5000                       case 'G':
5001                         func (stream, "%s", iwmmxt_cregnames[value]);
5002                         break;
5003
5004                       case 'x':
5005                         func (stream, "0x%lx", (value & 0xffffffffUL));
5006                         break;
5007
5008                       case 'c':
5009                         switch (value)
5010                           {
5011                           case 0:
5012                             func (stream, "eq");
5013                             break;
5014
5015                           case 1:
5016                             func (stream, "vs");
5017                             break;
5018
5019                           case 2:
5020                             func (stream, "ge");
5021                             break;
5022
5023                           case 3:
5024                             func (stream, "gt");
5025                             break;
5026
5027                           default:
5028                             func (stream, "??");
5029                             break;
5030                           }
5031                         break;
5032
5033                       case '`':
5034                         c++;
5035                         if (value == 0)
5036                           func (stream, "%c", *c);
5037                         break;
5038                       case '\'':
5039                         c++;
5040                         if (value == ((1ul << width) - 1))
5041                           func (stream, "%c", *c);
5042                         break;
5043                       case '?':
5044                         func (stream, "%c", c[(1 << width) - (int) value]);
5045                         c += 1 << width;
5046                         break;
5047                       default:
5048                         abort ();
5049                       }
5050                   }
5051                   break;
5052
5053                 case 'y':
5054                 case 'z':
5055                   {
5056                     int single = *c++ == 'y';
5057                     int regno;
5058
5059                     switch (*c)
5060                       {
5061                       case '4': /* Sm pair */
5062                       case '0': /* Sm, Dm */
5063                         regno = given & 0x0000000f;
5064                         if (single)
5065                           {
5066                             regno <<= 1;
5067                             regno += (given >> 5) & 1;
5068                           }
5069                         else
5070                           regno += ((given >> 5) & 1) << 4;
5071                         break;
5072
5073                       case '1': /* Sd, Dd */
5074                         regno = (given >> 12) & 0x0000000f;
5075                         if (single)
5076                           {
5077                             regno <<= 1;
5078                             regno += (given >> 22) & 1;
5079                           }
5080                         else
5081                           regno += ((given >> 22) & 1) << 4;
5082                         break;
5083
5084                       case '2': /* Sn, Dn */
5085                         regno = (given >> 16) & 0x0000000f;
5086                         if (single)
5087                           {
5088                             regno <<= 1;
5089                             regno += (given >> 7) & 1;
5090                           }
5091                         else
5092                           regno += ((given >> 7) & 1) << 4;
5093                         break;
5094
5095                       case '3': /* List */
5096                         func (stream, "{");
5097                         regno = (given >> 12) & 0x0000000f;
5098                         if (single)
5099                           {
5100                             regno <<= 1;
5101                             regno += (given >> 22) & 1;
5102                           }
5103                         else
5104                           regno += ((given >> 22) & 1) << 4;
5105                         break;
5106
5107                       default:
5108                         abort ();
5109                       }
5110
5111                     func (stream, "%c%d", single ? 's' : 'd', regno);
5112
5113                     if (*c == '3')
5114                       {
5115                         int count = given & 0xff;
5116
5117                         if (single == 0)
5118                           count >>= 1;
5119
5120                         if (--count)
5121                           {
5122                             func (stream, "-%c%d",
5123                                   single ? 's' : 'd',
5124                                   regno + count);
5125                           }
5126
5127                         func (stream, "}");
5128                       }
5129                     else if (*c == '4')
5130                       func (stream, ", %c%d", single ? 's' : 'd',
5131                             regno + 1);
5132                   }
5133                   break;
5134
5135                 case 'L':
5136                   switch (given & 0x00400100)
5137                     {
5138                     case 0x00000000: func (stream, "b"); break;
5139                     case 0x00400000: func (stream, "h"); break;
5140                     case 0x00000100: func (stream, "w"); break;
5141                     case 0x00400100: func (stream, "d"); break;
5142                     default:
5143                       break;
5144                     }
5145                   break;
5146
5147                 case 'Z':
5148                   {
5149                     /* given (20, 23) | given (0, 3) */
5150                     value = ((given >> 16) & 0xf0) | (given & 0xf);
5151                     func (stream, "%d", (int) value);
5152                   }
5153                   break;
5154
5155                 case 'l':
5156                   /* This is like the 'A' operator, except that if
5157                      the width field "M" is zero, then the offset is
5158                      *not* multiplied by four.  */
5159                   {
5160                     int offset = given & 0xff;
5161                     int multiplier = (given & 0x00000100) ? 4 : 1;
5162
5163                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
5164
5165                     if (multiplier > 1)
5166                       {
5167                         value_in_comment = offset * multiplier;
5168                         if (NEGATIVE_BIT_SET)
5169                           value_in_comment = - value_in_comment;
5170                       }
5171
5172                     if (offset)
5173                       {
5174                         if (PRE_BIT_SET)
5175                           func (stream, ", #%s%d]%s",
5176                                 NEGATIVE_BIT_SET ? "-" : "",
5177                                 offset * multiplier,
5178                                 WRITEBACK_BIT_SET ? "!" : "");
5179                         else
5180                           func (stream, "], #%s%d",
5181                                 NEGATIVE_BIT_SET ? "-" : "",
5182                                 offset * multiplier);
5183                       }
5184                     else
5185                       func (stream, "]");
5186                   }
5187                   break;
5188
5189                 case 'r':
5190                   {
5191                     int imm4 = (given >> 4) & 0xf;
5192                     int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
5193                     int ubit = ! NEGATIVE_BIT_SET;
5194                     const char *rm = arm_regnames [given & 0xf];
5195                     const char *rn = arm_regnames [(given >> 16) & 0xf];
5196
5197                     switch (puw_bits)
5198                       {
5199                       case 1:
5200                       case 3:
5201                         func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
5202                         if (imm4)
5203                           func (stream, ", lsl #%d", imm4);
5204                         break;
5205
5206                       case 4:
5207                       case 5:
5208                       case 6:
5209                       case 7:
5210                         func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
5211                         if (imm4 > 0)
5212                           func (stream, ", lsl #%d", imm4);
5213                         func (stream, "]");
5214                         if (puw_bits == 5 || puw_bits == 7)
5215                           func (stream, "!");
5216                         break;
5217
5218                       default:
5219                         func (stream, "INVALID");
5220                       }
5221                   }
5222                   break;
5223
5224                 case 'i':
5225                   {
5226                     long imm5;
5227                     imm5 = ((given & 0x100) >> 4) | (given & 0xf);
5228                     func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
5229                   }
5230                   break;
5231
5232                 default:
5233                   abort ();
5234                 }
5235             }
5236           else
5237             func (stream, "%c", *c);
5238         }
5239
5240       if (value_in_comment > 32 || value_in_comment < -16)
5241         func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
5242
5243       if (is_unpredictable)
5244         func (stream, UNPREDICTABLE_INSTRUCTION);
5245
5246       return TRUE;
5247     }
5248   return FALSE;
5249 }
5250
5251 /* Decodes and prints ARM addressing modes.  Returns the offset
5252    used in the address, if any, if it is worthwhile printing the
5253    offset as a hexadecimal value in a comment at the end of the
5254    line of disassembly.  */
5255
5256 static signed long
5257 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
5258 {
5259   void *stream = info->stream;
5260   fprintf_ftype func = info->fprintf_func;
5261   bfd_vma offset = 0;
5262
5263   if (((given & 0x000f0000) == 0x000f0000)
5264       && ((given & 0x02000000) == 0))
5265     {
5266       offset = given & 0xfff;
5267
5268       func (stream, "[pc");
5269
5270       if (PRE_BIT_SET)
5271         {
5272           /* Pre-indexed.  Elide offset of positive zero when
5273              non-writeback.  */
5274           if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
5275             func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
5276
5277           if (NEGATIVE_BIT_SET)
5278             offset = -offset;
5279
5280           offset += pc + 8;
5281
5282           /* Cope with the possibility of write-back
5283              being used.  Probably a very dangerous thing
5284              for the programmer to do, but who are we to
5285              argue ?  */
5286           func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
5287         }
5288       else  /* Post indexed.  */
5289         {
5290           func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
5291
5292           /* Ie ignore the offset.  */
5293           offset = pc + 8;
5294         }
5295
5296       func (stream, "\t; ");
5297       info->print_address_func (offset, info);
5298       offset = 0;
5299     }
5300   else
5301     {
5302       func (stream, "[%s",
5303             arm_regnames[(given >> 16) & 0xf]);
5304
5305       if (PRE_BIT_SET)
5306         {
5307           if ((given & 0x02000000) == 0)
5308             {
5309               /* Elide offset of positive zero when non-writeback.  */
5310               offset = given & 0xfff;
5311               if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
5312                 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
5313             }
5314           else
5315             {
5316               func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
5317               arm_decode_shift (given, func, stream, TRUE);
5318             }
5319
5320           func (stream, "]%s",
5321                 WRITEBACK_BIT_SET ? "!" : "");
5322         }
5323       else
5324         {
5325           if ((given & 0x02000000) == 0)
5326             {
5327               /* Always show offset.  */
5328               offset = given & 0xfff;
5329               func (stream, "], #%s%d",
5330                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
5331             }
5332           else
5333             {
5334               func (stream, "], %s",
5335                     NEGATIVE_BIT_SET ? "-" : "");
5336               arm_decode_shift (given, func, stream, TRUE);
5337             }
5338         }
5339       if (NEGATIVE_BIT_SET)
5340         offset = -offset;
5341     }
5342
5343   return (signed long) offset;
5344 }
5345
5346 /* Print one neon instruction on INFO->STREAM.
5347    Return TRUE if the instuction matched, FALSE if this is not a
5348    recognised neon instruction.  */
5349
5350 static bfd_boolean
5351 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
5352 {
5353   const struct opcode32 *insn;
5354   void *stream = info->stream;
5355   fprintf_ftype func = info->fprintf_func;
5356
5357   if (thumb)
5358     {
5359       if ((given & 0xef000000) == 0xef000000)
5360         {
5361           /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding.  */
5362           unsigned long bit28 = given & (1 << 28);
5363
5364           given &= 0x00ffffff;
5365           if (bit28)
5366             given |= 0xf3000000;
5367           else
5368             given |= 0xf2000000;
5369         }
5370       else if ((given & 0xff000000) == 0xf9000000)
5371         given ^= 0xf9000000 ^ 0xf4000000;
5372       /* vdup is also a valid neon instruction.  */
5373       else if ((given & 0xff910f5f) != 0xee800b10)
5374         return FALSE;
5375     }
5376
5377   for (insn = neon_opcodes; insn->assembler; insn++)
5378     {
5379       if ((given & insn->mask) == insn->value)
5380         {
5381           signed long value_in_comment = 0;
5382           bfd_boolean is_unpredictable = FALSE;
5383           const char *c;
5384
5385           for (c = insn->assembler; *c; c++)
5386             {
5387               if (*c == '%')
5388                 {
5389                   switch (*++c)
5390                     {
5391                     case '%':
5392                       func (stream, "%%");
5393                       break;
5394
5395                     case 'u':
5396                       if (thumb && ifthen_state)
5397                         is_unpredictable = TRUE;
5398
5399                       /* Fall through.  */
5400                     case 'c':
5401                       if (thumb && ifthen_state)
5402                         func (stream, "%s", arm_conditional[IFTHEN_COND]);
5403                       break;
5404
5405                     case 'A':
5406                       {
5407                         static const unsigned char enc[16] =
5408                         {
5409                           0x4, 0x14, /* st4 0,1 */
5410                           0x4, /* st1 2 */
5411                           0x4, /* st2 3 */
5412                           0x3, /* st3 4 */
5413                           0x13, /* st3 5 */
5414                           0x3, /* st1 6 */
5415                           0x1, /* st1 7 */
5416                           0x2, /* st2 8 */
5417                           0x12, /* st2 9 */
5418                           0x2, /* st1 10 */
5419                           0, 0, 0, 0, 0
5420                         };
5421                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
5422                         int rn = ((given >> 16) & 0xf);
5423                         int rm = ((given >> 0) & 0xf);
5424                         int align = ((given >> 4) & 0x3);
5425                         int type = ((given >> 8) & 0xf);
5426                         int n = enc[type] & 0xf;
5427                         int stride = (enc[type] >> 4) + 1;
5428                         int ix;
5429
5430                         func (stream, "{");
5431                         if (stride > 1)
5432                           for (ix = 0; ix != n; ix++)
5433                             func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
5434                         else if (n == 1)
5435                           func (stream, "d%d", rd);
5436                         else
5437                           func (stream, "d%d-d%d", rd, rd + n - 1);
5438                         func (stream, "}, [%s", arm_regnames[rn]);
5439                         if (align)
5440                           func (stream, " :%d", 32 << align);
5441                         func (stream, "]");
5442                         if (rm == 0xd)
5443                           func (stream, "!");
5444                         else if (rm != 0xf)
5445                           func (stream, ", %s", arm_regnames[rm]);
5446                       }
5447                       break;
5448
5449                     case 'B':
5450                       {
5451                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
5452                         int rn = ((given >> 16) & 0xf);
5453                         int rm = ((given >> 0) & 0xf);
5454                         int idx_align = ((given >> 4) & 0xf);
5455                         int align = 0;
5456                         int size = ((given >> 10) & 0x3);
5457                         int idx = idx_align >> (size + 1);
5458                         int length = ((given >> 8) & 3) + 1;
5459                         int stride = 1;
5460                         int i;
5461
5462                         if (length > 1 && size > 0)
5463                           stride = (idx_align & (1 << size)) ? 2 : 1;
5464
5465                         switch (length)
5466                           {
5467                           case 1:
5468                             {
5469                               int amask = (1 << size) - 1;
5470                               if ((idx_align & (1 << size)) != 0)
5471                                 return FALSE;
5472                               if (size > 0)
5473                                 {
5474                                   if ((idx_align & amask) == amask)
5475                                     align = 8 << size;
5476                                   else if ((idx_align & amask) != 0)
5477                                     return FALSE;
5478                                 }
5479                               }
5480                             break;
5481
5482                           case 2:
5483                             if (size == 2 && (idx_align & 2) != 0)
5484                               return FALSE;
5485                             align = (idx_align & 1) ? 16 << size : 0;
5486                             break;
5487
5488                           case 3:
5489                             if ((size == 2 && (idx_align & 3) != 0)
5490                                 || (idx_align & 1) != 0)
5491                               return FALSE;
5492                             break;
5493
5494                           case 4:
5495                             if (size == 2)
5496                               {
5497                                 if ((idx_align & 3) == 3)
5498                                   return FALSE;
5499                                 align = (idx_align & 3) * 64;
5500                               }
5501                             else
5502                               align = (idx_align & 1) ? 32 << size : 0;
5503                             break;
5504
5505                           default:
5506                             abort ();
5507                           }
5508
5509                         func (stream, "{");
5510                         for (i = 0; i < length; i++)
5511                           func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
5512                             rd + i * stride, idx);
5513                         func (stream, "}, [%s", arm_regnames[rn]);
5514                         if (align)
5515                           func (stream, " :%d", align);
5516                         func (stream, "]");
5517                         if (rm == 0xd)
5518                           func (stream, "!");
5519                         else if (rm != 0xf)
5520                           func (stream, ", %s", arm_regnames[rm]);
5521                       }
5522                       break;
5523
5524                     case 'C':
5525                       {
5526                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
5527                         int rn = ((given >> 16) & 0xf);
5528                         int rm = ((given >> 0) & 0xf);
5529                         int align = ((given >> 4) & 0x1);
5530                         int size = ((given >> 6) & 0x3);
5531                         int type = ((given >> 8) & 0x3);
5532                         int n = type + 1;
5533                         int stride = ((given >> 5) & 0x1);
5534                         int ix;
5535
5536                         if (stride && (n == 1))
5537                           n++;
5538                         else
5539                           stride++;
5540
5541                         func (stream, "{");
5542                         if (stride > 1)
5543                           for (ix = 0; ix != n; ix++)
5544                             func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
5545                         else if (n == 1)
5546                           func (stream, "d%d[]", rd);
5547                         else
5548                           func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
5549                         func (stream, "}, [%s", arm_regnames[rn]);
5550                         if (align)
5551                           {
5552                             align = (8 * (type + 1)) << size;
5553                             if (type == 3)
5554                               align = (size > 1) ? align >> 1 : align;
5555                             if (type == 2 || (type == 0 && !size))
5556                               func (stream, " :<bad align %d>", align);
5557                             else
5558                               func (stream, " :%d", align);
5559                           }
5560                         func (stream, "]");
5561                         if (rm == 0xd)
5562                           func (stream, "!");
5563                         else if (rm != 0xf)
5564                           func (stream, ", %s", arm_regnames[rm]);
5565                       }
5566                       break;
5567
5568                     case 'D':
5569                       {
5570                         int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
5571                         int size = (given >> 20) & 3;
5572                         int reg = raw_reg & ((4 << size) - 1);
5573                         int ix = raw_reg >> size >> 2;
5574
5575                         func (stream, "d%d[%d]", reg, ix);
5576                       }
5577                       break;
5578
5579                     case 'E':
5580                       /* Neon encoded constant for mov, mvn, vorr, vbic.  */
5581                       {
5582                         int bits = 0;
5583                         int cmode = (given >> 8) & 0xf;
5584                         int op = (given >> 5) & 0x1;
5585                         unsigned long value = 0, hival = 0;
5586                         unsigned shift;
5587                         int size = 0;
5588                         int isfloat = 0;
5589
5590                         bits |= ((given >> 24) & 1) << 7;
5591                         bits |= ((given >> 16) & 7) << 4;
5592                         bits |= ((given >> 0) & 15) << 0;
5593
5594                         if (cmode < 8)
5595                           {
5596                             shift = (cmode >> 1) & 3;
5597                             value = (unsigned long) bits << (8 * shift);
5598                             size = 32;
5599                           }
5600                         else if (cmode < 12)
5601                           {
5602                             shift = (cmode >> 1) & 1;
5603                             value = (unsigned long) bits << (8 * shift);
5604                             size = 16;
5605                           }
5606                         else if (cmode < 14)
5607                           {
5608                             shift = (cmode & 1) + 1;
5609                             value = (unsigned long) bits << (8 * shift);
5610                             value |= (1ul << (8 * shift)) - 1;
5611                             size = 32;
5612                           }
5613                         else if (cmode == 14)
5614                           {
5615                             if (op)
5616                               {
5617                                 /* Bit replication into bytes.  */
5618                                 int ix;
5619                                 unsigned long mask;
5620
5621                                 value = 0;
5622                                 hival = 0;
5623                                 for (ix = 7; ix >= 0; ix--)
5624                                   {
5625                                     mask = ((bits >> ix) & 1) ? 0xff : 0;
5626                                     if (ix <= 3)
5627                                       value = (value << 8) | mask;
5628                                     else
5629                                       hival = (hival << 8) | mask;
5630                                   }
5631                                 size = 64;
5632                               }
5633                             else
5634                               {
5635                                 /* Byte replication.  */
5636                                 value = (unsigned long) bits;
5637                                 size = 8;
5638                               }
5639                           }
5640                         else if (!op)
5641                           {
5642                             /* Floating point encoding.  */
5643                             int tmp;
5644
5645                             value = (unsigned long)  (bits & 0x7f) << 19;
5646                             value |= (unsigned long) (bits & 0x80) << 24;
5647                             tmp = bits & 0x40 ? 0x3c : 0x40;
5648                             value |= (unsigned long) tmp << 24;
5649                             size = 32;
5650                             isfloat = 1;
5651                           }
5652                         else
5653                           {
5654                             func (stream, "<illegal constant %.8x:%x:%x>",
5655                                   bits, cmode, op);
5656                             size = 32;
5657                             break;
5658                           }
5659                         switch (size)
5660                           {
5661                           case 8:
5662                             func (stream, "#%ld\t; 0x%.2lx", value, value);
5663                             break;
5664
5665                           case 16:
5666                             func (stream, "#%ld\t; 0x%.4lx", value, value);
5667                             break;
5668
5669                           case 32:
5670                             if (isfloat)
5671                               {
5672                                 unsigned char valbytes[4];
5673                                 double fvalue;
5674
5675                                 /* Do this a byte at a time so we don't have to
5676                                    worry about the host's endianness.  */
5677                                 valbytes[0] = value & 0xff;
5678                                 valbytes[1] = (value >> 8) & 0xff;
5679                                 valbytes[2] = (value >> 16) & 0xff;
5680                                 valbytes[3] = (value >> 24) & 0xff;
5681
5682                                 floatformat_to_double
5683                                   (& floatformat_ieee_single_little, valbytes,
5684                                   & fvalue);
5685
5686                                 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
5687                                       value);
5688                               }
5689                             else
5690                               func (stream, "#%ld\t; 0x%.8lx",
5691                                     (long) (((value & 0x80000000L) != 0)
5692                                             ? value | ~0xffffffffL : value),
5693                                     value);
5694                             break;
5695
5696                           case 64:
5697                             func (stream, "#0x%.8lx%.8lx", hival, value);
5698                             break;
5699
5700                           default:
5701                             abort ();
5702                           }
5703                       }
5704                       break;
5705
5706                     case 'F':
5707                       {
5708                         int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
5709                         int num = (given >> 8) & 0x3;
5710
5711                         if (!num)
5712                           func (stream, "{d%d}", regno);
5713                         else if (num + regno >= 32)
5714                           func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
5715                         else
5716                           func (stream, "{d%d-d%d}", regno, regno + num);
5717                       }
5718                       break;
5719
5720
5721                     case '0': case '1': case '2': case '3': case '4':
5722                     case '5': case '6': case '7': case '8': case '9':
5723                       {
5724                         int width;
5725                         unsigned long value;
5726
5727                         c = arm_decode_bitfield (c, given, &value, &width);
5728
5729                         switch (*c)
5730                           {
5731                           case 'r':
5732                             func (stream, "%s", arm_regnames[value]);
5733                             break;
5734                           case 'd':
5735                             func (stream, "%ld", value);
5736                             value_in_comment = value;
5737                             break;
5738                           case 'e':
5739                             func (stream, "%ld", (1ul << width) - value);
5740                             break;
5741
5742                           case 'S':
5743                           case 'T':
5744                           case 'U':
5745                             /* Various width encodings.  */
5746                             {
5747                               int base = 8 << (*c - 'S'); /* 8,16 or 32 */
5748                               int limit;
5749                               unsigned low, high;
5750
5751                               c++;
5752                               if (*c >= '0' && *c <= '9')
5753                                 limit = *c - '0';
5754                               else if (*c >= 'a' && *c <= 'f')
5755                                 limit = *c - 'a' + 10;
5756                               else
5757                                 abort ();
5758                               low = limit >> 2;
5759                               high = limit & 3;
5760
5761                               if (value < low || value > high)
5762                                 func (stream, "<illegal width %d>", base << value);
5763                               else
5764                                 func (stream, "%d", base << value);
5765                             }
5766                             break;
5767                           case 'R':
5768                             if (given & (1 << 6))
5769                               goto Q;
5770                             /* FALLTHROUGH */
5771                           case 'D':
5772                             func (stream, "d%ld", value);
5773                             break;
5774                           case 'Q':
5775                           Q:
5776                             if (value & 1)
5777                               func (stream, "<illegal reg q%ld.5>", value >> 1);
5778                             else
5779                               func (stream, "q%ld", value >> 1);
5780                             break;
5781
5782                           case '`':
5783                             c++;
5784                             if (value == 0)
5785                               func (stream, "%c", *c);
5786                             break;
5787                           case '\'':
5788                             c++;
5789                             if (value == ((1ul << width) - 1))
5790                               func (stream, "%c", *c);
5791                             break;
5792                           case '?':
5793                             func (stream, "%c", c[(1 << width) - (int) value]);
5794                             c += 1 << width;
5795                             break;
5796                           default:
5797                             abort ();
5798                           }
5799                       }
5800                       break;
5801
5802                     default:
5803                       abort ();
5804                     }
5805                 }
5806               else
5807                 func (stream, "%c", *c);
5808             }
5809
5810           if (value_in_comment > 32 || value_in_comment < -16)
5811             func (stream, "\t; 0x%lx", value_in_comment);
5812
5813           if (is_unpredictable)
5814             func (stream, UNPREDICTABLE_INSTRUCTION);
5815
5816           return TRUE;
5817         }
5818     }
5819   return FALSE;
5820 }
5821
5822 /* Print one mve instruction on INFO->STREAM.
5823    Return TRUE if the instuction matched, FALSE if this is not a
5824    recognised mve instruction.  */
5825
5826 static bfd_boolean
5827 print_insn_mve (struct disassemble_info *info, long given)
5828 {
5829   const struct mopcode32 *insn;
5830   void *stream = info->stream;
5831   fprintf_ftype func = info->fprintf_func;
5832
5833   for (insn = mve_opcodes; insn->assembler; insn++)
5834     {
5835       if (((given & insn->mask) == insn->value)
5836           && !is_mve_encoding_conflict (given, insn->mve_op))
5837         {
5838           signed long value_in_comment = 0;
5839           bfd_boolean is_unpredictable = FALSE;
5840           bfd_boolean is_undefined = FALSE;
5841           const char *c;
5842           enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
5843           enum mve_undefined undefined_cond = UNDEF_NONE;
5844
5845           /* Most vector mve instruction are illegal in a it block.
5846              There are a few exceptions; check for them.  */
5847           if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
5848             {
5849               is_unpredictable = TRUE;
5850               unpredictable_cond = UNPRED_IT_BLOCK;
5851             }
5852           else if (is_mve_unpredictable (given, insn->mve_op,
5853                                          &unpredictable_cond))
5854             is_unpredictable = TRUE;
5855
5856           if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
5857             is_undefined = TRUE;
5858
5859           for (c = insn->assembler; *c; c++)
5860             {
5861               if (*c == '%')
5862                 {
5863                   switch (*++c)
5864                     {
5865                     case '%':
5866                       func (stream, "%%");
5867                       break;
5868
5869                     case 'c':
5870                       if (ifthen_state)
5871                         func (stream, "%s", arm_conditional[IFTHEN_COND]);
5872                       break;
5873
5874                     case 'i':
5875                       {
5876                         long mve_mask = mve_extract_pred_mask (given);
5877                         func (stream, "%s", mve_predicatenames[mve_mask]);
5878                       }
5879                       break;
5880
5881                     case 'n':
5882                       print_vec_condition (info, given, insn->mve_op);
5883                       break;
5884
5885                     case 'v':
5886                       print_instruction_predicate (info);
5887                       break;
5888
5889                     case 'w':
5890                       if (arm_decode_field (given, 21, 21) == 1)
5891                         func (stream, "!");
5892                       break;
5893
5894                     case 'B':
5895                       print_mve_register_blocks (info, given, insn->mve_op);
5896                       break;
5897
5898                     case '0': case '1': case '2': case '3': case '4':
5899                     case '5': case '6': case '7': case '8': case '9':
5900                       {
5901                         int width;
5902                         unsigned long value;
5903
5904                         c = arm_decode_bitfield (c, given, &value, &width);
5905
5906                         switch (*c)
5907                           {
5908                           case 'Z':
5909                             if (value == 13)
5910                               is_unpredictable = TRUE;
5911                             else if (value == 15)
5912                               func (stream, "zr");
5913                             else
5914                               func (stream, "%s", arm_regnames[value]);
5915                             break;
5916                           case 's':
5917                             print_mve_size (info,
5918                                             value,
5919                                             insn->mve_op);
5920                             break;
5921                           case 'r':
5922                             func (stream, "%s", arm_regnames[value]);
5923                             break;
5924                           case 'd':
5925                             func (stream, "%ld", value);
5926                             value_in_comment = value;
5927                             break;
5928                           case 'Q':
5929                             if (value & 0x8)
5930                               func (stream, "<illegal reg q%ld.5>", value);
5931                             else
5932                               func (stream, "q%ld", value);
5933                             break;
5934                           default:
5935                             abort ();
5936                           }
5937                         break;
5938                       default:
5939                         abort ();
5940                       }
5941                     }
5942                 }
5943               else
5944                 func (stream, "%c", *c);
5945             }
5946
5947           if (value_in_comment > 32 || value_in_comment < -16)
5948             func (stream, "\t; 0x%lx", value_in_comment);
5949
5950           if (is_unpredictable)
5951             print_mve_unpredictable (info, unpredictable_cond);
5952
5953           if (is_undefined)
5954             print_mve_undefined (info, undefined_cond);
5955
5956           if ((vpt_block_state.in_vpt_block == FALSE)
5957               && !ifthen_state
5958               && (is_vpt_instruction (given) == TRUE))
5959             mark_inside_vpt_block (given);
5960           else if (vpt_block_state.in_vpt_block == TRUE)
5961             update_vpt_block_state ();
5962
5963           return TRUE;
5964         }
5965     }
5966   return FALSE;
5967 }
5968
5969
5970 /* Return the name of a v7A special register.  */
5971
5972 static const char *
5973 banked_regname (unsigned reg)
5974 {
5975   switch (reg)
5976     {
5977       case 15: return "CPSR";
5978       case 32: return "R8_usr";
5979       case 33: return "R9_usr";
5980       case 34: return "R10_usr";
5981       case 35: return "R11_usr";
5982       case 36: return "R12_usr";
5983       case 37: return "SP_usr";
5984       case 38: return "LR_usr";
5985       case 40: return "R8_fiq";
5986       case 41: return "R9_fiq";
5987       case 42: return "R10_fiq";
5988       case 43: return "R11_fiq";
5989       case 44: return "R12_fiq";
5990       case 45: return "SP_fiq";
5991       case 46: return "LR_fiq";
5992       case 48: return "LR_irq";
5993       case 49: return "SP_irq";
5994       case 50: return "LR_svc";
5995       case 51: return "SP_svc";
5996       case 52: return "LR_abt";
5997       case 53: return "SP_abt";
5998       case 54: return "LR_und";
5999       case 55: return "SP_und";
6000       case 60: return "LR_mon";
6001       case 61: return "SP_mon";
6002       case 62: return "ELR_hyp";
6003       case 63: return "SP_hyp";
6004       case 79: return "SPSR";
6005       case 110: return "SPSR_fiq";
6006       case 112: return "SPSR_irq";
6007       case 114: return "SPSR_svc";
6008       case 116: return "SPSR_abt";
6009       case 118: return "SPSR_und";
6010       case 124: return "SPSR_mon";
6011       case 126: return "SPSR_hyp";
6012       default: return NULL;
6013     }
6014 }
6015
6016 /* Return the name of the DMB/DSB option.  */
6017 static const char *
6018 data_barrier_option (unsigned option)
6019 {
6020   switch (option & 0xf)
6021     {
6022     case 0xf: return "sy";
6023     case 0xe: return "st";
6024     case 0xd: return "ld";
6025     case 0xb: return "ish";
6026     case 0xa: return "ishst";
6027     case 0x9: return "ishld";
6028     case 0x7: return "un";
6029     case 0x6: return "unst";
6030     case 0x5: return "nshld";
6031     case 0x3: return "osh";
6032     case 0x2: return "oshst";
6033     case 0x1: return "oshld";
6034     default:  return NULL;
6035     }
6036 }
6037
6038 /* Print one ARM instruction from PC on INFO->STREAM.  */
6039
6040 static void
6041 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
6042 {
6043   const struct opcode32 *insn;
6044   void *stream = info->stream;
6045   fprintf_ftype func = info->fprintf_func;
6046   struct arm_private_data *private_data = info->private_data;
6047
6048   if (print_insn_coprocessor (pc, info, given, FALSE))
6049     return;
6050
6051   if (print_insn_neon (info, given, FALSE))
6052     return;
6053
6054   for (insn = arm_opcodes; insn->assembler; insn++)
6055     {
6056       if ((given & insn->mask) != insn->value)
6057         continue;
6058
6059       if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
6060         continue;
6061
6062       /* Special case: an instruction with all bits set in the condition field
6063          (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
6064          or by the catchall at the end of the table.  */
6065       if ((given & 0xF0000000) != 0xF0000000
6066           || (insn->mask & 0xF0000000) == 0xF0000000
6067           || (insn->mask == 0 && insn->value == 0))
6068         {
6069           unsigned long u_reg = 16;
6070           unsigned long U_reg = 16;
6071           bfd_boolean is_unpredictable = FALSE;
6072           signed long value_in_comment = 0;
6073           const char *c;
6074
6075           for (c = insn->assembler; *c; c++)
6076             {
6077               if (*c == '%')
6078                 {
6079                   bfd_boolean allow_unpredictable = FALSE;
6080
6081                   switch (*++c)
6082                     {
6083                     case '%':
6084                       func (stream, "%%");
6085                       break;
6086
6087                     case 'a':
6088                       value_in_comment = print_arm_address (pc, info, given);
6089                       break;
6090
6091                     case 'P':
6092                       /* Set P address bit and use normal address
6093                          printing routine.  */
6094                       value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
6095                       break;
6096
6097                     case 'S':
6098                       allow_unpredictable = TRUE;
6099                       /* Fall through.  */
6100                     case 's':
6101                       if ((given & 0x004f0000) == 0x004f0000)
6102                         {
6103                           /* PC relative with immediate offset.  */
6104                           bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
6105
6106                           if (PRE_BIT_SET)
6107                             {
6108                               /* Elide positive zero offset.  */
6109                               if (offset || NEGATIVE_BIT_SET)
6110                                 func (stream, "[pc, #%s%d]\t; ",
6111                                       NEGATIVE_BIT_SET ? "-" : "", (int) offset);
6112                               else
6113                                 func (stream, "[pc]\t; ");
6114                               if (NEGATIVE_BIT_SET)
6115                                 offset = -offset;
6116                               info->print_address_func (offset + pc + 8, info);
6117                             }
6118                           else
6119                             {
6120                               /* Always show the offset.  */
6121                               func (stream, "[pc], #%s%d",
6122                                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
6123                               if (! allow_unpredictable)
6124                                 is_unpredictable = TRUE;
6125                             }
6126                         }
6127                       else
6128                         {
6129                           int offset = ((given & 0xf00) >> 4) | (given & 0xf);
6130
6131                           func (stream, "[%s",
6132                                 arm_regnames[(given >> 16) & 0xf]);
6133
6134                           if (PRE_BIT_SET)
6135                             {
6136                               if (IMMEDIATE_BIT_SET)
6137                                 {
6138                                   /* Elide offset for non-writeback
6139                                      positive zero.  */
6140                                   if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
6141                                       || offset)
6142                                     func (stream, ", #%s%d",
6143                                           NEGATIVE_BIT_SET ? "-" : "", offset);
6144
6145                                   if (NEGATIVE_BIT_SET)
6146                                     offset = -offset;
6147
6148                                   value_in_comment = offset;
6149                                 }
6150                               else
6151                                 {
6152                                   /* Register Offset or Register Pre-Indexed.  */
6153                                   func (stream, ", %s%s",
6154                                         NEGATIVE_BIT_SET ? "-" : "",
6155                                         arm_regnames[given & 0xf]);
6156
6157                                   /* Writing back to the register that is the source/
6158                                      destination of the load/store is unpredictable.  */
6159                                   if (! allow_unpredictable
6160                                       && WRITEBACK_BIT_SET
6161                                       && ((given & 0xf) == ((given >> 12) & 0xf)))
6162                                     is_unpredictable = TRUE;
6163                                 }
6164
6165                               func (stream, "]%s",
6166                                     WRITEBACK_BIT_SET ? "!" : "");
6167                             }
6168                           else
6169                             {
6170                               if (IMMEDIATE_BIT_SET)
6171                                 {
6172                                   /* Immediate Post-indexed.  */
6173                                   /* PR 10924: Offset must be printed, even if it is zero.  */
6174                                   func (stream, "], #%s%d",
6175                                         NEGATIVE_BIT_SET ? "-" : "", offset);
6176                                   if (NEGATIVE_BIT_SET)
6177                                     offset = -offset;
6178                                   value_in_comment = offset;
6179                                 }
6180                               else
6181                                 {
6182                                   /* Register Post-indexed.  */
6183                                   func (stream, "], %s%s",
6184                                         NEGATIVE_BIT_SET ? "-" : "",
6185                                         arm_regnames[given & 0xf]);
6186
6187                                   /* Writing back to the register that is the source/
6188                                      destination of the load/store is unpredictable.  */
6189                                   if (! allow_unpredictable
6190                                       && (given & 0xf) == ((given >> 12) & 0xf))
6191                                     is_unpredictable = TRUE;
6192                                 }
6193
6194                               if (! allow_unpredictable)
6195                                 {
6196                                   /* Writeback is automatically implied by post- addressing.
6197                                      Setting the W bit is unnecessary and ARM specify it as
6198                                      being unpredictable.  */
6199                                   if (WRITEBACK_BIT_SET
6200                                       /* Specifying the PC register as the post-indexed
6201                                          registers is also unpredictable.  */
6202                                       || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
6203                                     is_unpredictable = TRUE;
6204                                 }
6205                             }
6206                         }
6207                       break;
6208
6209                     case 'b':
6210                       {
6211                         bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
6212                         info->print_address_func (disp * 4 + pc + 8, info);
6213                       }
6214                       break;
6215
6216                     case 'c':
6217                       if (((given >> 28) & 0xf) != 0xe)
6218                         func (stream, "%s",
6219                               arm_conditional [(given >> 28) & 0xf]);
6220                       break;
6221
6222                     case 'm':
6223                       {
6224                         int started = 0;
6225                         int reg;
6226
6227                         func (stream, "{");
6228                         for (reg = 0; reg < 16; reg++)
6229                           if ((given & (1 << reg)) != 0)
6230                             {
6231                               if (started)
6232                                 func (stream, ", ");
6233                               started = 1;
6234                               func (stream, "%s", arm_regnames[reg]);
6235                             }
6236                         func (stream, "}");
6237                         if (! started)
6238                           is_unpredictable = TRUE;
6239                       }
6240                       break;
6241
6242                     case 'q':
6243                       arm_decode_shift (given, func, stream, FALSE);
6244                       break;
6245
6246                     case 'o':
6247                       if ((given & 0x02000000) != 0)
6248                         {
6249                           unsigned int rotate = (given & 0xf00) >> 7;
6250                           unsigned int immed = (given & 0xff);
6251                           unsigned int a, i;
6252
6253                           a = (((immed << (32 - rotate))
6254                                 | (immed >> rotate)) & 0xffffffff);
6255                           /* If there is another encoding with smaller rotate,
6256                              the rotate should be specified directly.  */
6257                           for (i = 0; i < 32; i += 2)
6258                             if ((a << i | a >> (32 - i)) <= 0xff)
6259                               break;
6260
6261                           if (i != rotate)
6262                             func (stream, "#%d, %d", immed, rotate);
6263                           else
6264                             func (stream, "#%d", a);
6265                           value_in_comment = a;
6266                         }
6267                       else
6268                         arm_decode_shift (given, func, stream, TRUE);
6269                       break;
6270
6271                     case 'p':
6272                       if ((given & 0x0000f000) == 0x0000f000)
6273                         {
6274                           arm_feature_set arm_ext_v6 =
6275                             ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
6276
6277                           /* The p-variants of tst/cmp/cmn/teq are the pre-V6
6278                              mechanism for setting PSR flag bits.  They are
6279                              obsolete in V6 onwards.  */
6280                           if (! ARM_CPU_HAS_FEATURE (private_data->features, \
6281                                                      arm_ext_v6))
6282                             func (stream, "p");
6283                           else
6284                             is_unpredictable = TRUE;
6285                         }
6286                       break;
6287
6288                     case 't':
6289                       if ((given & 0x01200000) == 0x00200000)
6290                         func (stream, "t");
6291                       break;
6292
6293                     case 'A':
6294                       {
6295                         int offset = given & 0xff;
6296
6297                         value_in_comment = offset * 4;
6298                         if (NEGATIVE_BIT_SET)
6299                           value_in_comment = - value_in_comment;
6300
6301                         func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
6302
6303                         if (PRE_BIT_SET)
6304                           {
6305                             if (offset)
6306                               func (stream, ", #%d]%s",
6307                                     (int) value_in_comment,
6308                                     WRITEBACK_BIT_SET ? "!" : "");
6309                             else
6310                               func (stream, "]");
6311                           }
6312                         else
6313                           {
6314                             func (stream, "]");
6315
6316                             if (WRITEBACK_BIT_SET)
6317                               {
6318                                 if (offset)
6319                                   func (stream, ", #%d", (int) value_in_comment);
6320                               }
6321                             else
6322                               {
6323                                 func (stream, ", {%d}", (int) offset);
6324                                 value_in_comment = offset;
6325                               }
6326                           }
6327                       }
6328                       break;
6329
6330                     case 'B':
6331                       /* Print ARM V5 BLX(1) address: pc+25 bits.  */
6332                       {
6333                         bfd_vma address;
6334                         bfd_vma offset = 0;
6335
6336                         if (! NEGATIVE_BIT_SET)
6337                           /* Is signed, hi bits should be ones.  */
6338                           offset = (-1) ^ 0x00ffffff;
6339
6340                         /* Offset is (SignExtend(offset field)<<2).  */
6341                         offset += given & 0x00ffffff;
6342                         offset <<= 2;
6343                         address = offset + pc + 8;
6344
6345                         if (given & 0x01000000)
6346                           /* H bit allows addressing to 2-byte boundaries.  */
6347                           address += 2;
6348
6349                         info->print_address_func (address, info);
6350                       }
6351                       break;
6352
6353                     case 'C':
6354                       if ((given & 0x02000200) == 0x200)
6355                         {
6356                           const char * name;
6357                           unsigned sysm = (given & 0x004f0000) >> 16;
6358
6359                           sysm |= (given & 0x300) >> 4;
6360                           name = banked_regname (sysm);
6361
6362                           if (name != NULL)
6363                             func (stream, "%s", name);
6364                           else
6365                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
6366                         }
6367                       else
6368                         {
6369                           func (stream, "%cPSR_",
6370                                 (given & 0x00400000) ? 'S' : 'C');
6371                           if (given & 0x80000)
6372                             func (stream, "f");
6373                           if (given & 0x40000)
6374                             func (stream, "s");
6375                           if (given & 0x20000)
6376                             func (stream, "x");
6377                           if (given & 0x10000)
6378                             func (stream, "c");
6379                         }
6380                       break;
6381
6382                     case 'U':
6383                       if ((given & 0xf0) == 0x60)
6384                         {
6385                           switch (given & 0xf)
6386                             {
6387                             case 0xf: func (stream, "sy"); break;
6388                             default:
6389                               func (stream, "#%d", (int) given & 0xf);
6390                               break;
6391                             }
6392                         }
6393                       else
6394                         {
6395                           const char * opt = data_barrier_option (given & 0xf);
6396                           if (opt != NULL)
6397                             func (stream, "%s", opt);
6398                           else
6399                               func (stream, "#%d", (int) given & 0xf);
6400                         }
6401                       break;
6402
6403                     case '0': case '1': case '2': case '3': case '4':
6404                     case '5': case '6': case '7': case '8': case '9':
6405                       {
6406                         int width;
6407                         unsigned long value;
6408
6409                         c = arm_decode_bitfield (c, given, &value, &width);
6410
6411                         switch (*c)
6412                           {
6413                           case 'R':
6414                             if (value == 15)
6415                               is_unpredictable = TRUE;
6416                             /* Fall through.  */
6417                           case 'r':
6418                           case 'T':
6419                             /* We want register + 1 when decoding T.  */
6420                             if (*c == 'T')
6421                               ++value;
6422
6423                             if (c[1] == 'u')
6424                               {
6425                                 /* Eat the 'u' character.  */
6426                                 ++ c;
6427
6428                                 if (u_reg == value)
6429                                   is_unpredictable = TRUE;
6430                                 u_reg = value;
6431                               }
6432                             if (c[1] == 'U')
6433                               {
6434                                 /* Eat the 'U' character.  */
6435                                 ++ c;
6436
6437                                 if (U_reg == value)
6438                                   is_unpredictable = TRUE;
6439                                 U_reg = value;
6440                               }
6441                             func (stream, "%s", arm_regnames[value]);
6442                             break;
6443                           case 'd':
6444                             func (stream, "%ld", value);
6445                             value_in_comment = value;
6446                             break;
6447                           case 'b':
6448                             func (stream, "%ld", value * 8);
6449                             value_in_comment = value * 8;
6450                             break;
6451                           case 'W':
6452                             func (stream, "%ld", value + 1);
6453                             value_in_comment = value + 1;
6454                             break;
6455                           case 'x':
6456                             func (stream, "0x%08lx", value);
6457
6458                             /* Some SWI instructions have special
6459                                meanings.  */
6460                             if ((given & 0x0fffffff) == 0x0FF00000)
6461                               func (stream, "\t; IMB");
6462                             else if ((given & 0x0fffffff) == 0x0FF00001)
6463                               func (stream, "\t; IMBRange");
6464                             break;
6465                           case 'X':
6466                             func (stream, "%01lx", value & 0xf);
6467                             value_in_comment = value;
6468                             break;
6469                           case '`':
6470                             c++;
6471                             if (value == 0)
6472                               func (stream, "%c", *c);
6473                             break;
6474                           case '\'':
6475                             c++;
6476                             if (value == ((1ul << width) - 1))
6477                               func (stream, "%c", *c);
6478                             break;
6479                           case '?':
6480                             func (stream, "%c", c[(1 << width) - (int) value]);
6481                             c += 1 << width;
6482                             break;
6483                           default:
6484                             abort ();
6485                           }
6486                       }
6487                       break;
6488
6489                     case 'e':
6490                       {
6491                         int imm;
6492
6493                         imm = (given & 0xf) | ((given & 0xfff00) >> 4);
6494                         func (stream, "%d", imm);
6495                         value_in_comment = imm;
6496                       }
6497                       break;
6498
6499                     case 'E':
6500                       /* LSB and WIDTH fields of BFI or BFC.  The machine-
6501                          language instruction encodes LSB and MSB.  */
6502                       {
6503                         long msb = (given & 0x001f0000) >> 16;
6504                         long lsb = (given & 0x00000f80) >> 7;
6505                         long w = msb - lsb + 1;
6506
6507                         if (w > 0)
6508                           func (stream, "#%lu, #%lu", lsb, w);
6509                         else
6510                           func (stream, "(invalid: %lu:%lu)", lsb, msb);
6511                       }
6512                       break;
6513
6514                     case 'R':
6515                       /* Get the PSR/banked register name.  */
6516                       {
6517                         const char * name;
6518                         unsigned sysm = (given & 0x004f0000) >> 16;
6519
6520                         sysm |= (given & 0x300) >> 4;
6521                         name = banked_regname (sysm);
6522
6523                         if (name != NULL)
6524                           func (stream, "%s", name);
6525                         else
6526                           func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
6527                       }
6528                       break;
6529
6530                     case 'V':
6531                       /* 16-bit unsigned immediate from a MOVT or MOVW
6532                          instruction, encoded in bits 0:11 and 15:19.  */
6533                       {
6534                         long hi = (given & 0x000f0000) >> 4;
6535                         long lo = (given & 0x00000fff);
6536                         long imm16 = hi | lo;
6537
6538                         func (stream, "#%lu", imm16);
6539                         value_in_comment = imm16;
6540                       }
6541                       break;
6542
6543                     default:
6544                       abort ();
6545                     }
6546                 }
6547               else
6548                 func (stream, "%c", *c);
6549             }
6550
6551           if (value_in_comment > 32 || value_in_comment < -16)
6552             func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
6553
6554           if (is_unpredictable)
6555             func (stream, UNPREDICTABLE_INSTRUCTION);
6556
6557           return;
6558         }
6559     }
6560   func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
6561   return;
6562 }
6563
6564 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM.  */
6565
6566 static void
6567 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
6568 {
6569   const struct opcode16 *insn;
6570   void *stream = info->stream;
6571   fprintf_ftype func = info->fprintf_func;
6572
6573   for (insn = thumb_opcodes; insn->assembler; insn++)
6574     if ((given & insn->mask) == insn->value)
6575       {
6576         signed long value_in_comment = 0;
6577         const char *c = insn->assembler;
6578
6579         for (; *c; c++)
6580           {
6581             int domaskpc = 0;
6582             int domasklr = 0;
6583
6584             if (*c != '%')
6585               {
6586                 func (stream, "%c", *c);
6587                 continue;
6588               }
6589
6590             switch (*++c)
6591               {
6592               case '%':
6593                 func (stream, "%%");
6594                 break;
6595
6596               case 'c':
6597                 if (ifthen_state)
6598                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
6599                 break;
6600
6601               case 'C':
6602                 if (ifthen_state)
6603                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
6604                 else
6605                   func (stream, "s");
6606                 break;
6607
6608               case 'I':
6609                 {
6610                   unsigned int tmp;
6611
6612                   ifthen_next_state = given & 0xff;
6613                   for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
6614                     func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
6615                   func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
6616                 }
6617                 break;
6618
6619               case 'x':
6620                 if (ifthen_next_state)
6621                   func (stream, "\t; unpredictable branch in IT block\n");
6622                 break;
6623
6624               case 'X':
6625                 if (ifthen_state)
6626                   func (stream, "\t; unpredictable <IT:%s>",
6627                         arm_conditional[IFTHEN_COND]);
6628                 break;
6629
6630               case 'S':
6631                 {
6632                   long reg;
6633
6634                   reg = (given >> 3) & 0x7;
6635                   if (given & (1 << 6))
6636                     reg += 8;
6637
6638                   func (stream, "%s", arm_regnames[reg]);
6639                 }
6640                 break;
6641
6642               case 'D':
6643                 {
6644                   long reg;
6645
6646                   reg = given & 0x7;
6647                   if (given & (1 << 7))
6648                     reg += 8;
6649
6650                   func (stream, "%s", arm_regnames[reg]);
6651                 }
6652                 break;
6653
6654               case 'N':
6655                 if (given & (1 << 8))
6656                   domasklr = 1;
6657                 /* Fall through.  */
6658               case 'O':
6659                 if (*c == 'O' && (given & (1 << 8)))
6660                   domaskpc = 1;
6661                 /* Fall through.  */
6662               case 'M':
6663                 {
6664                   int started = 0;
6665                   int reg;
6666
6667                   func (stream, "{");
6668
6669                   /* It would be nice if we could spot
6670                      ranges, and generate the rS-rE format: */
6671                   for (reg = 0; (reg < 8); reg++)
6672                     if ((given & (1 << reg)) != 0)
6673                       {
6674                         if (started)
6675                           func (stream, ", ");
6676                         started = 1;
6677                         func (stream, "%s", arm_regnames[reg]);
6678                       }
6679
6680                   if (domasklr)
6681                     {
6682                       if (started)
6683                         func (stream, ", ");
6684                       started = 1;
6685                       func (stream, "%s", arm_regnames[14] /* "lr" */);
6686                     }
6687
6688                   if (domaskpc)
6689                     {
6690                       if (started)
6691                         func (stream, ", ");
6692                       func (stream, "%s", arm_regnames[15] /* "pc" */);
6693                     }
6694
6695                   func (stream, "}");
6696                 }
6697                 break;
6698
6699               case 'W':
6700                 /* Print writeback indicator for a LDMIA.  We are doing a
6701                    writeback if the base register is not in the register
6702                    mask.  */
6703                 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
6704                   func (stream, "!");
6705                 break;
6706
6707               case 'b':
6708                 /* Print ARM V6T2 CZB address: pc+4+6 bits.  */
6709                 {
6710                   bfd_vma address = (pc + 4
6711                                      + ((given & 0x00f8) >> 2)
6712                                      + ((given & 0x0200) >> 3));
6713                   info->print_address_func (address, info);
6714                 }
6715                 break;
6716
6717               case 's':
6718                 /* Right shift immediate -- bits 6..10; 1-31 print
6719                    as themselves, 0 prints as 32.  */
6720                 {
6721                   long imm = (given & 0x07c0) >> 6;
6722                   if (imm == 0)
6723                     imm = 32;
6724                   func (stream, "#%ld", imm);
6725                 }
6726                 break;
6727
6728               case '0': case '1': case '2': case '3': case '4':
6729               case '5': case '6': case '7': case '8': case '9':
6730                 {
6731                   int bitstart = *c++ - '0';
6732                   int bitend = 0;
6733
6734                   while (*c >= '0' && *c <= '9')
6735                     bitstart = (bitstart * 10) + *c++ - '0';
6736
6737                   switch (*c)
6738                     {
6739                     case '-':
6740                       {
6741                         bfd_vma reg;
6742
6743                         c++;
6744                         while (*c >= '0' && *c <= '9')
6745                           bitend = (bitend * 10) + *c++ - '0';
6746                         if (!bitend)
6747                           abort ();
6748                         reg = given >> bitstart;
6749                         reg &= (2 << (bitend - bitstart)) - 1;
6750
6751                         switch (*c)
6752                           {
6753                           case 'r':
6754                             func (stream, "%s", arm_regnames[reg]);
6755                             break;
6756
6757                           case 'd':
6758                             func (stream, "%ld", (long) reg);
6759                             value_in_comment = reg;
6760                             break;
6761
6762                           case 'H':
6763                             func (stream, "%ld", (long) (reg << 1));
6764                             value_in_comment = reg << 1;
6765                             break;
6766
6767                           case 'W':
6768                             func (stream, "%ld", (long) (reg << 2));
6769                             value_in_comment = reg << 2;
6770                             break;
6771
6772                           case 'a':
6773                             /* PC-relative address -- the bottom two
6774                                bits of the address are dropped
6775                                before the calculation.  */
6776                             info->print_address_func
6777                               (((pc + 4) & ~3) + (reg << 2), info);
6778                             value_in_comment = 0;
6779                             break;
6780
6781                           case 'x':
6782                             func (stream, "0x%04lx", (long) reg);
6783                             break;
6784
6785                           case 'B':
6786                             reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6787                             info->print_address_func (reg * 2 + pc + 4, info);
6788                             value_in_comment = 0;
6789                             break;
6790
6791                           case 'c':
6792                             func (stream, "%s", arm_conditional [reg]);
6793                             break;
6794
6795                           default:
6796                             abort ();
6797                           }
6798                       }
6799                       break;
6800
6801                     case '\'':
6802                       c++;
6803                       if ((given & (1 << bitstart)) != 0)
6804                         func (stream, "%c", *c);
6805                       break;
6806
6807                     case '?':
6808                       ++c;
6809                       if ((given & (1 << bitstart)) != 0)
6810                         func (stream, "%c", *c++);
6811                       else
6812                         func (stream, "%c", *++c);
6813                       break;
6814
6815                     default:
6816                       abort ();
6817                     }
6818                 }
6819                 break;
6820
6821               default:
6822                 abort ();
6823               }
6824           }
6825
6826         if (value_in_comment > 32 || value_in_comment < -16)
6827           func (stream, "\t; 0x%lx", value_in_comment);
6828         return;
6829       }
6830
6831   /* No match.  */
6832   func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
6833   return;
6834 }
6835
6836 /* Return the name of an V7M special register.  */
6837
6838 static const char *
6839 psr_name (int regno)
6840 {
6841   switch (regno)
6842     {
6843     case 0x0: return "APSR";
6844     case 0x1: return "IAPSR";
6845     case 0x2: return "EAPSR";
6846     case 0x3: return "PSR";
6847     case 0x5: return "IPSR";
6848     case 0x6: return "EPSR";
6849     case 0x7: return "IEPSR";
6850     case 0x8: return "MSP";
6851     case 0x9: return "PSP";
6852     case 0xa: return "MSPLIM";
6853     case 0xb: return "PSPLIM";
6854     case 0x10: return "PRIMASK";
6855     case 0x11: return "BASEPRI";
6856     case 0x12: return "BASEPRI_MAX";
6857     case 0x13: return "FAULTMASK";
6858     case 0x14: return "CONTROL";
6859     case 0x88: return "MSP_NS";
6860     case 0x89: return "PSP_NS";
6861     case 0x8a: return "MSPLIM_NS";
6862     case 0x8b: return "PSPLIM_NS";
6863     case 0x90: return "PRIMASK_NS";
6864     case 0x91: return "BASEPRI_NS";
6865     case 0x93: return "FAULTMASK_NS";
6866     case 0x94: return "CONTROL_NS";
6867     case 0x98: return "SP_NS";
6868     default: return "<unknown>";
6869     }
6870 }
6871
6872 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM.  */
6873
6874 static void
6875 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
6876 {
6877   const struct opcode32 *insn;
6878   void *stream = info->stream;
6879   fprintf_ftype func = info->fprintf_func;
6880   bfd_boolean is_mve = is_mve_architecture (info);
6881
6882   if (print_insn_coprocessor (pc, info, given, TRUE))
6883     return;
6884
6885   if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
6886     return;
6887
6888   if (is_mve && print_insn_mve (info, given))
6889     return;
6890
6891   for (insn = thumb32_opcodes; insn->assembler; insn++)
6892     if ((given & insn->mask) == insn->value)
6893       {
6894         bfd_boolean is_clrm = FALSE;
6895         bfd_boolean is_unpredictable = FALSE;
6896         signed long value_in_comment = 0;
6897         const char *c = insn->assembler;
6898
6899         for (; *c; c++)
6900           {
6901             if (*c != '%')
6902               {
6903                 func (stream, "%c", *c);
6904                 continue;
6905               }
6906
6907             switch (*++c)
6908               {
6909               case '%':
6910                 func (stream, "%%");
6911                 break;
6912
6913               case 'c':
6914                 if (ifthen_state)
6915                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
6916                 break;
6917
6918               case 'x':
6919                 if (ifthen_next_state)
6920                   func (stream, "\t; unpredictable branch in IT block\n");
6921                 break;
6922
6923               case 'X':
6924                 if (ifthen_state)
6925                   func (stream, "\t; unpredictable <IT:%s>",
6926                         arm_conditional[IFTHEN_COND]);
6927                 break;
6928
6929               case 'I':
6930                 {
6931                   unsigned int imm12 = 0;
6932
6933                   imm12 |= (given & 0x000000ffu);
6934                   imm12 |= (given & 0x00007000u) >> 4;
6935                   imm12 |= (given & 0x04000000u) >> 15;
6936                   func (stream, "#%u", imm12);
6937                   value_in_comment = imm12;
6938                 }
6939                 break;
6940
6941               case 'M':
6942                 {
6943                   unsigned int bits = 0, imm, imm8, mod;
6944
6945                   bits |= (given & 0x000000ffu);
6946                   bits |= (given & 0x00007000u) >> 4;
6947                   bits |= (given & 0x04000000u) >> 15;
6948                   imm8 = (bits & 0x0ff);
6949                   mod = (bits & 0xf00) >> 8;
6950                   switch (mod)
6951                     {
6952                     case 0: imm = imm8; break;
6953                     case 1: imm = ((imm8 << 16) | imm8); break;
6954                     case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
6955                     case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
6956                     default:
6957                       mod  = (bits & 0xf80) >> 7;
6958                       imm8 = (bits & 0x07f) | 0x80;
6959                       imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
6960                     }
6961                   func (stream, "#%u", imm);
6962                   value_in_comment = imm;
6963                 }
6964                 break;
6965
6966               case 'J':
6967                 {
6968                   unsigned int imm = 0;
6969
6970                   imm |= (given & 0x000000ffu);
6971                   imm |= (given & 0x00007000u) >> 4;
6972                   imm |= (given & 0x04000000u) >> 15;
6973                   imm |= (given & 0x000f0000u) >> 4;
6974                   func (stream, "#%u", imm);
6975                   value_in_comment = imm;
6976                 }
6977                 break;
6978
6979               case 'K':
6980                 {
6981                   unsigned int imm = 0;
6982
6983                   imm |= (given & 0x000f0000u) >> 16;
6984                   imm |= (given & 0x00000ff0u) >> 0;
6985                   imm |= (given & 0x0000000fu) << 12;
6986                   func (stream, "#%u", imm);
6987                   value_in_comment = imm;
6988                 }
6989                 break;
6990
6991               case 'H':
6992                 {
6993                   unsigned int imm = 0;
6994
6995                   imm |= (given & 0x000f0000u) >> 4;
6996                   imm |= (given & 0x00000fffu) >> 0;
6997                   func (stream, "#%u", imm);
6998                   value_in_comment = imm;
6999                 }
7000                 break;
7001
7002               case 'V':
7003                 {
7004                   unsigned int imm = 0;
7005
7006                   imm |= (given & 0x00000fffu);
7007                   imm |= (given & 0x000f0000u) >> 4;
7008                   func (stream, "#%u", imm);
7009                   value_in_comment = imm;
7010                 }
7011                 break;
7012
7013               case 'S':
7014                 {
7015                   unsigned int reg = (given & 0x0000000fu);
7016                   unsigned int stp = (given & 0x00000030u) >> 4;
7017                   unsigned int imm = 0;
7018                   imm |= (given & 0x000000c0u) >> 6;
7019                   imm |= (given & 0x00007000u) >> 10;
7020
7021                   func (stream, "%s", arm_regnames[reg]);
7022                   switch (stp)
7023                     {
7024                     case 0:
7025                       if (imm > 0)
7026                         func (stream, ", lsl #%u", imm);
7027                       break;
7028
7029                     case 1:
7030                       if (imm == 0)
7031                         imm = 32;
7032                       func (stream, ", lsr #%u", imm);
7033                       break;
7034
7035                     case 2:
7036                       if (imm == 0)
7037                         imm = 32;
7038                       func (stream, ", asr #%u", imm);
7039                       break;
7040
7041                     case 3:
7042                       if (imm == 0)
7043                         func (stream, ", rrx");
7044                       else
7045                         func (stream, ", ror #%u", imm);
7046                     }
7047                 }
7048                 break;
7049
7050               case 'a':
7051                 {
7052                   unsigned int Rn  = (given & 0x000f0000) >> 16;
7053                   unsigned int U   = ! NEGATIVE_BIT_SET;
7054                   unsigned int op  = (given & 0x00000f00) >> 8;
7055                   unsigned int i12 = (given & 0x00000fff);
7056                   unsigned int i8  = (given & 0x000000ff);
7057                   bfd_boolean writeback = FALSE, postind = FALSE;
7058                   bfd_vma offset = 0;
7059
7060                   func (stream, "[%s", arm_regnames[Rn]);
7061                   if (U) /* 12-bit positive immediate offset.  */
7062                     {
7063                       offset = i12;
7064                       if (Rn != 15)
7065                         value_in_comment = offset;
7066                     }
7067                   else if (Rn == 15) /* 12-bit negative immediate offset.  */
7068                     offset = - (int) i12;
7069                   else if (op == 0x0) /* Shifted register offset.  */
7070                     {
7071                       unsigned int Rm = (i8 & 0x0f);
7072                       unsigned int sh = (i8 & 0x30) >> 4;
7073
7074                       func (stream, ", %s", arm_regnames[Rm]);
7075                       if (sh)
7076                         func (stream, ", lsl #%u", sh);
7077                       func (stream, "]");
7078                       break;
7079                     }
7080                   else switch (op)
7081                     {
7082                     case 0xE:  /* 8-bit positive immediate offset.  */
7083                       offset = i8;
7084                       break;
7085
7086                     case 0xC:  /* 8-bit negative immediate offset.  */
7087                       offset = -i8;
7088                       break;
7089
7090                     case 0xF:  /* 8-bit + preindex with wb.  */
7091                       offset = i8;
7092                       writeback = TRUE;
7093                       break;
7094
7095                     case 0xD:  /* 8-bit - preindex with wb.  */
7096                       offset = -i8;
7097                       writeback = TRUE;
7098                       break;
7099
7100                     case 0xB:  /* 8-bit + postindex.  */
7101                       offset = i8;
7102                       postind = TRUE;
7103                       break;
7104
7105                     case 0x9:  /* 8-bit - postindex.  */
7106                       offset = -i8;
7107                       postind = TRUE;
7108                       break;
7109
7110                     default:
7111                       func (stream, ", <undefined>]");
7112                       goto skip;
7113                     }
7114
7115                   if (postind)
7116                     func (stream, "], #%d", (int) offset);
7117                   else
7118                     {
7119                       if (offset)
7120                         func (stream, ", #%d", (int) offset);
7121                       func (stream, writeback ? "]!" : "]");
7122                     }
7123
7124                   if (Rn == 15)
7125                     {
7126                       func (stream, "\t; ");
7127                       info->print_address_func (((pc + 4) & ~3) + offset, info);
7128                     }
7129                 }
7130               skip:
7131                 break;
7132
7133               case 'A':
7134                 {
7135                   unsigned int U   = ! NEGATIVE_BIT_SET;
7136                   unsigned int W   = WRITEBACK_BIT_SET;
7137                   unsigned int Rn  = (given & 0x000f0000) >> 16;
7138                   unsigned int off = (given & 0x000000ff);
7139
7140                   func (stream, "[%s", arm_regnames[Rn]);
7141
7142                   if (PRE_BIT_SET)
7143                     {
7144                       if (off || !U)
7145                         {
7146                           func (stream, ", #%c%u", U ? '+' : '-', off * 4);
7147                           value_in_comment = off * 4 * (U ? 1 : -1);
7148                         }
7149                       func (stream, "]");
7150                       if (W)
7151                         func (stream, "!");
7152                     }
7153                   else
7154                     {
7155                       func (stream, "], ");
7156                       if (W)
7157                         {
7158                           func (stream, "#%c%u", U ? '+' : '-', off * 4);
7159                           value_in_comment = off * 4 * (U ? 1 : -1);
7160                         }
7161                       else
7162                         {
7163                           func (stream, "{%u}", off);
7164                           value_in_comment = off;
7165                         }
7166                     }
7167                 }
7168                 break;
7169
7170               case 'w':
7171                 {
7172                   unsigned int Sbit = (given & 0x01000000) >> 24;
7173                   unsigned int type = (given & 0x00600000) >> 21;
7174
7175                   switch (type)
7176                     {
7177                     case 0: func (stream, Sbit ? "sb" : "b"); break;
7178                     case 1: func (stream, Sbit ? "sh" : "h"); break;
7179                     case 2:
7180                       if (Sbit)
7181                         func (stream, "??");
7182                       break;
7183                     case 3:
7184                       func (stream, "??");
7185                       break;
7186                     }
7187                 }
7188                 break;
7189
7190               case 'n':
7191                 is_clrm = TRUE;
7192                 /* Fall through.  */
7193               case 'm':
7194                 {
7195                   int started = 0;
7196                   int reg;
7197
7198                   func (stream, "{");
7199                   for (reg = 0; reg < 16; reg++)
7200                     if ((given & (1 << reg)) != 0)
7201                       {
7202                         if (started)
7203                           func (stream, ", ");
7204                         started = 1;
7205                         if (is_clrm && reg == 13)
7206                           func (stream, "(invalid: %s)", arm_regnames[reg]);
7207                         else if (is_clrm && reg == 15)
7208                           func (stream, "%s", "APSR");
7209                         else
7210                           func (stream, "%s", arm_regnames[reg]);
7211                       }
7212                   func (stream, "}");
7213                 }
7214                 break;
7215
7216               case 'E':
7217                 {
7218                   unsigned int msb = (given & 0x0000001f);
7219                   unsigned int lsb = 0;
7220
7221                   lsb |= (given & 0x000000c0u) >> 6;
7222                   lsb |= (given & 0x00007000u) >> 10;
7223                   func (stream, "#%u, #%u", lsb, msb - lsb + 1);
7224                 }
7225                 break;
7226
7227               case 'F':
7228                 {
7229                   unsigned int width = (given & 0x0000001f) + 1;
7230                   unsigned int lsb = 0;
7231
7232                   lsb |= (given & 0x000000c0u) >> 6;
7233                   lsb |= (given & 0x00007000u) >> 10;
7234                   func (stream, "#%u, #%u", lsb, width);
7235                 }
7236                 break;
7237
7238               case 'G':
7239                 {
7240                   unsigned int boff = (((given & 0x07800000) >> 23) << 1);
7241                   func (stream, "%x", boff);
7242                 }
7243                 break;
7244
7245               case 'W':
7246                 {
7247                   unsigned int immA = (given & 0x001f0000u) >> 16;
7248                   unsigned int immB = (given & 0x000007feu) >> 1;
7249                   unsigned int immC = (given & 0x00000800u) >> 11;
7250                   bfd_vma offset = 0;
7251
7252                   offset |= immA << 12;
7253                   offset |= immB << 2;
7254                   offset |= immC << 1;
7255                   /* Sign extend.  */
7256                   offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
7257
7258                   info->print_address_func (pc + 4 + offset, info);
7259                 }
7260                 break;
7261
7262               case 'Y':
7263                 {
7264                   unsigned int immA = (given & 0x007f0000u) >> 16;
7265                   unsigned int immB = (given & 0x000007feu) >> 1;
7266                   unsigned int immC = (given & 0x00000800u) >> 11;
7267                   bfd_vma offset = 0;
7268
7269                   offset |= immA << 12;
7270                   offset |= immB << 2;
7271                   offset |= immC << 1;
7272                   /* Sign extend.  */
7273                   offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
7274
7275                   info->print_address_func (pc + 4 + offset, info);
7276                 }
7277                 break;
7278
7279               case 'Z':
7280                 {
7281                   unsigned int immA = (given & 0x00010000u) >> 16;
7282                   unsigned int immB = (given & 0x000007feu) >> 1;
7283                   unsigned int immC = (given & 0x00000800u) >> 11;
7284                   bfd_vma offset = 0;
7285
7286                   offset |= immA << 12;
7287                   offset |= immB << 2;
7288                   offset |= immC << 1;
7289                   /* Sign extend.  */
7290                   offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
7291
7292                   info->print_address_func (pc + 4 + offset, info);
7293
7294                   unsigned int T    = (given & 0x00020000u) >> 17;
7295                   unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
7296                   unsigned int boffset   = (T == 1) ? 4 : 2;
7297                   func (stream, ", ");
7298                   func (stream, "%x", endoffset + boffset);
7299                 }
7300                 break;
7301
7302               case 'Q':
7303                 {
7304                   unsigned int immh = (given & 0x000007feu) >> 1;
7305                   unsigned int imml = (given & 0x00000800u) >> 11;
7306                   bfd_vma imm32 = 0;
7307
7308                   imm32 |= immh << 2;
7309                   imm32 |= imml << 1;
7310
7311                   info->print_address_func (pc + 4 + imm32, info);
7312                 }
7313                 break;
7314
7315               case 'P':
7316                 {
7317                   unsigned int immh = (given & 0x000007feu) >> 1;
7318                   unsigned int imml = (given & 0x00000800u) >> 11;
7319                   bfd_vma imm32 = 0;
7320
7321                   imm32 |= immh << 2;
7322                   imm32 |= imml << 1;
7323
7324                   info->print_address_func (pc + 4 - imm32, info);
7325                 }
7326                 break;
7327
7328               case 'b':
7329                 {
7330                   unsigned int S = (given & 0x04000000u) >> 26;
7331                   unsigned int J1 = (given & 0x00002000u) >> 13;
7332                   unsigned int J2 = (given & 0x00000800u) >> 11;
7333                   bfd_vma offset = 0;
7334
7335                   offset |= !S << 20;
7336                   offset |= J2 << 19;
7337                   offset |= J1 << 18;
7338                   offset |= (given & 0x003f0000) >> 4;
7339                   offset |= (given & 0x000007ff) << 1;
7340                   offset -= (1 << 20);
7341
7342                   info->print_address_func (pc + 4 + offset, info);
7343                 }
7344                 break;
7345
7346               case 'B':
7347                 {
7348                   unsigned int S = (given & 0x04000000u) >> 26;
7349                   unsigned int I1 = (given & 0x00002000u) >> 13;
7350                   unsigned int I2 = (given & 0x00000800u) >> 11;
7351                   bfd_vma offset = 0;
7352
7353                   offset |= !S << 24;
7354                   offset |= !(I1 ^ S) << 23;
7355                   offset |= !(I2 ^ S) << 22;
7356                   offset |= (given & 0x03ff0000u) >> 4;
7357                   offset |= (given & 0x000007ffu) << 1;
7358                   offset -= (1 << 24);
7359                   offset += pc + 4;
7360
7361                   /* BLX target addresses are always word aligned.  */
7362                   if ((given & 0x00001000u) == 0)
7363                       offset &= ~2u;
7364
7365                   info->print_address_func (offset, info);
7366                 }
7367                 break;
7368
7369               case 's':
7370                 {
7371                   unsigned int shift = 0;
7372
7373                   shift |= (given & 0x000000c0u) >> 6;
7374                   shift |= (given & 0x00007000u) >> 10;
7375                   if (WRITEBACK_BIT_SET)
7376                     func (stream, ", asr #%u", shift);
7377                   else if (shift)
7378                     func (stream, ", lsl #%u", shift);
7379                   /* else print nothing - lsl #0 */
7380                 }
7381                 break;
7382
7383               case 'R':
7384                 {
7385                   unsigned int rot = (given & 0x00000030) >> 4;
7386
7387                   if (rot)
7388                     func (stream, ", ror #%u", rot * 8);
7389                 }
7390                 break;
7391
7392               case 'U':
7393                 if ((given & 0xf0) == 0x60)
7394                   {
7395                     switch (given & 0xf)
7396                       {
7397                         case 0xf: func (stream, "sy"); break;
7398                         default:
7399                           func (stream, "#%d", (int) given & 0xf);
7400                               break;
7401                       }
7402                   }
7403                 else
7404                   {
7405                     const char * opt = data_barrier_option (given & 0xf);
7406                     if (opt != NULL)
7407                       func (stream, "%s", opt);
7408                     else
7409                       func (stream, "#%d", (int) given & 0xf);
7410                    }
7411                 break;
7412
7413               case 'C':
7414                 if ((given & 0xff) == 0)
7415                   {
7416                     func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
7417                     if (given & 0x800)
7418                       func (stream, "f");
7419                     if (given & 0x400)
7420                       func (stream, "s");
7421                     if (given & 0x200)
7422                       func (stream, "x");
7423                     if (given & 0x100)
7424                       func (stream, "c");
7425                   }
7426                 else if ((given & 0x20) == 0x20)
7427                   {
7428                     char const* name;
7429                     unsigned sysm = (given & 0xf00) >> 8;
7430
7431                     sysm |= (given & 0x30);
7432                     sysm |= (given & 0x00100000) >> 14;
7433                     name = banked_regname (sysm);
7434
7435                     if (name != NULL)
7436                       func (stream, "%s", name);
7437                     else
7438                       func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
7439                   }
7440                 else
7441                   {
7442                     func (stream, "%s", psr_name (given & 0xff));
7443                   }
7444                 break;
7445
7446               case 'D':
7447                 if (((given & 0xff) == 0)
7448                     || ((given & 0x20) == 0x20))
7449                   {
7450                     char const* name;
7451                     unsigned sm = (given & 0xf0000) >> 16;
7452
7453                     sm |= (given & 0x30);
7454                     sm |= (given & 0x00100000) >> 14;
7455                     name = banked_regname (sm);
7456
7457                     if (name != NULL)
7458                       func (stream, "%s", name);
7459                     else
7460                       func (stream, "(UNDEF: %lu)", (unsigned long) sm);
7461                   }
7462                 else
7463                   func (stream, "%s", psr_name (given & 0xff));
7464                 break;
7465
7466               case '0': case '1': case '2': case '3': case '4':
7467               case '5': case '6': case '7': case '8': case '9':
7468                 {
7469                   int width;
7470                   unsigned long val;
7471
7472                   c = arm_decode_bitfield (c, given, &val, &width);
7473
7474                   switch (*c)
7475                     {
7476                     case 'd':
7477                       func (stream, "%lu", val);
7478                       value_in_comment = val;
7479                       break;
7480
7481                     case 'D':
7482                       func (stream, "%lu", val + 1);
7483                       value_in_comment = val + 1;
7484                       break;
7485
7486                     case 'W':
7487                       func (stream, "%lu", val * 4);
7488                       value_in_comment = val * 4;
7489                       break;
7490
7491                     case 'S':
7492                       if (val == 13)
7493                         is_unpredictable = TRUE;
7494                       /* Fall through.  */
7495                     case 'R':
7496                       if (val == 15)
7497                         is_unpredictable = TRUE;
7498                       /* Fall through.  */
7499                     case 'r':
7500                       func (stream, "%s", arm_regnames[val]);
7501                       break;
7502
7503                     case 'c':
7504                       func (stream, "%s", arm_conditional[val]);
7505                       break;
7506
7507                     case '\'':
7508                       c++;
7509                       if (val == ((1ul << width) - 1))
7510                         func (stream, "%c", *c);
7511                       break;
7512
7513                     case '`':
7514                       c++;
7515                       if (val == 0)
7516                         func (stream, "%c", *c);
7517                       break;
7518
7519                     case '?':
7520                       func (stream, "%c", c[(1 << width) - (int) val]);
7521                       c += 1 << width;
7522                       break;
7523
7524                     case 'x':
7525                       func (stream, "0x%lx", val & 0xffffffffUL);
7526                       break;
7527
7528                     default:
7529                       abort ();
7530                     }
7531                 }
7532                 break;
7533
7534               case 'L':
7535                 /* PR binutils/12534
7536                    If we have a PC relative offset in an LDRD or STRD
7537                    instructions then display the decoded address.  */
7538                 if (((given >> 16) & 0xf) == 0xf)
7539                   {
7540                     bfd_vma offset = (given & 0xff) * 4;
7541
7542                     if ((given & (1 << 23)) == 0)
7543                       offset = - offset;
7544                     func (stream, "\t; ");
7545                     info->print_address_func ((pc & ~3) + 4 + offset, info);
7546                   }
7547                 break;
7548
7549               default:
7550                 abort ();
7551               }
7552           }
7553
7554         if (value_in_comment > 32 || value_in_comment < -16)
7555           func (stream, "\t; 0x%lx", value_in_comment);
7556
7557         if (is_unpredictable)
7558           func (stream, UNPREDICTABLE_INSTRUCTION);
7559
7560         return;
7561       }
7562
7563   /* No match.  */
7564   func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
7565   return;
7566 }
7567
7568 /* Print data bytes on INFO->STREAM.  */
7569
7570 static void
7571 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
7572                  struct disassemble_info *info,
7573                  long given)
7574 {
7575   switch (info->bytes_per_chunk)
7576     {
7577     case 1:
7578       info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
7579       break;
7580     case 2:
7581       info->fprintf_func (info->stream, ".short\t0x%04lx", given);
7582       break;
7583     case 4:
7584       info->fprintf_func (info->stream, ".word\t0x%08lx", given);
7585       break;
7586     default:
7587       abort ();
7588     }
7589 }
7590
7591 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
7592    being displayed in symbol relative addresses.
7593
7594    Also disallow private symbol, with __tagsym$$ prefix,
7595    from ARM RVCT toolchain being displayed.  */
7596
7597 bfd_boolean
7598 arm_symbol_is_valid (asymbol * sym,
7599                      struct disassemble_info * info ATTRIBUTE_UNUSED)
7600 {
7601   const char * name;
7602
7603   if (sym == NULL)
7604     return FALSE;
7605
7606   name = bfd_asymbol_name (sym);
7607
7608   return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
7609 }
7610
7611 /* Parse the string of disassembler options.  */
7612
7613 static void
7614 parse_arm_disassembler_options (const char *options)
7615 {
7616   const char *opt;
7617
7618   FOR_EACH_DISASSEMBLER_OPTION (opt, options)
7619     {
7620       if (CONST_STRNEQ (opt, "reg-names-"))
7621         {
7622           unsigned int i;
7623           for (i = 0; i < NUM_ARM_OPTIONS; i++)
7624             if (disassembler_options_cmp (opt, regnames[i].name) == 0)
7625               {
7626                 regname_selected = i;
7627                 break;
7628               }
7629
7630           if (i >= NUM_ARM_OPTIONS)
7631             /* xgettext: c-format */
7632             opcodes_error_handler (_("unrecognised register name set: %s"),
7633                                    opt);
7634         }
7635       else if (CONST_STRNEQ (opt, "force-thumb"))
7636         force_thumb = 1;
7637       else if (CONST_STRNEQ (opt, "no-force-thumb"))
7638         force_thumb = 0;
7639       else
7640         /* xgettext: c-format */
7641         opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
7642     }
7643
7644   return;
7645 }
7646
7647 static bfd_boolean
7648 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
7649                          enum map_type *map_symbol);
7650
7651 /* Search back through the insn stream to determine if this instruction is
7652    conditionally executed.  */
7653
7654 static void
7655 find_ifthen_state (bfd_vma pc,
7656                    struct disassemble_info *info,
7657                    bfd_boolean little)
7658 {
7659   unsigned char b[2];
7660   unsigned int insn;
7661   int status;
7662   /* COUNT is twice the number of instructions seen.  It will be odd if we
7663      just crossed an instruction boundary.  */
7664   int count;
7665   int it_count;
7666   unsigned int seen_it;
7667   bfd_vma addr;
7668
7669   ifthen_address = pc;
7670   ifthen_state = 0;
7671
7672   addr = pc;
7673   count = 1;
7674   it_count = 0;
7675   seen_it = 0;
7676   /* Scan backwards looking for IT instructions, keeping track of where
7677      instruction boundaries are.  We don't know if something is actually an
7678      IT instruction until we find a definite instruction boundary.  */
7679   for (;;)
7680     {
7681       if (addr == 0 || info->symbol_at_address_func (addr, info))
7682         {
7683           /* A symbol must be on an instruction boundary, and will not
7684              be within an IT block.  */
7685           if (seen_it && (count & 1))
7686             break;
7687
7688           return;
7689         }
7690       addr -= 2;
7691       status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
7692       if (status)
7693         return;
7694
7695       if (little)
7696         insn = (b[0]) | (b[1] << 8);
7697       else
7698         insn = (b[1]) | (b[0] << 8);
7699       if (seen_it)
7700         {
7701           if ((insn & 0xf800) < 0xe800)
7702             {
7703               /* Addr + 2 is an instruction boundary.  See if this matches
7704                  the expected boundary based on the position of the last
7705                  IT candidate.  */
7706               if (count & 1)
7707                 break;
7708               seen_it = 0;
7709             }
7710         }
7711       if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
7712         {
7713           enum map_type type = MAP_ARM;
7714           bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
7715
7716           if (!found || (found && type == MAP_THUMB))
7717             {
7718               /* This could be an IT instruction.  */
7719               seen_it = insn;
7720               it_count = count >> 1;
7721             }
7722         }
7723       if ((insn & 0xf800) >= 0xe800)
7724         count++;
7725       else
7726         count = (count + 2) | 1;
7727       /* IT blocks contain at most 4 instructions.  */
7728       if (count >= 8 && !seen_it)
7729         return;
7730     }
7731   /* We found an IT instruction.  */
7732   ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
7733   if ((ifthen_state & 0xf) == 0)
7734     ifthen_state = 0;
7735 }
7736
7737 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
7738    mapping symbol.  */
7739
7740 static int
7741 is_mapping_symbol (struct disassemble_info *info, int n,
7742                    enum map_type *map_type)
7743 {
7744   const char *name;
7745
7746   name = bfd_asymbol_name (info->symtab[n]);
7747   if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
7748       && (name[2] == 0 || name[2] == '.'))
7749     {
7750       *map_type = ((name[1] == 'a') ? MAP_ARM
7751                    : (name[1] == 't') ? MAP_THUMB
7752                    : MAP_DATA);
7753       return TRUE;
7754     }
7755
7756   return FALSE;
7757 }
7758
7759 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
7760    Returns nonzero if *MAP_TYPE was set.  */
7761
7762 static int
7763 get_map_sym_type (struct disassemble_info *info,
7764                   int n,
7765                   enum map_type *map_type)
7766 {
7767   /* If the symbol is in a different section, ignore it.  */
7768   if (info->section != NULL && info->section != info->symtab[n]->section)
7769     return FALSE;
7770
7771   return is_mapping_symbol (info, n, map_type);
7772 }
7773
7774 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
7775    Returns nonzero if *MAP_TYPE was set.  */
7776
7777 static int
7778 get_sym_code_type (struct disassemble_info *info,
7779                    int n,
7780                    enum map_type *map_type)
7781 {
7782   elf_symbol_type *es;
7783   unsigned int type;
7784
7785   /* If the symbol is in a different section, ignore it.  */
7786   if (info->section != NULL && info->section != info->symtab[n]->section)
7787     return FALSE;
7788
7789   es = *(elf_symbol_type **)(info->symtab + n);
7790   type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
7791
7792   /* If the symbol has function type then use that.  */
7793   if (type == STT_FUNC || type == STT_GNU_IFUNC)
7794     {
7795       if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
7796           == ST_BRANCH_TO_THUMB)
7797         *map_type = MAP_THUMB;
7798       else
7799         *map_type = MAP_ARM;
7800       return TRUE;
7801     }
7802
7803   return FALSE;
7804 }
7805
7806 /* Search the mapping symbol state for instruction at pc.  This is only
7807    applicable for elf target.
7808
7809    There is an assumption Here, info->private_data contains the correct AND
7810    up-to-date information about current scan process.  The information will be
7811    used to speed this search process.
7812
7813    Return TRUE if the mapping state can be determined, and map_symbol
7814    will be updated accordingly.  Otherwise, return FALSE.  */
7815
7816 static bfd_boolean
7817 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
7818                          enum map_type *map_symbol)
7819 {
7820   bfd_vma addr, section_vma = 0;
7821   int n, last_sym = -1;
7822   bfd_boolean found = FALSE;
7823   bfd_boolean can_use_search_opt_p = FALSE;
7824
7825   /* Default to DATA.  A text section is required by the ABI to contain an
7826      INSN mapping symbol at the start.  A data section has no such
7827      requirement, hence if no mapping symbol is found the section must
7828      contain only data.  This however isn't very useful if the user has
7829      fully stripped the binaries.  If this is the case use the section
7830      attributes to determine the default.  If we have no section default to
7831      INSN as well, as we may be disassembling some raw bytes on a baremetal
7832      HEX file or similar.  */
7833   enum map_type type = MAP_DATA;
7834   if ((info->section && info->section->flags & SEC_CODE) || !info->section)
7835     type = MAP_ARM;
7836   struct arm_private_data *private_data;
7837
7838   if (info->private_data == NULL
7839       || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
7840     return FALSE;
7841
7842   private_data = info->private_data;
7843
7844   /* First, look for mapping symbols.  */
7845   if (info->symtab_size != 0)
7846   {
7847     if (pc <= private_data->last_mapping_addr)
7848       private_data->last_mapping_sym = -1;
7849
7850     /* Start scanning at the start of the function, or wherever
7851        we finished last time.  */
7852     n = info->symtab_pos + 1;
7853
7854     /* If the last stop offset is different from the current one it means we
7855        are disassembling a different glob of bytes.  As such the optimization
7856        would not be safe and we should start over.  */
7857     can_use_search_opt_p
7858       = private_data->last_mapping_sym >= 0
7859         && info->stop_offset == private_data->last_stop_offset;
7860
7861     if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
7862       n = private_data->last_mapping_sym;
7863
7864     /* Look down while we haven't passed the location being disassembled.
7865        The reason for this is that there's no defined order between a symbol
7866        and an mapping symbol that may be at the same address.  We may have to
7867        look at least one position ahead.  */
7868     for (; n < info->symtab_size; n++)
7869       {
7870         addr = bfd_asymbol_value (info->symtab[n]);
7871         if (addr > pc)
7872           break;
7873         if (get_map_sym_type (info, n, &type))
7874           {
7875             last_sym = n;
7876             found = TRUE;
7877           }
7878       }
7879
7880     if (!found)
7881       {
7882         n = info->symtab_pos;
7883         if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
7884           n = private_data->last_mapping_sym;
7885
7886         /* No mapping symbol found at this address.  Look backwards
7887            for a preceeding one, but don't go pass the section start
7888            otherwise a data section with no mapping symbol can pick up
7889            a text mapping symbol of a preceeding section.  The documentation
7890            says section can be NULL, in which case we will seek up all the
7891            way to the top.  */
7892         if (info->section)
7893           section_vma = info->section->vma;
7894
7895         for (; n >= 0; n--)
7896           {
7897             addr = bfd_asymbol_value (info->symtab[n]);
7898             if (addr < section_vma)
7899               break;
7900
7901             if (get_map_sym_type (info, n, &type))
7902               {
7903                 last_sym = n;
7904                 found = TRUE;
7905                 break;
7906               }
7907           }
7908       }
7909   }
7910
7911   /* If no mapping symbol was found, try looking up without a mapping
7912      symbol.  This is done by walking up from the current PC to the nearest
7913      symbol.  We don't actually have to loop here since symtab_pos will
7914      contain the nearest symbol already.  */
7915   if (!found)
7916     {
7917       n = info->symtab_pos;
7918       if (n >= 0 && get_sym_code_type (info, n, &type))
7919         {
7920           last_sym = n;
7921           found = TRUE;
7922         }
7923     }
7924
7925   private_data->last_mapping_sym = last_sym;
7926   private_data->last_type = type;
7927   private_data->last_stop_offset = info->stop_offset;
7928
7929   *map_symbol = type;
7930   return found;
7931 }
7932
7933 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
7934    of the supplied arm_feature_set structure with bitmasks indicating
7935    the supported base architectures and coprocessor extensions.
7936
7937    FIXME: This could more efficiently implemented as a constant array,
7938    although it would also be less robust.  */
7939
7940 static void
7941 select_arm_features (unsigned long mach,
7942                      arm_feature_set * features)
7943 {
7944   arm_feature_set arch_fset;
7945   const arm_feature_set fpu_any = FPU_ANY;
7946
7947 #undef ARM_SET_FEATURES
7948 #define ARM_SET_FEATURES(FSET) \
7949   {                                                     \
7950     const arm_feature_set fset = FSET;                  \
7951     arch_fset = fset;                                   \
7952   }
7953
7954   /* When several architecture versions share the same bfd_mach_arm_XXX value
7955      the most featureful is chosen.  */
7956   switch (mach)
7957     {
7958     case bfd_mach_arm_2:         ARM_SET_FEATURES (ARM_ARCH_V2); break;
7959     case bfd_mach_arm_2a:        ARM_SET_FEATURES (ARM_ARCH_V2S); break;
7960     case bfd_mach_arm_3:         ARM_SET_FEATURES (ARM_ARCH_V3); break;
7961     case bfd_mach_arm_3M:        ARM_SET_FEATURES (ARM_ARCH_V3M); break;
7962     case bfd_mach_arm_4:         ARM_SET_FEATURES (ARM_ARCH_V4); break;
7963     case bfd_mach_arm_4T:        ARM_SET_FEATURES (ARM_ARCH_V4T); break;
7964     case bfd_mach_arm_5:         ARM_SET_FEATURES (ARM_ARCH_V5); break;
7965     case bfd_mach_arm_5T:        ARM_SET_FEATURES (ARM_ARCH_V5T); break;
7966     case bfd_mach_arm_5TE:       ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
7967     case bfd_mach_arm_XScale:    ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
7968     case bfd_mach_arm_ep9312:
7969         ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
7970                                            ARM_CEXT_MAVERICK | FPU_MAVERICK));
7971        break;
7972     case bfd_mach_arm_iWMMXt:    ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
7973     case bfd_mach_arm_iWMMXt2:   ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
7974     case bfd_mach_arm_5TEJ:      ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
7975     case bfd_mach_arm_6:         ARM_SET_FEATURES (ARM_ARCH_V6); break;
7976     case bfd_mach_arm_6KZ:       ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
7977     case bfd_mach_arm_6T2:       ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
7978     case bfd_mach_arm_6K:        ARM_SET_FEATURES (ARM_ARCH_V6K); break;
7979     case bfd_mach_arm_7:         ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
7980     case bfd_mach_arm_6M:        ARM_SET_FEATURES (ARM_ARCH_V6M); break;
7981     case bfd_mach_arm_6SM:       ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
7982     case bfd_mach_arm_7EM:       ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
7983     case bfd_mach_arm_8:
7984         {
7985           /* Add bits for extensions that Armv8.5-A recognizes.  */
7986           arm_feature_set armv8_5_ext_fset
7987             = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
7988           ARM_SET_FEATURES (ARM_ARCH_V8_5A);
7989           ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
7990           break;
7991         }
7992     case bfd_mach_arm_8R:        ARM_SET_FEATURES (ARM_ARCH_V8R); break;
7993     case bfd_mach_arm_8M_BASE:   ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
7994     case bfd_mach_arm_8M_MAIN:   ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
7995     case bfd_mach_arm_8_1M_MAIN:
7996       ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
7997       force_thumb = 1;
7998       break;
7999       /* If the machine type is unknown allow all architecture types and all
8000          extensions.  */
8001     case bfd_mach_arm_unknown:   ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
8002     default:
8003       abort ();
8004     }
8005 #undef ARM_SET_FEATURES
8006
8007   /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
8008      and thus on bfd_mach_arm_XXX value.  Therefore for a given
8009      bfd_mach_arm_XXX value all coprocessor feature bits should be allowed.  */
8010   ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
8011 }
8012
8013
8014 /* NOTE: There are no checks in these routines that
8015    the relevant number of data bytes exist.  */
8016
8017 static int
8018 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
8019 {
8020   unsigned char b[4];
8021   long          given;
8022   int           status;
8023   int           is_thumb = FALSE;
8024   int           is_data = FALSE;
8025   int           little_code;
8026   unsigned int  size = 4;
8027   void          (*printer) (bfd_vma, struct disassemble_info *, long);
8028   bfd_boolean   found = FALSE;
8029   struct arm_private_data *private_data;
8030
8031   if (info->disassembler_options)
8032     {
8033       parse_arm_disassembler_options (info->disassembler_options);
8034
8035       /* To avoid repeated parsing of these options, we remove them here.  */
8036       info->disassembler_options = NULL;
8037     }
8038
8039   /* PR 10288: Control which instructions will be disassembled.  */
8040   if (info->private_data == NULL)
8041     {
8042       static struct arm_private_data private;
8043
8044       if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
8045         /* If the user did not use the -m command line switch then default to
8046            disassembling all types of ARM instruction.
8047
8048            The info->mach value has to be ignored as this will be based on
8049            the default archictecture for the target and/or hints in the notes
8050            section, but it will never be greater than the current largest arm
8051            machine value (iWMMXt2), which is only equivalent to the V5TE
8052            architecture.  ARM architectures have advanced beyond the machine
8053            value encoding, and these newer architectures would be ignored if
8054            the machine value was used.
8055
8056            Ie the -m switch is used to restrict which instructions will be
8057            disassembled.  If it is necessary to use the -m switch to tell
8058            objdump that an ARM binary is being disassembled, eg because the
8059            input is a raw binary file, but it is also desired to disassemble
8060            all ARM instructions then use "-marm".  This will select the
8061            "unknown" arm architecture which is compatible with any ARM
8062            instruction.  */
8063           info->mach = bfd_mach_arm_unknown;
8064
8065       /* Compute the architecture bitmask from the machine number.
8066          Note: This assumes that the machine number will not change
8067          during disassembly....  */
8068       select_arm_features (info->mach, & private.features);
8069
8070       private.last_mapping_sym = -1;
8071       private.last_mapping_addr = 0;
8072       private.last_stop_offset = 0;
8073
8074       info->private_data = & private;
8075     }
8076
8077   private_data = info->private_data;
8078
8079   /* Decide if our code is going to be little-endian, despite what the
8080      function argument might say.  */
8081   little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
8082
8083   /* For ELF, consult the symbol table to determine what kind of code
8084      or data we have.  */
8085   if (info->symtab_size != 0
8086       && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
8087     {
8088       bfd_vma addr;
8089       int n;
8090       int last_sym = -1;
8091       enum map_type type = MAP_ARM;
8092
8093       found = mapping_symbol_for_insn (pc, info, &type);
8094       last_sym = private_data->last_mapping_sym;
8095
8096       is_thumb = (private_data->last_type == MAP_THUMB);
8097       is_data = (private_data->last_type == MAP_DATA);
8098
8099       /* Look a little bit ahead to see if we should print out
8100          two or four bytes of data.  If there's a symbol,
8101          mapping or otherwise, after two bytes then don't
8102          print more.  */
8103       if (is_data)
8104         {
8105           size = 4 - (pc & 3);
8106           for (n = last_sym + 1; n < info->symtab_size; n++)
8107             {
8108               addr = bfd_asymbol_value (info->symtab[n]);
8109               if (addr > pc
8110                   && (info->section == NULL
8111                       || info->section == info->symtab[n]->section))
8112                 {
8113                   if (addr - pc < size)
8114                     size = addr - pc;
8115                   break;
8116                 }
8117             }
8118           /* If the next symbol is after three bytes, we need to
8119              print only part of the data, so that we can use either
8120              .byte or .short.  */
8121           if (size == 3)
8122             size = (pc & 1) ? 1 : 2;
8123         }
8124     }
8125
8126   if (info->symbols != NULL)
8127     {
8128       if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
8129         {
8130           coff_symbol_type * cs;
8131
8132           cs = coffsymbol (*info->symbols);
8133           is_thumb = (   cs->native->u.syment.n_sclass == C_THUMBEXT
8134                       || cs->native->u.syment.n_sclass == C_THUMBSTAT
8135                       || cs->native->u.syment.n_sclass == C_THUMBLABEL
8136                       || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
8137                       || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
8138         }
8139       else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
8140                && !found)
8141         {
8142           /* If no mapping symbol has been found then fall back to the type
8143              of the function symbol.  */
8144           elf_symbol_type *  es;
8145           unsigned int       type;
8146
8147           es = *(elf_symbol_type **)(info->symbols);
8148           type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
8149
8150           is_thumb =
8151             ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
8152               == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
8153         }
8154       else if (bfd_asymbol_flavour (*info->symbols)
8155                == bfd_target_mach_o_flavour)
8156         {
8157           bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
8158
8159           is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
8160         }
8161     }
8162
8163   if (force_thumb)
8164     is_thumb = TRUE;
8165
8166   if (is_data)
8167     info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
8168   else
8169     info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
8170
8171   info->bytes_per_line = 4;
8172
8173   /* PR 10263: Disassemble data if requested to do so by the user.  */
8174   if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
8175     {
8176       int i;
8177
8178       /* Size was already set above.  */
8179       info->bytes_per_chunk = size;
8180       printer = print_insn_data;
8181
8182       status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
8183       given = 0;
8184       if (little)
8185         for (i = size - 1; i >= 0; i--)
8186           given = b[i] | (given << 8);
8187       else
8188         for (i = 0; i < (int) size; i++)
8189           given = b[i] | (given << 8);
8190     }
8191   else if (!is_thumb)
8192     {
8193       /* In ARM mode endianness is a straightforward issue: the instruction
8194          is four bytes long and is either ordered 0123 or 3210.  */
8195       printer = print_insn_arm;
8196       info->bytes_per_chunk = 4;
8197       size = 4;
8198
8199       status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
8200       if (little_code)
8201         given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
8202       else
8203         given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
8204     }
8205   else
8206     {
8207       /* In Thumb mode we have the additional wrinkle of two
8208          instruction lengths.  Fortunately, the bits that determine
8209          the length of the current instruction are always to be found
8210          in the first two bytes.  */
8211       printer = print_insn_thumb16;
8212       info->bytes_per_chunk = 2;
8213       size = 2;
8214
8215       status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
8216       if (little_code)
8217         given = (b[0]) | (b[1] << 8);
8218       else
8219         given = (b[1]) | (b[0] << 8);
8220
8221       if (!status)
8222         {
8223           /* These bit patterns signal a four-byte Thumb
8224              instruction.  */
8225           if ((given & 0xF800) == 0xF800
8226               || (given & 0xF800) == 0xF000
8227               || (given & 0xF800) == 0xE800)
8228             {
8229               status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
8230               if (little_code)
8231                 given = (b[0]) | (b[1] << 8) | (given << 16);
8232               else
8233                 given = (b[1]) | (b[0] << 8) | (given << 16);
8234
8235               printer = print_insn_thumb32;
8236               size = 4;
8237             }
8238         }
8239
8240       if (ifthen_address != pc)
8241         find_ifthen_state (pc, info, little_code);
8242
8243       if (ifthen_state)
8244         {
8245           if ((ifthen_state & 0xf) == 0x8)
8246             ifthen_next_state = 0;
8247           else
8248             ifthen_next_state = (ifthen_state & 0xe0)
8249                                 | ((ifthen_state & 0xf) << 1);
8250         }
8251     }
8252
8253   if (status)
8254     {
8255       info->memory_error_func (status, pc, info);
8256       return -1;
8257     }
8258   if (info->flags & INSN_HAS_RELOC)
8259     /* If the instruction has a reloc associated with it, then
8260        the offset field in the instruction will actually be the
8261        addend for the reloc.  (We are using REL type relocs).
8262        In such cases, we can ignore the pc when computing
8263        addresses, since the addend is not currently pc-relative.  */
8264     pc = 0;
8265
8266   printer (pc, info, given);
8267
8268   if (is_thumb)
8269     {
8270       ifthen_state = ifthen_next_state;
8271       ifthen_address += size;
8272     }
8273   return size;
8274 }
8275
8276 int
8277 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
8278 {
8279   /* Detect BE8-ness and record it in the disassembler info.  */
8280   if (info->flavour == bfd_target_elf_flavour
8281       && info->section != NULL
8282       && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
8283     info->endian_code = BFD_ENDIAN_LITTLE;
8284
8285   return print_insn (pc, info, FALSE);
8286 }
8287
8288 int
8289 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
8290 {
8291   return print_insn (pc, info, TRUE);
8292 }
8293
8294 const disasm_options_and_args_t *
8295 disassembler_options_arm (void)
8296 {
8297   static disasm_options_and_args_t *opts_and_args;
8298
8299   if (opts_and_args == NULL)
8300     {
8301       disasm_options_t *opts;
8302       unsigned int i;
8303
8304       opts_and_args = XNEW (disasm_options_and_args_t);
8305       opts_and_args->args = NULL;
8306
8307       opts = &opts_and_args->options;
8308       opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
8309       opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
8310       opts->arg = NULL;
8311       for (i = 0; i < NUM_ARM_OPTIONS; i++)
8312         {
8313           opts->name[i] = regnames[i].name;
8314           if (regnames[i].description != NULL)
8315             opts->description[i] = _(regnames[i].description);
8316           else
8317             opts->description[i] = NULL;
8318         }
8319       /* The array we return must be NULL terminated.  */
8320       opts->name[i] = NULL;
8321       opts->description[i] = NULL;
8322     }
8323
8324   return opts_and_args;
8325 }
8326
8327 void
8328 print_arm_disassembler_options (FILE *stream)
8329 {
8330   unsigned int i, max_len = 0;
8331   fprintf (stream, _("\n\
8332 The following ARM specific disassembler options are supported for use with\n\
8333 the -M switch:\n"));
8334
8335   for (i = 0; i < NUM_ARM_OPTIONS; i++)
8336     {
8337       unsigned int len = strlen (regnames[i].name);
8338       if (max_len < len)
8339         max_len = len;
8340     }
8341
8342   for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
8343     fprintf (stream, "  %s%*c %s\n",
8344              regnames[i].name,
8345              (int)(max_len - strlen (regnames[i].name)), ' ',
8346              _(regnames[i].description));
8347 }