opcodes/arm-dis.c

   1 /* Instruction printing code for the ARM
   2    Copyright (C) 1994-2017 Free Software Foundation, Inc.
   3    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
   4    Modification by James G. Smith (jsmith@cygnus.co.uk)
   5
   6    This file is part of libopcodes.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include "sysdep.h"
  24
  25 #include "disassemble.h"
  26 #include "opcode/arm.h"
  27 #include "opintl.h"
  28 #include "safe-ctype.h"
  29 #include "libiberty.h"
  30 #include "floatformat.h"
  31
  32 /* FIXME: This shouldn't be done here.  */
  33 #include "coff/internal.h"
  34 #include "libcoff.h"
  35 #include "elf-bfd.h"
  36 #include "elf/internal.h"
  37 #include "elf/arm.h"
  38 #include "mach-o.h"
  39
  40 /* FIXME: Belongs in global header.  */
  41 #ifndef strneq
  42 #define strneq(a,b,n)   (strncmp ((a), (b), (n)) == 0)
  43 #endif
  44
  45 /* Cached mapping symbol state.  */
  46 enum map_type
  47 {
  48   MAP_ARM,
  49   MAP_THUMB,
  50   MAP_DATA
  51 };
  52
  53 struct arm_private_data
  54 {
  55   /* The features to use when disassembling optional instructions.  */
  56   arm_feature_set features;
  57
  58   /* Whether any mapping symbols are present in the provided symbol
  59      table.  -1 if we do not know yet, otherwise 0 or 1.  */
  60   int has_mapping_symbols;
  61
  62   /* Track the last type (although this doesn't seem to be useful) */
  63   enum map_type last_type;
  64
  65   /* Tracking symbol table information */
  66   int last_mapping_sym;
  67   bfd_vma last_mapping_addr;
  68 };
  69
  70 struct opcode32
  71 {
  72   arm_feature_set arch;         /* Architecture defining this insn.  */
  73   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
  74   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
  75   const char *  assembler;      /* How to disassemble this insn.  */
  76 };
  77
  78 struct opcode16
  79 {
  80   arm_feature_set arch;         /* Architecture defining this insn.  */
  81   unsigned short value, mask;   /* Recognise insn if (op & mask) == value.  */
  82   const char *assembler;        /* How to disassemble this insn.  */
  83 };
  84
  85 /* print_insn_coprocessor recognizes the following format control codes:
  86
  87    %%                   %
  88
  89    %c                   print condition code (always bits 28-31 in ARM mode)
  90    %q                   print shifter argument
  91    %u                   print condition code (unconditional in ARM mode,
  92                           UNPREDICTABLE if not AL in Thumb)
  93    %A                   print address for ldc/stc/ldf/stf instruction
  94    %B                   print vstm/vldm register list
  95    %I                   print cirrus signed shift immediate: bits 0..3|4..6
  96    %F                   print the COUNT field of a LFM/SFM instruction.
  97    %P                   print floating point precision in arithmetic insn
  98    %Q                   print floating point precision in ldf/stf insn
  99    %R                   print floating point rounding mode
 100
 101    %<bitfield>c         print as a condition code (for vsel)
 102    %<bitfield>r         print as an ARM register
 103    %<bitfield>R         as %<>r but r15 is UNPREDICTABLE
 104    %<bitfield>ru        as %<>r but each u register must be unique.
 105    %<bitfield>d         print the bitfield in decimal
 106    %<bitfield>k         print immediate for VFPv3 conversion instruction
 107    %<bitfield>x         print the bitfield in hex
 108    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
 109    %<bitfield>f         print a floating point constant if >7 else a
 110                         floating point register
 111    %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
 112    %<bitfield>g         print as an iWMMXt 64-bit register
 113    %<bitfield>G         print as an iWMMXt general purpose or control register
 114    %<bitfield>D         print as a NEON D register
 115    %<bitfield>Q         print as a NEON Q register
 116    %<bitfield>V         print as a NEON D or Q register
 117    %<bitfield>E         print a quarter-float immediate value
 118
 119    %y<code>             print a single precision VFP reg.
 120                           Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
 121    %z<code>             print a double precision VFP reg
 122                           Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
 123
 124    %<bitfield>'c        print specified char iff bitfield is all ones
 125    %<bitfield>`c        print specified char iff bitfield is all zeroes
 126    %<bitfield>?ab...    select from array of values in big endian order
 127
 128    %L                   print as an iWMMXt N/M width field.
 129    %Z                   print the Immediate of a WSHUFH instruction.
 130    %l                   like 'A' except use byte offsets for 'B' & 'H'
 131                         versions.
 132    %i                   print 5-bit immediate in bits 8,3..0
 133                         (print "32" when 0)
 134    %r                   print register offset address for wldt/wstr instruction.  */
 135
 136 enum opcode_sentinel_enum
 137 {
 138   SENTINEL_IWMMXT_START = 1,
 139   SENTINEL_IWMMXT_END,
 140   SENTINEL_GENERIC_START
 141 } opcode_sentinels;
 142
 143 #define UNDEFINED_INSTRUCTION      "\t\t; <UNDEFINED> instruction: %0-31x"
 144 #define UNPREDICTABLE_INSTRUCTION  "\t; <UNPREDICTABLE>"
 145
 146 /* Common coprocessor opcodes shared between Arm and Thumb-2.  */
 147
 148 static const struct opcode32 coprocessor_opcodes[] =
 149 {
 150   /* XScale instructions.  */
 151   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 152     0x0e200010, 0x0fff0ff0,
 153     "mia%c\tacc0, %0-3r, %12-15r"},
 154   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 155     0x0e280010, 0x0fff0ff0,
 156     "miaph%c\tacc0, %0-3r, %12-15r"},
 157   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 158     0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
 159   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 160     0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
 161   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 162     0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
 163
 164   /* Intel Wireless MMX technology instructions.  */
 165   {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
 166   {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
 167     0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
 168   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 169     0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
 170   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 171     0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
 172   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 173     0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
 174   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 175     0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
 176   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 177     0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
 178   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 179     0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
 180   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 181     0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
 182   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 183     0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
 184   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 185     0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
 186   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 187     0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
 188   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 189     0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
 190   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 191     0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
 192   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 193     0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
 194   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 195     0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
 196   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 197     0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
 198   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 199     0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
 200   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 201     0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 202   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 203     0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
 204   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 205     0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
 206   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 207     0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
 208   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 209     0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
 210   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 211     0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
 212   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 213     0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
 214   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 215     0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
 216   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 217     0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 218   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 219     0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 220   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 221     0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
 222   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 223     0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
 224   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 225     0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
 226   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 227     0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
 228   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 229     0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
 230   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 231     0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
 232   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 233     0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 234   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 235     0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
 236   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 237     0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 238   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 239     0x0e800120, 0x0f800ff0,
 240     "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 241   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 242     0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 243   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 244     0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
 245   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 246     0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
 247   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 248     0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
 249   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 250     0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
 251   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 252     0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
 253   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 254     0x0e8000a0, 0x0f800ff0,
 255     "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 256   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 257     0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 258   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 259     0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 260   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 261     0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
 262   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 263     0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 264   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 265     0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
 266   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 267     0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 268   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 269     0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
 270   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 271     0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
 272   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 273     0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
 274   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 275     0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
 276   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 277     0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 278   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 279     0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 280   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 281     0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
 282   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 283     0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 284   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 285     0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 286   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 287     0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
 288   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 289     0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 290   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 291     0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 292   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 293     0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
 294   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 295     0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
 296   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 297     0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
 298   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 299     0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 300   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 301     0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
 302   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 303     0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 304   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 305     0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
 306   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 307     0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
 308   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 309     0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
 310   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 311     0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
 312   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 313     0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 314   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 315     0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 316   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 317     0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
 318   {ARM_FEATURE_CORE_LOW (0),
 319     SENTINEL_IWMMXT_END, 0, "" },
 320
 321   /* Floating point coprocessor (FPA) instructions.  */
 322   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 323     0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 324   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 325     0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 326   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 327     0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 328   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 329     0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 330   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 331     0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 332   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 333     0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 334   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 335     0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
 336   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 337     0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
 338   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 339     0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 340   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 341     0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
 342   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 343     0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
 344   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 345     0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
 346   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 347     0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
 348   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 349     0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
 350   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 351     0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
 352   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 353     0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
 354   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 355     0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
 356   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 357     0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
 358   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 359     0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
 360   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 361     0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
 362   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 363     0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
 364   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 365     0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
 366   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 367     0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
 368   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 369     0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
 370   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 371     0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
 372   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 373     0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
 374   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 375     0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
 376   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 377     0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
 378   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 379     0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
 380   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 381     0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
 382   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 383     0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
 384   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 385     0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
 386   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 387     0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
 388   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 389     0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
 390   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 391     0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
 392   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 393     0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
 394   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 395     0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
 396   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 397     0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
 398   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 399     0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
 400   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 401     0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
 402   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 403     0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
 404   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 405     0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
 406   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 407     0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
 408
 409   /* ARMv8-M Mainline Security Extensions instructions.  */
 410   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 411     0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
 412   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 413     0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
 414
 415   /* Register load/store.  */
 416   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 417     0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
 418   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 419     0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
 420   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 421     0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
 422   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 423     0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
 424   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 425     0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
 426   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 427     0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
 428   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 429     0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
 430   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 431     0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
 432   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 433     0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
 434   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 435     0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
 436   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 437     0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
 438   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 439     0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
 440   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 441     0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
 442   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 443     0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
 444   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 445     0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
 446   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 447     0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
 448
 449   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 450     0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 451   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 452     0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 453   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 454     0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 455   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 456     0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 457
 458   /* Data transfer between ARM and NEON registers.  */
 459   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 460     0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
 461   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 462     0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
 463   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 464     0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
 465   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 466     0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
 467   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 468     0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
 469   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 470     0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
 471   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 472     0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
 473   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 474     0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
 475   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 476     0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
 477   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 478     0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
 479   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 480     0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
 481   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 482     0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
 483   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 484     0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
 485   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 486     0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
 487   /* Half-precision conversion instructions.  */
 488   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 489     0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
 490   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 491     0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
 492   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 493     0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
 494   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 495     0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
 496
 497   /* Floating point coprocessor (VFP) instructions.  */
 498   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 499     0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
 500   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 501     0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
 502   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 503     0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
 504   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 505     0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
 506   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 507     0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
 508   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 509     0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
 510   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 511     0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
 512   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 513     0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
 514   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 515     0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
 516   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 517     0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
 518   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 519     0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
 520   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 521     0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
 522   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 523     0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
 524   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 525     0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
 526   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 527     0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
 528   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 529     0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
 530   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 531     0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
 532   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 533     0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
 534   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 535     0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
 536   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 537     0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
 538   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 539     0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
 540   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 541     0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
 542   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 543     0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
 544   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 545     0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
 546   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 547     0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
 548   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 549     0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
 550   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 551     0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
 552   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 553     0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
 554   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 555     0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
 556   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 557     0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
 558   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 559     0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
 560   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 561     0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
 562   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 563     0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
 564   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 565     0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
 566   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 567     0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
 568   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 569     0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
 570   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 571     0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
 572   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 573     0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
 574   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 575     0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
 576   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 577     0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
 578   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 579     0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
 580   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 581     0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
 582   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 583     0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
 584   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 585     0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
 586   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 587     0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
 588   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 589     0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
 590   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 591     0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
 592   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 593     0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
 594   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 595     0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
 596   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 597     0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
 598   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 599     0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
 600   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 601     0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
 602   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 603     0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
 604   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 605     0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
 606   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 607     0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
 608   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 609     0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
 610   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 611     0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
 612   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 613     0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
 614   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 615     0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
 616   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 617     0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
 618   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 619     0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
 620   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 621     0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
 622   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 623     0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
 624   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 625     0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
 626   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 627     0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
 628   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 629     0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
 630   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 631     0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
 632   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 633     0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
 634   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 635     0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
 636
 637   /* Cirrus coprocessor instructions.  */
 638   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 639     0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 640   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 641     0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 642   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 643     0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 644   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 645     0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 646   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 647     0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 648   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 649     0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 650   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 651     0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 652   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 653     0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 654   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 655     0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 656   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 657     0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 658   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 659     0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 660   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 661     0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 662   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 663     0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 664   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 665     0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 666   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 667     0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 668   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 669     0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 670   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 671     0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
 672   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 673     0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
 674   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 675     0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
 676   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 677     0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
 678   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 679     0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
 680   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 681     0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
 682   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 683     0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
 684   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 685     0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
 686   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 687     0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
 688   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 689     0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
 690   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 691     0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
 692   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 693     0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
 694   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 695     0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
 696   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 697     0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
 698   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 699     0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
 700   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 701     0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
 702   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 703     0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
 704   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 705     0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
 706   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 707     0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
 708   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 709     0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
 710   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 711     0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
 712   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 713     0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
 714   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 715     0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
 716   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 717     0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
 718   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 719     0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
 720   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 721     0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
 722   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 723     0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
 724   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 725     0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
 726   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 727     0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
 728   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 729     0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
 730   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 731     0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
 732   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 733     0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
 734   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 735     0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
 736   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 737     0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
 738   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 739     0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
 740   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 741     0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
 742   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 743     0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
 744   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 745     0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
 746   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 747     0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
 748   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 749     0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
 750   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 751     0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
 752   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 753     0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
 754   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 755     0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
 756   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 757     0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
 758   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 759     0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
 760   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 761     0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
 762   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 763     0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 764   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 765     0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 766   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 767     0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 768   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 769     0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 770   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 771     0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 772   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 773     0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 774   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 775     0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
 776   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 777     0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
 778   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 779     0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
 780   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 781     0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
 782   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 783     0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 784   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 785     0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 786   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 787     0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 788   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 789     0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 790   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 791     0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 792   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 793     0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 794   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 795     0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 796   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 797     0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 798   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 799     0x0e000600, 0x0ff00f10,
 800     "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 801   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 802     0x0e100600, 0x0ff00f10,
 803     "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 804   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 805     0x0e200600, 0x0ff00f10,
 806     "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 807   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 808     0x0e300600, 0x0ff00f10,
 809     "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 810
 811   /* VFP Fused multiply add instructions.  */
 812   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 813     0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
 814   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 815     0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
 816   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 817     0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
 818   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 819     0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
 820   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 821     0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
 822   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 823     0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
 824   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 825     0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
 826   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 827     0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
 828
 829   /* FP v5.  */
 830   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 831     0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
 832   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 833     0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
 834   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 835     0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
 836   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 837     0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
 838   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 839     0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
 840   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 841     0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
 842   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 843     0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
 844   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 845     0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
 846   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 847     0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
 848   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 849     0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
 850   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 851     0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
 852   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 853     0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
 854
 855   /* Generic coprocessor instructions.  */
 856   {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
 857   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
 858     0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
 859   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
 860     0x0c500000, 0x0ff00000,
 861     "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 862   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 863     0x0e000000, 0x0f000010,
 864     "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 865   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 866     0x0e10f010, 0x0f10f010,
 867     "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
 868   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 869     0x0e100010, 0x0f100010,
 870     "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 871   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 872     0x0e000010, 0x0f100010,
 873     "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 874   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 875     0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
 876   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 877     0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
 878
 879   /* V6 coprocessor instructions.  */
 880   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
 881     0xfc500000, 0xfff00000,
 882     "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 883   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
 884     0xfc400000, 0xfff00000,
 885     "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
 886
 887   /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8.  */
 888   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 889     0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
 890   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 891     0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
 892   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 893     0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
 894   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 895     0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
 896   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 897     0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
 898   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 899     0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
 900   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 901     0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
 902   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 903     0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
 904   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 905     0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
 906   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 907     0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
 908
 909   /* Dot Product instructions in the space of coprocessor 13.  */
 910   {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
 911     0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
 912   {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
 913     0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
 914
 915   /* V5 coprocessor instructions.  */
 916   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 917     0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
 918   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 919     0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
 920   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 921     0xfe000000, 0xff000010,
 922     "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 923   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 924     0xfe000010, 0xff100010,
 925     "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 926   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 927     0xfe100010, 0xff100010,
 928     "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 929
 930   /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
 931      cp_num: bit <11:8> == 0b1001.
 932      cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE.  */
 933   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 934     0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
 935   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 936     0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
 937   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 938     0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
 939   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 940     0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
 941   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 942     0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
 943   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 944     0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
 945   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 946     0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
 947   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 948     0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
 949   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 950     0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
 951   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 952     0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
 953   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 954     0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
 955   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 956     0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
 957   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 958     0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
 959   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 960     0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
 961   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 962     0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
 963   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 964     0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
 965   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 966     0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
 967   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 968     0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
 969   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 970     0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
 971   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 972     0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
 973   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 974     0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
 975   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 976     0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
 977   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 978     0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
 979   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 980     0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
 981   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 982     0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
 983   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 984     0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
 985   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 986     0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
 987   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 988     0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
 989   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 990     0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
 991   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 992     0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
 993   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 994     0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
 995   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 996     0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
 997   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 998     0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
 999   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1000     0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1001   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1002     0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1003
1004   /* ARMv8.3 javascript conversion instruction.  */
1005   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1006     0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1007
1008   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1009 };
1010
1011 /* Neon opcode table:  This does not encode the top byte -- that is
1012    checked by the print_insn_neon routine, as it depends on whether we are
1013    doing thumb32 or arm32 disassembly.  */
1014
1015 /* print_insn_neon recognizes the following format control codes:
1016
1017    %%                   %
1018
1019    %c                   print condition code
1020    %u                   print condition code (unconditional in ARM mode,
1021                           UNPREDICTABLE if not AL in Thumb)
1022    %A                   print v{st,ld}[1234] operands
1023    %B                   print v{st,ld}[1234] any one operands
1024    %C                   print v{st,ld}[1234] single->all operands
1025    %D                   print scalar
1026    %E                   print vmov, vmvn, vorr, vbic encoded constant
1027    %F                   print vtbl,vtbx register list
1028
1029    %<bitfield>r         print as an ARM register
1030    %<bitfield>d         print the bitfield in decimal
1031    %<bitfield>e         print the 2^N - bitfield in decimal
1032    %<bitfield>D         print as a NEON D register
1033    %<bitfield>Q         print as a NEON Q register
1034    %<bitfield>R         print as a NEON D or Q register
1035    %<bitfield>Sn        print byte scaled width limited by n
1036    %<bitfield>Tn        print short scaled width limited by n
1037    %<bitfield>Un        print long scaled width limited by n
1038
1039    %<bitfield>'c        print specified char iff bitfield is all ones
1040    %<bitfield>`c        print specified char iff bitfield is all zeroes
1041    %<bitfield>?ab...    select from array of values in big endian order.  */
1042
1043 static const struct opcode32 neon_opcodes[] =
1044 {
1045   /* Extract.  */
1046   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1047     0xf2b00840, 0xffb00850,
1048     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1049   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1050     0xf2b00000, 0xffb00810,
1051     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1052
1053   /* Move data element to all lanes.  */
1054   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1055     0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1056   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1057     0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1058   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1059     0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1060
1061   /* Table lookup.  */
1062   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1063     0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1064   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1065     0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1066
1067   /* Half-precision conversions.  */
1068   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1069     0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1070   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1071     0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1072
1073   /* NEON fused multiply add instructions.  */
1074   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1075     0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1076   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1077     0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1078   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1079     0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1080   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1081     0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1082
1083   /* Two registers, miscellaneous.  */
1084   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1085     0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1086   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1087     0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1088   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1089     0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1090   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1091     0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1092   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1093     0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1094   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1095     0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1096   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1097     0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1098   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1099     0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1100   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1101     0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1102   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1103     0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1104   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1105     0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1106   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1107     0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1108   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1109     0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1110   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1111     0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1112   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1113     0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1114   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1115     0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1116   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1117     0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1118   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1119     0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1120   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1121     0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1122   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1123     0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1124   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1125     0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1126   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1127     0xf3b20300, 0xffb30fd0,
1128     "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1129   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1130     0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1131   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1132     0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1133   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1134     0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1135   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1136     0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1137   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1138     0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1139   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1140     0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1141   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1142     0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1143   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1144     0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1145   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1146     0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1147   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1148     0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1149   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1150     0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1151   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1152     0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1153   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1154     0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1155   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1156     0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1157   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1158     0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1159   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1160     0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1161   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1162     0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1163   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1164     0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1165   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1166     0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1167   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1168     0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1169   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1170     0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1171   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1172     0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1173   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1174     0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1175   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1176     0xf3bb0600, 0xffbf0e10,
1177     "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1178   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1179     0xf3b70600, 0xffbf0e10,
1180     "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1181
1182   /* Three registers of the same length.  */
1183   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1184     0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1185   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1186     0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1187   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1188     0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1189   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1190     0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1191   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1192     0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1193   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1194     0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1195   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1196     0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1197   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1198     0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1199   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1200     0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1201   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1202     0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1203   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1204     0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1205   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1206     0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1207   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1208     0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1209   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1210     0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1211   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1212     0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1213   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1214     0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1215   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1216     0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1217   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1218     0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1219   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1220     0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1221   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1222     0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1223   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1224     0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1225   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1226     0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1227   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1228     0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1229   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1230     0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1231   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1232     0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1233   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1234     0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1235   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1236     0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1237   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1238     0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1239   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1240     0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1241   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1242     0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1243   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1244     0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1245   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1246     0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1247   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1248     0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1249   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1250     0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1251   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1252     0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1253   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1254     0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1255   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1256     0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1257   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1258     0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1259   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1260     0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1261   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1262     0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1263   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1264     0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1265   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1266     0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1267   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1268     0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1269   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1270     0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1271   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1272     0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1273   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1274     0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1275   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1276     0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1277   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1278     0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1279   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1280     0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1281   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1282     0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1283   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1284     0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1285   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1286     0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1287   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1288     0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1289   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1290     0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1291   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1292     0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1293   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1294     0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1295   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1296     0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1297   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1298     0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1299   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1300     0xf2000b00, 0xff800f10,
1301     "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1302   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1303     0xf2000b10, 0xff800f10,
1304     "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1305   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1306     0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1307   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1308     0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1309   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1310     0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1311   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1312     0xf3000b00, 0xff800f10,
1313     "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1314   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1315     0xf2000000, 0xfe800f10,
1316     "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1317   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1318     0xf2000010, 0xfe800f10,
1319     "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1320   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1321     0xf2000100, 0xfe800f10,
1322     "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1323   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1324     0xf2000200, 0xfe800f10,
1325     "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1326   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1327     0xf2000210, 0xfe800f10,
1328     "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1329   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1330     0xf2000300, 0xfe800f10,
1331     "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1332   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1333     0xf2000310, 0xfe800f10,
1334     "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1335   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1336     0xf2000400, 0xfe800f10,
1337     "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1338   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1339     0xf2000410, 0xfe800f10,
1340     "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1341   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1342     0xf2000500, 0xfe800f10,
1343     "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1344   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1345     0xf2000510, 0xfe800f10,
1346     "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1347   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1348     0xf2000600, 0xfe800f10,
1349     "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1350   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1351     0xf2000610, 0xfe800f10,
1352     "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1353   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1354     0xf2000700, 0xfe800f10,
1355     "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1356   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1357     0xf2000710, 0xfe800f10,
1358     "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1359   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1360     0xf2000910, 0xfe800f10,
1361     "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1362   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1363     0xf2000a00, 0xfe800f10,
1364     "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1365   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1366     0xf2000a10, 0xfe800f10,
1367     "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1368   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1369     0xf3000b10, 0xff800f10,
1370     "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1371   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1372     0xf3000c10, 0xff800f10,
1373     "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1374
1375   /* One register and an immediate value.  */
1376   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1377     0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1378   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1379     0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1380   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1381     0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1382   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1383     0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1384   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1385     0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1386   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1387     0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1388   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1389     0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1390   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1391     0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1392   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1393     0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1394   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1395     0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1396   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1397     0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1398   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1399     0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1400   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401     0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1402
1403   /* Two registers and a shift amount.  */
1404   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1405     0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1406   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407     0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1408   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1409     0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1410   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411     0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1412   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413     0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1414   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415     0xf2880950, 0xfeb80fd0,
1416     "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1417   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1418     0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1419   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1420     0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1421   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1422     0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1423   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424     0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1425   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1426     0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1427   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1428     0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1429   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1430     0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1431   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1432     0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1433   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1434     0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1435   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436     0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1437   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1438     0xf2900950, 0xfeb00fd0,
1439     "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1440   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1441     0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1442   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1443     0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1444   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1445     0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1446   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1447     0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1448   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1449     0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1450   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1451     0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1452   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1453     0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1454   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1455     0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1456   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1457     0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1458   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1459     0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1460   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1461     0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1462   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1463     0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1464   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1465     0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1466   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1467     0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1468   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1469     0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1470   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471     0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1472   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473     0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1474   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475     0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1476   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477     0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1478   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479     0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1480   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481     0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1482   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1483     0xf2a00950, 0xfea00fd0,
1484     "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1485   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1486     0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1487   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1488     0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1489   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1490     0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1491   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492     0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1493   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494     0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1495   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1496     0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1497   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498     0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1499   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1500     0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1501   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1502     0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1503   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504     0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1505   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506     0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1507   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508     0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1509   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510     0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1511   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512     0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1513   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514     0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1515   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516     0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1517   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518     0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1519   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520     0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1521   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1522     0xf2a00e10, 0xfea00e90,
1523     "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1524   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1525     0xf2a00c10, 0xfea00e90,
1526     "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1527
1528   /* Three registers of different lengths.  */
1529   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1530     0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1531   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1532     0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1533   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1534     0xf2800400, 0xff800f50,
1535     "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1536   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1537     0xf2800600, 0xff800f50,
1538     "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1539   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1540     0xf2800900, 0xff800f50,
1541     "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1542   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1543     0xf2800b00, 0xff800f50,
1544     "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1545   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1546     0xf2800d00, 0xff800f50,
1547     "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1548   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1549     0xf3800400, 0xff800f50,
1550     "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1551   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552     0xf3800600, 0xff800f50,
1553     "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1554   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1555     0xf2800000, 0xfe800f50,
1556     "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1557   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1558     0xf2800100, 0xfe800f50,
1559     "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1560   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1561     0xf2800200, 0xfe800f50,
1562     "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1563   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1564     0xf2800300, 0xfe800f50,
1565     "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1566   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1567     0xf2800500, 0xfe800f50,
1568     "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1569   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1570     0xf2800700, 0xfe800f50,
1571     "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1572   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1573     0xf2800800, 0xfe800f50,
1574     "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1575   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1576     0xf2800a00, 0xfe800f50,
1577     "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1578   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1579     0xf2800c00, 0xfe800f50,
1580     "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1581
1582   /* Two registers and a scalar.  */
1583   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584     0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1585   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1586     0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1587   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1588     0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1589   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590     0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1591   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1592     0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1593   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1594     0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1595   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1596     0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1597   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1598     0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1599   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1600     0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1601   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1602     0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1603   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1604     0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1605   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606     0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1607   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1608     0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1609   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1610     0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1611   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1612     0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1613   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1614     0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1615   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1616     0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1617   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618     0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1619   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1620     0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1621   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1622     0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1623   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1624     0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1625   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626     0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1627   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1628     0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1629   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630     0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1631   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1632     0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1633   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1634     0xf2800240, 0xfe800f50,
1635     "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1636   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1637     0xf2800640, 0xfe800f50,
1638     "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1639   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1640     0xf2800a40, 0xfe800f50,
1641     "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1642   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1643     0xf2800e40, 0xff800f50,
1644    "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1645   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1646     0xf2800f40, 0xff800f50,
1647    "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1648   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1649     0xf3800e40, 0xff800f50,
1650    "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1651   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1652     0xf3800f40, 0xff800f50,
1653    "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1654   },
1655
1656   /* Element and structure load/store.  */
1657   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1658     0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1659   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1660     0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1661   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1662     0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1663   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1664     0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1665   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1666     0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1667   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1668     0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1669   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1670     0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1671   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1672     0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1673   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1674     0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1675   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1676     0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1677   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1678     0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1679   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1680     0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1681   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1682     0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1683   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1684     0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1685   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1686     0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1687   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1688     0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1689   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1690     0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1691   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1692     0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1693   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1694     0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1695
1696   {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1697 };
1698
1699 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb.  All three are partially
1700    ordered: they must be searched linearly from the top to obtain a correct
1701    match.  */
1702
1703 /* print_insn_arm recognizes the following format control codes:
1704
1705    %%                   %
1706
1707    %a                   print address for ldr/str instruction
1708    %s                   print address for ldr/str halfword/signextend instruction
1709    %S                   like %s but allow UNPREDICTABLE addressing
1710    %b                   print branch destination
1711    %c                   print condition code (always bits 28-31)
1712    %m                   print register mask for ldm/stm instruction
1713    %o                   print operand2 (immediate or register + shift)
1714    %p                   print 'p' iff bits 12-15 are 15
1715    %t                   print 't' iff bit 21 set and bit 24 clear
1716    %B                   print arm BLX(1) destination
1717    %C                   print the PSR sub type.
1718    %U                   print barrier type.
1719    %P                   print address for pli instruction.
1720
1721    %<bitfield>r         print as an ARM register
1722    %<bitfield>T         print as an ARM register + 1
1723    %<bitfield>R         as %r but r15 is UNPREDICTABLE
1724    %<bitfield>{r|R}u    as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1725    %<bitfield>{r|R}U    as %{r|R} but if matches the other %U field then is UNPREDICTABLE
1726    %<bitfield>d         print the bitfield in decimal
1727    %<bitfield>W         print the bitfield plus one in decimal
1728    %<bitfield>x         print the bitfield in hex
1729    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
1730
1731    %<bitfield>'c        print specified char iff bitfield is all ones
1732    %<bitfield>`c        print specified char iff bitfield is all zeroes
1733    %<bitfield>?ab...    select from array of values in big endian order
1734
1735    %e                   print arm SMI operand (bits 0..7,8..19).
1736    %E                   print the LSB and WIDTH fields of a BFI or BFC instruction.
1737    %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.
1738    %R                   print the SPSR/CPSR or banked register of an MRS.  */
1739
1740 static const struct opcode32 arm_opcodes[] =
1741 {
1742   /* ARM instructions.  */
1743   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1744     0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1745   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1746     0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1747
1748   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1749     0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1750   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1751     0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1752   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1753     0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1754   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1755     0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1756   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1757     0x00800090, 0x0fa000f0,
1758     "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1759   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1760     0x00a00090, 0x0fa000f0,
1761     "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1762
1763   /* V8.2 RAS extension instructions.  */
1764   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
1765     0xe320f010, 0xffffffff, "esb"},
1766
1767   /* V8 instructions.  */
1768   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1769     0x0320f005, 0x0fffffff, "sevl"},
1770   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1771     0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
1772   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
1773     0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
1774   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1775     0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1776   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1777     0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1778   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1779     0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
1780   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1781     0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
1782   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1783     0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
1784   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1785     0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
1786   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1787     0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
1788   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1789     0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
1790   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1791     0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
1792   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1793     0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
1794   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1795     0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
1796   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1797     0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
1798   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1799     0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
1800   /* CRC32 instructions.  */
1801   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1802     0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1803   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1804     0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1805   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1806     0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1807   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1808     0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1809   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1810     0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1811   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1812     0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
1813
1814   /* Privileged Access Never extension instructions.  */
1815   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1816     0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1817
1818   /* Virtualization Extension instructions.  */
1819   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1820   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
1821
1822   /* Integer Divide Extension instructions.  */
1823   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1824     0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1825   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1826     0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
1827
1828   /* MP Extension instructions.  */
1829   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
1830
1831   /* V7 instructions.  */
1832   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1833   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1834   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1835   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1836   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1837   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1838   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
1839    {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1840     0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
1841
1842   /* ARM V6T2 instructions.  */
1843   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1844     0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1845   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1846     0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1847   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1848     0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1849   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1850     0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1851
1852   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1853     0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1854   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1855     0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1856
1857   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
1858     0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
1859   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
1860     0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1861   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1862     0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1863   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1864     0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
1865
1866   /* ARM Security extension instructions.  */
1867   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1868     0x01600070, 0x0ff000f0, "smc%c\t%e"},
1869
1870   /* ARM V6K instructions.  */
1871   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1872     0xf57ff01f, 0xffffffff, "clrex"},
1873   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1874     0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1875   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1876     0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1877   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1878     0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1879   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1880     0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1881   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1882     0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1883   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1884     0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
1885
1886   /* ARM V6K NOP hints.  */
1887   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1888     0x0320f001, 0x0fffffff, "yield%c"},
1889   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1890     0x0320f002, 0x0fffffff, "wfe%c"},
1891   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1892     0x0320f003, 0x0fffffff, "wfi%c"},
1893   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1894     0x0320f004, 0x0fffffff, "sev%c"},
1895   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1896     0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
1897
1898   /* ARM V6 instructions.  */
1899   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1900     0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1901   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1902     0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1903   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1904     0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1905   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1906     0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1907   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1908     0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1909   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1910     0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1911   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1912     0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1913   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1914     0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1915   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1916     0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1917   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1918     0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1919   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1920     0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1921   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1922     0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1923   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1924     0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1925   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1926     0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1927   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1928     0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1929   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1930     0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1931   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1932     0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1933   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1934     0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1935   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1936     0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1937   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1938     0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1939   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1940     0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1941   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1942     0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1943   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1944     0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1945   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1946     0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1947   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1948     0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1949   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1950     0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1951   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1952     0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1953   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1954     0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1955   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1956     0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1957   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1958     0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1959   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1960     0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1961   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1962     0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1963   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1964     0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1965   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1966     0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1967   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1968     0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1969   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1970     0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
1971   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1972     0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
1973   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1974     0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
1975   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1976     0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
1977   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1978     0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
1979   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1980     0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
1981   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1982     0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
1983   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1984     0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
1985   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1986     0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
1987   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1988     0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
1989   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1990     0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
1991   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1992     0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
1993   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1994     0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
1995   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1996     0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
1997   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1998     0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
1999   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2000     0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2001   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2002     0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2003   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2004     0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2005   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2006     0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2007   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2008     0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2009   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2010     0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2011   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2012     0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2013   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2014     0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2015   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2016     0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2017   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2018     0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2019   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2020     0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2021   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2022     0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2023   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2024     0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2025   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2026     0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2027   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2028     0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2029   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2030     0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2031   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2032     0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2033   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2034     0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2035   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2036     0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2037   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2038     0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2039   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2040     0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2041   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2042     0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2043   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2044     0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2045   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2046     0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2047   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2048     0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2049   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2050     0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2051   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2052     0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2053   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2054     0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2055   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2056     0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2057   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2058     0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2059   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2060     0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2061   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2062     0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2063   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2064     0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2065   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2066     0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2067   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2068     0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2069   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2070     0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2071   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2072     0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2073   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2074     0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2075   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2076     0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2077   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2078     0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2079   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2080     0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2081   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2082     0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2083   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2084     0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2085   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2086     0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2087   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2088     0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2089   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2090     0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2091   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2092     0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2093   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2094     0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2095   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2096     0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2097   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2098     0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2099   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2100     0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2101   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2102     0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2103   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2104     0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2105   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2106     0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2107   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2108     0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2109   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2110     0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2111   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2112     0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2113   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2114     0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2115   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2116     0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2117   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2118     0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2119   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2120     0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2121   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2122     0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2123   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2124     0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2125   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2126     0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2127   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2128     0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2129   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2130     0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2131   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2132     0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2133   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2134     0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2135   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2136     0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2137   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2138     0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2139   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2140     0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2141   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2142     0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
2143
2144   /* V5J instruction.  */
2145   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2146     0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
2147
2148   /* V5 Instructions.  */
2149   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2150     0xe1200070, 0xfff000f0,
2151     "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2152   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2153     0xfa000000, 0xfe000000, "blx\t%B"},
2154   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2155     0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2156   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2157     0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2158
2159   /* V5E "El Segundo" Instructions.  */
2160   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2161     0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2162   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2163     0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2164   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2165     0xf450f000, 0xfc70f000, "pld\t%a"},
2166   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2167     0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2168   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2169     0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2170   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2171     0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2172   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2173     0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2174
2175   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2176     0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2177   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2178     0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2179
2180   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2181     0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2182   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2183     0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2184   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2185     0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2186   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2187     0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2188
2189   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2190     0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2191   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2192     0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2193   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2194     0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2195   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2196     0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2197
2198   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2199     0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2200   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2201     0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2202
2203   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2204     0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15R, %0-3R, %16-19R"},
2205   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2206     0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2207   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2208     0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15R, %0-3R, %16-19R"},
2209   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2210     0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
2211
2212   /* ARM Instructions.  */
2213   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2214     0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2215
2216   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2217     0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2218   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2219     0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2220   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2221     0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2222   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2223     0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2224   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2225     0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2226   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2227     0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2228
2229   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2230     0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2231   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2232     0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2233   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2234     0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2235   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2236     0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2237
2238   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2239     0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2240   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2241     0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2242   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2243     0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2244   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2245     0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2246
2247   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2248     0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2249   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2250     0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2251   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2252     0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2253
2254   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2255     0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2256   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2257     0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2258   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2259     0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2260
2261   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2262     0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2263   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2264     0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2265   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2266     0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2267
2268   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2269     0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2270   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2271     0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2272   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2273     0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2274
2275   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2276     0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2277   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2278     0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2279   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2280     0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2281
2282   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2283     0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2284   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2285     0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2286   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2287     0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2288
2289   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2290     0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2291   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2292     0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2293   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2294     0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2295
2296   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2297     0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2298   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2299     0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2300   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2301     0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2302
2303   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2304     0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2305   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2306     0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2307   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2308     0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2309
2310   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2311     0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2312   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2313     0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2314   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2315     0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2316
2317   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2318     0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
2319   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2320     0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
2321   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2322     0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
2323
2324   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2325     0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2326   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2327     0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2328   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2329     0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2330
2331   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2332     0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2333   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2334     0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2335   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2336     0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2337
2338   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2339     0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2340   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2341     0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2342   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2343     0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2344
2345   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2346     0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2347   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2348     0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2349   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2350     0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2351   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2352     0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2353   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2354     0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2355   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2356     0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2357   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2358     0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2359
2360   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2361     0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2362   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2363     0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2364   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2365     0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2366
2367   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2368     0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2369   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2370     0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2371   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2372     0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2373
2374   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2375     0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2376   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2377     0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2378
2379   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2380     0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2381
2382   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2383     0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2384   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2385     0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2386
2387   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2388     0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2389   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2390     0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2391   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2392     0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2393   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2394     0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2395   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2396     0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2397   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2398     0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2399   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2400     0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2401   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2402     0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2403   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2404     0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2405   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2406     0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2407   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2408     0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2409   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2410     0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2411   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2412     0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2413   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2414     0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2415   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2416     0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2417   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2418     0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2419   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2420     0x092d0000, 0x0fff0000, "push%c\t%m"},
2421   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2422     0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2423   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2424     0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2425
2426   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2427     0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2428   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2429     0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2430   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2431     0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2432   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2433     0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2434   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2435     0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2436   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2437     0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2438   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2439     0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2440   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2441     0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2442   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2443     0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2444   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2445     0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2446   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2447     0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2448   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2449     0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2450   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2451     0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2452   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2453     0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2454   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2455     0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2456   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2457     0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2458   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2459     0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2460   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2461     0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2462   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2463     0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2464
2465   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2466     0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2467   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2468     0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
2469
2470   /* The rest.  */
2471   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2472     0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
2473   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2474     0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2475   {ARM_FEATURE_CORE_LOW (0),
2476     0x00000000, 0x00000000, 0}
2477 };
2478
2479 /* print_insn_thumb16 recognizes the following format control codes:
2480
2481    %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
2482    %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
2483    %<bitfield>I         print bitfield as a signed decimal
2484                                 (top bit of range being the sign bit)
2485    %N                   print Thumb register mask (with LR)
2486    %O                   print Thumb register mask (with PC)
2487    %M                   print Thumb register mask
2488    %b                   print CZB's 6-bit unsigned branch destination
2489    %s                   print Thumb right-shift immediate (6..10; 0 == 32).
2490    %c                   print the condition code
2491    %C                   print the condition code, or "s" if not conditional
2492    %x                   print warning if conditional an not at end of IT block"
2493    %X                   print "\t; unpredictable <IT:code>" if conditional
2494    %I                   print IT instruction suffix and operands
2495    %W                   print Thumb Writeback indicator for LDMIA
2496    %<bitfield>r         print bitfield as an ARM register
2497    %<bitfield>d         print bitfield as a decimal
2498    %<bitfield>H         print (bitfield * 2) as a decimal
2499    %<bitfield>W         print (bitfield * 4) as a decimal
2500    %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
2501    %<bitfield>B         print Thumb branch destination (signed displacement)
2502    %<bitfield>c         print bitfield as a condition code
2503    %<bitnum>'c          print specified char iff bit is one
2504    %<bitnum>?ab         print a if bit is one else print b.  */
2505
2506 static const struct opcode16 thumb_opcodes[] =
2507 {
2508   /* Thumb instructions.  */
2509
2510   /* ARMv8-M Security Extensions instructions.  */
2511   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
2512   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff07, "bxns\t%3-6r"},
2513
2514   /* ARM V8 instructions.  */
2515   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xbf50, 0xffff, "sevl%c"},
2516   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xba80, 0xffc0, "hlt\t%0-5x"},
2517   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),  0xb610, 0xfff7, "setpan\t#%3-3d"},
2518
2519   /* ARM V6K no-argument instructions.  */
2520   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2521   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2522   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2523   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2524   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2525   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
2526
2527   /* ARM V6T2 instructions.  */
2528   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2529     0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2530   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2531     0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
2532   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
2533
2534   /* ARM V6.  */
2535   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2536   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2537   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2538   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2539   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2540   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2541   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2542   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2543   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2544   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2545   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
2546
2547   /* ARM V5 ISA extends Thumb.  */
2548   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2549     0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
2550   /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
2551   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2552     0x4780, 0xff87, "blx%c\t%3-6r%x"},  /* note: 4 bit register number.  */
2553   /* ARM V4T ISA (Thumb v1).  */
2554   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2555     0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
2556   /* Format 4.  */
2557   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2558   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2559   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2560   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2561   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2562   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2563   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2564   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2565   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2566   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2567   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2568   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2569   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2570   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2571   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2572   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
2573   /* format 13 */
2574   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2575   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
2576   /* format 5 */
2577   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2578   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2579   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2580   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
2581   /* format 14 */
2582   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2583   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
2584   /* format 2 */
2585   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2586     0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2587   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2588     0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2589   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2590     0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2591   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2592     0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
2593   /* format 8 */
2594   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2595     0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2596   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2597     0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2598   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2599     0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
2600   /* format 7 */
2601   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2602     0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2603   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2604     0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2605   /* format 1 */
2606   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2607   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2608     0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2609   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2610   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
2611   /* format 3 */
2612   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2613   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2614   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2615   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
2616   /* format 6 */
2617   /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2618   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2619     0x4800, 0xF800,
2620     "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
2621   /* format 9 */
2622   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2623     0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2624   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2625     0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2626   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2627     0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2628   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2629     0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
2630   /* format 10 */
2631   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2632     0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2633   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2634     0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
2635   /* format 11 */
2636   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2637     0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2638   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2639     0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
2640   /* format 12 */
2641   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2642     0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2643   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2644     0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
2645   /* format 15 */
2646   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2647   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
2648   /* format 17 */
2649   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
2650   /* format 16 */
2651   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2652   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2653   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
2654   /* format 18 */
2655   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
2656
2657   /* The E800 .. FFFF range is unconditionally redirected to the
2658      32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2659      are processed via that table.  Thus, we can never encounter a
2660      bare "second half of BL/BLX(1)" instruction here.  */
2661   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),  0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2662   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2663 };
2664
2665 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
2666    We adopt the convention that hw1 is the high 16 bits of .value and
2667    .mask, hw2 the low 16 bits.
2668
2669    print_insn_thumb32 recognizes the following format control codes:
2670
2671        %%               %
2672
2673        %I               print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2674        %M               print a modified 12-bit immediate (same location)
2675        %J               print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2676        %K               print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
2677        %H               print a 16-bit immediate from hw2[3:0],hw1[11:0]
2678        %S               print a possibly-shifted Rm
2679
2680        %L               print address for a ldrd/strd instruction
2681        %a               print the address of a plain load/store
2682        %w               print the width and signedness of a core load/store
2683        %m               print register mask for ldm/stm
2684
2685        %E               print the lsb and width fields of a bfc/bfi instruction
2686        %F               print the lsb and width fields of a sbfx/ubfx instruction
2687        %b               print a conditional branch offset
2688        %B               print an unconditional branch offset
2689        %s               print the shift field of an SSAT instruction
2690        %R               print the rotation field of an SXT instruction
2691        %U               print barrier type.
2692        %P               print address for pli instruction.
2693        %c               print the condition code
2694        %x               print warning if conditional an not at end of IT block"
2695        %X               print "\t; unpredictable <IT:code>" if conditional
2696
2697        %<bitfield>d     print bitfield in decimal
2698        %<bitfield>D     print bitfield plus one in decimal
2699        %<bitfield>W     print bitfield*4 in decimal
2700        %<bitfield>r     print bitfield as an ARM register
2701        %<bitfield>R     as %<>r but r15 is UNPREDICTABLE
2702        %<bitfield>c     print bitfield as a condition code
2703
2704        %<bitfield>'c    print specified char iff bitfield is all ones
2705        %<bitfield>`c    print specified char iff bitfield is all zeroes
2706        %<bitfield>?ab... select from array of values in big endian order
2707
2708    With one exception at the bottom (done because BL and BLX(1) need
2709    to come dead last), this table was machine-sorted first in
2710    decreasing order of number of bits set in the mask, then in
2711    increasing numeric order of mask, then in increasing numeric order
2712    of opcode.  This order is not the clearest for a human reader, but
2713    is guaranteed never to catch a special-case bit pattern with a more
2714    general mask, which is important, because this instruction encoding
2715    makes heavy use of special-case bit patterns.  */
2716 static const struct opcode32 thumb32_opcodes[] =
2717 {
2718   /* ARMv8-M and ARMv8-M Security Extensions instructions.  */
2719   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
2720   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2721     0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2722   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2723     0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
2724   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2725     0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
2726   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2727     0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
2728
2729   /* ARM V8.2 RAS extension instructions.  */
2730   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
2731     0xf3af8010, 0xffffffff, "esb"},
2732
2733   /* V8 instructions.  */
2734   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2735     0xf3af8005, 0xffffffff, "sevl%c.w"},
2736   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2737     0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2738   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2739     0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2740   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2741     0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2742   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2743     0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2744   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2745     0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2746   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2747     0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2748   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2749     0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2750   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2751     0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2752   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2753     0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2754   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2755     0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2756   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2757     0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2758   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2759     0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2760   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2761     0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2762   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2763     0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2764   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2765     0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
2766
2767   /* CRC32 instructions.  */
2768   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2769     0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
2770   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2771     0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
2772   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2773     0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
2774   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2775     0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
2776   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2777     0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
2778   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2779     0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
2780
2781   /* V7 instructions.  */
2782   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2783   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2784   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2785   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2786   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2787   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2788   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2789   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2790     0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2791   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2792     0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
2793
2794   /* Virtualization Extension instructions.  */
2795   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
2796   /* We skip ERET as that is SUBS pc, lr, #0.  */
2797
2798   /* MP Extension instructions.  */
2799   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP),   0xf830f000, 0xff70f000, "pldw%c\t%a"},
2800
2801   /* Security extension instructions.  */
2802   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
2803
2804   /* Instructions defined in the basic V6T2 set.  */
2805   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2806   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2807   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2808   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2809   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2810   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2811     0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2812   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2813
2814   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2815     0xf3bf8f2f, 0xffffffff, "clrex%c"},
2816   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2817     0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2818   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2819     0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2820   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2821     0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2822   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2823     0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2824   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2825     0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2826   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2827     0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2828   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2829     0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2830   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2831     0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2832   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2833     0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2834   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2835     0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2836   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2837     0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2838   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2839     0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2840   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2841     0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
2842   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2843     0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
2844   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2845     0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2846   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2847     0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2848   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2849     0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2850   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2851     0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2852   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2853     0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2854   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2855     0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2856   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2857     0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2858   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2859     0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2860   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2861     0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
2862   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2863     0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2864   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2865     0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2866   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2867     0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2868   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2869     0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2870   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2871     0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2872   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2873     0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2874   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2875     0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2876   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2877     0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2878   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2879     0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2880   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2881     0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2882   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2883     0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2884   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2885     0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2886   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2887     0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2888   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2889     0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2890   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2891     0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2892   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2893     0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2894   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2895     0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2896   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2897     0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2898   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2899     0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2900   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2901     0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2902   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2903     0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2904   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2905     0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2906   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2907     0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2908   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2909     0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2910   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2911     0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2912   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2913     0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2914   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2915     0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2916   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2917     0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2918   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2919     0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2920   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2921     0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2922   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2923     0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2924   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2925     0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2926   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2927     0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2928   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2929     0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2930   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2931     0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2932   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2933     0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2934   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2935     0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2936   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2937     0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2938   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2939     0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2940   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2941     0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2942   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2943     0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2944   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2945     0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2946   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2947     0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2948   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2949     0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2950   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2951     0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2952   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2953     0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2954   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2955     0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
2956   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2957     0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
2958   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2959     0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
2960   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2961     0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
2962   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2963     0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2964   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2965     0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2966   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2967     0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2968   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2969     0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
2970   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2971     0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
2972   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2973     0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
2974   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2975     0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
2976   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2977     0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
2978   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2979     0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2980   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2981     0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
2982   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2983     0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
2984   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2985     0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2986   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2987     0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2988   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2989     0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2990   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2991     0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2992   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2993     0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2994   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2995     0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2996   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2997     0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2998   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2999     0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
3000   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3001     0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
3002   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3003     0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3004   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3005     0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3006   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3007     0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3008   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3009     0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3010   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3011     0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3012   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3013     0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3014   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3015     0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3016   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3017     0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3018   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3019     0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3020   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3021     0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3022   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3023     0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3024   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3025     0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3026   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3027     0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3028   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3029     0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3030   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3031     0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3032   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3033     0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3034   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3035     0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3036   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3037     0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3038   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3039     0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3040   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3041     0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3042   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3043     0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3044   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3045     0xf810f000, 0xff70f000, "pld%c\t%a"},
3046   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3047     0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3048   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3049     0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3050   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3051     0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3052   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3053     0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3054   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3055     0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3056   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3057     0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3058   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3059     0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3060   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3061     0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3062   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3063     0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3064   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3065     0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3066   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3067     0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3068   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3069     0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3070   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3071     0xfb100000, 0xfff000c0,
3072     "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3073   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3074     0xfbc00080, 0xfff000c0,
3075     "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3076   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3077     0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3078   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3079     0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3080   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3081     0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
3082   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3083     0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3084   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3085     0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
3086   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3087     0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3088   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3089     0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
3090   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3091     0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3092   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3093     0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3094   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3095     0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3096   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3097     0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3098   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3099     0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3100   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3101     0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3102   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3103     0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3104   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3105     0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3106   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3107     0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3108   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3109     0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3110   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3111     0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
3112   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3113     0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3114   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3115     0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3116   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3117     0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3118   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3119     0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3120   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3121     0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3122   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3123     0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3124   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3125     0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3126   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3127     0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3128   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3129     0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3130   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3131     0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3132   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3133     0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3134   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3135     0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3136   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3137     0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3138   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3139     0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3140   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3141     0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3142   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3143     0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3144   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3145     0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3146   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3147     0xe9400000, 0xff500000,
3148     "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3149   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3150     0xe9500000, 0xff500000,
3151     "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3152   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3153     0xe8600000, 0xff700000,
3154     "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3155   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3156     0xe8700000, 0xff700000,
3157     "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3158   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3159     0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3160   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3161     0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
3162
3163   /* Filter out Bcc with cond=E or F, which are used for other instructions.  */
3164   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3165     0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3166   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3167     0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3168   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3169     0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3170   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3171     0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
3172
3173   /* These have been 32-bit since the invention of Thumb.  */
3174   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3175      0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3176   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3177      0xf000d000, 0xf800d000, "bl%c\t%B%x"},
3178
3179   /* Fallback.  */
3180   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3181       0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3182   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3183 };
3184
3185 static const char *const arm_conditional[] =
3186 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
3187  "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
3188
3189 static const char *const arm_fp_const[] =
3190 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3191
3192 static const char *const arm_shift[] =
3193 {"lsl", "lsr", "asr", "ror"};
3194
3195 typedef struct
3196 {
3197   const char *name;
3198   const char *description;
3199   const char *reg_names[16];
3200 }
3201 arm_regname;
3202
3203 static const arm_regname regnames[] =
3204 {
3205   { "reg-names-raw", N_("Select raw register names"),
3206     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3207   { "reg-names-gcc", N_("Select register names used by GCC"),
3208     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
3209   { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
3210     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp",  "lr",  "pc" }},
3211   { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
3212   { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
3213   { "reg-names-apcs", N_("Select register names used in the APCS"),
3214     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
3215   { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
3216     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7",  "v8",  "IP",  "SP",  "LR",  "PC" }},
3217   { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3218     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }}
3219 };
3220
3221 static const char *const iwmmxt_wwnames[] =
3222 {"b", "h", "w", "d"};
3223
3224 static const char *const iwmmxt_wwssnames[] =
3225 {"b", "bus", "bc", "bss",
3226  "h", "hus", "hc", "hss",
3227  "w", "wus", "wc", "wss",
3228  "d", "dus", "dc", "dss"
3229 };
3230
3231 static const char *const iwmmxt_regnames[] =
3232 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3233   "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3234 };
3235
3236 static const char *const iwmmxt_cregnames[] =
3237 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3238   "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3239 };
3240
3241 /* Default to GCC register name set.  */
3242 static unsigned int regname_selected = 1;
3243
3244 #define NUM_ARM_OPTIONS   ARRAY_SIZE (regnames)
3245 #define arm_regnames      regnames[regname_selected].reg_names
3246
3247 static bfd_boolean force_thumb = FALSE;
3248
3249 /* Current IT instruction state.  This contains the same state as the IT
3250    bits in the CPSR.  */
3251 static unsigned int ifthen_state;
3252 /* IT state for the next instruction.  */
3253 static unsigned int ifthen_next_state;
3254 /* The address of the insn for which the IT state is valid.  */
3255 static bfd_vma ifthen_address;
3256 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
3257 /* Indicates that the current Conditional state is unconditional or outside
3258    an IT block.  */
3259 #define COND_UNCOND 16
3260
3261 \f
3262 /* Functions.  */
3263
3264 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3265    Returns pointer to following character of the format string and
3266    fills in *VALUEP and *WIDTHP with the extracted value and number of
3267    bits extracted.  WIDTHP can be NULL.  */
3268
3269 static const char *
3270 arm_decode_bitfield (const char *ptr,
3271                      unsigned long insn,
3272                      unsigned long *valuep,
3273                      int *widthp)
3274 {
3275   unsigned long value = 0;
3276   int width = 0;
3277
3278   do
3279     {
3280       int start, end;
3281       int bits;
3282
3283       for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3284         start = start * 10 + *ptr - '0';
3285       if (*ptr == '-')
3286         for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3287           end = end * 10 + *ptr - '0';
3288       else
3289         end = start;
3290       bits = end - start;
3291       if (bits < 0)
3292         abort ();
3293       value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3294       width += bits + 1;
3295     }
3296   while (*ptr++ == ',');
3297   *valuep = value;
3298   if (widthp)
3299     *widthp = width;
3300   return ptr - 1;
3301 }
3302
3303 static void
3304 arm_decode_shift (long given, fprintf_ftype func, void *stream,
3305                   bfd_boolean print_shift)
3306 {
3307   func (stream, "%s", arm_regnames[given & 0xf]);
3308
3309   if ((given & 0xff0) != 0)
3310     {
3311       if ((given & 0x10) == 0)
3312         {
3313           int amount = (given & 0xf80) >> 7;
3314           int shift = (given & 0x60) >> 5;
3315
3316           if (amount == 0)
3317             {
3318               if (shift == 3)
3319                 {
3320                   func (stream, ", rrx");
3321                   return;
3322                 }
3323
3324               amount = 32;
3325             }
3326
3327           if (print_shift)
3328             func (stream, ", %s #%d", arm_shift[shift], amount);
3329           else
3330             func (stream, ", #%d", amount);
3331         }
3332       else if ((given & 0x80) == 0x80)
3333         func (stream, "\t; <illegal shifter operand>");
3334       else if (print_shift)
3335         func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3336               arm_regnames[(given & 0xf00) >> 8]);
3337       else
3338         func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
3339     }
3340 }
3341
3342 #define W_BIT 21
3343 #define I_BIT 22
3344 #define U_BIT 23
3345 #define P_BIT 24
3346
3347 #define WRITEBACK_BIT_SET   (given & (1 << W_BIT))
3348 #define IMMEDIATE_BIT_SET   (given & (1 << I_BIT))
3349 #define NEGATIVE_BIT_SET   ((given & (1 << U_BIT)) == 0)
3350 #define PRE_BIT_SET         (given & (1 << P_BIT))
3351
3352 /* Print one coprocessor instruction on INFO->STREAM.
3353    Return TRUE if the instuction matched, FALSE if this is not a
3354    recognised coprocessor instruction.  */
3355
3356 static bfd_boolean
3357 print_insn_coprocessor (bfd_vma pc,
3358                         struct disassemble_info *info,
3359                         long given,
3360                         bfd_boolean thumb)
3361 {
3362   const struct opcode32 *insn;
3363   void *stream = info->stream;
3364   fprintf_ftype func = info->fprintf_func;
3365   unsigned long mask;
3366   unsigned long value = 0;
3367   int cond;
3368   int cp_num;
3369   struct arm_private_data *private_data = info->private_data;
3370   arm_feature_set allowed_arches = ARM_ARCH_NONE;
3371
3372   ARM_FEATURE_COPY (allowed_arches, private_data->features);
3373
3374   for (insn = coprocessor_opcodes; insn->assembler; insn++)
3375     {
3376       unsigned long u_reg = 16;
3377       bfd_boolean is_unpredictable = FALSE;
3378       signed long value_in_comment = 0;
3379       const char *c;
3380
3381       if (ARM_FEATURE_ZERO (insn->arch))
3382         switch (insn->value)
3383           {
3384           case SENTINEL_IWMMXT_START:
3385             if (info->mach != bfd_mach_arm_XScale
3386                 && info->mach != bfd_mach_arm_iWMMXt
3387                 && info->mach != bfd_mach_arm_iWMMXt2)
3388               do
3389                 insn++;
3390               while ((! ARM_FEATURE_ZERO (insn->arch))
3391                      && insn->value != SENTINEL_IWMMXT_END);
3392             continue;
3393
3394           case SENTINEL_IWMMXT_END:
3395             continue;
3396
3397           case SENTINEL_GENERIC_START:
3398             ARM_FEATURE_COPY (allowed_arches, private_data->features);
3399             continue;
3400
3401           default:
3402             abort ();
3403           }
3404
3405       mask = insn->mask;
3406       value = insn->value;
3407       cp_num = (given >> 8) & 0xf;
3408
3409       if (thumb)
3410         {
3411           /* The high 4 bits are 0xe for Arm conditional instructions, and
3412              0xe for arm unconditional instructions.  The rest of the
3413              encoding is the same.  */
3414           mask |= 0xf0000000;
3415           value |= 0xe0000000;
3416           if (ifthen_state)
3417             cond = IFTHEN_COND;
3418           else
3419             cond = COND_UNCOND;
3420         }
3421       else
3422         {
3423           /* Only match unconditional instuctions against unconditional
3424              patterns.  */
3425           if ((given & 0xf0000000) == 0xf0000000)
3426             {
3427               mask |= 0xf0000000;
3428               cond = COND_UNCOND;
3429             }
3430           else
3431             {
3432               cond = (given >> 28) & 0xf;
3433               if (cond == 0xe)
3434                 cond = COND_UNCOND;
3435             }
3436         }
3437
3438       if ((given & mask) != value)
3439         continue;
3440
3441       if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
3442         continue;
3443
3444       if (insn->value == 0xfe000010     /* mcr2  */
3445           || insn->value == 0xfe100010  /* mrc2  */
3446           || insn->value == 0xfc100000  /* ldc2  */
3447           || insn->value == 0xfc000000) /* stc2  */
3448         {
3449           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
3450             is_unpredictable = TRUE;
3451         }
3452       else if (insn->value == 0x0e000000     /* cdp  */
3453                || insn->value == 0xfe000000  /* cdp2  */
3454                || insn->value == 0x0e000010  /* mcr  */
3455                || insn->value == 0x0e100010  /* mrc  */
3456                || insn->value == 0x0c100000  /* ldc  */
3457                || insn->value == 0x0c000000) /* stc  */
3458         {
3459           /* Floating-point instructions.  */
3460           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
3461             continue;
3462         }
3463
3464       for (c = insn->assembler; *c; c++)
3465         {
3466           if (*c == '%')
3467             {
3468               switch (*++c)
3469                 {
3470                 case '%':
3471                   func (stream, "%%");
3472                   break;
3473
3474                 case 'A':
3475                   {
3476                     int rn = (given >> 16) & 0xf;
3477                     bfd_vma offset = given & 0xff;
3478
3479                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3480
3481                     if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3482                       {
3483                         /* Not unindexed.  The offset is scaled.  */
3484                         if (cp_num == 9)
3485                           /* vldr.16/vstr.16 will shift the address
3486                              left by 1 bit only.  */
3487                           offset = offset * 2;
3488                         else
3489                           offset = offset * 4;
3490
3491                         if (NEGATIVE_BIT_SET)
3492                           offset = - offset;
3493                         if (rn != 15)
3494                           value_in_comment = offset;
3495                       }
3496
3497                     if (PRE_BIT_SET)
3498                       {
3499                         if (offset)
3500                           func (stream, ", #%d]%s",
3501                                 (int) offset,
3502                                 WRITEBACK_BIT_SET ? "!" : "");
3503                         else if (NEGATIVE_BIT_SET)
3504                           func (stream, ", #-0]");
3505                         else
3506                           func (stream, "]");
3507                       }
3508                     else
3509                       {
3510                         func (stream, "]");
3511
3512                         if (WRITEBACK_BIT_SET)
3513                           {
3514                             if (offset)
3515                               func (stream, ", #%d", (int) offset);
3516                             else if (NEGATIVE_BIT_SET)
3517                               func (stream, ", #-0");
3518                           }
3519                         else
3520                           {
3521                             func (stream, ", {%s%d}",
3522                                   (NEGATIVE_BIT_SET && !offset) ? "-" : "",
3523                                   (int) offset);
3524                             value_in_comment = offset;
3525                           }
3526                       }
3527                     if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3528                       {
3529                         func (stream, "\t; ");
3530                         /* For unaligned PCs, apply off-by-alignment
3531                            correction.  */
3532                         info->print_address_func (offset + pc
3533                                                   + info->bytes_per_chunk * 2
3534                                                   - (pc & 3),
3535                                                   info);
3536                       }
3537                   }
3538                   break;
3539
3540                 case 'B':
3541                   {
3542                     int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3543                     int offset = (given >> 1) & 0x3f;
3544
3545                     if (offset == 1)
3546                       func (stream, "{d%d}", regno);
3547                     else if (regno + offset > 32)
3548                       func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3549                     else
3550                       func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3551                   }
3552                   break;
3553
3554                 case 'u':
3555                   if (cond != COND_UNCOND)
3556                     is_unpredictable = TRUE;
3557
3558                   /* Fall through.  */
3559                 case 'c':
3560                   if (cond != COND_UNCOND && cp_num == 9)
3561                     is_unpredictable = TRUE;
3562
3563                   func (stream, "%s", arm_conditional[cond]);
3564                   break;
3565
3566                 case 'I':
3567                   /* Print a Cirrus/DSP shift immediate.  */
3568                   /* Immediates are 7bit signed ints with bits 0..3 in
3569                      bits 0..3 of opcode and bits 4..6 in bits 5..7
3570                      of opcode.  */
3571                   {
3572                     int imm;
3573
3574                     imm = (given & 0xf) | ((given & 0xe0) >> 1);
3575
3576                     /* Is ``imm'' a negative number?  */
3577                     if (imm & 0x40)
3578                       imm -= 0x80;
3579
3580                     func (stream, "%d", imm);
3581                   }
3582
3583                   break;
3584
3585                 case 'F':
3586                   switch (given & 0x00408000)
3587                     {
3588                     case 0:
3589                       func (stream, "4");
3590                       break;
3591                     case 0x8000:
3592                       func (stream, "1");
3593                       break;
3594                     case 0x00400000:
3595                       func (stream, "2");
3596                       break;
3597                     default:
3598                       func (stream, "3");
3599                     }
3600                   break;
3601
3602                 case 'P':
3603                   switch (given & 0x00080080)
3604                     {
3605                     case 0:
3606                       func (stream, "s");
3607                       break;
3608                     case 0x80:
3609                       func (stream, "d");
3610                       break;
3611                     case 0x00080000:
3612                       func (stream, "e");
3613                       break;
3614                     default:
3615                       func (stream, _("<illegal precision>"));
3616                       break;
3617                     }
3618                   break;
3619
3620                 case 'Q':
3621                   switch (given & 0x00408000)
3622                     {
3623                     case 0:
3624                       func (stream, "s");
3625                       break;
3626                     case 0x8000:
3627                       func (stream, "d");
3628                       break;
3629                     case 0x00400000:
3630                       func (stream, "e");
3631                       break;
3632                     default:
3633                       func (stream, "p");
3634                       break;
3635                     }
3636                   break;
3637
3638                 case 'R':
3639                   switch (given & 0x60)
3640                     {
3641                     case 0:
3642                       break;
3643                     case 0x20:
3644                       func (stream, "p");
3645                       break;
3646                     case 0x40:
3647                       func (stream, "m");
3648                       break;
3649                     default:
3650                       func (stream, "z");
3651                       break;
3652                     }
3653                   break;
3654
3655                 case '0': case '1': case '2': case '3': case '4':
3656                 case '5': case '6': case '7': case '8': case '9':
3657                   {
3658                     int width;
3659
3660                     c = arm_decode_bitfield (c, given, &value, &width);
3661
3662                     switch (*c)
3663                       {
3664                       case 'R':
3665                         if (value == 15)
3666                           is_unpredictable = TRUE;
3667                         /* Fall through.  */
3668                       case 'r':
3669                         if (c[1] == 'u')
3670                           {
3671                             /* Eat the 'u' character.  */
3672                             ++ c;
3673
3674                             if (u_reg == value)
3675                               is_unpredictable = TRUE;
3676                             u_reg = value;
3677                           }
3678                         func (stream, "%s", arm_regnames[value]);
3679                         break;
3680                       case 'V':
3681                         if (given & (1 << 6))
3682                           goto Q;
3683                         /* FALLTHROUGH */
3684                       case 'D':
3685                         func (stream, "d%ld", value);
3686                         break;
3687                       case 'Q':
3688                       Q:
3689                         if (value & 1)
3690                           func (stream, "<illegal reg q%ld.5>", value >> 1);
3691                         else
3692                           func (stream, "q%ld", value >> 1);
3693                         break;
3694                       case 'd':
3695                         func (stream, "%ld", value);
3696                         value_in_comment = value;
3697                         break;
3698                       case 'E':
3699                         {
3700                           /* Converts immediate 8 bit back to float value.  */
3701                           unsigned floatVal = (value & 0x80) << 24
3702                             | (value & 0x3F) << 19
3703                             | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3704
3705                           /* Quarter float have a maximum value of 31.0.
3706                              Get floating point value multiplied by 1e7.
3707                              The maximum value stays in limit of a 32-bit int.  */
3708                           unsigned decVal =
3709                             (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3710                             (16 + (value & 0xF));
3711
3712                           if (!(decVal % 1000000))
3713                             func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3714                                   floatVal, value & 0x80 ? '-' : ' ',
3715                                   decVal / 10000000,
3716                                   decVal % 10000000 / 1000000);
3717                           else if (!(decVal % 10000))
3718                             func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3719                                   floatVal, value & 0x80 ? '-' : ' ',
3720                                   decVal / 10000000,
3721                                   decVal % 10000000 / 10000);
3722                           else
3723                             func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3724                                   floatVal, value & 0x80 ? '-' : ' ',
3725                                   decVal / 10000000, decVal % 10000000);
3726                           break;
3727                         }
3728                       case 'k':
3729                         {
3730                           int from = (given & (1 << 7)) ? 32 : 16;
3731                           func (stream, "%ld", from - value);
3732                         }
3733                         break;
3734
3735                       case 'f':
3736                         if (value > 7)
3737                           func (stream, "#%s", arm_fp_const[value & 7]);
3738                         else
3739                           func (stream, "f%ld", value);
3740                         break;
3741
3742                       case 'w':
3743                         if (width == 2)
3744                           func (stream, "%s", iwmmxt_wwnames[value]);
3745                         else
3746                           func (stream, "%s", iwmmxt_wwssnames[value]);
3747                         break;
3748
3749                       case 'g':
3750                         func (stream, "%s", iwmmxt_regnames[value]);
3751                         break;
3752                       case 'G':
3753                         func (stream, "%s", iwmmxt_cregnames[value]);
3754                         break;
3755
3756                       case 'x':
3757                         func (stream, "0x%lx", (value & 0xffffffffUL));
3758                         break;
3759
3760                       case 'c':
3761                         switch (value)
3762                           {
3763                           case 0:
3764                             func (stream, "eq");
3765                             break;
3766
3767                           case 1:
3768                             func (stream, "vs");
3769                             break;
3770
3771                           case 2:
3772                             func (stream, "ge");
3773                             break;
3774
3775                           case 3:
3776                             func (stream, "gt");
3777                             break;
3778
3779                           default:
3780                             func (stream, "??");
3781                             break;
3782                           }
3783                         break;
3784
3785                       case '`':
3786                         c++;
3787                         if (value == 0)
3788                           func (stream, "%c", *c);
3789                         break;
3790                       case '\'':
3791                         c++;
3792                         if (value == ((1ul << width) - 1))
3793                           func (stream, "%c", *c);
3794                         break;
3795                       case '?':
3796                         func (stream, "%c", c[(1 << width) - (int) value]);
3797                         c += 1 << width;
3798                         break;
3799                       default:
3800                         abort ();
3801                       }
3802                     break;
3803
3804                   case 'y':
3805                   case 'z':
3806                     {
3807                       int single = *c++ == 'y';
3808                       int regno;
3809
3810                       switch (*c)
3811                         {
3812                         case '4': /* Sm pair */
3813                         case '0': /* Sm, Dm */
3814                           regno = given & 0x0000000f;
3815                           if (single)
3816                             {
3817                               regno <<= 1;
3818                               regno += (given >> 5) & 1;
3819                             }
3820                           else
3821                             regno += ((given >> 5) & 1) << 4;
3822                           break;
3823
3824                         case '1': /* Sd, Dd */
3825                           regno = (given >> 12) & 0x0000000f;
3826                           if (single)
3827                             {
3828                               regno <<= 1;
3829                               regno += (given >> 22) & 1;
3830                             }
3831                           else
3832                             regno += ((given >> 22) & 1) << 4;
3833                           break;
3834
3835                         case '2': /* Sn, Dn */
3836                           regno = (given >> 16) & 0x0000000f;
3837                           if (single)
3838                             {
3839                               regno <<= 1;
3840                               regno += (given >> 7) & 1;
3841                             }
3842                           else
3843                             regno += ((given >> 7) & 1) << 4;
3844                           break;
3845
3846                         case '3': /* List */
3847                           func (stream, "{");
3848                           regno = (given >> 12) & 0x0000000f;
3849                           if (single)
3850                             {
3851                               regno <<= 1;
3852                               regno += (given >> 22) & 1;
3853                             }
3854                           else
3855                             regno += ((given >> 22) & 1) << 4;
3856                           break;
3857
3858                         default:
3859                           abort ();
3860                         }
3861
3862                       func (stream, "%c%d", single ? 's' : 'd', regno);
3863
3864                       if (*c == '3')
3865                         {
3866                           int count = given & 0xff;
3867
3868                           if (single == 0)
3869                             count >>= 1;
3870
3871                           if (--count)
3872                             {
3873                               func (stream, "-%c%d",
3874                                     single ? 's' : 'd',
3875                                     regno + count);
3876                             }
3877
3878                           func (stream, "}");
3879                         }
3880                       else if (*c == '4')
3881                         func (stream, ", %c%d", single ? 's' : 'd',
3882                               regno + 1);
3883                     }
3884                     break;
3885
3886                   case 'L':
3887                     switch (given & 0x00400100)
3888                       {
3889                       case 0x00000000: func (stream, "b"); break;
3890                       case 0x00400000: func (stream, "h"); break;
3891                       case 0x00000100: func (stream, "w"); break;
3892                       case 0x00400100: func (stream, "d"); break;
3893                       default:
3894                         break;
3895                       }
3896                     break;
3897
3898                   case 'Z':
3899                     {
3900                       /* given (20, 23) | given (0, 3) */
3901                       value = ((given >> 16) & 0xf0) | (given & 0xf);
3902                       func (stream, "%d", (int) value);
3903                     }
3904                     break;
3905
3906                   case 'l':
3907                     /* This is like the 'A' operator, except that if
3908                        the width field "M" is zero, then the offset is
3909                        *not* multiplied by four.  */
3910                     {
3911                       int offset = given & 0xff;
3912                       int multiplier = (given & 0x00000100) ? 4 : 1;
3913
3914                       func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3915
3916                       if (multiplier > 1)
3917                         {
3918                           value_in_comment = offset * multiplier;
3919                           if (NEGATIVE_BIT_SET)
3920                             value_in_comment = - value_in_comment;
3921                         }
3922
3923                       if (offset)
3924                         {
3925                           if (PRE_BIT_SET)
3926                             func (stream, ", #%s%d]%s",
3927                                   NEGATIVE_BIT_SET ? "-" : "",
3928                                   offset * multiplier,
3929                                   WRITEBACK_BIT_SET ? "!" : "");
3930                           else
3931                             func (stream, "], #%s%d",
3932                                   NEGATIVE_BIT_SET ? "-" : "",
3933                                   offset * multiplier);
3934                         }
3935                       else
3936                         func (stream, "]");
3937                     }
3938                     break;
3939
3940                   case 'r':
3941                     {
3942                       int imm4 = (given >> 4) & 0xf;
3943                       int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3944                       int ubit = ! NEGATIVE_BIT_SET;
3945                       const char *rm = arm_regnames [given & 0xf];
3946                       const char *rn = arm_regnames [(given >> 16) & 0xf];
3947
3948                       switch (puw_bits)
3949                         {
3950                         case 1:
3951                         case 3:
3952                           func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3953                           if (imm4)
3954                             func (stream, ", lsl #%d", imm4);
3955                           break;
3956
3957                         case 4:
3958                         case 5:
3959                         case 6:
3960                         case 7:
3961                           func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3962                           if (imm4 > 0)
3963                             func (stream, ", lsl #%d", imm4);
3964                           func (stream, "]");
3965                           if (puw_bits == 5 || puw_bits == 7)
3966                             func (stream, "!");
3967                           break;
3968
3969                         default:
3970                           func (stream, "INVALID");
3971                         }
3972                     }
3973                     break;
3974
3975                   case 'i':
3976                     {
3977                       long imm5;
3978                       imm5 = ((given & 0x100) >> 4) | (given & 0xf);
3979                       func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
3980                     }
3981                     break;
3982
3983                   default:
3984                     abort ();
3985                   }
3986                 }
3987             }
3988           else
3989             func (stream, "%c", *c);
3990         }
3991
3992       if (value_in_comment > 32 || value_in_comment < -16)
3993         func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
3994
3995       if (is_unpredictable)
3996         func (stream, UNPREDICTABLE_INSTRUCTION);
3997
3998       return TRUE;
3999     }
4000   return FALSE;
4001 }
4002
4003 /* Decodes and prints ARM addressing modes.  Returns the offset
4004    used in the address, if any, if it is worthwhile printing the
4005    offset as a hexadecimal value in a comment at the end of the
4006    line of disassembly.  */
4007
4008 static signed long
4009 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
4010 {
4011   void *stream = info->stream;
4012   fprintf_ftype func = info->fprintf_func;
4013   bfd_vma offset = 0;
4014
4015   if (((given & 0x000f0000) == 0x000f0000)
4016       && ((given & 0x02000000) == 0))
4017     {
4018       offset = given & 0xfff;
4019
4020       func (stream, "[pc");
4021
4022       if (PRE_BIT_SET)
4023         {
4024           /* Pre-indexed.  Elide offset of positive zero when
4025              non-writeback.  */
4026           if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
4027             func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4028
4029           if (NEGATIVE_BIT_SET)
4030             offset = -offset;
4031
4032           offset += pc + 8;
4033
4034           /* Cope with the possibility of write-back
4035              being used.  Probably a very dangerous thing
4036              for the programmer to do, but who are we to
4037              argue ?  */
4038           func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
4039         }
4040       else  /* Post indexed.  */
4041         {
4042           func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4043
4044           /* Ie ignore the offset.  */
4045           offset = pc + 8;
4046         }
4047
4048       func (stream, "\t; ");
4049       info->print_address_func (offset, info);
4050       offset = 0;
4051     }
4052   else
4053     {
4054       func (stream, "[%s",
4055             arm_regnames[(given >> 16) & 0xf]);
4056
4057       if (PRE_BIT_SET)
4058         {
4059           if ((given & 0x02000000) == 0)
4060             {
4061               /* Elide offset of positive zero when non-writeback.  */
4062               offset = given & 0xfff;
4063               if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
4064                 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4065             }
4066           else
4067             {
4068               func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
4069               arm_decode_shift (given, func, stream, TRUE);
4070             }
4071
4072           func (stream, "]%s",
4073                 WRITEBACK_BIT_SET ? "!" : "");
4074         }
4075       else
4076         {
4077           if ((given & 0x02000000) == 0)
4078             {
4079               /* Always show offset.  */
4080               offset = given & 0xfff;
4081               func (stream, "], #%s%d",
4082                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4083             }
4084           else
4085             {
4086               func (stream, "], %s",
4087                     NEGATIVE_BIT_SET ? "-" : "");
4088               arm_decode_shift (given, func, stream, TRUE);
4089             }
4090         }
4091       if (NEGATIVE_BIT_SET)
4092         offset = -offset;
4093     }
4094
4095   return (signed long) offset;
4096 }
4097
4098 /* Print one neon instruction on INFO->STREAM.
4099    Return TRUE if the instuction matched, FALSE if this is not a
4100    recognised neon instruction.  */
4101
4102 static bfd_boolean
4103 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
4104 {
4105   const struct opcode32 *insn;
4106   void *stream = info->stream;
4107   fprintf_ftype func = info->fprintf_func;
4108
4109   if (thumb)
4110     {
4111       if ((given & 0xef000000) == 0xef000000)
4112         {
4113           /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding.  */
4114           unsigned long bit28 = given & (1 << 28);
4115
4116           given &= 0x00ffffff;
4117           if (bit28)
4118             given |= 0xf3000000;
4119           else
4120             given |= 0xf2000000;
4121         }
4122       else if ((given & 0xff000000) == 0xf9000000)
4123         given ^= 0xf9000000 ^ 0xf4000000;
4124       else
4125         return FALSE;
4126     }
4127
4128   for (insn = neon_opcodes; insn->assembler; insn++)
4129     {
4130       if ((given & insn->mask) == insn->value)
4131         {
4132           signed long value_in_comment = 0;
4133           bfd_boolean is_unpredictable = FALSE;
4134           const char *c;
4135
4136           for (c = insn->assembler; *c; c++)
4137             {
4138               if (*c == '%')
4139                 {
4140                   switch (*++c)
4141                     {
4142                     case '%':
4143                       func (stream, "%%");
4144                       break;
4145
4146                     case 'u':
4147                       if (thumb && ifthen_state)
4148                         is_unpredictable = TRUE;
4149
4150                       /* Fall through.  */
4151                     case 'c':
4152                       if (thumb && ifthen_state)
4153                         func (stream, "%s", arm_conditional[IFTHEN_COND]);
4154                       break;
4155
4156                     case 'A':
4157                       {
4158                         static const unsigned char enc[16] =
4159                         {
4160                           0x4, 0x14, /* st4 0,1 */
4161                           0x4, /* st1 2 */
4162                           0x4, /* st2 3 */
4163                           0x3, /* st3 4 */
4164                           0x13, /* st3 5 */
4165                           0x3, /* st1 6 */
4166                           0x1, /* st1 7 */
4167                           0x2, /* st2 8 */
4168                           0x12, /* st2 9 */
4169                           0x2, /* st1 10 */
4170                           0, 0, 0, 0, 0
4171                         };
4172                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4173                         int rn = ((given >> 16) & 0xf);
4174                         int rm = ((given >> 0) & 0xf);
4175                         int align = ((given >> 4) & 0x3);
4176                         int type = ((given >> 8) & 0xf);
4177                         int n = enc[type] & 0xf;
4178                         int stride = (enc[type] >> 4) + 1;
4179                         int ix;
4180
4181                         func (stream, "{");
4182                         if (stride > 1)
4183                           for (ix = 0; ix != n; ix++)
4184                             func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
4185                         else if (n == 1)
4186                           func (stream, "d%d", rd);
4187                         else
4188                           func (stream, "d%d-d%d", rd, rd + n - 1);
4189                         func (stream, "}, [%s", arm_regnames[rn]);
4190                         if (align)
4191                           func (stream, " :%d", 32 << align);
4192                         func (stream, "]");
4193                         if (rm == 0xd)
4194                           func (stream, "!");
4195                         else if (rm != 0xf)
4196                           func (stream, ", %s", arm_regnames[rm]);
4197                       }
4198                       break;
4199
4200                     case 'B':
4201                       {
4202                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4203                         int rn = ((given >> 16) & 0xf);
4204                         int rm = ((given >> 0) & 0xf);
4205                         int idx_align = ((given >> 4) & 0xf);
4206                         int align = 0;
4207                         int size = ((given >> 10) & 0x3);
4208                         int idx = idx_align >> (size + 1);
4209                         int length = ((given >> 8) & 3) + 1;
4210                         int stride = 1;
4211                         int i;
4212
4213                         if (length > 1 && size > 0)
4214                           stride = (idx_align & (1 << size)) ? 2 : 1;
4215
4216                         switch (length)
4217                           {
4218                           case 1:
4219                             {
4220                               int amask = (1 << size) - 1;
4221                               if ((idx_align & (1 << size)) != 0)
4222                                 return FALSE;
4223                               if (size > 0)
4224                                 {
4225                                   if ((idx_align & amask) == amask)
4226                                     align = 8 << size;
4227                                   else if ((idx_align & amask) != 0)
4228                                     return FALSE;
4229                                 }
4230                               }
4231                             break;
4232
4233                           case 2:
4234                             if (size == 2 && (idx_align & 2) != 0)
4235                               return FALSE;
4236                             align = (idx_align & 1) ? 16 << size : 0;
4237                             break;
4238
4239                           case 3:
4240                             if ((size == 2 && (idx_align & 3) != 0)
4241                                 || (idx_align & 1) != 0)
4242                               return FALSE;
4243                             break;
4244
4245                           case 4:
4246                             if (size == 2)
4247                               {
4248                                 if ((idx_align & 3) == 3)
4249                                   return FALSE;
4250                                 align = (idx_align & 3) * 64;
4251                               }
4252                             else
4253                               align = (idx_align & 1) ? 32 << size : 0;
4254                             break;
4255
4256                           default:
4257                             abort ();
4258                           }
4259
4260                         func (stream, "{");
4261                         for (i = 0; i < length; i++)
4262                           func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4263                             rd + i * stride, idx);
4264                         func (stream, "}, [%s", arm_regnames[rn]);
4265                         if (align)
4266                           func (stream, " :%d", align);
4267                         func (stream, "]");
4268                         if (rm == 0xd)
4269                           func (stream, "!");
4270                         else if (rm != 0xf)
4271                           func (stream, ", %s", arm_regnames[rm]);
4272                       }
4273                       break;
4274
4275                     case 'C':
4276                       {
4277                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4278                         int rn = ((given >> 16) & 0xf);
4279                         int rm = ((given >> 0) & 0xf);
4280                         int align = ((given >> 4) & 0x1);
4281                         int size = ((given >> 6) & 0x3);
4282                         int type = ((given >> 8) & 0x3);
4283                         int n = type + 1;
4284                         int stride = ((given >> 5) & 0x1);
4285                         int ix;
4286
4287                         if (stride && (n == 1))
4288                           n++;
4289                         else
4290                           stride++;
4291
4292                         func (stream, "{");
4293                         if (stride > 1)
4294                           for (ix = 0; ix != n; ix++)
4295                             func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4296                         else if (n == 1)
4297                           func (stream, "d%d[]", rd);
4298                         else
4299                           func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4300                         func (stream, "}, [%s", arm_regnames[rn]);
4301                         if (align)
4302                           {
4303                             align = (8 * (type + 1)) << size;
4304                             if (type == 3)
4305                               align = (size > 1) ? align >> 1 : align;
4306                             if (type == 2 || (type == 0 && !size))
4307                               func (stream, " :<bad align %d>", align);
4308                             else
4309                               func (stream, " :%d", align);
4310                           }
4311                         func (stream, "]");
4312                         if (rm == 0xd)
4313                           func (stream, "!");
4314                         else if (rm != 0xf)
4315                           func (stream, ", %s", arm_regnames[rm]);
4316                       }
4317                       break;
4318
4319                     case 'D':
4320                       {
4321                         int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4322                         int size = (given >> 20) & 3;
4323                         int reg = raw_reg & ((4 << size) - 1);
4324                         int ix = raw_reg >> size >> 2;
4325
4326                         func (stream, "d%d[%d]", reg, ix);
4327                       }
4328                       break;
4329
4330                     case 'E':
4331                       /* Neon encoded constant for mov, mvn, vorr, vbic.  */
4332                       {
4333                         int bits = 0;
4334                         int cmode = (given >> 8) & 0xf;
4335                         int op = (given >> 5) & 0x1;
4336                         unsigned long value = 0, hival = 0;
4337                         unsigned shift;
4338                         int size = 0;
4339                         int isfloat = 0;
4340
4341                         bits |= ((given >> 24) & 1) << 7;
4342                         bits |= ((given >> 16) & 7) << 4;
4343                         bits |= ((given >> 0) & 15) << 0;
4344
4345                         if (cmode < 8)
4346                           {
4347                             shift = (cmode >> 1) & 3;
4348                             value = (unsigned long) bits << (8 * shift);
4349                             size = 32;
4350                           }
4351                         else if (cmode < 12)
4352                           {
4353                             shift = (cmode >> 1) & 1;
4354                             value = (unsigned long) bits << (8 * shift);
4355                             size = 16;
4356                           }
4357                         else if (cmode < 14)
4358                           {
4359                             shift = (cmode & 1) + 1;
4360                             value = (unsigned long) bits << (8 * shift);
4361                             value |= (1ul << (8 * shift)) - 1;
4362                             size = 32;
4363                           }
4364                         else if (cmode == 14)
4365                           {
4366                             if (op)
4367                               {
4368                                 /* Bit replication into bytes.  */
4369                                 int ix;
4370                                 unsigned long mask;
4371
4372                                 value = 0;
4373                                 hival = 0;
4374                                 for (ix = 7; ix >= 0; ix--)
4375                                   {
4376                                     mask = ((bits >> ix) & 1) ? 0xff : 0;
4377                                     if (ix <= 3)
4378                                       value = (value << 8) | mask;
4379                                     else
4380                                       hival = (hival << 8) | mask;
4381                                   }
4382                                 size = 64;
4383                               }
4384                             else
4385                               {
4386                                 /* Byte replication.  */
4387                                 value = (unsigned long) bits;
4388                                 size = 8;
4389                               }
4390                           }
4391                         else if (!op)
4392                           {
4393                             /* Floating point encoding.  */
4394                             int tmp;
4395
4396                             value = (unsigned long)  (bits & 0x7f) << 19;
4397                             value |= (unsigned long) (bits & 0x80) << 24;
4398                             tmp = bits & 0x40 ? 0x3c : 0x40;
4399                             value |= (unsigned long) tmp << 24;
4400                             size = 32;
4401                             isfloat = 1;
4402                           }
4403                         else
4404                           {
4405                             func (stream, "<illegal constant %.8x:%x:%x>",
4406                                   bits, cmode, op);
4407                             size = 32;
4408                             break;
4409                           }
4410                         switch (size)
4411                           {
4412                           case 8:
4413                             func (stream, "#%ld\t; 0x%.2lx", value, value);
4414                             break;
4415
4416                           case 16:
4417                             func (stream, "#%ld\t; 0x%.4lx", value, value);
4418                             break;
4419
4420                           case 32:
4421                             if (isfloat)
4422                               {
4423                                 unsigned char valbytes[4];
4424                                 double fvalue;
4425
4426                                 /* Do this a byte at a time so we don't have to
4427                                    worry about the host's endianness.  */
4428                                 valbytes[0] = value & 0xff;
4429                                 valbytes[1] = (value >> 8) & 0xff;
4430                                 valbytes[2] = (value >> 16) & 0xff;
4431                                 valbytes[3] = (value >> 24) & 0xff;
4432
4433                                 floatformat_to_double
4434                                   (& floatformat_ieee_single_little, valbytes,
4435                                   & fvalue);
4436
4437                                 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4438                                       value);
4439                               }
4440                             else
4441                               func (stream, "#%ld\t; 0x%.8lx",
4442                                     (long) (((value & 0x80000000L) != 0)
4443                                             ? value | ~0xffffffffL : value),
4444                                     value);
4445                             break;
4446
4447                           case 64:
4448                             func (stream, "#0x%.8lx%.8lx", hival, value);
4449                             break;
4450
4451                           default:
4452                             abort ();
4453                           }
4454                       }
4455                       break;
4456
4457                     case 'F':
4458                       {
4459                         int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4460                         int num = (given >> 8) & 0x3;
4461
4462                         if (!num)
4463                           func (stream, "{d%d}", regno);
4464                         else if (num + regno >= 32)
4465                           func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4466                         else
4467                           func (stream, "{d%d-d%d}", regno, regno + num);
4468                       }
4469                       break;
4470
4471
4472                     case '0': case '1': case '2': case '3': case '4':
4473                     case '5': case '6': case '7': case '8': case '9':
4474                       {
4475                         int width;
4476                         unsigned long value;
4477
4478                         c = arm_decode_bitfield (c, given, &value, &width);
4479
4480                         switch (*c)
4481                           {
4482                           case 'r':
4483                             func (stream, "%s", arm_regnames[value]);
4484                             break;
4485                           case 'd':
4486                             func (stream, "%ld", value);
4487                             value_in_comment = value;
4488                             break;
4489                           case 'e':
4490                             func (stream, "%ld", (1ul << width) - value);
4491                             break;
4492
4493                           case 'S':
4494                           case 'T':
4495                           case 'U':
4496                             /* Various width encodings.  */
4497                             {
4498                               int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4499                               int limit;
4500                               unsigned low, high;
4501
4502                               c++;
4503                               if (*c >= '0' && *c <= '9')
4504                                 limit = *c - '0';
4505                               else if (*c >= 'a' && *c <= 'f')
4506                                 limit = *c - 'a' + 10;
4507                               else
4508                                 abort ();
4509                               low = limit >> 2;
4510                               high = limit & 3;
4511
4512                               if (value < low || value > high)
4513                                 func (stream, "<illegal width %d>", base << value);
4514                               else
4515                                 func (stream, "%d", base << value);
4516                             }
4517                             break;
4518                           case 'R':
4519                             if (given & (1 << 6))
4520                               goto Q;
4521                             /* FALLTHROUGH */
4522                           case 'D':
4523                             func (stream, "d%ld", value);
4524                             break;
4525                           case 'Q':
4526                           Q:
4527                             if (value & 1)
4528                               func (stream, "<illegal reg q%ld.5>", value >> 1);
4529                             else
4530                               func (stream, "q%ld", value >> 1);
4531                             break;
4532
4533                           case '`':
4534                             c++;
4535                             if (value == 0)
4536                               func (stream, "%c", *c);
4537                             break;
4538                           case '\'':
4539                             c++;
4540                             if (value == ((1ul << width) - 1))
4541                               func (stream, "%c", *c);
4542                             break;
4543                           case '?':
4544                             func (stream, "%c", c[(1 << width) - (int) value]);
4545                             c += 1 << width;
4546                             break;
4547                           default:
4548                             abort ();
4549                           }
4550                         break;
4551
4552                       default:
4553                         abort ();
4554                       }
4555                     }
4556                 }
4557               else
4558                 func (stream, "%c", *c);
4559             }
4560
4561           if (value_in_comment > 32 || value_in_comment < -16)
4562             func (stream, "\t; 0x%lx", value_in_comment);
4563
4564           if (is_unpredictable)
4565             func (stream, UNPREDICTABLE_INSTRUCTION);
4566
4567           return TRUE;
4568         }
4569     }
4570   return FALSE;
4571 }
4572
4573 /* Return the name of a v7A special register.  */
4574
4575 static const char *
4576 banked_regname (unsigned reg)
4577 {
4578   switch (reg)
4579     {
4580       case 15: return "CPSR";
4581       case 32: return "R8_usr";
4582       case 33: return "R9_usr";
4583       case 34: return "R10_usr";
4584       case 35: return "R11_usr";
4585       case 36: return "R12_usr";
4586       case 37: return "SP_usr";
4587       case 38: return "LR_usr";
4588       case 40: return "R8_fiq";
4589       case 41: return "R9_fiq";
4590       case 42: return "R10_fiq";
4591       case 43: return "R11_fiq";
4592       case 44: return "R12_fiq";
4593       case 45: return "SP_fiq";
4594       case 46: return "LR_fiq";
4595       case 48: return "LR_irq";
4596       case 49: return "SP_irq";
4597       case 50: return "LR_svc";
4598       case 51: return "SP_svc";
4599       case 52: return "LR_abt";
4600       case 53: return "SP_abt";
4601       case 54: return "LR_und";
4602       case 55: return "SP_und";
4603       case 60: return "LR_mon";
4604       case 61: return "SP_mon";
4605       case 62: return "ELR_hyp";
4606       case 63: return "SP_hyp";
4607       case 79: return "SPSR";
4608       case 110: return "SPSR_fiq";
4609       case 112: return "SPSR_irq";
4610       case 114: return "SPSR_svc";
4611       case 116: return "SPSR_abt";
4612       case 118: return "SPSR_und";
4613       case 124: return "SPSR_mon";
4614       case 126: return "SPSR_hyp";
4615       default: return NULL;
4616     }
4617 }
4618
4619 /* Return the name of the DMB/DSB option.  */
4620 static const char *
4621 data_barrier_option (unsigned option)
4622 {
4623   switch (option & 0xf)
4624     {
4625     case 0xf: return "sy";
4626     case 0xe: return "st";
4627     case 0xd: return "ld";
4628     case 0xb: return "ish";
4629     case 0xa: return "ishst";
4630     case 0x9: return "ishld";
4631     case 0x7: return "un";
4632     case 0x6: return "unst";
4633     case 0x5: return "nshld";
4634     case 0x3: return "osh";
4635     case 0x2: return "oshst";
4636     case 0x1: return "oshld";
4637     default:  return NULL;
4638     }
4639 }
4640
4641 /* Print one ARM instruction from PC on INFO->STREAM.  */
4642
4643 static void
4644 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
4645 {
4646   const struct opcode32 *insn;
4647   void *stream = info->stream;
4648   fprintf_ftype func = info->fprintf_func;
4649   struct arm_private_data *private_data = info->private_data;
4650
4651   if (print_insn_coprocessor (pc, info, given, FALSE))
4652     return;
4653
4654   if (print_insn_neon (info, given, FALSE))
4655     return;
4656
4657   for (insn = arm_opcodes; insn->assembler; insn++)
4658     {
4659       if ((given & insn->mask) != insn->value)
4660         continue;
4661
4662       if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
4663         continue;
4664
4665       /* Special case: an instruction with all bits set in the condition field
4666          (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4667          or by the catchall at the end of the table.  */
4668       if ((given & 0xF0000000) != 0xF0000000
4669           || (insn->mask & 0xF0000000) == 0xF0000000
4670           || (insn->mask == 0 && insn->value == 0))
4671         {
4672           unsigned long u_reg = 16;
4673           unsigned long U_reg = 16;
4674           bfd_boolean is_unpredictable = FALSE;
4675           signed long value_in_comment = 0;
4676           const char *c;
4677
4678           for (c = insn->assembler; *c; c++)
4679             {
4680               if (*c == '%')
4681                 {
4682                   bfd_boolean allow_unpredictable = FALSE;
4683
4684                   switch (*++c)
4685                     {
4686                     case '%':
4687                       func (stream, "%%");
4688                       break;
4689
4690                     case 'a':
4691                       value_in_comment = print_arm_address (pc, info, given);
4692                       break;
4693
4694                     case 'P':
4695                       /* Set P address bit and use normal address
4696                          printing routine.  */
4697                       value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
4698                       break;
4699
4700                     case 'S':
4701                       allow_unpredictable = TRUE;
4702                       /* Fall through.  */
4703                     case 's':
4704                       if ((given & 0x004f0000) == 0x004f0000)
4705                         {
4706                           /* PC relative with immediate offset.  */
4707                           bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
4708
4709                           if (PRE_BIT_SET)
4710                             {
4711                               /* Elide positive zero offset.  */
4712                               if (offset || NEGATIVE_BIT_SET)
4713                                 func (stream, "[pc, #%s%d]\t; ",
4714                                       NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4715                               else
4716                                 func (stream, "[pc]\t; ");
4717                               if (NEGATIVE_BIT_SET)
4718                                 offset = -offset;
4719                               info->print_address_func (offset + pc + 8, info);
4720                             }
4721                           else
4722                             {
4723                               /* Always show the offset.  */
4724                               func (stream, "[pc], #%s%d",
4725                                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4726                               if (! allow_unpredictable)
4727                                 is_unpredictable = TRUE;
4728                             }
4729                         }
4730                       else
4731                         {
4732                           int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4733
4734                           func (stream, "[%s",
4735                                 arm_regnames[(given >> 16) & 0xf]);
4736
4737                           if (PRE_BIT_SET)
4738                             {
4739                               if (IMMEDIATE_BIT_SET)
4740                                 {
4741                                   /* Elide offset for non-writeback
4742                                      positive zero.  */
4743                                   if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4744                                       || offset)
4745                                     func (stream, ", #%s%d",
4746                                           NEGATIVE_BIT_SET ? "-" : "", offset);
4747
4748                                   if (NEGATIVE_BIT_SET)
4749                                     offset = -offset;
4750
4751                                   value_in_comment = offset;
4752                                 }
4753                               else
4754                                 {
4755                                   /* Register Offset or Register Pre-Indexed.  */
4756                                   func (stream, ", %s%s",
4757                                         NEGATIVE_BIT_SET ? "-" : "",
4758                                         arm_regnames[given & 0xf]);
4759
4760                                   /* Writing back to the register that is the source/
4761                                      destination of the load/store is unpredictable.  */
4762                                   if (! allow_unpredictable
4763                                       && WRITEBACK_BIT_SET
4764                                       && ((given & 0xf) == ((given >> 12) & 0xf)))
4765                                     is_unpredictable = TRUE;
4766                                 }
4767
4768                               func (stream, "]%s",
4769                                     WRITEBACK_BIT_SET ? "!" : "");
4770                             }
4771                           else
4772                             {
4773                               if (IMMEDIATE_BIT_SET)
4774                                 {
4775                                   /* Immediate Post-indexed.  */
4776                                   /* PR 10924: Offset must be printed, even if it is zero.  */
4777                                   func (stream, "], #%s%d",
4778                                         NEGATIVE_BIT_SET ? "-" : "", offset);
4779                                   if (NEGATIVE_BIT_SET)
4780                                     offset = -offset;
4781                                   value_in_comment = offset;
4782                                 }
4783                               else
4784                                 {
4785                                   /* Register Post-indexed.  */
4786                                   func (stream, "], %s%s",
4787                                         NEGATIVE_BIT_SET ? "-" : "",
4788                                         arm_regnames[given & 0xf]);
4789
4790                                   /* Writing back to the register that is the source/
4791                                      destination of the load/store is unpredictable.  */
4792                                   if (! allow_unpredictable
4793                                       && (given & 0xf) == ((given >> 12) & 0xf))
4794                                     is_unpredictable = TRUE;
4795                                 }
4796
4797                               if (! allow_unpredictable)
4798                                 {
4799                                   /* Writeback is automatically implied by post- addressing.
4800                                      Setting the W bit is unnecessary and ARM specify it as
4801                                      being unpredictable.  */
4802                                   if (WRITEBACK_BIT_SET
4803                                       /* Specifying the PC register as the post-indexed
4804                                          registers is also unpredictable.  */
4805                                       || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4806                                     is_unpredictable = TRUE;
4807                                 }
4808                             }
4809                         }
4810                       break;
4811
4812                     case 'b':
4813                       {
4814                         bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
4815                         info->print_address_func (disp * 4 + pc + 8, info);
4816                       }
4817                       break;
4818
4819                     case 'c':
4820                       if (((given >> 28) & 0xf) != 0xe)
4821                         func (stream, "%s",
4822                               arm_conditional [(given >> 28) & 0xf]);
4823                       break;
4824
4825                     case 'm':
4826                       {
4827                         int started = 0;
4828                         int reg;
4829
4830                         func (stream, "{");
4831                         for (reg = 0; reg < 16; reg++)
4832                           if ((given & (1 << reg)) != 0)
4833                             {
4834                               if (started)
4835                                 func (stream, ", ");
4836                               started = 1;
4837                               func (stream, "%s", arm_regnames[reg]);
4838                             }
4839                         func (stream, "}");
4840                         if (! started)
4841                           is_unpredictable = TRUE;
4842                       }
4843                       break;
4844
4845                     case 'q':
4846                       arm_decode_shift (given, func, stream, FALSE);
4847                       break;
4848
4849                     case 'o':
4850                       if ((given & 0x02000000) != 0)
4851                         {
4852                           unsigned int rotate = (given & 0xf00) >> 7;
4853                           unsigned int immed = (given & 0xff);
4854                           unsigned int a, i;
4855
4856                           a = (((immed << (32 - rotate))
4857                                 | (immed >> rotate)) & 0xffffffff);
4858                           /* If there is another encoding with smaller rotate,
4859                              the rotate should be specified directly.  */
4860                           for (i = 0; i < 32; i += 2)
4861                             if ((a << i | a >> (32 - i)) <= 0xff)
4862                               break;
4863
4864                           if (i != rotate)
4865                             func (stream, "#%d, %d", immed, rotate);
4866                           else
4867                             func (stream, "#%d", a);
4868                           value_in_comment = a;
4869                         }
4870                       else
4871                         arm_decode_shift (given, func, stream, TRUE);
4872                       break;
4873
4874                     case 'p':
4875                       if ((given & 0x0000f000) == 0x0000f000)
4876                         {
4877                           arm_feature_set arm_ext_v6 =
4878                             ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4879
4880                           /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4881                              mechanism for setting PSR flag bits.  They are
4882                              obsolete in V6 onwards.  */
4883                           if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4884                                                      arm_ext_v6))
4885                             func (stream, "p");
4886                           else
4887                             is_unpredictable = TRUE;
4888                         }
4889                       break;
4890
4891                     case 't':
4892                       if ((given & 0x01200000) == 0x00200000)
4893                         func (stream, "t");
4894                       break;
4895
4896                     case 'A':
4897                       {
4898                         int offset = given & 0xff;
4899
4900                         value_in_comment = offset * 4;
4901                         if (NEGATIVE_BIT_SET)
4902                           value_in_comment = - value_in_comment;
4903
4904                         func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
4905
4906                         if (PRE_BIT_SET)
4907                           {
4908                             if (offset)
4909                               func (stream, ", #%d]%s",
4910                                     (int) value_in_comment,
4911                                     WRITEBACK_BIT_SET ? "!" : "");
4912                             else
4913                               func (stream, "]");
4914                           }
4915                         else
4916                           {
4917                             func (stream, "]");
4918
4919                             if (WRITEBACK_BIT_SET)
4920                               {
4921                                 if (offset)
4922                                   func (stream, ", #%d", (int) value_in_comment);
4923                               }
4924                             else
4925                               {
4926                                 func (stream, ", {%d}", (int) offset);
4927                                 value_in_comment = offset;
4928                               }
4929                           }
4930                       }
4931                       break;
4932
4933                     case 'B':
4934                       /* Print ARM V5 BLX(1) address: pc+25 bits.  */
4935                       {
4936                         bfd_vma address;
4937                         bfd_vma offset = 0;
4938
4939                         if (! NEGATIVE_BIT_SET)
4940                           /* Is signed, hi bits should be ones.  */
4941                           offset = (-1) ^ 0x00ffffff;
4942
4943                         /* Offset is (SignExtend(offset field)<<2).  */
4944                         offset += given & 0x00ffffff;
4945                         offset <<= 2;
4946                         address = offset + pc + 8;
4947
4948                         if (given & 0x01000000)
4949                           /* H bit allows addressing to 2-byte boundaries.  */
4950                           address += 2;
4951
4952                         info->print_address_func (address, info);
4953                       }
4954                       break;
4955
4956                     case 'C':
4957                       if ((given & 0x02000200) == 0x200)
4958                         {
4959                           const char * name;
4960                           unsigned sysm = (given & 0x004f0000) >> 16;
4961
4962                           sysm |= (given & 0x300) >> 4;
4963                           name = banked_regname (sysm);
4964
4965                           if (name != NULL)
4966                             func (stream, "%s", name);
4967                           else
4968                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
4969                         }
4970                       else
4971                         {
4972                           func (stream, "%cPSR_",
4973                                 (given & 0x00400000) ? 'S' : 'C');
4974                           if (given & 0x80000)
4975                             func (stream, "f");
4976                           if (given & 0x40000)
4977                             func (stream, "s");
4978                           if (given & 0x20000)
4979                             func (stream, "x");
4980                           if (given & 0x10000)
4981                             func (stream, "c");
4982                         }
4983                       break;
4984
4985                     case 'U':
4986                       if ((given & 0xf0) == 0x60)
4987                         {
4988                           switch (given & 0xf)
4989                             {
4990                             case 0xf: func (stream, "sy"); break;
4991                             default:
4992                               func (stream, "#%d", (int) given & 0xf);
4993                               break;
4994                             }
4995                         }
4996                       else
4997                         {
4998                           const char * opt = data_barrier_option (given & 0xf);
4999                           if (opt != NULL)
5000                             func (stream, "%s", opt);
5001                           else
5002                               func (stream, "#%d", (int) given & 0xf);
5003                         }
5004                       break;
5005
5006                     case '0': case '1': case '2': case '3': case '4':
5007                     case '5': case '6': case '7': case '8': case '9':
5008                       {
5009                         int width;
5010                         unsigned long value;
5011
5012                         c = arm_decode_bitfield (c, given, &value, &width);
5013
5014                         switch (*c)
5015                           {
5016                           case 'R':
5017                             if (value == 15)
5018                               is_unpredictable = TRUE;
5019                             /* Fall through.  */
5020                           case 'r':
5021                           case 'T':
5022                             /* We want register + 1 when decoding T.  */
5023                             if (*c == 'T')
5024                               ++value;
5025
5026                             if (c[1] == 'u')
5027                               {
5028                                 /* Eat the 'u' character.  */
5029                                 ++ c;
5030
5031                                 if (u_reg == value)
5032                                   is_unpredictable = TRUE;
5033                                 u_reg = value;
5034                               }
5035                             if (c[1] == 'U')
5036                               {
5037                                 /* Eat the 'U' character.  */
5038                                 ++ c;
5039
5040                                 if (U_reg == value)
5041                                   is_unpredictable = TRUE;
5042                                 U_reg = value;
5043                               }
5044                             func (stream, "%s", arm_regnames[value]);
5045                             break;
5046                           case 'd':
5047                             func (stream, "%ld", value);
5048                             value_in_comment = value;
5049                             break;
5050                           case 'b':
5051                             func (stream, "%ld", value * 8);
5052                             value_in_comment = value * 8;
5053                             break;
5054                           case 'W':
5055                             func (stream, "%ld", value + 1);
5056                             value_in_comment = value + 1;
5057                             break;
5058                           case 'x':
5059                             func (stream, "0x%08lx", value);
5060
5061                             /* Some SWI instructions have special
5062                                meanings.  */
5063                             if ((given & 0x0fffffff) == 0x0FF00000)
5064                               func (stream, "\t; IMB");
5065                             else if ((given & 0x0fffffff) == 0x0FF00001)
5066                               func (stream, "\t; IMBRange");
5067                             break;
5068                           case 'X':
5069                             func (stream, "%01lx", value & 0xf);
5070                             value_in_comment = value;
5071                             break;
5072                           case '`':
5073                             c++;
5074                             if (value == 0)
5075                               func (stream, "%c", *c);
5076                             break;
5077                           case '\'':
5078                             c++;
5079                             if (value == ((1ul << width) - 1))
5080                               func (stream, "%c", *c);
5081                             break;
5082                           case '?':
5083                             func (stream, "%c", c[(1 << width) - (int) value]);
5084                             c += 1 << width;
5085                             break;
5086                           default:
5087                             abort ();
5088                           }
5089                         break;
5090
5091                       case 'e':
5092                         {
5093                           int imm;
5094
5095                           imm = (given & 0xf) | ((given & 0xfff00) >> 4);
5096                           func (stream, "%d", imm);
5097                           value_in_comment = imm;
5098                         }
5099                         break;
5100
5101                       case 'E':
5102                         /* LSB and WIDTH fields of BFI or BFC.  The machine-
5103                            language instruction encodes LSB and MSB.  */
5104                         {
5105                           long msb = (given & 0x001f0000) >> 16;
5106                           long lsb = (given & 0x00000f80) >> 7;
5107                           long w = msb - lsb + 1;
5108
5109                           if (w > 0)
5110                             func (stream, "#%lu, #%lu", lsb, w);
5111                           else
5112                             func (stream, "(invalid: %lu:%lu)", lsb, msb);
5113                         }
5114                         break;
5115
5116                       case 'R':
5117                         /* Get the PSR/banked register name.  */
5118                         {
5119                           const char * name;
5120                           unsigned sysm = (given & 0x004f0000) >> 16;
5121
5122                           sysm |= (given & 0x300) >> 4;
5123                           name = banked_regname (sysm);
5124
5125                           if (name != NULL)
5126                             func (stream, "%s", name);
5127                           else
5128                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5129                         }
5130                         break;
5131
5132                       case 'V':
5133                         /* 16-bit unsigned immediate from a MOVT or MOVW
5134                            instruction, encoded in bits 0:11 and 15:19.  */
5135                         {
5136                           long hi = (given & 0x000f0000) >> 4;
5137                           long lo = (given & 0x00000fff);
5138                           long imm16 = hi | lo;
5139
5140                           func (stream, "#%lu", imm16);
5141                           value_in_comment = imm16;
5142                         }
5143                         break;
5144
5145                       default:
5146                         abort ();
5147                       }
5148                     }
5149                 }
5150               else
5151                 func (stream, "%c", *c);
5152             }
5153
5154           if (value_in_comment > 32 || value_in_comment < -16)
5155             func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
5156
5157           if (is_unpredictable)
5158             func (stream, UNPREDICTABLE_INSTRUCTION);
5159
5160           return;
5161         }
5162     }
5163   abort ();
5164 }
5165
5166 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM.  */
5167
5168 static void
5169 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
5170 {
5171   const struct opcode16 *insn;
5172   void *stream = info->stream;
5173   fprintf_ftype func = info->fprintf_func;
5174
5175   for (insn = thumb_opcodes; insn->assembler; insn++)
5176     if ((given & insn->mask) == insn->value)
5177       {
5178         signed long value_in_comment = 0;
5179         const char *c = insn->assembler;
5180
5181         for (; *c; c++)
5182           {
5183             int domaskpc = 0;
5184             int domasklr = 0;
5185
5186             if (*c != '%')
5187               {
5188                 func (stream, "%c", *c);
5189                 continue;
5190               }
5191
5192             switch (*++c)
5193               {
5194               case '%':
5195                 func (stream, "%%");
5196                 break;
5197
5198               case 'c':
5199                 if (ifthen_state)
5200                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
5201                 break;
5202
5203               case 'C':
5204                 if (ifthen_state)
5205                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
5206                 else
5207                   func (stream, "s");
5208                 break;
5209
5210               case 'I':
5211                 {
5212                   unsigned int tmp;
5213
5214                   ifthen_next_state = given & 0xff;
5215                   for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
5216                     func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5217                   func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
5218                 }
5219                 break;
5220
5221               case 'x':
5222                 if (ifthen_next_state)
5223                   func (stream, "\t; unpredictable branch in IT block\n");
5224                 break;
5225
5226               case 'X':
5227                 if (ifthen_state)
5228                   func (stream, "\t; unpredictable <IT:%s>",
5229                         arm_conditional[IFTHEN_COND]);
5230                 break;
5231
5232               case 'S':
5233                 {
5234                   long reg;
5235
5236                   reg = (given >> 3) & 0x7;
5237                   if (given & (1 << 6))
5238                     reg += 8;
5239
5240                   func (stream, "%s", arm_regnames[reg]);
5241                 }
5242                 break;
5243
5244               case 'D':
5245                 {
5246                   long reg;
5247
5248                   reg = given & 0x7;
5249                   if (given & (1 << 7))
5250                     reg += 8;
5251
5252                   func (stream, "%s", arm_regnames[reg]);
5253                 }
5254                 break;
5255
5256               case 'N':
5257                 if (given & (1 << 8))
5258                   domasklr = 1;
5259                 /* Fall through.  */
5260               case 'O':
5261                 if (*c == 'O' && (given & (1 << 8)))
5262                   domaskpc = 1;
5263                 /* Fall through.  */
5264               case 'M':
5265                 {
5266                   int started = 0;
5267                   int reg;
5268
5269                   func (stream, "{");
5270
5271                   /* It would be nice if we could spot
5272                      ranges, and generate the rS-rE format: */
5273                   for (reg = 0; (reg < 8); reg++)
5274                     if ((given & (1 << reg)) != 0)
5275                       {
5276                         if (started)
5277                           func (stream, ", ");
5278                         started = 1;
5279                         func (stream, "%s", arm_regnames[reg]);
5280                       }
5281
5282                   if (domasklr)
5283                     {
5284                       if (started)
5285                         func (stream, ", ");
5286                       started = 1;
5287                       func (stream, "%s", arm_regnames[14] /* "lr" */);
5288                     }
5289
5290                   if (domaskpc)
5291                     {
5292                       if (started)
5293                         func (stream, ", ");
5294                       func (stream, "%s", arm_regnames[15] /* "pc" */);
5295                     }
5296
5297                   func (stream, "}");
5298                 }
5299                 break;
5300
5301               case 'W':
5302                 /* Print writeback indicator for a LDMIA.  We are doing a
5303                    writeback if the base register is not in the register
5304                    mask.  */
5305                 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5306                   func (stream, "!");
5307                 break;
5308
5309               case 'b':
5310                 /* Print ARM V6T2 CZB address: pc+4+6 bits.  */
5311                 {
5312                   bfd_vma address = (pc + 4
5313                                      + ((given & 0x00f8) >> 2)
5314                                      + ((given & 0x0200) >> 3));
5315                   info->print_address_func (address, info);
5316                 }
5317                 break;
5318
5319               case 's':
5320                 /* Right shift immediate -- bits 6..10; 1-31 print
5321                    as themselves, 0 prints as 32.  */
5322                 {
5323                   long imm = (given & 0x07c0) >> 6;
5324                   if (imm == 0)
5325                     imm = 32;
5326                   func (stream, "#%ld", imm);
5327                 }
5328                 break;
5329
5330               case '0': case '1': case '2': case '3': case '4':
5331               case '5': case '6': case '7': case '8': case '9':
5332                 {
5333                   int bitstart = *c++ - '0';
5334                   int bitend = 0;
5335
5336                   while (*c >= '0' && *c <= '9')
5337                     bitstart = (bitstart * 10) + *c++ - '0';
5338
5339                   switch (*c)
5340                     {
5341                     case '-':
5342                       {
5343                         bfd_vma reg;
5344
5345                         c++;
5346                         while (*c >= '0' && *c <= '9')
5347                           bitend = (bitend * 10) + *c++ - '0';
5348                         if (!bitend)
5349                           abort ();
5350                         reg = given >> bitstart;
5351                         reg &= (2 << (bitend - bitstart)) - 1;
5352
5353                         switch (*c)
5354                           {
5355                           case 'r':
5356                             func (stream, "%s", arm_regnames[reg]);
5357                             break;
5358
5359                           case 'd':
5360                             func (stream, "%ld", (long) reg);
5361                             value_in_comment = reg;
5362                             break;
5363
5364                           case 'H':
5365                             func (stream, "%ld", (long) (reg << 1));
5366                             value_in_comment = reg << 1;
5367                             break;
5368
5369                           case 'W':
5370                             func (stream, "%ld", (long) (reg << 2));
5371                             value_in_comment = reg << 2;
5372                             break;
5373
5374                           case 'a':
5375                             /* PC-relative address -- the bottom two
5376                                bits of the address are dropped
5377                                before the calculation.  */
5378                             info->print_address_func
5379                               (((pc + 4) & ~3) + (reg << 2), info);
5380                             value_in_comment = 0;
5381                             break;
5382
5383                           case 'x':
5384                             func (stream, "0x%04lx", (long) reg);
5385                             break;
5386
5387                           case 'B':
5388                             reg = ((reg ^ (1 << bitend)) - (1 << bitend));
5389                             info->print_address_func (reg * 2 + pc + 4, info);
5390                             value_in_comment = 0;
5391                             break;
5392
5393                           case 'c':
5394                             func (stream, "%s", arm_conditional [reg]);
5395                             break;
5396
5397                           default:
5398                             abort ();
5399                           }
5400                       }
5401                       break;
5402
5403                     case '\'':
5404                       c++;
5405                       if ((given & (1 << bitstart)) != 0)
5406                         func (stream, "%c", *c);
5407                       break;
5408
5409                     case '?':
5410                       ++c;
5411                       if ((given & (1 << bitstart)) != 0)
5412                         func (stream, "%c", *c++);
5413                       else
5414                         func (stream, "%c", *++c);
5415                       break;
5416
5417                     default:
5418                       abort ();
5419                     }
5420                 }
5421                 break;
5422
5423               default:
5424                 abort ();
5425               }
5426           }
5427
5428         if (value_in_comment > 32 || value_in_comment < -16)
5429           func (stream, "\t; 0x%lx", value_in_comment);
5430         return;
5431       }
5432
5433   /* No match.  */
5434   abort ();
5435 }
5436
5437 /* Return the name of an V7M special register.  */
5438
5439 static const char *
5440 psr_name (int regno)
5441 {
5442   switch (regno)
5443     {
5444     case 0x0: return "APSR";
5445     case 0x1: return "IAPSR";
5446     case 0x2: return "EAPSR";
5447     case 0x3: return "PSR";
5448     case 0x5: return "IPSR";
5449     case 0x6: return "EPSR";
5450     case 0x7: return "IEPSR";
5451     case 0x8: return "MSP";
5452     case 0x9: return "PSP";
5453     case 0xa: return "MSPLIM";
5454     case 0xb: return "PSPLIM";
5455     case 0x10: return "PRIMASK";
5456     case 0x11: return "BASEPRI";
5457     case 0x12: return "BASEPRI_MAX";
5458     case 0x13: return "FAULTMASK";
5459     case 0x14: return "CONTROL";
5460     case 0x88: return "MSP_NS";
5461     case 0x89: return "PSP_NS";
5462     case 0x8a: return "MSPLIM_NS";
5463     case 0x8b: return "PSPLIM_NS";
5464     case 0x90: return "PRIMASK_NS";
5465     case 0x91: return "BASEPRI_NS";
5466     case 0x93: return "FAULTMASK_NS";
5467     case 0x94: return "CONTROL_NS";
5468     case 0x98: return "SP_NS";
5469     default: return "<unknown>";
5470     }
5471 }
5472
5473 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM.  */
5474
5475 static void
5476 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
5477 {
5478   const struct opcode32 *insn;
5479   void *stream = info->stream;
5480   fprintf_ftype func = info->fprintf_func;
5481
5482   if (print_insn_coprocessor (pc, info, given, TRUE))
5483     return;
5484
5485   if (print_insn_neon (info, given, TRUE))
5486     return;
5487
5488   for (insn = thumb32_opcodes; insn->assembler; insn++)
5489     if ((given & insn->mask) == insn->value)
5490       {
5491         bfd_boolean is_unpredictable = FALSE;
5492         signed long value_in_comment = 0;
5493         const char *c = insn->assembler;
5494
5495         for (; *c; c++)
5496           {
5497             if (*c != '%')
5498               {
5499                 func (stream, "%c", *c);
5500                 continue;
5501               }
5502
5503             switch (*++c)
5504               {
5505               case '%':
5506                 func (stream, "%%");
5507                 break;
5508
5509               case 'c':
5510                 if (ifthen_state)
5511                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
5512                 break;
5513
5514               case 'x':
5515                 if (ifthen_next_state)
5516                   func (stream, "\t; unpredictable branch in IT block\n");
5517                 break;
5518
5519               case 'X':
5520                 if (ifthen_state)
5521                   func (stream, "\t; unpredictable <IT:%s>",
5522                         arm_conditional[IFTHEN_COND]);
5523                 break;
5524
5525               case 'I':
5526                 {
5527                   unsigned int imm12 = 0;
5528
5529                   imm12 |= (given & 0x000000ffu);
5530                   imm12 |= (given & 0x00007000u) >> 4;
5531                   imm12 |= (given & 0x04000000u) >> 15;
5532                   func (stream, "#%u", imm12);
5533                   value_in_comment = imm12;
5534                 }
5535                 break;
5536
5537               case 'M':
5538                 {
5539                   unsigned int bits = 0, imm, imm8, mod;
5540
5541                   bits |= (given & 0x000000ffu);
5542                   bits |= (given & 0x00007000u) >> 4;
5543                   bits |= (given & 0x04000000u) >> 15;
5544                   imm8 = (bits & 0x0ff);
5545                   mod = (bits & 0xf00) >> 8;
5546                   switch (mod)
5547                     {
5548                     case 0: imm = imm8; break;
5549                     case 1: imm = ((imm8 << 16) | imm8); break;
5550                     case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5551                     case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
5552                     default:
5553                       mod  = (bits & 0xf80) >> 7;
5554                       imm8 = (bits & 0x07f) | 0x80;
5555                       imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5556                     }
5557                   func (stream, "#%u", imm);
5558                   value_in_comment = imm;
5559                 }
5560                 break;
5561
5562               case 'J':
5563                 {
5564                   unsigned int imm = 0;
5565
5566                   imm |= (given & 0x000000ffu);
5567                   imm |= (given & 0x00007000u) >> 4;
5568                   imm |= (given & 0x04000000u) >> 15;
5569                   imm |= (given & 0x000f0000u) >> 4;
5570                   func (stream, "#%u", imm);
5571                   value_in_comment = imm;
5572                 }
5573                 break;
5574
5575               case 'K':
5576                 {
5577                   unsigned int imm = 0;
5578
5579                   imm |= (given & 0x000f0000u) >> 16;
5580                   imm |= (given & 0x00000ff0u) >> 0;
5581                   imm |= (given & 0x0000000fu) << 12;
5582                   func (stream, "#%u", imm);
5583                   value_in_comment = imm;
5584                 }
5585                 break;
5586
5587               case 'H':
5588                 {
5589                   unsigned int imm = 0;
5590
5591                   imm |= (given & 0x000f0000u) >> 4;
5592                   imm |= (given & 0x00000fffu) >> 0;
5593                   func (stream, "#%u", imm);
5594                   value_in_comment = imm;
5595                 }
5596                 break;
5597
5598               case 'V':
5599                 {
5600                   unsigned int imm = 0;
5601
5602                   imm |= (given & 0x00000fffu);
5603                   imm |= (given & 0x000f0000u) >> 4;
5604                   func (stream, "#%u", imm);
5605                   value_in_comment = imm;
5606                 }
5607                 break;
5608
5609               case 'S':
5610                 {
5611                   unsigned int reg = (given & 0x0000000fu);
5612                   unsigned int stp = (given & 0x00000030u) >> 4;
5613                   unsigned int imm = 0;
5614                   imm |= (given & 0x000000c0u) >> 6;
5615                   imm |= (given & 0x00007000u) >> 10;
5616
5617                   func (stream, "%s", arm_regnames[reg]);
5618                   switch (stp)
5619                     {
5620                     case 0:
5621                       if (imm > 0)
5622                         func (stream, ", lsl #%u", imm);
5623                       break;
5624
5625                     case 1:
5626                       if (imm == 0)
5627                         imm = 32;
5628                       func (stream, ", lsr #%u", imm);
5629                       break;
5630
5631                     case 2:
5632                       if (imm == 0)
5633                         imm = 32;
5634                       func (stream, ", asr #%u", imm);
5635                       break;
5636
5637                     case 3:
5638                       if (imm == 0)
5639                         func (stream, ", rrx");
5640                       else
5641                         func (stream, ", ror #%u", imm);
5642                     }
5643                 }
5644                 break;
5645
5646               case 'a':
5647                 {
5648                   unsigned int Rn  = (given & 0x000f0000) >> 16;
5649                   unsigned int U   = ! NEGATIVE_BIT_SET;
5650                   unsigned int op  = (given & 0x00000f00) >> 8;
5651                   unsigned int i12 = (given & 0x00000fff);
5652                   unsigned int i8  = (given & 0x000000ff);
5653                   bfd_boolean writeback = FALSE, postind = FALSE;
5654                   bfd_vma offset = 0;
5655
5656                   func (stream, "[%s", arm_regnames[Rn]);
5657                   if (U) /* 12-bit positive immediate offset.  */
5658                     {
5659                       offset = i12;
5660                       if (Rn != 15)
5661                         value_in_comment = offset;
5662                     }
5663                   else if (Rn == 15) /* 12-bit negative immediate offset.  */
5664                     offset = - (int) i12;
5665                   else if (op == 0x0) /* Shifted register offset.  */
5666                     {
5667                       unsigned int Rm = (i8 & 0x0f);
5668                       unsigned int sh = (i8 & 0x30) >> 4;
5669
5670                       func (stream, ", %s", arm_regnames[Rm]);
5671                       if (sh)
5672                         func (stream, ", lsl #%u", sh);
5673                       func (stream, "]");
5674                       break;
5675                     }
5676                   else switch (op)
5677                     {
5678                     case 0xE:  /* 8-bit positive immediate offset.  */
5679                       offset = i8;
5680                       break;
5681
5682                     case 0xC:  /* 8-bit negative immediate offset.  */
5683                       offset = -i8;
5684                       break;
5685
5686                     case 0xF:  /* 8-bit + preindex with wb.  */
5687                       offset = i8;
5688                       writeback = TRUE;
5689                       break;
5690
5691                     case 0xD:  /* 8-bit - preindex with wb.  */
5692                       offset = -i8;
5693                       writeback = TRUE;
5694                       break;
5695
5696                     case 0xB:  /* 8-bit + postindex.  */
5697                       offset = i8;
5698                       postind = TRUE;
5699                       break;
5700
5701                     case 0x9:  /* 8-bit - postindex.  */
5702                       offset = -i8;
5703                       postind = TRUE;
5704                       break;
5705
5706                     default:
5707                       func (stream, ", <undefined>]");
5708                       goto skip;
5709                     }
5710
5711                   if (postind)
5712                     func (stream, "], #%d", (int) offset);
5713                   else
5714                     {
5715                       if (offset)
5716                         func (stream, ", #%d", (int) offset);
5717                       func (stream, writeback ? "]!" : "]");
5718                     }
5719
5720                   if (Rn == 15)
5721                     {
5722                       func (stream, "\t; ");
5723                       info->print_address_func (((pc + 4) & ~3) + offset, info);
5724                     }
5725                 }
5726               skip:
5727                 break;
5728
5729               case 'A':
5730                 {
5731                   unsigned int U   = ! NEGATIVE_BIT_SET;
5732                   unsigned int W   = WRITEBACK_BIT_SET;
5733                   unsigned int Rn  = (given & 0x000f0000) >> 16;
5734                   unsigned int off = (given & 0x000000ff);
5735
5736                   func (stream, "[%s", arm_regnames[Rn]);
5737
5738                   if (PRE_BIT_SET)
5739                     {
5740                       if (off || !U)
5741                         {
5742                           func (stream, ", #%c%u", U ? '+' : '-', off * 4);
5743                           value_in_comment = off * 4 * (U ? 1 : -1);
5744                         }
5745                       func (stream, "]");
5746                       if (W)
5747                         func (stream, "!");
5748                     }
5749                   else
5750                     {
5751                       func (stream, "], ");
5752                       if (W)
5753                         {
5754                           func (stream, "#%c%u", U ? '+' : '-', off * 4);
5755                           value_in_comment = off * 4 * (U ? 1 : -1);
5756                         }
5757                       else
5758                         {
5759                           func (stream, "{%u}", off);
5760                           value_in_comment = off;
5761                         }
5762                     }
5763                 }
5764                 break;
5765
5766               case 'w':
5767                 {
5768                   unsigned int Sbit = (given & 0x01000000) >> 24;
5769                   unsigned int type = (given & 0x00600000) >> 21;
5770
5771                   switch (type)
5772                     {
5773                     case 0: func (stream, Sbit ? "sb" : "b"); break;
5774                     case 1: func (stream, Sbit ? "sh" : "h"); break;
5775                     case 2:
5776                       if (Sbit)
5777                         func (stream, "??");
5778                       break;
5779                     case 3:
5780                       func (stream, "??");
5781                       break;
5782                     }
5783                 }
5784                 break;
5785
5786               case 'm':
5787                 {
5788                   int started = 0;
5789                   int reg;
5790
5791                   func (stream, "{");
5792                   for (reg = 0; reg < 16; reg++)
5793                     if ((given & (1 << reg)) != 0)
5794                       {
5795                         if (started)
5796                           func (stream, ", ");
5797                         started = 1;
5798                         func (stream, "%s", arm_regnames[reg]);
5799                       }
5800                   func (stream, "}");
5801                 }
5802                 break;
5803
5804               case 'E':
5805                 {
5806                   unsigned int msb = (given & 0x0000001f);
5807                   unsigned int lsb = 0;
5808
5809                   lsb |= (given & 0x000000c0u) >> 6;
5810                   lsb |= (given & 0x00007000u) >> 10;
5811                   func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5812                 }
5813                 break;
5814
5815               case 'F':
5816                 {
5817                   unsigned int width = (given & 0x0000001f) + 1;
5818                   unsigned int lsb = 0;
5819
5820                   lsb |= (given & 0x000000c0u) >> 6;
5821                   lsb |= (given & 0x00007000u) >> 10;
5822                   func (stream, "#%u, #%u", lsb, width);
5823                 }
5824                 break;
5825
5826               case 'b':
5827                 {
5828                   unsigned int S = (given & 0x04000000u) >> 26;
5829                   unsigned int J1 = (given & 0x00002000u) >> 13;
5830                   unsigned int J2 = (given & 0x00000800u) >> 11;
5831                   bfd_vma offset = 0;
5832
5833                   offset |= !S << 20;
5834                   offset |= J2 << 19;
5835                   offset |= J1 << 18;
5836                   offset |= (given & 0x003f0000) >> 4;
5837                   offset |= (given & 0x000007ff) << 1;
5838                   offset -= (1 << 20);
5839
5840                   info->print_address_func (pc + 4 + offset, info);
5841                 }
5842                 break;
5843
5844               case 'B':
5845                 {
5846                   unsigned int S = (given & 0x04000000u) >> 26;
5847                   unsigned int I1 = (given & 0x00002000u) >> 13;
5848                   unsigned int I2 = (given & 0x00000800u) >> 11;
5849                   bfd_vma offset = 0;
5850
5851                   offset |= !S << 24;
5852                   offset |= !(I1 ^ S) << 23;
5853                   offset |= !(I2 ^ S) << 22;
5854                   offset |= (given & 0x03ff0000u) >> 4;
5855                   offset |= (given & 0x000007ffu) << 1;
5856                   offset -= (1 << 24);
5857                   offset += pc + 4;
5858
5859                   /* BLX target addresses are always word aligned.  */
5860                   if ((given & 0x00001000u) == 0)
5861                       offset &= ~2u;
5862
5863                   info->print_address_func (offset, info);
5864                 }
5865                 break;
5866
5867               case 's':
5868                 {
5869                   unsigned int shift = 0;
5870
5871                   shift |= (given & 0x000000c0u) >> 6;
5872                   shift |= (given & 0x00007000u) >> 10;
5873                   if (WRITEBACK_BIT_SET)
5874                     func (stream, ", asr #%u", shift);
5875                   else if (shift)
5876                     func (stream, ", lsl #%u", shift);
5877                   /* else print nothing - lsl #0 */
5878                 }
5879                 break;
5880
5881               case 'R':
5882                 {
5883                   unsigned int rot = (given & 0x00000030) >> 4;
5884
5885                   if (rot)
5886                     func (stream, ", ror #%u", rot * 8);
5887                 }
5888                 break;
5889
5890               case 'U':
5891                 if ((given & 0xf0) == 0x60)
5892                   {
5893                     switch (given & 0xf)
5894                       {
5895                         case 0xf: func (stream, "sy"); break;
5896                         default:
5897                           func (stream, "#%d", (int) given & 0xf);
5898                               break;
5899                       }
5900                   }
5901                 else
5902                   {
5903                     const char * opt = data_barrier_option (given & 0xf);
5904                     if (opt != NULL)
5905                       func (stream, "%s", opt);
5906                     else
5907                       func (stream, "#%d", (int) given & 0xf);
5908                    }
5909                 break;
5910
5911               case 'C':
5912                 if ((given & 0xff) == 0)
5913                   {
5914                     func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5915                     if (given & 0x800)
5916                       func (stream, "f");
5917                     if (given & 0x400)
5918                       func (stream, "s");
5919                     if (given & 0x200)
5920                       func (stream, "x");
5921                     if (given & 0x100)
5922                       func (stream, "c");
5923                   }
5924                 else if ((given & 0x20) == 0x20)
5925                   {
5926                     char const* name;
5927                     unsigned sysm = (given & 0xf00) >> 8;
5928
5929                     sysm |= (given & 0x30);
5930                     sysm |= (given & 0x00100000) >> 14;
5931                     name = banked_regname (sysm);
5932
5933                     if (name != NULL)
5934                       func (stream, "%s", name);
5935                     else
5936                       func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5937                   }
5938                 else
5939                   {
5940                     func (stream, "%s", psr_name (given & 0xff));
5941                   }
5942                 break;
5943
5944               case 'D':
5945                 if (((given & 0xff) == 0)
5946                     || ((given & 0x20) == 0x20))
5947                   {
5948                     char const* name;
5949                     unsigned sm = (given & 0xf0000) >> 16;
5950
5951                     sm |= (given & 0x30);
5952                     sm |= (given & 0x00100000) >> 14;
5953                     name = banked_regname (sm);
5954
5955                     if (name != NULL)
5956                       func (stream, "%s", name);
5957                     else
5958                       func (stream, "(UNDEF: %lu)", (unsigned long) sm);
5959                   }
5960                 else
5961                   func (stream, "%s", psr_name (given & 0xff));
5962                 break;
5963
5964               case '0': case '1': case '2': case '3': case '4':
5965               case '5': case '6': case '7': case '8': case '9':
5966                 {
5967                   int width;
5968                   unsigned long val;
5969
5970                   c = arm_decode_bitfield (c, given, &val, &width);
5971
5972                   switch (*c)
5973                     {
5974                     case 'd':
5975                       func (stream, "%lu", val);
5976                       value_in_comment = val;
5977                       break;
5978
5979                     case 'D':
5980                       func (stream, "%lu", val + 1);
5981                       value_in_comment = val + 1;
5982                       break;
5983
5984                     case 'W':
5985                       func (stream, "%lu", val * 4);
5986                       value_in_comment = val * 4;
5987                       break;
5988
5989                     case 'R':
5990                       if (val == 15)
5991                         is_unpredictable = TRUE;
5992                       /* Fall through.  */
5993                     case 'r':
5994                       func (stream, "%s", arm_regnames[val]);
5995                       break;
5996
5997                     case 'c':
5998                       func (stream, "%s", arm_conditional[val]);
5999                       break;
6000
6001                     case '\'':
6002                       c++;
6003                       if (val == ((1ul << width) - 1))
6004                         func (stream, "%c", *c);
6005                       break;
6006
6007                     case '`':
6008                       c++;
6009                       if (val == 0)
6010                         func (stream, "%c", *c);
6011                       break;
6012
6013                     case '?':
6014                       func (stream, "%c", c[(1 << width) - (int) val]);
6015                       c += 1 << width;
6016                       break;
6017
6018                     case 'x':
6019                       func (stream, "0x%lx", val & 0xffffffffUL);
6020                       break;
6021
6022                     default:
6023                       abort ();
6024                     }
6025                 }
6026                 break;
6027
6028               case 'L':
6029                 /* PR binutils/12534
6030                    If we have a PC relative offset in an LDRD or STRD
6031                    instructions then display the decoded address.  */
6032                 if (((given >> 16) & 0xf) == 0xf)
6033                   {
6034                     bfd_vma offset = (given & 0xff) * 4;
6035
6036                     if ((given & (1 << 23)) == 0)
6037                       offset = - offset;
6038                     func (stream, "\t; ");
6039                     info->print_address_func ((pc & ~3) + 4 + offset, info);
6040                   }
6041                 break;
6042
6043               default:
6044                 abort ();
6045               }
6046           }
6047
6048         if (value_in_comment > 32 || value_in_comment < -16)
6049           func (stream, "\t; 0x%lx", value_in_comment);
6050
6051         if (is_unpredictable)
6052           func (stream, UNPREDICTABLE_INSTRUCTION);
6053
6054         return;
6055       }
6056
6057   /* No match.  */
6058   abort ();
6059 }
6060
6061 /* Print data bytes on INFO->STREAM.  */
6062
6063 static void
6064 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
6065                  struct disassemble_info *info,
6066                  long given)
6067 {
6068   switch (info->bytes_per_chunk)
6069     {
6070     case 1:
6071       info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
6072       break;
6073     case 2:
6074       info->fprintf_func (info->stream, ".short\t0x%04lx", given);
6075       break;
6076     case 4:
6077       info->fprintf_func (info->stream, ".word\t0x%08lx", given);
6078       break;
6079     default:
6080       abort ();
6081     }
6082 }
6083
6084 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
6085    being displayed in symbol relative addresses.
6086
6087    Also disallow private symbol, with __tagsym$$ prefix,
6088    from ARM RVCT toolchain being displayed.  */
6089
6090 bfd_boolean
6091 arm_symbol_is_valid (asymbol * sym,
6092                      struct disassemble_info * info ATTRIBUTE_UNUSED)
6093 {
6094   const char * name;
6095
6096   if (sym == NULL)
6097     return FALSE;
6098
6099   name = bfd_asymbol_name (sym);
6100
6101   return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
6102 }
6103
6104 /* Parse the string of disassembler options.  */
6105
6106 static void
6107 parse_arm_disassembler_options (const char *options)
6108 {
6109   const char *opt;
6110
6111   FOR_EACH_DISASSEMBLER_OPTION (opt, options)
6112     {
6113       if (CONST_STRNEQ (opt, "reg-names-"))
6114         {
6115           unsigned int i;
6116           for (i = 0; i < NUM_ARM_OPTIONS; i++)
6117             if (disassembler_options_cmp (opt, regnames[i].name) == 0)
6118               {
6119                 regname_selected = i;
6120                 break;
6121               }
6122
6123           if (i >= NUM_ARM_OPTIONS)
6124             fprintf (stderr, _("Unrecognised register name set: %s\n"), opt);
6125         }
6126       else if (CONST_STRNEQ (opt, "force-thumb"))
6127         force_thumb = 1;
6128       else if (CONST_STRNEQ (opt, "no-force-thumb"))
6129         force_thumb = 0;
6130       else
6131         fprintf (stderr, _("Unrecognised disassembler option: %s\n"), opt);
6132     }
6133
6134   return;
6135 }
6136
6137 static bfd_boolean
6138 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6139                          enum map_type *map_symbol);
6140
6141 /* Search back through the insn stream to determine if this instruction is
6142    conditionally executed.  */
6143
6144 static void
6145 find_ifthen_state (bfd_vma pc,
6146                    struct disassemble_info *info,
6147                    bfd_boolean little)
6148 {
6149   unsigned char b[2];
6150   unsigned int insn;
6151   int status;
6152   /* COUNT is twice the number of instructions seen.  It will be odd if we
6153      just crossed an instruction boundary.  */
6154   int count;
6155   int it_count;
6156   unsigned int seen_it;
6157   bfd_vma addr;
6158
6159   ifthen_address = pc;
6160   ifthen_state = 0;
6161
6162   addr = pc;
6163   count = 1;
6164   it_count = 0;
6165   seen_it = 0;
6166   /* Scan backwards looking for IT instructions, keeping track of where
6167      instruction boundaries are.  We don't know if something is actually an
6168      IT instruction until we find a definite instruction boundary.  */
6169   for (;;)
6170     {
6171       if (addr == 0 || info->symbol_at_address_func (addr, info))
6172         {
6173           /* A symbol must be on an instruction boundary, and will not
6174              be within an IT block.  */
6175           if (seen_it && (count & 1))
6176             break;
6177
6178           return;
6179         }
6180       addr -= 2;
6181       status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
6182       if (status)
6183         return;
6184
6185       if (little)
6186         insn = (b[0]) | (b[1] << 8);
6187       else
6188         insn = (b[1]) | (b[0] << 8);
6189       if (seen_it)
6190         {
6191           if ((insn & 0xf800) < 0xe800)
6192             {
6193               /* Addr + 2 is an instruction boundary.  See if this matches
6194                  the expected boundary based on the position of the last
6195                  IT candidate.  */
6196               if (count & 1)
6197                 break;
6198               seen_it = 0;
6199             }
6200         }
6201       if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6202         {
6203           enum map_type type = MAP_ARM;
6204           bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
6205
6206           if (!found || (found && type == MAP_THUMB))
6207             {
6208               /* This could be an IT instruction.  */
6209               seen_it = insn;
6210               it_count = count >> 1;
6211             }
6212         }
6213       if ((insn & 0xf800) >= 0xe800)
6214         count++;
6215       else
6216         count = (count + 2) | 1;
6217       /* IT blocks contain at most 4 instructions.  */
6218       if (count >= 8 && !seen_it)
6219         return;
6220     }
6221   /* We found an IT instruction.  */
6222   ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6223   if ((ifthen_state & 0xf) == 0)
6224     ifthen_state = 0;
6225 }
6226
6227 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6228    mapping symbol.  */
6229
6230 static int
6231 is_mapping_symbol (struct disassemble_info *info, int n,
6232                    enum map_type *map_type)
6233 {
6234   const char *name;
6235
6236   name = bfd_asymbol_name (info->symtab[n]);
6237   if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6238       && (name[2] == 0 || name[2] == '.'))
6239     {
6240       *map_type = ((name[1] == 'a') ? MAP_ARM
6241                    : (name[1] == 't') ? MAP_THUMB
6242                    : MAP_DATA);
6243       return TRUE;
6244     }
6245
6246   return FALSE;
6247 }
6248
6249 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6250    Returns nonzero if *MAP_TYPE was set.  */
6251
6252 static int
6253 get_map_sym_type (struct disassemble_info *info,
6254                   int n,
6255                   enum map_type *map_type)
6256 {
6257   /* If the symbol is in a different section, ignore it.  */
6258   if (info->section != NULL && info->section != info->symtab[n]->section)
6259     return FALSE;
6260
6261   return is_mapping_symbol (info, n, map_type);
6262 }
6263
6264 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
6265    Returns nonzero if *MAP_TYPE was set.  */
6266
6267 static int
6268 get_sym_code_type (struct disassemble_info *info,
6269                    int n,
6270                    enum map_type *map_type)
6271 {
6272   elf_symbol_type *es;
6273   unsigned int type;
6274
6275   /* If the symbol is in a different section, ignore it.  */
6276   if (info->section != NULL && info->section != info->symtab[n]->section)
6277     return FALSE;
6278
6279   es = *(elf_symbol_type **)(info->symtab + n);
6280   type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6281
6282   /* If the symbol has function type then use that.  */
6283   if (type == STT_FUNC || type == STT_GNU_IFUNC)
6284     {
6285       if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6286           == ST_BRANCH_TO_THUMB)
6287         *map_type = MAP_THUMB;
6288       else
6289         *map_type = MAP_ARM;
6290       return TRUE;
6291     }
6292
6293   return FALSE;
6294 }
6295
6296 /* Search the mapping symbol state for instruction at pc.  This is only
6297    applicable for elf target.
6298
6299    There is an assumption Here, info->private_data contains the correct AND
6300    up-to-date information about current scan process.  The information will be
6301    used to speed this search process.
6302
6303    Return TRUE if the mapping state can be determined, and map_symbol
6304    will be updated accordingly.  Otherwise, return FALSE.  */
6305
6306 static bfd_boolean
6307 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6308                          enum map_type *map_symbol)
6309 {
6310   bfd_vma addr;
6311   int n, start = 0;
6312   bfd_boolean found = FALSE;
6313   enum map_type type = MAP_ARM;
6314   struct arm_private_data *private_data;
6315
6316   if (info->private_data == NULL || info->symtab_size == 0
6317       || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
6318     return FALSE;
6319
6320   private_data = info->private_data;
6321   if (pc == 0)
6322     start = 0;
6323   else
6324     start = private_data->last_mapping_sym;
6325
6326   start = (start == -1)? 0 : start;
6327   addr = bfd_asymbol_value (info->symtab[start]);
6328
6329   if (pc >= addr)
6330     {
6331       if (get_map_sym_type (info, start, &type))
6332       found = TRUE;
6333     }
6334   else
6335     {
6336       for (n = start - 1; n >= 0; n--)
6337         {
6338           if (get_map_sym_type (info, n, &type))
6339             {
6340               found = TRUE;
6341               break;
6342             }
6343         }
6344     }
6345
6346   /* No mapping symbols were found.  A leading $d may be
6347      omitted for sections which start with data; but for
6348      compatibility with legacy and stripped binaries, only
6349      assume the leading $d if there is at least one mapping
6350      symbol in the file.  */
6351   if (!found && private_data->has_mapping_symbols == 1)
6352     {
6353       type = MAP_DATA;
6354       found = TRUE;
6355     }
6356
6357   *map_symbol = type;
6358   return found;
6359 }
6360
6361 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
6362    of the supplied arm_feature_set structure with bitmasks indicating
6363    the support base architectures and coprocessor extensions.
6364
6365    FIXME: This could more efficiently implemented as a constant array,
6366    although it would also be less robust.  */
6367
6368 static void
6369 select_arm_features (unsigned long mach,
6370                      arm_feature_set * features)
6371 {
6372 #undef ARM_SET_FEATURES
6373 #define ARM_SET_FEATURES(FSET) \
6374   {                                                     \
6375     const arm_feature_set fset = FSET;                  \
6376     arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \
6377     ARM_MERGE_FEATURE_SETS (*features, tmp, fset);      \
6378   }
6379
6380   switch (mach)
6381     {
6382     case bfd_mach_arm_2:       ARM_SET_FEATURES (ARM_ARCH_V2); break;
6383     case bfd_mach_arm_2a:      ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6384     case bfd_mach_arm_3:       ARM_SET_FEATURES (ARM_ARCH_V3); break;
6385     case bfd_mach_arm_3M:      ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6386     case bfd_mach_arm_4:       ARM_SET_FEATURES (ARM_ARCH_V4); break;
6387     case bfd_mach_arm_4T:      ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6388     case bfd_mach_arm_5:       ARM_SET_FEATURES (ARM_ARCH_V5); break;
6389     case bfd_mach_arm_5T:      ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6390     case bfd_mach_arm_5TE:     ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6391     case bfd_mach_arm_XScale:  ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
6392     case bfd_mach_arm_ep9312:
6393       ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6394                                          ARM_CEXT_MAVERICK | FPU_MAVERICK));
6395        break;
6396     case bfd_mach_arm_iWMMXt:  ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6397     case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
6398       /* If the machine type is unknown allow all
6399          architecture types and all extensions.  */
6400     case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
6401     default:
6402       abort ();
6403     }
6404
6405 #undef ARM_SET_FEATURES
6406 }
6407
6408
6409 /* NOTE: There are no checks in these routines that
6410    the relevant number of data bytes exist.  */
6411
6412 static int
6413 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
6414 {
6415   unsigned char b[4];
6416   long          given;
6417   int           status;
6418   int           is_thumb = FALSE;
6419   int           is_data = FALSE;
6420   int           little_code;
6421   unsigned int  size = 4;
6422   void          (*printer) (bfd_vma, struct disassemble_info *, long);
6423   bfd_boolean   found = FALSE;
6424   struct arm_private_data *private_data;
6425
6426   if (info->disassembler_options)
6427     {
6428       parse_arm_disassembler_options (info->disassembler_options);
6429
6430       /* To avoid repeated parsing of these options, we remove them here.  */
6431       info->disassembler_options = NULL;
6432     }
6433
6434   /* PR 10288: Control which instructions will be disassembled.  */
6435   if (info->private_data == NULL)
6436     {
6437       static struct arm_private_data private;
6438
6439       if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6440         /* If the user did not use the -m command line switch then default to
6441            disassembling all types of ARM instruction.
6442
6443            The info->mach value has to be ignored as this will be based on
6444            the default archictecture for the target and/or hints in the notes
6445            section, but it will never be greater than the current largest arm
6446            machine value (iWMMXt2), which is only equivalent to the V5TE
6447            architecture.  ARM architectures have advanced beyond the machine
6448            value encoding, and these newer architectures would be ignored if
6449            the machine value was used.
6450
6451            Ie the -m switch is used to restrict which instructions will be
6452            disassembled.  If it is necessary to use the -m switch to tell
6453            objdump that an ARM binary is being disassembled, eg because the
6454            input is a raw binary file, but it is also desired to disassemble
6455            all ARM instructions then use "-marm".  This will select the
6456            "unknown" arm architecture which is compatible with any ARM
6457            instruction.  */
6458           info->mach = bfd_mach_arm_unknown;
6459
6460       /* Compute the architecture bitmask from the machine number.
6461          Note: This assumes that the machine number will not change
6462          during disassembly....  */
6463       select_arm_features (info->mach, & private.features);
6464
6465       private.has_mapping_symbols = -1;
6466       private.last_mapping_sym = -1;
6467       private.last_mapping_addr = 0;
6468
6469       info->private_data = & private;
6470     }
6471
6472   private_data = info->private_data;
6473
6474   /* Decide if our code is going to be little-endian, despite what the
6475      function argument might say.  */
6476   little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6477
6478   /* For ELF, consult the symbol table to determine what kind of code
6479      or data we have.  */
6480   if (info->symtab_size != 0
6481       && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6482     {
6483       bfd_vma addr;
6484       int n, start;
6485       int last_sym = -1;
6486       enum map_type type = MAP_ARM;
6487
6488       /* Start scanning at the start of the function, or wherever
6489          we finished last time.  */
6490       /* PR 14006.  When the address is 0 we are either at the start of the
6491          very first function, or else the first function in a new, unlinked
6492          executable section (eg because of -ffunction-sections).  Either way
6493          start scanning from the beginning of the symbol table, not where we
6494          left off last time.  */
6495       if (pc == 0)
6496         start = 0;
6497       else
6498         {
6499           start = info->symtab_pos + 1;
6500           if (start < private_data->last_mapping_sym)
6501             start = private_data->last_mapping_sym;
6502         }
6503       found = FALSE;
6504
6505       /* First, look for mapping symbols.  */
6506       if (private_data->has_mapping_symbols != 0)
6507         {
6508           /* Scan up to the location being disassembled.  */
6509           for (n = start; n < info->symtab_size; n++)
6510             {
6511               addr = bfd_asymbol_value (info->symtab[n]);
6512               if (addr > pc)
6513                 break;
6514               if (get_map_sym_type (info, n, &type))
6515                 {
6516                   last_sym = n;
6517                   found = TRUE;
6518                 }
6519             }
6520
6521           if (!found)
6522             {
6523               /* No mapping symbol found at this address.  Look backwards
6524                  for a preceding one.  */
6525               for (n = start - 1; n >= 0; n--)
6526                 {
6527                   if (get_map_sym_type (info, n, &type))
6528                     {
6529                       last_sym = n;
6530                       found = TRUE;
6531                       break;
6532                     }
6533                 }
6534             }
6535
6536           if (found)
6537             private_data->has_mapping_symbols = 1;
6538
6539           /* No mapping symbols were found.  A leading $d may be
6540              omitted for sections which start with data; but for
6541              compatibility with legacy and stripped binaries, only
6542              assume the leading $d if there is at least one mapping
6543              symbol in the file.  */
6544           if (!found && private_data->has_mapping_symbols == -1)
6545             {
6546               /* Look for mapping symbols, in any section.  */
6547               for (n = 0; n < info->symtab_size; n++)
6548                 if (is_mapping_symbol (info, n, &type))
6549                   {
6550                     private_data->has_mapping_symbols = 1;
6551                     break;
6552                   }
6553               if (private_data->has_mapping_symbols == -1)
6554                 private_data->has_mapping_symbols = 0;
6555             }
6556
6557           if (!found && private_data->has_mapping_symbols == 1)
6558             {
6559               type = MAP_DATA;
6560               found = TRUE;
6561             }
6562         }
6563
6564       /* Next search for function symbols to separate ARM from Thumb
6565          in binaries without mapping symbols.  */
6566       if (!found)
6567         {
6568           /* Scan up to the location being disassembled.  */
6569           for (n = start; n < info->symtab_size; n++)
6570             {
6571               addr = bfd_asymbol_value (info->symtab[n]);
6572               if (addr > pc)
6573                 break;
6574               if (get_sym_code_type (info, n, &type))
6575                 {
6576                   last_sym = n;
6577                   found = TRUE;
6578                 }
6579             }
6580
6581           if (!found)
6582             {
6583               /* No mapping symbol found at this address.  Look backwards
6584                  for a preceding one.  */
6585               for (n = start - 1; n >= 0; n--)
6586                 {
6587                   if (get_sym_code_type (info, n, &type))
6588                     {
6589                       last_sym = n;
6590                       found = TRUE;
6591                       break;
6592                     }
6593                 }
6594             }
6595         }
6596
6597       private_data->last_mapping_sym = last_sym;
6598       private_data->last_type = type;
6599       is_thumb = (private_data->last_type == MAP_THUMB);
6600       is_data = (private_data->last_type == MAP_DATA);
6601
6602       /* Look a little bit ahead to see if we should print out
6603          two or four bytes of data.  If there's a symbol,
6604          mapping or otherwise, after two bytes then don't
6605          print more.  */
6606       if (is_data)
6607         {
6608           size = 4 - (pc & 3);
6609           for (n = last_sym + 1; n < info->symtab_size; n++)
6610             {
6611               addr = bfd_asymbol_value (info->symtab[n]);
6612               if (addr > pc
6613                   && (info->section == NULL
6614                       || info->section == info->symtab[n]->section))
6615                 {
6616                   if (addr - pc < size)
6617                     size = addr - pc;
6618                   break;
6619                 }
6620             }
6621           /* If the next symbol is after three bytes, we need to
6622              print only part of the data, so that we can use either
6623              .byte or .short.  */
6624           if (size == 3)
6625             size = (pc & 1) ? 1 : 2;
6626         }
6627     }
6628
6629   if (info->symbols != NULL)
6630     {
6631       if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6632         {
6633           coff_symbol_type * cs;
6634
6635           cs = coffsymbol (*info->symbols);
6636           is_thumb = (   cs->native->u.syment.n_sclass == C_THUMBEXT
6637                       || cs->native->u.syment.n_sclass == C_THUMBSTAT
6638                       || cs->native->u.syment.n_sclass == C_THUMBLABEL
6639                       || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6640                       || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6641         }
6642       else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6643                && !found)
6644         {
6645           /* If no mapping symbol has been found then fall back to the type
6646              of the function symbol.  */
6647           elf_symbol_type *  es;
6648           unsigned int       type;
6649
6650           es = *(elf_symbol_type **)(info->symbols);
6651           type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6652
6653           is_thumb =
6654             ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6655               == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
6656         }
6657       else if (bfd_asymbol_flavour (*info->symbols)
6658                == bfd_target_mach_o_flavour)
6659         {
6660           bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
6661
6662           is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
6663         }
6664     }
6665
6666   if (force_thumb)
6667     is_thumb = TRUE;
6668
6669   if (is_data)
6670     info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6671   else
6672     info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6673
6674   info->bytes_per_line = 4;
6675
6676   /* PR 10263: Disassemble data if requested to do so by the user.  */
6677   if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
6678     {
6679       int i;
6680
6681       /* Size was already set above.  */
6682       info->bytes_per_chunk = size;
6683       printer = print_insn_data;
6684
6685       status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
6686       given = 0;
6687       if (little)
6688         for (i = size - 1; i >= 0; i--)
6689           given = b[i] | (given << 8);
6690       else
6691         for (i = 0; i < (int) size; i++)
6692           given = b[i] | (given << 8);
6693     }
6694   else if (!is_thumb)
6695     {
6696       /* In ARM mode endianness is a straightforward issue: the instruction
6697          is four bytes long and is either ordered 0123 or 3210.  */
6698       printer = print_insn_arm;
6699       info->bytes_per_chunk = 4;
6700       size = 4;
6701
6702       status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
6703       if (little_code)
6704         given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6705       else
6706         given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
6707     }
6708   else
6709     {
6710       /* In Thumb mode we have the additional wrinkle of two
6711          instruction lengths.  Fortunately, the bits that determine
6712          the length of the current instruction are always to be found
6713          in the first two bytes.  */
6714       printer = print_insn_thumb16;
6715       info->bytes_per_chunk = 2;
6716       size = 2;
6717
6718       status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
6719       if (little_code)
6720         given = (b[0]) | (b[1] << 8);
6721       else
6722         given = (b[1]) | (b[0] << 8);
6723
6724       if (!status)
6725         {
6726           /* These bit patterns signal a four-byte Thumb
6727              instruction.  */
6728           if ((given & 0xF800) == 0xF800
6729               || (given & 0xF800) == 0xF000
6730               || (given & 0xF800) == 0xE800)
6731             {
6732               status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
6733               if (little_code)
6734                 given = (b[0]) | (b[1] << 8) | (given << 16);
6735               else
6736                 given = (b[1]) | (b[0] << 8) | (given << 16);
6737
6738               printer = print_insn_thumb32;
6739               size = 4;
6740             }
6741         }
6742
6743       if (ifthen_address != pc)
6744         find_ifthen_state (pc, info, little_code);
6745
6746       if (ifthen_state)
6747         {
6748           if ((ifthen_state & 0xf) == 0x8)
6749             ifthen_next_state = 0;
6750           else
6751             ifthen_next_state = (ifthen_state & 0xe0)
6752                                 | ((ifthen_state & 0xf) << 1);
6753         }
6754     }
6755
6756   if (status)
6757     {
6758       info->memory_error_func (status, pc, info);
6759       return -1;
6760     }
6761   if (info->flags & INSN_HAS_RELOC)
6762     /* If the instruction has a reloc associated with it, then
6763        the offset field in the instruction will actually be the
6764        addend for the reloc.  (We are using REL type relocs).
6765        In such cases, we can ignore the pc when computing
6766        addresses, since the addend is not currently pc-relative.  */
6767     pc = 0;
6768
6769   printer (pc, info, given);
6770
6771   if (is_thumb)
6772     {
6773       ifthen_state = ifthen_next_state;
6774       ifthen_address += size;
6775     }
6776   return size;
6777 }
6778
6779 int
6780 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
6781 {
6782   /* Detect BE8-ness and record it in the disassembler info.  */
6783   if (info->flavour == bfd_target_elf_flavour
6784       && info->section != NULL
6785       && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6786     info->endian_code = BFD_ENDIAN_LITTLE;
6787
6788   return print_insn (pc, info, FALSE);
6789 }
6790
6791 int
6792 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
6793 {
6794   return print_insn (pc, info, TRUE);
6795 }
6796
6797 const disasm_options_t *
6798 disassembler_options_arm (void)
6799 {
6800   static disasm_options_t *opts = NULL;
6801
6802   if (opts == NULL)
6803     {
6804       unsigned int i;
6805       opts = XNEW (disasm_options_t);
6806       opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
6807       opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
6808       for (i = 0; i < NUM_ARM_OPTIONS; i++)
6809         {
6810           opts->name[i] = regnames[i].name;
6811           if (regnames[i].description != NULL)
6812             opts->description[i] = _(regnames[i].description);
6813           else
6814             opts->description[i] = NULL;
6815         }
6816       /* The array we return must be NULL terminated.  */
6817       opts->name[i] = NULL;
6818       opts->description[i] = NULL;
6819     }
6820
6821   return opts;
6822 }
6823
6824 void
6825 print_arm_disassembler_options (FILE *stream)
6826 {
6827   unsigned int i, max_len = 0;
6828   fprintf (stream, _("\n\
6829 The following ARM specific disassembler options are supported for use with\n\
6830 the -M switch:\n"));
6831
6832   for (i = 0; i < NUM_ARM_OPTIONS; i++)
6833     {
6834       unsigned int len = strlen (regnames[i].name);
6835       if (max_len < len)
6836         max_len = len;
6837     }
6838
6839   for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
6840     fprintf (stream, "  %s%*c %s\n",
6841              regnames[i].name,
6842              (int)(max_len - strlen (regnames[i].name)), ' ',
6843              _(regnames[i].description));
6844 }