opcodes/arm-dis.c

   1 /* Instruction printing code for the ARM
   2    Copyright (C) 1994-2015 Free Software Foundation, Inc.
   3    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
   4    Modification by James G. Smith (jsmith@cygnus.co.uk)
   5
   6    This file is part of libopcodes.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include "sysdep.h"
  24
  25 #include "dis-asm.h"
  26 #include "opcode/arm.h"
  27 #include "opintl.h"
  28 #include "safe-ctype.h"
  29 #include "floatformat.h"
  30
  31 /* FIXME: This shouldn't be done here.  */
  32 #include "coff/internal.h"
  33 #include "libcoff.h"
  34 #include "elf-bfd.h"
  35 #include "elf/internal.h"
  36 #include "elf/arm.h"
  37
  38 /* FIXME: Belongs in global header.  */
  39 #ifndef strneq
  40 #define strneq(a,b,n)   (strncmp ((a), (b), (n)) == 0)
  41 #endif
  42
  43 #ifndef NUM_ELEM
  44 #define NUM_ELEM(a)     (sizeof (a) / sizeof (a)[0])
  45 #endif
  46
  47 /* Cached mapping symbol state.  */
  48 enum map_type
  49 {
  50   MAP_ARM,
  51   MAP_THUMB,
  52   MAP_DATA
  53 };
  54
  55 struct arm_private_data
  56 {
  57   /* The features to use when disassembling optional instructions.  */
  58   arm_feature_set features;
  59
  60   /* Whether any mapping symbols are present in the provided symbol
  61      table.  -1 if we do not know yet, otherwise 0 or 1.  */
  62   int has_mapping_symbols;
  63
  64   /* Track the last type (although this doesn't seem to be useful) */
  65   enum map_type last_type;
  66
  67   /* Tracking symbol table information */
  68   int last_mapping_sym;
  69   bfd_vma last_mapping_addr;
  70 };
  71
  72 struct opcode32
  73 {
  74   arm_feature_set arch;         /* Architecture defining this insn.  */
  75   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
  76   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
  77   const char *  assembler;      /* How to disassemble this insn.  */
  78 };
  79
  80 struct opcode16
  81 {
  82   arm_feature_set arch;         /* Architecture defining this insn.  */
  83   unsigned short value, mask;   /* Recognise insn if (op & mask) == value.  */
  84   const char *assembler;        /* How to disassemble this insn.  */
  85 };
  86
  87 /* print_insn_coprocessor recognizes the following format control codes:
  88
  89    %%                   %
  90
  91    %c                   print condition code (always bits 28-31 in ARM mode)
  92    %q                   print shifter argument
  93    %u                   print condition code (unconditional in ARM mode,
  94                           UNPREDICTABLE if not AL in Thumb)
  95    %A                   print address for ldc/stc/ldf/stf instruction
  96    %B                   print vstm/vldm register list
  97    %I                   print cirrus signed shift immediate: bits 0..3|4..6
  98    %F                   print the COUNT field of a LFM/SFM instruction.
  99    %P                   print floating point precision in arithmetic insn
 100    %Q                   print floating point precision in ldf/stf insn
 101    %R                   print floating point rounding mode
 102
 103    %<bitfield>c         print as a condition code (for vsel)
 104    %<bitfield>r         print as an ARM register
 105    %<bitfield>R         as %<>r but r15 is UNPREDICTABLE
 106    %<bitfield>ru        as %<>r but each u register must be unique.
 107    %<bitfield>d         print the bitfield in decimal
 108    %<bitfield>k         print immediate for VFPv3 conversion instruction
 109    %<bitfield>x         print the bitfield in hex
 110    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
 111    %<bitfield>f         print a floating point constant if >7 else a
 112                         floating point register
 113    %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
 114    %<bitfield>g         print as an iWMMXt 64-bit register
 115    %<bitfield>G         print as an iWMMXt general purpose or control register
 116    %<bitfield>D         print as a NEON D register
 117    %<bitfield>Q         print as a NEON Q register
 118    %<bitfield>E         print a quarter-float immediate value
 119
 120    %y<code>             print a single precision VFP reg.
 121                           Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
 122    %z<code>             print a double precision VFP reg
 123                           Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
 124
 125    %<bitfield>'c        print specified char iff bitfield is all ones
 126    %<bitfield>`c        print specified char iff bitfield is all zeroes
 127    %<bitfield>?ab...    select from array of values in big endian order
 128
 129    %L                   print as an iWMMXt N/M width field.
 130    %Z                   print the Immediate of a WSHUFH instruction.
 131    %l                   like 'A' except use byte offsets for 'B' & 'H'
 132                         versions.
 133    %i                   print 5-bit immediate in bits 8,3..0
 134                         (print "32" when 0)
 135    %r                   print register offset address for wldt/wstr instruction.  */
 136
 137 enum opcode_sentinel_enum
 138 {
 139   SENTINEL_IWMMXT_START = 1,
 140   SENTINEL_IWMMXT_END,
 141   SENTINEL_GENERIC_START
 142 } opcode_sentinels;
 143
 144 #define UNDEFINED_INSTRUCTION      "\t\t; <UNDEFINED> instruction: %0-31x"
 145 #define UNPREDICTABLE_INSTRUCTION  "\t; <UNPREDICTABLE>"
 146
 147 /* Common coprocessor opcodes shared between Arm and Thumb-2.  */
 148
 149 static const struct opcode32 coprocessor_opcodes[] =
 150 {
 151   /* XScale instructions.  */
 152   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 153     0x0e200010, 0x0fff0ff0,
 154     "mia%c\tacc0, %0-3r, %12-15r"},
 155   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 156     0x0e280010, 0x0fff0ff0,
 157     "miaph%c\tacc0, %0-3r, %12-15r"},
 158   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 159     0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
 160   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 161     0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
 162   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 163     0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
 164
 165   /* Intel Wireless MMX technology instructions.  */
 166   {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
 167   {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
 168     0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
 169   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 170     0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
 171   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 172     0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
 173   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 174     0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
 175   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 176     0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
 177   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 178     0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
 179   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 180     0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
 181   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 182     0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
 183   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 184     0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
 185   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 186     0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
 187   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 188     0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
 189   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 190     0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
 191   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 192     0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
 193   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 194     0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
 195   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 196     0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
 197   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 198     0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
 199   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 200     0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
 201   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 202     0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 203   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 204     0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
 205   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 206     0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
 207   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 208     0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
 209   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 210     0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
 211   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 212     0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
 213   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 214     0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
 215   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 216     0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
 217   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 218     0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 219   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 220     0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 221   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 222     0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
 223   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 224     0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
 225   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 226     0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
 227   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 228     0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
 229   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 230     0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
 231   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 232     0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
 233   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 234     0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 235   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 236     0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
 237   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 238     0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 239   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 240     0x0e800120, 0x0f800ff0,
 241     "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 242   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 243     0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 244   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 245     0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
 246   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 247     0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
 248   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 249     0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
 250   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 251     0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
 252   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 253     0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
 254   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 255     0x0e8000a0, 0x0f800ff0,
 256     "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 257   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 258     0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 259   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 260     0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 261   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 262     0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
 263   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 264     0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 265   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 266     0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
 267   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 268     0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 269   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 270     0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
 271   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 272     0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
 273   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 274     0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
 275   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 276     0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
 277   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 278     0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 279   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 280     0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 281   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 282     0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
 283   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 284     0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 285   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 286     0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 287   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 288     0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
 289   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 290     0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 291   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 292     0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 293   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 294     0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
 295   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 296     0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
 297   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 298     0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
 299   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 300     0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 301   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 302     0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
 303   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 304     0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 305   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 306     0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
 307   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 308     0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
 309   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 310     0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
 311   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 312     0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
 313   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 314     0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 315   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 316     0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 317   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 318     0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
 319   {ARM_FEATURE_CORE_LOW (0),
 320     SENTINEL_IWMMXT_END, 0, "" },
 321
 322   /* Floating point coprocessor (FPA) instructions.  */
 323   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 324     0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 325   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 326     0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 327   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 328     0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 329   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 330     0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 331   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 332     0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 333   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 334     0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 335   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 336     0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
 337   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 338     0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
 339   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 340     0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 341   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 342     0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
 343   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 344     0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
 345   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 346     0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
 347   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 348     0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
 349   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 350     0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
 351   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 352     0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
 353   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 354     0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
 355   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 356     0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
 357   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 358     0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
 359   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 360     0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
 361   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 362     0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
 363   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 364     0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
 365   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 366     0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
 367   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 368     0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
 369   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 370     0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
 371   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 372     0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
 373   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 374     0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
 375   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 376     0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
 377   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 378     0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
 379   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 380     0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
 381   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 382     0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
 383   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 384     0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
 385   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 386     0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
 387   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 388     0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
 389   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 390     0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
 391   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 392     0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
 393   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 394     0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
 395   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 396     0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
 397   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 398     0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
 399   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 400     0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
 401   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 402     0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
 403   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 404     0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
 405   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 406     0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
 407   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 408     0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
 409
 410   /* Register load/store.  */
 411   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 412     0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
 413   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 414     0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
 415   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 416     0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
 417   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 418     0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
 419   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 420     0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
 421   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 422     0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
 423   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 424     0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
 425   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 426     0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
 427   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 428     0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
 429   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 430     0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
 431   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 432     0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
 433   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 434     0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
 435   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 436     0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
 437   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 438     0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
 439   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 440     0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
 441   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 442     0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
 443
 444   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 445     0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 446   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 447     0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 448   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 449     0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 450   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 451     0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 452
 453   /* Data transfer between ARM and NEON registers.  */
 454   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 455     0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
 456   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 457     0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
 458   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 459     0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
 460   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 461     0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
 462   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 463     0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
 464   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 465     0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
 466   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 467     0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
 468   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 469     0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
 470   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 471     0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
 472   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 473     0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
 474   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 475     0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
 476   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 477     0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
 478   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 479     0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
 480   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 481     0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
 482   /* Half-precision conversion instructions.  */
 483   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 484     0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
 485   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 486     0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
 487   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 488     0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
 489   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 490     0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
 491
 492   /* Floating point coprocessor (VFP) instructions.  */
 493   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 494     0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
 495   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 496     0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
 497   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 498     0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
 499   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 500     0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
 501   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 502     0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
 503   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 504     0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
 505   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 506     0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
 507   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 508     0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
 509   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 510     0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
 511   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 512     0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
 513   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 514     0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
 515   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 516     0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
 517   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 518     0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
 519   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 520     0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
 521   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 522     0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
 523   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 524     0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
 525   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 526     0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
 527   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 528     0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
 529   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 530     0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
 531   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 532     0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
 533   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 534     0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
 535   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 536     0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
 537   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 538     0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
 539   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 540     0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
 541   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 542     0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
 543   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 544     0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
 545   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 546     0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
 547   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 548     0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
 549   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 550     0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
 551   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 552     0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
 553   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 554     0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
 555   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 556     0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
 557   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 558     0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
 559   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 560     0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
 561   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 562     0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
 563   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 564     0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
 565   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 566     0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
 567   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 568     0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
 569   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 570     0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
 571   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 572     0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
 573   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 574     0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
 575   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 576     0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
 577   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 578     0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
 579   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 580     0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
 581   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 582     0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
 583   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 584     0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
 585   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 586     0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
 587   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 588     0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
 589   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 590     0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
 591   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 592     0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
 593   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 594     0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
 595   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 596     0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
 597   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 598     0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
 599   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 600     0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
 601   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 602     0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
 603   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 604     0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
 605   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 606     0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
 607   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 608     0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
 609   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 610     0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
 611   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 612     0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
 613   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 614     0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
 615   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 616     0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
 617   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 618     0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
 619   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 620     0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
 621   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 622     0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
 623   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 624     0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
 625   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 626     0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
 627
 628   /* Cirrus coprocessor instructions.  */
 629   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 630     0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 631   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 632     0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 633   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 634     0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 635   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 636     0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 637   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 638     0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 639   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 640     0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 641   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 642     0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 643   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 644     0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 645   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 646     0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 647   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 648     0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 649   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 650     0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 651   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 652     0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 653   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 654     0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 655   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 656     0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 657   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 658     0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 659   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 660     0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 661   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 662     0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
 663   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 664     0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
 665   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 666     0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
 667   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 668     0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
 669   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 670     0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
 671   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 672     0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
 673   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 674     0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
 675   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 676     0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
 677   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 678     0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
 679   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 680     0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
 681   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 682     0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
 683   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 684     0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
 685   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 686     0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
 687   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 688     0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
 689   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 690     0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
 691   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 692     0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
 693   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 694     0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
 695   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 696     0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
 697   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 698     0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
 699   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 700     0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
 701   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 702     0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
 703   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 704     0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
 705   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 706     0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
 707   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 708     0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
 709   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 710     0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
 711   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 712     0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
 713   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 714     0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
 715   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 716     0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
 717   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 718     0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
 719   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 720     0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
 721   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 722     0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
 723   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 724     0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
 725   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 726     0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
 727   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 728     0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
 729   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 730     0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
 731   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 732     0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
 733   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 734     0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
 735   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 736     0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
 737   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 738     0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
 739   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 740     0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
 741   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 742     0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
 743   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 744     0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
 745   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 746     0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
 747   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 748     0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
 749   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 750     0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
 751   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 752     0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
 753   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 754     0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 755   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 756     0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 757   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 758     0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 759   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 760     0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 761   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 762     0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 763   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 764     0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 765   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 766     0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
 767   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 768     0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
 769   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 770     0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
 771   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 772     0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
 773   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 774     0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 775   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 776     0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 777   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 778     0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 779   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 780     0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 781   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 782     0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 783   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 784     0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 785   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 786     0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 787   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 788     0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 789   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 790     0x0e000600, 0x0ff00f10,
 791     "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 792   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 793     0x0e100600, 0x0ff00f10,
 794     "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 795   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 796     0x0e200600, 0x0ff00f10,
 797     "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 798   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 799     0x0e300600, 0x0ff00f10,
 800     "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 801
 802   /* VFP Fused multiply add instructions.  */
 803   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 804     0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
 805   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 806     0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
 807   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 808     0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
 809   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 810     0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
 811   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 812     0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
 813   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 814     0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
 815   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 816     0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
 817   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 818     0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
 819
 820   /* FP v5.  */
 821   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 822     0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
 823   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 824     0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
 825   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 826     0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"},
 827   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 828     0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"},
 829   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 830     0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"},
 831   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 832     0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},
 833   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 834     0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
 835   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 836     0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
 837   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 838     0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
 839   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 840     0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
 841   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 842     0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
 843   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 844     0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
 845
 846   /* Generic coprocessor instructions.  */
 847   {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
 848   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
 849     0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
 850   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
 851     0x0c500000, 0x0ff00000,
 852     "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 853   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 854     0x0e000000, 0x0f000010,
 855     "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 856   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 857     0x0e10f010, 0x0f10f010,
 858     "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
 859   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 860     0x0e100010, 0x0f100010,
 861     "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 862   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 863     0x0e000010, 0x0f100010,
 864     "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 865   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 866     0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
 867   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 868     0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
 869
 870   /* V6 coprocessor instructions.  */
 871   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
 872     0xfc500000, 0xfff00000,
 873     "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 874   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
 875     0xfc400000, 0xfff00000,
 876     "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
 877
 878   /* V5 coprocessor instructions.  */
 879   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 880     0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
 881   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 882     0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
 883   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 884     0xfe000000, 0xff000010,
 885     "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 886   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 887     0xfe000010, 0xff100010,
 888     "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 889   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 890     0xfe100010, 0xff100010,
 891     "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 892
 893   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
 894 };
 895
 896 /* Neon opcode table:  This does not encode the top byte -- that is
 897    checked by the print_insn_neon routine, as it depends on whether we are
 898    doing thumb32 or arm32 disassembly.  */
 899
 900 /* print_insn_neon recognizes the following format control codes:
 901
 902    %%                   %
 903
 904    %c                   print condition code
 905    %u                   print condition code (unconditional in ARM mode,
 906                           UNPREDICTABLE if not AL in Thumb)
 907    %A                   print v{st,ld}[1234] operands
 908    %B                   print v{st,ld}[1234] any one operands
 909    %C                   print v{st,ld}[1234] single->all operands
 910    %D                   print scalar
 911    %E                   print vmov, vmvn, vorr, vbic encoded constant
 912    %F                   print vtbl,vtbx register list
 913
 914    %<bitfield>r         print as an ARM register
 915    %<bitfield>d         print the bitfield in decimal
 916    %<bitfield>e         print the 2^N - bitfield in decimal
 917    %<bitfield>D         print as a NEON D register
 918    %<bitfield>Q         print as a NEON Q register
 919    %<bitfield>R         print as a NEON D or Q register
 920    %<bitfield>Sn        print byte scaled width limited by n
 921    %<bitfield>Tn        print short scaled width limited by n
 922    %<bitfield>Un        print long scaled width limited by n
 923
 924    %<bitfield>'c        print specified char iff bitfield is all ones
 925    %<bitfield>`c        print specified char iff bitfield is all zeroes
 926    %<bitfield>?ab...    select from array of values in big endian order.  */
 927
 928 static const struct opcode32 neon_opcodes[] =
 929 {
 930   /* Extract.  */
 931   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 932     0xf2b00840, 0xffb00850,
 933     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
 934   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 935     0xf2b00000, 0xffb00810,
 936     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
 937
 938   /* Move data element to all lanes.  */
 939   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 940     0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
 941   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 942     0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
 943   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 944     0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
 945
 946   /* Table lookup.  */
 947   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 948     0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
 949   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 950     0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
 951
 952   /* Half-precision conversions.  */
 953   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 954     0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
 955   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 956     0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
 957
 958   /* NEON fused multiply add instructions.  */
 959   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
 960     0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 961   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
 962     0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 963
 964   /* Two registers, miscellaneous.  */
 965   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
 966     0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
 967   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
 968     0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
 969   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
 970     0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
 971   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
 972     0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
 973   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
 974     0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
 975   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
 976     0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
 977   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
 978     0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
 979   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
 980     0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
 981   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
 982     0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
 983   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 984     0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
 985   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 986     0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
 987   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 988     0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
 989   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 990     0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
 991   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 992     0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
 993   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 994     0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
 995   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 996     0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
 997   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 998     0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
 999   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1000     0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1001   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1002     0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1003   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1004     0xf3b20300, 0xffb30fd0,
1005     "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1006   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1007     0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1008   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1009     0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1010   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1011     0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1012   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1013     0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1014   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1015     0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1016   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1017     0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1018   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1019     0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1020   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1021     0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1022   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1023     0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1024   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1025     0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1026   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1027     0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1028   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1029     0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1030   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1031     0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1032   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1033     0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1034   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1035     0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1036   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1037     0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1038   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1039     0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1040   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1041     0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1042   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1043     0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1044   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1045     0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1046   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1047     0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1048   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1049     0xf3b30600, 0xffb30e10,
1050     "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1051
1052   /* Three registers of the same length.  */
1053   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1054     0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1055   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1056     0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1057   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1058     0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1059   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1060     0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1061   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1062     0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1063   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1064     0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1065   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1066     0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1067   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1068     0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1069   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1070     0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1071   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1072     0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1073   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1074     0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1075   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1076     0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1077   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1078     0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1079   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1080     0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1081   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1082     0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1083   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1084     0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1085   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1086     0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1087   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1088     0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1089   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1090     0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1091   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1092     0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1093   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1094     0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1095   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1096     0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1097   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1098     0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1099   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1100     0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1101   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1102     0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1103   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1104     0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1105   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1106     0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1107   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1108     0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1109   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1110     0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1111   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1112     0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1113   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1114     0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1115   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1116     0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1117   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1118     0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1119   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1120     0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1121   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1122     0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1123   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1124     0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1125   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1126     0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1127   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1128     0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1129   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1130     0xf2000b00, 0xff800f10,
1131     "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1132   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1133     0xf2000b10, 0xff800f10,
1134     "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1135   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1136     0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1137   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1138     0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1139   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1140     0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1141   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1142     0xf3000b00, 0xff800f10,
1143     "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1144   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1145     0xf2000000, 0xfe800f10,
1146     "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1147   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1148     0xf2000010, 0xfe800f10,
1149     "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1150   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1151     0xf2000100, 0xfe800f10,
1152     "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1153   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1154     0xf2000200, 0xfe800f10,
1155     "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1156   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1157     0xf2000210, 0xfe800f10,
1158     "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1159   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1160     0xf2000300, 0xfe800f10,
1161     "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1162   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1163     0xf2000310, 0xfe800f10,
1164     "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1165   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1166     0xf2000400, 0xfe800f10,
1167     "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1168   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1169     0xf2000410, 0xfe800f10,
1170     "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1171   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1172     0xf2000500, 0xfe800f10,
1173     "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1174   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1175     0xf2000510, 0xfe800f10,
1176     "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1177   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1178     0xf2000600, 0xfe800f10,
1179     "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1180   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1181     0xf2000610, 0xfe800f10,
1182     "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1183   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1184     0xf2000700, 0xfe800f10,
1185     "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1186   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1187     0xf2000710, 0xfe800f10,
1188     "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1189   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1190     0xf2000910, 0xfe800f10,
1191     "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1192   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1193     0xf2000a00, 0xfe800f10,
1194     "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1195   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1196     0xf2000a10, 0xfe800f10,
1197     "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1198   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1199     0xf3000b10, 0xff800f10,
1200     "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1201   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1202     0xf3000c10, 0xff800f10,
1203     "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1204
1205   /* One register and an immediate value.  */
1206   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1207     0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1208   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1209     0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1210   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1211     0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1212   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1213     0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1214   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1215     0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1216   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1217     0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1218   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1219     0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1220   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1221     0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1222   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1223     0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1224   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1225     0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1226   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1227     0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1228   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1229     0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1230   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1231     0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1232
1233   /* Two registers and a shift amount.  */
1234   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1235     0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1236   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1237     0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1238   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1239     0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1240   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1241     0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1242   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1243     0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1244   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1245     0xf2880950, 0xfeb80fd0,
1246     "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1247   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1248     0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1249   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1250     0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1251   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1252     0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1253   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1254     0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1255   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1256     0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1257   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1258     0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1259   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1260     0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1261   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1262     0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1263   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1264     0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1265   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1266     0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1267   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1268     0xf2900950, 0xfeb00fd0,
1269     "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1270   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1271     0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1272   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1273     0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1274   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1275     0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1276   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1277     0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1278   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1279     0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1280   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1281     0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1282   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1283     0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1284   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1285     0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1286   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1287     0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1288   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1289     0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1290   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1291     0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1292   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1293     0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1294   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1295     0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1296   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1297     0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1298   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1299     0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1300   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1301     0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1302   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1303     0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1304   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1305     0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1306   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1307     0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1308   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1309     0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1310   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1311     0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1312   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1313     0xf2a00950, 0xfea00fd0,
1314     "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1315   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1316     0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1317   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1318     0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1319   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1320     0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1321   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1322     0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1323   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1324     0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1325   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1326     0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1327   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1328     0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1329   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1330     0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1331   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1332     0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1333   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1334     0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1335   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1336     0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1337   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1338     0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1339   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1340     0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1341   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1342     0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1343   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1344     0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1345   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1346     0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1347   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1348     0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1349   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1350     0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1351   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1352     0xf2a00e10, 0xfea00e90,
1353     "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1354
1355   /* Three registers of different lengths.  */
1356   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1357     0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1358   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1359     0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1360   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1361     0xf2800400, 0xff800f50,
1362     "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1363   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1364     0xf2800600, 0xff800f50,
1365     "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1366   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1367     0xf2800900, 0xff800f50,
1368     "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1369   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1370     0xf2800b00, 0xff800f50,
1371     "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1372   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1373     0xf2800d00, 0xff800f50,
1374     "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1375   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1376     0xf3800400, 0xff800f50,
1377     "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1378   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1379     0xf3800600, 0xff800f50,
1380     "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1381   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1382     0xf2800000, 0xfe800f50,
1383     "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1384   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1385     0xf2800100, 0xfe800f50,
1386     "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1387   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1388     0xf2800200, 0xfe800f50,
1389     "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1390   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1391     0xf2800300, 0xfe800f50,
1392     "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1393   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1394     0xf2800500, 0xfe800f50,
1395     "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1396   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1397     0xf2800700, 0xfe800f50,
1398     "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1399   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1400     0xf2800800, 0xfe800f50,
1401     "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1402   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1403     0xf2800a00, 0xfe800f50,
1404     "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1405   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1406     0xf2800c00, 0xfe800f50,
1407     "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1408
1409   /* Two registers and a scalar.  */
1410   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411     0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1412   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413     0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1414   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415     0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1416   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1417     0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1418   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419     0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1420   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1421     0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1422   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1423     0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1424   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1425     0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1426   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427     0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1428   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429     0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1430   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1431     0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1432   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1433     0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1434   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1435     0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1436   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1437     0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1438   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1439     0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1440   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1441     0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1442   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1443     0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1444   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1445     0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1446   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1447     0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1448   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1449     0xf2800240, 0xfe800f50,
1450     "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1451   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1452     0xf2800640, 0xfe800f50,
1453     "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1454   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1455     0xf2800a40, 0xfe800f50,
1456     "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1457   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1458     0xf2800e40, 0xff800f50,
1459    "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1460   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1461     0xf2800f40, 0xff800f50,
1462    "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1463   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1464     0xf3800e40, 0xff800f50,
1465    "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1466   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1467     0xf3800f40, 0xff800f50,
1468    "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1469   },
1470
1471   /* Element and structure load/store.  */
1472   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473     0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1474   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475     0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1476   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477     0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1478   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479     0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1480   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481     0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1482   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1483     0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1484   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1485     0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1486   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487     0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1488   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1489     0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1490   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1491     0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1492   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1493     0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1494   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1495     0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1496   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1497     0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1498   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1499     0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1500   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1501     0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1502   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1503     0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1504   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1505     0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1506   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1507     0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1508   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1509     0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1510
1511   {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1512 };
1513
1514 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb.  All three are partially
1515    ordered: they must be searched linearly from the top to obtain a correct
1516    match.  */
1517
1518 /* print_insn_arm recognizes the following format control codes:
1519
1520    %%                   %
1521
1522    %a                   print address for ldr/str instruction
1523    %s                   print address for ldr/str halfword/signextend instruction
1524    %S                   like %s but allow UNPREDICTABLE addressing
1525    %b                   print branch destination
1526    %c                   print condition code (always bits 28-31)
1527    %m                   print register mask for ldm/stm instruction
1528    %o                   print operand2 (immediate or register + shift)
1529    %p                   print 'p' iff bits 12-15 are 15
1530    %t                   print 't' iff bit 21 set and bit 24 clear
1531    %B                   print arm BLX(1) destination
1532    %C                   print the PSR sub type.
1533    %U                   print barrier type.
1534    %P                   print address for pli instruction.
1535
1536    %<bitfield>r         print as an ARM register
1537    %<bitfield>T         print as an ARM register + 1
1538    %<bitfield>R         as %r but r15 is UNPREDICTABLE
1539    %<bitfield>{r|R}u    as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1540    %<bitfield>{r|R}U    as %{r|R} but if matches the other %U field then is UNPREDICTABLE
1541    %<bitfield>d         print the bitfield in decimal
1542    %<bitfield>W         print the bitfield plus one in decimal
1543    %<bitfield>x         print the bitfield in hex
1544    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
1545
1546    %<bitfield>'c        print specified char iff bitfield is all ones
1547    %<bitfield>`c        print specified char iff bitfield is all zeroes
1548    %<bitfield>?ab...    select from array of values in big endian order
1549
1550    %e                   print arm SMI operand (bits 0..7,8..19).
1551    %E                   print the LSB and WIDTH fields of a BFI or BFC instruction.
1552    %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.
1553    %R                   print the SPSR/CPSR or banked register of an MRS.  */
1554
1555 static const struct opcode32 arm_opcodes[] =
1556 {
1557   /* ARM instructions.  */
1558   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1559     0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1560   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1561     0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1562
1563   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1564     0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1565   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1566     0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1567   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1568     0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1569   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1570     0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1571   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1572     0x00800090, 0x0fa000f0,
1573     "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1574   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1575     0x00a00090, 0x0fa000f0,
1576     "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1577
1578   /* V8 instructions.  */
1579   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1580     0x0320f005, 0x0fffffff, "sevl"},
1581   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1582     0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
1583   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1584     0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
1585   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1586     0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1587   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1588     0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1589   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1590     0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
1591   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1592     0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
1593   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1594     0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
1595   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1596     0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
1597   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1598     0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
1599   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1600     0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
1601   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1602     0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
1603   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1604     0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
1605   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1606     0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
1607   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1608     0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
1609   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1610     0x01f00c9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
1611   /* CRC32 instructions.  */
1612   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1613     0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1614   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1615     0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1616   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1617     0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1618   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1619     0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1620   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1621     0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1622   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1623     0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
1624
1625   /* Privileged Access Never extension instructions.  */
1626   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1627     0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1628
1629   /* Virtualization Extension instructions.  */
1630   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1631   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
1632
1633   /* Integer Divide Extension instructions.  */
1634   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1635     0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1636   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1637     0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
1638
1639   /* MP Extension instructions.  */
1640   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
1641
1642   /* V7 instructions.  */
1643   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1644   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1645   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1646   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1647   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1648   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1649   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
1650    {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1651     0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
1652
1653   /* ARM V6T2 instructions.  */
1654   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1655     0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1656   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1657     0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1658   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1659     0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1660   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1661     0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1662
1663   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1664     0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1665   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1666     0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1667
1668   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1669     0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
1670   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1671     0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1672   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1673     0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1674   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1675     0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
1676
1677   /* ARM Security extension instructions.  */
1678   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1679     0x01600070, 0x0ff000f0, "smc%c\t%e"},
1680
1681   /* ARM V6K instructions.  */
1682   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1683     0xf57ff01f, 0xffffffff, "clrex"},
1684   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1685     0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1686   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1687     0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1688   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1689     0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1690   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1691     0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1692   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1693     0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1694   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1695     0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
1696
1697   /* ARM V6K NOP hints.  */
1698   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1699     0x0320f001, 0x0fffffff, "yield%c"},
1700   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1701     0x0320f002, 0x0fffffff, "wfe%c"},
1702   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1703     0x0320f003, 0x0fffffff, "wfi%c"},
1704   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1705     0x0320f004, 0x0fffffff, "sev%c"},
1706   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1707     0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
1708
1709   /* ARM V6 instructions.  */
1710   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1711     0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1712   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1713     0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1714   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1715     0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1716   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1717     0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1718   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1719     0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1720   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1721     0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1722   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1723     0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1724   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1725     0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1726   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1727     0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1728   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1729     0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1730   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1731     0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1732   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1733     0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1734   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1735     0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1736   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1737     0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1738   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1739     0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1740   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1741     0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1742   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1743     0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1744   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1745     0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1746   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1747     0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1748   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1749     0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1750   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1751     0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1752   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1753     0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1754   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1755     0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1756   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1757     0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1758   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1759     0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1760   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1761     0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1762   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1763     0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1764   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1765     0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1766   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1767     0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1768   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1769     0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1770   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1771     0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1772   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1773     0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1774   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1775     0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1776   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1777     0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1778   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1779     0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1780   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1781     0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
1782   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1783     0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
1784   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1785     0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
1786   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1787     0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
1788   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1789     0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
1790   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1791     0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
1792   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1793     0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
1794   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1795     0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
1796   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1797     0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
1798   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1799     0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
1800   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1801     0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
1802   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1803     0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
1804   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1805     0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
1806   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1807     0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
1808   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1809     0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
1810   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1811     0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
1812   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1813     0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
1814   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1815     0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
1816   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1817     0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
1818   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1819     0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
1820   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1821     0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
1822   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1823     0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
1824   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1825     0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
1826   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1827     0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
1828   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1829     0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
1830   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1831     0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
1832   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1833     0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
1834   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1835     0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
1836   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1837     0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
1838   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1839     0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
1840   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1841     0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
1842   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1843     0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
1844   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1845     0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
1846   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1847     0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
1848   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1849     0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
1850   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1851     0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
1852   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1853     0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
1854   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1855     0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
1856   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1857     0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
1858   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1859     0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
1860   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1861     0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1862   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1863     0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1864   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1865     0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1866   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1867     0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
1868   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1869     0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1870   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1871     0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1872   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1873     0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1874   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1875     0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
1876   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1877     0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1878   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1879     0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1880   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1881     0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1882   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1883     0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
1884   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1885     0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1886   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1887     0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1888   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1889     0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1890   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1891     0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
1892   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1893     0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1894   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1895     0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1896   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1897     0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
1898   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1899     0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
1900   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1901     0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1902   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1903     0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1904   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1905     0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1906   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1907     0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
1908   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1909     0xf1010000, 0xfffffc00, "setend\t%9?ble"},
1910   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1911     0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
1912   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1913     0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
1914   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1915     0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1916   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1917     0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1918   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1919     0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1920   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1921     0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1922   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1923     0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
1924   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1925     0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1926   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1927     0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1928   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1929     0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
1930   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1931     0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
1932   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1933     0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
1934   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1935     0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
1936   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1937     0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
1938   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1939     0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
1940   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1941     0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
1942   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1943     0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
1944   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1945     0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1946   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1947     0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
1948   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1949     0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
1950   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1951     0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
1952   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1953     0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
1954
1955   /* V5J instruction.  */
1956   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
1957     0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
1958
1959   /* V5 Instructions.  */
1960   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1961     0xe1200070, 0xfff000f0,
1962     "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
1963   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1964     0xfa000000, 0xfe000000, "blx\t%B"},
1965   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1966     0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
1967   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1968     0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
1969
1970   /* V5E "El Segundo" Instructions.  */
1971   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1972     0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
1973   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1974     0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
1975   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1976     0xf450f000, 0xfc70f000, "pld\t%a"},
1977   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1978     0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1979   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1980     0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1981   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1982     0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1983   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1984     0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
1985
1986   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1987     0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1988   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1989     0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
1990
1991   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1992     0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1993   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1994     0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1995   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1996     0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1997   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1998     0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1999
2000   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2001     0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2002   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2003     0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2004   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2005     0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2006   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2007     0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2008
2009   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2010     0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2011   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2012     0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2013
2014   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2015     0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15R, %0-3R, %16-19R"},
2016   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2017     0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2018   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2019     0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15R, %0-3R, %16-19R"},
2020   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2021     0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
2022
2023   /* ARM Instructions.  */
2024   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2025     0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2026
2027   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2028     0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2029   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2030     0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2031   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2032     0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2033   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2034     0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2035   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2036     0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2037   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2038     0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2039
2040   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2041     0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2042   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2043     0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2044   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2045     0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2046   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2047     0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2048
2049   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2050     0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2051   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2052     0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2053   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2054     0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2055   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2056     0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2057
2058   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2059     0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2060   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2061     0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2062   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2063     0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2064
2065   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2066     0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2067   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2068     0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2069   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2070     0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2071
2072   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2073     0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2074   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2075     0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2076   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2077     0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2078
2079   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2080     0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2081   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2082     0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2083   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2084     0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2085
2086   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2087     0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2088   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2089     0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2090   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2091     0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2092
2093   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2094     0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2095   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2096     0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2097   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2098     0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2099
2100   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2101     0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2102   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2103     0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2104   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2105     0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2106
2107   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2108     0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2109   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2110     0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2111   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2112     0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2113
2114   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2115     0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2116   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2117     0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2118   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2119     0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2120
2121   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2122     0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2123   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2124     0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2125   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2126     0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2127
2128   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2129     0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
2130   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2131     0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
2132   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2133     0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
2134   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2135     0x0130f000, 0x0ff0f010, "bx%c\t%0-3r"},
2136
2137   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2138     0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2139   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2140     0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2141   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2142     0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2143
2144   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2145     0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2146   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2147     0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2148   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2149     0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2150
2151   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2152     0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2153   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2154     0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2155   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2156     0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2157
2158   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2159     0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2160   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2161     0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2162   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2163     0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2164   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2165     0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2166   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2167     0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2168   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2169     0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2170   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2171     0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2172
2173   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2174     0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2175   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2176     0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2177   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2178     0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2179
2180   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2181     0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2182   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2183     0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2184   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2185     0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2186
2187   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2188     0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2189   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2190     0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2191
2192   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2193     0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2194
2195   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2196     0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2197   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2198     0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2199
2200   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2201     0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2202   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2203     0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2204   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2205     0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2206   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2207     0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2208   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2209     0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2210   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2211     0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2212   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2213     0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2214   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2215     0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2216   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2217     0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2218   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2219     0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2220   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2221     0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2222   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2223     0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2224   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2225     0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2226   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2227     0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2228   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2229     0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2230   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2231     0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2232   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2233     0x092d0000, 0x0fff0000, "push%c\t%m"},
2234   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2235     0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2236   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2237     0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2238
2239   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2240     0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2241   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2242     0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2243   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2244     0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2245   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2246     0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2247   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2248     0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2249   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2250     0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2251   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2252     0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2253   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2254     0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2255   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2256     0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2257   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2258     0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2259   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2260     0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2261   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2262     0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2263   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2264     0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2265   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2266     0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2267   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2268     0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2269   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2270     0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2271   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2272     0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2273   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2274     0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2275   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2276     0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2277
2278   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2279     0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2280   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2281     0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
2282
2283   /* The rest.  */
2284   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2285     0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
2286   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2287     0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2288   {ARM_FEATURE_CORE_LOW (0),
2289     0x00000000, 0x00000000, 0}
2290 };
2291
2292 /* print_insn_thumb16 recognizes the following format control codes:
2293
2294    %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
2295    %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
2296    %<bitfield>I         print bitfield as a signed decimal
2297                                 (top bit of range being the sign bit)
2298    %N                   print Thumb register mask (with LR)
2299    %O                   print Thumb register mask (with PC)
2300    %M                   print Thumb register mask
2301    %b                   print CZB's 6-bit unsigned branch destination
2302    %s                   print Thumb right-shift immediate (6..10; 0 == 32).
2303    %c                   print the condition code
2304    %C                   print the condition code, or "s" if not conditional
2305    %x                   print warning if conditional an not at end of IT block"
2306    %X                   print "\t; unpredictable <IT:code>" if conditional
2307    %I                   print IT instruction suffix and operands
2308    %W                   print Thumb Writeback indicator for LDMIA
2309    %<bitfield>r         print bitfield as an ARM register
2310    %<bitfield>d         print bitfield as a decimal
2311    %<bitfield>H         print (bitfield * 2) as a decimal
2312    %<bitfield>W         print (bitfield * 4) as a decimal
2313    %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
2314    %<bitfield>B         print Thumb branch destination (signed displacement)
2315    %<bitfield>c         print bitfield as a condition code
2316    %<bitnum>'c          print specified char iff bit is one
2317    %<bitnum>?ab         print a if bit is one else print b.  */
2318
2319 static const struct opcode16 thumb_opcodes[] =
2320 {
2321   /* Thumb instructions.  */
2322
2323   /* ARM V8 instructions.  */
2324   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xbf50, 0xffff, "sevl%c"},
2325   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xba80, 0xffc0, "hlt\t%0-5x"},
2326   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),  0xb610, 0xfff7, "setpan\t#%3-3d"},
2327
2328   /* ARM V6K no-argument instructions.  */
2329   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2330   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2331   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2332   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2333   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2334   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
2335
2336   /* ARM V6T2 instructions.  */
2337   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2338   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
2339   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
2340
2341   /* ARM V6.  */
2342   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2343   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2344   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2345   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2346   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2347   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2348   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2349   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2350   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2351   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2352   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
2353
2354   /* ARM V5 ISA extends Thumb.  */
2355   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2356     0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
2357   /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
2358   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2359     0x4780, 0xff87, "blx%c\t%3-6r%x"},  /* note: 4 bit register number.  */
2360   /* ARM V4T ISA (Thumb v1).  */
2361   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2362     0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
2363   /* Format 4.  */
2364   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2365   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2366   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2367   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2368   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2369   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2370   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2371   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2372   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2373   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2374   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2375   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2376   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2377   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2378   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2379   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
2380   /* format 13 */
2381   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2382   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
2383   /* format 5 */
2384   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2385   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2386   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2387   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
2388   /* format 14 */
2389   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2390   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
2391   /* format 2 */
2392   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2393     0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2394   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2395     0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2396   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2397     0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2398   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2399     0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
2400   /* format 8 */
2401   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2402     0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2403   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2404     0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2405   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2406     0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
2407   /* format 7 */
2408   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2409     0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2410   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2411     0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2412   /* format 1 */
2413   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2414   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2415     0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2416   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2417   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
2418   /* format 3 */
2419   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2420   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2421   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2422   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
2423   /* format 6 */
2424   /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2425   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2426     0x4800, 0xF800,
2427     "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
2428   /* format 9 */
2429   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2430     0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2431   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2432     0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2433   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2434     0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2435   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2436     0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
2437   /* format 10 */
2438   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2439     0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2440   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2441     0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
2442   /* format 11 */
2443   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2444     0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2445   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2446     0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
2447   /* format 12 */
2448   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2449     0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2450   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2451     0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
2452   /* format 15 */
2453   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2454   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
2455   /* format 17 */
2456   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
2457   /* format 16 */
2458   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2459   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2460   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
2461   /* format 18 */
2462   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
2463
2464   /* The E800 .. FFFF range is unconditionally redirected to the
2465      32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2466      are processed via that table.  Thus, we can never encounter a
2467      bare "second half of BL/BLX(1)" instruction here.  */
2468   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),  0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2469   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2470 };
2471
2472 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
2473    We adopt the convention that hw1 is the high 16 bits of .value and
2474    .mask, hw2 the low 16 bits.
2475
2476    print_insn_thumb32 recognizes the following format control codes:
2477
2478        %%               %
2479
2480        %I               print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2481        %M               print a modified 12-bit immediate (same location)
2482        %J               print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2483        %K               print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
2484        %H               print a 16-bit immediate from hw2[3:0],hw1[11:0]
2485        %S               print a possibly-shifted Rm
2486
2487        %L               print address for a ldrd/strd instruction
2488        %a               print the address of a plain load/store
2489        %w               print the width and signedness of a core load/store
2490        %m               print register mask for ldm/stm
2491
2492        %E               print the lsb and width fields of a bfc/bfi instruction
2493        %F               print the lsb and width fields of a sbfx/ubfx instruction
2494        %b               print a conditional branch offset
2495        %B               print an unconditional branch offset
2496        %s               print the shift field of an SSAT instruction
2497        %R               print the rotation field of an SXT instruction
2498        %U               print barrier type.
2499        %P               print address for pli instruction.
2500        %c               print the condition code
2501        %x               print warning if conditional an not at end of IT block"
2502        %X               print "\t; unpredictable <IT:code>" if conditional
2503
2504        %<bitfield>d     print bitfield in decimal
2505        %<bitfield>D     print bitfield plus one in decimal
2506        %<bitfield>W     print bitfield*4 in decimal
2507        %<bitfield>r     print bitfield as an ARM register
2508        %<bitfield>R     as %<>r but r15 is UNPREDICTABLE
2509        %<bitfield>S     as %<>R but r13 is UNPREDICTABLE
2510        %<bitfield>c     print bitfield as a condition code
2511
2512        %<bitfield>'c    print specified char iff bitfield is all ones
2513        %<bitfield>`c    print specified char iff bitfield is all zeroes
2514        %<bitfield>?ab... select from array of values in big endian order
2515
2516    With one exception at the bottom (done because BL and BLX(1) need
2517    to come dead last), this table was machine-sorted first in
2518    decreasing order of number of bits set in the mask, then in
2519    increasing numeric order of mask, then in increasing numeric order
2520    of opcode.  This order is not the clearest for a human reader, but
2521    is guaranteed never to catch a special-case bit pattern with a more
2522    general mask, which is important, because this instruction encoding
2523    makes heavy use of special-case bit patterns.  */
2524 static const struct opcode32 thumb32_opcodes[] =
2525 {
2526   /* V8 instructions.  */
2527   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2528     0xf3af8005, 0xffffffff, "sevl%c.w"},
2529   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2530     0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2531   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2532     0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2533   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2534     0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2535   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2536     0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2537   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2538     0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2539   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2540     0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2541   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2542     0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2543   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2544     0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2545   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2546     0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2547   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2548     0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2549   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2550     0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2551   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2552     0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2553   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2554     0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2555   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2556     0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2557   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2558     0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
2559
2560   /* CRC32 instructions.  */
2561   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2562     0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"},
2563   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2564     0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"},
2565   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2566     0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"},
2567   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2568     0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"},
2569   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2570     0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"},
2571   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2572     0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"},
2573
2574   /* V7 instructions.  */
2575   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2576   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2577   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2578   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2579   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2580   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2581   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2582   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2583     0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2584   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2585     0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
2586
2587   /* Virtualization Extension instructions.  */
2588   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
2589   /* We skip ERET as that is SUBS pc, lr, #0.  */
2590
2591   /* MP Extension instructions.  */
2592   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP),   0xf830f000, 0xff70f000, "pldw%c\t%a"},
2593
2594   /* Security extension instructions.  */
2595   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
2596
2597   /* Instructions defined in the basic V6T2 set.  */
2598   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2599   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2600   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2601   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2602   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2603   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2604     0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2605   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2606
2607   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2608     0xf3bf8f2f, 0xffffffff, "clrex%c"},
2609   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2610     0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2611   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2612     0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2613   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2614     0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2615   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2616     0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2617   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2618     0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2619   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2620     0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2621   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2622     0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2623   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2624     0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2625   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2626     0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2627   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2628     0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2629   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2630     0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2631   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2632     0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2633   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2634     0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
2635   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2636     0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
2637   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2638     0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2639   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2640     0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2641   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2642     0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2643   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2644     0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2645   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2646     0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2647   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2648     0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2649   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2650     0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2651   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2652     0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2653   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2654     0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
2655   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2656     0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2657   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2658     0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2659   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2660     0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2661   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2662     0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2663   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2664     0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2665   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2666     0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2667   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2668     0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2669   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2670     0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2671   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2672     0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2673   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2674     0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2675   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2676     0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2677   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2678     0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2679   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2680     0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2681   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2682     0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2683   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2684     0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2685   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2686     0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2687   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2688     0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2689   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2690     0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2691   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2692     0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2693   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2694     0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2695   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2696     0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2697   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2698     0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2699   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2700     0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2701   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2702     0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2703   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2704     0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2705   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2706     0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2707   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2708     0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2709   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2710     0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2711   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2712     0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2713   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2714     0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2715   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2716     0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2717   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2718     0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2719   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2720     0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2721   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2722     0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2723   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2724     0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2725   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2726     0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2727   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2728     0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2729   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2730     0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2731   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2732     0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2733   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2734     0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2735   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2736     0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2737   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2738     0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2739   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2740     0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2741   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2742     0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2743   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2744     0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2745   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2746     0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2747   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2748     0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
2749   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2750     0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
2751   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2752     0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
2753   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2754     0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
2755   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2756     0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2757   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2758     0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2759   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2760     0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2761   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2762     0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
2763   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2764     0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
2765   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2766     0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
2767   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2768     0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
2769   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2770     0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
2771   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2772     0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2773   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2774     0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
2775   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2776     0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
2777   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2778     0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2779   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2780     0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2781   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2782     0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2783   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2784     0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2785   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2786     0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2787   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2788     0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2789   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2790     0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2791   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2792     0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
2793   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2794     0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
2795   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2796     0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
2797   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2798     0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
2799   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2800     0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
2801   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2802     0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
2803   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2804     0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
2805   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2806     0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
2807   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2808     0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
2809   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2810     0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
2811   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2812     0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
2813   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2814     0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
2815   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2816     0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2817   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2818     0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2819   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2820     0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2821   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2822     0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2823   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2824     0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2825   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2826     0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2827   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2828     0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2829   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2830     0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2831   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2832     0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
2833   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2834     0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
2835   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2836     0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
2837   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2838     0xf810f000, 0xff70f000, "pld%c\t%a"},
2839   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2840     0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2841   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2842     0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2843   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2844     0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2845   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2846     0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2847   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2848     0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2849   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2850     0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2851   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2852     0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2853   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2854     0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
2855   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2856     0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
2857   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2858     0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
2859   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2860     0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
2861   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2862     0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
2863   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2864     0xfb100000, 0xfff000c0,
2865     "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2866   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2867     0xfbc00080, 0xfff000c0,
2868     "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
2869   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2870     0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
2871   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2872     0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
2873   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2874     0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
2875   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2876     0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
2877   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2878     0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
2879   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2880     0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
2881   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2882     0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
2883   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2884     0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
2885   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2886     0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
2887   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2888     0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
2889   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2890     0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
2891   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2892     0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
2893   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2894     0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
2895   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2896     0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
2897   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2898     0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
2899   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2900     0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
2901   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2902     0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
2903   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2904     0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
2905   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2906     0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
2907   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2908     0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
2909   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2910     0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
2911   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2912     0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
2913   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2914     0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
2915   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2916     0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
2917   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2918     0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
2919   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2920     0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
2921   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2922     0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
2923   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2924     0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
2925   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2926     0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
2927   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2928     0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
2929   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2930     0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
2931   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2932     0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
2933   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2934     0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
2935   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2936     0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
2937   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2938     0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
2939   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2940     0xe9400000, 0xff500000,
2941     "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
2942   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2943     0xe9500000, 0xff500000,
2944     "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
2945   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2946     0xe8600000, 0xff700000,
2947     "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
2948   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2949     0xe8700000, 0xff700000,
2950     "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
2951   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2952     0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
2953   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2954     0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
2955
2956   /* Filter out Bcc with cond=E or F, which are used for other instructions.  */
2957   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2958     0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
2959   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2960     0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
2961   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2962     0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
2963   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2964     0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
2965
2966   /* These have been 32-bit since the invention of Thumb.  */
2967   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2968      0xf000c000, 0xf800d001, "blx%c\t%B%x"},
2969   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2970      0xf000d000, 0xf800d000, "bl%c\t%B%x"},
2971
2972   /* Fallback.  */
2973   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2974       0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2975   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2976 };
2977
2978 static const char *const arm_conditional[] =
2979 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
2980  "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
2981
2982 static const char *const arm_fp_const[] =
2983 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
2984
2985 static const char *const arm_shift[] =
2986 {"lsl", "lsr", "asr", "ror"};
2987
2988 typedef struct
2989 {
2990   const char *name;
2991   const char *description;
2992   const char *reg_names[16];
2993 }
2994 arm_regname;
2995
2996 static const arm_regname regnames[] =
2997 {
2998   { "raw" , "Select raw register names",
2999     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3000   { "gcc",  "Select register names used by GCC",
3001     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
3002   { "std",  "Select register names used in ARM's ISA documentation",
3003     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp",  "lr",  "pc" }},
3004   { "apcs", "Select register names used in the APCS",
3005     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
3006   { "atpcs", "Select register names used in the ATPCS",
3007     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7",  "v8",  "IP",  "SP",  "LR",  "PC" }},
3008   { "special-atpcs", "Select special register names used in the ATPCS",
3009     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }},
3010 };
3011
3012 static const char *const iwmmxt_wwnames[] =
3013 {"b", "h", "w", "d"};
3014
3015 static const char *const iwmmxt_wwssnames[] =
3016 {"b", "bus", "bc", "bss",
3017  "h", "hus", "hc", "hss",
3018  "w", "wus", "wc", "wss",
3019  "d", "dus", "dc", "dss"
3020 };
3021
3022 static const char *const iwmmxt_regnames[] =
3023 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3024   "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3025 };
3026
3027 static const char *const iwmmxt_cregnames[] =
3028 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3029   "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3030 };
3031
3032 /* Default to GCC register name set.  */
3033 static unsigned int regname_selected = 1;
3034
3035 #define NUM_ARM_REGNAMES  NUM_ELEM (regnames)
3036 #define arm_regnames      regnames[regname_selected].reg_names
3037
3038 static bfd_boolean force_thumb = FALSE;
3039
3040 /* Current IT instruction state.  This contains the same state as the IT
3041    bits in the CPSR.  */
3042 static unsigned int ifthen_state;
3043 /* IT state for the next instruction.  */
3044 static unsigned int ifthen_next_state;
3045 /* The address of the insn for which the IT state is valid.  */
3046 static bfd_vma ifthen_address;
3047 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
3048 /* Indicates that the current Conditional state is unconditional or outside
3049    an IT block.  */
3050 #define COND_UNCOND 16
3051
3052 \f
3053 /* Functions.  */
3054 int
3055 get_arm_regname_num_options (void)
3056 {
3057   return NUM_ARM_REGNAMES;
3058 }
3059
3060 int
3061 set_arm_regname_option (int option)
3062 {
3063   int old = regname_selected;
3064   regname_selected = option;
3065   return old;
3066 }
3067
3068 int
3069 get_arm_regnames (int option,
3070                   const char **setname,
3071                   const char **setdescription,
3072                   const char *const **register_names)
3073 {
3074   *setname = regnames[option].name;
3075   *setdescription = regnames[option].description;
3076   *register_names = regnames[option].reg_names;
3077   return 16;
3078 }
3079
3080 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3081    Returns pointer to following character of the format string and
3082    fills in *VALUEP and *WIDTHP with the extracted value and number of
3083    bits extracted.  WIDTHP can be NULL.  */
3084
3085 static const char *
3086 arm_decode_bitfield (const char *ptr,
3087                      unsigned long insn,
3088                      unsigned long *valuep,
3089                      int *widthp)
3090 {
3091   unsigned long value = 0;
3092   int width = 0;
3093
3094   do
3095     {
3096       int start, end;
3097       int bits;
3098
3099       for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3100         start = start * 10 + *ptr - '0';
3101       if (*ptr == '-')
3102         for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3103           end = end * 10 + *ptr - '0';
3104       else
3105         end = start;
3106       bits = end - start;
3107       if (bits < 0)
3108         abort ();
3109       value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3110       width += bits + 1;
3111     }
3112   while (*ptr++ == ',');
3113   *valuep = value;
3114   if (widthp)
3115     *widthp = width;
3116   return ptr - 1;
3117 }
3118
3119 static void
3120 arm_decode_shift (long given, fprintf_ftype func, void *stream,
3121                   bfd_boolean print_shift)
3122 {
3123   func (stream, "%s", arm_regnames[given & 0xf]);
3124
3125   if ((given & 0xff0) != 0)
3126     {
3127       if ((given & 0x10) == 0)
3128         {
3129           int amount = (given & 0xf80) >> 7;
3130           int shift = (given & 0x60) >> 5;
3131
3132           if (amount == 0)
3133             {
3134               if (shift == 3)
3135                 {
3136                   func (stream, ", rrx");
3137                   return;
3138                 }
3139
3140               amount = 32;
3141             }
3142
3143           if (print_shift)
3144             func (stream, ", %s #%d", arm_shift[shift], amount);
3145           else
3146             func (stream, ", #%d", amount);
3147         }
3148       else if ((given & 0x80) == 0x80)
3149         func (stream, "\t; <illegal shifter operand>");
3150       else if (print_shift)
3151         func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3152               arm_regnames[(given & 0xf00) >> 8]);
3153       else
3154         func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
3155     }
3156 }
3157
3158 #define W_BIT 21
3159 #define I_BIT 22
3160 #define U_BIT 23
3161 #define P_BIT 24
3162
3163 #define WRITEBACK_BIT_SET   (given & (1 << W_BIT))
3164 #define IMMEDIATE_BIT_SET   (given & (1 << I_BIT))
3165 #define NEGATIVE_BIT_SET   ((given & (1 << U_BIT)) == 0)
3166 #define PRE_BIT_SET         (given & (1 << P_BIT))
3167
3168 /* Print one coprocessor instruction on INFO->STREAM.
3169    Return TRUE if the instuction matched, FALSE if this is not a
3170    recognised coprocessor instruction.  */
3171
3172 static bfd_boolean
3173 print_insn_coprocessor (bfd_vma pc,
3174                         struct disassemble_info *info,
3175                         long given,
3176                         bfd_boolean thumb)
3177 {
3178   const struct opcode32 *insn;
3179   void *stream = info->stream;
3180   fprintf_ftype func = info->fprintf_func;
3181   unsigned long mask;
3182   unsigned long value = 0;
3183   int cond;
3184   struct arm_private_data *private_data = info->private_data;
3185   arm_feature_set allowed_arches = ARM_ARCH_NONE;
3186
3187   ARM_FEATURE_COPY (allowed_arches, private_data->features);
3188
3189   for (insn = coprocessor_opcodes; insn->assembler; insn++)
3190     {
3191       unsigned long u_reg = 16;
3192       bfd_boolean is_unpredictable = FALSE;
3193       signed long value_in_comment = 0;
3194       const char *c;
3195
3196       if (ARM_FEATURE_ZERO (insn->arch))
3197         switch (insn->value)
3198           {
3199           case SENTINEL_IWMMXT_START:
3200             if (info->mach != bfd_mach_arm_XScale
3201                 && info->mach != bfd_mach_arm_iWMMXt
3202                 && info->mach != bfd_mach_arm_iWMMXt2)
3203               do
3204                 insn++;
3205               while ((! ARM_FEATURE_ZERO (insn->arch))
3206                      && insn->value != SENTINEL_IWMMXT_END);
3207             continue;
3208
3209           case SENTINEL_IWMMXT_END:
3210             continue;
3211
3212           case SENTINEL_GENERIC_START:
3213             ARM_FEATURE_COPY (allowed_arches, private_data->features);
3214             continue;
3215
3216           default:
3217             abort ();
3218           }
3219
3220       mask = insn->mask;
3221       value = insn->value;
3222       if (thumb)
3223         {
3224           /* The high 4 bits are 0xe for Arm conditional instructions, and
3225              0xe for arm unconditional instructions.  The rest of the
3226              encoding is the same.  */
3227           mask |= 0xf0000000;
3228           value |= 0xe0000000;
3229           if (ifthen_state)
3230             cond = IFTHEN_COND;
3231           else
3232             cond = COND_UNCOND;
3233         }
3234       else
3235         {
3236           /* Only match unconditional instuctions against unconditional
3237              patterns.  */
3238           if ((given & 0xf0000000) == 0xf0000000)
3239             {
3240               mask |= 0xf0000000;
3241               cond = COND_UNCOND;
3242             }
3243           else
3244             {
3245               cond = (given >> 28) & 0xf;
3246               if (cond == 0xe)
3247                 cond = COND_UNCOND;
3248             }
3249         }
3250
3251       if ((given & mask) != value)
3252         continue;
3253
3254       if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
3255         continue;
3256
3257       for (c = insn->assembler; *c; c++)
3258         {
3259           if (*c == '%')
3260             {
3261               switch (*++c)
3262                 {
3263                 case '%':
3264                   func (stream, "%%");
3265                   break;
3266
3267                 case 'A':
3268                   {
3269                     int rn = (given >> 16) & 0xf;
3270                     bfd_vma offset = given & 0xff;
3271
3272                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3273
3274                     if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3275                       {
3276                         /* Not unindexed.  The offset is scaled.  */
3277                         offset = offset * 4;
3278                         if (NEGATIVE_BIT_SET)
3279                           offset = - offset;
3280                         if (rn != 15)
3281                           value_in_comment = offset;
3282                       }
3283
3284                     if (PRE_BIT_SET)
3285                       {
3286                         if (offset)
3287                           func (stream, ", #%d]%s",
3288                                 (int) offset,
3289                                 WRITEBACK_BIT_SET ? "!" : "");
3290                         else if (NEGATIVE_BIT_SET)
3291                           func (stream, ", #-0]");
3292                         else
3293                           func (stream, "]");
3294                       }
3295                     else
3296                       {
3297                         func (stream, "]");
3298
3299                         if (WRITEBACK_BIT_SET)
3300                           {
3301                             if (offset)
3302                               func (stream, ", #%d", (int) offset);
3303                             else if (NEGATIVE_BIT_SET)
3304                               func (stream, ", #-0");
3305                           }
3306                         else
3307                           {
3308                             func (stream, ", {%s%d}",
3309                                   (NEGATIVE_BIT_SET && !offset) ? "-" : "",
3310                                   (int) offset);
3311                             value_in_comment = offset;
3312                           }
3313                       }
3314                     if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3315                       {
3316                         func (stream, "\t; ");
3317                         /* For unaligned PCs, apply off-by-alignment
3318                            correction.  */
3319                         info->print_address_func (offset + pc
3320                                                   + info->bytes_per_chunk * 2
3321                                                   - (pc & 3),
3322                                                   info);
3323                       }
3324                   }
3325                   break;
3326
3327                 case 'B':
3328                   {
3329                     int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3330                     int offset = (given >> 1) & 0x3f;
3331
3332                     if (offset == 1)
3333                       func (stream, "{d%d}", regno);
3334                     else if (regno + offset > 32)
3335                       func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3336                     else
3337                       func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3338                   }
3339                   break;
3340
3341                 case 'u':
3342                   if (cond != COND_UNCOND)
3343                     is_unpredictable = TRUE;
3344
3345                   /* Fall through.  */
3346                 case 'c':
3347                   func (stream, "%s", arm_conditional[cond]);
3348                   break;
3349
3350                 case 'I':
3351                   /* Print a Cirrus/DSP shift immediate.  */
3352                   /* Immediates are 7bit signed ints with bits 0..3 in
3353                      bits 0..3 of opcode and bits 4..6 in bits 5..7
3354                      of opcode.  */
3355                   {
3356                     int imm;
3357
3358                     imm = (given & 0xf) | ((given & 0xe0) >> 1);
3359
3360                     /* Is ``imm'' a negative number?  */
3361                     if (imm & 0x40)
3362                       imm -= 0x80;
3363
3364                     func (stream, "%d", imm);
3365                   }
3366
3367                   break;
3368
3369                 case 'F':
3370                   switch (given & 0x00408000)
3371                     {
3372                     case 0:
3373                       func (stream, "4");
3374                       break;
3375                     case 0x8000:
3376                       func (stream, "1");
3377                       break;
3378                     case 0x00400000:
3379                       func (stream, "2");
3380                       break;
3381                     default:
3382                       func (stream, "3");
3383                     }
3384                   break;
3385
3386                 case 'P':
3387                   switch (given & 0x00080080)
3388                     {
3389                     case 0:
3390                       func (stream, "s");
3391                       break;
3392                     case 0x80:
3393                       func (stream, "d");
3394                       break;
3395                     case 0x00080000:
3396                       func (stream, "e");
3397                       break;
3398                     default:
3399                       func (stream, _("<illegal precision>"));
3400                       break;
3401                     }
3402                   break;
3403
3404                 case 'Q':
3405                   switch (given & 0x00408000)
3406                     {
3407                     case 0:
3408                       func (stream, "s");
3409                       break;
3410                     case 0x8000:
3411                       func (stream, "d");
3412                       break;
3413                     case 0x00400000:
3414                       func (stream, "e");
3415                       break;
3416                     default:
3417                       func (stream, "p");
3418                       break;
3419                     }
3420                   break;
3421
3422                 case 'R':
3423                   switch (given & 0x60)
3424                     {
3425                     case 0:
3426                       break;
3427                     case 0x20:
3428                       func (stream, "p");
3429                       break;
3430                     case 0x40:
3431                       func (stream, "m");
3432                       break;
3433                     default:
3434                       func (stream, "z");
3435                       break;
3436                     }
3437                   break;
3438
3439                 case '0': case '1': case '2': case '3': case '4':
3440                 case '5': case '6': case '7': case '8': case '9':
3441                   {
3442                     int width;
3443
3444                     c = arm_decode_bitfield (c, given, &value, &width);
3445
3446                     switch (*c)
3447                       {
3448                       case 'R':
3449                         if (value == 15)
3450                           is_unpredictable = TRUE;
3451                         /* Fall through.  */
3452                       case 'r':
3453                         if (c[1] == 'u')
3454                           {
3455                             /* Eat the 'u' character.  */
3456                             ++ c;
3457
3458                             if (u_reg == value)
3459                               is_unpredictable = TRUE;
3460                             u_reg = value;
3461                           }
3462                         func (stream, "%s", arm_regnames[value]);
3463                         break;
3464                       case 'D':
3465                         func (stream, "d%ld", value);
3466                         break;
3467                       case 'Q':
3468                         if (value & 1)
3469                           func (stream, "<illegal reg q%ld.5>", value >> 1);
3470                         else
3471                           func (stream, "q%ld", value >> 1);
3472                         break;
3473                       case 'd':
3474                         func (stream, "%ld", value);
3475                         value_in_comment = value;
3476                         break;
3477                       case 'E':
3478                         {
3479                           /* Converts immediate 8 bit back to float value.  */
3480                           unsigned floatVal = (value & 0x80) << 24
3481                             | (value & 0x3F) << 19
3482                             | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3483
3484                           /* Quarter float have a maximum value of 31.0.
3485                              Get floating point value multiplied by 1e7.
3486                              The maximum value stays in limit of a 32-bit int.  */
3487                           unsigned decVal =
3488                             (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3489                             (16 + (value & 0xF));
3490
3491                           if (!(decVal % 1000000))
3492                             func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3493                                   floatVal, value & 0x80 ? '-' : ' ',
3494                                   decVal / 10000000,
3495                                   decVal % 10000000 / 1000000);
3496                           else if (!(decVal % 10000))
3497                             func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3498                                   floatVal, value & 0x80 ? '-' : ' ',
3499                                   decVal / 10000000,
3500                                   decVal % 10000000 / 10000);
3501                           else
3502                             func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3503                                   floatVal, value & 0x80 ? '-' : ' ',
3504                                   decVal / 10000000, decVal % 10000000);
3505                           break;
3506                         }
3507                       case 'k':
3508                         {
3509                           int from = (given & (1 << 7)) ? 32 : 16;
3510                           func (stream, "%ld", from - value);
3511                         }
3512                         break;
3513
3514                       case 'f':
3515                         if (value > 7)
3516                           func (stream, "#%s", arm_fp_const[value & 7]);
3517                         else
3518                           func (stream, "f%ld", value);
3519                         break;
3520
3521                       case 'w':
3522                         if (width == 2)
3523                           func (stream, "%s", iwmmxt_wwnames[value]);
3524                         else
3525                           func (stream, "%s", iwmmxt_wwssnames[value]);
3526                         break;
3527
3528                       case 'g':
3529                         func (stream, "%s", iwmmxt_regnames[value]);
3530                         break;
3531                       case 'G':
3532                         func (stream, "%s", iwmmxt_cregnames[value]);
3533                         break;
3534
3535                       case 'x':
3536                         func (stream, "0x%lx", (value & 0xffffffffUL));
3537                         break;
3538
3539                       case 'c':
3540                         switch (value)
3541                           {
3542                           case 0:
3543                             func (stream, "eq");
3544                             break;
3545
3546                           case 1:
3547                             func (stream, "vs");
3548                             break;
3549
3550                           case 2:
3551                             func (stream, "ge");
3552                             break;
3553
3554                           case 3:
3555                             func (stream, "gt");
3556                             break;
3557
3558                           default:
3559                             func (stream, "??");
3560                             break;
3561                           }
3562                         break;
3563
3564                       case '`':
3565                         c++;
3566                         if (value == 0)
3567                           func (stream, "%c", *c);
3568                         break;
3569                       case '\'':
3570                         c++;
3571                         if (value == ((1ul << width) - 1))
3572                           func (stream, "%c", *c);
3573                         break;
3574                       case '?':
3575                         func (stream, "%c", c[(1 << width) - (int) value]);
3576                         c += 1 << width;
3577                         break;
3578                       default:
3579                         abort ();
3580                       }
3581                     break;
3582
3583                   case 'y':
3584                   case 'z':
3585                     {
3586                       int single = *c++ == 'y';
3587                       int regno;
3588
3589                       switch (*c)
3590                         {
3591                         case '4': /* Sm pair */
3592                         case '0': /* Sm, Dm */
3593                           regno = given & 0x0000000f;
3594                           if (single)
3595                             {
3596                               regno <<= 1;
3597                               regno += (given >> 5) & 1;
3598                             }
3599                           else
3600                             regno += ((given >> 5) & 1) << 4;
3601                           break;
3602
3603                         case '1': /* Sd, Dd */
3604                           regno = (given >> 12) & 0x0000000f;
3605                           if (single)
3606                             {
3607                               regno <<= 1;
3608                               regno += (given >> 22) & 1;
3609                             }
3610                           else
3611                             regno += ((given >> 22) & 1) << 4;
3612                           break;
3613
3614                         case '2': /* Sn, Dn */
3615                           regno = (given >> 16) & 0x0000000f;
3616                           if (single)
3617                             {
3618                               regno <<= 1;
3619                               regno += (given >> 7) & 1;
3620                             }
3621                           else
3622                             regno += ((given >> 7) & 1) << 4;
3623                           break;
3624
3625                         case '3': /* List */
3626                           func (stream, "{");
3627                           regno = (given >> 12) & 0x0000000f;
3628                           if (single)
3629                             {
3630                               regno <<= 1;
3631                               regno += (given >> 22) & 1;
3632                             }
3633                           else
3634                             regno += ((given >> 22) & 1) << 4;
3635                           break;
3636
3637                         default:
3638                           abort ();
3639                         }
3640
3641                       func (stream, "%c%d", single ? 's' : 'd', regno);
3642
3643                       if (*c == '3')
3644                         {
3645                           int count = given & 0xff;
3646
3647                           if (single == 0)
3648                             count >>= 1;
3649
3650                           if (--count)
3651                             {
3652                               func (stream, "-%c%d",
3653                                     single ? 's' : 'd',
3654                                     regno + count);
3655                             }
3656
3657                           func (stream, "}");
3658                         }
3659                       else if (*c == '4')
3660                         func (stream, ", %c%d", single ? 's' : 'd',
3661                               regno + 1);
3662                     }
3663                     break;
3664
3665                   case 'L':
3666                     switch (given & 0x00400100)
3667                       {
3668                       case 0x00000000: func (stream, "b"); break;
3669                       case 0x00400000: func (stream, "h"); break;
3670                       case 0x00000100: func (stream, "w"); break;
3671                       case 0x00400100: func (stream, "d"); break;
3672                       default:
3673                         break;
3674                       }
3675                     break;
3676
3677                   case 'Z':
3678                     {
3679                       /* given (20, 23) | given (0, 3) */
3680                       value = ((given >> 16) & 0xf0) | (given & 0xf);
3681                       func (stream, "%d", (int) value);
3682                     }
3683                     break;
3684
3685                   case 'l':
3686                     /* This is like the 'A' operator, except that if
3687                        the width field "M" is zero, then the offset is
3688                        *not* multiplied by four.  */
3689                     {
3690                       int offset = given & 0xff;
3691                       int multiplier = (given & 0x00000100) ? 4 : 1;
3692
3693                       func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3694
3695                       if (multiplier > 1)
3696                         {
3697                           value_in_comment = offset * multiplier;
3698                           if (NEGATIVE_BIT_SET)
3699                             value_in_comment = - value_in_comment;
3700                         }
3701
3702                       if (offset)
3703                         {
3704                           if (PRE_BIT_SET)
3705                             func (stream, ", #%s%d]%s",
3706                                   NEGATIVE_BIT_SET ? "-" : "",
3707                                   offset * multiplier,
3708                                   WRITEBACK_BIT_SET ? "!" : "");
3709                           else
3710                             func (stream, "], #%s%d",
3711                                   NEGATIVE_BIT_SET ? "-" : "",
3712                                   offset * multiplier);
3713                         }
3714                       else
3715                         func (stream, "]");
3716                     }
3717                     break;
3718
3719                   case 'r':
3720                     {
3721                       int imm4 = (given >> 4) & 0xf;
3722                       int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3723                       int ubit = ! NEGATIVE_BIT_SET;
3724                       const char *rm = arm_regnames [given & 0xf];
3725                       const char *rn = arm_regnames [(given >> 16) & 0xf];
3726
3727                       switch (puw_bits)
3728                         {
3729                         case 1:
3730                         case 3:
3731                           func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3732                           if (imm4)
3733                             func (stream, ", lsl #%d", imm4);
3734                           break;
3735
3736                         case 4:
3737                         case 5:
3738                         case 6:
3739                         case 7:
3740                           func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3741                           if (imm4 > 0)
3742                             func (stream, ", lsl #%d", imm4);
3743                           func (stream, "]");
3744                           if (puw_bits == 5 || puw_bits == 7)
3745                             func (stream, "!");
3746                           break;
3747
3748                         default:
3749                           func (stream, "INVALID");
3750                         }
3751                     }
3752                     break;
3753
3754                   case 'i':
3755                     {
3756                       long imm5;
3757                       imm5 = ((given & 0x100) >> 4) | (given & 0xf);
3758                       func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
3759                     }
3760                     break;
3761
3762                   default:
3763                     abort ();
3764                   }
3765                 }
3766             }
3767           else
3768             func (stream, "%c", *c);
3769         }
3770
3771       if (value_in_comment > 32 || value_in_comment < -16)
3772         func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
3773
3774       if (is_unpredictable)
3775         func (stream, UNPREDICTABLE_INSTRUCTION);
3776
3777       return TRUE;
3778     }
3779   return FALSE;
3780 }
3781
3782 /* Decodes and prints ARM addressing modes.  Returns the offset
3783    used in the address, if any, if it is worthwhile printing the
3784    offset as a hexadecimal value in a comment at the end of the
3785    line of disassembly.  */
3786
3787 static signed long
3788 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
3789 {
3790   void *stream = info->stream;
3791   fprintf_ftype func = info->fprintf_func;
3792   bfd_vma offset = 0;
3793
3794   if (((given & 0x000f0000) == 0x000f0000)
3795       && ((given & 0x02000000) == 0))
3796     {
3797       offset = given & 0xfff;
3798
3799       func (stream, "[pc");
3800
3801       if (PRE_BIT_SET)
3802         {
3803           /* Pre-indexed.  Elide offset of positive zero when
3804              non-writeback.  */
3805           if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
3806             func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3807
3808           if (NEGATIVE_BIT_SET)
3809             offset = -offset;
3810
3811           offset += pc + 8;
3812
3813           /* Cope with the possibility of write-back
3814              being used.  Probably a very dangerous thing
3815              for the programmer to do, but who are we to
3816              argue ?  */
3817           func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
3818         }
3819       else  /* Post indexed.  */
3820         {
3821           func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3822
3823           /* Ie ignore the offset.  */
3824           offset = pc + 8;
3825         }
3826
3827       func (stream, "\t; ");
3828       info->print_address_func (offset, info);
3829       offset = 0;
3830     }
3831   else
3832     {
3833       func (stream, "[%s",
3834             arm_regnames[(given >> 16) & 0xf]);
3835
3836       if (PRE_BIT_SET)
3837         {
3838           if ((given & 0x02000000) == 0)
3839             {
3840               /* Elide offset of positive zero when non-writeback.  */
3841               offset = given & 0xfff;
3842               if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
3843                 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3844             }
3845           else
3846             {
3847               func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
3848               arm_decode_shift (given, func, stream, TRUE);
3849             }
3850
3851           func (stream, "]%s",
3852                 WRITEBACK_BIT_SET ? "!" : "");
3853         }
3854       else
3855         {
3856           if ((given & 0x02000000) == 0)
3857             {
3858               /* Always show offset.  */
3859               offset = given & 0xfff;
3860               func (stream, "], #%s%d",
3861                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3862             }
3863           else
3864             {
3865               func (stream, "], %s",
3866                     NEGATIVE_BIT_SET ? "-" : "");
3867               arm_decode_shift (given, func, stream, TRUE);
3868             }
3869         }
3870       if (NEGATIVE_BIT_SET)
3871         offset = -offset;
3872     }
3873
3874   return (signed long) offset;
3875 }
3876
3877 /* Print one neon instruction on INFO->STREAM.
3878    Return TRUE if the instuction matched, FALSE if this is not a
3879    recognised neon instruction.  */
3880
3881 static bfd_boolean
3882 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
3883 {
3884   const struct opcode32 *insn;
3885   void *stream = info->stream;
3886   fprintf_ftype func = info->fprintf_func;
3887
3888   if (thumb)
3889     {
3890       if ((given & 0xef000000) == 0xef000000)
3891         {
3892           /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding.  */
3893           unsigned long bit28 = given & (1 << 28);
3894
3895           given &= 0x00ffffff;
3896           if (bit28)
3897             given |= 0xf3000000;
3898           else
3899             given |= 0xf2000000;
3900         }
3901       else if ((given & 0xff000000) == 0xf9000000)
3902         given ^= 0xf9000000 ^ 0xf4000000;
3903       else
3904         return FALSE;
3905     }
3906
3907   for (insn = neon_opcodes; insn->assembler; insn++)
3908     {
3909       if ((given & insn->mask) == insn->value)
3910         {
3911           signed long value_in_comment = 0;
3912           bfd_boolean is_unpredictable = FALSE;
3913           const char *c;
3914
3915           for (c = insn->assembler; *c; c++)
3916             {
3917               if (*c == '%')
3918                 {
3919                   switch (*++c)
3920                     {
3921                     case '%':
3922                       func (stream, "%%");
3923                       break;
3924
3925                     case 'u':
3926                       if (thumb && ifthen_state)
3927                         is_unpredictable = TRUE;
3928
3929                       /* Fall through.  */
3930                     case 'c':
3931                       if (thumb && ifthen_state)
3932                         func (stream, "%s", arm_conditional[IFTHEN_COND]);
3933                       break;
3934
3935                     case 'A':
3936                       {
3937                         static const unsigned char enc[16] =
3938                         {
3939                           0x4, 0x14, /* st4 0,1 */
3940                           0x4, /* st1 2 */
3941                           0x4, /* st2 3 */
3942                           0x3, /* st3 4 */
3943                           0x13, /* st3 5 */
3944                           0x3, /* st1 6 */
3945                           0x1, /* st1 7 */
3946                           0x2, /* st2 8 */
3947                           0x12, /* st2 9 */
3948                           0x2, /* st1 10 */
3949                           0, 0, 0, 0, 0
3950                         };
3951                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
3952                         int rn = ((given >> 16) & 0xf);
3953                         int rm = ((given >> 0) & 0xf);
3954                         int align = ((given >> 4) & 0x3);
3955                         int type = ((given >> 8) & 0xf);
3956                         int n = enc[type] & 0xf;
3957                         int stride = (enc[type] >> 4) + 1;
3958                         int ix;
3959
3960                         func (stream, "{");
3961                         if (stride > 1)
3962                           for (ix = 0; ix != n; ix++)
3963                             func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
3964                         else if (n == 1)
3965                           func (stream, "d%d", rd);
3966                         else
3967                           func (stream, "d%d-d%d", rd, rd + n - 1);
3968                         func (stream, "}, [%s", arm_regnames[rn]);
3969                         if (align)
3970                           func (stream, " :%d", 32 << align);
3971                         func (stream, "]");
3972                         if (rm == 0xd)
3973                           func (stream, "!");
3974                         else if (rm != 0xf)
3975                           func (stream, ", %s", arm_regnames[rm]);
3976                       }
3977                       break;
3978
3979                     case 'B':
3980                       {
3981                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
3982                         int rn = ((given >> 16) & 0xf);
3983                         int rm = ((given >> 0) & 0xf);
3984                         int idx_align = ((given >> 4) & 0xf);
3985                         int align = 0;
3986                         int size = ((given >> 10) & 0x3);
3987                         int idx = idx_align >> (size + 1);
3988                         int length = ((given >> 8) & 3) + 1;
3989                         int stride = 1;
3990                         int i;
3991
3992                         if (length > 1 && size > 0)
3993                           stride = (idx_align & (1 << size)) ? 2 : 1;
3994
3995                         switch (length)
3996                           {
3997                           case 1:
3998                             {
3999                               int amask = (1 << size) - 1;
4000                               if ((idx_align & (1 << size)) != 0)
4001                                 return FALSE;
4002                               if (size > 0)
4003                                 {
4004                                   if ((idx_align & amask) == amask)
4005                                     align = 8 << size;
4006                                   else if ((idx_align & amask) != 0)
4007                                     return FALSE;
4008                                 }
4009                               }
4010                             break;
4011
4012                           case 2:
4013                             if (size == 2 && (idx_align & 2) != 0)
4014                               return FALSE;
4015                             align = (idx_align & 1) ? 16 << size : 0;
4016                             break;
4017
4018                           case 3:
4019                             if ((size == 2 && (idx_align & 3) != 0)
4020                                 || (idx_align & 1) != 0)
4021                               return FALSE;
4022                             break;
4023
4024                           case 4:
4025                             if (size == 2)
4026                               {
4027                                 if ((idx_align & 3) == 3)
4028                                   return FALSE;
4029                                 align = (idx_align & 3) * 64;
4030                               }
4031                             else
4032                               align = (idx_align & 1) ? 32 << size : 0;
4033                             break;
4034
4035                           default:
4036                             abort ();
4037                           }
4038
4039                         func (stream, "{");
4040                         for (i = 0; i < length; i++)
4041                           func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4042                             rd + i * stride, idx);
4043                         func (stream, "}, [%s", arm_regnames[rn]);
4044                         if (align)
4045                           func (stream, " :%d", align);
4046                         func (stream, "]");
4047                         if (rm == 0xd)
4048                           func (stream, "!");
4049                         else if (rm != 0xf)
4050                           func (stream, ", %s", arm_regnames[rm]);
4051                       }
4052                       break;
4053
4054                     case 'C':
4055                       {
4056                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4057                         int rn = ((given >> 16) & 0xf);
4058                         int rm = ((given >> 0) & 0xf);
4059                         int align = ((given >> 4) & 0x1);
4060                         int size = ((given >> 6) & 0x3);
4061                         int type = ((given >> 8) & 0x3);
4062                         int n = type + 1;
4063                         int stride = ((given >> 5) & 0x1);
4064                         int ix;
4065
4066                         if (stride && (n == 1))
4067                           n++;
4068                         else
4069                           stride++;
4070
4071                         func (stream, "{");
4072                         if (stride > 1)
4073                           for (ix = 0; ix != n; ix++)
4074                             func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4075                         else if (n == 1)
4076                           func (stream, "d%d[]", rd);
4077                         else
4078                           func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4079                         func (stream, "}, [%s", arm_regnames[rn]);
4080                         if (align)
4081                           {
4082                             align = (8 * (type + 1)) << size;
4083                             if (type == 3)
4084                               align = (size > 1) ? align >> 1 : align;
4085                             if (type == 2 || (type == 0 && !size))
4086                               func (stream, " :<bad align %d>", align);
4087                             else
4088                               func (stream, " :%d", align);
4089                           }
4090                         func (stream, "]");
4091                         if (rm == 0xd)
4092                           func (stream, "!");
4093                         else if (rm != 0xf)
4094                           func (stream, ", %s", arm_regnames[rm]);
4095                       }
4096                       break;
4097
4098                     case 'D':
4099                       {
4100                         int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4101                         int size = (given >> 20) & 3;
4102                         int reg = raw_reg & ((4 << size) - 1);
4103                         int ix = raw_reg >> size >> 2;
4104
4105                         func (stream, "d%d[%d]", reg, ix);
4106                       }
4107                       break;
4108
4109                     case 'E':
4110                       /* Neon encoded constant for mov, mvn, vorr, vbic.  */
4111                       {
4112                         int bits = 0;
4113                         int cmode = (given >> 8) & 0xf;
4114                         int op = (given >> 5) & 0x1;
4115                         unsigned long value = 0, hival = 0;
4116                         unsigned shift;
4117                         int size = 0;
4118                         int isfloat = 0;
4119
4120                         bits |= ((given >> 24) & 1) << 7;
4121                         bits |= ((given >> 16) & 7) << 4;
4122                         bits |= ((given >> 0) & 15) << 0;
4123
4124                         if (cmode < 8)
4125                           {
4126                             shift = (cmode >> 1) & 3;
4127                             value = (unsigned long) bits << (8 * shift);
4128                             size = 32;
4129                           }
4130                         else if (cmode < 12)
4131                           {
4132                             shift = (cmode >> 1) & 1;
4133                             value = (unsigned long) bits << (8 * shift);
4134                             size = 16;
4135                           }
4136                         else if (cmode < 14)
4137                           {
4138                             shift = (cmode & 1) + 1;
4139                             value = (unsigned long) bits << (8 * shift);
4140                             value |= (1ul << (8 * shift)) - 1;
4141                             size = 32;
4142                           }
4143                         else if (cmode == 14)
4144                           {
4145                             if (op)
4146                               {
4147                                 /* Bit replication into bytes.  */
4148                                 int ix;
4149                                 unsigned long mask;
4150
4151                                 value = 0;
4152                                 hival = 0;
4153                                 for (ix = 7; ix >= 0; ix--)
4154                                   {
4155                                     mask = ((bits >> ix) & 1) ? 0xff : 0;
4156                                     if (ix <= 3)
4157                                       value = (value << 8) | mask;
4158                                     else
4159                                       hival = (hival << 8) | mask;
4160                                   }
4161                                 size = 64;
4162                               }
4163                             else
4164                               {
4165                                 /* Byte replication.  */
4166                                 value = (unsigned long) bits;
4167                                 size = 8;
4168                               }
4169                           }
4170                         else if (!op)
4171                           {
4172                             /* Floating point encoding.  */
4173                             int tmp;
4174
4175                             value = (unsigned long)  (bits & 0x7f) << 19;
4176                             value |= (unsigned long) (bits & 0x80) << 24;
4177                             tmp = bits & 0x40 ? 0x3c : 0x40;
4178                             value |= (unsigned long) tmp << 24;
4179                             size = 32;
4180                             isfloat = 1;
4181                           }
4182                         else
4183                           {
4184                             func (stream, "<illegal constant %.8x:%x:%x>",
4185                                   bits, cmode, op);
4186                             size = 32;
4187                             break;
4188                           }
4189                         switch (size)
4190                           {
4191                           case 8:
4192                             func (stream, "#%ld\t; 0x%.2lx", value, value);
4193                             break;
4194
4195                           case 16:
4196                             func (stream, "#%ld\t; 0x%.4lx", value, value);
4197                             break;
4198
4199                           case 32:
4200                             if (isfloat)
4201                               {
4202                                 unsigned char valbytes[4];
4203                                 double fvalue;
4204
4205                                 /* Do this a byte at a time so we don't have to
4206                                    worry about the host's endianness.  */
4207                                 valbytes[0] = value & 0xff;
4208                                 valbytes[1] = (value >> 8) & 0xff;
4209                                 valbytes[2] = (value >> 16) & 0xff;
4210                                 valbytes[3] = (value >> 24) & 0xff;
4211
4212                                 floatformat_to_double
4213                                   (& floatformat_ieee_single_little, valbytes,
4214                                   & fvalue);
4215
4216                                 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4217                                       value);
4218                               }
4219                             else
4220                               func (stream, "#%ld\t; 0x%.8lx",
4221                                     (long) (((value & 0x80000000L) != 0)
4222                                             ? value | ~0xffffffffL : value),
4223                                     value);
4224                             break;
4225
4226                           case 64:
4227                             func (stream, "#0x%.8lx%.8lx", hival, value);
4228                             break;
4229
4230                           default:
4231                             abort ();
4232                           }
4233                       }
4234                       break;
4235
4236                     case 'F':
4237                       {
4238                         int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4239                         int num = (given >> 8) & 0x3;
4240
4241                         if (!num)
4242                           func (stream, "{d%d}", regno);
4243                         else if (num + regno >= 32)
4244                           func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4245                         else
4246                           func (stream, "{d%d-d%d}", regno, regno + num);
4247                       }
4248                       break;
4249
4250
4251                     case '0': case '1': case '2': case '3': case '4':
4252                     case '5': case '6': case '7': case '8': case '9':
4253                       {
4254                         int width;
4255                         unsigned long value;
4256
4257                         c = arm_decode_bitfield (c, given, &value, &width);
4258
4259                         switch (*c)
4260                           {
4261                           case 'r':
4262                             func (stream, "%s", arm_regnames[value]);
4263                             break;
4264                           case 'd':
4265                             func (stream, "%ld", value);
4266                             value_in_comment = value;
4267                             break;
4268                           case 'e':
4269                             func (stream, "%ld", (1ul << width) - value);
4270                             break;
4271
4272                           case 'S':
4273                           case 'T':
4274                           case 'U':
4275                             /* Various width encodings.  */
4276                             {
4277                               int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4278                               int limit;
4279                               unsigned low, high;
4280
4281                               c++;
4282                               if (*c >= '0' && *c <= '9')
4283                                 limit = *c - '0';
4284                               else if (*c >= 'a' && *c <= 'f')
4285                                 limit = *c - 'a' + 10;
4286                               else
4287                                 abort ();
4288                               low = limit >> 2;
4289                               high = limit & 3;
4290
4291                               if (value < low || value > high)
4292                                 func (stream, "<illegal width %d>", base << value);
4293                               else
4294                                 func (stream, "%d", base << value);
4295                             }
4296                             break;
4297                           case 'R':
4298                             if (given & (1 << 6))
4299                               goto Q;
4300                             /* FALLTHROUGH */
4301                           case 'D':
4302                             func (stream, "d%ld", value);
4303                             break;
4304                           case 'Q':
4305                           Q:
4306                             if (value & 1)
4307                               func (stream, "<illegal reg q%ld.5>", value >> 1);
4308                             else
4309                               func (stream, "q%ld", value >> 1);
4310                             break;
4311
4312                           case '`':
4313                             c++;
4314                             if (value == 0)
4315                               func (stream, "%c", *c);
4316                             break;
4317                           case '\'':
4318                             c++;
4319                             if (value == ((1ul << width) - 1))
4320                               func (stream, "%c", *c);
4321                             break;
4322                           case '?':
4323                             func (stream, "%c", c[(1 << width) - (int) value]);
4324                             c += 1 << width;
4325                             break;
4326                           default:
4327                             abort ();
4328                           }
4329                         break;
4330
4331                       default:
4332                         abort ();
4333                       }
4334                     }
4335                 }
4336               else
4337                 func (stream, "%c", *c);
4338             }
4339
4340           if (value_in_comment > 32 || value_in_comment < -16)
4341             func (stream, "\t; 0x%lx", value_in_comment);
4342
4343           if (is_unpredictable)
4344             func (stream, UNPREDICTABLE_INSTRUCTION);
4345
4346           return TRUE;
4347         }
4348     }
4349   return FALSE;
4350 }
4351
4352 /* Return the name of a v7A special register.  */
4353
4354 static const char *
4355 banked_regname (unsigned reg)
4356 {
4357   switch (reg)
4358     {
4359       case 15: return "CPSR";
4360       case 32: return "R8_usr";
4361       case 33: return "R9_usr";
4362       case 34: return "R10_usr";
4363       case 35: return "R11_usr";
4364       case 36: return "R12_usr";
4365       case 37: return "SP_usr";
4366       case 38: return "LR_usr";
4367       case 40: return "R8_fiq";
4368       case 41: return "R9_fiq";
4369       case 42: return "R10_fiq";
4370       case 43: return "R11_fiq";
4371       case 44: return "R12_fiq";
4372       case 45: return "SP_fiq";
4373       case 46: return "LR_fiq";
4374       case 48: return "LR_irq";
4375       case 49: return "SP_irq";
4376       case 50: return "LR_svc";
4377       case 51: return "SP_svc";
4378       case 52: return "LR_abt";
4379       case 53: return "SP_abt";
4380       case 54: return "LR_und";
4381       case 55: return "SP_und";
4382       case 60: return "LR_mon";
4383       case 61: return "SP_mon";
4384       case 62: return "ELR_hyp";
4385       case 63: return "SP_hyp";
4386       case 79: return "SPSR";
4387       case 110: return "SPSR_fiq";
4388       case 112: return "SPSR_irq";
4389       case 114: return "SPSR_svc";
4390       case 116: return "SPSR_abt";
4391       case 118: return "SPSR_und";
4392       case 124: return "SPSR_mon";
4393       case 126: return "SPSR_hyp";
4394       default: return NULL;
4395     }
4396 }
4397
4398 /* Return the name of the DMB/DSB option.  */
4399 static const char *
4400 data_barrier_option (unsigned option)
4401 {
4402   switch (option & 0xf)
4403     {
4404     case 0xf: return "sy";
4405     case 0xe: return "st";
4406     case 0xd: return "ld";
4407     case 0xb: return "ish";
4408     case 0xa: return "ishst";
4409     case 0x9: return "ishld";
4410     case 0x7: return "un";
4411     case 0x6: return "unst";
4412     case 0x5: return "nshld";
4413     case 0x3: return "osh";
4414     case 0x2: return "oshst";
4415     case 0x1: return "oshld";
4416     default:  return NULL;
4417     }
4418 }
4419
4420 /* Print one ARM instruction from PC on INFO->STREAM.  */
4421
4422 static void
4423 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
4424 {
4425   const struct opcode32 *insn;
4426   void *stream = info->stream;
4427   fprintf_ftype func = info->fprintf_func;
4428   struct arm_private_data *private_data = info->private_data;
4429
4430   if (print_insn_coprocessor (pc, info, given, FALSE))
4431     return;
4432
4433   if (print_insn_neon (info, given, FALSE))
4434     return;
4435
4436   for (insn = arm_opcodes; insn->assembler; insn++)
4437     {
4438       if ((given & insn->mask) != insn->value)
4439         continue;
4440
4441       if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
4442         continue;
4443
4444       /* Special case: an instruction with all bits set in the condition field
4445          (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4446          or by the catchall at the end of the table.  */
4447       if ((given & 0xF0000000) != 0xF0000000
4448           || (insn->mask & 0xF0000000) == 0xF0000000
4449           || (insn->mask == 0 && insn->value == 0))
4450         {
4451           unsigned long u_reg = 16;
4452           unsigned long U_reg = 16;
4453           bfd_boolean is_unpredictable = FALSE;
4454           signed long value_in_comment = 0;
4455           const char *c;
4456
4457           for (c = insn->assembler; *c; c++)
4458             {
4459               if (*c == '%')
4460                 {
4461                   bfd_boolean allow_unpredictable = FALSE;
4462
4463                   switch (*++c)
4464                     {
4465                     case '%':
4466                       func (stream, "%%");
4467                       break;
4468
4469                     case 'a':
4470                       value_in_comment = print_arm_address (pc, info, given);
4471                       break;
4472
4473                     case 'P':
4474                       /* Set P address bit and use normal address
4475                          printing routine.  */
4476                       value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
4477                       break;
4478
4479                     case 'S':
4480                       allow_unpredictable = TRUE;
4481                     case 's':
4482                       if ((given & 0x004f0000) == 0x004f0000)
4483                         {
4484                           /* PC relative with immediate offset.  */
4485                           bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
4486
4487                           if (PRE_BIT_SET)
4488                             {
4489                               /* Elide positive zero offset.  */
4490                               if (offset || NEGATIVE_BIT_SET)
4491                                 func (stream, "[pc, #%s%d]\t; ",
4492                                       NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4493                               else
4494                                 func (stream, "[pc]\t; ");
4495                               if (NEGATIVE_BIT_SET)
4496                                 offset = -offset;
4497                               info->print_address_func (offset + pc + 8, info);
4498                             }
4499                           else
4500                             {
4501                               /* Always show the offset.  */
4502                               func (stream, "[pc], #%s%d",
4503                                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4504                               if (! allow_unpredictable)
4505                                 is_unpredictable = TRUE;
4506                             }
4507                         }
4508                       else
4509                         {
4510                           int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4511
4512                           func (stream, "[%s",
4513                                 arm_regnames[(given >> 16) & 0xf]);
4514
4515                           if (PRE_BIT_SET)
4516                             {
4517                               if (IMMEDIATE_BIT_SET)
4518                                 {
4519                                   /* Elide offset for non-writeback
4520                                      positive zero.  */
4521                                   if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4522                                       || offset)
4523                                     func (stream, ", #%s%d",
4524                                           NEGATIVE_BIT_SET ? "-" : "", offset);
4525
4526                                   if (NEGATIVE_BIT_SET)
4527                                     offset = -offset;
4528
4529                                   value_in_comment = offset;
4530                                 }
4531                               else
4532                                 {
4533                                   /* Register Offset or Register Pre-Indexed.  */
4534                                   func (stream, ", %s%s",
4535                                         NEGATIVE_BIT_SET ? "-" : "",
4536                                         arm_regnames[given & 0xf]);
4537
4538                                   /* Writing back to the register that is the source/
4539                                      destination of the load/store is unpredictable.  */
4540                                   if (! allow_unpredictable
4541                                       && WRITEBACK_BIT_SET
4542                                       && ((given & 0xf) == ((given >> 12) & 0xf)))
4543                                     is_unpredictable = TRUE;
4544                                 }
4545
4546                               func (stream, "]%s",
4547                                     WRITEBACK_BIT_SET ? "!" : "");
4548                             }
4549                           else
4550                             {
4551                               if (IMMEDIATE_BIT_SET)
4552                                 {
4553                                   /* Immediate Post-indexed.  */
4554                                   /* PR 10924: Offset must be printed, even if it is zero.  */
4555                                   func (stream, "], #%s%d",
4556                                         NEGATIVE_BIT_SET ? "-" : "", offset);
4557                                   if (NEGATIVE_BIT_SET)
4558                                     offset = -offset;
4559                                   value_in_comment = offset;
4560                                 }
4561                               else
4562                                 {
4563                                   /* Register Post-indexed.  */
4564                                   func (stream, "], %s%s",
4565                                         NEGATIVE_BIT_SET ? "-" : "",
4566                                         arm_regnames[given & 0xf]);
4567
4568                                   /* Writing back to the register that is the source/
4569                                      destination of the load/store is unpredictable.  */
4570                                   if (! allow_unpredictable
4571                                       && (given & 0xf) == ((given >> 12) & 0xf))
4572                                     is_unpredictable = TRUE;
4573                                 }
4574
4575                               if (! allow_unpredictable)
4576                                 {
4577                                   /* Writeback is automatically implied by post- addressing.
4578                                      Setting the W bit is unnecessary and ARM specify it as
4579                                      being unpredictable.  */
4580                                   if (WRITEBACK_BIT_SET
4581                                       /* Specifying the PC register as the post-indexed
4582                                          registers is also unpredictable.  */
4583                                       || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4584                                     is_unpredictable = TRUE;
4585                                 }
4586                             }
4587                         }
4588                       break;
4589
4590                     case 'b':
4591                       {
4592                         bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
4593                         info->print_address_func (disp * 4 + pc + 8, info);
4594                       }
4595                       break;
4596
4597                     case 'c':
4598                       if (((given >> 28) & 0xf) != 0xe)
4599                         func (stream, "%s",
4600                               arm_conditional [(given >> 28) & 0xf]);
4601                       break;
4602
4603                     case 'm':
4604                       {
4605                         int started = 0;
4606                         int reg;
4607
4608                         func (stream, "{");
4609                         for (reg = 0; reg < 16; reg++)
4610                           if ((given & (1 << reg)) != 0)
4611                             {
4612                               if (started)
4613                                 func (stream, ", ");
4614                               started = 1;
4615                               func (stream, "%s", arm_regnames[reg]);
4616                             }
4617                         func (stream, "}");
4618                         if (! started)
4619                           is_unpredictable = TRUE;
4620                       }
4621                       break;
4622
4623                     case 'q':
4624                       arm_decode_shift (given, func, stream, FALSE);
4625                       break;
4626
4627                     case 'o':
4628                       if ((given & 0x02000000) != 0)
4629                         {
4630                           unsigned int rotate = (given & 0xf00) >> 7;
4631                           unsigned int immed = (given & 0xff);
4632                           unsigned int a, i;
4633
4634                           a = (((immed << (32 - rotate))
4635                                 | (immed >> rotate)) & 0xffffffff);
4636                           /* If there is another encoding with smaller rotate,
4637                              the rotate should be specified directly.  */
4638                           for (i = 0; i < 32; i += 2)
4639                             if ((a << i | a >> (32 - i)) <= 0xff)
4640                               break;
4641
4642                           if (i != rotate)
4643                             func (stream, "#%d, %d", immed, rotate);
4644                           else
4645                             func (stream, "#%d", a);
4646                           value_in_comment = a;
4647                         }
4648                       else
4649                         arm_decode_shift (given, func, stream, TRUE);
4650                       break;
4651
4652                     case 'p':
4653                       if ((given & 0x0000f000) == 0x0000f000)
4654                         {
4655                           arm_feature_set arm_ext_v6 =
4656                             ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4657
4658                           /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4659                              mechanism for setting PSR flag bits.  They are
4660                              obsolete in V6 onwards.  */
4661                           if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4662                                                      arm_ext_v6))
4663                             func (stream, "p");
4664                           else
4665                             is_unpredictable = TRUE;
4666                         }
4667                       break;
4668
4669                     case 't':
4670                       if ((given & 0x01200000) == 0x00200000)
4671                         func (stream, "t");
4672                       break;
4673
4674                     case 'A':
4675                       {
4676                         int offset = given & 0xff;
4677
4678                         value_in_comment = offset * 4;
4679                         if (NEGATIVE_BIT_SET)
4680                           value_in_comment = - value_in_comment;
4681
4682                         func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
4683
4684                         if (PRE_BIT_SET)
4685                           {
4686                             if (offset)
4687                               func (stream, ", #%d]%s",
4688                                     (int) value_in_comment,
4689                                     WRITEBACK_BIT_SET ? "!" : "");
4690                             else
4691                               func (stream, "]");
4692                           }
4693                         else
4694                           {
4695                             func (stream, "]");
4696
4697                             if (WRITEBACK_BIT_SET)
4698                               {
4699                                 if (offset)
4700                                   func (stream, ", #%d", (int) value_in_comment);
4701                               }
4702                             else
4703                               {
4704                                 func (stream, ", {%d}", (int) offset);
4705                                 value_in_comment = offset;
4706                               }
4707                           }
4708                       }
4709                       break;
4710
4711                     case 'B':
4712                       /* Print ARM V5 BLX(1) address: pc+25 bits.  */
4713                       {
4714                         bfd_vma address;
4715                         bfd_vma offset = 0;
4716
4717                         if (! NEGATIVE_BIT_SET)
4718                           /* Is signed, hi bits should be ones.  */
4719                           offset = (-1) ^ 0x00ffffff;
4720
4721                         /* Offset is (SignExtend(offset field)<<2).  */
4722                         offset += given & 0x00ffffff;
4723                         offset <<= 2;
4724                         address = offset + pc + 8;
4725
4726                         if (given & 0x01000000)
4727                           /* H bit allows addressing to 2-byte boundaries.  */
4728                           address += 2;
4729
4730                         info->print_address_func (address, info);
4731                       }
4732                       break;
4733
4734                     case 'C':
4735                       if ((given & 0x02000200) == 0x200)
4736                         {
4737                           const char * name;
4738                           unsigned sysm = (given & 0x004f0000) >> 16;
4739
4740                           sysm |= (given & 0x300) >> 4;
4741                           name = banked_regname (sysm);
4742
4743                           if (name != NULL)
4744                             func (stream, "%s", name);
4745                           else
4746                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
4747                         }
4748                       else
4749                         {
4750                           func (stream, "%cPSR_",
4751                                 (given & 0x00400000) ? 'S' : 'C');
4752                           if (given & 0x80000)
4753                             func (stream, "f");
4754                           if (given & 0x40000)
4755                             func (stream, "s");
4756                           if (given & 0x20000)
4757                             func (stream, "x");
4758                           if (given & 0x10000)
4759                             func (stream, "c");
4760                         }
4761                       break;
4762
4763                     case 'U':
4764                       if ((given & 0xf0) == 0x60)
4765                         {
4766                           switch (given & 0xf)
4767                             {
4768                             case 0xf: func (stream, "sy"); break;
4769                             default:
4770                               func (stream, "#%d", (int) given & 0xf);
4771                               break;
4772                             }
4773                         }
4774                       else
4775                         {
4776                           const char * opt = data_barrier_option (given & 0xf);
4777                           if (opt != NULL)
4778                             func (stream, "%s", opt);
4779                           else
4780                               func (stream, "#%d", (int) given & 0xf);
4781                         }
4782                       break;
4783
4784                     case '0': case '1': case '2': case '3': case '4':
4785                     case '5': case '6': case '7': case '8': case '9':
4786                       {
4787                         int width;
4788                         unsigned long value;
4789
4790                         c = arm_decode_bitfield (c, given, &value, &width);
4791
4792                         switch (*c)
4793                           {
4794                           case 'R':
4795                             if (value == 15)
4796                               is_unpredictable = TRUE;
4797                             /* Fall through.  */
4798                           case 'r':
4799                           case 'T':
4800                             /* We want register + 1 when decoding T.  */
4801                             if (*c == 'T')
4802                               ++value;
4803
4804                             if (c[1] == 'u')
4805                               {
4806                                 /* Eat the 'u' character.  */
4807                                 ++ c;
4808
4809                                 if (u_reg == value)
4810                                   is_unpredictable = TRUE;
4811                                 u_reg = value;
4812                               }
4813                             if (c[1] == 'U')
4814                               {
4815                                 /* Eat the 'U' character.  */
4816                                 ++ c;
4817
4818                                 if (U_reg == value)
4819                                   is_unpredictable = TRUE;
4820                                 U_reg = value;
4821                               }
4822                             func (stream, "%s", arm_regnames[value]);
4823                             break;
4824                           case 'd':
4825                             func (stream, "%ld", value);
4826                             value_in_comment = value;
4827                             break;
4828                           case 'b':
4829                             func (stream, "%ld", value * 8);
4830                             value_in_comment = value * 8;
4831                             break;
4832                           case 'W':
4833                             func (stream, "%ld", value + 1);
4834                             value_in_comment = value + 1;
4835                             break;
4836                           case 'x':
4837                             func (stream, "0x%08lx", value);
4838
4839                             /* Some SWI instructions have special
4840                                meanings.  */
4841                             if ((given & 0x0fffffff) == 0x0FF00000)
4842                               func (stream, "\t; IMB");
4843                             else if ((given & 0x0fffffff) == 0x0FF00001)
4844                               func (stream, "\t; IMBRange");
4845                             break;
4846                           case 'X':
4847                             func (stream, "%01lx", value & 0xf);
4848                             value_in_comment = value;
4849                             break;
4850                           case '`':
4851                             c++;
4852                             if (value == 0)
4853                               func (stream, "%c", *c);
4854                             break;
4855                           case '\'':
4856                             c++;
4857                             if (value == ((1ul << width) - 1))
4858                               func (stream, "%c", *c);
4859                             break;
4860                           case '?':
4861                             func (stream, "%c", c[(1 << width) - (int) value]);
4862                             c += 1 << width;
4863                             break;
4864                           default:
4865                             abort ();
4866                           }
4867                         break;
4868
4869                       case 'e':
4870                         {
4871                           int imm;
4872
4873                           imm = (given & 0xf) | ((given & 0xfff00) >> 4);
4874                           func (stream, "%d", imm);
4875                           value_in_comment = imm;
4876                         }
4877                         break;
4878
4879                       case 'E':
4880                         /* LSB and WIDTH fields of BFI or BFC.  The machine-
4881                            language instruction encodes LSB and MSB.  */
4882                         {
4883                           long msb = (given & 0x001f0000) >> 16;
4884                           long lsb = (given & 0x00000f80) >> 7;
4885                           long w = msb - lsb + 1;
4886
4887                           if (w > 0)
4888                             func (stream, "#%lu, #%lu", lsb, w);
4889                           else
4890                             func (stream, "(invalid: %lu:%lu)", lsb, msb);
4891                         }
4892                         break;
4893
4894                       case 'R':
4895                         /* Get the PSR/banked register name.  */
4896                         {
4897                           const char * name;
4898                           unsigned sysm = (given & 0x004f0000) >> 16;
4899
4900                           sysm |= (given & 0x300) >> 4;
4901                           name = banked_regname (sysm);
4902
4903                           if (name != NULL)
4904                             func (stream, "%s", name);
4905                           else
4906                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
4907                         }
4908                         break;
4909
4910                       case 'V':
4911                         /* 16-bit unsigned immediate from a MOVT or MOVW
4912                            instruction, encoded in bits 0:11 and 15:19.  */
4913                         {
4914                           long hi = (given & 0x000f0000) >> 4;
4915                           long lo = (given & 0x00000fff);
4916                           long imm16 = hi | lo;
4917
4918                           func (stream, "#%lu", imm16);
4919                           value_in_comment = imm16;
4920                         }
4921                         break;
4922
4923                       default:
4924                         abort ();
4925                       }
4926                     }
4927                 }
4928               else
4929                 func (stream, "%c", *c);
4930             }
4931
4932           if (value_in_comment > 32 || value_in_comment < -16)
4933             func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
4934
4935           if (is_unpredictable)
4936             func (stream, UNPREDICTABLE_INSTRUCTION);
4937
4938           return;
4939         }
4940     }
4941   abort ();
4942 }
4943
4944 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM.  */
4945
4946 static void
4947 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
4948 {
4949   const struct opcode16 *insn;
4950   void *stream = info->stream;
4951   fprintf_ftype func = info->fprintf_func;
4952
4953   for (insn = thumb_opcodes; insn->assembler; insn++)
4954     if ((given & insn->mask) == insn->value)
4955       {
4956         signed long value_in_comment = 0;
4957         const char *c = insn->assembler;
4958
4959         for (; *c; c++)
4960           {
4961             int domaskpc = 0;
4962             int domasklr = 0;
4963
4964             if (*c != '%')
4965               {
4966                 func (stream, "%c", *c);
4967                 continue;
4968               }
4969
4970             switch (*++c)
4971               {
4972               case '%':
4973                 func (stream, "%%");
4974                 break;
4975
4976               case 'c':
4977                 if (ifthen_state)
4978                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
4979                 break;
4980
4981               case 'C':
4982                 if (ifthen_state)
4983                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
4984                 else
4985                   func (stream, "s");
4986                 break;
4987
4988               case 'I':
4989                 {
4990                   unsigned int tmp;
4991
4992                   ifthen_next_state = given & 0xff;
4993                   for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
4994                     func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
4995                   func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
4996                 }
4997                 break;
4998
4999               case 'x':
5000                 if (ifthen_next_state)
5001                   func (stream, "\t; unpredictable branch in IT block\n");
5002                 break;
5003
5004               case 'X':
5005                 if (ifthen_state)
5006                   func (stream, "\t; unpredictable <IT:%s>",
5007                         arm_conditional[IFTHEN_COND]);
5008                 break;
5009
5010               case 'S':
5011                 {
5012                   long reg;
5013
5014                   reg = (given >> 3) & 0x7;
5015                   if (given & (1 << 6))
5016                     reg += 8;
5017
5018                   func (stream, "%s", arm_regnames[reg]);
5019                 }
5020                 break;
5021
5022               case 'D':
5023                 {
5024                   long reg;
5025
5026                   reg = given & 0x7;
5027                   if (given & (1 << 7))
5028                     reg += 8;
5029
5030                   func (stream, "%s", arm_regnames[reg]);
5031                 }
5032                 break;
5033
5034               case 'N':
5035                 if (given & (1 << 8))
5036                   domasklr = 1;
5037                 /* Fall through.  */
5038               case 'O':
5039                 if (*c == 'O' && (given & (1 << 8)))
5040                   domaskpc = 1;
5041                 /* Fall through.  */
5042               case 'M':
5043                 {
5044                   int started = 0;
5045                   int reg;
5046
5047                   func (stream, "{");
5048
5049                   /* It would be nice if we could spot
5050                      ranges, and generate the rS-rE format: */
5051                   for (reg = 0; (reg < 8); reg++)
5052                     if ((given & (1 << reg)) != 0)
5053                       {
5054                         if (started)
5055                           func (stream, ", ");
5056                         started = 1;
5057                         func (stream, "%s", arm_regnames[reg]);
5058                       }
5059
5060                   if (domasklr)
5061                     {
5062                       if (started)
5063                         func (stream, ", ");
5064                       started = 1;
5065                       func (stream, "%s", arm_regnames[14] /* "lr" */);
5066                     }
5067
5068                   if (domaskpc)
5069                     {
5070                       if (started)
5071                         func (stream, ", ");
5072                       func (stream, "%s", arm_regnames[15] /* "pc" */);
5073                     }
5074
5075                   func (stream, "}");
5076                 }
5077                 break;
5078
5079               case 'W':
5080                 /* Print writeback indicator for a LDMIA.  We are doing a
5081                    writeback if the base register is not in the register
5082                    mask.  */
5083                 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5084                   func (stream, "!");
5085                 break;
5086
5087               case 'b':
5088                 /* Print ARM V6T2 CZB address: pc+4+6 bits.  */
5089                 {
5090                   bfd_vma address = (pc + 4
5091                                      + ((given & 0x00f8) >> 2)
5092                                      + ((given & 0x0200) >> 3));
5093                   info->print_address_func (address, info);
5094                 }
5095                 break;
5096
5097               case 's':
5098                 /* Right shift immediate -- bits 6..10; 1-31 print
5099                    as themselves, 0 prints as 32.  */
5100                 {
5101                   long imm = (given & 0x07c0) >> 6;
5102                   if (imm == 0)
5103                     imm = 32;
5104                   func (stream, "#%ld", imm);
5105                 }
5106                 break;
5107
5108               case '0': case '1': case '2': case '3': case '4':
5109               case '5': case '6': case '7': case '8': case '9':
5110                 {
5111                   int bitstart = *c++ - '0';
5112                   int bitend = 0;
5113
5114                   while (*c >= '0' && *c <= '9')
5115                     bitstart = (bitstart * 10) + *c++ - '0';
5116
5117                   switch (*c)
5118                     {
5119                     case '-':
5120                       {
5121                         bfd_vma reg;
5122
5123                         c++;
5124                         while (*c >= '0' && *c <= '9')
5125                           bitend = (bitend * 10) + *c++ - '0';
5126                         if (!bitend)
5127                           abort ();
5128                         reg = given >> bitstart;
5129                         reg &= (2 << (bitend - bitstart)) - 1;
5130
5131                         switch (*c)
5132                           {
5133                           case 'r':
5134                             func (stream, "%s", arm_regnames[reg]);
5135                             break;
5136
5137                           case 'd':
5138                             func (stream, "%ld", (long) reg);
5139                             value_in_comment = reg;
5140                             break;
5141
5142                           case 'H':
5143                             func (stream, "%ld", (long) (reg << 1));
5144                             value_in_comment = reg << 1;
5145                             break;
5146
5147                           case 'W':
5148                             func (stream, "%ld", (long) (reg << 2));
5149                             value_in_comment = reg << 2;
5150                             break;
5151
5152                           case 'a':
5153                             /* PC-relative address -- the bottom two
5154                                bits of the address are dropped
5155                                before the calculation.  */
5156                             info->print_address_func
5157                               (((pc + 4) & ~3) + (reg << 2), info);
5158                             value_in_comment = 0;
5159                             break;
5160
5161                           case 'x':
5162                             func (stream, "0x%04lx", (long) reg);
5163                             break;
5164
5165                           case 'B':
5166                             reg = ((reg ^ (1 << bitend)) - (1 << bitend));
5167                             info->print_address_func (reg * 2 + pc + 4, info);
5168                             value_in_comment = 0;
5169                             break;
5170
5171                           case 'c':
5172                             func (stream, "%s", arm_conditional [reg]);
5173                             break;
5174
5175                           default:
5176                             abort ();
5177                           }
5178                       }
5179                       break;
5180
5181                     case '\'':
5182                       c++;
5183                       if ((given & (1 << bitstart)) != 0)
5184                         func (stream, "%c", *c);
5185                       break;
5186
5187                     case '?':
5188                       ++c;
5189                       if ((given & (1 << bitstart)) != 0)
5190                         func (stream, "%c", *c++);
5191                       else
5192                         func (stream, "%c", *++c);
5193                       break;
5194
5195                     default:
5196                       abort ();
5197                     }
5198                 }
5199                 break;
5200
5201               default:
5202                 abort ();
5203               }
5204           }
5205
5206         if (value_in_comment > 32 || value_in_comment < -16)
5207           func (stream, "\t; 0x%lx", value_in_comment);
5208         return;
5209       }
5210
5211   /* No match.  */
5212   abort ();
5213 }
5214
5215 /* Return the name of an V7M special register.  */
5216
5217 static const char *
5218 psr_name (int regno)
5219 {
5220   switch (regno)
5221     {
5222     case 0: return "APSR";
5223     case 1: return "IAPSR";
5224     case 2: return "EAPSR";
5225     case 3: return "PSR";
5226     case 5: return "IPSR";
5227     case 6: return "EPSR";
5228     case 7: return "IEPSR";
5229     case 8: return "MSP";
5230     case 9: return "PSP";
5231     case 16: return "PRIMASK";
5232     case 17: return "BASEPRI";
5233     case 18: return "BASEPRI_MAX";
5234     case 19: return "FAULTMASK";
5235     case 20: return "CONTROL";
5236     default: return "<unknown>";
5237     }
5238 }
5239
5240 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM.  */
5241
5242 static void
5243 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
5244 {
5245   const struct opcode32 *insn;
5246   void *stream = info->stream;
5247   fprintf_ftype func = info->fprintf_func;
5248
5249   if (print_insn_coprocessor (pc, info, given, TRUE))
5250     return;
5251
5252   if (print_insn_neon (info, given, TRUE))
5253     return;
5254
5255   for (insn = thumb32_opcodes; insn->assembler; insn++)
5256     if ((given & insn->mask) == insn->value)
5257       {
5258         bfd_boolean is_unpredictable = FALSE;
5259         signed long value_in_comment = 0;
5260         const char *c = insn->assembler;
5261
5262         for (; *c; c++)
5263           {
5264             if (*c != '%')
5265               {
5266                 func (stream, "%c", *c);
5267                 continue;
5268               }
5269
5270             switch (*++c)
5271               {
5272               case '%':
5273                 func (stream, "%%");
5274                 break;
5275
5276               case 'c':
5277                 if (ifthen_state)
5278                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
5279                 break;
5280
5281               case 'x':
5282                 if (ifthen_next_state)
5283                   func (stream, "\t; unpredictable branch in IT block\n");
5284                 break;
5285
5286               case 'X':
5287                 if (ifthen_state)
5288                   func (stream, "\t; unpredictable <IT:%s>",
5289                         arm_conditional[IFTHEN_COND]);
5290                 break;
5291
5292               case 'I':
5293                 {
5294                   unsigned int imm12 = 0;
5295
5296                   imm12 |= (given & 0x000000ffu);
5297                   imm12 |= (given & 0x00007000u) >> 4;
5298                   imm12 |= (given & 0x04000000u) >> 15;
5299                   func (stream, "#%u", imm12);
5300                   value_in_comment = imm12;
5301                 }
5302                 break;
5303
5304               case 'M':
5305                 {
5306                   unsigned int bits = 0, imm, imm8, mod;
5307
5308                   bits |= (given & 0x000000ffu);
5309                   bits |= (given & 0x00007000u) >> 4;
5310                   bits |= (given & 0x04000000u) >> 15;
5311                   imm8 = (bits & 0x0ff);
5312                   mod = (bits & 0xf00) >> 8;
5313                   switch (mod)
5314                     {
5315                     case 0: imm = imm8; break;
5316                     case 1: imm = ((imm8 << 16) | imm8); break;
5317                     case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5318                     case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
5319                     default:
5320                       mod  = (bits & 0xf80) >> 7;
5321                       imm8 = (bits & 0x07f) | 0x80;
5322                       imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5323                     }
5324                   func (stream, "#%u", imm);
5325                   value_in_comment = imm;
5326                 }
5327                 break;
5328
5329               case 'J':
5330                 {
5331                   unsigned int imm = 0;
5332
5333                   imm |= (given & 0x000000ffu);
5334                   imm |= (given & 0x00007000u) >> 4;
5335                   imm |= (given & 0x04000000u) >> 15;
5336                   imm |= (given & 0x000f0000u) >> 4;
5337                   func (stream, "#%u", imm);
5338                   value_in_comment = imm;
5339                 }
5340                 break;
5341
5342               case 'K':
5343                 {
5344                   unsigned int imm = 0;
5345
5346                   imm |= (given & 0x000f0000u) >> 16;
5347                   imm |= (given & 0x00000ff0u) >> 0;
5348                   imm |= (given & 0x0000000fu) << 12;
5349                   func (stream, "#%u", imm);
5350                   value_in_comment = imm;
5351                 }
5352                 break;
5353
5354               case 'H':
5355                 {
5356                   unsigned int imm = 0;
5357
5358                   imm |= (given & 0x000f0000u) >> 4;
5359                   imm |= (given & 0x00000fffu) >> 0;
5360                   func (stream, "#%u", imm);
5361                   value_in_comment = imm;
5362                 }
5363                 break;
5364
5365               case 'V':
5366                 {
5367                   unsigned int imm = 0;
5368
5369                   imm |= (given & 0x00000fffu);
5370                   imm |= (given & 0x000f0000u) >> 4;
5371                   func (stream, "#%u", imm);
5372                   value_in_comment = imm;
5373                 }
5374                 break;
5375
5376               case 'S':
5377                 {
5378                   unsigned int reg = (given & 0x0000000fu);
5379                   unsigned int stp = (given & 0x00000030u) >> 4;
5380                   unsigned int imm = 0;
5381                   imm |= (given & 0x000000c0u) >> 6;
5382                   imm |= (given & 0x00007000u) >> 10;
5383
5384                   func (stream, "%s", arm_regnames[reg]);
5385                   switch (stp)
5386                     {
5387                     case 0:
5388                       if (imm > 0)
5389                         func (stream, ", lsl #%u", imm);
5390                       break;
5391
5392                     case 1:
5393                       if (imm == 0)
5394                         imm = 32;
5395                       func (stream, ", lsr #%u", imm);
5396                       break;
5397
5398                     case 2:
5399                       if (imm == 0)
5400                         imm = 32;
5401                       func (stream, ", asr #%u", imm);
5402                       break;
5403
5404                     case 3:
5405                       if (imm == 0)
5406                         func (stream, ", rrx");
5407                       else
5408                         func (stream, ", ror #%u", imm);
5409                     }
5410                 }
5411                 break;
5412
5413               case 'a':
5414                 {
5415                   unsigned int Rn  = (given & 0x000f0000) >> 16;
5416                   unsigned int U   = ! NEGATIVE_BIT_SET;
5417                   unsigned int op  = (given & 0x00000f00) >> 8;
5418                   unsigned int i12 = (given & 0x00000fff);
5419                   unsigned int i8  = (given & 0x000000ff);
5420                   bfd_boolean writeback = FALSE, postind = FALSE;
5421                   bfd_vma offset = 0;
5422
5423                   func (stream, "[%s", arm_regnames[Rn]);
5424                   if (U) /* 12-bit positive immediate offset.  */
5425                     {
5426                       offset = i12;
5427                       if (Rn != 15)
5428                         value_in_comment = offset;
5429                     }
5430                   else if (Rn == 15) /* 12-bit negative immediate offset.  */
5431                     offset = - (int) i12;
5432                   else if (op == 0x0) /* Shifted register offset.  */
5433                     {
5434                       unsigned int Rm = (i8 & 0x0f);
5435                       unsigned int sh = (i8 & 0x30) >> 4;
5436
5437                       func (stream, ", %s", arm_regnames[Rm]);
5438                       if (sh)
5439                         func (stream, ", lsl #%u", sh);
5440                       func (stream, "]");
5441                       break;
5442                     }
5443                   else switch (op)
5444                     {
5445                     case 0xE:  /* 8-bit positive immediate offset.  */
5446                       offset = i8;
5447                       break;
5448
5449                     case 0xC:  /* 8-bit negative immediate offset.  */
5450                       offset = -i8;
5451                       break;
5452
5453                     case 0xF:  /* 8-bit + preindex with wb.  */
5454                       offset = i8;
5455                       writeback = TRUE;
5456                       break;
5457
5458                     case 0xD:  /* 8-bit - preindex with wb.  */
5459                       offset = -i8;
5460                       writeback = TRUE;
5461                       break;
5462
5463                     case 0xB:  /* 8-bit + postindex.  */
5464                       offset = i8;
5465                       postind = TRUE;
5466                       break;
5467
5468                     case 0x9:  /* 8-bit - postindex.  */
5469                       offset = -i8;
5470                       postind = TRUE;
5471                       break;
5472
5473                     default:
5474                       func (stream, ", <undefined>]");
5475                       goto skip;
5476                     }
5477
5478                   if (postind)
5479                     func (stream, "], #%d", (int) offset);
5480                   else
5481                     {
5482                       if (offset)
5483                         func (stream, ", #%d", (int) offset);
5484                       func (stream, writeback ? "]!" : "]");
5485                     }
5486
5487                   if (Rn == 15)
5488                     {
5489                       func (stream, "\t; ");
5490                       info->print_address_func (((pc + 4) & ~3) + offset, info);
5491                     }
5492                 }
5493               skip:
5494                 break;
5495
5496               case 'A':
5497                 {
5498                   unsigned int U   = ! NEGATIVE_BIT_SET;
5499                   unsigned int W   = WRITEBACK_BIT_SET;
5500                   unsigned int Rn  = (given & 0x000f0000) >> 16;
5501                   unsigned int off = (given & 0x000000ff);
5502
5503                   func (stream, "[%s", arm_regnames[Rn]);
5504
5505                   if (PRE_BIT_SET)
5506                     {
5507                       if (off || !U)
5508                         {
5509                           func (stream, ", #%c%u", U ? '+' : '-', off * 4);
5510                           value_in_comment = off * 4 * U ? 1 : -1;
5511                         }
5512                       func (stream, "]");
5513                       if (W)
5514                         func (stream, "!");
5515                     }
5516                   else
5517                     {
5518                       func (stream, "], ");
5519                       if (W)
5520                         {
5521                           func (stream, "#%c%u", U ? '+' : '-', off * 4);
5522                           value_in_comment = off * 4 * U ? 1 : -1;
5523                         }
5524                       else
5525                         {
5526                           func (stream, "{%u}", off);
5527                           value_in_comment = off;
5528                         }
5529                     }
5530                 }
5531                 break;
5532
5533               case 'w':
5534                 {
5535                   unsigned int Sbit = (given & 0x01000000) >> 24;
5536                   unsigned int type = (given & 0x00600000) >> 21;
5537
5538                   switch (type)
5539                     {
5540                     case 0: func (stream, Sbit ? "sb" : "b"); break;
5541                     case 1: func (stream, Sbit ? "sh" : "h"); break;
5542                     case 2:
5543                       if (Sbit)
5544                         func (stream, "??");
5545                       break;
5546                     case 3:
5547                       func (stream, "??");
5548                       break;
5549                     }
5550                 }
5551                 break;
5552
5553               case 'm':
5554                 {
5555                   int started = 0;
5556                   int reg;
5557
5558                   func (stream, "{");
5559                   for (reg = 0; reg < 16; reg++)
5560                     if ((given & (1 << reg)) != 0)
5561                       {
5562                         if (started)
5563                           func (stream, ", ");
5564                         started = 1;
5565                         func (stream, "%s", arm_regnames[reg]);
5566                       }
5567                   func (stream, "}");
5568                 }
5569                 break;
5570
5571               case 'E':
5572                 {
5573                   unsigned int msb = (given & 0x0000001f);
5574                   unsigned int lsb = 0;
5575
5576                   lsb |= (given & 0x000000c0u) >> 6;
5577                   lsb |= (given & 0x00007000u) >> 10;
5578                   func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5579                 }
5580                 break;
5581
5582               case 'F':
5583                 {
5584                   unsigned int width = (given & 0x0000001f) + 1;
5585                   unsigned int lsb = 0;
5586
5587                   lsb |= (given & 0x000000c0u) >> 6;
5588                   lsb |= (given & 0x00007000u) >> 10;
5589                   func (stream, "#%u, #%u", lsb, width);
5590                 }
5591                 break;
5592
5593               case 'b':
5594                 {
5595                   unsigned int S = (given & 0x04000000u) >> 26;
5596                   unsigned int J1 = (given & 0x00002000u) >> 13;
5597                   unsigned int J2 = (given & 0x00000800u) >> 11;
5598                   bfd_vma offset = 0;
5599
5600                   offset |= !S << 20;
5601                   offset |= J2 << 19;
5602                   offset |= J1 << 18;
5603                   offset |= (given & 0x003f0000) >> 4;
5604                   offset |= (given & 0x000007ff) << 1;
5605                   offset -= (1 << 20);
5606
5607                   info->print_address_func (pc + 4 + offset, info);
5608                 }
5609                 break;
5610
5611               case 'B':
5612                 {
5613                   unsigned int S = (given & 0x04000000u) >> 26;
5614                   unsigned int I1 = (given & 0x00002000u) >> 13;
5615                   unsigned int I2 = (given & 0x00000800u) >> 11;
5616                   bfd_vma offset = 0;
5617
5618                   offset |= !S << 24;
5619                   offset |= !(I1 ^ S) << 23;
5620                   offset |= !(I2 ^ S) << 22;
5621                   offset |= (given & 0x03ff0000u) >> 4;
5622                   offset |= (given & 0x000007ffu) << 1;
5623                   offset -= (1 << 24);
5624                   offset += pc + 4;
5625
5626                   /* BLX target addresses are always word aligned.  */
5627                   if ((given & 0x00001000u) == 0)
5628                       offset &= ~2u;
5629
5630                   info->print_address_func (offset, info);
5631                 }
5632                 break;
5633
5634               case 's':
5635                 {
5636                   unsigned int shift = 0;
5637
5638                   shift |= (given & 0x000000c0u) >> 6;
5639                   shift |= (given & 0x00007000u) >> 10;
5640                   if (WRITEBACK_BIT_SET)
5641                     func (stream, ", asr #%u", shift);
5642                   else if (shift)
5643                     func (stream, ", lsl #%u", shift);
5644                   /* else print nothing - lsl #0 */
5645                 }
5646                 break;
5647
5648               case 'R':
5649                 {
5650                   unsigned int rot = (given & 0x00000030) >> 4;
5651
5652                   if (rot)
5653                     func (stream, ", ror #%u", rot * 8);
5654                 }
5655                 break;
5656
5657               case 'U':
5658                 if ((given & 0xf0) == 0x60)
5659                   {
5660                     switch (given & 0xf)
5661                       {
5662                         case 0xf: func (stream, "sy"); break;
5663                         default:
5664                           func (stream, "#%d", (int) given & 0xf);
5665                               break;
5666                       }
5667                   }
5668                 else
5669                   {
5670                     const char * opt = data_barrier_option (given & 0xf);
5671                     if (opt != NULL)
5672                       func (stream, "%s", opt);
5673                     else
5674                       func (stream, "#%d", (int) given & 0xf);
5675                    }
5676                 break;
5677
5678               case 'C':
5679                 if ((given & 0xff) == 0)
5680                   {
5681                     func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5682                     if (given & 0x800)
5683                       func (stream, "f");
5684                     if (given & 0x400)
5685                       func (stream, "s");
5686                     if (given & 0x200)
5687                       func (stream, "x");
5688                     if (given & 0x100)
5689                       func (stream, "c");
5690                   }
5691                 else if ((given & 0x20) == 0x20)
5692                   {
5693                     char const* name;
5694                     unsigned sysm = (given & 0xf00) >> 8;
5695
5696                     sysm |= (given & 0x30);
5697                     sysm |= (given & 0x00100000) >> 14;
5698                     name = banked_regname (sysm);
5699
5700                     if (name != NULL)
5701                       func (stream, "%s", name);
5702                     else
5703                       func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5704                   }
5705                 else
5706                   {
5707                     func (stream, "%s", psr_name (given & 0xff));
5708                   }
5709                 break;
5710
5711               case 'D':
5712                 if (((given & 0xff) == 0)
5713                     || ((given & 0x20) == 0x20))
5714                   {
5715                     char const* name;
5716                     unsigned sm = (given & 0xf0000) >> 16;
5717
5718                     sm |= (given & 0x30);
5719                     sm |= (given & 0x00100000) >> 14;
5720                     name = banked_regname (sm);
5721
5722                     if (name != NULL)
5723                       func (stream, "%s", name);
5724                     else
5725                       func (stream, "(UNDEF: %lu)", (unsigned long) sm);
5726                   }
5727                 else
5728                   func (stream, "%s", psr_name (given & 0xff));
5729                 break;
5730
5731               case '0': case '1': case '2': case '3': case '4':
5732               case '5': case '6': case '7': case '8': case '9':
5733                 {
5734                   int width;
5735                   unsigned long val;
5736
5737                   c = arm_decode_bitfield (c, given, &val, &width);
5738
5739                   switch (*c)
5740                     {
5741                     case 'd':
5742                       func (stream, "%lu", val);
5743                       value_in_comment = val;
5744                       break;
5745
5746                     case 'D':
5747                       func (stream, "%lu", val + 1);
5748                       value_in_comment = val + 1;
5749                       break;
5750
5751                     case 'W':
5752                       func (stream, "%lu", val * 4);
5753                       value_in_comment = val * 4;
5754                       break;
5755
5756                     case 'S':
5757                       if (val == 13)
5758                         is_unpredictable = TRUE;
5759                       /* Fall through.  */
5760                     case 'R':
5761                       if (val == 15)
5762                         is_unpredictable = TRUE;
5763                       /* Fall through.  */
5764                     case 'r':
5765                       func (stream, "%s", arm_regnames[val]);
5766                       break;
5767
5768                     case 'c':
5769                       func (stream, "%s", arm_conditional[val]);
5770                       break;
5771
5772                     case '\'':
5773                       c++;
5774                       if (val == ((1ul << width) - 1))
5775                         func (stream, "%c", *c);
5776                       break;
5777
5778                     case '`':
5779                       c++;
5780                       if (val == 0)
5781                         func (stream, "%c", *c);
5782                       break;
5783
5784                     case '?':
5785                       func (stream, "%c", c[(1 << width) - (int) val]);
5786                       c += 1 << width;
5787                       break;
5788
5789                     case 'x':
5790                       func (stream, "0x%lx", val & 0xffffffffUL);
5791                       break;
5792
5793                     default:
5794                       abort ();
5795                     }
5796                 }
5797                 break;
5798
5799               case 'L':
5800                 /* PR binutils/12534
5801                    If we have a PC relative offset in an LDRD or STRD
5802                    instructions then display the decoded address.  */
5803                 if (((given >> 16) & 0xf) == 0xf)
5804                   {
5805                     bfd_vma offset = (given & 0xff) * 4;
5806
5807                     if ((given & (1 << 23)) == 0)
5808                       offset = - offset;
5809                     func (stream, "\t; ");
5810                     info->print_address_func ((pc & ~3) + 4 + offset, info);
5811                   }
5812                 break;
5813
5814               default:
5815                 abort ();
5816               }
5817           }
5818
5819         if (value_in_comment > 32 || value_in_comment < -16)
5820           func (stream, "\t; 0x%lx", value_in_comment);
5821
5822         if (is_unpredictable)
5823           func (stream, UNPREDICTABLE_INSTRUCTION);
5824
5825         return;
5826       }
5827
5828   /* No match.  */
5829   abort ();
5830 }
5831
5832 /* Print data bytes on INFO->STREAM.  */
5833
5834 static void
5835 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
5836                  struct disassemble_info *info,
5837                  long given)
5838 {
5839   switch (info->bytes_per_chunk)
5840     {
5841     case 1:
5842       info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
5843       break;
5844     case 2:
5845       info->fprintf_func (info->stream, ".short\t0x%04lx", given);
5846       break;
5847     case 4:
5848       info->fprintf_func (info->stream, ".word\t0x%08lx", given);
5849       break;
5850     default:
5851       abort ();
5852     }
5853 }
5854
5855 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
5856    being displayed in symbol relative addresses.
5857
5858    Also disallow private symbol, with __tagsym$$ prefix,
5859    from ARM RVCT toolchain being displayed.  */
5860
5861 bfd_boolean
5862 arm_symbol_is_valid (asymbol * sym,
5863                      struct disassemble_info * info ATTRIBUTE_UNUSED)
5864 {
5865   const char * name;
5866
5867   if (sym == NULL)
5868     return FALSE;
5869
5870   name = bfd_asymbol_name (sym);
5871
5872   return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
5873 }
5874
5875 /* Parse an individual disassembler option.  */
5876
5877 void
5878 parse_arm_disassembler_option (char *option)
5879 {
5880   if (option == NULL)
5881     return;
5882
5883   if (CONST_STRNEQ (option, "reg-names-"))
5884     {
5885       int i;
5886
5887       option += 10;
5888
5889       for (i = NUM_ARM_REGNAMES; i--;)
5890         if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
5891           {
5892             regname_selected = i;
5893             break;
5894           }
5895
5896       if (i < 0)
5897         /* XXX - should break 'option' at following delimiter.  */
5898         fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
5899     }
5900   else if (CONST_STRNEQ (option, "force-thumb"))
5901     force_thumb = 1;
5902   else if (CONST_STRNEQ (option, "no-force-thumb"))
5903     force_thumb = 0;
5904   else
5905     /* XXX - should break 'option' at following delimiter.  */
5906     fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
5907
5908   return;
5909 }
5910
5911 /* Parse the string of disassembler options, spliting it at whitespaces
5912    or commas.  (Whitespace separators supported for backwards compatibility).  */
5913
5914 static void
5915 parse_disassembler_options (char *options)
5916 {
5917   if (options == NULL)
5918     return;
5919
5920   while (*options)
5921     {
5922       parse_arm_disassembler_option (options);
5923
5924       /* Skip forward to next seperator.  */
5925       while ((*options) && (! ISSPACE (*options)) && (*options != ','))
5926         ++ options;
5927       /* Skip forward past seperators.  */
5928       while (ISSPACE (*options) || (*options == ','))
5929         ++ options;
5930     }
5931 }
5932
5933 /* Search back through the insn stream to determine if this instruction is
5934    conditionally executed.  */
5935
5936 static void
5937 find_ifthen_state (bfd_vma pc,
5938                    struct disassemble_info *info,
5939                    bfd_boolean little)
5940 {
5941   unsigned char b[2];
5942   unsigned int insn;
5943   int status;
5944   /* COUNT is twice the number of instructions seen.  It will be odd if we
5945      just crossed an instruction boundary.  */
5946   int count;
5947   int it_count;
5948   unsigned int seen_it;
5949   bfd_vma addr;
5950
5951   ifthen_address = pc;
5952   ifthen_state = 0;
5953
5954   addr = pc;
5955   count = 1;
5956   it_count = 0;
5957   seen_it = 0;
5958   /* Scan backwards looking for IT instructions, keeping track of where
5959      instruction boundaries are.  We don't know if something is actually an
5960      IT instruction until we find a definite instruction boundary.  */
5961   for (;;)
5962     {
5963       if (addr == 0 || info->symbol_at_address_func (addr, info))
5964         {
5965           /* A symbol must be on an instruction boundary, and will not
5966              be within an IT block.  */
5967           if (seen_it && (count & 1))
5968             break;
5969
5970           return;
5971         }
5972       addr -= 2;
5973       status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
5974       if (status)
5975         return;
5976
5977       if (little)
5978         insn = (b[0]) | (b[1] << 8);
5979       else
5980         insn = (b[1]) | (b[0] << 8);
5981       if (seen_it)
5982         {
5983           if ((insn & 0xf800) < 0xe800)
5984             {
5985               /* Addr + 2 is an instruction boundary.  See if this matches
5986                  the expected boundary based on the position of the last
5987                  IT candidate.  */
5988               if (count & 1)
5989                 break;
5990               seen_it = 0;
5991             }
5992         }
5993       if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
5994         {
5995           /* This could be an IT instruction.  */
5996           seen_it = insn;
5997           it_count = count >> 1;
5998         }
5999       if ((insn & 0xf800) >= 0xe800)
6000         count++;
6001       else
6002         count = (count + 2) | 1;
6003       /* IT blocks contain at most 4 instructions.  */
6004       if (count >= 8 && !seen_it)
6005         return;
6006     }
6007   /* We found an IT instruction.  */
6008   ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6009   if ((ifthen_state & 0xf) == 0)
6010     ifthen_state = 0;
6011 }
6012
6013 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6014    mapping symbol.  */
6015
6016 static int
6017 is_mapping_symbol (struct disassemble_info *info, int n,
6018                    enum map_type *map_type)
6019 {
6020   const char *name;
6021
6022   name = bfd_asymbol_name (info->symtab[n]);
6023   if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6024       && (name[2] == 0 || name[2] == '.'))
6025     {
6026       *map_type = ((name[1] == 'a') ? MAP_ARM
6027                    : (name[1] == 't') ? MAP_THUMB
6028                    : MAP_DATA);
6029       return TRUE;
6030     }
6031
6032   return FALSE;
6033 }
6034
6035 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6036    Returns nonzero if *MAP_TYPE was set.  */
6037
6038 static int
6039 get_map_sym_type (struct disassemble_info *info,
6040                   int n,
6041                   enum map_type *map_type)
6042 {
6043   /* If the symbol is in a different section, ignore it.  */
6044   if (info->section != NULL && info->section != info->symtab[n]->section)
6045     return FALSE;
6046
6047   return is_mapping_symbol (info, n, map_type);
6048 }
6049
6050 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
6051    Returns nonzero if *MAP_TYPE was set.  */
6052
6053 static int
6054 get_sym_code_type (struct disassemble_info *info,
6055                    int n,
6056                    enum map_type *map_type)
6057 {
6058   elf_symbol_type *es;
6059   unsigned int type;
6060
6061   /* If the symbol is in a different section, ignore it.  */
6062   if (info->section != NULL && info->section != info->symtab[n]->section)
6063     return FALSE;
6064
6065   es = *(elf_symbol_type **)(info->symtab + n);
6066   type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6067
6068   /* If the symbol has function type then use that.  */
6069   if (type == STT_FUNC || type == STT_GNU_IFUNC)
6070     {
6071       if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB)
6072         *map_type = MAP_THUMB;
6073       else
6074         *map_type = MAP_ARM;
6075       return TRUE;
6076     }
6077
6078   return FALSE;
6079 }
6080
6081 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
6082    of the supplied arm_feature_set structure with bitmasks indicating
6083    the support base architectures and coprocessor extensions.
6084
6085    FIXME: This could more efficiently implemented as a constant array,
6086    although it would also be less robust.  */
6087
6088 static void
6089 select_arm_features (unsigned long mach,
6090                      arm_feature_set * features)
6091 {
6092 #undef ARM_SET_FEATURES
6093 #define ARM_SET_FEATURES(FSET) \
6094   {                                                     \
6095     const arm_feature_set fset = FSET;                  \
6096     arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \
6097     ARM_MERGE_FEATURE_SETS (*features, tmp, fset);      \
6098   }
6099
6100   switch (mach)
6101     {
6102     case bfd_mach_arm_2:       ARM_SET_FEATURES (ARM_ARCH_V2); break;
6103     case bfd_mach_arm_2a:      ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6104     case bfd_mach_arm_3:       ARM_SET_FEATURES (ARM_ARCH_V3); break;
6105     case bfd_mach_arm_3M:      ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6106     case bfd_mach_arm_4:       ARM_SET_FEATURES (ARM_ARCH_V4); break;
6107     case bfd_mach_arm_4T:      ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6108     case bfd_mach_arm_5:       ARM_SET_FEATURES (ARM_ARCH_V5); break;
6109     case bfd_mach_arm_5T:      ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6110     case bfd_mach_arm_5TE:     ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6111     case bfd_mach_arm_XScale:  ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
6112     case bfd_mach_arm_ep9312:
6113       ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6114                                          ARM_CEXT_MAVERICK | FPU_MAVERICK));
6115        break;
6116     case bfd_mach_arm_iWMMXt:  ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6117     case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
6118       /* If the machine type is unknown allow all
6119          architecture types and all extensions.  */
6120     case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
6121     default:
6122       abort ();
6123     }
6124
6125 #undef ARM_SET_FEATURES
6126 }
6127
6128
6129 /* NOTE: There are no checks in these routines that
6130    the relevant number of data bytes exist.  */
6131
6132 static int
6133 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
6134 {
6135   unsigned char b[4];
6136   long          given;
6137   int           status;
6138   int           is_thumb = FALSE;
6139   int           is_data = FALSE;
6140   int           little_code;
6141   unsigned int  size = 4;
6142   void          (*printer) (bfd_vma, struct disassemble_info *, long);
6143   bfd_boolean   found = FALSE;
6144   struct arm_private_data *private_data;
6145
6146   if (info->disassembler_options)
6147     {
6148       parse_disassembler_options (info->disassembler_options);
6149
6150       /* To avoid repeated parsing of these options, we remove them here.  */
6151       info->disassembler_options = NULL;
6152     }
6153
6154   /* PR 10288: Control which instructions will be disassembled.  */
6155   if (info->private_data == NULL)
6156     {
6157       static struct arm_private_data private;
6158
6159       if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6160         /* If the user did not use the -m command line switch then default to
6161            disassembling all types of ARM instruction.
6162
6163            The info->mach value has to be ignored as this will be based on
6164            the default archictecture for the target and/or hints in the notes
6165            section, but it will never be greater than the current largest arm
6166            machine value (iWMMXt2), which is only equivalent to the V5TE
6167            architecture.  ARM architectures have advanced beyond the machine
6168            value encoding, and these newer architectures would be ignored if
6169            the machine value was used.
6170
6171            Ie the -m switch is used to restrict which instructions will be
6172            disassembled.  If it is necessary to use the -m switch to tell
6173            objdump that an ARM binary is being disassembled, eg because the
6174            input is a raw binary file, but it is also desired to disassemble
6175            all ARM instructions then use "-marm".  This will select the
6176            "unknown" arm architecture which is compatible with any ARM
6177            instruction.  */
6178           info->mach = bfd_mach_arm_unknown;
6179
6180       /* Compute the architecture bitmask from the machine number.
6181          Note: This assumes that the machine number will not change
6182          during disassembly....  */
6183       select_arm_features (info->mach, & private.features);
6184
6185       private.has_mapping_symbols = -1;
6186       private.last_mapping_sym = -1;
6187       private.last_mapping_addr = 0;
6188
6189       info->private_data = & private;
6190     }
6191
6192   private_data = info->private_data;
6193
6194   /* Decide if our code is going to be little-endian, despite what the
6195      function argument might say.  */
6196   little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6197
6198   /* For ELF, consult the symbol table to determine what kind of code
6199      or data we have.  */
6200   if (info->symtab_size != 0
6201       && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6202     {
6203       bfd_vma addr;
6204       int n, start;
6205       int last_sym = -1;
6206       enum map_type type = MAP_ARM;
6207
6208       /* Start scanning at the start of the function, or wherever
6209          we finished last time.  */
6210       /* PR 14006.  When the address is 0 we are either at the start of the
6211          very first function, or else the first function in a new, unlinked
6212          executable section (eg because uf -ffunction-sections).  Either way
6213          start scanning from the beginning of the symbol table, not where we
6214          left off last time.  */
6215       if (pc == 0)
6216         start = 0;
6217       else
6218         {
6219           start = info->symtab_pos + 1;
6220           if (start < private_data->last_mapping_sym)
6221             start = private_data->last_mapping_sym;
6222         }
6223       found = FALSE;
6224
6225       /* First, look for mapping symbols.  */
6226       if (private_data->has_mapping_symbols != 0)
6227         {
6228           /* Scan up to the location being disassembled.  */
6229           for (n = start; n < info->symtab_size; n++)
6230             {
6231               addr = bfd_asymbol_value (info->symtab[n]);
6232               if (addr > pc)
6233                 break;
6234               if (get_map_sym_type (info, n, &type))
6235                 {
6236                   last_sym = n;
6237                   found = TRUE;
6238                 }
6239             }
6240
6241           if (!found)
6242             {
6243               /* No mapping symbol found at this address.  Look backwards
6244                  for a preceding one.  */
6245               for (n = start - 1; n >= 0; n--)
6246                 {
6247                   if (get_map_sym_type (info, n, &type))
6248                     {
6249                       last_sym = n;
6250                       found = TRUE;
6251                       break;
6252                     }
6253                 }
6254             }
6255
6256           if (found)
6257             private_data->has_mapping_symbols = 1;
6258
6259           /* No mapping symbols were found.  A leading $d may be
6260              omitted for sections which start with data; but for
6261              compatibility with legacy and stripped binaries, only
6262              assume the leading $d if there is at least one mapping
6263              symbol in the file.  */
6264           if (!found && private_data->has_mapping_symbols == -1)
6265             {
6266               /* Look for mapping symbols, in any section.  */
6267               for (n = 0; n < info->symtab_size; n++)
6268                 if (is_mapping_symbol (info, n, &type))
6269                   {
6270                     private_data->has_mapping_symbols = 1;
6271                     break;
6272                   }
6273               if (private_data->has_mapping_symbols == -1)
6274                 private_data->has_mapping_symbols = 0;
6275             }
6276
6277           if (!found && private_data->has_mapping_symbols == 1)
6278             {
6279               type = MAP_DATA;
6280               found = TRUE;
6281             }
6282         }
6283
6284       /* Next search for function symbols to separate ARM from Thumb
6285          in binaries without mapping symbols.  */
6286       if (!found)
6287         {
6288           /* Scan up to the location being disassembled.  */
6289           for (n = start; n < info->symtab_size; n++)
6290             {
6291               addr = bfd_asymbol_value (info->symtab[n]);
6292               if (addr > pc)
6293                 break;
6294               if (get_sym_code_type (info, n, &type))
6295                 {
6296                   last_sym = n;
6297                   found = TRUE;
6298                 }
6299             }
6300
6301           if (!found)
6302             {
6303               /* No mapping symbol found at this address.  Look backwards
6304                  for a preceding one.  */
6305               for (n = start - 1; n >= 0; n--)
6306                 {
6307                   if (get_sym_code_type (info, n, &type))
6308                     {
6309                       last_sym = n;
6310                       found = TRUE;
6311                       break;
6312                     }
6313                 }
6314             }
6315         }
6316
6317       private_data->last_mapping_sym = last_sym;
6318       private_data->last_type = type;
6319       is_thumb = (private_data->last_type == MAP_THUMB);
6320       is_data = (private_data->last_type == MAP_DATA);
6321
6322       /* Look a little bit ahead to see if we should print out
6323          two or four bytes of data.  If there's a symbol,
6324          mapping or otherwise, after two bytes then don't
6325          print more.  */
6326       if (is_data)
6327         {
6328           size = 4 - (pc & 3);
6329           for (n = last_sym + 1; n < info->symtab_size; n++)
6330             {
6331               addr = bfd_asymbol_value (info->symtab[n]);
6332               if (addr > pc
6333                   && (info->section == NULL
6334                       || info->section == info->symtab[n]->section))
6335                 {
6336                   if (addr - pc < size)
6337                     size = addr - pc;
6338                   break;
6339                 }
6340             }
6341           /* If the next symbol is after three bytes, we need to
6342              print only part of the data, so that we can use either
6343              .byte or .short.  */
6344           if (size == 3)
6345             size = (pc & 1) ? 1 : 2;
6346         }
6347     }
6348
6349   if (info->symbols != NULL)
6350     {
6351       if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6352         {
6353           coff_symbol_type * cs;
6354
6355           cs = coffsymbol (*info->symbols);
6356           is_thumb = (   cs->native->u.syment.n_sclass == C_THUMBEXT
6357                       || cs->native->u.syment.n_sclass == C_THUMBSTAT
6358                       || cs->native->u.syment.n_sclass == C_THUMBLABEL
6359                       || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6360                       || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6361         }
6362       else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6363                && !found)
6364         {
6365           /* If no mapping symbol has been found then fall back to the type
6366              of the function symbol.  */
6367           elf_symbol_type *  es;
6368           unsigned int       type;
6369
6370           es = *(elf_symbol_type **)(info->symbols);
6371           type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6372
6373           is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym)
6374                        == ST_BRANCH_TO_THUMB)
6375                       || type == STT_ARM_16BIT);
6376         }
6377     }
6378
6379   if (force_thumb)
6380     is_thumb = TRUE;
6381
6382   if (is_data)
6383     info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6384   else
6385     info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6386
6387   info->bytes_per_line = 4;
6388
6389   /* PR 10263: Disassemble data if requested to do so by the user.  */
6390   if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
6391     {
6392       int i;
6393
6394       /* Size was already set above.  */
6395       info->bytes_per_chunk = size;
6396       printer = print_insn_data;
6397
6398       status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
6399       given = 0;
6400       if (little)
6401         for (i = size - 1; i >= 0; i--)
6402           given = b[i] | (given << 8);
6403       else
6404         for (i = 0; i < (int) size; i++)
6405           given = b[i] | (given << 8);
6406     }
6407   else if (!is_thumb)
6408     {
6409       /* In ARM mode endianness is a straightforward issue: the instruction
6410          is four bytes long and is either ordered 0123 or 3210.  */
6411       printer = print_insn_arm;
6412       info->bytes_per_chunk = 4;
6413       size = 4;
6414
6415       status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
6416       if (little_code)
6417         given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6418       else
6419         given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
6420     }
6421   else
6422     {
6423       /* In Thumb mode we have the additional wrinkle of two
6424          instruction lengths.  Fortunately, the bits that determine
6425          the length of the current instruction are always to be found
6426          in the first two bytes.  */
6427       printer = print_insn_thumb16;
6428       info->bytes_per_chunk = 2;
6429       size = 2;
6430
6431       status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
6432       if (little_code)
6433         given = (b[0]) | (b[1] << 8);
6434       else
6435         given = (b[1]) | (b[0] << 8);
6436
6437       if (!status)
6438         {
6439           /* These bit patterns signal a four-byte Thumb
6440              instruction.  */
6441           if ((given & 0xF800) == 0xF800
6442               || (given & 0xF800) == 0xF000
6443               || (given & 0xF800) == 0xE800)
6444             {
6445               status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
6446               if (little_code)
6447                 given = (b[0]) | (b[1] << 8) | (given << 16);
6448               else
6449                 given = (b[1]) | (b[0] << 8) | (given << 16);
6450
6451               printer = print_insn_thumb32;
6452               size = 4;
6453             }
6454         }
6455
6456       if (ifthen_address != pc)
6457         find_ifthen_state (pc, info, little_code);
6458
6459       if (ifthen_state)
6460         {
6461           if ((ifthen_state & 0xf) == 0x8)
6462             ifthen_next_state = 0;
6463           else
6464             ifthen_next_state = (ifthen_state & 0xe0)
6465                                 | ((ifthen_state & 0xf) << 1);
6466         }
6467     }
6468
6469   if (status)
6470     {
6471       info->memory_error_func (status, pc, info);
6472       return -1;
6473     }
6474   if (info->flags & INSN_HAS_RELOC)
6475     /* If the instruction has a reloc associated with it, then
6476        the offset field in the instruction will actually be the
6477        addend for the reloc.  (We are using REL type relocs).
6478        In such cases, we can ignore the pc when computing
6479        addresses, since the addend is not currently pc-relative.  */
6480     pc = 0;
6481
6482   printer (pc, info, given);
6483
6484   if (is_thumb)
6485     {
6486       ifthen_state = ifthen_next_state;
6487       ifthen_address += size;
6488     }
6489   return size;
6490 }
6491
6492 int
6493 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
6494 {
6495   /* Detect BE8-ness and record it in the disassembler info.  */
6496   if (info->flavour == bfd_target_elf_flavour
6497       && info->section != NULL
6498       && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6499     info->endian_code = BFD_ENDIAN_LITTLE;
6500
6501   return print_insn (pc, info, FALSE);
6502 }
6503
6504 int
6505 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
6506 {
6507   return print_insn (pc, info, TRUE);
6508 }
6509
6510 void
6511 print_arm_disassembler_options (FILE *stream)
6512 {
6513   int i;
6514
6515   fprintf (stream, _("\n\
6516 The following ARM specific disassembler options are supported for use with\n\
6517 the -M switch:\n"));
6518
6519   for (i = NUM_ARM_REGNAMES; i--;)
6520     fprintf (stream, "  reg-names-%s %*c%s\n",
6521              regnames[i].name,
6522              (int)(14 - strlen (regnames[i].name)), ' ',
6523              regnames[i].description);
6524
6525   fprintf (stream, "  force-thumb              Assume all insns are Thumb insns\n");
6526   fprintf (stream, "  no-force-thumb           Examine preceding label to determine an insn's type\n\n");
6527 }