1 /* Instruction printing code for the ARM
2 Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
6 This file is part of libopcodes.
8 This program is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2 of the License, or (at your option)
13 This program is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
26 #include "coff/internal.h"
30 /* FIXME: This shouldn't be done here */
32 #include "elf/internal.h"
36 #define streq(a,b) (strcmp ((a), (b)) == 0)
40 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
44 #define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
47 static char * arm_conditional[] =
48 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
49 "hi", "ls", "ge", "lt", "gt", "le", "", "nv"};
54 const char * description;
55 const char * reg_names[16];
59 static arm_regname regnames[] =
61 { "raw" , "Select raw register names",
62 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
63 { "std", "Select register names used in ARM's ISA documentation",
64 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65 { "apcs", "Select register names used in the APCS",
66 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
67 { "atpcs", "Select register names used in the ATPCS",
68 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
69 { "atpcs-special", "Select special register names used in the ATPCS",
70 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
73 /* Default to standard register name set. */
74 static unsigned int regname_selected = 1;
76 #define NUM_ARM_REGNAMES NUM_ELEM (regnames)
77 #define arm_regnames regnames[regname_selected].reg_names
79 static boolean force_thumb = false;
81 static char * arm_fp_const[] =
82 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
84 static char * arm_shift[] =
85 {"lsl", "lsr", "asr", "ror"};
87 /* Forward declarations. */
88 static void arm_decode_shift PARAMS ((long, fprintf_ftype, void *));
89 static int print_insn_arm PARAMS ((bfd_vma, struct disassemble_info *, long));
90 static int print_insn_thumb PARAMS ((bfd_vma, struct disassemble_info *, long));
91 static void parse_disassembler_option PARAMS ((char *));
92 static void parse_disassembler_options PARAMS ((char *));
93 static int print_insn PARAMS ((bfd_vma, struct disassemble_info *, boolean));
97 arm_decode_shift (given, func, stream)
102 func (stream, "%s", arm_regnames[given & 0xf]);
104 if ((given & 0xff0) != 0)
106 if ((given & 0x10) == 0)
108 int amount = (given & 0xf80) >> 7;
109 int shift = (given & 0x60) >> 5;
115 func (stream, ", rrx");
122 func (stream, ", %s #%d", arm_shift[shift], amount);
125 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
126 arm_regnames[(given & 0xf00) >> 8]);
130 /* Print one instruction from PC on INFO->STREAM.
131 Return the size of the instruction (always 4 on ARM). */
133 print_insn_arm (pc, info, given)
135 struct disassemble_info * info;
138 struct arm_opcode * insn;
139 void * stream = info->stream;
140 fprintf_ftype func = info->fprintf_func;
142 for (insn = arm_opcodes; insn->assembler; insn++)
144 if ((given & insn->mask) == insn->value)
148 for (c = insn->assembler; *c; c++)
159 if (((given & 0x000f0000) == 0x000f0000)
160 && ((given & 0x02000000) == 0))
162 int offset = given & 0xfff;
164 func (stream, "[pc");
166 if (given & 0x01000000)
168 if ((given & 0x00800000) == 0)
172 func (stream, ", #%x]", offset);
176 /* Cope with the possibility of write-back
177 being used. Probably a very dangerous thing
178 for the programmer to do, but who are we to
180 if (given & 0x00200000)
186 func (stream, "], #%x", offset);
188 offset = pc + 8; /* ie ignore the offset. */
191 func (stream, "\t; ");
192 info->print_address_func (offset, info);
197 arm_regnames[(given >> 16) & 0xf]);
198 if ((given & 0x01000000) != 0)
200 if ((given & 0x02000000) == 0)
202 int offset = given & 0xfff;
204 func (stream, ", %s#%d",
205 (((given & 0x00800000) == 0)
206 ? "-" : ""), offset);
210 func (stream, ", %s",
211 (((given & 0x00800000) == 0)
213 arm_decode_shift (given, func, stream);
217 ((given & 0x00200000) != 0) ? "!" : "");
221 if ((given & 0x02000000) == 0)
223 int offset = given & 0xfff;
225 func (stream, "], %s#%d",
226 (((given & 0x00800000) == 0)
227 ? "-" : ""), offset);
233 func (stream, "], %s",
234 (((given & 0x00800000) == 0)
236 arm_decode_shift (given, func, stream);
243 if ((given & 0x004f0000) == 0x004f0000)
245 /* PC relative with immediate offset. */
246 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
248 if ((given & 0x00800000) == 0)
251 func (stream, "[pc, #%x]\t; ", offset);
253 (*info->print_address_func)
254 (offset + pc + 8, info);
259 arm_regnames[(given >> 16) & 0xf]);
260 if ((given & 0x01000000) != 0)
263 if ((given & 0x00400000) == 0x00400000)
266 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
268 func (stream, ", %s#%d",
269 (((given & 0x00800000) == 0)
270 ? "-" : ""), offset);
275 func (stream, ", %s%s",
276 (((given & 0x00800000) == 0)
278 arm_regnames[given & 0xf]);
282 ((given & 0x00200000) != 0) ? "!" : "");
287 if ((given & 0x00400000) == 0x00400000)
290 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
292 func (stream, "], %s#%d",
293 (((given & 0x00800000) == 0)
294 ? "-" : ""), offset);
301 func (stream, "], %s%s",
302 (((given & 0x00800000) == 0)
304 arm_regnames[given & 0xf]);
311 (*info->print_address_func)
312 (BDISP (given) * 4 + pc + 8, info);
317 arm_conditional [(given >> 28) & 0xf]);
326 for (reg = 0; reg < 16; reg++)
327 if ((given & (1 << reg)) != 0)
332 func (stream, "%s", arm_regnames[reg]);
339 if ((given & 0x02000000) != 0)
341 int rotate = (given & 0xf00) >> 7;
342 int immed = (given & 0xff);
343 immed = (((immed << (32 - rotate))
344 | (immed >> rotate)) & 0xffffffff);
345 func (stream, "#%d\t; 0x%x", immed, immed);
348 arm_decode_shift (given, func, stream);
352 if ((given & 0x0000f000) == 0x0000f000)
357 if ((given & 0x01200000) == 0x00200000)
362 if ((given & 0x00000020) == 0x00000020)
369 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
370 if ((given & 0x01000000) != 0)
372 int offset = given & 0xff;
374 func (stream, ", %s#%d]%s",
375 ((given & 0x00800000) == 0 ? "-" : ""),
377 ((given & 0x00200000) != 0 ? "!" : ""));
383 int offset = given & 0xff;
385 func (stream, "], %s#%d",
386 ((given & 0x00800000) == 0 ? "-" : ""),
394 switch (given & 0x00090000)
397 func (stream, "_???");
400 func (stream, "_all");
403 func (stream, "_ctl");
406 func (stream, "_flg");
412 switch (given & 0x00408000)
429 switch (given & 0x00080080)
441 func (stream, _("<illegal precision>"));
446 switch (given & 0x00408000)
463 switch (given & 0x60)
479 case '0': case '1': case '2': case '3': case '4':
480 case '5': case '6': case '7': case '8': case '9':
482 int bitstart = *c++ - '0';
484 while (*c >= '0' && *c <= '9')
485 bitstart = (bitstart * 10) + *c++ - '0';
492 while (*c >= '0' && *c <= '9')
493 bitend = (bitend * 10) + *c++ - '0';
504 reg = given >> bitstart;
505 reg &= (2 << (bitend - bitstart)) - 1;
507 func (stream, "%s", arm_regnames[reg]);
514 reg = given >> bitstart;
515 reg &= (2 << (bitend - bitstart)) - 1;
517 func (stream, "%d", reg);
524 reg = given >> bitstart;
525 reg &= (2 << (bitend - bitstart)) - 1;
527 func (stream, "0x%08x", reg);
529 /* Some SWI instructions have special
531 if ((given & 0x0fffffff) == 0x0FF00000)
532 func (stream, "\t; IMB");
533 else if ((given & 0x0fffffff) == 0x0FF00001)
534 func (stream, "\t; IMBRange");
541 reg = given >> bitstart;
542 reg &= (2 << (bitend - bitstart)) - 1;
544 func (stream, "%01x", reg & 0xf);
551 reg = given >> bitstart;
552 reg &= (2 << (bitend - bitstart)) - 1;
556 arm_fp_const[reg & 7]);
558 func (stream, "f%d", reg);
568 if ((given & (1 << bitstart)) == 0)
569 func (stream, "%c", *c);
573 if ((given & (1 << bitstart)) != 0)
574 func (stream, "%c", *c);
578 if ((given & (1 << bitstart)) != 0)
579 func (stream, "%c", *c++);
581 func (stream, "%c", *++c);
594 func (stream, "%c", *c);
602 /* Print one instruction from PC on INFO->STREAM.
603 Return the size of the instruction. */
605 print_insn_thumb (pc, info, given)
607 struct disassemble_info * info;
610 struct thumb_opcode * insn;
611 void * stream = info->stream;
612 fprintf_ftype func = info->fprintf_func;
614 for (insn = thumb_opcodes; insn->assembler; insn++)
616 if ((given & insn->mask) == insn->value)
618 char * c = insn->assembler;
620 /* Special processing for Thumb 2 instruction BL sequence: */
621 if (!*c) /* Check for empty (not NULL) assembler string. */
623 info->bytes_per_chunk = 4;
624 info->bytes_per_line = 4;
626 func (stream, "bl\t");
627 info->print_address_func (BDISP23 (given) * 2 + pc + 4, info);
632 info->bytes_per_chunk = 2;
633 info->bytes_per_line = 4;
654 reg = (given >> 3) & 0x7;
655 if (given & (1 << 6))
658 func (stream, "%s", arm_regnames[reg]);
667 if (given & (1 << 7))
670 func (stream, "%s", arm_regnames[reg]);
676 arm_conditional [(given >> 8) & 0xf]);
680 if (given & (1 << 8))
684 if (*c == 'O' && (given & (1 << 8)))
694 /* It would be nice if we could spot
695 ranges, and generate the rS-rE format: */
696 for (reg = 0; (reg < 8); reg++)
697 if ((given & (1 << reg)) != 0)
702 func (stream, "%s", arm_regnames[reg]);
725 case '0': case '1': case '2': case '3': case '4':
726 case '5': case '6': case '7': case '8': case '9':
728 int bitstart = *c++ - '0';
731 while (*c >= '0' && *c <= '9')
732 bitstart = (bitstart * 10) + *c++ - '0';
741 while (*c >= '0' && *c <= '9')
742 bitend = (bitend * 10) + *c++ - '0';
745 reg = given >> bitstart;
746 reg &= (2 << (bitend - bitstart)) - 1;
750 func (stream, "%s", arm_regnames[reg]);
754 func (stream, "%d", reg);
758 func (stream, "%d", reg << 1);
762 func (stream, "%d", reg << 2);
766 /* PC-relative address -- the bottom two
767 bits of the address are dropped
768 before the calculation. */
769 info->print_address_func
770 (((pc + 4) & ~3) + (reg << 2), info);
774 func (stream, "0x%04x", reg);
778 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
779 func (stream, "%d", reg);
783 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
784 (*info->print_address_func)
785 (reg * 2 + pc + 4, info);
796 if ((given & (1 << bitstart)) != 0)
797 func (stream, "%c", *c);
802 if ((given & (1 << bitstart)) != 0)
803 func (stream, "%c", *c++);
805 func (stream, "%c", *++c);
819 func (stream, "%c", *c);
830 /* Parse an individual disassembler option. */
832 parse_disassembler_option (option)
838 if (strneq (option, "reg-names-", 10))
844 for (i = NUM_ARM_REGNAMES; i--;)
845 if (streq (option, regnames[i].name))
847 regname_selected = i;
852 fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
854 else if (streq (option, "force-thumb"))
856 else if (streq (option, "no-force-thumb"))
859 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
864 /* Parse the string of disassembler options, spliting it at whitespaces. */
866 parse_disassembler_options (options)
876 space = strchr (options, ' ');
881 parse_disassembler_option (options);
886 parse_disassembler_option (options);
891 /* NOTE: There are no checks in these routines that
892 the relevant number of data bytes exist. */
894 print_insn (pc, info, little)
896 struct disassemble_info * info;
904 if (info->disassembler_options)
906 parse_disassembler_options (info->disassembler_options);
908 /* To avoid repeated parsing of these options, we remove them here. */
909 info->disassembler_options = NULL;
912 is_thumb = force_thumb;
914 if (!is_thumb && info->symbols != NULL)
916 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
918 coff_symbol_type * cs;
920 cs = coffsymbol (*info->symbols);
921 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
922 || cs->native->u.syment.n_sclass == C_THUMBSTAT
923 || cs->native->u.syment.n_sclass == C_THUMBLABEL
924 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
925 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
927 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour)
929 elf_symbol_type * es;
932 es = *(elf_symbol_type **)(info->symbols);
933 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
935 is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT);
939 info->bytes_per_chunk = 4;
940 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
944 status = info->read_memory_func (pc, (bfd_byte *) &b[0], 4, info);
945 if (status != 0 && is_thumb)
947 info->bytes_per_chunk = 2;
949 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
955 info->memory_error_func (status, pc, info);
959 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
963 status = info->read_memory_func
964 (pc & ~ 0x3, (bfd_byte *) &b[0], 4, info);
967 info->memory_error_func (status, pc, info);
975 given = (b[2] << 8) | b[3];
977 status = info->read_memory_func
978 ((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info);
981 info->memory_error_func (status, pc + 4, info);
985 given |= (b[0] << 24) | (b[1] << 16);
988 given = (b[0] << 8) | b[1] | (b[2] << 24) | (b[3] << 16);
991 given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]);
995 status = print_insn_thumb (pc, info, given);
997 status = print_insn_arm (pc, info, given);
1003 print_insn_big_arm (pc, info)
1005 struct disassemble_info * info;
1007 return print_insn (pc, info, false);
1011 print_insn_little_arm (pc, info)
1013 struct disassemble_info * info;
1015 return print_insn (pc, info, true);
1019 print_arm_disassembler_options (FILE * stream)
1023 fprintf (stream, _("\n\
1024 The following ARM specific disassembler options are supported for use with\n\
1025 the -M switch:\n"));
1027 for (i = NUM_ARM_REGNAMES; i--;)
1028 fprintf (stream, " reg-names-%s %*c%s\n",
1030 14 - strlen (regnames[i].name), ' ',
1031 regnames[i].description);
1033 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
1034 fprintf (stream, " no-force-thumb Examine preceeding label to determine an insn's type\n\n");