1 /* Opcode table for the ARC.
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software Foundation,
20 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
25 #include "opcode/arc.h"
27 #include "libiberty.h"
29 /* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
30 instructions. Support for this target is available when binutils is
31 configured and built for the 'arc*-mellanox-*-*' target. As far as
32 possible all ARC NPS400 features are built into all ARC target builds as
33 this reduces the chances that regressions might creep in. */
35 /* Insert RB register into a 32-bit opcode. */
37 insert_rb (unsigned insn,
39 const char **errmsg ATTRIBUTE_UNUSED)
41 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
45 extract_rb (unsigned insn ATTRIBUTE_UNUSED,
46 bfd_boolean * invalid ATTRIBUTE_UNUSED)
48 int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
50 if (value == 0x3e && invalid)
51 *invalid = TRUE; /* A limm operand, it should be extracted in a
58 insert_rad (unsigned insn,
60 const char **errmsg ATTRIBUTE_UNUSED)
63 *errmsg = _("Improper register value.");
65 return insn | (value & 0x3F);
69 insert_rcd (unsigned insn,
71 const char **errmsg ATTRIBUTE_UNUSED)
74 *errmsg = _("Improper register value.");
76 return insn | ((value & 0x3F) << 6);
79 /* Dummy insert ZERO operand function. */
82 insert_za (unsigned insn,
87 *errmsg = _("operand is not zero");
91 /* Insert Y-bit in bbit/br instructions. This function is called only
92 when solving fixups. */
95 insert_Ybit (unsigned insn,
97 const char **errmsg ATTRIBUTE_UNUSED)
105 /* Insert Y-bit in bbit/br instructions. This function is called only
106 when solving fixups. */
109 insert_NYbit (unsigned insn,
111 const char **errmsg ATTRIBUTE_UNUSED)
119 /* Insert H register into a 16-bit opcode. */
122 insert_rhv1 (unsigned insn,
124 const char **errmsg ATTRIBUTE_UNUSED)
126 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
130 extract_rhv1 (unsigned insn ATTRIBUTE_UNUSED,
131 bfd_boolean * invalid ATTRIBUTE_UNUSED)
138 /* Insert H register into a 16-bit opcode. */
141 insert_rhv2 (unsigned insn,
147 _("Register R30 is a limm indicator for this type of instruction.");
148 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
152 extract_rhv2 (unsigned insn ATTRIBUTE_UNUSED,
153 bfd_boolean * invalid ATTRIBUTE_UNUSED)
155 int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
161 insert_r0 (unsigned insn,
163 const char **errmsg ATTRIBUTE_UNUSED)
166 *errmsg = _("Register must be R0.");
171 extract_r0 (unsigned insn ATTRIBUTE_UNUSED,
172 bfd_boolean * invalid ATTRIBUTE_UNUSED)
179 insert_r1 (unsigned insn,
181 const char **errmsg ATTRIBUTE_UNUSED)
184 *errmsg = _("Register must be R1.");
189 extract_r1 (unsigned insn ATTRIBUTE_UNUSED,
190 bfd_boolean * invalid ATTRIBUTE_UNUSED)
196 insert_r2 (unsigned insn,
198 const char **errmsg ATTRIBUTE_UNUSED)
201 *errmsg = _("Register must be R2.");
206 extract_r2 (unsigned insn ATTRIBUTE_UNUSED,
207 bfd_boolean * invalid ATTRIBUTE_UNUSED)
213 insert_r3 (unsigned insn,
215 const char **errmsg ATTRIBUTE_UNUSED)
218 *errmsg = _("Register must be R3.");
223 extract_r3 (unsigned insn ATTRIBUTE_UNUSED,
224 bfd_boolean * invalid ATTRIBUTE_UNUSED)
230 insert_sp (unsigned insn,
232 const char **errmsg ATTRIBUTE_UNUSED)
235 *errmsg = _("Register must be SP.");
240 extract_sp (unsigned insn ATTRIBUTE_UNUSED,
241 bfd_boolean * invalid ATTRIBUTE_UNUSED)
247 insert_gp (unsigned insn,
249 const char **errmsg ATTRIBUTE_UNUSED)
252 *errmsg = _("Register must be GP.");
257 extract_gp (unsigned insn ATTRIBUTE_UNUSED,
258 bfd_boolean * invalid ATTRIBUTE_UNUSED)
264 insert_pcl (unsigned insn,
266 const char **errmsg ATTRIBUTE_UNUSED)
269 *errmsg = _("Register must be PCL.");
274 extract_pcl (unsigned insn ATTRIBUTE_UNUSED,
275 bfd_boolean * invalid ATTRIBUTE_UNUSED)
281 insert_blink (unsigned insn,
283 const char **errmsg ATTRIBUTE_UNUSED)
286 *errmsg = _("Register must be BLINK.");
291 extract_blink (unsigned insn ATTRIBUTE_UNUSED,
292 bfd_boolean * invalid ATTRIBUTE_UNUSED)
298 insert_ilink1 (unsigned insn,
300 const char **errmsg ATTRIBUTE_UNUSED)
303 *errmsg = _("Register must be ILINK1.");
308 extract_ilink1 (unsigned insn ATTRIBUTE_UNUSED,
309 bfd_boolean * invalid ATTRIBUTE_UNUSED)
315 insert_ilink2 (unsigned insn,
317 const char **errmsg ATTRIBUTE_UNUSED)
320 *errmsg = _("Register must be ILINK2.");
325 extract_ilink2 (unsigned insn ATTRIBUTE_UNUSED,
326 bfd_boolean * invalid ATTRIBUTE_UNUSED)
332 insert_ras (unsigned insn,
334 const char **errmsg ATTRIBUTE_UNUSED)
351 *errmsg = _("Register must be either r0-r3 or r12-r15.");
358 extract_ras (unsigned insn ATTRIBUTE_UNUSED,
359 bfd_boolean * invalid ATTRIBUTE_UNUSED)
361 int value = insn & 0x07;
369 insert_rbs (unsigned insn,
371 const char **errmsg ATTRIBUTE_UNUSED)
385 insn |= ((value - 8)) << 8;
388 *errmsg = _("Register must be either r0-r3 or r12-r15.");
395 extract_rbs (unsigned insn ATTRIBUTE_UNUSED,
396 bfd_boolean * invalid ATTRIBUTE_UNUSED)
398 int value = (insn >> 8) & 0x07;
406 insert_rcs (unsigned insn,
408 const char **errmsg ATTRIBUTE_UNUSED)
422 insn |= ((value - 8)) << 5;
425 *errmsg = _("Register must be either r0-r3 or r12-r15.");
432 extract_rcs (unsigned insn ATTRIBUTE_UNUSED,
433 bfd_boolean * invalid ATTRIBUTE_UNUSED)
435 int value = (insn >> 5) & 0x07;
443 insert_simm3s (unsigned insn,
445 const char **errmsg ATTRIBUTE_UNUSED)
475 *errmsg = _("Accepted values are from -1 to 6.");
484 extract_simm3s (unsigned insn ATTRIBUTE_UNUSED,
485 bfd_boolean * invalid ATTRIBUTE_UNUSED)
487 int value = (insn >> 8) & 0x07;
495 insert_rrange (unsigned insn,
497 const char **errmsg ATTRIBUTE_UNUSED)
499 int reg1 = (value >> 16) & 0xFFFF;
500 int reg2 = value & 0xFFFF;
503 *errmsg = _("First register of the range should be r13.");
506 if (reg2 < 13 || reg2 > 26)
508 *errmsg = _("Last register of the range doesn't fit.");
511 insn |= ((reg2 - 12) & 0x0F) << 1;
516 extract_rrange (unsigned insn ATTRIBUTE_UNUSED,
517 bfd_boolean * invalid ATTRIBUTE_UNUSED)
519 return (insn >> 1) & 0x0F;
523 insert_fpel (unsigned insn,
525 const char **errmsg ATTRIBUTE_UNUSED)
529 *errmsg = _("Invalid register number, should be fp.");
538 extract_fpel (unsigned insn ATTRIBUTE_UNUSED,
539 bfd_boolean * invalid ATTRIBUTE_UNUSED)
541 return (insn & 0x0100) ? 27 : -1;
545 insert_blinkel (unsigned insn,
547 const char **errmsg ATTRIBUTE_UNUSED)
551 *errmsg = _("Invalid register number, should be blink.");
560 extract_blinkel (unsigned insn ATTRIBUTE_UNUSED,
561 bfd_boolean * invalid ATTRIBUTE_UNUSED)
563 return (insn & 0x0200) ? 31 : -1;
567 insert_pclel (unsigned insn,
569 const char **errmsg ATTRIBUTE_UNUSED)
573 *errmsg = _("Invalid register number, should be pcl.");
582 extract_pclel (unsigned insn ATTRIBUTE_UNUSED,
583 bfd_boolean * invalid ATTRIBUTE_UNUSED)
585 return (insn & 0x0400) ? 63 : -1;
589 /* mask = 00000000000000000000111111000000
590 insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */
592 insert_w6 (unsigned insn ATTRIBUTE_UNUSED,
593 int value ATTRIBUTE_UNUSED,
594 const char **errmsg ATTRIBUTE_UNUSED)
596 insn |= ((value >> 0) & 0x003f) << 6;
602 /* mask = 00000000000000000000111111000000. */
604 extract_w6 (unsigned insn ATTRIBUTE_UNUSED,
605 bfd_boolean * invalid ATTRIBUTE_UNUSED)
609 value |= ((insn >> 6) & 0x003f) << 0;
615 /* mask = 0000011100022000
616 insn = 01000ggghhhGG0HH. */
618 insert_g_s (unsigned insn ATTRIBUTE_UNUSED,
619 int value ATTRIBUTE_UNUSED,
620 const char **errmsg ATTRIBUTE_UNUSED)
622 insn |= ((value >> 0) & 0x0007) << 8;
623 insn |= ((value >> 3) & 0x0003) << 3;
629 /* mask = 0000011100022000. */
631 extract_g_s (unsigned insn ATTRIBUTE_UNUSED,
632 bfd_boolean * invalid ATTRIBUTE_UNUSED)
636 value |= ((insn >> 8) & 0x0007) << 0;
637 value |= ((insn >> 3) & 0x0003) << 3;
639 /* Extend the sign. */
640 int signbit = 1 << (6 - 1);
641 value = (value ^ signbit) - signbit;
646 /* ARC NPS400 Support: See comment near head of file. */
648 insert_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED,
649 int value ATTRIBUTE_UNUSED,
650 const char **errmsg ATTRIBUTE_UNUSED)
664 insn |= (value - 8) << 24;
667 *errmsg = _("Register must be either r0-r3 or r12-r15.");
674 extract_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED,
675 bfd_boolean * invalid ATTRIBUTE_UNUSED)
677 int value = (insn >> 24) & 0x07;
685 insert_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED,
686 int value ATTRIBUTE_UNUSED,
687 const char **errmsg ATTRIBUTE_UNUSED)
701 insn |= (value - 8) << 21;
704 *errmsg = _("Register must be either r0-r3 or r12-r15.");
711 extract_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED,
712 bfd_boolean * invalid ATTRIBUTE_UNUSED)
714 int value = (insn >> 21) & 0x07;
722 insert_nps_bitop_size_2b (unsigned insn ATTRIBUTE_UNUSED,
723 int value ATTRIBUTE_UNUSED,
724 const char **errmsg ATTRIBUTE_UNUSED)
742 *errmsg = _("Invalid size, should be 1, 2, 4, or 8.");
751 extract_nps_bitop_size_2b (unsigned insn ATTRIBUTE_UNUSED,
752 bfd_boolean * invalid ATTRIBUTE_UNUSED)
754 return 1 << ((insn >> 10) & 0x3);
758 insert_nps_bitop_uimm8 (unsigned insn ATTRIBUTE_UNUSED,
759 int value ATTRIBUTE_UNUSED,
760 const char **errmsg ATTRIBUTE_UNUSED)
762 insn |= ((value >> 5) & 7) << 12;
763 insn |= (value & 0x1f);
768 extract_nps_bitop_uimm8 (unsigned insn ATTRIBUTE_UNUSED,
769 bfd_boolean * invalid ATTRIBUTE_UNUSED)
771 return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f);
775 insert_nps_rflt_uimm6 (unsigned insn ATTRIBUTE_UNUSED,
776 int value ATTRIBUTE_UNUSED,
777 const char **errmsg ATTRIBUTE_UNUSED)
787 *errmsg = _("invalid immediate, must be 1, 2, or 4");
791 insn |= (value << 6);
796 extract_nps_rflt_uimm6 (unsigned insn ATTRIBUTE_UNUSED,
797 bfd_boolean * invalid ATTRIBUTE_UNUSED)
799 return (insn >> 6) & 0x3f;
803 insert_nps_dst_pos_and_size (unsigned insn ATTRIBUTE_UNUSED,
804 int value ATTRIBUTE_UNUSED,
805 const char **errmsg ATTRIBUTE_UNUSED)
807 insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10));
812 extract_nps_dst_pos_and_size (unsigned insn ATTRIBUTE_UNUSED,
813 bfd_boolean * invalid ATTRIBUTE_UNUSED)
815 return (insn & 0x1f);
819 insert_nps_cmem_uimm16 (unsigned insn ATTRIBUTE_UNUSED,
820 int value ATTRIBUTE_UNUSED,
821 const char **errmsg ATTRIBUTE_UNUSED)
823 int top = (value >> 16) & 0xffff;
824 if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE)
825 *errmsg = _("invalid value for CMEM ld/st immediate");
826 insn |= (value & 0xffff);
831 extract_nps_cmem_uimm16 (unsigned insn ATTRIBUTE_UNUSED,
832 bfd_boolean * invalid ATTRIBUTE_UNUSED)
834 return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff);
837 #define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \
839 insert_nps_##NAME##_pos (unsigned insn ATTRIBUTE_UNUSED, \
840 int value ATTRIBUTE_UNUSED, \
841 const char **errmsg ATTRIBUTE_UNUSED) \
852 *errmsg = _("Invalid position, should be 0, 8, 16, or 24."); \
855 insn |= (value << SHIFT); \
860 extract_nps_##NAME##_pos (unsigned insn ATTRIBUTE_UNUSED, \
861 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
863 return ((insn >> SHIFT) & 0x3) * 8; \
866 MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12)
867 MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10)
869 #define MAKE_SIZE_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT)\
871 insert_nps_##NAME##_size (unsigned insn ATTRIBUTE_UNUSED, \
872 int value ATTRIBUTE_UNUSED, \
873 const char **errmsg ATTRIBUTE_UNUSED) \
875 if (value < LOWER || value > 32) \
877 *errmsg = _("Invalid size, value must be " \
878 #LOWER " to " #UPPER "."); \
882 insn |= (value << SHIFT); \
887 extract_nps_##NAME##_size (unsigned insn ATTRIBUTE_UNUSED, \
888 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
890 return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \
893 MAKE_SIZE_INSERT_EXTRACT_FUNCS(addb,2,32,5,1,5)
894 MAKE_SIZE_INSERT_EXTRACT_FUNCS(andb,1,32,5,1,5)
895 MAKE_SIZE_INSERT_EXTRACT_FUNCS(fxorb,8,32,5,8,5)
896 MAKE_SIZE_INSERT_EXTRACT_FUNCS(wxorb,16,32,5,16,5)
897 MAKE_SIZE_INSERT_EXTRACT_FUNCS(bitop,1,32,5,1,10)
898 MAKE_SIZE_INSERT_EXTRACT_FUNCS(qcmp,1,8,3,1,9)
901 extract_nps_qcmp_m3 (unsigned insn ATTRIBUTE_UNUSED,
902 bfd_boolean * invalid ATTRIBUTE_UNUSED)
904 int m3 = (insn >> 5) & 0xf;
911 extract_nps_qcmp_m2 (unsigned insn ATTRIBUTE_UNUSED,
912 bfd_boolean * invalid ATTRIBUTE_UNUSED)
914 bfd_boolean tmp_invalid = FALSE;
915 int m2 = (insn >> 15) & 0x1;
916 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
918 if (m2 == 0 && m3 == 0xf)
924 extract_nps_qcmp_m1 (unsigned insn ATTRIBUTE_UNUSED,
925 bfd_boolean * invalid ATTRIBUTE_UNUSED)
927 bfd_boolean tmp_invalid = FALSE;
928 int m1 = (insn >> 14) & 0x1;
929 int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid);
930 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
932 if (m1 == 0 && m2 == 0 && m3 == 0xf)
938 insert_nps_calc_entry_size (unsigned insn ATTRIBUTE_UNUSED,
939 int value ATTRIBUTE_UNUSED,
940 const char **errmsg ATTRIBUTE_UNUSED)
944 if (value < 1 || value > 256)
946 *errmsg = _("value out of range 1 - 256");
950 for (pwr = 0; (value & 1) == 0; value >>= 1)
955 *errmsg = _("value must be power of 2");
959 return insn | (pwr << 8);
963 extract_nps_calc_entry_size (unsigned insn ATTRIBUTE_UNUSED,
964 bfd_boolean * invalid ATTRIBUTE_UNUSED)
966 unsigned entry_size = (insn >> 8) & 0xf;
967 return 1 << entry_size;
970 /* Include the generic extract/insert functions. Order is important
971 as some of the functions present in the .h may be disabled via
975 /* The flag operands table.
977 The format of the table is
978 NAME CODE BITS SHIFT FAVAIL. */
979 const struct arc_flag_operand arc_flag_operands[] =
983 #define F_ALWAYS (F_NULL + 1)
984 { "al", 0, 0, 0, 0 },
985 #define F_RA (F_ALWAYS + 1)
986 { "ra", 0, 0, 0, 0 },
987 #define F_EQUAL (F_RA + 1)
988 { "eq", 1, 5, 0, 1 },
989 #define F_ZERO (F_EQUAL + 1)
991 #define F_NOTEQUAL (F_ZERO + 1)
992 { "ne", 2, 5, 0, 1 },
993 #define F_NOTZERO (F_NOTEQUAL + 1)
994 { "nz", 2, 5, 0, 0 },
995 #define F_POZITIVE (F_NOTZERO + 1)
997 #define F_PL (F_POZITIVE + 1)
998 { "pl", 3, 5, 0, 0 },
999 #define F_NEGATIVE (F_PL + 1)
1000 { "n", 4, 5, 0, 1 },
1001 #define F_MINUS (F_NEGATIVE + 1)
1002 { "mi", 4, 5, 0, 0 },
1003 #define F_CARRY (F_MINUS + 1)
1004 { "c", 5, 5, 0, 1 },
1005 #define F_CARRYSET (F_CARRY + 1)
1006 { "cs", 5, 5, 0, 0 },
1007 #define F_LOWER (F_CARRYSET + 1)
1008 { "lo", 5, 5, 0, 0 },
1009 #define F_CARRYCLR (F_LOWER + 1)
1010 { "cc", 6, 5, 0, 0 },
1011 #define F_NOTCARRY (F_CARRYCLR + 1)
1012 { "nc", 6, 5, 0, 1 },
1013 #define F_HIGHER (F_NOTCARRY + 1)
1014 { "hs", 6, 5, 0, 0 },
1015 #define F_OVERFLOWSET (F_HIGHER + 1)
1016 { "vs", 7, 5, 0, 0 },
1017 #define F_OVERFLOW (F_OVERFLOWSET + 1)
1018 { "v", 7, 5, 0, 1 },
1019 #define F_NOTOVERFLOW (F_OVERFLOW + 1)
1020 { "nv", 8, 5, 0, 1 },
1021 #define F_OVERFLOWCLR (F_NOTOVERFLOW + 1)
1022 { "vc", 8, 5, 0, 0 },
1023 #define F_GT (F_OVERFLOWCLR + 1)
1024 { "gt", 9, 5, 0, 1 },
1025 #define F_GE (F_GT + 1)
1026 { "ge", 10, 5, 0, 1 },
1027 #define F_LT (F_GE + 1)
1028 { "lt", 11, 5, 0, 1 },
1029 #define F_LE (F_LT + 1)
1030 { "le", 12, 5, 0, 1 },
1031 #define F_HI (F_LE + 1)
1032 { "hi", 13, 5, 0, 1 },
1033 #define F_LS (F_HI + 1)
1034 { "ls", 14, 5, 0, 1 },
1035 #define F_PNZ (F_LS + 1)
1036 { "pnz", 15, 5, 0, 1 },
1039 #define F_FLAG (F_PNZ + 1)
1040 { "f", 1, 1, 15, 1 },
1041 #define F_FFAKE (F_FLAG + 1)
1042 { "f", 0, 0, 0, 1 },
1045 #define F_ND (F_FFAKE + 1)
1046 { "nd", 0, 1, 5, 0 },
1047 #define F_D (F_ND + 1)
1048 { "d", 1, 1, 5, 1 },
1049 #define F_DFAKE (F_D + 1)
1050 { "d", 0, 0, 0, 1 },
1053 #define F_SIZEB1 (F_DFAKE + 1)
1054 { "b", 1, 2, 1, 1 },
1055 #define F_SIZEB7 (F_SIZEB1 + 1)
1056 { "b", 1, 2, 7, 1 },
1057 #define F_SIZEB17 (F_SIZEB7 + 1)
1058 { "b", 1, 2, 17, 1 },
1059 #define F_SIZEW1 (F_SIZEB17 + 1)
1060 { "w", 2, 2, 1, 0 },
1061 #define F_SIZEW7 (F_SIZEW1 + 1)
1062 { "w", 2, 2, 7, 0 },
1063 #define F_SIZEW17 (F_SIZEW7 + 1)
1064 { "w", 2, 2, 17, 0 },
1066 /* Sign extension. */
1067 #define F_SIGN6 (F_SIZEW17 + 1)
1068 { "x", 1, 1, 6, 1 },
1069 #define F_SIGN16 (F_SIGN6 + 1)
1070 { "x", 1, 1, 16, 1 },
1071 #define F_SIGNX (F_SIGN16 + 1)
1072 { "x", 0, 0, 0, 1 },
1074 /* Address write-back modes. */
1075 #define F_A3 (F_SIGNX + 1)
1076 { "a", 1, 2, 3, 0 },
1077 #define F_A9 (F_A3 + 1)
1078 { "a", 1, 2, 9, 0 },
1079 #define F_A22 (F_A9 + 1)
1080 { "a", 1, 2, 22, 0 },
1081 #define F_AW3 (F_A22 + 1)
1082 { "aw", 1, 2, 3, 1 },
1083 #define F_AW9 (F_AW3 + 1)
1084 { "aw", 1, 2, 9, 1 },
1085 #define F_AW22 (F_AW9 + 1)
1086 { "aw", 1, 2, 22, 1 },
1087 #define F_AB3 (F_AW22 + 1)
1088 { "ab", 2, 2, 3, 1 },
1089 #define F_AB9 (F_AB3 + 1)
1090 { "ab", 2, 2, 9, 1 },
1091 #define F_AB22 (F_AB9 + 1)
1092 { "ab", 2, 2, 22, 1 },
1093 #define F_AS3 (F_AB22 + 1)
1094 { "as", 3, 2, 3, 1 },
1095 #define F_AS9 (F_AS3 + 1)
1096 { "as", 3, 2, 9, 1 },
1097 #define F_AS22 (F_AS9 + 1)
1098 { "as", 3, 2, 22, 1 },
1099 #define F_ASFAKE (F_AS22 + 1)
1100 { "as", 0, 0, 0, 1 },
1103 #define F_DI5 (F_ASFAKE + 1)
1104 { "di", 1, 1, 5, 1 },
1105 #define F_DI11 (F_DI5 + 1)
1106 { "di", 1, 1, 11, 1 },
1107 #define F_DI15 (F_DI11 + 1)
1108 { "di", 1, 1, 15, 1 },
1110 /* ARCv2 specific. */
1111 #define F_NT (F_DI15 + 1)
1112 { "nt", 0, 1, 3, 1},
1113 #define F_T (F_NT + 1)
1115 #define F_H1 (F_T + 1)
1116 { "h", 2, 2, 1, 1 },
1117 #define F_H7 (F_H1 + 1)
1118 { "h", 2, 2, 7, 1 },
1119 #define F_H17 (F_H7 + 1)
1120 { "h", 2, 2, 17, 1 },
1123 #define F_NE (F_H17 + 1)
1124 { "ne", 0, 0, 0, 1 },
1126 /* ARC NPS400 Support: See comment near head of file. */
1127 #define F_NPS_CL (F_NE + 1)
1128 { "cl", 0, 0, 0, 1 },
1130 #define F_NPS_FLAG (F_NPS_CL + 1)
1131 { "f", 1, 1, 20, 1 },
1133 #define F_NPS_R (F_NPS_FLAG + 1)
1134 { "r", 1, 1, 15, 1 },
1136 #define F_NPS_RW (F_NPS_R + 1)
1137 { "rw", 0, 1, 7, 1 },
1139 #define F_NPS_RD (F_NPS_RW + 1)
1140 { "rd", 1, 1, 7, 1 },
1142 #define F_NPS_WFT (F_NPS_RD + 1)
1143 { "wft", 0, 0, 0, 1 },
1145 #define F_NPS_IE1 (F_NPS_WFT + 1)
1146 { "ie1", 1, 2, 8, 1 },
1148 #define F_NPS_IE2 (F_NPS_IE1 + 1)
1149 { "ie2", 2, 2, 8, 1 },
1151 #define F_NPS_IE12 (F_NPS_IE2 + 1)
1152 { "ie12", 3, 2, 8, 1 },
1154 #define F_NPS_SYNC_RD (F_NPS_IE12 + 1)
1155 { "rd", 0, 1, 6, 1 },
1157 #define F_NPS_SYNC_WR (F_NPS_SYNC_RD + 1)
1158 { "wr", 1, 1, 6, 1 },
1160 #define F_NPS_HWS_OFF (F_NPS_SYNC_WR + 1)
1161 { "off", 0, 0, 0, 1 },
1163 #define F_NPS_HWS_RESTORE (F_NPS_HWS_OFF + 1)
1164 { "restore", 0, 0, 0, 1 },
1166 #define F_NPS_SX (F_NPS_HWS_RESTORE + 1)
1167 { "sx", 1, 1, 14, 1 },
1169 #define F_NPS_AR (F_NPS_SX + 1)
1170 { "ar", 0, 1, 0, 1 },
1172 #define F_NPS_AL (F_NPS_AR + 1)
1173 { "al", 1, 1, 0, 1 },
1176 const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
1178 /* Table of the flag classes.
1180 The format of the table is
1181 CLASS {FLAG_CODE}. */
1182 const struct arc_flag_class arc_flag_classes[] =
1185 { F_CLASS_NONE, { F_NULL } },
1187 #define C_CC (C_EMPTY + 1)
1188 { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND,
1189 { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
1190 F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
1191 F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1192 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
1193 F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
1194 F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1196 #define C_AA_ADDR3 (C_CC + 1)
1197 #define C_AA27 (C_CC + 1)
1198 { F_CLASS_OPTIONAL, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
1199 #define C_AA_ADDR9 (C_AA_ADDR3 + 1)
1200 #define C_AA21 (C_AA_ADDR3 + 1)
1201 { F_CLASS_OPTIONAL, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
1202 #define C_AA_ADDR22 (C_AA_ADDR9 + 1)
1203 #define C_AA8 (C_AA_ADDR9 + 1)
1204 { F_CLASS_OPTIONAL, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
1206 #define C_F (C_AA_ADDR22 + 1)
1207 { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },
1208 #define C_FHARD (C_F + 1)
1209 { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } },
1211 #define C_T (C_FHARD + 1)
1212 { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
1213 #define C_D (C_T + 1)
1214 { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
1216 #define C_DHARD (C_D + 1)
1217 { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
1219 #define C_DI20 (C_DHARD + 1)
1220 { F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
1221 #define C_DI16 (C_DI20 + 1)
1222 { F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
1223 #define C_DI26 (C_DI16 + 1)
1224 { F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
1226 #define C_X25 (C_DI26 + 1)
1227 { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }},
1228 #define C_X15 (C_X25 + 1)
1229 { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }},
1230 #define C_XHARD (C_X15 + 1)
1231 #define C_X (C_X15 + 1)
1232 { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }},
1234 #define C_ZZ13 (C_X + 1)
1235 { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
1236 #define C_ZZ23 (C_ZZ13 + 1)
1237 { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
1238 #define C_ZZ29 (C_ZZ23 + 1)
1239 { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
1241 #define C_AS (C_ZZ29 + 1)
1242 { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
1244 #define C_NE (C_AS + 1)
1245 { F_CLASS_OPTIONAL, { F_NE, F_NULL}},
1247 /* ARC NPS400 Support: See comment near head of file. */
1248 #define C_NPS_CL (C_NE + 1)
1249 { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}},
1251 #define C_NPS_F (C_NPS_CL + 1)
1252 { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
1254 #define C_NPS_R (C_NPS_F + 1)
1255 { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}},
1257 #define C_NPS_SCHD_RW (C_NPS_R + 1)
1258 { F_CLASS_REQUIRED, { F_NPS_RW, F_NPS_RD, F_NULL}},
1260 #define C_NPS_SCHD_TRIG (C_NPS_SCHD_RW + 1)
1261 { F_CLASS_REQUIRED, { F_NPS_WFT, F_NULL}},
1263 #define C_NPS_SCHD_IE (C_NPS_SCHD_TRIG + 1)
1264 { F_CLASS_OPTIONAL, { F_NPS_IE1, F_NPS_IE2, F_NPS_IE12, F_NULL}},
1266 #define C_NPS_SYNC (C_NPS_SCHD_IE + 1)
1267 { F_CLASS_REQUIRED, { F_NPS_SYNC_RD, F_NPS_SYNC_WR, F_NULL}},
1269 #define C_NPS_HWS_OFF (C_NPS_SYNC + 1)
1270 { F_CLASS_REQUIRED, { F_NPS_HWS_OFF, F_NULL}},
1272 #define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1)
1273 { F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}},
1275 #define C_NPS_SX (C_NPS_HWS_RESTORE + 1)
1276 { F_CLASS_OPTIONAL, { F_NPS_SX, F_NULL}},
1278 #define C_NPS_AR_AL (C_NPS_SX + 1)
1279 { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}},
1282 const unsigned char flags_none[] = { 0 };
1283 const unsigned char flags_f[] = { C_F };
1284 const unsigned char flags_cc[] = { C_CC };
1285 const unsigned char flags_ccf[] = { C_CC, C_F };
1287 /* The operands table.
1289 The format of the operands table is:
1291 BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */
1292 const struct arc_operand arc_operands[] =
1294 /* The fields are bits, shift, insert, extract, flags. The zero
1295 index is used to indicate end-of-list. */
1297 { 0, 0, 0, 0, 0, 0 },
1298 /* The plain integer register fields. Used by 32 bit
1300 #define RA (UNUSED + 1)
1301 { 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
1303 { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
1305 { 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
1306 #define RBdup (RC + 1)
1307 { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
1309 #define RAD (RBdup + 1)
1310 { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
1311 #define RCD (RAD + 1)
1312 { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
1314 /* The plain integer register fields. Used by short
1316 #define RA16 (RCD + 1)
1317 #define RA_S (RCD + 1)
1318 { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
1319 #define RB16 (RA16 + 1)
1320 #define RB_S (RA16 + 1)
1321 { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs },
1322 #define RB16dup (RB16 + 1)
1323 #define RB_Sdup (RB16 + 1)
1324 { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs },
1325 #define RC16 (RB16dup + 1)
1326 #define RC_S (RB16dup + 1)
1327 { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs },
1328 #define R6H (RC16 + 1) /* 6bit register field 'h' used
1330 { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 },
1331 #define R5H (R6H + 1) /* 5bit register field 'h' used
1333 #define RH_S (R6H + 1) /* 5bit register field 'h' used
1335 { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 },
1336 #define R5Hdup (R5H + 1)
1337 #define RH_Sdup (R5H + 1)
1338 { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE,
1339 insert_rhv2, extract_rhv2 },
1341 #define RG (R5Hdup + 1)
1342 #define G_S (R5Hdup + 1)
1343 { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s },
1345 /* Fix registers. */
1347 #define R0_S (RG + 1)
1348 { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 },
1350 #define R1_S (R0 + 1)
1351 { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 },
1353 #define R2_S (R1 + 1)
1354 { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 },
1356 #define R3_S (R2 + 1)
1357 { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 },
1358 #define RSP (R3 + 1)
1359 #define SP_S (R3 + 1)
1360 { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp },
1361 #define SPdup (RSP + 1)
1362 #define SP_Sdup (RSP + 1)
1363 { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp },
1364 #define GP (SPdup + 1)
1365 #define GP_S (SPdup + 1)
1366 { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp },
1368 #define PCL_S (GP + 1)
1369 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl },
1371 #define BLINK (PCL_S + 1)
1372 #define BLINK_S (PCL_S + 1)
1373 { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink },
1375 #define ILINK1 (BLINK + 1)
1376 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 },
1377 #define ILINK2 (ILINK1 + 1)
1378 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 },
1380 /* Long immediate. */
1381 #define LIMM (ILINK2 + 1)
1382 #define LIMM_S (ILINK2 + 1)
1383 { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
1384 #define LIMMdup (LIMM + 1)
1385 { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 },
1387 /* Special operands. */
1388 #define ZA (LIMMdup + 1)
1389 #define ZB (LIMMdup + 1)
1390 #define ZA_S (LIMMdup + 1)
1391 #define ZB_S (LIMMdup + 1)
1392 #define ZC_S (LIMMdup + 1)
1393 { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 },
1395 #define RRANGE_EL (ZA + 1)
1396 { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
1397 insert_rrange, extract_rrange},
1398 #define FP_EL (RRANGE_EL + 1)
1399 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1400 insert_fpel, extract_fpel },
1401 #define BLINK_EL (FP_EL + 1)
1402 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1403 insert_blinkel, extract_blinkel },
1404 #define PCL_EL (BLINK_EL + 1)
1405 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1406 insert_pclel, extract_pclel },
1408 /* Fake operand to handle the T flag. */
1409 #define BRAKET (PCL_EL + 1)
1410 #define BRAKETdup (PCL_EL + 1)
1411 { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 },
1413 /* Fake operand to handle the T flag. */
1414 #define FKT_T (BRAKET + 1)
1415 { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 },
1416 /* Fake operand to handle the T flag. */
1417 #define FKT_NT (FKT_T + 1)
1418 { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 },
1420 /* UIMM6_20 mask = 00000000000000000000111111000000. */
1421 #define UIMM6_20 (FKT_NT + 1)
1422 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
1424 /* SIMM12_20 mask = 00000000000000000000111111222222. */
1425 #define SIMM12_20 (UIMM6_20 + 1)
1426 {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
1428 /* SIMM3_5_S mask = 0000011100000000. */
1429 #define SIMM3_5_S (SIMM12_20 + 1)
1430 {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
1431 insert_simm3s, extract_simm3s},
1433 /* UIMM7_A32_11_S mask = 0000000000011111. */
1434 #define UIMM7_A32_11_S (SIMM3_5_S + 1)
1435 {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1436 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
1437 extract_uimm7_a32_11_s},
1439 /* UIMM7_9_S mask = 0000000001111111. */
1440 #define UIMM7_9_S (UIMM7_A32_11_S + 1)
1441 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
1443 /* UIMM3_13_S mask = 0000000000000111. */
1444 #define UIMM3_13_S (UIMM7_9_S + 1)
1445 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
1447 /* SIMM11_A32_7_S mask = 0000000111111111. */
1448 #define SIMM11_A32_7_S (UIMM3_13_S + 1)
1449 {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1450 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
1452 /* UIMM6_13_S mask = 0000000002220111. */
1453 #define UIMM6_13_S (SIMM11_A32_7_S + 1)
1454 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s},
1455 /* UIMM5_11_S mask = 0000000000011111. */
1456 #define UIMM5_11_S (UIMM6_13_S + 1)
1457 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s,
1458 extract_uimm5_11_s},
1460 /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
1461 #define SIMM9_A16_8 (UIMM5_11_S + 1)
1462 {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1463 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8,
1464 extract_simm9_a16_8},
1466 /* UIMM6_8 mask = 00000000000000000000111111000000. */
1467 #define UIMM6_8 (SIMM9_A16_8 + 1)
1468 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8},
1470 /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
1471 #define SIMM21_A16_5 (UIMM6_8 + 1)
1472 {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
1473 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE,
1474 insert_simm21_a16_5, extract_simm21_a16_5},
1476 /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
1477 #define SIMM25_A16_5 (SIMM21_A16_5 + 1)
1478 {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED
1479 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
1480 insert_simm25_a16_5, extract_simm25_a16_5},
1482 /* SIMM10_A16_7_S mask = 0000000111111111. */
1483 #define SIMM10_A16_7_S (SIMM25_A16_5 + 1)
1484 {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1485 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s,
1486 extract_simm10_a16_7_s},
1488 #define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1)
1489 {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1490 | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s},
1492 /* SIMM7_A16_10_S mask = 0000000000111111. */
1493 #define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1)
1494 {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1495 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s,
1496 extract_simm7_a16_10_s},
1498 /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */
1499 #define SIMM21_A32_5 (SIMM7_A16_10_S + 1)
1500 {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1501 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5,
1502 extract_simm21_a32_5},
1504 /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */
1505 #define SIMM25_A32_5 (SIMM21_A32_5 + 1)
1506 {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1507 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5,
1508 extract_simm25_a32_5},
1510 /* SIMM13_A32_5_S mask = 0000011111111111. */
1511 #define SIMM13_A32_5_S (SIMM25_A32_5 + 1)
1512 {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1513 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s,
1514 extract_simm13_a32_5_s},
1516 /* SIMM8_A16_9_S mask = 0000000001111111. */
1517 #define SIMM8_A16_9_S (SIMM13_A32_5_S + 1)
1518 {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1519 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
1520 extract_simm8_a16_9_s},
1522 /* UIMM3_23 mask = 00000000000000000000000111000000. */
1523 #define UIMM3_23 (SIMM8_A16_9_S + 1)
1524 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23},
1526 /* UIMM10_6_S mask = 0000001111111111. */
1527 #define UIMM10_6_S (UIMM3_23 + 1)
1528 {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s},
1530 /* UIMM6_11_S mask = 0000002200011110. */
1531 #define UIMM6_11_S (UIMM10_6_S + 1)
1532 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s},
1534 /* SIMM9_8 mask = 00000000111111112000000000000000. */
1535 #define SIMM9_8 (UIMM6_11_S + 1)
1536 {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
1537 insert_simm9_8, extract_simm9_8},
1539 /* UIMM10_A32_8_S mask = 0000000011111111. */
1540 #define UIMM10_A32_8_S (SIMM9_8 + 1)
1541 {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1542 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
1543 extract_uimm10_a32_8_s},
1545 /* SIMM9_7_S mask = 0000000111111111. */
1546 #define SIMM9_7_S (UIMM10_A32_8_S + 1)
1547 {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s,
1550 /* UIMM6_A16_11_S mask = 0000000000011111. */
1551 #define UIMM6_A16_11_S (SIMM9_7_S + 1)
1552 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1553 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s,
1554 extract_uimm6_a16_11_s},
1556 /* UIMM5_A32_11_S mask = 0000020000011000. */
1557 #define UIMM5_A32_11_S (UIMM6_A16_11_S + 1)
1558 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1559 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s,
1560 extract_uimm5_a32_11_s},
1562 /* SIMM11_A32_13_S mask = 0000022222200111. */
1563 #define SIMM11_A32_13_S (UIMM5_A32_11_S + 1)
1564 {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1565 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s},
1567 /* UIMM7_13_S mask = 0000000022220111. */
1568 #define UIMM7_13_S (SIMM11_A32_13_S + 1)
1569 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s},
1571 /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */
1572 #define UIMM6_A16_21 (UIMM7_13_S + 1)
1573 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1574 | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21},
1576 /* UIMM7_11_S mask = 0000022200011110. */
1577 #define UIMM7_11_S (UIMM6_A16_21 + 1)
1578 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s},
1580 /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */
1581 #define UIMM7_A16_20 (UIMM7_11_S + 1)
1582 {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1583 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20,
1584 extract_uimm7_a16_20},
1586 /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
1587 #define SIMM13_A16_20 (UIMM7_A16_20 + 1)
1588 {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1589 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20,
1590 extract_simm13_a16_20},
1592 /* UIMM8_8_S mask = 0000000011111111. */
1593 #define UIMM8_8_S (SIMM13_A16_20 + 1)
1594 {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
1596 /* W6 mask = 00000000000000000000111111000000. */
1597 #define W6 (UIMM8_8_S + 1)
1598 {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
1600 /* UIMM6_5_S mask = 0000011111100000. */
1601 #define UIMM6_5_S (W6 + 1)
1602 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
1604 /* ARC NPS400 Support: See comment near head of file. */
1605 #define NPS_R_DST_3B (UIMM6_5_S + 1)
1606 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
1608 #define NPS_R_SRC1_3B (NPS_R_DST_3B + 1)
1609 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
1611 #define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1)
1612 { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_src2, extract_nps_3bit_src2 },
1614 #define NPS_R_DST (NPS_R_SRC2_3B + 1)
1615 { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL },
1617 #define NPS_R_SRC1 (NPS_R_DST + 1)
1618 { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
1620 #define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1)
1621 { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
1623 #define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
1624 { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
1626 #define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
1627 { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size, extract_nps_bitop_size },
1629 #define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1)
1630 { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size },
1632 #define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1)
1633 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size_2b, extract_nps_bitop_size_2b },
1635 #define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1)
1636 { 8, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 },
1638 #define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1)
1639 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1641 #define NPS_RFLT_UIMM6 (NPS_UIMM16 + 1)
1642 { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 },
1644 #define NPS_XLDST_UIMM16 (NPS_RFLT_UIMM6 + 1)
1645 { 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_cmem_uimm16, extract_nps_cmem_uimm16 },
1647 #define NPS_SRC2_POS (NPS_XLDST_UIMM16 + 1)
1648 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src2_pos, extract_nps_src2_pos },
1650 #define NPS_SRC1_POS (NPS_SRC2_POS + 1)
1651 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src1_pos, extract_nps_src1_pos },
1653 #define NPS_ADDB_SIZE (NPS_SRC1_POS + 1)
1654 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_addb_size, extract_nps_addb_size },
1656 #define NPS_ANDB_SIZE (NPS_ADDB_SIZE + 1)
1657 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_andb_size, extract_nps_andb_size },
1659 #define NPS_FXORB_SIZE (NPS_ANDB_SIZE + 1)
1660 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_fxorb_size, extract_nps_fxorb_size },
1662 #define NPS_WXORB_SIZE (NPS_FXORB_SIZE + 1)
1663 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_wxorb_size, extract_nps_wxorb_size },
1665 #define NPS_R_XLDST (NPS_WXORB_SIZE + 1)
1666 { 6, 5, 0, ARC_OPERAND_IR, NULL, NULL },
1668 #define NPS_DIV_UIMM4 (NPS_R_XLDST + 1)
1669 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1671 #define NPS_QCMP_SIZE (NPS_DIV_UIMM4 + 1)
1672 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_qcmp_size, extract_nps_qcmp_size },
1674 #define NPS_QCMP_M1 (NPS_QCMP_SIZE + 1)
1675 { 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1 },
1677 #define NPS_QCMP_M2 (NPS_QCMP_M1 + 1)
1678 { 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2 },
1680 #define NPS_QCMP_M3 (NPS_QCMP_M2 + 1)
1681 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3 },
1683 #define NPS_CALC_ENTRY_SIZE (NPS_QCMP_M3 + 1)
1684 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_calc_entry_size, extract_nps_calc_entry_size },
1687 const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
1689 const unsigned arc_Toperand = FKT_T;
1690 const unsigned arc_NToperand = FKT_NT;
1692 const unsigned char arg_none[] = { 0 };
1693 const unsigned char arg_32bit_rarbrc[] = { RA, RB, RC };
1694 const unsigned char arg_32bit_zarbrc[] = { ZA, RB, RC };
1695 const unsigned char arg_32bit_rbrbrc[] = { RB, RBdup, RC };
1696 const unsigned char arg_32bit_rarbu6[] = { RA, RB, UIMM6_20 };
1697 const unsigned char arg_32bit_zarbu6[] = { ZA, RB, UIMM6_20 };
1698 const unsigned char arg_32bit_rbrbu6[] = { RB, RBdup, UIMM6_20 };
1699 const unsigned char arg_32bit_rbrbs12[] = { RB, RBdup, SIMM12_20 };
1700 const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC };
1701 const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM };
1702 const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC };
1703 const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM };
1705 const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM };
1706 const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 };
1707 const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 };
1709 const unsigned char arg_32bit_zalimms12[] = { ZA, LIMM, SIMM12_20 };
1710 const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup };
1711 const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup };
1713 const unsigned char arg_32bit_rbrc[] = { RB, RC };
1714 const unsigned char arg_32bit_zarc[] = { ZA, RC };
1715 const unsigned char arg_32bit_rbu6[] = { RB, UIMM6_20 };
1716 const unsigned char arg_32bit_zau6[] = { ZA, UIMM6_20 };
1717 const unsigned char arg_32bit_rblimm[] = { RB, LIMM };
1718 const unsigned char arg_32bit_zalimm[] = { ZA, LIMM };
1720 const unsigned char arg_32bit_limmrc[] = { LIMM, RC };
1721 const unsigned char arg_32bit_limmu6[] = { LIMM, UIMM6_20 };
1722 const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 };
1723 const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup };
1725 const unsigned char arg_32bit_rc[] = { RC };
1726 const unsigned char arg_32bit_u6[] = { UIMM6_20 };
1727 const unsigned char arg_32bit_limm[] = { LIMM };
1729 /* The opcode table.
1731 The format of the opcode table is:
1733 NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }.
1735 The table is organised such that, where possible, all instructions with
1736 the same mnemonic are together in a block. When the assembler searches
1737 for a suitable instruction the entries are checked in table order, so
1738 more specific, or specialised cases should appear earlier in the table.
1740 As an example, consider two instructions 'add a,b,u6' and 'add
1741 a,b,limm'. The first takes a 6-bit immediate that is encoded within the
1742 32-bit instruction, while the second takes a 32-bit immediate that is
1743 encoded in a follow-on 32-bit, making the total instruction length
1744 64-bits. In this case the u6 variant must appear first in the table, as
1745 all u6 immediates could also be encoded using the 'limm' extension,
1746 however, we want to use the shorter instruction wherever possible.
1748 It is possible though to split instructions with the same mnemonic into
1749 multiple groups. However, the instructions are still checked in table
1750 order, even across groups. The only time that instructions with the
1751 same mnemonic should be split into different groups is when different
1752 variants of the instruction appear in different architectures, in which
1753 case, grouping all instructions from a particular architecture together
1754 might be preferable to merging the instruction into the main instruction
1757 An example of this split instruction groups can be found with the 'sync'
1758 instruction. The core arc architecture provides a 'sync' instruction,
1759 while the nps instruction set extension provides 'sync.rd' and
1760 'sync.wr'. The rd/wr flags are instruction flags, not part of the
1761 mnemonic, so we end up with two groups for the sync instruction, the
1762 first within the core arc instruction table, and the second within the
1763 nps extension instructions. */
1764 const struct arc_opcode arc_opcodes[] =
1766 #include "arc-tbl.h"
1767 #include "arc-nps400-tbl.h"
1768 #include "arc-ext-tbl.h"
1770 { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } }
1773 /* List with special cases instructions and the applicable flags. */
1774 const struct arc_flag_special arc_flag_special_cases[] =
1776 { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1777 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1778 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1779 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1780 { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1781 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1782 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1783 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1784 { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1785 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1786 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1787 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1788 { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1789 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1790 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1791 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1792 { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1793 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1794 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1795 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1796 { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1797 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1798 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1799 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1800 { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1801 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1802 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1803 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1804 { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } },
1805 { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } }
1808 const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
1811 const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
1813 { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
1814 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1815 { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
1816 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1817 { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
1818 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1819 { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
1820 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1822 /* Next two entries will cover the undefined behavior ldb/stb with
1824 { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
1825 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
1826 { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
1827 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
1829 { "sda", "ld", { F_ASFAKE, F_NULL },
1830 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
1831 { "sda", "st", { F_ASFAKE, F_NULL },
1832 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
1833 { "sda", "ldd", { F_ASFAKE, F_NULL },
1834 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
1835 { "sda", "std", { F_ASFAKE, F_NULL },
1836 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
1838 /* Short instructions. */
1839 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
1840 { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
1841 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
1842 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
1844 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
1845 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
1847 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
1848 BFD_RELOC_ARC_S25H_PCREL_PLT },
1849 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
1850 BFD_RELOC_ARC_S21H_PCREL_PLT },
1851 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
1852 BFD_RELOC_ARC_S25W_PCREL_PLT },
1853 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
1854 BFD_RELOC_ARC_S21W_PCREL_PLT },
1856 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
1859 const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
1861 const struct arc_pseudo_insn arc_pseudo_insns[] =
1863 { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
1864 { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
1865 { BRAKETdup, 1, 0, 4} } },
1866 { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
1867 { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
1868 { BRAKETdup, 1, 0, 4} } },
1870 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1871 { SIMM9_A16_8, 0, 0, 2 } } },
1872 { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1873 { SIMM9_A16_8, 0, 0, 2 } } },
1874 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1875 { SIMM9_A16_8, 0, 0, 2 } } },
1876 { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1877 { SIMM9_A16_8, 0, 0, 2 } } },
1878 { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1879 { SIMM9_A16_8, 0, 0, 2 } } },
1881 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1882 { SIMM9_A16_8, 0, 0, 2 } } },
1883 { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1884 { SIMM9_A16_8, 0, 0, 2 } } },
1885 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1886 { SIMM9_A16_8, 0, 0, 2 } } },
1887 { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1888 { SIMM9_A16_8, 0, 0, 2 } } },
1889 { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1890 { SIMM9_A16_8, 0, 0, 2 } } },
1892 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1893 { SIMM9_A16_8, 0, 0, 2 } } },
1894 { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1895 { SIMM9_A16_8, 0, 0, 2 } } },
1896 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1897 { SIMM9_A16_8, 0, 0, 2 } } },
1898 { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1899 { SIMM9_A16_8, 0, 0, 2 } } },
1900 { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1901 { SIMM9_A16_8, 0, 0, 2 } } },
1903 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1904 { SIMM9_A16_8, 0, 0, 2 } } },
1905 { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1906 { SIMM9_A16_8, 0, 0, 2 } } },
1907 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1908 { SIMM9_A16_8, 0, 0, 2 } } },
1909 { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1910 { SIMM9_A16_8, 0, 0, 2 } } },
1911 { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1912 { SIMM9_A16_8, 0, 0, 2 } } },
1915 const unsigned arc_num_pseudo_insn =
1916 sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
1918 const struct arc_aux_reg arc_aux_regs[] =
1921 #define DEF(ADDR, CPU, SUBCLASS, NAME) \
1922 { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 },
1924 #include "arc-regs.h"
1929 const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);
1931 /* NOTE: The order of this array MUST be consistent with 'enum
1932 arc_rlx_types' located in tc-arc.h! */
1933 const struct arc_opcode arc_relax_opcodes[] =
1935 { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } },
1937 /* bl_s s13 11111sssssssssss. */
1938 { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1939 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1940 { SIMM13_A32_5_S }, { 0 }},
1942 /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
1943 { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1944 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1945 { SIMM25_A32_5 }, { C_D }},
1947 /* b_s s10 1111000sssssssss. */
1948 { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1949 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1950 { SIMM10_A16_7_S }, { 0 }},
1952 /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
1953 { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1954 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1955 { SIMM25_A16_5 }, { C_D }},
1957 /* add_s c,b,u3 01101bbbccc00uuu. Wants UIMM3_13_S_PCREL. */
1958 { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1959 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1960 { RC_S, RB_S, UIMM3_13_S }, { 0 }},
1962 /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. Wants
1964 { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1965 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1966 { RA, RB, UIMM6_20 }, { C_F }},
1968 /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
1969 { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1970 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1971 { RA, RB, LIMM }, { C_F }},
1973 /* ld_s c,b,u7 10000bbbcccuuuuu. Wants UIMM7_A32_11_S_PCREL. */
1974 { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1975 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1976 { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
1978 /* ld<.di><.aa><.x><zz> a,b,s9
1979 00010bbbssssssssSBBBDaaZZXAAAAAA. Wants SIMM9_8_PCREL. */
1980 { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1981 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1982 { RA, BRAKET, RB, SIMM9_8, BRAKETdup },
1983 { C_ZZ23, C_DI20, C_AA21, C_X25 }},
1985 /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */
1986 { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1987 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1988 { RA, BRAKET, RB, LIMM, BRAKETdup },
1989 { C_ZZ13, C_DI16, C_AA8, C_X15 }},
1991 /* mov_s b,u8 11011bbbuuuuuuuu. Wants UIMM8_8_S_PCREL. */
1992 { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1993 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1994 { RB_S, UIMM8_8_S }, { 0 }},
1996 /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. Wants
1998 { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1999 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2000 { RB, SIMM12_20 }, { C_F }},
2002 /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
2003 { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2004 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2005 { RB, LIMM }, { C_F }},
2007 /* sub_s c,b,u3 01101bbbccc01uuu. UIMM3_13_S_PCREL. */
2008 { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2009 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2010 { RC_S, RB_S, UIMM3_13_S }, { 0 }},
2012 /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA.
2014 { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2015 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2016 { RA, RB, UIMM6_20 }, { C_F }},
2018 /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
2019 { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2020 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2021 { RA, RB, LIMM }, { C_F }},
2023 /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA.
2025 { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
2026 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }},
2028 /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
2029 { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
2030 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
2032 /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ.
2034 { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2035 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2036 { RB, UIMM6_20 }, { C_F, C_CC }},
2038 /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
2039 { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2040 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2041 { RB, LIMM }, { C_F, C_CC }},
2043 /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ.
2045 { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2046 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2047 { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
2049 /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
2050 { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2051 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2052 { RB, RBdup, LIMM }, { C_F, C_CC }}
2055 const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);