1 /* Opcode table for the ARC.
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software Foundation,
20 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
25 #include "opcode/arc.h"
27 #include "libiberty.h"
29 /* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
30 instructions. Support for this target is available when binutils is
31 configured and built for the 'arc*-mellanox-*-*' target. As far as
32 possible all ARC NPS400 features are built into all ARC target builds as
33 this reduces the chances that regressions might creep in. */
35 /* Insert RB register into a 32-bit opcode. */
37 insert_rb (unsigned insn,
39 const char **errmsg ATTRIBUTE_UNUSED)
41 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
45 extract_rb (unsigned insn ATTRIBUTE_UNUSED,
46 bfd_boolean * invalid ATTRIBUTE_UNUSED)
48 int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
50 if (value == 0x3e && invalid)
51 *invalid = TRUE; /* A limm operand, it should be extracted in a
58 insert_rad (unsigned insn,
60 const char **errmsg ATTRIBUTE_UNUSED)
63 *errmsg = _("Improper register value.");
65 return insn | (value & 0x3F);
69 insert_rcd (unsigned insn,
71 const char **errmsg ATTRIBUTE_UNUSED)
74 *errmsg = _("Improper register value.");
76 return insn | ((value & 0x3F) << 6);
79 /* Dummy insert ZERO operand function. */
82 insert_za (unsigned insn,
87 *errmsg = _("operand is not zero");
91 /* Insert Y-bit in bbit/br instructions. This function is called only
92 when solving fixups. */
95 insert_Ybit (unsigned insn,
97 const char **errmsg ATTRIBUTE_UNUSED)
105 /* Insert Y-bit in bbit/br instructions. This function is called only
106 when solving fixups. */
109 insert_NYbit (unsigned insn,
111 const char **errmsg ATTRIBUTE_UNUSED)
119 /* Insert H register into a 16-bit opcode. */
122 insert_rhv1 (unsigned insn,
124 const char **errmsg ATTRIBUTE_UNUSED)
126 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
130 extract_rhv1 (unsigned insn ATTRIBUTE_UNUSED,
131 bfd_boolean * invalid ATTRIBUTE_UNUSED)
133 int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7);
138 /* Insert H register into a 16-bit opcode. */
141 insert_rhv2 (unsigned insn,
147 _("Register R30 is a limm indicator for this type of instruction.");
148 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
152 extract_rhv2 (unsigned insn ATTRIBUTE_UNUSED,
153 bfd_boolean * invalid ATTRIBUTE_UNUSED)
155 int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
161 insert_r0 (unsigned insn,
163 const char **errmsg ATTRIBUTE_UNUSED)
166 *errmsg = _("Register must be R0.");
171 extract_r0 (unsigned insn ATTRIBUTE_UNUSED,
172 bfd_boolean * invalid ATTRIBUTE_UNUSED)
179 insert_r1 (unsigned insn,
181 const char **errmsg ATTRIBUTE_UNUSED)
184 *errmsg = _("Register must be R1.");
189 extract_r1 (unsigned insn ATTRIBUTE_UNUSED,
190 bfd_boolean * invalid ATTRIBUTE_UNUSED)
196 insert_r2 (unsigned insn,
198 const char **errmsg ATTRIBUTE_UNUSED)
201 *errmsg = _("Register must be R2.");
206 extract_r2 (unsigned insn ATTRIBUTE_UNUSED,
207 bfd_boolean * invalid ATTRIBUTE_UNUSED)
213 insert_r3 (unsigned insn,
215 const char **errmsg ATTRIBUTE_UNUSED)
218 *errmsg = _("Register must be R3.");
223 extract_r3 (unsigned insn ATTRIBUTE_UNUSED,
224 bfd_boolean * invalid ATTRIBUTE_UNUSED)
230 insert_sp (unsigned insn,
232 const char **errmsg ATTRIBUTE_UNUSED)
235 *errmsg = _("Register must be SP.");
240 extract_sp (unsigned insn ATTRIBUTE_UNUSED,
241 bfd_boolean * invalid ATTRIBUTE_UNUSED)
247 insert_gp (unsigned insn,
249 const char **errmsg ATTRIBUTE_UNUSED)
252 *errmsg = _("Register must be GP.");
257 extract_gp (unsigned insn ATTRIBUTE_UNUSED,
258 bfd_boolean * invalid ATTRIBUTE_UNUSED)
264 insert_pcl (unsigned insn,
266 const char **errmsg ATTRIBUTE_UNUSED)
269 *errmsg = _("Register must be PCL.");
274 extract_pcl (unsigned insn ATTRIBUTE_UNUSED,
275 bfd_boolean * invalid ATTRIBUTE_UNUSED)
281 insert_blink (unsigned insn,
283 const char **errmsg ATTRIBUTE_UNUSED)
286 *errmsg = _("Register must be BLINK.");
291 extract_blink (unsigned insn ATTRIBUTE_UNUSED,
292 bfd_boolean * invalid ATTRIBUTE_UNUSED)
298 insert_ilink1 (unsigned insn,
300 const char **errmsg ATTRIBUTE_UNUSED)
303 *errmsg = _("Register must be ILINK1.");
308 extract_ilink1 (unsigned insn ATTRIBUTE_UNUSED,
309 bfd_boolean * invalid ATTRIBUTE_UNUSED)
315 insert_ilink2 (unsigned insn,
317 const char **errmsg ATTRIBUTE_UNUSED)
320 *errmsg = _("Register must be ILINK2.");
325 extract_ilink2 (unsigned insn ATTRIBUTE_UNUSED,
326 bfd_boolean * invalid ATTRIBUTE_UNUSED)
332 insert_ras (unsigned insn,
334 const char **errmsg ATTRIBUTE_UNUSED)
351 *errmsg = _("Register must be either r0-r3 or r12-r15.");
358 extract_ras (unsigned insn ATTRIBUTE_UNUSED,
359 bfd_boolean * invalid ATTRIBUTE_UNUSED)
361 int value = insn & 0x07;
369 insert_rbs (unsigned insn,
371 const char **errmsg ATTRIBUTE_UNUSED)
385 insn |= ((value - 8)) << 8;
388 *errmsg = _("Register must be either r0-r3 or r12-r15.");
395 extract_rbs (unsigned insn ATTRIBUTE_UNUSED,
396 bfd_boolean * invalid ATTRIBUTE_UNUSED)
398 int value = (insn >> 8) & 0x07;
406 insert_rcs (unsigned insn,
408 const char **errmsg ATTRIBUTE_UNUSED)
422 insn |= ((value - 8)) << 5;
425 *errmsg = _("Register must be either r0-r3 or r12-r15.");
432 extract_rcs (unsigned insn ATTRIBUTE_UNUSED,
433 bfd_boolean * invalid ATTRIBUTE_UNUSED)
435 int value = (insn >> 5) & 0x07;
443 insert_simm3s (unsigned insn,
445 const char **errmsg ATTRIBUTE_UNUSED)
475 *errmsg = _("Accepted values are from -1 to 6.");
484 extract_simm3s (unsigned insn ATTRIBUTE_UNUSED,
485 bfd_boolean * invalid ATTRIBUTE_UNUSED)
487 int value = (insn >> 8) & 0x07;
495 insert_rrange (unsigned insn,
497 const char **errmsg ATTRIBUTE_UNUSED)
499 int reg1 = (value >> 16) & 0xFFFF;
500 int reg2 = value & 0xFFFF;
503 *errmsg = _("First register of the range should be r13.");
506 if (reg2 < 13 || reg2 > 26)
508 *errmsg = _("Last register of the range doesn't fit.");
511 insn |= ((reg2 - 12) & 0x0F) << 1;
516 extract_rrange (unsigned insn ATTRIBUTE_UNUSED,
517 bfd_boolean * invalid ATTRIBUTE_UNUSED)
519 return (insn >> 1) & 0x0F;
523 insert_fpel (unsigned insn,
525 const char **errmsg ATTRIBUTE_UNUSED)
529 *errmsg = _("Invalid register number, should be fp.");
538 extract_fpel (unsigned insn ATTRIBUTE_UNUSED,
539 bfd_boolean * invalid ATTRIBUTE_UNUSED)
541 return (insn & 0x0100) ? 27 : -1;
545 insert_blinkel (unsigned insn,
547 const char **errmsg ATTRIBUTE_UNUSED)
551 *errmsg = _("Invalid register number, should be blink.");
560 extract_blinkel (unsigned insn ATTRIBUTE_UNUSED,
561 bfd_boolean * invalid ATTRIBUTE_UNUSED)
563 return (insn & 0x0200) ? 31 : -1;
567 insert_pclel (unsigned insn,
569 const char **errmsg ATTRIBUTE_UNUSED)
573 *errmsg = _("Invalid register number, should be pcl.");
582 extract_pclel (unsigned insn ATTRIBUTE_UNUSED,
583 bfd_boolean * invalid ATTRIBUTE_UNUSED)
585 return (insn & 0x0400) ? 63 : -1;
589 /* mask = 00000000000000000000111111000000
590 insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */
592 insert_w6 (unsigned insn ATTRIBUTE_UNUSED,
593 int value ATTRIBUTE_UNUSED,
594 const char **errmsg ATTRIBUTE_UNUSED)
596 insn |= ((value >> 0) & 0x003f) << 6;
602 /* mask = 00000000000000000000111111000000. */
604 extract_w6 (unsigned insn ATTRIBUTE_UNUSED,
605 bfd_boolean * invalid ATTRIBUTE_UNUSED)
609 value |= ((insn >> 6) & 0x003f) << 0;
615 /* mask = 0000011100022000
616 insn = 01000ggghhhGG0HH. */
618 insert_g_s (unsigned insn ATTRIBUTE_UNUSED,
619 int value ATTRIBUTE_UNUSED,
620 const char **errmsg ATTRIBUTE_UNUSED)
622 insn |= ((value >> 0) & 0x0007) << 8;
623 insn |= ((value >> 3) & 0x0003) << 3;
629 /* mask = 0000011100022000. */
631 extract_g_s (unsigned insn ATTRIBUTE_UNUSED,
632 bfd_boolean * invalid ATTRIBUTE_UNUSED)
636 value |= ((insn >> 8) & 0x0007) << 0;
637 value |= ((insn >> 3) & 0x0003) << 3;
639 /* Extend the sign. */
640 int signbit = 1 << (6 - 1);
641 value = (value ^ signbit) - signbit;
646 /* ARC NPS400 Support: See comment near head of file. */
648 insert_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED,
649 int value ATTRIBUTE_UNUSED,
650 const char **errmsg ATTRIBUTE_UNUSED)
664 insn |= (value - 8) << 24;
667 *errmsg = _("Register must be either r0-r3 or r12-r15.");
674 extract_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED,
675 bfd_boolean * invalid ATTRIBUTE_UNUSED)
677 int value = (insn >> 24) & 0x07;
685 insert_nps_3bit_dst_short (unsigned insn ATTRIBUTE_UNUSED,
686 int value ATTRIBUTE_UNUSED,
687 const char **errmsg ATTRIBUTE_UNUSED)
701 insn |= (value - 8) << 8;
704 *errmsg = _("Register must be either r0-r3 or r12-r15.");
711 extract_nps_3bit_dst_short (unsigned insn ATTRIBUTE_UNUSED,
712 bfd_boolean * invalid ATTRIBUTE_UNUSED)
714 int value = (insn >> 8) & 0x07;
722 insert_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED,
723 int value ATTRIBUTE_UNUSED,
724 const char **errmsg ATTRIBUTE_UNUSED)
738 insn |= (value - 8) << 21;
741 *errmsg = _("Register must be either r0-r3 or r12-r15.");
748 extract_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED,
749 bfd_boolean * invalid ATTRIBUTE_UNUSED)
751 int value = (insn >> 21) & 0x07;
759 insert_nps_3bit_src2_short (unsigned insn ATTRIBUTE_UNUSED,
760 int value ATTRIBUTE_UNUSED,
761 const char **errmsg ATTRIBUTE_UNUSED)
775 insn |= (value - 8) << 5;
778 *errmsg = _("Register must be either r0-r3 or r12-r15.");
785 extract_nps_3bit_src2_short (unsigned insn ATTRIBUTE_UNUSED,
786 bfd_boolean * invalid ATTRIBUTE_UNUSED)
788 int value = (insn >> 5) & 0x07;
796 insert_nps_bitop_size_2b (unsigned insn ATTRIBUTE_UNUSED,
797 int value ATTRIBUTE_UNUSED,
798 const char **errmsg ATTRIBUTE_UNUSED)
816 *errmsg = _("Invalid size, should be 1, 2, 4, or 8.");
825 extract_nps_bitop_size_2b (unsigned insn ATTRIBUTE_UNUSED,
826 bfd_boolean * invalid ATTRIBUTE_UNUSED)
828 return 1 << ((insn >> 10) & 0x3);
832 insert_nps_bitop_uimm8 (unsigned insn ATTRIBUTE_UNUSED,
833 int value ATTRIBUTE_UNUSED,
834 const char **errmsg ATTRIBUTE_UNUSED)
836 insn |= ((value >> 5) & 7) << 12;
837 insn |= (value & 0x1f);
842 extract_nps_bitop_uimm8 (unsigned insn ATTRIBUTE_UNUSED,
843 bfd_boolean * invalid ATTRIBUTE_UNUSED)
845 return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f);
849 insert_nps_rflt_uimm6 (unsigned insn ATTRIBUTE_UNUSED,
850 int value ATTRIBUTE_UNUSED,
851 const char **errmsg ATTRIBUTE_UNUSED)
861 *errmsg = _("invalid immediate, must be 1, 2, or 4");
865 insn |= (value << 6);
870 extract_nps_rflt_uimm6 (unsigned insn ATTRIBUTE_UNUSED,
871 bfd_boolean * invalid ATTRIBUTE_UNUSED)
873 return (insn >> 6) & 0x3f;
877 insert_nps_dst_pos_and_size (unsigned insn ATTRIBUTE_UNUSED,
878 int value ATTRIBUTE_UNUSED,
879 const char **errmsg ATTRIBUTE_UNUSED)
881 insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10));
886 extract_nps_dst_pos_and_size (unsigned insn ATTRIBUTE_UNUSED,
887 bfd_boolean * invalid ATTRIBUTE_UNUSED)
889 return (insn & 0x1f);
893 insert_nps_cmem_uimm16 (unsigned insn ATTRIBUTE_UNUSED,
894 int value ATTRIBUTE_UNUSED,
895 const char **errmsg ATTRIBUTE_UNUSED)
897 int top = (value >> 16) & 0xffff;
898 if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE)
899 *errmsg = _("invalid value for CMEM ld/st immediate");
900 insn |= (value & 0xffff);
905 extract_nps_cmem_uimm16 (unsigned insn ATTRIBUTE_UNUSED,
906 bfd_boolean * invalid ATTRIBUTE_UNUSED)
908 return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff);
911 #define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \
913 insert_nps_##NAME##_pos (unsigned insn ATTRIBUTE_UNUSED, \
914 int value ATTRIBUTE_UNUSED, \
915 const char **errmsg ATTRIBUTE_UNUSED) \
926 *errmsg = _("Invalid position, should be 0, 8, 16, or 24."); \
929 insn |= (value << SHIFT); \
934 extract_nps_##NAME##_pos (unsigned insn ATTRIBUTE_UNUSED, \
935 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
937 return ((insn >> SHIFT) & 0x3) * 8; \
940 MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12)
941 MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10)
943 #define MAKE_BIAS_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT)\
945 insert_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED, \
946 int value ATTRIBUTE_UNUSED, \
947 const char **errmsg ATTRIBUTE_UNUSED) \
949 if (value < LOWER || value > UPPER) \
951 *errmsg = _("Invalid size, value must be " \
952 #LOWER " to " #UPPER "."); \
956 insn |= (value << SHIFT); \
961 extract_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED, \
962 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
964 return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \
967 MAKE_BIAS_INSERT_EXTRACT_FUNCS(addb_size,2,32,5,1,5)
968 MAKE_BIAS_INSERT_EXTRACT_FUNCS(andb_size,1,32,5,1,5)
969 MAKE_BIAS_INSERT_EXTRACT_FUNCS(fxorb_size,8,32,5,8,5)
970 MAKE_BIAS_INSERT_EXTRACT_FUNCS(wxorb_size,16,32,5,16,5)
971 MAKE_BIAS_INSERT_EXTRACT_FUNCS(bitop_size,1,32,5,1,10)
972 MAKE_BIAS_INSERT_EXTRACT_FUNCS(qcmp_size,1,8,3,1,9)
973 MAKE_BIAS_INSERT_EXTRACT_FUNCS(bitop1_size,1,32,5,1,20)
974 MAKE_BIAS_INSERT_EXTRACT_FUNCS(bitop2_size,1,32,5,1,25)
975 MAKE_BIAS_INSERT_EXTRACT_FUNCS(hash_width,1,32,5,1,6)
976 MAKE_BIAS_INSERT_EXTRACT_FUNCS(hash_len,1,8,3,1,2)
977 MAKE_BIAS_INSERT_EXTRACT_FUNCS(index3,4,7,2,4,0)
980 extract_nps_qcmp_m3 (unsigned insn ATTRIBUTE_UNUSED,
981 bfd_boolean * invalid ATTRIBUTE_UNUSED)
983 int m3 = (insn >> 5) & 0xf;
990 extract_nps_qcmp_m2 (unsigned insn ATTRIBUTE_UNUSED,
991 bfd_boolean * invalid ATTRIBUTE_UNUSED)
993 bfd_boolean tmp_invalid = FALSE;
994 int m2 = (insn >> 15) & 0x1;
995 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
997 if (m2 == 0 && m3 == 0xf)
1003 extract_nps_qcmp_m1 (unsigned insn ATTRIBUTE_UNUSED,
1004 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1006 bfd_boolean tmp_invalid = FALSE;
1007 int m1 = (insn >> 14) & 0x1;
1008 int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid);
1009 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
1011 if (m1 == 0 && m2 == 0 && m3 == 0xf)
1017 insert_nps_calc_entry_size (unsigned insn ATTRIBUTE_UNUSED,
1018 int value ATTRIBUTE_UNUSED,
1019 const char **errmsg ATTRIBUTE_UNUSED)
1023 if (value < 1 || value > 256)
1025 *errmsg = _("value out of range 1 - 256");
1029 for (pwr = 0; (value & 1) == 0; value >>= 1)
1034 *errmsg = _("value must be power of 2");
1038 return insn | (pwr << 8);
1042 extract_nps_calc_entry_size (unsigned insn ATTRIBUTE_UNUSED,
1043 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1045 unsigned entry_size = (insn >> 8) & 0xf;
1046 return 1 << entry_size;
1050 insert_nps_bitop_mod4_msb (unsigned insn ATTRIBUTE_UNUSED,
1051 int value ATTRIBUTE_UNUSED,
1052 const char **errmsg ATTRIBUTE_UNUSED)
1054 return insn | ((value & 0x2) << 30);
1058 extract_nps_bitop_mod4_msb (unsigned insn ATTRIBUTE_UNUSED,
1059 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1061 return (insn >> 30) & 0x2;
1065 insert_nps_bitop_mod4_lsb (unsigned insn ATTRIBUTE_UNUSED,
1066 int value ATTRIBUTE_UNUSED,
1067 const char **errmsg ATTRIBUTE_UNUSED)
1069 return insn | ((value & 0x1) << 15);
1073 extract_nps_bitop_mod4_lsb (unsigned insn ATTRIBUTE_UNUSED,
1074 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1076 return (insn >> 15) & 0x1;
1080 insert_nps_bitop_dst_pos3_pos4 (unsigned insn ATTRIBUTE_UNUSED,
1081 int value ATTRIBUTE_UNUSED,
1082 const char **errmsg ATTRIBUTE_UNUSED)
1084 return insn | (value << 10) | (value << 5);
1088 extract_nps_bitop_dst_pos3_pos4 (unsigned insn ATTRIBUTE_UNUSED,
1089 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1091 if (((insn >> 10) & 0x1f) != ((insn >> 5) & 0x1f))
1093 return ((insn >> 5) & 0x1f);
1097 insert_nps_bitop_ins_ext (unsigned insn ATTRIBUTE_UNUSED,
1098 int value ATTRIBUTE_UNUSED,
1099 const char **errmsg ATTRIBUTE_UNUSED)
1101 if (value < 0 || value > 28)
1102 *errmsg = _("Value must be in the range 0 to 28");
1103 return insn | (value << 20);
1107 extract_nps_bitop_ins_ext (unsigned insn ATTRIBUTE_UNUSED,
1108 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1110 int value = (insn >> 20) & 0x1f;
1116 #define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS) \
1118 insert_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED, \
1119 int value ATTRIBUTE_UNUSED, \
1120 const char **errmsg ATTRIBUTE_UNUSED) \
1122 if (value < 1 || value > UPPER) \
1123 *errmsg = _("Value must be in the range 1 to " #UPPER); \
1124 if (value == UPPER) \
1126 return insn | (value << SHIFT); \
1130 extract_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED, \
1131 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
1133 int value = (insn >> SHIFT) & ((1 << BITS) - 1); \
1139 MAKE_1BASED_INSERT_EXTRACT_FUNCS(field_size, 6, 8, 3)
1140 MAKE_1BASED_INSERT_EXTRACT_FUNCS(shift_factor, 9, 8, 3)
1141 MAKE_1BASED_INSERT_EXTRACT_FUNCS(bits_to_scramble, 12, 8, 3)
1142 MAKE_1BASED_INSERT_EXTRACT_FUNCS(bdlen_max_len, 5, 256, 8)
1145 insert_nps_min_hofs (unsigned insn ATTRIBUTE_UNUSED,
1146 int value ATTRIBUTE_UNUSED,
1147 const char **errmsg ATTRIBUTE_UNUSED)
1149 if (value < 0 || value > 240)
1150 *errmsg = _("Value must be in the range 0 to 240");
1151 if ((value % 16) != 0)
1152 *errmsg = _("Value must be a multiple of 16");
1154 return insn | (value << 6);
1158 extract_nps_min_hofs (unsigned insn ATTRIBUTE_UNUSED,
1159 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1161 int value = (insn >> 6) & 0xF;
1165 /* Include the generic extract/insert functions. Order is important
1166 as some of the functions present in the .h may be disabled via
1168 #include "arc-fxi.h"
1170 /* The flag operands table.
1172 The format of the table is
1173 NAME CODE BITS SHIFT FAVAIL. */
1174 const struct arc_flag_operand arc_flag_operands[] =
1178 #define F_ALWAYS (F_NULL + 1)
1179 { "al", 0, 0, 0, 0 },
1180 #define F_RA (F_ALWAYS + 1)
1181 { "ra", 0, 0, 0, 0 },
1182 #define F_EQUAL (F_RA + 1)
1183 { "eq", 1, 5, 0, 1 },
1184 #define F_ZERO (F_EQUAL + 1)
1185 { "z", 1, 5, 0, 0 },
1186 #define F_NOTEQUAL (F_ZERO + 1)
1187 { "ne", 2, 5, 0, 1 },
1188 #define F_NOTZERO (F_NOTEQUAL + 1)
1189 { "nz", 2, 5, 0, 0 },
1190 #define F_POZITIVE (F_NOTZERO + 1)
1191 { "p", 3, 5, 0, 1 },
1192 #define F_PL (F_POZITIVE + 1)
1193 { "pl", 3, 5, 0, 0 },
1194 #define F_NEGATIVE (F_PL + 1)
1195 { "n", 4, 5, 0, 1 },
1196 #define F_MINUS (F_NEGATIVE + 1)
1197 { "mi", 4, 5, 0, 0 },
1198 #define F_CARRY (F_MINUS + 1)
1199 { "c", 5, 5, 0, 1 },
1200 #define F_CARRYSET (F_CARRY + 1)
1201 { "cs", 5, 5, 0, 0 },
1202 #define F_LOWER (F_CARRYSET + 1)
1203 { "lo", 5, 5, 0, 0 },
1204 #define F_CARRYCLR (F_LOWER + 1)
1205 { "cc", 6, 5, 0, 0 },
1206 #define F_NOTCARRY (F_CARRYCLR + 1)
1207 { "nc", 6, 5, 0, 1 },
1208 #define F_HIGHER (F_NOTCARRY + 1)
1209 { "hs", 6, 5, 0, 0 },
1210 #define F_OVERFLOWSET (F_HIGHER + 1)
1211 { "vs", 7, 5, 0, 0 },
1212 #define F_OVERFLOW (F_OVERFLOWSET + 1)
1213 { "v", 7, 5, 0, 1 },
1214 #define F_NOTOVERFLOW (F_OVERFLOW + 1)
1215 { "nv", 8, 5, 0, 1 },
1216 #define F_OVERFLOWCLR (F_NOTOVERFLOW + 1)
1217 { "vc", 8, 5, 0, 0 },
1218 #define F_GT (F_OVERFLOWCLR + 1)
1219 { "gt", 9, 5, 0, 1 },
1220 #define F_GE (F_GT + 1)
1221 { "ge", 10, 5, 0, 1 },
1222 #define F_LT (F_GE + 1)
1223 { "lt", 11, 5, 0, 1 },
1224 #define F_LE (F_LT + 1)
1225 { "le", 12, 5, 0, 1 },
1226 #define F_HI (F_LE + 1)
1227 { "hi", 13, 5, 0, 1 },
1228 #define F_LS (F_HI + 1)
1229 { "ls", 14, 5, 0, 1 },
1230 #define F_PNZ (F_LS + 1)
1231 { "pnz", 15, 5, 0, 1 },
1234 #define F_FLAG (F_PNZ + 1)
1235 { "f", 1, 1, 15, 1 },
1236 #define F_FFAKE (F_FLAG + 1)
1237 { "f", 0, 0, 0, 1 },
1240 #define F_ND (F_FFAKE + 1)
1241 { "nd", 0, 1, 5, 0 },
1242 #define F_D (F_ND + 1)
1243 { "d", 1, 1, 5, 1 },
1244 #define F_DFAKE (F_D + 1)
1245 { "d", 0, 0, 0, 1 },
1248 #define F_SIZEB1 (F_DFAKE + 1)
1249 { "b", 1, 2, 1, 1 },
1250 #define F_SIZEB7 (F_SIZEB1 + 1)
1251 { "b", 1, 2, 7, 1 },
1252 #define F_SIZEB17 (F_SIZEB7 + 1)
1253 { "b", 1, 2, 17, 1 },
1254 #define F_SIZEW1 (F_SIZEB17 + 1)
1255 { "w", 2, 2, 1, 0 },
1256 #define F_SIZEW7 (F_SIZEW1 + 1)
1257 { "w", 2, 2, 7, 0 },
1258 #define F_SIZEW17 (F_SIZEW7 + 1)
1259 { "w", 2, 2, 17, 0 },
1261 /* Sign extension. */
1262 #define F_SIGN6 (F_SIZEW17 + 1)
1263 { "x", 1, 1, 6, 1 },
1264 #define F_SIGN16 (F_SIGN6 + 1)
1265 { "x", 1, 1, 16, 1 },
1266 #define F_SIGNX (F_SIGN16 + 1)
1267 { "x", 0, 0, 0, 1 },
1269 /* Address write-back modes. */
1270 #define F_A3 (F_SIGNX + 1)
1271 { "a", 1, 2, 3, 0 },
1272 #define F_A9 (F_A3 + 1)
1273 { "a", 1, 2, 9, 0 },
1274 #define F_A22 (F_A9 + 1)
1275 { "a", 1, 2, 22, 0 },
1276 #define F_AW3 (F_A22 + 1)
1277 { "aw", 1, 2, 3, 1 },
1278 #define F_AW9 (F_AW3 + 1)
1279 { "aw", 1, 2, 9, 1 },
1280 #define F_AW22 (F_AW9 + 1)
1281 { "aw", 1, 2, 22, 1 },
1282 #define F_AB3 (F_AW22 + 1)
1283 { "ab", 2, 2, 3, 1 },
1284 #define F_AB9 (F_AB3 + 1)
1285 { "ab", 2, 2, 9, 1 },
1286 #define F_AB22 (F_AB9 + 1)
1287 { "ab", 2, 2, 22, 1 },
1288 #define F_AS3 (F_AB22 + 1)
1289 { "as", 3, 2, 3, 1 },
1290 #define F_AS9 (F_AS3 + 1)
1291 { "as", 3, 2, 9, 1 },
1292 #define F_AS22 (F_AS9 + 1)
1293 { "as", 3, 2, 22, 1 },
1294 #define F_ASFAKE (F_AS22 + 1)
1295 { "as", 0, 0, 0, 1 },
1298 #define F_DI5 (F_ASFAKE + 1)
1299 { "di", 1, 1, 5, 1 },
1300 #define F_DI11 (F_DI5 + 1)
1301 { "di", 1, 1, 11, 1 },
1302 #define F_DI15 (F_DI11 + 1)
1303 { "di", 1, 1, 15, 1 },
1305 /* ARCv2 specific. */
1306 #define F_NT (F_DI15 + 1)
1307 { "nt", 0, 1, 3, 1},
1308 #define F_T (F_NT + 1)
1310 #define F_H1 (F_T + 1)
1311 { "h", 2, 2, 1, 1 },
1312 #define F_H7 (F_H1 + 1)
1313 { "h", 2, 2, 7, 1 },
1314 #define F_H17 (F_H7 + 1)
1315 { "h", 2, 2, 17, 1 },
1318 #define F_NE (F_H17 + 1)
1319 { "ne", 0, 0, 0, 1 },
1321 /* ARC NPS400 Support: See comment near head of file. */
1322 #define F_NPS_CL (F_NE + 1)
1323 { "cl", 0, 0, 0, 1 },
1325 #define F_NPS_FLAG (F_NPS_CL + 1)
1326 { "f", 1, 1, 20, 1 },
1328 #define F_NPS_R (F_NPS_FLAG + 1)
1329 { "r", 1, 1, 15, 1 },
1331 #define F_NPS_RW (F_NPS_R + 1)
1332 { "rw", 0, 1, 7, 1 },
1334 #define F_NPS_RD (F_NPS_RW + 1)
1335 { "rd", 1, 1, 7, 1 },
1337 #define F_NPS_WFT (F_NPS_RD + 1)
1338 { "wft", 0, 0, 0, 1 },
1340 #define F_NPS_IE1 (F_NPS_WFT + 1)
1341 { "ie1", 1, 2, 8, 1 },
1343 #define F_NPS_IE2 (F_NPS_IE1 + 1)
1344 { "ie2", 2, 2, 8, 1 },
1346 #define F_NPS_IE12 (F_NPS_IE2 + 1)
1347 { "ie12", 3, 2, 8, 1 },
1349 #define F_NPS_SYNC_RD (F_NPS_IE12 + 1)
1350 { "rd", 0, 1, 6, 1 },
1352 #define F_NPS_SYNC_WR (F_NPS_SYNC_RD + 1)
1353 { "wr", 1, 1, 6, 1 },
1355 #define F_NPS_HWS_OFF (F_NPS_SYNC_WR + 1)
1356 { "off", 0, 0, 0, 1 },
1358 #define F_NPS_HWS_RESTORE (F_NPS_HWS_OFF + 1)
1359 { "restore", 0, 0, 0, 1 },
1361 #define F_NPS_SX (F_NPS_HWS_RESTORE + 1)
1362 { "sx", 1, 1, 14, 1 },
1364 #define F_NPS_AR (F_NPS_SX + 1)
1365 { "ar", 0, 1, 0, 1 },
1367 #define F_NPS_AL (F_NPS_AR + 1)
1368 { "al", 1, 1, 0, 1 },
1370 #define F_NPS_S (F_NPS_AL + 1)
1371 { "s", 0, 0, 0, 1 },
1373 #define F_NPS_ZNCV_RD (F_NPS_S + 1)
1374 { "rd", 0, 1, 15, 1 },
1376 #define F_NPS_ZNCV_WR (F_NPS_ZNCV_RD + 1)
1377 { "wr", 1, 1, 15, 1 },
1379 #define F_NPS_P0 (F_NPS_ZNCV_WR + 1)
1380 { "p0", 0, 0, 0, 1 },
1382 #define F_NPS_P1 (F_NPS_P0 + 1)
1383 { "p1", 0, 0, 0, 1 },
1385 #define F_NPS_P2 (F_NPS_P1 + 1)
1386 { "p2", 0, 0, 0, 1 },
1388 #define F_NPS_P3 (F_NPS_P2 + 1)
1389 { "p3", 0, 0, 0, 1 },
1391 #define F_NPS_LDBIT_DI (F_NPS_P3 + 1)
1392 { "di", 0, 0, 0, 1 },
1394 #define F_NPS_LDBIT_CL1 (F_NPS_LDBIT_DI + 1)
1395 { "cl", 1, 1, 6, 1 },
1397 #define F_NPS_LDBIT_CL2 (F_NPS_LDBIT_CL1 + 1)
1398 { "cl", 1, 1, 16, 1 },
1400 #define F_NPS_LDBIT_X2_1 (F_NPS_LDBIT_CL2 + 1)
1401 { "x2", 1, 2, 9, 1 },
1403 #define F_NPS_LDBIT_X2_2 (F_NPS_LDBIT_X2_1 + 1)
1404 { "x2", 1, 2, 22, 1 },
1406 #define F_NPS_LDBIT_X4_1 (F_NPS_LDBIT_X2_2 + 1)
1407 { "x4", 2, 2, 9, 1 },
1409 #define F_NPS_LDBIT_X4_2 (F_NPS_LDBIT_X4_1 + 1)
1410 { "x4", 2, 2, 22, 1 },
1413 const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
1415 /* Table of the flag classes.
1417 The format of the table is
1418 CLASS {FLAG_CODE}. */
1419 const struct arc_flag_class arc_flag_classes[] =
1422 { F_CLASS_NONE, { F_NULL } },
1424 #define C_CC (C_EMPTY + 1)
1425 { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND,
1426 { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
1427 F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
1428 F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1429 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
1430 F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
1431 F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1433 #define C_AA_ADDR3 (C_CC + 1)
1434 #define C_AA27 (C_CC + 1)
1435 { F_CLASS_OPTIONAL, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
1436 #define C_AA_ADDR9 (C_AA_ADDR3 + 1)
1437 #define C_AA21 (C_AA_ADDR3 + 1)
1438 { F_CLASS_OPTIONAL, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
1439 #define C_AA_ADDR22 (C_AA_ADDR9 + 1)
1440 #define C_AA8 (C_AA_ADDR9 + 1)
1441 { F_CLASS_OPTIONAL, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
1443 #define C_F (C_AA_ADDR22 + 1)
1444 { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },
1445 #define C_FHARD (C_F + 1)
1446 { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } },
1448 #define C_T (C_FHARD + 1)
1449 { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
1450 #define C_D (C_T + 1)
1451 { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
1453 #define C_DHARD (C_D + 1)
1454 { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
1456 #define C_DI20 (C_DHARD + 1)
1457 { F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
1458 #define C_DI16 (C_DI20 + 1)
1459 { F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
1460 #define C_DI26 (C_DI16 + 1)
1461 { F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
1463 #define C_X25 (C_DI26 + 1)
1464 { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }},
1465 #define C_X15 (C_X25 + 1)
1466 { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }},
1467 #define C_XHARD (C_X15 + 1)
1468 #define C_X (C_X15 + 1)
1469 { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }},
1471 #define C_ZZ13 (C_X + 1)
1472 { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
1473 #define C_ZZ23 (C_ZZ13 + 1)
1474 { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
1475 #define C_ZZ29 (C_ZZ23 + 1)
1476 { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
1478 #define C_AS (C_ZZ29 + 1)
1479 { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
1481 #define C_NE (C_AS + 1)
1482 { F_CLASS_OPTIONAL, { F_NE, F_NULL}},
1484 /* ARC NPS400 Support: See comment near head of file. */
1485 #define C_NPS_CL (C_NE + 1)
1486 { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}},
1488 #define C_NPS_F (C_NPS_CL + 1)
1489 { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
1491 #define C_NPS_R (C_NPS_F + 1)
1492 { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}},
1494 #define C_NPS_SCHD_RW (C_NPS_R + 1)
1495 { F_CLASS_REQUIRED, { F_NPS_RW, F_NPS_RD, F_NULL}},
1497 #define C_NPS_SCHD_TRIG (C_NPS_SCHD_RW + 1)
1498 { F_CLASS_REQUIRED, { F_NPS_WFT, F_NULL}},
1500 #define C_NPS_SCHD_IE (C_NPS_SCHD_TRIG + 1)
1501 { F_CLASS_OPTIONAL, { F_NPS_IE1, F_NPS_IE2, F_NPS_IE12, F_NULL}},
1503 #define C_NPS_SYNC (C_NPS_SCHD_IE + 1)
1504 { F_CLASS_REQUIRED, { F_NPS_SYNC_RD, F_NPS_SYNC_WR, F_NULL}},
1506 #define C_NPS_HWS_OFF (C_NPS_SYNC + 1)
1507 { F_CLASS_REQUIRED, { F_NPS_HWS_OFF, F_NULL}},
1509 #define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1)
1510 { F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}},
1512 #define C_NPS_SX (C_NPS_HWS_RESTORE + 1)
1513 { F_CLASS_OPTIONAL, { F_NPS_SX, F_NULL}},
1515 #define C_NPS_AR_AL (C_NPS_SX + 1)
1516 { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}},
1518 #define C_NPS_S (C_NPS_AR_AL + 1)
1519 { F_CLASS_REQUIRED, { F_NPS_S, F_NULL}},
1521 #define C_NPS_ZNCV (C_NPS_S + 1)
1522 { F_CLASS_REQUIRED, { F_NPS_ZNCV_RD, F_NPS_ZNCV_WR, F_NULL}},
1524 #define C_NPS_P0 (C_NPS_ZNCV + 1)
1525 { F_CLASS_REQUIRED, { F_NPS_P0, F_NULL }},
1527 #define C_NPS_P1 (C_NPS_P0 + 1)
1528 { F_CLASS_REQUIRED, { F_NPS_P1, F_NULL }},
1530 #define C_NPS_P2 (C_NPS_P1 + 1)
1531 { F_CLASS_REQUIRED, { F_NPS_P2, F_NULL }},
1533 #define C_NPS_P3 (C_NPS_P2 + 1)
1534 { F_CLASS_REQUIRED, { F_NPS_P3, F_NULL }},
1536 #define C_NPS_LDBIT_DI (C_NPS_P3 + 1)
1537 { F_CLASS_REQUIRED, { F_NPS_LDBIT_DI, F_NULL }},
1539 #define C_NPS_LDBIT_CL1 (C_NPS_LDBIT_DI + 1)
1540 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL1, F_NULL }},
1542 #define C_NPS_LDBIT_CL2 (C_NPS_LDBIT_CL1 + 1)
1543 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL2, F_NULL }},
1545 #define C_NPS_LDBIT_X_1 (C_NPS_LDBIT_CL2 + 1)
1546 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1, F_NULL }},
1548 #define C_NPS_LDBIT_X_2 (C_NPS_LDBIT_X_1 + 1)
1549 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2, F_NULL }},
1552 const unsigned char flags_none[] = { 0 };
1553 const unsigned char flags_f[] = { C_F };
1554 const unsigned char flags_cc[] = { C_CC };
1555 const unsigned char flags_ccf[] = { C_CC, C_F };
1557 /* The operands table.
1559 The format of the operands table is:
1561 BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */
1562 const struct arc_operand arc_operands[] =
1564 /* The fields are bits, shift, insert, extract, flags. The zero
1565 index is used to indicate end-of-list. */
1567 { 0, 0, 0, 0, 0, 0 },
1569 #define IGNORED (UNUSED + 1)
1570 { 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0 },
1572 /* The plain integer register fields. Used by 32 bit
1574 #define RA (IGNORED + 1)
1575 { 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
1577 { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
1579 { 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
1580 #define RBdup (RC + 1)
1581 { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
1583 #define RAD (RBdup + 1)
1584 { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
1585 #define RCD (RAD + 1)
1586 { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
1588 /* The plain integer register fields. Used by short
1590 #define RA16 (RCD + 1)
1591 #define RA_S (RCD + 1)
1592 { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
1593 #define RB16 (RA16 + 1)
1594 #define RB_S (RA16 + 1)
1595 { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs },
1596 #define RB16dup (RB16 + 1)
1597 #define RB_Sdup (RB16 + 1)
1598 { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs },
1599 #define RC16 (RB16dup + 1)
1600 #define RC_S (RB16dup + 1)
1601 { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs },
1602 #define R6H (RC16 + 1) /* 6bit register field 'h' used
1604 { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 },
1605 #define R5H (R6H + 1) /* 5bit register field 'h' used
1607 #define RH_S (R6H + 1) /* 5bit register field 'h' used
1609 { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 },
1610 #define R5Hdup (R5H + 1)
1611 #define RH_Sdup (R5H + 1)
1612 { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE,
1613 insert_rhv2, extract_rhv2 },
1615 #define RG (R5Hdup + 1)
1616 #define G_S (R5Hdup + 1)
1617 { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s },
1619 /* Fix registers. */
1621 #define R0_S (RG + 1)
1622 { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 },
1624 #define R1_S (R0 + 1)
1625 { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 },
1627 #define R2_S (R1 + 1)
1628 { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 },
1630 #define R3_S (R2 + 1)
1631 { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 },
1632 #define RSP (R3 + 1)
1633 #define SP_S (R3 + 1)
1634 { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp },
1635 #define SPdup (RSP + 1)
1636 #define SP_Sdup (RSP + 1)
1637 { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp },
1638 #define GP (SPdup + 1)
1639 #define GP_S (SPdup + 1)
1640 { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp },
1642 #define PCL_S (GP + 1)
1643 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl },
1645 #define BLINK (PCL_S + 1)
1646 #define BLINK_S (PCL_S + 1)
1647 { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink },
1649 #define ILINK1 (BLINK + 1)
1650 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 },
1651 #define ILINK2 (ILINK1 + 1)
1652 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 },
1654 /* Long immediate. */
1655 #define LIMM (ILINK2 + 1)
1656 #define LIMM_S (ILINK2 + 1)
1657 { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
1658 #define LIMMdup (LIMM + 1)
1659 { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 },
1661 /* Special operands. */
1662 #define ZA (LIMMdup + 1)
1663 #define ZB (LIMMdup + 1)
1664 #define ZA_S (LIMMdup + 1)
1665 #define ZB_S (LIMMdup + 1)
1666 #define ZC_S (LIMMdup + 1)
1667 { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 },
1669 #define RRANGE_EL (ZA + 1)
1670 { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
1671 insert_rrange, extract_rrange},
1672 #define FP_EL (RRANGE_EL + 1)
1673 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1674 insert_fpel, extract_fpel },
1675 #define BLINK_EL (FP_EL + 1)
1676 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1677 insert_blinkel, extract_blinkel },
1678 #define PCL_EL (BLINK_EL + 1)
1679 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1680 insert_pclel, extract_pclel },
1682 /* Fake operand to handle the T flag. */
1683 #define BRAKET (PCL_EL + 1)
1684 #define BRAKETdup (PCL_EL + 1)
1685 { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 },
1687 /* Fake operand to handle the T flag. */
1688 #define FKT_T (BRAKET + 1)
1689 { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 },
1690 /* Fake operand to handle the T flag. */
1691 #define FKT_NT (FKT_T + 1)
1692 { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 },
1694 /* UIMM6_20 mask = 00000000000000000000111111000000. */
1695 #define UIMM6_20 (FKT_NT + 1)
1696 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
1698 /* SIMM12_20 mask = 00000000000000000000111111222222. */
1699 #define SIMM12_20 (UIMM6_20 + 1)
1700 {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
1702 /* SIMM3_5_S mask = 0000011100000000. */
1703 #define SIMM3_5_S (SIMM12_20 + 1)
1704 {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
1705 insert_simm3s, extract_simm3s},
1707 /* UIMM7_A32_11_S mask = 0000000000011111. */
1708 #define UIMM7_A32_11_S (SIMM3_5_S + 1)
1709 {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1710 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
1711 extract_uimm7_a32_11_s},
1713 /* UIMM7_9_S mask = 0000000001111111. */
1714 #define UIMM7_9_S (UIMM7_A32_11_S + 1)
1715 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
1717 /* UIMM3_13_S mask = 0000000000000111. */
1718 #define UIMM3_13_S (UIMM7_9_S + 1)
1719 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
1721 /* SIMM11_A32_7_S mask = 0000000111111111. */
1722 #define SIMM11_A32_7_S (UIMM3_13_S + 1)
1723 {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1724 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
1726 /* UIMM6_13_S mask = 0000000002220111. */
1727 #define UIMM6_13_S (SIMM11_A32_7_S + 1)
1728 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s},
1729 /* UIMM5_11_S mask = 0000000000011111. */
1730 #define UIMM5_11_S (UIMM6_13_S + 1)
1731 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s,
1732 extract_uimm5_11_s},
1734 /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
1735 #define SIMM9_A16_8 (UIMM5_11_S + 1)
1736 {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1737 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8,
1738 extract_simm9_a16_8},
1740 /* UIMM6_8 mask = 00000000000000000000111111000000. */
1741 #define UIMM6_8 (SIMM9_A16_8 + 1)
1742 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8},
1744 /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
1745 #define SIMM21_A16_5 (UIMM6_8 + 1)
1746 {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
1747 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE,
1748 insert_simm21_a16_5, extract_simm21_a16_5},
1750 /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
1751 #define SIMM25_A16_5 (SIMM21_A16_5 + 1)
1752 {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED
1753 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
1754 insert_simm25_a16_5, extract_simm25_a16_5},
1756 /* SIMM10_A16_7_S mask = 0000000111111111. */
1757 #define SIMM10_A16_7_S (SIMM25_A16_5 + 1)
1758 {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1759 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s,
1760 extract_simm10_a16_7_s},
1762 #define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1)
1763 {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1764 | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s},
1766 /* SIMM7_A16_10_S mask = 0000000000111111. */
1767 #define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1)
1768 {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1769 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s,
1770 extract_simm7_a16_10_s},
1772 /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */
1773 #define SIMM21_A32_5 (SIMM7_A16_10_S + 1)
1774 {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1775 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5,
1776 extract_simm21_a32_5},
1778 /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */
1779 #define SIMM25_A32_5 (SIMM21_A32_5 + 1)
1780 {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1781 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5,
1782 extract_simm25_a32_5},
1784 /* SIMM13_A32_5_S mask = 0000011111111111. */
1785 #define SIMM13_A32_5_S (SIMM25_A32_5 + 1)
1786 {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1787 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s,
1788 extract_simm13_a32_5_s},
1790 /* SIMM8_A16_9_S mask = 0000000001111111. */
1791 #define SIMM8_A16_9_S (SIMM13_A32_5_S + 1)
1792 {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1793 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
1794 extract_simm8_a16_9_s},
1796 /* UIMM3_23 mask = 00000000000000000000000111000000. */
1797 #define UIMM3_23 (SIMM8_A16_9_S + 1)
1798 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23},
1800 /* UIMM10_6_S mask = 0000001111111111. */
1801 #define UIMM10_6_S (UIMM3_23 + 1)
1802 {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s},
1804 /* UIMM6_11_S mask = 0000002200011110. */
1805 #define UIMM6_11_S (UIMM10_6_S + 1)
1806 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s},
1808 /* SIMM9_8 mask = 00000000111111112000000000000000. */
1809 #define SIMM9_8 (UIMM6_11_S + 1)
1810 {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
1811 insert_simm9_8, extract_simm9_8},
1813 /* UIMM10_A32_8_S mask = 0000000011111111. */
1814 #define UIMM10_A32_8_S (SIMM9_8 + 1)
1815 {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1816 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
1817 extract_uimm10_a32_8_s},
1819 /* SIMM9_7_S mask = 0000000111111111. */
1820 #define SIMM9_7_S (UIMM10_A32_8_S + 1)
1821 {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s,
1824 /* UIMM6_A16_11_S mask = 0000000000011111. */
1825 #define UIMM6_A16_11_S (SIMM9_7_S + 1)
1826 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1827 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s,
1828 extract_uimm6_a16_11_s},
1830 /* UIMM5_A32_11_S mask = 0000020000011000. */
1831 #define UIMM5_A32_11_S (UIMM6_A16_11_S + 1)
1832 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1833 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s,
1834 extract_uimm5_a32_11_s},
1836 /* SIMM11_A32_13_S mask = 0000022222200111. */
1837 #define SIMM11_A32_13_S (UIMM5_A32_11_S + 1)
1838 {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1839 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s},
1841 /* UIMM7_13_S mask = 0000000022220111. */
1842 #define UIMM7_13_S (SIMM11_A32_13_S + 1)
1843 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s},
1845 /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */
1846 #define UIMM6_A16_21 (UIMM7_13_S + 1)
1847 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1848 | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21},
1850 /* UIMM7_11_S mask = 0000022200011110. */
1851 #define UIMM7_11_S (UIMM6_A16_21 + 1)
1852 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s},
1854 /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */
1855 #define UIMM7_A16_20 (UIMM7_11_S + 1)
1856 {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1857 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20,
1858 extract_uimm7_a16_20},
1860 /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
1861 #define SIMM13_A16_20 (UIMM7_A16_20 + 1)
1862 {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1863 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20,
1864 extract_simm13_a16_20},
1866 /* UIMM8_8_S mask = 0000000011111111. */
1867 #define UIMM8_8_S (SIMM13_A16_20 + 1)
1868 {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
1870 /* W6 mask = 00000000000000000000111111000000. */
1871 #define W6 (UIMM8_8_S + 1)
1872 {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
1874 /* UIMM6_5_S mask = 0000011111100000. */
1875 #define UIMM6_5_S (W6 + 1)
1876 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
1878 /* ARC NPS400 Support: See comment near head of file. */
1879 #define NPS_R_DST_3B (UIMM6_5_S + 1)
1880 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
1882 #define NPS_R_SRC1_3B (NPS_R_DST_3B + 1)
1883 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
1885 #define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1)
1886 { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_src2, extract_nps_3bit_src2 },
1888 #define NPS_R_DST (NPS_R_SRC2_3B + 1)
1889 { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL },
1891 #define NPS_R_SRC1 (NPS_R_DST + 1)
1892 { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
1894 #define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1)
1895 { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
1897 #define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
1898 { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
1900 #define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
1901 { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size, extract_nps_bitop_size },
1903 #define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1)
1904 { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size },
1906 #define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1)
1907 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size_2b, extract_nps_bitop_size_2b },
1909 #define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1)
1910 { 8, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 },
1912 #define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1)
1913 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1915 #define NPS_SIMM16 (NPS_UIMM16 + 1)
1916 { 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL },
1918 #define NPS_RFLT_UIMM6 (NPS_SIMM16 + 1)
1919 { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 },
1921 #define NPS_XLDST_UIMM16 (NPS_RFLT_UIMM6 + 1)
1922 { 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_cmem_uimm16, extract_nps_cmem_uimm16 },
1924 #define NPS_SRC2_POS (NPS_XLDST_UIMM16 + 1)
1925 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src2_pos, extract_nps_src2_pos },
1927 #define NPS_SRC1_POS (NPS_SRC2_POS + 1)
1928 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src1_pos, extract_nps_src1_pos },
1930 #define NPS_ADDB_SIZE (NPS_SRC1_POS + 1)
1931 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_addb_size, extract_nps_addb_size },
1933 #define NPS_ANDB_SIZE (NPS_ADDB_SIZE + 1)
1934 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_andb_size, extract_nps_andb_size },
1936 #define NPS_FXORB_SIZE (NPS_ANDB_SIZE + 1)
1937 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_fxorb_size, extract_nps_fxorb_size },
1939 #define NPS_WXORB_SIZE (NPS_FXORB_SIZE + 1)
1940 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_wxorb_size, extract_nps_wxorb_size },
1942 #define NPS_R_XLDST (NPS_WXORB_SIZE + 1)
1943 { 6, 5, 0, ARC_OPERAND_IR, NULL, NULL },
1945 #define NPS_DIV_UIMM4 (NPS_R_XLDST + 1)
1946 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1948 #define NPS_QCMP_SIZE (NPS_DIV_UIMM4 + 1)
1949 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_qcmp_size, extract_nps_qcmp_size },
1951 #define NPS_QCMP_M1 (NPS_QCMP_SIZE + 1)
1952 { 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1 },
1954 #define NPS_QCMP_M2 (NPS_QCMP_M1 + 1)
1955 { 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2 },
1957 #define NPS_QCMP_M3 (NPS_QCMP_M2 + 1)
1958 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3 },
1960 #define NPS_CALC_ENTRY_SIZE (NPS_QCMP_M3 + 1)
1961 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_calc_entry_size, extract_nps_calc_entry_size },
1963 #define NPS_R_DST_3B_SHORT (NPS_CALC_ENTRY_SIZE + 1)
1964 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_dst_short, extract_nps_3bit_dst_short },
1966 #define NPS_R_SRC1_3B_SHORT (NPS_R_DST_3B_SHORT + 1)
1967 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_dst_short, extract_nps_3bit_dst_short },
1969 #define NPS_R_SRC2_3B_SHORT (NPS_R_SRC1_3B_SHORT + 1)
1970 { 3, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_src2_short, extract_nps_3bit_src2_short },
1972 #define NPS_BITOP_SIZE2 (NPS_R_SRC2_3B_SHORT + 1)
1973 { 5, 25, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop2_size, extract_nps_bitop2_size },
1975 #define NPS_BITOP_SIZE1 (NPS_BITOP_SIZE2 + 1)
1976 { 5, 20, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop1_size, extract_nps_bitop1_size },
1978 #define NPS_BITOP_DST_POS3_POS4 (NPS_BITOP_SIZE1 + 1)
1979 { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_dst_pos3_pos4, extract_nps_bitop_dst_pos3_pos4 },
1981 #define NPS_BITOP_DST_POS4 (NPS_BITOP_DST_POS3_POS4 + 1)
1982 { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1984 #define NPS_BITOP_DST_POS3 (NPS_BITOP_DST_POS4 + 1)
1985 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1987 #define NPS_BITOP_DST_POS2 (NPS_BITOP_DST_POS3 + 1)
1988 { 5, 15, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1990 #define NPS_BITOP_DST_POS1 (NPS_BITOP_DST_POS2 + 1)
1991 { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1993 #define NPS_BITOP_SRC_POS4 (NPS_BITOP_DST_POS1 + 1)
1994 { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1996 #define NPS_BITOP_SRC_POS3 (NPS_BITOP_SRC_POS4 + 1)
1997 { 5, 20, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1999 #define NPS_BITOP_SRC_POS2 (NPS_BITOP_SRC_POS3 + 1)
2000 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2002 #define NPS_BITOP_SRC_POS1 (NPS_BITOP_SRC_POS2 + 1)
2003 { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2005 #define NPS_BITOP_MOD4_MSB (NPS_BITOP_SRC_POS1 + 1)
2006 { 2, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_mod4_msb, extract_nps_bitop_mod4_msb },
2008 #define NPS_BITOP_MOD4_LSB (NPS_BITOP_MOD4_MSB + 1)
2009 { 2, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_mod4_lsb, extract_nps_bitop_mod4_lsb },
2011 #define NPS_BITOP_MOD3 (NPS_BITOP_MOD4_LSB + 1)
2012 { 2, 29, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2014 #define NPS_BITOP_MOD2 (NPS_BITOP_MOD3 + 1)
2015 { 2, 27, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2017 #define NPS_BITOP_MOD1 (NPS_BITOP_MOD2 + 1)
2018 { 2, 25, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2020 #define NPS_BITOP_INS_EXT (NPS_BITOP_MOD1 + 1)
2021 { 5, 20, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext },
2023 #define NPS_FIELD_START_POS (NPS_BITOP_INS_EXT + 1)
2024 { 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2026 #define NPS_FIELD_SIZE (NPS_FIELD_START_POS + 1)
2027 { 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_field_size, extract_nps_field_size },
2029 #define NPS_SHIFT_FACTOR (NPS_FIELD_SIZE + 1)
2030 { 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_shift_factor, extract_nps_shift_factor },
2032 #define NPS_BITS_TO_SCRAMBLE (NPS_SHIFT_FACTOR + 1)
2033 { 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bits_to_scramble, extract_nps_bits_to_scramble },
2035 #define NPS_SRC2_POS_5B (NPS_BITS_TO_SCRAMBLE + 1)
2036 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2038 #define NPS_BDLEN_MAX_LEN (NPS_SRC2_POS_5B + 1)
2039 { 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bdlen_max_len, extract_nps_bdlen_max_len },
2041 #define NPS_MIN_HOFS (NPS_BDLEN_MAX_LEN + 1)
2042 { 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_min_hofs, extract_nps_min_hofs },
2044 #define NPS_PSBC (NPS_MIN_HOFS + 1)
2045 { 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2047 #define NPS_DPI_DST (NPS_PSBC + 1)
2048 { 5, 11, 0, ARC_OPERAND_IR, NULL, NULL },
2050 /* NPS_DPI_SRC1_3B is similar to NPS_R_SRC1_3B but doesn't duplicate an operand */
2051 #define NPS_DPI_SRC1_3B (NPS_DPI_DST + 1)
2052 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
2054 #define NPS_HASH_WIDTH (NPS_DPI_SRC1_3B + 1)
2055 { 5, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_width, extract_nps_hash_width },
2057 #define NPS_HASH_PERM (NPS_HASH_WIDTH + 1)
2058 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2060 #define NPS_HASH_NONLINEAR (NPS_HASH_PERM + 1)
2061 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2063 #define NPS_HASH_BASEMAT (NPS_HASH_NONLINEAR + 1)
2064 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2066 #define NPS_HASH_LEN (NPS_HASH_BASEMAT + 1)
2067 { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_len, extract_nps_hash_len },
2069 #define NPS_HASH_OFS (NPS_HASH_LEN + 1)
2070 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2072 #define NPS_HASH_BASEMAT2 (NPS_HASH_OFS + 1)
2073 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2075 #define NPS_E4BY_INDEX0 (NPS_HASH_BASEMAT2 + 1)
2076 { 3, 8, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2078 #define NPS_E4BY_INDEX1 (NPS_E4BY_INDEX0 + 1)
2079 { 3, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2081 #define NPS_E4BY_INDEX2 (NPS_E4BY_INDEX1 + 1)
2082 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2084 #define NPS_E4BY_INDEX3 (NPS_E4BY_INDEX2 + 1)
2085 { 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_index3, extract_nps_index3 },
2088 const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
2090 const unsigned arc_Toperand = FKT_T;
2091 const unsigned arc_NToperand = FKT_NT;
2093 const unsigned char arg_none[] = { 0 };
2094 const unsigned char arg_32bit_rarbrc[] = { RA, RB, RC };
2095 const unsigned char arg_32bit_zarbrc[] = { ZA, RB, RC };
2096 const unsigned char arg_32bit_rbrbrc[] = { RB, RBdup, RC };
2097 const unsigned char arg_32bit_rarbu6[] = { RA, RB, UIMM6_20 };
2098 const unsigned char arg_32bit_zarbu6[] = { ZA, RB, UIMM6_20 };
2099 const unsigned char arg_32bit_rbrbu6[] = { RB, RBdup, UIMM6_20 };
2100 const unsigned char arg_32bit_rbrbs12[] = { RB, RBdup, SIMM12_20 };
2101 const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC };
2102 const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM };
2103 const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC };
2104 const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM };
2106 const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM };
2107 const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 };
2108 const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 };
2110 const unsigned char arg_32bit_zalimms12[] = { ZA, LIMM, SIMM12_20 };
2111 const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup };
2112 const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup };
2114 const unsigned char arg_32bit_rbrc[] = { RB, RC };
2115 const unsigned char arg_32bit_zarc[] = { ZA, RC };
2116 const unsigned char arg_32bit_rbu6[] = { RB, UIMM6_20 };
2117 const unsigned char arg_32bit_zau6[] = { ZA, UIMM6_20 };
2118 const unsigned char arg_32bit_rblimm[] = { RB, LIMM };
2119 const unsigned char arg_32bit_zalimm[] = { ZA, LIMM };
2121 const unsigned char arg_32bit_limmrc[] = { LIMM, RC };
2122 const unsigned char arg_32bit_limmu6[] = { LIMM, UIMM6_20 };
2123 const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 };
2124 const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup };
2126 const unsigned char arg_32bit_rc[] = { RC };
2127 const unsigned char arg_32bit_u6[] = { UIMM6_20 };
2128 const unsigned char arg_32bit_limm[] = { LIMM };
2130 /* The opcode table.
2132 The format of the opcode table is:
2134 NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }.
2136 The table is organised such that, where possible, all instructions with
2137 the same mnemonic are together in a block. When the assembler searches
2138 for a suitable instruction the entries are checked in table order, so
2139 more specific, or specialised cases should appear earlier in the table.
2141 As an example, consider two instructions 'add a,b,u6' and 'add
2142 a,b,limm'. The first takes a 6-bit immediate that is encoded within the
2143 32-bit instruction, while the second takes a 32-bit immediate that is
2144 encoded in a follow-on 32-bit, making the total instruction length
2145 64-bits. In this case the u6 variant must appear first in the table, as
2146 all u6 immediates could also be encoded using the 'limm' extension,
2147 however, we want to use the shorter instruction wherever possible.
2149 It is possible though to split instructions with the same mnemonic into
2150 multiple groups. However, the instructions are still checked in table
2151 order, even across groups. The only time that instructions with the
2152 same mnemonic should be split into different groups is when different
2153 variants of the instruction appear in different architectures, in which
2154 case, grouping all instructions from a particular architecture together
2155 might be preferable to merging the instruction into the main instruction
2158 An example of this split instruction groups can be found with the 'sync'
2159 instruction. The core arc architecture provides a 'sync' instruction,
2160 while the nps instruction set extension provides 'sync.rd' and
2161 'sync.wr'. The rd/wr flags are instruction flags, not part of the
2162 mnemonic, so we end up with two groups for the sync instruction, the
2163 first within the core arc instruction table, and the second within the
2164 nps extension instructions. */
2165 const struct arc_opcode arc_opcodes[] =
2167 #include "arc-tbl.h"
2168 #include "arc-nps400-tbl.h"
2169 #include "arc-ext-tbl.h"
2171 { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } }
2174 /* List with special cases instructions and the applicable flags. */
2175 const struct arc_flag_special arc_flag_special_cases[] =
2177 { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2178 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2179 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2180 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2181 { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2182 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2183 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2184 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2185 { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2186 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2187 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2188 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2189 { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2190 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2191 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2192 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2193 { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2194 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2195 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2196 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2197 { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2198 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2199 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2200 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2201 { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2202 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2203 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2204 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2205 { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } },
2206 { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } }
2209 const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
2212 const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
2214 { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
2215 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2216 { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
2217 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2218 { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
2219 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2220 { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
2221 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2223 /* Next two entries will cover the undefined behavior ldb/stb with
2225 { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
2226 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
2227 { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
2228 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
2230 { "sda", "ld", { F_ASFAKE, F_NULL },
2231 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
2232 { "sda", "st", { F_ASFAKE, F_NULL },
2233 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
2234 { "sda", "ldd", { F_ASFAKE, F_NULL },
2235 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
2236 { "sda", "std", { F_ASFAKE, F_NULL },
2237 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
2239 /* Short instructions. */
2240 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
2241 { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
2242 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
2243 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
2245 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
2246 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
2248 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
2249 BFD_RELOC_ARC_S25H_PCREL_PLT },
2250 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
2251 BFD_RELOC_ARC_S21H_PCREL_PLT },
2252 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
2253 BFD_RELOC_ARC_S25W_PCREL_PLT },
2254 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
2255 BFD_RELOC_ARC_S21W_PCREL_PLT },
2257 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
2260 const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
2262 const struct arc_pseudo_insn arc_pseudo_insns[] =
2264 { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
2265 { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
2266 { BRAKETdup, 1, 0, 4} } },
2267 { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
2268 { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
2269 { BRAKETdup, 1, 0, 4} } },
2271 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2272 { SIMM9_A16_8, 0, 0, 2 } } },
2273 { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2274 { SIMM9_A16_8, 0, 0, 2 } } },
2275 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2276 { SIMM9_A16_8, 0, 0, 2 } } },
2277 { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2278 { SIMM9_A16_8, 0, 0, 2 } } },
2279 { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2280 { SIMM9_A16_8, 0, 0, 2 } } },
2282 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2283 { SIMM9_A16_8, 0, 0, 2 } } },
2284 { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2285 { SIMM9_A16_8, 0, 0, 2 } } },
2286 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2287 { SIMM9_A16_8, 0, 0, 2 } } },
2288 { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2289 { SIMM9_A16_8, 0, 0, 2 } } },
2290 { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2291 { SIMM9_A16_8, 0, 0, 2 } } },
2293 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2294 { SIMM9_A16_8, 0, 0, 2 } } },
2295 { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2296 { SIMM9_A16_8, 0, 0, 2 } } },
2297 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2298 { SIMM9_A16_8, 0, 0, 2 } } },
2299 { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2300 { SIMM9_A16_8, 0, 0, 2 } } },
2301 { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2302 { SIMM9_A16_8, 0, 0, 2 } } },
2304 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2305 { SIMM9_A16_8, 0, 0, 2 } } },
2306 { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2307 { SIMM9_A16_8, 0, 0, 2 } } },
2308 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2309 { SIMM9_A16_8, 0, 0, 2 } } },
2310 { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2311 { SIMM9_A16_8, 0, 0, 2 } } },
2312 { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2313 { SIMM9_A16_8, 0, 0, 2 } } },
2316 const unsigned arc_num_pseudo_insn =
2317 sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
2319 const struct arc_aux_reg arc_aux_regs[] =
2322 #define DEF(ADDR, CPU, SUBCLASS, NAME) \
2323 { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 },
2325 #include "arc-regs.h"
2330 const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);
2332 /* NOTE: The order of this array MUST be consistent with 'enum
2333 arc_rlx_types' located in tc-arc.h! */
2334 const struct arc_opcode arc_relax_opcodes[] =
2336 { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } },
2338 /* bl_s s13 11111sssssssssss. */
2339 { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2340 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2341 { SIMM13_A32_5_S }, { 0 }},
2343 /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
2344 { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2345 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2346 { SIMM25_A32_5 }, { C_D }},
2348 /* b_s s10 1111000sssssssss. */
2349 { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2350 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2351 { SIMM10_A16_7_S }, { 0 }},
2353 /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
2354 { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2355 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2356 { SIMM25_A16_5 }, { C_D }},
2358 /* add_s c,b,u3 01101bbbccc00uuu. Wants UIMM3_13_S_PCREL. */
2359 { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2360 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2361 { RC_S, RB_S, UIMM3_13_S }, { 0 }},
2363 /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. Wants
2365 { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2366 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2367 { RA, RB, UIMM6_20 }, { C_F }},
2369 /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
2370 { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2371 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2372 { RA, RB, LIMM }, { C_F }},
2374 /* ld_s c,b,u7 10000bbbcccuuuuu. Wants UIMM7_A32_11_S_PCREL. */
2375 { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2376 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2377 { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
2379 /* ld<.di><.aa><.x><zz> a,b,s9
2380 00010bbbssssssssSBBBDaaZZXAAAAAA. Wants SIMM9_8_PCREL. */
2381 { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2382 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2383 { RA, BRAKET, RB, SIMM9_8, BRAKETdup },
2384 { C_ZZ23, C_DI20, C_AA21, C_X25 }},
2386 /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */
2387 { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2388 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2389 { RA, BRAKET, RB, LIMM, BRAKETdup },
2390 { C_ZZ13, C_DI16, C_AA8, C_X15 }},
2392 /* mov_s b,u8 11011bbbuuuuuuuu. Wants UIMM8_8_S_PCREL. */
2393 { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2394 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2395 { RB_S, UIMM8_8_S }, { 0 }},
2397 /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. Wants
2399 { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2400 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2401 { RB, SIMM12_20 }, { C_F }},
2403 /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
2404 { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2405 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2406 { RB, LIMM }, { C_F }},
2408 /* sub_s c,b,u3 01101bbbccc01uuu. UIMM3_13_S_PCREL. */
2409 { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2410 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2411 { RC_S, RB_S, UIMM3_13_S }, { 0 }},
2413 /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA.
2415 { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2416 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2417 { RA, RB, UIMM6_20 }, { C_F }},
2419 /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
2420 { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2421 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2422 { RA, RB, LIMM }, { C_F }},
2424 /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA.
2426 { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
2427 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }},
2429 /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
2430 { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
2431 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
2433 /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ.
2435 { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2436 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2437 { RB, UIMM6_20 }, { C_F, C_CC }},
2439 /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
2440 { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2441 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2442 { RB, LIMM }, { C_F, C_CC }},
2444 /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ.
2446 { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2447 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2448 { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
2450 /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
2451 { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2452 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2453 { RB, RBdup, LIMM }, { C_F, C_CC }}
2456 const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);
2458 /* The following instructions are all either 48 or 64 bits long, and
2459 require special handling in the assembler and disassembler.
2461 The first part of each ARC_LONG_OPCODE is the base ARC_OPCODE, this is
2462 either the 16 or 32 bit base instruction, and its opcode list will
2463 always end in a LIMM.
2465 The rest of the ARC_LONG_OPCODE describes how to build the LIMM from the
2466 instruction operands. There are therefore two lists of operands for
2467 each ARC_LONG_OPCODE, the second list contains operands that are merged
2468 into the limm template, in the same way that a standard 32-bit
2469 instruction is built. This generated limm is then added to the list of
2470 tokens that is passed to the standard instruction encoder, along with
2471 the first list of operands (from the base arc_opcode).
2473 The first list of operands then, describes how to build the base
2474 instruction, and includes the 32-bit limm that was previously generated
2475 as the last operand.
2477 In most cases operands are either encoded into the base instruction or
2478 into the limm. When this happens the operand slot will be filled with
2479 an operand identifier in one list, and will be IGNORED in the other
2480 list, this special operand value causes the operand to be ignored,
2481 without being encoded at this point.
2483 However, in some cases, an operand is split between the base instruction
2484 and the 32-bit limm, in this case the operand slot will be filled in
2485 both operand lists (see mov4b for one example of this). */
2486 const struct arc_long_opcode arc_long_opcodes[] =
2488 /* mrgb - (48 bit instruction). */
2489 { { "mrgb", 0x5803, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }},
2490 0x00000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_SRC_POS1, NPS_BITOP_SIZE1, NPS_BITOP_DST_POS2, NPS_BITOP_SRC_POS2, NPS_BITOP_SIZE2 }},
2492 /* mrgb.cl - (48 bit instruction). */
2493 { { "mrgb", 0x5803, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }},
2494 0x80000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_SRC_POS1, NPS_BITOP_SIZE1, NPS_BITOP_DST_POS2, NPS_BITOP_SRC_POS2, NPS_BITOP_SIZE2 }},
2496 /* mov2b - (48 bit instruction). */
2497 { { "mov2b", 0x5800, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }},
2498 0x00000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2 }},
2500 /* mov2b.cl - (48 bit instruction). */
2501 { { "mov2b", 0x5800, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }},
2502 0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2 }},
2504 /* ext4 - (48 bit instruction). */
2505 { { "ext4b", 0x5801, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }},
2506 0x00000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_INS_EXT, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2 }},
2508 /* ext4.cl - (48 bit instruction). */
2509 { { "ext4b", 0x5801, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }},
2510 0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_INS_EXT, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2 }},
2512 /* ins4 - (48 bit instruction). */
2513 { { "ins4b", 0x5802, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }},
2514 0x00000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_INS_EXT }},
2516 /* ins4.cl - (48 bit instruction). */
2517 { { "ins4b", 0x5802, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }},
2518 0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_INS_EXT }},
2520 /* mov3b - (64 bit instruction). */
2521 { { "mov3b", 0x58100000, 0xf81f801f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3_POS4, IGNORED, IGNORED, LIMM }, { 0 }},
2522 0x80000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3 }},
2524 /* mov4b - (64 bit instruction). */
2525 { { "mov4b", 0x58100000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3, IGNORED, IGNORED, NPS_BITOP_DST_POS4, NPS_BITOP_MOD4_LSB, NPS_BITOP_SRC_POS4, LIMM }, { 0 }},
2526 0x00000000, 0x00000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3, IGNORED, NPS_BITOP_MOD4_MSB, IGNORED}},
2528 /* mov3bcl - (64 bit instruction). */
2529 { { "mov3bcl", 0x58110000, 0xf81f801f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3_POS4, IGNORED, IGNORED, LIMM }, { 0 }},
2530 0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3 }},
2532 /* mov4bcl - (64 bit instruction). */
2533 { { "mov4bcl", 0x58110000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3, IGNORED, IGNORED, NPS_BITOP_DST_POS4, NPS_BITOP_MOD4_LSB, NPS_BITOP_SRC_POS4, LIMM }, { 0 }},
2534 0x00000000, 0x00000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3, IGNORED, NPS_BITOP_MOD4_MSB, IGNORED}},
2536 /* mov3b.cl - (64 bit instruction). */
2537 { { "mov3b", 0x58110000, 0xf81f801f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3_POS4, IGNORED, IGNORED, LIMM }, { C_NPS_CL }},
2538 0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3 }},
2540 /* mov4b.cl - (64 bit instruction). */
2541 { { "mov4b", 0x58110000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3, IGNORED, IGNORED, NPS_BITOP_DST_POS4, NPS_BITOP_MOD4_LSB, NPS_BITOP_SRC_POS4, LIMM }, { C_NPS_CL }},
2542 0x00000000, 0x00000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3, IGNORED, NPS_BITOP_MOD4_MSB, IGNORED}},
2545 const unsigned arc_num_long_opcodes = ARRAY_SIZE (arc_long_opcodes);