1 /* Opcode table for the ARC.
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software Foundation,
20 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
25 #include "opcode/arc.h"
27 #include "libiberty.h"
29 /* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
30 instructions. Support for this target is available when binutils is
31 configured and built for the 'arc*-mellanox-*-*' target. As far as
32 possible all ARC NPS400 features are built into all ARC target builds as
33 this reduces the chances that regressions might creep in. */
35 /* Insert RB register into a 32-bit opcode. */
37 insert_rb (unsigned insn,
39 const char **errmsg ATTRIBUTE_UNUSED)
41 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
45 extract_rb (unsigned insn ATTRIBUTE_UNUSED,
46 bfd_boolean * invalid ATTRIBUTE_UNUSED)
48 int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
50 if (value == 0x3e && invalid)
51 *invalid = TRUE; /* A limm operand, it should be extracted in a
58 insert_rad (unsigned insn,
60 const char **errmsg ATTRIBUTE_UNUSED)
63 *errmsg = _("Improper register value.");
65 return insn | (value & 0x3F);
69 insert_rcd (unsigned insn,
71 const char **errmsg ATTRIBUTE_UNUSED)
74 *errmsg = _("Improper register value.");
76 return insn | ((value & 0x3F) << 6);
79 /* Dummy insert ZERO operand function. */
82 insert_za (unsigned insn,
87 *errmsg = _("operand is not zero");
91 /* Insert Y-bit in bbit/br instructions. This function is called only
92 when solving fixups. */
95 insert_Ybit (unsigned insn,
97 const char **errmsg ATTRIBUTE_UNUSED)
105 /* Insert Y-bit in bbit/br instructions. This function is called only
106 when solving fixups. */
109 insert_NYbit (unsigned insn,
111 const char **errmsg ATTRIBUTE_UNUSED)
119 /* Insert H register into a 16-bit opcode. */
122 insert_rhv1 (unsigned insn,
124 const char **errmsg ATTRIBUTE_UNUSED)
126 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
130 extract_rhv1 (unsigned insn ATTRIBUTE_UNUSED,
131 bfd_boolean * invalid ATTRIBUTE_UNUSED)
138 /* Insert H register into a 16-bit opcode. */
141 insert_rhv2 (unsigned insn,
147 _("Register R30 is a limm indicator for this type of instruction.");
148 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
152 extract_rhv2 (unsigned insn ATTRIBUTE_UNUSED,
153 bfd_boolean * invalid ATTRIBUTE_UNUSED)
155 int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
161 insert_r0 (unsigned insn,
163 const char **errmsg ATTRIBUTE_UNUSED)
166 *errmsg = _("Register must be R0.");
171 extract_r0 (unsigned insn ATTRIBUTE_UNUSED,
172 bfd_boolean * invalid ATTRIBUTE_UNUSED)
179 insert_r1 (unsigned insn,
181 const char **errmsg ATTRIBUTE_UNUSED)
184 *errmsg = _("Register must be R1.");
189 extract_r1 (unsigned insn ATTRIBUTE_UNUSED,
190 bfd_boolean * invalid ATTRIBUTE_UNUSED)
196 insert_r2 (unsigned insn,
198 const char **errmsg ATTRIBUTE_UNUSED)
201 *errmsg = _("Register must be R2.");
206 extract_r2 (unsigned insn ATTRIBUTE_UNUSED,
207 bfd_boolean * invalid ATTRIBUTE_UNUSED)
213 insert_r3 (unsigned insn,
215 const char **errmsg ATTRIBUTE_UNUSED)
218 *errmsg = _("Register must be R3.");
223 extract_r3 (unsigned insn ATTRIBUTE_UNUSED,
224 bfd_boolean * invalid ATTRIBUTE_UNUSED)
230 insert_sp (unsigned insn,
232 const char **errmsg ATTRIBUTE_UNUSED)
235 *errmsg = _("Register must be SP.");
240 extract_sp (unsigned insn ATTRIBUTE_UNUSED,
241 bfd_boolean * invalid ATTRIBUTE_UNUSED)
247 insert_gp (unsigned insn,
249 const char **errmsg ATTRIBUTE_UNUSED)
252 *errmsg = _("Register must be GP.");
257 extract_gp (unsigned insn ATTRIBUTE_UNUSED,
258 bfd_boolean * invalid ATTRIBUTE_UNUSED)
264 insert_pcl (unsigned insn,
266 const char **errmsg ATTRIBUTE_UNUSED)
269 *errmsg = _("Register must be PCL.");
274 extract_pcl (unsigned insn ATTRIBUTE_UNUSED,
275 bfd_boolean * invalid ATTRIBUTE_UNUSED)
281 insert_blink (unsigned insn,
283 const char **errmsg ATTRIBUTE_UNUSED)
286 *errmsg = _("Register must be BLINK.");
291 extract_blink (unsigned insn ATTRIBUTE_UNUSED,
292 bfd_boolean * invalid ATTRIBUTE_UNUSED)
298 insert_ilink1 (unsigned insn,
300 const char **errmsg ATTRIBUTE_UNUSED)
303 *errmsg = _("Register must be ILINK1.");
308 extract_ilink1 (unsigned insn ATTRIBUTE_UNUSED,
309 bfd_boolean * invalid ATTRIBUTE_UNUSED)
315 insert_ilink2 (unsigned insn,
317 const char **errmsg ATTRIBUTE_UNUSED)
320 *errmsg = _("Register must be ILINK2.");
325 extract_ilink2 (unsigned insn ATTRIBUTE_UNUSED,
326 bfd_boolean * invalid ATTRIBUTE_UNUSED)
332 insert_ras (unsigned insn,
334 const char **errmsg ATTRIBUTE_UNUSED)
351 *errmsg = _("Register must be either r0-r3 or r12-r15.");
358 extract_ras (unsigned insn ATTRIBUTE_UNUSED,
359 bfd_boolean * invalid ATTRIBUTE_UNUSED)
361 int value = insn & 0x07;
369 insert_rbs (unsigned insn,
371 const char **errmsg ATTRIBUTE_UNUSED)
385 insn |= ((value - 8)) << 8;
388 *errmsg = _("Register must be either r0-r3 or r12-r15.");
395 extract_rbs (unsigned insn ATTRIBUTE_UNUSED,
396 bfd_boolean * invalid ATTRIBUTE_UNUSED)
398 int value = (insn >> 8) & 0x07;
406 insert_rcs (unsigned insn,
408 const char **errmsg ATTRIBUTE_UNUSED)
422 insn |= ((value - 8)) << 5;
425 *errmsg = _("Register must be either r0-r3 or r12-r15.");
432 extract_rcs (unsigned insn ATTRIBUTE_UNUSED,
433 bfd_boolean * invalid ATTRIBUTE_UNUSED)
435 int value = (insn >> 5) & 0x07;
443 insert_simm3s (unsigned insn,
445 const char **errmsg ATTRIBUTE_UNUSED)
475 *errmsg = _("Accepted values are from -1 to 6.");
484 extract_simm3s (unsigned insn ATTRIBUTE_UNUSED,
485 bfd_boolean * invalid ATTRIBUTE_UNUSED)
487 int value = (insn >> 8) & 0x07;
495 insert_rrange (unsigned insn,
497 const char **errmsg ATTRIBUTE_UNUSED)
499 int reg1 = (value >> 16) & 0xFFFF;
500 int reg2 = value & 0xFFFF;
503 *errmsg = _("First register of the range should be r13.");
506 if (reg2 < 13 || reg2 > 26)
508 *errmsg = _("Last register of the range doesn't fit.");
511 insn |= ((reg2 - 12) & 0x0F) << 1;
516 extract_rrange (unsigned insn ATTRIBUTE_UNUSED,
517 bfd_boolean * invalid ATTRIBUTE_UNUSED)
519 return (insn >> 1) & 0x0F;
523 insert_fpel (unsigned insn,
525 const char **errmsg ATTRIBUTE_UNUSED)
529 *errmsg = _("Invalid register number, should be fp.");
538 extract_fpel (unsigned insn ATTRIBUTE_UNUSED,
539 bfd_boolean * invalid ATTRIBUTE_UNUSED)
541 return (insn & 0x0100) ? 27 : -1;
545 insert_blinkel (unsigned insn,
547 const char **errmsg ATTRIBUTE_UNUSED)
551 *errmsg = _("Invalid register number, should be blink.");
560 extract_blinkel (unsigned insn ATTRIBUTE_UNUSED,
561 bfd_boolean * invalid ATTRIBUTE_UNUSED)
563 return (insn & 0x0200) ? 31 : -1;
567 insert_pclel (unsigned insn,
569 const char **errmsg ATTRIBUTE_UNUSED)
573 *errmsg = _("Invalid register number, should be pcl.");
582 extract_pclel (unsigned insn ATTRIBUTE_UNUSED,
583 bfd_boolean * invalid ATTRIBUTE_UNUSED)
585 return (insn & 0x0400) ? 63 : -1;
589 /* mask = 00000000000000000000111111000000
590 insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */
592 insert_w6 (unsigned insn ATTRIBUTE_UNUSED,
593 int value ATTRIBUTE_UNUSED,
594 const char **errmsg ATTRIBUTE_UNUSED)
596 insn |= ((value >> 0) & 0x003f) << 6;
602 /* mask = 00000000000000000000111111000000. */
604 extract_w6 (unsigned insn ATTRIBUTE_UNUSED,
605 bfd_boolean * invalid ATTRIBUTE_UNUSED)
609 value |= ((insn >> 6) & 0x003f) << 0;
615 /* mask = 0000011100022000
616 insn = 01000ggghhhGG0HH. */
618 insert_g_s (unsigned insn ATTRIBUTE_UNUSED,
619 int value ATTRIBUTE_UNUSED,
620 const char **errmsg ATTRIBUTE_UNUSED)
622 insn |= ((value >> 0) & 0x0007) << 8;
623 insn |= ((value >> 3) & 0x0003) << 3;
629 /* mask = 0000011100022000. */
631 extract_g_s (unsigned insn ATTRIBUTE_UNUSED,
632 bfd_boolean * invalid ATTRIBUTE_UNUSED)
636 value |= ((insn >> 8) & 0x0007) << 0;
637 value |= ((insn >> 3) & 0x0003) << 3;
639 /* Extend the sign. */
640 int signbit = 1 << (6 - 1);
641 value = (value ^ signbit) - signbit;
646 /* ARC NPS400 Support: See comment near head of file. */
648 insert_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED,
649 int value ATTRIBUTE_UNUSED,
650 const char **errmsg ATTRIBUTE_UNUSED)
664 insn |= (value - 8) << 24;
667 *errmsg = _("Register must be either r0-r3 or r12-r15.");
674 extract_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED,
675 bfd_boolean * invalid ATTRIBUTE_UNUSED)
677 int value = (insn >> 24) & 0x07;
685 insert_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED,
686 int value ATTRIBUTE_UNUSED,
687 const char **errmsg ATTRIBUTE_UNUSED)
701 insn |= (value - 8) << 21;
704 *errmsg = _("Register must be either r0-r3 or r12-r15.");
711 extract_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED,
712 bfd_boolean * invalid ATTRIBUTE_UNUSED)
714 int value = (insn >> 21) & 0x07;
722 insert_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED,
723 int value ATTRIBUTE_UNUSED,
724 const char **errmsg ATTRIBUTE_UNUSED)
726 if (value < 1 || value > 32)
728 *errmsg = _("Invalid bit size, should be between 1 and 32 inclusive.");
733 insn |= ((value & 0x1f) << 10);
738 extract_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED,
739 bfd_boolean * invalid ATTRIBUTE_UNUSED)
741 return ((insn >> 10) & 0x1f) + 1;
745 insert_nps_bitop_size_2b (unsigned insn ATTRIBUTE_UNUSED,
746 int value ATTRIBUTE_UNUSED,
747 const char **errmsg ATTRIBUTE_UNUSED)
765 *errmsg = _("Invalid size, should be 1, 2, 4, or 8.");
774 extract_nps_bitop_size_2b (unsigned insn ATTRIBUTE_UNUSED,
775 bfd_boolean * invalid ATTRIBUTE_UNUSED)
777 return 1 << ((insn >> 10) & 0x3);
781 insert_nps_bitop_uimm8 (unsigned insn ATTRIBUTE_UNUSED,
782 int value ATTRIBUTE_UNUSED,
783 const char **errmsg ATTRIBUTE_UNUSED)
785 insn |= ((value >> 5) & 7) << 12;
786 insn |= (value & 0x1f);
791 extract_nps_bitop_uimm8 (unsigned insn ATTRIBUTE_UNUSED,
792 bfd_boolean * invalid ATTRIBUTE_UNUSED)
794 return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f);
798 insert_nps_rflt_uimm6 (unsigned insn ATTRIBUTE_UNUSED,
799 int value ATTRIBUTE_UNUSED,
800 const char **errmsg ATTRIBUTE_UNUSED)
810 *errmsg = _("invalid immediate, must be 1, 2, or 4");
814 insn |= (value << 6);
819 extract_nps_rflt_uimm6 (unsigned insn ATTRIBUTE_UNUSED,
820 bfd_boolean * invalid ATTRIBUTE_UNUSED)
822 return (insn >> 6) & 0x3f;
826 insert_nps_dst_pos_and_size (unsigned insn ATTRIBUTE_UNUSED,
827 int value ATTRIBUTE_UNUSED,
828 const char **errmsg ATTRIBUTE_UNUSED)
830 insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10));
835 extract_nps_dst_pos_and_size (unsigned insn ATTRIBUTE_UNUSED,
836 bfd_boolean * invalid ATTRIBUTE_UNUSED)
838 return (insn & 0x1f);
841 /* Include the generic extract/insert functions. Order is important
842 as some of the functions present in the .h may be disabled via
846 /* The flag operands table.
848 The format of the table is
849 NAME CODE BITS SHIFT FAVAIL. */
850 const struct arc_flag_operand arc_flag_operands[] =
854 #define F_ALWAYS (F_NULL + 1)
855 { "al", 0, 0, 0, 0 },
856 #define F_RA (F_ALWAYS + 1)
857 { "ra", 0, 0, 0, 0 },
858 #define F_EQUAL (F_RA + 1)
859 { "eq", 1, 5, 0, 1 },
860 #define F_ZERO (F_EQUAL + 1)
862 #define F_NOTEQUAL (F_ZERO + 1)
863 { "ne", 2, 5, 0, 1 },
864 #define F_NOTZERO (F_NOTEQUAL + 1)
865 { "nz", 2, 5, 0, 0 },
866 #define F_POZITIVE (F_NOTZERO + 1)
868 #define F_PL (F_POZITIVE + 1)
869 { "pl", 3, 5, 0, 0 },
870 #define F_NEGATIVE (F_PL + 1)
872 #define F_MINUS (F_NEGATIVE + 1)
873 { "mi", 4, 5, 0, 0 },
874 #define F_CARRY (F_MINUS + 1)
876 #define F_CARRYSET (F_CARRY + 1)
877 { "cs", 5, 5, 0, 0 },
878 #define F_LOWER (F_CARRYSET + 1)
879 { "lo", 5, 5, 0, 0 },
880 #define F_CARRYCLR (F_LOWER + 1)
881 { "cc", 6, 5, 0, 0 },
882 #define F_NOTCARRY (F_CARRYCLR + 1)
883 { "nc", 6, 5, 0, 1 },
884 #define F_HIGHER (F_NOTCARRY + 1)
885 { "hs", 6, 5, 0, 0 },
886 #define F_OVERFLOWSET (F_HIGHER + 1)
887 { "vs", 7, 5, 0, 0 },
888 #define F_OVERFLOW (F_OVERFLOWSET + 1)
890 #define F_NOTOVERFLOW (F_OVERFLOW + 1)
891 { "nv", 8, 5, 0, 1 },
892 #define F_OVERFLOWCLR (F_NOTOVERFLOW + 1)
893 { "vc", 8, 5, 0, 0 },
894 #define F_GT (F_OVERFLOWCLR + 1)
895 { "gt", 9, 5, 0, 1 },
896 #define F_GE (F_GT + 1)
897 { "ge", 10, 5, 0, 1 },
898 #define F_LT (F_GE + 1)
899 { "lt", 11, 5, 0, 1 },
900 #define F_LE (F_LT + 1)
901 { "le", 12, 5, 0, 1 },
902 #define F_HI (F_LE + 1)
903 { "hi", 13, 5, 0, 1 },
904 #define F_LS (F_HI + 1)
905 { "ls", 14, 5, 0, 1 },
906 #define F_PNZ (F_LS + 1)
907 { "pnz", 15, 5, 0, 1 },
910 #define F_FLAG (F_PNZ + 1)
911 { "f", 1, 1, 15, 1 },
912 #define F_FFAKE (F_FLAG + 1)
916 #define F_ND (F_FFAKE + 1)
917 { "nd", 0, 1, 5, 0 },
918 #define F_D (F_ND + 1)
920 #define F_DFAKE (F_D + 1)
924 #define F_SIZEB1 (F_DFAKE + 1)
926 #define F_SIZEB7 (F_SIZEB1 + 1)
928 #define F_SIZEB17 (F_SIZEB7 + 1)
929 { "b", 1, 2, 17, 1 },
930 #define F_SIZEW1 (F_SIZEB17 + 1)
932 #define F_SIZEW7 (F_SIZEW1 + 1)
934 #define F_SIZEW17 (F_SIZEW7 + 1)
935 { "w", 2, 2, 17, 0 },
937 /* Sign extension. */
938 #define F_SIGN6 (F_SIZEW17 + 1)
940 #define F_SIGN16 (F_SIGN6 + 1)
941 { "x", 1, 1, 16, 1 },
942 #define F_SIGNX (F_SIGN16 + 1)
945 /* Address write-back modes. */
946 #define F_A3 (F_SIGNX + 1)
948 #define F_A9 (F_A3 + 1)
950 #define F_A22 (F_A9 + 1)
951 { "a", 1, 2, 22, 0 },
952 #define F_AW3 (F_A22 + 1)
953 { "aw", 1, 2, 3, 1 },
954 #define F_AW9 (F_AW3 + 1)
955 { "aw", 1, 2, 9, 1 },
956 #define F_AW22 (F_AW9 + 1)
957 { "aw", 1, 2, 22, 1 },
958 #define F_AB3 (F_AW22 + 1)
959 { "ab", 2, 2, 3, 1 },
960 #define F_AB9 (F_AB3 + 1)
961 { "ab", 2, 2, 9, 1 },
962 #define F_AB22 (F_AB9 + 1)
963 { "ab", 2, 2, 22, 1 },
964 #define F_AS3 (F_AB22 + 1)
965 { "as", 3, 2, 3, 1 },
966 #define F_AS9 (F_AS3 + 1)
967 { "as", 3, 2, 9, 1 },
968 #define F_AS22 (F_AS9 + 1)
969 { "as", 3, 2, 22, 1 },
970 #define F_ASFAKE (F_AS22 + 1)
971 { "as", 0, 0, 0, 1 },
974 #define F_DI5 (F_ASFAKE + 1)
975 { "di", 1, 1, 5, 1 },
976 #define F_DI11 (F_DI5 + 1)
977 { "di", 1, 1, 11, 1 },
978 #define F_DI15 (F_DI11 + 1)
979 { "di", 1, 1, 15, 1 },
981 /* ARCv2 specific. */
982 #define F_NT (F_DI15 + 1)
984 #define F_T (F_NT + 1)
986 #define F_H1 (F_T + 1)
988 #define F_H7 (F_H1 + 1)
990 #define F_H17 (F_H7 + 1)
991 { "h", 2, 2, 17, 1 },
994 #define F_NE (F_H17 + 1)
995 { "ne", 0, 0, 0, 1 },
997 /* ARC NPS400 Support: See comment near head of file. */
998 #define F_NPS_CL (F_NE + 1)
999 { "cl", 0, 0, 0, 1 },
1001 #define F_NPS_FLAG (F_NPS_CL + 1)
1002 { "f", 1, 1, 20, 1 },
1004 #define F_NPS_R (F_NPS_FLAG + 1)
1005 { "r", 1, 1, 15, 1 },
1008 const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
1010 /* Table of the flag classes.
1012 The format of the table is
1013 CLASS {FLAG_CODE}. */
1014 const struct arc_flag_class arc_flag_classes[] =
1017 { F_CLASS_NONE, { F_NULL } },
1019 #define C_CC (C_EMPTY + 1)
1020 { F_CLASS_OPTIONAL, { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
1021 F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
1022 F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1023 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
1024 F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
1025 F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1027 #define C_AA_ADDR3 (C_CC + 1)
1028 #define C_AA27 (C_CC + 1)
1029 { F_CLASS_OPTIONAL, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
1030 #define C_AA_ADDR9 (C_AA_ADDR3 + 1)
1031 #define C_AA21 (C_AA_ADDR3 + 1)
1032 { F_CLASS_OPTIONAL, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
1033 #define C_AA_ADDR22 (C_AA_ADDR9 + 1)
1034 #define C_AA8 (C_AA_ADDR9 + 1)
1035 { F_CLASS_OPTIONAL, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
1037 #define C_F (C_AA_ADDR22 + 1)
1038 { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },
1039 #define C_FHARD (C_F + 1)
1040 { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } },
1042 #define C_T (C_FHARD + 1)
1043 { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
1044 #define C_D (C_T + 1)
1045 { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
1047 #define C_DHARD (C_D + 1)
1048 { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
1050 #define C_DI20 (C_DHARD + 1)
1051 { F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
1052 #define C_DI16 (C_DI20 + 1)
1053 { F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
1054 #define C_DI26 (C_DI16 + 1)
1055 { F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
1057 #define C_X25 (C_DI26 + 1)
1058 { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }},
1059 #define C_X15 (C_X25 + 1)
1060 { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }},
1061 #define C_XHARD (C_X15 + 1)
1062 #define C_X (C_X15 + 1)
1063 { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }},
1065 #define C_ZZ13 (C_X + 1)
1066 { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
1067 #define C_ZZ23 (C_ZZ13 + 1)
1068 { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
1069 #define C_ZZ29 (C_ZZ23 + 1)
1070 { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
1072 #define C_AS (C_ZZ29 + 1)
1073 { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
1075 #define C_NE (C_AS + 1)
1076 { F_CLASS_OPTIONAL, { F_NE, F_NULL}},
1078 /* ARC NPS400 Support: See comment near head of file. */
1079 #define C_NPS_CL (C_NE + 1)
1080 { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}},
1082 #define C_NPS_F (C_NPS_CL + 1)
1083 { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
1085 #define C_NPS_R (C_NPS_F + 1)
1086 { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}},
1089 /* The operands table.
1091 The format of the operands table is:
1093 BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */
1094 const struct arc_operand arc_operands[] =
1096 /* The fields are bits, shift, insert, extract, flags. The zero
1097 index is used to indicate end-of-list. */
1099 { 0, 0, 0, 0, 0, 0 },
1100 /* The plain integer register fields. Used by 32 bit
1102 #define RA (UNUSED + 1)
1103 { 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
1105 { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
1107 { 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
1108 #define RBdup (RC + 1)
1109 { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
1111 #define RAD (RBdup + 1)
1112 { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
1113 #define RCD (RAD + 1)
1114 { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
1116 /* The plain integer register fields. Used by short
1118 #define RA16 (RCD + 1)
1119 #define RA_S (RCD + 1)
1120 { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
1121 #define RB16 (RA16 + 1)
1122 #define RB_S (RA16 + 1)
1123 { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs },
1124 #define RB16dup (RB16 + 1)
1125 #define RB_Sdup (RB16 + 1)
1126 { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs },
1127 #define RC16 (RB16dup + 1)
1128 #define RC_S (RB16dup + 1)
1129 { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs },
1130 #define R6H (RC16 + 1) /* 6bit register field 'h' used
1132 { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 },
1133 #define R5H (R6H + 1) /* 5bit register field 'h' used
1135 #define RH_S (R6H + 1) /* 5bit register field 'h' used
1137 { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 },
1138 #define R5Hdup (R5H + 1)
1139 #define RH_Sdup (R5H + 1)
1140 { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE,
1141 insert_rhv2, extract_rhv2 },
1143 #define RG (R5Hdup + 1)
1144 #define G_S (R5Hdup + 1)
1145 { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s },
1147 /* Fix registers. */
1149 #define R0_S (RG + 1)
1150 { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 },
1152 #define R1_S (R0 + 1)
1153 { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 },
1155 #define R2_S (R1 + 1)
1156 { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 },
1158 #define R3_S (R2 + 1)
1159 { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 },
1160 #define RSP (R3 + 1)
1161 #define SP_S (R3 + 1)
1162 { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp },
1163 #define SPdup (RSP + 1)
1164 #define SP_Sdup (RSP + 1)
1165 { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp },
1166 #define GP (SPdup + 1)
1167 #define GP_S (SPdup + 1)
1168 { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp },
1170 #define PCL_S (GP + 1)
1171 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl },
1173 #define BLINK (PCL_S + 1)
1174 #define BLINK_S (PCL_S + 1)
1175 { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink },
1177 #define ILINK1 (BLINK + 1)
1178 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 },
1179 #define ILINK2 (ILINK1 + 1)
1180 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 },
1182 /* Long immediate. */
1183 #define LIMM (ILINK2 + 1)
1184 #define LIMM_S (ILINK2 + 1)
1185 { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
1186 #define LIMMdup (LIMM + 1)
1187 { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 },
1189 /* Special operands. */
1190 #define ZA (LIMMdup + 1)
1191 #define ZB (LIMMdup + 1)
1192 #define ZA_S (LIMMdup + 1)
1193 #define ZB_S (LIMMdup + 1)
1194 #define ZC_S (LIMMdup + 1)
1195 { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 },
1197 #define RRANGE_EL (ZA + 1)
1198 { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
1199 insert_rrange, extract_rrange},
1200 #define FP_EL (RRANGE_EL + 1)
1201 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1202 insert_fpel, extract_fpel },
1203 #define BLINK_EL (FP_EL + 1)
1204 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1205 insert_blinkel, extract_blinkel },
1206 #define PCL_EL (BLINK_EL + 1)
1207 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1208 insert_pclel, extract_pclel },
1210 /* Fake operand to handle the T flag. */
1211 #define BRAKET (PCL_EL + 1)
1212 #define BRAKETdup (PCL_EL + 1)
1213 { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 },
1215 /* Fake operand to handle the T flag. */
1216 #define FKT_T (BRAKET + 1)
1217 { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 },
1218 /* Fake operand to handle the T flag. */
1219 #define FKT_NT (FKT_T + 1)
1220 { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 },
1222 /* UIMM6_20 mask = 00000000000000000000111111000000. */
1223 #define UIMM6_20 (FKT_NT + 1)
1224 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
1226 /* SIMM12_20 mask = 00000000000000000000111111222222. */
1227 #define SIMM12_20 (UIMM6_20 + 1)
1228 {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
1230 /* SIMM3_5_S mask = 0000011100000000. */
1231 #define SIMM3_5_S (SIMM12_20 + 1)
1232 {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
1233 insert_simm3s, extract_simm3s},
1235 /* UIMM7_A32_11_S mask = 0000000000011111. */
1236 #define UIMM7_A32_11_S (SIMM3_5_S + 1)
1237 {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1238 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
1239 extract_uimm7_a32_11_s},
1241 /* UIMM7_9_S mask = 0000000001111111. */
1242 #define UIMM7_9_S (UIMM7_A32_11_S + 1)
1243 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
1245 /* UIMM3_13_S mask = 0000000000000111. */
1246 #define UIMM3_13_S (UIMM7_9_S + 1)
1247 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
1249 /* SIMM11_A32_7_S mask = 0000000111111111. */
1250 #define SIMM11_A32_7_S (UIMM3_13_S + 1)
1251 {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1252 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
1254 /* UIMM6_13_S mask = 0000000002220111. */
1255 #define UIMM6_13_S (SIMM11_A32_7_S + 1)
1256 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s},
1257 /* UIMM5_11_S mask = 0000000000011111. */
1258 #define UIMM5_11_S (UIMM6_13_S + 1)
1259 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s,
1260 extract_uimm5_11_s},
1262 /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
1263 #define SIMM9_A16_8 (UIMM5_11_S + 1)
1264 {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1265 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8,
1266 extract_simm9_a16_8},
1268 /* UIMM6_8 mask = 00000000000000000000111111000000. */
1269 #define UIMM6_8 (SIMM9_A16_8 + 1)
1270 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8},
1272 /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
1273 #define SIMM21_A16_5 (UIMM6_8 + 1)
1274 {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
1275 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE,
1276 insert_simm21_a16_5, extract_simm21_a16_5},
1278 /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
1279 #define SIMM25_A16_5 (SIMM21_A16_5 + 1)
1280 {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED
1281 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
1282 insert_simm25_a16_5, extract_simm25_a16_5},
1284 /* SIMM10_A16_7_S mask = 0000000111111111. */
1285 #define SIMM10_A16_7_S (SIMM25_A16_5 + 1)
1286 {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1287 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s,
1288 extract_simm10_a16_7_s},
1290 #define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1)
1291 {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1292 | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s},
1294 /* SIMM7_A16_10_S mask = 0000000000111111. */
1295 #define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1)
1296 {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1297 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s,
1298 extract_simm7_a16_10_s},
1300 /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */
1301 #define SIMM21_A32_5 (SIMM7_A16_10_S + 1)
1302 {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1303 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5,
1304 extract_simm21_a32_5},
1306 /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */
1307 #define SIMM25_A32_5 (SIMM21_A32_5 + 1)
1308 {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1309 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5,
1310 extract_simm25_a32_5},
1312 /* SIMM13_A32_5_S mask = 0000011111111111. */
1313 #define SIMM13_A32_5_S (SIMM25_A32_5 + 1)
1314 {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1315 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s,
1316 extract_simm13_a32_5_s},
1318 /* SIMM8_A16_9_S mask = 0000000001111111. */
1319 #define SIMM8_A16_9_S (SIMM13_A32_5_S + 1)
1320 {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1321 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
1322 extract_simm8_a16_9_s},
1324 /* UIMM3_23 mask = 00000000000000000000000111000000. */
1325 #define UIMM3_23 (SIMM8_A16_9_S + 1)
1326 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23},
1328 /* UIMM10_6_S mask = 0000001111111111. */
1329 #define UIMM10_6_S (UIMM3_23 + 1)
1330 {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s},
1332 /* UIMM6_11_S mask = 0000002200011110. */
1333 #define UIMM6_11_S (UIMM10_6_S + 1)
1334 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s},
1336 /* SIMM9_8 mask = 00000000111111112000000000000000. */
1337 #define SIMM9_8 (UIMM6_11_S + 1)
1338 {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
1339 insert_simm9_8, extract_simm9_8},
1341 /* UIMM10_A32_8_S mask = 0000000011111111. */
1342 #define UIMM10_A32_8_S (SIMM9_8 + 1)
1343 {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1344 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
1345 extract_uimm10_a32_8_s},
1347 /* SIMM9_7_S mask = 0000000111111111. */
1348 #define SIMM9_7_S (UIMM10_A32_8_S + 1)
1349 {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s,
1352 /* UIMM6_A16_11_S mask = 0000000000011111. */
1353 #define UIMM6_A16_11_S (SIMM9_7_S + 1)
1354 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1355 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s,
1356 extract_uimm6_a16_11_s},
1358 /* UIMM5_A32_11_S mask = 0000020000011000. */
1359 #define UIMM5_A32_11_S (UIMM6_A16_11_S + 1)
1360 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1361 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s,
1362 extract_uimm5_a32_11_s},
1364 /* SIMM11_A32_13_S mask = 0000022222200111. */
1365 #define SIMM11_A32_13_S (UIMM5_A32_11_S + 1)
1366 {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1367 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s},
1369 /* UIMM7_13_S mask = 0000000022220111. */
1370 #define UIMM7_13_S (SIMM11_A32_13_S + 1)
1371 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s},
1373 /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */
1374 #define UIMM6_A16_21 (UIMM7_13_S + 1)
1375 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1376 | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21},
1378 /* UIMM7_11_S mask = 0000022200011110. */
1379 #define UIMM7_11_S (UIMM6_A16_21 + 1)
1380 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s},
1382 /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */
1383 #define UIMM7_A16_20 (UIMM7_11_S + 1)
1384 {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1385 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20,
1386 extract_uimm7_a16_20},
1388 /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
1389 #define SIMM13_A16_20 (UIMM7_A16_20 + 1)
1390 {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1391 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20,
1392 extract_simm13_a16_20},
1394 /* UIMM8_8_S mask = 0000000011111111. */
1395 #define UIMM8_8_S (SIMM13_A16_20 + 1)
1396 {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
1398 /* W6 mask = 00000000000000000000111111000000. */
1399 #define W6 (UIMM8_8_S + 1)
1400 {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
1402 /* UIMM6_5_S mask = 0000011111100000. */
1403 #define UIMM6_5_S (W6 + 1)
1404 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
1406 /* ARC NPS400 Support: See comment near head of file. */
1407 #define NPS_R_DST_3B (UIMM6_5_S + 1)
1408 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
1410 #define NPS_R_SRC1_3B (NPS_R_DST_3B + 1)
1411 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
1413 #define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1)
1414 { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_src2, extract_nps_3bit_src2 },
1416 #define NPS_R_DST (NPS_R_SRC2_3B + 1)
1417 { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL },
1419 #define NPS_R_SRC1 (NPS_R_DST + 1)
1420 { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
1422 #define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1)
1423 { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
1425 #define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
1426 { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
1428 #define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
1429 { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size, extract_nps_bitop_size },
1431 #define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1)
1432 { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size },
1434 #define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1)
1435 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size_2b, extract_nps_bitop_size_2b },
1437 #define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1)
1438 { 8, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 },
1440 #define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1)
1441 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1443 #define NPS_RFLT_UIMM6 (NPS_UIMM16 + 1)
1444 { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 },
1447 const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
1449 const unsigned arc_Toperand = FKT_T;
1450 const unsigned arc_NToperand = FKT_NT;
1452 /* The opcode table.
1454 The format of the opcode table is:
1456 NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }. */
1457 const struct arc_opcode arc_opcodes[] =
1459 #include "arc-tbl.h"
1460 #include "arc-nps400-tbl.h"
1461 #include "arc-ext-tbl.h"
1464 const unsigned arc_num_opcodes = ARRAY_SIZE (arc_opcodes);
1466 /* List with special cases instructions and the applicable flags. */
1467 const struct arc_flag_special arc_flag_special_cases[] =
1469 { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1470 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1471 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1472 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1473 { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1474 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1475 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1476 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1477 { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1478 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1479 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1480 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1481 { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1482 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1483 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1484 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1485 { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1486 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1487 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1488 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1489 { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1490 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1491 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1492 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1493 { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1494 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1495 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1496 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1497 { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } },
1498 { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } }
1501 const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
1504 const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
1506 { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
1507 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1508 { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
1509 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1510 { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
1511 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1512 { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
1513 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1515 /* Next two entries will cover the undefined behavior ldb/stb with
1517 { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
1518 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
1519 { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
1520 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
1522 { "sda", "ld", { F_ASFAKE, F_NULL },
1523 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
1524 { "sda", "st", { F_ASFAKE, F_NULL },
1525 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
1526 { "sda", "ldd", { F_ASFAKE, F_NULL },
1527 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
1528 { "sda", "std", { F_ASFAKE, F_NULL },
1529 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
1531 /* Short instructions. */
1532 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
1533 { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
1534 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
1535 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
1537 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
1538 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
1540 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
1541 BFD_RELOC_ARC_S25H_PCREL_PLT },
1542 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
1543 BFD_RELOC_ARC_S21H_PCREL_PLT },
1544 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
1545 BFD_RELOC_ARC_S25W_PCREL_PLT },
1546 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
1547 BFD_RELOC_ARC_S21W_PCREL_PLT },
1549 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
1552 const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
1554 const struct arc_pseudo_insn arc_pseudo_insns[] =
1556 { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
1557 { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
1558 { BRAKETdup, 1, 0, 4} } },
1559 { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
1560 { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
1561 { BRAKETdup, 1, 0, 4} } },
1563 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1564 { SIMM9_A16_8, 0, 0, 2 } } },
1565 { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1566 { SIMM9_A16_8, 0, 0, 2 } } },
1567 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1568 { SIMM9_A16_8, 0, 0, 2 } } },
1569 { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1570 { SIMM9_A16_8, 0, 0, 2 } } },
1571 { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1572 { SIMM9_A16_8, 0, 0, 2 } } },
1574 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1575 { SIMM9_A16_8, 0, 0, 2 } } },
1576 { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1577 { SIMM9_A16_8, 0, 0, 2 } } },
1578 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1579 { SIMM9_A16_8, 0, 0, 2 } } },
1580 { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1581 { SIMM9_A16_8, 0, 0, 2 } } },
1582 { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1583 { SIMM9_A16_8, 0, 0, 2 } } },
1585 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1586 { SIMM9_A16_8, 0, 0, 2 } } },
1587 { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1588 { SIMM9_A16_8, 0, 0, 2 } } },
1589 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1590 { SIMM9_A16_8, 0, 0, 2 } } },
1591 { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1592 { SIMM9_A16_8, 0, 0, 2 } } },
1593 { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1594 { SIMM9_A16_8, 0, 0, 2 } } },
1596 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1597 { SIMM9_A16_8, 0, 0, 2 } } },
1598 { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1599 { SIMM9_A16_8, 0, 0, 2 } } },
1600 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1601 { SIMM9_A16_8, 0, 0, 2 } } },
1602 { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1603 { SIMM9_A16_8, 0, 0, 2 } } },
1604 { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1605 { SIMM9_A16_8, 0, 0, 2 } } },
1608 const unsigned arc_num_pseudo_insn =
1609 sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
1611 const struct arc_aux_reg arc_aux_regs[] =
1614 #define DEF(ADDR, SUBCLASS, NAME) \
1615 { ADDR, SUBCLASS, #NAME, sizeof (#NAME)-1 },
1617 #include "arc-regs.h"
1622 const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);
1624 /* NOTE: The order of this array MUST be consistent with 'enum
1625 arc_rlx_types' located in tc-arc.h! */
1626 const struct arc_opcode arc_relax_opcodes[] =
1628 { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } },
1630 /* bl_s s13 11111sssssssssss. */
1631 { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1632 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1633 { SIMM13_A32_5_S }, { 0 }},
1635 /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
1636 { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1637 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1638 { SIMM25_A32_5 }, { C_D }},
1640 /* b_s s10 1111000sssssssss. */
1641 { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1642 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1643 { SIMM10_A16_7_S }, { 0 }},
1645 /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
1646 { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1647 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1648 { SIMM25_A16_5 }, { C_D }},
1650 /* add_s c,b,u3 01101bbbccc00uuu. Wants UIMM3_13_S_PCREL. */
1651 { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1652 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1653 { RC_S, RB_S, UIMM3_13_S }, { 0 }},
1655 /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. Wants
1657 { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1658 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1659 { RA, RB, UIMM6_20 }, { C_F }},
1661 /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
1662 { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1663 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1664 { RA, RB, LIMM }, { C_F }},
1666 /* ld_s c,b,u7 10000bbbcccuuuuu. Wants UIMM7_A32_11_S_PCREL. */
1667 { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1668 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1669 { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
1671 /* ld<.di><.aa><.x><zz> a,b,s9
1672 00010bbbssssssssSBBBDaaZZXAAAAAA. Wants SIMM9_8_PCREL. */
1673 { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1674 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1675 { RA, BRAKET, RB, SIMM9_8, BRAKETdup },
1676 { C_ZZ23, C_DI20, C_AA21, C_X25 }},
1678 /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */
1679 { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1680 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1681 { RA, BRAKET, RB, LIMM, BRAKETdup },
1682 { C_ZZ13, C_DI16, C_AA8, C_X15 }},
1684 /* mov_s b,u8 11011bbbuuuuuuuu. Wants UIMM8_8_S_PCREL. */
1685 { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1686 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1687 { RB_S, UIMM8_8_S }, { 0 }},
1689 /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. Wants
1691 { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1692 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1693 { RB, SIMM12_20 }, { C_F }},
1695 /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
1696 { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1697 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1698 { RB, LIMM }, { C_F }},
1700 /* sub_s c,b,u3 01101bbbccc01uuu. UIMM3_13_S_PCREL. */
1701 { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1702 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1703 { RC_S, RB_S, UIMM3_13_S }, { 0 }},
1705 /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA.
1707 { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1708 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1709 { RA, RB, UIMM6_20 }, { C_F }},
1711 /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
1712 { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1713 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1714 { RA, RB, LIMM }, { C_F }},
1716 /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA.
1718 { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
1719 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }},
1721 /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
1722 { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
1723 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
1725 /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ.
1727 { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1728 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1729 { RB, UIMM6_20 }, { C_F, C_CC }},
1731 /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
1732 { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1733 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1734 { RB, LIMM }, { C_F, C_CC }},
1736 /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ.
1738 { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1739 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1740 { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
1742 /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
1743 { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1744 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1745 { RB, RBdup, LIMM }, { C_F, C_CC }}
1748 const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);