1 /* Opcode table for the ARC.
2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
3 Contributed by Doug Evans (dje@cygnus.com).
5 This file is part of libopcodes.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software Foundation,
19 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
25 #include "opcode/arc.h"
28 enum operand {OP_NONE,OP_REG,OP_SHIMM,OP_LIMM};
32 enum operand ls_operand[OPERANDS];
34 struct arc_opcode *arc_ext_opcodes;
35 struct arc_ext_operand_value *arc_ext_operands;
42 /* Given a format letter, yields the index into `arc_operands'.
43 eg: arc_operand_map['a'] = REGA. */
44 unsigned char arc_operand_map[256];
46 /* Nonzero if we've seen an 'f' suffix (in certain insns). */
49 /* Nonzero if we've finished processing the 'f' suffix. */
50 static int flagshimm_handled_p;
52 /* Nonzero if we've seen a 'a' suffix (address writeback). */
55 /* Nonzero if we've seen a 'q' suffix (condition code). */
58 /* Nonzero if we've inserted a nullify condition. */
61 /* The value of the a nullify condition we inserted. */
64 /* Nonzero if we've inserted jumpflags. */
65 static int jumpflags_p;
67 /* Nonzero if we've inserted a shimm. */
70 /* The value of the shimm we inserted (each insn only gets one but it can
71 appear multiple times). */
74 /* Nonzero if we've inserted a limm (during assembly) or seen a limm
75 (during disassembly). */
78 /* The value of the limm we inserted. Each insn only gets one but it can
79 appear multiple times. */
82 #define INSERT_FN(fn) \
83 static arc_insn fn (arc_insn, const struct arc_operand *, \
84 int, const struct arc_operand_value *, long, \
87 #define EXTRACT_FN(fn) \
88 static long fn (arc_insn *, const struct arc_operand *, \
89 int, const struct arc_operand_value **, int *)
91 INSERT_FN (insert_reg);
92 INSERT_FN (insert_shimmfinish);
93 INSERT_FN (insert_limmfinish);
94 INSERT_FN (insert_offset);
95 INSERT_FN (insert_base);
96 INSERT_FN (insert_st_syntax);
97 INSERT_FN (insert_ld_syntax);
98 INSERT_FN (insert_addr_wb);
99 INSERT_FN (insert_flag);
100 INSERT_FN (insert_nullify);
101 INSERT_FN (insert_flagfinish);
102 INSERT_FN (insert_cond);
103 INSERT_FN (insert_forcelimm);
104 INSERT_FN (insert_reladdr);
105 INSERT_FN (insert_absaddr);
106 INSERT_FN (insert_jumpflags);
107 INSERT_FN (insert_unopmacro);
109 EXTRACT_FN (extract_reg);
110 EXTRACT_FN (extract_ld_offset);
111 EXTRACT_FN (extract_ld_syntax);
112 EXTRACT_FN (extract_st_offset);
113 EXTRACT_FN (extract_st_syntax);
114 EXTRACT_FN (extract_flag);
115 EXTRACT_FN (extract_cond);
116 EXTRACT_FN (extract_reladdr);
117 EXTRACT_FN (extract_jumpflags);
118 EXTRACT_FN (extract_unopmacro);
120 /* Various types of ARC operands, including insn suffixes. */
122 /* Insn format values:
124 'a' REGA register A field
125 'b' REGB register B field
126 'c' REGC register C field
127 'S' SHIMMFINISH finish inserting a shimm value
128 'L' LIMMFINISH finish inserting a limm value
129 'o' OFFSET offset in st insns
130 'O' OFFSET offset in ld insns
131 '0' SYNTAX_ST_NE enforce store insn syntax, no errors
132 '1' SYNTAX_LD_NE enforce load insn syntax, no errors
133 '2' SYNTAX_ST enforce store insn syntax, errors, last pattern only
134 '3' SYNTAX_LD enforce load insn syntax, errors, last pattern only
135 's' BASE base in st insn
137 'F' FLAGFINISH finish inserting the F flag
138 'G' FLAGINSN insert F flag in "flag" insn
139 'n' DELAY N field (nullify field)
140 'q' COND condition code field
141 'Q' FORCELIMM set `cond_p' to 1 to ensure a constant is a limm
142 'B' BRANCH branch address (22 bit pc relative)
143 'J' JUMP jump address (26 bit absolute)
144 'j' JUMPFLAGS optional high order bits of 'J'
145 'z' SIZE1 size field in ld a,[b,c]
146 'Z' SIZE10 size field in ld a,[b,shimm]
147 'y' SIZE22 size field in st c,[b,shimm]
148 'x' SIGN0 sign extend field ld a,[b,c]
149 'X' SIGN9 sign extend field ld a,[b,shimm]
150 'w' ADDRESS3 write-back field in ld a,[b,c]
151 'W' ADDRESS12 write-back field in ld a,[b,shimm]
152 'v' ADDRESS24 write-back field in st c,[b,shimm]
153 'e' CACHEBYPASS5 cache bypass in ld a,[b,c]
154 'E' CACHEBYPASS14 cache bypass in ld a,[b,shimm]
155 'D' CACHEBYPASS26 cache bypass in st c,[b,shimm]
156 'U' UNOPMACRO fake operand to copy REGB to REGC for unop macros
158 The following modifiers may appear between the % and char (eg: %.f):
160 '.' MODDOT '.' prefix must be present
161 'r' REG generic register value, for register table
162 'A' AUXREG auxiliary register in lr a,[b], sr c,[b]
166 CHAR BITS SHIFT FLAGS INSERT_FN EXTRACT_FN */
168 const struct arc_operand arc_operands[] =
170 /* Place holder (??? not sure if needed). */
172 { 0, 0, 0, 0, 0, 0 },
174 /* Register A or shimm/limm indicator. */
175 #define REGA (UNUSED + 1)
176 { 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg },
178 /* Register B or shimm/limm indicator. */
179 #define REGB (REGA + 1)
180 { 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg },
182 /* Register C or shimm/limm indicator. */
183 #define REGC (REGB + 1)
184 { 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg },
186 /* Fake operand used to insert shimm value into most instructions. */
187 #define SHIMMFINISH (REGC + 1)
188 { 'S', 9, 0, ARC_OPERAND_SIGNED + ARC_OPERAND_FAKE, insert_shimmfinish, 0 },
190 /* Fake operand used to insert limm value into most instructions. */
191 #define LIMMFINISH (SHIMMFINISH + 1)
192 { 'L', 32, 32, ARC_OPERAND_ADDRESS + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_limmfinish, 0 },
194 /* Shimm operand when there is no reg indicator (st). */
195 #define ST_OFFSET (LIMMFINISH + 1)
196 { 'o', 9, 0, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_STORE, insert_offset, extract_st_offset },
198 /* Shimm operand when there is no reg indicator (ld). */
199 #define LD_OFFSET (ST_OFFSET + 1)
200 { 'O', 9, 0,ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_LOAD, insert_offset, extract_ld_offset },
202 /* Operand for base. */
203 #define BASE (LD_OFFSET + 1)
204 { 's', 6, ARC_SHIFT_REGB, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, insert_base, extract_reg},
206 /* 0 enforce syntax for st insns. */
207 #define SYNTAX_ST_NE (BASE + 1)
208 { '0', 9, 0, ARC_OPERAND_FAKE, insert_st_syntax, extract_st_syntax },
210 /* 1 enforce syntax for ld insns. */
211 #define SYNTAX_LD_NE (SYNTAX_ST_NE + 1)
212 { '1', 9, 0, ARC_OPERAND_FAKE, insert_ld_syntax, extract_ld_syntax },
214 /* 0 enforce syntax for st insns. */
215 #define SYNTAX_ST (SYNTAX_LD_NE + 1)
216 { '2', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_st_syntax, extract_st_syntax },
218 /* 0 enforce syntax for ld insns. */
219 #define SYNTAX_LD (SYNTAX_ST + 1)
220 { '3', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_ld_syntax, extract_ld_syntax },
222 /* Flag update bit (insertion is defered until we know how). */
223 #define FLAG (SYNTAX_LD + 1)
224 { 'f', 1, 8, ARC_OPERAND_SUFFIX, insert_flag, extract_flag },
226 /* Fake utility operand to finish 'f' suffix handling. */
227 #define FLAGFINISH (FLAG + 1)
228 { 'F', 1, 8, ARC_OPERAND_FAKE, insert_flagfinish, 0 },
230 /* Fake utility operand to set the 'f' flag for the "flag" insn. */
231 #define FLAGINSN (FLAGFINISH + 1)
232 { 'G', 1, 8, ARC_OPERAND_FAKE, insert_flag, 0 },
234 /* Branch delay types. */
235 #define DELAY (FLAGINSN + 1)
236 { 'n', 2, 5, ARC_OPERAND_SUFFIX , insert_nullify, 0 },
239 #define COND (DELAY + 1)
240 { 'q', 5, 0, ARC_OPERAND_SUFFIX, insert_cond, extract_cond },
242 /* Set `cond_p' to 1 to ensure a constant is treated as a limm. */
243 #define FORCELIMM (COND + 1)
244 { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm, 0 },
246 /* Branch address; b, bl, and lp insns. */
247 #define BRANCH (FORCELIMM + 1)
248 { 'B', 20, 7, (ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED) | ARC_OPERAND_ERROR, insert_reladdr, extract_reladdr },
250 /* Jump address; j insn (this is basically the same as 'L' except that the
251 value is right shifted by 2). */
252 #define JUMP (BRANCH + 1)
253 { 'J', 24, 32, ARC_OPERAND_ERROR | (ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE), insert_absaddr, 0 },
255 /* Jump flags; j{,l} insn value or'ed into 'J' addr for flag values. */
256 #define JUMPFLAGS (JUMP + 1)
257 { 'j', 6, 26, ARC_OPERAND_JUMPFLAGS | ARC_OPERAND_ERROR, insert_jumpflags, extract_jumpflags },
259 /* Size field, stored in bit 1,2. */
260 #define SIZE1 (JUMPFLAGS + 1)
261 { 'z', 2, 1, ARC_OPERAND_SUFFIX, 0, 0 },
263 /* Size field, stored in bit 10,11. */
264 #define SIZE10 (SIZE1 + 1)
265 { 'Z', 2, 10, ARC_OPERAND_SUFFIX, 0, 0 },
267 /* Size field, stored in bit 22,23. */
268 #define SIZE22 (SIZE10 + 1)
269 { 'y', 2, 22, ARC_OPERAND_SUFFIX, 0, 0 },
271 /* Sign extend field, stored in bit 0. */
272 #define SIGN0 (SIZE22 + 1)
273 { 'x', 1, 0, ARC_OPERAND_SUFFIX, 0, 0 },
275 /* Sign extend field, stored in bit 9. */
276 #define SIGN9 (SIGN0 + 1)
277 { 'X', 1, 9, ARC_OPERAND_SUFFIX, 0, 0 },
279 /* Address write back, stored in bit 3. */
280 #define ADDRESS3 (SIGN9 + 1)
281 { 'w', 1, 3, ARC_OPERAND_SUFFIX, insert_addr_wb, 0},
283 /* Address write back, stored in bit 12. */
284 #define ADDRESS12 (ADDRESS3 + 1)
285 { 'W', 1, 12, ARC_OPERAND_SUFFIX, insert_addr_wb, 0},
287 /* Address write back, stored in bit 24. */
288 #define ADDRESS24 (ADDRESS12 + 1)
289 { 'v', 1, 24, ARC_OPERAND_SUFFIX, insert_addr_wb, 0},
291 /* Cache bypass, stored in bit 5. */
292 #define CACHEBYPASS5 (ADDRESS24 + 1)
293 { 'e', 1, 5, ARC_OPERAND_SUFFIX, 0, 0 },
295 /* Cache bypass, stored in bit 14. */
296 #define CACHEBYPASS14 (CACHEBYPASS5 + 1)
297 { 'E', 1, 14, ARC_OPERAND_SUFFIX, 0, 0 },
299 /* Cache bypass, stored in bit 26. */
300 #define CACHEBYPASS26 (CACHEBYPASS14 + 1)
301 { 'D', 1, 26, ARC_OPERAND_SUFFIX, 0, 0 },
303 /* Unop macro, used to copy REGB to REGC. */
304 #define UNOPMACRO (CACHEBYPASS26 + 1)
305 { 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro },
307 /* '.' modifier ('.' required). */
308 #define MODDOT (UNOPMACRO + 1)
309 { '.', 1, 0, ARC_MOD_DOT, 0, 0 },
311 /* Dummy 'r' modifier for the register table.
312 It's called a "dummy" because there's no point in inserting an 'r' into all
313 the %a/%b/%c occurrences in the insn table. */
314 #define REG (MODDOT + 1)
315 { 'r', 6, 0, ARC_MOD_REG, 0, 0 },
317 /* Known auxiliary register modifier (stored in shimm field). */
318 #define AUXREG (REG + 1)
319 { 'A', 9, 0, ARC_MOD_AUXREG, 0, 0 },
321 /* End of list place holder. */
325 /* Insert a value into a register field.
326 If REG is NULL, then this is actually a constant.
328 We must also handle auxiliary registers for lr/sr insns. */
331 insert_reg (arc_insn insn,
332 const struct arc_operand *operand,
334 const struct arc_operand_value *reg,
338 static char buf[100];
339 enum operand op_type = OP_NONE;
343 /* We have a constant that also requires a value stored in a register
344 field. Handle these by updating the register field and saving the
345 value for later handling by either %S (shimm) or %L (limm). */
347 /* Try to use a shimm value before a limm one. */
348 if (ARC_SHIMM_CONST_P (value)
349 /* If we've seen a conditional suffix we have to use a limm. */
351 /* If we already have a shimm value that is different than ours
352 we have to use a limm. */
353 && (!shimm_p || shimm == value))
358 /* Forget about shimm as dest mlm. */
360 if ('a' != operand->fmt)
364 flagshimm_handled_p = 1;
365 marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM;
369 /* Don't request flag setting on shimm as dest. */
370 marker = ARC_REG_SHIMM;
372 insn |= marker << operand->shift;
373 /* insn |= value & 511; - done later. */
375 /* We have to use a limm. If we've already seen one they must match. */
376 else if (!limm_p || limm == value)
381 insn |= ARC_REG_LIMM << operand->shift;
382 /* The constant is stored later. */
385 *errmsg = _("unable to fit different valued constants into instruction");
389 /* We have to handle both normal and auxiliary registers. */
391 if (reg->type == AUXREG)
393 if (!(mods & ARC_MOD_AUXREG))
394 *errmsg = _("auxiliary register not allowed here");
397 if ((insn & I(-1)) == I(2)) /* Check for use validity. */
399 if (reg->flags & ARC_REGISTER_READONLY)
400 *errmsg = _("attempt to set readonly register");
404 if (reg->flags & ARC_REGISTER_WRITEONLY)
405 *errmsg = _("attempt to read writeonly register");
407 insn |= ARC_REG_SHIMM << operand->shift;
408 insn |= reg->value << arc_operands[reg->type].shift;
413 /* check for use validity. */
414 if ('a' == operand->fmt || ((insn & I(-1)) < I(2)))
416 if (reg->flags & ARC_REGISTER_READONLY)
417 *errmsg = _("attempt to set readonly register");
419 if ('a' != operand->fmt)
421 if (reg->flags & ARC_REGISTER_WRITEONLY)
422 *errmsg = _("attempt to read writeonly register");
424 /* We should never get an invalid register number here. */
425 if ((unsigned int) reg->value > 60)
427 sprintf (buf, _("invalid register number `%d'"), reg->value);
430 insn |= reg->value << operand->shift;
435 switch (operand->fmt)
438 ls_operand[LS_DEST] = op_type;
441 ls_operand[LS_BASE] = op_type;
444 if ((insn & I(-1)) == I(2))
445 ls_operand[LS_VALUE] = op_type;
447 ls_operand[LS_OFFSET] = op_type;
450 ls_operand[LS_OFFSET] = op_type;
457 /* Called when we see an 'f' flag. */
460 insert_flag (arc_insn insn,
461 const struct arc_operand *operand ATTRIBUTE_UNUSED,
462 int mods ATTRIBUTE_UNUSED,
463 const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
464 long value ATTRIBUTE_UNUSED,
465 const char **errmsg ATTRIBUTE_UNUSED)
467 /* We can't store anything in the insn until we've parsed the registers.
468 Just record the fact that we've got this flag. `insert_reg' will use it
469 to store the correct value (ARC_REG_SHIMM_UPDATE or bit 0x100). */
474 /* Called when we see an nullify condition. */
477 insert_nullify (arc_insn insn,
478 const struct arc_operand *operand,
479 int mods ATTRIBUTE_UNUSED,
480 const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
482 const char **errmsg ATTRIBUTE_UNUSED)
485 insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
490 /* Called after completely building an insn to ensure the 'f' flag gets set
491 properly. This is needed because we don't know how to set this flag until
492 we've parsed the registers. */
495 insert_flagfinish (arc_insn insn,
496 const struct arc_operand *operand,
497 int mods ATTRIBUTE_UNUSED,
498 const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
499 long value ATTRIBUTE_UNUSED,
500 const char **errmsg ATTRIBUTE_UNUSED)
502 if (flag_p && !flagshimm_handled_p)
506 flagshimm_handled_p = 1;
507 insn |= (1 << operand->shift);
512 /* Called when we see a conditional flag (eg: .eq). */
515 insert_cond (arc_insn insn,
516 const struct arc_operand *operand,
517 int mods ATTRIBUTE_UNUSED,
518 const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
520 const char **errmsg ATTRIBUTE_UNUSED)
523 insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
527 /* Used in the "j" instruction to prevent constants from being interpreted as
528 shimm values (which the jump insn doesn't accept). This can also be used
529 to force the use of limm values in other situations (eg: ld r0,[foo] uses
531 ??? The mechanism is sound. Access to it is a bit klunky right now. */
534 insert_forcelimm (arc_insn insn,
535 const struct arc_operand *operand ATTRIBUTE_UNUSED,
536 int mods ATTRIBUTE_UNUSED,
537 const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
538 long value ATTRIBUTE_UNUSED,
539 const char **errmsg ATTRIBUTE_UNUSED)
546 insert_addr_wb (arc_insn insn,
547 const struct arc_operand *operand,
548 int mods ATTRIBUTE_UNUSED,
549 const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
550 long value ATTRIBUTE_UNUSED,
551 const char **errmsg ATTRIBUTE_UNUSED)
553 addrwb_p = 1 << operand->shift;
558 insert_base (arc_insn insn,
559 const struct arc_operand *operand,
561 const struct arc_operand_value *reg,
568 myinsn = insert_reg (0, operand,mods, reg, value, errmsg) >> operand->shift;
570 ls_operand[LS_BASE] = OP_REG;
572 else if (ARC_SHIMM_CONST_P (value) && !cond_p)
574 if (shimm_p && value != shimm)
576 /* Convert the previous shimm operand to a limm. */
579 insn &= ~C(-1); /* We know where the value is in insn. */
580 insn |= C(ARC_REG_LIMM);
581 ls_operand[LS_VALUE] = OP_LIMM;
583 insn |= ARC_REG_SHIMM << operand->shift;
586 ls_operand[LS_BASE] = OP_SHIMM;
587 ls_operand[LS_OFFSET] = OP_SHIMM;
591 if (limm_p && value != limm)
593 *errmsg = _("too many long constants");
598 insn |= B(ARC_REG_LIMM);
599 ls_operand[LS_BASE] = OP_LIMM;
605 /* Used in ld/st insns to handle the offset field. We don't try to
606 match operand syntax here. we catch bad combinations later. */
609 insert_offset (arc_insn insn,
610 const struct arc_operand *operand,
612 const struct arc_operand_value *reg,
621 myinsn = insert_reg (0,operand,mods,reg,value,errmsg) >> operand->shift;
622 ls_operand[LS_OFFSET] = OP_REG;
623 if (operand->flags & ARC_OPERAND_LOAD) /* Not if store, catch it later. */
624 if ((insn & I(-1)) != I(1)) /* Not if opcode == 1, catch it later. */
629 /* This is *way* more general than necessary, but maybe some day it'll
631 if (operand->flags & ARC_OPERAND_SIGNED)
633 minval = -(1 << (operand->bits - 1));
634 maxval = (1 << (operand->bits - 1)) - 1;
639 maxval = (1 << operand->bits) - 1;
641 if ((cond_p && !limm_p) || (value < minval || value > maxval))
643 if (limm_p && value != limm)
644 *errmsg = _("too many long constants");
650 if (operand->flags & ARC_OPERAND_STORE)
651 insn |= B(ARC_REG_LIMM);
652 if (operand->flags & ARC_OPERAND_LOAD)
653 insn |= C(ARC_REG_LIMM);
654 ls_operand[LS_OFFSET] = OP_LIMM;
659 if ((value < minval || value > maxval))
660 *errmsg = "need too many limms";
661 else if (shimm_p && value != shimm)
663 /* Check for bad operand combinations
664 before we lose info about them. */
665 if ((insn & I(-1)) == I(1))
667 *errmsg = _("too many shimms in load");
670 if (limm_p && operand->flags & ARC_OPERAND_LOAD)
672 *errmsg = _("too many long constants");
675 /* Convert what we thought was a shimm to a limm. */
678 if (ls_operand[LS_VALUE] == OP_SHIMM
679 && operand->flags & ARC_OPERAND_STORE)
682 insn |= C(ARC_REG_LIMM);
683 ls_operand[LS_VALUE] = OP_LIMM;
685 if (ls_operand[LS_BASE] == OP_SHIMM
686 && operand->flags & ARC_OPERAND_STORE)
689 insn |= B(ARC_REG_LIMM);
690 ls_operand[LS_BASE] = OP_LIMM;
695 ls_operand[LS_OFFSET] = OP_SHIMM;
702 /* Used in st insns to do final disasemble syntax check. */
705 extract_st_syntax (arc_insn *insn,
706 const struct arc_operand *operand ATTRIBUTE_UNUSED,
707 int mods ATTRIBUTE_UNUSED,
708 const struct arc_operand_value **opval ATTRIBUTE_UNUSED,
711 #define ST_SYNTAX(V,B,O) \
712 ((ls_operand[LS_VALUE] == (V) && \
713 ls_operand[LS_BASE] == (B) && \
714 ls_operand[LS_OFFSET] == (O)))
716 if (!((ST_SYNTAX(OP_REG,OP_REG,OP_NONE) && (insn[0] & 511) == 0)
717 || ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE)
718 || (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0)
719 || (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (insn[0] & 511) == 0)
720 || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE)
721 || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_SHIMM)
722 || ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM)
723 || (ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0)
724 || ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
725 || ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
726 || ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM)
727 || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM)
728 || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE)
729 || ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM)))
735 arc_limm_fixup_adjust (arc_insn insn)
739 /* Check for st shimm,[limm]. */
740 if ((insn & (I(-1) | C(-1) | B(-1))) ==
741 (I(2) | C(ARC_REG_SHIMM) | B(ARC_REG_LIMM)))
743 retval = insn & 0x1ff;
744 if (retval & 0x100) /* Sign extend 9 bit offset. */
747 return -retval; /* Negate offset for return. */
750 /* Used in st insns to do final syntax check. */
753 insert_st_syntax (arc_insn insn,
754 const struct arc_operand *operand ATTRIBUTE_UNUSED,
755 int mods ATTRIBUTE_UNUSED,
756 const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
757 long value ATTRIBUTE_UNUSED,
760 if (ST_SYNTAX (OP_SHIMM,OP_REG,OP_NONE) && shimm != 0)
762 /* Change an illegal insn into a legal one, it's easier to
763 do it here than to try to handle it during operand scan. */
768 insn = insn & ~(C(-1) | 511);
769 insn |= ARC_REG_LIMM << ARC_SHIFT_REGC;
770 ls_operand[LS_VALUE] = OP_LIMM;
773 if (ST_SYNTAX (OP_REG, OP_SHIMM, OP_NONE)
774 || ST_SYNTAX (OP_LIMM, OP_SHIMM, OP_NONE))
776 /* Try to salvage this syntax. */
777 if (shimm & 0x1) /* Odd shimms won't work. */
779 if (limm_p) /* Do we have a limm already? */
780 *errmsg = _("impossible store");
786 insn = insn & ~(B(-1) | 511);
787 insn |= B(ARC_REG_LIMM);
788 ls_operand[LS_BASE] = OP_LIMM;
795 ls_operand[LS_OFFSET] = OP_SHIMM;
798 if (ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE))
799 limm += arc_limm_fixup_adjust(insn);
801 if (! (ST_SYNTAX (OP_REG,OP_REG,OP_NONE)
802 || ST_SYNTAX (OP_REG,OP_LIMM,OP_NONE)
803 || ST_SYNTAX (OP_REG,OP_REG,OP_SHIMM)
804 || ST_SYNTAX (OP_REG,OP_SHIMM,OP_SHIMM)
805 || (ST_SYNTAX (OP_SHIMM,OP_SHIMM,OP_NONE) && (shimm == 0))
806 || ST_SYNTAX (OP_SHIMM,OP_LIMM,OP_NONE)
807 || ST_SYNTAX (OP_SHIMM,OP_REG,OP_NONE)
808 || ST_SYNTAX (OP_SHIMM,OP_REG,OP_SHIMM)
809 || ST_SYNTAX (OP_SHIMM,OP_SHIMM,OP_SHIMM)
810 || ST_SYNTAX (OP_LIMM,OP_SHIMM,OP_SHIMM)
811 || ST_SYNTAX (OP_LIMM,OP_REG,OP_NONE)
812 || ST_SYNTAX (OP_LIMM,OP_REG,OP_SHIMM)))
813 *errmsg = _("st operand error");
816 if (ls_operand[LS_BASE] != OP_REG)
817 *errmsg = _("address writeback not allowed");
820 if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm)
821 *errmsg = _("store value must be zero");
825 /* Used in ld insns to do final syntax check. */
828 insert_ld_syntax (arc_insn insn,
829 const struct arc_operand *operand ATTRIBUTE_UNUSED,
830 int mods ATTRIBUTE_UNUSED,
831 const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
832 long value ATTRIBUTE_UNUSED,
835 #define LD_SYNTAX(D, B, O) \
836 ( (ls_operand[LS_DEST] == (D) \
837 && ls_operand[LS_BASE] == (B) \
838 && ls_operand[LS_OFFSET] == (O)))
840 int test = insn & I (-1);
842 if (!(test == I (1)))
844 if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM
845 || ls_operand[LS_OFFSET] == OP_SHIMM))
846 *errmsg = _("invalid load/shimm insn");
848 if (!(LD_SYNTAX(OP_REG,OP_REG,OP_NONE)
849 || LD_SYNTAX(OP_REG,OP_REG,OP_REG)
850 || LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
851 || (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1)))
852 || (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1)))
853 || LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
854 || (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1)))))
855 *errmsg = _("ld operand error");
858 if (ls_operand[LS_BASE] != OP_REG)
859 *errmsg = _("address writeback not allowed");
865 /* Used in ld insns to do final syntax check. */
868 extract_ld_syntax (arc_insn *insn,
869 const struct arc_operand *operand ATTRIBUTE_UNUSED,
870 int mods ATTRIBUTE_UNUSED,
871 const struct arc_operand_value **opval ATTRIBUTE_UNUSED,
874 int test = insn[0] & I(-1);
878 if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM
879 || ls_operand[LS_OFFSET] == OP_SHIMM))
882 if (!( (LD_SYNTAX (OP_REG, OP_REG, OP_NONE) && (test == I(1)))
883 || LD_SYNTAX (OP_REG, OP_REG, OP_REG)
884 || LD_SYNTAX (OP_REG, OP_REG, OP_SHIMM)
885 || (LD_SYNTAX (OP_REG, OP_REG, OP_LIMM) && !(test == I(1)))
886 || (LD_SYNTAX (OP_REG, OP_LIMM, OP_REG) && !(test == I(1)))
887 || (LD_SYNTAX (OP_REG, OP_SHIMM, OP_NONE) && (shimm == 0))
888 || LD_SYNTAX (OP_REG, OP_SHIMM, OP_SHIMM)
889 || (LD_SYNTAX (OP_REG, OP_LIMM, OP_NONE) && (test == I(1)))))
894 /* Called at the end of processing normal insns (eg: add) to insert a shimm
895 value (if present) into the insn. */
898 insert_shimmfinish (arc_insn insn,
899 const struct arc_operand *operand,
900 int mods ATTRIBUTE_UNUSED,
901 const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
902 long value ATTRIBUTE_UNUSED,
903 const char **errmsg ATTRIBUTE_UNUSED)
906 insn |= (shimm & ((1 << operand->bits) - 1)) << operand->shift;
910 /* Called at the end of processing normal insns (eg: add) to insert a limm
911 value (if present) into the insn.
913 Note that this function is only intended to handle instructions (with 4 byte
914 immediate operands). It is not intended to handle data. */
916 /* ??? Actually, there's nothing for us to do as we can't call frag_more, the
917 caller must do that. The extract fns take a pointer to two words. The
918 insert fns could be converted and then we could do something useful, but
919 then the reloc handlers would have to know to work on the second word of
920 a 2 word quantity. That's too much so we don't handle them. */
923 insert_limmfinish (arc_insn insn,
924 const struct arc_operand *operand ATTRIBUTE_UNUSED,
925 int mods ATTRIBUTE_UNUSED,
926 const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
927 long value ATTRIBUTE_UNUSED,
928 const char **errmsg ATTRIBUTE_UNUSED)
934 insert_jumpflags (arc_insn insn,
935 const struct arc_operand *operand,
936 int mods ATTRIBUTE_UNUSED,
937 const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
942 *errmsg = _("jump flags, but no .f seen");
945 *errmsg = _("jump flags, but no limm addr");
947 else if (limm & 0xfc000000)
948 *errmsg = _("flag bits of jump address limm lost");
950 else if (limm & 0x03000000)
951 *errmsg = _("attempt to set HR bits");
953 else if ((value & ((1 << operand->bits) - 1)) != value)
954 *errmsg = _("bad jump flags value");
957 limm = ((limm & ((1 << operand->shift) - 1))
958 | ((value & ((1 << operand->bits) - 1)) << operand->shift));
962 /* Called at the end of unary operand macros to copy the B field to C. */
965 insert_unopmacro (arc_insn insn,
966 const struct arc_operand *operand,
967 int mods ATTRIBUTE_UNUSED,
968 const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
969 long value ATTRIBUTE_UNUSED,
970 const char **errmsg ATTRIBUTE_UNUSED)
972 insn |= ((insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) << operand->shift;
976 /* Insert a relative address for a branch insn (b, bl, or lp). */
979 insert_reladdr (arc_insn insn,
980 const struct arc_operand *operand,
981 int mods ATTRIBUTE_UNUSED,
982 const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
987 *errmsg = _("branch address not on 4 byte boundary");
988 insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift;
992 /* Insert a limm value as a 26 bit address right shifted 2 into the insn.
994 Note that this function is only intended to handle instructions (with 4 byte
995 immediate operands). It is not intended to handle data. */
997 /* ??? Actually, there's little for us to do as we can't call frag_more, the
998 caller must do that. The extract fns take a pointer to two words. The
999 insert fns could be converted and then we could do something useful, but
1000 then the reloc handlers would have to know to work on the second word of
1001 a 2 word quantity. That's too much so we don't handle them.
1003 We do check for correct usage of the nullify suffix, or we
1004 set the default correctly, though. */
1007 insert_absaddr (arc_insn insn,
1008 const struct arc_operand *operand ATTRIBUTE_UNUSED,
1009 int mods ATTRIBUTE_UNUSED,
1010 const struct arc_operand_value *reg ATTRIBUTE_UNUSED,
1011 long value ATTRIBUTE_UNUSED,
1012 const char **errmsg)
1016 /* If it is a jump and link, .jd must be specified. */
1017 if (insn & R (-1, 9, 1))
1020 insn |= 0x02 << 5; /* Default nullify to .jd. */
1022 else if (nullify != 0x02)
1023 *errmsg = _("must specify .jd or no nullify suffix");
1029 /* Extraction functions.
1031 The suffix extraction functions' return value is redundant since it can be
1032 obtained from (*OPVAL)->value. However, the boolean suffixes don't have
1033 a suffix table entry for the "false" case, so values of zero must be
1034 obtained from the return value (*OPVAL == NULL). */
1036 /* Called by the disassembler before printing an instruction. */
1039 arc_opcode_init_extract (void)
1041 arc_opcode_init_insert ();
1044 static const struct arc_operand_value *
1045 lookup_register (int type, long regno)
1047 const struct arc_operand_value *r,*end;
1048 struct arc_ext_operand_value *ext_oper = arc_ext_operands;
1052 if (ext_oper->operand.type == type && ext_oper->operand.value == regno)
1053 return (&ext_oper->operand);
1054 ext_oper = ext_oper->next;
1058 return &arc_reg_names[regno];
1060 /* ??? This is a little slow and can be speeded up. */
1061 for (r = arc_reg_names, end = arc_reg_names + arc_reg_names_count;
1063 if (type == r->type && regno == r->value)
1068 /* As we're extracting registers, keep an eye out for the 'f' indicator
1069 (ARC_REG_SHIMM_UPDATE). If we find a register (not a constant marker,
1070 like ARC_REG_SHIMM), set OPVAL so our caller will know this is a register.
1072 We must also handle auxiliary registers for lr/sr insns. They are just
1073 constants with special names. */
1076 extract_reg (arc_insn *insn,
1077 const struct arc_operand *operand,
1079 const struct arc_operand_value **opval,
1080 int *invalid ATTRIBUTE_UNUSED)
1084 enum operand op_type;
1086 /* Get the register number. */
1087 regno = (*insn >> operand->shift) & ((1 << operand->bits) - 1);
1089 /* Is it a constant marker? */
1090 if (regno == ARC_REG_SHIMM)
1093 /* Always return zero if dest is a shimm mlm. */
1095 if ('a' != operand->fmt)
1097 value = *insn & 511;
1098 if ((operand->flags & ARC_OPERAND_SIGNED)
1101 if (!flagshimm_handled_p)
1103 flagshimm_handled_p = 1;
1108 else if (regno == ARC_REG_SHIMM_UPDATE)
1112 /* Always return zero if dest is a shimm mlm. */
1113 if ('a' != operand->fmt)
1115 value = *insn & 511;
1116 if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256))
1123 flagshimm_handled_p = 1;
1125 else if (regno == ARC_REG_LIMM)
1131 /* If this is a jump instruction (j,jl), show new pc correctly. */
1132 if (0x07 == ((*insn & I(-1)) >> 27))
1133 value = (value & 0xffffff);
1136 /* It's a register, set OPVAL (that's the only way we distinguish registers
1137 from constants here). */
1140 const struct arc_operand_value *reg = lookup_register (REG, regno);
1151 /* If this field takes an auxiliary register, see if it's a known one. */
1152 if ((mods & ARC_MOD_AUXREG)
1153 && ARC_REG_CONSTANT_P (regno))
1155 const struct arc_operand_value *reg = lookup_register (AUXREG, value);
1157 /* This is really a constant, but tell the caller it has a special
1159 if (reg != NULL && opval != NULL)
1163 switch(operand->fmt)
1166 ls_operand[LS_DEST] = op_type;
1169 ls_operand[LS_BASE] = op_type;
1172 if ((insn[0]& I(-1)) == I(2))
1173 ls_operand[LS_VALUE] = op_type;
1175 ls_operand[LS_OFFSET] = op_type;
1178 ls_operand[LS_OFFSET] = op_type;
1185 /* Return the value of the "flag update" field for shimm insns.
1186 This value is actually stored in the register field. */
1189 extract_flag (arc_insn *insn,
1190 const struct arc_operand *operand,
1191 int mods ATTRIBUTE_UNUSED,
1192 const struct arc_operand_value **opval,
1193 int *invalid ATTRIBUTE_UNUSED)
1196 const struct arc_operand_value *val;
1198 if (flagshimm_handled_p)
1201 f = (*insn & (1 << operand->shift)) != 0;
1203 /* There is no text for zero values. */
1207 val = arc_opcode_lookup_suffix (operand, 1);
1208 if (opval != NULL && val != NULL)
1213 /* Extract the condition code (if it exists).
1214 If we've seen a shimm value in this insn (meaning that the insn can't have
1215 a condition code field), then we don't store anything in OPVAL and return
1219 extract_cond (arc_insn *insn,
1220 const struct arc_operand *operand,
1221 int mods ATTRIBUTE_UNUSED,
1222 const struct arc_operand_value **opval,
1223 int *invalid ATTRIBUTE_UNUSED)
1226 const struct arc_operand_value *val;
1228 if (flagshimm_handled_p)
1231 cond = (*insn >> operand->shift) & ((1 << operand->bits) - 1);
1232 val = arc_opcode_lookup_suffix (operand, cond);
1234 /* Ignore NULL values of `val'. Several condition code values are
1235 reserved for extensions. */
1236 if (opval != NULL && val != NULL)
1241 /* Extract a branch address.
1242 We return the value as a real address (not right shifted by 2). */
1245 extract_reladdr (arc_insn *insn,
1246 const struct arc_operand *operand,
1247 int mods ATTRIBUTE_UNUSED,
1248 const struct arc_operand_value **opval ATTRIBUTE_UNUSED,
1249 int *invalid ATTRIBUTE_UNUSED)
1253 addr = (*insn >> operand->shift) & ((1 << operand->bits) - 1);
1254 if ((operand->flags & ARC_OPERAND_SIGNED)
1255 && (addr & (1 << (operand->bits - 1))))
1256 addr -= 1 << operand->bits;
1260 /* Extract the flags bits from a j or jl long immediate. */
1263 extract_jumpflags (arc_insn *insn,
1264 const struct arc_operand *operand,
1265 int mods ATTRIBUTE_UNUSED,
1266 const struct arc_operand_value **opval ATTRIBUTE_UNUSED,
1269 if (!flag_p || !limm_p)
1271 return ((flag_p && limm_p)
1272 ? (insn[1] >> operand->shift) & ((1 << operand->bits) -1): 0);
1275 /* Extract st insn's offset. */
1278 extract_st_offset (arc_insn *insn,
1279 const struct arc_operand *operand,
1280 int mods ATTRIBUTE_UNUSED,
1281 const struct arc_operand_value **opval ATTRIBUTE_UNUSED,
1286 if (ls_operand[LS_VALUE] != OP_SHIMM || ls_operand[LS_BASE] != OP_LIMM)
1288 value = insn[0] & 511;
1289 if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256))
1292 ls_operand[LS_OFFSET] = OP_SHIMM;
1300 /* Extract ld insn's offset. */
1303 extract_ld_offset (arc_insn *insn,
1304 const struct arc_operand *operand,
1306 const struct arc_operand_value **opval,
1309 int test = insn[0] & I(-1);
1314 value = insn[0] & 511;
1315 if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256))
1318 ls_operand[LS_OFFSET] = OP_SHIMM;
1322 /* If it isn't in the insn, it's concealed behind reg 'c'. */
1323 return extract_reg (insn, &arc_operands[arc_operand_map['c']],
1324 mods, opval, invalid);
1327 /* The only thing this does is set the `invalid' flag if B != C.
1328 This is needed because the "mov" macro appears before it's real insn "and"
1329 and we don't want the disassembler to confuse them. */
1332 extract_unopmacro (arc_insn *insn,
1333 const struct arc_operand *operand ATTRIBUTE_UNUSED,
1334 int mods ATTRIBUTE_UNUSED,
1335 const struct arc_operand_value **opval ATTRIBUTE_UNUSED,
1338 /* This misses the case where B == ARC_REG_SHIMM_UPDATE &&
1339 C == ARC_REG_SHIMM (or vice versa). No big deal. Those insns will get
1340 printed as "and"s. */
1341 if (((*insn >> ARC_SHIFT_REGB) & ARC_MASK_REG)
1342 != ((*insn >> ARC_SHIFT_REGC) & ARC_MASK_REG))
1343 if (invalid != NULL)
1348 /* ARC instructions.
1350 Longer versions of insns must appear before shorter ones (if gas sees
1351 "lsr r2,r3,1" when it's parsing "lsr %a,%b" it will think the ",1" is
1352 junk). This isn't necessary for `ld' because of the trailing ']'.
1354 Instructions that are really macros based on other insns must appear
1355 before the real insn so they're chosen when disassembling. Eg: The `mov'
1356 insn is really the `and' insn. */
1358 struct arc_opcode arc_opcodes[] =
1360 /* Base case instruction set (core versions 5-8). */
1362 /* "mov" is really an "and". */
1363 { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12), ARC_MACH_5, 0, 0 },
1364 /* "asl" is really an "add". */
1365 { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 },
1366 /* "lsl" is really an "add". */
1367 { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 },
1368 /* "nop" is really an "xor". */
1369 { "nop", 0x7fffffff, 0x7fffffff, ARC_MACH_5, 0, 0 },
1370 /* "rlc" is really an "adc". */
1371 { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9), ARC_MACH_5, 0, 0 },
1372 { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9), ARC_MACH_5, 0, 0 },
1373 { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8), ARC_MACH_5, 0, 0 },
1374 { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12), ARC_MACH_5, 0, 0 },
1375 { "asr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(1), ARC_MACH_5, 0, 0 },
1376 { "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14), ARC_MACH_5, 0, 0 },
1377 { "b%q%.n %B", I(-1), I(4), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
1378 { "bl%q%.n %B", I(-1), I(5), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
1379 { "extb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(7), ARC_MACH_5, 0, 0 },
1380 { "extw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(8), ARC_MACH_5, 0, 0 },
1381 { "flag%.q %b%G%S%L", I(-1)|A(-1)|C(-1), I(3)|A(ARC_REG_SHIMM_UPDATE)|C(0), ARC_MACH_5, 0, 0 },
1382 { "brk", 0x1ffffe00, 0x1ffffe00, ARC_MACH_7, 0, 0 },
1383 { "sleep", 0x1ffffe01, 0x1ffffe01, ARC_MACH_7, 0, 0 },
1384 { "swi", 0x1ffffe02, 0x1ffffe02, ARC_MACH_8, 0, 0 },
1385 /* %Q: force cond_p=1 -> no shimm values. This insn allows an
1386 optional flags spec. */
1387 { "j%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
1388 { "j%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
1389 /* This insn allows an optional flags spec. */
1390 { "jl%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 },
1391 { "jl%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 },
1392 /* Put opcode 1 ld insns first so shimm gets prefered over limm.
1393 "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */
1394 { "ld%Z%.X%.W%.E %a,[%s]%S%L%1", I(-1)|R(-1,13,1)|R(-1,0,511), I(1)|R(0,13,1)|R(0,0,511), ARC_MACH_5, 0, 0 },
1395 { "ld%z%.x%.w%.e %a,[%s]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 },
1396 { "ld%z%.x%.w%.e %a,[%s,%O]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 },
1397 { "ld%Z%.X%.W%.E %a,[%s,%O]%S%L%3", I(-1)|R(-1,13,1), I(1)|R(0,13,1), ARC_MACH_5, 0, 0 },
1398 { "lp%q%.n %B", I(-1), I(6), ARC_MACH_5, 0, 0 },
1399 { "lr %a,[%Ab]%S%L", I(-1)|C(-1), I(1)|C(0x10), ARC_MACH_5, 0, 0 },
1400 { "lsr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(2), ARC_MACH_5, 0, 0 },
1401 { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13), ARC_MACH_5, 0, 0 },
1402 { "ror%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(3), ARC_MACH_5, 0, 0 },
1403 { "rrc%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(4), ARC_MACH_5, 0, 0 },
1404 { "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11), ARC_MACH_5, 0, 0 },
1405 { "sexb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(5), ARC_MACH_5, 0, 0 },
1406 { "sexw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(6), ARC_MACH_5, 0, 0 },
1407 { "sr %c,[%Ab]%S%L", I(-1)|A(-1), I(2)|A(0x10), ARC_MACH_5, 0, 0 },
1408 /* "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */
1409 { "st%y%.v%.D %c,[%s]%L%S%0", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 },
1410 { "st%y%.v%.D %c,[%s,%o]%S%L%2", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 },
1411 { "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10), ARC_MACH_5, 0, 0 },
1412 { "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15), ARC_MACH_5, 0, 0 }
1415 const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]);
1417 const struct arc_operand_value arc_reg_names[] =
1419 /* Core register set r0-r63. */
1421 /* r0-r28 - general purpose registers. */
1422 { "r0", 0, REG, 0 }, { "r1", 1, REG, 0 }, { "r2", 2, REG, 0 },
1423 { "r3", 3, REG, 0 }, { "r4", 4, REG, 0 }, { "r5", 5, REG, 0 },
1424 { "r6", 6, REG, 0 }, { "r7", 7, REG, 0 }, { "r8", 8, REG, 0 },
1425 { "r9", 9, REG, 0 }, { "r10", 10, REG, 0 }, { "r11", 11, REG, 0 },
1426 { "r12", 12, REG, 0 }, { "r13", 13, REG, 0 }, { "r14", 14, REG, 0 },
1427 { "r15", 15, REG, 0 }, { "r16", 16, REG, 0 }, { "r17", 17, REG, 0 },
1428 { "r18", 18, REG, 0 }, { "r19", 19, REG, 0 }, { "r20", 20, REG, 0 },
1429 { "r21", 21, REG, 0 }, { "r22", 22, REG, 0 }, { "r23", 23, REG, 0 },
1430 { "r24", 24, REG, 0 }, { "r25", 25, REG, 0 }, { "r26", 26, REG, 0 },
1431 { "r27", 27, REG, 0 }, { "r28", 28, REG, 0 },
1432 /* Maskable interrupt link register. */
1433 { "ilink1", 29, REG, 0 },
1434 /* Maskable interrupt link register. */
1435 { "ilink2", 30, REG, 0 },
1436 /* Branch-link register. */
1437 { "blink", 31, REG, 0 },
1439 /* r32-r59 reserved for extensions. */
1440 { "r32", 32, REG, 0 }, { "r33", 33, REG, 0 }, { "r34", 34, REG, 0 },
1441 { "r35", 35, REG, 0 }, { "r36", 36, REG, 0 }, { "r37", 37, REG, 0 },
1442 { "r38", 38, REG, 0 }, { "r39", 39, REG, 0 }, { "r40", 40, REG, 0 },
1443 { "r41", 41, REG, 0 }, { "r42", 42, REG, 0 }, { "r43", 43, REG, 0 },
1444 { "r44", 44, REG, 0 }, { "r45", 45, REG, 0 }, { "r46", 46, REG, 0 },
1445 { "r47", 47, REG, 0 }, { "r48", 48, REG, 0 }, { "r49", 49, REG, 0 },
1446 { "r50", 50, REG, 0 }, { "r51", 51, REG, 0 }, { "r52", 52, REG, 0 },
1447 { "r53", 53, REG, 0 }, { "r54", 54, REG, 0 }, { "r55", 55, REG, 0 },
1448 { "r56", 56, REG, 0 }, { "r57", 57, REG, 0 }, { "r58", 58, REG, 0 },
1449 { "r59", 59, REG, 0 },
1451 /* Loop count register (24 bits). */
1452 { "lp_count", 60, REG, 0 },
1453 /* Short immediate data indicator setting flags. */
1454 { "r61", 61, REG, ARC_REGISTER_READONLY },
1455 /* Long immediate data indicator setting flags. */
1456 { "r62", 62, REG, ARC_REGISTER_READONLY },
1457 /* Short immediate data indicator not setting flags. */
1458 { "r63", 63, REG, ARC_REGISTER_READONLY },
1460 /* Small-data base register. */
1461 { "gp", 26, REG, 0 },
1462 /* Frame pointer. */
1463 { "fp", 27, REG, 0 },
1464 /* Stack pointer. */
1465 { "sp", 28, REG, 0 },
1467 { "r29", 29, REG, 0 },
1468 { "r30", 30, REG, 0 },
1469 { "r31", 31, REG, 0 },
1470 { "r60", 60, REG, 0 },
1472 /* Auxiliary register set. */
1474 /* Auxiliary register address map:
1475 0xffffffff-0xffffff00 (-1..-256) - customer shimm allocation
1476 0xfffffeff-0x80000000 - customer limm allocation
1477 0x7fffffff-0x00000100 - ARC limm allocation
1478 0x000000ff-0x00000000 - ARC shimm allocation */
1480 /* Base case auxiliary registers (shimm address). */
1481 { "status", 0x00, AUXREG, 0 },
1482 { "semaphore", 0x01, AUXREG, 0 },
1483 { "lp_start", 0x02, AUXREG, 0 },
1484 { "lp_end", 0x03, AUXREG, 0 },
1485 { "identity", 0x04, AUXREG, ARC_REGISTER_READONLY },
1486 { "debug", 0x05, AUXREG, 0 },
1489 const int arc_reg_names_count =
1490 sizeof (arc_reg_names) / sizeof (arc_reg_names[0]);
1492 /* The suffix table.
1493 Operands with the same name must be stored together. */
1495 const struct arc_operand_value arc_suffixes[] =
1497 /* Entry 0 is special, default values aren't printed by the disassembler. */
1500 /* Base case condition codes. */
1501 { "al", 0, COND, 0 },
1502 { "ra", 0, COND, 0 },
1503 { "eq", 1, COND, 0 },
1504 { "z", 1, COND, 0 },
1505 { "ne", 2, COND, 0 },
1506 { "nz", 2, COND, 0 },
1507 { "pl", 3, COND, 0 },
1508 { "p", 3, COND, 0 },
1509 { "mi", 4, COND, 0 },
1510 { "n", 4, COND, 0 },
1511 { "cs", 5, COND, 0 },
1512 { "c", 5, COND, 0 },
1513 { "lo", 5, COND, 0 },
1514 { "cc", 6, COND, 0 },
1515 { "nc", 6, COND, 0 },
1516 { "hs", 6, COND, 0 },
1517 { "vs", 7, COND, 0 },
1518 { "v", 7, COND, 0 },
1519 { "vc", 8, COND, 0 },
1520 { "nv", 8, COND, 0 },
1521 { "gt", 9, COND, 0 },
1522 { "ge", 10, COND, 0 },
1523 { "lt", 11, COND, 0 },
1524 { "le", 12, COND, 0 },
1525 { "hi", 13, COND, 0 },
1526 { "ls", 14, COND, 0 },
1527 { "pnz", 15, COND, 0 },
1529 /* Condition codes 16-31 reserved for extensions. */
1531 { "f", 1, FLAG, 0 },
1533 { "nd", ARC_DELAY_NONE, DELAY, 0 },
1534 { "d", ARC_DELAY_NORMAL, DELAY, 0 },
1535 { "jd", ARC_DELAY_JUMP, DELAY, 0 },
1537 { "b", 1, SIZE1, 0 },
1538 { "b", 1, SIZE10, 0 },
1539 { "b", 1, SIZE22, 0 },
1540 { "w", 2, SIZE1, 0 },
1541 { "w", 2, SIZE10, 0 },
1542 { "w", 2, SIZE22, 0 },
1543 { "x", 1, SIGN0, 0 },
1544 { "x", 1, SIGN9, 0 },
1545 { "a", 1, ADDRESS3, 0 },
1546 { "a", 1, ADDRESS12, 0 },
1547 { "a", 1, ADDRESS24, 0 },
1549 { "di", 1, CACHEBYPASS5, 0 },
1550 { "di", 1, CACHEBYPASS14, 0 },
1551 { "di", 1, CACHEBYPASS26, 0 },
1554 const int arc_suffixes_count =
1555 sizeof (arc_suffixes) / sizeof (arc_suffixes[0]);
1557 /* Indexed by first letter of opcode. Points to chain of opcodes with same
1559 static struct arc_opcode *opcode_map[26 + 1];
1561 /* Indexed by insn code. Points to chain of opcodes with same insn code. */
1562 static struct arc_opcode *icode_map[32];
1564 /* Configuration flags. */
1566 /* Various ARC_HAVE_XXX bits. */
1567 static int cpu_type;
1569 /* Translate a bfd_mach_arc_xxx value to a ARC_MACH_XXX value. */
1572 arc_get_opcode_mach (int bfd_mach, int big_p)
1574 static int mach_type_map[] =
1581 return mach_type_map[bfd_mach - bfd_mach_arc_5] | (big_p ? ARC_MACH_BIG : 0);
1584 /* Initialize any tables that need it.
1585 Must be called once at start up (or when first needed).
1587 FLAGS is a set of bits that say what version of the cpu we have,
1588 and in particular at least (one of) ARC_MACH_XXX. */
1591 arc_opcode_init_tables (int flags)
1593 static int init_p = 0;
1597 /* We may be intentionally called more than once (for example gdb will call
1598 us each time the user switches cpu). These tables only need to be init'd
1604 memset (arc_operand_map, 0, sizeof (arc_operand_map));
1605 n = sizeof (arc_operands) / sizeof (arc_operands[0]);
1606 for (i = 0; i < n; ++i)
1607 arc_operand_map[arc_operands[i].fmt] = i;
1609 memset (opcode_map, 0, sizeof (opcode_map));
1610 memset (icode_map, 0, sizeof (icode_map));
1611 /* Scan the table backwards so macros appear at the front. */
1612 for (i = arc_opcodes_count - 1; i >= 0; --i)
1614 int opcode_hash = ARC_HASH_OPCODE (arc_opcodes[i].syntax);
1615 int icode_hash = ARC_HASH_ICODE (arc_opcodes[i].value);
1617 arc_opcodes[i].next_asm = opcode_map[opcode_hash];
1618 opcode_map[opcode_hash] = &arc_opcodes[i];
1620 arc_opcodes[i].next_dis = icode_map[icode_hash];
1621 icode_map[icode_hash] = &arc_opcodes[i];
1628 /* Return non-zero if OPCODE is supported on the specified cpu.
1629 Cpu selection is made when calling `arc_opcode_init_tables'. */
1632 arc_opcode_supported (const struct arc_opcode *opcode)
1634 if (ARC_OPCODE_CPU (opcode->flags) <= cpu_type)
1639 /* Return the first insn in the chain for assembling INSN. */
1641 const struct arc_opcode *
1642 arc_opcode_lookup_asm (const char *insn)
1644 return opcode_map[ARC_HASH_OPCODE (insn)];
1647 /* Return the first insn in the chain for disassembling INSN. */
1649 const struct arc_opcode *
1650 arc_opcode_lookup_dis (unsigned int insn)
1652 return icode_map[ARC_HASH_ICODE (insn)];
1655 /* Called by the assembler before parsing an instruction. */
1658 arc_opcode_init_insert (void)
1662 for(i = 0; i < OPERANDS; i++)
1663 ls_operand[i] = OP_NONE;
1666 flagshimm_handled_p = 0;
1673 nullify = 0; /* The default is important. */
1676 /* Called by the assembler to see if the insn has a limm operand.
1677 Also called by the disassembler to see if the insn contains a limm. */
1680 arc_opcode_limm_p (long *limmp)
1687 /* Utility for the extraction functions to return the index into
1690 const struct arc_operand_value *
1691 arc_opcode_lookup_suffix (const struct arc_operand *type, int value)
1693 const struct arc_operand_value *v,*end;
1694 struct arc_ext_operand_value *ext_oper = arc_ext_operands;
1698 if (type == &arc_operands[ext_oper->operand.type]
1699 && value == ext_oper->operand.value)
1700 return (&ext_oper->operand);
1701 ext_oper = ext_oper->next;
1704 /* ??? This is a little slow and can be speeded up. */
1705 for (v = arc_suffixes, end = arc_suffixes + arc_suffixes_count; v < end; ++v)
1706 if (type == &arc_operands[v->type]
1707 && value == v->value)
1713 arc_insn_is_j (arc_insn insn)
1715 return (insn & (I(-1))) == I(0x7);
1719 arc_insn_not_jl (arc_insn insn)
1721 return ((insn & (I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1)))
1722 != (I(0x7) | R(-1,9,1)));
1726 arc_operand_type (int opertype)
1743 struct arc_operand_value *
1744 get_ext_suffix (char *s)
1746 struct arc_ext_operand_value *suffix = arc_ext_operands;
1750 if ((COND == suffix->operand.type)
1751 && !strcmp(s,suffix->operand.name))
1752 return(&suffix->operand);
1753 suffix = suffix->next;
1759 arc_get_noshortcut_flag (void)
1761 return ARC_REGISTER_NOSHORT_CUT;