1 /* Instruction printing code for the ARC.
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
27 #include "opcode/arc.h"
32 /* Globals variables. */
34 static const char * const regnames[64] =
36 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
37 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
38 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
39 "r24", "r25", "gp", "fp", "sp", "ilink", "r30", "blink",
41 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
42 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
43 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
44 "r56", "r57", "ACCL", "ACCH", "lp_count", "rezerved", "LIMM", "pcl"
50 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
52 # define pr_debug(fmt, args...)
55 #define ARRANGE_ENDIAN(info, buf) \
56 (info->endian == BFD_ENDIAN_LITTLE ? bfd_getm32 (bfd_getl32 (buf)) \
59 #define BITS(word,s,e) (((word) << (sizeof (word) * 8 - 1 - e)) >> \
60 (s + (sizeof (word) * 8 - 1 - e)))
61 #define OPCODE(word) (BITS ((word), 27, 31))
63 #define OPCODE_AC(word) (BITS ((word), 11, 15))
65 /* Functions implementation. */
68 bfd_getm32 (unsigned int data)
72 value = ((data & 0xff00) | (data & 0xff)) << 16;
73 value |= ((data & 0xff0000) | (data & 0xff000000)) >> 16;
78 special_flag_p (const char *opname,
81 const struct arc_flag_special *flg_spec;
82 unsigned i, j, flgidx;
84 for (i = 0; i < arc_num_flag_special; i++)
86 flg_spec = &arc_flag_special_cases[i];
88 if (strcmp (opname, flg_spec->name))
91 /* Found potential special case instruction. */
94 flgidx = flg_spec->flags[j];
96 break; /* End of the array. */
98 if (strcmp (flgname, arc_flag_operands[flgidx].name) == 0)
105 /* Find proper format for the given opcode. */
106 static const struct arc_opcode *
107 find_format (const struct arc_opcode *arc_table,
108 unsigned *insn, int insnLen,
112 const struct arc_opcode *opcode = NULL;
113 const unsigned char *opidx;
114 const unsigned char *flgidx;
117 bfd_boolean invalid = FALSE;
119 opcode = &arc_table[i++];
121 if (ARC_SHORT (opcode->mask) && (insnLen == 2))
123 if (OPCODE_AC (opcode->opcode) != OPCODE_AC (insn[0]))
126 else if (!ARC_SHORT (opcode->mask) && (insnLen == 4))
128 if (OPCODE (opcode->opcode) != OPCODE (insn[0]))
134 if ((insn[0] ^ opcode->opcode) & opcode->mask)
137 if (!(opcode->cpu & isa_mask))
140 /* Possible candidate, check the operands. */
141 for (opidx = opcode->operands; *opidx; opidx++)
144 const struct arc_operand *operand = &arc_operands[*opidx];
146 if (operand->flags & ARC_OPERAND_FAKE)
149 if (operand->extract)
150 value = (*operand->extract) (insn[0], &invalid);
152 value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
154 /* Check for LIMM indicator. If it is there, then make sure
155 we pick the right format. */
156 if (operand->flags & ARC_OPERAND_IR
157 && !(operand->flags & ARC_OPERAND_LIMM))
159 if ((value == 0x3E && insnLen == 4)
160 || (value == 0x1E && insnLen == 2))
168 /* Check the flags. */
169 for (flgidx = opcode->flags; *flgidx; flgidx++)
171 /* Get a valid flag class. */
172 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
173 const unsigned *flgopridx;
174 int foundA = 0, foundB = 0;
177 /* Check first the extensions. */
178 if (cl_flags->class & F_CLASS_EXTEND)
180 value = (insn[0] & 0x1F);
181 if (arcExtMap_condCodeName (value))
184 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
186 const struct arc_flag_operand *flg_operand =
187 &arc_flag_operands[*flgopridx];
189 value = (insn[0] >> flg_operand->shift)
190 & ((1 << flg_operand->bits) - 1);
191 if (value == flg_operand->code)
196 if (!foundA && foundB)
206 /* The instruction is valid. */
208 } while (opcode->mask);
214 print_flags (const struct arc_opcode *opcode,
216 struct disassemble_info *info)
218 const unsigned char *flgidx;
221 /* Now extract and print the flags. */
222 for (flgidx = opcode->flags; *flgidx; flgidx++)
224 /* Get a valid flag class. */
225 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
226 const unsigned *flgopridx;
228 /* Check first the extensions. */
229 if (cl_flags->class & F_CLASS_EXTEND)
232 value = (insn[0] & 0x1F);
234 name = arcExtMap_condCodeName (value);
237 (*info->fprintf_func) (info->stream, ".%s", name);
242 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
244 const struct arc_flag_operand *flg_operand =
245 &arc_flag_operands[*flgopridx];
247 if (!flg_operand->favail)
250 value = (insn[0] >> flg_operand->shift)
251 & ((1 << flg_operand->bits) - 1);
252 if (value == flg_operand->code)
254 /* FIXME!: print correctly nt/t flag. */
255 if (!special_flag_p (opcode->name, flg_operand->name))
256 (*info->fprintf_func) (info->stream, ".");
257 else if (info->insn_type == dis_dref)
259 switch (flg_operand->name[0])
273 (*info->fprintf_func) (info->stream, "%s", flg_operand->name);
276 if (flg_operand->name[0] == 'd'
277 && flg_operand->name[1] == 0)
278 info->branch_delay_insns = 1;
284 get_auxreg (const struct arc_opcode *opcode,
290 const struct arc_aux_reg *auxr = &arc_aux_regs[0];
292 if (opcode->class != AUXREG)
295 name = arcExtMap_auxRegName (value);
299 for (i = 0; i < arc_num_aux_regs; i++, auxr++)
301 if (!(auxr->cpu & isa_mask))
304 if (auxr->subclass != NONE)
307 if (auxr->address == value)
312 /* Disassemble ARC instructions. */
315 print_insn_arc (bfd_vma memaddr,
316 struct disassemble_info *info)
319 unsigned int lowbyte, highbyte;
322 unsigned insn[2] = { 0, 0 };
324 const unsigned char *opidx;
325 const struct arc_opcode *opcode;
326 const extInstruction_t *einsn;
327 bfd_boolean need_comma;
328 bfd_boolean open_braket;
331 lowbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0);
332 highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1);
336 case bfd_mach_arc_nps400:
337 isa_mask = ARC_OPCODE_ARC700 | ARC_OPCODE_NPS400;
340 case bfd_mach_arc_arc700:
341 isa_mask = ARC_OPCODE_ARC700;
344 case bfd_mach_arc_arc600:
345 isa_mask = ARC_OPCODE_ARC600;
348 case bfd_mach_arc_arcv2:
350 isa_mask = ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARCv2EM;
354 /* This variable may be set by the instruction decoder. It suggests
355 the number of bytes objdump should display on a single line. If
356 the instruction decoder sets this, it should always set it to
357 the same value in order to get reasonable looking output. */
359 info->bytes_per_line = 8;
361 /* In the next lines, we set two info variables control the way
362 objdump displays the raw data. For example, if bytes_per_line is
363 8 and bytes_per_chunk is 4, the output will look like this:
364 00: 00000000 00000000
365 with the chunks displayed according to "display_endian". */
368 && !(info->section->flags & SEC_CODE))
370 /* This is not a CODE section. */
371 switch (info->section->size)
376 size = info->section->size;
379 size = (info->section->size & 0x01) ? 1 : 4;
382 info->bytes_per_chunk = 1;
383 info->display_endian = info->endian;
388 info->bytes_per_chunk = 2;
389 info->display_endian = info->endian;
392 /* Read the insn into a host word. */
393 status = (*info->read_memory_func) (memaddr, buffer, size, info);
396 (*info->memory_error_func) (status, memaddr, info);
401 && !(info->section->flags & SEC_CODE))
406 data = bfd_get_bits (buffer, size * 8,
407 info->display_endian == BFD_ENDIAN_BIG);
411 (*info->fprintf_func) (info->stream, ".byte\t0x%02lx", data);
414 (*info->fprintf_func) (info->stream, ".short\t0x%04lx", data);
417 (*info->fprintf_func) (info->stream, ".word\t0x%08lx", data);
425 if ((((buffer[lowbyte] & 0xf8) > 0x38)
426 && ((buffer[lowbyte] & 0xf8) != 0x48))
427 || ((info->mach == bfd_mach_arc_arcv2)
428 && ((buffer[lowbyte] & 0xF8) == 0x48)) /* FIXME! ugly. */
431 /* This is a short instruction. */
433 insn[0] = (buffer[lowbyte] << 8) | buffer[highbyte];
439 /* This is a long instruction: Read the remaning 2 bytes. */
440 status = (*info->read_memory_func) (memaddr + 2, &buffer[2], 2, info);
443 (*info->memory_error_func) (status, memaddr + 2, info);
446 insn[0] = ARRANGE_ENDIAN (info, buffer);
449 /* Set some defaults for the insn info. */
450 info->insn_info_valid = 1;
451 info->branch_delay_insns = 0;
453 info->insn_type = dis_nonbranch;
457 /* FIXME to be moved in dissasemble_init_for_target. */
458 info->disassembler_needs_relocs = TRUE;
460 /* Find the first match in the opcode table. */
461 opcode = find_format (arc_opcodes, insn, insnLen, isa_mask);
465 /* No instruction found. Try the extensions. */
466 einsn = arcExtMap_insn (OPCODE (insn[0]), insn[0]);
469 const char *errmsg = NULL;
470 opcode = arcExtMap_genOpcode (einsn, isa_mask, &errmsg);
473 (*info->fprintf_func) (info->stream,
474 "An error occured while "
475 "generating the extension instruction "
480 opcode = find_format (opcode, insn, insnLen, isa_mask);
481 assert (opcode != NULL);
486 (*info->fprintf_func) (info->stream, ".long %#04x", insn[0]);
488 (*info->fprintf_func) (info->stream, ".long %#08x", insn[0]);
490 info->insn_type = dis_noninsn;
495 /* Print the mnemonic. */
496 (*info->fprintf_func) (info->stream, "%s", opcode->name);
498 /* Preselect the insn class. */
499 switch (opcode->class)
503 if (!strncmp (opcode->name, "bl", 2)
504 || !strncmp (opcode->name, "jl", 2))
505 info->insn_type = dis_jsr;
507 info->insn_type = dis_branch;
510 info->insn_type = dis_dref; /* FIXME! DB indicates mov as memory! */
513 info->insn_type = dis_nonbranch;
517 pr_debug ("%s: 0x%08x\n", opcode->name, opcode->opcode);
519 print_flags (opcode, insn, info);
521 if (opcode->operands[0] != 0)
522 (*info->fprintf_func) (info->stream, "\t");
527 /* Now extract and print the operands. */
528 for (opidx = opcode->operands; *opidx; opidx++)
530 const struct arc_operand *operand = &arc_operands[*opidx];
533 if (open_braket && (operand->flags & ARC_OPERAND_BRAKET))
535 (*info->fprintf_func) (info->stream, "]");
540 /* Only take input from real operands. */
541 if ((operand->flags & ARC_OPERAND_FAKE)
542 && !(operand->flags & ARC_OPERAND_BRAKET))
545 if (operand->extract)
546 value = (*operand->extract) (insn[0], (int *) NULL);
549 if (operand->flags & ARC_OPERAND_ALIGNED32)
551 value = (insn[0] >> operand->shift)
552 & ((1 << (operand->bits - 2)) - 1);
557 value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
559 if (operand->flags & ARC_OPERAND_SIGNED)
561 int signbit = 1 << (operand->bits - 1);
562 value = (value ^ signbit) - signbit;
566 if (operand->flags & ARC_OPERAND_IGNORE
567 && (operand->flags & ARC_OPERAND_IR
572 (*info->fprintf_func) (info->stream, ",");
574 if (!open_braket && (operand->flags & ARC_OPERAND_BRAKET))
576 (*info->fprintf_func) (info->stream, "[");
582 /* Read the limm operand, if required. */
583 if (operand->flags & ARC_OPERAND_LIMM
584 && !(operand->flags & ARC_OPERAND_DUPLICATE))
586 status = (*info->read_memory_func) (memaddr + insnLen, buffer,
590 (*info->memory_error_func) (status, memaddr + insnLen, info);
593 insn[1] = ARRANGE_ENDIAN (info, buffer);
596 /* Print the operand as directed by the flags. */
597 if (operand->flags & ARC_OPERAND_IR)
601 assert (value >=0 && value < 64);
602 rname = arcExtMap_coreRegName (value);
604 rname = regnames[value];
605 (*info->fprintf_func) (info->stream, "%s", rname);
606 if (operand->flags & ARC_OPERAND_TRUNCATE)
608 rname = arcExtMap_coreRegName (value + 1);
610 rname = regnames[value + 1];
611 (*info->fprintf_func) (info->stream, "%s", rname);
614 else if (operand->flags & ARC_OPERAND_LIMM)
616 const char *rname = get_auxreg (opcode, insn[1], isa_mask);
617 if (rname && open_braket)
618 (*info->fprintf_func) (info->stream, "%s", rname);
621 (*info->fprintf_func) (info->stream, "%#x", insn[1]);
622 if (info->insn_type == dis_branch
623 || info->insn_type == dis_jsr)
624 info->target = (bfd_vma) insn[1];
627 else if (operand->flags & ARC_OPERAND_PCREL)
630 if (info->flags & INSN_HAS_RELOC)
632 (*info->print_address_func) ((memaddr & ~3) + value, info);
634 info->target = (bfd_vma) (memaddr & ~3) + value;
636 else if (operand->flags & ARC_OPERAND_SIGNED)
638 const char *rname = get_auxreg (opcode, value, isa_mask);
639 if (rname && open_braket)
640 (*info->fprintf_func) (info->stream, "%s", rname);
642 (*info->fprintf_func) (info->stream, "%d", value);
646 if (operand->flags & ARC_OPERAND_TRUNCATE
647 && !(operand->flags & ARC_OPERAND_ALIGNED32)
648 && !(operand->flags & ARC_OPERAND_ALIGNED16)
649 && value > 0 && value <= 14)
650 (*info->fprintf_func) (info->stream, "r13-%s",
651 regnames[13 + value - 1]);
654 const char *rname = get_auxreg (opcode, value, isa_mask);
655 if (rname && open_braket)
656 (*info->fprintf_func) (info->stream, "%s", rname);
658 (*info->fprintf_func) (info->stream, "%#x", value);
664 /* Adjust insn len. */
665 if (operand->flags & ARC_OPERAND_LIMM
666 && !(operand->flags & ARC_OPERAND_DUPLICATE))
675 arc_get_disassembler (bfd *abfd)
677 /* Read the extenssion insns and registers, if any. */
678 build_ARC_extmap (abfd);
683 return print_insn_arc;
686 /* Disassemble ARC instructions. Used by debugger. */
689 arcAnalyzeInstr (bfd_vma memaddr,
690 struct disassemble_info *info)
692 struct arcDisState ret;
693 memset (&ret, 0, sizeof (struct arcDisState));
695 ret.instructionLen = print_insn_arc (memaddr, info);
698 ret.words[0] = insn[0];
699 ret.words[1] = insn[1];
701 ret.coreRegName = _coreRegName;
702 ret.auxRegName = _auxRegName;
703 ret.condCodeName = _condCodeName;
704 ret.instName = _instName;
711 eval: (c-set-style "gnu")