1 /* Instruction printing code for the ARC.
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
27 #include "opcode/arc.h"
32 #include "libiberty.h"
35 /* Structure used to iterate over, and extract the values for, operands of
38 struct arc_operand_iterator
42 OPERAND_ITERATOR_STANDARD,
46 /* The array of 32-bit values that make up this instruction. All
47 required values have been pre-loaded into this array during the
55 /* The opcode this iterator is operating on. */
56 const struct arc_opcode *opcode;
58 /* The index into the opcodes operand index list. */
59 const unsigned char *opidx;
64 /* The long instruction opcode this iterator is operating on. */
65 const struct arc_long_opcode *long_opcode;
67 /* Two indexes into the opcodes operand index lists. */
68 const unsigned char *opidx_base, *opidx_limm;
73 /* Globals variables. */
75 static const char * const regnames[64] =
77 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
78 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
79 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
80 "r24", "r25", "gp", "fp", "sp", "ilink", "r30", "blink",
82 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
83 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
84 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
85 "r56", "r57", "ACCL", "ACCH", "lp_count", "rezerved", "LIMM", "pcl"
88 static const char * const addrtypenames[ARC_NUM_ADDRTYPES] =
90 "bd", "jid", "lbd", "mbd", "sd", "sm", "xa", "xd",
91 "cd", "cbd", "cjid", "clbd", "cm", "csd", "cxa", "cxd"
94 static int addrtypenames_max = ARC_NUM_ADDRTYPES - 1;
96 static const char * const addrtypeunknown = "unknown";
98 /* This structure keeps track which instruction class(es)
99 should be ignored durring disassembling. */
101 typedef struct skipclass
103 insn_class_t insn_class;
104 insn_subclass_t subclass;
105 struct skipclass *nxt;
106 } skipclass_t, *linkclass;
108 /* Intial classes of instructions to be consider first when
110 static linkclass decodelist = NULL;
112 /* Macros section. */
115 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
117 # define pr_debug(fmt, args...)
120 #define ARRANGE_ENDIAN(info, buf) \
121 (info->endian == BFD_ENDIAN_LITTLE ? bfd_getm32 (bfd_getl32 (buf)) \
124 #define BITS(word,s,e) (((word) << (sizeof (word) * 8 - 1 - e)) >> \
125 (s + (sizeof (word) * 8 - 1 - e)))
126 #define OPCODE(word) (BITS ((word), 27, 31))
128 #define OPCODE_AC(word) (BITS ((word), 11, 15))
130 /* Functions implementation. */
132 /* Return TRUE when two classes are not opcode conflicting. */
135 is_compatible_p (insn_class_t classA,
136 insn_subclass_t sclassA,
138 insn_subclass_t sclassB)
140 if (classA == DSP && sclassB == DPX)
142 if (sclassA == DPX && classB == DSP)
147 /* Add a new element to the decode list. */
150 add_to_decodelist (insn_class_t insn_class,
151 insn_subclass_t subclass)
153 linkclass t = (linkclass) xmalloc (sizeof (skipclass_t));
155 t->insn_class = insn_class;
156 t->subclass = subclass;
161 /* Return TRUE if we need to skip the opcode from being
165 skip_this_opcode (const struct arc_opcode * opcode,
166 struct disassemble_info * info)
168 linkclass t = decodelist;
169 bfd_boolean addme = TRUE;
171 /* Check opcode for major 0x06, return if it is not in. */
172 if (OPCODE (opcode->opcode) != 0x06)
176 && is_compatible_p (t->insn_class, t->subclass,
177 opcode->insn_class, opcode->subclass))
179 if ((t->insn_class == opcode->insn_class)
180 && (t->subclass == opcode->subclass))
185 /* If we found an incompatibility then we must skip. */
189 /* Even if we do not precisely know the if the right mnemonics
190 is correctly displayed, keep the disassmbled code class
194 switch (opcode->insn_class)
198 /* Add to the conflict list only the classes which
200 add_to_decodelist (opcode->insn_class, opcode->subclass);
201 /* Warn if we have to decode an opcode and no preferred
202 classes have been chosen. */
203 info->fprintf_func (info->stream, _("\n\
204 Warning: disassembly may be wrong due to guessed opcode class choice.\n\
205 Use -M<class[,class]> to select the correct opcode class(es).\n\t\t\t\t"));
215 bfd_getm32 (unsigned int data)
219 value = ((data & 0xff00) | (data & 0xff)) << 16;
220 value |= ((data & 0xff0000) | (data & 0xff000000)) >> 16;
225 special_flag_p (const char *opname,
228 const struct arc_flag_special *flg_spec;
229 unsigned i, j, flgidx;
231 for (i = 0; i < arc_num_flag_special; i++)
233 flg_spec = &arc_flag_special_cases[i];
235 if (strcmp (opname, flg_spec->name))
238 /* Found potential special case instruction. */
241 flgidx = flg_spec->flags[j];
243 break; /* End of the array. */
245 if (strcmp (flgname, arc_flag_operands[flgidx].name) == 0)
252 /* Find opcode from ARC_TABLE given the instruction described by INSN and
253 INSNLEN. The ISA_MASK restricts the possible matches in ARC_TABLE. */
255 static const struct arc_opcode *
256 find_format_from_table (struct disassemble_info *info,
257 const struct arc_opcode *arc_table,
259 unsigned int insn_len,
261 bfd_boolean *has_limm,
262 bfd_boolean overlaps)
265 const struct arc_opcode *opcode = NULL;
266 const unsigned char *opidx;
267 const unsigned char *flgidx;
271 bfd_boolean invalid = FALSE;
273 opcode = &arc_table[i++];
275 if (ARC_SHORT (opcode->mask) && (insn_len == 2))
277 if (OPCODE_AC (opcode->opcode) != OPCODE_AC (insn[0]))
280 else if (!ARC_SHORT (opcode->mask) && (insn_len == 4))
282 if (OPCODE (opcode->opcode) != OPCODE (insn[0]))
288 if ((insn[0] ^ opcode->opcode) & opcode->mask)
291 if (!(opcode->cpu & isa_mask))
296 /* Possible candidate, check the operands. */
297 for (opidx = opcode->operands; *opidx; opidx++)
300 const struct arc_operand *operand = &arc_operands[*opidx];
302 if (operand->flags & ARC_OPERAND_FAKE)
305 if (operand->extract)
306 value = (*operand->extract) (insn[0], &invalid);
308 value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
310 /* Check for LIMM indicator. If it is there, then make sure
311 we pick the right format. */
312 limmind = (isa_mask & ARC_OPCODE_ARCV2) ? 0x1E : 0x3E;
313 if (operand->flags & ARC_OPERAND_IR
314 && !(operand->flags & ARC_OPERAND_LIMM))
316 if ((value == 0x3E && insn_len == 4)
317 || (value == limmind && insn_len == 2))
324 if (operand->flags & ARC_OPERAND_LIMM
325 && !(operand->flags & ARC_OPERAND_DUPLICATE))
329 /* Check the flags. */
330 for (flgidx = opcode->flags; *flgidx; flgidx++)
332 /* Get a valid flag class. */
333 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
334 const unsigned *flgopridx;
335 int foundA = 0, foundB = 0;
338 /* Check first the extensions. */
339 if (cl_flags->flag_class & F_CLASS_EXTEND)
341 value = (insn[0] & 0x1F);
342 if (arcExtMap_condCodeName (value))
346 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
348 const struct arc_flag_operand *flg_operand =
349 &arc_flag_operands[*flgopridx];
351 value = (insn[0] >> flg_operand->shift)
352 & ((1 << flg_operand->bits) - 1);
353 if (value == flg_operand->code)
359 if (!foundA && foundB)
371 && skip_this_opcode (opcode, info))
374 /* The instruction is valid. */
377 while (opcode->mask);
382 /* Find long instructions matching values in INSN array. */
384 static const struct arc_long_opcode *
385 find_format_long_instructions (unsigned *insn,
386 unsigned int *insn_len,
389 struct disassemble_info *info)
393 bfd_boolean limm_loaded = FALSE;
395 for (i = 0; i < arc_num_long_opcodes; ++i)
399 const struct arc_opcode *opcode;
401 opcode = &arc_long_opcodes[i].base_opcode;
403 if (ARC_SHORT (opcode->mask) && (*insn_len == 2))
405 if (OPCODE_AC (opcode->opcode) != OPCODE_AC (insn[0]))
408 else if (!ARC_SHORT (opcode->mask) && (*insn_len == 4))
410 if (OPCODE (opcode->opcode) != OPCODE (insn[0]))
416 if ((insn[0] ^ opcode->opcode) & opcode->mask)
419 if (!(opcode->cpu & isa_mask))
424 status = (*info->read_memory_func) (memaddr + *insn_len, buffer,
429 limm = ARRANGE_ENDIAN (info, buffer);
433 /* Check the second word using the mask and template. */
434 if ((limm & arc_long_opcodes[i].limm_mask)
435 != arc_long_opcodes[i].limm_template)
440 return &arc_long_opcodes[i];
446 /* Find opcode for INSN, trying various different sources. The instruction
447 length in INSN_LEN will be updated if the instruction requires a LIMM
448 extension, and the additional values loaded into the INSN array (which
451 A pointer to the opcode is placed into OPCODE_RESULT, and ITER is
452 initialised, ready to iterate over the operands of the found opcode.
454 This function returns TRUE in almost all cases, FALSE is reserved to
455 indicate an error (failing to find an opcode is not an error) a
456 returned result of FALSE would indicate that the disassembler can't
459 If no matching opcode is found then the returned result will be TRUE,
460 the value placed into OPCODE_RESULT will be NULL, ITER will be
461 undefined, and INSN_LEN will be unchanged.
463 If a matching opcode is found, then the returned result will be TRUE,
464 the opcode pointer is placed into OPCODE_RESULT, INSN_LEN will be
465 increased by 4 if the instruction requires a LIMM, and the LIMM value
466 will have been loaded into the INSN[1]. Finally, ITER will have been
467 initialised so that calls to OPERAND_ITERATOR_NEXT will iterate over
468 the opcode's operands. */
471 find_format (bfd_vma memaddr,
473 unsigned int * insn_len,
475 struct disassemble_info * info,
476 const struct arc_opcode ** opcode_result,
477 struct arc_operand_iterator * iter)
479 const struct arc_opcode *opcode = NULL;
480 bfd_boolean needs_limm;
481 const extInstruction_t *einsn, *i;
483 /* First, try the extension instructions. */
484 einsn = arcExtMap_insn (OPCODE (insn[0]), insn[0]);
485 for (i = einsn; (i != NULL) && (opcode == NULL); i = i->next)
487 const char *errmsg = NULL;
489 opcode = arcExtMap_genOpcode (i, isa_mask, &errmsg);
492 (*info->fprintf_func) (info->stream, "\
493 An error occured while generating the extension instruction operations");
494 *opcode_result = NULL;
498 opcode = find_format_from_table (info, opcode, insn, *insn_len,
499 isa_mask, &needs_limm, FALSE);
502 /* Then, try finding the first match in the opcode table. */
504 opcode = find_format_from_table (info, arc_opcodes, insn, *insn_len,
505 isa_mask, &needs_limm, TRUE);
507 if (needs_limm && opcode != NULL)
512 status = (*info->read_memory_func) (memaddr + *insn_len, buffer,
520 insn[1] = ARRANGE_ENDIAN (info, buffer);
527 const struct arc_long_opcode *long_opcode;
529 /* No instruction found yet, try the long instructions. */
531 find_format_long_instructions (insn, insn_len, isa_mask,
534 if (long_opcode != NULL)
536 iter->mode = OPERAND_ITERATOR_LONG;
538 iter->state.long_insn.long_opcode = long_opcode;
539 iter->state.long_insn.opidx_base =
540 long_opcode->base_opcode.operands;
541 iter->state.long_insn.opidx_limm =
542 long_opcode->operands;
543 opcode = &long_opcode->base_opcode;
548 iter->mode = OPERAND_ITERATOR_STANDARD;
550 iter->state.standard.opcode = opcode;
551 iter->state.standard.opidx = opcode->operands;
554 *opcode_result = opcode;
559 print_flags (const struct arc_opcode *opcode,
561 struct disassemble_info *info)
563 const unsigned char *flgidx;
566 /* Now extract and print the flags. */
567 for (flgidx = opcode->flags; *flgidx; flgidx++)
569 /* Get a valid flag class. */
570 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
571 const unsigned *flgopridx;
573 /* Check first the extensions. */
574 if (cl_flags->flag_class & F_CLASS_EXTEND)
577 value = (insn[0] & 0x1F);
579 name = arcExtMap_condCodeName (value);
582 (*info->fprintf_func) (info->stream, ".%s", name);
587 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
589 const struct arc_flag_operand *flg_operand =
590 &arc_flag_operands[*flgopridx];
592 if (!flg_operand->favail)
595 value = (insn[0] >> flg_operand->shift)
596 & ((1 << flg_operand->bits) - 1);
597 if (value == flg_operand->code)
599 /* FIXME!: print correctly nt/t flag. */
600 if (!special_flag_p (opcode->name, flg_operand->name))
601 (*info->fprintf_func) (info->stream, ".");
602 else if (info->insn_type == dis_dref)
604 switch (flg_operand->name[0])
618 if (flg_operand->name[0] == 'd'
619 && flg_operand->name[1] == 0)
620 info->branch_delay_insns = 1;
622 /* Check if it is a conditional flag. */
623 if (cl_flags->flag_class & F_CLASS_COND)
625 if (info->insn_type == dis_jsr)
626 info->insn_type = dis_condjsr;
627 else if (info->insn_type == dis_branch)
628 info->insn_type = dis_condbranch;
631 (*info->fprintf_func) (info->stream, "%s", flg_operand->name);
638 get_auxreg (const struct arc_opcode *opcode,
644 const struct arc_aux_reg *auxr = &arc_aux_regs[0];
646 if (opcode->insn_class != AUXREG)
649 name = arcExtMap_auxRegName (value);
653 for (i = 0; i < arc_num_aux_regs; i++, auxr++)
655 if (!(auxr->cpu & isa_mask))
658 if (auxr->subclass != NONE)
661 if (auxr->address == value)
667 /* Convert a value representing an address type to a string used to refer to
668 the address type in assembly code. */
671 get_addrtype (int value)
673 if (value < 0 || value > addrtypenames_max)
674 return addrtypeunknown;
676 return addrtypenames[value];
679 /* Calculate the instruction length for an instruction starting with MSB
680 and LSB, the most and least significant byte. The ISA_MASK is used to
681 filter the instructions considered to only those that are part of the
682 current architecture.
684 The instruction lengths are calculated from the ARC_OPCODE table, and
685 cached for later use. */
688 arc_insn_length (bfd_byte msb, bfd_byte lsb, struct disassemble_info *info)
690 bfd_byte major_opcode = msb >> 3;
694 case bfd_mach_arc_arc700:
695 /* The nps400 extension set requires this special casing of the
696 instruction length calculation. Right now this is not causing any
697 problems as none of the known extensions overlap in opcode space,
698 but, if they ever do then we might need to start carrying
699 information around in the elf about which extensions are in use. */
700 if (major_opcode == 0xb)
702 bfd_byte minor_opcode = lsb & 0x1f;
704 if (minor_opcode < 4)
708 case bfd_mach_arc_arc600:
709 return (major_opcode > 0xb) ? 2 : 4;
712 case bfd_mach_arc_arcv2:
713 return (major_opcode > 0x7) ? 2 : 4;
721 /* Extract and return the value of OPERAND from the instruction whose value
722 is held in the array INSN. */
725 extract_operand_value (const struct arc_operand *operand, unsigned *insn)
729 /* Read the limm operand, if required. */
730 if (operand->flags & ARC_OPERAND_LIMM)
731 /* The second part of the instruction value will have been loaded as
732 part of the find_format call made earlier. */
736 if (operand->extract)
737 value = (*operand->extract) (insn[0], (int *) NULL);
740 if (operand->flags & ARC_OPERAND_ALIGNED32)
742 value = (insn[0] >> operand->shift)
743 & ((1 << (operand->bits - 2)) - 1);
748 value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
750 if (operand->flags & ARC_OPERAND_SIGNED)
752 int signbit = 1 << (operand->bits - 1);
753 value = (value ^ signbit) - signbit;
761 /* Find the next operand, and the operands value from ITER. Return TRUE if
762 there is another operand, otherwise return FALSE. If there is an
763 operand returned then the operand is placed into OPERAND, and the value
764 into VALUE. If there is no operand returned then OPERAND and VALUE are
768 operand_iterator_next (struct arc_operand_iterator *iter,
769 const struct arc_operand **operand,
772 if (iter->mode == OPERAND_ITERATOR_STANDARD)
774 if (*iter->state.standard.opidx == 0)
780 *operand = &arc_operands[*iter->state.standard.opidx];
781 *value = extract_operand_value (*operand, iter->insn);
782 iter->state.standard.opidx++;
786 const struct arc_operand *operand_base, *operand_limm;
787 int value_base, value_limm;
789 if (*iter->state.long_insn.opidx_limm == 0)
795 operand_base = &arc_operands[*iter->state.long_insn.opidx_base];
796 operand_limm = &arc_operands[*iter->state.long_insn.opidx_limm];
798 if (operand_base->flags & ARC_OPERAND_LIMM)
800 /* We've reached the end of the operand list. */
805 value_base = value_limm = 0;
806 if (!(operand_limm->flags & ARC_OPERAND_IGNORE))
808 /* This should never happen. If it does then the use of
809 extract_operand_value below will access memory beyond
811 assert ((operand_limm->flags & ARC_OPERAND_LIMM) == 0);
813 *operand = operand_limm;
814 value_limm = extract_operand_value (*operand, &iter->insn[1]);
817 if (!(operand_base->flags & ARC_OPERAND_IGNORE))
819 *operand = operand_base;
820 value_base = extract_operand_value (*operand, iter->insn);
823 /* This is a bit of a fudge. There's no reason why simply ORing
824 together the two values is the right thing to do, however, for all
825 the cases we currently have, it is the right thing, so, for now,
826 I've put off solving the more complex problem. */
827 *value = value_base | value_limm;
829 iter->state.long_insn.opidx_base++;
830 iter->state.long_insn.opidx_limm++;
835 /* Helper for parsing the options. */
838 parse_option (char *option)
840 if (CONST_STRNEQ (option, "dsp"))
841 add_to_decodelist (DSP, NONE);
843 else if (CONST_STRNEQ (option, "spfp"))
844 add_to_decodelist (FLOAT, SPX);
846 else if (CONST_STRNEQ (option, "dpfp"))
847 add_to_decodelist (FLOAT, DPX);
849 else if (CONST_STRNEQ (option, "quarkse_em"))
850 add_to_decodelist (FLOAT, QUARKSE);
852 else if (CONST_STRNEQ (option, "fpuda"))
853 add_to_decodelist (FLOAT, DPA);
855 else if (CONST_STRNEQ (option, "fpud"))
857 add_to_decodelist (FLOAT, SP);
858 add_to_decodelist (FLOAT, CVT);
861 else if (CONST_STRNEQ (option, "fpus"))
863 add_to_decodelist (FLOAT, DP);
864 add_to_decodelist (FLOAT, CVT);
867 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
870 /* Go over the options list and parse it. */
873 parse_disassembler_options (char *options)
880 /* Skip empty options. */
887 parse_option (options);
889 while (*options != ',' && *options != '\0')
894 /* Disassemble ARC instructions. */
897 print_insn_arc (bfd_vma memaddr,
898 struct disassemble_info *info)
901 unsigned int lowbyte, highbyte;
903 unsigned int insn_len;
904 unsigned insn[2] = { 0, 0 };
906 const struct arc_opcode *opcode;
907 bfd_boolean need_comma;
908 bfd_boolean open_braket;
910 const struct arc_operand *operand;
912 struct arc_operand_iterator iter;
913 Elf_Internal_Ehdr *header = NULL;
915 if (info->disassembler_options)
917 parse_disassembler_options (info->disassembler_options);
919 /* Avoid repeated parsing of the options. */
920 info->disassembler_options = NULL;
923 memset (&iter, 0, sizeof (iter));
924 lowbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0);
925 highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1);
927 if (info->section && info->section->owner)
928 header = elf_elfheader (info->section->owner);
932 case bfd_mach_arc_arc700:
933 isa_mask = ARC_OPCODE_ARC700;
936 case bfd_mach_arc_arc600:
937 isa_mask = ARC_OPCODE_ARC600;
940 case bfd_mach_arc_arcv2:
942 isa_mask = ARC_OPCODE_ARCv2EM;
943 /* TODO: Perhaps remove defitinion of header since it is only used at
946 && (header->e_flags & EF_ARC_MACH_MSK) == EF_ARC_CPU_ARCV2HS)
948 isa_mask = ARC_OPCODE_ARCv2HS;
949 /* FPU instructions are not extensions for HS. */
950 add_to_decodelist (FLOAT, SP);
951 add_to_decodelist (FLOAT, DP);
952 add_to_decodelist (FLOAT, CVT);
957 /* This variable may be set by the instruction decoder. It suggests
958 the number of bytes objdump should display on a single line. If
959 the instruction decoder sets this, it should always set it to
960 the same value in order to get reasonable looking output. */
962 info->bytes_per_line = 8;
964 /* In the next lines, we set two info variables control the way
965 objdump displays the raw data. For example, if bytes_per_line is
966 8 and bytes_per_chunk is 4, the output will look like this:
967 00: 00000000 00000000
968 with the chunks displayed according to "display_endian". */
971 && !(info->section->flags & SEC_CODE))
973 /* This is not a CODE section. */
974 switch (info->section->size)
979 size = info->section->size;
982 size = (info->section->size & 0x01) ? 1 : 4;
985 info->bytes_per_chunk = 1;
986 info->display_endian = info->endian;
991 info->bytes_per_chunk = 2;
992 info->display_endian = info->endian;
995 /* Read the insn into a host word. */
996 status = (*info->read_memory_func) (memaddr, buffer, size, info);
999 (*info->memory_error_func) (status, memaddr, info);
1004 && !(info->section->flags & SEC_CODE))
1009 data = bfd_get_bits (buffer, size * 8,
1010 info->display_endian == BFD_ENDIAN_BIG);
1014 (*info->fprintf_func) (info->stream, ".byte\t0x%02lx", data);
1017 (*info->fprintf_func) (info->stream, ".short\t0x%04lx", data);
1020 (*info->fprintf_func) (info->stream, ".word\t0x%08lx", data);
1028 insn_len = arc_insn_length (buffer[lowbyte], buffer[highbyte], info);
1029 pr_debug ("instruction length = %d bytes\n", insn_len);
1034 insn[0] = (buffer[lowbyte] << 8) | buffer[highbyte];
1038 /* An unknown instruction is treated as being length 4. This is
1039 possibly not the best solution, but matches the behaviour that was
1040 in place before the table based instruction length look-up was
1043 /* This is a long instruction: Read the remaning 2 bytes. */
1044 status = (*info->read_memory_func) (memaddr + 2, &buffer[2], 2, info);
1047 (*info->memory_error_func) (status, memaddr + 2, info);
1050 insn[0] = ARRANGE_ENDIAN (info, buffer);
1054 /* Set some defaults for the insn info. */
1055 info->insn_info_valid = 1;
1056 info->branch_delay_insns = 0;
1057 info->data_size = 0;
1058 info->insn_type = dis_nonbranch;
1062 /* FIXME to be moved in dissasemble_init_for_target. */
1063 info->disassembler_needs_relocs = TRUE;
1065 /* Find the first match in the opcode table. */
1066 if (!find_format (memaddr, insn, &insn_len, isa_mask, info, &opcode, &iter))
1072 (*info->fprintf_func) (info->stream, ".long %#04x", insn[0]);
1074 (*info->fprintf_func) (info->stream, ".long %#08x", insn[0]);
1076 info->insn_type = dis_noninsn;
1080 /* Print the mnemonic. */
1081 (*info->fprintf_func) (info->stream, "%s", opcode->name);
1083 /* Preselect the insn class. */
1084 switch (opcode->insn_class)
1088 if (!strncmp (opcode->name, "bl", 2)
1089 || !strncmp (opcode->name, "jl", 2))
1091 if (opcode->subclass == COND)
1092 info->insn_type = dis_condjsr;
1094 info->insn_type = dis_jsr;
1098 if (opcode->subclass == COND)
1099 info->insn_type = dis_condbranch;
1101 info->insn_type = dis_branch;
1105 info->insn_type = dis_dref; /* FIXME! DB indicates mov as memory! */
1108 info->insn_type = dis_nonbranch;
1112 pr_debug ("%s: 0x%08x\n", opcode->name, opcode->opcode);
1114 print_flags (opcode, insn, info);
1116 if (opcode->operands[0] != 0)
1117 (*info->fprintf_func) (info->stream, "\t");
1120 open_braket = FALSE;
1122 /* Now extract and print the operands. */
1124 while (operand_iterator_next (&iter, &operand, &value))
1126 if (open_braket && (operand->flags & ARC_OPERAND_BRAKET))
1128 (*info->fprintf_func) (info->stream, "]");
1129 open_braket = FALSE;
1133 /* Only take input from real operands. */
1134 if (ARC_OPERAND_IS_FAKE (operand))
1137 if ((operand->flags & ARC_OPERAND_IGNORE)
1138 && (operand->flags & ARC_OPERAND_IR)
1142 if (operand->flags & ARC_OPERAND_COLON)
1144 (*info->fprintf_func) (info->stream, ":");
1149 (*info->fprintf_func) (info->stream, ",");
1151 if (!open_braket && (operand->flags & ARC_OPERAND_BRAKET))
1153 (*info->fprintf_func) (info->stream, "[");
1161 /* Print the operand as directed by the flags. */
1162 if (operand->flags & ARC_OPERAND_IR)
1166 assert (value >=0 && value < 64);
1167 rname = arcExtMap_coreRegName (value);
1169 rname = regnames[value];
1170 (*info->fprintf_func) (info->stream, "%s", rname);
1171 if (operand->flags & ARC_OPERAND_TRUNCATE)
1173 rname = arcExtMap_coreRegName (value + 1);
1175 rname = regnames[value + 1];
1176 (*info->fprintf_func) (info->stream, "%s", rname);
1179 else if (operand->flags & ARC_OPERAND_LIMM)
1181 const char *rname = get_auxreg (opcode, value, isa_mask);
1183 if (rname && open_braket)
1184 (*info->fprintf_func) (info->stream, "%s", rname);
1187 (*info->fprintf_func) (info->stream, "%#x", value);
1188 if (info->insn_type == dis_branch
1189 || info->insn_type == dis_jsr)
1190 info->target = (bfd_vma) value;
1193 else if (operand->flags & ARC_OPERAND_PCREL)
1196 if (info->flags & INSN_HAS_RELOC)
1198 (*info->print_address_func) ((memaddr & ~3) + value, info);
1200 info->target = (bfd_vma) (memaddr & ~3) + value;
1202 else if (operand->flags & ARC_OPERAND_SIGNED)
1204 const char *rname = get_auxreg (opcode, value, isa_mask);
1205 if (rname && open_braket)
1206 (*info->fprintf_func) (info->stream, "%s", rname);
1208 (*info->fprintf_func) (info->stream, "%d", value);
1210 else if (operand->flags & ARC_OPERAND_ADDRTYPE)
1212 const char *addrtype = get_addrtype (value);
1213 (*info->fprintf_func) (info->stream, "%s", addrtype);
1214 /* A colon follow an address type. */
1219 if (operand->flags & ARC_OPERAND_TRUNCATE
1220 && !(operand->flags & ARC_OPERAND_ALIGNED32)
1221 && !(operand->flags & ARC_OPERAND_ALIGNED16)
1222 && value > 0 && value <= 14)
1223 (*info->fprintf_func) (info->stream, "r13-%s",
1224 regnames[13 + value - 1]);
1227 const char *rname = get_auxreg (opcode, value, isa_mask);
1228 if (rname && open_braket)
1229 (*info->fprintf_func) (info->stream, "%s", rname);
1231 (*info->fprintf_func) (info->stream, "%#x", value);
1241 arc_get_disassembler (bfd *abfd)
1243 /* BFD my be absent, if opcodes is invoked from the debugger that
1244 has connected to remote target and doesn't have an ELF file. */
1247 /* Read the extension insns and registers, if any. */
1248 build_ARC_extmap (abfd);
1254 return print_insn_arc;
1257 /* Disassemble ARC instructions. Used by debugger. */
1260 arcAnalyzeInstr (bfd_vma memaddr,
1261 struct disassemble_info *info)
1263 struct arcDisState ret;
1264 memset (&ret, 0, sizeof (struct arcDisState));
1266 ret.instructionLen = print_insn_arc (memaddr, info);
1269 ret.words[0] = insn[0];
1270 ret.words[1] = insn[1];
1272 ret.coreRegName = _coreRegName;
1273 ret.auxRegName = _auxRegName;
1274 ret.condCodeName = _condCodeName;
1275 ret.instName = _instName;
1282 print_arc_disassembler_options (FILE *stream)
1284 fprintf (stream, _("\n\
1285 The following ARC specific disassembler options are supported for use \n\
1286 with -M switch (multiple options should be separated by commas):\n"));
1288 fprintf (stream, _("\
1289 dsp Recognize DSP instructions.\n"));
1290 fprintf (stream, _("\
1291 spfp Recognize FPX SP instructions.\n"));
1292 fprintf (stream, _("\
1293 dpfp Recognize FPX DP instructions.\n"));
1294 fprintf (stream, _("\
1295 quarkse_em Recognize FPU QuarkSE-EM instructions.\n"));
1296 fprintf (stream, _("\
1297 fpuda Recognize double assist FPU instructions.\n"));
1298 fprintf (stream, _("\
1299 fpus Recognize single precision FPU instructions.\n"));
1300 fprintf (stream, _("\
1301 fpud Recognize double precision FPU instructions.\n"));
1306 eval: (c-set-style "gnu")