1 /* Instruction printing code for the ARC.
2 Copyright 1994, 1995, 1997, 1998, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Doug Evans (dje@cygnus.com).
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21 #include <libiberty.h>
23 #include "opcode/arc.h"
38 #define BIT(word,n) ((word) & (1 << n))
39 #define BITS(word,s,e) (((word) << (31 - e)) >> (s + (31 - e)))
40 #define OPCODE(word) (BITS ((word), 27, 31))
41 #define FIELDA(word) (BITS ((word), 21, 26))
42 #define FIELDB(word) (BITS ((word), 15, 20))
43 #define FIELDC(word) (BITS ((word), 9, 14))
45 /* FIELD D is signed in all of its uses, so we make sure argument is
46 treated as signed for bit shifting purposes: */
47 #define FIELDD(word) (BITS (((signed int)word), 0, 8))
49 #define PUT_NEXT_WORD_IN(a) \
52 if (is_limm == 1 && !NEXT_WORD (1)) \
53 mwerror (state, _("Illegal limm reference in last instruction!\n")); \
54 a = state->words[1]; \
58 #define CHECK_FLAG_COND_NULLIFY() \
63 flag = BIT (state->words[0], 8); \
64 state->nullifyMode = BITS (state->words[0], 5, 6); \
65 cond = BITS (state->words[0], 0, 4); \
70 #define CHECK_COND() \
74 cond = BITS (state->words[0], 0, 4); \
78 #define CHECK_FIELD(field) \
85 PUT_NEXT_WORD_IN (field); \
88 else if (field > 60) \
92 flag = (field == 61); \
93 field = FIELDD (state->words[0]); \
98 #define CHECK_FIELD_A() \
101 fieldA = FIELDA(state->words[0]); \
110 #define CHECK_FIELD_B() \
113 fieldB = FIELDB (state->words[0]); \
114 CHECK_FIELD (fieldB); \
118 #define CHECK_FIELD_C() \
121 fieldC = FIELDC (state->words[0]); \
122 CHECK_FIELD (fieldC); \
126 #define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257))
127 #define IS_REG(x) (field##x##isReg)
128 #define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT(x,"[","]","","")
129 #define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT(x,"",",[","",",[")
130 #define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT(x,",","]",",","]")
131 #define WRITE_FORMAT_x_RB(x) WRITE_FORMAT(x,"","]","","]")
132 #define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT(x,",","",",","")
133 #define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT(x,"",",","",",")
134 #define WRITE_FORMAT_x(x) WRITE_FORMAT(x,"","","","")
135 #define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString, \
136 (IS_REG (x) ? cb1"%r"ca1 : \
137 usesAuxReg ? cb"%a"ca : \
138 IS_SMALL (x) ? cb"%d"ca : cb"%h"ca))
139 #define WRITE_FORMAT_RB() strcat (formatString, "]")
140 #define WRITE_COMMENT(str) (state->comm[state->commNum++] = (str))
141 #define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT ("nop");
143 #define NEXT_WORD(x) (offset += 4, state->words[x])
145 #define add_target(x) (state->targets[state->tcnt++] = (x))
147 static char comment_prefix[] = "\t; ";
150 core_reg_name (state, val)
151 struct arcDisState * state;
154 if (state->coreRegName)
155 return (*state->coreRegName)(state->_this, val);
160 aux_reg_name (state, val)
161 struct arcDisState * state;
164 if (state->auxRegName)
165 return (*state->auxRegName)(state->_this, val);
170 cond_code_name (state, val)
171 struct arcDisState * state;
174 if (state->condCodeName)
175 return (*state->condCodeName)(state->_this, val);
180 instruction_name (state, op1, op2, flags)
181 struct arcDisState * state;
187 return (*state->instName)(state->_this, op1, op2, flags);
193 struct arcDisState * state;
197 (*state->err)(state->_this, (msg));
201 post_address (state, addr)
202 struct arcDisState * state;
205 static char id[3 * ARRAY_SIZE (state->addresses)];
206 int j, i = state->acnt;
208 if (i < ((int) ARRAY_SIZE (state->addresses)))
210 state->addresses[i] = addr;
224 struct arcDisState * state,
231 int size, leading_zero, regMap[2];
235 va_start (ap, format);
248 goto DOCOMM; /* (return) */
272 leading_zero = 1; /* e.g. %08x */
273 while (*p >= '0' && *p <= '9')
275 size = size * 10 + *p - '0';
280 #define inc_bp() bp = bp + strlen (bp)
284 unsigned u = va_arg (ap, int);
286 /* Hex. We can change the format to 0x%08x in
287 one place, here, if we wish.
288 We add underscores for easy reading. */
290 sprintf (bp, "0x%x_%04x", u >> 16, u & 0xffff);
292 sprintf (bp, "0x%x", u);
298 int val = va_arg (ap, int);
302 sprintf (bp, "%0*x", size, val);
304 sprintf (bp, "%*x", size, val);
306 sprintf (bp, "%x", val);
312 int val = va_arg (ap, int);
315 sprintf (bp, "%*d", size, val);
317 sprintf (bp, "%d", val);
324 int val = va_arg (ap, int);
326 #define REG2NAME(num, name) case num: sprintf (bp, ""name); \
327 regMap[(num < 32) ? 0 : 1] |= 1 << (num - ((num < 32) ? 0 : 32)); break;
334 REG2NAME (29, "ilink1");
335 REG2NAME (30, "ilink2");
336 REG2NAME (31, "blink");
337 REG2NAME (60, "lp_count");
342 ext = core_reg_name (state, val);
344 sprintf (bp, "%s", ext);
346 sprintf (bp,"r%d",val);
356 int val = va_arg (ap, int);
358 #define AUXREG2NAME(num, name) case num: sprintf (bp,name); break;
362 AUXREG2NAME (0x0, "status");
363 AUXREG2NAME (0x1, "semaphore");
364 AUXREG2NAME (0x2, "lp_start");
365 AUXREG2NAME (0x3, "lp_end");
366 AUXREG2NAME (0x4, "identity");
367 AUXREG2NAME (0x5, "debug");
372 ext = aux_reg_name (state, val);
374 sprintf (bp, "%s", ext);
376 my_sprintf (state, bp, "%h", val);
386 sprintf (bp, "%s", va_arg (ap, char *));
392 fprintf (stderr, "?? format %c\n", p[-1]);
401 write_comments_(state, shimm, is_limm, limm_value)
402 struct arcDisState * state;
407 if (state->commentBuffer != 0)
413 const char *name = post_address (state, limm_value + shimm);
416 WRITE_COMMENT (name);
418 for (i = 0; i < state->commNum; i++)
421 strcpy (state->commentBuffer, comment_prefix);
423 strcat (state->commentBuffer, ", ");
424 strncat (state->commentBuffer, state->comm[i], sizeof (state->commentBuffer));
429 #define write_comments2(x) write_comments_(state, x, is_limm, limm_value)
430 #define write_comments() write_comments2(0)
432 static const char *condName[] = {
434 "" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" ,
435 "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz"
439 write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend, addrWriteBack, directMem)
440 struct arcDisState * state;
441 const char * instrName;
443 int condCodeIsPartOfName;
449 strcpy (state->instrBuffer, instrName);
455 if (!condCodeIsPartOfName)
456 strcat (state->instrBuffer, ".");
461 cc = cond_code_name (state, cond);
466 strcat (state->instrBuffer, cc);
470 strcat (state->instrBuffer, ".f");
472 switch (state->nullifyMode)
475 strcat (state->instrBuffer, ".d");
477 case BR_exec_when_jump:
478 strcat (state->instrBuffer, ".jd");
483 strcat (state->instrBuffer, ".x");
486 strcat (state->instrBuffer, ".a");
489 strcat (state->instrBuffer, ".di");
492 #define write_instr_name() \
495 write_instr_name_(state, instrName,cond, condCodeIsPartOfName, \
496 flag, signExtend, addrWriteBack, directMem); \
497 formatString[0] = '\0'; \
502 op_LD0 = 0, op_LD1 = 1, op_ST = 2, op_3 = 3,
503 op_BC = 4, op_BLC = 5, op_LPC = 6, op_JC = 7,
504 op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11,
505 op_AND = 12, op_OR = 13, op_BIC = 14, op_XOR = 15
508 extern disassemble_info tm_print_insn_info;
511 dsmOneArcInst (addr, state)
513 struct arcDisState * state;
515 int condCodeIsPartOfName = 0;
517 const char * instrName;
531 int addrWriteBack = 0;
538 char formatString[60];
540 state->instructionLen = 4;
541 state->nullifyMode = BR_exec_when_no_jump;
545 state->_mem_load = 0;
546 state->_ea_present = 0;
547 state->_load_len = 0;
548 state->ea_reg1 = no_reg;
549 state->ea_reg2 = no_reg;
555 state->_opcode = OPCODE (state->words[0]);
557 decodingClass = 0; /* default! */
559 condCodeIsPartOfName=0;
563 state->flow = noflow;
566 if (state->commentBuffer)
567 state->commentBuffer[0] = '\0';
569 switch (state->_opcode)
572 switch (BITS (state->words[0],1,2))
576 state->_load_len = 4;
580 state->_load_len = 1;
584 state->_load_len = 2;
587 instrName = "??? (0[3])";
588 state->flow = invalid_instr;
595 if (BIT (state->words[0],13))
602 switch (BITS (state->words[0],10,11))
606 state->_load_len = 4;
610 state->_load_len = 1;
614 state->_load_len = 2;
617 instrName = "??? (1[3])";
618 state->flow = invalid_instr;
626 if (BIT (state->words[0],25))
633 switch (BITS (state->words[0],22,23))
645 instrName = "??? (2[3])";
646 state->flow = invalid_instr;
654 decodingClass = 1; /* default for opcode 3... */
655 switch (FIELDC (state->words[0]))
688 switch( FIELDD (state->words[0]) )
701 state->flow=invalid_instr;
707 /* ARC Extension Library Instructions
708 NOTE: We assume that extension codes are these instrs. */
710 instrName = instruction_name (state,
712 FIELDC (state->words[0]),
717 state->flow = invalid_instr;
719 if (flags & IGNORE_FIRST_OPD)
736 if (BITS (state->words[0],9,9))
747 condCodeIsPartOfName = 1;
748 decodingClass = ((state->_opcode == op_JC) ? 4 : 3);
755 repeatsOp = (FIELDC (state->words[0]) == FIELDB (state->words[0]));
758 switch (state->_opcode)
761 instrName = (repeatsOp ? "asl" : "add");
764 instrName = (repeatsOp ? "rlc" : "adc");
767 instrName = (repeatsOp ? "mov" : "and");
772 case op_SUB: instrName = "sub";
774 case op_SBC: instrName = "sbc";
776 case op_OR: instrName = "or";
778 case op_BIC: instrName = "bic";
782 if (state->words[0] == 0x7fffffff)
784 /* nop encoded as xor -1, -1, -1 */
793 instrName = instruction_name (state,state->_opcode,0,&flags);
794 /* if (instrName) printf("FLAGS=0x%x\n", flags); */
798 state->flow=invalid_instr;
800 if (flags & IGNORE_FIRST_OPD)
805 fieldAisReg = fieldBisReg = fieldCisReg = 1; /* Assume regs for now. */
806 flag = cond = is_shimm = is_limm = 0;
807 state->nullifyMode = BR_exec_when_no_jump; /* 0 */
808 signExtend = addrWriteBack = directMem = 0;
811 switch (decodingClass)
818 CHECK_FLAG_COND_NULLIFY ();
824 WRITE_FORMAT_COMMA_x (B);
826 WRITE_FORMAT_COMMA_x (C);
827 WRITE_NOP_COMMENT ();
828 my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
834 WRITE_FORMAT_COMMA_x (C);
835 my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldC);
843 CHECK_FLAG_COND_NULLIFY ();
849 WRITE_FORMAT_COMMA_x (B);
850 WRITE_NOP_COMMENT ();
851 my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB);
856 my_sprintf (state, state->operandBuffer, formatString, fieldB);
863 CHECK_FLAG_COND_NULLIFY ();
864 flag = 0; /* this is the FLAG instruction -- it's redundant */
868 my_sprintf (state, state->operandBuffer, formatString, fieldB);
873 fieldA = BITS (state->words[0],7,26) << 2;
874 fieldA = (fieldA << 10) >> 10; /* make it signed */
876 CHECK_FLAG_COND_NULLIFY ();
880 /* This address could be a label we know. Convert it. */
881 if (state->_opcode != op_LPC /* LP */)
883 add_target (fieldA); /* For debugger. */
884 state->flow = state->_opcode == op_BLC /* BL */
887 /* indirect calls are achieved by "lr blink,[status];
888 lr dest<- func addr; j [dest]" */
891 strcat (formatString, "%s"); /* address/label name */
892 my_sprintf (state, state->operandBuffer, formatString, post_address (state, fieldA));
897 /* For op_JC -- jump to address specified.
898 Also covers jump and link--bit 9 of the instr. word
899 selects whether linked, thus "is_linked" is set above. */
902 CHECK_FLAG_COND_NULLIFY ();
907 fieldA = (fieldB >> 25) & 0x7F; /* flags */
908 fieldB = (fieldB & 0xFFFFFF) << 2;
909 state->flow = is_linked ? direct_call : direct_jump;
911 /* screwy JLcc requires .jd mode to execute correctly
912 * but we pretend it is .nd (no delay slot). */
913 if (is_linked && state->nullifyMode == BR_exec_when_jump)
914 state->nullifyMode = BR_exec_when_no_jump;
918 state->flow = is_linked ? indirect_call : indirect_jump;
919 /* We should also treat this as indirect call if NOT linked
920 * but the preceding instruction was a "lr blink,[status]"
921 * and we have a delay slot with "add blink,blink,2".
922 * For now we can't detect such. */
923 state->register_for_indirect_jump = fieldB;
927 strcat (formatString,
928 IS_REG (B) ? "[%r]" : "%s"); /* address/label name */
932 WRITE_FORMAT_COMMA_x (A);
935 my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA);
937 my_sprintf (state, state->operandBuffer, formatString,
938 post_address (state, fieldB), fieldA);
944 B and C can be regs, or one (both?) can be limm. */
949 printf ("5:b reg %d %d c reg %d %d \n",
950 fieldBisReg,fieldB,fieldCisReg,fieldC);
952 state->_ea_present = 1;
954 state->ea_reg1 = fieldB;
956 state->_offset += fieldB;
958 state->ea_reg2 = fieldC;
960 state->_offset += fieldC;
961 state->_mem_load = 1;
963 directMem = BIT (state->words[0],5);
964 addrWriteBack = BIT (state->words[0],3);
965 signExtend = BIT (state->words[0],0);
968 WRITE_FORMAT_x_COMMA_LB(A);
969 if (fieldBisReg || fieldB != 0)
970 WRITE_FORMAT_x_COMMA (B);
974 WRITE_FORMAT_x_RB (C);
975 my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
980 /* LD instruction. */
983 fieldC = FIELDD (state->words[0]);
986 printf ("6:b reg %d %d c 0x%x \n",
987 fieldBisReg, fieldB, fieldC);
988 state->_ea_present = 1;
989 state->_offset = fieldC;
990 state->_mem_load = 1;
992 state->ea_reg1 = fieldB;
993 /* field B is either a shimm (same as fieldC) or limm (different!)
994 Say ea is not present, so only one of us will do the name lookup. */
996 state->_offset += fieldB, state->_ea_present = 0;
998 directMem = BIT (state->words[0],14);
999 addrWriteBack = BIT (state->words[0],12);
1000 signExtend = BIT (state->words[0],9);
1002 write_instr_name ();
1003 WRITE_FORMAT_x_COMMA_LB (A);
1006 fieldB = state->_offset;
1007 WRITE_FORMAT_x_RB (B);
1012 if (fieldC != 0 && !BIT (state->words[0],13))
1015 WRITE_FORMAT_COMMA_x_RB (C);
1020 my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
1025 /* ST instruction. */
1028 fieldA = FIELDD(state->words[0]); /* shimm */
1031 if (dbg) printf("7:b reg %d %x off %x\n",
1032 fieldBisReg,fieldB,fieldA);
1033 state->_ea_present = 1;
1034 state->_offset = fieldA;
1036 state->ea_reg1 = fieldB;
1037 /* field B is either a shimm (same as fieldA) or limm (different!)
1038 Say ea is not present, so only one of us will do the name lookup.
1039 (for is_limm we do the name translation here). */
1041 state->_offset += fieldB, state->_ea_present = 0;
1043 directMem = BIT(state->words[0],26);
1044 addrWriteBack = BIT(state->words[0],24);
1047 WRITE_FORMAT_x_COMMA_LB(C);
1051 fieldB = state->_offset;
1052 WRITE_FORMAT_x_RB(B);
1057 if (fieldBisReg && fieldA != 0)
1060 WRITE_FORMAT_COMMA_x_RB(A);
1065 my_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB, fieldA);
1066 write_comments2(fieldA);
1069 /* SR instruction */
1074 WRITE_FORMAT_x_COMMA_LB(C);
1075 /* Try to print B as an aux reg if it is not a core reg. */
1079 my_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB);
1085 state->operandBuffer[0] = '\0';
1089 /* LR instruction */
1094 WRITE_FORMAT_x_COMMA_LB(A);
1095 /* Try to print B as an aux reg if it is not a core reg. */
1099 my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB);
1106 state->operandBuffer[0] = '\0';
1110 mwerror (state, "Bad decoding class in ARC disassembler");
1114 state->_cond = cond;
1115 return state->instructionLen = offset;
1119 /* Returns the name the user specified core extension register. */
1121 _coreRegName(arg, regval)
1122 void * arg ATTRIBUTE_UNUSED;
1125 return arcExtMap_coreRegName (regval);
1128 /* Returns the name the user specified AUX extension register. */
1130 _auxRegName(void *_this ATTRIBUTE_UNUSED, int regval)
1132 return arcExtMap_auxRegName(regval);
1136 /* Returns the name the user specified condition code name. */
1138 _condCodeName(void *_this ATTRIBUTE_UNUSED, int regval)
1140 return arcExtMap_condCodeName(regval);
1143 /* Returns the name the user specified extension instruction. */
1145 _instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags)
1147 return arcExtMap_instName(majop, minop, flags);
1150 /* Decode an instruction returning the size of the instruction
1151 in bytes or zero if unrecognized. */
1153 decodeInstr (address, info)
1154 bfd_vma address; /* Address of this instruction. */
1155 disassemble_info * info;
1159 struct arcDisState s; /* ARC Disassembler state */
1160 void *stream = info->stream; /* output stream */
1161 fprintf_ftype func = info->fprintf_func;
1164 memset (&s, 0, sizeof(struct arcDisState));
1166 /* read first instruction */
1167 status = (*info->read_memory_func) (address, buffer, 4, info);
1170 (*info->memory_error_func) (status, address, info);
1173 if (info->endian == BFD_ENDIAN_LITTLE)
1174 s.words[0] = bfd_getl32(buffer);
1176 s.words[0] = bfd_getb32(buffer);
1177 /* always read second word in case of limm */
1179 /* we ignore the result since last insn may not have a limm */
1180 status = (*info->read_memory_func) (address + 4, buffer, 4, info);
1181 if (info->endian == BFD_ENDIAN_LITTLE)
1182 s.words[1] = bfd_getl32(buffer);
1184 s.words[1] = bfd_getb32(buffer);
1187 s.coreRegName = _coreRegName;
1188 s.auxRegName = _auxRegName;
1189 s.condCodeName = _condCodeName;
1190 s.instName = _instName;
1193 bytes = dsmOneArcInst(address, (void *)&s);
1195 /* display the disassembly instruction */
1196 (*func) (stream, "%08x ", s.words[0]);
1197 (*func) (stream, " ");
1199 (*func) (stream, "%-10s ", s.instrBuffer);
1201 if (__TRANSLATION_REQUIRED(s))
1203 bfd_vma addr = s.addresses[s.operandBuffer[1] - '0'];
1204 (*info->print_address_func) ((bfd_vma) addr, info);
1205 (*func) (stream, "\n");
1208 (*func) (stream, "%s",s.operandBuffer);
1209 return s.instructionLen;
1212 /* Return the print_insn function to use.
1213 Side effect: load (possibly empty) extension section */
1216 arc_get_disassembler (void *ptr)
1219 build_ARC_extmap (ptr);