1 /* Instruction printing code for the ARC.
2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
27 #include "opcode/arc.h"
32 #include "libiberty.h"
35 /* Structure used to iterate over, and extract the values for, operands of
38 struct arc_operand_iterator
40 /* The complete instruction value to extract operands from. */
41 unsigned long long insn;
43 /* The LIMM if this is being tracked separately. This field is only
44 valid if we find the LIMM operand in the operand list. */
47 /* The opcode this iterator is operating on. */
48 const struct arc_opcode *opcode;
50 /* The index into the opcodes operand index list. */
51 const unsigned char *opidx;
54 /* A private data used by ARC decoder. */
55 struct arc_disassemble_info
57 /* The current disassembled arc opcode. */
58 const struct arc_opcode *opcode;
60 /* Instruction length w/o limm field. */
63 /* TRUE if we have limm. */
66 /* LIMM value, if exists. */
69 /* Condition code, if exists. */
70 unsigned condition_code;
73 unsigned writeback_mode;
75 /* Number of operands. */
76 unsigned operands_count;
78 struct arc_insn_operand operands[MAX_INSN_ARGS];
81 /* Globals variables. */
83 static const char * const regnames[64] =
85 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
86 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
87 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
88 "r24", "r25", "gp", "fp", "sp", "ilink", "r30", "blink",
90 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
91 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
92 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
93 "r56", "r57", "ACCL", "ACCH", "lp_count", "rezerved", "LIMM", "pcl"
96 static const char * const addrtypenames[ARC_NUM_ADDRTYPES] =
98 "bd", "jid", "lbd", "mbd", "sd", "sm", "xa", "xd",
99 "cd", "cbd", "cjid", "clbd", "cm", "csd", "cxa", "cxd"
102 static int addrtypenames_max = ARC_NUM_ADDRTYPES - 1;
104 static const char * const addrtypeunknown = "unknown";
106 /* This structure keeps track which instruction class(es)
107 should be ignored durring disassembling. */
109 typedef struct skipclass
111 insn_class_t insn_class;
112 insn_subclass_t subclass;
113 struct skipclass *nxt;
114 } skipclass_t, *linkclass;
116 /* Intial classes of instructions to be consider first when
118 static linkclass decodelist = NULL;
120 /* ISA mask value enforced via disassembler info options. ARC_OPCODE_NONE
121 value means that no CPU is enforced. */
123 static unsigned enforced_isa_mask = ARC_OPCODE_NONE;
125 /* Macros section. */
128 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
130 # define pr_debug(fmt, args...)
133 #define ARRANGE_ENDIAN(info, buf) \
134 (info->endian == BFD_ENDIAN_LITTLE ? bfd_getm32 (bfd_getl32 (buf)) \
137 #define BITS(word,s,e) (((word) << (sizeof (word) * 8 - 1 - e)) >> \
138 (s + (sizeof (word) * 8 - 1 - e)))
139 #define OPCODE_32BIT_INSN(word) (BITS ((word), 27, 31))
141 /* Functions implementation. */
143 /* Initialize private data. */
145 init_arc_disasm_info (struct disassemble_info *info)
147 struct arc_disassemble_info *arc_infop
148 = calloc (sizeof (*arc_infop), 1);
150 if (arc_infop == NULL)
153 info->private_data = arc_infop;
157 /* Add a new element to the decode list. */
160 add_to_decodelist (insn_class_t insn_class,
161 insn_subclass_t subclass)
163 linkclass t = (linkclass) xmalloc (sizeof (skipclass_t));
165 t->insn_class = insn_class;
166 t->subclass = subclass;
171 /* Return TRUE if we need to skip the opcode from being
175 skip_this_opcode (const struct arc_opcode *opcode)
177 linkclass t = decodelist;
179 /* Check opcode for major 0x06, return if it is not in. */
180 if (arc_opcode_len (opcode) == 4
181 && OPCODE_32BIT_INSN (opcode->opcode) != 0x06)
184 /* or not a known truble class. */
185 switch (opcode->insn_class)
196 if ((t->insn_class == opcode->insn_class)
197 && (t->subclass == opcode->subclass))
206 bfd_getm32 (unsigned int data)
210 value = ((data & 0xff00) | (data & 0xff)) << 16;
211 value |= ((data & 0xff0000) | (data & 0xff000000)) >> 16;
216 special_flag_p (const char *opname,
219 const struct arc_flag_special *flg_spec;
220 unsigned i, j, flgidx;
222 for (i = 0; i < arc_num_flag_special; i++)
224 flg_spec = &arc_flag_special_cases[i];
226 if (strcmp (opname, flg_spec->name))
229 /* Found potential special case instruction. */
232 flgidx = flg_spec->flags[j];
234 break; /* End of the array. */
236 if (strcmp (flgname, arc_flag_operands[flgidx].name) == 0)
243 /* Find opcode from ARC_TABLE given the instruction described by INSN and
244 INSNLEN. The ISA_MASK restricts the possible matches in ARC_TABLE. */
246 static const struct arc_opcode *
247 find_format_from_table (struct disassemble_info *info,
248 const struct arc_opcode *arc_table,
249 unsigned long long insn,
250 unsigned int insn_len,
252 bfd_boolean *has_limm,
253 bfd_boolean overlaps)
256 const struct arc_opcode *opcode = NULL;
257 const struct arc_opcode *t_op = NULL;
258 const unsigned char *opidx;
259 const unsigned char *flgidx;
260 bfd_boolean warn_p = FALSE;
264 bfd_boolean invalid = FALSE;
266 opcode = &arc_table[i++];
268 if (!(opcode->cpu & isa_mask))
271 if (arc_opcode_len (opcode) != (int) insn_len)
274 if ((insn & opcode->mask) != opcode->opcode)
279 /* Possible candidate, check the operands. */
280 for (opidx = opcode->operands; *opidx; opidx++)
283 const struct arc_operand *operand = &arc_operands[*opidx];
285 if (operand->flags & ARC_OPERAND_FAKE)
288 if (operand->extract)
289 value = (*operand->extract) (insn, &invalid);
291 value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
293 /* Check for LIMM indicator. If it is there, then make sure
294 we pick the right format. */
295 limmind = (isa_mask & ARC_OPCODE_ARCV2) ? 0x1E : 0x3E;
296 if (operand->flags & ARC_OPERAND_IR
297 && !(operand->flags & ARC_OPERAND_LIMM))
299 if ((value == 0x3E && insn_len == 4)
300 || (value == limmind && insn_len == 2))
307 if (operand->flags & ARC_OPERAND_LIMM
308 && !(operand->flags & ARC_OPERAND_DUPLICATE))
312 /* Check the flags. */
313 for (flgidx = opcode->flags; *flgidx; flgidx++)
315 /* Get a valid flag class. */
316 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
317 const unsigned *flgopridx;
318 int foundA = 0, foundB = 0;
321 /* Check first the extensions. */
322 if (cl_flags->flag_class & F_CLASS_EXTEND)
324 value = (insn & 0x1F);
325 if (arcExtMap_condCodeName (value))
329 /* Check for the implicit flags. */
330 if (cl_flags->flag_class & F_CLASS_IMPLICIT)
333 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
335 const struct arc_flag_operand *flg_operand =
336 &arc_flag_operands[*flgopridx];
338 value = (insn >> flg_operand->shift)
339 & ((1 << flg_operand->bits) - 1);
340 if (value == flg_operand->code)
346 if (!foundA && foundB)
361 if (skip_this_opcode (opcode))
365 /* The instruction is valid. */
368 while (opcode->mask);
372 info->fprintf_func (info->stream,
373 _("\nWarning: disassembly may be wrong due to "
374 "guessed opcode class choice.\n"
375 "Use -M<class[,class]> to select the correct "
376 "opcode class(es).\n\t\t\t\t"));
383 /* Find opcode for INSN, trying various different sources. The instruction
384 length in INSN_LEN will be updated if the instruction requires a LIMM
387 A pointer to the opcode is placed into OPCODE_RESULT, and ITER is
388 initialised, ready to iterate over the operands of the found opcode. If
389 the found opcode requires a LIMM then the LIMM value will be loaded into a
392 This function returns TRUE in almost all cases, FALSE is reserved to
393 indicate an error (failing to find an opcode is not an error) a returned
394 result of FALSE would indicate that the disassembler can't continue.
396 If no matching opcode is found then the returned result will be TRUE, the
397 value placed into OPCODE_RESULT will be NULL, ITER will be undefined, and
398 INSN_LEN will be unchanged.
400 If a matching opcode is found, then the returned result will be TRUE, the
401 opcode pointer is placed into OPCODE_RESULT, INSN_LEN will be increased by
402 4 if the instruction requires a LIMM, and the LIMM value will have been
403 loaded into a field of ITER. Finally, ITER will have been initialised so
404 that calls to OPERAND_ITERATOR_NEXT will iterate over the opcode's
408 find_format (bfd_vma memaddr,
409 unsigned long long insn,
410 unsigned int * insn_len,
412 struct disassemble_info * info,
413 const struct arc_opcode ** opcode_result,
414 struct arc_operand_iterator * iter)
416 const struct arc_opcode *opcode = NULL;
417 bfd_boolean needs_limm;
418 const extInstruction_t *einsn, *i;
420 struct arc_disassemble_info *arc_infop = info->private_data;
422 /* First, try the extension instructions. */
425 einsn = arcExtMap_insn (OPCODE_32BIT_INSN (insn), insn);
426 for (i = einsn; (i != NULL) && (opcode == NULL); i = i->next)
428 const char *errmsg = NULL;
430 opcode = arcExtMap_genOpcode (i, isa_mask, &errmsg);
433 (*info->fprintf_func) (info->stream, "\
434 An error occured while generating the extension instruction operations");
435 *opcode_result = NULL;
439 opcode = find_format_from_table (info, opcode, insn, *insn_len,
440 isa_mask, &needs_limm, FALSE);
444 /* Then, try finding the first match in the opcode table. */
446 opcode = find_format_from_table (info, arc_opcodes, insn, *insn_len,
447 isa_mask, &needs_limm, TRUE);
449 if (needs_limm && opcode != NULL)
454 status = (*info->read_memory_func) (memaddr + *insn_len, buffer,
462 limm = ARRANGE_ENDIAN (info, buffer);
471 iter->opcode = opcode;
472 iter->opidx = opcode->operands;
475 *opcode_result = opcode;
477 /* Update private data. */
478 arc_infop->opcode = opcode;
479 arc_infop->limm = (needs_limm) ? limm : 0;
480 arc_infop->limm_p = needs_limm;
486 print_flags (const struct arc_opcode *opcode,
487 unsigned long long *insn,
488 struct disassemble_info *info)
490 const unsigned char *flgidx;
492 struct arc_disassemble_info *arc_infop = info->private_data;
494 /* Now extract and print the flags. */
495 for (flgidx = opcode->flags; *flgidx; flgidx++)
497 /* Get a valid flag class. */
498 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
499 const unsigned *flgopridx;
501 /* Check first the extensions. */
502 if (cl_flags->flag_class & F_CLASS_EXTEND)
505 value = (insn[0] & 0x1F);
507 name = arcExtMap_condCodeName (value);
510 (*info->fprintf_func) (info->stream, ".%s", name);
515 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
517 const struct arc_flag_operand *flg_operand =
518 &arc_flag_operands[*flgopridx];
520 /* Implicit flags are only used for the insn decoder. */
521 if (cl_flags->flag_class & F_CLASS_IMPLICIT)
523 if (cl_flags->flag_class & F_CLASS_COND)
524 arc_infop->condition_code = flg_operand->code;
525 else if (cl_flags->flag_class & F_CLASS_WB)
526 arc_infop->writeback_mode = flg_operand->code;
527 else if (cl_flags->flag_class & F_CLASS_ZZ)
528 info->data_size = flg_operand->code;
532 if (!flg_operand->favail)
535 value = (insn[0] >> flg_operand->shift)
536 & ((1 << flg_operand->bits) - 1);
537 if (value == flg_operand->code)
539 /* FIXME!: print correctly nt/t flag. */
540 if (!special_flag_p (opcode->name, flg_operand->name))
541 (*info->fprintf_func) (info->stream, ".");
542 else if (info->insn_type == dis_dref)
544 switch (flg_operand->name[0])
558 if (flg_operand->name[0] == 'd'
559 && flg_operand->name[1] == 0)
560 info->branch_delay_insns = 1;
562 /* Check if it is a conditional flag. */
563 if (cl_flags->flag_class & F_CLASS_COND)
565 if (info->insn_type == dis_jsr)
566 info->insn_type = dis_condjsr;
567 else if (info->insn_type == dis_branch)
568 info->insn_type = dis_condbranch;
569 arc_infop->condition_code = flg_operand->code;
572 /* Check for the write back modes. */
573 if (cl_flags->flag_class & F_CLASS_WB)
574 arc_infop->writeback_mode = flg_operand->code;
576 (*info->fprintf_func) (info->stream, "%s", flg_operand->name);
583 get_auxreg (const struct arc_opcode *opcode,
589 const struct arc_aux_reg *auxr = &arc_aux_regs[0];
591 if (opcode->insn_class != AUXREG)
594 name = arcExtMap_auxRegName (value);
598 for (i = 0; i < arc_num_aux_regs; i++, auxr++)
600 if (!(auxr->cpu & isa_mask))
603 if (auxr->subclass != NONE)
606 if (auxr->address == value)
612 /* Convert a value representing an address type to a string used to refer to
613 the address type in assembly code. */
616 get_addrtype (int value)
618 if (value < 0 || value > addrtypenames_max)
619 return addrtypeunknown;
621 return addrtypenames[value];
624 /* Calculate the instruction length for an instruction starting with MSB
625 and LSB, the most and least significant byte. The ISA_MASK is used to
626 filter the instructions considered to only those that are part of the
627 current architecture.
629 The instruction lengths are calculated from the ARC_OPCODE table, and
630 cached for later use. */
633 arc_insn_length (bfd_byte msb, bfd_byte lsb, struct disassemble_info *info)
635 bfd_byte major_opcode = msb >> 3;
639 case bfd_mach_arc_arc700:
640 /* The nps400 extension set requires this special casing of the
641 instruction length calculation. Right now this is not causing any
642 problems as none of the known extensions overlap in opcode space,
643 but, if they ever do then we might need to start carrying
644 information around in the elf about which extensions are in use. */
645 if (major_opcode == 0xb)
647 bfd_byte minor_opcode = lsb & 0x1f;
649 if (minor_opcode < 4)
651 else if (minor_opcode == 0x10 || minor_opcode == 0x11)
654 if (major_opcode == 0xa)
659 case bfd_mach_arc_arc600:
660 return (major_opcode > 0xb) ? 2 : 4;
663 case bfd_mach_arc_arcv2:
664 return (major_opcode > 0x7) ? 2 : 4;
672 /* Extract and return the value of OPERAND from the instruction whose value
673 is held in the array INSN. */
676 extract_operand_value (const struct arc_operand *operand,
677 unsigned long long insn,
682 /* Read the limm operand, if required. */
683 if (operand->flags & ARC_OPERAND_LIMM)
684 /* The second part of the instruction value will have been loaded as
685 part of the find_format call made earlier. */
689 if (operand->extract)
690 value = (*operand->extract) (insn, (int *) NULL);
693 if (operand->flags & ARC_OPERAND_ALIGNED32)
695 value = (insn >> operand->shift)
696 & ((1 << (operand->bits - 2)) - 1);
701 value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
703 if (operand->flags & ARC_OPERAND_SIGNED)
705 int signbit = 1 << (operand->bits - 1);
706 value = (value ^ signbit) - signbit;
714 /* Find the next operand, and the operands value from ITER. Return TRUE if
715 there is another operand, otherwise return FALSE. If there is an
716 operand returned then the operand is placed into OPERAND, and the value
717 into VALUE. If there is no operand returned then OPERAND and VALUE are
721 operand_iterator_next (struct arc_operand_iterator *iter,
722 const struct arc_operand **operand,
725 if (*iter->opidx == 0)
731 *operand = &arc_operands[*iter->opidx];
732 *value = extract_operand_value (*operand, iter->insn, iter->limm);
738 /* Helper for parsing the options. */
741 parse_option (const char *option)
743 if (CONST_STRNEQ (option, "dsp"))
744 add_to_decodelist (DSP, NONE);
746 else if (CONST_STRNEQ (option, "spfp"))
747 add_to_decodelist (FLOAT, SPX);
749 else if (CONST_STRNEQ (option, "dpfp"))
750 add_to_decodelist (FLOAT, DPX);
752 else if (CONST_STRNEQ (option, "quarkse_em"))
754 add_to_decodelist (FLOAT, DPX);
755 add_to_decodelist (FLOAT, SPX);
756 add_to_decodelist (FLOAT, QUARKSE1);
757 add_to_decodelist (FLOAT, QUARKSE2);
760 else if (CONST_STRNEQ (option, "fpuda"))
761 add_to_decodelist (FLOAT, DPA);
763 else if (CONST_STRNEQ (option, "fpus"))
765 add_to_decodelist (FLOAT, SP);
766 add_to_decodelist (FLOAT, CVT);
769 else if (CONST_STRNEQ (option, "fpud"))
771 add_to_decodelist (FLOAT, DP);
772 add_to_decodelist (FLOAT, CVT);
775 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
778 #define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
779 { #NAME, ARC_OPCODE_ARC600, "ARC600" }
780 #define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
781 { #NAME, ARC_OPCODE_ARC700, "ARC700" }
782 #define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
783 { #NAME, ARC_OPCODE_ARCv2EM, "ARC EM" }
784 #define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
785 { #NAME, ARC_OPCODE_ARCv2HS, "ARC HS" }
786 #define ARC_CPU_TYPE_NONE \
789 /* A table of CPU names and opcode sets. */
790 static const struct cpu_type
798 #include "elf/arc-cpu.def"
801 /* Helper for parsing the CPU options. Accept any of the ARC architectures
802 values. OPTION should be a value passed to cpu=. */
805 parse_cpu_option (const char *option)
809 for (i = 0; cpu_types[i].name; ++i)
811 if (!strcasecmp (cpu_types[i].name, option))
813 return cpu_types[i].flags;
817 fprintf (stderr, _("Unrecognised disassembler CPU option: %s\n"), option);
818 return ARC_OPCODE_NONE;
821 /* Go over the options list and parse it. */
824 parse_disassembler_options (const char *options)
829 /* Disassembler might be reused for difference CPU's, and cpu option set for
830 the first one shouldn't be applied to second (which might not have
831 explicit cpu in its options. Therefore it is required to reset enforced
832 CPU when new options are being parsed. */
833 enforced_isa_mask = ARC_OPCODE_NONE;
837 /* Skip empty options. */
844 /* A CPU option? Cannot use STRING_COMMA_LEN because strncmp is also a
845 preprocessor macro. */
846 if (strncmp (options, "cpu=", 4) == 0)
847 /* Strip leading `cpu=`. */
848 enforced_isa_mask = parse_cpu_option (options + 4);
850 parse_option (options);
852 while (*options != ',' && *options != '\0')
857 /* Return the instruction type for an instruction described by OPCODE. */
859 static enum dis_insn_type
860 arc_opcode_to_insn_type (const struct arc_opcode *opcode)
862 enum dis_insn_type insn_type;
864 switch (opcode->insn_class)
876 if (!strncmp (opcode->name, "bl", 2)
877 || !strncmp (opcode->name, "jl", 2))
879 if (opcode->subclass == COND)
880 insn_type = dis_condjsr;
886 if (opcode->subclass == COND)
887 insn_type = dis_condbranch;
889 insn_type = dis_branch;
898 insn_type = dis_dref;
901 insn_type = dis_branch;
904 insn_type = dis_nonbranch;
911 /* Disassemble ARC instructions. */
914 print_insn_arc (bfd_vma memaddr,
915 struct disassemble_info *info)
918 unsigned int highbyte, lowbyte;
920 unsigned int insn_len;
921 unsigned long long insn = 0;
922 unsigned isa_mask = ARC_OPCODE_NONE;
923 const struct arc_opcode *opcode;
924 bfd_boolean need_comma;
925 bfd_boolean open_braket;
927 const struct arc_operand *operand;
929 struct arc_operand_iterator iter;
930 struct arc_disassemble_info *arc_infop;
932 if (info->disassembler_options)
934 parse_disassembler_options (info->disassembler_options);
936 /* Avoid repeated parsing of the options. */
937 info->disassembler_options = NULL;
940 if (info->private_data == NULL && !init_arc_disasm_info (info))
943 memset (&iter, 0, sizeof (iter));
944 highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0);
945 lowbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1);
947 /* Figure out CPU type, unless it was enforced via disassembler options. */
948 if (enforced_isa_mask == ARC_OPCODE_NONE)
950 Elf_Internal_Ehdr *header = NULL;
952 if (info->section && info->section->owner)
953 header = elf_elfheader (info->section->owner);
957 case bfd_mach_arc_arc700:
958 isa_mask = ARC_OPCODE_ARC700;
961 case bfd_mach_arc_arc600:
962 isa_mask = ARC_OPCODE_ARC600;
965 case bfd_mach_arc_arcv2:
967 isa_mask = ARC_OPCODE_ARCv2EM;
968 /* TODO: Perhaps remove definition of header since it is only used at
971 && (header->e_flags & EF_ARC_MACH_MSK) == EF_ARC_CPU_ARCV2HS)
972 isa_mask = ARC_OPCODE_ARCv2HS;
977 isa_mask = enforced_isa_mask;
979 if (isa_mask == ARC_OPCODE_ARCv2HS)
981 /* FPU instructions are not extensions for HS. */
982 add_to_decodelist (FLOAT, SP);
983 add_to_decodelist (FLOAT, DP);
984 add_to_decodelist (FLOAT, CVT);
987 /* This variable may be set by the instruction decoder. It suggests
988 the number of bytes objdump should display on a single line. If
989 the instruction decoder sets this, it should always set it to
990 the same value in order to get reasonable looking output. */
992 info->bytes_per_line = 8;
994 /* In the next lines, we set two info variables control the way
995 objdump displays the raw data. For example, if bytes_per_line is
996 8 and bytes_per_chunk is 4, the output will look like this:
997 00: 00000000 00000000
998 with the chunks displayed according to "display_endian". */
1001 && !(info->section->flags & SEC_CODE))
1003 /* This is not a CODE section. */
1004 switch (info->section->size)
1009 size = info->section->size;
1012 size = (info->section->size & 0x01) ? 1 : 4;
1015 info->bytes_per_chunk = 1;
1016 info->display_endian = info->endian;
1021 info->bytes_per_chunk = 2;
1022 info->display_endian = info->endian;
1025 /* Read the insn into a host word. */
1026 status = (*info->read_memory_func) (memaddr, buffer, size, info);
1029 (*info->memory_error_func) (status, memaddr, info);
1034 && !(info->section->flags & SEC_CODE))
1039 data = bfd_get_bits (buffer, size * 8,
1040 info->display_endian == BFD_ENDIAN_BIG);
1044 (*info->fprintf_func) (info->stream, ".byte\t0x%02lx", data);
1047 (*info->fprintf_func) (info->stream, ".short\t0x%04lx", data);
1050 (*info->fprintf_func) (info->stream, ".word\t0x%08lx", data);
1058 insn_len = arc_insn_length (buffer[highbyte], buffer[lowbyte], info);
1059 pr_debug ("instruction length = %d bytes\n", insn_len);
1060 arc_infop = info->private_data;
1061 arc_infop->insn_len = insn_len;
1066 insn = (buffer[highbyte] << 8) | buffer[lowbyte];
1071 /* This is a long instruction: Read the remaning 2 bytes. */
1072 status = (*info->read_memory_func) (memaddr + 2, &buffer[2], 2, info);
1075 (*info->memory_error_func) (status, memaddr + 2, info);
1078 insn = (unsigned long long) ARRANGE_ENDIAN (info, buffer);
1084 status = (*info->read_memory_func) (memaddr + 2, &buffer[2], 4, info);
1087 (*info->memory_error_func) (status, memaddr + 2, info);
1090 insn = (unsigned long long) ARRANGE_ENDIAN (info, &buffer[2]);
1091 insn |= ((unsigned long long) buffer[highbyte] << 40)
1092 | ((unsigned long long) buffer[lowbyte] << 32);
1098 status = (*info->read_memory_func) (memaddr + 2, &buffer[2], 6, info);
1101 (*info->memory_error_func) (status, memaddr + 2, info);
1105 ((((unsigned long long) ARRANGE_ENDIAN (info, buffer)) << 32)
1106 | ((unsigned long long) ARRANGE_ENDIAN (info, &buffer[4])));
1111 /* There is no instruction whose length is not 2, 4, 6, or 8. */
1115 pr_debug ("instruction value = %llx\n", insn);
1117 /* Set some defaults for the insn info. */
1118 info->insn_info_valid = 1;
1119 info->branch_delay_insns = 0;
1120 info->data_size = 4;
1121 info->insn_type = dis_nonbranch;
1125 /* FIXME to be moved in dissasemble_init_for_target. */
1126 info->disassembler_needs_relocs = TRUE;
1128 /* Find the first match in the opcode table. */
1129 if (!find_format (memaddr, insn, &insn_len, isa_mask, info, &opcode, &iter))
1137 (*info->fprintf_func) (info->stream, ".long %#04llx",
1141 (*info->fprintf_func) (info->stream, ".long %#08llx",
1145 (*info->fprintf_func) (info->stream, ".long %#08llx",
1147 (*info->fprintf_func) (info->stream, ".long %#04llx",
1148 (insn >> 32) & 0xffff);
1151 (*info->fprintf_func) (info->stream, ".long %#08llx",
1153 (*info->fprintf_func) (info->stream, ".long %#08llx",
1160 info->insn_type = dis_noninsn;
1164 /* Print the mnemonic. */
1165 (*info->fprintf_func) (info->stream, "%s", opcode->name);
1167 /* Preselect the insn class. */
1168 info->insn_type = arc_opcode_to_insn_type (opcode);
1170 pr_debug ("%s: 0x%08llx\n", opcode->name, opcode->opcode);
1172 print_flags (opcode, &insn, info);
1174 if (opcode->operands[0] != 0)
1175 (*info->fprintf_func) (info->stream, "\t");
1178 open_braket = FALSE;
1179 arc_infop->operands_count = 0;
1181 /* Now extract and print the operands. */
1183 while (operand_iterator_next (&iter, &operand, &value))
1185 if (open_braket && (operand->flags & ARC_OPERAND_BRAKET))
1187 (*info->fprintf_func) (info->stream, "]");
1188 open_braket = FALSE;
1192 /* Only take input from real operands. */
1193 if (ARC_OPERAND_IS_FAKE (operand))
1196 if ((operand->flags & ARC_OPERAND_IGNORE)
1197 && (operand->flags & ARC_OPERAND_IR)
1201 if (operand->flags & ARC_OPERAND_COLON)
1203 (*info->fprintf_func) (info->stream, ":");
1208 (*info->fprintf_func) (info->stream, ",");
1210 if (!open_braket && (operand->flags & ARC_OPERAND_BRAKET))
1212 (*info->fprintf_func) (info->stream, "[");
1220 /* Print the operand as directed by the flags. */
1221 if (operand->flags & ARC_OPERAND_IR)
1225 assert (value >=0 && value < 64);
1226 rname = arcExtMap_coreRegName (value);
1228 rname = regnames[value];
1229 (*info->fprintf_func) (info->stream, "%s", rname);
1230 if (operand->flags & ARC_OPERAND_TRUNCATE)
1232 rname = arcExtMap_coreRegName (value + 1);
1234 rname = regnames[value + 1];
1235 (*info->fprintf_func) (info->stream, "%s", rname);
1238 else if (operand->flags & ARC_OPERAND_LIMM)
1240 const char *rname = get_auxreg (opcode, value, isa_mask);
1242 if (rname && open_braket)
1243 (*info->fprintf_func) (info->stream, "%s", rname);
1246 (*info->fprintf_func) (info->stream, "%#x", value);
1247 if (info->insn_type == dis_branch
1248 || info->insn_type == dis_jsr)
1249 info->target = (bfd_vma) value;
1252 else if (operand->flags & ARC_OPERAND_PCREL)
1255 if (info->flags & INSN_HAS_RELOC)
1257 (*info->print_address_func) ((memaddr & ~3) + value, info);
1259 info->target = (bfd_vma) (memaddr & ~3) + value;
1261 else if (operand->flags & ARC_OPERAND_SIGNED)
1263 const char *rname = get_auxreg (opcode, value, isa_mask);
1264 if (rname && open_braket)
1265 (*info->fprintf_func) (info->stream, "%s", rname);
1267 (*info->fprintf_func) (info->stream, "%d", value);
1269 else if (operand->flags & ARC_OPERAND_ADDRTYPE)
1271 const char *addrtype = get_addrtype (value);
1272 (*info->fprintf_func) (info->stream, "%s", addrtype);
1273 /* A colon follow an address type. */
1278 if (operand->flags & ARC_OPERAND_TRUNCATE
1279 && !(operand->flags & ARC_OPERAND_ALIGNED32)
1280 && !(operand->flags & ARC_OPERAND_ALIGNED16)
1281 && value >= 0 && value <= 14)
1289 (*info->fprintf_func) (info->stream, "r13");
1292 (*info->fprintf_func) (info->stream, "r13-%s",
1293 regnames[13 + value - 1]);
1299 const char *rname = get_auxreg (opcode, value, isa_mask);
1300 if (rname && open_braket)
1301 (*info->fprintf_func) (info->stream, "%s", rname);
1303 (*info->fprintf_func) (info->stream, "%#x", value);
1307 if (operand->flags & ARC_OPERAND_LIMM)
1309 arc_infop->operands[arc_infop->operands_count].kind
1310 = ARC_OPERAND_KIND_LIMM;
1311 /* It is not important to have exactly the LIMM indicator
1313 arc_infop->operands[arc_infop->operands_count].value = 63;
1317 arc_infop->operands[arc_infop->operands_count].value = value;
1318 arc_infop->operands[arc_infop->operands_count].kind
1319 = (operand->flags & ARC_OPERAND_IR
1320 ? ARC_OPERAND_KIND_REG
1321 : ARC_OPERAND_KIND_SHIMM);
1323 arc_infop->operands_count ++;
1331 arc_get_disassembler (bfd *abfd)
1333 /* BFD my be absent, if opcodes is invoked from the debugger that
1334 has connected to remote target and doesn't have an ELF file. */
1337 /* Read the extension insns and registers, if any. */
1338 build_ARC_extmap (abfd);
1344 return print_insn_arc;
1348 print_arc_disassembler_options (FILE *stream)
1352 fprintf (stream, _("\n\
1353 The following ARC specific disassembler options are supported for use \n\
1354 with -M switch (multiple options should be separated by commas):\n"));
1356 /* cpu=... options. */
1357 for (i = 0; cpu_types[i].name; ++i)
1359 /* As of now all value CPU values are less than 16 characters. */
1360 fprintf (stream, " cpu=%-16s\tEnforce %s ISA.\n",
1361 cpu_types[i].name, cpu_types[i].isa);
1364 fprintf (stream, _("\
1365 dsp Recognize DSP instructions.\n"));
1366 fprintf (stream, _("\
1367 spfp Recognize FPX SP instructions.\n"));
1368 fprintf (stream, _("\
1369 dpfp Recognize FPX DP instructions.\n"));
1370 fprintf (stream, _("\
1371 quarkse_em Recognize FPU QuarkSE-EM instructions.\n"));
1372 fprintf (stream, _("\
1373 fpuda Recognize double assist FPU instructions.\n"));
1374 fprintf (stream, _("\
1375 fpus Recognize single precision FPU instructions.\n"));
1376 fprintf (stream, _("\
1377 fpud Recognize double precision FPU instructions.\n"));
1380 void arc_insn_decode (bfd_vma addr,
1381 struct disassemble_info *info,
1382 disassembler_ftype disasm_func,
1383 struct arc_instruction *insn)
1385 const struct arc_opcode *opcode;
1386 struct arc_disassemble_info *arc_infop;
1388 /* Ensure that insn would be in the reset state. */
1389 memset (insn, 0, sizeof (struct arc_instruction));
1391 /* There was an error when disassembling, for example memory read error. */
1392 if (disasm_func (addr, info) < 0)
1394 insn->valid = FALSE;
1398 assert (info->private_data != NULL);
1399 arc_infop = info->private_data;
1401 insn->length = arc_infop->insn_len;;
1402 insn->address = addr;
1404 /* Quick exit if memory at this address is not an instruction. */
1405 if (info->insn_type == dis_noninsn)
1407 insn->valid = FALSE;
1413 opcode = (const struct arc_opcode *) arc_infop->opcode;
1414 insn->insn_class = opcode->insn_class;
1415 insn->limm_value = arc_infop->limm;
1416 insn->limm_p = arc_infop->limm_p;
1418 insn->is_control_flow = (info->insn_type == dis_branch
1419 || info->insn_type == dis_condbranch
1420 || info->insn_type == dis_jsr
1421 || info->insn_type == dis_condjsr);
1423 insn->has_delay_slot = info->branch_delay_insns;
1424 insn->writeback_mode
1425 = (enum arc_ldst_writeback_mode) arc_infop->writeback_mode;
1426 insn->data_size_mode = info->data_size;
1427 insn->condition_code = arc_infop->condition_code;
1428 memcpy (insn->operands, arc_infop->operands,
1429 sizeof (struct arc_insn_operand) * MAX_INSN_ARGS);
1430 insn->operands_count = arc_infop->operands_count;
1434 eval: (c-set-style "gnu")